zephyr: Move hardware init dependencies

Move some hardware initialization from components to zephyr folder.

Signed-off-by: Lucas Tamborrino <[email protected]>

Author: LucasTambor

components/bootloader_support/bootloader_flash/src/flash_qio_mode.c

@@ -18,7 +18,7 @@
 #include "soc/efuse_periph.h"
 #include "soc/io_mux_reg.h"
 #include "esp_private/spi_flash_os.h"
-
+#include "soc_flash_init.h"
 
 static const char *TAG = "qio_mode";
 
@@ -107,7 +107,7 @@ static void s_flash_set_qio_pins(void)
 #if SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
 
 #if CONFIG_IDF_TARGET_ESP32
-    esp_rom_spiflash_select_qio_pins(bootloader_flash_get_wp_pin(), esp_rom_efuse_get_flash_gpio_info());
+    esp_rom_spiflash_select_qio_pins(flash_get_wp_pin(), esp_rom_efuse_get_flash_gpio_info());
 #else
     esp_rom_spiflash_select_qio_pins(esp_rom_efuse_get_flash_wp_gpio(), esp_rom_efuse_get_flash_gpio_info());
 #endif // CONFIG_IDF_TARGET_ESP32

components/esp_psram/esp32/esp_psram_impl_quad.c

@@ -34,7 +34,7 @@
 #include "esp_private/periph_ctrl.h"
 #include "bootloader_common.h"
 #include "esp_rom_gpio.h"
-#include "bootloader_flash_config.h"
+#include "soc_flash_init.h"
 #include "esp_private/esp_gpio_reserve.h"
 
 #if CONFIG_SPIRAM
@@ -907,7 +907,7 @@ esp_err_t IRAM_ATTR esp_psram_impl_enable(psram_vaddr_mode_t vaddrmode)   //psra
         psram_io.psram_spiq_sd0_io  = EFUSE_SPICONFIG_RET_SPIQ(spiconfig);
         psram_io.psram_spid_sd1_io  = EFUSE_SPICONFIG_RET_SPID(spiconfig);
         psram_io.psram_spihd_sd2_io = EFUSE_SPICONFIG_RET_SPIHD(spiconfig);
-        psram_io.psram_spiwp_sd3_io = bootloader_flash_get_wp_pin();
+        psram_io.psram_spiwp_sd3_io = flash_get_wp_pin();
     }
 
     assert(mode < PSRAM_CACHE_MAX && "we don't support any other mode for now.");
@@ -944,7 +944,17 @@ esp_err_t IRAM_ATTR esp_psram_impl_enable(psram_vaddr_mode_t vaddrmode)   //psra
     }
 
     // Rise VDDSIO for 1.8V psram.
-    bootloader_common_vddsdio_configure();
+#if CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V
+    rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config();
+    if (cfg.enable == 1 && cfg.tieh == RTC_VDDSDIO_TIEH_1_8V) {    // VDDSDIO regulator is enabled @ 1.8V
+        cfg.drefh = 3;
+        cfg.drefm = 3;
+        cfg.drefl = 3;
+        cfg.force = 1;
+        rtc_vddsdio_set_config(cfg);
+        esp_rom_delay_us(10); // wait for regulator to become stable
+    }
+#endif // CONFIG_BOOTLOADER_VDDSDIO_BOOST
     // GPIO related settings
     psram_gpio_config(&psram_io, mode);
 

components/spi_flash/flash_ops.c

@@ -24,6 +24,7 @@
 #include "esp_private/esp_clk.h"
 #include "esp_private/esp_gpio_reserve.h"
 #if CONFIG_IDF_TARGET_ESP32
+#include "soc_flash_init.h"
 #include "esp32/rom/cache.h"
 #include "esp32/rom/spi_flash.h"
 #elif CONFIG_IDF_TARGET_ESP32S2
@@ -154,19 +155,6 @@ void IRAM_ATTR esp_mspi_pin_init(void)
     esp_gpio_reserve_pins(reserve_pin_mask);
 }
 
-esp_err_t IRAM_ATTR spi_flash_init_chip_state(void)
-{
-#if SOC_SPI_MEM_SUPPORT_OPI_MODE
-    if (bootloader_flash_is_octal_mode_enabled()) {
-        return esp_opiflash_init(rom_spiflash_legacy_data->chip.device_id);
-    }
-#endif
-#if CONFIG_SPI_FLASH_HPM_ON
-        return spi_flash_enable_high_performance_mode();
-#endif // CONFIG_SPI_FLASH_HPM_ON
-    return ESP_OK;
-}
-
 void IRAM_ATTR spi_flash_set_rom_required_regs(void)
 {
 #if SOC_SPI_MEM_SUPPORT_OPI_MODE
@@ -239,7 +227,7 @@ uint8_t esp_mspi_get_io(esp_mspi_io_t io)
          * 2. rom code take 0x3f as invalid wp pad num, but take 0 as other invalid mspi pads num
          */
 #if CONFIG_IDF_TARGET_ESP32
-        return bootloader_flash_get_wp_pin();
+        return flash_get_wp_pin();
 #else
         spiconfig = esp_rom_efuse_get_flash_wp_gpio();
         return (spiconfig == 0x3f) ? s_mspi_io_num_default[io] : spiconfig & 0x3f;

components/spi_flash/include/esp_private/spi_flash_os.h

@@ -45,11 +45,6 @@ typedef enum {
     ESP_MSPI_IO_MAX, /* Maximum IO MSPI occupied */
 } esp_mspi_io_t;
 
-/**
- * @brief To setup Flash chip
- */
-esp_err_t spi_flash_init_chip_state(void);
-
 /**
  * @brief To initislize the MSPI pins
  */

zephyr/common/console_init.c

@@ -0,0 +1,60 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/sys/util.h>
+#include "stubs.h"
+#include "console_init.h"
+#include "soc/uart_periph.h"
+#include "soc/uart_channel.h"
+#include "soc/io_mux_reg.h"
+#include "soc/gpio_periph.h"
+#include "soc/gpio_sig_map.h"
+#include "soc/rtc.h"
+#include "hal/clk_gate_ll.h"
+#include "hal/gpio_hal.h"
+#if CONFIG_SOC_SERIES_ESP32S2
+#include "esp32s2/rom/usb/cdc_acm.h"
+#include "esp32s2/rom/usb/usb_common.h"
+#include "esp32s2/rom/usb/usb_persist.h"
+#endif
+#include "esp_rom_gpio.h"
+#include "esp_rom_uart.h"
+#include "esp_rom_sys.h"
+#include "esp_rom_caps.h"
+
+void esp_console_deinit(void)
+{
+#ifdef CONFIG_ESP_CONSOLE_UART
+	/* Ensure any buffered log output is displayed */
+	esp_rom_uart_flush_tx(CONFIG_ESP_CONSOLE_UART_NUM);
+#endif /* CONFIG_ESP_CONSOLE_UART */
+}
+
+#ifdef CONFIG_ESP_CONSOLE_UART
+void esp_console_init(void)
+{
+	const int uart_num = CONFIG_ESP_CONSOLE_UART_NUM;
+
+	esp_rom_install_uart_printf();
+
+	esp_rom_uart_tx_wait_idle(0);
+
+	/* Set configured UART console baud rate */
+	uint32_t clock_hz = rtc_clk_apb_freq_get();
+#if ESP_ROM_UART_CLK_IS_XTAL
+	/* From esp32-s3 on, UART clk source is selected to XTAL in ROM */
+	clock_hz = (uint32_t)rtc_clk_xtal_freq_get() * MHZ(1);
+#endif
+	esp_rom_uart_set_clock_baudrate(uart_num, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE);
+}
+#endif /* CONFIG_ESP_CONSOLE_UART */
+
+#ifdef CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
+void esp_console_init(void)
+{
+	esp_rom_uart_switch_buffer(ESP_ROM_USB_SERIAL_DEVICE_NUM);
+}
+#endif /* CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG */

zephyr/common/flash_init.c

@@ -0,0 +1,40 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "flash_init.h"
+
+#include <stdbool.h>
+#include <bootloader_flash_priv.h>
+#include <hal/efuse_ll.h>
+#include <hal/efuse_hal.h>
+#include "esp_private/spi_flash_os.h"
+#if CONFIG_SOC_SERIES_ESP32S3
+#include <esp32s3/opi_flash_private.h>
+#endif
+
+bool flash_is_octal_mode_enabled(void)
+{
+#if SOC_SPI_MEM_SUPPORT_OPI_MODE
+	return efuse_ll_get_flash_type();
+#else
+	return false;
+#endif
+}
+
+int spi_flash_init_chip_state(void)
+{
+#if SOC_SPI_MEM_SUPPORT_OPI_MODE
+	if (flash_is_octal_mode_enabled()) {
+		return esp_opiflash_init(rom_spiflash_legacy_data->chip.device_id);
+	}
+#endif
+#if CONFIG_SPI_FLASH_HPM_ON
+	/* Currently, only esp32s3 allows high performance mode. */
+	return spi_flash_enable_high_performance_mode();
+#else
+	return 0;
+#endif /* CONFIG_SOC_SERIES_ESP32S3 */
+}

zephyr/common/include/console_init.h

@@ -0,0 +1,13 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+void esp_console_init(void);
+
+void esp_console_deinit(void);
+
+void esp_console_write_char_usb(char c);

zephyr/common/include/flash_init.h

@@ -0,0 +1,13 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include <stdbool.h>
+
+int spi_flash_init_chip_state(void);
+
+bool flash_is_octal_mode_enabled(void);

zephyr/common/include/soc_flash_init.h

@@ -0,0 +1,17 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+
+void flash_update_id(void);
+
+int init_spi_flash(void);
+
+#ifdef CONFIG_SOC_SERIES_ESP32
+int flash_get_wp_pin(void);
+#endif

zephyr/common/include/soc_init.h

@@ -0,0 +1,41 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdbool.h>
+
+void print_banner(void);
+int read_bootloader_header(void);
+int check_bootloader_validity(void);
+void config_wdt(void);
+
+
+#if defined(CONFIG_SOC_SERIES_ESP32) || defined (CONFIG_SOC_SERIES_ESP32S3)
+void wdt_reset_info_dump(int cpu);
+#endif
+
+void wdt_reset_cpu0_info_enable(void);
+
+#if defined(CONFIG_SOC_SERIES_ESP32)
+void reset_mmu(void);
+#endif
+
+#if !defined(CONFIG_SOC_SERIES_ESP32)
+void super_wdt_auto_feed(void);
+#endif
+
+
+void check_wdt_reset(void);
+
+void soc_hw_init(void);
+
+void ana_super_wdt_reset_config(bool enable);
+
+void ana_bod_reset_config(bool enable);
+
+void ana_clock_glitch_reset_config(bool enable);
+
+void ana_reset_config(void);

zephyr/common/include/soc_random.h

@@ -0,0 +1,10 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+void soc_random_enable(void);
+
+void soc_random_disable(void);