picorv32_design_constraints.csv

CLOCKS,frequency,duty_cycle,early_rise_delay,early_fall_delay,late_rise_delay,late_fall_delay,early_rise_slew,early_fall_slew,late_rise_slew,late_fall_slew,
clk,2,50,1,1,1,1,1,1,1,1,
,,,,,,,,,,,
INPUTS,early_rise_delay,early_fall_delay,late_rise_delay,late_fall_delay,early_rise_slew,early_fall_slew,late_rise_slew,late_fall_slew,clocks,bussed,bus width
resetn,0.5,0.5,1,1,0.5,0.5,1,1,clk,no,
mem_ready,0.5,0.5,1,1,0.5,0.5,1,1,clk,no,
mem_rdata,0.5,0.5,1,1,0.5,0.5,1,1,clk,yes,32
pcpi_wr,0.5,0.5,1,1,0.5,0.5,1,1,clk,no,
pcpi_rd,0.5,0.5,1,1,0.5,0.5,1,1,clk,yes,32
pcpi_wait,0.5,0.5,1,1,0.5,0.5,1,1,clk,no,
pcpi_ready,0.5,0.5,1,1,0.5,0.5,1,1,clk,no,
irq,0.5,0.5,1,1,0.5,0.5,1,1,clk,yes,32
,,,,,,,,,,,
OUTPUTS,early_rise_delay,early_fall_delay,late_rise_delay,late_fall_delay,clocks,load,bussed,bus width,,,
trap,0.5,0.5,1,1,clk,1,no,,,,
mem_valid,0.5,0.5,1,1,clk,1,no,,,,
mem_instr,0.5,0.5,1,1,clk,1,no,,,,
mem_addr,0.5,0.5,1,1,clk,1,yes,32,,,
mem_wdata,0.5,0.5,1,1,clk,1,yes,32,,,
mem_wstrb,0.5,0.5,1,1,clk,1,yes,4,,,
mem_la_read,0.5,0.5,1,1,clk,1,no,,,,
mem_la_write,0.5,0.5,1,1,clk,1,no,,,,
mem_la_addr,0.5,0.5,1,1,clk,1,yes,32,,,
mem_la_wdata,0.5,0.5,1,1,clk,1,yes,32,,,
mem_la_wstrb,0.5,0.5,1,1,clk,1,yes,4,,,
pcpi_valid,0.5,0.5,1,1,clk,1,no,,,,
pcpi_insn,0.5,0.5,1,1,clk,1,yes,32,,,
pcpi_rs1,0.5,0.5,1,1,clk,1,yes,32,,,
pcpi_rs2,0.5,0.5,1,1,clk,1,yes,32,,,
eoi,0.5,0.5,1,1,clk,1,yes,32,,,
trace_valid,0.5,0.5,1,1,clk,1,no,,,,
trace_data,0.5,0.5,1,1,clk,1,yes,36,,,