About the Std library

[captainliuy]

I have tried SpinalHDL, and it is quite feature-rich, but there are two difficulties for me:

1. Deployment in my development environment is challenging, requiring an internet connection.
2. Learning the Scale language is difficult.

After looking at Veryl, I find that these two issues are not present. My question is whether Veryl can reference SpinalHDL and provide more standard libraries?

[dalance]

Thank you for your interesting in our project.
The standard library of Veryl is still under development.
Now we focuses language design and implementation, and don't have enough time to develop it.

If you have any idea for standard library, please open an issue.
Of course, contribution is welcome too.

[captainliuy]

I often work with AXI interfaces and use the open-source code by alexforencich. I think directly wrapping the Verilog code would be a quick approach.

[nblei]

I'm curious what your use-case is in which you cannot get high quality, commercial IPs for AXI.

[captainliuy]

I am using Vivado's block design flow for development and need to write some AXI interface IPs.

[dalance]

I think interface definition of standard buses like AXI should be added to standard library at first.
If so, each modules can be added as wrapper at first, and replacing to Veryl implementation can be done gradually without affection to users.