Instruction streams incorrectly recognized as unpredictable

[mateusz-banaszek]

The method isUnpredictable() of InstEncoding (in instrs2asl.py) incorrectly recognizes instruction streams as unpredictable. For example:

>>> all_encodings['aarch32_ADD_i_T3_A'].isUnpredictable('11110001000000100000110000100100')
if (d == 15 && !setflags) || n == 15 then UNPREDICTABLE
d == 15 Converted to: d == 15
n == 15 Converted to: n == 15
d == 15 Converted to: d == 15
 // Armv8-A removes UNPREDICTABLE for R13
whether 11110001000000100000110000100100 meets d == 15 Converted to: d == 15 for aarch32/ADD_i/T3_A
related variable d
init variable d = BitVec('d',32)
related variable Rd
True  # <-- False expected

According to the ARM documentation, the stream 11110001000000100000110000100100 is a valid and predictable ADD (immediate) T3 instruction.