Modularize connect methods (#69)

* * Separate connect methods of BlockDevice, SerialAdapter, and UARTAdapter into objects for modularity
* Fix deprecation warnings

* SerialIO should not be an Option

* Add suggestName for uart_sim

* CR feedback; Move the option logic into SerialAdapter methods

Author: jwright6323

src/main/scala/BlockDevice.scala

@@ -458,15 +458,26 @@ trait CanHavePeripheryBlockDeviceModuleImp extends LazyModuleImp {
     io
   }
 
-  def connectSimBlockDevice(clock: Clock, reset: Bool) {
-    val sim = Module(new SimBlockDevice)
-    sim.io.clock := clock
-    sim.io.reset := reset
-    sim.io.bdev <> bdev.get
+  def connectSimBlockDevice(clock: Clock, reset: Bool) = SimBlockDevice.connect(clock, reset, bdev)
+  def connectBlockDeviceModel() = BlockDeviceModel.connect(bdev)
+}
+
+object SimBlockDevice {
+  def connect(clock: Clock, reset: Bool, bdev: Option[BlockDeviceIO])(implicit p: Parameters) {
+    bdev.foreach { b =>
+      val sim = Module(new SimBlockDevice)
+      sim.io.clock := clock
+      sim.io.reset := reset
+      sim.io.bdev <> b
+    }
   }
+}
 
-  def connectBlockDeviceModel() {
-    val model = Module(new BlockDeviceModel(16))
-    model.io <> bdev.get
+object BlockDeviceModel {
+  def connect(bdev: Option[BlockDeviceIO])(implicit p: Parameters) {
+    bdev.foreach { b =>
+      val model = Module(new BlockDeviceModel(16))
+      model.io <> b
+    }
   }
 }

src/main/scala/SerialAdapter.scala

@@ -1,7 +1,6 @@
 package testchipip
 
 import chisel3._
-import chisel3.core.Reset
 import chisel3.util._
 import freechips.rocketchip.config.{Parameters, Field}
 import freechips.rocketchip.subsystem.{BaseSubsystem}
@@ -12,6 +11,28 @@ import scala.math.min
 
 case object SerialAdapter {
   val SERIAL_IF_WIDTH = 32
+
+  def connectSimSerial(serial: Option[SerialIO], clock: Clock, reset: Reset): Bool = {
+    serial.map { s =>
+      val sim = Module(new SimSerial(SERIAL_IF_WIDTH))
+      sim.io.clock := clock
+      sim.io.reset := reset
+      sim.io.serial <> s
+      sim.io.exit
+    }.getOrElse(false.B)
+  }
+
+  def connectSimSerial(serial: SerialIO, clock: Clock, reset: Reset): Bool = connectSimSerial(Some(serial), clock, reset)
+
+  def tieoff(serial: Option[SerialIO]) {
+    serial.foreach { s =>
+      s.in.valid := false.B
+      s.in.bits := DontCare
+      s.out.ready := true.B
+    }
+  }
+
+  def tieoff(serial: SerialIO) { tieoff(Some(serial)) }
 }
 import SerialAdapter._
 
@@ -179,8 +200,8 @@ class SimSerial(w: Int) extends BlackBox with HasBlackBoxResource {
     val exit = Output(Bool())
   })
 
-  setResource("/testchipip/vsrc/SimSerial.v")
-  setResource("/testchipip/csrc/SimSerial.cc")
+  addResource("/testchipip/vsrc/SimSerial.v")
+  addResource("/testchipip/csrc/SimSerial.cc")
 }
 
 case object SerialKey extends Field[Boolean](false)
@@ -213,20 +234,9 @@ trait CanHavePeripherySerialModuleImp extends LazyModuleImp {
     None
   }
 
-  def connectSimSerial() = {
-    val sim = Module(new SimSerial(SERIAL_IF_WIDTH))
-    sim.io.clock := clock
-    sim.io.reset := reset
-    sim.io.serial <> serial.get
-    sim.io.exit
-  }
+  def connectSimSerial() = SerialAdapter.connectSimSerial(serial, clock, reset)
+
+  def tieoffSerial() = SerialAdapter.tieoff(serial)
 
-  def tieoffSerial() = {
-    serial.map { s =>
-      s.in.valid := false.B
-      s.in.bits := DontCare
-      s.out.ready := true.B
-    }
-  }
 }
 

src/main/scala/UARTAdapter.scala

@@ -23,17 +23,14 @@ import UARTAdapterConsts._
  * packets.
  *
  * @param uartno the uart number
- * @param baudrate the uart baudrate to deserialize/serialize data
+ * @param div the divisor (equal to the clock frequency divided by the baud rate)
  */
-class UARTAdapter(uartno: Int, baudrate: BigInt)(implicit p: Parameters) extends Module
+class UARTAdapter(uartno: Int, div: Int) extends Module
 {
   val io = IO(new Bundle {
     val uart = Flipped(new UARTPortIO)
   })
 
-  val frequency = p(PeripheryBusKey).frequency
-  val div = (p(PeripheryBusKey).frequency / baudrate).toInt
-
   val txfifo = Module(new Queue(UInt(DATA_WIDTH.W), 128))
   val rxfifo = Module(new Queue(UInt(DATA_WIDTH.W), 128))
 
@@ -124,6 +121,24 @@ class UARTAdapter(uartno: Int, baudrate: BigInt)(implicit p: Parameters) extends
   sim.io.serial.in.ready := rxfifo.io.enq.ready
 }
 
+object UARTAdapter {
+  def connect(uart: Seq[UARTPortIO], baudrate: BigInt = 115200)(implicit p: Parameters) {
+    UARTAdapter.connect(uart, baudrate, p(PeripheryBusKey).frequency)
+  }
+  def connect(uart: Seq[UARTPortIO], baudrate: BigInt, clockFrequency: BigInt) {
+    val div = (clockFrequency / baudrate).toInt
+    UARTAdapter.connect(uart, div)
+  }
+  def connect(uart: Seq[UARTPortIO], div: Int) {
+    uart.zipWithIndex.foreach { case (dut_io, i) =>
+      val uart_sim = Module(new UARTAdapter(i, div))
+      uart_sim.suggestName("uart_sim_${i}")
+      uart_sim.io.uart.txd := dut_io.txd
+      dut_io.rxd := uart_sim.io.uart.rxd
+    }
+  }
+}
+
 /**
  * Module to connect to a *.v blackbox that uses DPI calls to interact with the DUT UART.
  *