change memory model from gpu to npu

Author: lucarlig

README.md

@@ -7,7 +7,7 @@ Descend is a safe systems programming language that adapts and extends Rust's ty
 - **Extended Borrow Checking**: Prevents data races by tracking unique (`uniq`) and shared (`shrd`) references across thousands of parallel threads
 - **Memory Views**: Safe parallel access patterns that replace raw pointer indexing, statically verified to be race-free
 - **Execution Resource Tracking**: Types enforce that memory is only accessed in correct execution contexts (`cpu.thread`, `gpu.grid`, `gpu.block`, `gpu.thread`)
-- **Explicit Memory Spaces**: References track physical memory locations (`cpu.mem`, `gpu.global`, `gpu.shared`) preventing invalid cross-device accesses
+- **Explicit Memory Spaces**: References track physical memory locations (`cpu.mem`, `npu.global`, `gpu.shared`) preventing invalid cross-device accesses
 - **Safe Synchronization**: The type system enforces correct placement and usage of synchronization primitives
 
 **Design Philosophy:**
@@ -59,7 +59,7 @@ AscendNPU-IR defines custom MLIR dialects tailored to Ascend NPU capabilities:
 
 **Descend + AscendNPU-IR Integration:**
 
-The MLIR backend maps Descend's execution contexts (`gpu.grid`/`gpu.block`/`gpu.thread`) and memory hierarchies (`gpu.global`/`gpu.local`) to corresponding Ascend NPU constructs through AscendNPU-IR's HIVM dialect. This integration:
+The MLIR backend maps Descend's execution contexts (`gpu.grid`/`gpu.block`/`gpu.thread`) and memory hierarchies (`npu.global`/`gpu.local`) to corresponding Ascend NPU constructs through AscendNPU-IR's HIVM dialect. This integration:
 
 - Preserves Descend's compile-time safety guarantees (race freedom, memory safety, synchronization correctness)
 - Generates efficient code optimized for Ascend NPU hardware
@@ -97,9 +97,9 @@ Descend:
 
 ```rust
 fn add<n: nat, r: prv>(
-    a: &r shrd gpu.global [i16; 16],
-    b: &r shrd gpu.global [i16; 16],
-    c: &r uniq gpu.global [i16; 16]
+    a: &r shrd npu.global [i16; 16],
+    b: &r shrd npu.global [i16; 16],
+    c: &r uniq npu.global [i16; 16]
 ) -[grid: gpu.grid<X<1>, X<16>>]-> () {
     // Vector addition with GPU memory spaces
     ()
@@ -274,7 +274,7 @@ The CUDA backend generates C++ code for NVIDIA GPUs:
 ###### ✅ Phase 2: Ascend-Specific Lowering (Completed)
 
 - [x] Map execution contexts (`gpu.grid`/`gpu.block`/`gpu.thread`) to HIVM parallel constructs
-- [x] Map memory hierarchies (`gpu.global` → HIVM global, `gpu.local` → HIVM shared)
+- [x] Map memory hierarchies (`npu.global` → HIVM global, `gpu.local` → HIVM shared)
 - [x] HIVM dialect integration with proper address spaces
 - [x] HACC entry point and device function generation
 - [x] Comprehensive test suite (14 passing tests)

examples/core/assign.desc.off

@@ -1,6 +1,6 @@
 fn assign<n: nat, r: prv>(
-    a: &r shrd gpu.global [i16; 16],
-    b: &r uniq gpu.global [i16; 16]
+    a: &r shrd npu.global [i16; 16],
+    b: &r uniq npu.global [i16; 16]
 ) -[grid: gpu.grid<X<1>, X<16>>]-> () {
     b = a;
     ()

examples/core/func_params.desc

@@ -5,5 +5,3 @@ fn add(a: i32, b: i32) -[t: cpu.thread]-> i32 {
 fn main() -[t: cpu.thread]-> i32 {
     add(10, 32)
 }
-
-

examples/core/gpu_mem.desc.off

@@ -1,7 +1,7 @@
 fn add<n: nat, r: prv>(
-    a: &r shrd gpu.global [i16; 16],
-    b: &r shrd gpu.global [i16; 16],
-    c: &r uniq gpu.global [i16; 16]
+    a: &r shrd npu.global [i16; 16],
+    b: &r shrd npu.global [i16; 16],
+    c: &r uniq npu.global [i16; 16]
 ) -[grid: gpu.grid<X<1>, X<16>>]-> () {
     // a = b + c;
     ()

examples/core/lazy_load_ub.desc.off

@@ -1,6 +1,6 @@
 fn memory_load<n: nat, r: prv>(
-    a: &r shrd gpu.global [i16; 16],
-    b: &r uniq gpu.global [i16; 16]
+    a: &r shrd npu.global [i16; 16],
+    b: &r uniq npu.global [i16; 16]
 ) -[grid: gpu.grid<X<1>, X<16>>]-> () {
     ()
 }

examples/core/load_ub.desc.off

@@ -1,5 +1,5 @@
 fn memory_load<n: nat, r: prv>(
-    a: &r shrd gpu.global [i16; 16]
+    a: &r shrd npu.global [i16; 16]
 ) -[grid: gpu.grid<X<1>, X<16>>]-> () {
     a;
     ()

examples/core/load_ub_twice.desc.off

@@ -1,6 +1,6 @@
 fn memory_load<n: nat, r: prv>(
-    a: &r shrd gpu.global [i16; 16],
-    b: &r uniq gpu.global [i16; 16]
+    a: &r shrd npu.global [i16; 16],
+    b: &r uniq npu.global [i16; 16]
 ) -[grid: gpu.grid<X<1>, X<16>>]-> () {
     a;
     b;

examples/core/vadd.desc.off

@@ -1,6 +1,6 @@
 fn add<n: nat, r: prv>(
-    a: &r shrd gpu.global [i16; 16],
-    b: &r shrd gpu.global [i16; 16]
+    a: &r shrd npu.global [i16; 16],
+    b: &r shrd npu.global [i16; 16]
 ) -[grid: gpu.grid<X<1>, X<16>>]-> () {
     a + b;
     ()

examples/core/vdiv.desc.off

@@ -1,6 +1,6 @@
 fn div<n: nat, r: prv>(
-    a: &r shrd gpu.global [i16; 16],
-    b: &r shrd gpu.global [i16; 16]
+    a: &r shrd npu.global [i16; 16],
+    b: &r shrd npu.global [i16; 16]
 ) -[grid: gpu.grid<X<1>, X<16>>]-> () {
     a / b;
     ()

examples/core/vec_add.desc.off

@@ -6,19 +6,19 @@
 // - r: prv - Provenance parameter tracking memory region/lifetime for all references
 fn add<n: nat, r: prv>(
     // Shared reference to first input vector - multiple threads can read simultaneously
-    // Memory space: gpu.global (GPU global memory)
+    // Memory space: npu.global (GPU global memory)
     // Ownership: shrd (shared) - prevents write-after-read data races
     // Type: 16-element array of 16-bit signed integers
-    a: &r shrd gpu.global [i16; 16],
+    a: &r shrd npu.global [i16; 16],
 
     // Shared reference to second input vector - multiple threads can read simultaneously  
     // Same memory space and ownership constraints as 'a'
-    b: &r shrd gpu.global [i16; 16],
+    b: &r shrd npu.global [i16; 16],
 
     // Unique reference to output vector - only one thread can write at a time
     // Ownership: uniq (unique) - prevents write-after-write data races
     // The compiler statically ensures no conflicting borrows exist
-    c: &r uniq gpu.global [i16; 16]
+    c: &r uniq npu.global [i16; 16]
 
 // Execution context specification - defines how this function runs on GPU hardware
 // - grid: gpu.grid<X<1>, X<16>> - GPU execution grid with 1 block containing 16 threads