Use GetSrc in VALU insts instead of assuming vector reg (was vcc_lo) (shadps4-emu#2845)

* Use GetSrc in v_add_i32 instead of assuming vector reg (was vcc_lo)

* some other cases

Author: baggins183

src/shader_recompiler/frontend/translate/vector_alu.cpp

@@ -513,13 +513,13 @@ void Translator::V_LSHLREV_B32(const GcnInst& inst) {
 
 void Translator::V_AND_B32(const GcnInst& inst) {
     const IR::U32 src0{GetSrc(inst.src[0])};
-    const IR::U32 src1{ir.GetVectorReg(IR::VectorReg(inst.src[1].code))};
+    const IR::U32 src1{GetSrc(inst.src[1])};
     SetDst(inst.dst[0], ir.BitwiseAnd(src0, src1));
 }
 
 void Translator::V_OR_B32(bool is_xor, const GcnInst& inst) {
     const IR::U32 src0{GetSrc(inst.src[0])};
-    const IR::U32 src1{ir.GetVectorReg(IR::VectorReg(inst.src[1].code))};
+    const IR::U32 src1{GetSrc(inst.src[1])};
     SetDst(inst.dst[0], is_xor ? ir.BitwiseXor(src0, src1) : IR::U32(ir.BitwiseOr(src0, src1)));
 }
 
@@ -579,7 +579,7 @@ void Translator::V_MBCNT_U32_B32(bool is_low, const GcnInst& inst) {
 void Translator::V_ADD_I32(const GcnInst& inst) {
     // Signed or unsigned components
     const IR::U32 src0{GetSrc(inst.src[0])};
-    const IR::U32 src1{ir.GetVectorReg(IR::VectorReg(inst.src[1].code))};
+    const IR::U32 src1{GetSrc(inst.src[1])};
     const IR::U32 result{ir.IAdd(src0, src1)};
     SetDst(inst.dst[0], result);