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[Xtensa] Correcting FP instructions and intrinsics.
Correcting FP instruction descriptions. Implement lowering of the fma, powf and other FP intrinsics. Add test for base FP intrinsics.
1 parent 3872177 commit cb57f8b

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3 files changed

+421
-33
lines changed

3 files changed

+421
-33
lines changed

‎llvm/lib/Target/Xtensa/XtensaISelLowering.cpp

Lines changed: 41 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -217,56 +217,76 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm,
217217
for (unsigned I = MVT::FIRST_FP_VALUETYPE; I <= MVT::LAST_FP_VALUETYPE; ++I) {
218218
MVT VT = MVT::SimpleValueType(I);
219219
if (isTypeLegal(VT)) {
220-
// We can use FI for FRINT.
221-
// setOperationAction(ISD::FRINT, VT, Legal);
222220
if (VT.getSizeInBits() == 32 && Subtarget.hasSingleFloat()) {
221+
setOperationAction(ISD::FABS, VT, Legal);
223222
setOperationAction(ISD::FADD, VT, Legal);
224-
setOperationAction(ISD::FSUB, VT, Legal);
223+
setOperationAction(ISD::FMA, VT, Legal);
225224
setOperationAction(ISD::FMUL, VT, Legal);
226-
setOperationAction(ISD::FDIV, VT, Expand);
225+
setOperationAction(ISD::FNEG, VT, Legal);
226+
setOperationAction(ISD::FSUB, VT, Legal);
227227
} else {
228+
setOperationAction(ISD::FABS, VT, Expand);
228229
setOperationAction(ISD::FADD, VT, Expand);
229-
setOperationAction(ISD::FSUB, VT, Expand);
230+
setOperationAction(ISD::FMA, VT, Expand);
230231
setOperationAction(ISD::FMUL, VT, Expand);
231-
setOperationAction(ISD::FDIV, VT, Expand);
232+
setOperationAction(ISD::FNEG, VT, Expand);
233+
setOperationAction(ISD::FSUB, VT, Expand);
232234
}
233235

234-
// TODO: once implemented in InstrInfo uncomment
235-
setOperationAction(ISD::FSQRT, VT, Expand);
236-
237236
// No special instructions for these.
238-
setOperationAction(ISD::FSIN, VT, Expand);
237+
setOperationAction(ISD::FCBRT, VT, Expand);
238+
setOperationAction(ISD::FCEIL, VT, Expand);
239+
setOperationAction(ISD::FCOPYSIGN, VT, Expand);
239240
setOperationAction(ISD::FCOS, VT, Expand);
241+
setOperationAction(ISD::FDIV, VT, Expand);
242+
setOperationAction(ISD::FEXP, VT, Expand);
243+
setOperationAction(ISD::FEXP2, VT, Expand);
244+
setOperationAction(ISD::FFLOOR, VT, Expand);
245+
setOperationAction(ISD::FLOG, VT, Expand);
246+
setOperationAction(ISD::FLOG2, VT, Expand);
247+
setOperationAction(ISD::FLOG10, VT, Expand);
248+
setOperationAction(ISD::FMAXIMUM, VT, Expand);
249+
setOperationAction(ISD::FMINIMUM, VT, Expand);
250+
setOperationAction(ISD::FMAXNUM, VT, Expand);
251+
setOperationAction(ISD::FMINNUM, VT, Expand);
252+
setOperationAction(ISD::FNEARBYINT, VT, Expand);
253+
setOperationAction(ISD::FPOW, VT, Expand);
254+
setOperationAction(ISD::FPOWI, VT, Expand);
240255
setOperationAction(ISD::FREM, VT, Expand);
241-
setOperationAction(ISD::FABS, VT, Expand);
256+
setOperationAction(ISD::FRINT, VT, Expand);
257+
setOperationAction(ISD::FROUND, VT, Expand);
258+
setOperationAction(ISD::FSIN, VT, Expand);
259+
setOperationAction(ISD::FSINCOS, VT, Expand);
260+
setOperationAction(ISD::FSQRT, VT, Expand);
261+
setOperationAction(ISD::FTRUNC, VT, Expand);
262+
setOperationAction(ISD::LLRINT, VT, Expand);
263+
setOperationAction(ISD::LLROUND, VT, Expand);
264+
setOperationAction(ISD::LRINT, VT, Expand);
265+
setOperationAction(ISD::LROUND, VT, Expand);
242266
}
243267
}
244268

245-
// Handle floating-point types.
246269
if (Subtarget.hasSingleFloat()) {
247-
setOperationAction(ISD::FMA, MVT::f32, Legal);
248270
setOperationAction(ISD::BITCAST, MVT::i32, Legal);
249271
setOperationAction(ISD::BITCAST, MVT::f32, Legal);
250272
setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
251273
setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
252274
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
253275
setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
254-
setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
255276
} else {
256-
setOperationAction(ISD::FMA, MVT::f32, Expand);
257-
setOperationAction(ISD::SETCC, MVT::f32, Expand);
258277
setOperationAction(ISD::BITCAST, MVT::i32, Expand);
259278
setOperationAction(ISD::BITCAST, MVT::f32, Expand);
260279
setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
261280
setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
262281
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
263282
setOperationAction(ISD::FP_TO_SINT, MVT::i32, Expand);
264-
setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
265-
setOperationAction(ISD::SINT_TO_FP, MVT::i64, Expand);
266-
setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
267-
setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand);
268283
}
269-
setOperationAction(ISD::FMA, MVT::f64, Expand);
284+
285+
setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
286+
setOperationAction(ISD::SINT_TO_FP, MVT::i64, Expand);
287+
setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
288+
setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand);
289+
270290
setOperationAction(ISD::SETCC, MVT::f64, Expand);
271291
setOperationAction(ISD::BITCAST, MVT::i64, Expand);
272292
setOperationAction(ISD::BITCAST, MVT::f64, Expand);

‎llvm/lib/Target/Xtensa/XtensaInstrInfo.td

Lines changed: 17 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1040,10 +1040,12 @@ def UN_S : FCompare<0x01, 0x0b, "un.s", Xtensa_cmpuo, 1>;
10401040

10411041
def ABS_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s),
10421042
"abs.s\t$r, $s",
1043-
[(set FPR:$r, (fabs FPR:$s))]> {
1043+
[(set FPR:$r, (fabs FPR:$s))]>, Requires<[HasSingleFloat]> {
10441044
let t = 0x01;
10451045
}
10461046

1047+
def : Pat<(fabs FPR:$s), (ABS_S $s)>;
1048+
10471049
def ADDEXP_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s),
10481050
"addexp.s\t$r, $s", []>, Requires<[HasSingleFloat]> {
10491051
let t = 0x0E;
@@ -1078,7 +1080,7 @@ def DIVN_S : RRR_Inst<0x00, 0x0A, 0x07, (outs FPR:$r), (ins FPR:$s, FPR:$t),
10781080
"divn.s\t$r, $s, $t", []>, Requires<[HasSingleFloat]>;
10791081

10801082
def FLOAT_S : RRR_Inst<0x00, 0x0A, 0x0c, (outs FPR:$r), (ins AR:$s, uimm4:$imm),
1081-
"float.s\t$r, $s, $imm", []> {
1083+
"float.s\t$r, $s, $imm", []>, Requires<[HasSingleFloat]> {
10821084
bits<4> imm;
10831085

10841086
let t = imm;
@@ -1108,6 +1110,9 @@ def MADD_S : RRR_Inst<0x00, 0x0A, 0x04, (outs FPR:$r), (ins FPR:$a, FPR:$s, FPR:
11081110
let Constraints = "$r = $a";
11091111
}
11101112

1113+
def : Pat<(fma FPR:$r, FPR:$s, FPR:$t),
1114+
(MADD_S $r, $s, $t)>;
1115+
11111116
def MKDADJ_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s),
11121117
"mkdadj.s\t$r, $s", []>, Requires<[HasSingleFloat]> {
11131118
let t = 0x0D;
@@ -1159,7 +1164,7 @@ def NEXP01_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s),
11591164

11601165
def NEG_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s),
11611166
"neg.s\t$r, $s",
1162-
[(set FPR:$r, (fneg FPR:$s))]> {
1167+
[(set FPR:$r, (fneg FPR:$s))]>, Requires<[HasSingleFloat]> {
11631168
let t = 0x06;
11641169
}
11651170

@@ -1170,7 +1175,7 @@ def RECIP0_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s),
11701175

11711176
def RFR : RRR_Inst<0x00, 0x0A, 0x0f, (outs AR:$r), (ins FPR:$s),
11721177
"rfr\t$r, $s",
1173-
[(set AR:$r, (bitconvert FPR:$s))]> {
1178+
[(set AR:$r, (bitconvert FPR:$s))]>, Requires<[HasSingleFloat]> {
11741179
let t = 0x04;
11751180
}
11761181

@@ -1192,16 +1197,16 @@ def SQRT0_S : RRR_Inst<0x00, 0x0A, 0x0F, (outs FPR:$r), (ins FPR:$s),
11921197
}
11931198

11941199
def TRUNC_S : RRR_Inst<0x00, 0x0A, 0x09, (outs AR:$r), (ins FPR:$s, uimm4:$imm),
1195-
"trunc.s\t$r, $s, $imm", []> {
1200+
"trunc.s\t$r, $s, $imm", []>, Requires<[HasSingleFloat]> {
11961201
bits<4> imm;
11971202

11981203
let t = imm;
11991204
}
12001205

1201-
def : Pat<(i32 (fp_to_sint FPR:$s)), (TRUNC_S FPR:$s, 0)>;
1206+
def : Pat<(i32 (any_fp_to_sint FPR:$s)), (TRUNC_S FPR:$s, 0)>;
12021207

12031208
def UFLOAT_S : RRR_Inst<0x00, 0x0A, 0x0D, (outs FPR:$r), (ins AR:$s, uimm4:$imm),
1204-
"ufloat.s\t$r, $s, $imm", []> {
1209+
"ufloat.s\t$r, $s, $imm", []>, Requires<[HasSingleFloat]> {
12051210
bits<4> imm;
12061211

12071212
let t = imm;
@@ -1210,22 +1215,22 @@ def UFLOAT_S : RRR_Inst<0x00, 0x0A, 0x0D, (outs FPR:$r), (ins AR:$s, uimm4:$imm)
12101215
def : Pat<(f32 (uint_to_fp AR:$s)), (UFLOAT_S AR:$s, 0)>;
12111216

12121217
def UTRUNC_S : RRR_Inst<0x00, 0x0A, 0x0e, (outs AR:$r), (ins FPR:$s, uimm4:$imm),
1213-
"utrunc.s\t$r, $s, $imm", []> {
1218+
"utrunc.s\t$r, $s, $imm", []>, Requires<[HasSingleFloat]> {
12141219
bits<4> imm;
12151220

12161221
let t = imm;
12171222
}
12181223

1219-
def : Pat<(i32 (fp_to_uint FPR:$s)), (UTRUNC_S FPR:$s, 0)>;
1224+
def : Pat<(i32 (any_fp_to_uint FPR:$s)), (UTRUNC_S FPR:$s, 0)>;
12201225

12211226
def WFR : RRR_Inst<0x00, 0x0A, 0x0f, (outs FPR:$r), (ins AR:$s),
12221227
"wfr\t$r, $s",
1223-
[(set FPR:$r, (bitconvert AR:$s))]> {
1228+
[(set FPR:$r, (bitconvert AR:$s))]>, Requires<[HasSingleFloat]> {
12241229
let t = 0x05;
12251230
}
12261231

12271232
// FP select operations
1228-
let usesCustomInserter = 1 in {
1233+
let usesCustomInserter = 1, Predicates = [HasSingleFloat] in {
12291234
def SELECT_CC_FP_INT : Pseudo<(outs AR:$dst), (ins FPR:$lhs, FPR:$rhs, AR:$t, AR:$f, i32imm:$cond),
12301235
"!select_cc_fp_int $dst, $lhs, $rhs, $t, $f, $cond",
12311236
[(set AR:$dst, (Xtensa_select_cc_fp FPR:$lhs, FPR:$rhs, AR:$t, AR:$f, imm:$cond))]>;
@@ -1238,7 +1243,7 @@ let usesCustomInserter = 1 in {
12381243
}
12391244

12401245
// FP brcc pesudo operation
1241-
let usesCustomInserter = 1, isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1246+
let usesCustomInserter = 1, isBranch = 1, isTerminator = 1, isBarrier = 1, Predicates = [HasSingleFloat] in {
12421247
def BRCC_FP : Pseudo<(outs), (ins i32imm:$cond, FPR:$lhs, FPR:$rhs, brtarget:$target),
12431248
"!brcc_fp $cond, $lhs, $rhs, $target",
12441249
[(Xtensa_brcc_fp imm:$cond, FPR:$lhs, FPR:$rhs, bb:$target)]>;

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