fixes from David to make it actually NFC

jroelofs · dtellenbach · jroelofs · commit 4ab6eee235e6 · 2025-11-07T07:51:11.000-08:00
Co-Authored-By: David Tellenbach &lt;dtellenbach@apple.com&gt;
diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -723,7 +723,8 @@ void AArch64FrameLowering::resetCFIToInitialState(
   CFIBuilder.buildDefCFA(AArch64::SP, 0);
 
   // Flip the RA sign state.
-  if (MFI.shouldSignReturnAddress(MF))
+  if (MFI.shouldSignReturnAddress(MF) &&
+      !MF.getTarget().getTargetTriple().isOSDarwin())
     MFI.branchProtectionPAuthLR() ? CFIBuilder.buildNegateRAStateWithPC()
                                   : CFIBuilder.buildNegateRAState();
 
@@ -984,7 +985,8 @@ bool AArch64FrameLowering::shouldSignReturnAddressEverywhere(
   if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI())
     return false;
   const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
-  bool SignReturnAddressAll = AFI->shouldSignReturnAddress(/*SpillsLR=*/false);
+  bool SignReturnAddressAll =
+      AFI->shouldSignReturnAddress(MF, /*SpillsLR=*/false);
   return SignReturnAddressAll;
 }
 
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -9555,8 +9555,10 @@ outliningCandidatesSigningScopeConsensus(const outliner::Candidate &a,
   const auto &MFIa = a.getMF()->getInfo<AArch64FunctionInfo>();
   const auto &MFIb = b.getMF()->getInfo<AArch64FunctionInfo>();
 
-  return MFIa->shouldSignReturnAddress(false) == MFIb->shouldSignReturnAddress(false) &&
-         MFIa->shouldSignReturnAddress(true) == MFIb->shouldSignReturnAddress(true);
+  return MFIa->shouldSignReturnAddress(*a.getMF(), false) ==
+             MFIb->shouldSignReturnAddress(*b.getMF(), false) &&
+         MFIa->shouldSignReturnAddress(*a.getMF(), true) ==
+             MFIb->shouldSignReturnAddress(*b.getMF(), true);
 }
 
 static bool
@@ -9626,10 +9628,8 @@ AArch64InstrInfo::getOutliningCandidateInfo(
   // Performing a tail call may require extra checks when PAuth is enabled.
   // If PAuth is disabled, set it to zero for uniformity.
   unsigned NumBytesToCheckLRInTCEpilogue = 0;
-  if (RepeatedSequenceLocs[0]
-          .getMF()
-          ->getInfo<AArch64FunctionInfo>()
-          ->shouldSignReturnAddress(true)) {
+  const MachineFunction &MF = *RepeatedSequenceLocs[0].getMF();
+  if (MF.getInfo<AArch64FunctionInfo>()->shouldSignReturnAddress(MF, true)) {
     // One PAC and one AUT instructions
     NumBytesToCreateFrame += 8;
 
@@ -10433,7 +10433,7 @@ void AArch64InstrInfo::buildOutlinedFrame(
     Et = MBB.insert(Et, LDRXpost);
   }
 
-  bool ShouldSignReturnAddr = FI->shouldSignReturnAddress(!IsLeafFunction);
+  bool ShouldSignReturnAddr = FI->shouldSignReturnAddress(MF, !IsLeafFunction);
 
   // If this is a tail call outlined function, then there's already a return.
   if (OF.FrameConstructionID == MachineOutlinerTailCall ||
diff --git a/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp b/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
@@ -172,7 +172,18 @@ MachineFunctionInfo *AArch64FunctionInfo::clone(
   return DestMF.cloneInfo<AArch64FunctionInfo>(*this);
 }
 
-bool AArch64FunctionInfo::shouldSignReturnAddress(bool SpillsLR) const {
+static bool shouldAuthenticateLR(const MachineFunction &MF) {
+  // Return address authentication can be enabled at the function level, using
+  // the "ptrauth-returns" attribute.
+  const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
+  return Subtarget.isTargetMachO() &&
+         MF.getFunction().hasFnAttribute("ptrauth-returns");
+}
+
+bool AArch64FunctionInfo::shouldSignReturnAddress(const MachineFunction &MF,
+                                                  bool SpillsLR) const {
+  if (SpillsLR && shouldAuthenticateLR(MF))
+    return true;
   if (!SignReturnAddress)
     return false;
   if (SignReturnAddressAll)
@@ -188,7 +199,7 @@ static bool isLRSpilled(const MachineFunction &MF) {
 
 bool AArch64FunctionInfo::shouldSignReturnAddress(
     const MachineFunction &MF) const {
-  return shouldSignReturnAddress(isLRSpilled(MF));
+  return shouldSignReturnAddress(MF, isLRSpilled(MF));
 }
 
 bool AArch64FunctionInfo::needsShadowCallStackPrologueEpilogue(
diff --git a/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h b/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
@@ -596,7 +596,7 @@ class AArch64FunctionInfo final : public MachineFunctionInfo {
   }
 
   bool shouldSignReturnAddress(const MachineFunction &MF) const;
-  bool shouldSignReturnAddress(bool SpillsLR) const;
+  bool shouldSignReturnAddress(const MachineFunction &MF, bool SpillsLR) const;
 
   bool needsShadowCallStackPrologueEpilogue(MachineFunction &MF) const;
 
diff --git a/llvm/lib/Target/AArch64/AArch64PointerAuth.cpp b/llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
@@ -14,8 +14,10 @@
 #include "AArch64Subtarget.h"
 #include "llvm/CodeGen/CFIInstBuilder.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/IR/CallingConv.h"
 
 using namespace llvm;
 using namespace llvm::AArch64PAuth;
@@ -96,6 +98,9 @@ static void emitPACCFI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
   if (!EmitCFI)
     return;
 
+  if (MBB.getParent()->getTarget().getTargetTriple().isOSDarwin())
+    return;
+
   auto &MF = *MBB.getParent();
   auto &MFnI = *MF.getInfo<AArch64FunctionInfo>();
 
@@ -116,7 +121,7 @@ void AArch64PointerAuth::signLR(MachineFunction &MF,
   // Debug location must be unknown, see AArch64FrameLowering::emitPrologue.
   DebugLoc DL;
 
-  if (UseBKey) {
+  if (UseBKey && !MF.getTarget().getTargetTriple().isOSDarwin()) {
     BuildMI(MBB, MBBI, DL, TII->get(AArch64::EMITBKEY))
         .setMIFlag(MachineInstr::FrameSetup);
   }
@@ -133,17 +138,15 @@ void AArch64PointerAuth::signLR(MachineFunction &MF,
   if (MFnI.branchProtectionPAuthLR() && Subtarget->hasPAuthLR()) {
     emitPACCFI(MBB, MBBI, MachineInstr::FrameSetup, EmitCFI);
     BuildMI(MBB, MBBI, DL,
-            TII->get(MFnI.shouldSignWithBKey() ? AArch64::PACIBSPPC
-                                               : AArch64::PACIASPPC))
+            TII->get(UseBKey ? AArch64::PACIBSPPC : AArch64::PACIASPPC))
         .setMIFlag(MachineInstr::FrameSetup)
         ->setPreInstrSymbol(MF, MFnI.getSigningInstrLabel());
   } else {
     BuildPACM(*Subtarget, MBB, MBBI, DL, MachineInstr::FrameSetup);
     if (MFnI.branchProtectionPAuthLR())
       emitPACCFI(MBB, MBBI, MachineInstr::FrameSetup, EmitCFI);
     BuildMI(MBB, MBBI, DL,
-            TII->get(MFnI.shouldSignWithBKey() ? AArch64::PACIBSP
-                                               : AArch64::PACIASP))
+            TII->get(UseBKey ? AArch64::PACIBSP : AArch64::PACIASP))
         .setMIFlag(MachineInstr::FrameSetup)
         ->setPreInstrSymbol(MF, MFnI.getSigningInstrLabel());
     if (!MFnI.branchProtectionPAuthLR())
diff --git a/llvm/lib/Target/AArch64/AArch64PrologueEpilogue.cpp b/llvm/lib/Target/AArch64/AArch64PrologueEpilogue.cpp
@@ -1843,6 +1843,7 @@ void AArch64EpilogueEmitter::finalizeEpilogue() const {
   }
   if (EmitCFI)
     emitCalleeSavedGPRRestores(MBB.getFirstTerminator());
+
   if (AFI->shouldSignReturnAddress(MF)) {
     // If pac-ret+leaf is in effect, PAUTH_EPILOGUE pseudo instructions
     // are inserted by emitPacRetPlusLeafHardening().
diff --git a/llvm/test/CodeGen/AArch64/ptrauth-invoke-wrapper-globals.ll b/llvm/test/CodeGen/AArch64/ptrauth-invoke-wrapper-globals.ll
@@ -7,9 +7,7 @@
 ; CHECK-NEXT:  .cfi_personality 155, ___gxx_personality_v0
 ; CHECK-NEXT:  .cfi_lsda 16, [[EXCEPT:Lexception[0-9]+]]
 ; CHECK-NEXT: ; %bb.0:
-; CHECK-NEXT:  .cfi_b_key_frame
 ; CHECK-NEXT:  pacibsp
-; CHECK-NEXT:  .cfi_negate_ra_state
 ; CHECK-NEXT:  stp x20, x19, [sp, #-32]!
 ; CHECK-NEXT:  stp x29, x30, [sp, #16]
 ; CHECK-NEXT:  .cfi_def_cfa_offset 32
@@ -59,9 +57,7 @@ continuebb:
 ; CHECK-NEXT:  .cfi_personality 155, ___gxx_personality_v0
 ; CHECK-NEXT:  .cfi_lsda 16, [[EXCEPT:Lexception[0-9]+]]
 ; CHECK-NEXT: ; %bb.0:
-; CHECK-NEXT:  .cfi_b_key_frame
 ; CHECK-NEXT:  pacibsp
-; CHECK-NEXT:  .cfi_negate_ra_state
 ; CHECK-NEXT:  stp x20, x19, [sp, #-32]!
 ; CHECK-NEXT:  stp x29, x30, [sp, #16]
 ; CHECK-NEXT:  .cfi_def_cfa_offset 32
@@ -116,9 +112,7 @@ continuebb:
 ; CHECK-NEXT:         .cfi_personality 155, ___gxx_personality_v0
 ; CHECK-NEXT:         .cfi_lsda 16, [[EXCEPT:Lexception[0-9]+]]
 ; CHECK-NEXT: ; %bb.0:
-; CHECK-NEXT:         .cfi_b_key_frame
 ; CHECK-NEXT:         pacibsp
-; CHECK-NEXT:         .cfi_negate_ra_state
 ; CHECK-NEXT:         stp x20, x19, [sp, #-32]!
 ; CHECK-NEXT:         stp x29, x30, [sp, #16]
 ; CHECK-NEXT:         .cfi_def_cfa_offset 32
diff --git a/llvm/test/CodeGen/AArch64/swiftcorocc-call.ll b/llvm/test/CodeGen/AArch64/swiftcorocc-call.ll
@@ -10,9 +10,7 @@ declare i64 @g(ptr, ptr)
 define i64 @test_call_to_swiftcoro() #0 {
 ; CHECK-LABEL: test_call_to_swiftcoro:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    .cfi_b_key_frame
 ; CHECK-NEXT:    pacibsp
-; CHECK-NEXT:    .cfi_negate_ra_state
 ; CHECK-NEXT:    stp x26, x25, [sp, #-32]! ; 16-byte Folded Spill
 ; CHECK-NEXT:    stp x29, x30, [sp, #16] ; 16-byte Folded Spill
 ; CHECK-NEXT:    add x29, sp, #16
@@ -43,9 +41,7 @@ define i64 @test_call_to_swiftcoro() #0 {
 define i64 @test_call_to_normal() #0 {
 ; CHECK-LABEL: test_call_to_normal:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    .cfi_b_key_frame
 ; CHECK-NEXT:    pacibsp
-; CHECK-NEXT:    .cfi_negate_ra_state
 ; CHECK-NEXT:    sub sp, sp, #48
 ; CHECK-NEXT:    stp x26, x25, [sp, #16] ; 16-byte Folded Spill
 ; CHECK-NEXT:    stp x29, x30, [sp, #32] ; 16-byte Folded Spill
@@ -75,9 +71,7 @@ define i64 @test_call_to_normal() #0 {
 define swiftcorocc i64 @test_call() #0 {
 ; CHECK-LABEL: test_call:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    .cfi_b_key_frame
 ; CHECK-NEXT:    pacibsp
-; CHECK-NEXT:    .cfi_negate_ra_state
 ; CHECK-NEXT:    sub sp, sp, #48
 ; CHECK-NEXT:    stp x26, x25, [sp, #16] ; 16-byte Folded Spill
 ; CHECK-NEXT:    stp x29, x30, [sp, #32] ; 16-byte Folded Spill
@@ -105,9 +99,7 @@ define swiftcorocc i64 @test_call() #0 {
 define i64 @test_call_normal() #0 {
 ; CHECK-LABEL: test_call_normal:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    .cfi_b_key_frame
 ; CHECK-NEXT:    pacibsp
-; CHECK-NEXT:    .cfi_negate_ra_state
 ; CHECK-NEXT:    sub sp, sp, #48
 ; CHECK-NEXT:    stp x26, x25, [sp, #16] ; 16-byte Folded Spill
 ; CHECK-NEXT:    stp x29, x30, [sp, #32] ; 16-byte Folded Spill
diff --git a/llvm/test/CodeGen/AArch64/swiftcorocc-ret-popless.ll b/llvm/test/CodeGen/AArch64/swiftcorocc-ret-popless.ll
@@ -7,9 +7,7 @@ declare i64 @g(ptr, ptr)
 define swiftcorocc i64 @test_intrin_basic() #0 {
 ; CHECK-LABEL: test_intrin_basic:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    .cfi_b_key_frame
 ; CHECK-NEXT:    pacibsp
-; CHECK-NEXT:    .cfi_negate_ra_state
 ; CHECK-NEXT:    stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
 ; CHECK-NEXT:    mov x29, sp
 ; CHECK-NEXT:    .cfi_def_cfa w29, 16
@@ -24,9 +22,7 @@ define swiftcorocc i64 @test_intrin_basic() #0 {
 define swiftcorocc i64 @test_intrin() #0 {
 ; CHECK-LABEL: test_intrin:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    .cfi_b_key_frame
 ; CHECK-NEXT:    pacibsp
-; CHECK-NEXT:    .cfi_negate_ra_state
 ; CHECK-NEXT:    sub sp, sp, #48
 ; CHECK-NEXT:    stp x26, x25, [sp, #16] ; 16-byte Folded Spill
 ; CHECK-NEXT:    stp x29, x30, [sp, #32] ; 16-byte Folded Spill
@@ -67,9 +63,7 @@ else:
 define swiftcorocc i64 @test_vla(i32 %n) #0 {
 ; SDISEL-LABEL: test_vla:
 ; SDISEL:       ; %bb.0:
-; SDISEL-NEXT:    .cfi_b_key_frame
 ; SDISEL-NEXT:    pacibsp
-; SDISEL-NEXT:    .cfi_negate_ra_state
 ; SDISEL-NEXT:    stp x26, x25, [sp, #-32]! ; 16-byte Folded Spill
 ; SDISEL-NEXT:    stp x29, x30, [sp, #16] ; 16-byte Folded Spill
 ; SDISEL-NEXT:    add x29, sp, #16
@@ -104,9 +98,7 @@ define swiftcorocc i64 @test_vla(i32 %n) #0 {
 ;
 ; GISEL-LABEL: test_vla:
 ; GISEL:       ; %bb.0:
-; GISEL-NEXT:    .cfi_b_key_frame
 ; GISEL-NEXT:    pacibsp
-; GISEL-NEXT:    .cfi_negate_ra_state
 ; GISEL-NEXT:    stp x26, x25, [sp, #-32]! ; 16-byte Folded Spill
 ; GISEL-NEXT:    stp x29, x30, [sp, #16] ; 16-byte Folded Spill
 ; GISEL-NEXT:    add x29, sp, #16

Original file line number	Diff line number	Diff line change
`@@ -596,7 +596,7 @@ class AArch64FunctionInfo final : public MachineFunctionInfo {`
`596`	`596`	`}`
`597`	`597`
`598`	`598`	`bool shouldSignReturnAddress(const MachineFunction &MF) const;`
`599`		`- bool shouldSignReturnAddress(bool SpillsLR) const;`
	`599`	`+ bool shouldSignReturnAddress(const MachineFunction &MF, bool SpillsLR) const;`
`600`	`600`
`601`	`601`	`bool needsShadowCallStackPrologueEpilogue(MachineFunction &MF) const;`
`602`	`602`
Original file line number	Diff line number	Diff line change
`@@ -1843,6 +1843,7 @@ void AArch64EpilogueEmitter::finalizeEpilogue() const {`
`1843`	`1843`	`}`
`1844`	`1844`	`if (EmitCFI)`
`1845`	`1845`	`emitCalleeSavedGPRRestores(MBB.getFirstTerminator());`
	`1846`	`+`
`1846`	`1847`	`if (AFI->shouldSignReturnAddress(MF)) {`
`1847`	`1848`	`// If pac-ret+leaf is in effect, PAUTH_EPILOGUE pseudo instructions`
`1848`	`1849`	`// are inserted by emitPacRetPlusLeafHardening().`