diff --git a/README.md b/README.md index 90fb910d07..d37f286119 100644 --- a/README.md +++ b/README.md @@ -889,6 +889,8 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32WLE5CC | [RAK3172T Module](https://github.com/RAKWireless/rakwireless-docs/tree/master/docs/Product-Categories/WisDuo/RAK3172-Module) | *2.8.1* | RAK3172 Module with TCXO | | :green_heart: | STM32L151CB | [RAK811 LoRa Tracker](https://www.rakwireless.com/en/) | *1.4.0* | [Wiki](https://github.com/stm32duino/Arduino_Core_STM32/wiki/Connectivities#lora) | | :green_heart: | STM32L051C8 | [RHF76-052](https://lora-alliance.org/lora_products/rhf76-052/) | *1.7.0* | Basic support | +| :yellow_heart: | STM32WLE5CC | [Oceanus-I Module](https://www.we-online.com/en/components/products/OCEANUS-I) | **2.11.0** | [User Manual](https://www.we-online.com/en/components/products/manual/2618011182000)
LoRa & LoRaWAN support with [STM32LoRaWAN](https://github.com/stm32duino/STM32LoRaWAN) | +| :yellow_heart: | STM32WLE5CC | [Oceanus-I EV](https://www.we-online.com/en/components/products/OCEANUS-I) | **2.11.0** | [User Manual](https://www.we-online.com/en/components/products/manual/2618019382001)
LoRa & LoRaWAN support with [STM32LoRaWAN](https://github.com/stm32duino/STM32LoRaWAN) | ### Midatronics boards diff --git a/boards.txt b/boards.txt index df2d8ed270..d20b45ebaa 100644 --- a/boards.txt +++ b/boards.txt @@ -14211,6 +14211,34 @@ LoRa.menu.pnum.ELEKTOR_F072CB.build.st_extra_flags=-D{build.product_line} {build LoRa.menu.pnum.ELEKTOR_F072CB.openocd.target=stm32f0x LoRa.menu.pnum.ELEKTOR_F072CB.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F0xx/STM32F0x2.svd +# Oceanus-I Module +LoRa.menu.pnum.WE_OCEANUS1=Oceanus-I Module +LoRa.menu.pnum.WE_OCEANUS1.upload.maximum_size=262144 +LoRa.menu.pnum.WE_OCEANUS1.upload.maximum_data_size=65536 +LoRa.menu.pnum.WE_OCEANUS1.build.mcu=cortex-m4 +LoRa.menu.pnum.WE_OCEANUS1.build.board=WE_OCEANUS1 +LoRa.menu.pnum.WE_OCEANUS1.build.series=STM32WLxx +LoRa.menu.pnum.WE_OCEANUS1.build.product_line=STM32WLE5xx +LoRa.menu.pnum.WE_OCEANUS1.build.variant=STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U +LoRa.menu.pnum.WE_OCEANUS1.build.variant_h=variant_WE_OCEANUS1.h +LoRa.menu.pnum.WE_OCEANUS1.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS +LoRa.menu.pnum.WE_OCEANUS1.openocd.target=stm32wlx +LoRa.menu.pnum.WE_OCEANUS1.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WLxx/STM32WLE5_CM4.svd + +# Oceanus-I EV +LoRa.menu.pnum.WE_OCEANUS1_EV=Oceanus-I EV +LoRa.menu.pnum.WE_OCEANUS1_EV.upload.maximum_size=262144 +LoRa.menu.pnum.WE_OCEANUS1_EV.upload.maximum_data_size=65536 +LoRa.menu.pnum.WE_OCEANUS1_EV.build.mcu=cortex-m4 +LoRa.menu.pnum.WE_OCEANUS1_EV.build.board=WE_OCEANUS1_EV +LoRa.menu.pnum.WE_OCEANUS1_EV.build.series=STM32WLxx +LoRa.menu.pnum.WE_OCEANUS1_EV.build.product_line=STM32WLE5xx +LoRa.menu.pnum.WE_OCEANUS1_EV.build.variant=STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U +LoRa.menu.pnum.WE_OCEANUS1_EV.build.variant_h=variant_WE_OCEANUS1_EV.h +LoRa.menu.pnum.WE_OCEANUS1_EV.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS +LoRa.menu.pnum.WE_OCEANUS1_EV.openocd.target=stm32wlx +LoRa.menu.pnum.WE_OCEANUS1_EV.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WLxx/STM32WLE5_CM4.svd + # Upload menu LoRa.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) LoRa.menu.upload_method.swdMethod.upload.protocol=swd diff --git a/cmake/boards_db.cmake b/cmake/boards_db.cmake index 0ea33492d1..0f9c99efa5 100644 --- a/cmake/boards_db.cmake +++ b/cmake/boards_db.cmake @@ -7618,6 +7618,286 @@ target_compile_options(GENERIC_C071RBTX_usb_none INTERFACE "SHELL:" ) +# GENERIC_C092CBTX +# ----------------------------------------------------------------------------- + +set(GENERIC_C092CBTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)") +set(GENERIC_C092CBTX_MAXSIZE 131072) +set(GENERIC_C092CBTX_MAXDATASIZE 30720) +set(GENERIC_C092CBTX_MCU cortex-m0plus) +set(GENERIC_C092CBTX_FPCONF "-") +add_library(GENERIC_C092CBTX INTERFACE) +target_compile_options(GENERIC_C092CBTX INTERFACE + "SHELL:-DSTM32C092xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_C092CBTX_MCU} +) +target_compile_definitions(GENERIC_C092CBTX INTERFACE + "STM32C0xx" + "ARDUINO_GENERIC_C092CBTX" + "BOARD_NAME=\"GENERIC_C092CBTX\"" + "BOARD_ID=GENERIC_C092CBTX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_C092CBTX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32C0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ + ${GENERIC_C092CBTX_VARIANT_PATH} +) + +target_link_options(GENERIC_C092CBTX INTERFACE + "LINKER:--default-script=${GENERIC_C092CBTX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=30720" + "SHELL: " + -mcpu=${GENERIC_C092CBTX_MCU} +) + +add_library(GENERIC_C092CBTX_serial_disabled INTERFACE) +target_compile_options(GENERIC_C092CBTX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_C092CBTX_serial_generic INTERFACE) +target_compile_options(GENERIC_C092CBTX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_C092CBTX_serial_none INTERFACE) +target_compile_options(GENERIC_C092CBTX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_C092CBTX_usb_CDC INTERFACE) +target_compile_options(GENERIC_C092CBTX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_C092CBTX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_C092CBTX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_C092CBTX_usb_HID INTERFACE) +target_compile_options(GENERIC_C092CBTX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_C092CBTX_usb_none INTERFACE) +target_compile_options(GENERIC_C092CBTX_usb_none INTERFACE + "SHELL:" +) + +# GENERIC_C092RBTX +# ----------------------------------------------------------------------------- + +set(GENERIC_C092RBTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)") +set(GENERIC_C092RBTX_MAXSIZE 131072) +set(GENERIC_C092RBTX_MAXDATASIZE 30720) +set(GENERIC_C092RBTX_MCU cortex-m0plus) +set(GENERIC_C092RBTX_FPCONF "-") +add_library(GENERIC_C092RBTX INTERFACE) +target_compile_options(GENERIC_C092RBTX INTERFACE + "SHELL:-DSTM32C092xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_C092RBTX_MCU} +) +target_compile_definitions(GENERIC_C092RBTX INTERFACE + "STM32C0xx" + "ARDUINO_GENERIC_C092RBTX" + "BOARD_NAME=\"GENERIC_C092RBTX\"" + "BOARD_ID=GENERIC_C092RBTX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_C092RBTX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32C0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ + ${GENERIC_C092RBTX_VARIANT_PATH} +) + +target_link_options(GENERIC_C092RBTX INTERFACE + "LINKER:--default-script=${GENERIC_C092RBTX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=30720" + "SHELL: " + -mcpu=${GENERIC_C092RBTX_MCU} +) + +add_library(GENERIC_C092RBTX_serial_disabled INTERFACE) +target_compile_options(GENERIC_C092RBTX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_C092RBTX_serial_generic INTERFACE) +target_compile_options(GENERIC_C092RBTX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_C092RBTX_serial_none INTERFACE) +target_compile_options(GENERIC_C092RBTX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_C092RBTX_usb_CDC INTERFACE) +target_compile_options(GENERIC_C092RBTX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_C092RBTX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_C092RBTX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_C092RBTX_usb_HID INTERFACE) +target_compile_options(GENERIC_C092RBTX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_C092RBTX_usb_none INTERFACE) +target_compile_options(GENERIC_C092RBTX_usb_none INTERFACE + "SHELL:" +) + +# GENERIC_C092RCIX +# ----------------------------------------------------------------------------- + +set(GENERIC_C092RCIX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)") +set(GENERIC_C092RCIX_MAXSIZE 262144) +set(GENERIC_C092RCIX_MAXDATASIZE 30720) +set(GENERIC_C092RCIX_MCU cortex-m0plus) +set(GENERIC_C092RCIX_FPCONF "-") +add_library(GENERIC_C092RCIX INTERFACE) +target_compile_options(GENERIC_C092RCIX INTERFACE + "SHELL:-DSTM32C092xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_C092RCIX_MCU} +) +target_compile_definitions(GENERIC_C092RCIX INTERFACE + "STM32C0xx" + "ARDUINO_GENERIC_C092RCIX" + "BOARD_NAME=\"GENERIC_C092RCIX\"" + "BOARD_ID=GENERIC_C092RCIX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_C092RCIX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32C0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ + ${GENERIC_C092RCIX_VARIANT_PATH} +) + +target_link_options(GENERIC_C092RCIX INTERFACE + "LINKER:--default-script=${GENERIC_C092RCIX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=262144" + "LINKER:--defsym=LD_MAX_DATA_SIZE=30720" + "SHELL: " + -mcpu=${GENERIC_C092RCIX_MCU} +) + +add_library(GENERIC_C092RCIX_serial_disabled INTERFACE) +target_compile_options(GENERIC_C092RCIX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_C092RCIX_serial_generic INTERFACE) +target_compile_options(GENERIC_C092RCIX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_C092RCIX_serial_none INTERFACE) +target_compile_options(GENERIC_C092RCIX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_C092RCIX_usb_CDC INTERFACE) +target_compile_options(GENERIC_C092RCIX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_C092RCIX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_C092RCIX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_C092RCIX_usb_HID INTERFACE) +target_compile_options(GENERIC_C092RCIX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_C092RCIX_usb_none INTERFACE) +target_compile_options(GENERIC_C092RCIX_usb_none INTERFACE + "SHELL:" +) + +# GENERIC_C092RCTX +# ----------------------------------------------------------------------------- + +set(GENERIC_C092RCTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)") +set(GENERIC_C092RCTX_MAXSIZE 262144) +set(GENERIC_C092RCTX_MAXDATASIZE 30720) +set(GENERIC_C092RCTX_MCU cortex-m0plus) +set(GENERIC_C092RCTX_FPCONF "-") +add_library(GENERIC_C092RCTX INTERFACE) +target_compile_options(GENERIC_C092RCTX INTERFACE + "SHELL:-DSTM32C092xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_C092RCTX_MCU} +) +target_compile_definitions(GENERIC_C092RCTX INTERFACE + "STM32C0xx" + "ARDUINO_GENERIC_C092RCTX" + "BOARD_NAME=\"GENERIC_C092RCTX\"" + "BOARD_ID=GENERIC_C092RCTX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_C092RCTX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32C0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ + ${GENERIC_C092RCTX_VARIANT_PATH} +) + +target_link_options(GENERIC_C092RCTX INTERFACE + "LINKER:--default-script=${GENERIC_C092RCTX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=262144" + "LINKER:--defsym=LD_MAX_DATA_SIZE=30720" + "SHELL: " + -mcpu=${GENERIC_C092RCTX_MCU} +) + +add_library(GENERIC_C092RCTX_serial_disabled INTERFACE) +target_compile_options(GENERIC_C092RCTX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_C092RCTX_serial_generic INTERFACE) +target_compile_options(GENERIC_C092RCTX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_C092RCTX_serial_none INTERFACE) +target_compile_options(GENERIC_C092RCTX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_C092RCTX_usb_CDC INTERFACE) +target_compile_options(GENERIC_C092RCTX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_C092RCTX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_C092RCTX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_C092RCTX_usb_HID INTERFACE) +target_compile_options(GENERIC_C092RCTX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_C092RCTX_usb_none INTERFACE) +target_compile_options(GENERIC_C092RCTX_usb_none INTERFACE + "SHELL:" +) + # GENERIC_F030C6TX # ----------------------------------------------------------------------------- @@ -106776,6 +107056,88 @@ target_compile_options(NUCLEO_C071RB_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# NUCLEO_C092RC +# ----------------------------------------------------------------------------- + +set(NUCLEO_C092RC_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C092CBT_C092RBT_C092RC(I-T)") +set(NUCLEO_C092RC_MAXSIZE 262144) +set(NUCLEO_C092RC_MAXDATASIZE 30720) +set(NUCLEO_C092RC_MCU cortex-m0plus) +set(NUCLEO_C092RC_FPCONF "-") +add_library(NUCLEO_C092RC INTERFACE) +target_compile_options(NUCLEO_C092RC INTERFACE + "SHELL:-DSTM32C092xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${NUCLEO_C092RC_MCU} +) +target_compile_definitions(NUCLEO_C092RC INTERFACE + "STM32C0xx" + "ARDUINO_NUCLEO_C092RC" + "BOARD_NAME=\"NUCLEO_C092RC\"" + "BOARD_ID=NUCLEO_C092RC" + "VARIANT_H=\"variant_NUCLEO_C092RC.h\"" +) +target_include_directories(NUCLEO_C092RC INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32C0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ + ${NUCLEO_C092RC_VARIANT_PATH} +) + +target_link_options(NUCLEO_C092RC INTERFACE + "LINKER:--default-script=${NUCLEO_C092RC_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=262144" + "LINKER:--defsym=LD_MAX_DATA_SIZE=30720" + "SHELL: " + -mcpu=${NUCLEO_C092RC_MCU} +) + +add_library(NUCLEO_C092RC_serial_disabled INTERFACE) +target_compile_options(NUCLEO_C092RC_serial_disabled INTERFACE + "SHELL:" +) +add_library(NUCLEO_C092RC_serial_generic INTERFACE) +target_compile_options(NUCLEO_C092RC_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(NUCLEO_C092RC_serial_none INTERFACE) +target_compile_options(NUCLEO_C092RC_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(NUCLEO_C092RC_usb_CDC INTERFACE) +target_compile_options(NUCLEO_C092RC_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(NUCLEO_C092RC_usb_CDCgen INTERFACE) +target_compile_options(NUCLEO_C092RC_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(NUCLEO_C092RC_usb_HID INTERFACE) +target_compile_options(NUCLEO_C092RC_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(NUCLEO_C092RC_usb_none INTERFACE) +target_compile_options(NUCLEO_C092RC_usb_none INTERFACE + "SHELL:" +) +add_library(NUCLEO_C092RC_xusb_FS INTERFACE) +target_compile_options(NUCLEO_C092RC_xusb_FS INTERFACE + "SHELL:" +) +add_library(NUCLEO_C092RC_xusb_HS INTERFACE) +target_compile_options(NUCLEO_C092RC_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(NUCLEO_C092RC_xusb_HSFS INTERFACE) +target_compile_options(NUCLEO_C092RC_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # NUCLEO_F030R8 # ----------------------------------------------------------------------------- @@ -115220,6 +115582,114 @@ target_link_options(VCCGND_F407ZG_MINI_hid INTERFACE ) +# WE_OCEANUS1 +# ----------------------------------------------------------------------------- + +set(WE_OCEANUS1_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U") +set(WE_OCEANUS1_MAXSIZE 262144) +set(WE_OCEANUS1_MAXDATASIZE 65536) +set(WE_OCEANUS1_MCU cortex-m4) +set(WE_OCEANUS1_FPCONF "-") +add_library(WE_OCEANUS1 INTERFACE) +target_compile_options(WE_OCEANUS1 INTERFACE + "SHELL:-DSTM32WLE5xx" + "SHELL:-DCUSTOM_PERIPHERAL_PINS" + "SHELL:" + "SHELL: " + -mcpu=${WE_OCEANUS1_MCU} +) +target_compile_definitions(WE_OCEANUS1 INTERFACE + "STM32WLxx" + "ARDUINO_WE_OCEANUS1" + "BOARD_NAME=\"WE_OCEANUS1\"" + "BOARD_ID=WE_OCEANUS1" + "VARIANT_H=\"variant_WE_OCEANUS1.h\"" +) +target_include_directories(WE_OCEANUS1 INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32WLxx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/ + ${WE_OCEANUS1_VARIANT_PATH} +) + +target_link_options(WE_OCEANUS1 INTERFACE + "LINKER:--default-script=${WE_OCEANUS1_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=262144" + "LINKER:--defsym=LD_MAX_DATA_SIZE=65536" + "SHELL: " + -mcpu=${WE_OCEANUS1_MCU} +) + +add_library(WE_OCEANUS1_serial_disabled INTERFACE) +target_compile_options(WE_OCEANUS1_serial_disabled INTERFACE + "SHELL:" +) +add_library(WE_OCEANUS1_serial_generic INTERFACE) +target_compile_options(WE_OCEANUS1_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(WE_OCEANUS1_serial_none INTERFACE) +target_compile_options(WE_OCEANUS1_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) + +# WE_OCEANUS1_EV +# ----------------------------------------------------------------------------- + +set(WE_OCEANUS1_EV_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U") +set(WE_OCEANUS1_EV_MAXSIZE 262144) +set(WE_OCEANUS1_EV_MAXDATASIZE 65536) +set(WE_OCEANUS1_EV_MCU cortex-m4) +set(WE_OCEANUS1_EV_FPCONF "-") +add_library(WE_OCEANUS1_EV INTERFACE) +target_compile_options(WE_OCEANUS1_EV INTERFACE + "SHELL:-DSTM32WLE5xx" + "SHELL:-DCUSTOM_PERIPHERAL_PINS" + "SHELL:" + "SHELL: " + -mcpu=${WE_OCEANUS1_EV_MCU} +) +target_compile_definitions(WE_OCEANUS1_EV INTERFACE + "STM32WLxx" + "ARDUINO_WE_OCEANUS1_EV" + "BOARD_NAME=\"WE_OCEANUS1_EV\"" + "BOARD_ID=WE_OCEANUS1_EV" + "VARIANT_H=\"variant_WE_OCEANUS1_EV.h\"" +) +target_include_directories(WE_OCEANUS1_EV INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32WLxx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WLxx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/ + ${WE_OCEANUS1_EV_VARIANT_PATH} +) + +target_link_options(WE_OCEANUS1_EV INTERFACE + "LINKER:--default-script=${WE_OCEANUS1_EV_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=262144" + "LINKER:--defsym=LD_MAX_DATA_SIZE=65536" + "SHELL: " + -mcpu=${WE_OCEANUS1_EV_MCU} +) + +add_library(WE_OCEANUS1_EV_serial_disabled INTERFACE) +target_compile_options(WE_OCEANUS1_EV_serial_disabled INTERFACE + "SHELL:" +) +add_library(WE_OCEANUS1_EV_serial_generic INTERFACE) +target_compile_options(WE_OCEANUS1_EV_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(WE_OCEANUS1_EV_serial_none INTERFACE) +target_compile_options(WE_OCEANUS1_EV_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) + # WEACT_G474CE # ----------------------------------------------------------------------------- diff --git a/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/CMakeLists.txt b/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/CMakeLists.txt index e7d38eb5df..52c0fac732 100644 --- a/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/CMakeLists.txt +++ b/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/CMakeLists.txt @@ -24,6 +24,8 @@ add_library(variant_bin STATIC EXCLUDE_FROM_ALL variant_generic.cpp variant_GENERIC_NODE_SE_TTI.cpp variant_RAK3172_MODULE.cpp + PeripheralPins_WE_OCEANUS1.c + variant_WE_OCEANUS1.cpp ) target_link_libraries(variant_bin PUBLIC variant_usage) diff --git a/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/PeripheralPins_WE_OCEANUS1.c b/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/PeripheralPins_WE_OCEANUS1.c new file mode 100644 index 0000000000..071fda4eb6 --- /dev/null +++ b/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/PeripheralPins_WE_OCEANUS1.c @@ -0,0 +1,214 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32WL54CCUx.xml, STM32WL55CCUx.xml + * STM32WLE4C8Ux.xml, STM32WLE4CBUx.xml + * STM32WLE4CCUx.xml, STM32WLE5C8Ux.xml + * STM32WLE5CBUx.xml, STM32WLE5CCUx.xml + * CubeMX DB release 6.0.140 + */ +#if defined(ARDUINO_WE_OCEANUS1) || defined(ARDUINO_WE_OCEANUS1_EV) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_10, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC_IN6 + {PA_11, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC_IN7 + {PA_12, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC_IN8 + {PA_13, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC_IN9 + {PA_14, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC_IN10 + {PA_15, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC_IN11 + {PB_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC_IN4 + {PB_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC_IN2 + {PB_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC_IN3 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_10, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT1 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_10, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PA_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PA_15, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PA_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PA_12, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_6, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_2_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_3, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_3_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_1_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + // {PB_12, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_6, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_7_ALT1, SUBGHZSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF13_DEBUG_SUBGHZSPI)}, + {PA_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_5, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_6_ALT1, SUBGHZSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF13_DEBUG_SUBGHZSPI)}, + {PA_11, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_5_ALT1, SUBGHZSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF13_DEBUG_SUBGHZSPI)}, + {PA_8, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SUBGHZSPI, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF13_DEBUG_SUBGHZSPI)}, + {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_2, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + // {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** No USB *** + +//*** No SD *** + +#endif /* ARDUINO_WE_OCEANUS1 || ARDUINO_WE_OCEANUS1_EV */ diff --git a/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/variant_WE_OCEANUS1.cpp b/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/variant_WE_OCEANUS1.cpp new file mode 100644 index 0000000000..f5b9e7f738 --- /dev/null +++ b/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/variant_WE_OCEANUS1.cpp @@ -0,0 +1,115 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_WE_OCEANUS1) || defined(ARDUINO_WE_OCEANUS1_EV) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0 + PA_1, // D1 + PA_2, // D2 - USART2/LPUART1 TX + PA_3, // D3 - USART2/LPUART1 RX + PA_4, // D4 - SPI_NSS + PA_5, // D5 - SPI_SCK + PA_6, // D6 - SPI_MISO + PA_7, // D7 - SPI_MOSI + PA_8, // D8 + PA_9, // D9 + PA_10, // D10/A3 + PA_11, // D11/A7 - I2C_SDA + PA_12, // D12/A8 - I2C_SCL + PA_13, // D13/A5 - SWDIO + PA_14, // D14/A6 - SWCLK + PA_15, // D15/A4 + PB_2, // D16/A2 + PB_3, // D17/A0 + PB_4, // D18/A1 + PB_5, // D19 + PB_6, // D20 - USART1_TX + PB_7, // D21 - USAR1_RX + PB_8, // D22 + PB_12, // D23 + PC_13, // D24 + PH_3 // D25 - BOOT0 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 17, // A0, PB3 + 18, // A1, PB4 + 16, // A2, PB2 + 10, // A3, PA10 + 15, // A4, PA15 + 13, // A5, PA13 + 14, // A6, PA14 + 11, // A7, PA11 + 12 // A8, PA12 +}; + +// ---------------------------------------------------------------------------- +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + + /** Configure LSE Drive Capability + */ + HAL_PWR_EnableBkUpAccess(); + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMLOW); + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + + /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK3 | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.AHBCLK3Divider = RCC_SYSCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { + Error_Handler(); + } +} + +#ifdef __cplusplus +} +#endif + +#endif /* ARDUINO_WE_OCEANUS1 || ARDUINO_WE_OCEANUS1_EV */ diff --git a/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/variant_WE_OCEANUS1.h b/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/variant_WE_OCEANUS1.h new file mode 100644 index 0000000000..d2097ac9bb --- /dev/null +++ b/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/variant_WE_OCEANUS1.h @@ -0,0 +1,175 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 0 +#define PA1 1 +#define PA2 2 +#define PA3 3 +#define PA4 4 +#define PA5 5 +#define PA6 6 +#define PA7 7 +#define PA8 8 +#define PA9 9 +#define PA10 PIN_A3 +#define PA11 PIN_A7 +#define PA12 PIN_A8 +#define PA13 PIN_A5 +#define PA14 PIN_A6 +#define PA15 PIN_A4 +#define PB2 PIN_A2 +#define PB3 PIN_A0 +#define PB4 PIN_A1 +#define PB5 19 +#define PB6 20 +#define PB7 21 +#define PB8 22 +#define PB12 23 +#define PC13 24 +#define PH3 25 + +// Not available +// PB0 +// PC14 +// PC15 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) + +#define NUM_DIGITAL_PINS 26 +#define NUM_ANALOG_INPUTS 9 + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA4 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PB2 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA7 +#endif +#ifndef PIN_SPI_MISOSPI1_SCK + #define PIN_SPI_MISO PA6 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA5 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA11 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA12 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM16 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM17 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 101 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA3 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA2 +#endif + +// Alias +#ifndef DEBUG_SUBGHZSPI_MOSI + #define DEBUG_SUBGHZSPI_MOSI PA7_ALT1 +#endif +#ifndef DEBUG_SUBGHZSPI_MISO + #define DEBUG_SUBGHZSPI_MISO PA6_ALT1 +#endif +#ifndef DEBUG_SUBGHZSPI_SCLK + #define DEBUG_SUBGHZSPI_SCLK PA5_ALT1 +#endif +#ifndef DEBUG_SUBGHZSPI_SS + #define DEBUG_SUBGHZSPI_SS PA4_ALT1 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif + +// LoRaWAN definitions + +#define LORAWAN_BOARD_HAS_TCXO 1U +#define LORAWAN_BOARD_HAS_DCDC 1U +#define LORAWAN_TX_CONFIG RBI_CONF_RFO_LP + +#define LORAWAN_RFSWITCH_PINS PB12, PC13 +#define LORAWAN_RFSWITCH_PIN_COUNT 2 +#define LORAWAN_RFSWITCH_OFF_VALUES LOW, LOW +#define LORAWAN_RFSWITCH_RX_VALUES HIGH, LOW +#define LORAWAN_RFSWITCH_RFO_LP_VALUES HIGH, HIGH +#define LORAWAN_RFSWITCH_RFO_HP_VALUES HIGH, HIGH + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/variant_WE_OCEANUS1_EV.h b/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/variant_WE_OCEANUS1_EV.h new file mode 100644 index 0000000000..439d23cce2 --- /dev/null +++ b/variants/STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U/variant_WE_OCEANUS1_EV.h @@ -0,0 +1,22 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +#include "variant_WE_OCEANUS1.h" + +// On-board LED pin number +#define LED_BUILTIN PA7 + +// On-board user button +#define USER_BTN PA0 +