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Adding check and clear for all error flags
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+12
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+12
-2
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src/i2c.rs

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -840,10 +840,15 @@ where
840840
self.i2c.cr1.modify(|_, w| w.start().set_bit());
841841

842842
// Wait until START condition was generated
843-
while self.i2c.sr1.read().sb().bit_is_clear() {}
843+
while {
844+
self.check_and_clear_error_flags()?;
845+
self.i2c.sr1.read().sb().bit_is_clear()
846+
} {}
844847

845848
// Also wait until signalled we're master and everything is waiting for us
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while {
850+
self.check_and_clear_error_flags()?;
851+
847852
let sr2 = self.i2c.sr2.read();
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sr2.msl().bit_is_clear() && sr2.busy().bit_is_clear()
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} {}
@@ -876,7 +881,12 @@ where
876881

877882
fn send_byte(&self, byte: u8) -> Result<(), Error> {
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// Wait until we're ready for sending
879-
while self.i2c.sr1.read().tx_e().bit_is_clear() {}
884+
while {
885+
// Check for any I2C errors. If a NACK occurs, the ADDR bit will never be set.
886+
self.check_and_clear_error_flags()?;
887+
888+
self.i2c.sr1.read().tx_e().bit_is_clear()
889+
} {}
880890

881891
// Push out a byte of data
882892
self.i2c.dr.write(|w| unsafe { w.bits(u32::from(byte)) });

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