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f2 dma
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‎src/dma/traits/f2.rs

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use super::*;
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dma_map! {
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(Stream0<DMA1>:0, pac::SPI3, [PeripheralToMemory]), //SPI3_RX
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(Stream0<DMA1>:1, pac::I2C1, [PeripheralToMemory]), //I2C1_RX
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(Stream0<DMA1>:2, timer::CCR1<pac::TIM4>, [MemoryToPeripheral | PeripheralToMemory]), //TIM4_CH1
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(Stream0<DMA1>:4, pac::UART5, [PeripheralToMemory]), //UART5_RX
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(Stream0<DMA1>:6, timer::CCR3<pac::TIM5>, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_CH3
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(Stream0<DMA1>:6, timer::DMAR<pac::TIM5>, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_UP
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(Stream1<DMA1>:3, timer::DMAR<pac::TIM2>, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_UP
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(Stream1<DMA1>:3, timer::CCR3<pac::TIM2>, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH3
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(Stream1<DMA1>:4, pac::USART3, [PeripheralToMemory]), //USART3_RX
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(Stream1<DMA1>:6, timer::CCR4<pac::TIM5>, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_CH4
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(Stream1<DMA1>:6, TIM5_TRIG, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_TRIG
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(Stream1<DMA1>:7, TIM6_UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM6_UP
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(Stream2<DMA1>:0, pac::SPI3, [PeripheralToMemory]), //SPI3_RX
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(Stream2<DMA1>:1, TIM7_UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM7_UP
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(Stream2<DMA1>:3, pac::I2C3, [PeripheralToMemory]), //I2C3_RX
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(Stream2<DMA1>:4, pac::UART4, [PeripheralToMemory]), //UART4_RX
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(Stream2<DMA1>:5, timer::CCR4<pac::TIM3>, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_CH4
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(Stream2<DMA1>:5, TIM3_UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_UP
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(Stream2<DMA1>:6, timer::CCR1<pac::TIM5>, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_CH1
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(Stream2<DMA1>:7, pac::I2C2, [PeripheralToMemory]), //I2C2_RX
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(Stream3<DMA1>:0, pac::SPI2, [PeripheralToMemory]), //SPI2_RX
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(Stream3<DMA1>:2, timer::CCR2<pac::TIM4>, [MemoryToPeripheral | PeripheralToMemory]), //TIM4_CH2
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(Stream3<DMA1>:4, pac::USART3, [MemoryToPeripheral]), //USART3_TX
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(Stream3<DMA1>:6, timer::CCR4<pac::TIM5>, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_CH4
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(Stream3<DMA1>:6, TIM5_TRIG, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_TRIG
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(Stream3<DMA1>:7, pac::I2C2, [PeripheralToMemory]), //I2C2_RX
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(Stream4<DMA1>:0, pac::SPI2, [MemoryToPeripheral]), //SPI2_TX
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(Stream4<DMA1>:1, TIM7_UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM7_UP
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(Stream4<DMA1>:3, pac::I2C3, [MemoryToPeripheral]), //I2C3_TX
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(Stream4<DMA1>:4, pac::UART4, [MemoryToPeripheral]), //UART4_TX
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(Stream4<DMA1>:5, timer::CCR1<pac::TIM3>, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_CH1
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(Stream4<DMA1>:5, TIM3_TRIG, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_TRIG
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(Stream4<DMA1>:6, timer::CCR2<pac::TIM5>, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_CH2
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(Stream4<DMA1>:7, pac::USART3, [MemoryToPeripheral]), //USART3_TX:DMA_CHANNEL_7
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(Stream5<DMA1>:0, pac::SPI3, [MemoryToPeripheral]), //SPI3_TX
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(Stream5<DMA1>:1, pac::I2C1, [PeripheralToMemory]), //I2C1_RX
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(Stream5<DMA1>:3, timer::CCR1<pac::TIM2>, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH1
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(Stream5<DMA1>:4, pac::USART2, [PeripheralToMemory]), //USART2_RX
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(Stream5<DMA1>:5, timer::CCR2<pac::TIM3>, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_CH2
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(Stream5<DMA1>:7, pac::DAC1, [MemoryToPeripheral]), //DAC1
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(Stream6<DMA1>:1, pac::I2C1, [MemoryToPeripheral]), //I2C1_TX
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(Stream6<DMA1>:2, TIM4_UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM4_UP
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(Stream6<DMA1>:3, timer::CCR2<pac::TIM2>, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH2
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(Stream6<DMA1>:3, timer::CCR4<pac::TIM2>, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH4
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(Stream6<DMA1>:4, pac::USART2, [MemoryToPeripheral]), //USART2_TX
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(Stream6<DMA1>:6, TIM5_UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM5_UP
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(Stream6<DMA1>:7, pac::DAC2, [MemoryToPeripheral]), //DAC2
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(Stream7<DMA1>:0, pac::SPI3, [MemoryToPeripheral]), //SPI3_TX
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(Stream7<DMA1>:1, pac::I2C1, [MemoryToPeripheral]), //I2C1_TX
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(Stream7<DMA1>:2, timer::CCR3<pac::TIM4>, [MemoryToPeripheral | PeripheralToMemory]), //TIM4_CH3
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(Stream7<DMA1>:3, TIM2_UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_UP
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(Stream7<DMA1>:3, timer::CCR4<pac::TIM2>, [MemoryToPeripheral | PeripheralToMemory]), //TIM2_CH4
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(Stream7<DMA1>:4, pac::UART5, [MemoryToPeripheral]), //UART5_TX
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(Stream7<DMA1>:5, timer::CCR3<pac::TIM3>, [MemoryToPeripheral | PeripheralToMemory]), //TIM3_CH3
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(Stream7<DMA1>:7, pac::I2C2, [MemoryToPeripheral]), //I2C2_TX
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(Stream0<DMA2>:0, pac::ADC1, [PeripheralToMemory]), //ADC1
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(Stream0<DMA2>:2, pac::ADC3, [PeripheralToMemory]), //ADC3
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(Stream0<DMA2>:3, pac::SPI1, [PeripheralToMemory]), //SPI1_RX
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(Stream0<DMA2>:6, TIM1_TRIG, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_TRIG
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(Stream1<DMA2>:1, pac::DCMI, [PeripheralToMemory]), //DCMI
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(Stream1<DMA2>:2, pac::ADC3, [PeripheralToMemory]), //ADC3
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(Stream1<DMA2>:5, pac::USART6, [PeripheralToMemory]), //USART6_RX
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(Stream1<DMA2>:6, timer::CCR1<pac::TIM1>, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH1
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(Stream1<DMA2>:7, TIM8_UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_UP
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(Stream2<DMA2>:0, timer::CCR1<pac::TIM8>, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_CH1
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(Stream2<DMA2>:0, timer::CCR2<pac::TIM8>, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_CH2
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(Stream2<DMA2>:0, timer::CCR3<pac::TIM8>, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_CH3
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(Stream2<DMA2>:1, pac::ADC2, [PeripheralToMemory]), //ADC2
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(Stream2<DMA2>:3, pac::SPI1, [PeripheralToMemory]), //SPI1_RX
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(Stream2<DMA2>:4, pac::USART1, [PeripheralToMemory]), //USART1_RX
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(Stream2<DMA2>:5, pac::USART6, [PeripheralToMemory]), //USART6_RX
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(Stream2<DMA2>:6, timer::CCR2<pac::TIM1>, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH2
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(Stream2<DMA2>:7, timer::CCR1<pac::TIM8>, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_CH1
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(Stream3<DMA2>:1, pac::ADC2, [PeripheralToMemory]), //ADC2
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(Stream3<DMA2>:3, pac::SPI1, [MemoryToPeripheral]), //SPI1_TX
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(Stream3<DMA2>:4, pac::SDIO, [MemoryToPeripheral | PeripheralToMemory]), //SDIO:Conflict:SDIO_RX,SDIO_TX
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(Stream3<DMA2>:6, timer::CCR1<pac::TIM1>, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH1
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(Stream3<DMA2>:7, timer::CCR2<pac::TIM8>, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_CH2
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(Stream4<DMA2>:0, pac::ADC1, [PeripheralToMemory]), //ADC1
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(Stream4<DMA2>:6, timer::CCR4<pac::TIM1>, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH4
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(Stream4<DMA2>:6, TIM1_TRIG, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_TRIG
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(Stream4<DMA2>:6, TIM1_COM, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_COM
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(Stream4<DMA2>:7, timer::CCR3<pac::TIM8>, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_CH3
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(Stream5<DMA2>:2, CRYP_OUT, [PeripheralToMemory]), //CRYP_OUT
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(Stream5<DMA2>:3, pac::SPI1, [MemoryToPeripheral]), //SPI1_TX
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(Stream5<DMA2>:4, pac::USART1, [PeripheralToMemory]), //USART1_RX
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(Stream5<DMA2>:6, TIM1_UP, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_UP
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(Stream6<DMA2>:0, timer::CCR1<pac::TIM1>, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH1
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(Stream6<DMA2>:0, timer::CCR2<pac::TIM1>, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH2
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(Stream6<DMA2>:0, timer::CCR3<pac::TIM1>, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH3
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(Stream6<DMA2>:2, CRYP_IN, [MemoryToPeripheral]), //CRYP_IN
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(Stream6<DMA2>:4, pac::SDIO, [MemoryToPeripheral | PeripheralToMemory]), //SDIO_RX,SDIO_TX
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(Stream6<DMA2>:5, pac::USART6, [MemoryToPeripheral]), //USART6_TX
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(Stream6<DMA2>:6, timer::CCR3<pac::TIM1>, [MemoryToPeripheral | PeripheralToMemory]), //TIM1_CH3
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(Stream7<DMA2>:1, pac::DCMI, [PeripheralToMemory]), //DCMI
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(Stream7<DMA2>:2, HASH_IN, [MemoryToPeripheral]), //HASH_IN
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(Stream7<DMA2>:4, pac::USART1, [MemoryToPeripheral]), //USART1_TX
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(Stream7<DMA2>:5, pac::USART6, [MemoryToPeripheral]), //USART6_TX
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(Stream7<DMA2>:7, timer::CCR4<pac::TIM8>, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_CH4
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(Stream7<DMA2>:7, TIM8_TRIG, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_TRIG
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(Stream7<DMA2>:7, TIM8_COM, [MemoryToPeripheral | PeripheralToMemory]), //TIM8_COM
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}

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