@@ -546,7 +546,7 @@ impl<SPI: Instance, const BIDI: bool, W> Spi<SPI, BIDI, W> {
546546 /// Convert the spi to another mode.
547547 fn into_mode < const BIDI2 : bool , W2 : FrameSize > ( self ) -> Spi < SPI , BIDI2 , W2 > {
548548 let mut spi = Spi :: _new ( self . inner . spi , self . pins ) ;
549- spi. enable ( false ) ;
549+ spi. disable ( ) ;
550550 spi. init ( )
551551 }
552552}
@@ -563,7 +563,7 @@ impl<SPI: Instance, const BIDI: bool, W> SpiSlave<SPI, BIDI, W> {
563563 /// Convert the spi to another mode.
564564 fn into_mode < const BIDI2 : bool , W2 : FrameSize > ( self ) -> SpiSlave < SPI , BIDI2 , W2 > {
565565 let mut spi = SpiSlave :: _new ( self . inner . spi , self . pins ) ;
566- spi. enable ( false ) ;
566+ spi. disable ( ) ;
567567 spi. init ( )
568568 }
569569}
@@ -642,11 +642,21 @@ impl<SPI: Instance> Inner<SPI> {
642642 Self { spi }
643643 }
644644
645- /// Enable/disable spi
646- pub fn enable ( & mut self , enable : bool ) {
645+ /// Enable SPI
646+ pub fn enable ( & mut self ) {
647647 self . spi . cr1 . modify ( |_, w| {
648648 // spe: enable the SPI bus
649- w. spe ( ) . bit ( enable)
649+ w. spe ( ) . set_bit ( )
650+ } ) ;
651+ }
652+
653+ /// Disable SPI
654+ pub fn disable ( & mut self ) {
655+ // Wait for !BSY
656+ while self . is_busy ( ) { }
657+ self . spi . cr1 . modify ( |_, w| {
658+ // spe: enable the SPI bus
659+ w. spe ( ) . clear_bit ( )
650660 } ) ;
651661 }
652662
@@ -805,7 +815,10 @@ impl<SPI: Instance> Inner<SPI> {
805815 // RM SPI::3.5. This is more than twice as fast as the
806816 // default Write<> implementation (which reads and drops each
807817 // received value)
808- fn spi_write < const BIDI : bool , W : FrameSize > ( & mut self , words : impl IntoIterator < Item = W > ) -> Result < ( ) , Error > {
818+ fn spi_write < const BIDI : bool , W : FrameSize > (
819+ & mut self ,
820+ words : impl IntoIterator < Item = W > ,
821+ ) -> Result < ( ) , Error > {
809822 if BIDI {
810823 self . bidi_output ( ) ;
811824 }
@@ -824,8 +837,6 @@ impl<SPI: Instance> Inner<SPI> {
824837 }
825838 // Wait for final TXE
826839 while !self . is_tx_empty ( ) { }
827- // Wait for final !BSY
828- while self . is_busy ( ) { }
829840 if !BIDI {
830841 // Clear OVR set due to dropped received values
831842 let _: W = self . read_data_reg ( ) ;
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