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Merge pull request #173 from Sh3Rm4n/doc-lint
Document every public item
2 parents c6b4406 + 8ec4356 commit 831f9cf

15 files changed

+626
-426
lines changed

Cargo.toml

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -32,15 +32,12 @@ nb = "0.1"
3232
paste = "1"
3333
rtcc = "0.2"
3434
stm32f3 = "0.12"
35+
doc-comment = "0.3.3"
3536

3637
[dependencies.embedded-hal-can]
3738
version = "0.1.0"
3839
optional = true
3940

40-
[dependencies.heapless]
41-
version = "0.5.5"
42-
optional = true
43-
4441
[dependencies.bare-metal]
4542
version = "0.2"
4643
features = ["const-fn"]
@@ -65,15 +62,15 @@ unproven = ["embedded-hal/unproven"]
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device-selected = []
6663
direct-call-deprecated = []
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rt = ["stm32f3/rt"]
68-
can = ["embedded-hal-can", "heapless"]
65+
can = ["embedded-hal-can"]
6966

7067
gpio-f302 = []
7168
gpio-f303 = []
7269
gpio-f303e = []
7370
gpio-f333 = []
7471
gpio-f373 = []
7572

76-
# Any Changes here should be mirrored in README.md, src/lib.rs, and
73+
# Any changes here should be mirrored in README.md, src/lib.rs, and
7774
# .github/workflows/ci.yml.
7875
stm32f301 = ["gpio-f302", "stm32f3/stm32f301", "device-selected"]
7976
stm32f318 = ["gpio-f302", "stm32f3/stm32f301", "device-selected"]
@@ -138,3 +135,7 @@ required-features = ["stm32f303"]
138135
[[example]]
139136
name = "i2c_scanner"
140137
required-features = ["stm32f303xc"]
138+
139+
[[example]]
140+
name = "gpio_erased"
141+
required-features = ["rt", "stm32f303xc"]

examples/can.rs

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,7 @@ fn main() -> ! {
4242
let can_tx = gpioa.pa12.into_af9(&mut gpioa.moder, &mut gpioa.afrh);
4343

4444
// Initialize the CAN peripheral
45-
let can = Can::can(dp.CAN, can_rx, can_tx, &mut rcc.apb1);
45+
let can = Can::new(dp.CAN, can_rx, can_tx, &mut rcc.apb1);
4646

4747
// Uncomment the following line to enable CAN interrupts
4848
// can.listen(Event::Fifo0Fmp);
@@ -66,7 +66,7 @@ fn main() -> ! {
6666
asm::delay(100_000);
6767
let data: [u8; 1] = [0];
6868

69-
let frame = CanFrame::data_frame(CanId::BaseId(ID), &data);
69+
let frame = CanFrame::new_data(CanId::BaseId(ID), &data);
7070

7171
block!(can_tx.transmit(&frame)).expect("Cannot send first CAN frame");
7272

@@ -81,7 +81,7 @@ fn main() -> ! {
8181
}
8282

8383
let data: [u8; 1] = [counter];
84-
let frame = CanFrame::data_frame(CanId::BaseId(ID), &data);
84+
let frame = CanFrame::new_data(CanId::BaseId(ID), &data);
8585

8686
block!(can_tx.transmit(&frame)).expect("Cannot send CAN frame");
8787
}

examples/gpio_erased.rs

Lines changed: 56 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,56 @@
1+
// TOOD Implement:
2+
// https://github.com/dfrankland/proton-c/commit/0289f1cfa15000d6b1b2a8175420c16ffdff7451
3+
#![no_main]
4+
#![no_std]
5+
6+
use panic_semihosting as _;
7+
8+
use cortex_m::asm;
9+
use cortex_m_rt::entry;
10+
use cortex_m_semihosting::hprintln;
11+
12+
use hal::gpio::{self, Floating, Input};
13+
use hal::pac;
14+
use hal::prelude::*;
15+
use stm32f3xx_hal as hal;
16+
17+
#[entry]
18+
fn main() -> ! {
19+
let dp = pac::Peripherals::take().unwrap();
20+
21+
let mut rcc = dp.RCC.constrain();
22+
let mut gpiob = dp.GPIOB.split(&mut rcc.ahb);
23+
let mut gpioc = dp.GPIOC.split(&mut rcc.ahb);
24+
let mut gpiod = dp.GPIOD.split(&mut rcc.ahb);
25+
26+
let mut pin_array: [gpio::PXx<Input<Floating>>; 4] = [
27+
gpiob
28+
.pb11
29+
.into_floating_input(&mut gpiob.moder, &mut gpiob.pupdr)
30+
.downgrade()
31+
.downgrade(),
32+
gpioc
33+
.pc4
34+
.into_floating_input(&mut gpioc.moder, &mut gpioc.pupdr)
35+
.downgrade()
36+
.downgrade(),
37+
gpiod
38+
.pd3
39+
.into_floating_input(&mut gpiod.moder, &mut gpiod.pupdr)
40+
.downgrade()
41+
.downgrade(),
42+
gpiod
43+
.pd2
44+
.into_floating_input(&mut gpiod.moder, &mut gpiod.pupdr)
45+
.downgrade()
46+
.downgrade(),
47+
];
48+
49+
hprintln!("Start scanning pin array").unwrap();
50+
loop {
51+
for pin in pin_array.iter_mut() {
52+
hprintln!("Value is {}", pin.is_high().unwrap()).unwrap();
53+
asm::delay(1_000);
54+
}
55+
}
56+
}

src/adc.rs

Lines changed: 21 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,14 @@
11
//! API for the ADC (Analog to Digital Converter)
22
//!
33
//! # Examples
4-
//! Check `adc.rs` in the examples folder.
4+
//!
5+
//! Check out [examles/adc.rs].
6+
//!
57
//! It can be built for the STM32F3Discovery running
68
//! `cargo build --example adc --features=stm32f303xc`
9+
//!
10+
//! [examples/adc.rs]: https://github.com/stm32-rs/stm32f3xx-hal/blob/v0.5.0/examples/adc.rs
11+
712
use crate::{
813
gpio::Analog,
914
rcc::{Clocks, AHB},
@@ -29,10 +34,11 @@ use crate::{
2934
pac::{ADC3, ADC3_4, ADC4},
3035
};
3136

32-
/// ADC configuration
37+
/// Analog Digital Converter Peripheral
3338
// TODO: Remove `pub` from the register block once all functionalities are implemented.
3439
// Leave it here until then as it allows easy access to the registers.
3540
pub struct Adc<ADC> {
41+
/// ADC Register
3642
pub rb: ADC,
3743
clocks: Clocks,
3844
ckmode: CkMode,
@@ -46,13 +52,21 @@ pub struct Adc<ADC> {
4652
/// E.g. For Sampletime T_19 the total conversion time (in ADC clock cycles) is
4753
/// 13 + 19 = 32 ADC Clock Cycles
4854
pub enum SampleTime {
55+
/// 1.5 ADC clock cycles
4956
T_1,
57+
/// 2.5 ADC clock cycles
5058
T_2,
59+
/// 4.5 ADC clock cycles
5160
T_4,
61+
/// 7.5 ADC clock cycles
5262
T_7,
63+
/// 19.5 ADC clock cycles
5364
T_19,
65+
/// 61.5 ADC clock cycles
5466
T_61,
67+
/// 181.5 ADC clock cycles
5568
T_181,
69+
/// 601.5 ADC clock cycles
5670
T_601,
5771
}
5872

@@ -83,16 +97,21 @@ impl SampleTime {
8397
/// ADC operation mode
8498
// TODO: Implement other modes (DMA, Differential,…)
8599
pub enum OperationMode {
100+
/// OneShot Mode
86101
OneShot,
87102
}
88103

89104
#[derive(Clone, Copy, PartialEq)]
90105
/// ADC CkMode
91106
// TODO: Add ASYNCHRONOUS mode
92107
pub enum CkMode {
108+
// /// Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock
93109
// ASYNCHRONOUS = 0,
110+
/// Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck
94111
SYNCDIV1 = 1,
112+
/// Use AHB clock rcc_hclk3 divided by 2
95113
SYNCDIV2 = 2,
114+
/// Use AHB clock rcc_hclk3 divided by 4
96115
SYNCDIV4 = 4,
97116
}
98117

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