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david-sawatzkedavid-sawatzke
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Move pin af definitions to a universal pin_mappings file
For SPI & UART
1 parent 77a6dad commit fde2dba

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4 files changed

+113
-269
lines changed

4 files changed

+113
-269
lines changed

‎src/lib.rs

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -35,6 +35,8 @@ pub mod gpio;
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#[cfg(feature = "device-selected")]
3636
pub mod i2c;
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#[cfg(feature = "device-selected")]
38+
pub mod pin_mappings;
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#[cfg(feature = "device-selected")]
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pub mod prelude;
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#[cfg(feature = "device-selected")]
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pub mod rcc;

‎src/pin_mappings.rs

Lines changed: 111 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,111 @@
1+
#[cfg(feature = "device-selected")]
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use crate::gpio::gpioa::*;
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#[cfg(feature = "device-selected")]
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use crate::gpio::gpiob::*;
5+
#[allow(unused)]
6+
#[cfg(feature = "device-selected")]
7+
use crate::gpio::gpioc::*;
8+
#[cfg(feature = "stm32f030xc")]
9+
use crate::gpio::gpiod::*;
10+
#[allow(unused)]
11+
use crate::gpio::{Alternate, AF0, AF1, AF2, AF4, AF5};
12+
use crate::serial::*;
13+
use crate::spi::*;
14+
#[cfg(feature = "device-selected")]
15+
use crate::stm32::*;
16+
17+
macro_rules! pins {
18+
($($PIN:ident => {
19+
$($AF:ty: $TRAIT:ty),+
20+
}),+) => {
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$(
22+
$(
23+
impl $TRAIT for $PIN<Alternate<$AF>> {}
24+
)+
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)+
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}
27+
}
28+
29+
#[cfg(feature = "device-selected")]
30+
pins! {
31+
PA5 => {AF0: SckPin<SPI1>},
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PA6 => {AF0: MisoPin<SPI1>},
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PA7 => {AF0: MosiPin<SPI1>},
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PA9 => {AF1: TxPin<USART1>},
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PA10 => {AF1: RxPin<USART1>},
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PB3 => {AF0: SckPin<SPI1>},
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PB4 => {AF0: MisoPin<SPI1>},
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PB5 => {AF0: MosiPin<SPI1>},
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PB6 => {AF0: TxPin<USART1>},
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PB7 => {AF0: RxPin<USART1>}
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}
42+
43+
#[cfg(feature = "stm32f030x6")]
44+
pins! {
45+
PA2 => {AF1: TxPin<USART1>},
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PA3 => {AF1: RxPin<USART1>},
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PA14 => {AF1: TxPin<USART1>},
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PA15 => {AF1: RxPin<USART1>},
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PB13 => {AF0: SckPin<SPI1>},
50+
PB14 => {AF0: MisoPin<SPI1>},
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PB15 => {AF0: MosiPin<SPI1>}
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}
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54+
#[cfg(any(
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feature = "stm32f030x8",
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feature = "stm32f030xc",
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feature = "stm32f042",
58+
feature = "stm32f070",
59+
))]
60+
pins! {
61+
PA2 => {AF1: TxPin<USART2>},
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PA3 => {AF1: RxPin<USART2>},
63+
PA14 => {AF1: TxPin<USART2>},
64+
PA15 => {AF1: RxPin<USART2>}
65+
}
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67+
#[cfg(any(feature = "stm32f030xc", feature = "stm32f070xb"))]
68+
pins! {
69+
PA0 => {AF4: TxPin<USART4>},
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PA1 => {AF4: RxPin<USART4>},
71+
PB10 => {
72+
AF4: TxPin<USART3>,
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AF5: SckPin<SPI2>
74+
},
75+
PB11 => {AF4: RxPin<USART3>},
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PC2 => {AF1: MisoPin<SPI2>},
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PC3 => {AF1: MosiPin<SPI2>},
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PC4 => {AF1: TxPin<USART3>},
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PC5 => {AF1: RxPin<USART3>},
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PC10 => {
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AF0: TxPin<USART4>,
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AF1: TxPin<USART3>
83+
},
84+
PC11 => {
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AF0: RxPin<USART4>,
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AF1: RxPin<USART3>
87+
}
88+
}
89+
90+
#[cfg(feature = "stm32f030xc")]
91+
pins! {
92+
PA4 => {AF5: TxPin<USART6>},
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PA5 => {AF5: RxPin<USART6>},
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PB3 => {AF4: TxPin<USART5>},
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PB4 => {AF4: RxPin<USART5>},
96+
PC0 => {AF2: TxPin<USART6>},
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PC1 => {AF2: RxPin<USART6>},
98+
PC12 => {AF2: RxPin<USART5>},
99+
PD2 => {AF2: TxPin<USART5>}
100+
}
101+
102+
#[cfg(any(
103+
feature = "stm32f030x8",
104+
feature = "stm32f030xc",
105+
feature = "stm32f070xb"
106+
))]
107+
pins! {
108+
PB13 => {AF0: SckPin<SPI2>},
109+
PB14 => {AF0: MisoPin<SPI2>},
110+
PB15 => {AF0: MosiPin<SPI2>}
111+
}

‎src/serial.rs

Lines changed: 0 additions & 159 deletions
Original file line numberDiff line numberDiff line change
@@ -98,165 +98,6 @@ pub enum Event {
9898
pub trait TxPin<USART> {}
9999
pub trait RxPin<USART> {}
100100

101-
macro_rules! usart_pins {
102-
($($USART:ident => {
103-
tx => [$($tx:ty),+ $(,)*],
104-
rx => [$($rx:ty),+ $(,)*],
105-
})+) => {
106-
$(
107-
$(
108-
impl TxPin<crate::stm32::$USART> for $tx {}
109-
)+
110-
$(
111-
impl RxPin<crate::stm32::$USART> for $rx {}
112-
)+
113-
)+
114-
}
115-
}
116-
117-
#[cfg(any(
118-
feature = "stm32f030",
119-
feature = "stm32f031",
120-
feature = "stm32f038",
121-
feature = "stm32f042",
122-
feature = "stm32f048",
123-
feature = "stm32f051",
124-
feature = "stm32f058",
125-
feature = "stm32f070",
126-
feature = "stm32f071",
127-
feature = "stm32f072",
128-
feature = "stm32f078",
129-
feature = "stm32f091",
130-
feature = "stm32f098",
131-
))]
132-
usart_pins! {
133-
USART1 => {
134-
tx => [gpioa::PA9<Alternate<AF1>>, gpiob::PB6<Alternate<AF0>>],
135-
rx => [gpioa::PA10<Alternate<AF1>>, gpiob::PB7<Alternate<AF0>>],
136-
}
137-
}
138-
#[cfg(any(
139-
feature = "stm32f030x4",
140-
feature = "stm32f030x6",
141-
feature = "stm32f031",
142-
feature = "stm32f038",
143-
))]
144-
usart_pins! {
145-
USART1 => {
146-
tx => [gpioa::PA2<Alternate<AF1>>, gpioa::PA14<Alternate<AF1>>],
147-
rx => [gpioa::PA3<Alternate<AF1>>, gpioa::PA15<Alternate<AF1>>],
148-
}
149-
}
150-
151-
#[cfg(any(
152-
feature = "stm32f030x8",
153-
feature = "stm32f030xc",
154-
feature = "stm32f042",
155-
feature = "stm32f048",
156-
feature = "stm32f051",
157-
feature = "stm32f058",
158-
feature = "stm32f070",
159-
feature = "stm32f071",
160-
feature = "stm32f072",
161-
feature = "stm32f078",
162-
feature = "stm32f091",
163-
feature = "stm32f098",
164-
))]
165-
usart_pins! {
166-
USART2 => {
167-
tx => [gpioa::PA2<Alternate<AF1>>, gpioa::PA14<Alternate<AF1>>],
168-
rx => [gpioa::PA3<Alternate<AF1>>, gpioa::PA15<Alternate<AF1>>],
169-
}
170-
}
171-
#[cfg(any(
172-
feature = "stm32f071",
173-
feature = "stm32f072",
174-
feature = "stm32f078",
175-
feature = "stm32f091",
176-
feature = "stm32f098",
177-
))]
178-
usart_pins! {
179-
USART2 => {
180-
tx => [gpiod::PD5<Alternate<AF0>>],
181-
rx => [gpiod::PD6<Alternate<AF0>>],
182-
}
183-
}
184-
185-
#[cfg(any(
186-
feature = "stm32f030xc",
187-
feature = "stm32f070xb",
188-
feature = "stm32f071",
189-
feature = "stm32f072",
190-
feature = "stm32f078",
191-
feature = "stm32f091",
192-
feature = "stm32f098",
193-
))]
194-
usart_pins! {
195-
USART3 => {
196-
// According to the datasheet PB10 is both tx and rx, but in stm32cubemx it's only tx
197-
tx => [gpiob::PB10<Alternate<AF4>>, gpioc::PC4<Alternate<AF1>>, gpioc::PC10<Alternate<AF1>>],
198-
rx => [gpiob::PB11<Alternate<AF4>>, gpioc::PC5<Alternate<AF1>>, gpioc::PC11<Alternate<AF1>>],
199-
}
200-
USART4 => {
201-
tx => [gpioa::PA0<Alternate<AF4>>, gpioc::PC10<Alternate<AF0>>],
202-
rx => [gpioa::PA1<Alternate<AF4>>, gpioc::PC11<Alternate<AF0>>],
203-
}
204-
}
205-
#[cfg(any(
206-
feature = "stm32f071",
207-
feature = "stm32f072",
208-
feature = "stm32f078",
209-
feature = "stm32f091",
210-
feature = "stm32f098",
211-
))]
212-
usart_pins! {
213-
USART3 => {
214-
tx => [gpiod::PD8<Alternate<AF0>>],
215-
rx => [gpiod::PD9<Alternate<AF0>>],
216-
}
217-
}
218-
// TODO: The ST SVD files are missing the entire PE enable register.
219-
// Re-enable as soon as this gets fixed.
220-
// #[cfg(any(feature = "stm32f091", feature = "stm32f098"))]
221-
// usart_pins! {
222-
// USART4 => {
223-
// tx => [gpioe::PE8<Alternate<AF1>>],
224-
// rx => [gpioe::PE9<Alternate<AF1>>],
225-
// }
226-
// }
227-
228-
#[cfg(any(feature = "stm32f030xc", feature = "stm32f091", feature = "stm32f098"))]
229-
usart_pins! {
230-
USART5 => {
231-
tx => [gpioc::PC12<Alternate<AF2>>],
232-
rx => [gpiod::PD2<Alternate<AF2>>],
233-
}
234-
USART6 => {
235-
tx => [gpioa::PA4<Alternate<AF5>>, gpioc::PC0<Alternate<AF2>>],
236-
rx => [gpioa::PA5<Alternate<AF5>>, gpioc::PC1<Alternate<AF2>>],
237-
}
238-
}
239-
#[cfg(any(feature = "stm32f030xc", feature = "stm32f091"))]
240-
usart_pins! {
241-
USART5 => {
242-
tx => [gpiob::PB3<Alternate<AF4>>],
243-
rx => [gpiob::PB4<Alternate<AF4>>],
244-
}
245-
}
246-
// TODO: The ST SVD files are missing the entire PE enable register.
247-
// Re-enable as soon as this gets fixed.
248-
#[cfg(any(feature = "stm32f091", feature = "stm32f098"))]
249-
usart_pins! {
250-
// USART5 => {
251-
// tx => [gpioe::PE10<Alternate<AF1>>],
252-
// rx => [gpioe::PE11<Alternate<AF1>>],
253-
// }
254-
USART6 => {
255-
tx => [gpiof::PF9<Alternate<AF1>>],
256-
rx => [gpiof::PF10<Alternate<AF1>>],
257-
}
258-
}
259-
260101
/// Serial abstraction
261102
pub struct Serial<USART, TXPIN, RXPIN> {
262103
usart: USART,

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