Cortex-A55: Add some missing load and store operations

[mkannwischer]

In #376 I added a new test for testing the that the selftest correctly detects which registers are used as addresses.
However, could not add all memory operations to the test as they are not all supported by the Cortex-A55.

// TODO: Instructions not supported on Cortex-A55
// ldp q24, q25, [x24, #32]
// ld4 {v26.4s, v27.4s, v28.4s, v29.4s}, [x25], #64
// st4 {v30.4s, v31.4s, v0.4s, v1.4s}, [x26], #64
// ld3 {v2.4s, v3.4s, v4.4s}, [x27], #48
// st3 {v5.4s, v6.4s, v7.4s}, [x28], #48
// ld2 {v8.4s, v9.4s}, [x29], #32
// st2 {v10.4s, v11.4s}, [x30], #32

We should:

• Add those instructions also to instruction.s
• Add them to the Cortex-A55 microarchitecture model
• Uncomment the instructions in the ‎tests/naive/aarch64/aarch64_selftest_addr.s