Add missing instructions to Neoverse N1 model and test completeness in CI

[mkannwischer]

#265 requested a missing instruction from the Neoverse N1 microarchitectural model. There are more instructions missing.
It would be good if our uarch models would be aligned. I suggest to implement this in 3 steps:

• Add an instructions.s test containing all AArch64/Neon instructions along the lines of what we have for MVE now (functional_only=True).
• Enforce with that tests that each instruction is covered by the A55 uarch model (this should be easy by setting functional_only=False)
• Extend the test to Neoverse N1 and add all missing instructions

Does this make sense @hanno-becker?

According to Amazon Q the following instructions are still missing:

Missing Instruction Classes in Neoverse N1:

Load/Store Instructions:

• Ld2, Ld3, Ld4 - Multi-element load instructions
• St2 - Multi-element store instruction (St3, St4 are already present)
• Q_Ld2_Lane_Post_Inc - Lane-specific load with post-increment
• q_ldr1_stack, q_ldr1_post_inc - Q-register stack loads
• Various stack-specific loads/stores: b_ldr_stack_with_inc, d_ldr_stack_with_inc, d_stp_stack_with_inc,
d_str_stack_with_inc, x_ldr_stack_imm, x_str_sp_imm, w_stp_with_imm_sp

Vector Instructions:

• vbic - Vector bitwise clear
• veor - Vector exclusive OR
• vqdmulh_lane, vqrdmulh, vqrdmulh_lane - Vector saturating multiply high
• vsri - Vector shift right and insert
• vushr - Vector unsigned shift right
• vuzp1, vuzp2 - Vector unzip
• vzip1, vzip2 - Vector zip
• trn1, trn2 - Vector transpose
• VShiftImmediateRounding - Rounding shift operations
• Vins - Vector insert

Scalar Instructions:

• Basic arithmetic: add, add2, add_imm, add_lsl, add_lsr, add_sp_imm, sub
• Logical: and_imm, eor, eor_ror, bic, bic_ror
• Bit manipulation: bfi, lsr, ror
• Moves: mov, mov_imm, movk_imm, movw_imm, mov_b00, mov_d01
• Comparisons: cmge, cmn, cmp_imm, cmp_xzr2, tst_wform
• Multiply: mul_wform, umaddl_wform, umov_d
• Conditional: fcsel_dform
• Carry operations: adcs_to_zero, adcs_zero2, adcs_zero_r_to_zero, sbcs_zero_to_zero
• Memory: ldr_const, ldr_sxtw_wform
• Utility: nop

Move Instructions:

• Mov_xtov_d - Move from general purpose to vector register
• umov_d - Move from vector to general purpose register