[aarch64] Add register indexed load

* Add scalar register indexed load `ldr <Xa>, [<Xb>, <Xc>]`

Author: dop-amin

slothy/targets/aarch64/aarch64_neon.py

@@ -2005,6 +2005,24 @@ def write(self):
         return super().write()
 
 
+class x_ldr_regidx(Ldr_X):
+    pattern = "ldr <Xa>, [<Xb>, <Xc>]"
+    inputs = ["Xb", "Xc"]
+    outputs = ["Xa"]
+
+    @classmethod
+    def make(cls, src):
+        obj = AArch64Instruction.build(cls, src)
+        obj.increment = None
+        obj.pre_index = None
+        obj.addr = obj.args_in[0]
+        return obj
+
+    def write(self):
+        assert self.pre_index is None
+        return super().write()
+
+
 class x_ldr_with_postinc(Ldr_X):
     pattern = "ldr <Xa>, [<Xc>], <imm>"
     in_outs = ["Xc"]

tests/naive/aarch64/instructions.s

@@ -49,6 +49,7 @@ cmge v4.8h, v30.8h, v16.8h
 cmhi v4.8h, v30.8h, v16.8h
 mov x12, #0
 ldr q24, [x3, x12, lsl #4]
+ldr x6, [x3, x12]
 clz v0.16b, v0.16b
 cnt v0.16b, v0.16b
 tbl v16.16b, {v16.16b}, v24.16b