Activity
🐛 GUI error checking for FPGA memory link
🐛 GUI error checking for FPGA memory link
fixed bug on input/output credit logic
fixed bug on input/output credit logic
caches: fix bug for asic with larger cache lines
caches: fix bug for asic with larger cache lines
✨ make FPGA memory link width configurable
✨ make FPGA memory link width configurable
Updating blitzcoin for latest ESP changes
Updating blitzcoin for latest ESP changes
✨ support 2 memory tiles on VCU118 board
✨ support 2 memory tiles on VCU118 board
Force push
✨ support 2 memory tiles on VCU118 board
✨ support 2 memory tiles on VCU118 board
Force push
✨ support 2 memory tiles on VCU118 board
✨ support 2 memory tiles on VCU118 board
Force push
accgen: make templates comply with new interface, fix a few small issues
accgen: make templates comply with new interface, fix a few small issues
✨ support 2 memory tiles on VCU118 board
✨ support 2 memory tiles on VCU118 board