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Merge pull request #33 from siliconcompiler/surelog-fix
Revert "Hack to fix Surelog elaboration"
2 parents 9ca2c3e + 3b2464b commit fc99854

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2 files changed

+13
-19
lines changed

2 files changed

+13
-19
lines changed

lambdalib/__init__.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
import os
22

3-
__version__ = "0.1.1"
3+
__version__ = "0.1.2"
44

55

66
def register_data_source(chip):

lambdalib/padring/rtl/la_ioside.v

Lines changed: 12 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -9,12 +9,6 @@
99
*
1010
****************************************************************************/
1111

12-
// The following is a hack to fix Surelog elaboration. It doesn't seem to
13-
// properly handle generate if-statements with multibit compare, so we use a
14-
// macro to break it down into multiple single-bit comparisons.
15-
// TODO: remove once Surelog is fixed.
16-
`define CELLMAP_COMPARE(CELL) CELLMAP[i*24] == CELL[0] && CELLMAP[i*24+1] == CELL[1] && CELLMAP[i*24+2] == CELL[2] && CELLMAP[i*24+3] == CELL[3]
17-
1812
module la_ioside
1913
#(// per side parameters
2014
parameter SIDE = "NO", // "NO", "SO", "EA", "WE"
@@ -59,7 +53,7 @@ module la_ioside
5953
// BIDIR
6054
// initial
6155
// $display("cell=%d, pin=%d",i, CELLMAP[(i*24+8)+:8]);
62-
if (`CELLMAP_COMPARE(LA_BIDIR))
56+
if (CELLMAP[i*24+:4]==LA_BIDIR[3:0])
6357
begin: ila_iobidir
6458
la_iobidir #(.SIDE(SIDE),
6559
.TYPE(CELLMAP[(i*24+4)+:4]),
@@ -82,7 +76,7 @@ module la_ioside
8276
.ioring(ioring[CELLMAP[(i*24+16)+:8]*RINGW+:RINGW]));
8377
end
8478
// INPUT
85-
else if (`CELLMAP_COMPARE(LA_INPUT))
79+
else if (CELLMAP[i*24+:4]==LA_INPUT[3:0])
8680
begin: ila_ioinput
8781
la_ioinput #(.SIDE(SIDE),
8882
.TYPE(CELLMAP[(i*24+4)+:4]),
@@ -103,7 +97,7 @@ module la_ioside
10397
.ioring(ioring[CELLMAP[(i*24+16)+:8]*RINGW+:RINGW]));
10498
end
10599
// ANALOG
106-
else if (`CELLMAP_COMPARE(LA_ANALOG))
100+
else if (CELLMAP[i*24+:4]==LA_ANALOG[3:0])
107101
begin: ila_ioanalog
108102
la_ioanalog #(.SIDE(SIDE),
109103
.TYPE(CELLMAP[(i*24+4)+:4]),
@@ -121,7 +115,7 @@ module la_ioside
121115
.ioring(ioring[CELLMAP[(i*24+16)+:8]*RINGW+:RINGW]));
122116
end
123117
// XTAL
124-
else if (`CELLMAP_COMPARE(LA_XTAL))
118+
else if (CELLMAP[i*24+:4]==LA_XTAL[3:0])
125119
begin: ila_ioxtal
126120
la_ioxtal #(.SIDE(SIDE),
127121
.TYPE(CELLMAP[(i*24+4)+:4]),
@@ -141,7 +135,7 @@ module la_ioside
141135
.ioring(ioring[CELLMAP[(i*24+16)+:8]*RINGW+:RINGW]));
142136
end
143137
// POC
144-
else if (`CELLMAP_COMPARE(LA_POC))
138+
else if (CELLMAP[i*24+:4]==LA_POC[3:0])
145139
begin: ila_iopoc
146140
la_iopoc #(.SIDE(SIDE),
147141
.TYPE(CELLMAP[(i*24+4)+:4]),
@@ -155,14 +149,14 @@ module la_ioside
155149
.ioring(ioring[CELLMAP[(i*24+16)+:8]*RINGW+:RINGW]));
156150
end
157151
// CUT
158-
else if (`CELLMAP_COMPARE(LA_CUT))
152+
else if (CELLMAP[i*24+:4]==LA_CUT[3:0])
159153
begin: ila_iocut
160154
la_iocut #(.SIDE(SIDE),
161155
.TYPE(CELLMAP[(i*24+4)+:4]),
162156
.RINGW(RINGW))
163157
i0(.vss (vss));
164158
end
165-
else if (`CELLMAP_COMPARE(LA_VDDIO))
159+
else if (CELLMAP[i*24+:4]==LA_VDDIO[3:0])
166160
begin: ila_iovddio
167161
la_iovddio #(.SIDE(SIDE),
168162
.TYPE(CELLMAP[((i*24+8)+4)+:4]),
@@ -176,7 +170,7 @@ module la_ioside
176170
.ioring(ioring[CELLMAP[(i*24+16)+:8]*RINGW+:RINGW]));
177171
end
178172
// VSSIO
179-
else if (`CELLMAP_COMPARE(LA_VSSIO))
173+
else if (CELLMAP[i*24+:4]==LA_VSSIO[3:0])
180174
begin: ila_iovssio
181175
la_iovssio #(.SIDE(SIDE),
182176
.TYPE(CELLMAP[(i*24+4)+:4]),
@@ -190,7 +184,7 @@ module la_ioside
190184
.ioring(ioring[CELLMAP[(i*24+16)+:8]*RINGW+:RINGW]));
191185
end
192186
// VDD
193-
else if (`CELLMAP_COMPARE(LA_VDD))
187+
else if (CELLMAP[i*24+:4]==LA_VDD[3:0])
194188
begin: ila_iovdd
195189
la_iovdd #(.SIDE(SIDE),
196190
.TYPE(CELLMAP[(i*24+4)+:4]),
@@ -204,7 +198,7 @@ module la_ioside
204198
.ioring(ioring[CELLMAP[(i*24+16)+:8]*RINGW+:RINGW]));
205199
end
206200
// VSS
207-
else if (`CELLMAP_COMPARE(LA_VSS))
201+
else if (CELLMAP[i*24+:4]==LA_VSS[3:0])
208202
begin: ila_iovss
209203
la_iovss #(.SIDE(SIDE),
210204
.TYPE(CELLMAP[(i*24+4)+:4]),
@@ -218,7 +212,7 @@ module la_ioside
218212
.ioring(ioring[CELLMAP[(i*24+16)+:8]*RINGW+:RINGW]));
219213
end
220214
// VDDA
221-
else if (`CELLMAP_COMPARE(LA_VDDA))
215+
else if (CELLMAP[i*24+:4]==LA_VDDA[3:0])
222216
begin: ila_iovdda
223217
la_iovdda #(.SIDE(SIDE),
224218
.TYPE(CELLMAP[(i*24+4)+:4]),
@@ -232,7 +226,7 @@ module la_ioside
232226
.ioring(ioring[CELLMAP[(i*24+16)+:8]*RINGW+:RINGW]));
233227
end
234228
// VSSA
235-
else if (`CELLMAP_COMPARE(LA_VSSA))
229+
else if (CELLMAP[i*24+:4]==LA_VSSA[3:0])
236230
begin: ila_iovssa
237231
la_iovssa #(.SIDE(SIDE),
238232
.TYPE(CELLMAP[(i*24+4)+:4]),

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