From f0f16514ab691168f02543a09a9ef68c5daaeb2d Mon Sep 17 00:00:00 2001 From: Liu-Cheng Date: Fri, 14 Apr 2017 22:04:21 +0800 Subject: [PATCH] initial version --- DDR3.stats | 0 LICENSE | 20 + Makefile | 59 + README.md | 67 + configs/ALDRAM-config.cfg | 29 + configs/DDR3-config.cfg | 29 + configs/DDR4-config.cfg | 29 + configs/DSARP-config.cfg | 30 + configs/GDDR5-config.cfg | 29 + configs/HBM-config.cfg | 29 + configs/LPDDR3-config.cfg | 29 + configs/LPDDR4-config.cfg | 29 + configs/SALP-config.cfg | 30 + configs/TLDRAM-config.cfg | 30 + configs/WideIO-config.cfg | 29 + configs/WideIO2-config.cfg | 29 + dram.trace | 7 + src/ALDRAM.cpp | 361 + src/ALDRAM.h | 247 + src/Cache.cpp | 418 + src/Cache.h | 239 + src/Config.cpp | 64 + src/Config.h | 118 + src/Controller.cpp | 167 + src/Controller.h | 538 + src/DDR3.cpp | 356 + src/DDR3.h | 218 + src/DDR4.cpp | 402 + src/DDR4.h | 211 + src/DRAM.h | 451 + src/DSARP.cpp | 525 + src/DSARP.h | 271 + src/GDDR5.cpp | 355 + src/GDDR5.h | 211 + src/Gem5Wrapper.cpp | 55 + src/Gem5Wrapper.h | 31 + src/HBM.cpp | 359 + src/HBM.h | 199 + src/LPDDR3.cpp | 377 + src/LPDDR3.h | 208 + src/LPDDR4.cpp | 378 + src/LPDDR4.h | 222 + src/Main.cpp | 24 + src/MemWrapper.cpp | 493 + src/MemWrapper.h | 132 + src/Memory.h | 432 + src/MemoryFactory.cpp | 80 + src/MemoryFactory.h | 82 + src/Processor.cpp | 420 + src/Processor.h | 141 + src/Refresh.cpp | 255 + src/Refresh.h | 138 + src/Request.h | 81 + src/SALP.cpp | 646 + src/SALP.h | 229 + src/Scheduler.h | 279 + src/SpeedyController.h | 304 + src/StatType.cpp | 147 + src/StatType.h | 660 + src/Statistics.h | 246 + src/TLDRAM.cpp | 566 + src/TLDRAM.h | 259 + src/WideIO.cpp | 325 + src/WideIO.h | 201 + src/WideIO2.cpp | 338 + src/WideIO2.h | 197 + src/common.cpp | 375 + src/common.h | 127 + src/cscope.files | 53 + src/cscope.out | 105565 ++++++++++++++++++++++++++++++++++ src/pe.cpp | 315 + src/pe.h | 93 + src/tags | 2354 + src/temp.txt | 113 + 74 files changed, 123155 insertions(+) create mode 100644 DDR3.stats create mode 100644 LICENSE create mode 100644 Makefile create mode 100644 README.md create mode 100644 configs/ALDRAM-config.cfg create mode 100644 configs/DDR3-config.cfg create mode 100644 configs/DDR4-config.cfg create mode 100644 configs/DSARP-config.cfg create mode 100644 configs/GDDR5-config.cfg create mode 100644 configs/HBM-config.cfg create mode 100644 configs/LPDDR3-config.cfg create mode 100644 configs/LPDDR4-config.cfg create mode 100644 configs/SALP-config.cfg create mode 100644 configs/TLDRAM-config.cfg create mode 100644 configs/WideIO-config.cfg create mode 100644 configs/WideIO2-config.cfg create mode 100644 dram.trace create mode 100644 src/ALDRAM.cpp create mode 100644 src/ALDRAM.h create mode 100644 src/Cache.cpp create mode 100644 src/Cache.h create mode 100644 src/Config.cpp create mode 100644 src/Config.h create mode 100644 src/Controller.cpp create mode 100644 src/Controller.h create mode 100644 src/DDR3.cpp create mode 100644 src/DDR3.h create mode 100644 src/DDR4.cpp create mode 100644 src/DDR4.h create mode 100644 src/DRAM.h create mode 100644 src/DSARP.cpp create mode 100644 src/DSARP.h create mode 100644 src/GDDR5.cpp create mode 100644 src/GDDR5.h create mode 100644 src/Gem5Wrapper.cpp create mode 100644 src/Gem5Wrapper.h create mode 100644 src/HBM.cpp create mode 100644 src/HBM.h create mode 100644 src/LPDDR3.cpp create mode 100644 src/LPDDR3.h create mode 100644 src/LPDDR4.cpp create mode 100644 src/LPDDR4.h create mode 100644 src/Main.cpp create mode 100644 src/MemWrapper.cpp create mode 100644 src/MemWrapper.h create mode 100644 src/Memory.h create mode 100644 src/MemoryFactory.cpp create mode 100644 src/MemoryFactory.h create mode 100644 src/Processor.cpp create mode 100644 src/Processor.h create mode 100644 src/Refresh.cpp create mode 100644 src/Refresh.h create mode 100644 src/Request.h create mode 100644 src/SALP.cpp create mode 100644 src/SALP.h create mode 100644 src/Scheduler.h create mode 100644 src/SpeedyController.h create mode 100644 src/StatType.cpp create mode 100644 src/StatType.h create mode 100644 src/Statistics.h create mode 100644 src/TLDRAM.cpp create mode 100644 src/TLDRAM.h create mode 100644 src/WideIO.cpp create mode 100644 src/WideIO.h create mode 100644 src/WideIO2.cpp create mode 100644 src/WideIO2.h create mode 100644 src/common.cpp create mode 100644 src/common.h create mode 100644 src/cscope.files create mode 100644 src/cscope.out create mode 100644 src/pe.cpp create mode 100644 src/pe.h create mode 100644 src/tags create mode 100644 src/temp.txt diff --git a/DDR3.stats b/DDR3.stats new file mode 100644 index 0000000..e69de29 diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000..fb238d5 --- /dev/null +++ b/LICENSE @@ -0,0 +1,20 @@ +Copyright (c) 2015, SAFARI Research Group at Carnegie Mellon University + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice shall be included +in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..ef2c05b --- /dev/null +++ b/Makefile @@ -0,0 +1,59 @@ +SYSTEMC_HOME = /usr/local/systemc-2.3.1 +SYSTEMC_INC_DIR = $(SYSTEMC_HOME)/include +SYSTEMC_LIB_DIR = $(SYSTEMC_HOME)/lib/x86_64-linux-gnu + +SRCDIR := src +OBJDIR := obj +MAIN := $(SRCDIR)/Main.cpp +SRCS := $(filter-out $(MAIN) $(SRCDIR)/Gem5Wrapper.cpp, $(wildcard $(SRCDIR)/*.cpp)) +OBJS := $(patsubst $(SRCDIR)/%.cpp, $(OBJDIR)/%.o, $(SRCS)) + + +# Ramulator currently supports g++ 5.1+ or clang++ 3.4+. It will NOT work with +# g++ 4.x due to an internal compiler error when processing lambda functions. +#CXX := clang++ +CXX := g++-5 +CFLAGS = -std=c++11 -g -Wall -pedantic -Wno-long-long \ + -DSC_INCLUDE_DYNAMIC_PROCESSES -fpermissive \ + -I$(SYSTEMC_INC_DIR) + +LDFLAGS =-L$(SYSTEMC_LIB_DIR) -lsystemc -lm + +#CXXFLAGS := -O3 -std=c++11 -g -Wall +#CXXFLAGS := --std=c++11 -g -Wall +.PHONY: all clean depend + +all: depend ramulator + +clean: + rm -f ramulator + rm -rf $(OBJDIR) + +depend: $(OBJDIR)/.depend + +exe: + ./ramulator configs/DDR3-config.cfg --mode=acc dram.trace + +$(OBJDIR)/.depend: $(SRCS) + @mkdir -p $(OBJDIR) + @rm -f $(OBJDIR)/.depend + @$(foreach SRC, $(SRCS), $(CXX) $(CFLAGS) -DRAMULATOR -MM -MT $(patsubst $(SRCDIR)/%.cpp, $(OBJDIR)/%.o, $(SRC)) $(SRC) >> $(OBJDIR)/.depend ;) + +ifneq ($(MAKECMDGOALS),clean) +-include $(OBJDIR)/.depend +endif + + +ramulator: $(MAIN) $(OBJS) $(SRCDIR)/*.h | depend + $(CXX) $(CFLAGS) -DRAMULATOR -o $@ $(MAIN) $(OBJS) $(LDFLAGS) + +libramulator.a: $(OBJS) $(OBJDIR)/Gem5Wrapper.o + libtool -static -o $@ $(OBJS) $(OBJDIR)/Gem5Wrapper.o + +$(OBJS): | $(OBJDIR) + +$(OBJDIR): + @mkdir -p $@ + +$(OBJDIR)/%.o: $(SRCDIR)/%.cpp + $(CXX) $(CFLAGS) -DRAMULATOR -c -o $@ $< diff --git a/README.md b/README.md new file mode 100644 index 0000000..fcf92cf --- /dev/null +++ b/README.md @@ -0,0 +1,67 @@ +# An example of using Ramulator as memory model in a cycle-accurate SystemC Design +SystemC is convenient for developing cycle-accurate hardware accelerators. However, many +hardware accelerators require delicate memory access for the sake of +performance while there are few open source cycle-accurate DDR models immediately +available for SystemC. Myoungsoo developed a SystemC interface on top of DRAMSim2 +which has limited DDR models supported. Ramulator is a fast and cycle-accurate +DRAM simulator \[1\] that supports a wide array of commercial, as well as +academic, DRAM standards: + +- DDR3 (2007), DDR4 (2012) +- LPDDR3 (2012), LPDDR4 (2014) +- GDDR5 (2009) +- WIO (2011), WIO2 (2014) +- HBM (2013) +- SALP \[2\] +- TL-DRAM \[3\] +- RowClone \[4\] +- DSARP \[5\] + +[\[1\] Kim et al. *Ramulator: A Fast and Extensible DRAM Simulator.* IEEE CAL +2015.](https://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf) +[\[2\] Kim et al. *A Case for Exploiting Subarray-Level Parallelism (SALP) in +DRAM.* ISCA 2012.](https://users.ece.cmu.edu/~omutlu/pub/salp-dram_isca12.pdf) +[\[3\] Lee et al. *Tiered-Latency DRAM: A Low Latency and Low Cost DRAM +Architecture.* HPCA 2013.](https://users.ece.cmu.edu/~omutlu/pub/tldram_hpca13.pdf) +[\[4\] Seshadri et al. *RowClone: Fast and Energy-Efficient In-DRAM Bulk Data +Copy and Initialization.* MICRO +2013.](https://users.ece.cmu.edu/~omutlu/pub/rowclone_micro13.pdf) +[\[5\] Chang et al. *Improving DRAM Performance by Parallelizing Refreshes with +Accesses.* HPCA 2014.](https://users.ece.cmu.edu/~omutlu/pub/dram-access-refresh-parallelization_hpca14.pdf) +[\[6\] Myoungsoo Jung. *SCIC: A System C Interface Converter for DRAMSim.* 2011.] (https://github.com/LBNL-CODEX/DRAMSim_SystemC) + +Thus we use it for the cycle-accurate memory model in SystemC design. +In order to integrate ramulator for SystemC based hardware accelerator design, +we mainly solved the following problems in this project. + +1) Both Ramulator and SystemC have its own timing management, we basically pack the ramulator +as a SystemC thread and have it synchronized to the SystemC design. + +2) Ramulator provides only latency information but no memory content management +which is needed in many accelerator design. In this project, we keep the memory as +a dynamic vector and maintain the memory content based on sequential memory consistency. + +3) Ramulator provides only basic memory request i.e. each memory request operates on +a determined aligned length of data which is 64-byte in most cases. This is +not convenient for hardware accelerator design which has diverse burst transmission. +In this work, we developed a memory wrapper that provides arbitrary burst memory access. + +4) Finally, we developed a vector addition accelerator as an example. The users +may work on top of it for your own design. + +Also note that we also change part of the Ramulator source code (mostly the Request.h). + +## Getting Started +Ramulator requires a C++11 compiler (e.g., `clang++`, `g++-5`). +You may refer to [Ramulator git repo](https://github.com/CMU-SAFARI/ramulator) for more information about the details. In this project, we use [SystemC-2.3.1](http://accellera.org/downloads/standards/systemc) as the library. You need to download and compile it first. Then +you may change the SystemC library path accordingly in the Makefile. + +$ cd ramulator +$ make +$ make exe + +## Simulation Output +To be added. + +### Contributors +- Cheng Liu (National University of Singapore) diff --git a/configs/ALDRAM-config.cfg b/configs/ALDRAM-config.cfg new file mode 100644 index 0000000..7585d45 --- /dev/null +++ b/configs/ALDRAM-config.cfg @@ -0,0 +1,29 @@ +######################## +# Example config file +# Comments start with # +# There are restrictions for valid channel/rank numbers + standard = ALDRAM + channels = 1 + ranks = 1 + speed = ALDRAM_1600K + org = ALDRAM_4Gb_x8 +# record_cmd_trace: (default is off): on, off + record_cmd_trace = off +# print_cmd_trace: (default is off): on, off + print_cmd_trace = off + +### Below are parameters only for CPU trace + cpu_tick = 4 + mem_tick = 1 +### Below are parameters only for multicore mode +# When early_exit is on, all cores will be terminated when the earliest one finishes. + early_exit = on +# early_exit = on, off (default value is on) +# If expected_limit_insts is set, some per-core statistics will be recorded when this limit (or the end of the whole trace if it's shorter than specified limit) is reached. The simulation won't stop and will roll back automatically until the last one reaches the limit. + expected_limit_insts = 200000000 + cache = no +# cache = no, L1L2, L3, all (default value is no) + translation = None +# translation = None, Random (default value is None) +# +######################## diff --git a/configs/DDR3-config.cfg b/configs/DDR3-config.cfg new file mode 100644 index 0000000..53ca0ce --- /dev/null +++ b/configs/DDR3-config.cfg @@ -0,0 +1,29 @@ +######################## +# Example config file +# Comments start with # +# There are restrictions for valid channel/rank numbers + standard = DDR3 + channels = 1 + ranks = 1 + speed = DDR3_1600K + org = DDR3_2Gb_x8 +# record_cmd_trace: (default is off): on, off + record_cmd_trace = off +# print_cmd_trace: (default is off): on, off + print_cmd_trace = off + +### Below are parameters only for CPU trace + cpu_tick = 4 + mem_tick = 1 +### Below are parameters only for multicore mode +# When early_exit is on, all cores will be terminated when the earliest one finishes. + early_exit = on +# early_exit = on, off (default value is on) +# If expected_limit_insts is set, some per-core statistics will be recorded when this limit (or the end of the whole trace if it's shorter than specified limit) is reached. The simulation won't stop and will roll back automatically until the last one reaches the limit. + expected_limit_insts = 200000000 + cache = no +# cache = no, L1L2, L3, all (default value is no) + translation = None +# translation = None, Random (default value is None) +# +######################## diff --git a/configs/DDR4-config.cfg b/configs/DDR4-config.cfg new file mode 100644 index 0000000..a64ed7a --- /dev/null +++ b/configs/DDR4-config.cfg @@ -0,0 +1,29 @@ +######################## +# Example config file +# Comments start with # +# There are restrictions for valid channel/rank numbers + standard = DDR4 + channels = 1 + ranks = 1 + speed = DDR4_2400R + org = DDR4_4Gb_x8 +# record_cmd_trace: (default is off): on, off + record_cmd_trace = off +# print_cmd_trace: (default is off): on, off + print_cmd_trace = off + +### Below are parameters only for CPU trace + cpu_tick = 8 + mem_tick = 3 +### Below are parameters only for multicore mode +# When early_exit is on, all cores will be terminated when the earliest one finishes. + early_exit = on +# early_exit = on, off (default value is on) +# If expected_limit_insts is set, some per-core statistics will be recorded when this limit (or the end of the whole trace if it's shorter than specified limit) is reached. The simulation won't stop and will roll back automatically until the last one reaches the limit. + expected_limit_insts = 200000000 + cache = no +# cache = no, L1L2, L3, all (default value is no) + translation = None +# translation = None, Random (default value is None) +# +######################## diff --git a/configs/DSARP-config.cfg b/configs/DSARP-config.cfg new file mode 100644 index 0000000..825fb47 --- /dev/null +++ b/configs/DSARP-config.cfg @@ -0,0 +1,30 @@ +######################## +# Example config file +# Comments start with # +# There are restrictions for valid channel/rank numbers + standard = DSARP + subarrays = 8 + channels = 1 + ranks = 1 + speed = DSARP_1333 + org = DSARP_8Gb_x8 +# record_cmd_trace: (default is off): on, off + record_cmd_trace = off +# print_cmd_trace: (default is off): on, off + print_cmd_trace = off + +### Below are parameters only for CPU trace + cpu_tick = 4 + mem_tick = 1 +### Below are parameters only for multicore mode +# When early_exit is on, all cores will be terminated when the earliest one finishes. + early_exit = on +# early_exit = on, off (default value is on) +# If expected_limit_insts is set, some per-core statistics will be recorded when this limit (or the end of the whole trace if it's shorter than specified limit) is reached. The simulation won't stop and will roll back automatically until the last one reaches the limit. + expected_limit_insts = 200000000 + cache = no +# cache = no, L1L2, L3, all (default value is no) + translation = None +# translation = None, Random (default value is None) +# +######################## diff --git a/configs/GDDR5-config.cfg b/configs/GDDR5-config.cfg new file mode 100644 index 0000000..c3fab6f --- /dev/null +++ b/configs/GDDR5-config.cfg @@ -0,0 +1,29 @@ +######################## +# Example config file +# Comments start with # +# There are restrictions for valid channel/rank numbers + standard = GDDR5 + channels = 1 + ranks = 1 + speed = GDDR5_6000 + org = GDDR5_8Gb_x16 +# record_cmd_trace: (default is off): on, off + record_cmd_trace = off +# print_cmd_trace: (default is off): on, off + print_cmd_trace = off + +### Below are parameters only for CPU trace + cpu_tick = 2 + mem_tick = 1 +### Below are parameters only for multicore mode +# When early_exit is on, all cores will be terminated when the earliest one finishes. + early_exit = on +# early_exit = on, off (default value is on) +# If expected_limit_insts is set, some per-core statistics will be recorded when this limit (or the end of the whole trace if it's shorter than specified limit) is reached. The simulation won't stop and will roll back automatically until the last one reaches the limit. + expected_limit_insts = 200000000 + cache = no +# cache = no, L1L2, L3, all (default value is no) + translation = None +# translation = None, Random (default value is None) +# +######################## diff --git a/configs/HBM-config.cfg b/configs/HBM-config.cfg new file mode 100644 index 0000000..c9b2d2f --- /dev/null +++ b/configs/HBM-config.cfg @@ -0,0 +1,29 @@ +######################## +# Example config file +# Comments start with # +# There are restrictions for valid channel/rank numbers + standard = HBM + channels = 8 + ranks = 1 + speed = HBM_1Gbps + org = HBM_4Gb +# record_cmd_trace: (default is off): on, off + record_cmd_trace = off +# print_cmd_trace: (default is off): on, off + print_cmd_trace = off + +### Below are parameters only for CPU trace + cpu_tick = 32 + mem_tick = 5 +### Below are parameters only for multicore mode +# When early_exit is on, all cores will be terminated when the earliest one finishes. + early_exit = on +# early_exit = on, off (default value is on) +# If expected_limit_insts is set, some per-core statistics will be recorded when this limit (or the end of the whole trace if it's shorter than specified limit) is reached. The simulation won't stop and will roll back automatically until the last one reaches the limit. + expected_limit_insts = 200000000 + cache = no +# cache = no, L1L2, L3, all (default value is no) + translation = None +# translation = None, Random (default value is None) +# +######################## diff --git a/configs/LPDDR3-config.cfg b/configs/LPDDR3-config.cfg new file mode 100644 index 0000000..ab561a2 --- /dev/null +++ b/configs/LPDDR3-config.cfg @@ -0,0 +1,29 @@ +######################## +# Example config file +# Comments start with # +# There are restrictions for valid channel/rank numbers + standard = LPDDR3 + channels = 1 + ranks = 1 + speed = LPDDR3_1600 + org = LPDDR3_8Gb_x16 +# record_cmd_trace: (default is off): on, off + record_cmd_trace = off +# print_cmd_trace: (default is off): on, off + print_cmd_trace = off + +### Below are parameters only for CPU trace + cpu_tick = 4 + mem_tick = 1 +### Below are parameters only for multicore mode +# When early_exit is on, all cores will be terminated when the earliest one finishes. + early_exit = on +# early_exit = on, off (default value is on) +# If expected_limit_insts is set, some per-core statistics will be recorded when this limit (or the end of the whole trace if it's shorter than specified limit) is reached. The simulation won't stop and will roll back automatically until the last one reaches the limit. + expected_limit_insts = 200000000 + cache = no +# cache = no, L1L2, L3, all (default value is no) + translation = None +# translation = None, Random (default value is None) +# +######################## diff --git a/configs/LPDDR4-config.cfg b/configs/LPDDR4-config.cfg new file mode 100644 index 0000000..c370f67 --- /dev/null +++ b/configs/LPDDR4-config.cfg @@ -0,0 +1,29 @@ +######################## +# Example config file +# Comments start with # +# There are restrictions for valid channel/rank numbers + standard = LPDDR4 + channels = 2 + ranks = 1 + speed = LPDDR4_2400 + org = LPDDR4_8Gb_x16 +# record_cmd_trace: (default is off): on, off + record_cmd_trace = off +# print_cmd_trace: (default is off): on, off + print_cmd_trace = off + +### Below are parameters only for CPU trace + cpu_tick = 8 + mem_tick = 3 +### Below are parameters only for multicore mode +# When early_exit is on, all cores will be terminated when the earliest one finishes. + early_exit = on +# early_exit = on, off (default value is on) +# If expected_limit_insts is set, some per-core statistics will be recorded when this limit (or the end of the whole trace if it's shorter than specified limit) is reached. The simulation won't stop and will roll back automatically until the last one reaches the limit. + expected_limit_insts = 200000000 + cache = no +# cache = no, L1L2, L3, all (default value is no) + translation = None +# translation = None, Random (default value is None) +# +######################## diff --git a/configs/SALP-config.cfg b/configs/SALP-config.cfg new file mode 100644 index 0000000..10d3d11 --- /dev/null +++ b/configs/SALP-config.cfg @@ -0,0 +1,30 @@ +######################## +# Example config file +# Comments start with # +# There are restrictions for valid channel/rank numbers + standard = SALP-MASA + subarrays = 8 + channels = 1 + ranks = 1 + speed = SALP_1600K + org = SALP_4Gb_x8 +# record_cmd_trace: (default is off): on, off + record_cmd_trace = off +# print_cmd_trace: (default is off): on, off + print_cmd_trace = off + +### Below are parameters only for CPU trace + cpu_tick = 4 + mem_tick = 1 +### Below are parameters only for multicore mode +# When early_exit is on, all cores will be terminated when the earliest one finishes. + early_exit = on +# early_exit = on, off (default value is on) +# If expected_limit_insts is set, some per-core statistics will be recorded when this limit (or the end of the whole trace if it's shorter than specified limit) is reached. The simulation won't stop and will roll back automatically until the last one reaches the limit. + expected_limit_insts = 200000000 + cache = no +# cache = no, L1L2, L3, all (default value is no) + translation = None +# translation = None, Random (default value is None) +# +######################## diff --git a/configs/TLDRAM-config.cfg b/configs/TLDRAM-config.cfg new file mode 100644 index 0000000..14bf2a5 --- /dev/null +++ b/configs/TLDRAM-config.cfg @@ -0,0 +1,30 @@ +######################## +# Example config file +# Comments start with # +# There are restrictions for valid channel/rank numbers + standard = TLDRAM + subarrays = 16 + channels = 1 + ranks = 1 + speed = TLDRAM_1600K + org = TLDRAM_4Gb_x8 +# record_cmd_trace: (default is off): on, off + record_cmd_trace = off +# print_cmd_trace: (default is off): on, off + print_cmd_trace = off + +### Below are parameters only for CPU trace + cpu_tick = 4 + mem_tick = 1 +### Below are parameters only for multicore mode +# When early_exit is on, all cores will be terminated when the earliest one finishes. + early_exit = on +# early_exit = on, off (default value is on) +# If expected_limit_insts is set, some per-core statistics will be recorded when this limit (or the end of the whole trace if it's shorter than specified limit) is reached. The simulation won't stop and will roll back automatically until the last one reaches the limit. + expected_limit_insts = 200000000 + cache = no +# cache = no, L1L2, L3, all (default value is no) + translation = None +# translation = None, Random (default value is None) +# +######################## diff --git a/configs/WideIO-config.cfg b/configs/WideIO-config.cfg new file mode 100644 index 0000000..c8ef182 --- /dev/null +++ b/configs/WideIO-config.cfg @@ -0,0 +1,29 @@ +######################## +# Example config file +# Comments start with # +# There are restrictions for valid channel/rank numbers + standard = WideIO + channels = 4 + ranks = 1 + speed = WideIO_266 + org = WideIO_8Gb +# record_cmd_trace: (default is off): on, off + record_cmd_trace = off +# print_cmd_trace: (default is off): on, off + print_cmd_trace = off + +### Below are parameters only for CPU trace + cpu_tick = 4 + mem_tick = 1 +### Below are parameters only for multicore mode +# When early_exit is on, all cores will be terminated when the earliest one finishes. + early_exit = on +# early_exit = on, off (default value is on) +# If expected_limit_insts is set, some per-core statistics will be recorded when this limit (or the end of the whole trace if it's shorter than specified limit) is reached. The simulation won't stop and will roll back automatically until the last one reaches the limit. + expected_limit_insts = 200000000 + cache = no +# cache = no, L1L2, L3, all (default value is no) + translation = None +# translation = None, Random (default value is None) +# +######################## diff --git a/configs/WideIO2-config.cfg b/configs/WideIO2-config.cfg new file mode 100644 index 0000000..bafe1b1 --- /dev/null +++ b/configs/WideIO2-config.cfg @@ -0,0 +1,29 @@ +######################## +# Example config file +# Comments start with # +# There are restrictions for valid channel/rank numbers + standard = WideIO2 + channels = 8 + ranks = 1 + speed = WideIO2_1066 + org = WideIO2_8Gb +# record_cmd_trace: (default is off): on, off + record_cmd_trace = off +# print_cmd_trace: (default is off): on, off + print_cmd_trace = off + +### Below are parameters only for CPU trace + cpu_tick = 6 + mem_tick = 1 +### Below are parameters only for multicore mode +# When early_exit is on, all cores will be terminated when the earliest one finishes. + early_exit = on +# early_exit = on, off (default value is on) +# If expected_limit_insts is set, some per-core statistics will be recorded when this limit (or the end of the whole trace if it's shorter than specified limit) is reached. The simulation won't stop and will roll back automatically until the last one reaches the limit. + expected_limit_insts = 200000000 + cache = no +# cache = no, L1L2, L3, all (default value is no) + translation = None +# translatino = None, Random (default value is None) +# +######################## diff --git a/dram.trace b/dram.trace new file mode 100644 index 0000000..e1accc2 --- /dev/null +++ b/dram.trace @@ -0,0 +1,7 @@ +0x12345680 W +0x12345680 R +0x35d46f00 R +0x4cbd56c0 W +0x12345680 R +0x696fed40 W +0x7876af80 R diff --git a/src/ALDRAM.cpp b/src/ALDRAM.cpp new file mode 100644 index 0000000..c6f9fe3 --- /dev/null +++ b/src/ALDRAM.cpp @@ -0,0 +1,361 @@ +#include + +#include "ALDRAM.h" +#include "DRAM.h" +#include +#include +#include + +using namespace std; +using namespace ramulator; + +string ALDRAM::standard_name = "ALDRAM"; + +map ALDRAM::org_map = { + {"ALDRAM_512Mb_x4", ALDRAM::Org::ALDRAM_512Mb_x4}, {"ALDRAM_512Mb_x8", ALDRAM::Org::ALDRAM_512Mb_x8}, {"ALDRAM_512Mb_x16", ALDRAM::Org::ALDRAM_512Mb_x16}, + {"ALDRAM_1Gb_x4", ALDRAM::Org::ALDRAM_1Gb_x4}, {"ALDRAM_1Gb_x8", ALDRAM::Org::ALDRAM_1Gb_x8}, {"ALDRAM_1Gb_x16", ALDRAM::Org::ALDRAM_1Gb_x16}, + {"ALDRAM_2Gb_x4", ALDRAM::Org::ALDRAM_2Gb_x4}, {"ALDRAM_2Gb_x8", ALDRAM::Org::ALDRAM_2Gb_x8}, {"ALDRAM_2Gb_x16", ALDRAM::Org::ALDRAM_2Gb_x16}, + {"ALDRAM_4Gb_x4", ALDRAM::Org::ALDRAM_4Gb_x4}, {"ALDRAM_4Gb_x8", ALDRAM::Org::ALDRAM_4Gb_x8}, {"ALDRAM_4Gb_x16", ALDRAM::Org::ALDRAM_4Gb_x16}, + {"ALDRAM_8Gb_x4", ALDRAM::Org::ALDRAM_8Gb_x4}, {"ALDRAM_8Gb_x8", ALDRAM::Org::ALDRAM_8Gb_x8}, {"ALDRAM_8Gb_x16", ALDRAM::Org::ALDRAM_8Gb_x16}, +}; + +map ALDRAM::speed_map = { + {"ALDRAM_800D", ALDRAM::Speed::ALDRAM_800D}, {"ALDRAM_800E", ALDRAM::Speed::ALDRAM_800E}, + {"ALDRAM_1066E", ALDRAM::Speed::ALDRAM_1066E}, {"ALDRAM_1066F", ALDRAM::Speed::ALDRAM_1066F}, {"ALDRAM_1066G", ALDRAM::Speed::ALDRAM_1066G}, + {"ALDRAM_1333G", ALDRAM::Speed::ALDRAM_1333G}, {"ALDRAM_1333H", ALDRAM::Speed::ALDRAM_1333H}, + {"ALDRAM_1600H", ALDRAM::Speed::ALDRAM_1600H}, {"ALDRAM_1600J", ALDRAM::Speed::ALDRAM_1600J}, {"ALDRAM_1600K", ALDRAM::Speed::ALDRAM_1600K}, + {"ALDRAM_1866K", ALDRAM::Speed::ALDRAM_1866K}, {"ALDRAM_1866L", ALDRAM::Speed::ALDRAM_1866L}, + {"ALDRAM_2133L", ALDRAM::Speed::ALDRAM_2133L}, {"ALDRAM_2133M", ALDRAM::Speed::ALDRAM_2133M}, +}; + + +ALDRAM::ALDRAM(Org org, Speed speed) : + org_entry(org_table[int(org)]), + speed_entry(speed_table[int(Temp::COLD)][int(speed)]), + read_latency(speed_entry.nCL + speed_entry.nBL) +{ + current_speed = speed; + init_speed(); + init_prereq(); + init_rowhit(); // SAUGATA: added row hit function + init_lambda(); + init_timing(speed_table[int(Temp::HOT)][int(speed)]); + temperature = Temp::COLD; +} + +ALDRAM::ALDRAM(const string& org_str, const string& speed_str) : + ALDRAM(org_map[org_str], speed_map[speed_str]) +{ +} + +void ALDRAM::set_channel_number(int channel) { + org_entry.count[int(Level::Channel)] = channel; +} + +void ALDRAM::set_rank_number(int rank) { + org_entry.count[int(Level::Rank)] = rank; +} + +void ALDRAM::aldram_timing(Temp current_temperature) +{ + for (int i = 0; i < int(Level::MAX); i++) { + for (int j = 0; j < int(Command::MAX); j++) { + timing[i][j].clear(); + } + } + temperature = current_temperature; + read_latency = speed_entry.nCL + speed_entry.nBL; + init_timing(speed_table[int(temperature)][int(current_speed)]); + + //std::cout << "vector size: " << timing[int(Temp::HOT)][int(current_speed)].size() << endl; + //std::cout << "after cold nRCD : "; + //std::cout << int(timing[int(Level::Bank)][int(Command::ACT)][0].val) << endl << endl; +} + +void ALDRAM::init_speed() +{ + // nRRD, nFAW + int page = (org_entry.dq * org_entry.count[int(Level::Column)]) >> 13; + switch (speed_entry.rate) { + case 800: speed_entry.nRRD = (page==1) ? 4 : 4; speed_entry.nFAW = (page==1) ? 16 : 20; break; + case 1066: speed_entry.nRRD = (page==1) ? 4 : 6; speed_entry.nFAW = (page==1) ? 20 : 27; break; + case 1333: speed_entry.nRRD = (page==1) ? 4 : 5; speed_entry.nFAW = (page==1) ? 20 : 30; break; + case 1600: speed_entry.nRRD = (page==1) ? 5 : 6; speed_entry.nFAW = (page==1) ? 24 : 32; break; + case 1866: speed_entry.nRRD = (page==1) ? 5 : 6; speed_entry.nFAW = (page==1) ? 26 : 33; break; + case 2133: speed_entry.nRRD = (page==1) ? 5 : 6; speed_entry.nFAW = (page==1) ? 27 : 34; break; + default: assert(false); + } + + // nRFC, nXS + int chip = org_entry.size; + switch (speed_entry.rate) { + case 800: speed_entry.nRFC = (chip==512) ? 36 : (chip==1<<10) ? 44 : (chip==1<<11) ? 64 : (chip==1<<12) ? 104 : 140; break; + case 1066: speed_entry.nRFC = (chip==512) ? 48 : (chip==1<<10) ? 59 : (chip==1<<11) ? 86 : (chip==1<<12) ? 139 : 187; break; + case 1333: speed_entry.nRFC = (chip==512) ? 60 : (chip==1<<10) ? 74 : (chip==1<<11) ? 107 : (chip==1<<12) ? 174 : 234; break; + case 1600: speed_entry.nRFC = (chip==512) ? 72 : (chip==1<<10) ? 88 : (chip==1<<11) ? 128 : (chip==1<<12) ? 208 : 280; break; + case 1866: speed_entry.nRFC = (chip==512) ? 84 : (chip==1<<10) ? 103 : (chip==1<<11) ? 150 : (chip==1<<12) ? 243 : 327; break; + case 2133: speed_entry.nRFC = (chip==512) ? 96 : (chip==1<<10) ? 118 : (chip==1<<11) ? 171 : (chip==1<<12) ? 278 : 374; break; + default: assert(false); + } + switch (speed_entry.rate) { + case 800: speed_entry.nXS = (chip==512) ? 40 : (chip==1<<10) ? 48 : (chip==1<<11) ? 68 : (chip==1<<12) ? 108 : 144; break; + case 1066: speed_entry.nXS = (chip==512) ? 54 : (chip==1<<10) ? 64 : (chip==1<<11) ? 91 : (chip==1<<12) ? 144 : 192; break; + case 1333: speed_entry.nXS = (chip==512) ? 67 : (chip==1<<10) ? 80 : (chip==1<<11) ? 114 : (chip==1<<12) ? 180 : 240; break; + case 1600: speed_entry.nXS = (chip==512) ? 80 : (chip==1<<10) ? 96 : (chip==1<<11) ? 136 : (chip==1<<12) ? 216 : 288; break; + case 1866: speed_entry.nXS = (chip==512) ? 94 : (chip==1<<10) ? 112 : (chip==1<<11) ? 159 : (chip==1<<12) ? 252 : 336; break; + case 2133: speed_entry.nXS = (chip==512) ? 107 : (chip==1<<10) ? 128 : (chip==1<<11) ? 182 : (chip==1<<12) ? 288 : 384; break; + default: assert(false); + } +} + + +void ALDRAM::init_prereq() +{ + // RD + prereq[int(Level::Rank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::PowerUp): return Command::MAX; + case int(State::ActPowerDown): return Command::PDX; + case int(State::PrePowerDown): return Command::PDX; + case int(State::SelfRefresh): return Command::SRX; + default: assert(false); + }}; + prereq[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::Closed): return Command::ACT; + case int(State::Opened): + if (node->row_state.find(id) != node->row_state.end()) + return cmd; + return Command::PRE; + default: assert(false); + }}; + + // WR + prereq[int(Level::Rank)][int(Command::WR)] = prereq[int(Level::Rank)][int(Command::RD)]; + prereq[int(Level::Bank)][int(Command::WR)] = prereq[int(Level::Bank)][int(Command::RD)]; + + // REF + prereq[int(Level::Rank)][int(Command::REF)] = [] (DRAM* node, Command cmd, int id) { + for (auto bank : node->children) { + if (bank->state == State::Closed) + continue; + return Command::PREA; + } + return Command::REF;}; + + // PD + prereq[int(Level::Rank)][int(Command::PDE)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::PowerUp): return Command::PDE; + case int(State::ActPowerDown): return Command::PDE; + case int(State::PrePowerDown): return Command::PDE; + case int(State::SelfRefresh): return Command::SRX; + default: assert(false); + }}; + + // SR + prereq[int(Level::Rank)][int(Command::SRE)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::PowerUp): return Command::SRE; + case int(State::ActPowerDown): return Command::PDX; + case int(State::PrePowerDown): return Command::PDX; + case int(State::SelfRefresh): return Command::SRE; + default: assert(false); + }}; +} + +// SAUGATA: added row hit check functions to see if the desired location is currently open +void ALDRAM::init_rowhit() +{ + // RD + rowhit[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::Closed): return false; + case int(State::Opened): + if (node->row_state.find(id) != node->row_state.end()) + return true; + return false; + default: assert(false); + }}; + + // WR + rowhit[int(Level::Bank)][int(Command::WR)] = rowhit[int(Level::Bank)][int(Command::RD)]; +} + + +void ALDRAM::init_lambda() +{ + lambda[int(Level::Bank)][int(Command::ACT)] = [] (DRAM* node, int id) { + node->state = State::Opened; + node->row_state[id] = State::Opened;}; + lambda[int(Level::Bank)][int(Command::PRE)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + lambda[int(Level::Rank)][int(Command::PREA)] = [] (DRAM* node, int id) { + for (auto bank : node->children) { + bank->state = State::Closed; + bank->row_state.clear();}}; + lambda[int(Level::Rank)][int(Command::REF)] = [] (DRAM* node, int id) {}; + lambda[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, int id) {}; + lambda[int(Level::Bank)][int(Command::WR)] = [] (DRAM* node, int id) {}; + lambda[int(Level::Bank)][int(Command::RDA)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + lambda[int(Level::Bank)][int(Command::WRA)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + lambda[int(Level::Rank)][int(Command::PDE)] = [] (DRAM* node, int id) { + for (auto bank : node->children) { + if (bank->state == State::Closed) + continue; + node->state = State::ActPowerDown; + return; + } + node->state = State::PrePowerDown;}; + lambda[int(Level::Rank)][int(Command::PDX)] = [] (DRAM* node, int id) { + node->state = State::PowerUp;}; + lambda[int(Level::Rank)][int(Command::SRE)] = [] (DRAM* node, int id) { + node->state = State::SelfRefresh;}; + lambda[int(Level::Rank)][int(Command::SRX)] = [] (DRAM* node, int id) { + node->state = State::PowerUp;}; +} + + +void ALDRAM::init_timing(SpeedEntry speed_entry) +{ + SpeedEntry& s = speed_entry; + vector *t; + + /*** Channel ***/ + t = timing[int(Level::Channel)]; + + // CAS <-> CAS + t[int(Command::RD)].push_back({Command::RD, 1, s.nBL}); + t[int(Command::RD)].push_back({Command::RDA, 1, s.nBL}); + t[int(Command::RDA)].push_back({Command::RD, 1, s.nBL}); + t[int(Command::RDA)].push_back({Command::RDA, 1, s.nBL}); + t[int(Command::WR)].push_back({Command::WR, 1, s.nBL}); + t[int(Command::WR)].push_back({Command::WRA, 1, s.nBL}); + t[int(Command::WRA)].push_back({Command::WR, 1, s.nBL}); + t[int(Command::WRA)].push_back({Command::WRA, 1, s.nBL}); + + + /*** Rank ***/ + t = timing[int(Level::Rank)]; + + // CAS <-> CAS + t[int(Command::RD)].push_back({Command::RD, 1, s.nCCD}); + t[int(Command::RD)].push_back({Command::RDA, 1, s.nCCD}); + t[int(Command::RDA)].push_back({Command::RD, 1, s.nCCD}); + t[int(Command::RDA)].push_back({Command::RDA, 1, s.nCCD}); + t[int(Command::WR)].push_back({Command::WR, 1, s.nCCD}); + t[int(Command::WR)].push_back({Command::WRA, 1, s.nCCD}); + t[int(Command::WRA)].push_back({Command::WR, 1, s.nCCD}); + t[int(Command::WRA)].push_back({Command::WRA, 1, s.nCCD}); + t[int(Command::RD)].push_back({Command::WR, 1, s.nCL + s.nCCD + 2 - s.nCWL}); + t[int(Command::RD)].push_back({Command::WRA, 1, s.nCL + s.nCCD + 2 - s.nCWL}); + t[int(Command::RDA)].push_back({Command::WR, 1, s.nCL + s.nCCD + 2 - s.nCWL}); + t[int(Command::RDA)].push_back({Command::WRA, 1, s.nCL + s.nCCD + 2 - s.nCWL}); + t[int(Command::WR)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nWTR}); + t[int(Command::WR)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nWTR}); + t[int(Command::WRA)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nWTR}); + t[int(Command::WRA)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nWTR}); + + // CAS <-> CAS (between sibling ranks) + t[int(Command::RD)].push_back({Command::RD, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RD)].push_back({Command::RDA, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RDA)].push_back({Command::RD, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RDA)].push_back({Command::RDA, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RD)].push_back({Command::WR, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RD)].push_back({Command::WRA, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RDA)].push_back({Command::WR, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RDA)].push_back({Command::WRA, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RD)].push_back({Command::WR, 1, s.nCL + s.nBL + s.nRTRS - s.nCWL, true}); + t[int(Command::RD)].push_back({Command::WRA, 1, s.nCL + s.nBL + s.nRTRS - s.nCWL, true}); + t[int(Command::RDA)].push_back({Command::WR, 1, s.nCL + s.nBL + s.nRTRS - s.nCWL, true}); + t[int(Command::RDA)].push_back({Command::WRA, 1, s.nCL + s.nBL + s.nRTRS - s.nCWL, true}); + t[int(Command::WR)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nRTRS - s.nCL, true}); + t[int(Command::WR)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nRTRS - s.nCL, true}); + t[int(Command::WRA)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nRTRS - s.nCL, true}); + t[int(Command::WRA)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nRTRS - s.nCL, true}); + + t[int(Command::RD)].push_back({Command::PREA, 1, s.nRTP}); + t[int(Command::WR)].push_back({Command::PREA, 1, s.nCWL + s.nBL + s.nWR}); + + // CAS <-> PD + t[int(Command::RD)].push_back({Command::PDE, 1, s.nCL + s.nBL + 1}); + t[int(Command::RDA)].push_back({Command::PDE, 1, s.nCL + s.nBL + 1}); + t[int(Command::WR)].push_back({Command::PDE, 1, s.nCWL + s.nBL + s.nWR}); + t[int(Command::WRA)].push_back({Command::PDE, 1, s.nCWL + s.nBL + s.nWR + 1}); // +1 for pre + t[int(Command::PDX)].push_back({Command::RD, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::RDA, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::WR, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::WRA, 1, s.nXP}); + + // CAS <-> SR: none (all banks have to be precharged) + + // RAS <-> RAS + t[int(Command::ACT)].push_back({Command::ACT, 1, s.nRRD}); + t[int(Command::ACT)].push_back({Command::ACT, 4, s.nFAW}); + t[int(Command::ACT)].push_back({Command::PREA, 1, s.nRAS}); + t[int(Command::PREA)].push_back({Command::ACT, 1, s.nRP}); + + // RAS <-> REF + t[int(Command::PRE)].push_back({Command::REF, 1, s.nRP}); + t[int(Command::PREA)].push_back({Command::REF, 1, s.nRP}); + t[int(Command::REF)].push_back({Command::ACT, 1, s.nRFC}); + + // RAS <-> PD + t[int(Command::ACT)].push_back({Command::PDE, 1, 1}); + t[int(Command::PDX)].push_back({Command::ACT, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::PRE, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::PREA, 1, s.nXP}); + + // RAS <-> SR + t[int(Command::PRE)].push_back({Command::SRE, 1, s.nRP}); + t[int(Command::PREA)].push_back({Command::SRE, 1, s.nRP}); + t[int(Command::SRX)].push_back({Command::ACT, 1, s.nXS}); + + // REF <-> REF + t[int(Command::REF)].push_back({Command::REF, 1, s.nRFC}); + + // REF <-> PD + t[int(Command::REF)].push_back({Command::PDE, 1, 1}); + t[int(Command::PDX)].push_back({Command::REF, 1, s.nXP}); + + // REF <-> SR + t[int(Command::SRX)].push_back({Command::REF, 1, s.nXS}); + + // PD <-> PD + t[int(Command::PDE)].push_back({Command::PDX, 1, s.nPD}); + t[int(Command::PDX)].push_back({Command::PDE, 1, s.nXP}); + + // PD <-> SR + t[int(Command::PDX)].push_back({Command::SRE, 1, s.nXP}); + t[int(Command::SRX)].push_back({Command::PDE, 1, s.nXS}); + + // SR <-> SR + t[int(Command::SRE)].push_back({Command::SRX, 1, s.nCKESR}); + t[int(Command::SRX)].push_back({Command::SRE, 1, s.nXS}); + + + /*** Bank ***/ + t = timing[int(Level::Bank)]; + + // CAS <-> RAS + t[int(Command::ACT)].push_back({Command::RD, 1, s.nRCD}); + t[int(Command::ACT)].push_back({Command::RDA, 1, s.nRCD}); + t[int(Command::ACT)].push_back({Command::WR, 1, s.nRCD}); + t[int(Command::ACT)].push_back({Command::WRA, 1, s.nRCD}); + + t[int(Command::RD)].push_back({Command::PRE, 1, s.nRTP}); + t[int(Command::WR)].push_back({Command::PRE, 1, s.nCWL + s.nBL + s.nWR}); + + t[int(Command::RDA)].push_back({Command::ACT, 1, s.nRTP + s.nRP}); + t[int(Command::WRA)].push_back({Command::ACT, 1, s.nCWL + s.nBL + s.nWR + s.nRP}); + + // RAS <-> RAS + t[int(Command::ACT)].push_back({Command::ACT, 1, s.nRC}); + t[int(Command::ACT)].push_back({Command::PRE, 1, s.nRAS}); + t[int(Command::PRE)].push_back({Command::ACT, 1, s.nRP}); +} diff --git a/src/ALDRAM.h b/src/ALDRAM.h new file mode 100644 index 0000000..e002660 --- /dev/null +++ b/src/ALDRAM.h @@ -0,0 +1,247 @@ +#ifndef __ALDRAM_H +#define __ALDRAM_H + +#include "DRAM.h" +#include "Request.h" +#include +#include +#include +#include + +using namespace std; + +namespace ramulator +{ + +class ALDRAM +{ +public: + static string standard_name; + enum class Org; + enum class Speed; + enum class Temp; + + ALDRAM(Org org, Speed speed); + ALDRAM(const string& org_str, const string& speed_str); + + static map org_map; + static map speed_map; + /*** Level ***/ + enum class Level : int + { + Channel, Rank, Bank, Row, Column, MAX + }; + + /*** Command ***/ + enum class Command : int + { + ACT, PRE, PREA, + RD, WR, RDA, WRA, + REF, PDE, PDX, SRE, SRX, + MAX + }; + + string command_name[int(Command::MAX)] = { + "ACT", "PRE", "PREA", + "RD", "WR", "RDA", "WRA", + "REF", "PDE", "PDX", "SRE", "SRX" + }; + + Level scope[int(Command::MAX)] = { + Level::Row, Level::Bank, Level::Rank, + Level::Column, Level::Column, Level::Column, Level::Column, + Level::Rank, Level::Rank, Level::Rank, Level::Rank, Level::Rank + }; + + bool is_opening(Command cmd) + { + switch(int(cmd)) { + case int(Command::ACT): + return true; + default: + return false; + } + } + + bool is_accessing(Command cmd) + { + switch(int(cmd)) { + case int(Command::RD): + case int(Command::WR): + case int(Command::RDA): + case int(Command::WRA): + return true; + default: + return false; + } + } + + bool is_closing(Command cmd) + { + switch(int(cmd)) { + case int(Command::RDA): + case int(Command::WRA): + case int(Command::PRE): + case int(Command::PREA): + return true; + default: + return false; + } + } + + bool is_refreshing(Command cmd) + { + switch(int(cmd)) { + case int(Command::REF): + return true; + default: + return false; + } + } + + + /* State */ + enum class State : int + { + Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX + } start[int(Level::MAX)] = { + State::MAX, State::PowerUp, State::Closed, State::Closed, State::MAX + }; + + /* Translate */ + Command translate[int(Request::Type::MAX)] = { + Command::RD, Command::WR, + Command::REF, Command::PDE, Command::SRE + }; + + /* Prerequisite */ + function*, Command cmd, int)> prereq[int(Level::MAX)][int(Command::MAX)]; + + // SAUGATA: added function object container for row hit status + /* Row hit */ + function*, Command cmd, int)> rowhit[int(Level::MAX)][int(Command::MAX)]; + function*, Command cmd, int)> rowopen[int(Level::MAX)][int(Command::MAX)]; + + /* Timing */ + struct TimingEntry + { + Command cmd; + int dist; + int val; + bool sibling; + }; + vector timing[int(Level::MAX)][int(Command::MAX)]; + + /* Lambda */ + function*, int)> lambda[int(Level::MAX)][int(Command::MAX)]; + + /* Organization */ + enum class Org : int + { + ALDRAM_512Mb_x4, ALDRAM_512Mb_x8, ALDRAM_512Mb_x16, + ALDRAM_1Gb_x4, ALDRAM_1Gb_x8, ALDRAM_1Gb_x16, + ALDRAM_2Gb_x4, ALDRAM_2Gb_x8, ALDRAM_2Gb_x16, + ALDRAM_4Gb_x4, ALDRAM_4Gb_x8, ALDRAM_4Gb_x16, + ALDRAM_8Gb_x4, ALDRAM_8Gb_x8, ALDRAM_8Gb_x16, + MAX + }; + + struct OrgEntry { + int size; + int dq; + int count[int(Level::MAX)]; + } org_table[int(Org::MAX)] = { + { 512, 4, {0, 0, 8, 1<<13, 1<<11}}, { 512, 8, {0, 0, 8, 1<<13, 1<<10}}, { 512, 16, {0, 0, 8, 1<<12, 1<<10}}, + {1<<10, 4, {0, 0, 8, 1<<14, 1<<11}}, {1<<10, 8, {0, 0, 8, 1<<14, 1<<10}}, {1<<10, 16, {0, 0, 8, 1<<13, 1<<10}}, + {2<<10, 4, {0, 0, 8, 1<<15, 1<<11}}, {2<<10, 8, {0, 0, 8, 1<<15, 1<<10}}, {2<<10, 16, {0, 0, 8, 1<<14, 1<<10}}, + {4<<10, 4, {0, 0, 8, 1<<16, 1<<11}}, {4<<10, 8, {0, 0, 8, 1<<16, 1<<10}}, {4<<10, 16, {0, 0, 8, 1<<15, 1<<10}}, + {8<<10, 4, {0, 0, 8, 1<<16, 1<<12}}, {8<<10, 8, {0, 0, 8, 1<<16, 1<<11}}, {8<<10, 16, {0, 0, 8, 1<<16, 1<<10}} + }, org_entry; + + void set_channel_number(int channel); + void set_rank_number(int rank); + + /* Speed */ + enum class Speed : int + { + ALDRAM_800D, ALDRAM_800E, + ALDRAM_1066E, ALDRAM_1066F, ALDRAM_1066G, + ALDRAM_1333G, ALDRAM_1333H, + ALDRAM_1600H, ALDRAM_1600J, ALDRAM_1600K, + ALDRAM_1866K, ALDRAM_1866L, + ALDRAM_2133L, ALDRAM_2133M, + MAX + }; + + Speed current_speed; + + enum class Temp : int + { + COLD, HOT, MAX + }; + + Temp temperature = Temp::HOT; // DHL + + int prefetch_size = 8; // 8n prefetch DDR + int channel_width = 64; + + struct SpeedEntry { + int rate; + double freq, tCK; + int nBL, nCCD, nRTRS; + int nCL, nRCD, nRP, nCWL; + int nRAS, nRC; + int nRTP, nWTR, nWR; + int nRRD, nFAW; + int nRFC, nREFI; + int nPD, nXP, nXPDLL; + int nCKESR, nXS, nXSDLL; + } speed_table[int(Temp::MAX)][int(Speed::MAX)] = { + { + {800, (400.0/3)*3, (3/0.4)/3, 4, 4, 2, 5, 5-1, 5-1, 5, 15-5, 20-6, 4, 4, 6, 0, 0, 0, 3120, 3, 3, 10, 4, 0, 512}, + {800, (400.0/3)*3, (3/0.4)/3, 4, 4, 2, 6, 6-1, 6-1, 5, 15-5, 21-6, 4, 4, 6, 0, 0, 0, 3120, 3, 3, 10, 4, 0, 512}, + {1066, (400.0/3)*4, (3/0.4)/4, 4, 4, 2, 6, 6-1, 6-1, 6, 20-5, 26-6, 4, 4, 8, 0, 0, 0, 4160, 3, 4, 13, 4, 0, 512}, + {1066, (400.0/3)*4, (3/0.4)/4, 4, 4, 2, 7, 7-1, 7-1, 6, 20-5, 27-6, 4, 4, 8, 0, 0, 0, 4160, 3, 4, 13, 4, 0, 512}, + {1066, (400.0/3)*4, (3/0.4)/4, 4, 4, 2, 8, 8-1, 8-1, 6, 20-5, 28-6, 4, 4, 8, 0, 0, 0, 4160, 3, 4, 13, 4, 0, 512}, + {1333, (400.0/3)*5, (3/0.4)/5, 4, 4, 2, 8, 8-1, 8-1, 7, 24-5, 32-6, 5, 5, 10, 0, 0, 0, 5200, 4, 4, 16, 5, 0, 512}, + {1333, (400.0/3)*5, (3/0.4)/5, 4, 4, 2, 9, 9-1, 9-1, 7, 24-5, 33-6, 5, 5, 10, 0, 0, 0, 5200, 4, 4, 16, 5, 0, 512}, + {1600, (400.0/3)*6, (3/0.4)/6, 4, 4, 2, 9, 9-2, 9-2, 8, 28-10, 37-12, 6, 6, 12, 0, 0, 0, 6240, 4, 5, 20, 5, 0, 512}, + {1600, (400.0/3)*6, (3/0.4)/6, 4, 4, 2, 10, 10-2, 10-2, 8, 28-10, 38-12, 6, 6, 12, 0, 0, 0, 6240, 4, 5, 20, 5, 0, 512}, + {1600, (400.0/3)*6, (3/0.4)/6, 4, 4, 2, 11, 11-2, 11-2, 8, 28-10, 39-12, 6, 6, 12, 0, 0, 0, 6240, 4, 5, 20, 5, 0, 512}, + {1866, (400.0/3)*7, (3/0.4)/7, 4, 4, 2, 11, 11-2, 11-2, 9, 32-10, 43-12, 7, 7, 14, 0, 0, 0, 7280, 5, 6, 23, 6, 0, 512}, + {1866, (400.0/3)*7, (3/0.4)/7, 4, 4, 2, 12, 12-2, 12-3, 9, 32-10, 44-13, 7, 7, 14, 0, 0, 0, 7280, 5, 6, 23, 6, 0, 512}, + {2133, (400.0/3)*8, (3/0.4)/8, 4, 4, 2, 12, 12-2, 12-3, 10, 36-10, 48-13, 8, 8, 16, 0, 0, 0, 8320, 6, 7, 26, 7, 0, 512}, + {2133, (400.0/3)*8, (3/0.4)/8, 4, 4, 2, 13, 13-2, 13-3, 10, 36-10, 49-13, 8, 8, 16, 0, 0, 0, 8320, 6, 7, 26, 7, 0, 512} + }, + { + {800, (400.0/3)*3, (3/0.4)/3, 4, 4, 2, 5, 5, 5, 5, 15, 20, 4, 4, 6, 0, 0, 0, 3120, 3, 3, 10, 4, 0, 512}, + {800, (400.0/3)*3, (3/0.4)/3, 4, 4, 2, 6, 6, 6, 5, 15, 21, 4, 4, 6, 0, 0, 0, 3120, 3, 3, 10, 4, 0, 512}, + {1066, (400.0/3)*4, (3/0.4)/4, 4, 4, 2, 6, 6, 6, 6, 20, 26, 4, 4, 8, 0, 0, 0, 4160, 3, 4, 13, 4, 0, 512}, + {1066, (400.0/3)*4, (3/0.4)/4, 4, 4, 2, 7, 7, 7, 6, 20, 27, 4, 4, 8, 0, 0, 0, 4160, 3, 4, 13, 4, 0, 512}, + {1066, (400.0/3)*4, (3/0.4)/4, 4, 4, 2, 8, 8, 8, 6, 20, 28, 4, 4, 8, 0, 0, 0, 4160, 3, 4, 13, 4, 0, 512}, + {1333, (400.0/3)*5, (3/0.4)/5, 4, 4, 2, 8, 8, 8, 7, 24, 32, 5, 5, 10, 0, 0, 0, 5200, 4, 4, 16, 5, 0, 512}, + {1333, (400.0/3)*5, (3/0.4)/5, 4, 4, 2, 9, 9, 9, 7, 24, 33, 5, 5, 10, 0, 0, 0, 5200, 4, 4, 16, 5, 0, 512}, + {1600, (400.0/3)*6, (3/0.4)/6, 4, 4, 2, 9, 9, 9, 8, 28, 37, 6, 6, 12, 0, 0, 0, 6240, 4, 5, 20, 5, 0, 512}, + {1600, (400.0/3)*6, (3/0.4)/6, 4, 4, 2, 10, 10, 10, 8, 28, 38, 6, 6, 12, 0, 0, 0, 6240, 4, 5, 20, 5, 0, 512}, + {1600, (400.0/3)*6, (3/0.4)/6, 4, 4, 2, 11, 11, 11, 8, 28, 39, 6, 6, 12, 0, 0, 0, 6240, 4, 5, 20, 5, 0, 512}, + {1866, (400.0/3)*7, (3/0.4)/7, 4, 4, 2, 11, 11, 11, 9, 32, 43, 7, 7, 14, 0, 0, 0, 7280, 5, 6, 23, 6, 0, 512}, + {1866, (400.0/3)*7, (3/0.4)/7, 4, 4, 2, 12, 12, 12, 9, 32, 44, 7, 7, 14, 0, 0, 0, 7280, 5, 6, 23, 6, 0, 512}, + {2133, (400.0/3)*8, (3/0.4)/8, 4, 4, 2, 12, 12, 12, 10, 36, 48, 8, 8, 16, 0, 0, 0, 8320, 6, 7, 26, 7, 0, 512}, + {2133, (400.0/3)*8, (3/0.4)/8, 4, 4, 2, 13, 13, 13, 10, 36, 49, 8, 8, 16, 0, 0, 0, 8320, 6, 7, 26, 7, 0, 512} + } + }, speed_entry; + + int read_latency; + void aldram_timing(Temp current_temperature); +private: + void init_speed(); + void init_lambda(); + void init_prereq(); + void init_rowhit(); // SAUGATA: added function to check for row hits + void init_rowopen(); + void init_timing(SpeedEntry speed_entry); +}; + +} /*namespace ramulator*/ + +#endif /*__ALDRAM_H*/ diff --git a/src/Cache.cpp b/src/Cache.cpp new file mode 100644 index 0000000..c4cd1eb --- /dev/null +++ b/src/Cache.cpp @@ -0,0 +1,418 @@ +#include "Cache.h" + +#ifndef DEBUG_CACHE +#define debug(...) +#else +#define debug(...) do { \ + printf("\033[36m[DEBUG] %s ", __FUNCTION__); \ + printf(__VA_ARGS__); \ + printf("\033[0m\n"); \ + } while (0) +#endif + +namespace ramulator +{ + +Cache::Cache(int size, int assoc, int block_size, + int mshr_entry_num, Level level, + std::shared_ptr cachesys): + level(level), cachesys(cachesys), higher_cache(0), + lower_cache(nullptr), size(size), assoc(assoc), + block_size(block_size), mshr_entry_num(mshr_entry_num) { + + debug("level %d size %d assoc %d block_size %d\n", + int(level), size, assoc, block_size); + + if (level == Level::L1) { + level_string = "L1"; + } else if (level == Level::L2) { + level_string = "L2"; + } else if (level == Level::L3) { + level_string = "L3"; + } + + is_first_level = (level == cachesys->first_level); + is_last_level = (level == cachesys->last_level); + + // Check size, block size and assoc are 2^N + assert((size & (size - 1)) == 0); + assert((block_size & (block_size - 1)) == 0); + assert((assoc & (assoc - 1)) == 0); + assert(size >= block_size); + + // Initialize cache configuration + block_num = size / (block_size * assoc); + index_mask = block_num - 1; + index_offset = calc_log2(block_size); + tag_offset = calc_log2(block_num) + index_offset; + + debug("index_offset %d", index_offset); + debug("index_mask 0x%x", index_mask); + debug("tag_offset %d", tag_offset); + + // regStats + cache_read_miss.name(level_string + string("_cache_read_miss")) + .desc("cache read miss count") + .precision(0) + ; + + cache_write_miss.name(level_string + string("_cache_write_miss")) + .desc("cache write miss count") + .precision(0) + ; + + cache_total_miss.name(level_string + string("_cache_total_miss")) + .desc("cache total miss count") + .precision(0) + ; + + cache_eviction.name(level_string + string("_cache_eviction")) + .desc("number of evict from this level to lower level") + .precision(0) + ; + + cache_read_access.name(level_string + string("_cache_read_access")) + .desc("cache read access count") + .precision(0) + ; + + cache_write_access.name(level_string + string("_cache_write_access")) + .desc("cache write access count") + .precision(0) + ; + + cache_total_access.name(level_string + string("_cache_total_access")) + .desc("cache total access count") + .precision(0) + ; + + cache_mshr_hit.name(level_string + string("_cache_mshr_hit")) + .desc("cache mshr hit count") + .precision(0) + ; + cache_mshr_unavailable.name(level_string + string("_cache_mshr_unavailable")) + .desc("cache mshr not available count") + .precision(0) + ; + cache_set_unavailable.name(level_string + string("_cache_set_unavailable")) + .desc("cache set not available") + .precision(0) + ; +} + +bool Cache::send(Request req) { + debug("level %d req.addr %lx req.type %d, index %d, tag %ld", + int(level), req.addr, int(req.type), get_index(req.addr), + get_tag(req.addr)); + + cache_total_access++; + if (req.type == Request::Type::WRITE) { + cache_write_access++; + } else { + assert(req.type == Request::Type::READ); + cache_read_access++; + } + // If there isn't a set, create it. + auto& lines = get_lines(req.addr); + std::list::iterator line; + + if (is_hit(lines, req.addr, &line)) { + lines.push_back(Line(req.addr, get_tag(req.addr), false, + line->dirty || (req.type == Request::Type::WRITE))); + lines.erase(line); + cachesys->hit_list.push_back( + make_pair(cachesys->clk + latency[int(level)], req)); + + debug("hit, update timestamp %ld", cachesys->clk); + debug("hit finish time %ld", + cachesys->clk + latency[int(level)]); + + return true; + + } else { + debug("miss @level %d", int(level)); + cache_total_miss++; + if (req.type == Request::Type::WRITE) { + cache_write_miss++; + } else { + assert(req.type == Request::Type::READ); + cache_read_miss++; + } + + // The dirty bit will be set if this is a write request and @L1 + bool dirty = (req.type == Request::Type::WRITE); + + // Modify the type of the request to lower level + if (req.type == Request::Type::WRITE) { + req.type = Request::Type::READ; + } + + // Look it up in MSHR entries + assert(req.type == Request::Type::READ); + auto mshr = hit_mshr(req.addr); + if (mshr != mshr_entries.end()) { + debug("hit mshr"); + cache_mshr_hit++; + mshr->second->dirty = dirty || mshr->second->dirty; + return true; + } + + // All requests come to this stage will be READ, so they + // should be recorded in MSHR entries. + if (mshr_entries.size() == mshr_entry_num) { + // When no MSHR entries available, the miss request + // is stalling. + cache_mshr_unavailable++; + debug("no mshr entry available"); + return false; + } + + // Check whether there is a line available + if (all_sets_locked(lines)) { + cache_set_unavailable++; + return false; + } + + auto newline = allocate_line(lines, req.addr); + if (newline == lines.end()) { + return false; + } + + newline->dirty = dirty; + + // Add to MSHR entries + mshr_entries.push_back(make_pair(req.addr, newline)); + + // Send the request to next level; + if (!is_last_level) { + lower_cache->send(req); + } else { + cachesys->wait_list.push_back( + make_pair(cachesys->clk + latency[int(level)], req)); + } + return true; + } +} + +void Cache::evictline(long addr, bool dirty) { + + auto it = cache_lines.find(get_index(addr)); + assert(it != cache_lines.end()); // check inclusive cache + auto& lines = it->second; + auto line = find_if(lines.begin(), lines.end(), + [addr, this](Line l){return (l.tag == get_tag(addr));}); + + assert(line != lines.end()); + // Update LRU queue. The dirty bit will be set if the dirty + // bit inherited from higher level(s) is set. + lines.push_back(Line(addr, get_tag(addr), false, + dirty || line->dirty)); + lines.erase(line); +} + +std::pair Cache::invalidate(long addr) { + long delay = latency_each[int(level)]; + bool dirty = false; + + auto& lines = get_lines(addr); + if (lines.size() == 0) { + // The line of this address doesn't exist. + return make_pair(0, false); + } + auto line = find_if(lines.begin(), lines.end(), + [addr, this](Line l){return (l.tag == get_tag(addr));}); + + // If the line is in this level cache, then erase it from + // the buffer. + if (line != lines.end()) { + assert(!line->lock); + debug("invalidate %lx @ level %d", addr, int(level)); + lines.erase(line); + } else { + // If it's not in current level, then no need to go up. + return make_pair(delay, false); + } + + if (higher_cache.size()) { + long max_delay = delay; + for (auto hc : higher_cache) { + auto result = hc->invalidate(addr); + if (result.second) { + max_delay = max(max_delay, delay + result.first * 2); + } else { + max_delay = max(max_delay, delay + result.first); + } + dirty = dirty || line->dirty || result.second; + } + delay = max_delay; + } else { + dirty = line->dirty; + } + return make_pair(delay, dirty); +} + + +void Cache::evict(std::list* lines, + std::list::iterator victim) { + debug("level %d miss evict victim %lx", int(level), victim->addr); + cache_eviction++; + + long addr = victim->addr; + long invalidate_time = 0; + bool dirty = victim->dirty; + + // First invalidate the victim line in higher level. + if (higher_cache.size()) { + for (auto hc : higher_cache) { + auto result = hc->invalidate(addr); + invalidate_time = max(invalidate_time, + result.first + (result.second ? latency_each[int(level)] : 0)); + dirty = dirty || result.second || victim->dirty; + } + } + + debug("invalidate delay: %ld, dirty: %s", invalidate_time, + dirty ? "true" : "false"); + + if (!is_last_level) { + // not LLC eviction + assert(lower_cache != nullptr); + lower_cache->evictline(addr, dirty); + } else { + // LLC eviction + if (dirty) { + Request write_req(addr, Request::Type::WRITE); + cachesys->wait_list.push_back(make_pair( + cachesys->clk + invalidate_time + latency[int(level)], + write_req)); + + debug("inject one write request to memory system " + "addr %lx, invalidate time %ld, issue time %ld", + write_req.addr, invalidate_time, + cachesys->clk + invalidate_time + latency[int(level)]); + } + } + + lines->erase(victim); +} + +std::list::iterator Cache::allocate_line( + std::list& lines, long addr) { + // See if an eviction is needed + if (need_eviction(lines, addr)) { + // Get victim. + // The first one might still be locked due to reorder in MC + auto victim = find_if(lines.begin(), lines.end(), + [this](Line line) { + bool check = !line.lock; + if (!is_first_level) { + for (auto hc : higher_cache) { + if(!check) { + return check; + } + check = check && hc->check_unlock(line.addr); + } + } + return check; + }); + if (victim == lines.end()) { + return victim; // doesn't exist a line that's already unlocked in each level + } + assert(victim != lines.end()); + evict(&lines, victim); + } + + // Allocate newline, with lock bit on and dirty bit off + lines.push_back(Line(addr, get_tag(addr))); + auto last_element = lines.end(); + --last_element; + return last_element; +} + +bool Cache::is_hit(std::list& lines, long addr, + std::list::iterator* pos_ptr) { + auto pos = find_if(lines.begin(), lines.end(), + [addr, this](Line l){return (l.tag == get_tag(addr));}); + *pos_ptr = pos; + if (pos == lines.end()) { + return false; + } + return !pos->lock; +} + +void Cache::concatlower(Cache* lower) { + lower_cache = lower; + assert(lower != nullptr); + lower->higher_cache.push_back(this); +} + +bool Cache::need_eviction(const std::list& lines, long addr) { + if (find_if(lines.begin(), lines.end(), + [addr, this](Line l){ + return (get_tag(addr) == l.tag);}) + != lines.end()) { + // Due to MSHR, the program can't reach here. Just for checking + assert(false); + } else { + if (lines.size() < assoc) { + return false; + } else { + return true; + } + } +} + +void Cache::callback(Request& req) { + debug("level %d", int(level)); + + auto it = find_if(mshr_entries.begin(), mshr_entries.end(), + [&req, this](std::pair::iterator> mshr_entry) { + return (align(mshr_entry.first) == align(req.addr)); + }); + + if (it != mshr_entries.end()) { + it->second->lock = false; + mshr_entries.erase(it); + } + + if (higher_cache.size()) { + for (auto hc : higher_cache) { + hc->callback(req); + } + } +} + +void CacheSystem::tick() { + debug("clk %ld", clk); + + ++clk; + + // Sends ready waiting request to memory + auto it = wait_list.begin(); + while (it != wait_list.end() && clk >= it->first) { + if (!send_memory(it->second)) { + ++it; + } else { + + debug("complete req: addr %lx", (it->second).addr); + + it = wait_list.erase(it); + } + } + + // hit request callback + it = hit_list.begin(); + while (it != hit_list.end()) { + if (clk >= it->first) { + it->second.callback(it->second); + + debug("finish hit: addr %lx", (it->second).addr); + + it = hit_list.erase(it); + } else { + ++it; + } + } +} + +} // namespace ramulator diff --git a/src/Cache.h b/src/Cache.h new file mode 100644 index 0000000..a48e44c --- /dev/null +++ b/src/Cache.h @@ -0,0 +1,239 @@ +#ifndef __CACHE_H +#define __CACHE_H + +#include "Config.h" +#include "Request.h" +#include "Statistics.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include + +namespace ramulator +{ +class CacheSystem; + +class Cache { +protected: + ScalarStat cache_read_miss; + ScalarStat cache_write_miss; + ScalarStat cache_total_miss; + ScalarStat cache_eviction; + ScalarStat cache_read_access; + ScalarStat cache_write_access; + ScalarStat cache_total_access; + ScalarStat cache_mshr_hit; + ScalarStat cache_mshr_unavailable; + ScalarStat cache_set_unavailable; +public: + enum class Level { + L1, + L2, + L3, + MAX + } level; + std::string level_string; + + struct Line { + long addr; + long tag; + bool lock; // When the lock is on, the value is not valid yet. + bool dirty; + Line(long addr, long tag): + addr(addr), tag(tag), lock(true), dirty(false) {} + Line(long addr, long tag, bool lock, bool dirty): + addr(addr), tag(tag), lock(lock), dirty(dirty) {} + }; + + Cache(int size, int assoc, int block_size, int mshr_entry_num, + Level level, std::shared_ptr cachesys); + + // L1, L2, L3 accumulated latencies + int latency[int(Level::MAX)] = {4, 4 + 12, 4 + 12 + 31}; + int latency_each[int(Level::MAX)] = {4, 12, 31}; + + std::shared_ptr cachesys; + // LLC has multiple higher caches + std::vector higher_cache; + Cache* lower_cache; + + bool send(Request req); + + void concatlower(Cache* lower); + + void callback(Request& req); + +protected: + + bool is_first_level; + bool is_last_level; + size_t size; + unsigned int assoc; + unsigned int block_num; + unsigned int index_mask; + unsigned int block_size; + unsigned int index_offset; + unsigned int tag_offset; + unsigned int mshr_entry_num; + std::vector::iterator>> mshr_entries; + + std::map > cache_lines; + + int calc_log2(int val) { + int n = 0; + while ((val >>= 1)) + n ++; + return n; + } + + int get_index(long addr) { + return (addr >> index_offset) & index_mask; + }; + + long get_tag(long addr) { + return (addr >> tag_offset); + } + + // Align the address to cache line size + long align(long addr) { + return (addr & ~(block_size-1l)); + } + + // Evict the cache line from higher level to this level. + // Pass the dirty bit and update LRU queue. + void evictline(long addr, bool dirty); + + // Invalidate the line from this level to higher levels + // The return value is a pair. The first element is invalidation + // latency, and the second is wether the value has new version + // in higher level and this level. + std::pair invalidate(long addr); + + // Evict the victim from current set of lines. + // First do invalidation, then call evictline(L1 or L2) or send + // a write request to memory(L3) when dirty bit is on. + void evict(std::list* lines, + std::list::iterator victim); + + // First test whether need eviction, if so, do eviction by + // calling evict function. Then allocate a new line and return + // the iterator points to it. + std::list::iterator allocate_line( + std::list& lines, long addr); + + // Check whether the set to hold addr has space or eviction is + // needed. + bool need_eviction(const std::list& lines, long addr); + + // Check whether this addr is hit and fill in the pos_ptr with + // the iterator to the hit line or lines.end() + bool is_hit(std::list& lines, long addr, + std::list::iterator* pos_ptr); + + bool all_sets_locked(const std::list& lines) { + if (lines.size() < assoc) { + return false; + } + for (const auto& line : lines) { + if (!line.lock) { + return false; + } + } + return true; + } + + bool check_unlock(long addr) { + auto it = cache_lines.find(get_index(addr)); + if (it == cache_lines.end()) { + return true; + } else { + auto& lines = it->second; + auto line = find_if(lines.begin(), lines.end(), + [addr, this](Line l){return (l.tag == get_tag(addr));}); + if (line == lines.end()) { + return true; + } else { + bool check = !line->lock; + if (!is_first_level) { + for (auto hc : higher_cache) { + if (!check) { + return check; + } + check = check && hc->check_unlock(line->addr); + } + } + return check; + } + } + } + + std::vector::iterator>>::iterator + hit_mshr(long addr) { + auto mshr_it = + find_if(mshr_entries.begin(), mshr_entries.end(), + [addr, this](std::pair::iterator> + mshr_entry) { + return (align(mshr_entry.first) == align(addr)); + }); + return mshr_it; + } + + std::list& get_lines(long addr) { + if (cache_lines.find(get_index(addr)) + == cache_lines.end()) { + cache_lines.insert(make_pair(get_index(addr), + std::list())); + } + return cache_lines[get_index(addr)]; + } + +}; + +class CacheSystem { +public: + CacheSystem(const Config& configs, std::function send_memory): + send_memory(send_memory) { + if (configs.has_core_caches()) { + first_level = Cache::Level::L1; + } else if (configs.has_l3_cache()) { + first_level = Cache::Level::L3; + } else { + last_level = Cache::Level::MAX; // no cache + } + + if (configs.has_l3_cache()) { + last_level = Cache::Level::L3; + } else if (configs.has_core_caches()) { + last_level = Cache::Level::L2; + } else { + last_level = Cache::Level::MAX; // no cache + } + } + + // wait_list contains miss requests with their latencies in + // cache. When this latency is met, the send_memory function + // will be called to send the request to the memory system. + std::list > wait_list; + + // hit_list contains hit requests with their latencies in cache. + // callback function will be called when this latency is met and + // set the instruction status to ready in processor's window. + std::list > hit_list; + + std::function send_memory; + + long clk = 0; + void tick(); + + Cache::Level first_level; + Cache::Level last_level; +}; + +} // namespace ramulator + +#endif /* __CACHE_H */ diff --git a/src/Config.cpp b/src/Config.cpp new file mode 100644 index 0000000..1c788d4 --- /dev/null +++ b/src/Config.cpp @@ -0,0 +1,64 @@ +#include "Config.h" + +using namespace std; +using namespace ramulator; + +Config::Config(const std::string& fname) { + parse(fname); +} + +void Config::parse(const string& fname) +{ + ifstream file(fname); + assert(file.good() && "Bad config file"); + string line; + while (getline(file, line)) { + char delim[] = " \t="; + vector tokens; + + while (true) { + size_t start = line.find_first_not_of(delim); + if (start == string::npos) + break; + + size_t end = line.find_first_of(delim, start); + if (end == string::npos) { + tokens.push_back(line.substr(start)); + break; + } + + tokens.push_back(line.substr(start, end - start)); + line = line.substr(end); + } + + // empty line + if (!tokens.size()) + continue; + + // comment line + if (tokens[0][0] == '#') + continue; + + // parameter line + assert(tokens.size() == 2 && "Only allow two tokens in one line"); + + options[tokens[0]] = tokens[1]; + + if (tokens[0] == "channels") { + channels = atoi(tokens[1].c_str()); + } else if (tokens[0] == "ranks") { + ranks = atoi(tokens[1].c_str()); + } else if (tokens[0] == "subarrays") { + subarrays = atoi(tokens[1].c_str()); + } else if (tokens[0] == "cpu_tick") { + cpu_tick = atoi(tokens[1].c_str()); + } else if (tokens[0] == "mem_tick") { + mem_tick = atoi(tokens[1].c_str()); + } else if (tokens[0] == "expected_limit_insts") { + expected_limit_insts = atoi(tokens[1].c_str()); + } + } + file.close(); +} + + diff --git a/src/Config.h b/src/Config.h new file mode 100644 index 0000000..4d1193e --- /dev/null +++ b/src/Config.h @@ -0,0 +1,118 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include +#include +#include +#include +#include + +namespace ramulator +{ + +class Config { + +private: + std::map options; + int channels; + int ranks; + int subarrays; + int cpu_tick; + int mem_tick; + int core_num = 0; + long expected_limit_insts = 0; + +public: + Config() {} + Config(const std::string& fname); + void parse(const std::string& fname); + std::string operator [] (const std::string& name) const { + if (options.find(name) != options.end()) { + return (options.find(name))->second; + } else { + return ""; + } + } + + bool contains(const std::string& name) const { + if (options.find(name) != options.end()) { + return true; + } else { + return false; + } + } + + void add (const std::string& name, const std::string& value) { + if (!contains(name)) { + options.insert(make_pair(name, value)); + } else { + printf("ramulator::Config::add options[%s] already set.\n", name.c_str()); + } + } + + void set_core_num(int _core_num) {core_num = _core_num;} + + int get_channels() const {return channels;} + int get_subarrays() const {return subarrays;} + int get_ranks() const {return ranks;} + int get_cpu_tick() const {return cpu_tick;} + int get_mem_tick() const {return mem_tick;} + int get_core_num() const {return core_num;} + long get_expected_limit_insts() const {return expected_limit_insts;} + bool has_l3_cache() const { + if (options.find("cache") != options.end()) { + const std::string& cache_option = (options.find("cache"))->second; + return (cache_option == "all") || (cache_option == "L3"); + } else { + return false; + } + } + bool has_core_caches() const { + if (options.find("cache") != options.end()) { + const std::string& cache_option = (options.find("cache"))->second; + return (cache_option == "all" || cache_option == "L1L2"); + } else { + return false; + } + } + bool is_early_exit() const { + // the default value is true + if (options.find("early_exit") != options.end()) { + if ((options.find("early_exit"))->second == "off") { + return false; + } + return true; + } + return true; + } + bool calc_weighted_speedup() const { + return (expected_limit_insts != 0); + } + bool record_cmd_trace() const { + // the default value is false + if (options.find("record_cmd_trace") != options.end()) { + if ((options.find("record_cmd_trace"))->second == "on") { + return true; + } + return false; + } + return false; + } + bool print_cmd_trace() const { + // the default value is false + if (options.find("print_cmd_trace") != options.end()) { + if ((options.find("print_cmd_trace"))->second == "on") { + return true; + } + return false; + } + return false; + } +}; + + +} /* namespace ramulator */ + +#endif /* _CONFIG_H */ + diff --git a/src/Controller.cpp b/src/Controller.cpp new file mode 100644 index 0000000..db255b2 --- /dev/null +++ b/src/Controller.cpp @@ -0,0 +1,167 @@ +#include "Controller.h" +#include "SALP.h" +#include "ALDRAM.h" +#include "TLDRAM.h" + +using namespace ramulator; + +namespace ramulator +{ + +static vector get_offending_subarray(DRAM* channel, vector & addr_vec){ + int sa_id = 0; + auto rank = channel->children[addr_vec[int(SALP::Level::Rank)]]; + auto bank = rank->children[addr_vec[int(SALP::Level::Bank)]]; + auto sa = bank->children[addr_vec[int(SALP::Level::SubArray)]]; + for (auto sa_other : bank->children) + if (sa != sa_other && sa_other->state == SALP::State::Opened){ + sa_id = sa_other->id; + break; + } + vector offending = addr_vec; + offending[int(SALP::Level::SubArray)] = sa_id; + offending[int(SALP::Level::Row)] = -1; + return offending; +} + + +template <> +vector Controller::get_addr_vec(SALP::Command cmd, list::iterator req){ + if (cmd == SALP::Command::PRE_OTHER) + return get_offending_subarray(channel, req->addr_vec); + else + return req->addr_vec; +} + + +template <> +bool Controller::is_ready(list::iterator req){ + SALP::Command cmd = get_first_cmd(req); + if (cmd == SALP::Command::PRE_OTHER){ + + vector addr_vec = get_offending_subarray(channel, req->addr_vec); + return channel->check(cmd, addr_vec.data(), clk); + } + else return channel->check(cmd, req->addr_vec.data(), clk); +} + +template <> +void Controller::update_temp(ALDRAM::Temp current_temperature){ + channel->spec->aldram_timing(current_temperature); +} + + +template <> +void Controller::tick(){ + clk++; + req_queue_length_sum += readq.size() + writeq.size(); + read_req_queue_length_sum += readq.size(); + write_req_queue_length_sum += writeq.size(); + + /*** 1. Serve completed reads ***/ + if (pending.size()) { + Request& req = pending[0]; + if (req.depart <= clk) { + if (req.depart - req.arrive > 1) { + read_latency_sum += req.depart - req.arrive; + channel->update_serving_requests( + req.addr_vec.data(), -1, clk); + } + req.callback(req); + pending.pop_front(); + } + } + + /*** 2. Should we schedule refreshes? ***/ + refresh->tick_ref(); + + /*** 3. Should we schedule writes? ***/ + if (!write_mode) { + // yes -- write queue is almost full or read queue is empty + if (writeq.size() >= int(0.8 * writeq.max) || readq.size() == 0) + write_mode = true; + } + else { + // no -- write queue is almost empty and read queue is not empty + if (writeq.size() <= int(0.2 * writeq.max) && readq.size() != 0) + write_mode = false; + } + + /*** 4. Find the best command to schedule, if any ***/ + Queue* queue = !write_mode ? &readq : &writeq; + if (otherq.size()) + queue = &otherq; // "other" requests are rare, so we give them precedence over reads/writes + + auto req = scheduler->get_head(queue->q); + if (req == queue->q.end() || !is_ready(req)) { + // we couldn't find a command to schedule -- let's try to be speculative + auto cmd = TLDRAM::Command::PRE; + vector victim = rowpolicy->get_victim(cmd); + if (!victim.empty()){ + issue_cmd(cmd, victim); + } + return; // nothing more to be done this cycle + } + + if (req->is_first_command) { + int coreid = req->coreid; + req->is_first_command = false; + if (req->type == Request::Type::READ || req->type == Request::Type::WRITE) { + channel->update_serving_requests(req->addr_vec.data(), 1, clk); + } + int tx = (channel->spec->prefetch_size * channel->spec->channel_width / 8); + if (req->type == Request::Type::READ) { + if (is_row_hit(req)) { + ++read_row_hits[coreid]; + ++row_hits; + } else if (is_row_open(req)) { + ++read_row_conflicts[coreid]; + ++row_conflicts; + } else { + ++read_row_misses[coreid]; + ++row_misses; + } + read_transaction_bytes += tx; + } else if (req->type == Request::Type::WRITE) { + if (is_row_hit(req)) { + ++write_row_hits[coreid]; + ++row_hits; + } else if (is_row_open(req)) { + ++write_row_conflicts[coreid]; + ++row_conflicts; + } else { + ++write_row_misses[coreid]; + ++row_misses; + } + write_transaction_bytes += tx; + } + } + + /*** 5. Change a read request to a migration request ***/ + if (req->type == Request::Type::READ) { + req->type = Request::Type::EXTENSION; + } + + // issue command on behalf of request + auto cmd = get_first_cmd(req); + issue_cmd(cmd, get_addr_vec(cmd, req)); + + // check whether this is the last command (which finishes the request) + if (cmd != channel->spec->translate[int(req->type)]) + return; + + // set a future completion time for read requests + if (req->type == Request::Type::READ || req->type == Request::Type::EXTENSION) { + req->depart = clk + channel->spec->read_latency; + pending.push_back(*req); + } + if (req->type == Request::Type::WRITE) { + channel->update_serving_requests(req->addr_vec.data(), -1, clk); + req->callback(*req); + } + + // remove request from queue + queue->q.erase(req); +} + +} /* namespace ramulator */ diff --git a/src/Controller.h b/src/Controller.h new file mode 100644 index 0000000..0188614 --- /dev/null +++ b/src/Controller.h @@ -0,0 +1,538 @@ +#ifndef __CONTROLLER_H +#define __CONTROLLER_H + +#include +#include +#include +#include +#include +#include +#include + +#include "Config.h" +#include "DRAM.h" +#include "Refresh.h" +#include "Request.h" +#include "Scheduler.h" +#include "Statistics.h" + +#include "ALDRAM.h" +#include "SALP.h" +#include "TLDRAM.h" + +using namespace std; + +namespace ramulator +{ + +template +class Controller +{ +protected: + // For counting bandwidth + ScalarStat read_transaction_bytes; + ScalarStat write_transaction_bytes; + + ScalarStat row_hits; + ScalarStat row_misses; + ScalarStat row_conflicts; + VectorStat read_row_hits; + VectorStat read_row_misses; + VectorStat read_row_conflicts; + VectorStat write_row_hits; + VectorStat write_row_misses; + VectorStat write_row_conflicts; + + ScalarStat read_latency_avg; + ScalarStat read_latency_sum; + + ScalarStat req_queue_length_avg; + ScalarStat req_queue_length_sum; + ScalarStat read_req_queue_length_avg; + ScalarStat read_req_queue_length_sum; + ScalarStat write_req_queue_length_avg; + ScalarStat write_req_queue_length_sum; + +#ifndef INTEGRATED_WITH_GEM5 + VectorStat record_read_hits; + VectorStat record_read_misses; + VectorStat record_read_conflicts; + VectorStat record_write_hits; + VectorStat record_write_misses; + VectorStat record_write_conflicts; +#endif + +public: + /* Member Variables */ + long clk = 0; + DRAM* channel; + + Scheduler* scheduler; // determines the highest priority request whose commands will be issued + RowPolicy* rowpolicy; // determines the row-policy (e.g., closed-row vs. open-row) + RowTable* rowtable; // tracks metadata about rows (e.g., which are open and for how long) + Refresh* refresh; + + struct Queue { + list q; + unsigned int max = 32; + unsigned int size() {return q.size();} + }; + + Queue readq; // queue for read requests + Queue writeq; // queue for write requests + Queue otherq; // queue for all "other" requests (e.g., refresh) + + deque pending; // read requests that are about to receive data from DRAM + bool write_mode = false; // whether write requests should be prioritized over reads + //long refreshed = 0; // last time refresh requests were generated + + /* Command trace for DRAMPower 3.1 */ + string cmd_trace_prefix = "cmd-trace-"; + vector cmd_trace_files; + bool record_cmd_trace = false; + /* Commands to stdout */ + bool print_cmd_trace = false; + + /* Constructor */ + Controller(const Config& configs, DRAM* channel) : + channel(channel), + scheduler(new Scheduler(this)), + rowpolicy(new RowPolicy(this)), + rowtable(new RowTable(this)), + refresh(new Refresh(this)), + cmd_trace_files(channel->children.size()) + { + record_cmd_trace = configs.record_cmd_trace(); + print_cmd_trace = configs.print_cmd_trace(); + if (record_cmd_trace){ + if (configs["cmd_trace_prefix"] != "") { + cmd_trace_prefix = configs["cmd_trace_prefix"]; + } + string prefix = cmd_trace_prefix + "chan-" + to_string(channel->id) + "-rank-"; + string suffix = ".cmdtrace"; + for (unsigned int i = 0; i < channel->children.size(); i++) + cmd_trace_files[i].open(prefix + to_string(i) + suffix); + } + + // regStats + + row_hits + .name("row_hits_channel_"+to_string(channel->id) + "_core") + .desc("Number of row hits per channel per core") + .precision(0) + ; + row_misses + .name("row_misses_channel_"+to_string(channel->id) + "_core") + .desc("Number of row misses per channel per core") + .precision(0) + ; + row_conflicts + .name("row_conflicts_channel_"+to_string(channel->id) + "_core") + .desc("Number of row conflicts per channel per core") + .precision(0) + ; + + read_row_hits + .init(configs.get_core_num()) + .name("read_row_hits_channel_"+to_string(channel->id) + "_core") + .desc("Number of row hits for read requests per channel per core") + .precision(0) + ; + read_row_misses + .init(configs.get_core_num()) + .name("read_row_misses_channel_"+to_string(channel->id) + "_core") + .desc("Number of row misses for read requests per channel per core") + .precision(0) + ; + read_row_conflicts + .init(configs.get_core_num()) + .name("read_row_conflicts_channel_"+to_string(channel->id) + "_core") + .desc("Number of row conflicts for read requests per channel per core") + .precision(0) + ; + + write_row_hits + .init(configs.get_core_num()) + .name("write_row_hits_channel_"+to_string(channel->id) + "_core") + .desc("Number of row hits for write requests per channel per core") + .precision(0) + ; + write_row_misses + .init(configs.get_core_num()) + .name("write_row_misses_channel_"+to_string(channel->id) + "_core") + .desc("Number of row misses for write requests per channel per core") + .precision(0) + ; + write_row_conflicts + .init(configs.get_core_num()) + .name("write_row_conflicts_channel_"+to_string(channel->id) + "_core") + .desc("Number of row conflicts for write requests per channel per core") + .precision(0) + ; + + read_transaction_bytes + .name("read_transaction_bytes_"+to_string(channel->id)) + .desc("The total byte of read transaction per channel") + .precision(0) + ; + write_transaction_bytes + .name("write_transaction_bytes_"+to_string(channel->id)) + .desc("The total byte of write transaction per channel") + .precision(0) + ; + + read_latency_sum + .name("read_latency_sum_"+to_string(channel->id)) + .desc("The memory latency cycles (in memory time domain) sum for all read requests in this channel") + .precision(0) + ; + read_latency_avg + .name("read_latency_avg_"+to_string(channel->id)) + .desc("The average memory latency cycles (in memory time domain) per request for all read requests in this channel") + .precision(6) + ; + + req_queue_length_sum + .name("req_queue_length_sum_"+to_string(channel->id)) + .desc("Sum of read and write queue length per memory cycle per channel.") + .precision(0) + ; + req_queue_length_avg + .name("req_queue_length_avg_"+to_string(channel->id)) + .desc("Average of read and write queue length per memory cycle per channel.") + .precision(6) + ; + + read_req_queue_length_sum + .name("read_req_queue_length_sum_"+to_string(channel->id)) + .desc("Read queue length sum per memory cycle per channel.") + .precision(0) + ; + read_req_queue_length_avg + .name("read_req_queue_length_avg_"+to_string(channel->id)) + .desc("Read queue length average per memory cycle per channel.") + .precision(6) + ; + + write_req_queue_length_sum + .name("write_req_queue_length_sum_"+to_string(channel->id)) + .desc("Write queue length sum per memory cycle per channel.") + .precision(0) + ; + write_req_queue_length_avg + .name("write_req_queue_length_avg_"+to_string(channel->id)) + .desc("Write queue length average per memory cycle per channel.") + .precision(6) + ; + +#ifndef INTEGRATED_WITH_GEM5 + record_read_hits + .init(configs.get_core_num()) + .name("record_read_hits") + .desc("record read hit count for this core when it reaches request limit or to the end") + ; + + record_read_misses + .init(configs.get_core_num()) + .name("record_read_misses") + .desc("record_read_miss count for this core when it reaches request limit or to the end") + ; + + record_read_conflicts + .init(configs.get_core_num()) + .name("record_read_conflicts") + .desc("record read conflict count for this core when it reaches request limit or to the end") + ; + + record_write_hits + .init(configs.get_core_num()) + .name("record_write_hits") + .desc("record write hit count for this core when it reaches request limit or to the end") + ; + + record_write_misses + .init(configs.get_core_num()) + .name("record_write_misses") + .desc("record write miss count for this core when it reaches request limit or to the end") + ; + + record_write_conflicts + .init(configs.get_core_num()) + .name("record_write_conflicts") + .desc("record write conflict for this core when it reaches request limit or to the end") + ; +#endif + } + + ~Controller(){ + delete scheduler; + delete rowpolicy; + delete rowtable; + delete channel; + delete refresh; + for (auto& file : cmd_trace_files) + file.close(); + cmd_trace_files.clear(); + } + + void finish(long read_req, long dram_cycles) { + read_latency_avg = read_latency_sum.value() / read_req; + req_queue_length_avg = req_queue_length_sum.value() / dram_cycles; + read_req_queue_length_avg = read_req_queue_length_sum.value() / dram_cycles; + write_req_queue_length_avg = write_req_queue_length_sum.value() / dram_cycles; + // call finish function of each channel + channel->finish(dram_cycles); + } + + /* Member Functions */ + Queue& get_queue(Request::Type type) + { + switch (int(type)) { + case int(Request::Type::READ): return readq; + case int(Request::Type::WRITE): return writeq; + default: return otherq; + } + } + + bool enqueue(Request& req) + { + Queue& queue = get_queue(req.type); + if (queue.max == queue.size()) + return false; + + req.arrive = clk; + queue.q.push_back(req); + // shortcut for read requests, if a write to same addr exists + // necessary for coherence + if (req.type == Request::Type::READ && find_if(writeq.q.begin(), writeq.q.end(), + [req](Request& wreq){ return req.addr == wreq.addr;}) != writeq.q.end()){ + req.depart = clk + 1; + pending.push_back(req); + readq.q.pop_back(); + } + return true; + } + + void tick() + { + clk++; + req_queue_length_sum += readq.size() + writeq.size() + pending.size(); + read_req_queue_length_sum += readq.size() + pending.size(); + write_req_queue_length_sum += writeq.size(); + + /*** 1. Serve completed reads ***/ + if (pending.size()) { + Request& req = pending[0]; + if (req.depart <= clk) { + if (req.depart - req.arrive > 1) { // this request really accessed a row + read_latency_sum += req.depart - req.arrive; + channel->update_serving_requests( + req.addr_vec.data(), -1, clk); + } + req.callback(req); + pending.pop_front(); + } + } + + /*** 2. Refresh scheduler ***/ + refresh->tick_ref(); + + /*** 3. Should we schedule writes? ***/ + if (!write_mode) { + // yes -- write queue is almost full or read queue is empty + if (writeq.size() >= int(0.8 * writeq.max) || readq.size() == 0) + write_mode = true; + } + else { + // no -- write queue is almost empty and read queue is not empty + if (writeq.size() <= int(0.2 * writeq.max) && readq.size() != 0) + write_mode = false; + } + + /*** 4. Find the best command to schedule, if any ***/ + Queue* queue = !write_mode ? &readq : &writeq; + if (otherq.size()) + queue = &otherq; // "other" requests are rare, so we give them precedence over reads/writes + + auto req = scheduler->get_head(queue->q); + if (req == queue->q.end() || !is_ready(req)) { + // we couldn't find a command to schedule -- let's try to be speculative + auto cmd = T::Command::PRE; + vector victim = rowpolicy->get_victim(cmd); + if (!victim.empty()){ + issue_cmd(cmd, victim); + } + return; // nothing more to be done this cycle + } + + if (req->is_first_command) { + req->is_first_command = false; + int coreid = req->coreid; + if (req->type == Request::Type::READ || req->type == Request::Type::WRITE) { + channel->update_serving_requests(req->addr_vec.data(), 1, clk); + } + int tx = (channel->spec->prefetch_size * channel->spec->channel_width / 8); + if (req->type == Request::Type::READ) { + if (is_row_hit(req)) { + ++read_row_hits[coreid]; + ++row_hits; + } else if (is_row_open(req)) { + ++read_row_conflicts[coreid]; + ++row_conflicts; + } else { + ++read_row_misses[coreid]; + ++row_misses; + } + read_transaction_bytes += tx; + } else if (req->type == Request::Type::WRITE) { + if (is_row_hit(req)) { + ++write_row_hits[coreid]; + ++row_hits; + } else if (is_row_open(req)) { + ++write_row_conflicts[coreid]; + ++row_conflicts; + } else { + ++write_row_misses[coreid]; + ++row_misses; + } + write_transaction_bytes += tx; + } + } + + // issue command on behalf of request + auto cmd = get_first_cmd(req); + issue_cmd(cmd, get_addr_vec(cmd, req)); + + // check whether this is the last command (which finishes the request) + if (cmd != channel->spec->translate[int(req->type)]) + return; + + // set a future completion time for read requests + if (req->type == Request::Type::READ) { + req->depart = clk + channel->spec->read_latency; + pending.push_back(*req); + } + + if (req->type == Request::Type::WRITE) { + channel->update_serving_requests(req->addr_vec.data(), -1, clk); + } + + // remove request from queue + queue->q.erase(req); + } + + bool is_ready(list::iterator req) + { + typename T::Command cmd = get_first_cmd(req); + return channel->check(cmd, req->addr_vec.data(), clk); + } + + bool is_ready(typename T::Command cmd, const vector& addr_vec) + { + return channel->check(cmd, addr_vec.data(), clk); + } + + bool is_row_hit(list::iterator req) + { + // cmd must be decided by the request type, not the first cmd + typename T::Command cmd = channel->spec->translate[int(req->type)]; + return channel->check_row_hit(cmd, req->addr_vec.data()); + } + + bool is_row_hit(typename T::Command cmd, const vector& addr_vec) + { + return channel->check_row_hit(cmd, addr_vec.data()); + } + + bool is_row_open(list::iterator req) + { + // cmd must be decided by the request type, not the first cmd + typename T::Command cmd = channel->spec->translate[int(req->type)]; + return channel->check_row_open(cmd, req->addr_vec.data()); + } + + bool is_row_open(typename T::Command cmd, const vector& addr_vec) + { + return channel->check_row_open(cmd, addr_vec.data()); + } + + void update_temp(ALDRAM::Temp current_temperature) + { + } + + // For telling whether this channel is busying in processing read or write + bool is_active() { + return (channel->cur_serving_requests > 0); + } + + // For telling whether this channel is under refresh + bool is_refresh() { + return clk <= channel->end_of_refreshing; + } + + void record_core(int coreid) { +#ifndef INTEGRATED_WITH_GEM5 + record_read_hits[coreid] = read_row_hits[coreid]; + record_read_misses[coreid] = read_row_misses[coreid]; + record_read_conflicts[coreid] = read_row_conflicts[coreid]; + record_write_hits[coreid] = write_row_hits[coreid]; + record_write_misses[coreid] = write_row_misses[coreid]; + record_write_conflicts[coreid] = write_row_conflicts[coreid]; +#endif + } + +private: + typename T::Command get_first_cmd(list::iterator req) + { + typename T::Command cmd = channel->spec->translate[int(req->type)]; + return channel->decode(cmd, req->addr_vec.data()); + } + + void issue_cmd(typename T::Command cmd, const vector& addr_vec) + { + assert(is_ready(cmd, addr_vec)); + channel->update(cmd, addr_vec.data(), clk); + rowtable->update(cmd, addr_vec, clk); + if (record_cmd_trace){ + // select rank + auto& file = cmd_trace_files[addr_vec[1]]; + string& cmd_name = channel->spec->command_name[int(cmd)]; + file<spec->standard_name == "DDR4" || channel->spec->standard_name == "GDDR5") + bank_id += addr_vec[int(T::Level::Bank) - 1] * channel->spec->org_entry.count[int(T::Level::Bank)]; + file<<','<spec->command_name[int(cmd)].c_str(), clk); + for (int lev = 0; lev < int(T::Level::MAX); lev++) + printf(" %5d", addr_vec[lev]); + printf("\n"); + } + } + vector get_addr_vec(typename T::Command cmd, list::iterator req){ + return req->addr_vec; + } +}; + +template <> +vector Controller::get_addr_vec( + SALP::Command cmd, list::iterator req); + +template <> +bool Controller::is_ready(list::iterator req); + +template <> +void Controller::update_temp(ALDRAM::Temp current_temperature); + +template <> +void Controller::tick(); + +} /*namespace ramulator*/ + +#endif /*__CONTROLLER_H*/ diff --git a/src/DDR3.cpp b/src/DDR3.cpp new file mode 100644 index 0000000..e0e95b2 --- /dev/null +++ b/src/DDR3.cpp @@ -0,0 +1,356 @@ +#include "DDR3.h" +#include "DRAM.h" +#include +#include +#include + +using namespace std; +using namespace ramulator; + +string DDR3::standard_name = "DDR3"; + +map DDR3::org_map = { + {"DDR3_512Mb_x4", DDR3::Org::DDR3_512Mb_x4}, {"DDR3_512Mb_x8", DDR3::Org::DDR3_512Mb_x8}, {"DDR3_512Mb_x16", DDR3::Org::DDR3_512Mb_x16}, + {"DDR3_1Gb_x4", DDR3::Org::DDR3_1Gb_x4}, {"DDR3_1Gb_x8", DDR3::Org::DDR3_1Gb_x8}, {"DDR3_1Gb_x16", DDR3::Org::DDR3_1Gb_x16}, + {"DDR3_2Gb_x4", DDR3::Org::DDR3_2Gb_x4}, {"DDR3_2Gb_x8", DDR3::Org::DDR3_2Gb_x8}, {"DDR3_2Gb_x16", DDR3::Org::DDR3_2Gb_x16}, + {"DDR3_4Gb_x4", DDR3::Org::DDR3_4Gb_x4}, {"DDR3_4Gb_x8", DDR3::Org::DDR3_4Gb_x8}, {"DDR3_4Gb_x16", DDR3::Org::DDR3_4Gb_x16}, + {"DDR3_8Gb_x4", DDR3::Org::DDR3_8Gb_x4}, {"DDR3_8Gb_x8", DDR3::Org::DDR3_8Gb_x8}, {"DDR3_8Gb_x16", DDR3::Org::DDR3_8Gb_x16}, +}; + +map DDR3::speed_map = { + {"DDR3_800D", DDR3::Speed::DDR3_800D}, {"DDR3_800E", DDR3::Speed::DDR3_800E}, + {"DDR3_1066E", DDR3::Speed::DDR3_1066E}, {"DDR3_1066F", DDR3::Speed::DDR3_1066F}, {"DDR3_1066G", DDR3::Speed::DDR3_1066G}, + {"DDR3_1333G", DDR3::Speed::DDR3_1333G}, {"DDR3_1333H", DDR3::Speed::DDR3_1333H}, + {"DDR3_1600H", DDR3::Speed::DDR3_1600H}, {"DDR3_1600J", DDR3::Speed::DDR3_1600J}, {"DDR3_1600K", DDR3::Speed::DDR3_1600K}, + {"DDR3_1866K", DDR3::Speed::DDR3_1866K}, {"DDR3_1866L", DDR3::Speed::DDR3_1866L}, + {"DDR3_2133L", DDR3::Speed::DDR3_2133L}, {"DDR3_2133M", DDR3::Speed::DDR3_2133M}, +}; + + +DDR3::DDR3(Org org, Speed speed) : + org_entry(org_table[int(org)]), + speed_entry(speed_table[int(speed)]), + read_latency(speed_entry.nCL + speed_entry.nBL) +{ + init_speed(); + init_prereq(); + init_rowhit(); // SAUGATA: added row hit function + init_rowopen(); + init_lambda(); + init_timing(); +} + +DDR3::DDR3(const string& org_str, const string& speed_str) : + DDR3(org_map[org_str], speed_map[speed_str]) +{ +} + +void DDR3::set_channel_number(int channel) { + org_entry.count[int(Level::Channel)] = channel; +} + +void DDR3::set_rank_number(int rank) { + org_entry.count[int(Level::Rank)] = rank; +} + +void DDR3::init_speed() +{ + // nRRD, nFAW + int page = (org_entry.dq * org_entry.count[int(Level::Column)]) >> 13; + switch (speed_entry.rate) { + case 800: speed_entry.nRRD = (page==1) ? 4 : 4; speed_entry.nFAW = (page==1) ? 16 : 20; break; + case 1066: speed_entry.nRRD = (page==1) ? 4 : 6; speed_entry.nFAW = (page==1) ? 20 : 27; break; + case 1333: speed_entry.nRRD = (page==1) ? 4 : 5; speed_entry.nFAW = (page==1) ? 20 : 30; break; + case 1600: speed_entry.nRRD = (page==1) ? 5 : 6; speed_entry.nFAW = (page==1) ? 24 : 32; break; + case 1866: speed_entry.nRRD = (page==1) ? 5 : 6; speed_entry.nFAW = (page==1) ? 26 : 33; break; + case 2133: speed_entry.nRRD = (page==1) ? 5 : 6; speed_entry.nFAW = (page==1) ? 27 : 34; break; + default: assert(false); + } + + // nRFC, nXS + int chip = org_entry.size; + switch (speed_entry.rate) { + case 800: speed_entry.nRFC = (chip==512) ? 36 : (chip==1<<10) ? 44 : (chip==1<<11) ? 64 : (chip==1<<12) ? 104 : 140; break; + case 1066: speed_entry.nRFC = (chip==512) ? 48 : (chip==1<<10) ? 59 : (chip==1<<11) ? 86 : (chip==1<<12) ? 139 : 187; break; + case 1333: speed_entry.nRFC = (chip==512) ? 60 : (chip==1<<10) ? 74 : (chip==1<<11) ? 107 : (chip==1<<12) ? 174 : 234; break; + case 1600: speed_entry.nRFC = (chip==512) ? 72 : (chip==1<<10) ? 88 : (chip==1<<11) ? 128 : (chip==1<<12) ? 208 : 280; break; + case 1866: speed_entry.nRFC = (chip==512) ? 84 : (chip==1<<10) ? 103 : (chip==1<<11) ? 150 : (chip==1<<12) ? 243 : 327; break; + case 2133: speed_entry.nRFC = (chip==512) ? 96 : (chip==1<<10) ? 118 : (chip==1<<11) ? 171 : (chip==1<<12) ? 278 : 374; break; + default: assert(false); + } + switch (speed_entry.rate) { + case 800: speed_entry.nXS = (chip==512) ? 40 : (chip==1<<10) ? 48 : (chip==1<<11) ? 68 : (chip==1<<12) ? 108 : 144; break; + case 1066: speed_entry.nXS = (chip==512) ? 54 : (chip==1<<10) ? 64 : (chip==1<<11) ? 91 : (chip==1<<12) ? 144 : 192; break; + case 1333: speed_entry.nXS = (chip==512) ? 67 : (chip==1<<10) ? 80 : (chip==1<<11) ? 114 : (chip==1<<12) ? 180 : 240; break; + case 1600: speed_entry.nXS = (chip==512) ? 80 : (chip==1<<10) ? 96 : (chip==1<<11) ? 136 : (chip==1<<12) ? 216 : 288; break; + case 1866: speed_entry.nXS = (chip==512) ? 94 : (chip==1<<10) ? 112 : (chip==1<<11) ? 159 : (chip==1<<12) ? 252 : 336; break; + case 2133: speed_entry.nXS = (chip==512) ? 107 : (chip==1<<10) ? 128 : (chip==1<<11) ? 182 : (chip==1<<12) ? 288 : 384; break; + default: assert(false); + } +} + + +void DDR3::init_prereq() +{ + // RD + prereq[int(Level::Rank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::PowerUp): return Command::MAX; + case int(State::ActPowerDown): return Command::PDX; + case int(State::PrePowerDown): return Command::PDX; + case int(State::SelfRefresh): return Command::SRX; + default: assert(false); + }}; + prereq[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::Closed): return Command::ACT; + case int(State::Opened): + if (node->row_state.find(id) != node->row_state.end()) + return cmd; + return Command::PRE; + default: assert(false); + }}; + + // WR + prereq[int(Level::Rank)][int(Command::WR)] = prereq[int(Level::Rank)][int(Command::RD)]; + prereq[int(Level::Bank)][int(Command::WR)] = prereq[int(Level::Bank)][int(Command::RD)]; + + // REF + prereq[int(Level::Rank)][int(Command::REF)] = [] (DRAM* node, Command cmd, int id) { + for (auto bank : node->children) { + if (bank->state == State::Closed) + continue; + return Command::PREA; + } + return Command::REF;}; + + // PD + prereq[int(Level::Rank)][int(Command::PDE)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::PowerUp): return Command::PDE; + case int(State::ActPowerDown): return Command::PDE; + case int(State::PrePowerDown): return Command::PDE; + case int(State::SelfRefresh): return Command::SRX; + default: assert(false); + }}; + + // SR + prereq[int(Level::Rank)][int(Command::SRE)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::PowerUp): return Command::SRE; + case int(State::ActPowerDown): return Command::PDX; + case int(State::PrePowerDown): return Command::PDX; + case int(State::SelfRefresh): return Command::SRE; + default: assert(false); + }}; +} + + +// SAUGATA: added row hit check functions to see if the desired location is currently open +void DDR3::init_rowhit() +{ + // RD + rowhit[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::Closed): return false; + case int(State::Opened): + if (node->row_state.find(id) != node->row_state.end()) + return true; + return false; + default: assert(false); + }}; + + // WR + rowhit[int(Level::Bank)][int(Command::WR)] = rowhit[int(Level::Bank)][int(Command::RD)]; +} + +void DDR3::init_rowopen() +{ + // RD + rowopen[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::Closed): return false; + case int(State::Opened): return true; + default: assert(false); + }}; + + // WR + rowopen[int(Level::Bank)][int(Command::WR)] = rowopen[int(Level::Bank)][int(Command::RD)]; +} + +void DDR3::init_lambda() +{ + lambda[int(Level::Bank)][int(Command::ACT)] = [] (DRAM* node, int id) { + node->state = State::Opened; + node->row_state[id] = State::Opened;}; + lambda[int(Level::Bank)][int(Command::PRE)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + lambda[int(Level::Rank)][int(Command::PREA)] = [] (DRAM* node, int id) { + for (auto bank : node->children) { + bank->state = State::Closed; + bank->row_state.clear();}}; + lambda[int(Level::Rank)][int(Command::REF)] = [] (DRAM* node, int id) {}; + lambda[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, int id) {}; + lambda[int(Level::Bank)][int(Command::WR)] = [] (DRAM* node, int id) {}; + lambda[int(Level::Bank)][int(Command::RDA)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + lambda[int(Level::Bank)][int(Command::WRA)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + lambda[int(Level::Rank)][int(Command::PDE)] = [] (DRAM* node, int id) { + for (auto bank : node->children) { + if (bank->state == State::Closed) + continue; + node->state = State::ActPowerDown; + return; + } + node->state = State::PrePowerDown;}; + lambda[int(Level::Rank)][int(Command::PDX)] = [] (DRAM* node, int id) { + node->state = State::PowerUp;}; + lambda[int(Level::Rank)][int(Command::SRE)] = [] (DRAM* node, int id) { + node->state = State::SelfRefresh;}; + lambda[int(Level::Rank)][int(Command::SRX)] = [] (DRAM* node, int id) { + node->state = State::PowerUp;}; +} + + +void DDR3::init_timing() +{ + SpeedEntry& s = speed_entry; + vector *t; + + /*** Channel ***/ + t = timing[int(Level::Channel)]; + + // CAS <-> CAS + t[int(Command::RD)].push_back({Command::RD, 1, s.nBL}); + t[int(Command::RD)].push_back({Command::RDA, 1, s.nBL}); + t[int(Command::RDA)].push_back({Command::RD, 1, s.nBL}); + t[int(Command::RDA)].push_back({Command::RDA, 1, s.nBL}); + t[int(Command::WR)].push_back({Command::WR, 1, s.nBL}); + t[int(Command::WR)].push_back({Command::WRA, 1, s.nBL}); + t[int(Command::WRA)].push_back({Command::WR, 1, s.nBL}); + t[int(Command::WRA)].push_back({Command::WRA, 1, s.nBL}); + + + /*** Rank ***/ + t = timing[int(Level::Rank)]; + + // CAS <-> CAS + t[int(Command::RD)].push_back({Command::RD, 1, s.nCCD}); + t[int(Command::RD)].push_back({Command::RDA, 1, s.nCCD}); + t[int(Command::RDA)].push_back({Command::RD, 1, s.nCCD}); + t[int(Command::RDA)].push_back({Command::RDA, 1, s.nCCD}); + t[int(Command::WR)].push_back({Command::WR, 1, s.nCCD}); + t[int(Command::WR)].push_back({Command::WRA, 1, s.nCCD}); + t[int(Command::WRA)].push_back({Command::WR, 1, s.nCCD}); + t[int(Command::WRA)].push_back({Command::WRA, 1, s.nCCD}); + t[int(Command::RD)].push_back({Command::WR, 1, s.nCL + s.nCCD + 2 - s.nCWL}); + t[int(Command::RD)].push_back({Command::WRA, 1, s.nCL + s.nCCD + 2 - s.nCWL}); + t[int(Command::RDA)].push_back({Command::WR, 1, s.nCL + s.nCCD + 2 - s.nCWL}); + t[int(Command::RDA)].push_back({Command::WRA, 1, s.nCL + s.nCCD + 2 - s.nCWL}); + t[int(Command::WR)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nWTR}); + t[int(Command::WR)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nWTR}); + t[int(Command::WRA)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nWTR}); + t[int(Command::WRA)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nWTR}); + + // CAS <-> CAS (between sibling ranks) + t[int(Command::RD)].push_back({Command::RD, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RD)].push_back({Command::RDA, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RDA)].push_back({Command::RD, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RDA)].push_back({Command::RDA, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RD)].push_back({Command::WR, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RD)].push_back({Command::WRA, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RDA)].push_back({Command::WR, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RDA)].push_back({Command::WRA, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RD)].push_back({Command::WR, 1, s.nCL + s.nBL + s.nRTRS - s.nCWL, true}); + t[int(Command::RD)].push_back({Command::WRA, 1, s.nCL + s.nBL + s.nRTRS - s.nCWL, true}); + t[int(Command::RDA)].push_back({Command::WR, 1, s.nCL + s.nBL + s.nRTRS - s.nCWL, true}); + t[int(Command::RDA)].push_back({Command::WRA, 1, s.nCL + s.nBL + s.nRTRS - s.nCWL, true}); + t[int(Command::WR)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nRTRS - s.nCL, true}); + t[int(Command::WR)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nRTRS - s.nCL, true}); + t[int(Command::WRA)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nRTRS - s.nCL, true}); + t[int(Command::WRA)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nRTRS - s.nCL, true}); + + t[int(Command::RD)].push_back({Command::PREA, 1, s.nRTP}); + t[int(Command::WR)].push_back({Command::PREA, 1, s.nCWL + s.nBL + s.nWR}); + + // CAS <-> PD + t[int(Command::RD)].push_back({Command::PDE, 1, s.nCL + s.nBL + 1}); + t[int(Command::RDA)].push_back({Command::PDE, 1, s.nCL + s.nBL + 1}); + t[int(Command::WR)].push_back({Command::PDE, 1, s.nCWL + s.nBL + s.nWR}); + t[int(Command::WRA)].push_back({Command::PDE, 1, s.nCWL + s.nBL + s.nWR + 1}); // +1 for pre + t[int(Command::PDX)].push_back({Command::RD, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::RDA, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::WR, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::WRA, 1, s.nXP}); + + // CAS <-> SR: none (all banks have to be precharged) + + // RAS <-> RAS + t[int(Command::ACT)].push_back({Command::ACT, 1, s.nRRD}); + t[int(Command::ACT)].push_back({Command::ACT, 4, s.nFAW}); + t[int(Command::ACT)].push_back({Command::PREA, 1, s.nRAS}); + t[int(Command::PREA)].push_back({Command::ACT, 1, s.nRP}); + + // RAS <-> REF + t[int(Command::PRE)].push_back({Command::REF, 1, s.nRP}); + t[int(Command::PREA)].push_back({Command::REF, 1, s.nRP}); + t[int(Command::REF)].push_back({Command::ACT, 1, s.nRFC}); + + // RAS <-> PD + t[int(Command::ACT)].push_back({Command::PDE, 1, 1}); + t[int(Command::PDX)].push_back({Command::ACT, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::PRE, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::PREA, 1, s.nXP}); + + // RAS <-> SR + t[int(Command::PRE)].push_back({Command::SRE, 1, s.nRP}); + t[int(Command::PREA)].push_back({Command::SRE, 1, s.nRP}); + t[int(Command::SRX)].push_back({Command::ACT, 1, s.nXS}); + + // REF <-> REF + t[int(Command::REF)].push_back({Command::REF, 1, s.nRFC}); + + // REF <-> PD + t[int(Command::REF)].push_back({Command::PDE, 1, 1}); + t[int(Command::PDX)].push_back({Command::REF, 1, s.nXP}); + + // REF <-> SR + t[int(Command::SRX)].push_back({Command::REF, 1, s.nXS}); + + // PD <-> PD + t[int(Command::PDE)].push_back({Command::PDX, 1, s.nPD}); + t[int(Command::PDX)].push_back({Command::PDE, 1, s.nXP}); + + // PD <-> SR + t[int(Command::PDX)].push_back({Command::SRE, 1, s.nXP}); + t[int(Command::SRX)].push_back({Command::PDE, 1, s.nXS}); + + // SR <-> SR + t[int(Command::SRE)].push_back({Command::SRX, 1, s.nCKESR}); + t[int(Command::SRX)].push_back({Command::SRE, 1, s.nXS}); + + + /*** Bank ***/ + t = timing[int(Level::Bank)]; + + // CAS <-> RAS + t[int(Command::ACT)].push_back({Command::RD, 1, s.nRCD}); + t[int(Command::ACT)].push_back({Command::RDA, 1, s.nRCD}); + t[int(Command::ACT)].push_back({Command::WR, 1, s.nRCD}); + t[int(Command::ACT)].push_back({Command::WRA, 1, s.nRCD}); + + t[int(Command::RD)].push_back({Command::PRE, 1, s.nRTP}); + t[int(Command::WR)].push_back({Command::PRE, 1, s.nCWL + s.nBL + s.nWR}); + + t[int(Command::RDA)].push_back({Command::ACT, 1, s.nRTP + s.nRP}); + t[int(Command::WRA)].push_back({Command::ACT, 1, s.nCWL + s.nBL + s.nWR + s.nRP}); + + // RAS <-> RAS + t[int(Command::ACT)].push_back({Command::ACT, 1, s.nRC}); + t[int(Command::ACT)].push_back({Command::PRE, 1, s.nRAS}); + t[int(Command::PRE)].push_back({Command::ACT, 1, s.nRP}); +} diff --git a/src/DDR3.h b/src/DDR3.h new file mode 100644 index 0000000..8aa2a19 --- /dev/null +++ b/src/DDR3.h @@ -0,0 +1,218 @@ +#ifndef __DDR3_H +#define __DDR3_H + +#include "DRAM.h" +#include "Request.h" +#include +#include +#include +#include + +using namespace std; + +namespace ramulator +{ + +class DDR3 +{ +public: + static string standard_name; + enum class Org; + enum class Speed; + DDR3(Org org, Speed speed); + DDR3(const string& org_str, const string& speed_str); + + static map org_map; + static map speed_map; + /*** Level ***/ + enum class Level : int + { + Channel, Rank, Bank, Row, Column, MAX + }; + + /*** Command ***/ + enum class Command : int + { + ACT, PRE, PREA, + RD, WR, RDA, WRA, + REF, PDE, PDX, SRE, SRX, + MAX + }; + + string command_name[int(Command::MAX)] = { + "ACT", "PRE", "PREA", + "RD", "WR", "RDA", "WRA", + "REF", "PDE", "PDX", "SRE", "SRX" + }; + + Level scope[int(Command::MAX)] = { + Level::Row, Level::Bank, Level::Rank, + Level::Column, Level::Column, Level::Column, Level::Column, + Level::Rank, Level::Rank, Level::Rank, Level::Rank, Level::Rank + }; + + bool is_opening(Command cmd) + { + switch(int(cmd)) { + case int(Command::ACT): + return true; + default: + return false; + } + } + + bool is_accessing(Command cmd) + { + switch(int(cmd)) { + case int(Command::RD): + case int(Command::WR): + case int(Command::RDA): + case int(Command::WRA): + return true; + default: + return false; + } + } + + bool is_closing(Command cmd) + { + switch(int(cmd)) { + case int(Command::RDA): + case int(Command::WRA): + case int(Command::PRE): + case int(Command::PREA): + return true; + default: + return false; + } + } + + bool is_refreshing(Command cmd) + { + switch(int(cmd)) { + case int(Command::REF): + return true; + default: + return false; + } + } + + + /* State */ + enum class State : int + { + Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX + } start[int(Level::MAX)] = { + State::MAX, State::PowerUp, State::Closed, State::Closed, State::MAX + }; + + /* Translate */ + Command translate[int(Request::Type::MAX)] = { + Command::RD, Command::WR, + Command::REF, Command::PDE, Command::SRE + }; + + /* Prerequisite */ + function*, Command cmd, int)> prereq[int(Level::MAX)][int(Command::MAX)]; + + // SAUGATA: added function object container for row hit status + /* Row hit */ + function*, Command cmd, int)> rowhit[int(Level::MAX)][int(Command::MAX)]; + function*, Command cmd, int)> rowopen[int(Level::MAX)][int(Command::MAX)]; + + /* Timing */ + struct TimingEntry + { + Command cmd; + int dist; + int val; + bool sibling; + }; + vector timing[int(Level::MAX)][int(Command::MAX)]; + + /* Lambda */ + function*, int)> lambda[int(Level::MAX)][int(Command::MAX)]; + + /* Organization */ + enum class Org : int + { + DDR3_512Mb_x4, DDR3_512Mb_x8, DDR3_512Mb_x16, + DDR3_1Gb_x4, DDR3_1Gb_x8, DDR3_1Gb_x16, + DDR3_2Gb_x4, DDR3_2Gb_x8, DDR3_2Gb_x16, + DDR3_4Gb_x4, DDR3_4Gb_x8, DDR3_4Gb_x16, + DDR3_8Gb_x4, DDR3_8Gb_x8, DDR3_8Gb_x16, + MAX + }; + + struct OrgEntry { + int size; + int dq; + int count[int(Level::MAX)]; + } org_table[int(Org::MAX)] = { + { 512, 4, {0, 0, 8, 1<<13, 1<<11}}, { 512, 8, {0, 0, 8, 1<<13, 1<<10}}, { 512, 16, {0, 0, 8, 1<<12, 1<<10}}, + {1<<10, 4, {0, 0, 8, 1<<14, 1<<11}}, {1<<10, 8, {0, 0, 8, 1<<14, 1<<10}}, {1<<10, 16, {0, 0, 8, 1<<13, 1<<10}}, + {2<<10, 4, {0, 0, 8, 1<<15, 1<<11}}, {2<<10, 8, {0, 0, 8, 1<<15, 1<<10}}, {2<<10, 16, {0, 0, 8, 1<<14, 1<<10}}, + {4<<10, 4, {0, 0, 8, 1<<16, 1<<11}}, {4<<10, 8, {0, 0, 8, 1<<16, 1<<10}}, {4<<10, 16, {0, 0, 8, 1<<15, 1<<10}}, + {8<<10, 4, {0, 0, 8, 1<<16, 1<<12}}, {8<<10, 8, {0, 0, 8, 1<<16, 1<<11}}, {8<<10, 16, {0, 0, 8, 1<<16, 1<<10}} + }, org_entry; + + void set_channel_number(int channel); + void set_rank_number(int rank); + + /* Speed */ + enum class Speed : int + { + DDR3_800D, DDR3_800E, + DDR3_1066E, DDR3_1066F, DDR3_1066G, + DDR3_1333G, DDR3_1333H, + DDR3_1600H, DDR3_1600J, DDR3_1600K, + DDR3_1866K, DDR3_1866L, + DDR3_2133L, DDR3_2133M, + MAX + }; + + int prefetch_size = 8; // 8n prefetch DDR + int channel_width = 64; + + struct SpeedEntry { + int rate; + double freq, tCK; + int nBL, nCCD, nRTRS; + int nCL, nRCD, nRP, nCWL; + int nRAS, nRC; + int nRTP, nWTR, nWR; + int nRRD, nFAW; + int nRFC, nREFI; + int nPD, nXP, nXPDLL; + int nCKESR, nXS, nXSDLL; + } speed_table[int(Speed::MAX)] = { + {800, (400.0/3)*3, (3/0.4)/3, 4, 4, 2, 5, 5, 5, 5, 15, 20, 4, 4, 6, 0, 0, 0, 3120, 3, 3, 10, 4, 0, 512}, + {800, (400.0/3)*3, (3/0.4)/3, 4, 4, 2, 6, 6, 6, 5, 15, 21, 4, 4, 6, 0, 0, 0, 3120, 3, 3, 10, 4, 0, 512}, + {1066, (400.0/3)*4, (3/0.4)/4, 4, 4, 2, 6, 6, 6, 6, 20, 26, 4, 4, 8, 0, 0, 0, 4160, 3, 4, 13, 4, 0, 512}, + {1066, (400.0/3)*4, (3/0.4)/4, 4, 4, 2, 7, 7, 7, 6, 20, 27, 4, 4, 8, 0, 0, 0, 4160, 3, 4, 13, 4, 0, 512}, + {1066, (400.0/3)*4, (3/0.4)/4, 4, 4, 2, 8, 8, 8, 6, 20, 28, 4, 4, 8, 0, 0, 0, 4160, 3, 4, 13, 4, 0, 512}, + {1333, (400.0/3)*5, (3/0.4)/5, 4, 4, 2, 8, 8, 8, 7, 24, 32, 5, 5, 10, 0, 0, 0, 5200, 4, 4, 16, 5, 0, 512}, + {1333, (400.0/3)*5, (3/0.4)/5, 4, 4, 2, 9, 9, 9, 7, 24, 33, 5, 5, 10, 0, 0, 0, 5200, 4, 4, 16, 5, 0, 512}, + {1600, (400.0/3)*6, (3/0.4)/6, 4, 4, 2, 9, 9, 9, 8, 28, 37, 6, 6, 12, 0, 0, 0, 6240, 4, 5, 20, 5, 0, 512}, + {1600, (400.0/3)*6, (3/0.4)/6, 4, 4, 2, 10, 10, 10, 8, 28, 38, 6, 6, 12, 0, 0, 0, 6240, 4, 5, 20, 5, 0, 512}, + {1600, (400.0/3)*6, (3/0.4)/6, 4, 4, 2, 11, 11, 11, 8, 28, 39, 6, 6, 12, 0, 0, 0, 6240, 4, 5, 20, 5, 0, 512}, + {1866, (400.0/3)*7, (3/0.4)/7, 4, 4, 2, 11, 11, 11, 9, 32, 43, 7, 7, 14, 0, 0, 0, 7280, 5, 6, 23, 6, 0, 512}, + {1866, (400.0/3)*7, (3/0.4)/7, 4, 4, 2, 12, 12, 12, 9, 32, 44, 7, 7, 14, 0, 0, 0, 7280, 5, 6, 23, 6, 0, 512}, + {2133, (400.0/3)*8, (3/0.4)/8, 4, 4, 2, 12, 12, 12, 10, 36, 48, 8, 8, 16, 0, 0, 0, 8320, 6, 7, 26, 7, 0, 512}, + {2133, (400.0/3)*8, (3/0.4)/8, 4, 4, 2, 13, 13, 13, 10, 36, 49, 8, 8, 16, 0, 0, 0, 8320, 6, 7, 26, 7, 0, 512} + }, speed_entry; + + int read_latency; + +private: + void init_speed(); + void init_lambda(); + void init_prereq(); + void init_rowhit(); // SAUGATA: added function to check for row hits + void init_rowopen(); + void init_timing(); +}; + +} /*namespace ramulator*/ + +#endif /*__DDR3_H*/ diff --git a/src/DDR4.cpp b/src/DDR4.cpp new file mode 100644 index 0000000..dc4d5dd --- /dev/null +++ b/src/DDR4.cpp @@ -0,0 +1,402 @@ +#include "DDR4.h" +#include "DRAM.h" + +#include +#include +#include + +using namespace std; +using namespace ramulator; + +string DDR4::standard_name = "DDR4"; + +map DDR4::org_map = { + {"DDR4_2Gb_x4", DDR4::Org::DDR4_2Gb_x4}, {"DDR4_2Gb_x8", DDR4::Org::DDR4_2Gb_x8}, {"DDR4_2Gb_x16", DDR4::Org::DDR4_2Gb_x16}, + {"DDR4_4Gb_x4", DDR4::Org::DDR4_4Gb_x4}, {"DDR4_4Gb_x8", DDR4::Org::DDR4_4Gb_x8}, {"DDR4_4Gb_x16", DDR4::Org::DDR4_4Gb_x16}, + {"DDR4_8Gb_x4", DDR4::Org::DDR4_8Gb_x4}, {"DDR4_8Gb_x8", DDR4::Org::DDR4_8Gb_x8}, {"DDR4_8Gb_x16", DDR4::Org::DDR4_8Gb_x16}, +}; + +map DDR4::speed_map = { + {"DDR4_1600K", DDR4::Speed::DDR4_1600K}, {"DDR4_1600L", DDR4::Speed::DDR4_1600L}, + {"DDR4_1866M", DDR4::Speed::DDR4_1866M}, {"DDR4_1866N", DDR4::Speed::DDR4_1866N}, + {"DDR4_2133P", DDR4::Speed::DDR4_2133P}, {"DDR4_2133R", DDR4::Speed::DDR4_2133R}, + {"DDR4_2400R", DDR4::Speed::DDR4_2400R}, {"DDR4_2400U", DDR4::Speed::DDR4_2400U}, +}; + + +DDR4::DDR4(Org org, Speed speed) + : org_entry(org_table[int(org)]), + speed_entry(speed_table[int(speed)]), + read_latency(speed_entry.nCL + speed_entry.nBL) +{ + init_speed(); + init_prereq(); + init_rowhit(); // SAUGATA: added row hit function + init_rowopen(); + init_lambda(); + init_timing(); +} + +DDR4::DDR4(const string& org_str, const string& speed_str) : + DDR4(org_map[org_str], speed_map[speed_str]) +{ +} + +void DDR4::set_channel_number(int channel) { + org_entry.count[int(Level::Channel)] = channel; +} + +void DDR4::set_rank_number(int rank) { + org_entry.count[int(Level::Rank)] = rank; +} + +void DDR4::init_speed() +{ + const static int RRDS_TABLE[2][4] = { + {4, 4, 4, 4}, + {5, 5, 6, 7} + }; + const static int RRDL_TABLE[2][4] = { + {5, 5, 6, 6}, + {6, 6, 7, 8} + }; + const static int FAW_TABLE[3][4] = { + {16, 16, 16, 16}, + {20, 22, 23, 26}, + {28, 28, 32, 36} + }; + const static int RFC_TABLE[int(RefreshMode::MAX)][3][4] = {{ + {128, 150, 171, 192}, + {208, 243, 278, 312}, + {280, 327, 374, 420} + },{ + {88, 103, 118, 132}, + {128, 150, 171, 192}, + {208, 243, 278, 312} + },{ + {72, 84, 96, 108}, + {88, 103, 118, 132}, + {128, 150, 171, 192} + } + }; + const static int REFI_TABLE[4] = { + 6240, 7280, 8320, 9360 + }; + const static int XS_TABLE[3][4] = { + {136, 159, 182, 204}, + {216, 252, 288, 324}, + {288, 336, 384, 432} + }; + + int speed = 0, density = 0; + switch (speed_entry.rate) { + case 1600: speed = 0; break; + case 1866: speed = 1; break; + case 2133: speed = 2; break; + case 2400: speed = 3; break; + default: assert(false); + }; + switch (org_entry.size >> 10){ + case 2: density = 0; break; + case 4: density = 1; break; + case 8: density = 2; break; + default: assert(false); + } + speed_entry.nRRDS = RRDS_TABLE[org_entry.dq == 16? 1: 0][speed]; + speed_entry.nRRDL = RRDL_TABLE[org_entry.dq == 16? 1: 0][speed]; + speed_entry.nFAW = FAW_TABLE[org_entry.dq == 4? 0: org_entry.dq == 8? 1: 2][speed]; + speed_entry.nRFC = RFC_TABLE[(int)refresh_mode][density][speed]; + speed_entry.nREFI = (REFI_TABLE[speed] >> int(refresh_mode)); + speed_entry.nXS = XS_TABLE[density][speed]; +} + + +void DDR4::init_prereq() +{ + // RD + prereq[int(Level::Rank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::PowerUp): return Command::MAX; + case int(State::ActPowerDown): return Command::PDX; + case int(State::PrePowerDown): return Command::PDX; + case int(State::SelfRefresh): return Command::SRX; + default: assert(false); + }}; + prereq[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::Closed): return Command::ACT; + case int(State::Opened): + if (node->row_state.find(id) != node->row_state.end()) + return cmd; + else return Command::PRE; + default: assert(false); + }}; + + // WR + prereq[int(Level::Rank)][int(Command::WR)] = prereq[int(Level::Rank)][int(Command::RD)]; + prereq[int(Level::Bank)][int(Command::WR)] = prereq[int(Level::Bank)][int(Command::RD)]; + + // REF + prereq[int(Level::Rank)][int(Command::REF)] = [] (DRAM* node, Command cmd, int id) { + for (auto bg : node->children) + for (auto bank: bg->children) { + if (bank->state == State::Closed) + continue; + return Command::PREA; + } + return Command::REF;}; + + // PD + prereq[int(Level::Rank)][int(Command::PDE)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::PowerUp): return Command::PDE; + case int(State::ActPowerDown): return Command::PDE; + case int(State::PrePowerDown): return Command::PDE; + case int(State::SelfRefresh): return Command::SRX; + default: assert(false); + }}; + + // SR + prereq[int(Level::Rank)][int(Command::SRE)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::PowerUp): return Command::SRE; + case int(State::ActPowerDown): return Command::PDX; + case int(State::PrePowerDown): return Command::PDX; + case int(State::SelfRefresh): return Command::SRE; + default: assert(false); + }}; +} + +// SAUGATA: added row hit check functions to see if the desired location is currently open +void DDR4::init_rowhit() +{ + // RD + rowhit[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::Closed): return false; + case int(State::Opened): + if (node->row_state.find(id) != node->row_state.end()) + return true; + return false; + default: assert(false); + }}; + + // WR + rowhit[int(Level::Bank)][int(Command::WR)] = rowhit[int(Level::Bank)][int(Command::RD)]; +} + +void DDR4::init_rowopen() +{ + // RD + rowopen[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::Closed): return false; + case int(State::Opened): return true; + default: assert(false); + }}; + + // WR + rowopen[int(Level::Bank)][int(Command::WR)] = rowopen[int(Level::Bank)][int(Command::RD)]; +} + +void DDR4::init_lambda() +{ + lambda[int(Level::Bank)][int(Command::ACT)] = [] (DRAM* node, int id) { + node->state = State::Opened; + node->row_state[id] = State::Opened;}; + lambda[int(Level::Bank)][int(Command::PRE)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + lambda[int(Level::Rank)][int(Command::PREA)] = [] (DRAM* node, int id) { + for (auto bg : node->children) + for (auto bank : bg->children) { + bank->state = State::Closed; + bank->row_state.clear(); + }}; + lambda[int(Level::Rank)][int(Command::REF)] = [] (DRAM* node, int id) {}; + lambda[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, int id) {}; + lambda[int(Level::Bank)][int(Command::WR)] = [] (DRAM* node, int id) {}; + lambda[int(Level::Bank)][int(Command::RDA)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + lambda[int(Level::Bank)][int(Command::WRA)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + lambda[int(Level::Rank)][int(Command::PDE)] = [] (DRAM* node, int id) { + for (auto bg : node->children) + for (auto bank : bg->children) { + if (bank->state == State::Closed) + continue; + node->state = State::ActPowerDown; + return; + } + node->state = State::PrePowerDown;}; + lambda[int(Level::Rank)][int(Command::PDX)] = [] (DRAM* node, int id) { + node->state = State::PowerUp;}; + lambda[int(Level::Rank)][int(Command::SRE)] = [] (DRAM* node, int id) { + node->state = State::SelfRefresh;}; + lambda[int(Level::Rank)][int(Command::SRX)] = [] (DRAM* node, int id) { + node->state = State::PowerUp;}; +} + + +void DDR4::init_timing() +{ + SpeedEntry& s = speed_entry; + vector *t; + + /*** Channel ***/ + t = timing[int(Level::Channel)]; + + // CAS <-> CAS + t[int(Command::RD)].push_back({Command::RD, 1, s.nBL}); + t[int(Command::RD)].push_back({Command::RDA, 1, s.nBL}); + t[int(Command::RDA)].push_back({Command::RD, 1, s.nBL}); + t[int(Command::RDA)].push_back({Command::RDA, 1, s.nBL}); + t[int(Command::WR)].push_back({Command::WR, 1, s.nBL}); + t[int(Command::WR)].push_back({Command::WRA, 1, s.nBL}); + t[int(Command::WRA)].push_back({Command::WR, 1, s.nBL}); + t[int(Command::WRA)].push_back({Command::WRA, 1, s.nBL}); + + + /*** Rank ***/ + t = timing[int(Level::Rank)]; + + // CAS <-> CAS + t[int(Command::RD)].push_back({Command::RD, 1, s.nCCDS}); + t[int(Command::RD)].push_back({Command::RDA, 1, s.nCCDS}); + t[int(Command::RDA)].push_back({Command::RD, 1, s.nCCDS}); + t[int(Command::RDA)].push_back({Command::RDA, 1, s.nCCDS}); + t[int(Command::WR)].push_back({Command::WR, 1, s.nCCDS}); + t[int(Command::WR)].push_back({Command::WRA, 1, s.nCCDS}); + t[int(Command::WRA)].push_back({Command::WR, 1, s.nCCDS}); + t[int(Command::WRA)].push_back({Command::WRA, 1, s.nCCDS}); + t[int(Command::RD)].push_back({Command::WR, 1, s.nCL + s.nCCDS + 2 - s.nCWL}); + t[int(Command::RD)].push_back({Command::WRA, 1, s.nCL + s.nCCDS + 2 - s.nCWL}); + t[int(Command::RDA)].push_back({Command::WR, 1, s.nCL + s.nCCDS + 2 - s.nCWL}); + t[int(Command::RDA)].push_back({Command::WRA, 1, s.nCL + s.nCCDS + 2 - s.nCWL}); + t[int(Command::WR)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nWTRS}); + t[int(Command::WR)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nWTRS}); + t[int(Command::WRA)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nWTRS}); + t[int(Command::WRA)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nWTRS}); + + // CAS <-> CAS (between sibling ranks) + t[int(Command::RD)].push_back({Command::RD, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RD)].push_back({Command::RDA, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RDA)].push_back({Command::RD, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RDA)].push_back({Command::RDA, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RD)].push_back({Command::WR, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RD)].push_back({Command::WRA, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RDA)].push_back({Command::WR, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RDA)].push_back({Command::WRA, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RD)].push_back({Command::WR, 1, s.nCL + s.nBL + s.nRTRS - s.nCWL, true}); + t[int(Command::RD)].push_back({Command::WRA, 1, s.nCL + s.nBL + s.nRTRS - s.nCWL, true}); + t[int(Command::RDA)].push_back({Command::WR, 1, s.nCL + s.nBL + s.nRTRS - s.nCWL, true}); + t[int(Command::RDA)].push_back({Command::WRA, 1, s.nCL + s.nBL + s.nRTRS - s.nCWL, true}); + t[int(Command::WR)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nRTRS - s.nCL, true}); + t[int(Command::WR)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nRTRS - s.nCL, true}); + t[int(Command::WRA)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nRTRS - s.nCL, true}); + t[int(Command::WRA)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nRTRS - s.nCL, true}); + + t[int(Command::RD)].push_back({Command::PREA, 1, s.nRTP}); + t[int(Command::WR)].push_back({Command::PREA, 1, s.nCWL + s.nBL + s.nWR}); + + // CAS <-> PD + t[int(Command::RD)].push_back({Command::PDE, 1, s.nCL + s.nBL + 1}); + t[int(Command::RDA)].push_back({Command::PDE, 1, s.nCL + s.nBL + 1}); + t[int(Command::WR)].push_back({Command::PDE, 1, s.nCWL + s.nBL + s.nWR}); + t[int(Command::WRA)].push_back({Command::PDE, 1, s.nCWL + s.nBL + s.nWR + 1}); // +1 for pre + t[int(Command::PDX)].push_back({Command::RD, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::RDA, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::WR, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::WRA, 1, s.nXP}); + + // CAS <-> SR: none (all banks have to be precharged) + + // RAS <-> RAS + t[int(Command::ACT)].push_back({Command::ACT, 1, s.nRRDS}); + t[int(Command::ACT)].push_back({Command::ACT, 4, s.nFAW}); + t[int(Command::ACT)].push_back({Command::PREA, 1, s.nRAS}); + t[int(Command::PREA)].push_back({Command::ACT, 1, s.nRP}); + + // RAS <-> REF + t[int(Command::PRE)].push_back({Command::REF, 1, s.nRP}); + t[int(Command::PREA)].push_back({Command::REF, 1, s.nRP}); + t[int(Command::REF)].push_back({Command::ACT, 1, s.nRFC}); + + // RAS <-> PD + t[int(Command::ACT)].push_back({Command::PDE, 1, 1}); + t[int(Command::PDX)].push_back({Command::ACT, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::PRE, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::PREA, 1, s.nXP}); + + // RAS <-> SR + t[int(Command::PRE)].push_back({Command::SRE, 1, s.nRP}); + t[int(Command::PREA)].push_back({Command::SRE, 1, s.nRP}); + t[int(Command::SRX)].push_back({Command::ACT, 1, s.nXS}); + + // REF <-> REF + t[int(Command::REF)].push_back({Command::REF, 1, s.nRFC}); + + // REF <-> PD + t[int(Command::REF)].push_back({Command::PDE, 1, 1}); + t[int(Command::PDX)].push_back({Command::REF, 1, s.nXP}); + + // REF <-> SR + t[int(Command::SRX)].push_back({Command::REF, 1, s.nXS}); + + // PD <-> PD + t[int(Command::PDE)].push_back({Command::PDX, 1, s.nPD}); + t[int(Command::PDX)].push_back({Command::PDE, 1, s.nXP}); + + // PD <-> SR + t[int(Command::PDX)].push_back({Command::SRE, 1, s.nXP}); + t[int(Command::SRX)].push_back({Command::PDE, 1, s.nXS}); + + // SR <-> SR + t[int(Command::SRE)].push_back({Command::SRX, 1, s.nCKESR}); + t[int(Command::SRX)].push_back({Command::SRE, 1, s.nXS}); + + /*** Bank Group ***/ + t = timing[int(Level::BankGroup)]; + // CAS <-> CAS + t[int(Command::RD)].push_back({Command::RD, 1, s.nCCDL}); + t[int(Command::RD)].push_back({Command::RDA, 1, s.nCCDL}); + t[int(Command::RDA)].push_back({Command::RD, 1, s.nCCDL}); + t[int(Command::RDA)].push_back({Command::RDA, 1, s.nCCDL}); + t[int(Command::WR)].push_back({Command::WR, 1, s.nCCDL}); + t[int(Command::WR)].push_back({Command::WRA, 1, s.nCCDL}); + t[int(Command::WRA)].push_back({Command::WR, 1, s.nCCDL}); + t[int(Command::WRA)].push_back({Command::WRA, 1, s.nCCDL}); + t[int(Command::WR)].push_back({Command::WR, 1, s.nCCDL}); + t[int(Command::WR)].push_back({Command::WRA, 1, s.nCCDL}); + t[int(Command::WRA)].push_back({Command::WR, 1, s.nCCDL}); + t[int(Command::WRA)].push_back({Command::WRA, 1, s.nCCDL}); + t[int(Command::WR)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nWTRL}); + t[int(Command::WR)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nWTRL}); + t[int(Command::WRA)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nWTRL}); + t[int(Command::WRA)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nWTRL}); + + // RAS <-> RAS + t[int(Command::ACT)].push_back({Command::ACT, 1, s.nRRDL}); + + /*** Bank ***/ + t = timing[int(Level::Bank)]; + + // CAS <-> RAS + t[int(Command::ACT)].push_back({Command::RD, 1, s.nRCD}); + t[int(Command::ACT)].push_back({Command::RDA, 1, s.nRCD}); + t[int(Command::ACT)].push_back({Command::WR, 1, s.nRCD}); + t[int(Command::ACT)].push_back({Command::WRA, 1, s.nRCD}); + + t[int(Command::RD)].push_back({Command::PRE, 1, s.nRTP}); + t[int(Command::WR)].push_back({Command::PRE, 1, s.nCWL + s.nBL + s.nWR}); + + t[int(Command::RDA)].push_back({Command::ACT, 1, s.nRTP + s.nRP}); + t[int(Command::WRA)].push_back({Command::ACT, 1, s.nCWL + s.nBL + s.nWR + s.nRP}); + + // RAS <-> RAS + t[int(Command::ACT)].push_back({Command::ACT, 1, s.nRC}); + t[int(Command::ACT)].push_back({Command::PRE, 1, s.nRAS}); + t[int(Command::PRE)].push_back({Command::ACT, 1, s.nRP}); +} diff --git a/src/DDR4.h b/src/DDR4.h new file mode 100644 index 0000000..64b3a87 --- /dev/null +++ b/src/DDR4.h @@ -0,0 +1,211 @@ +#ifndef __DDR4_H +#define __DDR4_H + +#include "DRAM.h" +#include "Request.h" +#include +#include + +using namespace std; + +namespace ramulator +{ + +class DDR4 +{ +public: + static string standard_name; + enum class Org; + enum class Speed; + DDR4(Org org, Speed speed); + DDR4(const string& org_str, const string& speed_str); + + static map org_map; + static map speed_map; + /* Level */ + enum class Level : int + { + Channel, Rank, BankGroup, Bank, Row, Column, MAX + }; + + /* Command */ + enum class Command : int + { + ACT, PRE, PREA, + RD, WR, RDA, WRA, + REF, PDE, PDX, SRE, SRX, + MAX + }; + + string command_name[int(Command::MAX)] = { + "ACT", "PRE", "PREA", + "RD", "WR", "RDA", "WRA", + "REF", "PDE", "PDX", "SRE", "SRX" + }; + + Level scope[int(Command::MAX)] = { + Level::Row, Level::Bank, Level::Rank, + Level::Column, Level::Column, Level::Column, Level::Column, + Level::Rank, Level::Rank, Level::Rank, Level::Rank, Level::Rank + }; + + bool is_opening(Command cmd) + { + switch(int(cmd)) { + case int(Command::ACT): + return true; + default: + return false; + } + } + + bool is_accessing(Command cmd) + { + switch(int(cmd)) { + case int(Command::RD): + case int(Command::WR): + case int(Command::RDA): + case int(Command::WRA): + return true; + default: + return false; + } + } + + bool is_closing(Command cmd) + { + switch(int(cmd)) { + case int(Command::RDA): + case int(Command::WRA): + case int(Command::PRE): + case int(Command::PREA): + return true; + default: + return false; + } + } + + bool is_refreshing(Command cmd) + { + switch(int(cmd)) { + case int(Command::REF): + return true; + default: + return false; + } + } + + /* State */ + enum class State : int + { + Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX + } start[int(Level::MAX)] = { + State::MAX, State::PowerUp, State::MAX, State::Closed, State::Closed, State::MAX + }; + + /* Translate */ + Command translate[int(Request::Type::MAX)] = { + Command::RD, Command::WR, + Command::REF, Command::PDE, Command::SRE + }; + + /* Prereq */ + function*, Command cmd, int)> prereq[int(Level::MAX)][int(Command::MAX)]; + + // SAUGATA: added function object container for row hit status + /* Row hit */ + function*, Command cmd, int)> rowhit[int(Level::MAX)][int(Command::MAX)]; + function*, Command cmd, int)> rowopen[int(Level::MAX)][int(Command::MAX)]; + + /* Timing */ + struct TimingEntry + { + Command cmd; + int dist; + int val; + bool sibling; + }; + vector timing[int(Level::MAX)][int(Command::MAX)]; + + /* Lambda */ + function*, int)> lambda[int(Level::MAX)][int(Command::MAX)]; + + /* Organization */ + enum class Org : int + { + DDR4_2Gb_x4, DDR4_2Gb_x8, DDR4_2Gb_x16, + DDR4_4Gb_x4, DDR4_4Gb_x8, DDR4_4Gb_x16, + DDR4_8Gb_x4, DDR4_8Gb_x8, DDR4_8Gb_x16, + MAX + }; + + struct OrgEntry { + int size; + int dq; + int count[int(Level::MAX)]; + } org_table[int(Org::MAX)] = { + {2<<10, 4, {0, 0, 4, 4, 1<<15, 1<<10}}, {2<<10, 8, {0, 0, 4, 4, 1<<14, 1<<10}}, {2<<10, 16, {0, 0, 2, 4, 1<<14, 1<<10}}, + {4<<10, 4, {0, 0, 4, 4, 1<<16, 1<<10}}, {4<<10, 8, {0, 0, 4, 4, 1<<15, 1<<10}}, {4<<10, 16, {0, 0, 2, 4, 1<<15, 1<<10}}, + {8<<10, 4, {0, 0, 4, 4, 1<<17, 1<<10}}, {8<<10, 8, {0, 0, 4, 4, 1<<16, 1<<10}}, {8<<10, 16, {0, 0, 2, 4, 1<<16, 1<<10}} + }, org_entry; + + void set_channel_number(int channel); + void set_rank_number(int rank); + + /* Speed */ + enum class Speed : int + { + DDR4_1600K, DDR4_1600L, + DDR4_1866M, DDR4_1866N, + DDR4_2133P, DDR4_2133R, + DDR4_2400R, DDR4_2400U, + MAX + }; + + enum class RefreshMode : int + { + Refresh_1X, + Refresh_2X, + Refresh_4X, + MAX + } refresh_mode = RefreshMode::Refresh_1X; + + int prefetch_size = 8; // 8n prefetch DDR + int channel_width = 64; + + struct SpeedEntry { + int rate; + double freq, tCK; + int nBL, nCCDS, nCCDL, nRTRS; + int nCL, nRCD, nRP, nCWL; + int nRAS, nRC; + int nRTP, nWTRS, nWTRL, nWR; + int nRRDS, nRRDL, nFAW; + int nRFC, nREFI; + int nPD, nXP, nXPDLL; // XPDLL not found in DDR4?? + int nCKESR, nXS, nXSDLL; // nXSDLL TBD (nDLLK), nXS = (tRFC+10ns)/tCK + } speed_table[int(Speed::MAX)] = { + {1600, (400.0/3)*6, (3/0.4)/6, 4, 4, 5, 2, 11, 11, 11, 9, 28, 39, 6, 2, 6, 12, 0, 0, 0, 0, 0, 4, 5, 0, 5, 0, 0}, + {1600, (400.0/3)*6, (3/0.4)/6, 4, 4, 5, 2, 12, 12, 12, 9, 28, 40, 6, 2, 6, 12, 0, 0, 0, 0, 0, 4, 5, 0, 5, 0, 0}, + {1866, (400.0/3)*7, (3/0.4)/7, 4, 4, 5, 2, 13, 13, 13, 10, 32, 45, 7, 3, 7, 14, 0, 0, 0, 0, 0, 5, 6, 0, 6, 0, 0}, + {1866, (400.0/3)*7, (3/0.4)/7, 4, 4, 5, 2, 14, 14, 14, 10, 32, 46, 7, 3, 7, 14, 0, 0, 0, 0, 0, 5, 6, 0, 6, 0, 0}, + {2133, (400.0/3)*8, (3/0.4)/8, 4, 4, 6, 2, 15, 15, 15, 11, 36, 51, 8, 3, 8, 16, 0, 0, 0, 0, 0, 6, 7, 0, 7, 0, 0}, + {2133, (400.0/3)*8, (3/0.4)/8, 4, 4, 6, 2, 16, 16, 16, 11, 36, 52, 8, 3, 8, 16, 0, 0, 0, 0, 0, 6, 7, 0, 7, 0, 0}, + {2400, (400.0/3)*9, (3/0.4)/9, 4, 4, 6, 2, 16, 16, 16, 12, 39, 55, 9, 3, 9, 18, 0, 0, 0, 0, 0, 6, 8, 0, 7, 0, 0}, + {2400, (400.0/3)*9, (3/0.4)/9, 4, 4, 6, 2, 18, 18, 18, 12, 39, 57, 9, 3, 9, 18, 0, 0, 0, 0, 0, 6, 8, 0, 7, 0, 0} + }, speed_entry; + + int read_latency; + +private: + void init_speed(); + void init_lambda(); + void init_prereq(); + void init_rowhit(); // SAUGATA: added function to check for row hits + void init_rowopen(); + void init_timing(); +}; + +} /*namespace ramulator*/ + +#endif /*__DDR4_H*/ diff --git a/src/DRAM.h b/src/DRAM.h new file mode 100644 index 0000000..1456b4b --- /dev/null +++ b/src/DRAM.h @@ -0,0 +1,451 @@ +#ifndef __DRAM_H +#define __DRAM_H + +#include "Statistics.h" +#include +#include +#include +#include +#include +#include +#include +#include + +using namespace std; + +namespace ramulator +{ + +template +class DRAM +{ +public: + ScalarStat active_cycles; + ScalarStat refresh_cycles; + ScalarStat busy_cycles; + ScalarStat active_refresh_overlap_cycles; + + ScalarStat serving_requests; + ScalarStat average_serving_requests; + + // Constructor + DRAM(T* spec, typename T::Level level); + ~DRAM(); + + // Specification (e.g., DDR3) + T* spec; + + // Tree Organization (e.g., Channel->Rank->Bank->Row->Column) + typename T::Level level; + int id; + long size; + DRAM* parent; + vector children; + + // State (e.g., Opened, Closed) + typename T::State state; + + // State of Rows: + // There are too many rows for them to be instantiated individually + // Instead, their bank (or an equivalent entity) tracks their state for them + map row_state; + + // Insert a node as one of my child nodes + void insert(DRAM* child); + + // Decode a command into its "prerequisite" command (if any is needed) + typename T::Command decode(typename T::Command cmd, const int* addr); + + // Check whether a command is ready to be scheduled + bool check(typename T::Command cmd, const int* addr, long clk); + + // Check whether a command is a row hit + bool check_row_hit(typename T::Command cmd, const int* addr); + + // Check whether a row is open + bool check_row_open(typename T::Command cmd, const int* addr); + + // Return the earliest clock when a command is ready to be scheduled + long get_next(typename T::Command cmd, const int* addr); + + // Update the timing/state of the tree, signifying that a command has been issued + void update(typename T::Command cmd, const int* addr, long clk); + // Update statistics: + + // Update the number of requests it serves currently + void update_serving_requests(const int* addr, int delta, long clk); + + // TIANSHI: current serving requests count + int cur_serving_requests = 0; + long begin_of_serving = -1; + long end_of_serving = -1; + long begin_of_cur_reqcnt = -1; + long begin_of_refreshing = -1; + long end_of_refreshing = -1; + std::vector> refresh_intervals; + + // register statistics + void regStats(const std::string& identifier); + + void finish(long dram_cycles); + +private: + // Constructor + DRAM(){} + + // Timing + long cur_clk = 0; + long next[int(T::Command::MAX)]; // the earliest time in the future when a command could be ready + deque prev[int(T::Command::MAX)]; // the most recent history of when commands were issued + + // Lookup table for which commands must be preceded by which other commands (i.e., "prerequisite") + // E.g., a read command to a closed bank must be preceded by an activate command + function*, typename T::Command cmd, int)>* prereq; + + // SAUGATA: added table for row hits + // Lookup table for whether a command is a row hit + // E.g., a read command to a closed bank must be preceded by an activate command + function*, typename T::Command cmd, int)>* rowhit; + function*, typename T::Command cmd, int)>* rowopen; + + // Lookup table between commands and the state transitions they trigger + // E.g., an activate command to a closed bank opens both the bank and the row + function*, int)>* lambda; + + // Lookup table for timing parameters + // E.g., activate->precharge: tRAS@bank, activate->activate: tRC@bank + vector* timing; + + // Helper Functions + void update_state(typename T::Command cmd, const int* addr); + void update_timing(typename T::Command cmd, const int* addr, long clk); +}; /* class DRAM */ + + +// register statistics +template +void DRAM::regStats(const std::string& identifier) { + active_cycles + .name("active_cycles" + identifier + "_" + to_string(id)) + .desc("Total active cycles for level " + identifier + "_" + to_string(id)) + .precision(0) + ; + refresh_cycles + .name("refresh_cycles" + identifier + "_" + to_string(id)) + .desc("(All-bank refresh only, only valid for rank level) The sum of cycles that is under refresh per memory cycle for level " + identifier + "_" + to_string(id)) + .precision(0) + .flags(Stats::nozero) + ; + busy_cycles + .name("busy_cycles" + identifier + "_" + to_string(id)) + .desc("(All-bank refresh only. busy cycles only include refresh time in rank level) The sum of cycles that the DRAM part is active or under refresh for level " + identifier + "_" + to_string(id)) + .precision(0) + ; + active_refresh_overlap_cycles + .name("active_refresh_overlap_cycles" + identifier + "_" + to_string(id)) + .desc("(All-bank refresh only, only valid for rank level) The sum of cycles that are both active and under refresh per memory cycle for level " + identifier + "_" + to_string(id)) + .precision(0) + .flags(Stats::nozero) + ; + serving_requests + .name("serving_requests" + identifier + "_" + to_string(id)) + .desc("The sum of read and write requests that are served in this DRAM element per memory cycle for level " + identifier + "_" + to_string(id)) + .precision(0) + ; + average_serving_requests + .name("average_serving_requests" + identifier + "_" + to_string(id)) + .desc("The average of read and write requests that are served in this DRAM element per memory cycle for level " + identifier + "_" + to_string(id)) + .precision(6) + ; + + if (!children.size()) { + return; + } + + // recursively register children statistics + for (auto child : children) { + child->regStats(identifier + "_" + to_string(id)); + } +} + +template +void DRAM::finish(long dram_cycles) { + // finalize busy cycles + busy_cycles = active_cycles.value() + refresh_cycles.value() - active_refresh_overlap_cycles.value(); + + // finalize average serving requests + average_serving_requests = serving_requests.value() / dram_cycles; + + if (!children.size()) { + return; + } + + for (auto child : children) { + child->finish(dram_cycles); + } +} + +// Constructor +template +DRAM::DRAM(T* spec, typename T::Level level) : + spec(spec), level(level), id(0), parent(NULL) +{ + + state = spec->start[(int)level]; + prereq = spec->prereq[int(level)]; + rowhit = spec->rowhit[int(level)]; + rowopen = spec->rowopen[int(level)]; + lambda = spec->lambda[int(level)]; + timing = spec->timing[int(level)]; + + fill_n(next, int(T::Command::MAX), -1); // initialize future + for (int cmd = 0; cmd < int(T::Command::MAX); cmd++) { + int dist = 0; + for (auto& t : timing[cmd]) + dist = max(dist, t.dist); + + if (dist) + prev[cmd].resize(dist, -1); // initialize history + } + + // try to recursively construct my children + int child_level = int(level) + 1; + if (child_level == int(T::Level::Row)) + return; // stop recursion: rows are not instantiated as nodes + + int child_max = spec->org_entry.count[child_level]; + if (!child_max) + return; // stop recursion: the number of children is unspecified + + // recursively construct my children + for (int i = 0; i < child_max; i++) { + DRAM* child = new DRAM(spec, typename T::Level(child_level)); + child->parent = this; + child->id = i; + children.push_back(child); + } + +} + +template +DRAM::~DRAM() +{ + for (auto child: children) + delete child; +} + +// Insert +template +void DRAM::insert(DRAM* child) +{ + child->parent = this; + child->id = children.size(); + children.push_back(child); +} + +// Decode +template +typename T::Command DRAM::decode(typename T::Command cmd, const int* addr) +{ + int child_id = addr[int(level)+1]; + if (prereq[int(cmd)]) { + typename T::Command prereq_cmd = prereq[int(cmd)](this, cmd, child_id); + if (prereq_cmd != T::Command::MAX) + return prereq_cmd; // stop recursion: there is a prerequisite at this level + } + + if (child_id < 0 || !children.size()) + return cmd; // stop recursion: there were no prequisites at any level + + // recursively decode at my child + return children[child_id]->decode(cmd, addr); +} + + +// Check +template +bool DRAM::check(typename T::Command cmd, const int* addr, long clk) +{ + if (next[int(cmd)] != -1 && clk < next[int(cmd)]) + return false; // stop recursion: the check failed at this level + + int child_id = addr[int(level)+1]; + if (child_id < 0 || level == spec->scope[int(cmd)] || !children.size()) + return true; // stop recursion: the check passed at all levels + + // recursively check my child + return children[child_id]->check(cmd, addr, clk); +} + +// SAUGATA: added function to check whether a command is a row hit +// Check row hits +template +bool DRAM::check_row_hit(typename T::Command cmd, const int* addr) +{ + int child_id = addr[int(level)+1]; + if (rowhit[int(cmd)]) { + return rowhit[int(cmd)](this, cmd, child_id); // stop recursion: there is a row hit at this level + } + + if (child_id < 0 || !children.size()) + return false; // stop recursion: there were no row hits at any level + + // recursively check for row hits at my child + return children[child_id]->check_row_hit(cmd, addr); +} + +template +bool DRAM::check_row_open(typename T::Command cmd, const int* addr) +{ + int child_id = addr[int(level)+1]; + if (rowopen[int(cmd)]) { + return rowopen[int(cmd)](this, cmd, child_id); // stop recursion: there is a row hit at this level + } + + if (child_id < 0 || !children.size()) + return false; // stop recursion: there were no row hits at any level + + // recursively check for row hits at my child + return children[child_id]->check_row_open(cmd, addr); +} + +template +long DRAM::get_next(typename T::Command cmd, const int* addr) +{ + long next_clk = max(cur_clk, next[int(cmd)]); + auto node = this; + for (int l = int(level); l < int(spec->scope[int(cmd)]) && node->children.size() && addr[l + 1] >= 0; l++){ + node = node->children[addr[l + 1]]; + next_clk = max(next_clk, node->next[int(cmd)]); + } + return next_clk; +} + +// Update +template +void DRAM::update(typename T::Command cmd, const int* addr, long clk) +{ + cur_clk = clk; + update_state(cmd, addr); + update_timing(cmd, addr, clk); +} + + +// Update (State) +template +void DRAM::update_state(typename T::Command cmd, const int* addr) +{ + int child_id = addr[int(level)+1]; + if (lambda[int(cmd)]) + lambda[int(cmd)](this, child_id); // update this level + + if (level == spec->scope[int(cmd)] || !children.size()) + return; // stop recursion: updated all levels + + // recursively update my child + children[child_id]->update_state(cmd, addr); +} + + +// Update (Timing) +template +void DRAM::update_timing(typename T::Command cmd, const int* addr, long clk) +{ + // I am not a target node: I am merely one of its siblings + if (id != addr[int(level)]) { + for (auto& t : timing[int(cmd)]) { + if (!t.sibling) + continue; // not an applicable timing parameter + + assert (t.dist == 1); + + long future = clk + t.val; + next[int(t.cmd)] = max(next[int(t.cmd)], future); // update future + } + + return; // stop recursion: only target nodes should be recursed + } + + // I am a target node + if (prev[int(cmd)].size()) { + prev[int(cmd)].pop_back(); // FIXME TIANSHI why pop back? + prev[int(cmd)].push_front(clk); // update history + } + + for (auto& t : timing[int(cmd)]) { + if (t.sibling) + continue; // not an applicable timing parameter + + long past = prev[int(cmd)][t.dist-1]; + if (past < 0) + continue; // not enough history + + long future = past + t.val; + next[int(t.cmd)] = max(next[int(t.cmd)], future); // update future + // TIANSHI: for refresh statistics + if (spec->is_refreshing(cmd) && spec->is_opening(t.cmd)) { + assert(past == clk); + begin_of_refreshing = clk; + end_of_refreshing = max(end_of_refreshing, next[int(t.cmd)]); + refresh_cycles += end_of_refreshing - clk; + if (cur_serving_requests > 0) { + refresh_intervals.push_back(make_pair(begin_of_refreshing, end_of_refreshing)); + } + } + } + + // Some commands have timings that are higher that their scope levels, thus + // we do not stop at the cmd's scope level + if (!children.size()) + return; // stop recursion: updated all levels + + // recursively update *all* of my children + for (auto child : children) + child->update_timing(cmd, addr, clk); + +} + +template +void DRAM::update_serving_requests(const int* addr, int delta, long clk) { + assert(id == addr[int(level)]); + assert(delta == 1 || delta == -1); + // update total serving requests + if (begin_of_cur_reqcnt != -1 && cur_serving_requests > 0) { + serving_requests += (clk - begin_of_cur_reqcnt) * cur_serving_requests; + active_cycles += clk - begin_of_cur_reqcnt; + } + // update begin of current request number + begin_of_cur_reqcnt = clk; + cur_serving_requests += delta; + assert(cur_serving_requests >= 0); + + if (delta == 1 && cur_serving_requests == 1) { + // transform from inactive to active + begin_of_serving = clk; + if (end_of_refreshing > begin_of_serving) { + active_refresh_overlap_cycles += end_of_refreshing - begin_of_serving; + } + } else if (cur_serving_requests == 0) { + // transform from active to inactive + assert(begin_of_serving != -1); + assert(delta == -1); + active_cycles += clk - begin_of_cur_reqcnt; + end_of_serving = clk; + + for (const auto& ref: refresh_intervals) { + active_refresh_overlap_cycles += min(end_of_serving, ref.second) - ref.first; + } + refresh_intervals.clear(); + } + + int child_id = addr[int(level) + 1]; + // We only count the level bank or the level higher than bank + if (child_id < 0 || !children.size() || (int(level) > int(T::Level::Bank)) ) { + return; + } + children[child_id]->update_serving_requests(addr, delta, clk); +} + +} /* namespace ramulator */ + +#endif /* __DRAM_H */ diff --git a/src/DSARP.cpp b/src/DSARP.cpp new file mode 100644 index 0000000..bc395bb --- /dev/null +++ b/src/DSARP.cpp @@ -0,0 +1,525 @@ +/* + * DSARP.cpp + * + * This a re-implementation of the refresh mechanisms proposed in Chang et al., + * "Improving DRAM Performance by Parallelizing Refreshes with Accesses", HPCA + * 2014. + * + * Created on: Mar 16, 2015 + * Author: kevincha + */ + +#include +#include +#include +#include +#include "DSARP.h" +#include "DRAM.h" + +using namespace std; +using namespace ramulator; + +string DSARP::standard_name = "DSARP"; + +map DSARP::org_map = { + {"DSARP_8Gb_x8", DSARP::Org::DSARP_8Gb_x8}, + {"DSARP_16Gb_x9", DSARP::Org::DSARP_16Gb_x8}, + {"DSARP_32Gb_x8", DSARP::Org::DSARP_32Gb_x8}, +}; + +map DSARP::speed_map = { + {"DSARP_1333", DSARP::Speed::DSARP_1333}, +}; + +DSARP::DSARP(Org org, Speed speed, Type type, int n_sa) : + type(type), + org_entry(org_table[int(org)]), + speed_entry(speed_table[int(speed)]), + read_latency(speed_entry.nCL + speed_entry.nBL), + n_sa(n_sa) +{ + init_speed(); + init_prereq(); + init_rowhit(); // SAUGATA: added row hit function + init_rowopen(); + init_lambda(); + init_timing(); + + // All mechanisms are built on top of REFpb, except for REFab + b_ref_rank = false; + switch(int(type)){ + case int(Type::REFAB): + standard_name = "REFAB"; + b_ref_rank = true; + break; + case int(Type::REFPB): standard_name = "REFPB"; break; + case int(Type::DARP): standard_name = "DARP"; break; + case int(Type::SARP): standard_name = "SARP"; break; + case int(Type::DSARP): standard_name = "DSARP"; break; + } + + // Update the SA count (is power of 2, within [1, 128]) and row count + assert(n_sa && n_sa <= 128 && (n_sa & (n_sa-1)) == 0); + org_entry.count[int(Level::SubArray)] = n_sa; + long tmp = long(org_entry.dq) * org_entry.count[int(Level::Bank)] * + n_sa * org_entry.count[int(Level::Column)]; + org_entry.count[int(Level::Row)] = long(org_entry.size) * (1<<20) / tmp; + + // Change the translation for refresh requests + if (!b_ref_rank) + translate[int(Request::Type::REFRESH)] = Command::REFPB; +} + +DSARP::DSARP(const string& org_str, const string& speed_str, Type type, int n_sa) : + DSARP(org_map[org_str], speed_map[speed_str], type, n_sa) {} + +void DSARP::set_channel_number(int channel) { + org_entry.count[int(Level::Channel)] = channel; +} + +void DSARP::set_rank_number(int rank) { + org_entry.count[int(Level::Rank)] = rank; +} + + +void DSARP::init_speed() +{ + /* Numbers are in DRAM cycles */ + + // The numbers for RFCab are extrapolated based on past and current DRAM + // generation since they are not available yet. Details on the extrapolation + // are in the paper. + const static int RFCAB_TABLE[int(Org::MAX)][int(Speed::MAX)] = { + {234}, {354}, {594}, + }; + + // These are extrapolated using the RFCab/REFpb ratio from the LPDDR standard, which is 2.16. + const static int RFCPB_TABLE[int(Org::MAX)][int(Speed::MAX)] = { + {109}, {164}, {275} + }; + + // High temperature mode (32ms retention time) + const static int REFI_TABLE[int(RefreshMode::MAX)][int(Speed::MAX)] = { + {2600}, + }; + + const static int REFIPB_TABLE[int(RefreshMode::MAX)][int(Speed::MAX)] = { + {325}, + }; + + int speed = 0, density = 0; + switch (speed_entry.rate) { + case 1333: speed = 0; break; + default: assert(false); + }; + switch (org_entry.size >> 10){ + case 8: density = 0; break; + case 16: density = 1; break; + case 32: density = 2; break; + default: assert(false && "Unknown density"); + } + + speed_entry.nRFCpb = RFCPB_TABLE[density][speed]; + speed_entry.nRFCab = RFCAB_TABLE[density][speed]; + speed_entry.nREFI = REFI_TABLE[int(refresh_mode)][speed]; + speed_entry.nREFIpb = REFIPB_TABLE[int(refresh_mode)][speed]; +} + +void DSARP::init_prereq() +{ + // RD + prereq[int(Level::Rank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::PowerUp): return Command::MAX; + case int(State::ActPowerDown): return Command::PDX; + case int(State::PrePowerDown): return Command::PDX; + case int(State::SelfRefresh): return Command::SRX; + default: assert(false); + }}; + // Rank transitions to Bank + prereq[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::Closed): return Command::ACT; + case int(State::Opened): + // Really is the subarray state. If the subarray matches, check the row ID + if (node->row_state.find(id) != node->row_state.end()) + return Command::MAX; + return Command::PRE; + default: assert(false); + }}; + // Bank transitions to Subarray + prereq[int(Level::SubArray)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::Closed): return Command::ACT; + case int(State::Opened): + // Actual row state + if (node->row_state.find(id) != node->row_state.end()) + return cmd; + return Command::PRE; + default: assert(false); + }}; + + // WR + prereq[int(Level::Rank)][int(Command::WR)] = prereq[int(Level::Rank)][int(Command::RD)]; + prereq[int(Level::Bank)][int(Command::WR)] = prereq[int(Level::Bank)][int(Command::RD)]; + prereq[int(Level::SubArray)][int(Command::WR)] = prereq[int(Level::SubArray)][int(Command::RD)]; + + // REF -- on all banks + prereq[int(Level::Rank)][int(Command::REF)] = [] (DRAM* node, Command cmd, int id) { + for (auto bank : node->children) { + if (bank->state == State::Closed) + continue; + return Command::PREA; + } + return Command::REF;}; + + // REF -- per bank + prereq[int(Level::Bank)][int(Command::REFPB)] = [] (DRAM* node, Command cmd, int id) { + if (node->state == State::Closed) return Command::REFPB; + else return Command::PRE;}; + + // PD + prereq[int(Level::Rank)][int(Command::PDE)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::PowerUp): return Command::PDE; + case int(State::ActPowerDown): return Command::PDE; + case int(State::PrePowerDown): return Command::PDE; + case int(State::SelfRefresh): return Command::SRX; + default: assert(false); + }}; + + // SR + prereq[int(Level::Rank)][int(Command::SRE)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::PowerUp): return Command::SRE; + case int(State::ActPowerDown): return Command::PDX; + case int(State::PrePowerDown): return Command::PDX; + case int(State::SelfRefresh): return Command::SRE; + default: assert(false); + }}; +} + +// SAUGATA: added row hit check functions to see if the desired location is currently open +void DSARP::init_rowhit() +{ + // RD + rowhit[int(Level::SubArray)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)){ + case int(State::Closed): return false; + case int(State::Opened): + if (node->row_state.find(id) != node->row_state.end()) return true; + else return false; + default: assert(false); + }}; + // WR + rowhit[int(Level::SubArray)][int(Command::WR)] = rowhit[int(Level::SubArray)][int(Command::RD)]; +} + +void DSARP::init_rowopen() +{ + // RD + rowopen[int(Level::SubArray)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)){ + case int(State::Closed): return false; + case int(State::Opened): return true; + default: assert(false); + }}; + // WR + rowopen[int(Level::SubArray)][int(Command::WR)] = rowopen[int(Level::SubArray)][int(Command::RD)]; +} + +void DSARP::init_lambda() +{ + // RANK + lambda[int(Level::Rank)][int(Command::PREA)] = [] (DRAM* node, int id) { + node->row_state.clear(); + for (auto bank : node->children) { + bank->state = State::Closed; + bank->row_state.clear(); + for (auto sa : bank->children){ + sa->state = State::Closed; + sa->row_state.clear();}}}; + lambda[int(Level::Rank)][int(Command::REF)] = [] (DRAM* node, int id) {}; + + // Power down related commands + lambda[int(Level::Rank)][int(Command::PDE)] = [] (DRAM* node, int id) { + for (auto bank : node->children) { + if (bank->state == State::Closed) + continue; + node->state = State::ActPowerDown; + return; + } + node->state = State::PrePowerDown;}; + lambda[int(Level::Rank)][int(Command::PDX)] = [] (DRAM* node, int id) { + node->state = State::PowerUp;}; + lambda[int(Level::Rank)][int(Command::SRE)] = [] (DRAM* node, int id) { + node->state = State::SelfRefresh;}; + lambda[int(Level::Rank)][int(Command::SRX)] = [] (DRAM* node, int id) { + node->state = State::PowerUp;}; + + // Open a row + lambda[int(Level::Bank)][int(Command::ACT)] = [] (DRAM* node, int id) { + node->state = State::Opened; + node->row_state[id] = State::Opened;}; + lambda[int(Level::SubArray)][int(Command::ACT)] = [] (DRAM* node, int id) { + node->state = State::Opened; + node->row_state[id] = State::Opened;}; + + // Close a bank + lambda[int(Level::Bank)][int(Command::PRE)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear(); + for (auto sa : node->children){ + sa->state = State::Closed; + sa->row_state.clear();}}; + + lambda[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, int id) {}; + lambda[int(Level::Bank)][int(Command::WR)] = [] (DRAM* node, int id) {}; + + // Make sure the bank is closed after the column command + lambda[int(Level::Bank)][int(Command::RDA)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + + lambda[int(Level::Bank)][int(Command::WRA)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + + // Nothing much, just make sure the bank is closed + lambda[int(Level::Bank)][int(Command::REFPB)] = [] (DRAM* node, int id) { + assert(node->state == State::Closed); + node->row_state.clear();}; + + // COL + lambda[int(Level::SubArray)][int(Command::RDA)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + lambda[int(Level::SubArray)][int(Command::WRA)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + + // PowerDown -- this has not been tested + lambda[int(Level::Rank)][int(Command::PDE)] = [] (DRAM* node, int id) { + for (auto bank : node->children) + for (auto sa : bank->children) { + if (sa->state == State::Closed) + continue; + node->state = State::ActPowerDown; + return; + } + node->state = State::PrePowerDown;}; +} + +void DSARP::init_timing() +{ + SpeedEntry& s = speed_entry; + vector *t; + + /*** Channel ***/ + t = timing[int(Level::Channel)]; + + // CAS <-> CAS + t[int(Command::RD)].push_back({Command::RD, 1, s.nBL}); + t[int(Command::RD)].push_back({Command::RDA, 1, s.nBL}); + t[int(Command::RDA)].push_back({Command::RD, 1, s.nBL}); + t[int(Command::RDA)].push_back({Command::RDA, 1, s.nBL}); + t[int(Command::WR)].push_back({Command::WR, 1, s.nBL}); + t[int(Command::WR)].push_back({Command::WRA, 1, s.nBL}); + t[int(Command::WRA)].push_back({Command::WR, 1, s.nBL}); + t[int(Command::WRA)].push_back({Command::WRA, 1, s.nBL}); + + /*** Rank ***/ + t = timing[int(Level::Rank)]; + + // CAS <-> CAS + t[int(Command::RD)].push_back({Command::RD, 1, s.nCCD}); + t[int(Command::RD)].push_back({Command::RDA, 1, s.nCCD}); + t[int(Command::RDA)].push_back({Command::RD, 1, s.nCCD}); + t[int(Command::RDA)].push_back({Command::RDA, 1, s.nCCD}); + t[int(Command::WR)].push_back({Command::WR, 1, s.nCCD}); + t[int(Command::WR)].push_back({Command::WRA, 1, s.nCCD}); + t[int(Command::WRA)].push_back({Command::WR, 1, s.nCCD}); + t[int(Command::WRA)].push_back({Command::WRA, 1, s.nCCD}); + + // READ to WRITE + t[int(Command::RD)].push_back({Command::WR, 1, s.nCL + s.nCCD + 2 - s.nCWL}); + t[int(Command::RD)].push_back({Command::WRA, 1, s.nCL + s.nCCD + 2 - s.nCWL}); + t[int(Command::RDA)].push_back({Command::WR, 1, s.nCL + s.nCCD + 2 - s.nCWL}); + t[int(Command::RDA)].push_back({Command::WRA, 1, s.nCL + s.nCCD + 2 - s.nCWL}); + + // WRITE to READ + t[int(Command::WR)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nWTR}); + t[int(Command::WR)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nWTR}); + t[int(Command::WRA)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nWTR}); + t[int(Command::WRA)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nWTR}); + + // CAS <-> CAS (between sibling ranks) + t[int(Command::RD)].push_back({Command::RD, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RD)].push_back({Command::RDA, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RDA)].push_back({Command::RD, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RDA)].push_back({Command::RDA, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RD)].push_back({Command::WR, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RD)].push_back({Command::WRA, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RDA)].push_back({Command::WR, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RDA)].push_back({Command::WRA, 1, s.nBL + s.nRTRS, true}); + + t[int(Command::RD)].push_back({Command::WR, 1, s.nCL + s.nBL + s.nRTRS - s.nCWL, true}); + t[int(Command::RD)].push_back({Command::WRA, 1, s.nCL + s.nBL + s.nRTRS - s.nCWL, true}); + t[int(Command::RDA)].push_back({Command::WR, 1, s.nCL + s.nBL + s.nRTRS - s.nCWL, true}); + t[int(Command::RDA)].push_back({Command::WRA, 1, s.nCL + s.nBL + s.nRTRS - s.nCWL, true}); + t[int(Command::WR)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nRTRS - s.nCL, true}); + t[int(Command::WR)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nRTRS - s.nCL, true}); + t[int(Command::WRA)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nRTRS - s.nCL, true}); + t[int(Command::WRA)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nRTRS - s.nCL, true}); + + // CAS <-> PREA + t[int(Command::RD)].push_back({Command::PREA, 1, s.nRTP}); + t[int(Command::WR)].push_back({Command::PREA, 1, s.nCWL + s.nBL + s.nWR}); + + // CAS <-> PD + t[int(Command::RD)].push_back({Command::PDE, 1, s.nCL + s.nBL + 1}); + t[int(Command::RDA)].push_back({Command::PDE, 1, s.nCL + s.nBL + 1}); + t[int(Command::WR)].push_back({Command::PDE, 1, s.nCWL + s.nBL + s.nWR}); + t[int(Command::WRA)].push_back({Command::PDE, 1, s.nCWL + s.nBL + s.nWR + 1}); // +1 for pre + t[int(Command::PDX)].push_back({Command::RD, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::RDA, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::WR, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::WRA, 1, s.nXP}); + + // RAS <-> RAS + t[int(Command::ACT)].push_back({Command::ACT, 1, s.nRRD}); + t[int(Command::ACT)].push_back({Command::ACT, 4, s.nFAW}); + t[int(Command::ACT)].push_back({Command::PREA, 1, s.nRAS}); + t[int(Command::PREA)].push_back({Command::ACT, 1, s.nRPab}); + + // RAS <-> REF + t[int(Command::PRE)].push_back({Command::REF, 1, s.nRPpb}); + t[int(Command::PREA)].push_back({Command::REF, 1, s.nRPab}); + t[int(Command::REF)].push_back({Command::ACT, 1, s.nRFCab}); + + // RAS <-> PD + t[int(Command::ACT)].push_back({Command::PDE, 1, 1}); + t[int(Command::PDX)].push_back({Command::ACT, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::PRE, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::PREA, 1, s.nXP}); + + // RAS <-> SR + t[int(Command::PRE)].push_back({Command::SRE, 1, s.nRPpb}); + t[int(Command::PREA)].push_back({Command::SRE, 1, s.nRPab}); + t[int(Command::SRX)].push_back({Command::ACT, 1, s.nXS}); + + // REF <-> REF + t[int(Command::REF)].push_back({Command::REF, 1, s.nRFCab}); + t[int(Command::REF)].push_back({Command::REFPB, 1, s.nRFCab}); + t[int(Command::REFPB)].push_back({Command::REF, 1, s.nRFCpb}); + + // REF <-> PD + t[int(Command::REF)].push_back({Command::PDE, 1, 1}); + t[int(Command::REFPB)].push_back({Command::PDE, 1, 1}); + t[int(Command::PDX)].push_back({Command::REF, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::REFPB, 1, s.nXP}); + + // REF <-> SR + t[int(Command::SRX)].push_back({Command::REF, 1, s.nXS}); + t[int(Command::SRX)].push_back({Command::REFPB, 1, s.nXS}); + + // PD <-> PD + t[int(Command::PDE)].push_back({Command::PDX, 1, s.nPD}); + t[int(Command::PDX)].push_back({Command::PDE, 1, s.nXP}); + + // PD <-> SR + t[int(Command::PDX)].push_back({Command::SRE, 1, s.nXP}); + t[int(Command::SRX)].push_back({Command::PDE, 1, s.nXS}); + + // SR <-> SR + t[int(Command::SRE)].push_back({Command::SRX, 1, s.nCKESR}); + t[int(Command::SRX)].push_back({Command::SRE, 1, s.nXS}); + + // REFPB + t[int(Command::REFPB)].push_back( { Command::REFPB, 1, s.nRFCpb }); + + /*** Bank ***/ + t = timing[int(Level::Bank)]; + + // CAS <-> RAS + t[int(Command::ACT)].push_back({Command::RD, 1, s.nRCD}); + t[int(Command::ACT)].push_back({Command::RDA, 1, s.nRCD}); + t[int(Command::ACT)].push_back({Command::WR, 1, s.nRCD}); + t[int(Command::ACT)].push_back({Command::WRA, 1, s.nRCD}); + + t[int(Command::RD)].push_back({Command::PRE, 1, s.nRTP}); + t[int(Command::WR)].push_back({Command::PRE, 1, s.nCWL + s.nBL + s.nWR}); + + t[int(Command::RDA)].push_back({Command::ACT, 1, s.nRTP + s.nRPpb}); + t[int(Command::WRA)].push_back({Command::ACT, 1, s.nCWL + s.nBL + s.nWR + s.nRPpb}); + + // RAS <-> RAS + t[int(Command::ACT)].push_back({Command::ACT, 1, s.nRC}); + t[int(Command::ACT)].push_back({Command::PRE, 1, s.nRAS}); + t[int(Command::PRE)].push_back({Command::ACT, 1, s.nRPpb}); + t[int(Command::PRE)].push_back({Command::REFPB, 1, s.nRPpb}); + + // Cannot overlap REFPB + t[int(Command::REFPB)].push_back( { Command::REFPB, 1, s.nRFCpb }); + + // B/w banks + t[int(Command::REFPB)].push_back( { Command::REFPB, 1, s.nRFCpb, true}); + t[int(Command::ACT)].push_back({Command::REFPB, 1, s.nRRD, true}); + t[int(Command::REFPB)].push_back({Command::ACT, 1, s.nRRD, true}); + + // REFPB -- these are used when SARP is not enabled + if (!(type == Type::DSARP || type == Type::SARP)) { + t[int(Command::REFPB)].push_back( { Command::ACT, 1, s.nRFCpb }); + t[int(Command::REFPB)].push_back( { Command::RD, 1, s.nRFCpb }); + t[int(Command::REFPB)].push_back( { Command::RDA, 1, s.nRFCpb }); + t[int(Command::REFPB)].push_back( { Command::WR, 1, s.nRFCpb }); + t[int(Command::REFPB)].push_back( { Command::WRA, 1, s.nRFCpb }); + t[int(Command::REFPB)].push_back( { Command::PRE, 1, s.nRFCpb }); + t[int(Command::REFPB)].push_back( { Command::PREA, 1, s.nRFCpb }); + } + + /*** SubArray ***/ + if (type == Type::DSARP || type == Type::SARP) { + t = timing[int(Level::SubArray)]; + + // between different subarrays -> Increase RRD + t[int(Command::ACT)].push_back({Command::REFPB, 1, + (int)ceil(((double)s.nRRD)*nRRD_factor), true}); + t[int(Command::REFPB)].push_back({Command::ACT, 1, + (int)ceil(((double)s.nRRD)*nRRD_factor), true}); + + // Same subarray + t[int(Command::REF)].push_back( { Command::ACT, 1, s.nRFCab }); + t[int(Command::REFPB)].push_back( { Command::ACT, 1, s.nRFCpb }); + + // CAS <-> RAS + t[int(Command::ACT)].push_back( { Command::RD, 1, s.nRCD }); + t[int(Command::ACT)].push_back( { Command::RDA, 1, s.nRCD }); + t[int(Command::ACT)].push_back( { Command::WR, 1, s.nRCD }); + t[int(Command::ACT)].push_back( { Command::WRA, 1, s.nRCD }); + + t[int(Command::RD)].push_back( { Command::PRE, 1, s.nRTP }); + t[int(Command::WR)].push_back( + { Command::PRE, 1, s.nCWL + s.nBL + s.nWR }); + + t[int(Command::RDA)].push_back( { Command::ACT, 1, s.nRTP + s.nRPpb }); + t[int(Command::WRA)].push_back( + { Command::ACT, 1, s.nCWL + s.nBL + s.nWR + s.nRPpb }); + + // RAS <-> RAS + t[int(Command::ACT)].push_back( { Command::ACT, 1, s.nRC }); + t[int(Command::ACT)].push_back( { Command::PRE, 1, s.nRAS }); + t[int(Command::PRE)].push_back( { Command::ACT, 1, s.nRPpb }); + t[int(Command::PRE)].push_back( { Command::REFPB, 1, s.nRPpb }); + t[int(Command::PRE)].push_back( { Command::REF, 1, s.nRPpb }); + + // Enforcing timings such that there's no subarray parallelism + // between sibling subarrays for demand requests + t[int(Command::ACT)].push_back( { Command::ACT, 1, s.nRC, true }); + t[int(Command::PRE)].push_back( { Command::ACT, 1, s.nRPpb, true }); + t[int(Command::RDA)].push_back( { Command::ACT, 1, s.nRTP + s.nRPpb, + true }); + t[int(Command::WRA)].push_back( + { Command::ACT, 1, s.nCWL + s.nBL + s.nWR + s.nRPpb, true }); + } +} diff --git a/src/DSARP.h b/src/DSARP.h new file mode 100644 index 0000000..be92950 --- /dev/null +++ b/src/DSARP.h @@ -0,0 +1,271 @@ +/* + * DSARP.h + * + * This a re-implementation of the refresh mechanisms proposed in Chang et al., + * "Improving DRAM Performance by Parallelizing Refreshes with Accesses", HPCA + * 2014. + * + * Note: the re-implementation of DSARP has not been widely tested across + * different benchmarks and parameters. However, timing violations of + * SARP/DSARP have been checked. + * + * Usage: The "type" determines the refresh mechanisms. + * Examples: + * DSARP::Org test_org = DSARP::Org::DSARP_8Gb_x8; + * + * DSARP* dsddr3_ab = new DSARP(test_org, + * DSARP::Speed::DSARP_1333, DSARP::Type::REFAB, 8); + * + * DSARP* dsddr3_pb = new DSARP(test_org, + * DSARP::Speed::DSARP_1333, DSARP::Type::REFPB, 8); + * + * DSARP* dsddr3_darp = new DSARP(test_org, + * DSARP::Speed::DSARP_1333, DSARP::Type::DARP, 8); + * + * DSARP* dsddr3_sarp = new DSARP(test_org, + * DSARP::Speed::DSARP_1333, DSARP::Type::SARP, 8); + * + * DSARP* dsddr3_dsarp = new DSARP(test_org, + * DSARP::Speed::DSARP_1333, DSARP::Type::DSARP, 8); + * + * Created on: Mar 16, 2015 + * Author: kevincha + */ + +#ifndef DSARP_H_ +#define DSARP_H_ + +#include +#include +#include "DRAM.h" +#include "Request.h" + +using namespace std; + +namespace ramulator +{ + +class DSARP +{ +public: + static string standard_name; + enum class Org; + enum class Speed; + enum class Type; + DSARP(Org org, Speed speed, Type type, int n_sa); + DSARP(const string& org_str, const string& speed_str, Type type, int n_sa); + + static map org_map; + static map speed_map; + + enum class Type : int + { + REFAB, REFPB, DARP, SARP, DSARP, MAX + } type; + + /* Level */ + // NOTE: Although there's subarray, there's no SALP at all. This is used + // for parallelizing REF and demand accesses. + enum class Level : int + { + Channel, Rank, Bank, SubArray, Row, Column, MAX + }; + + /* Command */ + enum class Command : int + { + ACT, PRE, PREA, + RD, WR, RDA, WRA, + REF, REFPB, PDE, PDX, SRE, SRX, + MAX + }; + + string command_name[int(Command::MAX)] = { + "ACT", "PRE", "PREA", + "RD", "WR", "RDA", "WRA", + "REF", "REFPB", + "PDE", "PDX", "SRE", "SRX" + }; + + // SubArray scope for REFPB to propagate the timings + Level scope[int(Command::MAX)] = { + Level::Row, Level::Bank, Level::Rank, + Level::Column, Level::Column, Level::Column, Level::Column, + Level::Rank, Level::Bank, + Level::Rank, Level::Rank, Level::Rank, Level::Rank + }; + + bool is_opening(Command cmd) + { + switch(int(cmd)) { + case int(Command::ACT): + return true; + default: + return false; + } + } + + bool is_accessing(Command cmd) + { + switch(int(cmd)) { + case int(Command::RD): + case int(Command::WR): + case int(Command::RDA): + case int(Command::WRA): + return true; + default: + return false; + } + } + + bool is_closing(Command cmd) + { + switch(int(cmd)) { + case int(Command::RDA): + case int(Command::WRA): + case int(Command::PRE): + case int(Command::PREA): + return true; + default: + return false; + } + } + + bool is_refreshing(Command cmd) + { + switch(int(cmd)) { + case int(Command::REF): + case int(Command::REFPB): + return true; + default: + return false; + } + } + + /* State */ + enum class State : int + { + Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX + } start[int(Level::MAX)] = { + State::MAX, State::PowerUp, State::Closed, State::Closed, State::MAX + }; + + /* Translate */ + Command translate[int(Request::Type::MAX)] = { + Command::RD, Command::WR, + Command::REF, Command::PDE, Command::SRE + }; + + /* Prerequisite */ + function*, Command cmd, int)> prereq[int(Level::MAX)][int(Command::MAX)]; + + // SAUGATA: added function object container for row hit status + /* Row hit */ + function*, Command cmd, int)> rowhit[int(Level::MAX)][int(Command::MAX)]; + function*, Command cmd, int)> rowopen[int(Level::MAX)][int(Command::MAX)]; + + /* Timing */ + struct TimingEntry + { + Command cmd; + int dist; + int val; + bool sibling; + }; + vector timing[int(Level::MAX)][int(Command::MAX)]; + + /* Lambda */ + function*, int)> lambda[int(Level::MAX)][int(Command::MAX)]; + + /* Organization */ + enum class Org : int + { + // These are the configurations used in the original paper, essentially DDR3 + DSARP_8Gb_x8, + DSARP_16Gb_x8, + DSARP_32Gb_x8, + MAX + }; + + struct OrgEntry { + int size; + int dq; + int count[int(Level::MAX)]; + } org_table[int(Org::MAX)] = { + // IMPORTANT: Do not change the count for channel/rank, where is set to + // 0 now. 0 means that this a flexible configuration that is not part + // of the spec, but rather something to change at a higher level + // (main.cpp). + {8<<10, 8, {0, 0, 8, 0, 1<<16, 1<<11}}, + {16<<10, 8, {0, 0, 8, 0, 1<<17, 1<<11}}, + {32<<10, 8, {0, 0, 8, 0, 1<<18, 1<<11}}, + }, org_entry; + + void set_channel_number(int channel); + void set_rank_number(int rank); + + /* Speed */ + enum class Speed : int + { + DSARP_1333, + MAX + }; + + enum class RefreshMode : int + { + Refresh_1X, + MAX + } refresh_mode = RefreshMode::Refresh_1X; + + int prefetch_size = 16; // 16n prefetch DDR + int channel_width = 32; + + struct SpeedEntry { + int rate; + double freq, tCK; + int nBL, nCCD, nRTRS; + int nCL, nRCD, nRPpb, nRPab, nCWL; + int nRAS, nRC; + int nRTP, nWTR, nWR; + int nRRD, nFAW; + int nRFCab, nRFCpb, nREFI, nREFIpb; + int nPD, nXP, nXPDLL; + int nCKESR, nXS, nXSDLL; + //int nCKE, nXP; // CKE value n/a + //int nSR, nXSR; // tXSR = tRFCab + 7.5ns + } speed_table[int(Speed::MAX)] = { + {1333, + (400.0/3)*5, (3/0.4)/5, + 4, 4, 2, + 9, 9, 8, 9, 7, + 24, 33, + 5, 5, 10, + 5, 30, + 0, 0, 0, 0, // set in DSARP.cpp + 4, 4, 16, + 5, 114, 512}, + }, speed_entry; + + int read_latency; + + // Number of subarrays -- mainly for SARP. Doesn't affect others. + int n_sa; + + // Refresh rank? + bool b_ref_rank; + + // Increase RRD b/w REF and ACT when they go to the same bank (SARP) + double nRRD_factor = 1.138; + +private: + void init_speed(); + void init_lambda(); + void init_prereq(); + void init_rowhit(); // SAUGATA: added function to check for row hits + void init_rowopen(); + void init_timing(); +}; + +} /*namespace ramulator*/ + +#endif /* DSARP_H_ */ diff --git a/src/GDDR5.cpp b/src/GDDR5.cpp new file mode 100644 index 0000000..8162574 --- /dev/null +++ b/src/GDDR5.cpp @@ -0,0 +1,355 @@ +#include "GDDR5.h" +#include "DRAM.h" +#include +#include +#include + +using namespace std; +using namespace ramulator; + +string GDDR5::standard_name = "GDDR5"; + +map GDDR5::org_map = { + {"GDDR5_512Mb_x16", GDDR5::Org::GDDR5_512Mb_x16}, {"GDDR5_512Mb_x32", GDDR5::Org::GDDR5_512Mb_x32}, + {"GDDR5_1Gb_x16", GDDR5::Org::GDDR5_1Gb_x16}, {"GDDR5_1Gb_x32", GDDR5::Org::GDDR5_1Gb_x32}, + {"GDDR5_2Gb_x16", GDDR5::Org::GDDR5_2Gb_x16}, {"GDDR5_2Gb_x32", GDDR5::Org::GDDR5_2Gb_x32}, + {"GDDR5_4Gb_x16", GDDR5::Org::GDDR5_4Gb_x16}, {"GDDR5_4Gb_x32", GDDR5::Org::GDDR5_4Gb_x32}, + {"GDDR5_8Gb_x16", GDDR5::Org::GDDR5_8Gb_x16}, {"GDDR5_8Gb_x32", GDDR5::Org::GDDR5_8Gb_x32}, +}; + +map GDDR5::speed_map = { + {"GDDR5_4000", GDDR5::Speed::GDDR5_4000}, {"GDDR5_4500", GDDR5::Speed::GDDR5_4500}, + {"GDDR5_5000", GDDR5::Speed::GDDR5_5000}, {"GDDR5_5500", GDDR5::Speed::GDDR5_5500}, + {"GDDR5_6000", GDDR5::Speed::GDDR5_6000}, {"GDDR5_6500", GDDR5::Speed::GDDR5_6500}, + {"GDDR5_7000", GDDR5::Speed::GDDR5_7000}, +}; + +GDDR5::GDDR5(Org org, Speed speed) : + org_entry(org_table[int(org)]), + speed_entry(speed_table[int(speed)]), + read_latency(speed_entry.nCL + speed_entry.nBL) +{ + init_speed(); + init_prereq(); + init_rowhit(); // SAUGATA: added row hit function + init_rowopen(); + init_lambda(); + init_timing(); +} + +GDDR5::GDDR5(const string& org_str, const string& speed_str) : + GDDR5(org_map[org_str], speed_map[speed_str]) +{ +} + +void GDDR5::set_channel_number(int channel) { + org_entry.count[int(Level::Channel)] = channel; +} + +void GDDR5::set_rank_number(int rank) { + assert((rank == 1) && "GDDR5 rank number is fixed to 1."); +} + +void GDDR5::init_speed() +{ + const int REFIL_TABLE[int(Speed::MAX)] = {3900, 4388, 4875, 5363, 5850, 6338, 6825}; + const int REFIS_TABLE[int(Speed::MAX)] = {1900, 2138, 2375, 2613, 2850, 3088, 3325}; + const int RFC_TABLE[5][int(Speed::MAX)] = { + // using DDR3 values + {90, 102, 113, 124, 135, 147, 158}, + {110, 124, 138, 152, 165, 179, 193}, + {160, 180, 200, 220, 240, 260, 280}, + {260, 293, 325, 358, 390, 423, 455}, + {350, 394, 438, 482, 525, 569, 613} + }; + int speed = 0, density = 0; + switch (speed_entry.rate){ + case 4000: speed = 0; break; + case 4500: speed = 1; break; + case 5000: speed = 2; break; + case 5500: speed = 3; break; + case 6000: speed = 4; break; + case 6500: speed = 5; break; + case 7000: speed = 6; break; + default: assert(0); + } + switch (org_entry.size >> 9){ + case 1: density = 0; break; + case 2: density = 1; break; + case 4: density = 2; break; + case 8: density = 3; break; + case 16: density = 4; break; + default: assert(0); + } + if (org_entry.size <= 1024) speed_entry.nREFI = REFIL_TABLE[speed]; + else speed_entry.nREFI = REFIS_TABLE[speed]; + speed_entry.nRFC = RFC_TABLE[density][speed]; +} + + +void GDDR5::init_prereq() +{ + // RD + prereq[int(Level::Rank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::PowerUp): return Command::MAX; + case int(State::ActPowerDown): return Command::PDX; + case int(State::PrePowerDown): return Command::PDX; + case int(State::SelfRefresh): return Command::SRX; + default: assert(false); + }}; + prereq[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::Closed): return Command::ACT; + case int(State::Opened): + if (node->row_state.find(id) != node->row_state.end()) + return cmd; + return Command::PRE; + default: assert(false); + }}; + + // WR + prereq[int(Level::Rank)][int(Command::WR)] = prereq[int(Level::Rank)][int(Command::RD)]; + prereq[int(Level::Bank)][int(Command::WR)] = prereq[int(Level::Bank)][int(Command::RD)]; + + // REF + prereq[int(Level::Rank)][int(Command::REF)] = [] (DRAM* node, Command cmd, int id) { + for (auto bg : node->children) + for (auto bank : bg->children) { + if (bank->state == State::Closed) + continue; + return Command::PREA; + } + return Command::REF;}; + + // PD + prereq[int(Level::Rank)][int(Command::PDE)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::PowerUp): return Command::PDE; + case int(State::ActPowerDown): return Command::PDE; + case int(State::PrePowerDown): return Command::PDE; + case int(State::SelfRefresh): return Command::SRX; + default: assert(false); + }}; + + // SR + prereq[int(Level::Rank)][int(Command::SRE)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::PowerUp): return Command::SRE; + case int(State::ActPowerDown): return Command::PDX; + case int(State::PrePowerDown): return Command::PDX; + case int(State::SelfRefresh): return Command::SRE; + default: assert(false); + }}; +} + +// SAUGATA: added row hit check functions to see if the desired location is currently open +void GDDR5::init_rowhit() +{ + // RD + rowhit[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::Closed): return false; + case int(State::Opened): + if (node->row_state.find(id) != node->row_state.end()) + return true; + return false; + default: assert(false); + }}; + + // WR + rowhit[int(Level::Bank)][int(Command::WR)] = rowhit[int(Level::Bank)][int(Command::RD)]; +} + +void GDDR5::init_rowopen() +{ + // RD + rowopen[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::Closed): return false; + case int(State::Opened): return true; + default: assert(false); + }}; + + // WR + rowopen[int(Level::Bank)][int(Command::WR)] = rowopen[int(Level::Bank)][int(Command::RD)]; +} + +void GDDR5::init_lambda() +{ + lambda[int(Level::Bank)][int(Command::ACT)] = [] (DRAM* node, int id) { + node->state = State::Opened; + node->row_state[id] = State::Opened;}; + lambda[int(Level::Bank)][int(Command::PRE)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + lambda[int(Level::Rank)][int(Command::PREA)] = [] (DRAM* node, int id) { + for (auto bg : node->children) + for (auto bank : bg->children) { + bank->state = State::Closed; + bank->row_state.clear();}}; + lambda[int(Level::Rank)][int(Command::REF)] = [] (DRAM* node, int id) {}; + lambda[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, int id) {}; + lambda[int(Level::Bank)][int(Command::WR)] = [] (DRAM* node, int id) {}; + lambda[int(Level::Bank)][int(Command::RDA)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + lambda[int(Level::Bank)][int(Command::WRA)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + lambda[int(Level::Rank)][int(Command::PDE)] = [] (DRAM* node, int id) { + for (auto bg : node->children) + for (auto bank : bg->children) { + if (bank->state == State::Closed) + continue; + node->state = State::ActPowerDown; + return; + } + node->state = State::PrePowerDown;}; + lambda[int(Level::Rank)][int(Command::PDX)] = [] (DRAM* node, int id) { + node->state = State::PowerUp;}; + lambda[int(Level::Rank)][int(Command::SRE)] = [] (DRAM* node, int id) { + node->state = State::SelfRefresh;}; + lambda[int(Level::Rank)][int(Command::SRX)] = [] (DRAM* node, int id) { + node->state = State::PowerUp;}; +} + + +void GDDR5::init_timing() +{ + SpeedEntry& s = speed_entry; + vector *t; + + /*** Channel ***/ + t = timing[int(Level::Channel)]; + + // CAS <-> CAS + t[int(Command::RD)].push_back({Command::RD, 1, s.nBL}); + t[int(Command::RD)].push_back({Command::RDA, 1, s.nBL}); + t[int(Command::RDA)].push_back({Command::RD, 1, s.nBL}); + t[int(Command::RDA)].push_back({Command::RDA, 1, s.nBL}); + t[int(Command::WR)].push_back({Command::WR, 1, s.nBL}); + t[int(Command::WR)].push_back({Command::WRA, 1, s.nBL}); + t[int(Command::WRA)].push_back({Command::WR, 1, s.nBL}); + t[int(Command::WRA)].push_back({Command::WRA, 1, s.nBL}); + + + /*** Rank ***/ + t = timing[int(Level::Rank)]; + + // CAS <-> CAS + t[int(Command::RD)].push_back({Command::RD, 1, s.nCCDS}); + t[int(Command::RD)].push_back({Command::RDA, 1, s.nCCDS}); + t[int(Command::RDA)].push_back({Command::RD, 1, s.nCCDS}); + t[int(Command::RDA)].push_back({Command::RDA, 1, s.nCCDS}); + t[int(Command::WR)].push_back({Command::WR, 1, s.nCCDS}); + t[int(Command::WR)].push_back({Command::WRA, 1, s.nCCDS}); + t[int(Command::WRA)].push_back({Command::WR, 1, s.nCCDS}); + t[int(Command::WRA)].push_back({Command::WRA, 1, s.nCCDS}); + t[int(Command::RD)].push_back({Command::WR, 1, s.nCL + s.nCCDS + 2 - s.nCWL}); + t[int(Command::RD)].push_back({Command::WRA, 1, s.nCL + s.nCCDS + 2 - s.nCWL}); + t[int(Command::RDA)].push_back({Command::WR, 1, s.nCL + s.nCCDS + 2 - s.nCWL}); + t[int(Command::RDA)].push_back({Command::WRA, 1, s.nCL + s.nCCDS + 2 - s.nCWL}); + t[int(Command::WR)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nWTR}); + t[int(Command::WR)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nWTR}); + t[int(Command::WRA)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nWTR}); + t[int(Command::WRA)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nWTR}); + + t[int(Command::RD)].push_back({Command::PREA, 1, s.nRTP}); + t[int(Command::WR)].push_back({Command::PREA, 1, s.nCWL + s.nBL + s.nWR}); + + // CAS <-> PD + t[int(Command::RD)].push_back({Command::PDE, 1, s.nCL + s.nBL + 1}); + t[int(Command::RDA)].push_back({Command::PDE, 1, s.nCL + s.nBL + 1}); + t[int(Command::WR)].push_back({Command::PDE, 1, s.nCWL + s.nBL + s.nWR}); + t[int(Command::WRA)].push_back({Command::PDE, 1, s.nCWL + s.nBL + s.nWR + 1}); // +1 for pre + t[int(Command::PDX)].push_back({Command::RD, 1, s.nXPN}); + t[int(Command::PDX)].push_back({Command::RDA, 1, s.nXPN}); + t[int(Command::PDX)].push_back({Command::WR, 1, s.nXPN}); + t[int(Command::PDX)].push_back({Command::WRA, 1, s.nXPN}); + + // CAS <-> SR: none (all banks have to be precharged) + + // RAS <-> RAS + t[int(Command::ACT)].push_back({Command::ACT, 1, s.nRRD}); + t[int(Command::ACT)].push_back({Command::ACT, 4, s.nFAW}); + t[int(Command::ACT)].push_back({Command::ACT, 32, s.n32AW}); + t[int(Command::ACT)].push_back({Command::PREA, 1, s.nRAS}); + t[int(Command::PREA)].push_back({Command::ACT, 1, s.nRP}); + t[int(Command::PRE)].push_back({Command::PRE, 1, s.nPPD}); + + // RAS <-> REF + t[int(Command::PRE)].push_back({Command::REF, 1, s.nRP}); + t[int(Command::PREA)].push_back({Command::REF, 1, s.nRP}); + t[int(Command::REF)].push_back({Command::ACT, 1, s.nRFC}); + + // RAS <-> PD + t[int(Command::ACT)].push_back({Command::PDE, 1, 1}); + t[int(Command::PDX)].push_back({Command::ACT, 1, s.nXPN}); + t[int(Command::PDX)].push_back({Command::PRE, 1, s.nXPN}); + t[int(Command::PDX)].push_back({Command::PREA, 1, s.nXPN}); + + // RAS <-> SR + t[int(Command::PRE)].push_back({Command::SRE, 1, s.nRP}); + t[int(Command::PREA)].push_back({Command::SRE, 1, s.nRP}); + t[int(Command::SRX)].push_back({Command::ACT, 1, s.nXS}); + + // REF <-> REF + t[int(Command::REF)].push_back({Command::REF, 1, s.nRFC}); + + // REF <-> PD + t[int(Command::REF)].push_back({Command::PDE, 1, 1}); + t[int(Command::PDX)].push_back({Command::REF, 1, s.nXPN}); + + // REF <-> SR + t[int(Command::SRX)].push_back({Command::REF, 1, s.nXS}); + + // PD <-> PD + t[int(Command::PDE)].push_back({Command::PDX, 1, s.nPD}); + t[int(Command::PDX)].push_back({Command::PDE, 1, s.nXPN}); + + // PD <-> SR + t[int(Command::PDX)].push_back({Command::SRE, 1, s.nXPN}); + t[int(Command::SRX)].push_back({Command::PDE, 1, s.nXS}); + + // SR <-> SR + t[int(Command::SRE)].push_back({Command::SRX, 1, s.nCKESR}); + t[int(Command::SRX)].push_back({Command::SRE, 1, s.nXS}); + + + // Bank group level + t = timing[int(Level::BankGroup)]; + // CAS <-> CAS + t[int(Command::RD)].push_back({Command::RD, 1, s.nCCDL}); + t[int(Command::RD)].push_back({Command::RDA, 1, s.nCCDL}); + t[int(Command::RDA)].push_back({Command::RD, 1, s.nCCDL}); + t[int(Command::RDA)].push_back({Command::RDA, 1, s.nCCDL}); + t[int(Command::WR)].push_back({Command::WR, 1, s.nCCDL}); + t[int(Command::WR)].push_back({Command::WRA, 1, s.nCCDL}); + t[int(Command::WRA)].push_back({Command::WR, 1, s.nCCDL}); + t[int(Command::WRA)].push_back({Command::WRA, 1, s.nCCDL}); + t[int(Command::WR)].push_back({Command::WR, 1, s.nCCDL}); + t[int(Command::WR)].push_back({Command::WRA, 1, s.nCCDL}); + t[int(Command::WRA)].push_back({Command::WR, 1, s.nCCDL}); + t[int(Command::WRA)].push_back({Command::WRA, 1, s.nCCDL}); + + /*** Bank ***/ + t = timing[int(Level::Bank)]; + + // CAS <-> RAS + t[int(Command::ACT)].push_back({Command::RD, 1, s.nRCDR}); + t[int(Command::ACT)].push_back({Command::RDA, 1, s.nRCDR}); + t[int(Command::ACT)].push_back({Command::WR, 1, s.nRCDW}); + t[int(Command::ACT)].push_back({Command::WRA, 1, s.nRCDW}); + + t[int(Command::RD)].push_back({Command::PRE, 1, s.nRTP}); + t[int(Command::WR)].push_back({Command::PRE, 1, s.nCWL + s.nBL + s.nWR}); + + t[int(Command::RDA)].push_back({Command::ACT, 1, s.nRTP + s.nRP}); + t[int(Command::WRA)].push_back({Command::ACT, 1, s.nCWL + s.nBL + s.nWR + s.nRP}); + + // RAS <-> RAS + t[int(Command::ACT)].push_back({Command::ACT, 1, s.nRC}); + t[int(Command::ACT)].push_back({Command::PRE, 1, s.nRAS}); + t[int(Command::PRE)].push_back({Command::ACT, 1, s.nRP}); +} diff --git a/src/GDDR5.h b/src/GDDR5.h new file mode 100644 index 0000000..5cc79de --- /dev/null +++ b/src/GDDR5.h @@ -0,0 +1,211 @@ +#ifndef __GDDR5_H +#define __GDDR5_H + +#include "DRAM.h" +#include "Request.h" +#include +#include + +using namespace std; + +namespace ramulator +{ + +class GDDR5 +{ +public: + static string standard_name; + enum class Org; + enum class Speed; + GDDR5(Org org, Speed speed); + GDDR5(const string& org_str, const string& speed_str); + + static map org_map; + static map speed_map; + + /*** Level ***/ + enum class Level : int + { + Channel, Rank, BankGroup, Bank, Row, Column, MAX + }; + + /*** Command ***/ + enum class Command : int + { + ACT, PRE, PREA, + RD, WR, RDA, WRA, + REF, PDE, PDX, SRE, SRX, + MAX + }; + + string command_name[int(Command::MAX)] = { + "ACT", "PRE", "PREA", + "RD", "WR", "RDA", "WRA", + "REF", "PDE", "PDX", "SRE", "SRX" + }; + + Level scope[int(Command::MAX)] = { + Level::Row, Level::Bank, Level::Rank, + Level::Column, Level::Column, Level::Column, Level::Column, + Level::Rank, Level::Rank, Level::Rank, Level::Rank, Level::Rank + }; + + bool is_opening(Command cmd) + { + switch(int(cmd)) { + case int(Command::ACT): + return true; + default: + return false; + } + } + + bool is_accessing(Command cmd) + { + switch(int(cmd)) { + case int(Command::RD): + case int(Command::WR): + case int(Command::RDA): + case int(Command::WRA): + return true; + default: + return false; + } + } + + bool is_closing(Command cmd) + { + switch(int(cmd)) { + case int(Command::RDA): + case int(Command::WRA): + case int(Command::PRE): + case int(Command::PREA): + return true; + default: + return false; + } + } + + bool is_refreshing(Command cmd) + { + switch(int(cmd)) { + case int(Command::REF): + return true; + default: + return false; + } + } + + + /* State */ + enum class State : int + { + Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX + } start[int(Level::MAX)] = { + State::MAX, State::PowerUp, State::MAX, State::Closed, State::Closed, State::MAX + }; + + /* Translate */ + Command translate[int(Request::Type::MAX)] = { + Command::RD, Command::WR, + Command::REF, Command::PDE, Command::SRE + }; + + /* Prerequisite */ + function*, Command cmd, int)> prereq[int(Level::MAX)][int(Command::MAX)]; + + // SAUGATA: added function object container for row hit status + /* Row hit */ + function*, Command cmd, int)> rowhit[int(Level::MAX)][int(Command::MAX)]; + function*, Command cmd, int)> rowopen[int(Level::MAX)][int(Command::MAX)]; + + /* Timing */ + struct TimingEntry + { + Command cmd; + int dist; + int val; + bool sibling; + }; + vector timing[int(Level::MAX)][int(Command::MAX)]; + + /* Lambda */ + function*, int)> lambda[int(Level::MAX)][int(Command::MAX)]; + + /* Organization */ + enum class Org : int + { + GDDR5_512Mb_x16, GDDR5_512Mb_x32, + GDDR5_1Gb_x16, GDDR5_1Gb_x32, + GDDR5_2Gb_x16, GDDR5_2Gb_x32, + GDDR5_4Gb_x16, GDDR5_4Gb_x32, + GDDR5_8Gb_x16, GDDR5_8Gb_x32, + MAX + }; + + struct OrgEntry { + int size; + int dq; + int count[int(Level::MAX)]; + } org_table[int(Org::MAX)] = { + // fixed to have 1 rank + // in GDDR5 the column address is unique for a burst. e.g. 64 column addresses correspond with + // 256 column addresses actually. So we multiply 8 to the original address bit number in JEDEC standard + { 512, 16, {0, 1, 4, 2, 1<<12, 1<<(7+3)}}, { 512, 32, {0, 1, 4, 2, 1<<12, 1<<(6+3)}}, + {1<<10, 16, {0, 1, 4, 4, 1<<12, 1<<(7+3)}}, {1<<10, 32, {0, 1, 4, 4, 1<<12, 1<<(6+3)}}, + {2<<10, 16, {0, 1, 4, 4, 1<<13, 1<<(7+3)}}, {2<<10, 32, {0, 1, 4, 4, 1<<13, 1<<(6+3)}}, + {4<<10, 16, {0, 1, 4, 4, 1<<14, 1<<(7+3)}}, {2<<10, 32, {0, 1, 4, 4, 1<<14, 1<<(6+3)}}, + {8<<10, 16, {0, 1, 4, 4, 1<<14, 1<<(8+3)}}, {8<<10, 32, {0, 1, 4, 4, 1<<14, 1<<(7+3)}} + }, org_entry; + + void set_channel_number(int channel); + void set_rank_number(int rank); + + /* Speed */ + enum class Speed : int + { + GDDR5_4000, GDDR5_4500, + GDDR5_5000, GDDR5_5500, + GDDR5_6000, GDDR5_6500, + GDDR5_7000, + MAX + }; + + int prefetch_size = 8; // 8n prefetch QDR + int channel_width = 64; + + struct SpeedEntry { + int rate; + double freq, tCK; + int nBL, nCCDS, nCCDL; + int nCL, nRCDR, nRCDW, nRP, nCWL; + int nRAS, nRC; + int nPPD, nRTP, nWTR, nWR; + int nRRD, nFAW, n32AW; + int nRFC, nREFI; + int nPD, nXPN, nLK; + int nCKESR, nXS, nXSDLL; + } speed_table[int(Speed::MAX)] = { + {4000, 8*500/4, 8.0/8, 2, 2, 3, 12, 12, 10, 12, 3, 28, 40, 1, 2, 5, 12, 6, 23, 184, 0, 0, 10, 10, 0, 0, 0, 0}, + {4500, 9*500/4, 8.0/9, 2, 2, 3, 14, 14, 12, 14, 4, 32, 46, 2, 2, 6, 14, 7, 26, 207, 0, 0, 10, 10, 0, 0, 0, 0}, + {5000, 10*500/4, 8.0/10, 2, 2, 3, 15, 15, 13, 15, 4, 35, 50, 2, 2, 7, 15, 7, 29, 230, 0, 0, 10, 10, 0, 0, 0, 0}, + {5500, 11*500/4, 8.0/11, 2, 2, 3, 17, 17, 14, 17, 5, 39, 56, 2, 2, 7, 17, 8, 32, 253, 0, 0, 10, 10, 0, 0, 0, 0}, + {6000, 12*500/4, 8.0/12, 2, 2, 3, 18, 18, 15, 18, 5, 42, 60, 2, 2, 8, 18, 9, 35, 276, 0, 0, 10, 10, 0, 0, 0, 0}, + {6500, 13*500/4, 8.0/13, 2, 2, 3, 20, 20, 17, 20, 5, 46, 66, 2, 2, 9, 20, 9, 38, 299, 0, 0, 10, 10, 0, 0, 0, 0}, + {7000, 14*500/4, 8.0/14, 2, 2, 3, 21, 21, 18, 21, 6, 49, 70, 2, 2, 9, 21, 10, 41, 322, 0, 0, 10, 10, 0, 0, 0, 0} + }, speed_entry; + + int read_latency; + +private: + void init_speed(); + void init_lambda(); + void init_prereq(); + void init_rowhit(); // SAUGATA: added function to check for row hits + void init_rowopen(); + void init_timing(); +}; + +} /*namespace ramulator*/ + +#endif /*__GDDR5_H*/ diff --git a/src/Gem5Wrapper.cpp b/src/Gem5Wrapper.cpp new file mode 100644 index 0000000..b836e79 --- /dev/null +++ b/src/Gem5Wrapper.cpp @@ -0,0 +1,55 @@ +#include + +#include "Gem5Wrapper.h" +#include "Config.h" +#include "Request.h" +#include "MemoryFactory.h" +#include "Memory.h" +#include "DDR3.h" +#include "DDR4.h" +#include "LPDDR3.h" +#include "LPDDR4.h" +#include "GDDR5.h" +#include "WideIO.h" +#include "WideIO2.h" +#include "HBM.h" +#include "SALP.h" + +using namespace ramulator; + +static map > name_to_func = { + {"DDR3", &MemoryFactory::create}, {"DDR4", &MemoryFactory::create}, + {"LPDDR3", &MemoryFactory::create}, {"LPDDR4", &MemoryFactory::create}, + {"GDDR5", &MemoryFactory::create}, + {"WideIO", &MemoryFactory::create}, {"WideIO2", &MemoryFactory::create}, + {"HBM", &MemoryFactory::create}, + {"SALP-1", &MemoryFactory::create}, {"SALP-2", &MemoryFactory::create}, {"SALP-MASA", &MemoryFactory::create}, +}; + + +Gem5Wrapper::Gem5Wrapper(const Config& configs, int cacheline) +{ + const string& std_name = configs["standard"]; + assert(name_to_func.find(std_name) != name_to_func.end() && "unrecognized standard name"); + mem = name_to_func[std_name](configs, cacheline); + tCK = mem->clk_ns(); +} + + +Gem5Wrapper::~Gem5Wrapper() { + delete mem; +} + +void Gem5Wrapper::tick() +{ + mem->tick(); +} + +bool Gem5Wrapper::send(Request req) +{ + return mem->send(req); +} + +void Gem5Wrapper::finish(void) { + mem->finish(); +} diff --git a/src/Gem5Wrapper.h b/src/Gem5Wrapper.h new file mode 100644 index 0000000..9090fac --- /dev/null +++ b/src/Gem5Wrapper.h @@ -0,0 +1,31 @@ +#ifndef __GEM5_WRAPPER_H +#define __GEM5_WRAPPER_H + +#include + +#include "Config.h" + +using namespace std; + +namespace ramulator +{ + +class Request; +class MemoryBase; + +class Gem5Wrapper +{ +private: + MemoryBase *mem; +public: + double tCK; + Gem5Wrapper(const Config& configs, int cacheline); + ~Gem5Wrapper(); + void tick(); + bool send(Request req); + void finish(void); +}; + +} /*namespace ramulator*/ + +#endif /*__GEM5_WRAPPER_H*/ diff --git a/src/HBM.cpp b/src/HBM.cpp new file mode 100644 index 0000000..9abfe74 --- /dev/null +++ b/src/HBM.cpp @@ -0,0 +1,359 @@ +#include "HBM.h" +#include "DRAM.h" + +#include +#include +#include + +using namespace std; +using namespace ramulator; + +string HBM::standard_name = "HBM"; + +map HBM::org_map = { + {"HBM_1Gb", HBM::Org::HBM_1Gb}, + {"HBM_2Gb", HBM::Org::HBM_2Gb}, + {"HBM_4Gb", HBM::Org::HBM_4Gb}, +}; + +map HBM::speed_map = { + {"HBM_1Gbps", HBM::Speed::HBM_1Gbps}, +}; + +HBM::HBM(Org org, Speed speed) + : org_entry(org_table[int(org)]), + speed_entry(speed_table[int(speed)]), + read_latency(speed_entry.nCL + speed_entry.nBL) +{ + init_speed(); + init_prereq(); + init_rowhit(); // SAUGATA: added row hit function + init_rowopen(); + init_lambda(); + init_timing(); +} + +HBM::HBM(const string& org_str, const string& speed_str) : + HBM(org_map[org_str], speed_map[speed_str]) +{ +} + +void HBM::set_channel_number(int channel) { + org_entry.count[int(Level::Channel)] = channel; +} + +void HBM::set_rank_number(int rank) { + org_entry.count[int(Level::Rank)] = rank; +} + + +void HBM::init_speed() +{ + const static int RFC_TABLE[int(Speed::MAX)][int(Org::MAX)] = { + {55, 80, 130} + }; + const static int REFI1B_TABLE[int(Speed::MAX)][int(Org::MAX)] = { + {64, 128, 256} + }; + const static int XS_TABLE[int(Speed::MAX)][int(Org::MAX)] = { + {60, 85, 135} + }; + + int speed = 0, density = 0; + switch (speed_entry.rate) { + case 1000: speed = 0; break; + default: assert(false); + }; + switch (org_entry.size >> 10){ + case 1: density = 0; break; + case 2: density = 1; break; + case 4: density = 2; break; + default: assert(false); + } + speed_entry.nRFC = RFC_TABLE[speed][density]; + speed_entry.nREFI1B = REFI1B_TABLE[speed][density]; + speed_entry.nXS = XS_TABLE[speed][density]; +} + + +void HBM::init_prereq() +{ + // RD + prereq[int(Level::Rank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::PowerUp): return Command::MAX; + case int(State::ActPowerDown): return Command::PDX; + case int(State::PrePowerDown): return Command::PDX; + case int(State::SelfRefresh): return Command::SRX; + default: assert(false); + }}; + prereq[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::Closed): return Command::ACT; + case int(State::Opened): + if (node->row_state.find(id) != node->row_state.end()) + return cmd; + else return Command::PRE; + default: assert(false); + }}; + + // WR + prereq[int(Level::Rank)][int(Command::WR)] = prereq[int(Level::Rank)][int(Command::RD)]; + prereq[int(Level::Bank)][int(Command::WR)] = prereq[int(Level::Bank)][int(Command::RD)]; + + // REF + prereq[int(Level::Rank)][int(Command::REF)] = [] (DRAM* node, Command cmd, int id) { + for (auto bg : node->children) + for (auto bank: bg->children) { + if (bank->state == State::Closed) + continue; + return Command::PREA; + } + return Command::REF;}; + + // REFSB + prereq[int(Level::Bank)][int(Command::REFSB)] = [] (DRAM* node, Command cmd, int id) { + if (node->state == State::Closed) return Command::REFSB; + return Command::PRE;}; + + // PD + prereq[int(Level::Rank)][int(Command::PDE)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::PowerUp): return Command::PDE; + case int(State::ActPowerDown): return Command::PDE; + case int(State::PrePowerDown): return Command::PDE; + case int(State::SelfRefresh): return Command::SRX; + default: assert(false); + }}; + + // SR + prereq[int(Level::Rank)][int(Command::SRE)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::PowerUp): return Command::SRE; + case int(State::ActPowerDown): return Command::PDX; + case int(State::PrePowerDown): return Command::PDX; + case int(State::SelfRefresh): return Command::SRE; + default: assert(false); + }}; +} + +// SAUGATA: added row hit check functions to see if the desired location is currently open +void HBM::init_rowhit() +{ + // RD + rowhit[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::Closed): return false; + case int(State::Opened): + if (node->row_state.find(id) != node->row_state.end()) + return true; + return false; + default: assert(false); + }}; + + // WR + rowhit[int(Level::Bank)][int(Command::WR)] = rowhit[int(Level::Bank)][int(Command::RD)]; +} + +void HBM::init_rowopen() +{ + // RD + rowopen[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::Closed): return false; + case int(State::Opened): return true; + default: assert(false); + }}; + + // WR + rowopen[int(Level::Bank)][int(Command::WR)] = rowopen[int(Level::Bank)][int(Command::RD)]; +} + +void HBM::init_lambda() +{ + lambda[int(Level::Bank)][int(Command::ACT)] = [] (DRAM* node, int id) { + node->state = State::Opened; + node->row_state[id] = State::Opened;}; + lambda[int(Level::Bank)][int(Command::PRE)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + lambda[int(Level::Rank)][int(Command::PREA)] = [] (DRAM* node, int id) { + for (auto bg : node->children) + for (auto bank : bg->children) { + bank->state = State::Closed; + bank->row_state.clear(); + }}; + lambda[int(Level::Rank)][int(Command::REF)] = [] (DRAM* node, int id) {}; + lambda[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, int id) {}; + lambda[int(Level::Bank)][int(Command::WR)] = [] (DRAM* node, int id) {}; + lambda[int(Level::Bank)][int(Command::RDA)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + lambda[int(Level::Bank)][int(Command::WRA)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + lambda[int(Level::Rank)][int(Command::PDE)] = [] (DRAM* node, int id) { + for (auto bg : node->children) + for (auto bank : bg->children) { + if (bank->state == State::Closed) + continue; + node->state = State::ActPowerDown; + return; + } + node->state = State::PrePowerDown;}; + lambda[int(Level::Rank)][int(Command::PDX)] = [] (DRAM* node, int id) { + node->state = State::PowerUp;}; + lambda[int(Level::Rank)][int(Command::SRE)] = [] (DRAM* node, int id) { + node->state = State::SelfRefresh;}; + lambda[int(Level::Rank)][int(Command::SRX)] = [] (DRAM* node, int id) { + node->state = State::PowerUp;}; +} + + +void HBM::init_timing() +{ + SpeedEntry& s = speed_entry; + vector *t; + + /*** Channel ***/ + t = timing[int(Level::Channel)]; + + // CAS <-> CAS + t[int(Command::RD)].push_back({Command::RD, 1, s.nBL}); + t[int(Command::RD)].push_back({Command::RDA, 1, s.nBL}); + t[int(Command::RDA)].push_back({Command::RD, 1, s.nBL}); + t[int(Command::RDA)].push_back({Command::RDA, 1, s.nBL}); + t[int(Command::WR)].push_back({Command::WR, 1, s.nBL}); + t[int(Command::WR)].push_back({Command::WRA, 1, s.nBL}); + t[int(Command::WRA)].push_back({Command::WR, 1, s.nBL}); + t[int(Command::WRA)].push_back({Command::WRA, 1, s.nBL}); + + + /*** Rank ***/ + t = timing[int(Level::Rank)]; + + // CAS <-> CAS + t[int(Command::RD)].push_back({Command::RD, 1, s.nCCDS}); + t[int(Command::RD)].push_back({Command::RDA, 1, s.nCCDS}); + t[int(Command::RDA)].push_back({Command::RD, 1, s.nCCDS}); + t[int(Command::RDA)].push_back({Command::RDA, 1, s.nCCDS}); + t[int(Command::WR)].push_back({Command::WR, 1, s.nCCDS}); + t[int(Command::WR)].push_back({Command::WRA, 1, s.nCCDS}); + t[int(Command::WRA)].push_back({Command::WR, 1, s.nCCDS}); + t[int(Command::WRA)].push_back({Command::WRA, 1, s.nCCDS}); + t[int(Command::RD)].push_back({Command::WR, 1, s.nCL + s.nCCDS + 2 - s.nCWL}); + t[int(Command::RD)].push_back({Command::WRA, 1, s.nCL + s.nCCDS + 2 - s.nCWL}); + t[int(Command::RDA)].push_back({Command::WR, 1, s.nCL + s.nCCDS + 2 - s.nCWL}); + t[int(Command::RDA)].push_back({Command::WRA, 1, s.nCL + s.nCCDS + 2 - s.nCWL}); + t[int(Command::WR)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nWTRS}); + t[int(Command::WR)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nWTRS}); + t[int(Command::WRA)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nWTRS}); + t[int(Command::WRA)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nWTRS}); + + t[int(Command::RD)].push_back({Command::PREA, 1, s.nRTP}); + t[int(Command::WR)].push_back({Command::PREA, 1, s.nCWL + s.nBL + s.nWR}); + + // CAS <-> PD + t[int(Command::RD)].push_back({Command::PDE, 1, s.nCL + s.nBL + 1}); + t[int(Command::RDA)].push_back({Command::PDE, 1, s.nCL + s.nBL + 1}); + t[int(Command::WR)].push_back({Command::PDE, 1, s.nCWL + s.nBL + s.nWR}); + t[int(Command::WRA)].push_back({Command::PDE, 1, s.nCWL + s.nBL + s.nWR + 1}); // +1 for pre + t[int(Command::PDX)].push_back({Command::RD, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::RDA, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::WR, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::WRA, 1, s.nXP}); + + // CAS <-> SR: none (all banks have to be precharged) + + // RAS <-> RAS + t[int(Command::ACT)].push_back({Command::ACT, 1, s.nRRDS}); + t[int(Command::ACT)].push_back({Command::ACT, 4, s.nFAW}); + t[int(Command::ACT)].push_back({Command::PREA, 1, s.nRAS}); + t[int(Command::PREA)].push_back({Command::ACT, 1, s.nRP}); + + // RAS <-> REF + t[int(Command::PRE)].push_back({Command::REF, 1, s.nRP}); + t[int(Command::PREA)].push_back({Command::REF, 1, s.nRP}); + t[int(Command::REF)].push_back({Command::ACT, 1, s.nRFC}); + + // RAS <-> PD + t[int(Command::ACT)].push_back({Command::PDE, 1, 1}); + t[int(Command::PDX)].push_back({Command::ACT, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::PRE, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::PREA, 1, s.nXP}); + + // RAS <-> SR + t[int(Command::PRE)].push_back({Command::SRE, 1, s.nRP}); + t[int(Command::PREA)].push_back({Command::SRE, 1, s.nRP}); + t[int(Command::SRX)].push_back({Command::ACT, 1, s.nXS}); + + // REF <-> REF + t[int(Command::REF)].push_back({Command::REF, 1, s.nRFC}); + + // REF <-> PD + t[int(Command::REF)].push_back({Command::PDE, 1, 1}); + t[int(Command::PDX)].push_back({Command::REF, 1, s.nXP}); + + // REF <-> SR + t[int(Command::SRX)].push_back({Command::REF, 1, s.nXS}); + + // PD <-> PD + t[int(Command::PDE)].push_back({Command::PDX, 1, s.nPD}); + t[int(Command::PDX)].push_back({Command::PDE, 1, s.nXP}); + + // PD <-> SR + t[int(Command::PDX)].push_back({Command::SRE, 1, s.nXP}); + t[int(Command::SRX)].push_back({Command::PDE, 1, s.nXS}); + + // SR <-> SR + t[int(Command::SRE)].push_back({Command::SRX, 1, s.nCKESR}); + t[int(Command::SRX)].push_back({Command::SRE, 1, s.nXS}); + + /*** Bank Group ***/ + t = timing[int(Level::BankGroup)]; + // CAS <-> CAS + t[int(Command::RD)].push_back({Command::RD, 1, s.nCCDL}); + t[int(Command::RD)].push_back({Command::RDA, 1, s.nCCDL}); + t[int(Command::RDA)].push_back({Command::RD, 1, s.nCCDL}); + t[int(Command::RDA)].push_back({Command::RDA, 1, s.nCCDL}); + t[int(Command::WR)].push_back({Command::WR, 1, s.nCCDL}); + t[int(Command::WR)].push_back({Command::WRA, 1, s.nCCDL}); + t[int(Command::WRA)].push_back({Command::WR, 1, s.nCCDL}); + t[int(Command::WRA)].push_back({Command::WRA, 1, s.nCCDL}); + t[int(Command::WR)].push_back({Command::WR, 1, s.nCCDL}); + t[int(Command::WR)].push_back({Command::WRA, 1, s.nCCDL}); + t[int(Command::WRA)].push_back({Command::WR, 1, s.nCCDL}); + t[int(Command::WRA)].push_back({Command::WRA, 1, s.nCCDL}); + t[int(Command::WR)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nWTRL}); + t[int(Command::WR)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nWTRL}); + t[int(Command::WRA)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nWTRL}); + t[int(Command::WRA)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nWTRL}); + + // RAS <-> RAS + t[int(Command::ACT)].push_back({Command::ACT, 1, s.nRRDL}); + + /*** Bank ***/ + t = timing[int(Level::Bank)]; + + // CAS <-> RAS + t[int(Command::ACT)].push_back({Command::RD, 1, s.nRCDR}); + t[int(Command::ACT)].push_back({Command::RDA, 1, s.nRCDR}); + t[int(Command::ACT)].push_back({Command::WR, 1, s.nRCDW}); + t[int(Command::ACT)].push_back({Command::WRA, 1, s.nRCDW}); + + t[int(Command::RD)].push_back({Command::PRE, 1, s.nRTP}); + t[int(Command::WR)].push_back({Command::PRE, 1, s.nCWL + s.nBL + s.nWR}); + + t[int(Command::RDA)].push_back({Command::ACT, 1, s.nRTP + s.nRP}); + t[int(Command::WRA)].push_back({Command::ACT, 1, s.nCWL + s.nBL + s.nWR + s.nRP}); + + // RAS <-> RAS + t[int(Command::ACT)].push_back({Command::ACT, 1, s.nRC}); + t[int(Command::ACT)].push_back({Command::PRE, 1, s.nRAS}); + t[int(Command::PRE)].push_back({Command::ACT, 1, s.nRP}); + + // REFSB + t[int(Command::PRE)].push_back({Command::REFSB, 1, s.nRP}); + t[int(Command::REFSB)].push_back({Command::REFSB, 1, s.nRFC}); + t[int(Command::REFSB)].push_back({Command::ACT, 1, s.nRFC}); +} diff --git a/src/HBM.h b/src/HBM.h new file mode 100644 index 0000000..228c826 --- /dev/null +++ b/src/HBM.h @@ -0,0 +1,199 @@ +#ifndef __HBM_H +#define __HBM_H + +#include "DRAM.h" +#include "Request.h" +#include +#include + +using namespace std; + +namespace ramulator +{ + +class HBM +{ +public: + static string standard_name; + enum class Org; + enum class Speed; + HBM(Org org, Speed speed); + HBM(const string& org_str, const string& speed_str); + + static map org_map; + static map speed_map; + + /* Level */ + enum class Level : int + { + Channel, Rank, BankGroup, Bank, Row, Column, MAX + }; + + /* Command */ + enum class Command : int + { + ACT, PRE, PREA, + RD, WR, RDA, WRA, + REF, REFSB, PDE, PDX, SRE, SRX, + MAX + }; + + // REFSB and REF is not compatible, choose one or the other. + // REFSB can be issued to banks in any order, as long as REFI1B + // is satisfied for all banks + + string command_name[int(Command::MAX)] = { + "ACT", "PRE", "PREA", + "RD", "WR", "RDA", "WRA", + "REF", "REFSB", "PDE", "PDX", "SRE", "SRX" + }; + + Level scope[int(Command::MAX)] = { + Level::Row, Level::Bank, Level::Rank, + Level::Column, Level::Column, Level::Column, Level::Column, + Level::Rank, Level::Bank, Level::Rank, Level::Rank, Level::Rank, Level::Rank + }; + + bool is_opening(Command cmd) + { + switch(int(cmd)) { + case int(Command::ACT): + return true; + default: + return false; + } + } + + bool is_accessing(Command cmd) + { + switch(int(cmd)) { + case int(Command::RD): + case int(Command::WR): + case int(Command::RDA): + case int(Command::WRA): + return true; + default: + return false; + } + } + + bool is_closing(Command cmd) + { + switch(int(cmd)) { + case int(Command::RDA): + case int(Command::WRA): + case int(Command::PRE): + case int(Command::PREA): + return true; + default: + return false; + } + } + + bool is_refreshing(Command cmd) + { + switch(int(cmd)) { + case int(Command::REF): + case int(Command::REFSB): + return true; + default: + return false; + } + } + + /* State */ + enum class State : int + { + Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX + } start[int(Level::MAX)] = { + State::MAX, State::PowerUp, State::MAX, State::Closed, State::Closed, State::MAX + }; + + /* Translate */ + Command translate[int(Request::Type::MAX)] = { + Command::RD, Command::WR, + Command::REF, Command::PDE, Command::SRE + }; + + /* Prereq */ + function*, Command cmd, int)> prereq[int(Level::MAX)][int(Command::MAX)]; + + // SAUGATA: added function object container for row hit status + /* Row hit */ + function*, Command cmd, int)> rowhit[int(Level::MAX)][int(Command::MAX)]; + function*, Command cmd, int)> rowopen[int(Level::MAX)][int(Command::MAX)]; + + /* Timing */ + struct TimingEntry + { + Command cmd; + int dist; + int val; + bool sibling; + }; + vector timing[int(Level::MAX)][int(Command::MAX)]; + + /* Lambda */ + function*, int)> lambda[int(Level::MAX)][int(Command::MAX)]; + + /* Organization */ + enum class Org : int + { // per channel density here. Each stack comes with 8 channels + HBM_1Gb, + HBM_2Gb, + HBM_4Gb, + MAX + }; + + struct OrgEntry { + int size; + int dq; + int count[int(Level::MAX)]; + } org_table[int(Org::MAX)] = { + {1<<10, 128, {0, 0, 4, 2, 1<<13, 1<<(6+1)}}, + {2<<10, 128, {0, 0, 4, 2, 1<<14, 1<<(6+1)}}, + {4<<10, 128, {0, 0, 4, 4, 1<<14, 1<<(6+1)}}, + }, org_entry; + + void set_channel_number(int channel); + void set_rank_number(int rank); + + /* Speed */ + enum class Speed : int + { + HBM_1Gbps, + MAX + }; + + int prefetch_size = 4; // burst length could be 2 and 4 (choose 4 here), 2n prefetch + int channel_width = 128; + + struct SpeedEntry { + int rate; + double freq, tCK; + int nBL, nCCDS, nCCDL; + int nCL, nRCDR, nRCDW, nRP, nCWL; + int nRAS, nRC; + int nRTP, nWTRS, nWTRL, nWR; + int nRRDS, nRRDL, nFAW; + int nRFC, nREFI, nREFI1B; + int nPD, nXP; + int nCKESR, nXS; + } speed_table[int(Speed::MAX)] = { + {1000, 500, 2.0, 2, 2, 3, 7, 7, 6, 7, 4, 17, 24, 7, 2, 4, 8, 4, 5, 20, 0, 1950, 0, 5, 5, 5, 0} + }, speed_entry; + + int read_latency; + +private: + void init_speed(); + void init_lambda(); + void init_prereq(); + void init_rowhit(); // SAUGATA: added function to check for row hits + void init_rowopen(); + void init_timing(); +}; + +} /*namespace ramulator*/ + +#endif /*__HBM_H*/ diff --git a/src/LPDDR3.cpp b/src/LPDDR3.cpp new file mode 100644 index 0000000..4b007e8 --- /dev/null +++ b/src/LPDDR3.cpp @@ -0,0 +1,377 @@ +#include "LPDDR3.h" +#include "DRAM.h" + +#include +#include +#include + +using namespace std; +using namespace ramulator; + +string LPDDR3::standard_name = "LPDDR3"; + +map LPDDR3::org_map = { + {"LPDDR3_4Gb_x16", LPDDR3::Org::LPDDR3_4Gb_x16}, {"LPDDR3_4Gb_x32", LPDDR3::Org::LPDDR3_4Gb_x32}, + {"LPDDR3_6Gb_x16", LPDDR3::Org::LPDDR3_6Gb_x16}, {"LPDDR3_6Gb_x32", LPDDR3::Org::LPDDR3_6Gb_x32}, + {"LPDDR3_8Gb_x16", LPDDR3::Org::LPDDR3_8Gb_x16}, {"LPDDR3_8Gb_x32", LPDDR3::Org::LPDDR3_8Gb_x32}, + {"LPDDR3_12Gb_x16", LPDDR3::Org::LPDDR3_12Gb_x16}, {"LPDDR3_12Gb_x32", LPDDR3::Org::LPDDR3_12Gb_x32}, + {"LPDDR3_16Gb_x16", LPDDR3::Org::LPDDR3_16Gb_x16}, {"LPDDR3_16Gb_x32", LPDDR3::Org::LPDDR3_16Gb_x32}, +}; + +map LPDDR3::speed_map = { + {"LPDDR3_1333", LPDDR3::Speed::LPDDR3_1333}, + {"LPDDR3_1600", LPDDR3::Speed::LPDDR3_1600}, + {"LPDDR3_1866", LPDDR3::Speed::LPDDR3_1866}, + {"LPDDR3_2133", LPDDR3::Speed::LPDDR3_2133}, +}; + +LPDDR3::LPDDR3(Org org, Speed speed) + : org_entry(org_table[int(org)]), + speed_entry(speed_table[int(speed)]), + read_latency(speed_entry.nCL + speed_entry.nDQSCK + speed_entry.nBL) +{ + init_speed(); + init_prereq(); + init_rowhit(); // SAUGATA: added row hit function + init_rowopen(); + init_lambda(); + init_timing(); +} + +LPDDR3::LPDDR3(const string& org_str, const string& speed_str) : + LPDDR3(org_map[org_str], speed_map[speed_str]) +{ +} + +void LPDDR3::set_channel_number(int channel) { + org_entry.count[int(Level::Channel)] = channel; +} + +void LPDDR3::set_rank_number(int rank) { + org_entry.count[int(Level::Rank)] = rank; +} + +void LPDDR3::init_speed() +{ + // 12Gb/16Gb RFCab/RFCpb TBD + + const static int RFCPB_TABLE[3][4] = { + {40, 48, 56, 64}, + {60, 72, 84, 96}, + {60, 72, 84, 96} + }; + + const static int RFCAB_TABLE[3][4] = { + {87, 104, 122, 139}, + {140, 168, 196, 224}, + {140, 168, 196, 224} + }; + + const static int XSR_TABLE[3][4] = { + {94, 112, 131, 150}, + {147, 176, 206, 235}, + {147, 176, 206, 235} + }; + + int speed = 0, density = 0; + switch (speed_entry.rate) { + case 1333: speed = 0; break; + case 1600: speed = 1; break; + case 1866: speed = 2; break; + case 2133: speed = 3; break; + default: assert(false); + }; + switch (org_entry.size >> 10){ + case 4: density = 0; break; + case 6: density = 1; break; + case 8: density = 2; break; + default: assert(false && "12Gb/16Gb is still TBD"); + } + speed_entry.nRFCpb = RFCPB_TABLE[density][speed]; + speed_entry.nRFCab = RFCAB_TABLE[density][speed]; + speed_entry.nXSR = XSR_TABLE[density][speed]; +} + + +void LPDDR3::init_prereq() +{ + // RD + prereq[int(Level::Rank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::PowerUp): return Command::MAX; + case int(State::ActPowerDown): return Command::PDX; + case int(State::PrePowerDown): return Command::PDX; + case int(State::SelfRefresh): return Command::SREFX; + default: assert(false); + }}; + prereq[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::Closed): return Command::ACT; + case int(State::Opened): + if (node->row_state.find(id) != node->row_state.end()) + return cmd; + return Command::PRE; + default: assert(false); + }}; + + // WR + prereq[int(Level::Rank)][int(Command::WR)] = prereq[int(Level::Rank)][int(Command::RD)]; + prereq[int(Level::Bank)][int(Command::WR)] = prereq[int(Level::Bank)][int(Command::RD)]; + + // REF + prereq[int(Level::Rank)][int(Command::REF)] = [] (DRAM* node, Command cmd, int id) { + for (auto bank : node->children) { + if (bank->state == State::Closed) + continue; + return Command::PRA; + } + return Command::REF;}; + + // REFPB + prereq[int(Level::Bank)][int(Command::REFPB)] = [] (DRAM* node, Command cmd, int id) { + if (node->state == State::Closed) return Command::REFPB; + else return Command::PRE;}; + + // PD + prereq[int(Level::Rank)][int(Command::PD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::PowerUp): return Command::PD; + case int(State::ActPowerDown): return Command::PD; + case int(State::PrePowerDown): return Command::PD; + case int(State::SelfRefresh): return Command::SREFX; + default: assert(false); + }}; + + // SR + prereq[int(Level::Rank)][int(Command::SREF)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::PowerUp): return Command::SREF; + case int(State::ActPowerDown): return Command::PDX; + case int(State::PrePowerDown): return Command::PDX; + case int(State::SelfRefresh): return Command::SREF; + default: assert(false); + }}; +} + +// SAUGATA: added row hit check functions to see if the desired location is currently open +void LPDDR3::init_rowhit() +{ + // RD + rowhit[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::Closed): return false; + case int(State::Opened): + if (node->row_state.find(id) != node->row_state.end()) + return true; + return false; + default: assert(false); + }}; + + // WR + rowhit[int(Level::Bank)][int(Command::WR)] = rowhit[int(Level::Bank)][int(Command::RD)]; +} + +void LPDDR3::init_rowopen() +{ + // RD + rowopen[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::Closed): return false; + case int(State::Opened): return true; + default: assert(false); + }}; + + // WR + rowopen[int(Level::Bank)][int(Command::WR)] = rowopen[int(Level::Bank)][int(Command::RD)]; +} + +void LPDDR3::init_lambda() +{ + lambda[int(Level::Bank)][int(Command::ACT)] = [] (DRAM* node, int id) { + node->state = State::Opened; + node->row_state[id] = State::Opened;}; + lambda[int(Level::Bank)][int(Command::PRE)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + lambda[int(Level::Rank)][int(Command::PRA)] = [] (DRAM* node, int id) { + for (auto bank : node->children) { + bank->state = State::Closed; + bank->row_state.clear();}}; + lambda[int(Level::Rank)][int(Command::REF)] = [] (DRAM* node, int id) {}; + lambda[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, int id) {}; + lambda[int(Level::Bank)][int(Command::WR)] = [] (DRAM* node, int id) {}; + lambda[int(Level::Bank)][int(Command::RDA)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + lambda[int(Level::Bank)][int(Command::WRA)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + lambda[int(Level::Rank)][int(Command::PD)] = [] (DRAM* node, int id) { + for (auto bank : node->children) { + if (bank->state == State::Closed) + continue; + node->state = State::ActPowerDown; + return; + } + node->state = State::PrePowerDown;}; + lambda[int(Level::Rank)][int(Command::PDX)] = [] (DRAM* node, int id) { + node->state = State::PowerUp;}; + lambda[int(Level::Rank)][int(Command::SREF)] = [] (DRAM* node, int id) { + node->state = State::SelfRefresh;}; + lambda[int(Level::Rank)][int(Command::SREFX)] = [] (DRAM* node, int id) { + node->state = State::PowerUp;}; +} + + +void LPDDR3::init_timing() +{ + SpeedEntry& s = speed_entry; + vector *t; + + /*** Channel ***/ + t = timing[int(Level::Channel)]; + + // CAS <-> CAS + t[int(Command::RD)].push_back({Command::RD, 1, s.nBL}); + t[int(Command::RD)].push_back({Command::RDA, 1, s.nBL}); + t[int(Command::RDA)].push_back({Command::RD, 1, s.nBL}); + t[int(Command::RDA)].push_back({Command::RDA, 1, s.nBL}); + t[int(Command::WR)].push_back({Command::WR, 1, s.nBL}); + t[int(Command::WR)].push_back({Command::WRA, 1, s.nBL}); + t[int(Command::WRA)].push_back({Command::WR, 1, s.nBL}); + t[int(Command::WRA)].push_back({Command::WRA, 1, s.nBL}); + + + /*** Rank ***/ + t = timing[int(Level::Rank)]; + + // CAS <-> CAS + t[int(Command::RD)].push_back({Command::RD, 1, s.nCCD}); + t[int(Command::RD)].push_back({Command::RDA, 1, s.nCCD}); + t[int(Command::RDA)].push_back({Command::RD, 1, s.nCCD}); + t[int(Command::RDA)].push_back({Command::RDA, 1, s.nCCD}); + t[int(Command::WR)].push_back({Command::WR, 1, s.nCCD}); + t[int(Command::WR)].push_back({Command::WRA, 1, s.nCCD}); + t[int(Command::WRA)].push_back({Command::WR, 1, s.nCCD}); + t[int(Command::WRA)].push_back({Command::WRA, 1, s.nCCD}); + // section 4.7.3 table 11 + t[int(Command::RD)].push_back({Command::WR, 1, s.nCL + s.nBL + s.nDQSCK + 1 - s.nCWL}); + t[int(Command::RD)].push_back({Command::WRA, 1, s.nCL + s.nBL + s.nDQSCK + 1 - s.nCWL}); + t[int(Command::RDA)].push_back({Command::WR, 1, s.nCL + s.nBL + s.nDQSCK + 1 - s.nCWL}); + t[int(Command::RDA)].push_back({Command::WRA, 1, s.nCL + s.nBL + s.nDQSCK + 1 - s.nCWL}); + + t[int(Command::WR)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nWTR + 1}); + t[int(Command::WR)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nWTR + 1}); + t[int(Command::WRA)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nWTR + 1}); + t[int(Command::WRA)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nWTR + 1}); + + // CAS <-> CAS (between sibling ranks) + t[int(Command::RD)].push_back({Command::RD, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RD)].push_back({Command::RDA, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RDA)].push_back({Command::RD, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RDA)].push_back({Command::RDA, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RD)].push_back({Command::WR, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RD)].push_back({Command::WRA, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RDA)].push_back({Command::WR, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RDA)].push_back({Command::WRA, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RD)].push_back({Command::WR, 1, s.nCL + s.nBL + s.nDQSCK + 1 + s.nRTRS - s.nCWL, true}); + t[int(Command::RD)].push_back({Command::WRA, 1, s.nCL + s.nBL + s.nDQSCK + 1 + s.nRTRS - s.nCWL, true}); + t[int(Command::RDA)].push_back({Command::WR, 1, s.nCL + s.nBL + s.nDQSCK + 1 + s.nRTRS - s.nCWL, true}); + t[int(Command::RDA)].push_back({Command::WRA, 1, s.nCL + s.nBL + s.nDQSCK + 1 + s.nRTRS - s.nCWL, true}); + t[int(Command::WR)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nRTRS - s.nCL, true}); + t[int(Command::WR)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nRTRS - s.nCL, true}); + t[int(Command::WRA)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nRTRS - s.nCL, true}); + t[int(Command::WRA)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nRTRS - s.nCL, true}); + + // CAS <-> PRA + t[int(Command::RD)].push_back({Command::PRA, 1, s.nRTP}); + t[int(Command::WR)].push_back({Command::PRA, 1, s.nCWL + s.nBL + s.nWR}); + + // CAS <-> PD + t[int(Command::RD)].push_back({Command::PD, 1, s.nCL + s.nBL + 1}); + t[int(Command::RDA)].push_back({Command::PD, 1, s.nCL + s.nBL + 1}); + t[int(Command::WR)].push_back({Command::PD, 1, s.nCWL + s.nBL + s.nWR}); + t[int(Command::WRA)].push_back({Command::PD, 1, s.nCWL + s.nBL + s.nWR + 1}); // +1 for pre + t[int(Command::PDX)].push_back({Command::RD, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::RDA, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::WR, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::WRA, 1, s.nXP}); + + // RAS <-> RAS + t[int(Command::ACT)].push_back({Command::ACT, 1, s.nRRD}); + t[int(Command::ACT)].push_back({Command::ACT, 4, s.nFAW}); + t[int(Command::ACT)].push_back({Command::PRA, 1, s.nRAS}); + t[int(Command::PRA)].push_back({Command::ACT, 1, s.nRPab}); + + // RAS <-> REF + t[int(Command::PRE)].push_back({Command::REF, 1, s.nRPpb}); + t[int(Command::PRA)].push_back({Command::REF, 1, s.nRPab}); + t[int(Command::REF)].push_back({Command::ACT, 1, s.nRFCab}); + + // RAS <-> PD + t[int(Command::ACT)].push_back({Command::PD, 1, 1}); + t[int(Command::PDX)].push_back({Command::ACT, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::PRE, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::PRA, 1, s.nXP}); + + // RAS <-> SR + t[int(Command::PRE)].push_back({Command::SREF, 1, s.nRPpb}); + t[int(Command::PRA)].push_back({Command::SREF, 1, s.nRPab}); + t[int(Command::SREFX)].push_back({Command::ACT, 1, s.nXSR}); + + // REF <-> REF + t[int(Command::REF)].push_back({Command::REF, 1, s.nRFCab}); + t[int(Command::REF)].push_back({Command::REFPB, 1, s.nRFCab}); + t[int(Command::REFPB)].push_back({Command::REF, 1, s.nRFCpb}); + + // REF <-> PD + t[int(Command::REF)].push_back({Command::PD, 1, 1}); + t[int(Command::REFPB)].push_back({Command::PD, 1, 1}); + t[int(Command::PDX)].push_back({Command::REF, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::REFPB, 1, s.nXP}); + + // REF <-> SR + t[int(Command::SREFX)].push_back({Command::REF, 1, s.nXSR}); + t[int(Command::SREFX)].push_back({Command::REFPB, 1, s.nXSR}); + + // PD <-> PD + t[int(Command::PD)].push_back({Command::PDX, 1, s.nCKE}); + t[int(Command::PDX)].push_back({Command::PD, 1, s.nXP}); + + // PD <-> SR + t[int(Command::PDX)].push_back({Command::SREF, 1, s.nXP}); + t[int(Command::SREFX)].push_back({Command::PD, 1, s.nXSR}); + + // SR <-> SR + t[int(Command::SREF)].push_back({Command::SREFX, 1, s.nCKESR}); + t[int(Command::SREFX)].push_back({Command::SREF, 1, s.nXSR}); + + /*** Bank ***/ + t = timing[int(Level::Bank)]; + + // CAS <-> RAS + t[int(Command::ACT)].push_back({Command::RD, 1, s.nRCD}); + t[int(Command::ACT)].push_back({Command::RDA, 1, s.nRCD}); + t[int(Command::ACT)].push_back({Command::WR, 1, s.nRCD}); + t[int(Command::ACT)].push_back({Command::WRA, 1, s.nRCD}); + + t[int(Command::RD)].push_back({Command::PRE, 1, s.nRTP}); + t[int(Command::WR)].push_back({Command::PRE, 1, s.nCWL + s.nBL + s.nWR}); + + t[int(Command::RDA)].push_back({Command::ACT, 1, s.nRTP + s.nRPpb}); + t[int(Command::WRA)].push_back({Command::ACT, 1, s.nCWL + s.nBL + s.nWR + s.nRPpb}); + + // RAS <-> RAS + t[int(Command::ACT)].push_back({Command::ACT, 1, s.nRC}); + t[int(Command::ACT)].push_back({Command::PRE, 1, s.nRAS}); + t[int(Command::PRE)].push_back({Command::ACT, 1, s.nRPpb}); + t[int(Command::PRE)].push_back({Command::REFPB, 1, s.nRPpb}); + + // between different banks + t[int(Command::ACT)].push_back({Command::REFPB, 1, s.nRRD, true}); + t[int(Command::REFPB)].push_back({Command::ACT, 1, s.nRRD, true}); + + // REFSB + t[int(Command::REFPB)].push_back({Command::REFPB, 1, s.nRFCpb}); + t[int(Command::REFPB)].push_back({Command::ACT, 1, s.nRFCpb}); +} diff --git a/src/LPDDR3.h b/src/LPDDR3.h new file mode 100644 index 0000000..c127975 --- /dev/null +++ b/src/LPDDR3.h @@ -0,0 +1,208 @@ +#ifndef __LPDDR3_H +#define __LPDDR3_H + +#include "DRAM.h" +#include "Request.h" +#include +#include + +using namespace std; + +namespace ramulator +{ + +class LPDDR3 +{ +public: + static string standard_name; + enum class Org; + enum class Speed; + LPDDR3(Org org, Speed speed); + LPDDR3(const string& org_str, const string& speed_str); + + static map org_map; + static map speed_map; + + /* Level */ + enum class Level : int + { + Channel, Rank, Bank, Row, Column, MAX + }; + + /* Command */ + enum class Command : int + { + ACT, PRE, PRA, + RD, WR, RDA, WRA, + REF, REFPB, PD, PDX, SREF, SREFX, + MAX + }; + + string command_name[int(Command::MAX)] = { + "ACT", "PRE", "PRA", + "RD", "WR", "RDA", "WRA", + "REF", "REFPB", "PD", "PDX", "SREF", "SREFX" + }; + + Level scope[int(Command::MAX)] = { + Level::Row, Level::Bank, Level::Rank, + Level::Column, Level::Column, Level::Column, Level::Column, + Level::Rank, Level::Bank, Level::Rank, Level::Rank, Level::Rank, Level::Rank + }; + + bool is_opening(Command cmd) + { + switch(int(cmd)) { + case int(Command::ACT): + return true; + default: + return false; + } + } + + bool is_accessing(Command cmd) + { + switch(int(cmd)) { + case int(Command::RD): + case int(Command::WR): + case int(Command::RDA): + case int(Command::WRA): + return true; + default: + return false; + } + } + + bool is_closing(Command cmd) + { + switch(int(cmd)) { + case int(Command::RDA): + case int(Command::WRA): + case int(Command::PRE): + case int(Command::PRA): + return true; + default: + return false; + } + } + + bool is_refreshing(Command cmd) + { + switch(int(cmd)) { + case int(Command::REF): + case int(Command::REFPB): + return true; + default: + return false; + } + } + + /* State */ + enum class State : int + { + Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX + } start[int(Level::MAX)] = { + State::MAX, State::PowerUp, State::Closed, State::Closed, State::MAX + }; + + /* Translate */ + Command translate[int(Request::Type::MAX)] = { + Command::RD, Command::WR, + Command::REF, Command::PD, Command::SREF + }; + + /* Prerequisite */ + function*, Command cmd, int)> prereq[int(Level::MAX)][int(Command::MAX)]; + + // SAUGATA: added function object container for row hit status + /* Row hit */ + function*, Command cmd, int)> rowhit[int(Level::MAX)][int(Command::MAX)]; + function*, Command cmd, int)> rowopen[int(Level::MAX)][int(Command::MAX)]; + + /* Timing */ + struct TimingEntry + { + Command cmd; + int dist; + int val; + bool sibling; + }; + vector timing[int(Level::MAX)][int(Command::MAX)]; + + /* Lambda */ + function*, int)> lambda[int(Level::MAX)][int(Command::MAX)]; + + /* Organization */ + enum class Org : int + { + LPDDR3_4Gb_x16, LPDDR3_4Gb_x32, + LPDDR3_6Gb_x16, LPDDR3_6Gb_x32, + LPDDR3_8Gb_x16, LPDDR3_8Gb_x32, + LPDDR3_12Gb_x16, LPDDR3_12Gb_x32, + LPDDR3_16Gb_x16, LPDDR3_16Gb_x32, + MAX + }; + + struct OrgEntry { + int size; + int dq; + int count[int(Level::MAX)]; + } org_table[int(Org::MAX)] = { + {4<<10, 16, {0, 0, 8, 1<<14, 1<<11}}, {4<<10, 32, {0, 0, 8, 1<<14, 1<<10}}, + {6<<10, 16, {0, 0, 8, 3<<13, 1<<11}}, {6<<10, 32, {0, 0, 8, 3<<13, 1<<10}}, + {8<<10, 16, {0, 0, 8, 1<<15, 1<<11}}, {8<<10, 32, {0, 0, 8, 1<<15, 1<<10}}, + {12<<10, 16, {0, 0, 8, 3<<13, 1<<12}}, {12<<10, 32, {0, 0, 8, 3<<13, 1<<11}}, + {16<<10, 16, {0, 0, 8, 1<<15, 1<<12}}, {16<<10, 32, {0, 0, 8, 1<<15, 1<<11}}, + }, org_entry; + + void set_channel_number(int channel); + void set_rank_number(int rank); + + /* Speed */ + enum class Speed : int + { + LPDDR3_1333, + LPDDR3_1600, + LPDDR3_1866, + LPDDR3_2133, + MAX + }; + + int prefetch_size = 8; // 16n prefetch DDR + int channel_width = 64; + + struct SpeedEntry { + int rate; + double freq, tCK; + int nBL, nCCD, nRTRS, nDQSCK; + int nCL, nRCD, nRPpb, nRPab, nCWL; + int nRAS, nRC; + int nRTP, nWTR, nWR; + int nRRD, nFAW; + int nRFCab, nRFCpb, nREFI; + int nCKE, nXP; // CKE is PD, LPDDR3 has no DLL + int nCKESR, nXSR; // tXSR = tRFCab + 10ns + } speed_table[int(Speed::MAX)] = { + {1333, (400.0/3)*5, (3/0.4)/5, 4, 4, 2, 2, 10, 12, 12, 14, 6, 28, 40, 5, 5, 10, 7, 34, 0, 0, 2600, 5, 5, 10, 0}, + {1600, (400.0/3)*6, (3/0.4)/6, 4, 4, 2, 2, 12, 15, 15, 17, 6, 34, 48, 6, 6, 12, 8, 40, 0, 0, 3120, 6, 6, 12, 0}, + {1866, (400.0/3)*7, (3/0.4)/7, 4, 4, 2, 3, 14, 17, 17, 20, 8, 40, 56, 7, 7, 14, 10, 47, 0, 0, 3640, 7, 7, 14, 0}, + {2133, (400.0/3)*8, (3/0.4)/8, 4, 4, 2, 3, 16, 20, 20, 23, 8, 45, 64, 8, 8, 16, 11, 54, 0, 0, 4160, 8, 8, 16, 0} + }, speed_entry; + + // LPDDR3 defines {fast, typical, slow} timing for tRCD and tRP. (typ) + // WL as diff. values for set A/B (A) + + int read_latency; + +private: + void init_speed(); + void init_lambda(); + void init_prereq(); + void init_rowhit(); // SAUGATA: added function to check for row hits + void init_rowopen(); + void init_timing(); +}; + +} /*namespace ramulator*/ + +#endif /*__LPDDR3_H*/ diff --git a/src/LPDDR4.cpp b/src/LPDDR4.cpp new file mode 100644 index 0000000..83a706d --- /dev/null +++ b/src/LPDDR4.cpp @@ -0,0 +1,378 @@ +#include "LPDDR4.h" +#include "DRAM.h" + +#include +#include +#include + +using namespace std; +using namespace ramulator; + +string LPDDR4::standard_name = "LPDDR4"; + +map LPDDR4::org_map = { + {"LPDDR4_4Gb_x16", LPDDR4::Org::LPDDR4_4Gb_x16}, + {"LPDDR4_6Gb_x16", LPDDR4::Org::LPDDR4_6Gb_x16}, + {"LPDDR4_8Gb_x16", LPDDR4::Org::LPDDR4_8Gb_x16}, +}; + +map LPDDR4::speed_map = { + {"LPDDR4_1600", LPDDR4::Speed::LPDDR4_1600}, + {"LPDDR4_2400", LPDDR4::Speed::LPDDR4_2400}, + {"LPDDR4_3200", LPDDR4::Speed::LPDDR4_3200}, +}; + +LPDDR4::LPDDR4(Org org, Speed speed) + : org_entry(org_table[int(org)]), + speed_entry(speed_table[int(speed)]), + read_latency(speed_entry.nCL + speed_entry.nDQSCK + speed_entry.nBL) +{ + init_speed(); + init_prereq(); + init_rowhit(); // SAUGATA: added row hit function + init_rowopen(); + init_lambda(); + init_timing(); +} + +LPDDR4::LPDDR4(const string& org_str, const string& speed_str) : + LPDDR4(org_map[org_str], speed_map[speed_str]) +{ +} + +void LPDDR4::set_channel_number(int channel) { + org_entry.count[int(Level::Channel)] = channel; +} + +void LPDDR4::set_rank_number(int rank) { + org_entry.count[int(Level::Rank)] = rank; +} + + +void LPDDR4::init_speed() +{ + // 12Gb/16Gb RFCab/RFCpb TBD + // Numbers are in DRAM cycles + const static int RFCPB_TABLE[int(Org::MAX)][int(Speed::MAX)] = { + {48, 72, 96}, + {72, 108, 144}, + {72, 108, 144} + }; + + const static int RFCAB_TABLE[int(Org::MAX)][int(Speed::MAX)] = { + {104, 156, 208}, + {144, 216, 288}, + {144, 216, 288} + }; + + const static int REFI_TABLE[int(RefreshMode::MAX)][int(Speed::MAX)] = { + {3124, 4685, 6247}, + {1563, 2344, 3125}, + { 782, 1172, 1563} + }; + + const static int XSR_TABLE[int(Org::MAX)][int(Speed::MAX)] = { + {110, 165, 220}, + {150, 225, 300}, + {150, 225, 300}, + }; + + int speed = 0, density = 0; + switch (speed_entry.rate) { + case 1600: speed = 0; break; + case 2400: speed = 1; break; + case 3200: speed = 2; break; + default: assert(false); + }; + switch (org_entry.size >> 10){ + case 2: density = 0; break; + case 3: density = 1; break; + case 4: density = 2; break; + default: assert(false && "12Gb/16Gb is still TBD"); + } + speed_entry.nRFCpb = RFCPB_TABLE[density][speed]; + speed_entry.nRFCab = RFCAB_TABLE[density][speed]; + speed_entry.nREFI = REFI_TABLE[int(refresh_mode)][speed]; + speed_entry.nXSR = XSR_TABLE[density][speed]; +} + + +void LPDDR4::init_prereq() +{ + // RD + prereq[int(Level::Rank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::PowerUp): return Command::MAX; + case int(State::ActPowerDown): return Command::PDX; + case int(State::PrePowerDown): return Command::PDX; + case int(State::SelfRefresh): return Command::SREFX; + default: assert(false); + }}; + prereq[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::Closed): return Command::ACT; + case int(State::Opened): + if (node->row_state.find(id) != node->row_state.end()) + return cmd; + return Command::PRE; + default: assert(false); + }}; + + // WR + prereq[int(Level::Rank)][int(Command::WR)] = prereq[int(Level::Rank)][int(Command::RD)]; + prereq[int(Level::Bank)][int(Command::WR)] = prereq[int(Level::Bank)][int(Command::RD)]; + + // REF + prereq[int(Level::Rank)][int(Command::REF)] = [] (DRAM* node, Command cmd, int id) { + for (auto bank : node->children) { + if (bank->state == State::Closed) + continue; + return Command::PREA; + } + return Command::REF;}; + + // PD + prereq[int(Level::Rank)][int(Command::PDE)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::PowerUp): return Command::PDE; + case int(State::ActPowerDown): return Command::PDE; + case int(State::PrePowerDown): return Command::PDE; + case int(State::SelfRefresh): return Command::SREFX; + default: assert(false); + }}; + + // SR + prereq[int(Level::Rank)][int(Command::SREF)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::PowerUp): return Command::SREF; + case int(State::ActPowerDown): return Command::PDX; + case int(State::PrePowerDown): return Command::PDX; + case int(State::SelfRefresh): return Command::SREF; + default: assert(false); + }}; +} + +// SAUGATA: added row hit check functions to see if the desired location is currently open +void LPDDR4::init_rowhit() +{ + // RD + rowhit[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::Closed): return false; + case int(State::Opened): + if (node->row_state.find(id) != node->row_state.end()) + return true; + return false; + default: assert(false); + }}; + + // WR + rowhit[int(Level::Bank)][int(Command::WR)] = rowhit[int(Level::Bank)][int(Command::RD)]; +} + +void LPDDR4::init_rowopen() +{ + // RD + rowopen[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::Closed): return false; + case int(State::Opened): return true; + default: assert(false); + }}; + + // WR + rowopen[int(Level::Bank)][int(Command::WR)] = rowopen[int(Level::Bank)][int(Command::RD)]; +} + +void LPDDR4::init_lambda() +{ + lambda[int(Level::Bank)][int(Command::ACT)] = [] (DRAM* node, int id) { + node->state = State::Opened; + node->row_state[id] = State::Opened;}; + lambda[int(Level::Bank)][int(Command::PRE)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + lambda[int(Level::Rank)][int(Command::PREA)] = [] (DRAM* node, int id) { + for (auto bank : node->children) { + bank->state = State::Closed; + bank->row_state.clear();}}; + lambda[int(Level::Rank)][int(Command::REF)] = [] (DRAM* node, int id) {}; + lambda[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, int id) {}; + lambda[int(Level::Bank)][int(Command::WR)] = [] (DRAM* node, int id) {}; + lambda[int(Level::Bank)][int(Command::RDA)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + lambda[int(Level::Bank)][int(Command::WRA)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + lambda[int(Level::Rank)][int(Command::PDE)] = [] (DRAM* node, int id) { + for (auto bank : node->children) { + if (bank->state == State::Closed) + continue; + node->state = State::ActPowerDown; + return; + } + node->state = State::PrePowerDown;}; + lambda[int(Level::Rank)][int(Command::PDX)] = [] (DRAM* node, int id) { + node->state = State::PowerUp;}; + lambda[int(Level::Rank)][int(Command::SREF)] = [] (DRAM* node, int id) { + node->state = State::SelfRefresh;}; + lambda[int(Level::Rank)][int(Command::SREFX)] = [] (DRAM* node, int id) { + node->state = State::PowerUp;}; +} + + +void LPDDR4::init_timing() +{ + SpeedEntry& s = speed_entry; + vector *t; + + /*** Channel ***/ + t = timing[int(Level::Channel)]; + + // CAS <-> CAS + t[int(Command::RD)].push_back({Command::RD, 1, s.nBL}); + t[int(Command::RD)].push_back({Command::RDA, 1, s.nBL}); + t[int(Command::RDA)].push_back({Command::RD, 1, s.nBL}); + t[int(Command::RDA)].push_back({Command::RDA, 1, s.nBL}); + t[int(Command::WR)].push_back({Command::WR, 1, s.nBL}); + t[int(Command::WR)].push_back({Command::WRA, 1, s.nBL}); + t[int(Command::WRA)].push_back({Command::WR, 1, s.nBL}); + t[int(Command::WRA)].push_back({Command::WRA, 1, s.nBL}); + + + /*** Rank ***/ + t = timing[int(Level::Rank)]; + + // CAS <-> CAS + t[int(Command::RD)].push_back({Command::RD, 1, s.nCCD}); + t[int(Command::RD)].push_back({Command::RDA, 1, s.nCCD}); + t[int(Command::RDA)].push_back({Command::RD, 1, s.nCCD}); + t[int(Command::RDA)].push_back({Command::RDA, 1, s.nCCD}); + t[int(Command::WR)].push_back({Command::WR, 1, s.nCCD}); + t[int(Command::WR)].push_back({Command::WRA, 1, s.nCCD}); + t[int(Command::WRA)].push_back({Command::WR, 1, s.nCCD}); + t[int(Command::WRA)].push_back({Command::WRA, 1, s.nCCD}); + + t[int(Command::RD)].push_back({Command::WR, 1, s.nCL + s.nBL + s.nDQSCK + 1 - s.nCWL}); + t[int(Command::RD)].push_back({Command::WRA, 1, s.nCL + s.nBL + s.nDQSCK + 1 - s.nCWL}); + t[int(Command::RDA)].push_back({Command::WR, 1, s.nCL + s.nBL + s.nDQSCK + 1 - s.nCWL}); + t[int(Command::RDA)].push_back({Command::WRA, 1, s.nCL + s.nBL + s.nDQSCK + 1 - s.nCWL}); + + t[int(Command::WR)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nWTR + 1}); + t[int(Command::WR)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nWTR + 1}); + t[int(Command::WRA)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nWTR + 1}); + t[int(Command::WRA)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nWTR + 1}); + + + // CAS <-> CAS (between sibling ranks) + t[int(Command::RD)].push_back({Command::RD, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RD)].push_back({Command::RDA, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RDA)].push_back({Command::RD, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RDA)].push_back({Command::RDA, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RD)].push_back({Command::WR, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RD)].push_back({Command::WRA, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RDA)].push_back({Command::WR, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RDA)].push_back({Command::WRA, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RD)].push_back({Command::WR, 1, s.nCL + s.nBL + s.nDQSCK + 1 + s.nRTRS - s.nCWL, true}); + t[int(Command::RD)].push_back({Command::WRA, 1, s.nCL + s.nBL + s.nDQSCK + 1 + s.nRTRS - s.nCWL, true}); + t[int(Command::RDA)].push_back({Command::WR, 1, s.nCL + s.nBL + s.nDQSCK + 1 + s.nRTRS - s.nCWL, true}); + t[int(Command::RDA)].push_back({Command::WRA, 1, s.nCL + s.nBL + s.nDQSCK + 1 + s.nRTRS - s.nCWL, true}); + t[int(Command::WR)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nRTRS - s.nCL, true}); + t[int(Command::WR)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nRTRS - s.nCL, true}); + t[int(Command::WRA)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nRTRS - s.nCL, true}); + t[int(Command::WRA)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nRTRS - s.nCL, true}); + + // CAS <-> PREA + t[int(Command::RD)].push_back({Command::PREA, 1, s.nRTP}); + t[int(Command::WR)].push_back({Command::PREA, 1, s.nCWL + s.nBL + s.nWR}); + + // CAS <-> PD + t[int(Command::RD)].push_back({Command::PDE, 1, s.nCL + s.nBL + 1}); + t[int(Command::RDA)].push_back({Command::PDE, 1, s.nCL + s.nBL + 1}); + t[int(Command::WR)].push_back({Command::PDE, 1, s.nCWL + s.nBL + s.nWR}); + t[int(Command::WRA)].push_back({Command::PDE, 1, s.nCWL + s.nBL + s.nWR + 1}); // +1 for pre + t[int(Command::PDX)].push_back({Command::RD, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::RDA, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::WR, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::WRA, 1, s.nXP}); + + // RAS <-> RAS + t[int(Command::ACT)].push_back({Command::ACT, 1, s.nRRD}); + t[int(Command::ACT)].push_back({Command::ACT, 4, s.nFAW}); + t[int(Command::ACT)].push_back({Command::PREA, 1, s.nRAS}); + t[int(Command::PREA)].push_back({Command::ACT, 1, s.nRPab}); + t[int(Command::PRE)].push_back({Command::PRE, 1, s.nPPD}); + + // RAS <-> REF + t[int(Command::PRE)].push_back({Command::REF, 1, s.nRPpb}); + t[int(Command::PREA)].push_back({Command::REF, 1, s.nRPab}); + t[int(Command::REF)].push_back({Command::ACT, 1, s.nRFCab}); + + // RAS <-> PD + t[int(Command::ACT)].push_back({Command::PDE, 1, 1}); + t[int(Command::PDX)].push_back({Command::ACT, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::PRE, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::PREA, 1, s.nXP}); + + // RAS <-> SR + t[int(Command::PRE)].push_back({Command::SREF, 1, s.nRPpb}); + t[int(Command::PREA)].push_back({Command::SREF, 1, s.nRPab}); + t[int(Command::SREFX)].push_back({Command::ACT, 1, s.nXSR}); + + // REF <-> REF + t[int(Command::REF)].push_back({Command::REF, 1, s.nRFCab}); + t[int(Command::REF)].push_back({Command::REFPB, 1, s.nRFCab}); + t[int(Command::REFPB)].push_back({Command::REF, 1, s.nRFCpb}); + + // REF <-> PD + t[int(Command::REF)].push_back({Command::PDE, 1, 1}); + t[int(Command::REFPB)].push_back({Command::PDE, 1, 1}); + t[int(Command::PDX)].push_back({Command::REF, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::REFPB, 1, s.nXP}); + + // REF <-> SR + t[int(Command::SREFX)].push_back({Command::REF, 1, s.nXSR}); + t[int(Command::SREFX)].push_back({Command::REFPB, 1, s.nXSR}); + + // PD <-> PD + t[int(Command::PDE)].push_back({Command::PDX, 1, s.nCKE}); + t[int(Command::PDX)].push_back({Command::PDE, 1, s.nXP}); + + // PD <-> SR + t[int(Command::PDX)].push_back({Command::SREF, 1, s.nXP}); + t[int(Command::SREFX)].push_back({Command::PDE, 1, s.nXSR}); + + // SR <-> SR + t[int(Command::SREF)].push_back({Command::SREFX, 1, s.nSR}); + t[int(Command::SREFX)].push_back({Command::SREF, 1, s.nXSR}); + + /*** Bank ***/ + t = timing[int(Level::Bank)]; + + // CAS <-> RAS + t[int(Command::ACT)].push_back({Command::RD, 1, s.nRCD}); + t[int(Command::ACT)].push_back({Command::RDA, 1, s.nRCD}); + t[int(Command::ACT)].push_back({Command::WR, 1, s.nRCD}); + t[int(Command::ACT)].push_back({Command::WRA, 1, s.nRCD}); + + t[int(Command::RD)].push_back({Command::PRE, 1, s.nRTP}); + t[int(Command::WR)].push_back({Command::PRE, 1, s.nCWL + s.nBL + s.nWR}); + + t[int(Command::RDA)].push_back({Command::ACT, 1, s.nRTP + s.nRPpb}); + t[int(Command::WRA)].push_back({Command::ACT, 1, s.nCWL + s.nBL + s.nWR + s.nRPpb}); + + // RAS <-> RAS + t[int(Command::ACT)].push_back({Command::ACT, 1, s.nRC}); + t[int(Command::ACT)].push_back({Command::PRE, 1, s.nRAS}); + t[int(Command::PRE)].push_back({Command::ACT, 1, s.nRPpb}); + t[int(Command::PRE)].push_back({Command::REFPB, 1, s.nRPpb}); + + // between different banks + t[int(Command::ACT)].push_back({Command::REFPB, 1, s.nRRD, true}); + t[int(Command::REFPB)].push_back({Command::ACT, 1, s.nRRD, true}); + + // REFPB + t[int(Command::REFPB)].push_back({Command::REFPB, 1, s.nRFCpb}); + t[int(Command::REFPB)].push_back({Command::ACT, 1, s.nRFCpb}); +} diff --git a/src/LPDDR4.h b/src/LPDDR4.h new file mode 100644 index 0000000..024c453 --- /dev/null +++ b/src/LPDDR4.h @@ -0,0 +1,222 @@ +#ifndef __LPDDR4_H +#define __LPDDR4_H + +#include "DRAM.h" +#include "Request.h" +#include +#include + +using namespace std; + +namespace ramulator +{ + +class LPDDR4 +{ +public: + static string standard_name; + enum class Org; + enum class Speed; + LPDDR4(Org org, Speed speed); + LPDDR4(const string& org_str, const string& speed_str); + + static map org_map; + static map speed_map; + + /* Level */ + enum class Level : int + { + Channel, Rank, Bank, Row, Column, MAX + }; + + /* Command */ + enum class Command : int + { + ACT, PRE, PREA, + RD, WR, RDA, WRA, + REF, REFPB, PDE, PDX, SREF, SREFX, + MAX + }; + // Due to multiplexing on the cmd/addr bus: + // ACT, RD, WR, RDA, WRA take 4 cycles + // PRE, PREA, REF, REFPB, PDE, PDX, SREF, SREFX take 2 cycles + string command_name[int(Command::MAX)] = { + "ACT", "PRE", "PREA", + "RD", "WR", "RDA", "WRA", + "REF", "REFPB", "PDE", "PDX", "SREF", "SREFX" + }; + + Level scope[int(Command::MAX)] = { + Level::Row, Level::Bank, Level::Rank, + Level::Column, Level::Column, Level::Column, Level::Column, + Level::Rank, Level::Bank, Level::Rank, Level::Rank, Level::Rank, Level::Rank + }; + + bool is_opening(Command cmd) + { + switch(int(cmd)) { + case int(Command::ACT): + return true; + default: + return false; + } + } + + bool is_accessing(Command cmd) + { + switch(int(cmd)) { + case int(Command::RD): + case int(Command::WR): + case int(Command::RDA): + case int(Command::WRA): + return true; + default: + return false; + } + } + + bool is_closing(Command cmd) + { + switch(int(cmd)) { + case int(Command::RDA): + case int(Command::WRA): + case int(Command::PRE): + case int(Command::PREA): + return true; + default: + return false; + } + } + + bool is_refreshing(Command cmd) + { + switch(int(cmd)) { + case int(Command::REF): + case int(Command::REFPB): + return true; + default: + return false; + } + } + + /* State */ + enum class State : int + { + Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX + } start[int(Level::MAX)] = { + State::MAX, State::PowerUp, State::Closed, State::Closed, State::MAX + }; + + /* Translate */ + Command translate[int(Request::Type::MAX)] = { + Command::RD, Command::WR, + Command::REF, Command::PDE, Command::SREF + }; + + /* Prerequisite */ + function*, Command cmd, int)> prereq[int(Level::MAX)][int(Command::MAX)]; + + // SAUGATA: added function object container for row hit status + /* Row hit */ + function*, Command cmd, int)> rowhit[int(Level::MAX)][int(Command::MAX)]; + function*, Command cmd, int)> rowopen[int(Level::MAX)][int(Command::MAX)]; + + /* Timing */ + struct TimingEntry + { + Command cmd; + int dist; + int val; + bool sibling; + }; + vector timing[int(Level::MAX)][int(Command::MAX)]; + + /* Lambda */ + function*, int)> lambda[int(Level::MAX)][int(Command::MAX)]; + + /* Organization */ + enum class Org : int + { + // this is per-die density, actual per-chan density is half + LPDDR4_4Gb_x16, + LPDDR4_6Gb_x16, + LPDDR4_8Gb_x16, + // LPDDR4_12Gb_x16, // tRFC TBD + // LPDDR4_16Gb_x16, // tRFC TBD + MAX + }; + + struct OrgEntry { + int size; + int dq; + int count[int(Level::MAX)]; + } org_table[int(Org::MAX)] = { + {2<<10, 16, {0, 0, 8, 1<<14, 1<<10}}, + {3<<10, 16, {0, 0, 8, 3<<13, 1<<10}}, + {4<<10, 16, {0, 0, 8, 1<<15, 1<<10}}, + }, org_entry; + + void set_channel_number(int channel); + void set_rank_number(int rank); + + + /* Speed */ + enum class Speed : int + { + LPDDR4_1600, + LPDDR4_2400, + LPDDR4_3200, + MAX + }; + + enum class RefreshMode : int + { + Refresh_1X, + Refresh_2X, + Refresh_4X, + MAX + } refresh_mode = RefreshMode::Refresh_1X; + + int prefetch_size = 16; // 16n prefetch DDR + int channel_width = 32; + + struct SpeedEntry { + int rate; + double freq, tCK; + int nBL, nCCD, nRTRS, nDQSCK; + int nCL, nRCD, nRPpb, nRPab, nCWL; + int nRAS, nRC; + int nRTP, nWTR, nWR; + int nPPD, nRRD, nFAW; + int nRFCab, nRFCpb, nREFI; + int nCKE, nXP; // CKE value n/a + int nSR, nXSR; // tXSR = tRFCab + 7.5ns + } speed_table[int(Speed::MAX)] = { + // LPDDR4 is 16n prefetch. Latencies in JESD209-4 counts from and to + // the end of each command, I've converted them as if all commands take + // only 1 cycle like other standards + // CL-RCD-RPpb are set to the same value althrough CL is not explicitly specified. + // CWL is made up, half of CL. + // calculated from 10.2 core timing table 89 + {1600, 400.0*2, 2.5/2, 8, 8, 2, 1, 15+3, 15, 15-2, 17-2, 8+3, 34, 47, 8+2, 8, 15-1, 4, 8, 32, 0, 0, 0, 0, 6, 12, 0}, + {2400, 400.0*3, 2.5/3, 8, 8, 2, 2, 22+3, 22, 22-2, 26-2, 11+3, 51, 71, 9+2, 12, 22-1, 4, 12, 48, 0, 0, 0, 0, 9, 18, 0}, + {3200, 400.0*4, 2.5/4, 8, 8, 2, 3, 29+3, 29, 29-2, 34-2, 15+3, 68, 95, 12+2, 16, 29-1, 4, 16, 64, 0, 0, 0, 0, 12, 24, 0} + }, speed_entry; + + // LPDDR4 defines {fast, typical, slow} timing for tRCD and tRP. (typ) + // WL as diff. values for set A/B (A) + + int read_latency; + +private: + void init_speed(); + void init_lambda(); + void init_prereq(); + void init_rowhit(); // SAUGATA: added function to check for row hits + void init_rowopen(); + void init_timing(); +}; + +} /*namespace ramulator*/ + +#endif /*__LPDDR4_H*/ diff --git a/src/Main.cpp b/src/Main.cpp new file mode 100644 index 0000000..39adfaa --- /dev/null +++ b/src/Main.cpp @@ -0,0 +1,24 @@ +#include "MemWrapper.h" +#include "pe.h" + +int sc_main(int argc, char *argv[]){ + + sc_signal burstReq; + sc_signal burstResp; + + int peClkCycle = 10; + int memClkCycle = 5; + + MemWrapper memWrapper("memWrapper", memClkCycle, peClkCycle, argc, argv); + memWrapper.burstReq(burstReq); + memWrapper.burstResp(burstResp); + + pe peInst("peInst", 0, peClkCycle); + peInst.burstReq(burstReq); + peInst.burstResp(burstResp); + + sc_start(); + + return 0; + +} diff --git a/src/MemWrapper.cpp b/src/MemWrapper.cpp new file mode 100644 index 0000000..5cc7fe7 --- /dev/null +++ b/src/MemWrapper.cpp @@ -0,0 +1,493 @@ +#include "MemWrapper.h" + +// The memory configuration is initially ported from ramulator. +// which are mostly parsed from input argument. We don't want to change it for now. +MemWrapper::MemWrapper(sc_module_name _name, + int _memClkCycle, + int _peClkCycle, + int argc, + char* argv[]) + : sc_module(_name), configs(argv[1]){ + + loadConfig(argc, argv); + memClkCycle = _memClkCycle; + peClkCycle = _peClkCycle; + GL::burstLen = calBurstLen(); + ramInit(); + + SC_THREAD(runMemSim); + SC_THREAD(getBurstReq); + SC_THREAD(sendBurstResp); + SC_THREAD(respMonitor); + +} + +// This function is used to update ram content. +// As the ramulator doesn't returns the write response to request, +// it is not easy to decide when to update write request based on the +// basic read/write request. To solve this problem, we update ram content +// based on the burst request order. We will not update write burst +// request until there is a following read request coming up. In this case, +// we can be sure the ram follows the sequential consistence despite the +// parallel memory processing. +void MemWrapper::updateBurstToRam(long watchedBurstIdx){ + for(auto it = burstReqQueue.begin(); it != burstReqQueue.end(); it++){ + // All the write burst requests that arrive after the watched burst request + // will not affect the read processing. + if(it->burstIdx == watchedBurstIdx){ + break; + } + else{ + if(it->type == ramulator::Request::Type::WRITE){ + it->reqToRam(ramData); + writebackHistory[it->burstIdx] = true; + } + } + } +} + +// This process basically detects the respQueue every memClkCycle. +// When a burstRequest has all its requests processed, we will declare +// the end of the burstRequest processing. And a burst Response will be +// genenrated and enqueued into the burstRespQueue. +void MemWrapper::respMonitor(){ + while(true){ + for(auto bit = burstReqQueue.begin(); bit != burstReqQueue.end(); bit++){ + + // Skip the burst requests that have been responsed. + if(burstStatus[bit->burstIdx]) continue; + + // Check if all the splitted requests get responsed. + bool burstRespReady = true; + if(burstStatus[bit->burstIdx] == false){ + for(auto rit = bit->reqVec.begin(); rit != bit->reqVec.end(); rit++){ + if(reqStatus[*rit] == false){ + burstRespReady = false; + break; + } + } + } + + if(burstRespReady){ + burstStatus[bit->burstIdx] = true; + BurstOp resp = *bit; + resp.setArriveMemTime(getMinArriveTime(bit->reqVec)); + resp.setDepartMemTime(getMaxDepartTime(bit->reqVec)); + burstRespQueue.push_back(resp); + cleanRespQueue(bit->reqVec); + } + } + + wait(memClkCycle, SC_NS); + } +} + +// Analyze the arrive memory time of all basic requests of a single burst operation. +// To save the function passsing cost, we have only the involved reqIdx vectoe passed. +long MemWrapper::getMinArriveTime(const std::vector &reqVec){ + std::vector arriveTime; + for(auto rit = reqVec.begin(); rit != reqVec.end(); rit++){ + for(auto it = respQueue.begin(); it != respQueue.end(); it++){ + if(it->udf.reqIdx == *rit){ + arriveTime.push_back(it->udf.arriveMemTime); + break; + } + } + } + + auto mit = std::min_element(arriveTime.begin(), arriveTime.end()); + return *mit; + +} + +long MemWrapper::getMaxDepartTime(const std::vector &reqVec){ + std::vector departTime; + for(auto rit = reqVec.begin(); rit != reqVec.end(); rit++){ + for(auto it = respQueue.begin(); it != respQueue.end(); it++){ + if(it->udf.reqIdx == *rit){ + departTime.push_back(it->udf.departMemTime); + break; + } + } + } + + auto it = std::max_element(departTime.begin(), departTime.end()); + return *it; +} + +// As we don't want to have the resp/req queues grow with time and don't want to +// implement complex and accurate clean strategy, thus we just clean +// the old memory requests based on the timestamps. +void MemWrapper::cleanProcessedRequests(){} + +// It reads request from pe and thus is synchronized to the pe's clock +void MemWrapper::getBurstReq(){ + int counter = 0; + while(true){ + BurstOp op = burstReq.read(); + if(op.valid){ + burstReqQueue.push_back(op); + burstStatus[op.burstIdx] = false; + if(op.type == ramulator::Request::Type::WRITE){ + writebackHistory[op.burstIdx] = false; + } + + op.convertToReq(reqQueue); + + // update request status + for(auto it = op.reqVec.begin(); it != op.reqVec.end(); it++){ + reqStatus[*it] = false; + } + + if(op.type == ramulator::Request::Type::READ){ + counter++; + std::cout << counter << " burst requests are received." << std::endl; + } + } + wait(peClkCycle, SC_NS); + } +} + +// Traverse the response request and write the response to +// pe based on the response time. Basically, we need to synchronize +// pe and memory operations. +void MemWrapper::sendBurstResp(){ + while(true){ + long currentTimeStamp = (long)(sc_time_stamp()/sc_time(1, SC_NS)); + if(burstRespQueue.empty()){ + BurstOp op(false); + burstResp.write(op); + } + else { + // Although multiple memory response may be sent, only a single + // one can be sent to a pe each time. Basically, it is possible + // that memory responses may not be able to sent out and + // additional queuing time is required. + auto it = burstRespQueue.begin(); + while(it != burstRespQueue.end()){ + long respReadyTime = it->getDepartMemTime(); + if(respReadyTime <= currentTimeStamp){ + if(it->type == ramulator::Request::Type::READ){ + // Update all the write burst requests that + // arrives earlier than this request to ramData + updateBurstToRam(it->burstIdx); + it->ramToReq(ramData); + } + burstResp.write(*it); + burstRespQueue.erase(it++); + break; + } + else{ + it++; + } + } + } + + wait(peClkCycle, SC_NS); + } +} + +int MemWrapper::calBurstLen(){ + + int burstlen; + if (standard == "DDR3") { + DDR3* ddr3 = new DDR3(configs["org"], configs["speed"]); + burstlen = ddr3->prefetch_size * ddr3->channel_width / 8; + } else if (standard == "DDR4") { + DDR4* ddr4 = new DDR4(configs["org"], configs["speed"]); + burstlen = ddr4->prefetch_size * ddr4->channel_width / 8; + } else if (standard == "SALP-MASA") { + SALP* salp8 = new SALP(configs["org"], configs["speed"], "SALP-MASA", configs.get_subarrays()); + burstlen = salp8->prefetch_size * salp8->channel_width / 8; + } else if (standard == "LPDDR3") { + LPDDR3* lpddr3 = new LPDDR3(configs["org"], configs["speed"]); + burstlen = lpddr3->prefetch_size * lpddr3->channel_width / 8; + } else if (standard == "LPDDR4") { + // total cap: 2GB, 1/2 of others + LPDDR4* lpddr4 = new LPDDR4(configs["org"], configs["speed"]); + burstlen = lpddr4->prefetch_size * lpddr4->channel_width / 8; + } else if (standard == "GDDR5") { + GDDR5* gddr5 = new GDDR5(configs["org"], configs["speed"]); + burstlen = gddr5->prefetch_size * gddr5->channel_width / 8; + } else if (standard == "HBM") { + HBM* hbm = new HBM(configs["org"], configs["speed"]); + burstlen = hbm->prefetch_size * hbm->channel_width / 8; + } else if (standard == "WideIO") { + // total cap: 1GB, 1/4 of others + WideIO* wio = new WideIO(configs["org"], configs["speed"]); + burstlen = wio->prefetch_size * wio->channel_width / 8; + } else if (standard == "WideIO2") { + // total cap: 2GB, 1/2 of others + WideIO2* wio2 = new WideIO2(configs["org"], configs["speed"], configs.get_channels()); + wio2->channel_width *= 2; + burstlen = wio2->prefetch_size * wio2->channel_width / 8; + } + // Various refresh mechanisms + else if (standard == "DSARP") { + DSARP* dsddr3_dsarp = new DSARP(configs["org"], configs["speed"], DSARP::Type::DSARP, configs.get_subarrays()); + burstlen = dsddr3_dsarp->prefetch_size * dsddr3_dsarp->channel_width / 8; + } else if (standard == "ALDRAM") { + ALDRAM* aldram = new ALDRAM(configs["org"], configs["speed"]); + burstlen = aldram->prefetch_size * aldram->channel_width / 8; + } else if (standard == "TLDRAM") { + TLDRAM* tldram = new TLDRAM(configs["org"], configs["speed"], configs.get_subarrays()); + burstlen = tldram->prefetch_size * tldram->channel_width / 8; + } + else{ + HERE; + std::cout << "Unknown memory standard." << std::endl; + exit(EXIT_FAILURE); + } + + return burstlen; +} + +void MemWrapper::runMemSim(){ + + if (standard == "DDR3") { + DDR3* ddr3 = new DDR3(configs["org"], configs["speed"]); + start_run(configs, ddr3, files); + } else if (standard == "DDR4") { + DDR4* ddr4 = new DDR4(configs["org"], configs["speed"]); + start_run(configs, ddr4, files); + } else if (standard == "SALP-MASA") { + SALP* salp8 = new SALP(configs["org"], configs["speed"], "SALP-MASA", configs.get_subarrays()); + start_run(configs, salp8, files); + } else if (standard == "LPDDR3") { + LPDDR3* lpddr3 = new LPDDR3(configs["org"], configs["speed"]); + start_run(configs, lpddr3, files); + } else if (standard == "LPDDR4") { + // total cap: 2GB, 1/2 of others + LPDDR4* lpddr4 = new LPDDR4(configs["org"], configs["speed"]); + start_run(configs, lpddr4, files); + } else if (standard == "GDDR5") { + GDDR5* gddr5 = new GDDR5(configs["org"], configs["speed"]); + start_run(configs, gddr5, files); + } else if (standard == "HBM") { + HBM* hbm = new HBM(configs["org"], configs["speed"]); + start_run(configs, hbm, files); + } else if (standard == "WideIO") { + // total cap: 1GB, 1/4 of others + WideIO* wio = new WideIO(configs["org"], configs["speed"]); + start_run(configs, wio, files); + } else if (standard == "WideIO2") { + // total cap: 2GB, 1/2 of others + WideIO2* wio2 = new WideIO2(configs["org"], configs["speed"], configs.get_channels()); + wio2->channel_width *= 2; + start_run(configs, wio2, files); + } + // Various refresh mechanisms + else if (standard == "DSARP") { + DSARP* dsddr3_dsarp = new DSARP(configs["org"], configs["speed"], DSARP::Type::DSARP, configs.get_subarrays()); + start_run(configs, dsddr3_dsarp, files); + } else if (standard == "ALDRAM") { + ALDRAM* aldram = new ALDRAM(configs["org"], configs["speed"]); + start_run(configs, aldram, files); + } else if (standard == "TLDRAM") { + TLDRAM* tldram = new TLDRAM(configs["org"], configs["speed"], configs.get_subarrays()); + start_run(configs, tldram, files); + } + printf("Simulation done. Statistics written to %s\n", stats_out.c_str()); + +} + +void MemWrapper::loadConfig(int argc, char* argv[]){ + if (argc < 2) { + printf("Usage: %s --mode=cpu,dram,acc [--stats ] Example: %s ramulator-configs.cfg --mode=cpu cpu.trace cpu.trace\n", argv[0], argv[0]); + } + + standard = configs["standard"]; + assert(standard != "" || "DRAM standard should be specified."); + + const char *trace_type = strstr(argv[2], "="); + trace_type++; + if (strcmp(trace_type, "acc") == 0){ + configs.add("trace_type", "acc"); + } else { + printf("invalid trace type: %s\n", trace_type); + assert(false); + } + + int trace_start = 3; + Stats::statlist.output(standard+".stats"); + stats_out = standard + string(".stats"); + + // When the accelerator is used, there is no need for trace files. + if(argc >=3){ + for(int i = trace_start; i < argc; i++){ + files.push_back(argv[i]); + } + } + + configs.set_core_num(argc - trace_start); +} + +template +void MemWrapper::start_run(const Config& configs, T* spec, const vector& files) { + // initiate controller and memory + int C = configs.get_channels(), R = configs.get_ranks(); + // Check and Set channel, rank number + spec->set_channel_number(C); + spec->set_rank_number(R); + std::vector*> ctrls; + for (int c = 0 ; c < C ; c++) { + DRAM* channel = new DRAM(spec, T::Level::Channel); + channel->id = c; + channel->regStats(""); + Controller* ctrl = new Controller(configs, channel); + ctrls.push_back(ctrl); + } + Memory memory(configs, ctrls); + + if (configs["trace_type"] == "acc") { + run_acc(configs, memory); + } + else { + std::cout << "Error: unexpected trace type." << std::endl; + exit(EXIT_FAILURE); + } +} + +// The reqQueue can always accept requests from pe, +// but the memory requests may not be processed by the +// ramulator due to the internal queue limitation. This +// infinite queue here is used to simplify the synchronization +// between pe and ramulator. For example, they don't have to +// constantly check the internal queue if it is ready to accept +// new requests. At the same time, it keeps the original parallel +// memory processing limitation of the DRAM model. +bool MemWrapper::getMemReq(Request &req){ + std::list::iterator it; + if(!reqQueue.empty()){ + it = reqQueue.begin(); + shallowReqCopy(*it, req); + req.udf.arriveMemTime = (long)(sc_time_stamp()/sc_time(1, SC_NS)); + reqQueue.pop_front(); + return true; + } + else{ + return false; + } +} + +template +void MemWrapper::run_acc(const Config& configs, Memory& memory) { + /* run simulation */ + bool stall = false; + bool end = false; + int reads = 0; + int writes = 0; + int clks = 0; + Request::Type type = Request::Type::READ; + map latencies; + + // Callback function + auto read_complete = [this, &latencies](Request& r){ + long latency = r.depart - r.arrive; + latencies[latency]++; + //update departMemTime + r.udf.departMemTime = r.udf.arriveMemTime + memClkCycle * latency; + respQueue.push_back(r); + reqStatus[r.udf.reqIdx] = true; + std::cout << "req: " << r.udf.reqIdx << " is returnned at " << sc_time_stamp() << std::endl; + std::cout << "req: " << r.udf.reqIdx << " " << r.arrive << " " << r.depart << std::endl; + }; + + std::vector addr_vec; + Request req(addr_vec, type, read_complete); + + // Keep waiting for the memory request processing + while (true){ + if (!stall){ + end = !getMemReq(req); + } + + if (!end){ + stall = !memory.send(req); + if (!stall){ + if (req.type == Request::Type::READ){ + std::cout << "req: " << req.udf.reqIdx << " is issued at " << sc_time_stamp() << std::endl; + reads++; + } + // At this time, we can already assume that the write operation is done. + else if (req.type == Request::Type::WRITE){ + writes++; + long currentTimeStamp = (long)(sc_time_stamp()/sc_time(1, SC_NS)); + req.udf.departMemTime = currentTimeStamp; + respQueue.push_back(req); + reqStatus[req.udf.reqIdx] = true; + } + } + } + + wait(memClkCycle, SC_NS); + memory.tick(); + clks ++; + Stats::curTick++; // memory clock, global, for Statistics + } + // This a workaround for statistics set only initially lost in the end + // memory.finish(); + // Stats::statlist.printall(); +} + + +// We don't want to mess up the callback function while copying +void MemWrapper::shallowReqCopy(const Request &simpleReq, Request &req){ + req.type = simpleReq.type; + req.coreid = simpleReq.coreid; + req.addr = simpleReq.addr; + req.udf.burstIdx = simpleReq.udf.burstIdx; + req.udf.reqIdx = simpleReq.udf.reqIdx; + req.udf.peIdx = simpleReq.udf.peIdx; + req.udf.departPeTime = simpleReq.udf.departPeTime; + req.udf.arriveMemTime = simpleReq.udf.arriveMemTime; + req.udf.departMemTime = simpleReq.udf.departMemTime; + req.udf.arrivePeTime = simpleReq.udf.arrivePeTime; +} + +void MemWrapper::ramInit(){ + + ramData.resize(1024*1024); + + long addrVa = GL::vaMemAddr; + long addrVb = GL::vbMemAddr; + long addrVp = GL::vpMemAddr; + int val = 0; + + for(int i = 0; i < 512; i++){ + updateSingleDataToRam(addrVa, val); + updateSingleDataToRam(addrVb, val); + updateSingleDataToRam(addrVp, 0); + val++; + addrVa += (long)sizeof(int); + addrVb += (long)sizeof(int); + addrVp += (long)sizeof(int); + } + +} + +// Update ram on a specified addr with specified data type. +template +void MemWrapper::updateSingleDataToRam(long addr, T t){ + T* p = (T*)malloc(sizeof(T)); + *p = t; + + for(int i = 0; i < (int)sizeof(T); i++){ + ramData[addr+i] = *((char*)p + i); + } + + delete p; +} + + +// Clean the resp that has been combined to a burst response from the queue. +void MemWrapper::cleanRespQueue(const std::vector &reqVec){ + for(auto rit = reqVec.begin(); rit != reqVec.end(); rit++){ + for(auto it = respQueue.begin(); it != respQueue.end(); it++){ + if(it->udf.reqIdx == *rit){ + respQueue.erase(it); + break; + } + } + } +} diff --git a/src/MemWrapper.h b/src/MemWrapper.h new file mode 100644 index 0000000..e8d3246 --- /dev/null +++ b/src/MemWrapper.h @@ -0,0 +1,132 @@ +#ifndef __MEM_WRAPPER_H__ +#define __MEM_WRAPPER_H__ + +#include "Processor.h" +#include "Config.h" +#include "Controller.h" +#include "SpeedyController.h" +#include "Memory.h" +#include "DRAM.h" +#include "Statistics.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "pe.h" +#include "common.h" + +/* Standards */ +#include "Gem5Wrapper.h" +#include "DDR3.h" +#include "DDR4.h" +#include "DSARP.h" +#include "GDDR5.h" +#include "LPDDR3.h" +#include "LPDDR4.h" +#include "WideIO.h" +#include "WideIO2.h" +#include "HBM.h" +#include "SALP.h" +#include "ALDRAM.h" +#include "TLDRAM.h" + +class MemWrapper : public sc_module{ + + SC_HAS_PROCESS(MemWrapper); + + public: + // Memory related configurations + std::string name; + std::string standard; + Config configs; + string stats_out; + std::vector files; + + // Signals from/to pes. They will be processed following the peClk. + sc_in burstReq; + sc_out burstResp; + + // The queue stores all the burst request transactions + // and it will not be removed untill the end of the program. + // In addition, as the requests are stored in order, + // it is also the basis of the data memory content management. + std::list burstReqQueue; + + // It stores the response obtained from the ramulator and it will + // be gradually removed when the response is sent out. + std::list burstRespQueue; + + // It stores all the requests to be sent to the ramulator + // It will gradually be removed when it is processed. + std::list reqQueue; + + // It stores all the responses returned from the ramulator as well as + // the write response generated accordingly. The response will be removed + // when it is combined to a burst response and sent back to pe. + std::list respQueue; + + MemWrapper(sc_module_name _name, + int _memClkCycle, + int _peClkCycle, + int argc, + char* argv[]); + + template + void run_acc(const Config& configs, Memory& memory); + + template + void start_run(const Config& configs, T* spec, const vector& files); + void getBurstReq(); + void runMemSim(); + bool getMemReq(Request &req); + void sendBurstResp(); + void memReqMonitor(); + void respMonitor(); + void updateBurstToRam(long watchedBurstIdx); + ~MemWrapper(){}; + + private: + int memSize; // # of bytes + std::vector ramData; // byte level memory data management. + + // It stores the status of all the basic memory requests. + // If a reqIdx is not found, it means the request doesn't exist. + // If a regIdx is found and boolean value is false, it means the + // request is under processing. + // If a reqIdx is found and boolean value is true, it means the request gets + // responsed. + std::map reqStatus; + + // burstStatus represnts similar information with that of reqStatus. + std::map burstStatus; + + // Basically we keep a record of the write request updating history. + // If the write request has its content written to ramData, it will be set + // true. If the write response is under processing, it will be set as false; + // It it is not found here, it means there is no such write request yet. + std::map writebackHistory; + + int memClkCycle; + int peClkCycle; + + void loadConfig(int argc, char* argv[]); + int calBurstLen(); + long getMaxDepartTime(const std::vector &reqVec); + long getMinArriveTime(const std::vector &reqVec); + void cleanProcessedRequests(); + void shallowReqCopy(const Request &simpleReq, Request &req); + void ramInit(); + + // Update ram on a specified addr with specified data type. + template + void updateSingleDataToRam(long addr, T t); + void cleanRespQueue(const std::vector &reqVec); +}; + +#endif diff --git a/src/Memory.h b/src/Memory.h new file mode 100644 index 0000000..e0f51ca --- /dev/null +++ b/src/Memory.h @@ -0,0 +1,432 @@ +#ifndef __MEMORY_H +#define __MEMORY_H + +#include "Config.h" +#include "DRAM.h" +#include "Request.h" +#include "Controller.h" +#include "SpeedyController.h" +#include "Statistics.h" +#include "GDDR5.h" +#include "HBM.h" +#include "LPDDR3.h" +#include "LPDDR4.h" +#include "WideIO2.h" +#include "DSARP.h" +#include +#include +#include +#include +#include + +using namespace std; + +namespace ramulator +{ + +class MemoryBase{ +public: + MemoryBase() {} + virtual ~MemoryBase() {} + virtual double clk_ns() = 0; + virtual void tick() = 0; + virtual bool send(Request req) = 0; + virtual int pending_requests() = 0; + virtual void finish(void) = 0; + virtual long page_allocator(long addr, int coreid) = 0; + virtual void record_core(int coreid) = 0; +}; + +template class Controller = Controller > +class Memory : public MemoryBase +{ +protected: + ScalarStat dram_capacity; + ScalarStat num_dram_cycles; + ScalarStat num_incoming_requests; + VectorStat num_read_requests; + VectorStat num_write_requests; + ScalarStat ramulator_active_cycles; + VectorStat incoming_requests_per_channel; + VectorStat incoming_read_reqs_per_channel; + + ScalarStat physical_page_replacement; + ScalarStat maximum_bandwidth; + ScalarStat in_queue_req_num_sum; + ScalarStat in_queue_read_req_num_sum; + ScalarStat in_queue_write_req_num_sum; + ScalarStat in_queue_req_num_avg; + ScalarStat in_queue_read_req_num_avg; + ScalarStat in_queue_write_req_num_avg; + +#ifndef INTEGRATED_WITH_GEM5 + VectorStat record_read_requests; + VectorStat record_write_requests; +#endif + + long max_address; +public: + enum class Type { + ChRaBaRoCo, + RoBaRaCoCh, + MAX, + } type = Type::RoBaRaCoCh; + + enum class Translation { + None, + Random, + MAX, + } translation = Translation::None; + + std::map name_to_translation = { + {"None", Translation::None}, + {"Random", Translation::Random}, + }; + + vector free_physical_pages; + long free_physical_pages_remaining; + map, long> page_translation; + + vector*> ctrls; + T * spec; + vector addr_bits; + + int tx_bits; + + Memory(const Config& configs, vector*> ctrls) + : ctrls(ctrls), + spec(ctrls[0]->channel->spec), + addr_bits(int(T::Level::MAX)) + { + // make sure 2^N channels/ranks + // TODO support channel number that is not powers of 2 + int *sz = spec->org_entry.count; + assert((sz[0] & (sz[0] - 1)) == 0); + assert((sz[1] & (sz[1] - 1)) == 0); + // validate size of one transaction + int tx = (spec->prefetch_size * spec->channel_width / 8); + tx_bits = calc_log2(tx); + assert((1<standard_name.substr(0, 5) == "LPDDR") + assert((sz[int(T::Level::Row)] & (sz[int(T::Level::Row)] - 1)) == 0); + + max_address = spec->channel_width / 8; + + for (unsigned int lev = 0; lev < addr_bits.size(); lev++) { + addr_bits[lev] = calc_log2(sz[lev]); + max_address *= sz[lev]; + } + + addr_bits[int(T::Level::MAX) - 1] -= calc_log2(spec->prefetch_size); + + // Initiating translation + if (configs.contains("translation")) { + translation = name_to_translation[configs["translation"]]; + } + if (translation != Translation::None) { + // construct a list of available pages + // TODO: this should not assume a 4KB page! + free_physical_pages_remaining = max_address >> 12; + + free_physical_pages.resize(free_physical_pages_remaining, -1); + } + + dram_capacity + .name("dram_capacity") + .desc("Number of bytes in simulated DRAM") + .precision(0) + ; + dram_capacity = max_address; + + num_dram_cycles + .name("dram_cycles") + .desc("Number of DRAM cycles simulated") + .precision(0) + ; + num_incoming_requests + .name("incoming_requests") + .desc("Number of incoming requests to DRAM") + .precision(0) + ; + num_read_requests + .init(configs.get_core_num()) + .name("read_requests") + .desc("Number of incoming read requests to DRAM per core") + .precision(0) + ; + num_write_requests + .init(configs.get_core_num()) + .name("write_requests") + .desc("Number of incoming write requests to DRAM per core") + .precision(0) + ; + incoming_requests_per_channel + .init(sz[int(T::Level::Channel)]) + .name("incoming_requests_per_channel") + .desc("Number of incoming requests to each DRAM channel") + ; + incoming_read_reqs_per_channel + .init(sz[int(T::Level::Channel)]) + .name("incoming_read_reqs_per_channel") + .desc("Number of incoming read requests to each DRAM channel") + ; + + ramulator_active_cycles + .name("ramulator_active_cycles") + .desc("The total number of cycles that the DRAM part is active (serving R/W)") + .precision(0) + ; + physical_page_replacement + .name("physical_page_replacement") + .desc("The number of times that physical page replacement happens.") + .precision(0) + ; + maximum_bandwidth + .name("maximum_bandwidth") + .desc("The theoretical maximum bandwidth (Bps)") + .precision(0) + ; + in_queue_req_num_sum + .name("in_queue_req_num_sum") + .desc("Sum of read/write queue length") + .precision(0) + ; + in_queue_read_req_num_sum + .name("in_queue_read_req_num_sum") + .desc("Sum of read queue length") + .precision(0) + ; + in_queue_write_req_num_sum + .name("in_queue_write_req_num_sum") + .desc("Sum of write queue length") + .precision(0) + ; + in_queue_req_num_avg + .name("in_queue_req_num_avg") + .desc("Average of read/write queue length per memory cycle") + .precision(6) + ; + in_queue_read_req_num_avg + .name("in_queue_read_req_num_avg") + .desc("Average of read queue length per memory cycle") + .precision(6) + ; + in_queue_write_req_num_avg + .name("in_queue_write_req_num_avg") + .desc("Average of write queue length per memory cycle") + .precision(6) + ; +#ifndef INTEGRATED_WITH_GEM5 + record_read_requests + .init(configs.get_core_num()) + .name("record_read_requests") + .desc("record read requests for this core when it reaches request limit or to the end") + ; + + record_write_requests + .init(configs.get_core_num()) + .name("record_write_requests") + .desc("record write requests for this core when it reaches request limit or to the end") + ; +#endif + + } + + ~Memory() + { + for (auto ctrl: ctrls) + delete ctrl; + delete spec; + } + + double clk_ns() + { + return spec->speed_entry.tCK; + } + + void record_core(int coreid) { +#ifndef INTEGRATED_WITH_GEM5 + record_read_requests[coreid] = num_read_requests[coreid]; + record_write_requests[coreid] = num_write_requests[coreid]; +#endif + for (auto ctrl : ctrls) { + ctrl->record_core(coreid); + } + } + + void tick() + { + ++num_dram_cycles; + int cur_que_req_num = 0; + int cur_que_readreq_num = 0; + int cur_que_writereq_num = 0; + for (auto ctrl : ctrls) { + cur_que_req_num += ctrl->readq.size() + ctrl->writeq.size() + ctrl->pending.size(); + cur_que_readreq_num += ctrl->readq.size() + ctrl->pending.size(); + cur_que_writereq_num += ctrl->writeq.size(); + } + in_queue_req_num_sum += cur_que_req_num; + in_queue_read_req_num_sum += cur_que_readreq_num; + in_queue_write_req_num_sum += cur_que_writereq_num; + + bool is_active = false; + for (auto ctrl : ctrls) { + is_active = is_active || ctrl->is_active(); + ctrl->tick(); + } + if (is_active) { + ramulator_active_cycles++; + } + } + + bool send(Request req) + { + req.addr_vec.resize(addr_bits.size()); + long addr = req.addr; + int coreid = req.coreid; + + // Each transaction size is 2^tx_bits, so first clear the lowest tx_bits bits + clear_lower_bits(addr, tx_bits); + + switch(int(type)){ + case int(Type::ChRaBaRoCo): + for (int i = addr_bits.size() - 1; i >= 0; i--) + req.addr_vec[i] = slice_lower_bits(addr, addr_bits[i]); + break; + case int(Type::RoBaRaCoCh): + req.addr_vec[0] = slice_lower_bits(addr, addr_bits[0]); + req.addr_vec[addr_bits.size() - 1] = slice_lower_bits(addr, addr_bits[addr_bits.size() - 1]); + for (int i = 1; i <= int(T::Level::Row); i++) + req.addr_vec[i] = slice_lower_bits(addr, addr_bits[i]); + break; + default: + assert(false); + } + + if(ctrls[req.addr_vec[0]]->enqueue(req)) { + // tally stats here to avoid double counting for requests that aren't enqueued + ++num_incoming_requests; + if (req.type == Request::Type::READ) { + ++num_read_requests[coreid]; + int tmp = (int) (T::Level::Channel); + ++incoming_read_reqs_per_channel[req.addr_vec[tmp]]; + } + if (req.type == Request::Type::WRITE) { + ++num_write_requests[coreid]; + } + ++incoming_requests_per_channel[req.addr_vec[int(T::Level::Channel)]]; + return true; + } + + return false; + } + + int pending_requests() + { + int reqs = 0; + for (auto ctrl: ctrls) + reqs += ctrl->readq.size() + ctrl->writeq.size() + ctrl->otherq.size() + ctrl->pending.size(); + return reqs; + } + + void finish(void) { + dram_capacity = max_address; + int *sz = spec->org_entry.count; + maximum_bandwidth = spec->speed_entry.rate * 1e6 * spec->channel_width * sz[int(T::Level::Channel)] / 8; + long dram_cycles = num_dram_cycles.value(); + for (auto ctrl : ctrls) { + long read_req = long(incoming_read_reqs_per_channel[ctrl->channel->id].value()); + ctrl->finish(read_req, dram_cycles); + } + + // finalize average queueing requests + in_queue_req_num_avg = in_queue_req_num_sum.value() / dram_cycles; + in_queue_read_req_num_avg = in_queue_read_req_num_sum.value() / dram_cycles; + in_queue_write_req_num_avg = in_queue_write_req_num_sum.value() / dram_cycles; + } + + long page_allocator(long addr, int coreid) { + long virtual_page_number = addr >> 12; + + switch(int(translation)) { + case int(Translation::None): { + return addr; + } + case int(Translation::Random): { + auto target = make_pair(coreid, virtual_page_number); + if(page_translation.find(target) == page_translation.end()) { + // page doesn't exist, so assign a new page + // make sure there are physical pages left to be assigned + + // if physical page doesn't remain, replace a previous assigned + // physical page. + if (!free_physical_pages_remaining) { + physical_page_replacement++; + long phys_page_to_read = lrand() % free_physical_pages.size(); + assert(free_physical_pages[phys_page_to_read] != -1); + page_translation[target] = phys_page_to_read; + } else { + // assign a new page + long phys_page_to_read = lrand() % free_physical_pages.size(); + // if the randomly-selected page was already assigned + if(free_physical_pages[phys_page_to_read] != -1) { + long starting_page_of_search = phys_page_to_read; + + do { + // iterate through the list until we find a free page + // TODO: does this introduce serious non-randomness? + ++phys_page_to_read; + phys_page_to_read %= free_physical_pages.size(); + } + while((phys_page_to_read != starting_page_of_search) && free_physical_pages[phys_page_to_read] != -1); + } + + assert(free_physical_pages[phys_page_to_read] == -1); + + page_translation[target] = phys_page_to_read; + free_physical_pages[phys_page_to_read] = coreid; + --free_physical_pages_remaining; + } + } + + // SAUGATA TODO: page size should not always be fixed to 4KB + return (page_translation[target] << 12) | (addr & ((1 << 12) - 1)); + } + default: + assert(false); + } + + } + +private: + + int calc_log2(int val){ + int n = 0; + while ((val >>= 1)) + n ++; + return n; + } + int slice_lower_bits(long& addr, int bits) + { + int lbits = addr & ((1<>= bits; + return lbits; + } + void clear_lower_bits(long& addr, int bits) + { + addr >>= bits; + } + long lrand(void) { + if(sizeof(int) < sizeof(long)) { + return static_cast(rand()) << (sizeof(int) * 8) | rand(); + } + + return rand(); + } +}; + +} /*namespace ramulator*/ + +#endif /*__MEMORY_H*/ diff --git a/src/MemoryFactory.cpp b/src/MemoryFactory.cpp new file mode 100644 index 0000000..6a8f389 --- /dev/null +++ b/src/MemoryFactory.cpp @@ -0,0 +1,80 @@ +#include "MemoryFactory.h" +#include "LPDDR4.h" +#include "WideIO.h" +#include "WideIO2.h" +#include "HBM.h" +#include "SALP.h" + +using namespace ramulator; + +namespace ramulator +{ + +template <> +void MemoryFactory::validate(int channels, int ranks, const Config& configs) { + assert(channels >= 2 && "LPDDR4 requires 2, 4, 8 ... channels"); +} + +template <> +void MemoryFactory::validate(int channels, int ranks, const Config& configs) { + assert(channels == 4 && "WideIO comes with 4 channels"); +} + +template <> +void MemoryFactory::validate(int channels, int ranks, const Config& configs) { + assert((channels == 4 || channels == 8) && "WideIO2 comes with 4 or 8 channels"); + assert((ranks == 1 || ranks == 2) && "WideIO2 comes with 1 or 2 ranks"); +} + +template <> +void MemoryFactory::validate(int channels, int ranks, const Config& configs) { + assert(channels == 8 && "HBM comes with 8 channels"); +} + +template <> +MemoryBase *MemoryFactory::create(const Config& configs, int cacheline) { + int channels = stoi(configs["channels"], NULL, 0); + int ranks = stoi(configs["ranks"], NULL, 0); + validate(channels, ranks, configs); + + const string& org_name = configs["org"]; + const string& speed_name = configs["speed"]; + + WideIO2 *spec = new WideIO2(org_name, speed_name, channels); + + extend_channel_width(spec, cacheline); + + return (MemoryBase *)populate_memory(configs, spec, channels, ranks); +} + + +template <> +MemoryBase *MemoryFactory::create(const Config& configs, int cacheline) { + int channels = stoi(configs["channels"], NULL, 0); + int ranks = stoi(configs["ranks"], NULL, 0); + int subarrays = stoi(configs["subarrays"], NULL, 0); + validate(channels, ranks, configs); + + const string& std_name = configs["standard"]; + const string& org_name = configs["org"]; + const string& speed_name = configs["speed"]; + + SALP *spec = new SALP(org_name, speed_name, std_name, subarrays); + + extend_channel_width(spec, cacheline); + + return (MemoryBase *)populate_memory(configs, spec, channels, ranks); +} + +} + +// This function can be used by autoconf AC_CHECK_LIB since +// apparently it can't detect C++ functions. +// Basically just an entry in the symbol table +extern "C" +{ + void libramulator_is_present(void) + { + ; + } +} diff --git a/src/MemoryFactory.h b/src/MemoryFactory.h new file mode 100644 index 0000000..43fef6a --- /dev/null +++ b/src/MemoryFactory.h @@ -0,0 +1,82 @@ +#ifndef __MEMORY_FACTORY_H +#define __MEMORY_FACTORY_H + +#include +#include +#include + +#include "Config.h" +#include "Memory.h" + +#include "WideIO2.h" +#include "SALP.h" + +using namespace std; + +namespace ramulator +{ + +template +class MemoryFactory { +public: + static void extend_channel_width(T* spec, int cacheline) + { + int channel_unit = spec->prefetch_size * spec->channel_width / 8; + int gang_number = cacheline / channel_unit; + + assert(gang_number >= 1 && + "cacheline size must be greater or equal to minimum channel width"); + + assert(cacheline == gang_number * channel_unit && + "cacheline size must be a multiple of minimum channel width"); + + spec->channel_width *= gang_number; + } + + static Memory *populate_memory(const Config& configs, T *spec, int channels, int ranks) { + int& default_ranks = spec->org_entry.count[int(T::Level::Rank)]; + int& default_channels = spec->org_entry.count[int(T::Level::Channel)]; + + if (default_channels == 0) default_channels = channels; + if (default_ranks == 0) default_ranks = ranks; + + vector *> ctrls; + for (int c = 0; c < channels; c++){ + DRAM* channel = new DRAM(spec, T::Level::Channel); + channel->id = c; + channel->regStats(""); + ctrls.push_back(new Controller(configs, channel)); + } + return new Memory(configs, ctrls); + } + + static void validate(int channels, int ranks, const Config& configs) { + assert(channels > 0 && ranks > 0); + } + + static MemoryBase *create(const Config& configs, int cacheline) + { + int channels = stoi(configs["channels"], NULL, 0); + int ranks = stoi(configs["ranks"], NULL, 0); + + validate(channels, ranks, configs); + + const string& org_name = configs["org"]; + const string& speed_name = configs["speed"]; + + T *spec = new T(org_name, speed_name); + + extend_channel_width(spec, cacheline); + + return (MemoryBase *)populate_memory(configs, spec, channels, ranks); + } +}; + +template <> +MemoryBase *MemoryFactory::create(const Config& configs, int cacheline); +template <> +MemoryBase *MemoryFactory::create(const Config& configs, int cacheline); + +} /*namespace ramulator*/ + +#endif /*__MEMORY_FACTORY_H*/ diff --git a/src/Processor.cpp b/src/Processor.cpp new file mode 100644 index 0000000..724d654 --- /dev/null +++ b/src/Processor.cpp @@ -0,0 +1,420 @@ +#include "Processor.h" +#include + +using namespace std; +using namespace ramulator; + +Processor::Processor(const Config& configs, + vector trace_list, + function send_memory, + MemoryBase& memory) + : ipcs(trace_list.size(), -1), + early_exit(configs.is_early_exit()), + no_core_caches(!configs.has_core_caches()), + no_shared_cache(!configs.has_l3_cache()), + cachesys(new CacheSystem(configs, send_memory)), + llc(l3_size, l3_assoc, l3_blocksz, + mshr_per_bank * trace_list.size(), + Cache::Level::L3, cachesys) { + + assert(cachesys != nullptr); + int tracenum = trace_list.size(); + assert(tracenum > 0); + printf("tracenum: %d\n", tracenum); + for (int i = 0 ; i < tracenum ; ++i) { + printf("trace_list[%d]: %s\n", i, trace_list[i]); + } + if (no_shared_cache) { + for (int i = 0 ; i < tracenum ; ++i) { + cores.emplace_back(new Core( + configs, i, trace_list[i], send_memory, nullptr, + cachesys, memory)); + } + } else { + for (int i = 0 ; i < tracenum ; ++i) { + cores.emplace_back(new Core(configs, i, trace_list[i], + std::bind(&Cache::send, &llc, std::placeholders::_1), + &llc, cachesys, memory)); + } + } + for (int i = 0 ; i < tracenum ; ++i) { + cores[i]->callback = std::bind(&Processor::receive, this, + placeholders::_1); + } + + // regStats + cpu_cycles.name("cpu_cycles") + .desc("cpu cycle number") + .precision(0) + ; + cpu_cycles = 0; +} + +void Processor::tick() { + cpu_cycles++; + if (!(no_core_caches && no_shared_cache)) { + cachesys->tick(); + } + for (unsigned int i = 0 ; i < cores.size() ; ++i) { + Core* core = cores[i].get(); + core->tick(); + } +} + +void Processor::receive(Request& req) { + if (!no_shared_cache) { + llc.callback(req); + } else if (!cores[0]->no_core_caches) { + // Assume all cores have caches or don't have caches + // at the same time. + for (unsigned int i = 0 ; i < cores.size() ; ++i) { + Core* core = cores[i].get(); + core->caches[0]->callback(req); + } + } + for (unsigned int i = 0 ; i < cores.size() ; ++i) { + Core* core = cores[i].get(); + core->receive(req); + } +} + +bool Processor::finished() { + if (early_exit) { + for (unsigned int i = 0 ; i < cores.size(); ++i) { + if (cores[i]->finished()) { + for (unsigned int j = 0 ; j < cores.size() ; ++j) { + ipc += cores[j]->calc_ipc(); + } + return true; + } + } + return false; + } else { + for (unsigned int i = 0 ; i < cores.size(); ++i) { + if (!cores[i]->finished()) { + return false; + } + if (ipcs[i] < 0) { + ipcs[i] = cores[i]->calc_ipc(); + ipc += ipcs[i]; + } + } + return true; + } +} + +bool Processor::has_reached_limit() { + for (unsigned int i = 0 ; i < cores.size() ; ++i) { + if (!cores[i]->has_reached_limit()) { + return false; + } + } + return true; +} + +Core::Core(const Config& configs, int coreid, + const char* trace_fname, function send_next, + Cache* llc, std::shared_ptr cachesys, MemoryBase& memory) + : id(coreid), no_core_caches(!configs.has_core_caches()), + no_shared_cache(!configs.has_l3_cache()), + llc(llc), trace(trace_fname), memory(memory) +{ + // Build cache hierarchy + if (no_core_caches) { + send = send_next; + } else { + // L2 caches[0] + caches.emplace_back(new Cache( + l2_size, l2_assoc, l2_blocksz, l2_mshr_num, + Cache::Level::L2, cachesys)); + // L1 caches[1] + caches.emplace_back(new Cache( + l1_size, l1_assoc, l1_blocksz, l1_mshr_num, + Cache::Level::L1, cachesys)); + send = bind(&Cache::send, caches[1].get(), placeholders::_1); + if (llc != nullptr) { + caches[0]->concatlower(llc); + } + caches[1]->concatlower(caches[0].get()); + } + if (no_core_caches) { + more_reqs = trace.get_filtered_request( + bubble_cnt, req_addr, req_type); + req_addr = memory.page_allocator(req_addr, id); + } else { + more_reqs = trace.get_unfiltered_request( + bubble_cnt, req_addr, req_type); + req_addr = memory.page_allocator(req_addr, id); + } + + // set expected limit instruction for calculating weighted speedup + expected_limit_insts = configs.get_expected_limit_insts(); + + // regStats + record_cycs.name("record_cycs_core_" + to_string(id)) + .desc("Record cycle number for calculating weighted speedup. (Only valid when expected limit instruction number is non zero in config file.)") + .precision(0) + ; + + record_insts.name("record_insts_core_" + to_string(id)) + .desc("Retired instruction number when record cycle number. (Only valid when expected limit instruction number is non zero in config file.)") + .precision(0) + ; + + memory_access_cycles.name("memory_access_cycles_core_" + to_string(id)) + .desc("memory access cycles in memory time domain") + .precision(0) + ; + memory_access_cycles = 0; + cpu_inst.name("cpu_instructions_core_" + to_string(id)) + .desc("cpu instruction number") + .precision(0) + ; + cpu_inst = 0; +} + + +double Core::calc_ipc() +{ + printf("[%d]retired: %ld, clk, %ld\n", id, retired, clk); + return (double) retired / clk; +} + +void Core::tick() +{ + clk++; + + retired += window.retire(); + + if (expected_limit_insts == 0 && !more_reqs) return; + + // bubbles (non-memory operations) + int inserted = 0; + while (bubble_cnt > 0) { + if (inserted == window.ipc) return; + if (window.is_full()) return; + + window.insert(true, -1); + inserted++; + bubble_cnt--; + cpu_inst++; + if (long(cpu_inst.value()) == expected_limit_insts && !reached_limit) { + record_cycs = clk; + record_insts = long(cpu_inst.value()); + memory.record_core(id); + reached_limit = true; + } + } + + if (req_type == Request::Type::READ) { + // read request + if (inserted == window.ipc) return; + if (window.is_full()) return; + + Request req(req_addr, req_type, callback, id); + if (!send(req)) return; + + window.insert(false, req_addr); + cpu_inst++; + } + else { + // write request + assert(req_type == Request::Type::WRITE); + Request req(req_addr, req_type, callback, id); + if (!send(req)) return; + cpu_inst++; + } + if (long(cpu_inst.value()) == expected_limit_insts && !reached_limit) { + record_cycs = clk; + record_insts = long(cpu_inst.value()); + memory.record_core(id); + reached_limit = true; + } + + if (no_core_caches) { + more_reqs = trace.get_filtered_request( + bubble_cnt, req_addr, req_type); + if (req_addr != -1) { + req_addr = memory.page_allocator(req_addr, id); + } + } else { + more_reqs = trace.get_unfiltered_request( + bubble_cnt, req_addr, req_type); + if (req_addr != -1) { + req_addr = memory.page_allocator(req_addr, id); + } + } + if (!more_reqs) { + if (!reached_limit) { // if the length of this trace is shorter than expected length, then record it when the whole trace finishes, and set reached_limit to true. + record_cycs = clk; + record_insts = long(cpu_inst.value()); + memory.record_core(id); + reached_limit = true; + } + } +} + +bool Core::finished() +{ + return !more_reqs && window.is_empty(); +} + +bool Core::has_reached_limit() { + return reached_limit; +} + +void Core::receive(Request& req) +{ + window.set_ready(req.addr, ~(l1_blocksz - 1l)); + if (req.arrive != -1 && req.depart > last) { + memory_access_cycles += (req.depart - max(last, req.arrive)); + last = req.depart; + } +} + +bool Window::is_full() +{ + return load == depth; +} + +bool Window::is_empty() +{ + return load == 0; +} + + +void Window::insert(bool ready, long addr) +{ + assert(load <= depth); + + ready_list.at(head) = ready; + addr_list.at(head) = addr; + + head = (head + 1) % depth; + load++; +} + + +long Window::retire() +{ + assert(load <= depth); + + if (load == 0) return 0; + + int retired = 0; + while (load > 0 && retired < ipc) { + if (!ready_list.at(tail)) + break; + + tail = (tail + 1) % depth; + load--; + retired++; + } + + return retired; +} + + +void Window::set_ready(long addr, int mask) +{ + if (load == 0) return; + + for (int i = 0; i < load; i++) { + int index = (tail + i) % depth; + if ((addr_list.at(index) & mask) != (addr & mask)) + continue; + ready_list.at(index) = true; + } +} + + + +Trace::Trace(const char* trace_fname) : file(trace_fname), trace_name(trace_fname) +{ + if (!file.good()) { + std::cerr << "Bad trace file: " << trace_fname << std::endl; + exit(1); + } +} + +bool Trace::get_unfiltered_request(long& bubble_cnt, long& req_addr, Request::Type& req_type) +{ + string line; + getline(file, line); + if (file.eof()) { + file.clear(); + file.seekg(0, file.beg); + return false; + } + size_t pos, end; + bubble_cnt = std::stoul(line, &pos, 10); + pos = line.find_first_not_of(' ', pos+1); + req_addr = std::stoul(line.substr(pos), &end, 0); + + pos = line.find_first_not_of(' ', pos+end); + + if (pos == string::npos || line.substr(pos)[0] == 'R') + req_type = Request::Type::READ; + else if (line.substr(pos)[0] == 'W') + req_type = Request::Type::WRITE; + else assert(false); + return true; +} + +bool Trace::get_filtered_request(long& bubble_cnt, long& req_addr, Request::Type& req_type) +{ + static bool has_write = false; + static long write_addr; + static int line_num = 0; + if (has_write){ + bubble_cnt = 0; + req_addr = write_addr; + req_type = Request::Type::WRITE; + has_write = false; + return true; + } + string line; + getline(file, line); + line_num ++; + if (file.eof() || line.size() == 0) { + file.clear(); + file.seekg(0, file.beg); + has_write = false; + line_num = 0; + return false; + } + + size_t pos, end; + bubble_cnt = std::stoul(line, &pos, 10); + + pos = line.find_first_not_of(' ', pos+1); + req_addr = stoul(line.substr(pos), &end, 0); + req_type = Request::Type::READ; + + pos = line.find_first_not_of(' ', pos+end); + if (pos != string::npos){ + has_write = true; + write_addr = stoul(line.substr(pos), NULL, 0); + } + return true; +} + +bool Trace::get_dramtrace_request(long& req_addr, Request::Type& req_type) +{ + string line; + getline(file, line); + if (file.eof()) { + return false; + } + size_t pos; + req_addr = std::stoul(line, &pos, 16); + + pos = line.find_first_not_of(' ', pos+1); + + if (pos == string::npos || line.substr(pos)[0] == 'R') + req_type = Request::Type::READ; + else if (line.substr(pos)[0] == 'W') + req_type = Request::Type::WRITE; + else assert(false); + return true; +} diff --git a/src/Processor.h b/src/Processor.h new file mode 100644 index 0000000..2023062 --- /dev/null +++ b/src/Processor.h @@ -0,0 +1,141 @@ +#ifndef __PROCESSOR_H +#define __PROCESSOR_H + +#include "Cache.h" +#include "Config.h" +#include "Memory.h" +#include "Request.h" +#include "Statistics.h" +#include +#include +#include +#include +#include +#include + +namespace ramulator +{ + +class Trace { +public: + Trace(const char* trace_fname); + // trace file format 1: + // [# of bubbles(non-mem instructions)] [read address(dec or hex)] + bool get_unfiltered_request(long& bubble_cnt, long& req_addr, Request::Type& req_type); + bool get_filtered_request(long& bubble_cnt, long& req_addr, Request::Type& req_type); + // trace file format 2: + // [address(hex)] [R/W] + bool get_dramtrace_request(long& req_addr, Request::Type& req_type); + +private: + std::ifstream file; + std::string trace_name; +}; + + +class Window { +public: + int ipc = 4; + int depth = 128; + + Window() : ready_list(depth), addr_list(depth, -1) {} + bool is_full(); + bool is_empty(); + void insert(bool ready, long addr); + long retire(); + void set_ready(long addr, int mask); + +private: + int load = 0; + int head = 0; + int tail = 0; + std::vector ready_list; + std::vector addr_list; +}; + + +class Core { +public: + long clk = 0; + long retired = 0; + int id = 0; + function send; + + Core(const Config& configs, int coreid, + const char* trace_fname, + function send_next, Cache* llc, + std::shared_ptr cachesys, MemoryBase& memory); + void tick(); + void receive(Request& req); + double calc_ipc(); + bool finished(); + bool has_reached_limit(); + function callback; + + bool no_core_caches = true; + bool no_shared_cache = true; + int l1_size = 1 << 15; + int l1_assoc = 1 << 3; + int l1_blocksz = 1 << 6; + int l1_mshr_num = 16; + + int l2_size = 1 << 18; + int l2_assoc = 1 << 3; + int l2_blocksz = 1 << 6; + int l2_mshr_num = 16; + std::vector> caches; + Cache* llc; + + ScalarStat record_cycs; + ScalarStat record_insts; + long expected_limit_insts; + // This is set true iff expected number of instructions has been executed or all instructions are executed. + bool reached_limit = false; + +private: + Trace trace; + Window window; + + long bubble_cnt; + long req_addr = -1; + Request::Type req_type; + bool more_reqs; + long last = 0; + + ScalarStat memory_access_cycles; + ScalarStat cpu_inst; + MemoryBase& memory; +}; + +class Processor { +public: + Processor(const Config& configs, vector trace_list, + function send, MemoryBase& memory); + void tick(); + void receive(Request& req); + bool finished(); + bool has_reached_limit(); + + std::vector> cores; + std::vector ipcs; + double ipc = 0; + + // When early_exit is true, the simulation exits when the earliest trace finishes. + bool early_exit; + + bool no_core_caches = true; + bool no_shared_cache = true; + + int l3_size = 1 << 23; + int l3_assoc = 1 << 3; + int l3_blocksz = 1 << 6; + int mshr_per_bank = 16; + + std::shared_ptr cachesys; + Cache llc; + + ScalarStat cpu_cycles; +}; + +} +#endif /* __PROCESSOR_H */ diff --git a/src/Refresh.cpp b/src/Refresh.cpp new file mode 100644 index 0000000..b3b59ce --- /dev/null +++ b/src/Refresh.cpp @@ -0,0 +1,255 @@ +/* + * Refresh.cpp + * + * Mainly DSARP specialization at the moment. + * + * Created on: Mar 17, 2015 + * Author: kevincha + */ + +#include + +#include "Refresh.h" +#include "Controller.h" +#include "DRAM.h" +#include "DSARP.h" + +using namespace std; +using namespace ramulator; + +namespace ramulator { + +/**** DSARP specialization ****/ +template<> +Refresh::Refresh(Controller* ctrl) : ctrl(ctrl) { + clk = refreshed = 0; + max_rank_count = ctrl->channel->children.size(); + max_bank_count = ctrl->channel->spec->org_entry.count[(int)DSARP::Level::Bank]; + max_sa_count = ctrl->channel->spec->org_entry.count[(int)DSARP::Level::SubArray]; + + // Init refresh counters + for (int r = 0; r < max_rank_count; r++) { + bank_ref_counters.push_back(0); + bank_refresh_backlog.push_back(new vector(max_bank_count, 0)); + vector sa_counters(ctrl->channel->spec->org_entry.count[(int)DSARP::Level::SubArray], 0); + subarray_ref_counters.push_back(sa_counters); + } + + level_chan = (int)DSARP::Level::Channel; + level_rank = (int)DSARP::Level::Rank; + level_bank = (int)DSARP::Level::Bank; + level_sa = (int)DSARP::Level::SubArray; +} + +template<> +void Refresh::early_inject_refresh() { + // Only enabled during reads + if (ctrl->write_mode) + return; + + // OoO bank-level refresh + vector is_bank_occupied(max_rank_count * max_bank_count, false); + Controller::Queue& rdq = ctrl->readq; + + // Figure out which banks are idle in order to refresh one of them + for (auto req: rdq.q) + { + assert(req.addr_vec[level_chan] == ctrl->channel->id); + int ridx = req.addr_vec[level_rank] * max_bank_count; + int bidx = req.addr_vec[level_bank]; + is_bank_occupied[ridx+bidx] = true; + } + + // Try to pick an idle bank to refresh per rank + for (int r = 0; r < max_rank_count; r++) { + // Randomly pick a bank to examine + int bidx_start = rand() % max_bank_count; + + for (int b = 0; b < max_bank_count; b++) + { + int bidx = (bidx_start + b) % max_bank_count; + // Idle cycle only + if (is_bank_occupied[(r * max_bank_count) + bidx]) + continue; + + // Pending refresh + bool pending_ref = false; + for (Request req : ctrl->otherq.q) + if (req.type == Request::Type::REFRESH + && req.addr_vec[level_chan] == ctrl->channel->id + && req.addr_vec[level_rank] == r && req.addr_vec[level_bank] == bidx) + pending_ref = true; + if (pending_ref) + continue; + + // Only pull in refreshes when we are almost running out of credits + if ((*(bank_refresh_backlog[r]))[bidx] >= backlog_early_pull_threshold || + ctrl->otherq.q.size() >= ctrl->otherq.max) + continue; + + // Refresh now + refresh_target(ctrl, r, bidx, subarray_ref_counters[r][bidx]); + // One credit for delaying a future ref + (*(bank_refresh_backlog[r]))[bidx]++; + subarray_ref_counters[r][bidx] = (subarray_ref_counters[r][bidx]+1) % max_sa_count; + break; + } + } +} + +template<> +void Refresh::inject_refresh(bool b_ref_rank) { + // Rank-level refresh + if (b_ref_rank) + for (auto rank : ctrl->channel->children) + refresh_target(ctrl, rank->id, -1, -1); + // Bank-level refresh. Simultaneously issue to all ranks (better performance than staggered refreshes). + else { + for (auto rank : ctrl->channel->children) { + int rid = rank->id; + int bid = bank_ref_counters[rid]; + + // Behind refresh schedule by 1 ref + (*(bank_refresh_backlog[rid]))[bid]--; + + // Next time, refresh the next bank in the same bank + bank_ref_counters[rid] = (bank_ref_counters[rid] + 1) % max_bank_count; + + // Check to see if we can skip a refresh + if (ctrl->channel->spec->type == DSARP::Type::DARP || + ctrl->channel->spec->type == DSARP::Type::DSARP) { + + bool ref_now = false; + // 1. Any pending refrehes? + bool pending_ref = false; + for (Request req : ctrl->otherq.q) { + if (req.type == Request::Type::REFRESH) { + pending_ref = true; + break; + } + } + + // 2. Track readq + if (!pending_ref && ctrl->readq.size() == 0) + ref_now = true; + + // 3. Track log status. If we are too behind the schedule, then we need to refresh now. + if ((*(bank_refresh_backlog[rid]))[bid] <= backlog_min) + ref_now = true; + + // Otherwise skip refresh + if (!ref_now) + continue; + } + + refresh_target(ctrl, rid, bid, subarray_ref_counters[rid][bid]); + // Get 1 ref credit + (*(bank_refresh_backlog[rid]))[bid]++; + // Next time, refresh the next sa in the same bank + subarray_ref_counters[rid][bid] = (subarray_ref_counters[rid][bid]+1) % max_sa_count; + } + } + refreshed = clk; +} + +// first = wrq.count; second = bank idx +typedef pair wrq_idx; +bool wrq_comp (wrq_idx l, wrq_idx r) +{ + return l.first < r.first; +} + +// WRP +template<> +void Refresh::wrp() { + for (int ref_rid = 0; ref_rid < max_rank_count; ref_rid++) + { + // Pending refresh in the rank? + bool pending_ref = false; + for (Request req : ctrl->otherq.q) { + if (req.type == Request::Type::REFRESH && req.addr_vec[level_rank] == ref_rid) { + pending_ref = true; + break; + } + } + if (pending_ref) + continue; + + // Find the bank with the lowest number of writes+reads + vector sorted_bank_demand; + for (int b = 0; b < max_bank_count; b++) + sorted_bank_demand.push_back(wrq_idx(0,b)); + // Filter out all the writes to this rank + int total_wr = 0; + for (auto req : ctrl->writeq.q) { + if (req.addr_vec[level_rank] == ref_rid) { + sorted_bank_demand[req.addr_vec[level_bank]].first++; + total_wr++; + } + } + // If there's no write, just skip. + if (total_wr == 0) + continue; + + // Add read + for (auto req : ctrl->readq.q) + if (req.addr_vec[level_rank] == ref_rid) + sorted_bank_demand[req.addr_vec[level_bank]].first++; + + // Sort based on the entries + std::sort(sorted_bank_demand.begin(), sorted_bank_demand.end(), wrq_comp); + + // Randomly select an idle bank to refresh + int top_idle_idx = 0; + for (int i = 0; i < max_bank_count; i++) { + if (sorted_bank_demand[i].second != 0) { + top_idle_idx = i; + break; + } + } + + // Select a bank to ref + int ref_bid_idx = (top_idle_idx == 0) ? 0 : rand() % top_idle_idx; + int ref_bid = sorted_bank_demand[ref_bid_idx].second; + + // Make sure we don't exceed the credit + if ((*(bank_refresh_backlog[ref_rid]))[ref_bid] < backlog_max + && ctrl->otherq.q.size() < ctrl->otherq.max) { + refresh_target(ctrl, ref_rid, ref_bid, subarray_ref_counters[ref_rid][ref_bid]); + // Get 1 ref credit + (*(bank_refresh_backlog[ref_rid]))[ref_bid]++; + subarray_ref_counters[ref_rid][ref_bid] = (subarray_ref_counters[ref_rid][ref_bid]+1) % max_sa_count; + } + } +} + +// OoO refresh of DSARP +template<> +void Refresh::tick_ref() { + clk++; + + bool b_ref_rank = ctrl->channel->spec->b_ref_rank; + int refresh_interval = + (b_ref_rank) ? + ctrl->channel->spec->speed_entry.nREFI : + ctrl->channel->spec->speed_entry.nREFIpb; + + // DARP + if (ctrl->channel->spec->type == DSARP::Type::DARP || + ctrl->channel->spec->type == DSARP::Type::DSARP) { + // Write-Refresh Parallelization. Issue refreshes when the controller enters writeback mode + if (!ctrl_write_mode && ctrl->write_mode) + wrp(); + // Record write mode + ctrl_write_mode = ctrl->write_mode; + // Inject early to pull in some refreshes during read mode + early_inject_refresh(); + } + + // Time to schedule a refresh and also try to skip some refreshes + if ((clk - refreshed) >= refresh_interval) + inject_refresh(b_ref_rank); +} +/**** End DSARP specialization ****/ + +} /* namespace ramulator */ diff --git a/src/Refresh.h b/src/Refresh.h new file mode 100644 index 0000000..a0549ff --- /dev/null +++ b/src/Refresh.h @@ -0,0 +1,138 @@ +/* + * Refresh.h + * + * This is a refresh scheduler. A list of refresh policies implemented: + * + * 1. All-bank refresh + * 2. Per-bank refresh (only DSARP memory module has been completed to work with REFpb). + * The other modules (LPDDRx) have not been updated to pass a knob to turn on/off REFpb. + * 3. A re-implementation of DSARP from the refresh mechanisms proposed in Chang et al., + * "Improving DRAM Performance by Parallelizing Refreshes with Accesses", HPCA 2014. + * + * Created on: Mar 17, 2015 + * Author: kevincha + */ + +#ifndef __REFRESH_H_ +#define __REFRESH_H_ + +#include +#include +#include +#include + +#include "Request.h" +#include "DSARP.h" +#include "ALDRAM.h" + +using namespace std; +using namespace ramulator; + +namespace ramulator { + +template +class Controller; + +template +class Refresh { +public: + Controller* ctrl; + long clk, refreshed; + // Per-bank refresh counter to track the refresh progress for each rank + vector bank_ref_counters; + int max_rank_count, max_bank_count; + int level_chan, level_rank, level_bank, level_sa; + + // ctor + Refresh(Controller* ctrl) : ctrl(ctrl) { + clk = refreshed = 0; + max_rank_count = ctrl->channel->children.size(); + max_bank_count = ctrl->channel->spec->org_entry.count[(int)T::Level::Bank]; + + // Init refresh counters + for (int r = 0; r < max_rank_count; r++) { + bank_ref_counters.push_back(0); + bank_refresh_backlog.push_back(new vector(max_bank_count, 0)); + } + + level_chan = (int)T::Level::Channel; + level_rank = (int)T::Level::Rank; + level_bank = (int)T::Level::Bank; + level_sa = -1; // Most DRAM doesn't have subarray level + } + + // dtor + virtual ~Refresh() { + // Clean up backlog + for (unsigned int i = 0; i < bank_refresh_backlog.size(); i++) + delete bank_refresh_backlog[i]; + } + + // Basic refresh scheduling for all bank refresh that is applicable to all DRAM types + void tick_ref() { + clk++; + + int refresh_interval = ctrl->channel->spec->speed_entry.nREFI; + + // Time to schedule a refresh + if ((clk - refreshed) >= refresh_interval) { + inject_refresh(true); + // ALDRAM: update timing parameters based on temperatures + ALDRAM::Temp current_temperature = ALDRAM::Temp::COLD; + ctrl->update_temp(current_temperature); + } + } + +private: + // Keeping track of refresh status of every bank: + means ahead of schedule, - means behind schedule + vector*> bank_refresh_backlog; + // Keeping track of which subarray to refresh next + vector> subarray_ref_counters; + int max_sa_count = 0; + // As defined in the standards + int backlog_max = 8; + int backlog_min = -8; + int backlog_early_pull_threshold = -6; + bool ctrl_write_mode = false; + + // Refresh based on the specified address + void refresh_target(Controller* ctrl, int rank, int bank, int sa) + { + vector addr_vec(int(T::Level::MAX), -1); + addr_vec[0] = ctrl->channel->id; + addr_vec[1] = rank; + addr_vec[2] = bank; + addr_vec[3] = sa; + Request req(addr_vec, Request::Type::REFRESH, NULL); + bool res = ctrl->enqueue(req); + assert(res); + } + + // Inject refresh at either rank or bank level + void inject_refresh(bool b_ref_rank) { + // Rank-level refresh + if (b_ref_rank) { + for (auto rank : ctrl->channel->children) + refresh_target(ctrl, rank->id, -1, -1); + } + // Bank-level refresh. Simultaneously issue to all ranks (better performance than staggered refreshes). + else { + for (auto rank : ctrl->channel->children) + refresh_target(ctrl, rank->id, bank_ref_counters[rank->id], -1); + } + refreshed = clk; + } + + // DSARP + void early_inject_refresh(); + void wrp(); +}; + +// Declaration of specialized constructor and tick_ref, so the compiler knows +// where to look for these definitions when controller calls them! +template<> Refresh::Refresh(Controller* ctrl); +template<> void Refresh::tick_ref(); + +} /* namespace ramulator */ + +#endif /* SRC_REFRESH_H_ */ diff --git a/src/Request.h b/src/Request.h new file mode 100644 index 0000000..539aae8 --- /dev/null +++ b/src/Request.h @@ -0,0 +1,81 @@ +#ifndef __REQUEST_H +#define __REQUEST_H + +#include +#include +#include + +using namespace std; + +namespace ramulator +{ + //----------------------------- + // User defined member + // ---------------------------- + + struct UDF{ + long burstIdx; + long reqIdx; + int peIdx; + + long departPeTime; + long arriveMemTime; + long departMemTime; + long arrivePeTime; + }; + + class Request + { + public: + bool is_first_command; + long addr; + + // long addr_row; + // It specifies the id of the memory + // hierarchy such as channel id, rank id, + // bank id, row id, column id + vector addr_vec; + + // specify which core this request sent from, for virtual address translation + int coreid; + + UDF udf; + + enum class Type + { + READ, + WRITE, + REFRESH, + POWERDOWN, + SELFREFRESH, + EXTENSION, + MAX + } type; + + long arrive = -1; + long depart; + function callback; // call back with more info + + Request(long addr, Type type, int coreid = 0) + : is_first_command(true), addr(addr), coreid(coreid), type(type), + callback([](Request& req){}) { + } + + Request(long addr, Type type, function callback, int coreid = 0) + : is_first_command(true), addr(addr), coreid(coreid), type(type), callback(callback) { + } + + Request(vector& addr_vec, Type type, function callback, int coreid = 0) + : is_first_command(true), addr_vec(addr_vec), coreid(coreid), type(type), callback(callback) { + } + + Request() + : is_first_command(true), coreid(0) { + } + }; + + +} /*namespace ramulator*/ + +#endif /*__REQUEST_H*/ + diff --git a/src/SALP.cpp b/src/SALP.cpp new file mode 100644 index 0000000..d5e418a --- /dev/null +++ b/src/SALP.cpp @@ -0,0 +1,646 @@ +#include "SALP.h" +#include "DRAM.h" +#include +#include +#include + +using namespace ramulator; + +map SALP::org_map = { + {"SALP_512Mb_x4", SALP::Org::SALP_512Mb_x4}, {"SALP_512Mb_x8", SALP::Org::SALP_512Mb_x8}, {"SALP_512Mb_x16", SALP::Org::SALP_512Mb_x16}, + {"SALP_1Gb_x4", SALP::Org::SALP_1Gb_x4}, {"SALP_1Gb_x8", SALP::Org::SALP_1Gb_x8}, {"SALP_1Gb_x16", SALP::Org::SALP_1Gb_x16}, + {"SALP_2Gb_x4", SALP::Org::SALP_2Gb_x4}, {"SALP_2Gb_x8", SALP::Org::SALP_2Gb_x8}, {"SALP_2Gb_x16", SALP::Org::SALP_2Gb_x16}, + {"SALP_4Gb_x4", SALP::Org::SALP_4Gb_x4}, {"SALP_4Gb_x8", SALP::Org::SALP_4Gb_x8}, {"SALP_4Gb_x16", SALP::Org::SALP_4Gb_x16}, + {"SALP_8Gb_x4", SALP::Org::SALP_8Gb_x4}, {"SALP_8Gb_x8", SALP::Org::SALP_8Gb_x8}, {"SALP_8Gb_x16", SALP::Org::SALP_8Gb_x16}, +}; + +map SALP::speed_map = { + {"SALP_800D", SALP::Speed::SALP_800D}, {"SALP_800E", SALP::Speed::SALP_800E}, + {"SALP_1066E", SALP::Speed::SALP_1066E}, {"SALP_1066F", SALP::Speed::SALP_1066F}, {"SALP_1066G", SALP::Speed::SALP_1066G}, + {"SALP_1333G", SALP::Speed::SALP_1333G}, {"SALP_1333H", SALP::Speed::SALP_1333H}, + {"SALP_1600H", SALP::Speed::SALP_1600H}, {"SALP_1600J", SALP::Speed::SALP_1600J}, {"SALP_1600K", SALP::Speed::SALP_1600K}, + {"SALP_1866K", SALP::Speed::SALP_1866K}, {"SALP_1866L", SALP::Speed::SALP_1866L}, + {"SALP_2133L", SALP::Speed::SALP_2133L}, {"SALP_2133M", SALP::Speed::SALP_2133M}, +}; + +map SALP::type_map = { + {"SALP-1", SALP::Type::SALP_1}, + {"SALP-2", SALP::Type::SALP_2}, + {"SALP-MASA", SALP::Type::MASA}, +}; + +SALP::SALP(Org org, Speed speed, Type type, int n_sa) : + type(type), + n_sa(n_sa), + org_entry(org_table[int(org)]), + speed_entry(speed_table[int(speed)]), + read_latency(speed_entry.nCL + speed_entry.nBL) +{ + switch(int(type)){ + case int(Type::SALP_1): standard_name = "SALP-1"; break; + case int(Type::SALP_2): standard_name = "SALP-2"; break; + case int(Type::MASA): standard_name = "SALP-MASA"; break; + } + if (type == Type::SALP_1) { + scope[int(Command::PRE)] = Level::Bank; + } + assert(n_sa && n_sa <= 128 && (n_sa & (n_sa-1)) == 0); // is power of 2, within [1, 128] + org_entry.count[int(Level::SubArray)] = n_sa; + long tmp = long(org_entry.dq) * org_entry.count[int(Level::Bank)] * n_sa * org_entry.count[int(Level::Column)]; + org_entry.count[int(Level::Row)] = long(org_entry.size) * (1<<20) / tmp; + init_speed(); + init_prereq(); + init_rowhit(); // SAUGATA: added row hit function + init_rowopen(); + init_lambda(); + init_timing(); +} + +SALP::SALP(const string& org_str, const string& speed_str, const string& type_str, int n_sa) : + SALP(org_map[org_str], speed_map[speed_str], type_map[type_str], n_sa) +{ +} + +void SALP::set_channel_number(int channel) { + org_entry.count[int(Level::Channel)] = channel; +} + +void SALP::set_rank_number(int rank) { + org_entry.count[int(Level::Rank)] = rank; +} + +void SALP::init_speed() +{ + // nRRD, nFAW + int page = (org_entry.dq * org_entry.count[int(Level::Column)]) >> 13; + switch (speed_entry.rate) { + case 800: speed_entry.nRRD = (page==1) ? 4 : 4; speed_entry.nFAW = (page==1) ? 16 : 20; break; + case 1066: speed_entry.nRRD = (page==1) ? 4 : 6; speed_entry.nFAW = (page==1) ? 20 : 27; break; + case 1333: speed_entry.nRRD = (page==1) ? 4 : 5; speed_entry.nFAW = (page==1) ? 20 : 30; break; + case 1600: speed_entry.nRRD = (page==1) ? 5 : 6; speed_entry.nFAW = (page==1) ? 24 : 32; break; + case 1866: speed_entry.nRRD = (page==1) ? 5 : 6; speed_entry.nFAW = (page==1) ? 26 : 33; break; + case 2133: speed_entry.nRRD = (page==1) ? 5 : 6; speed_entry.nFAW = (page==1) ? 27 : 34; break; + default: assert(false); + } + + // nRFC, nXS + int chip = org_entry.size; + switch (speed_entry.rate) { + case 800: speed_entry.nRFC = (chip==512) ? 36 : (chip==1<<10) ? 44 : (chip==1<<11) ? 64 : (chip==1<<12) ? 104 : 140; break; + case 1066: speed_entry.nRFC = (chip==512) ? 48 : (chip==1<<10) ? 59 : (chip==1<<11) ? 86 : (chip==1<<12) ? 139 : 187; break; + case 1333: speed_entry.nRFC = (chip==512) ? 60 : (chip==1<<10) ? 74 : (chip==1<<11) ? 107 : (chip==1<<12) ? 174 : 234; break; + case 1600: speed_entry.nRFC = (chip==512) ? 72 : (chip==1<<10) ? 88 : (chip==1<<11) ? 128 : (chip==1<<12) ? 208 : 280; break; + case 1866: speed_entry.nRFC = (chip==512) ? 84 : (chip==1<<10) ? 103 : (chip==1<<11) ? 150 : (chip==1<<12) ? 243 : 327; break; + case 2133: speed_entry.nRFC = (chip==512) ? 96 : (chip==1<<10) ? 118 : (chip==1<<11) ? 171 : (chip==1<<12) ? 278 : 374; break; + default: assert(false); + } + switch (speed_entry.rate) { + case 800: speed_entry.nXS = (chip==512) ? 40 : (chip==1<<10) ? 48 : (chip==1<<11) ? 68 : (chip==1<<12) ? 108 : 144; break; + case 1066: speed_entry.nXS = (chip==512) ? 54 : (chip==1<<10) ? 64 : (chip==1<<11) ? 91 : (chip==1<<12) ? 144 : 192; break; + case 1333: speed_entry.nXS = (chip==512) ? 67 : (chip==1<<10) ? 80 : (chip==1<<11) ? 114 : (chip==1<<12) ? 180 : 240; break; + case 1600: speed_entry.nXS = (chip==512) ? 80 : (chip==1<<10) ? 96 : (chip==1<<11) ? 136 : (chip==1<<12) ? 216 : 288; break; + case 1866: speed_entry.nXS = (chip==512) ? 94 : (chip==1<<10) ? 112 : (chip==1<<11) ? 159 : (chip==1<<12) ? 252 : 336; break; + case 2133: speed_entry.nXS = (chip==512) ? 107 : (chip==1<<10) ? 128 : (chip==1<<11) ? 182 : (chip==1<<12) ? 288 : 384; break; + default: assert(false); + } +} + + +void SALP::init_prereq() +{ + prereq[int(Level::Rank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::PowerUp): return Command::MAX; + case int(State::ActPowerDown): return Command::PDX; + case int(State::PrePowerDown): return Command::PDX; + case int(State::SelfRefresh): return Command::SRX; + default: assert(false); + }}; + prereq[int(Level::Rank)][int(Command::WR)] = prereq[int(Level::Rank)][int(Command::RD)]; + + switch(int(type)){ + case int(Type::SALP_1): + prereq[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)){ + case int(State::Closed): return Command::ACT; + case int(State::Opened): + return Command::MAX; + default: assert(false);}}; + prereq[int(Level::Bank)][int(Command::WR)] = prereq[int(Level::Bank)][int(Command::RD)]; + prereq[int(Level::SubArray)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + if (node->row_state.find(id) != node->row_state.end()) { + return cmd; + } else if (node->row_state.size()) { + return Command::PRE; + } else { + return Command::PRE_OTHER; + } + }; + prereq[int(Level::SubArray)][int(Command::WR)] = prereq[int(Level::SubArray)][int(Command::RD)]; + prereq[int(Level::Rank)][int(Command::REF)] = [] (DRAM* node, Command cmd, int id) { + for (auto bank : node->children) { + if (bank->state == State::Closed) + continue; + return Command::PRER; + } + return Command::REF;}; + break; + case int(Type::SALP_2): + prereq[int(Level::SubArray)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)){ + case int(State::Closed): return Command::ACT; + case int(State::Opened): + if (node->row_state.find(id) != node->row_state.end()) { + for (auto sa : node->parent->children) { + if (sa != node && sa->state == State::Opened) { + return Command::PRE_OTHER; + } + } + return cmd; + } else { + // if this subarray has another row open, close it + // first + return Command::PRE; + } + default: assert(false);}}; + prereq[int(Level::SubArray)][int(Command::WR)] = prereq[int(Level::SubArray)][int(Command::RD)]; + prereq[int(Level::Rank)][int(Command::REF)] = [] (DRAM* node, Command cmd, int id) { + for (auto bank : node->children) + for (auto sa : bank->children) { + if (sa->state == State::Closed) + continue; + return Command::PRER; + } + return Command::REF;}; + break; + case int(Type::MASA): + prereq[int(Level::SubArray)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)){ + case int(State::Closed): return Command::ACT; + case int(State::Opened): + if (node->row_state.find(id) != node->row_state.end()) return Command::SASEL; + else return Command::PRE; + case int(State::Selected): + if (node->row_state.find(id) != node->row_state.end()) return cmd; + else return Command::PRE; + default: assert(false); + }}; + prereq[int(Level::SubArray)][int(Command::WR)] = prereq[int(Level::SubArray)][int(Command::RD)]; + prereq[int(Level::Rank)][int(Command::REF)] = [] (DRAM* node, Command cmd, int id) { + for (auto bank : node->children) + for (auto sa : bank->children){ + if (sa->state == State::Closed) + continue; + return Command::PRER; + } + return Command::REF;}; + break; + default: assert(false); + } + // PD + prereq[int(Level::Rank)][int(Command::PDE)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::PowerUp): return Command::PDE; + case int(State::ActPowerDown): return Command::PDE; + case int(State::PrePowerDown): return Command::PDE; + case int(State::SelfRefresh): return Command::SRX; + default: assert(false); + }}; + + // SR + prereq[int(Level::Rank)][int(Command::SRE)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::PowerUp): return Command::SRE; + case int(State::ActPowerDown): return Command::PDX; + case int(State::PrePowerDown): return Command::PDX; + case int(State::SelfRefresh): return Command::SRE; + default: assert(false); + }}; +} + +// SAUGATA: added row hit check functions to see if the desired location is currently open +void SALP::init_rowhit() +{ + switch(int(type)) { + case int(Type::SALP_1): + // RD + rowhit[int(Level::SubArray)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::Closed): return false; + case int(State::Opened): + if (node->row_state.find(id) != node->row_state.end()) return true; + else return false; + default: assert(false); + } + }; + // WR + rowhit[int(Level::SubArray)][int(Command::WR)] = rowhit[int(Level::SubArray)][int(Command::RD)]; + break; + case int(Type::SALP_2): + // RD + rowhit[int(Level::SubArray)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)){ + case int(State::Closed): return false; + case int(State::Opened): + if (node->row_state.find(id) != node->row_state.end()) return true; + else return false; + default: assert(false); + }}; + // WR + rowhit[int(Level::SubArray)][int(Command::WR)] = rowhit[int(Level::SubArray)][int(Command::RD)]; + break; + case int(Type::MASA): + // RD + rowhit[int(Level::SubArray)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)){ + case int(State::Closed): return false; + case int(State::Opened): + // opened but not selected still counts as a row hit + if (node->row_state.find(id) != node->row_state.end()) return true; + else return false; + case int(State::Selected): + if (node->row_state.find(id) != node->row_state.end()) return true; + else return false; + default: assert(false); + }}; + // WR + rowhit[int(Level::SubArray)][int(Command::WR)] = rowhit[int(Level::SubArray)][int(Command::RD)]; + break; + default: assert(false); + } +} + +void SALP::init_rowopen() +{ + switch(int(type)) { + case int(Type::SALP_1): + // RD + rowopen[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)){ + case int(State::Closed): return false; + case int(State::Opened): return true; + default: assert(false); + }}; + // WR + rowopen[int(Level::Bank)][int(Command::WR)] = rowopen[int(Level::Bank)][int(Command::RD)]; + break; + case int(Type::SALP_2): + // RD + rowopen[int(Level::SubArray)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)){ + case int(State::Closed): return false; + case int(State::Opened): return true; + default: assert(false); + }}; + // WR + rowopen[int(Level::SubArray)][int(Command::WR)] = rowopen[int(Level::SubArray)][int(Command::RD)]; + break; + case int(Type::MASA): + // RD + rowopen[int(Level::SubArray)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)){ + case int(State::Closed): return false; + case int(State::Opened): return true; + case int(State::Selected): return true; + default: assert(false); + }}; + // WR + rowopen[int(Level::SubArray)][int(Command::WR)] = rowopen[int(Level::SubArray)][int(Command::RD)]; + break; + default: assert(false); + } +} + +void SALP::init_lambda() +{ + switch(int(type)){ + case int(Type::SALP_1): + lambda[int(Level::Bank)][int(Command::ACT)] = [] (DRAM* node, int id) { + node->state = State::Opened; + }; + lambda[int(Level::SubArray)][int(Command::ACT)] = [] (DRAM* node, int id) { + node->state = State::Opened; + node->row_state[id] = State::Opened; + }; + lambda[int(Level::Bank)][int(Command::PRE)] = [] (DRAM* node, int id) { + node->state = State::Closed; + // For SALP_1, we stick to original design that allows + // only one row in a bank open, so here close subarray id + // is equivalent to close the whole bank + node->children[id]->state = State::Closed; + node->children[id]->row_state.clear(); + }; + lambda[int(Level::Bank)][int(Command::PRE_OTHER)] = lambda[int(Level::Bank)][int(Command::PRE)]; + lambda[int(Level::Rank)][int(Command::PRER)] = [] (DRAM* node, int id) { + for (auto bank : node->children) { + bank->state = State::Closed; + for (auto sa : bank->children){ + sa->state = State::Closed; + sa->row_state.clear();}}}; + lambda[int(Level::Bank)][int(Command::RDA)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->children[id]->state = State::Closed; + node->children[id]->row_state.clear();}; + lambda[int(Level::Bank)][int(Command::WRA)] = lambda[int(Level::Bank)][int(Command::RDA)]; + lambda[int(Level::Rank)][int(Command::PDE)] = [] (DRAM* node, int id) { + for (auto bank : node->children) { + if (bank->state == State::Closed) + continue; + node->state = State::ActPowerDown; + return; + } + node->state = State::PrePowerDown;}; + break; + case int(Type::SALP_2): + lambda[int(Level::SubArray)][int(Command::ACT)] = [] (DRAM* node, int id) { + node->state = State::Opened; + node->row_state[id] = State::Opened;}; + lambda[int(Level::SubArray)][int(Command::PRE)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + lambda[int(Level::SubArray)][int(Command::PRE_OTHER)] = lambda[int(Level::SubArray)][int(Command::PRE)]; + lambda[int(Level::Rank)][int(Command::PRER)] = [] (DRAM* node, int id) { + for (auto bank : node->children) + for (auto sa : bank->children) { + sa->state = State::Closed; + sa->row_state.clear();}}; + lambda[int(Level::SubArray)][int(Command::RDA)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + lambda[int(Level::SubArray)][int(Command::WRA)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + lambda[int(Level::Rank)][int(Command::PDE)] = [] (DRAM* node, int id) { + for (auto bank : node->children) + for (auto sa : bank->children) { + if (sa->state == State::Closed) + continue; + node->state = State::ActPowerDown; + return; + } + node->state = State::PrePowerDown;}; + break; + case int(Type::MASA): + lambda[int(Level::SubArray)][int(Command::ACT)] = [] (DRAM* node, int id) { + node->state = State::Selected; + node->row_state[id] = State::Opened; + for (auto sa : node->parent->children) + if (sa != node && sa->state == State::Selected) { + sa->state = State::Opened; + break;}}; + lambda[int(Level::SubArray)][int(Command::SASEL)] = [] (DRAM* node, int id) { + node->state = State::Selected; + for (auto sa : node->parent->children) + if (sa != node && sa->state == State::Selected) { + sa->state = State::Opened; + break;}}; + lambda[int(Level::SubArray)][int(Command::PRE)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + + lambda[int(Level::Rank)][int(Command::PRER)] = [] (DRAM* node, int id) { + for (auto bank : node->children) + for (auto sa : bank->children) { + sa->state = State::Closed; + sa->row_state.clear();}}; + lambda[int(Level::SubArray)][int(Command::RDA)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + lambda[int(Level::SubArray)][int(Command::WRA)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + lambda[int(Level::Rank)][int(Command::PDE)] = [] (DRAM* node, int id) { + for (auto bank : node->children) + for (auto sa : bank->children) { + if (sa->state == State::Closed) + continue; + node->state = State::ActPowerDown; + return; + } + node->state = State::PrePowerDown;}; + break; + default: assert(false); + } + lambda[int(Level::Rank)][int(Command::PDX)] = [] (DRAM* node, int id) { + node->state = State::PowerUp;}; + lambda[int(Level::Rank)][int(Command::SRE)] = [] (DRAM* node, int id) { + node->state = State::SelfRefresh;}; + lambda[int(Level::Rank)][int(Command::SRX)] = [] (DRAM* node, int id) { + node->state = State::PowerUp;}; +} + +void SALP::init_timing() +{ + SpeedEntry& s = speed_entry; + vector *t; + + /*** Channel ***/ + t = timing[int(Level::Channel)]; + + // CAS <-> CAS + t[int(Command::RD)].push_back({Command::RD, 1, s.nBL}); + t[int(Command::RD)].push_back({Command::RDA, 1, s.nBL}); + t[int(Command::RDA)].push_back({Command::RD, 1, s.nBL}); + t[int(Command::RDA)].push_back({Command::RDA, 1, s.nBL}); + t[int(Command::WR)].push_back({Command::WR, 1, s.nBL}); + t[int(Command::WR)].push_back({Command::WRA, 1, s.nBL}); + t[int(Command::WRA)].push_back({Command::WR, 1, s.nBL}); + t[int(Command::WRA)].push_back({Command::WRA, 1, s.nBL}); + + + /*** Rank ***/ + t = timing[int(Level::Rank)]; + + // CAS <-> CAS + t[int(Command::RD)].push_back({Command::RD, 1, s.nCCD}); + t[int(Command::RD)].push_back({Command::RDA, 1, s.nCCD}); + t[int(Command::RDA)].push_back({Command::RD, 1, s.nCCD}); + t[int(Command::RDA)].push_back({Command::RDA, 1, s.nCCD}); + t[int(Command::WR)].push_back({Command::WR, 1, s.nCCD}); + t[int(Command::WR)].push_back({Command::WRA, 1, s.nCCD}); + t[int(Command::WRA)].push_back({Command::WR, 1, s.nCCD}); + t[int(Command::WRA)].push_back({Command::WRA, 1, s.nCCD}); + t[int(Command::RD)].push_back({Command::WR, 1, s.nCL + s.nCCD + 2 - s.nCWL}); + t[int(Command::RD)].push_back({Command::WRA, 1, s.nCL + s.nCCD + 2 - s.nCWL}); + t[int(Command::RDA)].push_back({Command::WR, 1, s.nCL + s.nCCD + 2 - s.nCWL}); + t[int(Command::RDA)].push_back({Command::WRA, 1, s.nCL + s.nCCD + 2 - s.nCWL}); + t[int(Command::WR)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nWTR}); + t[int(Command::WR)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nWTR}); + t[int(Command::WRA)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nWTR}); + t[int(Command::WRA)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nWTR}); + + // CAS <-> CAS (between sibling ranks) + t[int(Command::RD)].push_back({Command::RD, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RD)].push_back({Command::RDA, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RDA)].push_back({Command::RD, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RDA)].push_back({Command::RDA, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RD)].push_back({Command::WR, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RD)].push_back({Command::WRA, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RDA)].push_back({Command::WR, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RDA)].push_back({Command::WRA, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RD)].push_back({Command::WR, 1, s.nCL + s.nBL + s.nRTRS - s.nCWL, true}); + t[int(Command::RD)].push_back({Command::WRA, 1, s.nCL + s.nBL + s.nRTRS - s.nCWL, true}); + t[int(Command::RDA)].push_back({Command::WR, 1, s.nCL + s.nBL + s.nRTRS - s.nCWL, true}); + t[int(Command::RDA)].push_back({Command::WRA, 1, s.nCL + s.nBL + s.nRTRS - s.nCWL, true}); + t[int(Command::WR)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nRTRS - s.nCL, true}); + t[int(Command::WR)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nRTRS - s.nCL, true}); + t[int(Command::WRA)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nRTRS - s.nCL, true}); + t[int(Command::WRA)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nRTRS - s.nCL, true}); + + // CAS <-> PRER + t[int(Command::RD)].push_back({Command::PRER, 1, s.nRTP}); + t[int(Command::WR)].push_back({Command::PRER, 1, s.nCWL + s.nBL + s.nWR}); + + // CAS <-> REF: none (all banks have to be precharged) + + // CAS <-> PD + t[int(Command::RD)].push_back({Command::PDE, 1, s.nCL + s.nBL + 1}); + t[int(Command::RDA)].push_back({Command::PDE, 1, s.nCL + s.nBL + 1}); + t[int(Command::WR)].push_back({Command::PDE, 1, s.nCWL + s.nBL + s.nWR}); + t[int(Command::WRA)].push_back({Command::PDE, 1, s.nCWL + s.nBL + s.nWR + 1}); // +1 for pre + t[int(Command::PDX)].push_back({Command::RD, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::RDA, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::WR, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::WRA, 1, s.nXP}); + + // CAS <-> SR: none (all banks have to be precharged) + + // RAS <-> RAS + t[int(Command::ACT)].push_back({Command::ACT, 1, s.nRRD}); + t[int(Command::ACT)].push_back({Command::ACT, 4, s.nFAW}); + + t[int(Command::ACT)].push_back({Command::PRER, 1, s.nRAS}); + t[int(Command::PRER)].push_back({Command::ACT, 1, s.nRP}); + + // RAS <-> REF + t[int(Command::PRE)].push_back({Command::REF, 1, s.nRP}); + t[int(Command::PRER)].push_back({Command::REF, 1, s.nRP}); + t[int(Command::PRE_OTHER)].push_back({Command::REF, 1, s.nRP}); + t[int(Command::REF)].push_back({Command::ACT, 1, s.nRFC}); + + // RAS <-> PD + t[int(Command::ACT)].push_back({Command::PDE, 1, 1}); + t[int(Command::PDX)].push_back({Command::ACT, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::PRE, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::PRER, 1, s.nXP}); + + // RAS <-> SR + t[int(Command::PRE)].push_back({Command::SRE, 1, s.nRP}); + t[int(Command::PRER)].push_back({Command::SRE, 1, s.nRP}); + t[int(Command::PRE_OTHER)].push_back({Command::SRE, 1, s.nRP}); + t[int(Command::SRX)].push_back({Command::ACT, 1, s.nXS}); + + // REF <-> REF + t[int(Command::REF)].push_back({Command::REF, 1, s.nRFC}); + + // REF <-> PD + t[int(Command::REF)].push_back({Command::PDE, 1, 1}); + t[int(Command::PDX)].push_back({Command::REF, 1, s.nXP}); + + // REF <-> SR + t[int(Command::SRX)].push_back({Command::REF, 1, s.nXS}); + + // PD <-> PD + t[int(Command::PDE)].push_back({Command::PDX, 1, s.nPD}); + t[int(Command::PDX)].push_back({Command::PDE, 1, s.nXP}); + + // PD <-> SR + t[int(Command::PDX)].push_back({Command::SRE, 1, s.nXP}); + t[int(Command::SRX)].push_back({Command::PDE, 1, s.nXS}); + + // SR <-> SR + t[int(Command::SRE)].push_back({Command::SRX, 1, s.nCKESR}); + t[int(Command::SRX)].push_back({Command::SRE, 1, s.nXS}); + + + /*** Bank ***/ + t = timing[int(Level::Bank)]; + + switch(int(type)) { + case int(Type::SALP_1): + // memory controller doesn't specify a row to precharge, + // all subarrays are precharged together, so we should check + // whether other activation/column access are still ongoing. + t[int(Command::ACT)].push_back({Command::PRE, 1, s.nRAS}); + t[int(Command::RD)].push_back({Command::PRE, 1, s.nRTP}); + t[int(Command::WR)].push_back({Command::PRE, 1, s.nCWL + s.nBL + s.nWR,}); + t[int(Command::ACT)].push_back({Command::PRE_OTHER, 1, s.nRAS}); + t[int(Command::RD)].push_back({Command::PRE_OTHER, 1, s.nRTP}); + t[int(Command::WR)].push_back({Command::PRE_OTHER, 1, s.nCWL + s.nBL + s.nWR,}); + case int(Type::SALP_2): + case int(Type::MASA): + break; + default: assert(false); + } + + /*** SubArray ***/ + t = timing[int(Level::SubArray)]; + + // CAS <-> RAS + t[int(Command::ACT)].push_back({Command::RD, 1, s.nRCD}); + t[int(Command::ACT)].push_back({Command::RDA, 1, s.nRCD}); + t[int(Command::ACT)].push_back({Command::WR, 1, s.nRCD}); + t[int(Command::ACT)].push_back({Command::WRA, 1, s.nRCD}); + + t[int(Command::RD)].push_back({Command::PRE, 1, s.nRTP}); + t[int(Command::WR)].push_back({Command::PRE, 1, s.nCWL + s.nBL + s.nWR}); + + t[int(Command::RDA)].push_back({Command::ACT, 1, s.nRTP + s.nRP}); + t[int(Command::WRA)].push_back({Command::ACT, 1, s.nCWL + s.nBL + s.nWR + s.nRP}); + + // RAS <-> RAS + t[int(Command::ACT)].push_back({Command::ACT, 1, s.nRC}); + t[int(Command::ACT)].push_back({Command::PRE, 1, s.nRAS}); + t[int(Command::PRE)].push_back({Command::ACT, 1, s.nRP}); + + switch(int(type)) { + case int(Type::SALP_1): + case int(Type::SALP_2): + break; + case int(Type::MASA): + t[int(Command::SASEL)].push_back({Command::RD, 1, s.nSCD}); + t[int(Command::SASEL)].push_back({Command::RDA, 1, s.nSCD}); + t[int(Command::SASEL)].push_back({Command::WR, 1, s.nSCD}); + t[int(Command::SASEL)].push_back({Command::WRA, 1, s.nSCD}); + break; + default: assert(false); + } + + // sibling subarray constraints + switch(int(type)) { + case int(Type::SALP_1): + t[int(Command::PRE)].push_back({Command::ACT, 1, s.nPA, true}); + t[int(Command::PRE_OTHER)].push_back({Command::ACT, 1, s.nPA, true}); + // for auto precharge command + t[int(Command::ACT)].push_back({Command::ACT, 1, s.nRC - s.nRP + s.nPA, true}); + t[int(Command::RDA)].push_back({Command::ACT, 1, s.nRTP + s.nPA, true}); + t[int(Command::WRA)].push_back({Command::ACT, 1, s.nCWL + s.nBL + s.nWR + s.nPA, true}); + break; + + case int(Type::SALP_2): + t[int(Command::ACT)].push_back({Command::ACT, 1, s.nRCD + s.nRA, true}); + t[int(Command::RD)].push_back({Command::ACT, 1, s.nRA, true}); + t[int(Command::RDA)].push_back({Command::ACT, 1, s.nRA, true}); + t[int(Command::WR)].push_back({Command::ACT, 1, s.nWA, true}); + t[int(Command::WRA)].push_back({Command::ACT, 1, s.nWA, true}); + break; + case int(Type::MASA): + t[int(Command::RD)].push_back({Command::ACT, 1, s.nRA, true}); + t[int(Command::RDA)].push_back({Command::ACT, 1, s.nRA, true}); + t[int(Command::WR)].push_back({Command::ACT, 1, s.nWA, true}); + t[int(Command::WRA)].push_back({Command::ACT, 1, s.nWA, true}); + + t[int(Command::RD)].push_back({Command::SASEL, 1, s.nRA, true}); + t[int(Command::RDA)].push_back({Command::SASEL, 1, s.nRA, true}); + t[int(Command::WR)].push_back({Command::SASEL, 1, s.nWA, true}); + t[int(Command::WRA)].push_back({Command::SASEL, 1, s.nWA, true}); + + t[int(Command::RD)].push_back({Command::RD, 1, s.nRA, true}); + t[int(Command::RDA)].push_back({Command::RDA, 1, s.nRA, true}); + t[int(Command::WR)].push_back({Command::WR, 1, s.nWA, true}); + t[int(Command::WRA)].push_back({Command::WRA, 1, s.nWA, true}); + break; + default: assert(false); + } + // between sibling subarrays +} diff --git a/src/SALP.h b/src/SALP.h new file mode 100644 index 0000000..bbb99d9 --- /dev/null +++ b/src/SALP.h @@ -0,0 +1,229 @@ +#ifndef __SALP_H +#define __SALP_H + +#include "DRAM.h" +#include "Request.h" +#include +#include + +using namespace std; + +namespace ramulator +{ + +class SALP +{ +public: + string standard_name; + enum class Org; + enum class Speed; + enum class Type; + SALP(Org org, Speed speed, Type type = Type::MASA, int n_sa = 8); + SALP(const string& org_str, const string& speed_str, const string& type_str = "SALP-MASA", int n_sa = 8); + + static map org_map; + static map speed_map; + static map type_map; + + enum class Type : int + { + SALP_1, SALP_2, MASA, MAX + } type; + /*** Level ***/ + enum class Level : int + { + Channel, Rank, Bank, SubArray, Row, Column, MAX + }; + + /*** Command ***/ + enum class Command : int + { + ACT, SASEL, PRE, PRER, // precharge bank/bank/rank(SALP-1), subarray/bank/rank(SALP-2, MASA) + RD, WR, RDA, WRA, // auto-precharge: bank(SALP-1), subarray(SALP-2, MASA) + REF, PDE, PDX, SRE, SRX, + PRE_OTHER, + MAX + }; + + string command_name[int(Command::MAX)] = { + "ACT", "SASEL", "PRE", "PRER", + "RD", "WR", "RDA", "WRA", + "REF", "PDE", "PDX", "SRE", "SRX", "PRE_OTHER" + }; + + // The scope of each command + Level scope[int(Command::MAX)] = { + Level::Row, Level::SubArray, Level::SubArray, Level::Rank, + Level::Column, Level::Column, Level::Column, Level::Column, + Level::Rank, Level::Rank, Level::Rank, Level::Rank, Level::Rank, Level::SubArray + }; + + bool is_opening(Command cmd) + { + switch(int(cmd)) { + case int(Command::ACT): + return true; + default: + return false; + } + } + + bool is_accessing(Command cmd) + { + switch(int(cmd)) { + case int(Command::RD): + case int(Command::WR): + case int(Command::RDA): + case int(Command::WRA): + return true; + default: + return false; + } + } + + bool is_closing(Command cmd) + { + switch(int(cmd)) { + case int(Command::RDA): + case int(Command::WRA): + case int(Command::PRE): + case int(Command::PRER): + case int(Command::PRE_OTHER): + return true; + default: + return false; + } + } + + bool is_refreshing(Command cmd) + { + switch(int(cmd)) { + case int(Command::REF): + return true; + default: + return false; + } + } + + + /* State */ + enum class State : int + { + Opened, Closed, Selected, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX + } start[int(Level::MAX)] = { + State::MAX, State::PowerUp, State::Closed, State::Closed, State::Closed, State::MAX + }; + + /* Translate */ + Command translate[int(Request::Type::MAX)] = { + Command::RD, Command::WR, + Command::REF, Command::PDE, Command::SRE + }; + + /* Prerequisite */ + function*, Command cmd, int)> prereq[int(Level::MAX)][int(Command::MAX)]; + + // SAUGATA: added function object container for row hit status + /* Row hit */ + function*, Command cmd, int)> rowhit[int(Level::MAX)][int(Command::MAX)]; + function*, Command cmd, int)> rowopen[int(Level::MAX)][int(Command::MAX)]; + + /* Timing */ + struct TimingEntry + { + Command cmd; + int dist; + int val; + bool sibling; + }; + vector timing[int(Level::MAX)][int(Command::MAX)]; + + /* Lambda */ + function*, int)> lambda[int(Level::MAX)][int(Command::MAX)]; + + /* Organization */ + enum class Org : int + { + SALP_512Mb_x4, SALP_512Mb_x8, SALP_512Mb_x16, + SALP_1Gb_x4, SALP_1Gb_x8, SALP_1Gb_x16, + SALP_2Gb_x4, SALP_2Gb_x8, SALP_2Gb_x16, + SALP_4Gb_x4, SALP_4Gb_x8, SALP_4Gb_x16, + SALP_8Gb_x4, SALP_8Gb_x8, SALP_8Gb_x16, + MAX + }; + + int n_sa; // number of subarrays per bank + + struct OrgEntry { + int size; + int dq; + int count[int(Level::MAX)]; + } org_table[int(Org::MAX)] = { + { 512, 4, {0, 0, 8, 0, 0, 1<<11}}, { 512, 8, {0, 0, 8, 0, 0, 1<<10}}, { 512, 16, {0, 0, 8, 0, 0, 1<<10}}, + {1<<10, 4, {0, 0, 8, 0, 0, 1<<11}}, {1<<10, 8, {0, 0, 8, 0, 0, 1<<10}}, {1<<10, 16, {0, 0, 8, 0, 0, 1<<10}}, + {2<<10, 4, {0, 0, 8, 0, 0, 1<<11}}, {2<<10, 8, {0, 0, 8, 0, 0, 1<<10}}, {2<<10, 16, {0, 0, 8, 0, 0, 1<<10}}, + {4<<10, 4, {0, 0, 8, 0, 0, 1<<11}}, {4<<10, 8, {0, 0, 8, 0, 0, 1<<10}}, {4<<10, 16, {0, 0, 8, 0, 0, 1<<10}}, + {8<<10, 4, {0, 0, 8, 0, 0, 1<<12}}, {8<<10, 8, {0, 0, 8, 0, 0, 1<<11}}, {8<<10, 16, {0, 0, 8, 0, 0, 1<<10}} + }, org_entry; + + void set_channel_number(int channel); + void set_rank_number(int rank); + + /* Speed */ + enum class Speed : int + { + SALP_800D, SALP_800E, + SALP_1066E, SALP_1066F, SALP_1066G, + SALP_1333G, SALP_1333H, + SALP_1600H, SALP_1600J, SALP_1600K, + SALP_1866K, SALP_1866L, + SALP_2133L, SALP_2133M, + MAX + }; + + int prefetch_size = 8; // 8n prefetch DDR + int channel_width = 64; + + struct SpeedEntry { + int rate; + double freq, tCK; + int nBL, nCCD, nRTRS; + int nCL, nRCD, nRP, nPA, nCWL; // nRP for pre2act same sa, nPA for pre2act diff sa (1 cycle) + int nRAS, nRC; + int nRTP, nWTR, nWR, nRA, nWA; // nRA = nCL/2, nWA = nCWL + nBL + nWR/2 + int nRRD, nFAW; + int nRFC, nREFI; + int nPD, nXP, nXPDLL; + int nCKESR, nXS, nXSDLL; + int nSCD; + } speed_table[int(Speed::MAX)] = { + {800, (400.0/3)*3, (3/0.4)/3, 4, 4, 2, 5, 5, 5, 1, 5, 15, 20, 4, 4, 6, 3, 12, 0, 0, 0, 3120, 3, 3, 10, 4, 0, 512, 1}, + {800, (400.0/3)*3, (3/0.4)/3, 4, 4, 2, 6, 6, 6, 1, 5, 15, 21, 4, 4, 6, 3, 12, 0, 0, 0, 3120, 3, 3, 10, 4, 0, 512, 1}, + {1066, (400.0/3)*4, (3/0.4)/4, 4, 4, 2, 6, 6, 6, 1, 6, 20, 26, 4, 4, 8, 3, 14, 0, 0, 0, 4160, 3, 4, 13, 4, 0, 512, 1}, + {1066, (400.0/3)*4, (3/0.4)/4, 4, 4, 2, 7, 7, 7, 1, 6, 20, 27, 4, 4, 8, 4, 14, 0, 0, 0, 4160, 3, 4, 13, 4, 0, 512, 1}, + {1066, (400.0/3)*4, (3/0.4)/4, 4, 4, 2, 8, 8, 8, 1, 6, 20, 28, 4, 4, 8, 4, 14, 0, 0, 0, 4160, 3, 4, 13, 4, 0, 512, 1}, + {1333, (400.0/3)*5, (3/0.4)/5, 4, 4, 2, 8, 8, 8, 1, 7, 24, 32, 5, 5, 10, 4, 16, 0, 0, 0, 5200, 4, 4, 16, 5, 0, 512, 1}, + {1333, (400.0/3)*5, (3/0.4)/5, 4, 4, 2, 9, 9, 9, 1, 7, 24, 33, 5, 5, 10, 5, 16, 0, 0, 0, 5200, 4, 4, 16, 5, 0, 512, 1}, + {1600, (400.0/3)*6, (3/0.4)/6, 4, 4, 2, 9, 9, 9, 1, 8, 28, 37, 6, 6, 12, 5, 18, 0, 0, 0, 6240, 4, 5, 20, 5, 0, 512, 1}, + {1600, (400.0/3)*6, (3/0.4)/6, 4, 4, 2, 10, 10, 10, 1, 8, 28, 38, 6, 6, 12, 5, 18, 0, 0, 0, 6240, 4, 5, 20, 5, 0, 512, 1}, + {1600, (400.0/3)*6, (3/0.4)/6, 4, 4, 2, 11, 11, 11, 1, 8, 28, 39, 6, 6, 12, 6, 18, 0, 0, 0, 6240, 4, 5, 20, 5, 0, 512, 1}, + {1866, (400.0/3)*7, (3/0.4)/7, 4, 4, 2, 11, 11, 11, 1, 9, 32, 43, 7, 7, 14, 6, 20, 0, 0, 0, 7280, 5, 6, 23, 6, 0, 512, 1}, + {1866, (400.0/3)*7, (3/0.4)/7, 4, 4, 2, 12, 12, 12, 1, 9, 32, 44, 7, 7, 14, 6, 20, 0, 0, 0, 7280, 5, 6, 23, 6, 0, 512, 1}, + {2133, (400.0/3)*8, (3/0.4)/8, 4, 4, 2, 12, 12, 12, 1, 10, 36, 48, 8, 8, 16, 6, 22, 0, 0, 0, 8320, 6, 7, 26, 7, 0, 512, 1}, + {2133, (400.0/3)*8, (3/0.4)/8, 4, 4, 2, 13, 13, 13, 1, 10, 36, 49, 8, 8, 16, 7, 22, 0, 0, 0, 8320, 6, 7, 26, 7, 0, 512, 1} + }, speed_entry; + + int read_latency; + +private: + void init_speed(); + void init_lambda(); + void init_prereq(); + void init_rowhit(); // SAUGATA: added function to check for row hits + void init_rowopen(); + void init_timing(); +}; + +} /*namespace ramulator*/ + +#endif /*__SALP_H*/ diff --git a/src/Scheduler.h b/src/Scheduler.h new file mode 100644 index 0000000..cd5cd8e --- /dev/null +++ b/src/Scheduler.h @@ -0,0 +1,279 @@ +#ifndef __SCHEDULER_H +#define __SCHEDULER_H + +#include "DRAM.h" +#include "Request.h" +#include "Controller.h" +#include +#include +#include +#include +#include + +using namespace std; + +namespace ramulator +{ + +template +class Controller; + +template +class Scheduler +{ +public: + Controller* ctrl; + + enum class Type { + FCFS, FRFCFS, FRFCFS_Cap, FRFCFS_PriorHit, MAX + } type = Type::FRFCFS_PriorHit; + + long cap = 16; + + Scheduler(Controller* ctrl) : ctrl(ctrl) {} + + list::iterator get_head(list& q) + { + // TODO make the decision at compile time + if (type != Type::FRFCFS_PriorHit) { + if (!q.size()) + return q.end(); + + auto head = q.begin(); + for (auto itr = next(q.begin(), 1); itr != q.end(); itr++) + head = compare[int(type)](head, itr); + + return head; + } else { + if (!q.size()) + return q.end(); + + auto head = q.begin(); + for (auto itr = next(q.begin(), 1); itr != q.end(); itr++) { + head = compare[int(Type::FRFCFS_PriorHit)](head, itr); + } + + if (this->ctrl->is_ready(head) && this->ctrl->is_row_hit(head)) { + return head; + } + + // prepare a list of hit request + vector> hit_reqs; + for (auto itr = q.begin() ; itr != q.end() ; ++itr) { + if (this->ctrl->is_row_hit(itr)) { + auto begin = itr->addr_vec.begin(); + // TODO Here it assumes all DRAM standards use PRE to close a row + // It's better to make it more general. + auto end = begin + int(ctrl->channel->spec->scope[int(T::Command::PRE)]) + 1; + vector rowgroup(begin, end); // bank or subarray + hit_reqs.push_back(rowgroup); + } + } + // if we can't find proper request, we need to return q.end(), + // so that no command will be scheduled + head = q.end(); + for (auto itr = q.begin(); itr != q.end(); itr++) { + bool violate_hit = false; + if ((!this->ctrl->is_row_hit(itr)) && this->ctrl->is_row_open(itr)) { + // so the next instruction to be scheduled is PRE, might violate hit + auto begin = itr->addr_vec.begin(); + // TODO Here it assumes all DRAM standards use PRE to close a row + // It's better to make it more general. + auto end = begin + int(ctrl->channel->spec->scope[int(T::Command::PRE)]) + 1; + vector rowgroup(begin, end); // bank or subarray + for (const auto& hit_req_rowgroup : hit_reqs) { + if (rowgroup == hit_req_rowgroup) { + violate_hit = true; + break; + } + } + } + if (violate_hit) { + continue; + } + // If it comes here, that means it won't violate any hit request + if (head == q.end()) { + head = itr; + } else { + head = compare[int(Type::FRFCFS)](head, itr); + } + } + + return head; + } + } + +private: + typedef list::iterator ReqIter; + function compare[int(Type::MAX)] = { + // FCFS + [this] (ReqIter req1, ReqIter req2) { + if (req1->arrive <= req2->arrive) return req1; + return req2;}, + + // FRFCFS + [this] (ReqIter req1, ReqIter req2) { + bool ready1 = this->ctrl->is_ready(req1); + bool ready2 = this->ctrl->is_ready(req2); + + if (ready1 ^ ready2) { + if (ready1) return req1; + return req2; + } + + if (req1->arrive <= req2->arrive) return req1; + return req2;}, + + // FRFCFS_CAP + [this] (ReqIter req1, ReqIter req2) { + bool ready1 = this->ctrl->is_ready(req1); + bool ready2 = this->ctrl->is_ready(req2); + + ready1 = ready1 && (this->ctrl->rowtable->get_hits(req1->addr_vec) <= this->cap); + ready2 = ready2 && (this->ctrl->rowtable->get_hits(req2->addr_vec) <= this->cap); + + if (ready1 ^ ready2) { + if (ready1) return req1; + return req2; + } + + if (req1->arrive <= req2->arrive) return req1; + return req2;}, + // FRFCFS_PriorHit + [this] (ReqIter req1, ReqIter req2) { + bool ready1 = this->ctrl->is_ready(req1) && this->ctrl->is_row_hit(req1); + bool ready2 = this->ctrl->is_ready(req2) && this->ctrl->is_row_hit(req2); + + if (ready1 ^ ready2) { + if (ready1) return req1; + return req2; + } + + if (req1->arrive <= req2->arrive) return req1; + return req2;} + }; +}; + + +template +class RowPolicy +{ +public: + Controller* ctrl; + + enum class Type { + Closed, Opened, Timeout, MAX + } type = Type::Opened; + + int timeout = 50; + + RowPolicy(Controller* ctrl) : ctrl(ctrl) {} + + vector get_victim(typename T::Command cmd) + { + return policy[int(type)](cmd); + } + +private: + function(typename T::Command)> policy[int(Type::MAX)] = { + // Closed + [this] (typename T::Command cmd) -> vector { + for (auto& kv : this->ctrl->rowtable->table) { + if (!this->ctrl->is_ready(cmd, kv.first)) + continue; + return kv.first; + } + return vector();}, + + // Opened + [this] (typename T::Command cmd) { + return vector();}, + + // Timeout + [this] (typename T::Command cmd) -> vector { + for (auto& kv : this->ctrl->rowtable->table) { + auto& entry = kv.second; + if (this->ctrl->clk - entry.timestamp < timeout) + continue; + if (!this->ctrl->is_ready(cmd, kv.first)) + continue; + return kv.first; + } + return vector();} + }; + +}; + + +template +class RowTable +{ +public: + Controller* ctrl; + + struct Entry { + int row; + int hits; + long timestamp; + }; + + map, Entry> table; + + RowTable(Controller* ctrl) : ctrl(ctrl) {} + + void update(typename T::Command cmd, const vector& addr_vec, long clk) + { + auto begin = addr_vec.begin(); + auto end = begin + int(T::Level::Row); + vector rowgroup(begin, end); // bank or subarray + int row = *end; + + T* spec = ctrl->channel->spec; + + if (spec->is_opening(cmd)) + table.insert({rowgroup, {row, 0, clk}}); + + if (spec->is_accessing(cmd)) { + // we are accessing a row -- update its entry + auto match = table.find(rowgroup); + assert(match != table.end()); + assert(match->second.row == row); + match->second.hits++; + match->second.timestamp = clk; + } /* accessing */ + + if (spec->is_closing(cmd)) { + // we are closing one or more rows -- remove their entries + int n_rm = 0; + int scope = int(spec->scope[int(cmd)]); + for (auto it = table.begin(); it != table.end();) { + if (equal(begin, begin + scope + 1, it->first.begin())) { + n_rm++; + it = table.erase(it); + } + else + it++; + } + assert(n_rm > 0); + } /* closing */ + } + + int get_hits(vector& addr_vec) + { + auto begin = addr_vec.begin(); + auto end = begin + int(T::Level::Row); + + vector rowgroup(begin, end); + int row = *end; + + auto itr = table.find(rowgroup); + if (itr == table.end() || itr->second.row != row) + return 0; + + return itr->second.hits; + } +}; + +} /*namespace ramulator*/ + +#endif /*__SCHEDULER_H*/ diff --git a/src/SpeedyController.h b/src/SpeedyController.h new file mode 100644 index 0000000..f234633 --- /dev/null +++ b/src/SpeedyController.h @@ -0,0 +1,304 @@ +#ifndef __SPEEDYCONTROLLER_H +#define __SPEEDYCONTROLLER_H + +#include "Config.h" +#include "DRAM.h" +#include "Request.h" +#include "Statistics.h" +#include +#include +#include +#include +#include +#include +#include +#include + +using namespace std; + +namespace ramulator +{ + +template +class SpeedyController +// A FR-FCFS Open Row Controller, optimized for simulation speed. +// Not For SALP-2 +{ +protected: + ScalarStat row_hits; + ScalarStat row_misses; +private: + class compair_depart_clk{ + public: + bool operator()(const Request& lhs, const Request& rhs) { + return lhs.depart > rhs.depart; + } + }; +public: + /* Command trace for DRAMPower 3.1 */ + string cmd_trace_prefix = "cmd-trace-"; + vector cmd_trace_files; + bool record_cmd_trace = false; + /* Commands to stdout */ + bool print_cmd_trace = false; + /* Member Variables */ + const unsigned int queue_capacity = 32; + long clk = 0; + DRAM* channel; + + double write_hi = 0.875; + double write_low = 0.5; + + // request, first command, earliest clk + typedef tuple request_info; + typedef vector request_queue; + request_queue readq; // queue for read requests + request_queue writeq; // queue for write requests + request_queue otherq; // queue for all "other" requests (e.g., refresh) + + // read requests that are about to receive data from DRAM + priority_queue, compair_depart_clk> pending; + + bool write_mode = false; // whether write requests should be prioritized over reads + long refreshed = 0; // last time refresh requests were generated + + /* Constructor */ + SpeedyController(const Config& configs, DRAM* channel) : + channel(channel) + { + record_cmd_trace = configs.record_cmd_trace(); + print_cmd_trace = configs.print_cmd_trace(); + if (record_cmd_trace){ + string prefix = cmd_trace_prefix + "chan-" + to_string(channel->id) + "-rank-"; + string suffix = ".cmdtrace"; + for (unsigned int i = 0; i < channel->children.size(); i++) + cmd_trace_files.emplace_back(prefix + to_string(i) + suffix); + } + readq.reserve(queue_capacity); + writeq.reserve(queue_capacity); + otherq.reserve(queue_capacity); + + // regStats + + row_hits + .name("row_hits_channel_"+to_string(channel->id)) + .desc("Number of row hits") + .precision(0) + ; + row_misses + .name("row_misses_channel_"+to_string(channel->id)) + .desc("Number of row misses") + .precision(0) + ; + } + + ~SpeedyController(){ + delete channel; + for (auto& file : cmd_trace_files) + file.close(); + } + + /* Member Functions */ + + void finish(int read_req, int write_req, int dram_cycles) { + // call finish function of each channel + channel->finish(dram_cycles); + } + + bool enqueue(Request& req) + { + request_queue& q = + req.type == Request::Type::READ? readq: + req.type == Request::Type::WRITE? writeq: + otherq; + if (queue_capacity == q.size()) + return false; + + req.arrive = clk; + if (req.type == Request::Type::READ){ + for (auto& info : writeq) + if (req.addr == get<0>(info).addr){ + req.depart = clk + 1; + pending.push(req); + return true; + } + } + typename T::Command first_cmd = get_first_cmd(req); + long first_clk = channel->get_next(first_cmd, req.addr_vec.data()); + q.emplace_back(req, first_cmd, first_clk); + push_heap(q.begin(), q.end(), compair_first_clk);; + return true; + } + + void tick() + { + clk++; + + /*** 1. Serve completed reads ***/ + if (pending.size()) { + Request req = pending.top(); + if (req.depart <= clk) { + req.depart = clk; // actual depart clk + req.callback(req); + pending.pop(); + } + } + + /*** 2. Should we schedule refreshes? ***/ + int refresh_interval = channel->spec->speed_entry.nREFI; + if (clk - refreshed >= refresh_interval) { + auto req_type = Request::Type::REFRESH; + vector addr_vec(int(T::Level::MAX), -1); + addr_vec[0] = channel->id; + for (auto child : channel->children) { + addr_vec[1] = child->id; + Request req(addr_vec, req_type, NULL); + bool res = enqueue(req); + assert(res); + } + + refreshed = clk; + } + + /*** 3. Should we schedule writes? ***/ + if (!write_mode) { + // yes -- write queue is almost full or read queue is empty + if (writeq.size() >= (unsigned int)(write_hi * queue_capacity) || readq.size() == 0) + write_mode = true; + } + else { + // no -- write queue is almost empty and read queue is not empty + if (writeq.size() <= (unsigned int)(write_low * queue_capacity) && readq.size() != 0) + write_mode = false; + } + + /*** 4. Find the best command to schedule, if any ***/ + request_queue& q = otherq.size()? otherq: write_mode ? writeq : readq; + + schedule(q); + } + + bool is_row_hit(Request& req) + { + typename T::Command cmd = get_first_cmd(req); + return channel->check_row_hit(cmd, req.addr_vec.data()); + } + +private: + + static bool compair_first_clk(const request_info& lhs, const request_info& rhs) { + return (get<2>(lhs) > get<2>(rhs)); + } + + typename T::Command get_first_cmd(Request& req) + { + typename T::Command cmd = channel->spec->translate[int(req.type)]; + switch (int(req.type)){ + case int(Request::Type::READ): + case int(Request::Type::WRITE):{ + auto node = channel; + for (int i = 1; i < int(T::Level::Row); i++) + node = node->children[req.addr_vec[i]]; + assert(int(node->level) == int(T::Level::Row) - 1); + if (node->state == T::State::Closed) return T::Command::ACT; + else if (node->row_state.find(req.addr_vec[int(T::Level::Row)]) != node->row_state.end()) return cmd; + else return T::Command::PRE; + } + case int(Request::Type::REFRESH): + return channel->decode(cmd, req.addr_vec.data()); + default: + assert(false); + } + // return channel->decode(cmd, req.addr_vec.data()); + } + void update(typename T::Command cmd, bool state_change, vector::iterator& begin, vector::iterator& end, request_queue& q){ + if (q.empty()) return; + + for (auto& info : q) { + bool addr_eq = equal(begin, end, get<0>(info).addr_vec.begin()); + if (state_change && addr_eq) + get<1>(info) = get_first_cmd(get<0>(info)); + if ((cmd == T::Command::RD || cmd == T::Command::WR) + && get<1>(info) == T::Command::ACT) + continue; + get<2>(info) = channel->get_next(get<1>(info), get<0>(info).addr_vec.data()); + } + make_heap(q.begin(), q.end(), compair_first_clk); + } + + void schedule(request_queue& q){ + if (q.empty()) return; + + Request& req = get<0>(q[0]); + typename T::Command& first_cmd = get<1>(q[0]); + long first_clk = get<2>(q[0]); + + if (first_clk > clk) return; + + if (req.is_first_command) { + req.is_first_command = false; + if (req.type == Request::Type::READ || req.type == Request::Type::WRITE) { + if (is_row_hit(req)) + ++row_hits; + else + ++row_misses; + } + } + + issue_cmd(first_cmd, req.addr_vec.data()); + + if (first_cmd == channel->spec->translate[int(req.type)]){ + if (req.type == Request::Type::READ) { + req.depart = clk + channel->spec->read_latency; + pending.push(req); + } + pop_heap(q.begin(), q.end(), compair_first_clk); + q.pop_back(); + } + + bool state_change = channel->spec->is_opening(first_cmd) + || channel->spec->is_closing(first_cmd) + || channel->spec->is_refreshing(first_cmd); + + auto begin = req.addr_vec.begin(); + auto end = begin + 1; + for (; end < begin + int(T::Level::Row) && *end >= 0; end++); + + update(first_cmd, state_change, begin, end, readq); + update(first_cmd, state_change, begin, end, writeq); + update(first_cmd, state_change, begin, end, otherq); + } + + void issue_cmd(typename T::Command cmd, int* addr_vec) + { + // assert(channel->check(cmd, addr_vec, clk)); + channel->update(cmd, addr_vec, clk); + + if (record_cmd_trace){ + // select rank + auto& file = cmd_trace_files[addr_vec[1]]; + string& cmd_name = channel->spec->command_name[int(cmd)]; + file<spec->standard_name == "DDR4" || channel->spec->standard_name == "GDDR5") + bank_id += addr_vec[int(T::Level::Bank) - 1] * + channel->spec->org_entry.count[int(T::Level::Bank)]; + file<<','<spec->command_name[int(cmd)].c_str(), clk); + for (int lev = 0; lev < int(T::Level::MAX); lev++) + printf(" %5d", addr_vec[lev]); + printf("\n"); + } + } +}; + +} /*namespace ramulator*/ + +#endif /*__SPEEDYCONTROLLER_H*/ diff --git a/src/StatType.cpp b/src/StatType.cpp new file mode 100644 index 0000000..058d923 --- /dev/null +++ b/src/StatType.cpp @@ -0,0 +1,147 @@ +#include "StatType.h" + +namespace Stats { + +// Statistics list +StatList statlist; + +// The smallest timing granularity. +Tick curTick = 0; + +void +Histogram::grow_out() +{ + int size = cvec.size(); + int zero = size / 2; // round down! + int top_half = zero + (size - zero + 1) / 2; // round up! + int bottom_half = (size - zero) / 2; // round down! + + // grow down + int low_pair = zero - 1; + for (int i = zero - 1; i >= bottom_half; i--) { + cvec[i] = cvec[low_pair]; + if (low_pair - 1 >= 0) + cvec[i] += cvec[low_pair - 1]; + low_pair -= 2; + } + assert(low_pair == 0 || low_pair == -1 || low_pair == -2); + + for (int i = bottom_half - 1; i >= 0; i--) + cvec[i] = Counter(); + + // grow up + int high_pair = zero; + for (int i = zero; i < top_half; i++) { + cvec[i] = cvec[high_pair]; + if (high_pair + 1 < size) + cvec[i] += cvec[high_pair + 1]; + high_pair += 2; + } + assert(high_pair == size || high_pair == size + 1); + + for (int i = top_half; i < size; i++) + cvec[i] = Counter(); + + max_bucket *= 2; + min_bucket *= 2; + bucket_size *= 2; +} + +void +Histogram::grow_convert() +{ + int size = cvec.size(); + int half = (size + 1) / 2; // round up! + //bool even = (size & 1) == 0; + + int pair = size - 1; + for (int i = size - 1; i >= half; --i) { + cvec[i] = cvec[pair]; + if (pair - 1 >= 0) + cvec[i] += cvec[pair - 1]; + pair -= 2; + } + + for (int i = half - 1; i >= 0; i--) + cvec[i] = Counter(); + + min_bucket = -max_bucket;// - (even ? bucket_size : 0); + bucket_size *= 2; +} + +void +Histogram::grow_up() +{ + int size = cvec.size(); + int half = (size + 1) / 2; // round up! + + int pair = 0; + for (int i = 0; i < half; i++) { + cvec[i] = cvec[pair]; + if (pair + 1 < size) + cvec[i] += cvec[pair + 1]; + pair += 2; + } + assert(pair == size || pair == size + 1); + + for (int i = half; i < size; i++) + cvec[i] = Counter(); + + max_bucket *= 2; + bucket_size *= 2; +} + +void +Histogram::add(Histogram &hs) +{ + size_type b_size = hs.size(); + assert(size() == b_size); + assert(min_bucket == hs.min_bucket); + + sum += hs.sum; + logs += hs.logs; + squares += hs.squares; + samples += hs.samples; + + while(bucket_size > hs.bucket_size) + hs.grow_up(); + while(bucket_size < hs.bucket_size) + grow_up(); + + for (uint32_t i = 0; i < b_size; i++) + cvec[i] += hs.cvec[i]; +} + +void +Histogram::sample(Counter val, int number) +{ + assert(min_bucket < max_bucket); + if (val < min_bucket) { + if (min_bucket == 0) + grow_convert(); + + while (val < min_bucket) + grow_out(); + } else if (val >= max_bucket + bucket_size) { + if (min_bucket == 0) { + while (val >= max_bucket + bucket_size) + grow_up(); + } else { + while (val >= max_bucket + bucket_size) + grow_out(); + } + } + + size_type index = + (int64_t)std::floor((val - min_bucket) / bucket_size); + + assert(index >= 0 && index < size()); + cvec[index] += number; + + sum += val * number; + squares += val * val * number; + logs += log(val) * number; + samples += number; +} + +} /* namespace Stats */ diff --git a/src/StatType.h b/src/StatType.h new file mode 100644 index 0000000..331d6ff --- /dev/null +++ b/src/StatType.h @@ -0,0 +1,660 @@ +#ifndef __STATTYPE_H +#define __STATTYPE_H + +#include +#include +#include +#include + +#include +#include +#include + +namespace ramulator { + +class ScalarStat; +class AverageStat; +class VectorStat; +class AverageVectorStat; +} // namespace ramulator + +namespace Stats { + +const double eps = 1e-8; + +typedef unsigned int size_type; +typedef unsigned int off_type; +typedef double Counter; +typedef double Result; +typedef uint64_t Tick; +typedef std::vector VCounter; +typedef std::vector VResult; +typedef std::numeric_limits CounterLimits; + +// Flags +const uint16_t init = 0x00000001; +const uint16_t display = 0x00000002; +const uint16_t total = 0x00000010; +const uint16_t pdf = 0x00000020; +const uint16_t cdf = 0x00000040; +const uint16_t dist = 0x00000080; +const uint16_t nozero = 0x00000100; +const uint16_t nonan = 0x00000200; + +class Flags { + protected: + uint16_t flags; + public: + Flags(){} + Flags(uint16_t flags):flags(flags){} + void operator=(uint16_t _flags){flags = _flags;} + bool is_total() const {return flags & total;} + bool is_pdf() const {return flags & pdf;} + bool is_nozero() const {return flags & nozero;} + bool is_nonan() const {return flags & nonan;} + bool is_cdf() const {return flags & cdf;} + bool is_display() const {return flags & display;} +}; + +class StatBase { + public: + // TODO implement print for Distribution, Histogram, + // AverageDeviation, StandardDeviation + virtual void print(std::ofstream& file) = 0; + + virtual size_type size() const = 0; + virtual bool zero() const = 0; + virtual void prepare() = 0; + virtual void reset() = 0; + + virtual VResult vresult() const { return VResult(); }; + virtual Result total() const { return Result(); }; + + virtual bool is_display() const = 0; + virtual bool is_nozero() const = 0; +}; + +class StatList { + protected: + std::vector list; + std::ofstream stat_output; + public: + void add(StatBase* stat) { + list.push_back(stat); + } + void output(std::string filename) { + stat_output.open(filename.c_str(), std::ios_base::out); + if (!stat_output.good()) { + assert(false && "!stat_output.good()"); + } + } + void printall() { + for(off_type i = 0 ; i < list.size() ; ++i) { + if (!list[i]) { + continue; + } + if (list[i]->is_nozero() && list[i]->zero()) { + continue; + } + if (list[i]->is_display()) { + list[i]->prepare(); + list[i]->print(stat_output); + } + } + } + ~StatList() { + stat_output.close(); + } +}; + +extern StatList statlist; + +template +class Stat : public StatBase { + protected: + std::string _name; + std::string _desc; + int _precision = 1; + Flags _flags = display; + std::string separatorString; + public: + Stat() { + statlist.add(selfptr()); + } + Derived &self() {return *static_cast(this);} + Derived *selfptr() {return static_cast(this);} + Derived &name(const std::string &__name) { + _name = __name; + return self(); + }; + Derived &desc(const std::string &__desc) { + _desc = __desc; + return self(); + }; + Derived &precision(int __precision) { + _precision = __precision; + return self(); + }; + Derived &flags(Flags __flags) { + _flags = __flags; + return self(); + }; + + template + Derived &prereq(const GenericStat & prereq) { + // TODO deal with prereq; + // only print the stat if the prereq is not zero. + return self(); + } + + Derived &setSeparator(std::string str) { + separatorString = str; + return self(); + } + const std::string& setSeparator() const {return separatorString;} + + size_type size() const { return 0; } + + virtual void print(std::ofstream& file) {}; + virtual void printname(std::ofstream& file) { + file.width(40); + file << _name; + } + + virtual void printdesc(std::ofstream& file) { + file.width(40); + file << "# " << _desc << std::endl; + } + + virtual bool is_display() const { + return _flags.is_display(); + } + + virtual bool is_nozero() const { + return _flags.is_nozero(); + } +}; + +template +class ScalarBase: public Stat { + public: + virtual Counter value() const = 0; + virtual Result result() const = 0; + virtual Result total() const = 0; + + size_type size() const {return 1;} + VResult vresult() const {return VResult(1, result());} + + virtual void print(std::ofstream& file) { + Stat::printname(file); + // TODO deal with flag + file.precision(Stat::_precision); + file.width(20); + Result res = Stat::self().result(); + file << std::fixed << res; + Stat::printdesc(file); + } +}; + +class ConstValue: public ScalarBase { + private: + Counter _value; + public: + ConstValue(Counter __value):_value(__value){} + + void operator ++ () { ++_value; } + void operator -- () { --_value; } + void operator ++ (int) { _value++; } + void operator -- (int) { _value--; } + + template + void operator = (const U &v) { _value = v; } + + template + void operator += (const U &v) { _value += v;} + + template + void operator -= (const U &v) { _value -= v;} + + + Counter value() const {return _value;} + Result result() const {return (Result)_value;} + Result total() const {return result();} + bool zero() const {return (fabs(_value) < eps);} + void prepare() {} + void reset() {} +}; + +class Scalar: public ScalarBase { + private: + Counter _value; + public: + Scalar():_value(0) {} + Counter value() const {return _value;} + Result result() const {return (Result)_value;} + Result total() const {return (Result)_value;} + + void operator ++ () { ++_value; } + void operator -- () { --_value; } + void operator ++ (int) { _value++; } + void operator -- (int) { _value--; } + + template + void operator = (const U &v) { _value = v; } + + template + void operator += (const U &v) { _value += v;} + + template + void operator -= (const U &v) { _value -= v;} + + + virtual bool zero() const {return (fabs(_value) < eps);} + void prepare() {} + void reset() {_value = Counter();} + +}; + +extern Tick curTick; + +class Average: public ScalarBase { + private: + Counter current; + Tick lastReset; + Result total_val; + Tick last; + public: + Average():current(0), lastReset(0), total_val(0), last(0){} + + void set(Counter val) { + total_val += current * (curTick - last); + last = curTick; + current = val; + } + void inc(Counter val) { + set(current + val); + } + void dec(Counter val) { + set(current - val); + } + void operator ++ () { inc(1); } + void operator -- () { dec(1); } + void operator ++ (int) { inc(1); } + void operator -- (int) { dec(1); } + + template + void operator = (const U &v) { set(v); } + + template + void operator += (const U &v) { inc(v);} + + template + void operator -= (const U &v) { dec(v);} + + + bool zero() const { return (fabs(total_val) < eps); } + void prepare() { + total_val += current * (curTick - last); + last = curTick; + } + void reset() { + total_val = 0.0; + last = curTick; + lastReset = curTick; + } + + Counter value() const { return current; } + Result result() const { + assert(last == curTick); + return (Result)(total_val + current)/ (Result)(curTick - lastReset + 1); + } + Result total() const {return result();} +}; + +template +class VectorBase: public Stat { + private: + size_type _size = 0; + std::vector data; + + public: + void init(size_type __size) { + _size = __size; + data.resize(size()); + for (off_type i = 0 ; i < size() ; ++i) { + data[i].flags(0) + .name("[" + std::string(1, char(i + '0')) + "]"); + } + } + size_type size() const {return _size;} + // Copy the values to a local vector and return a reference to it. + void value(VCounter& vec) const { + vec.resize(size()); + for (off_type i = 0 ; i < size() ; ++i) { + vec[i] = data[i].value(); + } + } + // Copy the results to a local vector and return a reference to it. + void result(VResult& vec) const { + vec.resize(size()); + for (off_type i = 0 ; i < size() ; ++i) { + vec[i] = data[i].result(); + } + } + + Result total() const { + Result sum = 0.0; + for (off_type i = 0 ; i < size() ; ++i) { + sum += data[i].result(); + } + return sum; + } + + VResult vresult() const { + VResult vres; + for (off_type i = 0 ; i < size() ; ++i) { + vres[i] = data[i].result(); + } + return vres; + } + + bool check() const { + // We don't separate storage and access as gem5 does. + // So here is always true. + return true; + } + + Element &operator[](off_type index) { + assert(index >= 0 && index < size()); + return data[index]; + } + + bool zero() const { + return (fabs(total()) < eps); + } + + void prepare() { + for (off_type i = 0 ; i < size() ; ++i) { + data[i].prepare(); + } + } + void reset() { + for (off_type i = 0 ; i < size() ; ++i) { + data[i].reset(); + } + } + void print(std::ofstream& file) { + Stat::printname(file); + file.precision(Stat::_precision); + file.width(20); + file << std::fixed << total(); + Stat::printdesc(file); + for (off_type i = 0 ; i < size() ; ++i) { + data[i].print(file); + } + } +}; + +class Vector: public VectorBase { +}; + +class AverageVector: public VectorBase { +}; + +class Distribution: public Stat { + private: + // Parameter part: + Counter param_min; + Counter param_max; + Counter param_bucket_size; + Counter param_buckets; + + // The minimum value to track + Counter min_track; + // The maximum value to track + Counter max_track; + // The number of entries in each bucket + Counter bucket_size; + + Counter min_val; + Counter max_val; + // The number of values sampled less than min + Counter underflow; + // The number of values sampled more than max + Counter overflow; + // The current sum + Counter sum; + // The sum of squares + Counter squares; + // The number of samples + Counter samples; + // Counter for each bucket + VCounter cvec; + + public: + Distribution():param_min(Counter()), param_max(Counter()), + param_bucket_size(Counter()) { reset(); } + void init(Counter min, Counter max, Counter bkt) { + param_min = min; + param_max = max; + param_bucket_size = bkt; + param_buckets = (size_type)ceil((max - min + 1.0) / bkt); + cvec.resize(param_buckets); + + reset(); + } + void sample(Counter val, int number) { + if (val < min_track) + underflow += number; + else if (val > max_track) + overflow += number; + else { + size_type index = + (size_type)std::floor((val - min_track) / bucket_size); + assert(index < size()); + cvec[index] += number; + } + + if (val < min_val) + min_val = val; + + if (val > max_val) + max_val = val; + + sum += val * number; + squares += val * val * number; + samples += number; + } + + size_type size() const {return cvec.size();} + bool zero() const { + return (fabs(samples) < eps); + } + void prepare() {}; + void reset() { + min_track = param_min; + max_track = param_max; + bucket_size = param_bucket_size; + + min_val = CounterLimits::max(); + max_val = CounterLimits::min(); + underflow = Counter(); + overflow = Counter(); + + size_type _size = cvec.size(); + for (off_type i = 0 ; i < _size ; ++i) { + cvec[i] = Counter(); + } + + sum = Counter(); + squares = Counter(); + samples = Counter(); + }; + void add(Distribution &d) { + size_type d_size = d.size(); + assert(size() == d_size); + assert(min_track == d.min_track); + assert(max_track == d.max_track); + + underflow += d.underflow; + overflow += d.overflow; + + sum += d.sum; + squares += d.squares; + samples += d.samples; + + if (d.min_val < min_val) { + min_val = d.min_val; + } + + if (d.max_val > max_val) { + max_val = d.max_val; + } + + for (off_type i = 0 ; i < d_size ; ++i) { + cvec[i] += d.cvec[i]; + } + } +}; + +class Histogram: public Stat { + private: + size_type param_buckets; + + Counter min_bucket; + Counter max_bucket; + Counter bucket_size; + + Counter sum; + Counter logs; + Counter squares; + Counter samples; + VCounter cvec; + + public: + Histogram():param_buckets(0) { reset(); } + Histogram(size_type __buckets):cvec(__buckets) { + init(__buckets); + } + void init(size_type __buckets) { + cvec.resize(__buckets); + param_buckets = __buckets; + reset(); + } + + void grow_up(); + void grow_out(); + void grow_convert(); + void add(Histogram& hs); + void sample(Counter val, int number); + + bool zero() const { + return (fabs(samples) < eps); + } + void prepare() {} + void reset() { + min_bucket = 0; + max_bucket = param_buckets - 1; + bucket_size = 1; + + size_type size = param_buckets; + for (off_type i = 0 ; i < size ; ++i) { + cvec[i] = Counter(); + } + + sum = Counter(); + squares = Counter(); + samples = Counter(); + logs = Counter(); + } + + size_type size() const {return param_buckets;} +}; + +class StandardDeviation: public Stat { + private: + Counter sum; + Counter squares; + Counter samples; + + public: + StandardDeviation():sum(Counter()), squares(Counter()), + samples(Counter()) {} + void sample(Counter val, int number) { + Counter value = val * number; + sum += value; + squares += value * value; + samples += number; + } + size_type size() const {return 1;} + bool zero() const {return (fabs(samples) < eps);} + void prepare() {} + void reset() { + sum = Counter(); + squares = Counter(); + samples = Counter(); + } + void add(StandardDeviation& sd) { + sum += sd.sum; + squares += sd.squares; + samples += sd.samples; + } +}; + +class AverageDeviation: public Stat { + private: + Counter sum; + Counter squares; + + public: + AverageDeviation():sum(Counter()), squares(Counter()) {} + void sample(Counter val, int number) { + Counter value = val * number; + sum += value; + squares += value * value; + } + size_type size() const {return 1;} + bool zero() const {return (fabs(sum) < eps);} + void prepare() {} + void reset() { + sum = Counter(); + squares = Counter(); + } + void add(AverageDeviation& ad) { + sum += ad.sum; + squares += ad.squares; + } +}; + +class Op { + private: + std::string opstring; + public: + Op() {} + Op(std::string __opstring):opstring(__opstring){} + Result operator() (Result r) const { + if (opstring == "-") { + return -r; + } else { + assert("Unary operation can only be unary negation." && false); + } + } + Result operator() (Result l, Result r) const { + if (opstring == "+") { + return l + r; + } else if (opstring == "-") { + return l - r; + } else if (opstring == "*") { + return l * r; + } else if (opstring == "/") { + assert(fabs(r) > 1e-8 || "divide zero error"); + return l / r; + } else { + assert("invalid binary opstring " && false); + } + } +}; + +} // namespace Stats + +#endif diff --git a/src/Statistics.h b/src/Statistics.h new file mode 100644 index 0000000..b9f7489 --- /dev/null +++ b/src/Statistics.h @@ -0,0 +1,246 @@ +#ifndef __STATISTICS_H +#define __STATISTICS_H + +#include + +// FIXME Find better way to decide where does it come from +#if !defined(RAMULATOR) +#define INTEGRATED_WITH_GEM5 +#endif + +#ifdef INTEGRATED_WITH_GEM5 +#include "base/statistics.hh" +#else +#include "StatType.h" +#endif + +/* + IMPORTANT NOTE - Read this first! + + This version of the file provides wrappers to the gem5 statistics classes. + Feel free to go through this file, though it can be difficult to follow + with the degree of abstraction going on. In short, this file currently + provides the following mapping of stat classes. In almost all cases, the + wrapper provides identical and complete functionality to the gem5 stat + classes. All of our classes are defined in the ramulator namespace. + + GEM5 CLASS --> RAMULATOR CLASS + ============================== + Stats::Scalar --> ScalarStat + Stats::Average --> AverageStat + Stats::Vector --> VectorStat + Stats::AverageVector --> AverageVectorStat + Stats::Distribution --> DistributionStat + Stats::Histogram --> HistogramStat + Stats::StandardDeviation --> StandardDeviationStat + Stats::AverageDeviation --> AverageDeviationStat + + All of the stats that you create will be named "ramulator." + automatically, and will be dumped at the end of simulation into the gem5 + stats file. +*/ + +namespace ramulator { + +template +class StatBase { // wrapper for Stats::DataWrap + protected: + StatType stat; + std::string statName; + + StatBase & self() { return *this; } + public: + StatBase() {} + +#ifndef INTEGRATED_WITH_GEM5 + const StatType* get_stat() const { + return &stat; + } +#endif + + StatBase(std::string _name) { + name(_name); + } + + StatBase(std::string _name, std::string _desc) { + name(_name); + desc(_desc); + } + + StatBase & name(std::string _name) { + statName = _name; + stat.name("ramulator." + _name); + + return self(); + } + + const std::string &name(void) const { return statName; } + + StatBase & setSeparator(const std::string & _sep) { + stat.setSeparator(_sep); + return self(); + } + + const std::string &setSeparator() const { return stat.setSeparator(); } + + StatBase & desc(std::string _desc) { + stat.desc(_desc); + return self(); + } + + StatBase & precision(int _precision) { + stat.precision(_precision); + return self(); + } + + StatBase & flags(Stats::Flags _flags) { + stat.flags(_flags); + return self(); + } + + template + StatBase & prereq(const Stat & _prereq) { + stat.prereq(_prereq); + return self(); + } + + Stats::size_type size(void) const { return stat.size(); } + bool zero(void) const { return stat.zero(); } + void prepare(void) { stat.prepare(); } + void reset(void) { stat.reset(); } +}; + +template +class StatBaseVec : public StatBase { // wrapper for Stats::DataWrapVec + protected: + StatBaseVec & self() { return *this; } + + public: + StatBaseVec & subname(Stats::off_type index, const std::string & name) { + StatBase::stat.subname(index, name); + return self(); + } + + StatBaseVec & subdesc(Stats::off_type index, const std::string & desc) { + StatBase::stat.subdesc(index, desc); + return self(); + } +}; + +template +class ScalarStatBase : public StatBase { // wrapper for Stats::ScalarBase + public: + Stats::Counter value() const { return StatBase::stat.value(); }; + void operator++() { ++StatBase::stat; } + void operator--() { --StatBase::stat; } + + void operator++(int) { StatBase::stat++; } + void operator--(int) { StatBase::stat--; } + + template + void operator=(const U &v) { StatBase::stat = v; } + + template + void operator+=(const U &v) { StatBase::stat += v; } + + template + void operator-=(const U &v) { StatBase::stat -= v; } +}; + +template +class VectorStatBase : public StatBaseVec { // wrapper for Stats::VectorBase + protected: + VectorStatBase & self() { return *this; } + + public: + void value(Stats::VCounter & vec) const { StatBase::stat.value(vec); } + void result(Stats::VResult & vec) const { StatBase::stat.result(vec); } + Stats::Result total(void) const { return StatBase::stat.total(); } + + bool check(void) const { return StatBase::stat.check(); } + + VectorStatBase & init(Stats::size_type size) { + StatBase::stat.init(size); + return self(); + } + +#ifdef INTEGRATED_WITH_GEM5 + Stats::ScalarProxy operator[](Stats::off_type index) { return StatBase::stat[index]; } +#else + Element &operator[](Stats::off_type index) { return StatBase::stat[index]; } +#endif +}; + + +template +class DistStatBase : public StatBase { // wrapper for Stats::DistBase + public: + template + void sample(const U &v, int n = 1) { StatBase::stat.sample(v, n); } + + void add(DistStatBase & d) { StatBase::stat.add(d.StatBase::stat); } +}; + + +/* + nice wrappers for the gem5 stats classes used throughout the rest of the code +*/ + +class ScalarStat : public ScalarStatBase { + public: + using ScalarStatBase::operator=; +}; + +class AverageStat : public ScalarStatBase { + public: + using ScalarStatBase::operator=; +}; + +class VectorStat : public VectorStatBase { +}; + +class AverageVectorStat : public VectorStatBase { +}; + +class DistributionStat : public DistStatBase { + protected: + DistributionStat & self() { return *this; } + + public: + DistributionStat & init(Stats::Counter min, Stats::Counter max, Stats::Counter bkt) { + StatBase::stat.init(min, max, bkt); + return self(); + } + +}; + +class HistogramStat : public DistStatBase { + protected: + HistogramStat & self() { return *this; } + + public: + HistogramStat & init(Stats::size_type size) { + StatBase::stat.init(size); + return self(); + } +}; + +class StandardDeviationStat : public DistStatBase { +}; + +class AverageDeviationStat : public DistStatBase { +}; + +/* + Stats TODO + * Formula + * VectorDistribution + * VectorStandardDeviation + * VectorAverageDeviation + * Vector2d + * SparseHistogram +*/ + +} /* namespace ramulator */ + +#endif diff --git a/src/TLDRAM.cpp b/src/TLDRAM.cpp new file mode 100644 index 0000000..5e2f5d9 --- /dev/null +++ b/src/TLDRAM.cpp @@ -0,0 +1,566 @@ +#include "TLDRAM.h" +#include "DRAM.h" +#include +#include +#include + +#include + +using namespace std; +using namespace ramulator; + +string TLDRAM::standard_name = "TLDRAM"; + +map TLDRAM::org_map = { + {"TLDRAM_512Mb_x4", TLDRAM::Org::TLDRAM_512Mb_x4}, + {"TLDRAM_512Mb_x8", TLDRAM::Org::TLDRAM_512Mb_x8}, + {"TLDRAM_512Mb_x16", TLDRAM::Org::TLDRAM_512Mb_x16}, + {"TLDRAM_1Gb_x4", TLDRAM::Org::TLDRAM_1Gb_x4}, + {"TLDRAM_1Gb_x8", TLDRAM::Org::TLDRAM_1Gb_x8}, + {"TLDRAM_1Gb_x16", TLDRAM::Org::TLDRAM_1Gb_x16}, + {"TLDRAM_2Gb_x4", TLDRAM::Org::TLDRAM_2Gb_x4}, + {"TLDRAM_2Gb_x8", TLDRAM::Org::TLDRAM_2Gb_x8}, + {"TLDRAM_2Gb_x16", TLDRAM::Org::TLDRAM_2Gb_x16}, + {"TLDRAM_4Gb_x4", TLDRAM::Org::TLDRAM_4Gb_x4}, + {"TLDRAM_4Gb_x8", TLDRAM::Org::TLDRAM_4Gb_x8}, + {"TLDRAM_4Gb_x16", TLDRAM::Org::TLDRAM_4Gb_x16}, + {"TLDRAM_8Gb_x4", TLDRAM::Org::TLDRAM_8Gb_x4}, + {"TLDRAM_8Gb_x8", TLDRAM::Org::TLDRAM_8Gb_x8}, + {"TLDRAM_8Gb_x16", TLDRAM::Org::TLDRAM_8Gb_x16}, +}; + +map TLDRAM::speed_map = { + {"TLDRAM_800D", TLDRAM::Speed::TLDRAM_800D}, + {"TLDRAM_800E", TLDRAM::Speed::TLDRAM_800E}, + {"TLDRAM_1066E", TLDRAM::Speed::TLDRAM_1066E}, + {"TLDRAM_1066F", TLDRAM::Speed::TLDRAM_1066F}, + {"TLDRAM_1066G", TLDRAM::Speed::TLDRAM_1066G}, + {"TLDRAM_1333G", TLDRAM::Speed::TLDRAM_1333G}, + {"TLDRAM_1333H", TLDRAM::Speed::TLDRAM_1333H}, + {"TLDRAM_1600H", TLDRAM::Speed::TLDRAM_1600H}, + {"TLDRAM_1600J", TLDRAM::Speed::TLDRAM_1600J}, + {"TLDRAM_1600K", TLDRAM::Speed::TLDRAM_1600K}, + {"TLDRAM_1866K", TLDRAM::Speed::TLDRAM_1866K}, + {"TLDRAM_1866L", TLDRAM::Speed::TLDRAM_1866L}, + {"TLDRAM_2133L", TLDRAM::Speed::TLDRAM_2133L}, + {"TLDRAM_2133M", TLDRAM::Speed::TLDRAM_2133M}, +}; + + +TLDRAM::TLDRAM(Org org, Speed speed, int segment_ratio) : + segment_ratio(segment_ratio), + org_entry(org_table[int(org)]), + speed_entry(speed_table[int(speed)]), + read_latency(speed_entry.nCL + speed_entry.nBL) +{ + this->segment_ratio = segment_ratio; + init_speed(); + init_prereq(); + init_rowhit(); // SAUGATA: added row hit function + init_rowopen(); + init_lambda(); + init_timing(); +} + +TLDRAM::TLDRAM(const string& org_str, const string& speed_str, int segment_ratio) : + TLDRAM(org_map[org_str], speed_map[speed_str], segment_ratio) +{ + this->segment_ratio = segment_ratio; +} + +void TLDRAM::set_channel_number(int channel) { + org_entry.count[int(Level::Channel)] = channel; +} + +void TLDRAM::set_rank_number(int rank) { + org_entry.count[int(Level::Rank)] = rank; +} + +void TLDRAM::init_speed() +{ + // nRRD, nFAW + int page = (org_entry.dq * org_entry.count[int(Level::Column)]) >> 13; + switch (speed_entry.rate) { + case 800: speed_entry.nRRD = (page==1) ? 4 : 4; + speed_entry.nFAW = (page==1) ? 16 : 20; + break; + case 1066: speed_entry.nRRD = (page==1) ? 4 : 6; + speed_entry.nFAW = (page==1) ? 20 : 27; + break; + case 1333: + speed_entry.nRRD = (page==1) ? 4 : 5; + speed_entry.nFAW = (page==1) ? 20 : 30; + break; + case 1600: + speed_entry.nRRD = (page==1) ? 5 : 6; + speed_entry.nFAW = (page==1) ? 24 : 32; + break; + case 1866: + speed_entry.nRRD = (page==1) ? 5 : 6; + speed_entry.nFAW = (page==1) ? 26 : 33; + break; + case 2133: + speed_entry.nRRD = (page==1) ? 5 : 6; + speed_entry.nFAW = (page==1) ? 27 : 34; + break; + default: assert(false); + } + + // nRFC, nXS + int chip = org_entry.size; + switch (speed_entry.rate) { + case 800: speed_entry.nRFC = (chip==512) ? 36 : (chip==1<<10) ? 44 + : (chip==1<<11) ? 64 : (chip==1<<12) ? 104 : 140; break; + case 1066: speed_entry.nRFC = (chip==512) ? 48 : (chip==1<<10) ? 59 + : (chip==1<<11) ? 86 : (chip==1<<12) ? 139 : 187; break; + case 1333: speed_entry.nRFC = (chip==512) ? 60 : (chip==1<<10) ? 74 + : (chip==1<<11) ? 107 : (chip==1<<12) ? 174 : 234; break; + case 1600: speed_entry.nRFC = (chip==512) ? 72 : (chip==1<<10) ? 88 + : (chip==1<<11) ? 128 : (chip==1<<12) ? 208 : 280; break; + case 1866: speed_entry.nRFC = (chip==512) ? 84 : (chip==1<<10) ? 103 + : (chip==1<<11) ? 150 : (chip==1<<12) ? 243 : 327; break; + case 2133: speed_entry.nRFC = (chip==512) ? 96 : (chip==1<<10) ? 118 + : (chip==1<<11) ? 171 : (chip==1<<12) ? 278 : 374; break; + default: assert(false); + } + switch (speed_entry.rate) { + case 800: speed_entry.nXS = (chip==512) ? 40 : (chip==1<<10) ? 48 + : (chip==1<<11) ? 68 : (chip==1<<12) ? 108 : 144; break; + case 1066: speed_entry.nXS = (chip==512) ? 54 : (chip==1<<10) ? 64 + : (chip==1<<11) ? 91 : (chip==1<<12) ? 144 : 192; break; + case 1333: speed_entry.nXS = (chip==512) ? 67 : (chip==1<<10) ? 80 + : (chip==1<<11) ? 114 : (chip==1<<12) ? 180 : 240; break; + case 1600: speed_entry.nXS = (chip==512) ? 80 : (chip==1<<10) ? 96 + : (chip==1<<11) ? 136 : (chip==1<<12) ? 216 : 288; break; + case 1866: speed_entry.nXS = (chip==512) ? 94 : (chip==1<<10) ? 112 + : (chip==1<<11) ? 159 : (chip==1<<12) ? 252 : 336; break; + case 2133: speed_entry.nXS = (chip==512) ? 107 : (chip==1<<10) ? 128 + : (chip==1<<11) ? 182 : (chip==1<<12) ? 288 : 384; break; + default: assert(false); + } +} + + +void TLDRAM::init_prereq() +{ + // RD + prereq[int(Level::Rank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::PowerUp): return Command::MAX; + case int(State::ActPowerDown): return Command::PDX; + case int(State::PrePowerDown): return Command::PDX; + case int(State::SelfRefresh): return Command::SRX; + default: assert(false); + } + }; + prereq[int(Level::Rank)][int(Command::MIG)] = prereq[int(Level::Rank)][int(Command::RD)]; + + prereq[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::Closed): + if (id % node->spec->segment_ratio) + return Command::ACT; + else + return Command::ACTF; + case int(State::Opened): + if (node->row_state.find(id) != node->row_state.end()) + return cmd; + if (id % node->spec->segment_ratio) + return Command::PRE; + else + return Command::PREF; + default: assert(false); + } + }; + prereq[int(Level::Bank)][int(Command::MIG)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::Closed): + return Command::ACTM; + case int(State::Opened): + if (node->row_state.find(id) != node->row_state.end()) + return cmd; + return Command::PREM; + default: assert(false); + } + }; + + // WR + prereq[int(Level::Rank)][int(Command::WR)] = prereq[int(Level::Rank)][int(Command::RD)]; + prereq[int(Level::Bank)][int(Command::WR)] = prereq[int(Level::Bank)][int(Command::RD)]; + + // REF + prereq[int(Level::Rank)][int(Command::REF)] = [] (DRAM* node, Command cmd, int id) { + for (auto bank : node->children) { + if (bank->state == State::Closed) + continue; + if (id % node->spec->segment_ratio) + return Command::PREA; + else + return Command::PREAF; + } + return Command::REF; + }; + + // PD + prereq[int(Level::Rank)][int(Command::PDE)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::PowerUp): return Command::PDE; + case int(State::ActPowerDown): return Command::PDE; + case int(State::PrePowerDown): return Command::PDE; + case int(State::SelfRefresh): return Command::SRX; + default: assert(false); + } + }; + + // SR + prereq[int(Level::Rank)][int(Command::SRE)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::PowerUp): return Command::SRE; + case int(State::ActPowerDown): return Command::PDX; + case int(State::PrePowerDown): return Command::PDX; + case int(State::SelfRefresh): return Command::SRE; + default: assert(false); + } + }; +} + +// SAUGATA: added row hit check functions to see if the desired location is currently open +void TLDRAM::init_rowhit() +{ + // RD + rowhit[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::Closed): return false; + case int(State::Opened): + if (node->row_state.find(id) != node->row_state.end()) + return true; + return false; + default: assert(false); + }}; + + // WR + rowhit[int(Level::Bank)][int(Command::WR)] = rowhit[int(Level::Bank)][int(Command::RD)]; +} + +void TLDRAM::init_rowopen() +{ + // RD + rowopen[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::Closed): return false; + case int(State::Opened): return true; + default: assert(false); + }}; + + // WR + rowopen[int(Level::Bank)][int(Command::WR)] = rowopen[int(Level::Bank)][int(Command::RD)]; +} + +void TLDRAM::init_lambda() +{ + lambda[int(Level::Bank)][int(Command::ACT)] = [] (DRAM* node, int id) { + node->state = State::Opened; + node->row_state[id] = State::Opened; + }; + lambda[int(Level::Bank)][int(Command::ACTF)] = [] (DRAM* node, int id) { + node->state = State::Opened; + node->row_state[id] = State::Opened; + }; + lambda[int(Level::Bank)][int(Command::ACTM)] = [] (DRAM* node, int id) { + node->state = State::Opened; + node->row_state[id] = State::Opened; + }; + lambda[int(Level::Bank)][int(Command::PRE)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear(); + }; + lambda[int(Level::Bank)][int(Command::PREF)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear(); + }; + lambda[int(Level::Bank)][int(Command::PREM)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear(); + }; + lambda[int(Level::Rank)][int(Command::PREA)] = [] (DRAM* node, int id) { + for (auto bank : node->children) { + bank->state = State::Closed; + bank->row_state.clear(); + } + }; + lambda[int(Level::Rank)][int(Command::PREAF)] = [] (DRAM* node, int id) { + for (auto bank : node->children) { + bank->state = State::Closed; + bank->row_state.clear(); + } + }; + lambda[int(Level::Rank)][int(Command::PREAM)] = [] (DRAM* node, int id) { + for (auto bank : node->children) { + bank->state = State::Closed; + bank->row_state.clear(); + } + }; + lambda[int(Level::Rank)][int(Command::REF)] = [] (DRAM* node, int id) {}; + lambda[int(Level::Rank)][int(Command::REF)] = [] (DRAM* node, int id) {}; + lambda[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, int id) {}; + lambda[int(Level::Bank)][int(Command::WR)] = [] (DRAM* node, int id) {}; + lambda[int(Level::Bank)][int(Command::MIG)] = [] (DRAM* node, int id) {}; + lambda[int(Level::Rank)][int(Command::PDE)] = [] (DRAM* node, int id) { + for (auto bank : node->children) { + if (bank->state == State::Closed) + continue; + node->state = State::ActPowerDown; + return; + } + node->state = State::PrePowerDown; + }; + lambda[int(Level::Rank)][int(Command::PDX)] = [] (DRAM* node, int id) { + node->state = State::PowerUp; + }; + lambda[int(Level::Rank)][int(Command::SRE)] = [] (DRAM* node, int id) { + node->state = State::SelfRefresh; + }; + lambda[int(Level::Rank)][int(Command::SRX)] = [] (DRAM* node, int id) { + node->state = State::PowerUp; + }; +} + + +void TLDRAM::init_timing() +{ + SpeedEntry& s = speed_entry; + vector *t; + + /*** Channel ***/ + t = timing[int(Level::Channel)]; + + // CAS <-> CAS + t[int(Command::RD)].push_back({Command::RD, 1, s.nBL}); + t[int(Command::RD)].push_back({Command::MIG, 1, s.nBL}); + t[int(Command::MIG)].push_back({Command::RD, 1, s.nBL}); + t[int(Command::MIG)].push_back({Command::MIG, 1, s.nBL}); + t[int(Command::WR)].push_back({Command::WR, 1, s.nBL}); + + + /*** Rank ***/ + t = timing[int(Level::Rank)]; + + // CAS <-> CAS + t[int(Command::RD)].push_back({Command::RD, 1, s.nCCD}); + t[int(Command::RD)].push_back({Command::MIG, 1, s.nCCD}); + t[int(Command::MIG)].push_back({Command::RD, 1, s.nCCD}); + t[int(Command::MIG)].push_back({Command::MIG, 1, s.nCCD}); + + t[int(Command::RD)].push_back({Command::WR, 1, s.nCL + s.nCCD + 2 - s.nCWL}); + t[int(Command::MIG)].push_back({Command::WR, 1, s.nCL + s.nCCD + 2 - s.nCWL}); + t[int(Command::WR)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nWTR}); + t[int(Command::WR)].push_back({Command::MIG, 1, s.nCWL + s.nBL + s.nWTR}); + + t[int(Command::WR)].push_back({Command::WR, 1, s.nCCD}); + + // CAS <-> CAS (between sibling ranks) + t[int(Command::RD)].push_back({Command::RD, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RD)].push_back({Command::MIG, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RD)].push_back({Command::WR, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RD)].push_back({Command::WR, 1, s.nCL + s.nBL + s.nRTRS - s.nCWL, true}); + t[int(Command::RD)].push_back({Command::PREA, 1, s.nRTP}); + t[int(Command::RD)].push_back({Command::PREAF, 1, s.nRTP}); + t[int(Command::RD)].push_back({Command::PREAM, 1, s.nRTP}); + + t[int(Command::MIG)].push_back({Command::RD, 1, s.nBL + s.nRTRS, true}); + t[int(Command::MIG)].push_back({Command::MIG, 1, s.nBL + s.nRTRS, true}); + t[int(Command::MIG)].push_back({Command::WR, 1, s.nBL + s.nRTRS, true}); + t[int(Command::MIG)].push_back({Command::WR, 1, s.nCL + s.nBL + s.nRTRS - s.nCWL, true}); + t[int(Command::MIG)].push_back({Command::PREA, 1, s.nRTP}); + t[int(Command::MIG)].push_back({Command::PREAF, 1, s.nRTP}); + t[int(Command::MIG)].push_back({Command::PREAM, 1, s.nRTP}); + + t[int(Command::WR)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nRTRS - s.nCL, true}); + t[int(Command::WR)].push_back({Command::MIG, 1, s.nCWL + s.nBL + s.nRTRS - s.nCL, true}); + t[int(Command::WR)].push_back({Command::PREA, 1, s.nCWL + s.nBL + s.nWR}); + t[int(Command::WR)].push_back({Command::PREAF, 1, s.nCWL + s.nBL + s.nWR}); + t[int(Command::WR)].push_back({Command::PREAM, 1, s.nCWL + s.nBL + s.nWR}); + + // CAS <-> PD + t[int(Command::RD)].push_back({Command::PDE, 1, s.nCL + s.nBL + 1}); + t[int(Command::MIG)].push_back({Command::PDE, 1, s.nCL + s.nBL + 1}); + t[int(Command::WR)].push_back({Command::PDE, 1, s.nCWL + s.nBL + s.nWR}); + t[int(Command::PDX)].push_back({Command::RD, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::MIG, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::WR, 1, s.nXP}); + + // CAS <-> SR: none (all banks have to be precharged) + + // RAS <-> RAS + t[int(Command::ACT)].push_back({Command::ACT, 1, s.nRRD}); + t[int(Command::ACT)].push_back({Command::ACT, 4, s.nFAW}); + t[int(Command::ACT)].push_back({Command::ACTF, 1, s.nRRD}); + t[int(Command::ACT)].push_back({Command::ACTF, 4, s.nFAW}); + t[int(Command::ACT)].push_back({Command::ACTM, 1, s.nRRD}); + t[int(Command::ACT)].push_back({Command::ACTM, 4, s.nFAW}); + t[int(Command::ACT)].push_back({Command::PRE, 1, s.nRAS}); + t[int(Command::ACT)].push_back({Command::PREA, 1, s.nRAS}); + t[int(Command::ACT)].push_back({Command::PREF, 1, s.nRAS}); + t[int(Command::ACT)].push_back({Command::PREAF, 1, s.nRAS}); + t[int(Command::ACT)].push_back({Command::PREM, 1, s.nRAS}); + t[int(Command::ACT)].push_back({Command::PREAM, 1, s.nRAS}); + + t[int(Command::ACTF)].push_back({Command::ACT, 1, s.nRRD}); + t[int(Command::ACTF)].push_back({Command::ACT, 4, s.nFAW}); + t[int(Command::ACTF)].push_back({Command::ACTF, 1, s.nRRD}); + t[int(Command::ACTF)].push_back({Command::ACTF, 4, s.nFAW}); + t[int(Command::ACTF)].push_back({Command::ACTM, 1, s.nRRD}); + t[int(Command::ACTF)].push_back({Command::ACTM, 4, s.nFAW}); + t[int(Command::ACTF)].push_back({Command::PRE, 1, s.nRASF}); + t[int(Command::ACTF)].push_back({Command::PREA, 1, s.nRASF}); + t[int(Command::ACTF)].push_back({Command::PREF, 1, s.nRASF}); + t[int(Command::ACTF)].push_back({Command::PREAF, 1, s.nRASF}); + t[int(Command::ACTF)].push_back({Command::PREM, 1, s.nRASF}); + t[int(Command::ACTF)].push_back({Command::PREAM, 1, s.nRASF}); + + t[int(Command::ACTM)].push_back({Command::ACT, 1, s.nRRD}); + t[int(Command::ACTM)].push_back({Command::ACT, 4, s.nFAW}); + t[int(Command::ACTM)].push_back({Command::ACTF, 1, s.nRRD}); + t[int(Command::ACTM)].push_back({Command::ACTF, 4, s.nFAW}); + t[int(Command::ACTM)].push_back({Command::ACTM, 1, s.nRRD}); + t[int(Command::ACTM)].push_back({Command::ACTM, 4, s.nFAW}); + t[int(Command::ACTM)].push_back({Command::PRE, 1, s.nRASM}); + t[int(Command::ACTM)].push_back({Command::PREA, 1, s.nRASM}); + t[int(Command::ACTM)].push_back({Command::PREF, 1, s.nRASM}); + t[int(Command::ACTM)].push_back({Command::PREAF, 1, s.nRASM}); + t[int(Command::ACTM)].push_back({Command::PREM, 1, s.nRASM}); + t[int(Command::ACTM)].push_back({Command::PREAM, 1, s.nRASM}); + + t[int(Command::PRE)].push_back({Command::ACT, 1, s.nRP}); + t[int(Command::PRE)].push_back({Command::ACTF, 1, s.nRP}); + t[int(Command::PRE)].push_back({Command::ACTM, 1, s.nRP}); + + t[int(Command::PREF)].push_back({Command::ACT, 1, s.nRPF}); + t[int(Command::PREF)].push_back({Command::ACTF, 1, s.nRPF}); + t[int(Command::PREF)].push_back({Command::ACTM, 1, s.nRPF}); + + t[int(Command::PREM)].push_back({Command::ACT, 1, s.nRPM}); + t[int(Command::PREM)].push_back({Command::ACTF, 1, s.nRPM}); + t[int(Command::PREM)].push_back({Command::ACTM, 1, s.nRPM}); + + // RAS <-> REF + t[int(Command::PRE)].push_back({Command::REF, 1, s.nRP}); + t[int(Command::PREF)].push_back({Command::REF, 1, s.nRPF}); + t[int(Command::PREM)].push_back({Command::REF, 1, s.nRPM}); + + t[int(Command::PREA)].push_back({Command::REF, 1, s.nRP}); + t[int(Command::PREAF)].push_back({Command::REF, 1, s.nRPF}); + t[int(Command::PREAM)].push_back({Command::REF, 1, s.nRPM}); + + t[int(Command::REF)].push_back({Command::ACT, 1, s.nRFC}); + t[int(Command::REF)].push_back({Command::ACTF, 1, s.nRFC}); + t[int(Command::REF)].push_back({Command::ACTM, 1, s.nRFC}); + + // RAS <-> PD + t[int(Command::ACT)].push_back({Command::PDE, 1, 1}); + t[int(Command::ACTF)].push_back({Command::PDE, 1, 1}); + t[int(Command::ACTM)].push_back({Command::PDE, 1, 1}); + + t[int(Command::PDX)].push_back({Command::ACT, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::ACTF, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::ACTM, 1, s.nXP}); + + t[int(Command::PDX)].push_back({Command::PRE, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::PREF, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::PREM, 1, s.nXP}); + + // RAS <-> SR + t[int(Command::PRE)].push_back({Command::SRE, 1, s.nRP}); + t[int(Command::PREF)].push_back({Command::SRE, 1, s.nRPF}); + t[int(Command::PREM)].push_back({Command::SRE, 1, s.nRPM}); + t[int(Command::PREA)].push_back({Command::SRE, 1, s.nRP}); + t[int(Command::PREAF)].push_back({Command::SRE, 1, s.nRPF}); + t[int(Command::PREAM)].push_back({Command::SRE, 1, s.nRPM}); + + t[int(Command::SRX)].push_back({Command::ACT, 1, s.nXS}); + t[int(Command::SRX)].push_back({Command::ACTF, 1, s.nXS}); + t[int(Command::SRX)].push_back({Command::ACTM, 1, s.nXS}); + + // REF <-> REF + t[int(Command::REF)].push_back({Command::REF, 1, s.nRFC}); + + // REF <-> PD + t[int(Command::REF)].push_back({Command::PDE, 1, 1}); + t[int(Command::PDX)].push_back({Command::REF, 1, s.nXP}); + + // REF <-> SR + t[int(Command::SRX)].push_back({Command::REF, 1, s.nXS}); + + // PD <-> PD + t[int(Command::PDE)].push_back({Command::PDX, 1, s.nPD}); + t[int(Command::PDX)].push_back({Command::PDE, 1, s.nXP}); + + // PD <-> SR + t[int(Command::PDX)].push_back({Command::SRE, 1, s.nXP}); + t[int(Command::SRX)].push_back({Command::PDE, 1, s.nXS}); + + // SR <-> SR + t[int(Command::SRE)].push_back({Command::SRX, 1, s.nCKESR}); + t[int(Command::SRX)].push_back({Command::SRE, 1, s.nXS}); + + + /*** Bank ***/ + t = timing[int(Level::Bank)]; + + // CAS <-> RAS + t[int(Command::ACT)].push_back({Command::RD, 1, s.nRCD}); + t[int(Command::ACTF)].push_back({Command::RD, 1, s.nRCDF}); // Fast Segment + t[int(Command::ACTM)].push_back({Command::RD, 1, s.nRCDM}); // Fast Segment + + t[int(Command::ACT)].push_back({Command::MIG, 1, s.nRCD}); + t[int(Command::ACTF)].push_back({Command::MIG, 1, s.nRCDF}); // Fast Segment + t[int(Command::ACTM)].push_back({Command::MIG, 1, s.nRCDM}); // Fast Segment + + t[int(Command::ACT)].push_back({Command::WR, 1, s.nRCD}); + t[int(Command::ACTF)].push_back({Command::WR, 1, s.nRCDF}); // Fast Segment + t[int(Command::ACTM)].push_back({Command::WR, 1, s.nRCDM}); // Fast Segment + + t[int(Command::RD)].push_back({Command::PRE, 1, s.nRTP}); + t[int(Command::RD)].push_back({Command::PREF, 1, s.nRTP}); + t[int(Command::RD)].push_back({Command::PREM, 1, s.nRTP}); + + t[int(Command::MIG)].push_back({Command::PRE, 1, s.nRTP}); + t[int(Command::MIG)].push_back({Command::PREF, 1, s.nRTP}); + t[int(Command::MIG)].push_back({Command::PREM, 1, s.nRTP}); + + t[int(Command::WR)].push_back({Command::PRE, 1, s.nCWL + s.nBL + s.nWR}); + t[int(Command::WR)].push_back({Command::PREF, 1, s.nCWL + s.nBL + s.nWR}); + + + // RAS <-> RAS + t[int(Command::ACT)].push_back({Command::ACT, 1, s.nRC}); + t[int(Command::ACT)].push_back({Command::ACTF, 1, s.nRC}); + t[int(Command::ACT)].push_back({Command::ACTM, 1, s.nRC}); + t[int(Command::ACTF)].push_back({Command::ACT, 1, s.nRCF}); + t[int(Command::ACTF)].push_back({Command::ACTF, 1, s.nRCF}); + t[int(Command::ACTF)].push_back({Command::ACTM, 1, s.nRCF}); + t[int(Command::ACTM)].push_back({Command::ACT, 1, s.nRCM}); + t[int(Command::ACTM)].push_back({Command::ACTF, 1, s.nRCM}); + t[int(Command::ACTM)].push_back({Command::ACTM, 1, s.nRCM}); + + t[int(Command::ACT)].push_back({Command::PRE, 1, s.nRAS}); + t[int(Command::ACT)].push_back({Command::PREF, 1, s.nRAS}); + t[int(Command::ACT)].push_back({Command::PREM, 1, s.nRAS}); + t[int(Command::ACTF)].push_back({Command::PRE, 1, s.nRASF}); + t[int(Command::ACTF)].push_back({Command::PREF, 1, s.nRASF}); + t[int(Command::ACTF)].push_back({Command::PREM, 1, s.nRASF}); + t[int(Command::ACTM)].push_back({Command::PRE, 1, s.nRASM}); + t[int(Command::ACTM)].push_back({Command::PREF, 1, s.nRASM}); + t[int(Command::ACTM)].push_back({Command::PREM, 1, s.nRASM}); + + t[int(Command::PRE)].push_back({Command::ACT, 1, s.nRP}); + t[int(Command::PRE)].push_back({Command::ACTF, 1, s.nRP}); + t[int(Command::PRE)].push_back({Command::ACTM, 1, s.nRP}); + t[int(Command::PREF)].push_back({Command::ACT, 1, s.nRPF}); + t[int(Command::PREF)].push_back({Command::ACTF, 1, s.nRPF}); + t[int(Command::PREF)].push_back({Command::ACTM, 1, s.nRPF}); + t[int(Command::PREM)].push_back({Command::ACT, 1, s.nRPM}); + t[int(Command::PREM)].push_back({Command::ACTF, 1, s.nRPM}); + t[int(Command::PREM)].push_back({Command::ACTM, 1, s.nRPM}); + +} diff --git a/src/TLDRAM.h b/src/TLDRAM.h new file mode 100644 index 0000000..74ac3af --- /dev/null +++ b/src/TLDRAM.h @@ -0,0 +1,259 @@ +#ifndef __TLDRAM_H +#define __TLDRAM_H + +#include "DRAM.h" +#include "Request.h" +#include +#include +#include +#include + +using namespace std; + +namespace ramulator +{ + +class TLDRAM +{ +public: + int segment_ratio = 16; + + static string standard_name; + enum class Org; + enum class Speed; + TLDRAM(Org org, Speed speed, int segment_ratio); + TLDRAM(const string& org_str, const string& speed_str, int segment_ratio); + + static map org_map; + static map speed_map; + /*** Level ***/ + enum class Level : int + { + Channel, Rank, Bank, Row, Column, MAX + }; + + /*** Command ***/ + enum class Command : int + { + ACT, PRE, PREA, + RD, WR, + REF, PDE, PDX, SRE, SRX, + ACTF, PREF, PREAF, + MIG, + ACTM, PREM, PREAM, + MAX + }; + + string command_name[int(Command::MAX)] = { + "ACT", "PRE", "PREA", + "RD", "WR", + "REF", "PDE", "PDX", "SRE", "SRX", + "ACTF", "PREF", "PREAF", + "MIG", + "ACTM", "PREM", "PREAM" + }; + + Level scope[int(Command::MAX)] = { + Level::Row, Level::Bank, Level::Rank, + Level::Column, Level::Column, + Level::Rank, Level::Rank, Level::Rank, Level::Rank, Level::Rank, + Level::Row, Level::Bank, Level::Rank, + Level::Column, + Level::Row, Level::Bank, Level::Rank + }; + + bool is_opening(Command cmd) + { + switch(int(cmd)) { + case int(Command::ACT): + case int(Command::ACTF): + case int(Command::ACTM): + return true; + default: + return false; + } + } + + bool is_accessing(Command cmd) + { + switch(int(cmd)) { + case int(Command::RD): + case int(Command::WR): + case int(Command::MIG): + return true; + default: + return false; + } + } + + bool is_closing(Command cmd) + { + switch(int(cmd)) { + case int(Command::PRE): + case int(Command::PREF): + case int(Command::PREM): + case int(Command::PREA): + case int(Command::PREAF): + case int(Command::PREAM): + return true; + default: + return false; + } + } + + bool is_refreshing(Command cmd) + { + switch(int(cmd)) { + case int(Command::REF): + return true; + default: + return false; + } + } + + + /* State */ + enum class State : int + { + Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX + } start[int(Level::MAX)] = { + State::MAX, State::PowerUp, State::Closed, State::Closed, State::MAX + }; + + /* Translate */ + Command translate[int(Request::Type::MAX)] = { + Command::RD, Command::WR, + Command::REF, Command::PDE, Command::SRE, + Command::MIG + }; + + /* Prerequisite */ + function*, Command cmd, int)> prereq[int(Level::MAX)][int(Command::MAX)]; + + // SAUGATA: added function object container for row hit status + /* Row hit */ + function*, Command cmd, int)> rowhit[int(Level::MAX)][int(Command::MAX)]; + function*, Command cmd, int)> rowopen[int(Level::MAX)][int(Command::MAX)]; + + /* Timing */ + struct TimingEntry + { + Command cmd; + int dist; + int val; + bool sibling; + }; + vector timing[int(Level::MAX)][int(Command::MAX)]; + + /* Lambda */ + function*, int)> lambda[int(Level::MAX)][int(Command::MAX)]; + + /* Organization */ + enum class Org : int + { + TLDRAM_512Mb_x4, TLDRAM_512Mb_x8, TLDRAM_512Mb_x16, + TLDRAM_1Gb_x4, TLDRAM_1Gb_x8, TLDRAM_1Gb_x16, + TLDRAM_2Gb_x4, TLDRAM_2Gb_x8, TLDRAM_2Gb_x16, + TLDRAM_4Gb_x4, TLDRAM_4Gb_x8, TLDRAM_4Gb_x16, + TLDRAM_8Gb_x4, TLDRAM_8Gb_x8, TLDRAM_8Gb_x16, + MAX + }; + + struct OrgEntry { + int size; + int dq; + int count[int(Level::MAX)]; + } org_table[int(Org::MAX)] = { + { 512, 4, {0, 0, 8, 1<<13, 1<<11}}, + { 512, 8, {0, 0, 8, 1<<13, 1<<10}}, + { 512, 16, {0, 0, 8, 1<<12, 1<<10}}, + {1<<10, 4, {0, 0, 8, 1<<14, 1<<11}}, + {1<<10, 8, {0, 0, 8, 1<<14, 1<<10}}, + {1<<10, 16, {0, 0, 8, 1<<13, 1<<10}}, + {2<<10, 4, {0, 0, 8, 1<<15, 1<<11}}, + {2<<10, 8, {0, 0, 8, 1<<15, 1<<10}}, + {2<<10, 16, {0, 0, 8, 1<<14, 1<<10}}, + {4<<10, 4, {0, 0, 8, 1<<16, 1<<11}}, + {4<<10, 8, {0, 0, 8, 1<<16, 1<<10}}, + {4<<10, 16, {0, 0, 8, 1<<15, 1<<10}}, + {8<<10, 4, {0, 0, 8, 1<<16, 1<<12}}, + {8<<10, 8, {0, 0, 8, 1<<16, 1<<11}}, + {8<<10, 16, {0, 0, 8, 1<<16, 1<<10}} + }, org_entry; + + void set_channel_number(int channel); + void set_rank_number(int rank); + + /* Speed */ + enum class Speed : int + { + TLDRAM_800D, TLDRAM_800E, + TLDRAM_1066E, TLDRAM_1066F, TLDRAM_1066G, + TLDRAM_1333G, TLDRAM_1333H, + TLDRAM_1600H, TLDRAM_1600J, TLDRAM_1600K, + TLDRAM_1866K, TLDRAM_1866L, + TLDRAM_2133L, TLDRAM_2133M, + MAX + }; + + int prefetch_size = 8; // 8n prefetch DDR + int channel_width = 64; + + struct SpeedEntry { + int rate; + double freq, tCK; + int nBL, nCCD, nRTRS; + int nCL, nRCD, nRP, nCWL; + int nRAS, nRC; + int nRTP, nWTR, nWR; + int nRRD, nFAW; + int nRFC, nREFI; + int nPD, nXP, nXPDLL; + int nCKESR, nXS, nXSDLL; + int nRCDF, nRPF, nRASF, nRCF; + int nRCDM, nRPM, nRASM, nRCM; + } speed_table[int(Speed::MAX)] = { + {800, (400.0/3)*3, (3/0.4)/3, 4, 4, 2, 5, 5, 5, 5, 15, 20, 4, 4, 6, 0, 0, 0, + 3120, 3, 3, 10, 4, 0, 512, 3, 3, 10, 13, 6, 6, 20, 26}, + {800, (400.0/3)*3, (3/0.4)/3, 4, 4, 2, 6, 6, 6, 5, 15, 21, 4, 4, 6, 0, 0, 0, + 3120, 3, 3, 10, 4, 0, 512, 3, 3, 10, 13, 6, 6, 20, 26}, + {1066, (400.0/3)*4, (3/0.4)/4, 4, 4, 2, 6, 6, 6, 6, 20, 26, 4, 4, 8, 0, 0, 0, + 4160, 3, 4, 13, 4, 0, 512, 3, 3, 10, 13, 6, 6, 20, 26}, + {1066, (400.0/3)*4, (3/0.4)/4, 4, 4, 2, 7, 7, 7, 6, 20, 27, 4, 4, 8, 0, 0, 0, + 4160, 3, 4, 13, 4, 0, 512, 3, 3, 10, 13, 6, 6, 20, 26}, + {1066, (400.0/3)*4, (3/0.4)/4, 4, 4, 2, 8, 8, 8, 6, 20, 28, 4, 4, 8, 0, 0, 0, + 4160, 3, 4, 13, 4, 0, 512, 3, 3, 10, 13, 6, 6, 20, 26}, + {1333, (400.0/3)*5, (3/0.4)/5, 4, 4, 2, 8, 8, 8, 7, 24, 32, 5, 5, 10, 0, 0, 0, + 5200, 4, 4, 16, 5, 0, 512, 3, 3, 10, 13, 6, 6, 20, 26}, + {1333, (400.0/3)*5, (3/0.4)/5, 4, 4, 2, 9, 9, 9, 7, 24, 33, 5, 5, 10, 0, 0, 0, + 5200, 4, 4, 16, 5, 0, 512, 3, 3, 10, 13, 6, 6, 20, 26}, + {1600, (400.0/3)*6, (3/0.4)/6, 4, 4, 2, 9, 9, 9, 8, 28, 37, 6, 6, 12, 0, 0, 0, + 6240, 4, 5, 20, 5, 0, 512, 3, 3, 10, 13, 6, 6, 20, 26}, + {1600, (400.0/3)*6, (3/0.4)/6, 4, 4, 2, 10, 10, 10, 8, 28, 38, 6, 6, 12, 0, 0, 0, + 6240, 4, 5, 20, 5, 0, 512, 3, 3, 10, 13, 6, 6, 20, 26}, + {1600, (400.0/3)*6, (3/0.4)/6, 4, 4, 2, 11, 11, 11, 8, 28, 39, 6, 6, 12, 0, 0, 0, + 6240, 4, 5, 20, 5, 0, 512, 3, 3, 10, 13, 6, 6, 20, 26}, + {1866, (400.0/3)*7, (3/0.4)/7, 4, 4, 2, 11, 11, 11, 9, 32, 43, 7, 7, 14, 0, 0, 0, + 7280, 5, 6, 23, 6, 0, 512, 3, 3, 10, 13, 6, 6, 20, 26}, + {1866, (400.0/3)*7, (3/0.4)/7, 4, 4, 2, 12, 12, 12, 9, 32, 44, 7, 7, 14, 0, 0, 0, + 7280, 5, 6, 23, 6, 0, 512, 3, 3, 10, 13, 6, 6, 20, 26}, + {2133, (400.0/3)*8, (3/0.4)/8, 4, 4, 2, 12, 12, 12, 10, 36, 48, 8, 8, 16, 0, 0, 0, + 8320, 6, 7, 26, 7, 0, 512, 3, 3, 10, 13, 6, 6, 20, 26}, + {2133, (400.0/3)*8, (3/0.4)/8, 4, 4, 2, 13, 13, 13, 10, 36, 49, 8, 8, 16, 0, 0, 0, + 8320, 6, 7, 26, 7, 0, 512, 3, 3, 10, 13, 6, 6, 20, 26} + }, speed_entry; + + int read_latency; + +private: + void init_speed(); + void init_lambda(); + void init_prereq(); + void init_rowhit(); // SAUGATA: added function to check for row hits + void init_rowopen(); + void init_timing(); +}; + +} /*namespace ramulator*/ + +#endif /*__TLDRAM_H*/ diff --git a/src/WideIO.cpp b/src/WideIO.cpp new file mode 100644 index 0000000..ed73d28 --- /dev/null +++ b/src/WideIO.cpp @@ -0,0 +1,325 @@ +#include "WideIO.h" +#include "DRAM.h" +#include +#include +#include + +using namespace std; +using namespace ramulator; + +string WideIO::standard_name = "WideIO"; + +map WideIO::org_map = { + {"WideIO_1Gb", WideIO::Org::WideIO_1Gb}, + {"WideIO_2Gb", WideIO::Org::WideIO_2Gb}, + {"WideIO_4Gb", WideIO::Org::WideIO_4Gb}, + {"WideIO_8Gb", WideIO::Org::WideIO_8Gb}, +}; + +map WideIO::speed_map = { + {"WideIO_200", WideIO::Speed::WideIO_200}, + {"WideIO_266", WideIO::Speed::WideIO_266}, +}; + +WideIO::WideIO(Org org, Speed speed) : + org_entry(org_table[int(org)]), + speed_entry(speed_table[int(speed)]), + read_latency(speed_entry.nCL + speed_entry.nDQSCK + speed_entry.nBL) +{ + init_speed(); + init_prereq(); + init_rowhit(); // SAUGATA: added row hit function + init_rowopen(); + init_lambda(); + init_timing(); +} + +WideIO::WideIO(const string& org_str, const string& speed_str) : + WideIO(org_map[org_str], speed_map[speed_str]) +{ +} + +void WideIO::set_channel_number(int channel) { + assert((channel == 4) && "The Wide I/O interface supports 4 physical and 4 logical channels."); + org_entry.count[int(Level::Channel)] = channel; +} + +void WideIO::set_rank_number(int rank) { + assert((rank == 1) && "WideIO rank number is fixed to 1."); + org_entry.count[int(Level::Rank)] = rank; +} + +void WideIO::init_speed() +{ + const static int RFC_TABLE[int(Speed::MAX)][int(Org::MAX)] = { + {18, 26, 26, 42}, + {24, 35, 35, 56} + }; + const static int REFI_TABLE[int(Speed::MAX)][int(Org::MAX)] = { + {3120, 1560, 780, 780}, + {4160, 2080, 1040, 520} + }; + int speed = 0, density = 0; + switch(speed_entry.rate){ + case 200: speed = 0; break; + case 266: speed = 1; break; + default: assert(false); + } + switch(org_entry.size >> 8){ + case 1: density = 0; break; + case 2: density = 1; break; + case 4: density = 2; break; + case 8: density = 3; break; + default: assert(false); + } + speed_entry.nRFC = RFC_TABLE[speed][density]; + speed_entry.nREFI = REFI_TABLE[speed][density]; +} + + +void WideIO::init_prereq() +{ + // RD + prereq[int(Level::Rank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::PowerUp): return Command::MAX; + case int(State::ActPowerDown): return Command::PDX; + case int(State::PrePowerDown): return Command::PDX; + case int(State::SelfRefresh): return Command::SREFX; + default: assert(false); + }}; + prereq[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::Closed): return Command::ACT; + case int(State::Opened): + if (node->row_state.find(id) != node->row_state.end()) + return cmd; + return Command::PRE; + default: assert(false); + }}; + + // WR + prereq[int(Level::Rank)][int(Command::WR)] = prereq[int(Level::Rank)][int(Command::RD)]; + prereq[int(Level::Bank)][int(Command::WR)] = prereq[int(Level::Bank)][int(Command::RD)]; + + // REF + prereq[int(Level::Rank)][int(Command::REF)] = [] (DRAM* node, Command cmd, int id) { + for (auto bank : node->children) { + if (bank->state == State::Closed) + continue; + return Command::PRA; + } + return Command::REF;}; + + // PD + prereq[int(Level::Rank)][int(Command::PD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::PowerUp): return Command::PD; + case int(State::ActPowerDown): return Command::PD; + case int(State::PrePowerDown): return Command::PD; + case int(State::SelfRefresh): return Command::SREFX; + default: assert(false); + }}; + + // SR + prereq[int(Level::Rank)][int(Command::SREF)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::PowerUp): return Command::SREF; + case int(State::ActPowerDown): return Command::PDX; + case int(State::PrePowerDown): return Command::PDX; + case int(State::SelfRefresh): return Command::SREF; + default: assert(false); + }}; +} + +// SAUGATA: added row hit check functions to see if the desired location is currently open +void WideIO::init_rowhit() +{ + // RD + rowhit[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::Closed): return false; + case int(State::Opened): + if (node->row_state.find(id) != node->row_state.end()) + return true; + return false; + default: assert(false); + }}; + + // WR + rowhit[int(Level::Bank)][int(Command::WR)] = rowhit[int(Level::Bank)][int(Command::RD)]; +} + +void WideIO::init_rowopen() +{ + // RD + rowopen[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::Closed): return false; + case int(State::Opened): return true; + default: assert(false); + }}; + + // WR + rowopen[int(Level::Bank)][int(Command::WR)] = rowopen[int(Level::Bank)][int(Command::RD)]; +} + +void WideIO::init_lambda() +{ + lambda[int(Level::Bank)][int(Command::ACT)] = [] (DRAM* node, int id) { + node->state = State::Opened; + node->row_state[id] = State::Opened;}; + lambda[int(Level::Bank)][int(Command::PRE)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + lambda[int(Level::Rank)][int(Command::PRA)] = [] (DRAM* node, int id) { + for (auto bank : node->children) { + bank->state = State::Closed; + bank->row_state.clear();}}; + lambda[int(Level::Rank)][int(Command::REF)] = [] (DRAM* node, int id) {}; + lambda[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, int id) {}; + lambda[int(Level::Bank)][int(Command::WR)] = [] (DRAM* node, int id) {}; + lambda[int(Level::Bank)][int(Command::RDA)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + lambda[int(Level::Bank)][int(Command::WRA)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + lambda[int(Level::Rank)][int(Command::PD)] = [] (DRAM* node, int id) { + for (auto bank : node->children) { + if (bank->state == State::Closed) + continue; + node->state = State::ActPowerDown; + return; + } + node->state = State::PrePowerDown;}; + lambda[int(Level::Rank)][int(Command::PDX)] = [] (DRAM* node, int id) { + node->state = State::PowerUp;}; + lambda[int(Level::Rank)][int(Command::SREF)] = [] (DRAM* node, int id) { + node->state = State::SelfRefresh;}; + lambda[int(Level::Rank)][int(Command::SREFX)] = [] (DRAM* node, int id) { + node->state = State::PowerUp;}; +} + + +void WideIO::init_timing() +{ + SpeedEntry& s = speed_entry; + vector *t; + + /*** Channel ***/ + t = timing[int(Level::Channel)]; + + // CAS <-> CAS + t[int(Command::RD)].push_back({Command::RD, 1, s.nBL}); + t[int(Command::RD)].push_back({Command::RDA, 1, s.nBL}); + t[int(Command::RDA)].push_back({Command::RD, 1, s.nBL}); + t[int(Command::RDA)].push_back({Command::RDA, 1, s.nBL}); + t[int(Command::WR)].push_back({Command::WR, 1, s.nBL}); + t[int(Command::WR)].push_back({Command::WRA, 1, s.nBL}); + t[int(Command::WRA)].push_back({Command::WR, 1, s.nBL}); + t[int(Command::WRA)].push_back({Command::WRA, 1, s.nBL}); + + + /*** Rank ***/ + t = timing[int(Level::Rank)]; + + // CAS <-> CAS + t[int(Command::RD)].push_back({Command::RD, 1, s.nCCD}); + t[int(Command::RD)].push_back({Command::RDA, 1, s.nCCD}); + t[int(Command::RDA)].push_back({Command::RD, 1, s.nCCD}); + t[int(Command::RDA)].push_back({Command::RDA, 1, s.nCCD}); + t[int(Command::WR)].push_back({Command::WR, 1, s.nCCD}); + t[int(Command::WR)].push_back({Command::WRA, 1, s.nCCD}); + t[int(Command::WRA)].push_back({Command::WR, 1, s.nCCD}); + t[int(Command::WRA)].push_back({Command::WRA, 1, s.nCCD}); + t[int(Command::RD)].push_back({Command::WR, 1, s.nRTW}); + t[int(Command::RD)].push_back({Command::WRA, 1, s.nRTW}); + t[int(Command::RDA)].push_back({Command::WR, 1, s.nRTW}); + t[int(Command::RDA)].push_back({Command::WRA, 1, s.nRTW}); + t[int(Command::WR)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nWTR}); + t[int(Command::WR)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nWTR}); + t[int(Command::WRA)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nWTR}); + t[int(Command::WRA)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nWTR}); + + // CAS <-> PRA + t[int(Command::RD)].push_back({Command::PRA, 1, s.nRTP}); + t[int(Command::WR)].push_back({Command::PRA, 1, s.nCWL + s.nBL + s.nWR}); + + // CAS <-> PD + t[int(Command::RD)].push_back({Command::PD, 1, s.nCL + s.nBL + 1}); + t[int(Command::RDA)].push_back({Command::PD, 1, s.nCL + s.nBL + 1}); + t[int(Command::WR)].push_back({Command::PD, 1, s.nCWL + s.nBL + s.nWR}); + t[int(Command::WRA)].push_back({Command::PD, 1, s.nCWL + s.nBL + s.nWR + 1}); // +1 for pre + t[int(Command::PDX)].push_back({Command::RD, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::RDA, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::WR, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::WRA, 1, s.nXP}); + + // CAS <-> SR: none (all banks have to be precharged) + + // RAS <-> RAS + t[int(Command::ACT)].push_back({Command::ACT, 1, s.nRRD}); + t[int(Command::ACT)].push_back({Command::ACT, 2, s.nTAW}); + t[int(Command::ACT)].push_back({Command::PRA, 1, s.nRAS}); + t[int(Command::PRA)].push_back({Command::ACT, 1, s.nRP}); + + // RAS <-> REF + t[int(Command::PRE)].push_back({Command::REF, 1, s.nRP}); + t[int(Command::PRA)].push_back({Command::REF, 1, s.nRP}); + t[int(Command::REF)].push_back({Command::ACT, 1, s.nRFC}); + + // RAS <-> PD + t[int(Command::ACT)].push_back({Command::PD, 1, 1}); + t[int(Command::PDX)].push_back({Command::ACT, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::PRE, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::PRA, 1, s.nXP}); + + // RAS <-> SR + t[int(Command::PRE)].push_back({Command::SREF, 1, s.nRP}); + t[int(Command::PRA)].push_back({Command::SREF, 1, s.nRP}); + t[int(Command::SREFX)].push_back({Command::ACT, 1, s.nXSR}); + + // REF <-> REF + t[int(Command::REF)].push_back({Command::REF, 1, s.nRFC}); + + // REF <-> PD + t[int(Command::REF)].push_back({Command::PD, 1, 1}); + t[int(Command::PDX)].push_back({Command::REF, 1, s.nXP}); + + // REF <-> SR + t[int(Command::SREFX)].push_back({Command::REF, 1, s.nXSR}); + + // PD <-> PD + t[int(Command::PD)].push_back({Command::PDX, 1, s.nCKE}); + t[int(Command::PDX)].push_back({Command::PD, 1, s.nXP}); + + // PD <-> SR + t[int(Command::PDX)].push_back({Command::SREF, 1, s.nXP}); + t[int(Command::SREFX)].push_back({Command::PD, 1, s.nXSR}); + + // SR <-> SR + t[int(Command::SREF)].push_back({Command::SREFX, 1, s.nCKESR}); + t[int(Command::SREFX)].push_back({Command::SREF, 1, s.nXSR}); + + + /*** Bank ***/ + t = timing[int(Level::Bank)]; + + // CAS <-> RAS + t[int(Command::ACT)].push_back({Command::RD, 1, s.nRCD}); + t[int(Command::ACT)].push_back({Command::RDA, 1, s.nRCD}); + t[int(Command::ACT)].push_back({Command::WR, 1, s.nRCD}); + t[int(Command::ACT)].push_back({Command::WRA, 1, s.nRCD}); + + t[int(Command::RD)].push_back({Command::PRE, 1, s.nRTP}); + t[int(Command::WR)].push_back({Command::PRE, 1, s.nCWL + s.nBL + s.nWR}); + + t[int(Command::RDA)].push_back({Command::ACT, 1, s.nRTP + s.nRP}); + t[int(Command::WRA)].push_back({Command::ACT, 1, s.nCWL + s.nBL + s.nWR + s.nRP}); + + // RAS <-> RAS + t[int(Command::ACT)].push_back({Command::ACT, 1, s.nRC}); + t[int(Command::ACT)].push_back({Command::PRE, 1, s.nRAS}); + t[int(Command::PRE)].push_back({Command::ACT, 1, s.nRP}); +} diff --git a/src/WideIO.h b/src/WideIO.h new file mode 100644 index 0000000..7c23675 --- /dev/null +++ b/src/WideIO.h @@ -0,0 +1,201 @@ +#ifndef __WIDEIO_H +#define __WIDEIO_H + +#include "DRAM.h" +#include "Request.h" +#include +#include + +using namespace std; + +namespace ramulator +{ + +class WideIO +{ +public: + static string standard_name; + enum class Org; + enum class Speed; + WideIO(Org org, Speed speed); + WideIO(const string& org_str, const string& speed_str); + + static map org_map; + static map speed_map; + + /*** Level ***/ + enum class Level : int + { + Channel, Rank, Bank, Row, Column, MAX + }; + + /*** Command ***/ + enum class Command : int + { + ACT, PRE, PRA, + RD, WR, RDA, WRA, + REF, PD, PDX, SREF, SREFX, + MAX + }; + + string command_name[int(Command::MAX)] = { + "ACT", "PRE", "PRA", + "RD", "WR", "RDA", "WRA", + "REF", "PD", "PDX", "SREF", "SREFX" + }; + + Level scope[int(Command::MAX)] = { + Level::Row, Level::Bank, Level::Rank, + Level::Column, Level::Column, Level::Column, Level::Column, + Level::Rank, Level::Rank, Level::Rank, Level::Rank, Level::Rank + }; + + bool is_opening(Command cmd) + { + switch(int(cmd)) { + case int(Command::ACT): + return true; + default: + return false; + } + } + + bool is_accessing(Command cmd) + { + switch(int(cmd)) { + case int(Command::RD): + case int(Command::WR): + case int(Command::RDA): + case int(Command::WRA): + return true; + default: + return false; + } + } + + bool is_closing(Command cmd) + { + switch(int(cmd)) { + case int(Command::RDA): + case int(Command::WRA): + case int(Command::PRE): + case int(Command::PRA): + return true; + default: + return false; + } + } + + bool is_refreshing(Command cmd) + { + switch(int(cmd)) { + case int(Command::REF): + return true; + default: + return false; + } + } + + + /* State */ + enum class State : int + { + Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX + } start[int(Level::MAX)] = { + State::MAX, State::PowerUp, State::Closed, State::Closed, State::MAX + }; + + /* Translate */ + Command translate[int(Request::Type::MAX)] = { + Command::RD, Command::WR, + Command::REF, Command::PD, Command::SREF + }; + + /* Prerequisite */ + function*, Command cmd, int)> prereq[int(Level::MAX)][int(Command::MAX)]; + + // SAUGATA: added function object container for row hit status + /* Row hit */ + function*, Command cmd, int)> rowhit[int(Level::MAX)][int(Command::MAX)]; + function*, Command cmd, int)> rowopen[int(Level::MAX)][int(Command::MAX)]; + + + /* Timing */ + struct TimingEntry + { + Command cmd; + int dist; + int val; + bool sibling; + }; + vector timing[int(Level::MAX)][int(Command::MAX)]; + + /* Lambda */ + function*, int)> lambda[int(Level::MAX)][int(Command::MAX)]; + + /* Organization */ + enum class Org : int + { + WideIO_1Gb, + WideIO_2Gb, + WideIO_4Gb, + WideIO_8Gb, + MAX + }; + + struct OrgEntry { + int size; + int dq; + int count[int(Level::MAX)]; + } org_table[int(Org::MAX)] = { + // fixed to have 1 rank + { 256, 128, {0, 1, 4, 1<<12, 1<<7}}, + { 512, 128, {0, 1, 4, 1<<13, 1<<7}}, + {1024, 128, {0, 1, 4, 1<<14, 1<<7}}, + {2048, 128, {0, 1, 4, 1<<15, 1<<7}} + }, org_entry; + + void set_channel_number(int channel); + void set_rank_number(int rank); + + /* Speed */ + enum class Speed : int + { + WideIO_200, + WideIO_266, + MAX + }; + + int prefetch_size = 4; // 4n prefetch SDR + int channel_width = 128; + + struct SpeedEntry { + int rate; + double freq, tCK; + int nBL, nCCD, nDQSCK; + int nCL, nRCD, nRP, nCWL; + int nRAS, nRC; + int nRTP, nRTW, nWTR, nWR; + int nRRD, nTAW; + int nRFC, nREFI; + int nCKE, nXP; + int nCKESR, nXSR; // tXSR = tRFC+10 + } speed_table[int(Speed::MAX)] = { + {200, 200.0/3*3, 5.0*3/3, 4, 4, 1, 3, 4, 4, 1, 9, 12, 4, 8, 3, 3, 2, 10, 0, 0, 3, 2, 3, 0}, + {266, 200.0/3*4, 5.0*3/4, 4, 4, 1, 3, 5, 5, 1, 12, 16, 4, 8, 4, 4, 3, 14, 0, 0, 3, 3, 4, 0} + }, speed_entry; + + int read_latency; + +private: + void init_speed(); + void init_lambda(); + void init_prereq(); + void init_rowhit(); // SAUGATA: added function to check for row hits + void init_rowopen(); + void init_timing(); +}; + +} /*namespace ramulator*/ + +#endif /*__WIDEIO_H*/ diff --git a/src/WideIO2.cpp b/src/WideIO2.cpp new file mode 100644 index 0000000..c90d940 --- /dev/null +++ b/src/WideIO2.cpp @@ -0,0 +1,338 @@ +#include "WideIO2.h" +#include "DRAM.h" +#include +#include +#include + +using namespace std; +using namespace ramulator; + +string WideIO2::standard_name = "WideIO2"; + +map WideIO2::org_map = { + {"WideIO2_8Gb", WideIO2::Org::WideIO2_8Gb}, +}; + +map WideIO2::speed_map = { + {"WideIO2_800", WideIO2::Speed::WideIO2_800}, + {"WideIO2_1066", WideIO2::Speed::WideIO2_1066}, +}; + +WideIO2::WideIO2(Org org, Speed speed, int channels) : + speed_entry(speed_table[int(speed)]), + read_latency(speed_entry.nCL + speed_entry.nDQSCK + speed_entry.nBL) +{ + switch(int(org)){ + case int(Org::WideIO2_8Gb): + org_entry.size = (8<<10) / channels; + org_entry.dq = 64; + if (channels == 4) { + org_entry.size = 2<<10; + org_entry.count[int(Level::Channel)] = channels; + org_entry.count[int(Level::Rank)] = 0; + org_entry.count[int(Level::Bank)] = 8; + org_entry.count[int(Level::Row)] = 1<<13; + org_entry.count[int(Level::Column)] = 1<<9; + } else if (channels == 8) { + org_entry.size = 1<<10; + org_entry.count[int(Level::Channel)] = channels; + org_entry.count[int(Level::Rank)] = 0; + org_entry.count[int(Level::Bank)] = 4; + org_entry.count[int(Level::Row)] = 1<<14; + org_entry.count[int(Level::Column)] = 1<<8; + } else assert(false && "The WideIO2 interface supports 4 or 8 physical channels."); + break; + default: assert(false); + } + speed_entry.nRPab = (channels == 4)? speed_entry.nRP8b: speed_entry.nRPpb; + init_prereq(); + init_rowhit(); // SAUGATA: added row hit function + init_lambda(); + init_timing(); +} + +WideIO2::WideIO2(const string& org_str, const string& speed_str, int channels) : + WideIO2(org_map[org_str], speed_map[speed_str], channels) +{ +} + +void WideIO2::set_channel_number(int channel) { + assert((channel == org_entry.count[int(Level::Channel)]) && "channel number must be consistent with spec initializaiton configuration."); + org_entry.count[int(Level::Channel)] = channel; +} + +void WideIO2::set_rank_number(int rank) { + assert(((rank == 1) || (rank == 2)) && "WideIO2 supports single and dual rank configurations."); + org_entry.count[int(Level::Rank)] = rank; +} + +void WideIO2::init_prereq() +{ + // RD + prereq[int(Level::Rank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::PowerUp): return Command::MAX; + case int(State::ActPowerDown): return Command::PDX; + case int(State::PrePowerDown): return Command::PDX; + case int(State::SelfRefresh): return Command::SREFX; + default: assert(false); + }}; + prereq[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::Closed): return Command::ACT; + case int(State::Opened): + if (node->row_state.find(id) != node->row_state.end()) + return cmd; + return Command::PRE; + default: assert(false); + }}; + // WR + prereq[int(Level::Rank)][int(Command::WR)] = prereq[int(Level::Rank)][int(Command::RD)]; + prereq[int(Level::Bank)][int(Command::WR)] = prereq[int(Level::Bank)][int(Command::RD)]; + // REF + prereq[int(Level::Rank)][int(Command::REF)] = [] (DRAM* node, Command cmd, int id) { + for (auto bank : node->children) { + if (bank->state == State::Closed) + continue; + return Command::PRA; + } + return Command::REF;}; + // PD + prereq[int(Level::Rank)][int(Command::PD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::PowerUp): return Command::PD; + case int(State::ActPowerDown): return Command::PD; + case int(State::PrePowerDown): return Command::PD; + case int(State::SelfRefresh): return Command::SREFX; + default: assert(false); + }}; + // SR + prereq[int(Level::Rank)][int(Command::SREF)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::PowerUp): return Command::SREF; + case int(State::ActPowerDown): return Command::PDX; + case int(State::PrePowerDown): return Command::PDX; + case int(State::SelfRefresh): return Command::SREF; + default: assert(false); + }}; +} + +// SAUGATA: added row hit check functions to see if the desired location is currently open +void WideIO2::init_rowhit() +{ + // RD + rowhit[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::Closed): return false; + case int(State::Opened): + if (node->row_state.find(id) != node->row_state.end()) + return true; + return false; + default: assert(false); + }}; + + // WR + rowhit[int(Level::Bank)][int(Command::WR)] = rowhit[int(Level::Bank)][int(Command::RD)]; +} + +void WideIO2::init_rowopen() +{ + // RD + rowopen[int(Level::Bank)][int(Command::RD)] = [] (DRAM* node, Command cmd, int id) { + switch (int(node->state)) { + case int(State::Closed): return false; + case int(State::Opened): return true; + default: assert(false); + }}; + + // WR + rowopen[int(Level::Bank)][int(Command::WR)] = rowopen[int(Level::Bank)][int(Command::RD)]; +} + +void WideIO2::init_lambda() +{ + lambda[int(Level::Bank)][int(Command::ACT)] = [] (DRAM* node, int id) { + node->state = State::Opened; + node->row_state[id] = State::Opened;}; + lambda[int(Level::Bank)][int(Command::PRE)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + lambda[int(Level::Rank)][int(Command::PRA)] = [] (DRAM* node, int id) { + for (auto bank : node->children) { + bank->state = State::Closed; + bank->row_state.clear();}}; + lambda[int(Level::Bank)][int(Command::RDA)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + lambda[int(Level::Bank)][int(Command::WRA)] = [] (DRAM* node, int id) { + node->state = State::Closed; + node->row_state.clear();}; + lambda[int(Level::Rank)][int(Command::PD)] = [] (DRAM* node, int id) { + for (auto bank : node->children) { + if (bank->state == State::Closed) + continue; + node->state = State::ActPowerDown; + return; + } + node->state = State::PrePowerDown;}; + lambda[int(Level::Rank)][int(Command::PDX)] = [] (DRAM* node, int id) { + node->state = State::PowerUp;}; + lambda[int(Level::Rank)][int(Command::SREF)] = [] (DRAM* node, int id) { + node->state = State::SelfRefresh;}; + lambda[int(Level::Rank)][int(Command::SREFX)] = [] (DRAM* node, int id) { + node->state = State::PowerUp;}; +} + + +void WideIO2::init_timing() +{ + SpeedEntry& s = speed_entry; + vector *t; + + /*** Channel ***/ + t = timing[int(Level::Channel)]; + + // CAS <-> CAS + t[int(Command::RD)].push_back({Command::RD, 1, s.nBL}); + t[int(Command::RD)].push_back({Command::RDA, 1, s.nBL}); + t[int(Command::RDA)].push_back({Command::RD, 1, s.nBL}); + t[int(Command::RDA)].push_back({Command::RDA, 1, s.nBL}); + t[int(Command::WR)].push_back({Command::WR, 1, s.nBL}); + t[int(Command::WR)].push_back({Command::WRA, 1, s.nBL}); + t[int(Command::WRA)].push_back({Command::WR, 1, s.nBL}); + t[int(Command::WRA)].push_back({Command::WRA, 1, s.nBL}); + + + /*** Rank ***/ + t = timing[int(Level::Rank)]; + + // CAS <-> CAS + t[int(Command::RD)].push_back({Command::RD, 1, s.nCCD}); + t[int(Command::RD)].push_back({Command::RDA, 1, s.nCCD}); + t[int(Command::RDA)].push_back({Command::RD, 1, s.nCCD}); + t[int(Command::RDA)].push_back({Command::RDA, 1, s.nCCD}); + t[int(Command::WR)].push_back({Command::WR, 1, s.nCCD}); + t[int(Command::WR)].push_back({Command::WRA, 1, s.nCCD}); + t[int(Command::WRA)].push_back({Command::WR, 1, s.nCCD}); + t[int(Command::WRA)].push_back({Command::WRA, 1, s.nCCD}); + t[int(Command::RD)].push_back({Command::WR, 1, s.nCL + s.nDQSCK + s.nBL + 1 - s.nCWL}); + t[int(Command::RD)].push_back({Command::WRA, 1, s.nCL + s.nDQSCK + s.nBL + 1 - s.nCWL}); + t[int(Command::RDA)].push_back({Command::WR, 1, s.nCL + s.nDQSCK + s.nBL + 1 - s.nCWL}); + t[int(Command::RDA)].push_back({Command::WRA, 1, s.nCL + s.nDQSCK + s.nBL + 1 - s.nCWL}); + t[int(Command::WR)].push_back({Command::RD, 1, s.nCWL + 1 + s.nBL + s.nWTR}); + t[int(Command::WR)].push_back({Command::RDA, 1, s.nCWL + 1 + s.nBL + s.nWTR}); + t[int(Command::WRA)].push_back({Command::RD, 1, s.nCWL + 1 + s.nBL + s.nWTR}); + t[int(Command::WRA)].push_back({Command::RDA, 1, s.nCWL + 1 + s.nBL + s.nWTR}); + + // CAS <-> CAS (between sibling ranks) + t[int(Command::RD)].push_back({Command::RD, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RD)].push_back({Command::RDA, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RDA)].push_back({Command::RD, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RDA)].push_back({Command::RDA, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RD)].push_back({Command::WR, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RD)].push_back({Command::WRA, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RDA)].push_back({Command::WR, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RDA)].push_back({Command::WRA, 1, s.nBL + s.nRTRS, true}); + t[int(Command::RD)].push_back({Command::WR, 1, s.nCL + s.nBL + s.nDQSCK + 1 + s.nRTRS - s.nCWL, true}); + t[int(Command::RD)].push_back({Command::WRA, 1, s.nCL + s.nBL + s.nDQSCK + 1 + s.nRTRS - s.nCWL, true}); + t[int(Command::RDA)].push_back({Command::WR, 1, s.nCL + s.nBL + s.nDQSCK + 1 + s.nRTRS - s.nCWL, true}); + t[int(Command::RDA)].push_back({Command::WRA, 1, s.nCL + s.nBL + s.nDQSCK + 1 + s.nRTRS - s.nCWL, true}); + t[int(Command::WR)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nRTRS - s.nCL, true}); + t[int(Command::WR)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nRTRS - s.nCL, true}); + t[int(Command::WRA)].push_back({Command::RD, 1, s.nCWL + s.nBL + s.nRTRS - s.nCL, true}); + t[int(Command::WRA)].push_back({Command::RDA, 1, s.nCWL + s.nBL + s.nRTRS - s.nCL, true}); + + // CAS <-> PRA + t[int(Command::RD)].push_back({Command::PRA, 1, s.nRTP}); + t[int(Command::WR)].push_back({Command::PRA, 1, s.nCWL + 1 + s.nBL + s.nWR}); + + // CAS <-> PD + t[int(Command::RD)].push_back({Command::PD, 1, s.nCL + s.nDQSCK + s.nBL + 1}); + t[int(Command::RDA)].push_back({Command::PD, 1, s.nCL + s.nDQSCK + s.nBL + 1}); + t[int(Command::WR)].push_back({Command::PD, 1, s.nCWL + 1 + s.nBL + s.nWR}); + t[int(Command::WRA)].push_back({Command::PD, 1, s.nCWL + 1 + s.nBL + s.nWR + 1}); // +1 for pre + t[int(Command::PDX)].push_back({Command::RD, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::RDA, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::WR, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::WRA, 1, s.nXP}); + + // CAS <-> SR: none (all banks have to be precharged) + + // RAS <-> RAS + t[int(Command::ACT)].push_back({Command::ACT, 1, s.nRRD}); + t[int(Command::ACT)].push_back({Command::ACT, 4, s.nFAW}); + t[int(Command::ACT)].push_back({Command::PRA, 1, s.nRAS}); + t[int(Command::PRA)].push_back({Command::ACT, 1, s.nRPab}); + + // RAS <-> REF + t[int(Command::PRE)].push_back({Command::REF, 1, s.nRPpb}); + t[int(Command::PRA)].push_back({Command::REF, 1, s.nRPab}); + t[int(Command::REF)].push_back({Command::ACT, 1, s.nRFCab}); + + // RAS <-> PD + t[int(Command::ACT)].push_back({Command::PD, 1, 1}); + t[int(Command::PDX)].push_back({Command::ACT, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::PRE, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::PRA, 1, s.nXP}); + + // RAS <-> SR + t[int(Command::PRE)].push_back({Command::SREF, 1, s.nRPpb}); + t[int(Command::PRA)].push_back({Command::SREF, 1, s.nRPab}); + t[int(Command::SREFX)].push_back({Command::ACT, 1, s.nXSR}); + + // REF <-> REF + t[int(Command::REF)].push_back({Command::REF, 1, s.nRFCab}); + t[int(Command::REF)].push_back({Command::REFPB, 1, s.nRFCab}); + t[int(Command::REFPB)].push_back({Command::REF, 1, s.nRFCpb}); + + // REF <-> PD + t[int(Command::REF)].push_back({Command::PD, 1, 1}); + t[int(Command::REFPB)].push_back({Command::PD, 1, 1}); + t[int(Command::PDX)].push_back({Command::REF, 1, s.nXP}); + t[int(Command::PDX)].push_back({Command::REFPB, 1, s.nXP}); + + // REF <-> SR + t[int(Command::SREFX)].push_back({Command::REF, 1, s.nXSR}); + t[int(Command::SREFX)].push_back({Command::REFPB, 1, s.nXSR}); + + // PD <-> PD + t[int(Command::PD)].push_back({Command::PDX, 1, s.nCKE}); + t[int(Command::PDX)].push_back({Command::PD, 1, s.nXP}); + + // PD <-> SR + t[int(Command::PDX)].push_back({Command::SREF, 1, s.nXP}); + t[int(Command::SREFX)].push_back({Command::PD, 1, s.nXSR}); + + // SR <-> SR + t[int(Command::SREF)].push_back({Command::SREFX, 1, s.nCKESR}); + t[int(Command::SREFX)].push_back({Command::SREF, 1, s.nXSR}); + + /*** Bank ***/ + t = timing[int(Level::Bank)]; + + // CAS <-> RAS + t[int(Command::ACT)].push_back({Command::RD, 1, s.nRCD}); + t[int(Command::ACT)].push_back({Command::RDA, 1, s.nRCD}); + t[int(Command::ACT)].push_back({Command::WR, 1, s.nRCD}); + t[int(Command::ACT)].push_back({Command::WRA, 1, s.nRCD}); + + t[int(Command::RD)].push_back({Command::PRE, 1, s.nRTP}); + t[int(Command::WR)].push_back({Command::PRE, 1, s.nCWL + 1 + s.nBL + s.nWR}); + + t[int(Command::RDA)].push_back({Command::ACT, 1, s.nRTP + s.nRPpb}); + t[int(Command::WRA)].push_back({Command::ACT, 1, s.nCWL + 1 + s.nBL + s.nWR + s.nRPpb}); + + // RAS <-> RAS + t[int(Command::ACT)].push_back({Command::ACT, 1, s.nRC}); + t[int(Command::ACT)].push_back({Command::PRE, 1, s.nRAS}); + t[int(Command::PRE)].push_back({Command::ACT, 1, s.nRPpb}); + t[int(Command::PRE)].push_back({Command::REFPB, 1, s.nRPpb}); + + // between different banks + t[int(Command::ACT)].push_back({Command::REFPB, 1, s.nRRD, true}); + t[int(Command::REFPB)].push_back({Command::ACT, 1, s.nRRD, true}); + + // REFPB + t[int(Command::REFPB)].push_back({Command::REFPB, 1, s.nRFCpb}); + t[int(Command::REFPB)].push_back({Command::ACT, 1, s.nRFCpb}); +} diff --git a/src/WideIO2.h b/src/WideIO2.h new file mode 100644 index 0000000..120576a --- /dev/null +++ b/src/WideIO2.h @@ -0,0 +1,197 @@ +#ifndef __WIDEIO2_H +#define __WIDEIO2_H + +#include "DRAM.h" +#include "Request.h" +#include +#include + +using namespace std; + +namespace ramulator +{ + +class WideIO2 +{ +public: + static string standard_name; + enum class Org; + enum class Speed; + WideIO2(Org org, Speed speed, int channels = 4); + WideIO2(const string& org_str, const string& speed_str, int channels = 4); + + static map org_map; + static map speed_map; + + /*** Level ***/ + enum class Level : int + { + Channel, Rank, Bank, Row, Column, MAX + }; + + /*** Command ***/ + enum class Command : int + { + ACT, PRE, PRA, + RD, WR, RDA, WRA, + REF, REFPB, PD, PDX, SREF, SREFX, + MAX + }; + + string command_name[int(Command::MAX)] = { + "ACT", "PRE", "PRA", + "RD", "WR", "RDA", "WRA", + "REF", "REFPB", "PD", "PDX", "SREF", "SREFX" + }; + + Level scope[int(Command::MAX)] = { + Level::Row, Level::Bank, Level::Rank, + Level::Column, Level::Column, Level::Column, Level::Column, + Level::Rank, Level::Bank, Level::Rank, Level::Rank, Level::Rank, Level::Rank + }; + + bool is_opening(Command cmd) + { + switch(int(cmd)) { + case int(Command::ACT): + return true; + default: + return false; + } + } + + bool is_accessing(Command cmd) + { + switch(int(cmd)) { + case int(Command::RD): + case int(Command::WR): + case int(Command::RDA): + case int(Command::WRA): + return true; + default: + return false; + } + } + + bool is_closing(Command cmd) + { + switch(int(cmd)) { + case int(Command::RDA): + case int(Command::WRA): + case int(Command::PRE): + case int(Command::PRA): + return true; + default: + return false; + } + } + + bool is_refreshing(Command cmd) + { + switch(int(cmd)) { + case int(Command::REF): + case int(Command::REFPB): + return true; + default: + return false; + } + } + + + /* State */ + enum class State : int + { + Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX + } start[int(Level::MAX)] = { + State::MAX, State::PowerUp, State::Closed, State::Closed, State::MAX + }; + + /* Translate */ + Command translate[int(Request::Type::MAX)] = { + Command::RD, Command::WR, + Command::REF, Command::PD, Command::SREF + }; + + /* Prerequisite */ + function*, Command cmd, int)> prereq[int(Level::MAX)][int(Command::MAX)]; + + // SAUGATA: added function object container for row hit status + /* Row hit */ + function*, Command cmd, int)> rowhit[int(Level::MAX)][int(Command::MAX)]; + function*, Command cmd, int)> rowopen[int(Level::MAX)][int(Command::MAX)]; + + /* Timing */ + struct TimingEntry + { + Command cmd; + int dist; + int val; + bool sibling; + }; + vector timing[int(Level::MAX)][int(Command::MAX)]; + + /* Lambda */ + function*, int)> lambda[int(Level::MAX)][int(Command::MAX)]; + + /* Organization */ + enum class Org : int + { + // per-die density + WideIO2_8Gb, + // WideIO2_12Gb, tRFC TBD + // WideIO2_16Gb, tRFC TBD + // WideIO2_24Gb, TBD + // WideIO2_32Gb, TBD + MAX + }; + + struct OrgEntry { + int size; // per-channel density + int dq; + int count[int(Level::MAX)]; + } org_entry; + + void set_channel_number(int channel); + void set_rank_number(int rank); + + /* Speed */ + enum class Speed : int + { + WideIO2_800, + WideIO2_1066, + MAX + }; + // WideIO2 specified /4, /2, x1, x2, x4 refresh rates. x1 is used here + + int prefetch_size = 4; + int channel_width = 64; + + struct SpeedEntry { + int rate; + double freq, tCK; + int nBL, nCCD, nDQSCK, nRTRS; // 4n prefetch, DDR (although 8n is allowed?) + int nCL, nRCD, nRPpb, nRP8b, nRPab, nCWL; + int nRAS, nRC; + int nRTP, nWTR, nWR; + int nRRD, nFAW; + int nRFCab, nRFCpb, nREFI; + int nCKE, nXP; + int nCKESR, nXSR; + } speed_table[int(Speed::MAX)] = { + { 800, 800.0/3*3, 2.5*3/3, 2, 2, 1, 2, 7, 8, 8, 9, 0, 5, 17, 25, 3, 4, 8, 4, 24, 72, 36, 1560, 3, 3, 6, 76}, + {1066, 800.0/3*4, 2.5*3/4, 2, 2, 1, 2, 9, 10, 10, 12, 0, 7, 23, 33, 4, 6, 11, 6, 32, 96, 48, 2080, 3, 4, 8, 102} + }, speed_entry; + + int read_latency; + +private: + void init_lambda(); + void init_prereq(); + void init_rowhit(); // SAUGATA: added function to check for row hits + void init_rowopen(); + void init_timing(); +}; + +} /*namespace ramulator*/ + +#endif /*__WIDEIO2_H*/ diff --git a/src/common.cpp b/src/common.cpp new file mode 100644 index 0000000..21e79d0 --- /dev/null +++ b/src/common.cpp @@ -0,0 +1,375 @@ +#include "common.h" + +int GL::vaBufferDepth = 4096; +int GL::vbBufferDepth = 4096; +int GL::vpBufferDepth = 4096; + +long GL::vaMemAddr = 0; +long GL::vbMemAddr = 32768; +long GL::vpMemAddr = 65536; + +int GL::vaLen = 4096; +int GL::vbLen = 4096; +int GL::vpLen = 4096; + +long GL::reqIdx = -1; +long GL::burstIdx = -1; +int GL::burstLen = 64; +int GL::burstAddrWidth = GL::getBurstAddrWidth(); + +long GL::getBurstIdx(){ + burstIdx++; + return burstIdx; +} + +long GL::getReqIdx(){ + reqIdx++; + return reqIdx; +} + +// Calculate the # of bits when mapping a basic memory burst to the address. +int GL::getBurstAddrWidth(){ + + int width = 1; + int val = 1; + for(int i = 0; i <= 10; i++){ + if(val == burstLen){ + return width; + } + else{ + width++; + val = val * 2; + } + } + + HERE; + std::cout << "burstLen is not power(2,n)." << std::endl; + exit(EXIT_FAILURE); + +} + + +// Overload ostream of type for convenient output +std::ostream& operator<< (std::ostream &os, const ramulator::Request::Type &type){ + + switch (type){ + case ramulator::Request::Type::READ: + os << "READ"; + break; + case ramulator::Request::Type::WRITE: + os << "WRITE"; + break; + case ramulator::Request::Type::REFRESH: + os << "REFRESH"; + break; + case ramulator::Request::Type::POWERDOWN: + os << "POWERDOWN"; + break; + case ramulator::Request::Type::SELFREFRESH: + os << "SELFREFRESH"; + break; + case ramulator::Request::Type::EXTENSION: + os << "EXTENSION"; + break; + case ramulator::Request::Type::MAX: + os << "MAX"; + break; + default: + os << "Unknown Type"; + break; + } + + return os; +} + +std::ostream& operator<<(std::ostream &os, const BurstOp &op){ + + os << "valid: " << op.valid << " "; + os << "type: " << op.type << " "; + os << "burstIdx: " << op.burstIdx << " "; + os << "peIdx: " << op.peIdx << " "; + os << "addr: " << op.addr << " "; + os << "length: " << op.length << " "; + os << "localAddr " << op.localAddr << " "; + + os << "departPeTime: " << op.departPeTime << " "; + os << "arriveMemTime: " << op.arriveMemTime << " "; + os << "departMemTime: " << op.departMemTime << " "; + os << "arrivePeTime: " << op.arrivePeTime << " "; + + return os; +} + +BurstOp::BurstOp( + ramulator::Request::Type _type, + long _burstIdx, + int _peIdx, + long _addr, + int _length, + int _localAddr) +{ + valid = true; + type = _type; + burstIdx = _burstIdx; + peIdx = _peIdx; + addr = _addr; + length = _length; + localAddr = _localAddr; + departPeTime = 0; + arriveMemTime = 0; + departMemTime = 0; + arrivePeTime = 0; +} + +BurstOp::BurstOp(bool _valid){ + valid = _valid; + type = ramulator::Request::Type::READ; + peIdx = 0; + addr = 0; + burstIdx = 0; + length = 0; + localAddr = 0; + departPeTime = 0; + arriveMemTime = 0; + departMemTime = 0; + arrivePeTime = 0; +} + +void BurstOp::operator=(const BurstOp &op){ + + valid = op.valid; + type = op.type; + burstIdx = op.burstIdx; + peIdx = op.peIdx; + addr = op.addr; + length = op.length; + localAddr = op.localAddr; + reqVec = op.reqVec; + addrVec = op.addrVec; + data = op.data; + + departPeTime = op.departPeTime; + arriveMemTime = op.arriveMemTime; + departMemTime = op.departMemTime; + arrivePeTime = op.arrivePeTime; + +} + +// We may ignore the vector data and it should be fine. +bool BurstOp::operator==(const BurstOp &op) const{ + + bool equal = true;; + equal &= (valid == op.valid); + equal &= (type == op.type); + equal &= (burstIdx == op.burstIdx); + equal &= (peIdx == op.peIdx); + equal &= (addr == op.addr); + equal &= (length == op.length); + equal &= (localAddr == op.localAddr); + + equal &= (departPeTime == op.departPeTime); + equal &= (arriveMemTime == op.arriveMemTime); + equal &= (departMemTime == op.departMemTime); + equal &= (arrivePeTime == op.arrivePeTime); + + return equal; + +} + +void sc_trace(sc_trace_file *tf, const BurstOp &op, const std::string &name){ + + std::ostringstream oss; + oss << op.type; + sc_trace(tf, op.valid, name+".valid"); + sc_trace(tf, oss.str().c_str(), name+".type"); + sc_trace(tf, op.burstIdx, name+".burstIdx"); + sc_trace(tf, op.peIdx, name+".peIdx"); + sc_trace(tf, op.addr, name+".addr"); + sc_trace(tf, op.length, name+".length"); + sc_trace(tf, op.localAddr, name+".localAddr"); + sc_trace(tf, op.departPeTime, name+".departPeTime"); + sc_trace(tf, op.arriveMemTime, name+".arriveMemTime"); + sc_trace(tf, op.departMemTime, name+".departMemTime"); + sc_trace(tf, op.arrivePeTime, name+".arrivePeTime"); + +} + +// Convert the burst operations to basic memory requests +// and put the basic requests in a queue. +void BurstOp::convertToReq(std::list &reqQueue){ + int reqNum = getReqNum(); + for(int i = 0; i < reqNum; i++){ + ramulator::Request req; + req.type = type; + req.addr = addrVec[i]; + req.udf.burstIdx = burstIdx; + req.udf.reqIdx = reqVec[i]; + req.udf.peIdx = peIdx; + req.udf.departPeTime = departPeTime; + req.udf.arriveMemTime = arriveMemTime; + req.udf.departMemTime = departMemTime; + req.udf.arrivePeTime = arrivePeTime; + reqQueue.push_back(req); + } +} + +// Align address to the memory burst +long BurstOp::getAlignedAddr() const { + long alignedAddr = (addr >> GL::burstAddrWidth) << GL::burstAddrWidth; + return alignedAddr; +} + +// Calculate the offset to the aligned addr; +int BurstOp::getOffset() const { + long offset = addr - getAlignedAddr(); + return (int) offset; +} + +int BurstOp::getReqNum() const { + + int reqNum; + long offset = getOffset(); + if(offset == 0){ + if(length%GL::burstLen == 0){ + reqNum = length/GL::burstLen; + } + else{ + reqNum = length/GL::burstLen + 1; + } + } + else{ + reqNum = 1; + int residueLen = length - (GL::burstLen - offset); + if(residueLen%GL::burstLen == 0){ + reqNum += residueLen/GL::burstLen; + } + else{ + reqNum += residueLen/GL::burstLen + 1; + } + } + + return reqNum; + +} + +void BurstOp::updateReqVec() { + + int reqNum = getReqNum(); + for(int i = 0; i < reqNum; i++){ + reqVec.push_back(GL::getReqIdx()); + } + +} + +void BurstOp::updateAddrVec() { + + int reqNum = getReqNum(); + int offset = getOffset(); + long reqAddr; + + if(offset == 0){ + reqAddr = addr; + for(int i = 0; i < reqNum; i++){ + addrVec.push_back(reqAddr); + reqAddr += GL::burstLen; + } + } + else{ + reqAddr = getAlignedAddr(); + addrVec.push_back(reqAddr); + int reqLen = GL::burstLen - offset; + while(reqLen < length){ + reqAddr += GL::burstLen; + addrVec.push_back(reqAddr); + if(reqLen + GL::burstLen <= length){ + reqLen += GL::burstLen; + } + else{ + reqLen = length; + } + } + } +} + +// Needs to be fixed latter +BurstOp::~BurstOp(){} + +long BurstOp::getDepartPeTime() const{ + return departPeTime; +} + +long BurstOp::getArrivePeTime() const{ + return arrivePeTime; +} + +long BurstOp::getDepartMemTime() const{ + return departMemTime; +} + +long BurstOp::getArriveMemTime() const{ + return arriveMemTime; +} + +void BurstOp::setDepartPeTime(long departTime){ + departPeTime = departTime; +} + +void BurstOp::setArrivePeTime(long arriveTime){ + arrivePeTime = arriveTime; +} + +void BurstOp::setDepartMemTime(long departTime){ + departMemTime = departTime; +} + +void BurstOp::setArriveMemTime(long arriveTime){ + arriveMemTime = arriveTime; +} + +// Basically it copies the data attached to the read burst response to on chip buffer. +void BurstOp::burstReqToBuffer(std::vector &buffer, int localAddr){ + char* p = (char*) malloc(sizeof(int)); + if(length%sizeof(int) != 0){ + HERE; + std::cout << "The burst request length is not aligned to the buffer type."; + std::cout << std::endl; + exit(EXIT_FAILURE); + } + int index = localAddr; + for(int i = 0; i < length;){ + for(int j = 0; j < (int)sizeof(int); j++){ + *(p+j) = data[i]; + i++; + } + buffer[index] = *((int*)p); + index++; + } + delete p; +} + +// This fucntion copies the data from local buffer to the write burst request data section. +void BurstOp::bufferToBurstReq(std::vector &buffer, int localAddr){ + int* p = (int*)malloc(sizeof(int)); + int size = length/sizeof(int); + int index = localAddr; + for(int i = 0; i < size; i++){ + *p = buffer[index]; + index++; + for(int j = 0; j < (int)sizeof(int); j++){ + data.push_back(*((char*)p+j)); + } + } +} + +void BurstOp::ramToReq(const std::vector &ramData){ + for(int i = 0; i < length; i++){ + data.push_back(ramData[addr+i]); + } +} + +void BurstOp::reqToRam(std::vector &ramData){ + for(int i = 0; i < length; i++){ + ramData[addr+i] = data[i]; + } +} + diff --git a/src/common.h b/src/common.h new file mode 100644 index 0000000..ab51922 --- /dev/null +++ b/src/common.h @@ -0,0 +1,127 @@ +#ifndef __COMMON_H__ +#define __COMMON_H__ + +#include +#include +#include "Request.h" +#include "systemc.h" + +std::ostream& operator<< (std::ostream &os, const ramulator::Request::Type &type); + +class GL{ + public: + // Application parameters + static int vaLen; + static int vbLen; + static int vpLen; + + // Initial va, vb, and vp address. + // Suppose they stay in a continuous address space. + static long vaMemAddr; + static long vbMemAddr; + static long vpMemAddr; + + // Processing element setup + static int vaBufferDepth; + static int vbBufferDepth; + static int vpBufferDepth; + + // It will be reset based on memory configuration + static int burstLen; + static int burstAddrWidth; + static long getReqIdx(); + static long getBurstIdx(); + + private: + static long reqIdx; + static long burstIdx; + static int getBurstAddrWidth(); +}; + +// ---------------------------------------------------------------------------- +// The burst operation is decoded in the memory wrapper and +// it provides a simple and easy-to-use interface to the processing elements. +// Although the data between the memory wrapper and the pe is supposed to +// be transmitted word by word, now we will not send the burst data +// untill the whole burst transmission from the ramulator is +// detected while the real system may does the transmission gradually. +// Basically the difference is where we are going to +// buffer the partital data in the system. Since +// buffering in memory controller makes the +// whole system much more convenient and it is precise enough to simulate the +// data transmission, we adopt it in the simulator. +// ---------------------------------------------------------------------------- +struct BurstOp{ + + public: + bool valid; + ramulator::Request::Type type; + long burstIdx; + int peIdx; + long addr; + int length; + + // corresponding local buffer address + int localAddr; + + // Each burst operation consists of multiple basic memory requests/responses + // and the memory opid and address will be stored in the vector. + std::vector reqVec; + std::vector addrVec; + + void convertToReq(std::list &reqQueue); + void burstReqToBuffer(std::vector &buffer, int localAddr); + void bufferToBurstReq(std::vector &buffer, int localAddr); + + // Overloaded operators that are requred to support sc_in/out port + void operator=(const BurstOp &op); + bool operator==(const BurstOp &op) const; + friend void sc_trace(sc_trace_file *tf, const BurstOp &op, const std::string &name); + friend std::ostream& operator<<(std::ostream &os, const BurstOp &op); + + void setDepartPeTime(long departTime); + void setArrivePeTime(long arriveTime); + void setDepartMemTime(long departTime); + void setArriveMemTime(long arriveTime); + + long getDepartPeTime() const; + long getArrivePeTime() const; + long getDepartMemTime() const; + long getArriveMemTime() const; + int getReqNum() const; + + void updateReqVec(); + void updateAddrVec(); + + void ramToReq(const std::vector &ramData); + void reqToRam(std::vector &ramData); + + // Constructors + BurstOp(ramulator::Request::Type _type, + long _burstIdx, + int _peIdx, + long _addr, + int _length, + int localAddr); + + BurstOp(bool _valid = false); + + ~BurstOp(); + + private: + long departPeTime; + long arriveMemTime; + long departMemTime; + long arrivePeTime; + + // Attached data. + std::vector data; + + long getAlignedAddr() const; + int getOffset() const; +}; + +// This macro is used to locate the code position. +#define HERE do {std::cout <<"File: " << __FILE__ << " Line: " << __LINE__ << std::endl;} while(0) + +#endif diff --git a/src/cscope.files b/src/cscope.files new file mode 100644 index 0000000..7eff81b --- /dev/null +++ b/src/cscope.files @@ -0,0 +1,53 @@ +ALDRAM.cpp +ALDRAM.h +Cache.cpp +Cache.h +common.cpp +common.h +Config.cpp +Config.h +Controller.cpp +Controller.h +DDR3.cpp +DDR3.h +DDR4.cpp +DDR4.h +DRAM.h +DSARP.cpp +DSARP.h +GDDR5.cpp +GDDR5.h +Gem5Wrapper.cpp +Gem5Wrapper.h +HBM.cpp +HBM.h +LPDDR3.cpp +LPDDR3.h +LPDDR4.cpp +LPDDR4.h +Main.cpp +MemoryFactory.cpp +MemoryFactory.h +Memory.h +MemWrapper.cpp +MemWrapper.h +pe.cpp +pe.h +Processor.cpp +Processor.h +Refresh.cpp +Refresh.h +Request.h +SALP.cpp +SALP.h +Scheduler.h +SpeedyController.h +Statistics.h +StatType.cpp +StatType.h +TLDRAM.cpp +TLDRAM.h +WideIO2.cpp +WideIO2.h +WideIO.cpp +WideIO.h diff --git a/src/cscope.out b/src/cscope.out new file mode 100644 index 0000000..4d2e401 --- /dev/null +++ b/src/cscope.out @@ -0,0 +1,105565 @@ +cscope 15 $HOME/gitrepo/graph_accelerator/ramulator_example/src 0000544025 + @ALDRAM.cpp + +1  + ~ + +3  + ~"ALDRAM.h +" + +4  + ~"DRAM.h +" + +5  + ~ + +6  + ~ + +7  + ~<ÿs£¹ +> + +9 +usšg + +Çme¥aû + + g¡d +; + +10 +usšg + +Çme¥aû + + g¿muÏtÜ +; + +12 +¡ršg + + gALDRAM +:: +¡ªd¬d_Çme + = "ALDRAM"; + +14 + gm­ +< + g¡ršg +, + gALDRAM +:: +Org +> +ALDRAM +:: +Üg_m­ + = { + +15 {"ALDRAM_512Mb_x4", +ALDRAM +:: +Org +:: +ALDRAM_512Mb_x4 +}, {"ALDRAM_512Mb_x8", ALDRAM::Org:: +ALDRAM_512Mb_x8 +}, {"ALDRAM_512Mb_x16", ALDRAM::Org:: +ALDRAM_512Mb_x16 +}, + +16 {"ALDRAM_1Gb_x4", +ALDRAM +:: +Org +:: +ALDRAM_1Gb_x4 +}, {"ALDRAM_1Gb_x8", ALDRAM::Org:: +ALDRAM_1Gb_x8 +}, {"ALDRAM_1Gb_x16", ALDRAM::Org:: +ALDRAM_1Gb_x16 +}, + +17 {"ALDRAM_2Gb_x4", +ALDRAM +:: +Org +:: +ALDRAM_2Gb_x4 +}, {"ALDRAM_2Gb_x8", ALDRAM::Org:: +ALDRAM_2Gb_x8 +}, {"ALDRAM_2Gb_x16", ALDRAM::Org:: +ALDRAM_2Gb_x16 +}, + +18 {"ALDRAM_4Gb_x4", +ALDRAM +:: +Org +:: +ALDRAM_4Gb_x4 +}, {"ALDRAM_4Gb_x8", ALDRAM::Org:: +ALDRAM_4Gb_x8 +}, {"ALDRAM_4Gb_x16", ALDRAM::Org:: +ALDRAM_4Gb_x16 +}, + +19 {"ALDRAM_8Gb_x4", +ALDRAM +:: +Org +:: +ALDRAM_8Gb_x4 +}, {"ALDRAM_8Gb_x8", ALDRAM::Org:: +ALDRAM_8Gb_x8 +}, {"ALDRAM_8Gb_x16", ALDRAM::Org:: +ALDRAM_8Gb_x16 +}, + +22 + gm­ +< + g¡ršg +, + gALDRAM +:: +S³ed +> +ALDRAM +:: +¥“d_m­ + = { + +23 {"ALDRAM_800D", +ALDRAM +:: +S³ed +:: +ALDRAM_800D +}, {"ALDRAM_800E", ALDRAM::S³ed:: +ALDRAM_800E +}, + +24 {"ALDRAM_1066E", +ALDRAM +:: +S³ed +:: +ALDRAM_1066E +}, {"ALDRAM_1066F", ALDRAM::S³ed:: +ALDRAM_1066F +}, {"ALDRAM_1066G", ALDRAM::S³ed:: +ALDRAM_1066G +}, + +25 {"ALDRAM_1333G", +ALDRAM +:: +S³ed +:: +ALDRAM_1333G +}, {"ALDRAM_1333H", ALDRAM::S³ed:: +ALDRAM_1333H +}, + +26 {"ALDRAM_1600H", +ALDRAM +:: +S³ed +:: +ALDRAM_1600H +}, {"ALDRAM_1600J", ALDRAM::S³ed:: +ALDRAM_1600J +}, {"ALDRAM_1600K", ALDRAM::S³ed:: +ALDRAM_1600K +}, + +27 {"ALDRAM_1866K", +ALDRAM +:: +S³ed +:: +ALDRAM_1866K +}, {"ALDRAM_1866L", ALDRAM::S³ed:: +ALDRAM_1866L +}, + +28 {"ALDRAM_2133L", +ALDRAM +:: +S³ed +:: +ALDRAM_2133L +}, {"ALDRAM_2133M", ALDRAM::S³ed:: +ALDRAM_2133M +}, + +32 + gALDRAM +:: + $ALDRAM +( +Org + +Üg +, +S³ed + +¥“d +) : + +33 + `Üg_’Œy +( +Üg_bË +[( +Üg +)]), + +34 + `¥“d_’Œy +( +¥“d_bË +[( +Temp +:: +COLD +)][( +¥“d +)]), + +35 + `»ad_Ï‹ncy +( +¥“d_’Œy +. +nCL + + s³ed_’Œy. +nBL +) + +37 +cu¼’t_¥“d + = +¥“d +; + +38 + `š™_¥“d +(); + +39 + `š™_´”eq +(); + +40 + `š™_rowh™ +(); + +41 + `š™_Ïmbda +(); + +42 + `š™_timšg +( +¥“d_bË +[( +Temp +:: +HOT +)][( +¥“d +)]); + +43 +‹m³¿tu» + = +Temp +:: +COLD +; + +44 + } +} + +46 + gALDRAM +:: + $ALDRAM +(cÚ¡ +¡ršg +& +Üg_¡r +, cÚ¡ sŒšg& +¥“d_¡r +) : + +47 + $ALDRAM +( +Üg_m­ +[ +Üg_¡r +], +¥“d_m­ +[ +¥“d_¡r +]) + +49 + } +} + +51  + gALDRAM +:: + $£t_chªÃl_numb” +( +chªÃl +) { + +52 +Üg_’Œy +. +couÁ +[( +Lev– +:: +ChªÃl +)] = +chªÃl +; + +53 + } +} + +55  + gALDRAM +:: + $£t_¿nk_numb” +( +¿nk +) { + +56 +Üg_’Œy +. +couÁ +[( +Lev– +:: +Rªk +)] = +¿nk +; + +57 + } +} + +59  + gALDRAM +:: + $®d¿m_timšg +( +Temp + +cu¼’t_‹m³¿tu» +) + +61  +i + = 0; i < ( +Lev– +:: +MAX +); i++) { + +62  +j + = 0; j < ( +Commªd +:: +MAX +); j++) { + +63 +timšg +[ +i +][ +j +]. + `þ—r +(); + +66 +‹m³¿tu» + = +cu¼’t_‹m³¿tu» +; + +67 +»ad_Ï‹ncy + = +¥“d_’Œy +. +nCL + + s³ed_’Œy. +nBL +; + +68 + `š™_timšg +( +¥“d_bË +[( +‹m³¿tu» +)][( +cu¼’t_¥“d +)]); + +73 + } +} + +75  + gALDRAM +:: + $š™_¥“d +() + +78  +·ge + = ( +Üg_’Œy +. +dq + * org_’Œy. +couÁ +[( +Lev– +:: +CÞumn +)]) >> 13; + +79  +¥“d_’Œy +. +¿‹ +) { + +80 800: +¥“d_’Œy +. +nRRD + = ( +·ge +==1è? 4 : 4; s³ed_’Œy. +nFAW + = (page==1) ? 16 : 20; ; + +81 1066: +¥“d_’Œy +. +nRRD + = ( +·ge +==1è? 4 : 6; s³ed_’Œy. +nFAW + = (page==1) ? 20 : 27; ; + +82 1333: +¥“d_’Œy +. +nRRD + = ( +·ge +==1è? 4 : 5; s³ed_’Œy. +nFAW + = (page==1) ? 20 : 30; ; + +83 1600: +¥“d_’Œy +. +nRRD + = ( +·ge +==1è? 5 : 6; s³ed_’Œy. +nFAW + = (page==1) ? 24 : 32; ; + +84 1866: +¥“d_’Œy +. +nRRD + = ( +·ge +==1è? 5 : 6; s³ed_’Œy. +nFAW + = (page==1) ? 26 : 33; ; + +85 2133: +¥“d_’Œy +. +nRRD + = ( +·ge +==1è? 5 : 6; s³ed_’Œy. +nFAW + = (page==1) ? 27 : 34; ; + +86 : + `as£¹ +( +çl£ +); + +90  +ch + = +Üg_’Œy +. +size +; + +91  +¥“d_’Œy +. +¿‹ +) { + +92 800: +¥“d_’Œy +. +nRFC + = ( +ch +==512) ? 36 : (chip==1<<10) ? 44 : (chip==1<<11) ? 64 : (chip==1<<12) ? 104 : 140; ; + +93 1066: +¥“d_’Œy +. +nRFC + = ( +ch +==512) ? 48 : (chip==1<<10) ? 59 : (chip==1<<11) ? 86 : (chip==1<<12) ? 139 : 187; ; + +94 1333: +¥“d_’Œy +. +nRFC + = ( +ch +==512) ? 60 : (chip==1<<10) ? 74 : (chip==1<<11) ? 107 : (chip==1<<12) ? 174 : 234; ; + +95 1600: +¥“d_’Œy +. +nRFC + = ( +ch +==512) ? 72 : (chip==1<<10) ? 88 : (chip==1<<11) ? 128 : (chip==1<<12) ? 208 : 280; ; + +96 1866: +¥“d_’Œy +. +nRFC + = ( +ch +==512) ? 84 : (chip==1<<10) ? 103 : (chip==1<<11) ? 150 : (chip==1<<12) ? 243 : 327; ; + +97 2133: +¥“d_’Œy +. +nRFC + = ( +ch +==512) ? 96 : (chip==1<<10) ? 118 : (chip==1<<11) ? 171 : (chip==1<<12) ? 278 : 374; ; + +98 : + `as£¹ +( +çl£ +); + +100  +¥“d_’Œy +. +¿‹ +) { + +101 800: +¥“d_’Œy +. +nXS + = ( +ch +==512) ? 40 : (chip==1<<10) ? 48 : (chip==1<<11) ? 68 : (chip==1<<12) ? 108 : 144; ; + +102 1066: +¥“d_’Œy +. +nXS + = ( +ch +==512) ? 54 : (chip==1<<10) ? 64 : (chip==1<<11) ? 91 : (chip==1<<12) ? 144 : 192; ; + +103 1333: +¥“d_’Œy +. +nXS + = ( +ch +==512) ? 67 : (chip==1<<10) ? 80 : (chip==1<<11) ? 114 : (chip==1<<12) ? 180 : 240; ; + +104 1600: +¥“d_’Œy +. +nXS + = ( +ch +==512) ? 80 : (chip==1<<10) ? 96 : (chip==1<<11) ? 136 : (chip==1<<12) ? 216 : 288; ; + +105 1866: +¥“d_’Œy +. +nXS + = ( +ch +==512) ? 94 : (chip==1<<10) ? 112 : (chip==1<<11) ? 159 : (chip==1<<12) ? 252 : 336; ; + +106 2133: +¥“d_’Œy +. +nXS + = ( +ch +==512) ? 107 : (chip==1<<10) ? 128 : (chip==1<<11) ? 182 : (chip==1<<12) ? 288 : 384; ; + +107 : + `as£¹ +( +çl£ +); + +109 + } +} + +112  + gALDRAM +:: + $š™_´”eq +() + +115 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +ALDRAM +>* +node +, Commªd +cmd +,  +id +) { + +116 ( +node +-> +¡©e +)) { + +117 ( +S‹ +:: +Pow”Up +):  +Commªd +:: +MAX +; + +118 ( +S‹ +:: +AùPow”Down +):  +Commªd +:: +PDX +; + +119 ( +S‹ +:: +P»Pow”Down +):  +Commªd +:: +PDX +; + +120 ( +S‹ +:: +S–fReäesh +):  +Commªd +:: +SRX +; + +121 : + `as£¹ +( +çl£ +); + +123 +´”eq +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +ALDRAM +>* +node +, Commªd +cmd +,  +id +) { + +124 ( +node +-> +¡©e +)) { + +125 ( +S‹ +:: +Clo£d +):  +Commªd +:: +ACT +; + +126 ( +S‹ +:: +O³Ãd +): + +127 ià( +node +-> +row_¡©e +. + `fšd +( +id +è!ðnode->row_¡©e. + `’d +()) + +128  +cmd +; + +129  +Commªd +:: +PRE +; + +130 : + `as£¹ +( +çl£ +); + +134 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +WR +)] =…»»q[(Lev–::Rªk)][(Commªd:: +RD +)]; + +135 +´”eq +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] =…»»q[(Lev–::Bªk)][(Commªd:: +RD +)]; + +138 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +REF +)] = [] ( +DRAM +< +ALDRAM +>* +node +, Commªd +cmd +,  +id +) { + +139 autØ +bªk + : +node +-> +chžd»n +) { + +140 ià( +bªk +-> +¡©e + =ð +S‹ +:: +Clo£d +) + +142  +Commªd +:: +PREA +; + +144  +Commªd +:: +REF +;}; + +147 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PDE +)] = [] ( +DRAM +< +ALDRAM +>* +node +, Commªd +cmd +,  +id +) { + +148 ( +node +-> +¡©e +)) { + +149 ( +S‹ +:: +Pow”Up +):  +Commªd +:: +PDE +; + +150 ( +S‹ +:: +AùPow”Down +):  +Commªd +:: +PDE +; + +151 ( +S‹ +:: +P»Pow”Down +):  +Commªd +:: +PDE +; + +152 ( +S‹ +:: +S–fReäesh +):  +Commªd +:: +SRX +; + +153 : + `as£¹ +( +çl£ +); + +157 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +SRE +)] = [] ( +DRAM +< +ALDRAM +>* +node +, Commªd +cmd +,  +id +) { + +158 ( +node +-> +¡©e +)) { + +159 ( +S‹ +:: +Pow”Up +):  +Commªd +:: +SRE +; + +160 ( +S‹ +:: +AùPow”Down +):  +Commªd +:: +PDX +; + +161 ( +S‹ +:: +P»Pow”Down +):  +Commªd +:: +PDX +; + +162 ( +S‹ +:: +S–fReäesh +):  +Commªd +:: +SRE +; + +163 : + `as£¹ +( +çl£ +); + +165 + } +} + +168  + gALDRAM +:: + $š™_rowh™ +() + +171 +rowh™ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +ALDRAM +>* +node +, Commªd +cmd +,  +id +) { + +172 ( +node +-> +¡©e +)) { + +173 ( +S‹ +:: +Clo£d +):  +çl£ +; + +174 ( +S‹ +:: +O³Ãd +): + +175 ià( +node +-> +row_¡©e +. + `fšd +( +id +è!ðnode->row_¡©e. + `’d +()) + +176  +Œue +; + +177  +çl£ +; + +178 : + `as£¹ +( +çl£ +); + +182 +rowh™ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] =„owh™[(Lev–::Bªk)][(Commªd:: +RD +)]; + +183 + } +} + +186  + gALDRAM +:: + $š™_Ïmbda +() + +188 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +ACT +)] = [] ( +DRAM +< +ALDRAM +>* +node +,  +id +) { + +189 +node +-> +¡©e + = +S‹ +:: +O³Ãd +; + +190 +node +-> +row_¡©e +[ +id +] = +S‹ +:: +O³Ãd +;}; + +191 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +PRE +)] = [] ( +DRAM +< +ALDRAM +>* +node +,  +id +) { + +192 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +193 +node +-> +row_¡©e +. + `þ—r +();}; + +194 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PREA +)] = [] ( +DRAM +< +ALDRAM +>* +node +,  +id +) { + +195 autØ +bªk + : +node +-> +chžd»n +) { + +196 +bªk +-> +¡©e + = +S‹ +:: +Clo£d +; + +197 +bªk +-> +row_¡©e +. + `þ—r +();}}; + +198 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +REF +)] = [] ( +DRAM +< +ALDRAM +>* +node +,  +id +) {}; + +199 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +ALDRAM +>* +node +,  +id +) {}; + +200 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] = [] ( +DRAM +< +ALDRAM +>* +node +,  +id +) {}; + +201 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RDA +)] = [] ( +DRAM +< +ALDRAM +>* +node +,  +id +) { + +202 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +203 +node +-> +row_¡©e +. + `þ—r +();}; + +204 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WRA +)] = [] ( +DRAM +< +ALDRAM +>* +node +,  +id +) { + +205 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +206 +node +-> +row_¡©e +. + `þ—r +();}; + +207 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PDE +)] = [] ( +DRAM +< +ALDRAM +>* +node +,  +id +) { + +208 autØ +bªk + : +node +-> +chžd»n +) { + +209 ià( +bªk +-> +¡©e + =ð +S‹ +:: +Clo£d +) + +211 +node +-> +¡©e + = +S‹ +:: +AùPow”Down +; + +214 +node +-> +¡©e + = +S‹ +:: +P»Pow”Down +;}; + +215 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PDX +)] = [] ( +DRAM +< +ALDRAM +>* +node +,  +id +) { + +216 +node +-> +¡©e + = +S‹ +:: +Pow”Up +;}; + +217 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +SRE +)] = [] ( +DRAM +< +ALDRAM +>* +node +,  +id +) { + +218 +node +-> +¡©e + = +S‹ +:: +S–fReäesh +;}; + +219 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +SRX +)] = [] ( +DRAM +< +ALDRAM +>* +node +,  +id +) { + +220 +node +-> +¡©e + = +S‹ +:: +Pow”Up +;}; + +221 + } +} + +224  + gALDRAM +:: + $š™_timšg +( +S³edEÁry + +¥“d_’Œy +) + +226 +S³edEÁry +& +s + = +¥“d_’Œy +; + +227 +veùÜ +< +TimšgEÁry +> * +t +; + +230 +t + = +timšg +[( +Lev– +:: +ChªÃl +)]; + +233 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nBL +}); + +234 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nBL +}); + +235 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nBL +}); + +236 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd::RDA, 1, +s +. +nBL +}); + +237 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd::WR, 1, +s +. +nBL +}); + +238 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nBL +}); + +239 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nBL +}); + +240 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd::WRA, 1, +s +. +nBL +}); + +244 +t + = +timšg +[( +Lev– +:: +Rªk +)]; + +247 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nCCD +}); + +248 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCCD +}); + +249 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCCD +}); + +250 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd::RDA, 1, +s +. +nCCD +}); + +251 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd::WR, 1, +s +. +nCCD +}); + +252 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCCD +}); + +253 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCCD +}); + +254 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd::WRA, 1, +s +. +nCCD +}); + +255 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nCCD + + 2 - s. +nCWL +}); + +256 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCL + + s. +nCCD + + 2 - s. +nCWL +}); + +257 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nCCD + + 2 - s. +nCWL +}); + +258 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCL + + s. +nCCD + + 2 - s. +nCWL +}); + +259 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTR +}); + +260 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTR +}); + +261 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTR +}); + +262 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTR +}); + +265 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +266 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +267 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +268 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd::RDA, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +269 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +270 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +271 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +272 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +273 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nBL + + s. +nRTRS + - s. +nCWL +, +Œue +}); + +274 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCL + + s. +nBL + + s. +nRTRS + - s. +nCWL +, +Œue +}); + +275 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nBL + + s. +nRTRS + - s. +nCWL +, +Œue +}); + +276 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCL + + s. +nBL + + s. +nRTRS + - s. +nCWL +, +Œue +}); + +277 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nRTRS + - s. +nCL +, +Œue +}); + +278 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nRTRS + - s. +nCL +, +Œue +}); + +279 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nRTRS + - s. +nCL +, +Œue +}); + +280 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nRTRS + - s. +nCL +, +Œue +}); + +282 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PREA +, 1, +s +. +nRTP +}); + +283 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PREA +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +}); + +286 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nCL + + s. +nBL + + 1}); + +287 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nCL + + s. +nBL + + 1}); + +288 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +}); + +289 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR + + 1}); + +290 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nXP +}); + +291 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nXP +}); + +292 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nXP +}); + +293 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nXP +}); + +298 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 1, +s +. +nRRD +}); + +299 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 4, +s +. +nFAW +}); + +300 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PREA +, 1, +s +. +nRAS +}); + +301 +t +[( +Commªd +:: +PREA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRP +}); + +304 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nRP +}); + +305 +t +[( +Commªd +:: +PREA +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nRP +}); + +306 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRFC +}); + +309 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PDE +, 1, 1}); + +310 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nXP +}); + +311 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nXP +}); + +312 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PREA +, 1, +s +. +nXP +}); + +315 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nRP +}); + +316 +t +[( +Commªd +:: +PREA +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nRP +}); + +317 +t +[( +Commªd +:: +SRX +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nXS +}); + +320 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd::REF, 1, +s +. +nRFC +}); + +323 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd:: +PDE +, 1, 1}); + +324 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nXP +}); + +327 +t +[( +Commªd +:: +SRX +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nXS +}); + +330 +t +[( +Commªd +:: +PDE +)]. + `push_back +({Commªd:: +PDX +, 1, +s +. +nPD +}); + +331 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nXP +}); + +334 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nXP +}); + +335 +t +[( +Commªd +:: +SRX +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nXS +}); + +338 +t +[( +Commªd +:: +SRE +)]. + `push_back +({Commªd:: +SRX +, 1, +s +. +nCKESR +}); + +339 +t +[( +Commªd +:: +SRX +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nXS +}); + +343 +t + = +timšg +[( +Lev– +:: +Bªk +)]; + +346 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nRCD +}); + +347 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nRCD +}); + +348 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nRCD +}); + +349 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nRCD +}); + +351 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nRTP +}); + +352 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +}); + +354 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRTP + + s. +nRP +}); + +355 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR + + s. +nRP +}); + +358 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 1, +s +. +nRC +}); + +359 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nRAS +}); + +360 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRP +}); + +361 + } +} + + @ALDRAM.h + +1 #iâdeà +__ALDRAM_H + + +2  + #__ALDRAM_H + + + ) + +4  + ~"DRAM.h +" + +5  + ~"Reque¡.h +" + +6  + ~ + +7  + ~ + +8  + ~<¡ršg +> + +9  + ~ + +11 +usšg + +Çme¥aû + + g¡d +; + +13 +Çme¥aû + + g¿muÏtÜ + + +16 þas  + cALDRAM + + +18 + gpublic +: + +19  +¡ršg + +¡ªd¬d_Çme +; + +20 +þass + + gOrg +; + +21 +þass + + gS³ed +; + +22 +þass + + gTemp +; + +24 +ALDRAM +( +Org + +Üg +, +S³ed + +¥“d +); + +25 +ALDRAM +(cÚ¡ +¡ršg +& +Üg_¡r +, cÚ¡ sŒšg& +¥“d_¡r +); + +27  + gm­ +< + g¡ršg +, + gOrg +> + gÜg_m­ +; + +28  + gm­ +< + g¡ršg +, + gS³ed +> + g¥“d_m­ +; + +30 þas  + cLev– + :  + +32 +ChªÃl +, + gRªk +, + gBªk +, + gRow +, + gCÞumn +, + gMAX + + +36 þas  + cCommªd + :  + +38 +ACT +, + gPRE +, + gPREA +, + +39 + gRD +, + gWR +, + gRDA +, + gWRA +, + +40 + gREF +, + gPDE +, + gPDX +, + gSRE +, + gSRX +, + +41 + gMAX + + +44 +¡ršg + + gcommªd_Çme +[( +Commªd +:: +MAX +)] = { + +50 +Lev– + + gscÝe +[( +Commªd +:: +MAX +)] = { + +51 +Lev– +:: +Row +, Lev–:: +Bªk +, Lev–:: +Rªk +, + +52 +Lev– +:: +CÞumn +, Level::Column, Level::Column, Level::Column, + +53 +Lev– +:: +Rªk +, Level::Rank, Level::Rank, Level::Rank, Level::Rank + +56 +boÞ + +is_Ý’šg +( +Commªd + +cmd +) + +58 ( + gcmd +)) { + +59 ( + gCommªd +:: +ACT +): + +60  +Œue +; + +62  +çl£ +; + +66 +boÞ + +is_acûssšg +( +Commªd + +cmd +) + +68 ( + gcmd +)) { + +69 ( + gCommªd +:: +RD +): + +70 ( +Commªd +:: +WR +): + +71 ( +Commªd +:: +RDA +): + +72 ( +Commªd +:: +WRA +): + +73  +Œue +; + +75  +çl£ +; + +79 +boÞ + +is_þosšg +( +Commªd + +cmd +) + +81 ( + gcmd +)) { + +82 ( + gCommªd +:: +RDA +): + +83 ( +Commªd +:: +WRA +): + +84 ( +Commªd +:: +PRE +): + +85 ( +Commªd +:: +PREA +): + +86  +Œue +; + +88  +çl£ +; + +92 +boÞ + +is_»äeshšg +( +Commªd + +cmd +) + +94 ( + gcmd +)) { + +95 ( + gCommªd +:: +REF +): + +96  +Œue +; + +98  +çl£ +; + +104 þas  + cS‹ + :  + +106 +O³Ãd +, + gClo£d +, + gPow”Up +, + gAùPow”Down +, + gP»Pow”Down +, + gS–fReäesh +, + gMAX + + +107 } + g¡¬t +[( +Lev– +:: +MAX +)] = { + +108 +S‹ +:: +MAX +, S‹:: +Pow”Up +, S‹:: +Clo£d +, State::Closed, State::MAX + +112 +Commªd + + gŒª¦©e +[( +Reque¡ +:: +Ty³ +:: +MAX +)] = { + +113 +Commªd +:: +RD +, Commªd:: +WR +, + +114 +Commªd +:: +REF +, Commªd:: +PDE +, Commªd:: +SRE + + +118 + gfunùiÚ +< +Commªd +( +DRAM +< +ALDRAM +>*, Commªd +cmd +, )> + g´”eq +[( +Lev– +:: +MAX +)][(Command::MAX)]; + +122 + gfunùiÚ +< +boÞ +( +DRAM +< +ALDRAM +>*, +Commªd + +cmd +, )> + growh™ +[( +Lev– +:: +MAX +)][(Command::MAX)]; + +123 + gfunùiÚ +< +boÞ +( +DRAM +< +ALDRAM +>*, +Commªd + +cmd +, )> + growÝ’ +[( +Lev– +:: +MAX +)][(Command::MAX)]; + +126  + sTimšgEÁry + + +128 +Commªd + + gcmd +; + +129  + gdi¡ +; + +130  + gv® +; + +131 +boÞ + + gsiblšg +; + +133 + gveùÜ +< + gTimšgEÁry +> + gtimšg +[( +Lev– +:: +MAX +)][( +Commªd +::MAX)]; + +136 + gfunùiÚ +<( + gDRAM +< + gALDRAM +>*, )> + gÏmbda +[( +Lev– +:: +MAX +)][( +Commªd +::MAX)]; + +139 þas  + cOrg + :  + +141 +ALDRAM_512Mb_x4 +, + gALDRAM_512Mb_x8 +, + gALDRAM_512Mb_x16 +, + +142 + gALDRAM_1Gb_x4 +, + gALDRAM_1Gb_x8 +, + gALDRAM_1Gb_x16 +, + +143 + gALDRAM_2Gb_x4 +, + gALDRAM_2Gb_x8 +, + gALDRAM_2Gb_x16 +, + +144 + gALDRAM_4Gb_x4 +, + gALDRAM_4Gb_x8 +, + gALDRAM_4Gb_x16 +, + +145 + gALDRAM_8Gb_x4 +, + gALDRAM_8Gb_x8 +, + gALDRAM_8Gb_x16 +, + +146 + gMAX + + +149  + sOrgEÁry + { + +150  + gsize +; + +151  + gdq +; + +152  + gcouÁ +[( +Lev– +:: +MAX +)]; + +153 } + gÜg_bË +[( +Org +:: +MAX +)] = { + +159 }, + gÜg_’Œy +; + +161  +£t_chªÃl_numb” +( +chªÃl +); + +162  +£t_¿nk_numb” +( +¿nk +); + +165 þas  + cS³ed + :  + +167 +ALDRAM_800D +, + gALDRAM_800E +, + +168 + gALDRAM_1066E +, + gALDRAM_1066F +, + gALDRAM_1066G +, + +169 + gALDRAM_1333G +, + gALDRAM_1333H +, + +170 + gALDRAM_1600H +, + gALDRAM_1600J +, + gALDRAM_1600K +, + +171 + gALDRAM_1866K +, + gALDRAM_1866L +, + +172 + gALDRAM_2133L +, + gALDRAM_2133M +, + +173 + gMAX + + +176 +S³ed + + gcu¼’t_¥“d +; + +178 þas  + cTemp + :  + +180 +COLD +, + gHOT +, + gMAX + + +183 +Temp + + g‹m³¿tu» + = Temp:: +HOT +; + +185  + g´eãtch_size + = 8; + +186  + gchªÃl_width + = 64; + +188  + sS³edEÁry + { + +189  + g¿‹ +; + +190  + gäeq +, + gtCK +; + +191  + gnBL +, + gnCCD +, + gnRTRS +; + +192  + gnCL +, + gnRCD +, + gnRP +, + gnCWL +; + +193  + gnRAS +, + gnRC +; + +194  + gnRTP +, + gnWTR +, + gnWR +; + +195  + gnRRD +, + gnFAW +; + +196  + gnRFC +, + gnREFI +; + +197  + gnPD +, + gnXP +, + gnXPDLL +; + +198  + gnCKESR +, + gnXS +, + gnXSDLL +; + +199 } + g¥“d_bË +[( +Temp +:: +MAX +)][( +S³ed +::MAX)] = { + +232 }, + g¥“d_’Œy +; + +234  + g»ad_Ï‹ncy +; + +235  +®d¿m_timšg +( +Temp + +cu¼’t_‹m³¿tu» +); + +236 + g´iv©e +: + +237  +š™_¥“d +(); + +238  +š™_Ïmbda +(); + +239  +š™_´”eq +(); + +240  +š™_rowh™ +(); + +241  +š™_rowÝ’ +(); + +242  +š™_timšg +( +S³edEÁry + +¥“d_’Œy +); + + @Cache.cpp + +1  + ~"Cache.h +" + +3 #iâdeà +DEBUG_CACHE + + +4  + #debug +(...) + + ) + +6  + #debug +(...) do { \ + +7 + `´štf +("\033[36m[DEBUG] % ", +__FUNCTION__ +); \ + +8 + `´štf +( +__VA_ARGS__ +); \ + +9 + `´štf +("\033[0m\n"); \ + +10 } 0) + + ) + +13 +Çme¥aû + + g¿muÏtÜ + + +16 + gCache +:: +Cache +( +size +,  +assoc +,  +block_size +, + +17  +mshr_’Œy_num +, +Lev– + +Ëv– +, + +18 +¡d +:: +sh¬ed_±r +< +CacheSy¡em +> +ÿchesys +): + +19 +Ëv– +Öev–), +ÿchesys +(ÿchesys), +high”_ÿche +(0), + +20 +low”_ÿche +( +nuαr +), +size +(size), +assoc +(assoc), + +21 +block_size +(block_size), +mshr_’Œy_num +(mshr_entry_num) { + +23 +debug +("level %d size %d‡ssoc %d block_size %d\n", + +24 ( +Ëv– +), +size +, +assoc +, +block_size +); + +26 ià( + gËv– + =ð +Lev– +:: +L1 +) { + +27 +Ëv–_¡ršg + = "L1"; + +28 } ià( + gËv– + =ð +Lev– +:: +L2 +) { + +29 +Ëv–_¡ršg + = "L2"; + +30 } ià( + gËv– + =ð +Lev– +:: +L3 +) { + +31 +Ëv–_¡ršg + = "L3"; + +34 + gis_fœ¡_Ëv– + = ( +Ëv– + =ð +ÿchesys +-> +fœ¡_Ëv– +); + +35 + gis_Ï¡_Ëv– + = ( +Ëv– + =ð +ÿchesys +-> +Ï¡_Ëv– +); + +38 +as£¹ +(( +size + & (size - 1)) == 0); + +39 +as£¹ +(( +block_size + & (block_size - 1)) == 0); + +40 +as£¹ +(( +assoc + & (assoc - 1)) == 0); + +41 +as£¹ +( +size + >ð +block_size +); + +44 + gblock_num + = +size + / ( +block_size + * +assoc +); + +45 + gšdex_mask + = +block_num + - 1; + +46 + gšdex_off£t + = +ÿlc_log2 +( +block_size +); + +47 + gg_off£t + = +ÿlc_log2 +( +block_num +è+ +šdex_off£t +; + +49 +debug +("šdex_off£ˆ%d", +šdex_off£t +); + +50 +debug +("šdex_mask 0x%x", +šdex_mask +); + +51 +debug +("g_off£ˆ%d", +g_off£t +); + +54 + gÿche_»ad_miss +. +Çme +( +Ëv–_¡ršg + + +¡ršg +("_cache_read_miss")) + +55 . +desc +("cache„ead miss count") + +56 . +´ecisiÚ +(0) + +59 + gÿche_wr™e_miss +. +Çme +( +Ëv–_¡ršg + + +¡ršg +("_cache_write_miss")) + +60 . +desc +("cache write miss count") + +61 . +´ecisiÚ +(0) + +64 + gÿche_tÙ®_miss +. +Çme +( +Ëv–_¡ršg + + +¡ršg +("_cache_total_miss")) + +65 . +desc +("cacheotal miss count") + +66 . +´ecisiÚ +(0) + +69 + gÿche_eviùiÚ +. +Çme +( +Ëv–_¡ršg + + +¡ršg +("_cache_eviction")) + +70 . +desc +("number ofƒvict fromhis†evelo†ower†evel") + +71 . +´ecisiÚ +(0) + +74 + gÿche_»ad_acûss +. +Çme +( +Ëv–_¡ršg + + +¡ršg +("_cache_read_access")) + +75 . +desc +("cache„ead‡ccess count") + +76 . +´ecisiÚ +(0) + +79 + gÿche_wr™e_acûss +. +Çme +( +Ëv–_¡ršg + + +¡ršg +("_cache_write_access")) + +80 . +desc +("cache write‡ccess count") + +81 . +´ecisiÚ +(0) + +84 + gÿche_tÙ®_acûss +. +Çme +( +Ëv–_¡ršg + + +¡ršg +("_cache_total_access")) + +85 . +desc +("cacheotal‡ccess count") + +86 . +´ecisiÚ +(0) + +89 + gÿche_mshr_h™ +. +Çme +( +Ëv–_¡ršg + + +¡ršg +("_cache_mshr_hit")) + +90 . +desc +("cache mshr hit count") + +91 . +´ecisiÚ +(0) + +93 + gÿche_mshr_uÇvažabË +. +Çme +( +Ëv–_¡ršg + + +¡ršg +("_cache_mshr_unavailable")) + +94 . +desc +("cache mshr‚ot‡vailable count") + +95 . +´ecisiÚ +(0) + +97 + gÿche_£t_uÇvažabË +. +Çme +( +Ëv–_¡ršg + + +¡ršg +("_cache_set_unavailable")) + +98 . +desc +("cache set‚ot‡vailable") + +99 . +´ecisiÚ +(0) + +103 +boÞ + + gCache +:: +£nd +( +Reque¡ + +»q +) { + +104 +debug +("level %d„eq.addr %lx„eq.type %d, index %d,ag %ld", + +105 ( +Ëv– +), +»q +. +addr +, Ôeq. +ty³ +), +g‘_šdex +(req.addr), + +106 +g‘_g +( +»q +. +addr +)); + +108 + gÿche_tÙ®_acûss +++; + +109 ià( + g»q +. + gty³ + =ð +Reque¡ +:: +Ty³ +:: +WRITE +) { + +110 +ÿche_wr™e_acûss +++; + +112 +as£¹ +( +»q +. +ty³ + =ð +Reque¡ +:: +Ty³ +:: +READ +); + +113 + gÿche_»ad_acûss +++; + +116 auto& + glšes + = +g‘_lšes +( +»q +. +addr +); + +117 + g¡d +:: +li¡ +< +Lše +>:: +™”©Ü + +lše +; + +119 ià( +is_h™ +( +lšes +, +»q +. +addr +, & +lše +)) { + +120 + glšes +. +push_back +( +Lše +( +»q +. +addr +, +g‘_g +Ôeq.addr), +çl£ +, + +121 +lše +-> +dœty + || ( +»q +. +ty³ + =ð +Reque¡ +:: +Ty³ +:: +WRITE +))); + +122 + glšes +. +”a£ +( +lše +); + +123 + gÿchesys +-> + gh™_li¡ +. +push_back +( + +124 +make_·œ +( +ÿchesys +-> +þk + + +Ï‹ncy +[( +Ëv– +)], +»q +)); + +126 +debug +("h™, upd©time¡am°%ld", +ÿchesys +-> +þk +); + +127 +debug +("hit finishime %ld", + +128 +ÿchesys +-> +þk + + +Ï‹ncy +[( +Ëv– +)]); + +130  + gŒue +; + +133 +debug +("mis @Ëv– %d", ( +Ëv– +)); + +134 + gÿche_tÙ®_miss +++; + +135 ià( + g»q +. + gty³ + =ð +Reque¡ +:: +Ty³ +:: +WRITE +) { + +136 +ÿche_wr™e_miss +++; + +138 +as£¹ +( +»q +. +ty³ + =ð +Reque¡ +:: +Ty³ +:: +READ +); + +139 + gÿche_»ad_miss +++; + +143 +boÞ + + gdœty + = ( +»q +. +ty³ + =ð +Reque¡ +:: +Ty³ +:: +WRITE +); + +146 ià( + g»q +. + gty³ + =ð +Reque¡ +:: +Ty³ +:: +WRITE +) { + +147 +»q +. +ty³ + = +Reque¡ +:: +Ty³ +:: +READ +; + +151 +as£¹ +( +»q +. +ty³ + =ð +Reque¡ +:: +Ty³ +:: +READ +); + +152 autØ + gmshr + = +h™_mshr +( +»q +. +addr +); + +153 ià( + gmshr + !ð +mshr_’Œ›s +. +’d +()) { + +154 +debug +("hit mshr"); + +155 + gÿche_mshr_h™ +++; + +156 + gmshr +-> + g£cÚd +-> + gdœty + = +dœty + || +mshr +-> +£cÚd +->dirty; + +157  + gŒue +; + +162 ià( + gmshr_’Œ›s +. +size +(è=ð +mshr_’Œy_num +) { + +165 +ÿche_mshr_uÇvažabË +++; + +166 +debug +("no mshrƒntry‡vailable"); + +167  + gçl£ +; + +171 ià( +®l_£ts_locked +( +lšes +)) { + +172 + gÿche_£t_uÇvažabË +++; + +173  + gçl£ +; + +176 autØ + gÃwlše + = +®loÿ‹_lše +( +lšes +, +»q +. +addr +); + +177 ià( + gÃwlše + =ð +lšes +. +’d +()) { + +178  +çl£ +; + +181 + gÃwlše +-> + gdœty + = +dœty +; + +184 + gmshr_’Œ›s +. +push_back +( +make_·œ +( +»q +. +addr +, +Ãwlše +)); + +187 ià(! + gis_Ï¡_Ëv– +) { + +188 + glow”_ÿche +-> +£nd +( +»q +); + +190 + gÿchesys +-> + gwa™_li¡ +. +push_back +( + +191 +make_·œ +( +ÿchesys +-> +þk + + +Ï‹ncy +[( +Ëv– +)], +»q +)); + +193  + gŒue +; + +197  + gCache +:: +eviùlše +( +addr +, +boÞ + +dœty +) { + +199 autØ + g™ + = +ÿche_lšes +. +fšd +( +g‘_šdex +( +addr +)); + +200 +as£¹ +( +™ + !ð +ÿche_lšes +. +’d +()); + +201 auto& + glšes + = +™ +-> +£cÚd +; + +202 autØ + glše + = +fšd_if +( +lšes +. +begš +(),†šes. +’d +(), + +203 [ +addr +, +this +]( +Lše + +l +){ (l. +g + =ð +g‘_g +(addr));}); + +205 +as£¹ +( +lše + !ð +lšes +. +’d +()); + +208 + glšes +. +push_back +( +Lše +( +addr +, +g‘_g +×ddr), +çl£ +, + +209 +dœty + || +lše +->dirty)); + +210 + glšes +. +”a£ +( +lše +); + +213 + g¡d +:: +·œ +<, + gboÞ +> + gCache +:: +šv®id©e +( +addr +) { + +214  +d–ay + = +Ï‹ncy_—ch +[( +Ëv– +)]; + +215 +boÞ + + gdœty + = +çl£ +; + +217 auto& + glšes + = +g‘_lšes +( +addr +); + +218 ià( + glšes +. +size +() == 0) { + +220  +make_·œ +(0, +çl£ +); + +222 autØ + glše + = +fšd_if +( +lšes +. +begš +(),†šes. +’d +(), + +223 [ +addr +, +this +]( +Lše + +l +){ (l. +g + =ð +g‘_g +(addr));}); + +227 ià( + glše + !ð +lšes +. +’d +()) { + +228 +as£¹ +(! +lše +-> +lock +); + +229 +debug +("šv®id©%lx @†ev– %d", +addr +, ( +Ëv– +)); + +230 + glšes +. +”a£ +( +lše +); + +233  +make_·œ +( +d–ay +, +çl£ +); + +236 ià( + ghigh”_ÿche +. +size +()) { + +237  + gmax_d–ay + = +d–ay +; + +238 autØ + ghc + : +high”_ÿche +) { + +239 autØ +»suÉ + = +hc +-> +šv®id©e +( +addr +); + +240 ià( + g»suÉ +. + g£cÚd +) { + +241 + gmax_d–ay + = +max +( +max_d–ay +, +d–ay + + +»suÉ +. +fœ¡ + * 2); + +243 + gmax_d–ay + = +max +( +max_d–ay +, +d–ay + + +»suÉ +. +fœ¡ +); + +245 + gdœty + = +dœty + || +lše +->dœty || +»suÉ +. +£cÚd +; + +247 + gd–ay + = +max_d–ay +; + +249 + gdœty + = +lše +-> +dœty +; + +251  +make_·œ +( +d–ay +, +dœty +); + +255  + gCache +:: +eviù +( +¡d +:: +li¡ +< +Lše +>* +lšes +, + +256 +¡d +:: +li¡ +< +Lše +>:: +™”©Ü + +viùim +) { + +257 +debug +("Ëv– %d mis eviù viùim %lx", ( +Ëv– +), +viùim +-> +addr +); + +258 + gÿche_eviùiÚ +++; + +260  + gaddr + = +viùim +-> +addr +; + +261  + gšv®id©e_time + = 0; + +262 +boÞ + + gdœty + = +viùim +-> +dœty +; + +265 ià( + ghigh”_ÿche +. +size +()) { + +266 autØ + ghc + : +high”_ÿche +) { + +267 autØ +»suÉ + = +hc +-> +šv®id©e +( +addr +); + +268 + gšv®id©e_time + = +max +( +šv®id©e_time +, + +269 +»suÉ +. +fœ¡ + + (»suÉ. +£cÚd + ? +Ï‹ncy_—ch +[( +Ëv– +)] : 0)); + +270 + gdœty + = +dœty + || +»suÉ +. +£cÚd + || +viùim +->dirty; + +274 +debug +("šv®id©d–ay: %ld, dœty: %s", +šv®id©e_time +, + +275 +dœty + ? "true" : "false"); + +277 ià(! + gis_Ï¡_Ëv– +) { + +279 +as£¹ +( +low”_ÿche + !ð +nuαr +); + +280 + glow”_ÿche +-> +eviùlše +( +addr +, +dœty +); + +283 ià( + gdœty +) { + +284 +Reque¡ + +wr™e_»q +( +addr +, Reque¡:: +Ty³ +:: +WRITE +); + +285 + gÿchesys +-> + gwa™_li¡ +. +push_back +( +make_·œ +( + +286 +ÿchesys +-> +þk + + +šv®id©e_time + + +Ï‹ncy +[( +Ëv– +)], + +287 +wr™e_»q +)); + +289 +debug +("inject one write„equesto memory system " + +291 +wr™e_»q +. +addr +, +šv®id©e_time +, + +292 +ÿchesys +-> +þk + + +šv®id©e_time + + +Ï‹ncy +[( +Ëv– +)]); + +296 + glšes +-> +”a£ +( +viùim +); + +299 + g¡d +:: +li¡ +< +Cache +:: +Lše +>:: +™”©Ü + Cache:: +®loÿ‹_lše +( + +300 +¡d +:: +li¡ +< +Lše +>& +lšes +,  +addr +) { + +302 ià( +Ãed_eviùiÚ +( +lšes +, +addr +)) { + +305 autØ + gviùim + = +fšd_if +( +lšes +. +begš +(),†šes. +’d +(), + +306 [ +this +]( +Lše + +lše +) { + +307 +boÞ + +check + = ! +lše +. +lock +; + +308 ià(! +is_fœ¡_Ëv– +) { + +309 autØ +hc + : +high”_ÿche +) { + +310 if(! +check +) { + +311  +check +; + +313 +check + = check && +hc +-> +check_uÆock +( +lše +. +addr +); + +316  +check +; + +318 ià( + gviùim + =ð +lšes +. +’d +()) { + +319  +viùim +; + +321 +as£¹ +( +viùim + !ð +lšes +. +’d +()); + +322 +eviù +(& +lšes +, +viùim +); + +326 + glšes +. +push_back +( +Lše +( +addr +, +g‘_g +(addr))); + +327 autØ + gÏ¡_–em’t + = +lšes +. +’d +(); + +328 -- + gÏ¡_–em’t +; + +329  + gÏ¡_–em’t +; + +332 +boÞ + + gCache +:: +is_h™ +( +¡d +:: +li¡ +< +Lše +>& +lšes +,  +addr +, + +333 +¡d +:: +li¡ +< +Lše +>:: +™”©Ü +* +pos_±r +) { + +334 autØ +pos + = +fšd_if +( +lšes +. +begš +(),†šes. +’d +(), + +335 [ +addr +, +this +]( +Lše + +l +){ (l. +g + =ð +g‘_g +(addr));}); + +336 * + gpos_±r + = +pos +; + +337 ià( + gpos + =ð +lšes +. +’d +()) { + +338  +çl£ +; + +340  ! + gpos +-> + glock +; + +343  + gCache +:: +cÚÿŽow” +( +Cache +* +low” +) { + +344 +low”_ÿche + = +low” +; + +345 +as£¹ +( +low” + !ð +nuαr +); + +346 + glow” +-> + ghigh”_ÿche +. +push_back +( +this +); + +349 +boÞ + + gCache +:: +Ãed_eviùiÚ +(cÚ¡ +¡d +:: +li¡ +< +Lše +>& +lšes +,  +addr +) { + +350 ià( +fšd_if +( +lšes +. +begš +(),†šes. +’d +(), + +351 [ +addr +, +this +]( +Lše + +l +){ + +352  ( +g‘_g +( +addr +è=ð +l +. +g +);}) + +353 !ð +lšes +. +’d +()) { + +355 +as£¹ +( +çl£ +); + +357 ià( + glšes +. +size +(è< + gassoc +) { + +358  + gçl£ +; + +360  + gŒue +; + +365  + gCache +:: +ÿÎback +( +Reque¡ +& +»q +) { + +366 +debug +("Ëv– %d", ( +Ëv– +)); + +368 autØ + g™ + = +fšd_if +( +mshr_’Œ›s +. +begš +(), mshr_’Œ›s. +’d +(), + +369 [& +»q +, +this +]( +¡d +:: +·œ +<, std:: +li¡ +< +Lše +>:: +™”©Ü +> +mshr_’Œy +) { + +370  ( +®ign +( +mshr_’Œy +. +fœ¡ +è=ð®ign( +»q +. +addr +)); + +373 ià( + g™ + !ð +mshr_’Œ›s +. +’d +()) { + +374 +™ +-> +£cÚd +-> +lock + = +çl£ +; + +375 + gmshr_’Œ›s +. +”a£ +( +™ +); + +378 ià( + ghigh”_ÿche +. +size +()) { + +379 autØ + ghc + : +high”_ÿche +) { + +380 +hc +-> +ÿÎback +( +»q +); + +385  + gCacheSy¡em +:: +tick +() { + +386 +debug +("þk %ld", +þk +); + +388 ++ + gþk +; + +391 autØ + g™ + = +wa™_li¡ +. +begš +(); + +392  + g™ + !ð +wa™_li¡ +. +’d +(è&& +þk + >ð +™ +-> +fœ¡ +) { + +393 ià(! +£nd_memÜy +( +™ +-> +£cÚd +)) { + +394 ++ +™ +; + +397 +debug +("com¶‘»q:‡dd¸%lx", ( +™ +-> +£cÚd +). +addr +); + +399 + g™ + = +wa™_li¡ +. +”a£ +( +™ +); + +404 + g™ + = +h™_li¡ +. +begš +(); + +405  + g™ + !ð +h™_li¡ +. +’d +()) { + +406 ià( +þk + >ð +™ +-> +fœ¡ +) { + +407 +™ +-> +£cÚd +. +ÿÎback +(it->second); + +409 +debug +("fšish h™:‡dd¸%lx", ( +™ +-> +£cÚd +). +addr +); + +411 + g™ + = +h™_li¡ +. +”a£ +( +™ +); + +413 ++ + g™ +; + + @Cache.h + +1 #iâdeà +__CACHE_H + + +2  + #__CACHE_H + + + ) + +4  + ~"CÚfig.h +" + +5  + ~"Reque¡.h +" + +6  + ~"Sti¡ics.h +" + +7  + ~<®gÜ™hm +> + +8  + ~ + +9  + ~<ÿs£¹ +> + +10  + ~ + +11  + ~ + +12  + ~ + +13  + ~ + +14  + ~ + +15  + ~ + +17 +Çme¥aû + + g¿muÏtÜ + + +19 +þass + + gCacheSy¡em +; + +21 þas  + cCache + { + +22 + g´Ùeùed +: + +23 +SÿÏrSt + +ÿche_»ad_miss +; + +24 +SÿÏrSt + + gÿche_wr™e_miss +; + +25 +SÿÏrSt + + gÿche_tÙ®_miss +; + +26 +SÿÏrSt + + gÿche_eviùiÚ +; + +27 +SÿÏrSt + + gÿche_»ad_acûss +; + +28 +SÿÏrSt + + gÿche_wr™e_acûss +; + +29 +SÿÏrSt + + gÿche_tÙ®_acûss +; + +30 +SÿÏrSt + + gÿche_mshr_h™ +; + +31 +SÿÏrSt + + gÿche_mshr_uÇvažabË +; + +32 +SÿÏrSt + + gÿche_£t_uÇvažabË +; + +33 + gpublic +: + +34 þas  + cLev– + { + +35 +L1 +, + +36 + gL2 +, + +37 + gL3 +, + +38 + gMAX + + +39 } + gËv– +; + +40 + g¡d +:: +¡ršg + +Ëv–_¡ršg +; + +42  + sLše + { + +43  + gaddr +; + +44  + gg +; + +45 +boÞ + + glock +; + +46 +boÞ + + gdœty +; + +47 +Lše +( +addr +,  +g +): + +48 +addr +×ddr), +g +Ñag), +lock +( +Œue +), +dœty +( +çl£ +) {} + +49 +Lše +( +addr +,  +g +, +boÞ + +lock +, boÞ +dœty +): + +50 +addr +×ddr), +g +Ñag), +lock +Öock), +dœty +(dirty) {} + +53 +Cache +( +size +,  +assoc +,  +block_size +,  +mshr_’Œy_num +, + +54 +Lev– + +Ëv– +, +¡d +:: +sh¬ed_±r +< +CacheSy¡em +> +ÿchesys +); + +57  + gÏ‹ncy +[( +Lev– +:: +MAX +)] = {4, 4 + 12, 4 + 12 + 31}; + +58  + gÏ‹ncy_—ch +[( +Lev– +:: +MAX +)] = {4, 12, 31}; + +60 + g¡d +:: +sh¬ed_±r +< +CacheSy¡em +> +ÿchesys +; + +62 + g¡d +:: +veùÜ +< +Cache +*> +high”_ÿche +; + +63 +Cache +* + glow”_ÿche +; + +65 +boÞ + +£nd +( +Reque¡ + +»q +); + +67  +cÚÿŽow” +( +Cache +* +low” +); + +69  +ÿÎback +( +Reque¡ +& +»q +); + +71 + g´Ùeùed +: + +73 +boÞ + +is_fœ¡_Ëv– +; + +74 +boÞ + + gis_Ï¡_Ëv– +; + +75 +size_t + + gsize +; + +76  + gassoc +; + +77  + gblock_num +; + +78  + gšdex_mask +; + +79  + gblock_size +; + +80  + gšdex_off£t +; + +81  + gg_off£t +; + +82  + gmshr_’Œy_num +; + +83 + g¡d +:: +veùÜ +< +¡d +:: +·œ +<, std:: +li¡ +< +Lše +>:: +™”©Ü +>> +mshr_’Œ›s +; + +85 + g¡d +:: +m­ +<, std:: +li¡ +< +Lše +> > +ÿche_lšes +; + +87  +ÿlc_log2 +( +v® +) { + +88  + gn + = 0; + +89 ( + gv® + >>= 1)) + +90 +n + ++; + +91  + gn +; + +94  +g‘_šdex +( +addr +) { + +95  ( + gaddr + >> + gšdex_off£t +è& + gšdex_mask +; + +98  +g‘_g +( +addr +) { + +99  ( + gaddr + >> + gg_off£t +); + +103  +®ign +( +addr +) { + +104  ( + gaddr + & ~( + gblock_size +-1l)); + +109  +eviùlše +( +addr +, +boÞ + +dœty +); + +115 + g¡d +:: +·œ +<, + gboÞ +> +šv®id©e +( +addr +); + +120  +eviù +( +¡d +:: +li¡ +< +Lše +>* +lšes +, + +121 +¡d +:: +li¡ +< +Lše +>:: +™”©Ü + +viùim +); + +126 + g¡d +:: +li¡ +< +Lše +>:: +™”©Ü + +®loÿ‹_lše +( + +127 +¡d +:: +li¡ +< +Lše +>& +lšes +,  +addr +); + +131 +boÞ + +Ãed_eviùiÚ +(cÚ¡ +¡d +:: +li¡ +< +Lše +>& +lšes +,  +addr +); + +135 +boÞ + +is_h™ +( +¡d +:: +li¡ +< +Lše +>& +lšes +,  +addr +, + +136 +¡d +:: +li¡ +< +Lše +>:: +™”©Ü +* +pos_±r +); + +138 +boÞ + +®l_£ts_locked +(cÚ¡ +¡d +:: +li¡ +< +Lše +>& +lšes +) { + +139 ià( +lšes +. +size +(è< +assoc +) { + +140  +çl£ +; + +142 cÚ¡‡uto& + glše + : +lšes +) { + +143 ià(! +lše +. +lock +) { + +144  +çl£ +; + +147  + gŒue +; + +150 +boÞ + +check_uÆock +( +addr +) { + +151 autØ + g™ + = +ÿche_lšes +. +fšd +( +g‘_šdex +( +addr +)); + +152 ià( + g™ + =ð +ÿche_lšes +. +’d +()) { + +153  +Œue +; + +155 auto& + glšes + = +™ +-> +£cÚd +; + +156 autØ + glše + = +fšd_if +( +lšes +. +begš +(),†šes. +’d +(), + +157 [ +addr +, +this +]( +Lše + +l +){ (l. +g + =ð +g‘_g +(addr));}); + +158 ià( + glše + =ð +lšes +. +’d +()) { + +159  +Œue +; + +161 +boÞ + + gcheck + = ! +lše +-> +lock +; + +162 ià(! + gis_fœ¡_Ëv– +) { + +163 autØ + ghc + : +high”_ÿche +) { + +164 ià(! +check +) { + +165  +check +; + +167 + gcheck + = +check + && +hc +-> +check_uÆock +( +lše +-> +addr +); + +170  + gcheck +; + +175 + g¡d +:: +veùÜ +< +¡d +:: +·œ +<, std:: +li¡ +< +Lše +>:: +™”©Ü +>>::iterator + +176 +h™_mshr +( +addr +) { + +177 autØ +mshr_™ + = + +178 +fšd_if +( +mshr_’Œ›s +. +begš +(), mshr_’Œ›s. +’d +(), + +179 [ +addr +, +this +]( +¡d +:: +·œ +<, std:: +li¡ +< +Lše +>:: +™”©Ü +> + +180 +mshr_’Œy +) { + +181  ( +®ign +( +mshr_’Œy +. +fœ¡ +è=ð®ign( +addr +)); + +183  + gmshr_™ +; + +186 + g¡d +:: +li¡ +< +Lše +>& +g‘_lšes +( +addr +) { + +187 ià( +ÿche_lšes +. +fšd +( +g‘_šdex +( +addr +)) + +188 =ð +ÿche_lšes +. +’d +()) { + +189 +ÿche_lšes +. +š£¹ +( +make_·œ +( +g‘_šdex +( +addr +), + +190 +¡d +:: +li¡ +< +Lše +>())); + +192  + gÿche_lšes +[ +g‘_šdex +( +addr +)]; + +197 þas  + cCacheSy¡em + { + +198 + gpublic +: + +199 +CacheSy¡em +(cÚ¡ +CÚfig +& +cÚfigs +, +¡d +:: +funùiÚ +< +boÞ +( +Reque¡ +)> +£nd_memÜy +): + +200 +£nd_memÜy +(send_memory) { + +201 ià( +cÚfigs +. +has_cÜe_ÿches +()) { + +202 +fœ¡_Ëv– + = +Cache +:: +Lev– +:: +L1 +; + +203 } ià( + gcÚfigs +. +has_l3_ÿche +()) { + +204 + gfœ¡_Ëv– + = +Cache +:: +Lev– +:: +L3 +; + +206 + gÏ¡_Ëv– + = +Cache +:: +Lev– +:: +MAX +; + +209 ià( + gcÚfigs +. +has_l3_ÿche +()) { + +210 + gÏ¡_Ëv– + = +Cache +:: +Lev– +:: +L3 +; + +211 } ià( + gcÚfigs +. +has_cÜe_ÿches +()) { + +212 + gÏ¡_Ëv– + = +Cache +:: +Lev– +:: +L2 +; + +214 + gÏ¡_Ëv– + = +Cache +:: +Lev– +:: +MAX +; + +221 + g¡d +:: +li¡ +< +¡d +:: +·œ +<, + gReque¡ +> > + gwa™_li¡ +; + +226 + g¡d +:: +li¡ +< +¡d +:: +·œ +<, + gReque¡ +> > + gh™_li¡ +; + +228 + g¡d +:: +funùiÚ +< +boÞ +( +Reque¡ +)> +£nd_memÜy +; + +230  + gþk + = 0; + +231  +tick +(); + +233 + gCache +:: +Lev– + +fœ¡_Ëv– +; + +234 + gCache +:: +Lev– + +Ï¡_Ëv– +; + + @Config.cpp + +1  + ~"CÚfig.h +" + +3 +usšg + +Çme¥aû + + g¡d +; + +4 +usšg + +Çme¥aû + + g¿muÏtÜ +; + +6 + gCÚfig +:: + $CÚfig +(cÚ¡ +¡d +:: +¡ršg +& +âame +) { + +7 + `·r£ +( +âame +); + +8 + } +} + +10  + gCÚfig +:: + $·r£ +(cÚ¡ +¡ršg +& +âame +) + +12 +if¡»am + + `fže +( +âame +); + +13 + `as£¹ +( +fže +. + `good +() && "Bad config file"); + +14 +¡ršg + +lše +; + +15  + `g‘lše +( +fže +, +lše +)) { + +16  +d–im +[] = " \t="; + +17 +veùÜ +< +¡ršg +> +tok’s +; + +19  +Œue +) { + +20 +size_t + +¡¬t + = +lše +. + `fšd_fœ¡_nÙ_of +( +d–im +); + +21 ià( +¡¬t + =ð +¡ršg +:: +Åos +) + +24 +size_t + +’d + = +lše +. + `fšd_fœ¡_of +( +d–im +, +¡¬t +); + +25 ià( +’d + =ð +¡ršg +:: +Åos +) { + +26 +tok’s +. + `push_back +( +lše +. + `sub¡r +( +¡¬t +)); + +30 +tok’s +. + `push_back +( +lše +. + `sub¡r +( +¡¬t +, +’d + - start)); + +31 +lše + =†še. + `sub¡r +( +’d +); + +35 ià(! +tok’s +. + `size +()) + +39 ià( +tok’s +[0][0] == '#') + +43 + `as£¹ +( +tok’s +. + `size +() == 2 && "Only‡llowwookens in one†ine"); + +45 +ÝtiÚs +[ +tok’s +[0]] =okens[1]; + +47 ià( +tok’s +[0] == "channels") { + +48 +chªÃls + = + `©oi +( +tok’s +[1]. + `c_¡r +()); + +49 } ià( +tok’s +[0] == "ranks") { + +50 +¿nks + = + `©oi +( +tok’s +[1]. + `c_¡r +()); + +51 } ià( +tok’s +[0] == "subarrays") { + +52 +sub¬¿ys + = + `©oi +( +tok’s +[1]. + `c_¡r +()); + +53 } ià( +tok’s +[0] == "cpu_tick") { + +54 +ýu_tick + = + `©oi +( +tok’s +[1]. + `c_¡r +()); + +55 } ià( +tok’s +[0] == "mem_tick") { + +56 +mem_tick + = + `©oi +( +tok’s +[1]. + `c_¡r +()); + +57 } ià( +tok’s +[0] == "expected_limit_insts") { + +58 +ex³ùed_lim™_š¡s + = + `©oi +( +tok’s +[1]. + `c_¡r +()); + +61 +fže +. + `þo£ +(); + +62 + } +} + + @Config.h + +1 #iâdeà +__CONFIG_H + + +2  + #__CONFIG_H + + + ) + +4  + ~<¡ršg +> + +5  + ~ + +6  + ~ + +7  + ~ + +8  + ~ + +9  + ~<ÿs£¹ +> + +11 +Çme¥aû + + g¿muÏtÜ + + +14 þas  + cCÚfig + { + +16 + g´iv©e +: + +17 +¡d +:: +m­ +<¡d:: +¡ršg +, + g¡d +::¡ršg> +ÝtiÚs +; + +18  + gchªÃls +; + +19  + g¿nks +; + +20  + gsub¬¿ys +; + +21  + gýu_tick +; + +22  + gmem_tick +; + +23  + gcÜe_num + = 0; + +24  + gex³ùed_lim™_š¡s + = 0; + +26 + gpublic +: + +27 +CÚfig +() {} + +28 +CÚfig +(cÚ¡ +¡d +:: +¡ršg +& +âame +); + +29  +·r£ +(cÚ¡ +¡d +:: +¡ršg +& +âame +); + +30 + g¡d +:: +¡ršg + +Ý”©Ü + [] (cÚ¡ +¡d +::¡ršg& +Çme +) const { + +31 ià( +ÝtiÚs +. +fšd +( +Çme +è!ðÝtiÚs. +’d +()) { + +32  ( +ÝtiÚs +. +fšd +( +Çme +))-> +£cÚd +; + +38 +boÞ + +cÚšs +(cÚ¡ +¡d +:: +¡ršg +& +Çme +) const { + +39 ià( +ÝtiÚs +. +fšd +( +Çme +è!ðÝtiÚs. +’d +()) { + +40  +Œue +; + +42  + gçl£ +; + +46  +add + (cÚ¡ +¡d +:: +¡ršg +& +Çme +, cÚ¡ std::¡ršg& +v®ue +) { + +47 ià(! +cÚšs +( +Çme +)) { + +48 +ÝtiÚs +. +š£¹ +( +make_·œ +( +Çme +, +v®ue +)); + +50 +´štf +("¿muÏtÜ::CÚfig::add o±iÚs[%s]‡Ì—dy s‘.\n", +Çme +. +c_¡r +()); + +54  +£t_cÜe_num +( +_cÜe_num +è{ + gcÜe_num + = _core_num;} + +56  +g‘_chªÃls +(ècÚ¡ { + gchªÃls +;} + +57  +g‘_sub¬¿ys +(ècÚ¡ { + gsub¬¿ys +;} + +58  +g‘_¿nks +(ècÚ¡ { + g¿nks +;} + +59  +g‘_ýu_tick +(ècÚ¡ { + gýu_tick +;} + +60  +g‘_mem_tick +(ècÚ¡ { + gmem_tick +;} + +61  +g‘_cÜe_num +(ècÚ¡ { + gcÜe_num +;} + +62  +g‘_ex³ùed_lim™_š¡s +(ècÚ¡ { + gex³ùed_lim™_š¡s +;} + +63 +boÞ + +has_l3_ÿche +() const { + +64 ià( + gÝtiÚs +. +fšd +("ÿche"è!ð +ÝtiÚs +. +’d +()) { + +65 cÚ¡ +¡d +:: +¡ršg +& +ÿche_ÝtiÚ + = ( +ÝtiÚs +. +fšd +("ÿche"))-> +£cÚd +; + +66  ( + gÿche_ÝtiÚ + =ð"®l"è|| ( +ÿche_ÝtiÚ + == "L3"); + +68  + gçl£ +; + +71 +boÞ + +has_cÜe_ÿches +() const { + +72 ià( + gÝtiÚs +. +fšd +("ÿche"è!ð +ÝtiÚs +. +’d +()) { + +73 cÚ¡ +¡d +:: +¡ršg +& +ÿche_ÝtiÚ + = ( +ÝtiÚs +. +fšd +("ÿche"))-> +£cÚd +; + +74  ( + gÿche_ÝtiÚ + =ð"®l" || +ÿche_ÝtiÚ + == "L1L2"); + +76  + gçl£ +; + +79 +boÞ + +is_—¾y_ex™ +() const { + +81 ià( + gÝtiÚs +. +fšd +("—¾y_ex™"è!ð +ÝtiÚs +. +’d +()) { + +82 ià(( +ÝtiÚs +. +fšd +("—¾y_ex™"))-> +£cÚd + == "off") { + +83  +çl£ +; + +85  + gŒue +; + +87  + gŒue +; + +89 +boÞ + +ÿlc_weigh‹d_¥“dup +() const { + +90  ( + gex³ùed_lim™_š¡s + != 0); + +92 +boÞ + +»cÜd_cmd_Œaû +() const { + +94 ià( + gÝtiÚs +. +fšd +("»cÜd_cmd_Œaû"è!ð +ÝtiÚs +. +’d +()) { + +95 ià(( +ÝtiÚs +. +fšd +("»cÜd_cmd_Œaû"))-> +£cÚd + == "on") { + +96  +Œue +; + +98  + gçl£ +; + +100  + gçl£ +; + +102 +boÞ + +´št_cmd_Œaû +() const { + +104 ià( + gÝtiÚs +. +fšd +("´št_cmd_Œaû"è!ð +ÝtiÚs +. +’d +()) { + +105 ià(( +ÝtiÚs +. +fšd +("´št_cmd_Œaû"))-> +£cÚd + == "on") { + +106  +Œue +; + +108  + gçl£ +; + +110  + gçl£ +; + + @Controller.cpp + +1  + ~"CÚŒÞËr.h +" + +2  + ~"SALP.h +" + +3  + ~"ALDRAM.h +" + +4  + ~"TLDRAM.h +" + +6 +usšg + +Çme¥aû + + g¿muÏtÜ +; + +8 +Çme¥aû + + g¿muÏtÜ + + +11  + gveùÜ +<> +g‘_ofãndšg_sub¬¿y +( +DRAM +< +SALP +>* +chªÃl +, +veùÜ +<> & +addr_vec +){ + +12  + g§_id + = 0; + +13 autØ + g¿nk + = +chªÃl +-> +chžd»n +[ +addr_vec +[( +SALP +:: +Lev– +:: +Rªk +)]]; + +14 autØ + gbªk + = +¿nk +-> +chžd»n +[ +addr_vec +[( +SALP +:: +Lev– +:: +Bªk +)]]; + +15 autØ + g§ + = +bªk +-> +chžd»n +[ +addr_vec +[( +SALP +:: +Lev– +:: +SubA¼ay +)]]; + +16 autØ + g§_Ùh” + : +bªk +-> +chžd»n +) + +17 ià( +§ + !ð +§_Ùh” + && sa_Ùh”-> +¡©e + =ð +SALP +:: +S‹ +:: +O³Ãd +){ + +18 +§_id + = +§_Ùh” +-> +id +; + +21 + gveùÜ +<> + gofãndšg + = +addr_vec +; + +22 + gofãndšg +[( +SALP +:: +Lev– +:: +SubA¼ay +)] = +§_id +; + +23 + gofãndšg +[( +SALP +:: +Lev– +:: +Row +)] = -1; + +24  + gofãndšg +; + +28 + g‹m¶©e + <> + +29 + gveùÜ +<> + gCÚŒÞËr +< + gSALP +>:: +g‘_addr_vec +( +SALP +:: +Commªd + +cmd +, +li¡ +< +Reque¡ +>:: +™”©Ü + +»q +){ + +30 ià( +cmd + =ð +SALP +:: +Commªd +:: +PRE_OTHER +) + +31  +g‘_ofãndšg_sub¬¿y +( +chªÃl +, +»q +-> +addr_vec +); + +33  + g»q +-> + gaddr_vec +; + +37 + g‹m¶©e + <> + +38 +boÞ + + gCÚŒÞËr +< + gSALP +>:: +is_»ady +( +li¡ +< +Reque¡ +>:: +™”©Ü + +»q +){ + +39 +SALP +:: +Commªd + +cmd + = +g‘_fœ¡_cmd +( +»q +); + +40 ià( + gcmd + =ð +SALP +:: +Commªd +:: +PRE_OTHER +){ + +42 +veùÜ +<> +addr_vec + = +g‘_ofãndšg_sub¬¿y +( +chªÃl +, +»q +->addr_vec); + +43  + gchªÃl +-> +check +( +cmd +, +addr_vec +. +d©a +(), +þk +); + +45  + gchªÃl +-> +check +( +cmd +, +»q +-> +addr_vec +. +d©a +(), +þk +); + +48 + g‹m¶©e + <> + +49  + gCÚŒÞËr +< + gALDRAM +>:: +upd©e_‹mp +( +ALDRAM +:: +Temp + +cu¼’t_‹m³¿tu» +){ + +50 +chªÃl +-> +¥ec +-> +®d¿m_timšg +( +cu¼’t_‹m³¿tu» +); + +54 + g‹m¶©e + <> + +55  + gCÚŒÞËr +< + gTLDRAM +>:: +tick +(){ + +56 +þk +++; + +57 + g»q_queue_Ëngth_sum + +ð +»adq +. +size +(è+ +wr™eq +.size(); + +58 + g»ad_»q_queue_Ëngth_sum + +ð +»adq +. +size +(); + +59 + gwr™e_»q_queue_Ëngth_sum + +ð +wr™eq +. +size +(); + +62 ià( + g³ndšg +. +size +()) { + +63 + gReque¡ +& + g»q + = +³ndšg +[0]; + +64 ià( + g»q +. + gd•¬t + <ð +þk +) { + +65 ià( +»q +. +d•¬t + -„eq. +¬rive + > 1) { + +66 +»ad_Ï‹ncy_sum + +ð +»q +. +d•¬t + -„eq. +¬rive +; + +67 + gchªÃl +-> +upd©e_£rvšg_»que¡s +( + +68 +»q +. +addr_vec +. +d©a +(), -1, +þk +); + +70 + g»q +. +ÿÎback +( +»q +); + +71 + g³ndšg +. +pÝ_äÚt +(); + +76 + g»äesh +-> +tick_»f +(); + +79 ià(! + gwr™e_mode +) { + +81 ià( + gwr™eq +. +size +(è>ð(0.8 * +wr™eq +. +max +è|| +»adq +.size() == 0) + +82 +wr™e_mode + = +Œue +; + +86 ià( + gwr™eq +. +size +(è<ð(0.2 * +wr™eq +. +max +è&& +»adq +.size() != 0) + +87 +wr™e_mode + = +çl£ +; + +91 +Queue +* + gqueue + = ! +wr™e_mode + ? & +»adq + : & +wr™eq +; + +92 ià( + gÙh”q +. +size +()) + +93 + gqueue + = & +Ùh”q +; + +95 autØ + g»q + = +scheduËr +-> +g‘_h—d +( +queue +-> +q +); + +96 ià( + g»q + =ð +queue +-> +q +. +’d +(è|| ! +is_»ady +( +»q +)) { + +98 autØ +cmd + = +TLDRAM +:: +Commªd +:: +PRE +; + +99 + gveùÜ +<> + gviùim + = +rowpÞicy +-> +g‘_viùim +( +cmd +); + +100 ià(! + gviùim +. +em±y +()){ + +101 +issue_cmd +( +cmd +, +viùim +); + +106 ià( + g»q +-> + gis_fœ¡_commªd +) { + +107  + gcÜeid + = +»q +-> +cÜeid +; + +108 + g»q +-> + gis_fœ¡_commªd + = +çl£ +; + +109 ià( + g»q +-> + gty³ + =ð +Reque¡ +:: +Ty³ +:: +READ + || +»q +-> +ty³ + =ðReque¡::Ty³:: +WRITE +) { + +110 +chªÃl +-> +upd©e_£rvšg_»que¡s +( +»q +-> +addr_vec +. +d©a +(), 1, +þk +); + +112  + gtx + = ( +chªÃl +-> +¥ec +-> +´eãtch_size + * chªÃl->¥ec-> +chªÃl_width + / 8); + +113 ià( + g»q +-> + gty³ + =ð +Reque¡ +:: +Ty³ +:: +READ +) { + +114 ià( +is_row_h™ +( +»q +)) { + +115 ++ +»ad_row_h™s +[ +cÜeid +]; + +116 ++ + grow_h™s +; + +117 } ià( +is_row_Ý’ +( +»q +)) { + +118 ++ + g»ad_row_cÚæiùs +[ +cÜeid +]; + +119 ++ + grow_cÚæiùs +; + +121 ++ + g»ad_row_mis£s +[ +cÜeid +]; + +122 ++ + grow_mis£s +; + +124 + g»ad_Œª§ùiÚ_by‹s + +ð +tx +; + +125 } ià( + g»q +-> + gty³ + =ð +Reque¡ +:: +Ty³ +:: +WRITE +) { + +126 ià( +is_row_h™ +( +»q +)) { + +127 ++ +wr™e_row_h™s +[ +cÜeid +]; + +128 ++ + grow_h™s +; + +129 } ià( +is_row_Ý’ +( +»q +)) { + +130 ++ + gwr™e_row_cÚæiùs +[ +cÜeid +]; + +131 ++ + grow_cÚæiùs +; + +133 ++ + gwr™e_row_mis£s +[ +cÜeid +]; + +134 ++ + grow_mis£s +; + +136 + gwr™e_Œª§ùiÚ_by‹s + +ð +tx +; + +141 ià( + g»q +-> + gty³ + =ð +Reque¡ +:: +Ty³ +:: +READ +) { + +142 +»q +-> +ty³ + = +Reque¡ +:: +Ty³ +:: +EXTENSION +; + +146 autØ + gcmd + = +g‘_fœ¡_cmd +( +»q +); + +147 +issue_cmd +( +cmd +, +g‘_addr_vec +(cmd, +»q +)); + +150 ià( + gcmd + !ð +chªÃl +-> +¥ec +-> +Œª¦©e +[( +»q +-> +ty³ +)]) + +154 ià( + g»q +-> + gty³ + =ð +Reque¡ +:: +Ty³ +:: +READ + || +»q +-> +ty³ + =ðReque¡::Ty³:: +EXTENSION +) { + +155 +»q +-> +d•¬t + = +þk + + +chªÃl +-> +¥ec +-> +»ad_Ï‹ncy +; + +156 + g³ndšg +. +push_back +(* +»q +); + +158 ià( + g»q +-> + gty³ + =ð +Reque¡ +:: +Ty³ +:: +WRITE +) { + +159 +chªÃl +-> +upd©e_£rvšg_»que¡s +( +»q +-> +addr_vec +. +d©a +(), -1, +þk +); + +160 + g»q +-> +ÿÎback +(* +»q +); + +164 + gqueue +-> + gq +. +”a£ +( +»q +); + + @Controller.h + +1 #iâdeà +__CONTROLLER_H + + +2  + #__CONTROLLER_H + + + ) + +4  + ~<ÿs£¹ +> + +5  + ~ + +6  + ~ + +7  + ~ + +8  + ~ + +9  + ~<¡ršg +> + +10  + ~ + +12  + ~"CÚfig.h +" + +13  + ~"DRAM.h +" + +14  + ~"Reäesh.h +" + +15  + ~"Reque¡.h +" + +16  + ~"ScheduËr.h +" + +17  + ~"Sti¡ics.h +" + +19  + ~"ALDRAM.h +" + +20  + ~"SALP.h +" + +21  + ~"TLDRAM.h +" + +23 +usšg + +Çme¥aû + + g¡d +; + +25 +Çme¥aû + + g¿muÏtÜ + + +28 + g‹m¶©e + < +ty³Çme + + gT +> + +29 þas  + cCÚŒÞËr + + +31 + g´Ùeùed +: + +33 +SÿÏrSt + +»ad_Œª§ùiÚ_by‹s +; + +34 +SÿÏrSt + + gwr™e_Œª§ùiÚ_by‹s +; + +36 +SÿÏrSt + + grow_h™s +; + +37 +SÿÏrSt + + grow_mis£s +; + +38 +SÿÏrSt + + grow_cÚæiùs +; + +39 +VeùÜSt + + g»ad_row_h™s +; + +40 +VeùÜSt + + g»ad_row_mis£s +; + +41 +VeùÜSt + + g»ad_row_cÚæiùs +; + +42 +VeùÜSt + + gwr™e_row_h™s +; + +43 +VeùÜSt + + gwr™e_row_mis£s +; + +44 +VeùÜSt + + gwr™e_row_cÚæiùs +; + +46 +SÿÏrSt + + g»ad_Ï‹ncy_avg +; + +47 +SÿÏrSt + + g»ad_Ï‹ncy_sum +; + +49 +SÿÏrSt + + g»q_queue_Ëngth_avg +; + +50 +SÿÏrSt + + g»q_queue_Ëngth_sum +; + +51 +SÿÏrSt + + g»ad_»q_queue_Ëngth_avg +; + +52 +SÿÏrSt + + g»ad_»q_queue_Ëngth_sum +; + +53 +SÿÏrSt + + gwr™e_»q_queue_Ëngth_avg +; + +54 +SÿÏrSt + + gwr™e_»q_queue_Ëngth_sum +; + +56 #iâdeà +INTEGRATED_WITH_GEM5 + + +57 +VeùÜSt + + g»cÜd_»ad_h™s +; + +58 +VeùÜSt + + g»cÜd_»ad_mis£s +; + +59 +VeùÜSt + + g»cÜd_»ad_cÚæiùs +; + +60 +VeùÜSt + + g»cÜd_wr™e_h™s +; + +61 +VeùÜSt + + g»cÜd_wr™e_mis£s +; + +62 +VeùÜSt + + g»cÜd_wr™e_cÚæiùs +; + +65 + gpublic +: + +67  +þk + = 0; + +68 + gDRAM +< + gT +>* + gchªÃl +; + +70 + gScheduËr +< + gT +>* + gscheduËr +; + +71 + gRowPÞicy +< + gT +>* + growpÞicy +; + +72 + gRowTabË +< + gT +>* + growbË +; + +73 + gReäesh +< + gT +>* + g»äesh +; + +75  + sQueue + { + +76 + gli¡ +< + gReque¡ +> + gq +; + +77  + gmax + = 32; + +78  +size +(è{ + gq +.size();} + +81 +Queue + + g»adq +; + +82 +Queue + + gwr™eq +; + +83 +Queue + + gÙh”q +; + +85 + gdeque +< + gReque¡ +> + g³ndšg +; + +86 +boÞ + + gwr™e_mode + = +çl£ +; + +90 +¡ršg + + gcmd_Œaû_´efix + = "cmd-trace-"; + +91 + gveùÜ +< + gof¡»am +> + gcmd_Œaû_fžes +; + +92 +boÞ + + g»cÜd_cmd_Œaû + = +çl£ +; + +94 +boÞ + + g´št_cmd_Œaû + = +çl£ +; + +97 +CÚŒÞËr +(cÚ¡ +CÚfig +& +cÚfigs +, +DRAM +< +T +>* +chªÃl +) : + +98 +chªÃl +(channel), + +99 +scheduËr +( +Ãw + +ScheduËr +< +T +>( +this +)), + +100 +rowpÞicy +( +Ãw + +RowPÞicy +< +T +>( +this +)), + +101 +rowbË +( +Ãw + +RowTabË +< +T +>( +this +)), + +102 +»äesh +( +Ãw + +Reäesh +< +T +>( +this +)), + +103 +cmd_Œaû_fžes +( +chªÃl +-> +chžd»n +. +size +()) + +105 + g»cÜd_cmd_Œaû + = +cÚfigs +. +»cÜd_cmd_Œaû +(); + +106 + g´št_cmd_Œaû + = +cÚfigs +. +´št_cmd_Œaû +(); + +107 ià( + g»cÜd_cmd_Œaû +){ + +108 ià( + gcÚfigs +["cmd_trace_prefix"] != "") { + +109 +cmd_Œaû_´efix + = +cÚfigs +["cmd_trace_prefix"]; + +111 +¡ršg + + g´efix + = +cmd_Œaû_´efix + + "chª-" + +to_¡ršg +( +chªÃl +-> +id +) + "-rank-"; + +112 +¡ršg + + gsuffix + = ".cmdtrace"; + +113  + gi + = 0; i < + gchªÃl +-> + gchžd»n +. +size +(); i++) + +114 + gcmd_Œaû_fžes +[ +i +]. +Ý’ +( +´efix + + +to_¡ršg +(iè+ +suffix +); + +119 + grow_h™s + + +120 . +Çme +("row_h™s_chªÃl_"+ +to_¡ršg +( +chªÃl +-> +id +) + "_core") + +121 . +desc +("Number of„ow hits…er channel…er core") + +122 . +´ecisiÚ +(0) + +124 + grow_mis£s + + +125 . +Çme +("row_mis£s_chªÃl_"+ +to_¡ršg +( +chªÃl +-> +id +) + "_core") + +126 . +desc +("Number of„ow misses…er channel…er core") + +127 . +´ecisiÚ +(0) + +129 + grow_cÚæiùs + + +130 . +Çme +("row_cÚæiùs_chªÃl_"+ +to_¡ršg +( +chªÃl +-> +id +) + "_core") + +131 . +desc +("Number of„ow conflicts…er channel…er core") + +132 . +´ecisiÚ +(0) + +135 + g»ad_row_h™s + + +136 . +š™ +( +cÚfigs +. +g‘_cÜe_num +()) + +137 . +Çme +("»ad_row_h™s_chªÃl_"+ +to_¡ršg +( +chªÃl +-> +id +) + "_core") + +138 . +desc +("Number of„ow hits for„ead„equests…er channel…er core") + +139 . +´ecisiÚ +(0) + +141 + g»ad_row_mis£s + + +142 . +š™ +( +cÚfigs +. +g‘_cÜe_num +()) + +143 . +Çme +("»ad_row_mis£s_chªÃl_"+ +to_¡ršg +( +chªÃl +-> +id +) + "_core") + +144 . +desc +("Number of„ow misses for„ead„equests…er channel…er core") + +145 . +´ecisiÚ +(0) + +147 + g»ad_row_cÚæiùs + + +148 . +š™ +( +cÚfigs +. +g‘_cÜe_num +()) + +149 . +Çme +("»ad_row_cÚæiùs_chªÃl_"+ +to_¡ršg +( +chªÃl +-> +id +) + "_core") + +150 . +desc +("Number of„ow conflicts for„ead„equests…er channel…er core") + +151 . +´ecisiÚ +(0) + +154 + gwr™e_row_h™s + + +155 . +š™ +( +cÚfigs +. +g‘_cÜe_num +()) + +156 . +Çme +("wr™e_row_h™s_chªÃl_"+ +to_¡ršg +( +chªÃl +-> +id +) + "_core") + +157 . +desc +("Number of„ow hits for write„equests…er channel…er core") + +158 . +´ecisiÚ +(0) + +160 + gwr™e_row_mis£s + + +161 . +š™ +( +cÚfigs +. +g‘_cÜe_num +()) + +162 . +Çme +("wr™e_row_mis£s_chªÃl_"+ +to_¡ršg +( +chªÃl +-> +id +) + "_core") + +163 . +desc +("Number of„ow misses for write„equests…er channel…er core") + +164 . +´ecisiÚ +(0) + +166 + gwr™e_row_cÚæiùs + + +167 . +š™ +( +cÚfigs +. +g‘_cÜe_num +()) + +168 . +Çme +("wr™e_row_cÚæiùs_chªÃl_"+ +to_¡ršg +( +chªÃl +-> +id +) + "_core") + +169 . +desc +("Number of„ow conflicts for write„equests…er channel…er core") + +170 . +´ecisiÚ +(0) + +173 + g»ad_Œª§ùiÚ_by‹s + + +174 . +Çme +("»ad_Œª§ùiÚ_by‹s_"+ +to_¡ršg +( +chªÃl +-> +id +)) + +175 . +desc +("Theotal byte of„eadransaction…er channel") + +176 . +´ecisiÚ +(0) + +178 + gwr™e_Œª§ùiÚ_by‹s + + +179 . +Çme +("wr™e_Œª§ùiÚ_by‹s_"+ +to_¡ršg +( +chªÃl +-> +id +)) + +180 . +desc +("Theotal byte of writeransaction…er channel") + +181 . +´ecisiÚ +(0) + +184 + g»ad_Ï‹ncy_sum + + +185 . +Çme +("»ad_Ï‹ncy_sum_"+ +to_¡ršg +( +chªÃl +-> +id +)) + +186 . +desc +("The memory†atency cycles (in memoryime domain) sum for‡ll„ead„equests inhis channel") + +187 . +´ecisiÚ +(0) + +189 + g»ad_Ï‹ncy_avg + + +190 . +Çme +("»ad_Ï‹ncy_avg_"+ +to_¡ršg +( +chªÃl +-> +id +)) + +191 . +desc +("The‡verage memory†atency cycles (in memoryime domain)…er„equest for‡ll„ead„equests inhis channel") + +192 . +´ecisiÚ +(6) + +195 + g»q_queue_Ëngth_sum + + +196 . +Çme +("»q_queue_Ëngth_sum_"+ +to_¡ršg +( +chªÃl +-> +id +)) + +197 . +desc +("Sum of„ead‡nd write queue†ength…er memory cycle…er channel.") + +198 . +´ecisiÚ +(0) + +200 + g»q_queue_Ëngth_avg + + +201 . +Çme +("»q_queue_Ëngth_avg_"+ +to_¡ršg +( +chªÃl +-> +id +)) + +202 . +desc +("Average of„ead‡nd write queue†ength…er memory cycle…er channel.") + +203 . +´ecisiÚ +(6) + +206 + g»ad_»q_queue_Ëngth_sum + + +207 . +Çme +("»ad_»q_queue_Ëngth_sum_"+ +to_¡ršg +( +chªÃl +-> +id +)) + +208 . +desc +("Read queue†ength sum…er memory cycle…er channel.") + +209 . +´ecisiÚ +(0) + +211 + g»ad_»q_queue_Ëngth_avg + + +212 . +Çme +("»ad_»q_queue_Ëngth_avg_"+ +to_¡ršg +( +chªÃl +-> +id +)) + +213 . +desc +("Read queue†ength‡verage…er memory cycle…er channel.") + +214 . +´ecisiÚ +(6) + +217 + gwr™e_»q_queue_Ëngth_sum + + +218 . +Çme +("wr™e_»q_queue_Ëngth_sum_"+ +to_¡ršg +( +chªÃl +-> +id +)) + +219 . +desc +("Write queue†ength sum…er memory cycle…er channel.") + +220 . +´ecisiÚ +(0) + +222 + gwr™e_»q_queue_Ëngth_avg + + +223 . +Çme +("wr™e_»q_queue_Ëngth_avg_"+ +to_¡ršg +( +chªÃl +-> +id +)) + +224 . +desc +("Write queue†ength‡verage…er memory cycle…er channel.") + +225 . +´ecisiÚ +(6) + +228 #iâdeà +INTEGRATED_WITH_GEM5 + + +229 + g»cÜd_»ad_h™s + + +230 . +š™ +( +cÚfigs +. +g‘_cÜe_num +()) + +231 . +Çme +("record_read_hits") + +232 . +desc +("record„ead hit count forhis core when it„eaches„equest†imit oroheƒnd") + +235 + g»cÜd_»ad_mis£s + + +236 . +š™ +( +cÚfigs +. +g‘_cÜe_num +()) + +237 . +Çme +("record_read_misses") + +238 . +desc +("record_read_miss count forhis core when it„eaches„equest†imit oroheƒnd") + +241 + g»cÜd_»ad_cÚæiùs + + +242 . +š™ +( +cÚfigs +. +g‘_cÜe_num +()) + +243 . +Çme +("record_read_conflicts") + +244 . +desc +("record„ead conflict count forhis core when it„eaches„equest†imit oroheƒnd") + +247 + g»cÜd_wr™e_h™s + + +248 . +š™ +( +cÚfigs +. +g‘_cÜe_num +()) + +249 . +Çme +("record_write_hits") + +250 . +desc +("record write hit count forhis core when it„eaches„equest†imit oroheƒnd") + +253 + g»cÜd_wr™e_mis£s + + +254 . +š™ +( +cÚfigs +. +g‘_cÜe_num +()) + +255 . +Çme +("record_write_misses") + +256 . +desc +("record write miss count forhis core when it„eaches„equest†imit oroheƒnd") + +259 + g»cÜd_wr™e_cÚæiùs + + +260 . +š™ +( +cÚfigs +. +g‘_cÜe_num +()) + +261 . +Çme +("record_write_conflicts") + +262 . +desc +("record write conflict forhis core when it„eaches„equest†imit oroheƒnd") + +267 ~ +CÚŒÞËr +(){ + +268 +d–‘e + + gscheduËr +; + +269 +d–‘e + + growpÞicy +; + +270 +d–‘e + + growbË +; + +271 +d–‘e + + gchªÃl +; + +272 +d–‘e + + g»äesh +; + +273 auto& + gfže + : +cmd_Œaû_fžes +) + +274 +fže +. +þo£ +(); + +275 + gcmd_Œaû_fžes +. +þ—r +(); + +278  +fšish +( +»ad_»q +,  +d¿m_cyþes +) { + +279 + g»ad_Ï‹ncy_avg + = +»ad_Ï‹ncy_sum +. +v®ue +(è/ +»ad_»q +; + +280 + g»q_queue_Ëngth_avg + = +»q_queue_Ëngth_sum +. +v®ue +(è/ +d¿m_cyþes +; + +281 + g»ad_»q_queue_Ëngth_avg + = +»ad_»q_queue_Ëngth_sum +. +v®ue +(è/ +d¿m_cyþes +; + +282 + gwr™e_»q_queue_Ëngth_avg + = +wr™e_»q_queue_Ëngth_sum +. +v®ue +(è/ +d¿m_cyþes +; + +284 + gchªÃl +-> +fšish +( +d¿m_cyþes +); + +288 + gQueue +& +g‘_queue +( +Reque¡ +:: +Ty³ + +ty³ +) + +290 ( +ty³ +)) { + +291 ( +Reque¡ +:: +Ty³ +:: +READ +):  +»adq +; + +292 ( + gReque¡ +:: +Ty³ +:: +WRITE +):  +wr™eq +; + +293 :  +Ùh”q +; + +297 +boÞ + +’queue +( +Reque¡ +& +»q +) + +299 + gQueue +& + gqueue + = +g‘_queue +( +»q +. +ty³ +); + +300 ià( + gqueue +. + gmax + =ð +queue +. +size +()) + +301  +çl£ +; + +303 + g»q +. + g¬rive + = +þk +; + +304 + gqueue +. + gq +. +push_back +( +»q +); + +307 ià( + g»q +. + gty³ + =ð +Reque¡ +:: +Ty³ +:: +READ + && +fšd_if +( +wr™eq +. +q +. +begš +(), wr™eq.q. +’d +(), + +308 [ +»q +]( +Reque¡ +& +w»q +){ „eq. +addr + =ðw»q.addr;}è!ð +wr™eq +. +q +. +’d +()){ + +309 +»q +. +d•¬t + = +þk + + 1; + +310 + g³ndšg +. +push_back +( +»q +); + +311 + g»adq +. + gq +. +pÝ_back +(); + +313  + gŒue +; + +316  +tick +() + +318 + gþk +++; + +319 + g»q_queue_Ëngth_sum + +ð +»adq +. +size +(è+ +wr™eq +.size(è+ +³ndšg +.size(); + +320 + g»ad_»q_queue_Ëngth_sum + +ð +»adq +. +size +(è+ +³ndšg +.size(); + +321 + gwr™e_»q_queue_Ëngth_sum + +ð +wr™eq +. +size +(); + +324 ià( + g³ndšg +. +size +()) { + +325 + gReque¡ +& + g»q + = +³ndšg +[0]; + +326 ià( + g»q +. + gd•¬t + <ð +þk +) { + +327 ià( +»q +. +d•¬t + -„eq. +¬rive + > 1) { + +328 +»ad_Ï‹ncy_sum + +ð +»q +. +d•¬t + -„eq. +¬rive +; + +329 + gchªÃl +-> +upd©e_£rvšg_»que¡s +( + +330 +»q +. +addr_vec +. +d©a +(), -1, +þk +); + +332 + g»q +. +ÿÎback +( +»q +); + +333 + g³ndšg +. +pÝ_äÚt +(); + +338 + g»äesh +-> +tick_»f +(); + +341 ià(! + gwr™e_mode +) { + +343 ià( + gwr™eq +. +size +(è>ð(0.8 * +wr™eq +. +max +è|| +»adq +.size() == 0) + +344 +wr™e_mode + = +Œue +; + +348 ià( + gwr™eq +. +size +(è<ð(0.2 * +wr™eq +. +max +è&& +»adq +.size() != 0) + +349 +wr™e_mode + = +çl£ +; + +353 +Queue +* + gqueue + = ! +wr™e_mode + ? & +»adq + : & +wr™eq +; + +354 ià( + gÙh”q +. +size +()) + +355 + gqueue + = & +Ùh”q +; + +357 autØ + g»q + = +scheduËr +-> +g‘_h—d +( +queue +-> +q +); + +358 ià( + g»q + =ð +queue +-> +q +. +’d +(è|| ! +is_»ady +( +»q +)) { + +360 autØ +cmd + = +T +:: +Commªd +:: +PRE +; + +361 + gveùÜ +<> + gviùim + = +rowpÞicy +-> +g‘_viùim +( +cmd +); + +362 ià(! + gviùim +. +em±y +()){ + +363 +issue_cmd +( +cmd +, +viùim +); + +368 ià( + g»q +-> + gis_fœ¡_commªd +) { + +369 + g»q +-> + gis_fœ¡_commªd + = +çl£ +; + +370  + gcÜeid + = +»q +-> +cÜeid +; + +371 ià( + g»q +-> + gty³ + =ð +Reque¡ +:: +Ty³ +:: +READ + || +»q +-> +ty³ + =ðReque¡::Ty³:: +WRITE +) { + +372 +chªÃl +-> +upd©e_£rvšg_»que¡s +( +»q +-> +addr_vec +. +d©a +(), 1, +þk +); + +374  + gtx + = ( +chªÃl +-> +¥ec +-> +´eãtch_size + * chªÃl->¥ec-> +chªÃl_width + / 8); + +375 ià( + g»q +-> + gty³ + =ð +Reque¡ +:: +Ty³ +:: +READ +) { + +376 ià( +is_row_h™ +( +»q +)) { + +377 ++ +»ad_row_h™s +[ +cÜeid +]; + +378 ++ + grow_h™s +; + +379 } ià( +is_row_Ý’ +( +»q +)) { + +380 ++ + g»ad_row_cÚæiùs +[ +cÜeid +]; + +381 ++ + grow_cÚæiùs +; + +383 ++ + g»ad_row_mis£s +[ +cÜeid +]; + +384 ++ + grow_mis£s +; + +386 + g»ad_Œª§ùiÚ_by‹s + +ð +tx +; + +387 } ià( + g»q +-> + gty³ + =ð +Reque¡ +:: +Ty³ +:: +WRITE +) { + +388 ià( +is_row_h™ +( +»q +)) { + +389 ++ +wr™e_row_h™s +[ +cÜeid +]; + +390 ++ + grow_h™s +; + +391 } ià( +is_row_Ý’ +( +»q +)) { + +392 ++ + gwr™e_row_cÚæiùs +[ +cÜeid +]; + +393 ++ + grow_cÚæiùs +; + +395 ++ + gwr™e_row_mis£s +[ +cÜeid +]; + +396 ++ + grow_mis£s +; + +398 + gwr™e_Œª§ùiÚ_by‹s + +ð +tx +; + +403 autØ + gcmd + = +g‘_fœ¡_cmd +( +»q +); + +404 +issue_cmd +( +cmd +, +g‘_addr_vec +(cmd, +»q +)); + +407 ià( + gcmd + !ð +chªÃl +-> +¥ec +-> +Œª¦©e +[( +»q +-> +ty³ +)]) + +411 ià( + g»q +-> + gty³ + =ð +Reque¡ +:: +Ty³ +:: +READ +) { + +412 +»q +-> +d•¬t + = +þk + + +chªÃl +-> +¥ec +-> +»ad_Ï‹ncy +; + +413 + g³ndšg +. +push_back +(* +»q +); + +416 ià( + g»q +-> + gty³ + =ð +Reque¡ +:: +Ty³ +:: +WRITE +) { + +417 +chªÃl +-> +upd©e_£rvšg_»que¡s +( +»q +-> +addr_vec +. +d©a +(), -1, +þk +); + +421 + gqueue +-> + gq +. +”a£ +( +»q +); + +424 +boÞ + +is_»ady +( +li¡ +< +Reque¡ +>:: +™”©Ü + +»q +) + +426 +ty³Çme + +T +:: +Commªd + +cmd + = +g‘_fœ¡_cmd +( +»q +); + +427  + gchªÃl +-> +check +( +cmd +, +»q +-> +addr_vec +. +d©a +(), +þk +); + +430 +boÞ + +is_»ady +( +ty³Çme + +T +:: +Commªd + +cmd +, cÚ¡ +veùÜ +<>& +addr_vec +) + +432  + gchªÃl +-> +check +( +cmd +, +addr_vec +. +d©a +(), +þk +); + +435 +boÞ + +is_row_h™ +( +li¡ +< +Reque¡ +>:: +™”©Ü + +»q +) + +438 +ty³Çme + +T +:: +Commªd + +cmd + = +chªÃl +-> +¥ec +-> +Œª¦©e +[( +»q +-> +ty³ +)]; + +439  + gchªÃl +-> +check_row_h™ +( +cmd +, +»q +-> +addr_vec +. +d©a +()); + +442 +boÞ + +is_row_h™ +( +ty³Çme + +T +:: +Commªd + +cmd +, cÚ¡ +veùÜ +<>& +addr_vec +) + +444  + gchªÃl +-> +check_row_h™ +( +cmd +, +addr_vec +. +d©a +()); + +447 +boÞ + +is_row_Ý’ +( +li¡ +< +Reque¡ +>:: +™”©Ü + +»q +) + +450 +ty³Çme + +T +:: +Commªd + +cmd + = +chªÃl +-> +¥ec +-> +Œª¦©e +[( +»q +-> +ty³ +)]; + +451  + gchªÃl +-> +check_row_Ý’ +( +cmd +, +»q +-> +addr_vec +. +d©a +()); + +454 +boÞ + +is_row_Ý’ +( +ty³Çme + +T +:: +Commªd + +cmd +, cÚ¡ +veùÜ +<>& +addr_vec +) + +456  + gchªÃl +-> +check_row_Ý’ +( +cmd +, +addr_vec +. +d©a +()); + +459  +upd©e_‹mp +( +ALDRAM +:: +Temp + +cu¼’t_‹m³¿tu» +) + +464 +boÞ + +is_aùive +() { + +465  ( +chªÃl +-> +cur_£rvšg_»que¡s + > 0); + +469 +boÞ + +is_»äesh +() { + +470  + gþk + <ð +chªÃl +-> +’d_of_»äeshšg +; + +473  +»cÜd_cÜe +( +cÜeid +) { + +474 #iâdeà +INTEGRATED_WITH_GEM5 + + +475 + g»cÜd_»ad_h™s +[ +cÜeid +] = +»ad_row_h™s +[coreid]; + +476 + g»cÜd_»ad_mis£s +[ +cÜeid +] = +»ad_row_mis£s +[coreid]; + +477 + g»cÜd_»ad_cÚæiùs +[ +cÜeid +] = +»ad_row_cÚæiùs +[coreid]; + +478 + g»cÜd_wr™e_h™s +[ +cÜeid +] = +wr™e_row_h™s +[coreid]; + +479 + g»cÜd_wr™e_mis£s +[ +cÜeid +] = +wr™e_row_mis£s +[coreid]; + +480 + g»cÜd_wr™e_cÚæiùs +[ +cÜeid +] = +wr™e_row_cÚæiùs +[coreid]; + +484 + g´iv©e +: + +485 +ty³Çme + +T +:: +Commªd + +g‘_fœ¡_cmd +( +li¡ +< +Reque¡ +>:: +™”©Ü + +»q +) + +487 +ty³Çme + +T +:: +Commªd + +cmd + = +chªÃl +-> +¥ec +-> +Œª¦©e +[( +»q +-> +ty³ +)]; + +488  + gchªÃl +-> +decode +( +cmd +, +»q +-> +addr_vec +. +d©a +()); + +491  +issue_cmd +( +ty³Çme + +T +:: +Commªd + +cmd +, cÚ¡ +veùÜ +<>& +addr_vec +) + +493 +as£¹ +( +is_»ady +( +cmd +, +addr_vec +)); + +494 + gchªÃl +-> +upd©e +( +cmd +, +addr_vec +. +d©a +(), +þk +); + +495 + growbË +-> +upd©e +( +cmd +, +addr_vec +, +þk +); + +496 ià( + g»cÜd_cmd_Œaû +){ + +498 auto& + gfže + = +cmd_Œaû_fžes +[ +addr_vec +[1]]; + +499 + g¡ršg +& + gcmd_Çme + = +chªÃl +-> +¥ec +-> +commªd_Çme +[( +cmd +)]; + +500 + gfže +<< + gþk +<<','<< + gcmd_Çme +; + +502 ià( + gcmd_Çme + =ð"PREA" || +cmd_Çme + == "REF") + +503 +fže +<< +’dl +; + +505  + gbªk_id + = +addr_vec +[( +T +:: +Lev– +:: +Bªk +)]; + +506 ià( + gchªÃl +-> + g¥ec +-> + g¡ªd¬d_Çme + =ð"DDR4" || +chªÃl +-> +¥ec +-> +¡ªd¬d_Çme + == "GDDR5") + +507 +bªk_id + +ð +addr_vec +[( +T +:: +Lev– +:: +Bªk +è- 1] * +chªÃl +-> +¥ec +-> +Üg_’Œy +. +couÁ +[(T::Level::Bank)]; + +508 + gfže +<<','<< + gbªk_id +<< + g’dl +; + +511 ià( + g´št_cmd_Œaû +){ + +512 +´štf +("%5 %10ld:", +chªÃl +-> +¥ec +-> +commªd_Çme +[( +cmd +)]. +c_¡r +(), +þk +); + +513  + gËv + = 0;†ev < ( + gT +:: +Lev– +:: +MAX +);†ev++) + +514 +´štf +(" %5d", +addr_vec +[ +Ëv +]); + +515 +´štf +("\n"); + +518 + gveùÜ +<> +g‘_addr_vec +( +ty³Çme + +T +:: +Commªd + +cmd +, +li¡ +< +Reque¡ +>:: +™”©Ü + +»q +){ + +519  +»q +-> +addr_vec +; + +523 + g‹m¶©e + <> + +524 + gveùÜ +<> + gCÚŒÞËr +< + gSALP +>:: +g‘_addr_vec +( + +525 +SALP +:: +Commªd + +cmd +, +li¡ +< +Reque¡ +>:: +™”©Ü + +»q +); + +527 + g‹m¶©e + <> + +528 +boÞ + + gCÚŒÞËr +< + gSALP +>:: +is_»ady +( +li¡ +< +Reque¡ +>:: +™”©Ü + +»q +); + +530 + g‹m¶©e + <> + +531  + gCÚŒÞËr +< + gALDRAM +>:: +upd©e_‹mp +( +ALDRAM +:: +Temp + +cu¼’t_‹m³¿tu» +); + +533 + g‹m¶©e + <> + +534  + gCÚŒÞËr +< + gTLDRAM +>:: +tick +(); + + @DDR3.cpp + +1  + ~"DDR3.h +" + +2  + ~"DRAM.h +" + +3  + ~ + +4  + ~ + +5  + ~<ÿs£¹ +> + +7 +usšg + +Çme¥aû + + g¡d +; + +8 +usšg + +Çme¥aû + + g¿muÏtÜ +; + +10 +¡ršg + + gDDR3 +:: +¡ªd¬d_Çme + = "DDR3"; + +12 + gm­ +< + g¡ršg +, + gDDR3 +:: +Org +> +DDR3 +:: +Üg_m­ + = { + +13 {"DDR3_512Mb_x4", +DDR3 +:: +Org +:: +DDR3_512Mb_x4 +}, {"DDR3_512Mb_x8", DDR3::Org:: +DDR3_512Mb_x8 +}, {"DDR3_512Mb_x16", DDR3::Org:: +DDR3_512Mb_x16 +}, + +14 {"DDR3_1Gb_x4", +DDR3 +:: +Org +:: +DDR3_1Gb_x4 +}, {"DDR3_1Gb_x8", DDR3::Org:: +DDR3_1Gb_x8 +}, {"DDR3_1Gb_x16", DDR3::Org:: +DDR3_1Gb_x16 +}, + +15 {"DDR3_2Gb_x4", +DDR3 +:: +Org +:: +DDR3_2Gb_x4 +}, {"DDR3_2Gb_x8", DDR3::Org:: +DDR3_2Gb_x8 +}, {"DDR3_2Gb_x16", DDR3::Org:: +DDR3_2Gb_x16 +}, + +16 {"DDR3_4Gb_x4", +DDR3 +:: +Org +:: +DDR3_4Gb_x4 +}, {"DDR3_4Gb_x8", DDR3::Org:: +DDR3_4Gb_x8 +}, {"DDR3_4Gb_x16", DDR3::Org:: +DDR3_4Gb_x16 +}, + +17 {"DDR3_8Gb_x4", +DDR3 +:: +Org +:: +DDR3_8Gb_x4 +}, {"DDR3_8Gb_x8", DDR3::Org:: +DDR3_8Gb_x8 +}, {"DDR3_8Gb_x16", DDR3::Org:: +DDR3_8Gb_x16 +}, + +20 + gm­ +< + g¡ršg +, + gDDR3 +:: +S³ed +> +DDR3 +:: +¥“d_m­ + = { + +21 {"DDR3_800D", +DDR3 +:: +S³ed +:: +DDR3_800D +}, {"DDR3_800E", DDR3::S³ed:: +DDR3_800E +}, + +22 {"DDR3_1066E", +DDR3 +:: +S³ed +:: +DDR3_1066E +}, {"DDR3_1066F", DDR3::S³ed:: +DDR3_1066F +}, {"DDR3_1066G", DDR3::S³ed:: +DDR3_1066G +}, + +23 {"DDR3_1333G", +DDR3 +:: +S³ed +:: +DDR3_1333G +}, {"DDR3_1333H", DDR3::S³ed:: +DDR3_1333H +}, + +24 {"DDR3_1600H", +DDR3 +:: +S³ed +:: +DDR3_1600H +}, {"DDR3_1600J", DDR3::S³ed:: +DDR3_1600J +}, {"DDR3_1600K", DDR3::S³ed:: +DDR3_1600K +}, + +25 {"DDR3_1866K", +DDR3 +:: +S³ed +:: +DDR3_1866K +}, {"DDR3_1866L", DDR3::S³ed:: +DDR3_1866L +}, + +26 {"DDR3_2133L", +DDR3 +:: +S³ed +:: +DDR3_2133L +}, {"DDR3_2133M", DDR3::S³ed:: +DDR3_2133M +}, + +30 + gDDR3 +:: + $DDR3 +( +Org + +Üg +, +S³ed + +¥“d +) : + +31 + `Üg_’Œy +( +Üg_bË +[( +Üg +)]), + +32 + `¥“d_’Œy +( +¥“d_bË +[( +¥“d +)]), + +33 + `»ad_Ï‹ncy +( +¥“d_’Œy +. +nCL + + s³ed_’Œy. +nBL +) + +35 + `š™_¥“d +(); + +36 + `š™_´”eq +(); + +37 + `š™_rowh™ +(); + +38 + `š™_rowÝ’ +(); + +39 + `š™_Ïmbda +(); + +40 + `š™_timšg +(); + +41 + } +} + +43 + gDDR3 +:: + $DDR3 +(cÚ¡ +¡ršg +& +Üg_¡r +, cÚ¡ sŒšg& +¥“d_¡r +) : + +44 + $DDR3 +( +Üg_m­ +[ +Üg_¡r +], +¥“d_m­ +[ +¥“d_¡r +]) + +46 + } +} + +48  + gDDR3 +:: + $£t_chªÃl_numb” +( +chªÃl +) { + +49 +Üg_’Œy +. +couÁ +[( +Lev– +:: +ChªÃl +)] = +chªÃl +; + +50 + } +} + +52  + gDDR3 +:: + $£t_¿nk_numb” +( +¿nk +) { + +53 +Üg_’Œy +. +couÁ +[( +Lev– +:: +Rªk +)] = +¿nk +; + +54 + } +} + +56  + gDDR3 +:: + $š™_¥“d +() + +59  +·ge + = ( +Üg_’Œy +. +dq + * org_’Œy. +couÁ +[( +Lev– +:: +CÞumn +)]) >> 13; + +60  +¥“d_’Œy +. +¿‹ +) { + +61 800: +¥“d_’Œy +. +nRRD + = ( +·ge +==1è? 4 : 4; s³ed_’Œy. +nFAW + = (page==1) ? 16 : 20; ; + +62 1066: +¥“d_’Œy +. +nRRD + = ( +·ge +==1è? 4 : 6; s³ed_’Œy. +nFAW + = (page==1) ? 20 : 27; ; + +63 1333: +¥“d_’Œy +. +nRRD + = ( +·ge +==1è? 4 : 5; s³ed_’Œy. +nFAW + = (page==1) ? 20 : 30; ; + +64 1600: +¥“d_’Œy +. +nRRD + = ( +·ge +==1è? 5 : 6; s³ed_’Œy. +nFAW + = (page==1) ? 24 : 32; ; + +65 1866: +¥“d_’Œy +. +nRRD + = ( +·ge +==1è? 5 : 6; s³ed_’Œy. +nFAW + = (page==1) ? 26 : 33; ; + +66 2133: +¥“d_’Œy +. +nRRD + = ( +·ge +==1è? 5 : 6; s³ed_’Œy. +nFAW + = (page==1) ? 27 : 34; ; + +67 : + `as£¹ +( +çl£ +); + +71  +ch + = +Üg_’Œy +. +size +; + +72  +¥“d_’Œy +. +¿‹ +) { + +73 800: +¥“d_’Œy +. +nRFC + = ( +ch +==512) ? 36 : (chip==1<<10) ? 44 : (chip==1<<11) ? 64 : (chip==1<<12) ? 104 : 140; ; + +74 1066: +¥“d_’Œy +. +nRFC + = ( +ch +==512) ? 48 : (chip==1<<10) ? 59 : (chip==1<<11) ? 86 : (chip==1<<12) ? 139 : 187; ; + +75 1333: +¥“d_’Œy +. +nRFC + = ( +ch +==512) ? 60 : (chip==1<<10) ? 74 : (chip==1<<11) ? 107 : (chip==1<<12) ? 174 : 234; ; + +76 1600: +¥“d_’Œy +. +nRFC + = ( +ch +==512) ? 72 : (chip==1<<10) ? 88 : (chip==1<<11) ? 128 : (chip==1<<12) ? 208 : 280; ; + +77 1866: +¥“d_’Œy +. +nRFC + = ( +ch +==512) ? 84 : (chip==1<<10) ? 103 : (chip==1<<11) ? 150 : (chip==1<<12) ? 243 : 327; ; + +78 2133: +¥“d_’Œy +. +nRFC + = ( +ch +==512) ? 96 : (chip==1<<10) ? 118 : (chip==1<<11) ? 171 : (chip==1<<12) ? 278 : 374; ; + +79 : + `as£¹ +( +çl£ +); + +81  +¥“d_’Œy +. +¿‹ +) { + +82 800: +¥“d_’Œy +. +nXS + = ( +ch +==512) ? 40 : (chip==1<<10) ? 48 : (chip==1<<11) ? 68 : (chip==1<<12) ? 108 : 144; ; + +83 1066: +¥“d_’Œy +. +nXS + = ( +ch +==512) ? 54 : (chip==1<<10) ? 64 : (chip==1<<11) ? 91 : (chip==1<<12) ? 144 : 192; ; + +84 1333: +¥“d_’Œy +. +nXS + = ( +ch +==512) ? 67 : (chip==1<<10) ? 80 : (chip==1<<11) ? 114 : (chip==1<<12) ? 180 : 240; ; + +85 1600: +¥“d_’Œy +. +nXS + = ( +ch +==512) ? 80 : (chip==1<<10) ? 96 : (chip==1<<11) ? 136 : (chip==1<<12) ? 216 : 288; ; + +86 1866: +¥“d_’Œy +. +nXS + = ( +ch +==512) ? 94 : (chip==1<<10) ? 112 : (chip==1<<11) ? 159 : (chip==1<<12) ? 252 : 336; ; + +87 2133: +¥“d_’Œy +. +nXS + = ( +ch +==512) ? 107 : (chip==1<<10) ? 128 : (chip==1<<11) ? 182 : (chip==1<<12) ? 288 : 384; ; + +88 : + `as£¹ +( +çl£ +); + +90 + } +} + +93  + gDDR3 +:: + $š™_´”eq +() + +96 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +DDR3 +>* +node +, Commªd +cmd +,  +id +) { + +97 ( +node +-> +¡©e +)) { + +98 ( +S‹ +:: +Pow”Up +):  +Commªd +:: +MAX +; + +99 ( +S‹ +:: +AùPow”Down +):  +Commªd +:: +PDX +; + +100 ( +S‹ +:: +P»Pow”Down +):  +Commªd +:: +PDX +; + +101 ( +S‹ +:: +S–fReäesh +):  +Commªd +:: +SRX +; + +102 : + `as£¹ +( +çl£ +); + +104 +´”eq +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +DDR3 +>* +node +, Commªd +cmd +,  +id +) { + +105 ( +node +-> +¡©e +)) { + +106 ( +S‹ +:: +Clo£d +):  +Commªd +:: +ACT +; + +107 ( +S‹ +:: +O³Ãd +): + +108 ià( +node +-> +row_¡©e +. + `fšd +( +id +è!ðnode->row_¡©e. + `’d +()) + +109  +cmd +; + +110  +Commªd +:: +PRE +; + +111 : + `as£¹ +( +çl£ +); + +115 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +WR +)] =…»»q[(Lev–::Rªk)][(Commªd:: +RD +)]; + +116 +´”eq +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] =…»»q[(Lev–::Bªk)][(Commªd:: +RD +)]; + +119 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +REF +)] = [] ( +DRAM +< +DDR3 +>* +node +, Commªd +cmd +,  +id +) { + +120 autØ +bªk + : +node +-> +chžd»n +) { + +121 ià( +bªk +-> +¡©e + =ð +S‹ +:: +Clo£d +) + +123  +Commªd +:: +PREA +; + +125  +Commªd +:: +REF +;}; + +128 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PDE +)] = [] ( +DRAM +< +DDR3 +>* +node +, Commªd +cmd +,  +id +) { + +129 ( +node +-> +¡©e +)) { + +130 ( +S‹ +:: +Pow”Up +):  +Commªd +:: +PDE +; + +131 ( +S‹ +:: +AùPow”Down +):  +Commªd +:: +PDE +; + +132 ( +S‹ +:: +P»Pow”Down +):  +Commªd +:: +PDE +; + +133 ( +S‹ +:: +S–fReäesh +):  +Commªd +:: +SRX +; + +134 : + `as£¹ +( +çl£ +); + +138 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +SRE +)] = [] ( +DRAM +< +DDR3 +>* +node +, Commªd +cmd +,  +id +) { + +139 ( +node +-> +¡©e +)) { + +140 ( +S‹ +:: +Pow”Up +):  +Commªd +:: +SRE +; + +141 ( +S‹ +:: +AùPow”Down +):  +Commªd +:: +PDX +; + +142 ( +S‹ +:: +P»Pow”Down +):  +Commªd +:: +PDX +; + +143 ( +S‹ +:: +S–fReäesh +):  +Commªd +:: +SRE +; + +144 : + `as£¹ +( +çl£ +); + +146 + } +} + +150  + gDDR3 +:: + $š™_rowh™ +() + +153 +rowh™ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +DDR3 +>* +node +, Commªd +cmd +,  +id +) { + +154 ( +node +-> +¡©e +)) { + +155 ( +S‹ +:: +Clo£d +):  +çl£ +; + +156 ( +S‹ +:: +O³Ãd +): + +157 ià( +node +-> +row_¡©e +. + `fšd +( +id +è!ðnode->row_¡©e. + `’d +()) + +158  +Œue +; + +159  +çl£ +; + +160 : + `as£¹ +( +çl£ +); + +164 +rowh™ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] =„owh™[(Lev–::Bªk)][(Commªd:: +RD +)]; + +165 + } +} + +167  + gDDR3 +:: + $š™_rowÝ’ +() + +170 +rowÝ’ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +DDR3 +>* +node +, Commªd +cmd +,  +id +) { + +171 ( +node +-> +¡©e +)) { + +172 ( +S‹ +:: +Clo£d +):  +çl£ +; + +173 ( +S‹ +:: +O³Ãd +):  +Œue +; + +174 : + `as£¹ +( +çl£ +); + +178 +rowÝ’ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] =„owÝ’[(Lev–::Bªk)][(Commªd:: +RD +)]; + +179 + } +} + +181  + gDDR3 +:: + $š™_Ïmbda +() + +183 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +ACT +)] = [] ( +DRAM +< +DDR3 +>* +node +,  +id +) { + +184 +node +-> +¡©e + = +S‹ +:: +O³Ãd +; + +185 +node +-> +row_¡©e +[ +id +] = +S‹ +:: +O³Ãd +;}; + +186 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +PRE +)] = [] ( +DRAM +< +DDR3 +>* +node +,  +id +) { + +187 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +188 +node +-> +row_¡©e +. + `þ—r +();}; + +189 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PREA +)] = [] ( +DRAM +< +DDR3 +>* +node +,  +id +) { + +190 autØ +bªk + : +node +-> +chžd»n +) { + +191 +bªk +-> +¡©e + = +S‹ +:: +Clo£d +; + +192 +bªk +-> +row_¡©e +. + `þ—r +();}}; + +193 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +REF +)] = [] ( +DRAM +< +DDR3 +>* +node +,  +id +) {}; + +194 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +DDR3 +>* +node +,  +id +) {}; + +195 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] = [] ( +DRAM +< +DDR3 +>* +node +,  +id +) {}; + +196 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RDA +)] = [] ( +DRAM +< +DDR3 +>* +node +,  +id +) { + +197 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +198 +node +-> +row_¡©e +. + `þ—r +();}; + +199 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WRA +)] = [] ( +DRAM +< +DDR3 +>* +node +,  +id +) { + +200 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +201 +node +-> +row_¡©e +. + `þ—r +();}; + +202 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PDE +)] = [] ( +DRAM +< +DDR3 +>* +node +,  +id +) { + +203 autØ +bªk + : +node +-> +chžd»n +) { + +204 ià( +bªk +-> +¡©e + =ð +S‹ +:: +Clo£d +) + +206 +node +-> +¡©e + = +S‹ +:: +AùPow”Down +; + +209 +node +-> +¡©e + = +S‹ +:: +P»Pow”Down +;}; + +210 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PDX +)] = [] ( +DRAM +< +DDR3 +>* +node +,  +id +) { + +211 +node +-> +¡©e + = +S‹ +:: +Pow”Up +;}; + +212 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +SRE +)] = [] ( +DRAM +< +DDR3 +>* +node +,  +id +) { + +213 +node +-> +¡©e + = +S‹ +:: +S–fReäesh +;}; + +214 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +SRX +)] = [] ( +DRAM +< +DDR3 +>* +node +,  +id +) { + +215 +node +-> +¡©e + = +S‹ +:: +Pow”Up +;}; + +216 + } +} + +219  + gDDR3 +:: + $š™_timšg +() + +221 +S³edEÁry +& +s + = +¥“d_’Œy +; + +222 +veùÜ +< +TimšgEÁry +> * +t +; + +225 +t + = +timšg +[( +Lev– +:: +ChªÃl +)]; + +228 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nBL +}); + +229 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nBL +}); + +230 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nBL +}); + +231 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd::RDA, 1, +s +. +nBL +}); + +232 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd::WR, 1, +s +. +nBL +}); + +233 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nBL +}); + +234 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nBL +}); + +235 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd::WRA, 1, +s +. +nBL +}); + +239 +t + = +timšg +[( +Lev– +:: +Rªk +)]; + +242 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nCCD +}); + +243 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCCD +}); + +244 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCCD +}); + +245 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd::RDA, 1, +s +. +nCCD +}); + +246 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd::WR, 1, +s +. +nCCD +}); + +247 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCCD +}); + +248 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCCD +}); + +249 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd::WRA, 1, +s +. +nCCD +}); + +250 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nCCD + + 2 - s. +nCWL +}); + +251 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCL + + s. +nCCD + + 2 - s. +nCWL +}); + +252 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nCCD + + 2 - s. +nCWL +}); + +253 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCL + + s. +nCCD + + 2 - s. +nCWL +}); + +254 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTR +}); + +255 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTR +}); + +256 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTR +}); + +257 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTR +}); + +260 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +261 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +262 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +263 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd::RDA, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +264 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +265 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +266 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +267 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +268 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nBL + + s. +nRTRS + - s. +nCWL +, +Œue +}); + +269 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCL + + s. +nBL + + s. +nRTRS + - s. +nCWL +, +Œue +}); + +270 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nBL + + s. +nRTRS + - s. +nCWL +, +Œue +}); + +271 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCL + + s. +nBL + + s. +nRTRS + - s. +nCWL +, +Œue +}); + +272 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nRTRS + - s. +nCL +, +Œue +}); + +273 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nRTRS + - s. +nCL +, +Œue +}); + +274 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nRTRS + - s. +nCL +, +Œue +}); + +275 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nRTRS + - s. +nCL +, +Œue +}); + +277 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PREA +, 1, +s +. +nRTP +}); + +278 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PREA +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +}); + +281 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nCL + + s. +nBL + + 1}); + +282 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nCL + + s. +nBL + + 1}); + +283 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +}); + +284 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR + + 1}); + +285 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nXP +}); + +286 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nXP +}); + +287 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nXP +}); + +288 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nXP +}); + +293 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 1, +s +. +nRRD +}); + +294 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 4, +s +. +nFAW +}); + +295 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PREA +, 1, +s +. +nRAS +}); + +296 +t +[( +Commªd +:: +PREA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRP +}); + +299 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nRP +}); + +300 +t +[( +Commªd +:: +PREA +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nRP +}); + +301 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRFC +}); + +304 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PDE +, 1, 1}); + +305 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nXP +}); + +306 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nXP +}); + +307 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PREA +, 1, +s +. +nXP +}); + +310 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nRP +}); + +311 +t +[( +Commªd +:: +PREA +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nRP +}); + +312 +t +[( +Commªd +:: +SRX +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nXS +}); + +315 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd::REF, 1, +s +. +nRFC +}); + +318 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd:: +PDE +, 1, 1}); + +319 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nXP +}); + +322 +t +[( +Commªd +:: +SRX +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nXS +}); + +325 +t +[( +Commªd +:: +PDE +)]. + `push_back +({Commªd:: +PDX +, 1, +s +. +nPD +}); + +326 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nXP +}); + +329 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nXP +}); + +330 +t +[( +Commªd +:: +SRX +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nXS +}); + +333 +t +[( +Commªd +:: +SRE +)]. + `push_back +({Commªd:: +SRX +, 1, +s +. +nCKESR +}); + +334 +t +[( +Commªd +:: +SRX +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nXS +}); + +338 +t + = +timšg +[( +Lev– +:: +Bªk +)]; + +341 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nRCD +}); + +342 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nRCD +}); + +343 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nRCD +}); + +344 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nRCD +}); + +346 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nRTP +}); + +347 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +}); + +349 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRTP + + s. +nRP +}); + +350 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR + + s. +nRP +}); + +353 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 1, +s +. +nRC +}); + +354 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nRAS +}); + +355 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRP +}); + +356 + } +} + + @DDR3.h + +1 #iâdeà +__DDR3_H + + +2  + #__DDR3_H + + + ) + +4  + ~"DRAM.h +" + +5  + ~"Reque¡.h +" + +6  + ~ + +7  + ~ + +8  + ~<¡ršg +> + +9  + ~ + +11 +usšg + +Çme¥aû + + g¡d +; + +13 +Çme¥aû + + g¿muÏtÜ + + +16 þas  + cDDR3 + + +18 + gpublic +: + +19  +¡ršg + +¡ªd¬d_Çme +; + +20 +þass + + gOrg +; + +21 +þass + + gS³ed +; + +22 +DDR3 +( +Org + +Üg +, +S³ed + +¥“d +); + +23 +DDR3 +(cÚ¡ +¡ršg +& +Üg_¡r +, cÚ¡ sŒšg& +¥“d_¡r +); + +25  + gm­ +< + g¡ršg +, + gOrg +> + gÜg_m­ +; + +26  + gm­ +< + g¡ršg +, + gS³ed +> + g¥“d_m­ +; + +28 þas  + cLev– + :  + +30 +ChªÃl +, + gRªk +, + gBªk +, + gRow +, + gCÞumn +, + gMAX + + +34 þas  + cCommªd + :  + +36 +ACT +, + gPRE +, + gPREA +, + +37 + gRD +, + gWR +, + gRDA +, + gWRA +, + +38 + gREF +, + gPDE +, + gPDX +, + gSRE +, + gSRX +, + +39 + gMAX + + +42 +¡ršg + + gcommªd_Çme +[( +Commªd +:: +MAX +)] = { + +48 +Lev– + + gscÝe +[( +Commªd +:: +MAX +)] = { + +49 +Lev– +:: +Row +, Lev–:: +Bªk +, Lev–:: +Rªk +, + +50 +Lev– +:: +CÞumn +, Level::Column, Level::Column, Level::Column, + +51 +Lev– +:: +Rªk +, Level::Rank, Level::Rank, Level::Rank, Level::Rank + +54 +boÞ + +is_Ý’šg +( +Commªd + +cmd +) + +56 ( + gcmd +)) { + +57 ( + gCommªd +:: +ACT +): + +58  +Œue +; + +60  +çl£ +; + +64 +boÞ + +is_acûssšg +( +Commªd + +cmd +) + +66 ( + gcmd +)) { + +67 ( + gCommªd +:: +RD +): + +68 ( +Commªd +:: +WR +): + +69 ( +Commªd +:: +RDA +): + +70 ( +Commªd +:: +WRA +): + +71  +Œue +; + +73  +çl£ +; + +77 +boÞ + +is_þosšg +( +Commªd + +cmd +) + +79 ( + gcmd +)) { + +80 ( + gCommªd +:: +RDA +): + +81 ( +Commªd +:: +WRA +): + +82 ( +Commªd +:: +PRE +): + +83 ( +Commªd +:: +PREA +): + +84  +Œue +; + +86  +çl£ +; + +90 +boÞ + +is_»äeshšg +( +Commªd + +cmd +) + +92 ( + gcmd +)) { + +93 ( + gCommªd +:: +REF +): + +94  +Œue +; + +96  +çl£ +; + +102 þas  + cS‹ + :  + +104 +O³Ãd +, + gClo£d +, + gPow”Up +, + gAùPow”Down +, + gP»Pow”Down +, + gS–fReäesh +, + gMAX + + +105 } + g¡¬t +[( +Lev– +:: +MAX +)] = { + +106 +S‹ +:: +MAX +, S‹:: +Pow”Up +, S‹:: +Clo£d +, State::Closed, State::MAX + +110 +Commªd + + gŒª¦©e +[( +Reque¡ +:: +Ty³ +:: +MAX +)] = { + +111 +Commªd +:: +RD +, Commªd:: +WR +, + +112 +Commªd +:: +REF +, Commªd:: +PDE +, Commªd:: +SRE + + +116 + gfunùiÚ +< +Commªd +( +DRAM +< +DDR3 +>*, Commªd +cmd +, )> + g´”eq +[( +Lev– +:: +MAX +)][(Command::MAX)]; + +120 + gfunùiÚ +< +boÞ +( +DRAM +< +DDR3 +>*, +Commªd + +cmd +, )> + growh™ +[( +Lev– +:: +MAX +)][(Command::MAX)]; + +121 + gfunùiÚ +< +boÞ +( +DRAM +< +DDR3 +>*, +Commªd + +cmd +, )> + growÝ’ +[( +Lev– +:: +MAX +)][(Command::MAX)]; + +124  + sTimšgEÁry + + +126 +Commªd + + gcmd +; + +127  + gdi¡ +; + +128  + gv® +; + +129 +boÞ + + gsiblšg +; + +131 + gveùÜ +< + gTimšgEÁry +> + gtimšg +[( +Lev– +:: +MAX +)][( +Commªd +::MAX)]; + +134 + gfunùiÚ +<( + gDRAM +< + gDDR3 +>*, )> + gÏmbda +[( +Lev– +:: +MAX +)][( +Commªd +::MAX)]; + +137 þas  + cOrg + :  + +139 +DDR3_512Mb_x4 +, + gDDR3_512Mb_x8 +, + gDDR3_512Mb_x16 +, + +140 + gDDR3_1Gb_x4 +, + gDDR3_1Gb_x8 +, + gDDR3_1Gb_x16 +, + +141 + gDDR3_2Gb_x4 +, + gDDR3_2Gb_x8 +, + gDDR3_2Gb_x16 +, + +142 + gDDR3_4Gb_x4 +, + gDDR3_4Gb_x8 +, + gDDR3_4Gb_x16 +, + +143 + gDDR3_8Gb_x4 +, + gDDR3_8Gb_x8 +, + gDDR3_8Gb_x16 +, + +144 + gMAX + + +147  + sOrgEÁry + { + +148  + gsize +; + +149  + gdq +; + +150  + gcouÁ +[( +Lev– +:: +MAX +)]; + +151 } + gÜg_bË +[( +Org +:: +MAX +)] = { + +157 }, + gÜg_’Œy +; + +159  +£t_chªÃl_numb” +( +chªÃl +); + +160  +£t_¿nk_numb” +( +¿nk +); + +163 þas  + cS³ed + :  + +165 +DDR3_800D +, + gDDR3_800E +, + +166 + gDDR3_1066E +, + gDDR3_1066F +, + gDDR3_1066G +, + +167 + gDDR3_1333G +, + gDDR3_1333H +, + +168 + gDDR3_1600H +, + gDDR3_1600J +, + gDDR3_1600K +, + +169 + gDDR3_1866K +, + gDDR3_1866L +, + +170 + gDDR3_2133L +, + gDDR3_2133M +, + +171 + gMAX + + +174  + g´eãtch_size + = 8; + +175  + gchªÃl_width + = 64; + +177  + sS³edEÁry + { + +178  + g¿‹ +; + +179  + gäeq +, + gtCK +; + +180  + gnBL +, + gnCCD +, + gnRTRS +; + +181  + gnCL +, + gnRCD +, + gnRP +, + gnCWL +; + +182  + gnRAS +, + gnRC +; + +183  + gnRTP +, + gnWTR +, + gnWR +; + +184  + gnRRD +, + gnFAW +; + +185  + gnRFC +, + gnREFI +; + +186  + gnPD +, + gnXP +, + gnXPDLL +; + +187  + gnCKESR +, + gnXS +, + gnXSDLL +; + +188 } + g¥“d_bË +[( +S³ed +:: +MAX +)] = { + +203 }, + g¥“d_’Œy +; + +205  + g»ad_Ï‹ncy +; + +207 + g´iv©e +: + +208  +š™_¥“d +(); + +209  +š™_Ïmbda +(); + +210  +š™_´”eq +(); + +211  +š™_rowh™ +(); + +212  +š™_rowÝ’ +(); + +213  +š™_timšg +(); + + @DDR4.cpp + +1  + ~"DDR4.h +" + +2  + ~"DRAM.h +" + +4  + ~ + +5  + ~ + +6  + ~<ÿs£¹ +> + +8 +usšg + +Çme¥aû + + g¡d +; + +9 +usšg + +Çme¥aû + + g¿muÏtÜ +; + +11 +¡ršg + + gDDR4 +:: +¡ªd¬d_Çme + = "DDR4"; + +13 + gm­ +< + g¡ršg +, + gDDR4 +:: +Org +> +DDR4 +:: +Üg_m­ + = { + +14 {"DDR4_2Gb_x4", +DDR4 +:: +Org +:: +DDR4_2Gb_x4 +}, {"DDR4_2Gb_x8", DDR4::Org:: +DDR4_2Gb_x8 +}, {"DDR4_2Gb_x16", DDR4::Org:: +DDR4_2Gb_x16 +}, + +15 {"DDR4_4Gb_x4", +DDR4 +:: +Org +:: +DDR4_4Gb_x4 +}, {"DDR4_4Gb_x8", DDR4::Org:: +DDR4_4Gb_x8 +}, {"DDR4_4Gb_x16", DDR4::Org:: +DDR4_4Gb_x16 +}, + +16 {"DDR4_8Gb_x4", +DDR4 +:: +Org +:: +DDR4_8Gb_x4 +}, {"DDR4_8Gb_x8", DDR4::Org:: +DDR4_8Gb_x8 +}, {"DDR4_8Gb_x16", DDR4::Org:: +DDR4_8Gb_x16 +}, + +19 + gm­ +< + g¡ršg +, + gDDR4 +:: +S³ed +> +DDR4 +:: +¥“d_m­ + = { + +20 {"DDR4_1600K", +DDR4 +:: +S³ed +:: +DDR4_1600K +}, {"DDR4_1600L", DDR4::S³ed:: +DDR4_1600L +}, + +21 {"DDR4_1866M", +DDR4 +:: +S³ed +:: +DDR4_1866M +}, {"DDR4_1866N", DDR4::S³ed:: +DDR4_1866N +}, + +22 {"DDR4_2133P", +DDR4 +:: +S³ed +:: +DDR4_2133P +}, {"DDR4_2133R", DDR4::S³ed:: +DDR4_2133R +}, + +23 {"DDR4_2400R", +DDR4 +:: +S³ed +:: +DDR4_2400R +}, {"DDR4_2400U", DDR4::S³ed:: +DDR4_2400U +}, + +27 + gDDR4 +:: + $DDR4 +( +Org + +Üg +, +S³ed + +¥“d +) + +28 : + `Üg_’Œy +( +Üg_bË +[( +Üg +)]), + +29 + `¥“d_’Œy +( +¥“d_bË +[( +¥“d +)]), + +30 + `»ad_Ï‹ncy +( +¥“d_’Œy +. +nCL + + s³ed_’Œy. +nBL +) + +32 + `š™_¥“d +(); + +33 + `š™_´”eq +(); + +34 + `š™_rowh™ +(); + +35 + `š™_rowÝ’ +(); + +36 + `š™_Ïmbda +(); + +37 + `š™_timšg +(); + +38 + } +} + +40 + gDDR4 +:: + $DDR4 +(cÚ¡ +¡ršg +& +Üg_¡r +, cÚ¡ sŒšg& +¥“d_¡r +) : + +41 + $DDR4 +( +Üg_m­ +[ +Üg_¡r +], +¥“d_m­ +[ +¥“d_¡r +]) + +43 + } +} + +45  + gDDR4 +:: + $£t_chªÃl_numb” +( +chªÃl +) { + +46 +Üg_’Œy +. +couÁ +[( +Lev– +:: +ChªÃl +)] = +chªÃl +; + +47 + } +} + +49  + gDDR4 +:: + $£t_¿nk_numb” +( +¿nk +) { + +50 +Üg_’Œy +. +couÁ +[( +Lev– +:: +Rªk +)] = +¿nk +; + +51 + } +} + +53  + gDDR4 +:: + $š™_¥“d +() + +55 cÚ¡  +RRDS_TABLE +[2][4] = { + +59 cÚ¡  +RRDL_TABLE +[2][4] = { + +63 cÚ¡  +FAW_TABLE +[3][4] = { + +68 cÚ¡  +RFC_TABLE +[( +ReäeshMode +:: +MAX +)][3][4] = {{ + +82 cÚ¡  +REFI_TABLE +[4] = { + +85 cÚ¡  +XS_TABLE +[3][4] = { + +91  +¥“d + = 0, +d’s™y + = 0; + +92  +¥“d_’Œy +. +¿‹ +) { + +93 1600: +¥“d + = 0; ; + +94 1866: +¥“d + = 1; ; + +95 2133: +¥“d + = 2; ; + +96 2400: +¥“d + = 3; ; + +97 : + `as£¹ +( +çl£ +); + +99  +Üg_’Œy +. +size + >> 10){ + +100 2: +d’s™y + = 0; ; + +101 4: +d’s™y + = 1; ; + +102 8: +d’s™y + = 2; ; + +103 : + `as£¹ +( +çl£ +); + +105 +¥“d_’Œy +. +nRRDS + = +RRDS_TABLE +[ +Üg_’Œy +. +dq + =ð16? 1: 0][ +¥“d +]; + +106 +¥“d_’Œy +. +nRRDL + = +RRDL_TABLE +[ +Üg_’Œy +. +dq + =ð16? 1: 0][ +¥“d +]; + +107 +¥“d_’Œy +. +nFAW + = +FAW_TABLE +[ +Üg_’Œy +. +dq + =ð4? 0: org_’Œy.dq =ð8? 1: 2][ +¥“d +]; + +108 +¥“d_’Œy +. +nRFC + = +RFC_TABLE +[() +»äesh_mode +][ +d’s™y +][ +¥“d +]; + +109 +¥“d_’Œy +. +nREFI + = ( +REFI_TABLE +[ +¥“d +] >> ( +»äesh_mode +)); + +110 +¥“d_’Œy +. +nXS + = +XS_TABLE +[ +d’s™y +][ +¥“d +]; + +111 + } +} + +114  + gDDR4 +:: + $š™_´”eq +() + +117 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +DDR4 +>* +node +, Commªd +cmd +,  +id +) { + +118 ( +node +-> +¡©e +)) { + +119 ( +S‹ +:: +Pow”Up +):  +Commªd +:: +MAX +; + +120 ( +S‹ +:: +AùPow”Down +):  +Commªd +:: +PDX +; + +121 ( +S‹ +:: +P»Pow”Down +):  +Commªd +:: +PDX +; + +122 ( +S‹ +:: +S–fReäesh +):  +Commªd +:: +SRX +; + +123 : + `as£¹ +( +çl£ +); + +125 +´”eq +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +DDR4 +>* +node +, Commªd +cmd +,  +id +) { + +126 ( +node +-> +¡©e +)) { + +127 ( +S‹ +:: +Clo£d +):  +Commªd +:: +ACT +; + +128 ( +S‹ +:: +O³Ãd +): + +129 ià( +node +-> +row_¡©e +. + `fšd +( +id +è!ðnode->row_¡©e. + `’d +()) + +130  +cmd +; + +131  +Commªd +:: +PRE +; + +132 : + `as£¹ +( +çl£ +); + +136 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +WR +)] =…»»q[(Lev–::Rªk)][(Commªd:: +RD +)]; + +137 +´”eq +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] =…»»q[(Lev–::Bªk)][(Commªd:: +RD +)]; + +140 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +REF +)] = [] ( +DRAM +< +DDR4 +>* +node +, Commªd +cmd +,  +id +) { + +141 autØ +bg + : +node +-> +chžd»n +) + +142 autØ +bªk +: +bg +-> +chžd»n +) { + +143 ià( +bªk +-> +¡©e + =ð +S‹ +:: +Clo£d +) + +145  +Commªd +:: +PREA +; + +147  +Commªd +:: +REF +;}; + +150 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PDE +)] = [] ( +DRAM +< +DDR4 +>* +node +, Commªd +cmd +,  +id +) { + +151 ( +node +-> +¡©e +)) { + +152 ( +S‹ +:: +Pow”Up +):  +Commªd +:: +PDE +; + +153 ( +S‹ +:: +AùPow”Down +):  +Commªd +:: +PDE +; + +154 ( +S‹ +:: +P»Pow”Down +):  +Commªd +:: +PDE +; + +155 ( +S‹ +:: +S–fReäesh +):  +Commªd +:: +SRX +; + +156 : + `as£¹ +( +çl£ +); + +160 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +SRE +)] = [] ( +DRAM +< +DDR4 +>* +node +, Commªd +cmd +,  +id +) { + +161 ( +node +-> +¡©e +)) { + +162 ( +S‹ +:: +Pow”Up +):  +Commªd +:: +SRE +; + +163 ( +S‹ +:: +AùPow”Down +):  +Commªd +:: +PDX +; + +164 ( +S‹ +:: +P»Pow”Down +):  +Commªd +:: +PDX +; + +165 ( +S‹ +:: +S–fReäesh +):  +Commªd +:: +SRE +; + +166 : + `as£¹ +( +çl£ +); + +168 + } +} + +171  + gDDR4 +:: + $š™_rowh™ +() + +174 +rowh™ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +DDR4 +>* +node +, Commªd +cmd +,  +id +) { + +175 ( +node +-> +¡©e +)) { + +176 ( +S‹ +:: +Clo£d +):  +çl£ +; + +177 ( +S‹ +:: +O³Ãd +): + +178 ià( +node +-> +row_¡©e +. + `fšd +( +id +è!ðnode->row_¡©e. + `’d +()) + +179  +Œue +; + +180  +çl£ +; + +181 : + `as£¹ +( +çl£ +); + +185 +rowh™ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] =„owh™[(Lev–::Bªk)][(Commªd:: +RD +)]; + +186 + } +} + +188  + gDDR4 +:: + $š™_rowÝ’ +() + +191 +rowÝ’ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +DDR4 +>* +node +, Commªd +cmd +,  +id +) { + +192 ( +node +-> +¡©e +)) { + +193 ( +S‹ +:: +Clo£d +):  +çl£ +; + +194 ( +S‹ +:: +O³Ãd +):  +Œue +; + +195 : + `as£¹ +( +çl£ +); + +199 +rowÝ’ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] =„owÝ’[(Lev–::Bªk)][(Commªd:: +RD +)]; + +200 + } +} + +202  + gDDR4 +:: + $š™_Ïmbda +() + +204 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +ACT +)] = [] ( +DRAM +< +DDR4 +>* +node +,  +id +) { + +205 +node +-> +¡©e + = +S‹ +:: +O³Ãd +; + +206 +node +-> +row_¡©e +[ +id +] = +S‹ +:: +O³Ãd +;}; + +207 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +PRE +)] = [] ( +DRAM +< +DDR4 +>* +node +,  +id +) { + +208 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +209 +node +-> +row_¡©e +. + `þ—r +();}; + +210 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PREA +)] = [] ( +DRAM +< +DDR4 +>* +node +,  +id +) { + +211 autØ +bg + : +node +-> +chžd»n +) + +212 autØ +bªk + : +bg +-> +chžd»n +) { + +213 +bªk +-> +¡©e + = +S‹ +:: +Clo£d +; + +214 +bªk +-> +row_¡©e +. + `þ—r +(); + +216 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +REF +)] = [] ( +DRAM +< +DDR4 +>* +node +,  +id +) {}; + +217 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +DDR4 +>* +node +,  +id +) {}; + +218 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] = [] ( +DRAM +< +DDR4 +>* +node +,  +id +) {}; + +219 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RDA +)] = [] ( +DRAM +< +DDR4 +>* +node +,  +id +) { + +220 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +221 +node +-> +row_¡©e +. + `þ—r +();}; + +222 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WRA +)] = [] ( +DRAM +< +DDR4 +>* +node +,  +id +) { + +223 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +224 +node +-> +row_¡©e +. + `þ—r +();}; + +225 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PDE +)] = [] ( +DRAM +< +DDR4 +>* +node +,  +id +) { + +226 autØ +bg + : +node +-> +chžd»n +) + +227 autØ +bªk + : +bg +-> +chžd»n +) { + +228 ià( +bªk +-> +¡©e + =ð +S‹ +:: +Clo£d +) + +230 +node +-> +¡©e + = +S‹ +:: +AùPow”Down +; + +233 +node +-> +¡©e + = +S‹ +:: +P»Pow”Down +;}; + +234 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PDX +)] = [] ( +DRAM +< +DDR4 +>* +node +,  +id +) { + +235 +node +-> +¡©e + = +S‹ +:: +Pow”Up +;}; + +236 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +SRE +)] = [] ( +DRAM +< +DDR4 +>* +node +,  +id +) { + +237 +node +-> +¡©e + = +S‹ +:: +S–fReäesh +;}; + +238 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +SRX +)] = [] ( +DRAM +< +DDR4 +>* +node +,  +id +) { + +239 +node +-> +¡©e + = +S‹ +:: +Pow”Up +;}; + +240 + } +} + +243  + gDDR4 +:: + $š™_timšg +() + +245 +S³edEÁry +& +s + = +¥“d_’Œy +; + +246 +veùÜ +< +TimšgEÁry +> * +t +; + +249 +t + = +timšg +[( +Lev– +:: +ChªÃl +)]; + +252 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nBL +}); + +253 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nBL +}); + +254 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nBL +}); + +255 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd::RDA, 1, +s +. +nBL +}); + +256 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd::WR, 1, +s +. +nBL +}); + +257 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nBL +}); + +258 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nBL +}); + +259 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd::WRA, 1, +s +. +nBL +}); + +263 +t + = +timšg +[( +Lev– +:: +Rªk +)]; + +266 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nCCDS +}); + +267 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCCDS +}); + +268 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCCDS +}); + +269 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd::RDA, 1, +s +. +nCCDS +}); + +270 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd::WR, 1, +s +. +nCCDS +}); + +271 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCCDS +}); + +272 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCCDS +}); + +273 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd::WRA, 1, +s +. +nCCDS +}); + +274 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nCCDS + + 2 - s. +nCWL +}); + +275 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCL + + s. +nCCDS + + 2 - s. +nCWL +}); + +276 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nCCDS + + 2 - s. +nCWL +}); + +277 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCL + + s. +nCCDS + + 2 - s. +nCWL +}); + +278 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTRS +}); + +279 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTRS +}); + +280 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTRS +}); + +281 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTRS +}); + +284 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +285 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +286 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +287 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd::RDA, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +288 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +289 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +290 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +291 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +292 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nBL + + s. +nRTRS + - s. +nCWL +, +Œue +}); + +293 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCL + + s. +nBL + + s. +nRTRS + - s. +nCWL +, +Œue +}); + +294 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nBL + + s. +nRTRS + - s. +nCWL +, +Œue +}); + +295 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCL + + s. +nBL + + s. +nRTRS + - s. +nCWL +, +Œue +}); + +296 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nRTRS + - s. +nCL +, +Œue +}); + +297 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nRTRS + - s. +nCL +, +Œue +}); + +298 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nRTRS + - s. +nCL +, +Œue +}); + +299 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nRTRS + - s. +nCL +, +Œue +}); + +301 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PREA +, 1, +s +. +nRTP +}); + +302 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PREA +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +}); + +305 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nCL + + s. +nBL + + 1}); + +306 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nCL + + s. +nBL + + 1}); + +307 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +}); + +308 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR + + 1}); + +309 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nXP +}); + +310 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nXP +}); + +311 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nXP +}); + +312 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nXP +}); + +317 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 1, +s +. +nRRDS +}); + +318 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 4, +s +. +nFAW +}); + +319 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PREA +, 1, +s +. +nRAS +}); + +320 +t +[( +Commªd +:: +PREA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRP +}); + +323 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nRP +}); + +324 +t +[( +Commªd +:: +PREA +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nRP +}); + +325 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRFC +}); + +328 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PDE +, 1, 1}); + +329 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nXP +}); + +330 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nXP +}); + +331 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PREA +, 1, +s +. +nXP +}); + +334 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nRP +}); + +335 +t +[( +Commªd +:: +PREA +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nRP +}); + +336 +t +[( +Commªd +:: +SRX +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nXS +}); + +339 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd::REF, 1, +s +. +nRFC +}); + +342 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd:: +PDE +, 1, 1}); + +343 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nXP +}); + +346 +t +[( +Commªd +:: +SRX +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nXS +}); + +349 +t +[( +Commªd +:: +PDE +)]. + `push_back +({Commªd:: +PDX +, 1, +s +. +nPD +}); + +350 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nXP +}); + +353 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nXP +}); + +354 +t +[( +Commªd +:: +SRX +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nXS +}); + +357 +t +[( +Commªd +:: +SRE +)]. + `push_back +({Commªd:: +SRX +, 1, +s +. +nCKESR +}); + +358 +t +[( +Commªd +:: +SRX +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nXS +}); + +361 +t + = +timšg +[( +Lev– +:: +BªkGroup +)]; + +363 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nCCDL +}); + +364 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCCDL +}); + +365 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCCDL +}); + +366 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd::RDA, 1, +s +. +nCCDL +}); + +367 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd::WR, 1, +s +. +nCCDL +}); + +368 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCCDL +}); + +369 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCCDL +}); + +370 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd::WRA, 1, +s +. +nCCDL +}); + +371 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd::WR, 1, +s +. +nCCDL +}); + +372 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCCDL +}); + +373 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCCDL +}); + +374 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd::WRA, 1, +s +. +nCCDL +}); + +375 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTRL +}); + +376 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTRL +}); + +377 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTRL +}); + +378 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTRL +}); + +381 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 1, +s +. +nRRDL +}); + +384 +t + = +timšg +[( +Lev– +:: +Bªk +)]; + +387 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nRCD +}); + +388 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nRCD +}); + +389 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nRCD +}); + +390 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nRCD +}); + +392 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nRTP +}); + +393 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +}); + +395 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRTP + + s. +nRP +}); + +396 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR + + s. +nRP +}); + +399 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 1, +s +. +nRC +}); + +400 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nRAS +}); + +401 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRP +}); + +402 + } +} + + @DDR4.h + +1 #iâdeà +__DDR4_H + + +2  + #__DDR4_H + + + ) + +4  + ~"DRAM.h +" + +5  + ~"Reque¡.h +" + +6  + ~ + +7  + ~ + +9 +usšg + +Çme¥aû + + g¡d +; + +11 +Çme¥aû + + g¿muÏtÜ + + +14 þas  + cDDR4 + + +16 + gpublic +: + +17  +¡ršg + +¡ªd¬d_Çme +; + +18 +þass + + gOrg +; + +19 +þass + + gS³ed +; + +20 +DDR4 +( +Org + +Üg +, +S³ed + +¥“d +); + +21 +DDR4 +(cÚ¡ +¡ršg +& +Üg_¡r +, cÚ¡ sŒšg& +¥“d_¡r +); + +23  + gm­ +< + g¡ršg +, + gOrg +> + gÜg_m­ +; + +24  + gm­ +< + g¡ršg +, + gS³ed +> + g¥“d_m­ +; + +26 þas  + cLev– + :  + +28 +ChªÃl +, + gRªk +, + gBªkGroup +, + gBªk +, + gRow +, + gCÞumn +, + gMAX + + +32 þas  + cCommªd + :  + +34 +ACT +, + gPRE +, + gPREA +, + +35 + gRD +, + gWR +, + gRDA +, + gWRA +, + +36 + gREF +, + gPDE +, + gPDX +, + gSRE +, + gSRX +, + +37 + gMAX + + +40 +¡ršg + + gcommªd_Çme +[( +Commªd +:: +MAX +)] = { + +46 +Lev– + + gscÝe +[( +Commªd +:: +MAX +)] = { + +47 +Lev– +:: +Row +, Lev–:: +Bªk +, Lev–:: +Rªk +, + +48 +Lev– +:: +CÞumn +, Level::Column, Level::Column, Level::Column, + +49 +Lev– +:: +Rªk +, Level::Rank, Level::Rank, Level::Rank, Level::Rank + +52 +boÞ + +is_Ý’šg +( +Commªd + +cmd +) + +54 ( + gcmd +)) { + +55 ( + gCommªd +:: +ACT +): + +56  +Œue +; + +58  +çl£ +; + +62 +boÞ + +is_acûssšg +( +Commªd + +cmd +) + +64 ( + gcmd +)) { + +65 ( + gCommªd +:: +RD +): + +66 ( +Commªd +:: +WR +): + +67 ( +Commªd +:: +RDA +): + +68 ( +Commªd +:: +WRA +): + +69  +Œue +; + +71  +çl£ +; + +75 +boÞ + +is_þosšg +( +Commªd + +cmd +) + +77 ( + gcmd +)) { + +78 ( + gCommªd +:: +RDA +): + +79 ( +Commªd +:: +WRA +): + +80 ( +Commªd +:: +PRE +): + +81 ( +Commªd +:: +PREA +): + +82  +Œue +; + +84  +çl£ +; + +88 +boÞ + +is_»äeshšg +( +Commªd + +cmd +) + +90 ( + gcmd +)) { + +91 ( + gCommªd +:: +REF +): + +92  +Œue +; + +94  +çl£ +; + +99 þas  + cS‹ + :  + +101 +O³Ãd +, + gClo£d +, + gPow”Up +, + gAùPow”Down +, + gP»Pow”Down +, + gS–fReäesh +, + gMAX + + +102 } + g¡¬t +[( +Lev– +:: +MAX +)] = { + +103 +S‹ +:: +MAX +, S‹:: +Pow”Up +, S‹::MAX, S‹:: +Clo£d +, State::Closed, State::MAX + +107 +Commªd + + gŒª¦©e +[( +Reque¡ +:: +Ty³ +:: +MAX +)] = { + +108 +Commªd +:: +RD +, Commªd:: +WR +, + +109 +Commªd +:: +REF +, Commªd:: +PDE +, Commªd:: +SRE + + +113 + gfunùiÚ +< +Commªd +( +DRAM +< +DDR4 +>*, Commªd +cmd +, )> + g´”eq +[( +Lev– +:: +MAX +)][(Command::MAX)]; + +117 + gfunùiÚ +< +boÞ +( +DRAM +< +DDR4 +>*, +Commªd + +cmd +, )> + growh™ +[( +Lev– +:: +MAX +)][(Command::MAX)]; + +118 + gfunùiÚ +< +boÞ +( +DRAM +< +DDR4 +>*, +Commªd + +cmd +, )> + growÝ’ +[( +Lev– +:: +MAX +)][(Command::MAX)]; + +121  + sTimšgEÁry + + +123 +Commªd + + gcmd +; + +124  + gdi¡ +; + +125  + gv® +; + +126 +boÞ + + gsiblšg +; + +128 + gveùÜ +< + gTimšgEÁry +> + gtimšg +[( +Lev– +:: +MAX +)][( +Commªd +::MAX)]; + +131 + gfunùiÚ +<( + gDRAM +< + gDDR4 +>*, )> + gÏmbda +[( +Lev– +:: +MAX +)][( +Commªd +::MAX)]; + +134 þas  + cOrg + :  + +136 +DDR4_2Gb_x4 +, + gDDR4_2Gb_x8 +, + gDDR4_2Gb_x16 +, + +137 + gDDR4_4Gb_x4 +, + gDDR4_4Gb_x8 +, + gDDR4_4Gb_x16 +, + +138 + gDDR4_8Gb_x4 +, + gDDR4_8Gb_x8 +, + gDDR4_8Gb_x16 +, + +139 + gMAX + + +142  + sOrgEÁry + { + +143  + gsize +; + +144  + gdq +; + +145  + gcouÁ +[( +Lev– +:: +MAX +)]; + +146 } + gÜg_bË +[( +Org +:: +MAX +)] = { + +150 }, + gÜg_’Œy +; + +152  +£t_chªÃl_numb” +( +chªÃl +); + +153  +£t_¿nk_numb” +( +¿nk +); + +156 þas  + cS³ed + :  + +158 +DDR4_1600K +, + gDDR4_1600L +, + +159 + gDDR4_1866M +, + gDDR4_1866N +, + +160 + gDDR4_2133P +, + gDDR4_2133R +, + +161 + gDDR4_2400R +, + gDDR4_2400U +, + +162 + gMAX + + +165 þas  + cReäeshMode + :  + +167 +Reäesh_1X +, + +168 + gReäesh_2X +, + +169 + gReäesh_4X +, + +170 + gMAX + + +171 } + g»äesh_mode + = +ReäeshMode +:: +Reäesh_1X +; + +173  + g´eãtch_size + = 8; + +174  + gchªÃl_width + = 64; + +176  + sS³edEÁry + { + +177  + g¿‹ +; + +178  + gäeq +, + gtCK +; + +179  + gnBL +, + gnCCDS +, + gnCCDL +, + gnRTRS +; + +180  + gnCL +, + gnRCD +, + gnRP +, + gnCWL +; + +181  + gnRAS +, + gnRC +; + +182  + gnRTP +, + gnWTRS +, + gnWTRL +, + gnWR +; + +183  + gnRRDS +, + gnRRDL +, + gnFAW +; + +184  + gnRFC +, + gnREFI +; + +185  + gnPD +, + gnXP +, + gnXPDLL +; + +186  + gnCKESR +, + gnXS +, + gnXSDLL +; + +187 } + g¥“d_bË +[( +S³ed +:: +MAX +)] = { + +196 }, + g¥“d_’Œy +; + +198  + g»ad_Ï‹ncy +; + +200 + g´iv©e +: + +201  +š™_¥“d +(); + +202  +š™_Ïmbda +(); + +203  +š™_´”eq +(); + +204  +š™_rowh™ +(); + +205  +š™_rowÝ’ +(); + +206  +š™_timšg +(); + + @DRAM.h + +1 #iâdeà +__DRAM_H + + +2  + #__DRAM_H + + + ) + +4  + ~"Sti¡ics.h +" + +5  + ~ + +6  + ~ + +7  + ~ + +8  + ~ + +9  + ~ + +10  + ~<®gÜ™hm +> + +11  + ~<ÿs£¹ +> + +12  + ~ + +14 +usšg + +Çme¥aû + + g¡d +; + +16 +Çme¥aû + + g¿muÏtÜ + + +19 + g‹m¶©e + < +ty³Çme + + gT +> + +20 þas  + cDRAM + + +22 + gpublic +: + +23 +SÿÏrSt + +aùive_cyþes +; + +24 +SÿÏrSt + + g»äesh_cyþes +; + +25 +SÿÏrSt + + gbusy_cyþes +; + +26 +SÿÏrSt + + gaùive_»äesh_ov”Ïp_cyþes +; + +28 +SÿÏrSt + + g£rvšg_»que¡s +; + +29 +SÿÏrSt + + gav”age_£rvšg_»que¡s +; + +32 +DRAM +( +T +* +¥ec +, +ty³Çme + T:: +Lev– + +Ëv– +); + +33 ~ +DRAM +(); + +36 +T +* + g¥ec +; + +39 +ty³Çme + + gT +:: +Lev– + +Ëv– +; + +40  + gid +; + +41  + gsize +; + +42 +DRAM +* + g·»Á +; + +43 + gveùÜ +< + gDRAM +*> + gchžd»n +; + +46 +ty³Çme + + gT +:: +S‹ + +¡©e +; + +51 + gm­ +<, +ty³Çme + + gT +:: +S‹ +> +row_¡©e +; + +54  +š£¹ +( +DRAM +< +T +>* +chžd +); + +57 +ty³Çme + + gT +:: +Commªd + +decode +Ñy³Çm +T +::Commªd +cmd +, cÚ¡ * +addr +); + +60 +boÞ + +check +( +ty³Çme + +T +:: +Commªd + +cmd +, cÚ¡ * +addr +,  +þk +); + +63 +boÞ + +check_row_h™ +( +ty³Çme + +T +:: +Commªd + +cmd +, cÚ¡ * +addr +); + +66 +boÞ + +check_row_Ý’ +( +ty³Çme + +T +:: +Commªd + +cmd +, cÚ¡ * +addr +); + +69  +g‘_Ãxt +( +ty³Çme + +T +:: +Commªd + +cmd +, cÚ¡ * +addr +); + +72  +upd©e +( +ty³Çme + +T +:: +Commªd + +cmd +, cÚ¡ * +addr +,  +þk +); + +76  +upd©e_£rvšg_»que¡s +(cÚ¡ * +addr +,  +d– +,  +þk +); + +79  + gcur_£rvšg_»que¡s + = 0; + +80  + gbegš_of_£rvšg + = -1; + +81  + g’d_of_£rvšg + = -1; + +82  + gbegš_of_cur_»qút + = -1; + +83  + gbegš_of_»äeshšg + = -1; + +84  + g’d_of_»äeshšg + = -1; + +85 + g¡d +:: +veùÜ +< +¡d +:: +·œ +<, >> + g»äesh_š‹rv®s +; + +88  +»gSts +(cÚ¡ +¡d +:: +¡ršg +& +id’tif›r +); + +90  +fšish +( +d¿m_cyþes +); + +92 + g´iv©e +: + +94 +DRAM +(){} + +97  +cur_þk + = 0; + +98  + gÃxt +[( +T +:: +Commªd +:: +MAX +)]; + +99 + gdeque +<> + g´ev +[( +T +:: +Commªd +:: +MAX +)]; + +103 + gfunùiÚ +< +ty³Çme + + gT +:: +Commªd +( +DRAM +< +T +>*,y³ÇmT::Commªd +cmd +, )>* + g´”eq +; + +108 + gfunùiÚ +< +boÞ +( +DRAM +< +T +>*, +ty³Çme + T:: +Commªd + +cmd +, )>* + growh™ +; + +109 + gfunùiÚ +< +boÞ +( +DRAM +< +T +>*, +ty³Çme + T:: +Commªd + +cmd +, )>* + growÝ’ +; + +113 + gfunùiÚ +<( + gDRAM +< + gT +>*, )>* + gÏmbda +; + +117 + gveùÜ +< +ty³Çme + + gT +:: +TimšgEÁry +>* +timšg +; + +120  +upd©e_¡©e +( +ty³Çme + +T +:: +Commªd + +cmd +, cÚ¡ * +addr +); + +121  +upd©e_timšg +( +ty³Çme + +T +:: +Commªd + +cmd +, cÚ¡ * +addr +,  +þk +); + +126 + g‹m¶©e + < +ty³Çme + + gT +> + +127  + gDRAM +< + gT +>:: + $»gSts +(cÚ¡ +¡d +:: +¡ršg +& +id’tif›r +) { + +128 +aùive_cyþes + + +129 . + `Çme +("aùive_cyþes" + +id’tif›r + + "_" + + `to_¡ršg +( +id +)) + +130 . + `desc +("TÙ®‡ùivcyþe f܆ev– " + +id’tif›r + + "_" + + `to_¡ršg +( +id +)) + +131 . + `´ecisiÚ +(0) + +133 +»äesh_cyþes + + +134 . + `Çme +("»äesh_cyþes" + +id’tif›r + + "_" + + `to_¡ršg +( +id +)) + +135 . + `desc +("(AÎ-bªk„eäesh oÆy, oÆy v®id fÜ„ªk†ev–èThsum oàcyþe th© i und”„eäesh…” memÜy cyþf܆ev– " + +id’tif›r + + "_" + + `to_¡ršg +( +id +)) + +136 . + `´ecisiÚ +(0) + +137 . + `æags +( +Sts +:: +noz”o +) + +139 +busy_cyþes + + +140 . + `Çme +("busy_cyþes" + +id’tif›r + + "_" + + `to_¡ršg +( +id +)) + +141 . + `desc +("(AÎ-bªk„eäesh oÆy. busy cyþe Úly inþud»äeshimš„ªk†ev–èThsum oàcyþe th©hDRAM…¬ˆi aùivÜ und”„eäesh f܆ev– " + +id’tif›r + + "_" + + `to_¡ršg +( +id +)) + +142 . + `´ecisiÚ +(0) + +144 +aùive_»äesh_ov”Ïp_cyþes + + +145 . + `Çme +("aùive_»äesh_ov”Ïp_cyþes" + +id’tif›r + + "_" + + `to_¡ršg +( +id +)) + +146 . + `desc +("(AÎ-bªk„eäesh oÆy, oÆy v®id fÜ„ªk†ev–èThsum oàcyþe th©‡» bÙh‡ùivªd und”„eäesh…” memÜy cyþf܆ev– " + +id’tif›r + + "_" + + `to_¡ršg +( +id +)) + +147 . + `´ecisiÚ +(0) + +148 . + `æags +( +Sts +:: +noz”o +) + +150 +£rvšg_»que¡s + + +151 . + `Çme +("£rvšg_»que¡s" + +id’tif›r + + "_" + + `to_¡ršg +( +id +)) + +152 . + `desc +("Thsum oà»ad‡nd wr™»que¡ th©‡» s”ved iÀthi DRAMƒËm’ˆ³¸memÜy cyþf܆ev– " + +id’tif›r + + "_" + + `to_¡ršg +( +id +)) + +153 . + `´ecisiÚ +(0) + +155 +av”age_£rvšg_»que¡s + + +156 . + `Çme +("av”age_£rvšg_»que¡s" + +id’tif›r + + "_" + + `to_¡ršg +( +id +)) + +157 . + `desc +("Thav”agoà»ad‡nd wr™»que¡ th©‡» s”ved iÀthi DRAMƒËm’ˆ³¸memÜy cyþf܆ev– " + +id’tif›r + + "_" + + `to_¡ršg +( +id +)) + +158 . + `´ecisiÚ +(6) + +161 ià(! +chžd»n +. + `size +()) { + +166 autØ +chžd + : +chžd»n +) { + +167 +chžd +-> + `»gSts +( +id’tif›r + + "_" + + `to_¡ršg +( +id +)); + +169 + } +} + +171 + g‹m¶©e + < +ty³Çme + + gT +> + +172  + gDRAM +< + gT +>:: + $fšish +( +d¿m_cyþes +) { + +174 +busy_cyþes + = +aùive_cyþes +. + `v®ue +(è+ +»äesh_cyþes +.v®ue(è- +aùive_»äesh_ov”Ïp_cyþes +.value(); + +177 +av”age_£rvšg_»que¡s + = +£rvšg_»que¡s +. + `v®ue +(è/ +d¿m_cyþes +; + +179 ià(! +chžd»n +. + `size +()) { + +183 autØ +chžd + : +chžd»n +) { + +184 +chžd +-> + `fšish +( +d¿m_cyþes +); + +186 + } +} + +189 + g‹m¶©e + < +ty³Çme + + gT +> + +190 + gDRAM +< + gT +>:: + $DRAM +( +T +* +¥ec +, +ty³Çme + T:: +Lev– + +Ëv– +) : + +191 + `¥ec +( +¥ec +), + `Ëv– +( +Ëv– +), + `id +(0), + $·»Á +( +NULL +) + +194 +¡©e + = +¥ec +-> +¡¬t +[() +Ëv– +]; + +195 +´”eq + = +¥ec +->´”eq[( +Ëv– +)]; + +196 +rowh™ + = +¥ec +->rowh™[( +Ëv– +)]; + +197 +rowÝ’ + = +¥ec +->rowÝ’[( +Ëv– +)]; + +198 +Ïmbda + = +¥ec +->Ïmbda[( +Ëv– +)]; + +199 +timšg + = +¥ec +->timšg[( +Ëv– +)]; + +201 + `fžl_n +( +Ãxt +, ( +T +:: +Commªd +:: +MAX +), -1); + +202  +cmd + = 0; cmd < ( +T +:: +Commªd +:: +MAX +); cmd++) { + +203  +di¡ + = 0; + +204 auto& +t + : +timšg +[ +cmd +]) + +205 +di¡ + = + `max +(di¡, +t +.dist); + +207 ià( +di¡ +) + +208 +´ev +[ +cmd +]. + `»size +( +di¡ +, -1); + +212  +chžd_Ëv– + = ( +Ëv– +) + 1; + +213 ià( +chžd_Ëv– + =ð( +T +:: +Lev– +:: +Row +)) + +216  +chžd_max + = +¥ec +-> +Üg_’Œy +. +couÁ +[ +chžd_Ëv– +]; + +217 ià(! +chžd_max +) + +221  +i + = 0; i < +chžd_max +; i++) { + +222 +DRAM +< +T +>* +chžd + = +Ãw + DRAM( +¥ec +, +ty³Çme + T:: + `Lev– +( +chžd_Ëv– +)); + +223 +chžd +-> +·»Á + = +this +; + +224 +chžd +-> +id + = +i +; + +225 +chžd»n +. + `push_back +( +chžd +); + +228 + } +} + +230 + g‹m¶©e + < +ty³Çme + + gT +> + +231 + gDRAM +< + gT +>::~ + $DRAM +() + +233 autØ +chžd +: +chžd»n +) + +234 +d–‘e + +chžd +; + +235 + } +} + +238 + g‹m¶©e + < +ty³Çme + + gT +> + +239  + gDRAM +< + gT +>:: +š£¹ +( +DRAM +< +T +>* +chžd +) + +241 +chžd +-> +·»Á + = +this +; + +242 + gchžd +-> + gid + = +chžd»n +. +size +(); + +243 + gchžd»n +. +push_back +( +chžd +); + +247 + g‹m¶©e + < +ty³Çme + + gT +> + +248 +ty³Çme + + gT +:: +Commªd + +DRAM +< +T +>:: + $decode +( +ty³Çme + +T +:: +Commªd + +cmd +, cÚ¡ * +addr +) + +250  +chžd_id + = +addr +[( +Ëv– +)+1]; + +251 ià( +´”eq +[( +cmd +)]) { + +252 +ty³Çme + +T +:: +Commªd + +´”eq_cmd + = +´”eq +[( +cmd +)]( +this +, cmd, +chžd_id +); + +253 ià( +´”eq_cmd + !ð +T +:: +Commªd +:: +MAX +) + +254  +´”eq_cmd +; + +257 ià( +chžd_id + < 0 || ! +chžd»n +. + `size +()) + +258  +cmd +; + +261  +chžd»n +[ +chžd_id +]-> + `decode +( +cmd +, +addr +); + +262 + } +} + +266 + g‹m¶©e + < +ty³Çme + + gT +> + +267 +boÞ + + gDRAM +< + gT +>:: + $check +( +ty³Çme + +T +:: +Commªd + +cmd +, cÚ¡ * +addr +,  +þk +) + +269 ià( +Ãxt +[( +cmd +)] !ð-1 && +þk + <‚ext[(cmd)]) + +270  +çl£ +; + +272  +chžd_id + = +addr +[( +Ëv– +)+1]; + +273 ià( +chžd_id + < 0 || +Ëv– + =ð +¥ec +-> +scÝe +[( +cmd +)] || ! +chžd»n +. + `size +()) + +274  +Œue +; + +277  +chžd»n +[ +chžd_id +]-> + `check +( +cmd +, +addr +, +þk +); + +278 + } +} + +282 + g‹m¶©e + < +ty³Çme + + gT +> + +283 +boÞ + + gDRAM +< + gT +>:: + $check_row_h™ +( +ty³Çme + +T +:: +Commªd + +cmd +, cÚ¡ * +addr +) + +285  +chžd_id + = +addr +[( +Ëv– +)+1]; + +286 ià( +rowh™ +[( +cmd +)]) { + +287  +rowh™ +[( +cmd +)]( +this +, cmd, +chžd_id +); + +290 ià( +chžd_id + < 0 || ! +chžd»n +. + `size +()) + +291  +çl£ +; + +294  +chžd»n +[ +chžd_id +]-> + `check_row_h™ +( +cmd +, +addr +); + +295 + } +} + +297 + g‹m¶©e + < +ty³Çme + + gT +> + +298 +boÞ + + gDRAM +< + gT +>:: + $check_row_Ý’ +( +ty³Çme + +T +:: +Commªd + +cmd +, cÚ¡ * +addr +) + +300  +chžd_id + = +addr +[( +Ëv– +)+1]; + +301 ià( +rowÝ’ +[( +cmd +)]) { + +302  +rowÝ’ +[( +cmd +)]( +this +, cmd, +chžd_id +); + +305 ià( +chžd_id + < 0 || ! +chžd»n +. + `size +()) + +306  +çl£ +; + +309  +chžd»n +[ +chžd_id +]-> + `check_row_Ý’ +( +cmd +, +addr +); + +310 + } +} + +312 + g‹m¶©e + < +ty³Çme + + gT +> + +313  + gDRAM +< + gT +>:: + $g‘_Ãxt +( +ty³Çme + +T +:: +Commªd + +cmd +, cÚ¡ * +addr +) + +315  +Ãxt_þk + = + `max +( +cur_þk +, +Ãxt +[( +cmd +)]); + +316 autØ +node + = +this +; + +317  +l + = ( +Ëv– +);† < ( +¥ec +-> +scÝe +[( +cmd +)]è&& +node +-> +chžd»n +. + `size +(è&& +addr +[l + 1] >= 0;†++){ + +318 +node + =‚ode-> +chžd»n +[ +addr +[ +l + + 1]]; + +319 +Ãxt_þk + = + `max +Òext_þk, +node +-> +Ãxt +[( +cmd +)]); + +321  +Ãxt_þk +; + +322 + } +} + +325 + g‹m¶©e + < +ty³Çme + + gT +> + +326  + gDRAM +< + gT +>:: + $upd©e +( +ty³Çme + +T +:: +Commªd + +cmd +, cÚ¡ * +addr +,  +þk +) + +328 +cur_þk + = +þk +; + +329 + `upd©e_¡©e +( +cmd +, +addr +); + +330 + `upd©e_timšg +( +cmd +, +addr +, +þk +); + +331 + } +} + +335 + g‹m¶©e + < +ty³Çme + + gT +> + +336  + gDRAM +< + gT +>:: + $upd©e_¡©e +( +ty³Çme + +T +:: +Commªd + +cmd +, cÚ¡ * +addr +) + +338  +chžd_id + = +addr +[( +Ëv– +)+1]; + +339 ià( +Ïmbda +[( +cmd +)]) + +340 +Ïmbda +[( +cmd +)]( +this +, +chžd_id +); + +342 ià( +Ëv– + =ð +¥ec +-> +scÝe +[( +cmd +)] || ! +chžd»n +. + `size +()) + +346 +chžd»n +[ +chžd_id +]-> + `upd©e_¡©e +( +cmd +, +addr +); + +347 + } +} + +351 + g‹m¶©e + < +ty³Çme + + gT +> + +352  + gDRAM +< + gT +>:: + $upd©e_timšg +( +ty³Çme + +T +:: +Commªd + +cmd +, cÚ¡ * +addr +,  +þk +) + +355 ià( +id + !ð +addr +[( +Ëv– +)]) { + +356 auto& +t + : +timšg +[( +cmd +)]) { + +357 ià(! +t +. +siblšg +) + +360 + `as£¹ + ( +t +. +di¡ + == 1); + +362  +futu» + = +þk + + +t +. +v® +; + +363 +Ãxt +[( +t +. +cmd +)] = + `max +Òext[Ñ.cmd)], +futu» +); + +370 ià( +´ev +[( +cmd +)]. + `size +()) { + +371 +´ev +[( +cmd +)]. + `pÝ_back +(); + +372 +´ev +[( +cmd +)]. + `push_äÚt +( +þk +); + +375 auto& +t + : +timšg +[( +cmd +)]) { + +376 ià( +t +. +siblšg +) + +379  +·¡ + = +´ev +[( +cmd +)][ +t +. +di¡ +-1]; + +380 ià( +·¡ + < 0) + +383  +futu» + = +·¡ + + +t +. +v® +; + +384 +Ãxt +[( +t +. +cmd +)] = + `max +Òext[Ñ.cmd)], +futu» +); + +386 ià( +¥ec +-> + `is_»äeshšg +( +cmd +è&& s³c-> + `is_Ý’šg +( +t +.cmd)) { + +387 + `as£¹ +( +·¡ + =ð +þk +); + +388 +begš_of_»äeshšg + = +þk +; + +389 +’d_of_»äeshšg + = + `max +Ónd_of_»äeshšg, +Ãxt +[( +t +. +cmd +)]); + +390 +»äesh_cyþes + +ð +’d_of_»äeshšg + - +þk +; + +391 ià( +cur_£rvšg_»que¡s + > 0) { + +392 +»äesh_š‹rv®s +. + `push_back +( + `make_·œ +( +begš_of_»äeshšg +, +’d_of_»äeshšg +)); + +399 ià(! +chžd»n +. + `size +()) + +403 autØ +chžd + : +chžd»n +) + +404 +chžd +-> + `upd©e_timšg +( +cmd +, +addr +, +þk +); + +406 + } +} + +408 + g‹m¶©e + < +ty³Çme + + gT +> + +409  + gDRAM +< + gT +>:: + $upd©e_£rvšg_»que¡s +(cÚ¡ * +addr +,  +d– +,  +þk +) { + +410 + `as£¹ +( +id + =ð +addr +[( +Ëv– +)]); + +411 + `as£¹ +( +d– + == 1 || delta == -1); + +413 ià( +begš_of_cur_»qút + !ð-1 && +cur_£rvšg_»que¡s + > 0) { + +414 +£rvšg_»que¡s + +ð( +þk + - +begš_of_cur_»qút +è* +cur_£rvšg_»que¡s +; + +415 +aùive_cyþes + +ð +þk + - +begš_of_cur_»qút +; + +418 +begš_of_cur_»qút + = +þk +; + +419 +cur_£rvšg_»que¡s + +ð +d– +; + +420 + `as£¹ +( +cur_£rvšg_»que¡s + >= 0); + +422 ià( +d– + =ð1 && +cur_£rvšg_»que¡s + == 1) { + +424 +begš_of_£rvšg + = +þk +; + +425 ià( +’d_of_»äeshšg + > +begš_of_£rvšg +) { + +426 +aùive_»äesh_ov”Ïp_cyþes + +ð +’d_of_»äeshšg + - +begš_of_£rvšg +; + +428 } ià( +cur_£rvšg_»que¡s + == 0) { + +430 + `as£¹ +( +begš_of_£rvšg + != -1); + +431 + `as£¹ +( +d– + == -1); + +432 +aùive_cyþes + +ð +þk + - +begš_of_cur_»qút +; + +433 +’d_of_£rvšg + = +þk +; + +435 cÚ¡‡uto& +»f +: +»äesh_š‹rv®s +) { + +436 +aùive_»äesh_ov”Ïp_cyþes + +ð + `mš +( +’d_of_£rvšg +, +»f +. +£cÚd +è-„ef. +fœ¡ +; + +438 +»äesh_š‹rv®s +. + `þ—r +(); + +441  +chžd_id + = +addr +[( +Ëv– +) + 1]; + +443 ià( +chžd_id + < 0 || ! +chžd»n +. + `size +(è|| (( +Ëv– +è> ( +T +:: +Lev– +:: +Bªk +)) ) { + +446 +chžd»n +[ +chžd_id +]-> + `upd©e_£rvšg_»que¡s +( +addr +, +d– +, +þk +); + +447 + } +} + + @DSARP.cpp + +12  + ~ + +13  + ~ + +14  + ~<ÿs£¹ +> + +15  + ~ + +16  + ~"DSARP.h +" + +17  + ~"DRAM.h +" + +19 +usšg + +Çme¥aû + + g¡d +; + +20 +usšg + +Çme¥aû + + g¿muÏtÜ +; + +22 +¡ršg + + gDSARP +:: +¡ªd¬d_Çme + = "DSARP"; + +24 + gm­ +< + g¡ršg +, + gDSARP +:: +Org +> +DSARP +:: +Üg_m­ + = { + +25 {"DSARP_8Gb_x8", +DSARP +:: +Org +:: +DSARP_8Gb_x8 +}, + +26 {"DSARP_16Gb_x9", +DSARP +:: +Org +:: +DSARP_16Gb_x8 +}, + +27 {"DSARP_32Gb_x8", +DSARP +:: +Org +:: +DSARP_32Gb_x8 +}, + +30 + gm­ +< + g¡ršg +, + gDSARP +:: +S³ed +> +DSARP +:: +¥“d_m­ + = { + +31 {"DSARP_1333", +DSARP +:: +S³ed +:: +DSARP_1333 +}, + +34 + gDSARP +:: + $DSARP +( +Org + +Üg +, +S³ed + +¥“d +, +Ty³ + +ty³ +,  +n_§ +) : + +35 + `ty³ +( +ty³ +), + +36 + `Üg_’Œy +( +Üg_bË +[( +Üg +)]), + +37 + `¥“d_’Œy +( +¥“d_bË +[( +¥“d +)]), + +38 + `»ad_Ï‹ncy +( +¥“d_’Œy +. +nCL + + s³ed_’Œy. +nBL +), + +39 + $n_§ +( +n_§ +) + +41 + `š™_¥“d +(); + +42 + `š™_´”eq +(); + +43 + `š™_rowh™ +(); + +44 + `š™_rowÝ’ +(); + +45 + `š™_Ïmbda +(); + +46 + `š™_timšg +(); + +49 +b_»f_¿nk + = +çl£ +; + +50 ( +ty³ +)){ + +51 ( +Ty³ +:: +REFAB +): + +52 +¡ªd¬d_Çme + = "REFAB"; + +53 +b_»f_¿nk + = +Œue +; + +55 ( +Ty³ +:: +REFPB +): +¡ªd¬d_Çme + = "REFPB"; ; + +56 ( +Ty³ +:: +DARP +): +¡ªd¬d_Çme + = "DARP"; ; + +57 ( +Ty³ +:: +SARP +): +¡ªd¬d_Çme + = "SARP"; ; + +58 ( +Ty³ +:: +DSARP +): +¡ªd¬d_Çme + = "DSARP"; ; + +62 + `as£¹ +( +n_§ + &&‚_sa <= 128 && (n_sa & (n_sa-1)) == 0); + +63 +Üg_’Œy +. +couÁ +[( +Lev– +:: +SubA¼ay +)] = +n_§ +; + +64  +tmp + = ( +Üg_’Œy +. +dq +è* org_’Œy. +couÁ +[( +Lev– +:: +Bªk +)] * + +65 +n_§ + * +Üg_’Œy +. +couÁ +[( +Lev– +:: +CÞumn +)]; + +66 +Üg_’Œy +. +couÁ +[( +Lev– +:: +Row +)] = (Üg_’Œy. +size +è* (1<<20è/ +tmp +; + +69 ià(! +b_»f_¿nk +) + +70 +Œª¦©e +[( +Reque¡ +:: +Ty³ +:: +REFRESH +)] = +Commªd +:: +REFPB +; + +71 + } +} + +73 + gDSARP +:: + $DSARP +(cÚ¡ +¡ršg +& +Üg_¡r +, cÚ¡ sŒšg& +¥“d_¡r +, +Ty³ + +ty³ +,  +n_§ +) : + +74 + $DSARP +( +Üg_m­ +[ +Üg_¡r +], +¥“d_m­ +[ +¥“d_¡r +], +ty³ +, +n_§ +è{ + } +} + +76  + gDSARP +:: + $£t_chªÃl_numb” +( +chªÃl +) { + +77 +Üg_’Œy +. +couÁ +[( +Lev– +:: +ChªÃl +)] = +chªÃl +; + +78 + } +} + +80  + gDSARP +:: + $£t_¿nk_numb” +( +¿nk +) { + +81 +Üg_’Œy +. +couÁ +[( +Lev– +:: +Rªk +)] = +¿nk +; + +82 + } +} + +85  + gDSARP +:: + $š™_¥“d +() + +92 cÚ¡  +RFCAB_TABLE +[( +Org +:: +MAX +)][( +S³ed +::MAX)] = { + +97 cÚ¡  +RFCPB_TABLE +[( +Org +:: +MAX +)][( +S³ed +::MAX)] = { + +102 cÚ¡  +REFI_TABLE +[( +ReäeshMode +:: +MAX +)][( +S³ed +::MAX)] = { + +106 cÚ¡  +REFIPB_TABLE +[( +ReäeshMode +:: +MAX +)][( +S³ed +::MAX)] = { + +110  +¥“d + = 0, +d’s™y + = 0; + +111  +¥“d_’Œy +. +¿‹ +) { + +112 1333: +¥“d + = 0; ; + +113 : + `as£¹ +( +çl£ +); + +115  +Üg_’Œy +. +size + >> 10){ + +116 8: +d’s™y + = 0; ; + +117 16: +d’s™y + = 1; ; + +118 32: +d’s™y + = 2; ; + +119 : + `as£¹ +( +çl£ + && "Unknown density"); + +122 +¥“d_’Œy +. +nRFCpb + = +RFCPB_TABLE +[ +d’s™y +][ +¥“d +]; + +123 +¥“d_’Œy +. +nRFCab + = +RFCAB_TABLE +[ +d’s™y +][ +¥“d +]; + +124 +¥“d_’Œy +. +nREFI + = +REFI_TABLE +[( +»äesh_mode +)][ +¥“d +]; + +125 +¥“d_’Œy +. +nREFIpb + = +REFIPB_TABLE +[( +»äesh_mode +)][ +¥“d +]; + +126 + } +} + +128  + gDSARP +:: + $š™_´”eq +() + +131 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +DSARP +>* +node +, Commªd +cmd +,  +id +) { + +132 ( +node +-> +¡©e +)) { + +133 ( +S‹ +:: +Pow”Up +):  +Commªd +:: +MAX +; + +134 ( +S‹ +:: +AùPow”Down +):  +Commªd +:: +PDX +; + +135 ( +S‹ +:: +P»Pow”Down +):  +Commªd +:: +PDX +; + +136 ( +S‹ +:: +S–fReäesh +):  +Commªd +:: +SRX +; + +137 : + `as£¹ +( +çl£ +); + +140 +´”eq +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +DSARP +>* +node +, Commªd +cmd +,  +id +) { + +141 ( +node +-> +¡©e +)) { + +142 ( +S‹ +:: +Clo£d +):  +Commªd +:: +ACT +; + +143 ( +S‹ +:: +O³Ãd +): + +145 ià( +node +-> +row_¡©e +. + `fšd +( +id +è!ðnode->row_¡©e. + `’d +()) + +146  +Commªd +:: +MAX +; + +147  +Commªd +:: +PRE +; + +148 : + `as£¹ +( +çl£ +); + +151 +´”eq +[( +Lev– +:: +SubA¼ay +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +DSARP +>* +node +, Commªd +cmd +,  +id +) { + +152 ( +node +-> +¡©e +)) { + +153 ( +S‹ +:: +Clo£d +):  +Commªd +:: +ACT +; + +154 ( +S‹ +:: +O³Ãd +): + +156 ià( +node +-> +row_¡©e +. + `fšd +( +id +è!ðnode->row_¡©e. + `’d +()) + +157  +cmd +; + +158  +Commªd +:: +PRE +; + +159 : + `as£¹ +( +çl£ +); + +163 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +WR +)] =…»»q[(Lev–::Rªk)][(Commªd:: +RD +)]; + +164 +´”eq +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] =…»»q[(Lev–::Bªk)][(Commªd:: +RD +)]; + +165 +´”eq +[( +Lev– +:: +SubA¼ay +)][( +Commªd +:: +WR +)] =…»»q[(Lev–::SubA¼ay)][(Commªd:: +RD +)]; + +168 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +REF +)] = [] ( +DRAM +< +DSARP +>* +node +, Commªd +cmd +,  +id +) { + +169 autØ +bªk + : +node +-> +chžd»n +) { + +170 ià( +bªk +-> +¡©e + =ð +S‹ +:: +Clo£d +) + +172  +Commªd +:: +PREA +; + +174  +Commªd +:: +REF +;}; + +177 +´”eq +[( +Lev– +:: +Bªk +)][( +Commªd +:: +REFPB +)] = [] ( +DRAM +< +DSARP +>* +node +, Commªd +cmd +,  +id +) { + +178 ià( +node +-> +¡©e + =ð +S‹ +:: +Clo£d +è +Commªd +:: +REFPB +; + +179  +Commªd +:: +PRE +;}; + +182 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PDE +)] = [] ( +DRAM +< +DSARP +>* +node +, Commªd +cmd +,  +id +) { + +183 ( +node +-> +¡©e +)) { + +184 ( +S‹ +:: +Pow”Up +):  +Commªd +:: +PDE +; + +185 ( +S‹ +:: +AùPow”Down +):  +Commªd +:: +PDE +; + +186 ( +S‹ +:: +P»Pow”Down +):  +Commªd +:: +PDE +; + +187 ( +S‹ +:: +S–fReäesh +):  +Commªd +:: +SRX +; + +188 : + `as£¹ +( +çl£ +); + +192 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +SRE +)] = [] ( +DRAM +< +DSARP +>* +node +, Commªd +cmd +,  +id +) { + +193 ( +node +-> +¡©e +)) { + +194 ( +S‹ +:: +Pow”Up +):  +Commªd +:: +SRE +; + +195 ( +S‹ +:: +AùPow”Down +):  +Commªd +:: +PDX +; + +196 ( +S‹ +:: +P»Pow”Down +):  +Commªd +:: +PDX +; + +197 ( +S‹ +:: +S–fReäesh +):  +Commªd +:: +SRE +; + +198 : + `as£¹ +( +çl£ +); + +200 + } +} + +203  + gDSARP +:: + $š™_rowh™ +() + +206 +rowh™ +[( +Lev– +:: +SubA¼ay +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +DSARP +>* +node +, Commªd +cmd +,  +id +) { + +207 ( +node +-> +¡©e +)){ + +208 ( +S‹ +:: +Clo£d +):  +çl£ +; + +209 ( +S‹ +:: +O³Ãd +): + +210 ià( +node +-> +row_¡©e +. + `fšd +( +id +è!ðnode->row_¡©e. + `’d +()è +Œue +; + +211  +çl£ +; + +212 : + `as£¹ +( +çl£ +); + +215 +rowh™ +[( +Lev– +:: +SubA¼ay +)][( +Commªd +:: +WR +)] =„owh™[(Lev–::SubA¼ay)][(Commªd:: +RD +)]; + +216 + } +} + +218  + gDSARP +:: + $š™_rowÝ’ +() + +221 +rowÝ’ +[( +Lev– +:: +SubA¼ay +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +DSARP +>* +node +, Commªd +cmd +,  +id +) { + +222 ( +node +-> +¡©e +)){ + +223 ( +S‹ +:: +Clo£d +):  +çl£ +; + +224 ( +S‹ +:: +O³Ãd +):  +Œue +; + +225 : + `as£¹ +( +çl£ +); + +228 +rowÝ’ +[( +Lev– +:: +SubA¼ay +)][( +Commªd +:: +WR +)] =„owÝ’[(Lev–::SubA¼ay)][(Commªd:: +RD +)]; + +229 + } +} + +231  + gDSARP +:: + $š™_Ïmbda +() + +234 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PREA +)] = [] ( +DRAM +< +DSARP +>* +node +,  +id +) { + +235 +node +-> +row_¡©e +. + `þ—r +(); + +236 autØ +bªk + : +node +-> +chžd»n +) { + +237 +bªk +-> +¡©e + = +S‹ +:: +Clo£d +; + +238 +bªk +-> +row_¡©e +. + `þ—r +(); + +239 autØ +§ + : +bªk +-> +chžd»n +){ + +240 +§ +-> +¡©e + = +S‹ +:: +Clo£d +; + +241 +§ +-> +row_¡©e +. + `þ—r +();}}}; + +242 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +REF +)] = [] ( +DRAM +< +DSARP +>* +node +,  +id +) {}; + +245 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PDE +)] = [] ( +DRAM +< +DSARP +>* +node +,  +id +) { + +246 autØ +bªk + : +node +-> +chžd»n +) { + +247 ià( +bªk +-> +¡©e + =ð +S‹ +:: +Clo£d +) + +249 +node +-> +¡©e + = +S‹ +:: +AùPow”Down +; + +252 +node +-> +¡©e + = +S‹ +:: +P»Pow”Down +;}; + +253 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PDX +)] = [] ( +DRAM +< +DSARP +>* +node +,  +id +) { + +254 +node +-> +¡©e + = +S‹ +:: +Pow”Up +;}; + +255 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +SRE +)] = [] ( +DRAM +< +DSARP +>* +node +,  +id +) { + +256 +node +-> +¡©e + = +S‹ +:: +S–fReäesh +;}; + +257 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +SRX +)] = [] ( +DRAM +< +DSARP +>* +node +,  +id +) { + +258 +node +-> +¡©e + = +S‹ +:: +Pow”Up +;}; + +261 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +ACT +)] = [] ( +DRAM +< +DSARP +>* +node +,  +id +) { + +262 +node +-> +¡©e + = +S‹ +:: +O³Ãd +; + +263 +node +-> +row_¡©e +[ +id +] = +S‹ +:: +O³Ãd +;}; + +264 +Ïmbda +[( +Lev– +:: +SubA¼ay +)][( +Commªd +:: +ACT +)] = [] ( +DRAM +< +DSARP +>* +node +,  +id +) { + +265 +node +-> +¡©e + = +S‹ +:: +O³Ãd +; + +266 +node +-> +row_¡©e +[ +id +] = +S‹ +:: +O³Ãd +;}; + +269 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +PRE +)] = [] ( +DRAM +< +DSARP +>* +node +,  +id +) { + +270 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +271 +node +-> +row_¡©e +. + `þ—r +(); + +272 autØ +§ + : +node +-> +chžd»n +){ + +273 +§ +-> +¡©e + = +S‹ +:: +Clo£d +; + +274 +§ +-> +row_¡©e +. + `þ—r +();}}; + +276 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +DSARP +>* +node +,  +id +) {}; + +277 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] = [] ( +DRAM +< +DSARP +>* +node +,  +id +) {}; + +280 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RDA +)] = [] ( +DRAM +< +DSARP +>* +node +,  +id +) { + +281 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +282 +node +-> +row_¡©e +. + `þ—r +();}; + +284 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WRA +)] = [] ( +DRAM +< +DSARP +>* +node +,  +id +) { + +285 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +286 +node +-> +row_¡©e +. + `þ—r +();}; + +289 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +REFPB +)] = [] ( +DRAM +< +DSARP +>* +node +,  +id +) { + +290 + `as£¹ +( +node +-> +¡©e + =ð +S‹ +:: +Clo£d +); + +291 +node +-> +row_¡©e +. + `þ—r +();}; + +294 +Ïmbda +[( +Lev– +:: +SubA¼ay +)][( +Commªd +:: +RDA +)] = [] ( +DRAM +< +DSARP +>* +node +,  +id +) { + +295 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +296 +node +-> +row_¡©e +. + `þ—r +();}; + +297 +Ïmbda +[( +Lev– +:: +SubA¼ay +)][( +Commªd +:: +WRA +)] = [] ( +DRAM +< +DSARP +>* +node +,  +id +) { + +298 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +299 +node +-> +row_¡©e +. + `þ—r +();}; + +302 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PDE +)] = [] ( +DRAM +< +DSARP +>* +node +,  +id +) { + +303 autØ +bªk + : +node +-> +chžd»n +) + +304 autØ +§ + : +bªk +-> +chžd»n +) { + +305 ià( +§ +-> +¡©e + =ð +S‹ +:: +Clo£d +) + +307 +node +-> +¡©e + = +S‹ +:: +AùPow”Down +; + +310 +node +-> +¡©e + = +S‹ +:: +P»Pow”Down +;}; + +311 + } +} + +313  + gDSARP +:: + $š™_timšg +() + +315 +S³edEÁry +& +s + = +¥“d_’Œy +; + +316 +veùÜ +< +TimšgEÁry +> * +t +; + +319 +t + = +timšg +[( +Lev– +:: +ChªÃl +)]; + +322 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nBL +}); + +323 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nBL +}); + +324 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nBL +}); + +325 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd::RDA, 1, +s +. +nBL +}); + +326 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd::WR, 1, +s +. +nBL +}); + +327 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nBL +}); + +328 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nBL +}); + +329 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd::WRA, 1, +s +. +nBL +}); + +332 +t + = +timšg +[( +Lev– +:: +Rªk +)]; + +335 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nCCD +}); + +336 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCCD +}); + +337 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCCD +}); + +338 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd::RDA, 1, +s +. +nCCD +}); + +339 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd::WR, 1, +s +. +nCCD +}); + +340 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCCD +}); + +341 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCCD +}); + +342 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd::WRA, 1, +s +. +nCCD +}); + +345 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nCCD + + 2 - s. +nCWL +}); + +346 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCL + + s. +nCCD + + 2 - s. +nCWL +}); + +347 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nCCD + + 2 - s. +nCWL +}); + +348 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCL + + s. +nCCD + + 2 - s. +nCWL +}); + +351 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTR +}); + +352 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTR +}); + +353 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTR +}); + +354 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTR +}); + +357 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +358 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +359 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +360 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd::RDA, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +361 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +362 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +363 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +364 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +366 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nBL + + s. +nRTRS + - s. +nCWL +, +Œue +}); + +367 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCL + + s. +nBL + + s. +nRTRS + - s. +nCWL +, +Œue +}); + +368 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nBL + + s. +nRTRS + - s. +nCWL +, +Œue +}); + +369 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCL + + s. +nBL + + s. +nRTRS + - s. +nCWL +, +Œue +}); + +370 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nRTRS + - s. +nCL +, +Œue +}); + +371 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nRTRS + - s. +nCL +, +Œue +}); + +372 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nRTRS + - s. +nCL +, +Œue +}); + +373 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nRTRS + - s. +nCL +, +Œue +}); + +376 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PREA +, 1, +s +. +nRTP +}); + +377 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PREA +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +}); + +380 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nCL + + s. +nBL + + 1}); + +381 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nCL + + s. +nBL + + 1}); + +382 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +}); + +383 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR + + 1}); + +384 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nXP +}); + +385 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nXP +}); + +386 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nXP +}); + +387 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nXP +}); + +390 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 1, +s +. +nRRD +}); + +391 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 4, +s +. +nFAW +}); + +392 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PREA +, 1, +s +. +nRAS +}); + +393 +t +[( +Commªd +:: +PREA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRPab +}); + +396 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nRPpb +}); + +397 +t +[( +Commªd +:: +PREA +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nRPab +}); + +398 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRFCab +}); + +401 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PDE +, 1, 1}); + +402 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nXP +}); + +403 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nXP +}); + +404 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PREA +, 1, +s +. +nXP +}); + +407 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nRPpb +}); + +408 +t +[( +Commªd +:: +PREA +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nRPab +}); + +409 +t +[( +Commªd +:: +SRX +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nXS +}); + +412 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd::REF, 1, +s +. +nRFCab +}); + +413 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd:: +REFPB +, 1, +s +. +nRFCab +}); + +414 +t +[( +Commªd +:: +REFPB +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nRFCpb +}); + +417 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd:: +PDE +, 1, 1}); + +418 +t +[( +Commªd +:: +REFPB +)]. + `push_back +({Commªd:: +PDE +, 1, 1}); + +419 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nXP +}); + +420 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +REFPB +, 1, +s +. +nXP +}); + +423 +t +[( +Commªd +:: +SRX +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nXS +}); + +424 +t +[( +Commªd +:: +SRX +)]. + `push_back +({Commªd:: +REFPB +, 1, +s +. +nXS +}); + +427 +t +[( +Commªd +:: +PDE +)]. + `push_back +({Commªd:: +PDX +, 1, +s +. +nPD +}); + +428 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nXP +}); + +431 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nXP +}); + +432 +t +[( +Commªd +:: +SRX +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nXS +}); + +435 +t +[( +Commªd +:: +SRE +)]. + `push_back +({Commªd:: +SRX +, 1, +s +. +nCKESR +}); + +436 +t +[( +Commªd +:: +SRX +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nXS +}); + +439 +t +[( +Commªd +:: +REFPB +)]. + `push_back +Ð{ Commªd::REFPB, 1, +s +. +nRFCpb + }); + +442 +t + = +timšg +[( +Lev– +:: +Bªk +)]; + +445 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nRCD +}); + +446 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nRCD +}); + +447 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nRCD +}); + +448 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nRCD +}); + +450 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nRTP +}); + +451 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +}); + +453 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRTP + + s. +nRPpb +}); + +454 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR + + s. +nRPpb +}); + +457 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 1, +s +. +nRC +}); + +458 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nRAS +}); + +459 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRPpb +}); + +460 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +REFPB +, 1, +s +. +nRPpb +}); + +463 +t +[( +Commªd +:: +REFPB +)]. + `push_back +Ð{ Commªd::REFPB, 1, +s +. +nRFCpb + }); + +466 +t +[( +Commªd +:: +REFPB +)]. + `push_back +Ð{ Commªd::REFPB, 1, +s +. +nRFCpb +, +Œue +}); + +467 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +REFPB +, 1, +s +. +nRRD +, +Œue +}); + +468 +t +[( +Commªd +:: +REFPB +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRRD +, +Œue +}); + +471 ià(!( +ty³ + =ð +Ty³ +:: +DSARP + ||y³ =ðTy³:: +SARP +)) { + +472 +t +[( +Commªd +:: +REFPB +)]. + `push_back +Ð{ Commªd:: +ACT +, 1, +s +. +nRFCpb + }); + +473 +t +[( +Commªd +:: +REFPB +)]. + `push_back +Ð{ Commªd:: +RD +, 1, +s +. +nRFCpb + }); + +474 +t +[( +Commªd +:: +REFPB +)]. + `push_back +Ð{ Commªd:: +RDA +, 1, +s +. +nRFCpb + }); + +475 +t +[( +Commªd +:: +REFPB +)]. + `push_back +Ð{ Commªd:: +WR +, 1, +s +. +nRFCpb + }); + +476 +t +[( +Commªd +:: +REFPB +)]. + `push_back +Ð{ Commªd:: +WRA +, 1, +s +. +nRFCpb + }); + +477 +t +[( +Commªd +:: +REFPB +)]. + `push_back +Ð{ Commªd:: +PRE +, 1, +s +. +nRFCpb + }); + +478 +t +[( +Commªd +:: +REFPB +)]. + `push_back +Ð{ Commªd:: +PREA +, 1, +s +. +nRFCpb + }); + +482 ià( +ty³ + =ð +Ty³ +:: +DSARP + ||y³ =ðTy³:: +SARP +) { + +483 +t + = +timšg +[( +Lev– +:: +SubA¼ay +)]; + +486 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +REFPB +, 1, + +487 () + `ûž +((() +s +. +nRRD +)* +nRRD_çùÜ +), +Œue +}); + +488 +t +[( +Commªd +:: +REFPB +)]. + `push_back +({Commªd:: +ACT +, 1, + +489 () + `ûž +((() +s +. +nRRD +)* +nRRD_çùÜ +), +Œue +}); + +492 +t +[( +Commªd +:: +REF +)]. + `push_back +Ð{ Commªd:: +ACT +, 1, +s +. +nRFCab + }); + +493 +t +[( +Commªd +:: +REFPB +)]. + `push_back +Ð{ Commªd:: +ACT +, 1, +s +. +nRFCpb + }); + +496 +t +[( +Commªd +:: +ACT +)]. + `push_back +Ð{ Commªd:: +RD +, 1, +s +. +nRCD + }); + +497 +t +[( +Commªd +:: +ACT +)]. + `push_back +Ð{ Commªd:: +RDA +, 1, +s +. +nRCD + }); + +498 +t +[( +Commªd +:: +ACT +)]. + `push_back +Ð{ Commªd:: +WR +, 1, +s +. +nRCD + }); + +499 +t +[( +Commªd +:: +ACT +)]. + `push_back +Ð{ Commªd:: +WRA +, 1, +s +. +nRCD + }); + +501 +t +[( +Commªd +:: +RD +)]. + `push_back +Ð{ Commªd:: +PRE +, 1, +s +. +nRTP + }); + +502 +t +[( +Commªd +:: +WR +)]. + `push_back +( + +503 { +Commªd +:: +PRE +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR + }); + +505 +t +[( +Commªd +:: +RDA +)]. + `push_back +Ð{ Commªd:: +ACT +, 1, +s +. +nRTP + + s. +nRPpb + }); + +506 +t +[( +Commªd +:: +WRA +)]. + `push_back +( + +507 { +Commªd +:: +ACT +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR + + s. +nRPpb + }); + +510 +t +[( +Commªd +:: +ACT +)]. + `push_back +Ð{ Commªd::ACT, 1, +s +. +nRC + }); + +511 +t +[( +Commªd +:: +ACT +)]. + `push_back +Ð{ Commªd:: +PRE +, 1, +s +. +nRAS + }); + +512 +t +[( +Commªd +:: +PRE +)]. + `push_back +Ð{ Commªd:: +ACT +, 1, +s +. +nRPpb + }); + +513 +t +[( +Commªd +:: +PRE +)]. + `push_back +Ð{ Commªd:: +REFPB +, 1, +s +. +nRPpb + }); + +514 +t +[( +Commªd +:: +PRE +)]. + `push_back +Ð{ Commªd:: +REF +, 1, +s +. +nRPpb + }); + +518 +t +[( +Commªd +:: +ACT +)]. + `push_back +Ð{ Commªd::ACT, 1, +s +. +nRC +, +Œue + }); + +519 +t +[( +Commªd +:: +PRE +)]. + `push_back +Ð{ Commªd:: +ACT +, 1, +s +. +nRPpb +, +Œue + }); + +520 +t +[( +Commªd +:: +RDA +)]. + `push_back +Ð{ Commªd:: +ACT +, 1, +s +. +nRTP + + s. +nRPpb +, + +521 +Œue + }); + +522 +t +[( +Commªd +:: +WRA +)]. + `push_back +( + +523 { +Commªd +:: +ACT +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR + + s. +nRPpb +, +Œue + }); + +525 + } +} + + @DSARP.h + +35 #iâdeà +DSARP_H_ + + +36  + #DSARP_H_ + + + ) + +38  + ~ + +39  + ~ + +40  + ~"DRAM.h +" + +41  + ~"Reque¡.h +" + +43 +usšg + +Çme¥aû + + g¡d +; + +45 +Çme¥aû + + g¿muÏtÜ + + +48 þas  + cDSARP + + +50 + gpublic +: + +51  +¡ršg + +¡ªd¬d_Çme +; + +52 +þass + + gOrg +; + +53 +þass + + gS³ed +; + +54 +þass + + gTy³ +; + +55 +DSARP +( +Org + +Üg +, +S³ed + +¥“d +, +Ty³ + +ty³ +,  +n_§ +); + +56 +DSARP +(cÚ¡ +¡ršg +& +Üg_¡r +, cÚ¡ sŒšg& +¥“d_¡r +, +Ty³ + +ty³ +,  +n_§ +); + +58  + gm­ +< + g¡ršg +, + gOrg +> + gÜg_m­ +; + +59  + gm­ +< + g¡ršg +, + gS³ed +> + g¥“d_m­ +; + +61 þas  + cTy³ + :  + +63 +REFAB +, + gREFPB +, + gDARP +, + gSARP +, + gDSARP +, + gMAX + + +64 } + gty³ +; + +69 þas  + cLev– + :  + +71 +ChªÃl +, + gRªk +, + gBªk +, + gSubA¼ay +, + gRow +, + gCÞumn +, + gMAX + + +75 þas  + cCommªd + :  + +77 +ACT +, + gPRE +, + gPREA +, + +78 + gRD +, + gWR +, + gRDA +, + gWRA +, + +79 + gREF +, + gREFPB +, + gPDE +, + gPDX +, + gSRE +, + gSRX +, + +80 + gMAX + + +83 +¡ršg + + gcommªd_Çme +[( +Commªd +:: +MAX +)] = { + +91 +Lev– + + gscÝe +[( +Commªd +:: +MAX +)] = { + +92 +Lev– +:: +Row +, Lev–:: +Bªk +, Lev–:: +Rªk +, + +93 +Lev– +:: +CÞumn +, Level::Column, Level::Column, Level::Column, + +94 +Lev– +:: +Rªk +, Lev–:: +Bªk +, + +95 +Lev– +:: +Rªk +, Level::Rank, Level::Rank, Level::Rank + +98 +boÞ + +is_Ý’šg +( +Commªd + +cmd +) + +100 ( + gcmd +)) { + +101 ( + gCommªd +:: +ACT +): + +102  +Œue +; + +104  +çl£ +; + +108 +boÞ + +is_acûssšg +( +Commªd + +cmd +) + +110 ( + gcmd +)) { + +111 ( + gCommªd +:: +RD +): + +112 ( +Commªd +:: +WR +): + +113 ( +Commªd +:: +RDA +): + +114 ( +Commªd +:: +WRA +): + +115  +Œue +; + +117  +çl£ +; + +121 +boÞ + +is_þosšg +( +Commªd + +cmd +) + +123 ( + gcmd +)) { + +124 ( + gCommªd +:: +RDA +): + +125 ( +Commªd +:: +WRA +): + +126 ( +Commªd +:: +PRE +): + +127 ( +Commªd +:: +PREA +): + +128  +Œue +; + +130  +çl£ +; + +134 +boÞ + +is_»äeshšg +( +Commªd + +cmd +) + +136 ( + gcmd +)) { + +137 ( + gCommªd +:: +REF +): + +138 ( +Commªd +:: +REFPB +): + +139  +Œue +; + +141  +çl£ +; + +146 þas  + cS‹ + :  + +148 +O³Ãd +, + gClo£d +, + gPow”Up +, + gAùPow”Down +, + gP»Pow”Down +, + gS–fReäesh +, + gMAX + + +149 } + g¡¬t +[( +Lev– +:: +MAX +)] = { + +150 +S‹ +:: +MAX +, S‹:: +Pow”Up +, S‹:: +Clo£d +, State::Closed, State::MAX + +154 +Commªd + + gŒª¦©e +[( +Reque¡ +:: +Ty³ +:: +MAX +)] = { + +155 +Commªd +:: +RD +, Commªd:: +WR +, + +156 +Commªd +:: +REF +, Commªd:: +PDE +, Commªd:: +SRE + + +160 + gfunùiÚ +< +Commªd +( +DRAM +< +DSARP +>*, Commªd +cmd +, )> + g´”eq +[( +Lev– +:: +MAX +)][(Command::MAX)]; + +164 + gfunùiÚ +< +boÞ +( +DRAM +< +DSARP +>*, +Commªd + +cmd +, )> + growh™ +[( +Lev– +:: +MAX +)][(Command::MAX)]; + +165 + gfunùiÚ +< +boÞ +( +DRAM +< +DSARP +>*, +Commªd + +cmd +, )> + growÝ’ +[( +Lev– +:: +MAX +)][(Command::MAX)]; + +168  + sTimšgEÁry + + +170 +Commªd + + gcmd +; + +171  + gdi¡ +; + +172  + gv® +; + +173 +boÞ + + gsiblšg +; + +175 + gveùÜ +< + gTimšgEÁry +> + gtimšg +[( +Lev– +:: +MAX +)][( +Commªd +::MAX)]; + +178 + gfunùiÚ +<( + gDRAM +< + gDSARP +>*, )> + gÏmbda +[( +Lev– +:: +MAX +)][( +Commªd +::MAX)]; + +181 þas  + cOrg + :  + +184 +DSARP_8Gb_x8 +, + +185 + gDSARP_16Gb_x8 +, + +186 + gDSARP_32Gb_x8 +, + +187 + gMAX + + +190  + sOrgEÁry + { + +191  + gsize +; + +192  + gdq +; + +193  + gcouÁ +[( +Lev– +:: +MAX +)]; + +194 } + gÜg_bË +[( +Org +:: +MAX +)] = { + +202 }, + gÜg_’Œy +; + +204  +£t_chªÃl_numb” +( +chªÃl +); + +205  +£t_¿nk_numb” +( +¿nk +); + +208 þas  + cS³ed + :  + +210 +DSARP_1333 +, + +211 + gMAX + + +214 þas  + cReäeshMode + :  + +216 +Reäesh_1X +, + +217 + gMAX + + +218 } + g»äesh_mode + = +ReäeshMode +:: +Reäesh_1X +; + +220  + g´eãtch_size + = 16; + +221  + gchªÃl_width + = 32; + +223  + sS³edEÁry + { + +224  + g¿‹ +; + +225  + gäeq +, + gtCK +; + +226  + gnBL +, + gnCCD +, + gnRTRS +; + +227  + gnCL +, + gnRCD +, + gnRPpb +, + gnRPab +, + gnCWL +; + +228  + gnRAS +, + gnRC +; + +229  + gnRTP +, + gnWTR +, + gnWR +; + +230  + gnRRD +, + gnFAW +; + +231  + gnRFCab +, + gnRFCpb +, + gnREFI +, + gnREFIpb +; + +232  + gnPD +, + gnXP +, + gnXPDLL +; + +233  + gnCKESR +, + gnXS +, + gnXSDLL +; + +236 } + g¥“d_bË +[( +S³ed +:: +MAX +)] = { + +247 }, + g¥“d_’Œy +; + +249  + g»ad_Ï‹ncy +; + +252  + gn_§ +; + +255 +boÞ + + gb_»f_¿nk +; + +258  + gnRRD_çùÜ + = 1.138; + +260 + g´iv©e +: + +261  +š™_¥“d +(); + +262  +š™_Ïmbda +(); + +263  +š™_´”eq +(); + +264  +š™_rowh™ +(); + +265  +š™_rowÝ’ +(); + +266  +š™_timšg +(); + + @GDDR5.cpp + +1  + ~"GDDR5.h +" + +2  + ~"DRAM.h +" + +3  + ~ + +4  + ~ + +5  + ~<ÿs£¹ +> + +7 +usšg + +Çme¥aû + + g¡d +; + +8 +usšg + +Çme¥aû + + g¿muÏtÜ +; + +10 +¡ršg + + gGDDR5 +:: +¡ªd¬d_Çme + = "GDDR5"; + +12 + gm­ +< + g¡ršg +, + gGDDR5 +:: +Org +> +GDDR5 +:: +Üg_m­ + = { + +13 {"GDDR5_512Mb_x16", +GDDR5 +:: +Org +:: +GDDR5_512Mb_x16 +}, {"GDDR5_512Mb_x32", GDDR5::Org:: +GDDR5_512Mb_x32 +}, + +14 {"GDDR5_1Gb_x16", +GDDR5 +:: +Org +:: +GDDR5_1Gb_x16 +}, {"GDDR5_1Gb_x32", GDDR5::Org:: +GDDR5_1Gb_x32 +}, + +15 {"GDDR5_2Gb_x16", +GDDR5 +:: +Org +:: +GDDR5_2Gb_x16 +}, {"GDDR5_2Gb_x32", GDDR5::Org:: +GDDR5_2Gb_x32 +}, + +16 {"GDDR5_4Gb_x16", +GDDR5 +:: +Org +:: +GDDR5_4Gb_x16 +}, {"GDDR5_4Gb_x32", GDDR5::Org:: +GDDR5_4Gb_x32 +}, + +17 {"GDDR5_8Gb_x16", +GDDR5 +:: +Org +:: +GDDR5_8Gb_x16 +}, {"GDDR5_8Gb_x32", GDDR5::Org:: +GDDR5_8Gb_x32 +}, + +20 + gm­ +< + g¡ršg +, + gGDDR5 +:: +S³ed +> +GDDR5 +:: +¥“d_m­ + = { + +21 {"GDDR5_4000", +GDDR5 +:: +S³ed +:: +GDDR5_4000 +}, {"GDDR5_4500", GDDR5::S³ed:: +GDDR5_4500 +}, + +22 {"GDDR5_5000", +GDDR5 +:: +S³ed +:: +GDDR5_5000 +}, {"GDDR5_5500", GDDR5::S³ed:: +GDDR5_5500 +}, + +23 {"GDDR5_6000", +GDDR5 +:: +S³ed +:: +GDDR5_6000 +}, {"GDDR5_6500", GDDR5::S³ed:: +GDDR5_6500 +}, + +24 {"GDDR5_7000", +GDDR5 +:: +S³ed +:: +GDDR5_7000 +}, + +27 + gGDDR5 +:: + $GDDR5 +( +Org + +Üg +, +S³ed + +¥“d +) : + +28 + `Üg_’Œy +( +Üg_bË +[( +Üg +)]), + +29 + `¥“d_’Œy +( +¥“d_bË +[( +¥“d +)]), + +30 + `»ad_Ï‹ncy +( +¥“d_’Œy +. +nCL + + s³ed_’Œy. +nBL +) + +32 + `š™_¥“d +(); + +33 + `š™_´”eq +(); + +34 + `š™_rowh™ +(); + +35 + `š™_rowÝ’ +(); + +36 + `š™_Ïmbda +(); + +37 + `š™_timšg +(); + +38 + } +} + +40 + gGDDR5 +:: + $GDDR5 +(cÚ¡ +¡ršg +& +Üg_¡r +, cÚ¡ sŒšg& +¥“d_¡r +) : + +41 + $GDDR5 +( +Üg_m­ +[ +Üg_¡r +], +¥“d_m­ +[ +¥“d_¡r +]) + +43 + } +} + +45  + gGDDR5 +:: + $£t_chªÃl_numb” +( +chªÃl +) { + +46 +Üg_’Œy +. +couÁ +[( +Lev– +:: +ChªÃl +)] = +chªÃl +; + +47 + } +} + +49  + gGDDR5 +:: + $£t_¿nk_numb” +( +¿nk +) { + +50 + `as£¹ +(( +¿nk + == 1) && "GDDR5„ank‚umber is fixedo 1."); + +51 + } +} + +53  + gGDDR5 +:: + $š™_¥“d +() + +55 cÚ¡  +REFIL_TABLE +[( +S³ed +:: +MAX +)] = {3900, 4388, 4875, 5363, 5850, 6338, 6825}; + +56 cÚ¡  +REFIS_TABLE +[( +S³ed +:: +MAX +)] = {1900, 2138, 2375, 2613, 2850, 3088, 3325}; + +57 cÚ¡  +RFC_TABLE +[5][( +S³ed +:: +MAX +)] = { + +65  +¥“d + = 0, +d’s™y + = 0; + +66  +¥“d_’Œy +. +¿‹ +){ + +67 4000: +¥“d + = 0; ; + +68 4500: +¥“d + = 1; ; + +69 5000: +¥“d + = 2; ; + +70 5500: +¥“d + = 3; ; + +71 6000: +¥“d + = 4; ; + +72 6500: +¥“d + = 5; ; + +73 7000: +¥“d + = 6; ; + +74 : + `as£¹ +(0); + +76  +Üg_’Œy +. +size + >> 9){ + +77 1: +d’s™y + = 0; ; + +78 2: +d’s™y + = 1; ; + +79 4: +d’s™y + = 2; ; + +80 8: +d’s™y + = 3; ; + +81 16: +d’s™y + = 4; ; + +82 : + `as£¹ +(0); + +84 ià( +Üg_’Œy +. +size + <ð1024è +¥“d_’Œy +. +nREFI + = +REFIL_TABLE +[ +¥“d +]; + +85 +¥“d_’Œy +. +nREFI + = +REFIS_TABLE +[ +¥“d +]; + +86 +¥“d_’Œy +. +nRFC + = +RFC_TABLE +[ +d’s™y +][ +¥“d +]; + +87 + } +} + +90  + gGDDR5 +:: + $š™_´”eq +() + +93 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +GDDR5 +>* +node +, Commªd +cmd +,  +id +) { + +94 ( +node +-> +¡©e +)) { + +95 ( +S‹ +:: +Pow”Up +):  +Commªd +:: +MAX +; + +96 ( +S‹ +:: +AùPow”Down +):  +Commªd +:: +PDX +; + +97 ( +S‹ +:: +P»Pow”Down +):  +Commªd +:: +PDX +; + +98 ( +S‹ +:: +S–fReäesh +):  +Commªd +:: +SRX +; + +99 : + `as£¹ +( +çl£ +); + +101 +´”eq +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +GDDR5 +>* +node +, Commªd +cmd +,  +id +) { + +102 ( +node +-> +¡©e +)) { + +103 ( +S‹ +:: +Clo£d +):  +Commªd +:: +ACT +; + +104 ( +S‹ +:: +O³Ãd +): + +105 ià( +node +-> +row_¡©e +. + `fšd +( +id +è!ðnode->row_¡©e. + `’d +()) + +106  +cmd +; + +107  +Commªd +:: +PRE +; + +108 : + `as£¹ +( +çl£ +); + +112 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +WR +)] =…»»q[(Lev–::Rªk)][(Commªd:: +RD +)]; + +113 +´”eq +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] =…»»q[(Lev–::Bªk)][(Commªd:: +RD +)]; + +116 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +REF +)] = [] ( +DRAM +< +GDDR5 +>* +node +, Commªd +cmd +,  +id +) { + +117 autØ +bg + : +node +-> +chžd»n +) + +118 autØ +bªk + : +bg +-> +chžd»n +) { + +119 ià( +bªk +-> +¡©e + =ð +S‹ +:: +Clo£d +) + +121  +Commªd +:: +PREA +; + +123  +Commªd +:: +REF +;}; + +126 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PDE +)] = [] ( +DRAM +< +GDDR5 +>* +node +, Commªd +cmd +,  +id +) { + +127 ( +node +-> +¡©e +)) { + +128 ( +S‹ +:: +Pow”Up +):  +Commªd +:: +PDE +; + +129 ( +S‹ +:: +AùPow”Down +):  +Commªd +:: +PDE +; + +130 ( +S‹ +:: +P»Pow”Down +):  +Commªd +:: +PDE +; + +131 ( +S‹ +:: +S–fReäesh +):  +Commªd +:: +SRX +; + +132 : + `as£¹ +( +çl£ +); + +136 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +SRE +)] = [] ( +DRAM +< +GDDR5 +>* +node +, Commªd +cmd +,  +id +) { + +137 ( +node +-> +¡©e +)) { + +138 ( +S‹ +:: +Pow”Up +):  +Commªd +:: +SRE +; + +139 ( +S‹ +:: +AùPow”Down +):  +Commªd +:: +PDX +; + +140 ( +S‹ +:: +P»Pow”Down +):  +Commªd +:: +PDX +; + +141 ( +S‹ +:: +S–fReäesh +):  +Commªd +:: +SRE +; + +142 : + `as£¹ +( +çl£ +); + +144 + } +} + +147  + gGDDR5 +:: + $š™_rowh™ +() + +150 +rowh™ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +GDDR5 +>* +node +, Commªd +cmd +,  +id +) { + +151 ( +node +-> +¡©e +)) { + +152 ( +S‹ +:: +Clo£d +):  +çl£ +; + +153 ( +S‹ +:: +O³Ãd +): + +154 ià( +node +-> +row_¡©e +. + `fšd +( +id +è!ðnode->row_¡©e. + `’d +()) + +155  +Œue +; + +156  +çl£ +; + +157 : + `as£¹ +( +çl£ +); + +161 +rowh™ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] =„owh™[(Lev–::Bªk)][(Commªd:: +RD +)]; + +162 + } +} + +164  + gGDDR5 +:: + $š™_rowÝ’ +() + +167 +rowÝ’ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +GDDR5 +>* +node +, Commªd +cmd +,  +id +) { + +168 ( +node +-> +¡©e +)) { + +169 ( +S‹ +:: +Clo£d +):  +çl£ +; + +170 ( +S‹ +:: +O³Ãd +):  +Œue +; + +171 : + `as£¹ +( +çl£ +); + +175 +rowÝ’ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] =„owÝ’[(Lev–::Bªk)][(Commªd:: +RD +)]; + +176 + } +} + +178  + gGDDR5 +:: + $š™_Ïmbda +() + +180 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +ACT +)] = [] ( +DRAM +< +GDDR5 +>* +node +,  +id +) { + +181 +node +-> +¡©e + = +S‹ +:: +O³Ãd +; + +182 +node +-> +row_¡©e +[ +id +] = +S‹ +:: +O³Ãd +;}; + +183 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +PRE +)] = [] ( +DRAM +< +GDDR5 +>* +node +,  +id +) { + +184 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +185 +node +-> +row_¡©e +. + `þ—r +();}; + +186 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PREA +)] = [] ( +DRAM +< +GDDR5 +>* +node +,  +id +) { + +187 autØ +bg + : +node +-> +chžd»n +) + +188 autØ +bªk + : +bg +-> +chžd»n +) { + +189 +bªk +-> +¡©e + = +S‹ +:: +Clo£d +; + +190 +bªk +-> +row_¡©e +. + `þ—r +();}}; + +191 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +REF +)] = [] ( +DRAM +< +GDDR5 +>* +node +,  +id +) {}; + +192 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +GDDR5 +>* +node +,  +id +) {}; + +193 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] = [] ( +DRAM +< +GDDR5 +>* +node +,  +id +) {}; + +194 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RDA +)] = [] ( +DRAM +< +GDDR5 +>* +node +,  +id +) { + +195 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +196 +node +-> +row_¡©e +. + `þ—r +();}; + +197 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WRA +)] = [] ( +DRAM +< +GDDR5 +>* +node +,  +id +) { + +198 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +199 +node +-> +row_¡©e +. + `þ—r +();}; + +200 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PDE +)] = [] ( +DRAM +< +GDDR5 +>* +node +,  +id +) { + +201 autØ +bg + : +node +-> +chžd»n +) + +202 autØ +bªk + : +bg +-> +chžd»n +) { + +203 ià( +bªk +-> +¡©e + =ð +S‹ +:: +Clo£d +) + +205 +node +-> +¡©e + = +S‹ +:: +AùPow”Down +; + +208 +node +-> +¡©e + = +S‹ +:: +P»Pow”Down +;}; + +209 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PDX +)] = [] ( +DRAM +< +GDDR5 +>* +node +,  +id +) { + +210 +node +-> +¡©e + = +S‹ +:: +Pow”Up +;}; + +211 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +SRE +)] = [] ( +DRAM +< +GDDR5 +>* +node +,  +id +) { + +212 +node +-> +¡©e + = +S‹ +:: +S–fReäesh +;}; + +213 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +SRX +)] = [] ( +DRAM +< +GDDR5 +>* +node +,  +id +) { + +214 +node +-> +¡©e + = +S‹ +:: +Pow”Up +;}; + +215 + } +} + +218  + gGDDR5 +:: + $š™_timšg +() + +220 +S³edEÁry +& +s + = +¥“d_’Œy +; + +221 +veùÜ +< +TimšgEÁry +> * +t +; + +224 +t + = +timšg +[( +Lev– +:: +ChªÃl +)]; + +227 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nBL +}); + +228 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nBL +}); + +229 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nBL +}); + +230 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd::RDA, 1, +s +. +nBL +}); + +231 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd::WR, 1, +s +. +nBL +}); + +232 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nBL +}); + +233 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nBL +}); + +234 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd::WRA, 1, +s +. +nBL +}); + +238 +t + = +timšg +[( +Lev– +:: +Rªk +)]; + +241 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nCCDS +}); + +242 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCCDS +}); + +243 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCCDS +}); + +244 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd::RDA, 1, +s +. +nCCDS +}); + +245 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd::WR, 1, +s +. +nCCDS +}); + +246 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCCDS +}); + +247 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCCDS +}); + +248 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd::WRA, 1, +s +. +nCCDS +}); + +249 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nCCDS + + 2 - s. +nCWL +}); + +250 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCL + + s. +nCCDS + + 2 - s. +nCWL +}); + +251 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nCCDS + + 2 - s. +nCWL +}); + +252 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCL + + s. +nCCDS + + 2 - s. +nCWL +}); + +253 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTR +}); + +254 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTR +}); + +255 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTR +}); + +256 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTR +}); + +258 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PREA +, 1, +s +. +nRTP +}); + +259 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PREA +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +}); + +262 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nCL + + s. +nBL + + 1}); + +263 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nCL + + s. +nBL + + 1}); + +264 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +}); + +265 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR + + 1}); + +266 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nXPN +}); + +267 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nXPN +}); + +268 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nXPN +}); + +269 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nXPN +}); + +274 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 1, +s +. +nRRD +}); + +275 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 4, +s +. +nFAW +}); + +276 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 32, +s +. +n32AW +}); + +277 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PREA +, 1, +s +. +nRAS +}); + +278 +t +[( +Commªd +:: +PREA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRP +}); + +279 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd::PRE, 1, +s +. +nPPD +}); + +282 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nRP +}); + +283 +t +[( +Commªd +:: +PREA +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nRP +}); + +284 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRFC +}); + +287 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PDE +, 1, 1}); + +288 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nXPN +}); + +289 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nXPN +}); + +290 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PREA +, 1, +s +. +nXPN +}); + +293 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nRP +}); + +294 +t +[( +Commªd +:: +PREA +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nRP +}); + +295 +t +[( +Commªd +:: +SRX +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nXS +}); + +298 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd::REF, 1, +s +. +nRFC +}); + +301 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd:: +PDE +, 1, 1}); + +302 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nXPN +}); + +305 +t +[( +Commªd +:: +SRX +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nXS +}); + +308 +t +[( +Commªd +:: +PDE +)]. + `push_back +({Commªd:: +PDX +, 1, +s +. +nPD +}); + +309 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nXPN +}); + +312 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nXPN +}); + +313 +t +[( +Commªd +:: +SRX +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nXS +}); + +316 +t +[( +Commªd +:: +SRE +)]. + `push_back +({Commªd:: +SRX +, 1, +s +. +nCKESR +}); + +317 +t +[( +Commªd +:: +SRX +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nXS +}); + +321 +t + = +timšg +[( +Lev– +:: +BªkGroup +)]; + +323 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nCCDL +}); + +324 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCCDL +}); + +325 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCCDL +}); + +326 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd::RDA, 1, +s +. +nCCDL +}); + +327 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd::WR, 1, +s +. +nCCDL +}); + +328 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCCDL +}); + +329 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCCDL +}); + +330 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd::WRA, 1, +s +. +nCCDL +}); + +331 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd::WR, 1, +s +. +nCCDL +}); + +332 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCCDL +}); + +333 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCCDL +}); + +334 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd::WRA, 1, +s +. +nCCDL +}); + +337 +t + = +timšg +[( +Lev– +:: +Bªk +)]; + +340 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nRCDR +}); + +341 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nRCDR +}); + +342 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nRCDW +}); + +343 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nRCDW +}); + +345 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nRTP +}); + +346 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +}); + +348 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRTP + + s. +nRP +}); + +349 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR + + s. +nRP +}); + +352 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 1, +s +. +nRC +}); + +353 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nRAS +}); + +354 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRP +}); + +355 + } +} + + @GDDR5.h + +1 #iâdeà +__GDDR5_H + + +2  + #__GDDR5_H + + + ) + +4  + ~"DRAM.h +" + +5  + ~"Reque¡.h +" + +6  + ~ + +7  + ~ + +9 +usšg + +Çme¥aû + + g¡d +; + +11 +Çme¥aû + + g¿muÏtÜ + + +14 þas  + cGDDR5 + + +16 + gpublic +: + +17  +¡ršg + +¡ªd¬d_Çme +; + +18 +þass + + gOrg +; + +19 +þass + + gS³ed +; + +20 +GDDR5 +( +Org + +Üg +, +S³ed + +¥“d +); + +21 +GDDR5 +(cÚ¡ +¡ršg +& +Üg_¡r +, cÚ¡ sŒšg& +¥“d_¡r +); + +23  + gm­ +< + g¡ršg +, + gOrg +> + gÜg_m­ +; + +24  + gm­ +< + g¡ršg +, + gS³ed +> + g¥“d_m­ +; + +27 þas  + cLev– + :  + +29 +ChªÃl +, + gRªk +, + gBªkGroup +, + gBªk +, + gRow +, + gCÞumn +, + gMAX + + +33 þas  + cCommªd + :  + +35 +ACT +, + gPRE +, + gPREA +, + +36 + gRD +, + gWR +, + gRDA +, + gWRA +, + +37 + gREF +, + gPDE +, + gPDX +, + gSRE +, + gSRX +, + +38 + gMAX + + +41 +¡ršg + + gcommªd_Çme +[( +Commªd +:: +MAX +)] = { + +47 +Lev– + + gscÝe +[( +Commªd +:: +MAX +)] = { + +48 +Lev– +:: +Row +, Lev–:: +Bªk +, Lev–:: +Rªk +, + +49 +Lev– +:: +CÞumn +, Level::Column, Level::Column, Level::Column, + +50 +Lev– +:: +Rªk +, Level::Rank, Level::Rank, Level::Rank, Level::Rank + +53 +boÞ + +is_Ý’šg +( +Commªd + +cmd +) + +55 ( + gcmd +)) { + +56 ( + gCommªd +:: +ACT +): + +57  +Œue +; + +59  +çl£ +; + +63 +boÞ + +is_acûssšg +( +Commªd + +cmd +) + +65 ( + gcmd +)) { + +66 ( + gCommªd +:: +RD +): + +67 ( +Commªd +:: +WR +): + +68 ( +Commªd +:: +RDA +): + +69 ( +Commªd +:: +WRA +): + +70  +Œue +; + +72  +çl£ +; + +76 +boÞ + +is_þosšg +( +Commªd + +cmd +) + +78 ( + gcmd +)) { + +79 ( + gCommªd +:: +RDA +): + +80 ( +Commªd +:: +WRA +): + +81 ( +Commªd +:: +PRE +): + +82 ( +Commªd +:: +PREA +): + +83  +Œue +; + +85  +çl£ +; + +89 +boÞ + +is_»äeshšg +( +Commªd + +cmd +) + +91 ( + gcmd +)) { + +92 ( + gCommªd +:: +REF +): + +93  +Œue +; + +95  +çl£ +; + +101 þas  + cS‹ + :  + +103 +O³Ãd +, + gClo£d +, + gPow”Up +, + gAùPow”Down +, + gP»Pow”Down +, + gS–fReäesh +, + gMAX + + +104 } + g¡¬t +[( +Lev– +:: +MAX +)] = { + +105 +S‹ +:: +MAX +, S‹:: +Pow”Up +, S‹::MAX, S‹:: +Clo£d +, State::Closed, State::MAX + +109 +Commªd + + gŒª¦©e +[( +Reque¡ +:: +Ty³ +:: +MAX +)] = { + +110 +Commªd +:: +RD +, Commªd:: +WR +, + +111 +Commªd +:: +REF +, Commªd:: +PDE +, Commªd:: +SRE + + +115 + gfunùiÚ +< +Commªd +( +DRAM +< +GDDR5 +>*, Commªd +cmd +, )> + g´”eq +[( +Lev– +:: +MAX +)][(Command::MAX)]; + +119 + gfunùiÚ +< +boÞ +( +DRAM +< +GDDR5 +>*, +Commªd + +cmd +, )> + growh™ +[( +Lev– +:: +MAX +)][(Command::MAX)]; + +120 + gfunùiÚ +< +boÞ +( +DRAM +< +GDDR5 +>*, +Commªd + +cmd +, )> + growÝ’ +[( +Lev– +:: +MAX +)][(Command::MAX)]; + +123  + sTimšgEÁry + + +125 +Commªd + + gcmd +; + +126  + gdi¡ +; + +127  + gv® +; + +128 +boÞ + + gsiblšg +; + +130 + gveùÜ +< + gTimšgEÁry +> + gtimšg +[( +Lev– +:: +MAX +)][( +Commªd +::MAX)]; + +133 + gfunùiÚ +<( + gDRAM +< + gGDDR5 +>*, )> + gÏmbda +[( +Lev– +:: +MAX +)][( +Commªd +::MAX)]; + +136 þas  + cOrg + :  + +138 +GDDR5_512Mb_x16 +, + gGDDR5_512Mb_x32 +, + +139 + gGDDR5_1Gb_x16 +, + gGDDR5_1Gb_x32 +, + +140 + gGDDR5_2Gb_x16 +, + gGDDR5_2Gb_x32 +, + +141 + gGDDR5_4Gb_x16 +, + gGDDR5_4Gb_x32 +, + +142 + gGDDR5_8Gb_x16 +, + gGDDR5_8Gb_x32 +, + +143 + gMAX + + +146  + sOrgEÁry + { + +147  + gsize +; + +148  + gdq +; + +149  + gcouÁ +[( +Lev– +:: +MAX +)]; + +150 } + gÜg_bË +[( +Org +:: +MAX +)] = { + +159 }, + gÜg_’Œy +; + +161  +£t_chªÃl_numb” +( +chªÃl +); + +162  +£t_¿nk_numb” +( +¿nk +); + +165 þas  + cS³ed + :  + +167 +GDDR5_4000 +, + gGDDR5_4500 +, + +168 + gGDDR5_5000 +, + gGDDR5_5500 +, + +169 + gGDDR5_6000 +, + gGDDR5_6500 +, + +170 + gGDDR5_7000 +, + +171 + gMAX + + +174  + g´eãtch_size + = 8; + +175  + gchªÃl_width + = 64; + +177  + sS³edEÁry + { + +178  + g¿‹ +; + +179  + gäeq +, + gtCK +; + +180  + gnBL +, + gnCCDS +, + gnCCDL +; + +181  + gnCL +, + gnRCDR +, + gnRCDW +, + gnRP +, + gnCWL +; + +182  + gnRAS +, + gnRC +; + +183  + gnPPD +, + gnRTP +, + gnWTR +, + gnWR +; + +184  + gnRRD +, + gnFAW +, + gn32AW +; + +185  + gnRFC +, + gnREFI +; + +186  + gnPD +, + gnXPN +, + gnLK +; + +187  + gnCKESR +, + gnXS +, + gnXSDLL +; + +188 } + g¥“d_bË +[( +S³ed +:: +MAX +)] = { + +196 }, + g¥“d_’Œy +; + +198  + g»ad_Ï‹ncy +; + +200 + g´iv©e +: + +201  +š™_¥“d +(); + +202  +š™_Ïmbda +(); + +203  +š™_´”eq +(); + +204  +š™_rowh™ +(); + +205  +š™_rowÝ’ +(); + +206  +š™_timšg +(); + + @Gem5Wrapper.cpp + +1  + ~ + +3  + ~"Gem5W¿µ”.h +" + +4  + ~"CÚfig.h +" + +5  + ~"Reque¡.h +" + +6  + ~"MemÜyFaùÜy.h +" + +7  + ~"MemÜy.h +" + +8  + ~"DDR3.h +" + +9  + ~"DDR4.h +" + +10  + ~"LPDDR3.h +" + +11  + ~"LPDDR4.h +" + +12  + ~"GDDR5.h +" + +13  + ~"WideIO.h +" + +14  + ~"WideIO2.h +" + +15  + ~"HBM.h +" + +16  + ~"SALP.h +" + +18 +usšg + +Çme¥aû + + g¿muÏtÜ +; + +20  + gm­ +< + g¡ršg +, + gfunùiÚ +< + gMemÜyBa£ + *(cÚ¡ + gCÚfig +&, )> > + gÇme_to_func + = { + +21 {"DDR3", & +MemÜyFaùÜy +< +DDR3 +>:: +ü—‹ +}, {"DDR4", &MemÜyFaùÜy< +DDR4 +>::create}, + +22 {"LPDDR3", & +MemÜyFaùÜy +< +LPDDR3 +>:: +ü—‹ +}, {"LPDDR4", &MemÜyFaùÜy< +LPDDR4 +>::create}, + +23 {"GDDR5", & +MemÜyFaùÜy +< +GDDR5 +>:: +ü—‹ +}, + +24 {"WideIO", & +MemÜyFaùÜy +< +WideIO +>:: +ü—‹ +}, {"WideIO2", &MemÜyFaùÜy< +WideIO2 +>::create}, + +25 {"HBM", & +MemÜyFaùÜy +< +HBM +>:: +ü—‹ +}, + +26 {"SALP-1", & +MemÜyFaùÜy +< +SALP +>:: +ü—‹ +}, {"SALP-2", &MemoryFactory::create}, {"SALP-MASA", &MemoryFactory::create}, + +30 + gGem5W¿µ” +:: + $Gem5W¿µ” +(cÚ¡ +CÚfig +& +cÚfigs +,  +ÿch–še +) + +32 cÚ¡ +¡ršg +& +¡d_Çme + = +cÚfigs +["standard"]; + +33 + `as£¹ +( +Çme_to_func +. + `fšd +( +¡d_Çme +è!ðÇme_to_func. + `’d +() && "unrecognized standard‚ame"); + +34 +mem + = +Çme_to_func +[ +¡d_Çme +]( +cÚfigs +, +ÿch–še +); + +35 +tCK + = +mem +-> + `þk_ns +(); + +36 + } +} + +39 + gGem5W¿µ” +::~ + $Gem5W¿µ” +() { + +40 +d–‘e + +mem +; + +41 + } +} + +43  + gGem5W¿µ” +:: + $tick +() + +45 +mem +-> + `tick +(); + +46 + } +} + +48 +boÞ + + gGem5W¿µ” +:: + $£nd +( +Reque¡ + +»q +) + +50  +mem +-> + `£nd +( +»q +); + +51 + } +} + +53  + gGem5W¿µ” +:: + $fšish +() { + +54 +mem +-> + `fšish +(); + +55 + } +} + + @Gem5Wrapper.h + +1 #iâdeà +__GEM5_WRAPPER_H + + +2  + #__GEM5_WRAPPER_H + + + ) + +4  + ~<¡ršg +> + +6  + ~"CÚfig.h +" + +8 +usšg + +Çme¥aû + + g¡d +; + +10 +Çme¥aû + + g¿muÏtÜ + + +13 +þass + + gReque¡ +; + +14 +þass + + gMemÜyBa£ +; + +16 þas  + cGem5W¿µ” + + +18 + g´iv©e +: + +19 +MemÜyBa£ + * +mem +; + +20 + gpublic +: + +21  +tCK +; + +22 +Gem5W¿µ” +(cÚ¡ +CÚfig +& +cÚfigs +,  +ÿch–še +); + +23 ~ +Gem5W¿µ” +(); + +24  +tick +(); + +25 +boÞ + +£nd +( +Reque¡ + +»q +); + +26  +fšish +(); + + @HBM.cpp + +1  + ~"HBM.h +" + +2  + ~"DRAM.h +" + +4  + ~ + +5  + ~ + +6  + ~<ÿs£¹ +> + +8 +usšg + +Çme¥aû + + g¡d +; + +9 +usšg + +Çme¥aû + + g¿muÏtÜ +; + +11 +¡ršg + + gHBM +:: +¡ªd¬d_Çme + = "HBM"; + +13 + gm­ +< + g¡ršg +, + gHBM +:: +Org +> +HBM +:: +Üg_m­ + = { + +14 {"HBM_1Gb", +HBM +:: +Org +:: +HBM_1Gb +}, + +15 {"HBM_2Gb", +HBM +:: +Org +:: +HBM_2Gb +}, + +16 {"HBM_4Gb", +HBM +:: +Org +:: +HBM_4Gb +}, + +19 + gm­ +< + g¡ršg +, + gHBM +:: +S³ed +> +HBM +:: +¥“d_m­ + = { + +20 {"HBM_1Gbps", +HBM +:: +S³ed +:: +HBM_1Gbps +}, + +23 + gHBM +:: + $HBM +( +Org + +Üg +, +S³ed + +¥“d +) + +24 : + `Üg_’Œy +( +Üg_bË +[( +Üg +)]), + +25 + `¥“d_’Œy +( +¥“d_bË +[( +¥“d +)]), + +26 + `»ad_Ï‹ncy +( +¥“d_’Œy +. +nCL + + s³ed_’Œy. +nBL +) + +28 + `š™_¥“d +(); + +29 + `š™_´”eq +(); + +30 + `š™_rowh™ +(); + +31 + `š™_rowÝ’ +(); + +32 + `š™_Ïmbda +(); + +33 + `š™_timšg +(); + +34 + } +} + +36 + gHBM +:: + $HBM +(cÚ¡ +¡ršg +& +Üg_¡r +, cÚ¡ sŒšg& +¥“d_¡r +) : + +37 + $HBM +( +Üg_m­ +[ +Üg_¡r +], +¥“d_m­ +[ +¥“d_¡r +]) + +39 + } +} + +41  + gHBM +:: + $£t_chªÃl_numb” +( +chªÃl +) { + +42 +Üg_’Œy +. +couÁ +[( +Lev– +:: +ChªÃl +)] = +chªÃl +; + +43 + } +} + +45  + gHBM +:: + $£t_¿nk_numb” +( +¿nk +) { + +46 +Üg_’Œy +. +couÁ +[( +Lev– +:: +Rªk +)] = +¿nk +; + +47 + } +} + +50  + gHBM +:: + $š™_¥“d +() + +52 cÚ¡  +RFC_TABLE +[( +S³ed +:: +MAX +)][( +Org +::MAX)] = { + +55 cÚ¡  +REFI1B_TABLE +[( +S³ed +:: +MAX +)][( +Org +::MAX)] = { + +58 cÚ¡  +XS_TABLE +[( +S³ed +:: +MAX +)][( +Org +::MAX)] = { + +62  +¥“d + = 0, +d’s™y + = 0; + +63  +¥“d_’Œy +. +¿‹ +) { + +64 1000: +¥“d + = 0; ; + +65 : + `as£¹ +( +çl£ +); + +67  +Üg_’Œy +. +size + >> 10){ + +68 1: +d’s™y + = 0; ; + +69 2: +d’s™y + = 1; ; + +70 4: +d’s™y + = 2; ; + +71 : + `as£¹ +( +çl£ +); + +73 +¥“d_’Œy +. +nRFC + = +RFC_TABLE +[ +¥“d +][ +d’s™y +]; + +74 +¥“d_’Œy +. +nREFI1B + = +REFI1B_TABLE +[ +¥“d +][ +d’s™y +]; + +75 +¥“d_’Œy +. +nXS + = +XS_TABLE +[ +¥“d +][ +d’s™y +]; + +76 + } +} + +79  + gHBM +:: + $š™_´”eq +() + +82 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +HBM +>* +node +, Commªd +cmd +,  +id +) { + +83 ( +node +-> +¡©e +)) { + +84 ( +S‹ +:: +Pow”Up +):  +Commªd +:: +MAX +; + +85 ( +S‹ +:: +AùPow”Down +):  +Commªd +:: +PDX +; + +86 ( +S‹ +:: +P»Pow”Down +):  +Commªd +:: +PDX +; + +87 ( +S‹ +:: +S–fReäesh +):  +Commªd +:: +SRX +; + +88 : + `as£¹ +( +çl£ +); + +90 +´”eq +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +HBM +>* +node +, Commªd +cmd +,  +id +) { + +91 ( +node +-> +¡©e +)) { + +92 ( +S‹ +:: +Clo£d +):  +Commªd +:: +ACT +; + +93 ( +S‹ +:: +O³Ãd +): + +94 ià( +node +-> +row_¡©e +. + `fšd +( +id +è!ðnode->row_¡©e. + `’d +()) + +95  +cmd +; + +96  +Commªd +:: +PRE +; + +97 : + `as£¹ +( +çl£ +); + +101 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +WR +)] =…»»q[(Lev–::Rªk)][(Commªd:: +RD +)]; + +102 +´”eq +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] =…»»q[(Lev–::Bªk)][(Commªd:: +RD +)]; + +105 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +REF +)] = [] ( +DRAM +< +HBM +>* +node +, Commªd +cmd +,  +id +) { + +106 autØ +bg + : +node +-> +chžd»n +) + +107 autØ +bªk +: +bg +-> +chžd»n +) { + +108 ià( +bªk +-> +¡©e + =ð +S‹ +:: +Clo£d +) + +110  +Commªd +:: +PREA +; + +112  +Commªd +:: +REF +;}; + +115 +´”eq +[( +Lev– +:: +Bªk +)][( +Commªd +:: +REFSB +)] = [] ( +DRAM +< +HBM +>* +node +, Commªd +cmd +,  +id +) { + +116 ià( +node +-> +¡©e + =ð +S‹ +:: +Clo£d +è +Commªd +:: +REFSB +; + +117  +Commªd +:: +PRE +;}; + +120 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PDE +)] = [] ( +DRAM +< +HBM +>* +node +, Commªd +cmd +,  +id +) { + +121 ( +node +-> +¡©e +)) { + +122 ( +S‹ +:: +Pow”Up +):  +Commªd +:: +PDE +; + +123 ( +S‹ +:: +AùPow”Down +):  +Commªd +:: +PDE +; + +124 ( +S‹ +:: +P»Pow”Down +):  +Commªd +:: +PDE +; + +125 ( +S‹ +:: +S–fReäesh +):  +Commªd +:: +SRX +; + +126 : + `as£¹ +( +çl£ +); + +130 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +SRE +)] = [] ( +DRAM +< +HBM +>* +node +, Commªd +cmd +,  +id +) { + +131 ( +node +-> +¡©e +)) { + +132 ( +S‹ +:: +Pow”Up +):  +Commªd +:: +SRE +; + +133 ( +S‹ +:: +AùPow”Down +):  +Commªd +:: +PDX +; + +134 ( +S‹ +:: +P»Pow”Down +):  +Commªd +:: +PDX +; + +135 ( +S‹ +:: +S–fReäesh +):  +Commªd +:: +SRE +; + +136 : + `as£¹ +( +çl£ +); + +138 + } +} + +141  + gHBM +:: + $š™_rowh™ +() + +144 +rowh™ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +HBM +>* +node +, Commªd +cmd +,  +id +) { + +145 ( +node +-> +¡©e +)) { + +146 ( +S‹ +:: +Clo£d +):  +çl£ +; + +147 ( +S‹ +:: +O³Ãd +): + +148 ià( +node +-> +row_¡©e +. + `fšd +( +id +è!ðnode->row_¡©e. + `’d +()) + +149  +Œue +; + +150  +çl£ +; + +151 : + `as£¹ +( +çl£ +); + +155 +rowh™ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] =„owh™[(Lev–::Bªk)][(Commªd:: +RD +)]; + +156 + } +} + +158  + gHBM +:: + $š™_rowÝ’ +() + +161 +rowÝ’ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +HBM +>* +node +, Commªd +cmd +,  +id +) { + +162 ( +node +-> +¡©e +)) { + +163 ( +S‹ +:: +Clo£d +):  +çl£ +; + +164 ( +S‹ +:: +O³Ãd +):  +Œue +; + +165 : + `as£¹ +( +çl£ +); + +169 +rowÝ’ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] =„owÝ’[(Lev–::Bªk)][(Commªd:: +RD +)]; + +170 + } +} + +172  + gHBM +:: + $š™_Ïmbda +() + +174 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +ACT +)] = [] ( +DRAM +< +HBM +>* +node +,  +id +) { + +175 +node +-> +¡©e + = +S‹ +:: +O³Ãd +; + +176 +node +-> +row_¡©e +[ +id +] = +S‹ +:: +O³Ãd +;}; + +177 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +PRE +)] = [] ( +DRAM +< +HBM +>* +node +,  +id +) { + +178 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +179 +node +-> +row_¡©e +. + `þ—r +();}; + +180 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PREA +)] = [] ( +DRAM +< +HBM +>* +node +,  +id +) { + +181 autØ +bg + : +node +-> +chžd»n +) + +182 autØ +bªk + : +bg +-> +chžd»n +) { + +183 +bªk +-> +¡©e + = +S‹ +:: +Clo£d +; + +184 +bªk +-> +row_¡©e +. + `þ—r +(); + +186 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +REF +)] = [] ( +DRAM +< +HBM +>* +node +,  +id +) {}; + +187 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +HBM +>* +node +,  +id +) {}; + +188 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] = [] ( +DRAM +< +HBM +>* +node +,  +id +) {}; + +189 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RDA +)] = [] ( +DRAM +< +HBM +>* +node +,  +id +) { + +190 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +191 +node +-> +row_¡©e +. + `þ—r +();}; + +192 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WRA +)] = [] ( +DRAM +< +HBM +>* +node +,  +id +) { + +193 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +194 +node +-> +row_¡©e +. + `þ—r +();}; + +195 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PDE +)] = [] ( +DRAM +< +HBM +>* +node +,  +id +) { + +196 autØ +bg + : +node +-> +chžd»n +) + +197 autØ +bªk + : +bg +-> +chžd»n +) { + +198 ià( +bªk +-> +¡©e + =ð +S‹ +:: +Clo£d +) + +200 +node +-> +¡©e + = +S‹ +:: +AùPow”Down +; + +203 +node +-> +¡©e + = +S‹ +:: +P»Pow”Down +;}; + +204 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PDX +)] = [] ( +DRAM +< +HBM +>* +node +,  +id +) { + +205 +node +-> +¡©e + = +S‹ +:: +Pow”Up +;}; + +206 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +SRE +)] = [] ( +DRAM +< +HBM +>* +node +,  +id +) { + +207 +node +-> +¡©e + = +S‹ +:: +S–fReäesh +;}; + +208 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +SRX +)] = [] ( +DRAM +< +HBM +>* +node +,  +id +) { + +209 +node +-> +¡©e + = +S‹ +:: +Pow”Up +;}; + +210 + } +} + +213  + gHBM +:: + $š™_timšg +() + +215 +S³edEÁry +& +s + = +¥“d_’Œy +; + +216 +veùÜ +< +TimšgEÁry +> * +t +; + +219 +t + = +timšg +[( +Lev– +:: +ChªÃl +)]; + +222 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nBL +}); + +223 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nBL +}); + +224 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nBL +}); + +225 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd::RDA, 1, +s +. +nBL +}); + +226 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd::WR, 1, +s +. +nBL +}); + +227 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nBL +}); + +228 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nBL +}); + +229 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd::WRA, 1, +s +. +nBL +}); + +233 +t + = +timšg +[( +Lev– +:: +Rªk +)]; + +236 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nCCDS +}); + +237 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCCDS +}); + +238 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCCDS +}); + +239 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd::RDA, 1, +s +. +nCCDS +}); + +240 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd::WR, 1, +s +. +nCCDS +}); + +241 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCCDS +}); + +242 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCCDS +}); + +243 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd::WRA, 1, +s +. +nCCDS +}); + +244 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nCCDS + + 2 - s. +nCWL +}); + +245 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCL + + s. +nCCDS + + 2 - s. +nCWL +}); + +246 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nCCDS + + 2 - s. +nCWL +}); + +247 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCL + + s. +nCCDS + + 2 - s. +nCWL +}); + +248 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTRS +}); + +249 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTRS +}); + +250 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTRS +}); + +251 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTRS +}); + +253 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PREA +, 1, +s +. +nRTP +}); + +254 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PREA +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +}); + +257 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nCL + + s. +nBL + + 1}); + +258 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nCL + + s. +nBL + + 1}); + +259 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +}); + +260 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR + + 1}); + +261 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nXP +}); + +262 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nXP +}); + +263 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nXP +}); + +264 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nXP +}); + +269 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 1, +s +. +nRRDS +}); + +270 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 4, +s +. +nFAW +}); + +271 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PREA +, 1, +s +. +nRAS +}); + +272 +t +[( +Commªd +:: +PREA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRP +}); + +275 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nRP +}); + +276 +t +[( +Commªd +:: +PREA +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nRP +}); + +277 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRFC +}); + +280 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PDE +, 1, 1}); + +281 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nXP +}); + +282 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nXP +}); + +283 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PREA +, 1, +s +. +nXP +}); + +286 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nRP +}); + +287 +t +[( +Commªd +:: +PREA +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nRP +}); + +288 +t +[( +Commªd +:: +SRX +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nXS +}); + +291 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd::REF, 1, +s +. +nRFC +}); + +294 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd:: +PDE +, 1, 1}); + +295 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nXP +}); + +298 +t +[( +Commªd +:: +SRX +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nXS +}); + +301 +t +[( +Commªd +:: +PDE +)]. + `push_back +({Commªd:: +PDX +, 1, +s +. +nPD +}); + +302 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nXP +}); + +305 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nXP +}); + +306 +t +[( +Commªd +:: +SRX +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nXS +}); + +309 +t +[( +Commªd +:: +SRE +)]. + `push_back +({Commªd:: +SRX +, 1, +s +. +nCKESR +}); + +310 +t +[( +Commªd +:: +SRX +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nXS +}); + +313 +t + = +timšg +[( +Lev– +:: +BªkGroup +)]; + +315 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nCCDL +}); + +316 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCCDL +}); + +317 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCCDL +}); + +318 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd::RDA, 1, +s +. +nCCDL +}); + +319 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd::WR, 1, +s +. +nCCDL +}); + +320 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCCDL +}); + +321 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCCDL +}); + +322 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd::WRA, 1, +s +. +nCCDL +}); + +323 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd::WR, 1, +s +. +nCCDL +}); + +324 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCCDL +}); + +325 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCCDL +}); + +326 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd::WRA, 1, +s +. +nCCDL +}); + +327 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTRL +}); + +328 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTRL +}); + +329 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTRL +}); + +330 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTRL +}); + +333 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 1, +s +. +nRRDL +}); + +336 +t + = +timšg +[( +Lev– +:: +Bªk +)]; + +339 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nRCDR +}); + +340 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nRCDR +}); + +341 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nRCDW +}); + +342 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nRCDW +}); + +344 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nRTP +}); + +345 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +}); + +347 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRTP + + s. +nRP +}); + +348 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR + + s. +nRP +}); + +351 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 1, +s +. +nRC +}); + +352 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nRAS +}); + +353 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRP +}); + +356 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +REFSB +, 1, +s +. +nRP +}); + +357 +t +[( +Commªd +:: +REFSB +)]. + `push_back +({Commªd::REFSB, 1, +s +. +nRFC +}); + +358 +t +[( +Commªd +:: +REFSB +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRFC +}); + +359 + } +} + + @HBM.h + +1 #iâdeà +__HBM_H + + +2  + #__HBM_H + + + ) + +4  + ~"DRAM.h +" + +5  + ~"Reque¡.h +" + +6  + ~ + +7  + ~ + +9 +usšg + +Çme¥aû + + g¡d +; + +11 +Çme¥aû + + g¿muÏtÜ + + +14 þas  + cHBM + + +16 + gpublic +: + +17  +¡ršg + +¡ªd¬d_Çme +; + +18 +þass + + gOrg +; + +19 +þass + + gS³ed +; + +20 +HBM +( +Org + +Üg +, +S³ed + +¥“d +); + +21 +HBM +(cÚ¡ +¡ršg +& +Üg_¡r +, cÚ¡ sŒšg& +¥“d_¡r +); + +23  + gm­ +< + g¡ršg +, + gOrg +> + gÜg_m­ +; + +24  + gm­ +< + g¡ršg +, + gS³ed +> + g¥“d_m­ +; + +27 þas  + cLev– + :  + +29 +ChªÃl +, + gRªk +, + gBªkGroup +, + gBªk +, + gRow +, + gCÞumn +, + gMAX + + +33 þas  + cCommªd + :  + +35 +ACT +, + gPRE +, + gPREA +, + +36 + gRD +, + gWR +, + gRDA +, + gWRA +, + +37 + gREF +, + gREFSB +, + gPDE +, + gPDX +, + gSRE +, + gSRX +, + +38 + gMAX + + +45 +¡ršg + + gcommªd_Çme +[( +Commªd +:: +MAX +)] = { + +51 +Lev– + + gscÝe +[( +Commªd +:: +MAX +)] = { + +52 +Lev– +:: +Row +, Lev–:: +Bªk +, Lev–:: +Rªk +, + +53 +Lev– +:: +CÞumn +, Level::Column, Level::Column, Level::Column, + +54 +Lev– +:: +Rªk +, Lev–:: +Bªk +, Level::Rank, Level::Rank, Level::Rank, Level::Rank + +57 +boÞ + +is_Ý’šg +( +Commªd + +cmd +) + +59 ( + gcmd +)) { + +60 ( + gCommªd +:: +ACT +): + +61  +Œue +; + +63  +çl£ +; + +67 +boÞ + +is_acûssšg +( +Commªd + +cmd +) + +69 ( + gcmd +)) { + +70 ( + gCommªd +:: +RD +): + +71 ( +Commªd +:: +WR +): + +72 ( +Commªd +:: +RDA +): + +73 ( +Commªd +:: +WRA +): + +74  +Œue +; + +76  +çl£ +; + +80 +boÞ + +is_þosšg +( +Commªd + +cmd +) + +82 ( + gcmd +)) { + +83 ( + gCommªd +:: +RDA +): + +84 ( +Commªd +:: +WRA +): + +85 ( +Commªd +:: +PRE +): + +86 ( +Commªd +:: +PREA +): + +87  +Œue +; + +89  +çl£ +; + +93 +boÞ + +is_»äeshšg +( +Commªd + +cmd +) + +95 ( + gcmd +)) { + +96 ( + gCommªd +:: +REF +): + +97 ( +Commªd +:: +REFSB +): + +98  +Œue +; + +100  +çl£ +; + +105 þas  + cS‹ + :  + +107 +O³Ãd +, + gClo£d +, + gPow”Up +, + gAùPow”Down +, + gP»Pow”Down +, + gS–fReäesh +, + gMAX + + +108 } + g¡¬t +[( +Lev– +:: +MAX +)] = { + +109 +S‹ +:: +MAX +, S‹:: +Pow”Up +, S‹::MAX, S‹:: +Clo£d +, State::Closed, State::MAX + +113 +Commªd + + gŒª¦©e +[( +Reque¡ +:: +Ty³ +:: +MAX +)] = { + +114 +Commªd +:: +RD +, Commªd:: +WR +, + +115 +Commªd +:: +REF +, Commªd:: +PDE +, Commªd:: +SRE + + +119 + gfunùiÚ +< +Commªd +( +DRAM +< +HBM +>*, Commªd +cmd +, )> + g´”eq +[( +Lev– +:: +MAX +)][(Command::MAX)]; + +123 + gfunùiÚ +< +boÞ +( +DRAM +< +HBM +>*, +Commªd + +cmd +, )> + growh™ +[( +Lev– +:: +MAX +)][(Command::MAX)]; + +124 + gfunùiÚ +< +boÞ +( +DRAM +< +HBM +>*, +Commªd + +cmd +, )> + growÝ’ +[( +Lev– +:: +MAX +)][(Command::MAX)]; + +127  + sTimšgEÁry + + +129 +Commªd + + gcmd +; + +130  + gdi¡ +; + +131  + gv® +; + +132 +boÞ + + gsiblšg +; + +134 + gveùÜ +< + gTimšgEÁry +> + gtimšg +[( +Lev– +:: +MAX +)][( +Commªd +::MAX)]; + +137 + gfunùiÚ +<( + gDRAM +< + gHBM +>*, )> + gÏmbda +[( +Lev– +:: +MAX +)][( +Commªd +::MAX)]; + +140 þas  + cOrg + :  + +142 +HBM_1Gb +, + +143 + gHBM_2Gb +, + +144 + gHBM_4Gb +, + +145 + gMAX + + +148  + sOrgEÁry + { + +149  + gsize +; + +150  + gdq +; + +151  + gcouÁ +[( +Lev– +:: +MAX +)]; + +152 } + gÜg_bË +[( +Org +:: +MAX +)] = { + +156 }, + gÜg_’Œy +; + +158  +£t_chªÃl_numb” +( +chªÃl +); + +159  +£t_¿nk_numb” +( +¿nk +); + +162 þas  + cS³ed + :  + +164 +HBM_1Gbps +, + +165 + gMAX + + +168  + g´eãtch_size + = 4; + +169  + gchªÃl_width + = 128; + +171  + sS³edEÁry + { + +172  + g¿‹ +; + +173  + gäeq +, + gtCK +; + +174  + gnBL +, + gnCCDS +, + gnCCDL +; + +175  + gnCL +, + gnRCDR +, + gnRCDW +, + gnRP +, + gnCWL +; + +176  + gnRAS +, + gnRC +; + +177  + gnRTP +, + gnWTRS +, + gnWTRL +, + gnWR +; + +178  + gnRRDS +, + gnRRDL +, + gnFAW +; + +179  + gnRFC +, + gnREFI +, + gnREFI1B +; + +180  + gnPD +, + gnXP +; + +181  + gnCKESR +, + gnXS +; + +182 } + g¥“d_bË +[( +S³ed +:: +MAX +)] = { + +184 }, + g¥“d_’Œy +; + +186  + g»ad_Ï‹ncy +; + +188 + g´iv©e +: + +189  +š™_¥“d +(); + +190  +š™_Ïmbda +(); + +191  +š™_´”eq +(); + +192  +š™_rowh™ +(); + +193  +š™_rowÝ’ +(); + +194  +š™_timšg +(); + + @LPDDR3.cpp + +1  + ~"LPDDR3.h +" + +2  + ~"DRAM.h +" + +4  + ~ + +5  + ~ + +6  + ~<ÿs£¹ +> + +8 +usšg + +Çme¥aû + + g¡d +; + +9 +usšg + +Çme¥aû + + g¿muÏtÜ +; + +11 +¡ršg + + gLPDDR3 +:: +¡ªd¬d_Çme + = "LPDDR3"; + +13 + gm­ +< + g¡ršg +, + gLPDDR3 +:: +Org +> +LPDDR3 +:: +Üg_m­ + = { + +14 {"LPDDR3_4Gb_x16", +LPDDR3 +:: +Org +:: +LPDDR3_4Gb_x16 +}, {"LPDDR3_4Gb_x32", LPDDR3::Org:: +LPDDR3_4Gb_x32 +}, + +15 {"LPDDR3_6Gb_x16", +LPDDR3 +:: +Org +:: +LPDDR3_6Gb_x16 +}, {"LPDDR3_6Gb_x32", LPDDR3::Org:: +LPDDR3_6Gb_x32 +}, + +16 {"LPDDR3_8Gb_x16", +LPDDR3 +:: +Org +:: +LPDDR3_8Gb_x16 +}, {"LPDDR3_8Gb_x32", LPDDR3::Org:: +LPDDR3_8Gb_x32 +}, + +17 {"LPDDR3_12Gb_x16", +LPDDR3 +:: +Org +:: +LPDDR3_12Gb_x16 +}, {"LPDDR3_12Gb_x32", LPDDR3::Org:: +LPDDR3_12Gb_x32 +}, + +18 {"LPDDR3_16Gb_x16", +LPDDR3 +:: +Org +:: +LPDDR3_16Gb_x16 +}, {"LPDDR3_16Gb_x32", LPDDR3::Org:: +LPDDR3_16Gb_x32 +}, + +21 + gm­ +< + g¡ršg +, + gLPDDR3 +:: +S³ed +> +LPDDR3 +:: +¥“d_m­ + = { + +22 {"LPDDR3_1333", +LPDDR3 +:: +S³ed +:: +LPDDR3_1333 +}, + +23 {"LPDDR3_1600", +LPDDR3 +:: +S³ed +:: +LPDDR3_1600 +}, + +24 {"LPDDR3_1866", +LPDDR3 +:: +S³ed +:: +LPDDR3_1866 +}, + +25 {"LPDDR3_2133", +LPDDR3 +:: +S³ed +:: +LPDDR3_2133 +}, + +28 + gLPDDR3 +:: + $LPDDR3 +( +Org + +Üg +, +S³ed + +¥“d +) + +29 : + `Üg_’Œy +( +Üg_bË +[( +Üg +)]), + +30 + `¥“d_’Œy +( +¥“d_bË +[( +¥“d +)]), + +31 + `»ad_Ï‹ncy +( +¥“d_’Œy +. +nCL + + s³ed_’Œy. +nDQSCK + + s³ed_’Œy. +nBL +) + +33 + `š™_¥“d +(); + +34 + `š™_´”eq +(); + +35 + `š™_rowh™ +(); + +36 + `š™_rowÝ’ +(); + +37 + `š™_Ïmbda +(); + +38 + `š™_timšg +(); + +39 + } +} + +41 + gLPDDR3 +:: + $LPDDR3 +(cÚ¡ +¡ršg +& +Üg_¡r +, cÚ¡ sŒšg& +¥“d_¡r +) : + +42 + $LPDDR3 +( +Üg_m­ +[ +Üg_¡r +], +¥“d_m­ +[ +¥“d_¡r +]) + +44 + } +} + +46  + gLPDDR3 +:: + $£t_chªÃl_numb” +( +chªÃl +) { + +47 +Üg_’Œy +. +couÁ +[( +Lev– +:: +ChªÃl +)] = +chªÃl +; + +48 + } +} + +50  + gLPDDR3 +:: + $£t_¿nk_numb” +( +¿nk +) { + +51 +Üg_’Œy +. +couÁ +[( +Lev– +:: +Rªk +)] = +¿nk +; + +52 + } +} + +54  + gLPDDR3 +:: + $š™_¥“d +() + +58 cÚ¡  +RFCPB_TABLE +[3][4] = { + +64 cÚ¡  +RFCAB_TABLE +[3][4] = { + +70 cÚ¡  +XSR_TABLE +[3][4] = { + +76  +¥“d + = 0, +d’s™y + = 0; + +77  +¥“d_’Œy +. +¿‹ +) { + +78 1333: +¥“d + = 0; ; + +79 1600: +¥“d + = 1; ; + +80 1866: +¥“d + = 2; ; + +81 2133: +¥“d + = 3; ; + +82 : + `as£¹ +( +çl£ +); + +84  +Üg_’Œy +. +size + >> 10){ + +85 4: +d’s™y + = 0; ; + +86 6: +d’s™y + = 1; ; + +87 8: +d’s™y + = 2; ; + +88 : + `as£¹ +( +çl£ + && "12Gb/16Gb is still TBD"); + +90 +¥“d_’Œy +. +nRFCpb + = +RFCPB_TABLE +[ +d’s™y +][ +¥“d +]; + +91 +¥“d_’Œy +. +nRFCab + = +RFCAB_TABLE +[ +d’s™y +][ +¥“d +]; + +92 +¥“d_’Œy +. +nXSR + = +XSR_TABLE +[ +d’s™y +][ +¥“d +]; + +93 + } +} + +96  + gLPDDR3 +:: + $š™_´”eq +() + +99 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +LPDDR3 +>* +node +, Commªd +cmd +,  +id +) { + +100 ( +node +-> +¡©e +)) { + +101 ( +S‹ +:: +Pow”Up +):  +Commªd +:: +MAX +; + +102 ( +S‹ +:: +AùPow”Down +):  +Commªd +:: +PDX +; + +103 ( +S‹ +:: +P»Pow”Down +):  +Commªd +:: +PDX +; + +104 ( +S‹ +:: +S–fReäesh +):  +Commªd +:: +SREFX +; + +105 : + `as£¹ +( +çl£ +); + +107 +´”eq +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +LPDDR3 +>* +node +, Commªd +cmd +,  +id +) { + +108 ( +node +-> +¡©e +)) { + +109 ( +S‹ +:: +Clo£d +):  +Commªd +:: +ACT +; + +110 ( +S‹ +:: +O³Ãd +): + +111 ià( +node +-> +row_¡©e +. + `fšd +( +id +è!ðnode->row_¡©e. + `’d +()) + +112  +cmd +; + +113  +Commªd +:: +PRE +; + +114 : + `as£¹ +( +çl£ +); + +118 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +WR +)] =…»»q[(Lev–::Rªk)][(Commªd:: +RD +)]; + +119 +´”eq +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] =…»»q[(Lev–::Bªk)][(Commªd:: +RD +)]; + +122 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +REF +)] = [] ( +DRAM +< +LPDDR3 +>* +node +, Commªd +cmd +,  +id +) { + +123 autØ +bªk + : +node +-> +chžd»n +) { + +124 ià( +bªk +-> +¡©e + =ð +S‹ +:: +Clo£d +) + +126  +Commªd +:: +PRA +; + +128  +Commªd +:: +REF +;}; + +131 +´”eq +[( +Lev– +:: +Bªk +)][( +Commªd +:: +REFPB +)] = [] ( +DRAM +< +LPDDR3 +>* +node +, Commªd +cmd +,  +id +) { + +132 ià( +node +-> +¡©e + =ð +S‹ +:: +Clo£d +è +Commªd +:: +REFPB +; + +133  +Commªd +:: +PRE +;}; + +136 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PD +)] = [] ( +DRAM +< +LPDDR3 +>* +node +, Commªd +cmd +,  +id +) { + +137 ( +node +-> +¡©e +)) { + +138 ( +S‹ +:: +Pow”Up +):  +Commªd +:: +PD +; + +139 ( +S‹ +:: +AùPow”Down +):  +Commªd +:: +PD +; + +140 ( +S‹ +:: +P»Pow”Down +):  +Commªd +:: +PD +; + +141 ( +S‹ +:: +S–fReäesh +):  +Commªd +:: +SREFX +; + +142 : + `as£¹ +( +çl£ +); + +146 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +SREF +)] = [] ( +DRAM +< +LPDDR3 +>* +node +, Commªd +cmd +,  +id +) { + +147 ( +node +-> +¡©e +)) { + +148 ( +S‹ +:: +Pow”Up +):  +Commªd +:: +SREF +; + +149 ( +S‹ +:: +AùPow”Down +):  +Commªd +:: +PDX +; + +150 ( +S‹ +:: +P»Pow”Down +):  +Commªd +:: +PDX +; + +151 ( +S‹ +:: +S–fReäesh +):  +Commªd +:: +SREF +; + +152 : + `as£¹ +( +çl£ +); + +154 + } +} + +157  + gLPDDR3 +:: + $š™_rowh™ +() + +160 +rowh™ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +LPDDR3 +>* +node +, Commªd +cmd +,  +id +) { + +161 ( +node +-> +¡©e +)) { + +162 ( +S‹ +:: +Clo£d +):  +çl£ +; + +163 ( +S‹ +:: +O³Ãd +): + +164 ià( +node +-> +row_¡©e +. + `fšd +( +id +è!ðnode->row_¡©e. + `’d +()) + +165  +Œue +; + +166  +çl£ +; + +167 : + `as£¹ +( +çl£ +); + +171 +rowh™ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] =„owh™[(Lev–::Bªk)][(Commªd:: +RD +)]; + +172 + } +} + +174  + gLPDDR3 +:: + $š™_rowÝ’ +() + +177 +rowÝ’ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +LPDDR3 +>* +node +, Commªd +cmd +,  +id +) { + +178 ( +node +-> +¡©e +)) { + +179 ( +S‹ +:: +Clo£d +):  +çl£ +; + +180 ( +S‹ +:: +O³Ãd +):  +Œue +; + +181 : + `as£¹ +( +çl£ +); + +185 +rowÝ’ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] =„owÝ’[(Lev–::Bªk)][(Commªd:: +RD +)]; + +186 + } +} + +188  + gLPDDR3 +:: + $š™_Ïmbda +() + +190 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +ACT +)] = [] ( +DRAM +< +LPDDR3 +>* +node +,  +id +) { + +191 +node +-> +¡©e + = +S‹ +:: +O³Ãd +; + +192 +node +-> +row_¡©e +[ +id +] = +S‹ +:: +O³Ãd +;}; + +193 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +PRE +)] = [] ( +DRAM +< +LPDDR3 +>* +node +,  +id +) { + +194 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +195 +node +-> +row_¡©e +. + `þ—r +();}; + +196 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PRA +)] = [] ( +DRAM +< +LPDDR3 +>* +node +,  +id +) { + +197 autØ +bªk + : +node +-> +chžd»n +) { + +198 +bªk +-> +¡©e + = +S‹ +:: +Clo£d +; + +199 +bªk +-> +row_¡©e +. + `þ—r +();}}; + +200 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +REF +)] = [] ( +DRAM +< +LPDDR3 +>* +node +,  +id +) {}; + +201 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +LPDDR3 +>* +node +,  +id +) {}; + +202 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] = [] ( +DRAM +< +LPDDR3 +>* +node +,  +id +) {}; + +203 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RDA +)] = [] ( +DRAM +< +LPDDR3 +>* +node +,  +id +) { + +204 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +205 +node +-> +row_¡©e +. + `þ—r +();}; + +206 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WRA +)] = [] ( +DRAM +< +LPDDR3 +>* +node +,  +id +) { + +207 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +208 +node +-> +row_¡©e +. + `þ—r +();}; + +209 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PD +)] = [] ( +DRAM +< +LPDDR3 +>* +node +,  +id +) { + +210 autØ +bªk + : +node +-> +chžd»n +) { + +211 ià( +bªk +-> +¡©e + =ð +S‹ +:: +Clo£d +) + +213 +node +-> +¡©e + = +S‹ +:: +AùPow”Down +; + +216 +node +-> +¡©e + = +S‹ +:: +P»Pow”Down +;}; + +217 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PDX +)] = [] ( +DRAM +< +LPDDR3 +>* +node +,  +id +) { + +218 +node +-> +¡©e + = +S‹ +:: +Pow”Up +;}; + +219 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +SREF +)] = [] ( +DRAM +< +LPDDR3 +>* +node +,  +id +) { + +220 +node +-> +¡©e + = +S‹ +:: +S–fReäesh +;}; + +221 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +SREFX +)] = [] ( +DRAM +< +LPDDR3 +>* +node +,  +id +) { + +222 +node +-> +¡©e + = +S‹ +:: +Pow”Up +;}; + +223 + } +} + +226  + gLPDDR3 +:: + $š™_timšg +() + +228 +S³edEÁry +& +s + = +¥“d_’Œy +; + +229 +veùÜ +< +TimšgEÁry +> * +t +; + +232 +t + = +timšg +[( +Lev– +:: +ChªÃl +)]; + +235 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nBL +}); + +236 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nBL +}); + +237 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nBL +}); + +238 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd::RDA, 1, +s +. +nBL +}); + +239 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd::WR, 1, +s +. +nBL +}); + +240 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nBL +}); + +241 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nBL +}); + +242 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd::WRA, 1, +s +. +nBL +}); + +246 +t + = +timšg +[( +Lev– +:: +Rªk +)]; + +249 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nCCD +}); + +250 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCCD +}); + +251 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCCD +}); + +252 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd::RDA, 1, +s +. +nCCD +}); + +253 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd::WR, 1, +s +. +nCCD +}); + +254 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCCD +}); + +255 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCCD +}); + +256 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd::WRA, 1, +s +. +nCCD +}); + +258 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nBL + + s. +nDQSCK + + 1 - s. +nCWL +}); + +259 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCL + + s. +nBL + + s. +nDQSCK + + 1 - s. +nCWL +}); + +260 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nBL + + s. +nDQSCK + + 1 - s. +nCWL +}); + +261 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCL + + s. +nBL + + s. +nDQSCK + + 1 - s. +nCWL +}); + +263 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTR + + 1}); + +264 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTR + + 1}); + +265 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTR + + 1}); + +266 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTR + + 1}); + +269 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +270 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +271 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +272 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd::RDA, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +273 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +274 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +275 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +276 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +277 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nBL + + s. +nDQSCK + + 1 + s. +nRTRS + - s. +nCWL +, +Œue +}); + +278 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCL + + s. +nBL + + s. +nDQSCK + + 1 + s. +nRTRS + - s. +nCWL +, +Œue +}); + +279 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nBL + + s. +nDQSCK + + 1 + s. +nRTRS + - s. +nCWL +, +Œue +}); + +280 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCL + + s. +nBL + + s. +nDQSCK + + 1 + s. +nRTRS + - s. +nCWL +, +Œue +}); + +281 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nRTRS + - s. +nCL +, +Œue +}); + +282 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nRTRS + - s. +nCL +, +Œue +}); + +283 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nRTRS + - s. +nCL +, +Œue +}); + +284 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nRTRS + - s. +nCL +, +Œue +}); + +287 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PRA +, 1, +s +. +nRTP +}); + +288 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PRA +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +}); + +291 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PD +, 1, +s +. +nCL + + s. +nBL + + 1}); + +292 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +PD +, 1, +s +. +nCL + + s. +nBL + + 1}); + +293 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PD +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +}); + +294 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +PD +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR + + 1}); + +295 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nXP +}); + +296 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nXP +}); + +297 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nXP +}); + +298 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nXP +}); + +301 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 1, +s +. +nRRD +}); + +302 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 4, +s +. +nFAW +}); + +303 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PRA +, 1, +s +. +nRAS +}); + +304 +t +[( +Commªd +:: +PRA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRPab +}); + +307 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nRPpb +}); + +308 +t +[( +Commªd +:: +PRA +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nRPab +}); + +309 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRFCab +}); + +312 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PD +, 1, 1}); + +313 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nXP +}); + +314 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nXP +}); + +315 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PRA +, 1, +s +. +nXP +}); + +318 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +SREF +, 1, +s +. +nRPpb +}); + +319 +t +[( +Commªd +:: +PRA +)]. + `push_back +({Commªd:: +SREF +, 1, +s +. +nRPab +}); + +320 +t +[( +Commªd +:: +SREFX +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nXSR +}); + +323 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd::REF, 1, +s +. +nRFCab +}); + +324 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd:: +REFPB +, 1, +s +. +nRFCab +}); + +325 +t +[( +Commªd +:: +REFPB +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nRFCpb +}); + +328 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd:: +PD +, 1, 1}); + +329 +t +[( +Commªd +:: +REFPB +)]. + `push_back +({Commªd:: +PD +, 1, 1}); + +330 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nXP +}); + +331 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +REFPB +, 1, +s +. +nXP +}); + +334 +t +[( +Commªd +:: +SREFX +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nXSR +}); + +335 +t +[( +Commªd +:: +SREFX +)]. + `push_back +({Commªd:: +REFPB +, 1, +s +. +nXSR +}); + +338 +t +[( +Commªd +:: +PD +)]. + `push_back +({Commªd:: +PDX +, 1, +s +. +nCKE +}); + +339 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PD +, 1, +s +. +nXP +}); + +342 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +SREF +, 1, +s +. +nXP +}); + +343 +t +[( +Commªd +:: +SREFX +)]. + `push_back +({Commªd:: +PD +, 1, +s +. +nXSR +}); + +346 +t +[( +Commªd +:: +SREF +)]. + `push_back +({Commªd:: +SREFX +, 1, +s +. +nCKESR +}); + +347 +t +[( +Commªd +:: +SREFX +)]. + `push_back +({Commªd:: +SREF +, 1, +s +. +nXSR +}); + +350 +t + = +timšg +[( +Lev– +:: +Bªk +)]; + +353 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nRCD +}); + +354 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nRCD +}); + +355 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nRCD +}); + +356 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nRCD +}); + +358 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nRTP +}); + +359 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +}); + +361 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRTP + + s. +nRPpb +}); + +362 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR + + s. +nRPpb +}); + +365 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 1, +s +. +nRC +}); + +366 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nRAS +}); + +367 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRPpb +}); + +368 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +REFPB +, 1, +s +. +nRPpb +}); + +371 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +REFPB +, 1, +s +. +nRRD +, +Œue +}); + +372 +t +[( +Commªd +:: +REFPB +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRRD +, +Œue +}); + +375 +t +[( +Commªd +:: +REFPB +)]. + `push_back +({Commªd::REFPB, 1, +s +. +nRFCpb +}); + +376 +t +[( +Commªd +:: +REFPB +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRFCpb +}); + +377 + } +} + + @LPDDR3.h + +1 #iâdeà +__LPDDR3_H + + +2  + #__LPDDR3_H + + + ) + +4  + ~"DRAM.h +" + +5  + ~"Reque¡.h +" + +6  + ~ + +7  + ~ + +9 +usšg + +Çme¥aû + + g¡d +; + +11 +Çme¥aû + + g¿muÏtÜ + + +14 þas  + cLPDDR3 + + +16 + gpublic +: + +17  +¡ršg + +¡ªd¬d_Çme +; + +18 +þass + + gOrg +; + +19 +þass + + gS³ed +; + +20 +LPDDR3 +( +Org + +Üg +, +S³ed + +¥“d +); + +21 +LPDDR3 +(cÚ¡ +¡ršg +& +Üg_¡r +, cÚ¡ sŒšg& +¥“d_¡r +); + +23  + gm­ +< + g¡ršg +, + gOrg +> + gÜg_m­ +; + +24  + gm­ +< + g¡ršg +, + gS³ed +> + g¥“d_m­ +; + +27 þas  + cLev– + :  + +29 +ChªÃl +, + gRªk +, + gBªk +, + gRow +, + gCÞumn +, + gMAX + + +33 þas  + cCommªd + :  + +35 +ACT +, + gPRE +, + gPRA +, + +36 + gRD +, + gWR +, + gRDA +, + gWRA +, + +37 + gREF +, + gREFPB +, + gPD +, + gPDX +, + gSREF +, + gSREFX +, + +38 + gMAX + + +41 +¡ršg + + gcommªd_Çme +[( +Commªd +:: +MAX +)] = { + +47 +Lev– + + gscÝe +[( +Commªd +:: +MAX +)] = { + +48 +Lev– +:: +Row +, Lev–:: +Bªk +, Lev–:: +Rªk +, + +49 +Lev– +:: +CÞumn +, Level::Column, Level::Column, Level::Column, + +50 +Lev– +:: +Rªk +, Lev–:: +Bªk +, Level::Rank, Level::Rank, Level::Rank, Level::Rank + +53 +boÞ + +is_Ý’šg +( +Commªd + +cmd +) + +55 ( + gcmd +)) { + +56 ( + gCommªd +:: +ACT +): + +57  +Œue +; + +59  +çl£ +; + +63 +boÞ + +is_acûssšg +( +Commªd + +cmd +) + +65 ( + gcmd +)) { + +66 ( + gCommªd +:: +RD +): + +67 ( +Commªd +:: +WR +): + +68 ( +Commªd +:: +RDA +): + +69 ( +Commªd +:: +WRA +): + +70  +Œue +; + +72  +çl£ +; + +76 +boÞ + +is_þosšg +( +Commªd + +cmd +) + +78 ( + gcmd +)) { + +79 ( + gCommªd +:: +RDA +): + +80 ( +Commªd +:: +WRA +): + +81 ( +Commªd +:: +PRE +): + +82 ( +Commªd +:: +PRA +): + +83  +Œue +; + +85  +çl£ +; + +89 +boÞ + +is_»äeshšg +( +Commªd + +cmd +) + +91 ( + gcmd +)) { + +92 ( + gCommªd +:: +REF +): + +93 ( +Commªd +:: +REFPB +): + +94  +Œue +; + +96  +çl£ +; + +101 þas  + cS‹ + :  + +103 +O³Ãd +, + gClo£d +, + gPow”Up +, + gAùPow”Down +, + gP»Pow”Down +, + gS–fReäesh +, + gMAX + + +104 } + g¡¬t +[( +Lev– +:: +MAX +)] = { + +105 +S‹ +:: +MAX +, S‹:: +Pow”Up +, S‹:: +Clo£d +, State::Closed, State::MAX + +109 +Commªd + + gŒª¦©e +[( +Reque¡ +:: +Ty³ +:: +MAX +)] = { + +110 +Commªd +:: +RD +, Commªd:: +WR +, + +111 +Commªd +:: +REF +, Commªd:: +PD +, Commªd:: +SREF + + +115 + gfunùiÚ +< +Commªd +( +DRAM +< +LPDDR3 +>*, Commªd +cmd +, )> + g´”eq +[( +Lev– +:: +MAX +)][(Command::MAX)]; + +119 + gfunùiÚ +< +boÞ +( +DRAM +< +LPDDR3 +>*, +Commªd + +cmd +, )> + growh™ +[( +Lev– +:: +MAX +)][(Command::MAX)]; + +120 + gfunùiÚ +< +boÞ +( +DRAM +< +LPDDR3 +>*, +Commªd + +cmd +, )> + growÝ’ +[( +Lev– +:: +MAX +)][(Command::MAX)]; + +123  + sTimšgEÁry + + +125 +Commªd + + gcmd +; + +126  + gdi¡ +; + +127  + gv® +; + +128 +boÞ + + gsiblšg +; + +130 + gveùÜ +< + gTimšgEÁry +> + gtimšg +[( +Lev– +:: +MAX +)][( +Commªd +::MAX)]; + +133 + gfunùiÚ +<( + gDRAM +< + gLPDDR3 +>*, )> + gÏmbda +[( +Lev– +:: +MAX +)][( +Commªd +::MAX)]; + +136 þas  + cOrg + :  + +138 +LPDDR3_4Gb_x16 +, + gLPDDR3_4Gb_x32 +, + +139 + gLPDDR3_6Gb_x16 +, + gLPDDR3_6Gb_x32 +, + +140 + gLPDDR3_8Gb_x16 +, + gLPDDR3_8Gb_x32 +, + +141 + gLPDDR3_12Gb_x16 +, + gLPDDR3_12Gb_x32 +, + +142 + gLPDDR3_16Gb_x16 +, + gLPDDR3_16Gb_x32 +, + +143 + gMAX + + +146  + sOrgEÁry + { + +147  + gsize +; + +148  + gdq +; + +149  + gcouÁ +[( +Lev– +:: +MAX +)]; + +150 } + gÜg_bË +[( +Org +:: +MAX +)] = { + +156 }, + gÜg_’Œy +; + +158  +£t_chªÃl_numb” +( +chªÃl +); + +159  +£t_¿nk_numb” +( +¿nk +); + +162 þas  + cS³ed + :  + +164 +LPDDR3_1333 +, + +165 + gLPDDR3_1600 +, + +166 + gLPDDR3_1866 +, + +167 + gLPDDR3_2133 +, + +168 + gMAX + + +171  + g´eãtch_size + = 8; + +172  + gchªÃl_width + = 64; + +174  + sS³edEÁry + { + +175  + g¿‹ +; + +176  + gäeq +, + gtCK +; + +177  + gnBL +, + gnCCD +, + gnRTRS +, + gnDQSCK +; + +178  + gnCL +, + gnRCD +, + gnRPpb +, + gnRPab +, + gnCWL +; + +179  + gnRAS +, + gnRC +; + +180  + gnRTP +, + gnWTR +, + gnWR +; + +181  + gnRRD +, + gnFAW +; + +182  + gnRFCab +, + gnRFCpb +, + gnREFI +; + +183  + gnCKE +, + gnXP +; + +184  + gnCKESR +, + gnXSR +; + +185 } + g¥“d_bË +[( +S³ed +:: +MAX +)] = { + +190 }, + g¥“d_’Œy +; + +195  + g»ad_Ï‹ncy +; + +197 + g´iv©e +: + +198  +š™_¥“d +(); + +199  +š™_Ïmbda +(); + +200  +š™_´”eq +(); + +201  +š™_rowh™ +(); + +202  +š™_rowÝ’ +(); + +203  +š™_timšg +(); + + @LPDDR4.cpp + +1  + ~"LPDDR4.h +" + +2  + ~"DRAM.h +" + +4  + ~ + +5  + ~ + +6  + ~<ÿs£¹ +> + +8 +usšg + +Çme¥aû + + g¡d +; + +9 +usšg + +Çme¥aû + + g¿muÏtÜ +; + +11 +¡ršg + + gLPDDR4 +:: +¡ªd¬d_Çme + = "LPDDR4"; + +13 + gm­ +< + g¡ršg +, + gLPDDR4 +:: +Org +> +LPDDR4 +:: +Üg_m­ + = { + +14 {"LPDDR4_4Gb_x16", +LPDDR4 +:: +Org +:: +LPDDR4_4Gb_x16 +}, + +15 {"LPDDR4_6Gb_x16", +LPDDR4 +:: +Org +:: +LPDDR4_6Gb_x16 +}, + +16 {"LPDDR4_8Gb_x16", +LPDDR4 +:: +Org +:: +LPDDR4_8Gb_x16 +}, + +19 + gm­ +< + g¡ršg +, + gLPDDR4 +:: +S³ed +> +LPDDR4 +:: +¥“d_m­ + = { + +20 {"LPDDR4_1600", +LPDDR4 +:: +S³ed +:: +LPDDR4_1600 +}, + +21 {"LPDDR4_2400", +LPDDR4 +:: +S³ed +:: +LPDDR4_2400 +}, + +22 {"LPDDR4_3200", +LPDDR4 +:: +S³ed +:: +LPDDR4_3200 +}, + +25 + gLPDDR4 +:: + $LPDDR4 +( +Org + +Üg +, +S³ed + +¥“d +) + +26 : + `Üg_’Œy +( +Üg_bË +[( +Üg +)]), + +27 + `¥“d_’Œy +( +¥“d_bË +[( +¥“d +)]), + +28 + `»ad_Ï‹ncy +( +¥“d_’Œy +. +nCL + + s³ed_’Œy. +nDQSCK + + s³ed_’Œy. +nBL +) + +30 + `š™_¥“d +(); + +31 + `š™_´”eq +(); + +32 + `š™_rowh™ +(); + +33 + `š™_rowÝ’ +(); + +34 + `š™_Ïmbda +(); + +35 + `š™_timšg +(); + +36 + } +} + +38 + gLPDDR4 +:: + $LPDDR4 +(cÚ¡ +¡ršg +& +Üg_¡r +, cÚ¡ sŒšg& +¥“d_¡r +) : + +39 + $LPDDR4 +( +Üg_m­ +[ +Üg_¡r +], +¥“d_m­ +[ +¥“d_¡r +]) + +41 + } +} + +43  + gLPDDR4 +:: + $£t_chªÃl_numb” +( +chªÃl +) { + +44 +Üg_’Œy +. +couÁ +[( +Lev– +:: +ChªÃl +)] = +chªÃl +; + +45 + } +} + +47  + gLPDDR4 +:: + $£t_¿nk_numb” +( +¿nk +) { + +48 +Üg_’Œy +. +couÁ +[( +Lev– +:: +Rªk +)] = +¿nk +; + +49 + } +} + +52  + gLPDDR4 +:: + $š™_¥“d +() + +56 cÚ¡  +RFCPB_TABLE +[( +Org +:: +MAX +)][( +S³ed +::MAX)] = { + +62 cÚ¡  +RFCAB_TABLE +[( +Org +:: +MAX +)][( +S³ed +::MAX)] = { + +68 cÚ¡  +REFI_TABLE +[( +ReäeshMode +:: +MAX +)][( +S³ed +::MAX)] = { + +74 cÚ¡  +XSR_TABLE +[( +Org +:: +MAX +)][( +S³ed +::MAX)] = { + +80  +¥“d + = 0, +d’s™y + = 0; + +81  +¥“d_’Œy +. +¿‹ +) { + +82 1600: +¥“d + = 0; ; + +83 2400: +¥“d + = 1; ; + +84 3200: +¥“d + = 2; ; + +85 : + `as£¹ +( +çl£ +); + +87  +Üg_’Œy +. +size + >> 10){ + +88 2: +d’s™y + = 0; ; + +89 3: +d’s™y + = 1; ; + +90 4: +d’s™y + = 2; ; + +91 : + `as£¹ +( +çl£ + && "12Gb/16Gb is still TBD"); + +93 +¥“d_’Œy +. +nRFCpb + = +RFCPB_TABLE +[ +d’s™y +][ +¥“d +]; + +94 +¥“d_’Œy +. +nRFCab + = +RFCAB_TABLE +[ +d’s™y +][ +¥“d +]; + +95 +¥“d_’Œy +. +nREFI + = +REFI_TABLE +[( +»äesh_mode +)][ +¥“d +]; + +96 +¥“d_’Œy +. +nXSR + = +XSR_TABLE +[ +d’s™y +][ +¥“d +]; + +97 + } +} + +100  + gLPDDR4 +:: + $š™_´”eq +() + +103 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +LPDDR4 +>* +node +, Commªd +cmd +,  +id +) { + +104 ( +node +-> +¡©e +)) { + +105 ( +S‹ +:: +Pow”Up +):  +Commªd +:: +MAX +; + +106 ( +S‹ +:: +AùPow”Down +):  +Commªd +:: +PDX +; + +107 ( +S‹ +:: +P»Pow”Down +):  +Commªd +:: +PDX +; + +108 ( +S‹ +:: +S–fReäesh +):  +Commªd +:: +SREFX +; + +109 : + `as£¹ +( +çl£ +); + +111 +´”eq +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +LPDDR4 +>* +node +, Commªd +cmd +,  +id +) { + +112 ( +node +-> +¡©e +)) { + +113 ( +S‹ +:: +Clo£d +):  +Commªd +:: +ACT +; + +114 ( +S‹ +:: +O³Ãd +): + +115 ià( +node +-> +row_¡©e +. + `fšd +( +id +è!ðnode->row_¡©e. + `’d +()) + +116  +cmd +; + +117  +Commªd +:: +PRE +; + +118 : + `as£¹ +( +çl£ +); + +122 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +WR +)] =…»»q[(Lev–::Rªk)][(Commªd:: +RD +)]; + +123 +´”eq +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] =…»»q[(Lev–::Bªk)][(Commªd:: +RD +)]; + +126 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +REF +)] = [] ( +DRAM +< +LPDDR4 +>* +node +, Commªd +cmd +,  +id +) { + +127 autØ +bªk + : +node +-> +chžd»n +) { + +128 ià( +bªk +-> +¡©e + =ð +S‹ +:: +Clo£d +) + +130  +Commªd +:: +PREA +; + +132  +Commªd +:: +REF +;}; + +135 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PDE +)] = [] ( +DRAM +< +LPDDR4 +>* +node +, Commªd +cmd +,  +id +) { + +136 ( +node +-> +¡©e +)) { + +137 ( +S‹ +:: +Pow”Up +):  +Commªd +:: +PDE +; + +138 ( +S‹ +:: +AùPow”Down +):  +Commªd +:: +PDE +; + +139 ( +S‹ +:: +P»Pow”Down +):  +Commªd +:: +PDE +; + +140 ( +S‹ +:: +S–fReäesh +):  +Commªd +:: +SREFX +; + +141 : + `as£¹ +( +çl£ +); + +145 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +SREF +)] = [] ( +DRAM +< +LPDDR4 +>* +node +, Commªd +cmd +,  +id +) { + +146 ( +node +-> +¡©e +)) { + +147 ( +S‹ +:: +Pow”Up +):  +Commªd +:: +SREF +; + +148 ( +S‹ +:: +AùPow”Down +):  +Commªd +:: +PDX +; + +149 ( +S‹ +:: +P»Pow”Down +):  +Commªd +:: +PDX +; + +150 ( +S‹ +:: +S–fReäesh +):  +Commªd +:: +SREF +; + +151 : + `as£¹ +( +çl£ +); + +153 + } +} + +156  + gLPDDR4 +:: + $š™_rowh™ +() + +159 +rowh™ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +LPDDR4 +>* +node +, Commªd +cmd +,  +id +) { + +160 ( +node +-> +¡©e +)) { + +161 ( +S‹ +:: +Clo£d +):  +çl£ +; + +162 ( +S‹ +:: +O³Ãd +): + +163 ià( +node +-> +row_¡©e +. + `fšd +( +id +è!ðnode->row_¡©e. + `’d +()) + +164  +Œue +; + +165  +çl£ +; + +166 : + `as£¹ +( +çl£ +); + +170 +rowh™ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] =„owh™[(Lev–::Bªk)][(Commªd:: +RD +)]; + +171 + } +} + +173  + gLPDDR4 +:: + $š™_rowÝ’ +() + +176 +rowÝ’ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +LPDDR4 +>* +node +, Commªd +cmd +,  +id +) { + +177 ( +node +-> +¡©e +)) { + +178 ( +S‹ +:: +Clo£d +):  +çl£ +; + +179 ( +S‹ +:: +O³Ãd +):  +Œue +; + +180 : + `as£¹ +( +çl£ +); + +184 +rowÝ’ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] =„owÝ’[(Lev–::Bªk)][(Commªd:: +RD +)]; + +185 + } +} + +187  + gLPDDR4 +:: + $š™_Ïmbda +() + +189 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +ACT +)] = [] ( +DRAM +< +LPDDR4 +>* +node +,  +id +) { + +190 +node +-> +¡©e + = +S‹ +:: +O³Ãd +; + +191 +node +-> +row_¡©e +[ +id +] = +S‹ +:: +O³Ãd +;}; + +192 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +PRE +)] = [] ( +DRAM +< +LPDDR4 +>* +node +,  +id +) { + +193 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +194 +node +-> +row_¡©e +. + `þ—r +();}; + +195 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PREA +)] = [] ( +DRAM +< +LPDDR4 +>* +node +,  +id +) { + +196 autØ +bªk + : +node +-> +chžd»n +) { + +197 +bªk +-> +¡©e + = +S‹ +:: +Clo£d +; + +198 +bªk +-> +row_¡©e +. + `þ—r +();}}; + +199 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +REF +)] = [] ( +DRAM +< +LPDDR4 +>* +node +,  +id +) {}; + +200 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +LPDDR4 +>* +node +,  +id +) {}; + +201 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] = [] ( +DRAM +< +LPDDR4 +>* +node +,  +id +) {}; + +202 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RDA +)] = [] ( +DRAM +< +LPDDR4 +>* +node +,  +id +) { + +203 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +204 +node +-> +row_¡©e +. + `þ—r +();}; + +205 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WRA +)] = [] ( +DRAM +< +LPDDR4 +>* +node +,  +id +) { + +206 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +207 +node +-> +row_¡©e +. + `þ—r +();}; + +208 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PDE +)] = [] ( +DRAM +< +LPDDR4 +>* +node +,  +id +) { + +209 autØ +bªk + : +node +-> +chžd»n +) { + +210 ià( +bªk +-> +¡©e + =ð +S‹ +:: +Clo£d +) + +212 +node +-> +¡©e + = +S‹ +:: +AùPow”Down +; + +215 +node +-> +¡©e + = +S‹ +:: +P»Pow”Down +;}; + +216 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PDX +)] = [] ( +DRAM +< +LPDDR4 +>* +node +,  +id +) { + +217 +node +-> +¡©e + = +S‹ +:: +Pow”Up +;}; + +218 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +SREF +)] = [] ( +DRAM +< +LPDDR4 +>* +node +,  +id +) { + +219 +node +-> +¡©e + = +S‹ +:: +S–fReäesh +;}; + +220 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +SREFX +)] = [] ( +DRAM +< +LPDDR4 +>* +node +,  +id +) { + +221 +node +-> +¡©e + = +S‹ +:: +Pow”Up +;}; + +222 + } +} + +225  + gLPDDR4 +:: + $š™_timšg +() + +227 +S³edEÁry +& +s + = +¥“d_’Œy +; + +228 +veùÜ +< +TimšgEÁry +> * +t +; + +231 +t + = +timšg +[( +Lev– +:: +ChªÃl +)]; + +234 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nBL +}); + +235 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nBL +}); + +236 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nBL +}); + +237 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd::RDA, 1, +s +. +nBL +}); + +238 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd::WR, 1, +s +. +nBL +}); + +239 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nBL +}); + +240 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nBL +}); + +241 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd::WRA, 1, +s +. +nBL +}); + +245 +t + = +timšg +[( +Lev– +:: +Rªk +)]; + +248 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nCCD +}); + +249 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCCD +}); + +250 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCCD +}); + +251 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd::RDA, 1, +s +. +nCCD +}); + +252 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd::WR, 1, +s +. +nCCD +}); + +253 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCCD +}); + +254 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCCD +}); + +255 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd::WRA, 1, +s +. +nCCD +}); + +257 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nBL + + s. +nDQSCK + + 1 - s. +nCWL +}); + +258 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCL + + s. +nBL + + s. +nDQSCK + + 1 - s. +nCWL +}); + +259 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nBL + + s. +nDQSCK + + 1 - s. +nCWL +}); + +260 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCL + + s. +nBL + + s. +nDQSCK + + 1 - s. +nCWL +}); + +262 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTR + + 1}); + +263 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTR + + 1}); + +264 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTR + + 1}); + +265 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTR + + 1}); + +269 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +270 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +271 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +272 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd::RDA, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +273 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +274 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +275 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +276 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +277 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nBL + + s. +nDQSCK + + 1 + s. +nRTRS + - s. +nCWL +, +Œue +}); + +278 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCL + + s. +nBL + + s. +nDQSCK + + 1 + s. +nRTRS + - s. +nCWL +, +Œue +}); + +279 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nBL + + s. +nDQSCK + + 1 + s. +nRTRS + - s. +nCWL +, +Œue +}); + +280 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCL + + s. +nBL + + s. +nDQSCK + + 1 + s. +nRTRS + - s. +nCWL +, +Œue +}); + +281 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nRTRS + - s. +nCL +, +Œue +}); + +282 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nRTRS + - s. +nCL +, +Œue +}); + +283 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nRTRS + - s. +nCL +, +Œue +}); + +284 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nRTRS + - s. +nCL +, +Œue +}); + +287 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PREA +, 1, +s +. +nRTP +}); + +288 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PREA +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +}); + +291 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nCL + + s. +nBL + + 1}); + +292 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nCL + + s. +nBL + + 1}); + +293 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +}); + +294 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR + + 1}); + +295 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nXP +}); + +296 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nXP +}); + +297 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nXP +}); + +298 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nXP +}); + +301 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 1, +s +. +nRRD +}); + +302 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 4, +s +. +nFAW +}); + +303 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PREA +, 1, +s +. +nRAS +}); + +304 +t +[( +Commªd +:: +PREA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRPab +}); + +305 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd::PRE, 1, +s +. +nPPD +}); + +308 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nRPpb +}); + +309 +t +[( +Commªd +:: +PREA +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nRPab +}); + +310 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRFCab +}); + +313 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PDE +, 1, 1}); + +314 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nXP +}); + +315 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nXP +}); + +316 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PREA +, 1, +s +. +nXP +}); + +319 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +SREF +, 1, +s +. +nRPpb +}); + +320 +t +[( +Commªd +:: +PREA +)]. + `push_back +({Commªd:: +SREF +, 1, +s +. +nRPab +}); + +321 +t +[( +Commªd +:: +SREFX +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nXSR +}); + +324 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd::REF, 1, +s +. +nRFCab +}); + +325 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd:: +REFPB +, 1, +s +. +nRFCab +}); + +326 +t +[( +Commªd +:: +REFPB +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nRFCpb +}); + +329 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd:: +PDE +, 1, 1}); + +330 +t +[( +Commªd +:: +REFPB +)]. + `push_back +({Commªd:: +PDE +, 1, 1}); + +331 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nXP +}); + +332 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +REFPB +, 1, +s +. +nXP +}); + +335 +t +[( +Commªd +:: +SREFX +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nXSR +}); + +336 +t +[( +Commªd +:: +SREFX +)]. + `push_back +({Commªd:: +REFPB +, 1, +s +. +nXSR +}); + +339 +t +[( +Commªd +:: +PDE +)]. + `push_back +({Commªd:: +PDX +, 1, +s +. +nCKE +}); + +340 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nXP +}); + +343 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +SREF +, 1, +s +. +nXP +}); + +344 +t +[( +Commªd +:: +SREFX +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nXSR +}); + +347 +t +[( +Commªd +:: +SREF +)]. + `push_back +({Commªd:: +SREFX +, 1, +s +. +nSR +}); + +348 +t +[( +Commªd +:: +SREFX +)]. + `push_back +({Commªd:: +SREF +, 1, +s +. +nXSR +}); + +351 +t + = +timšg +[( +Lev– +:: +Bªk +)]; + +354 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nRCD +}); + +355 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nRCD +}); + +356 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nRCD +}); + +357 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nRCD +}); + +359 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nRTP +}); + +360 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +}); + +362 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRTP + + s. +nRPpb +}); + +363 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR + + s. +nRPpb +}); + +366 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 1, +s +. +nRC +}); + +367 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nRAS +}); + +368 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRPpb +}); + +369 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +REFPB +, 1, +s +. +nRPpb +}); + +372 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +REFPB +, 1, +s +. +nRRD +, +Œue +}); + +373 +t +[( +Commªd +:: +REFPB +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRRD +, +Œue +}); + +376 +t +[( +Commªd +:: +REFPB +)]. + `push_back +({Commªd::REFPB, 1, +s +. +nRFCpb +}); + +377 +t +[( +Commªd +:: +REFPB +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRFCpb +}); + +378 + } +} + + @LPDDR4.h + +1 #iâdeà +__LPDDR4_H + + +2  + #__LPDDR4_H + + + ) + +4  + ~"DRAM.h +" + +5  + ~"Reque¡.h +" + +6  + ~ + +7  + ~ + +9 +usšg + +Çme¥aû + + g¡d +; + +11 +Çme¥aû + + g¿muÏtÜ + + +14 þas  + cLPDDR4 + + +16 + gpublic +: + +17  +¡ršg + +¡ªd¬d_Çme +; + +18 +þass + + gOrg +; + +19 +þass + + gS³ed +; + +20 +LPDDR4 +( +Org + +Üg +, +S³ed + +¥“d +); + +21 +LPDDR4 +(cÚ¡ +¡ršg +& +Üg_¡r +, cÚ¡ sŒšg& +¥“d_¡r +); + +23  + gm­ +< + g¡ršg +, + gOrg +> + gÜg_m­ +; + +24  + gm­ +< + g¡ršg +, + gS³ed +> + g¥“d_m­ +; + +27 þas  + cLev– + :  + +29 +ChªÃl +, + gRªk +, + gBªk +, + gRow +, + gCÞumn +, + gMAX + + +33 þas  + cCommªd + :  + +35 +ACT +, + gPRE +, + gPREA +, + +36 + gRD +, + gWR +, + gRDA +, + gWRA +, + +37 + gREF +, + gREFPB +, + gPDE +, + gPDX +, + gSREF +, + gSREFX +, + +38 + gMAX + + +43 +¡ršg + + gcommªd_Çme +[( +Commªd +:: +MAX +)] = { + +49 +Lev– + + gscÝe +[( +Commªd +:: +MAX +)] = { + +50 +Lev– +:: +Row +, Lev–:: +Bªk +, Lev–:: +Rªk +, + +51 +Lev– +:: +CÞumn +, Level::Column, Level::Column, Level::Column, + +52 +Lev– +:: +Rªk +, Lev–:: +Bªk +, Level::Rank, Level::Rank, Level::Rank, Level::Rank + +55 +boÞ + +is_Ý’šg +( +Commªd + +cmd +) + +57 ( + gcmd +)) { + +58 ( + gCommªd +:: +ACT +): + +59  +Œue +; + +61  +çl£ +; + +65 +boÞ + +is_acûssšg +( +Commªd + +cmd +) + +67 ( + gcmd +)) { + +68 ( + gCommªd +:: +RD +): + +69 ( +Commªd +:: +WR +): + +70 ( +Commªd +:: +RDA +): + +71 ( +Commªd +:: +WRA +): + +72  +Œue +; + +74  +çl£ +; + +78 +boÞ + +is_þosšg +( +Commªd + +cmd +) + +80 ( + gcmd +)) { + +81 ( + gCommªd +:: +RDA +): + +82 ( +Commªd +:: +WRA +): + +83 ( +Commªd +:: +PRE +): + +84 ( +Commªd +:: +PREA +): + +85  +Œue +; + +87  +çl£ +; + +91 +boÞ + +is_»äeshšg +( +Commªd + +cmd +) + +93 ( + gcmd +)) { + +94 ( + gCommªd +:: +REF +): + +95 ( +Commªd +:: +REFPB +): + +96  +Œue +; + +98  +çl£ +; + +103 þas  + cS‹ + :  + +105 +O³Ãd +, + gClo£d +, + gPow”Up +, + gAùPow”Down +, + gP»Pow”Down +, + gS–fReäesh +, + gMAX + + +106 } + g¡¬t +[( +Lev– +:: +MAX +)] = { + +107 +S‹ +:: +MAX +, S‹:: +Pow”Up +, S‹:: +Clo£d +, State::Closed, State::MAX + +111 +Commªd + + gŒª¦©e +[( +Reque¡ +:: +Ty³ +:: +MAX +)] = { + +112 +Commªd +:: +RD +, Commªd:: +WR +, + +113 +Commªd +:: +REF +, Commªd:: +PDE +, Commªd:: +SREF + + +117 + gfunùiÚ +< +Commªd +( +DRAM +< +LPDDR4 +>*, Commªd +cmd +, )> + g´”eq +[( +Lev– +:: +MAX +)][(Command::MAX)]; + +121 + gfunùiÚ +< +boÞ +( +DRAM +< +LPDDR4 +>*, +Commªd + +cmd +, )> + growh™ +[( +Lev– +:: +MAX +)][(Command::MAX)]; + +122 + gfunùiÚ +< +boÞ +( +DRAM +< +LPDDR4 +>*, +Commªd + +cmd +, )> + growÝ’ +[( +Lev– +:: +MAX +)][(Command::MAX)]; + +125  + sTimšgEÁry + + +127 +Commªd + + gcmd +; + +128  + gdi¡ +; + +129  + gv® +; + +130 +boÞ + + gsiblšg +; + +132 + gveùÜ +< + gTimšgEÁry +> + gtimšg +[( +Lev– +:: +MAX +)][( +Commªd +::MAX)]; + +135 + gfunùiÚ +<( + gDRAM +< + gLPDDR4 +>*, )> + gÏmbda +[( +Lev– +:: +MAX +)][( +Commªd +::MAX)]; + +138 þas  + cOrg + :  + +141 +LPDDR4_4Gb_x16 +, + +142 + gLPDDR4_6Gb_x16 +, + +143 + gLPDDR4_8Gb_x16 +, + +146 + gMAX + + +149  + sOrgEÁry + { + +150  + gsize +; + +151  + gdq +; + +152  + gcouÁ +[( +Lev– +:: +MAX +)]; + +153 } + gÜg_bË +[( +Org +:: +MAX +)] = { + +157 }, + gÜg_’Œy +; + +159  +£t_chªÃl_numb” +( +chªÃl +); + +160  +£t_¿nk_numb” +( +¿nk +); + +164 þas  + cS³ed + :  + +166 +LPDDR4_1600 +, + +167 + gLPDDR4_2400 +, + +168 + gLPDDR4_3200 +, + +169 + gMAX + + +172 þas  + cReäeshMode + :  + +174 +Reäesh_1X +, + +175 + gReäesh_2X +, + +176 + gReäesh_4X +, + +177 + gMAX + + +178 } + g»äesh_mode + = +ReäeshMode +:: +Reäesh_1X +; + +180  + g´eãtch_size + = 16; + +181  + gchªÃl_width + = 32; + +183  + sS³edEÁry + { + +184  + g¿‹ +; + +185  + gäeq +, + gtCK +; + +186  + gnBL +, + gnCCD +, + gnRTRS +, + gnDQSCK +; + +187  + gnCL +, + gnRCD +, + gnRPpb +, + gnRPab +, + gnCWL +; + +188  + gnRAS +, + gnRC +; + +189  + gnRTP +, + gnWTR +, + gnWR +; + +190  + gnPPD +, + gnRRD +, + gnFAW +; + +191  + gnRFCab +, + gnRFCpb +, + gnREFI +; + +192  + gnCKE +, + gnXP +; + +193  + gnSR +, + gnXSR +; + +194 } + g¥“d_bË +[( +S³ed +:: +MAX +)] = { + +204 }, + g¥“d_’Œy +; + +209  + g»ad_Ï‹ncy +; + +211 + g´iv©e +: + +212  +š™_¥“d +(); + +213  +š™_Ïmbda +(); + +214  +š™_´”eq +(); + +215  +š™_rowh™ +(); + +216  +š™_rowÝ’ +(); + +217  +š™_timšg +(); + + @Main.cpp + +1  + ~"MemW¿µ”.h +" + +2  + ~"³.h +" + +4  + $sc_maš +( +¬gc +, * +¬gv +[]){ + +6 +sc_sigÇl +< +MemOp +> +memReq +; + +7 +sc_sigÇl +< +MemOp +> +memRe¥ +; + +9 +³ + + `³In¡ +("peInst"); + +10 +³In¡ +. + `memReq +( +memReq +); + +11 +³In¡ +. + `memRe¥ +( +memRe¥ +); + +13 +MemW¿µ” + + `memW¿µ” +("memW¿µ”", +¬gc +, +¬gv +); + +14 +memW¿µ” +. + `memReq +( +memReq +); + +15 +memW¿µ” +. + `memRe¥ +( +memRe¥ +); + +17 + `sc_¡¬t +(); + +21 + } +} + + @MemWrapper.cpp + +1  + ~"MemW¿µ”.h +" + +5 + gMemW¿µ” +:: + $MemW¿µ” +( +sc_moduË_Çme + +_Çme +,  +¬gc +, * +¬gv +[]) + +6 : + `sc_moduË +( +_Çme +), + $cÚfigs +( +¬gv +[1]){ + +8 + `lßdCÚfig +( +¬gc +, +¬gv +); + +9 +memClkCyþe + = 5; + +10 +³ClkCyþe + = 10; + +11 +noNewMemReq + = +çl£ +; + +12 +»qCouÁ” + = 0; + +13 +»¥CouÁ” + = 0; + +15 + `SC_THREAD +( +runMemSim +); + +16 + `SC_THREAD +( +g‘Reque¡ +); + +17 + `SC_THREAD +( +£ndRe¥ +); + +18 + `SC_THREAD +( +memReqMÚ™Ü +); + +19 + } +} + +29  + gMemW¿µ” +:: + $memReqMÚ™Ü +(){ + +30 +boÞ + +d–ay1 + = +çl£ +; + +31  +Œue +){ + +32 +noNewMemReq + = +d–ay1 +; + +33 if( +»qCouÁ” + == 10){ + +34 +d–ay1 + = +Œue +; + +38 +d–ay1 + = +çl£ +; + +42 + `wa™ +( +³ClkCyþe +, +SC_NS +); + +44 + } +} + +47  + gMemW¿µ” +:: + $g‘Reque¡ +(){ + +48  +Œue +){ + +49 +MemOp + +tmpOp + = +memReq +. + `»ad +(); + +50 if( +tmpOp +. +v®id +){ + +51 +»qCouÁ” +++; + +52 +memReqQueue +. + `push_back +( +tmpOp +); + +55 + `wa™ +( +³ClkCyþe +, +SC_NS +); + +57 + } +} + +62  + gMemW¿µ” +:: + $£ndRe¥ +(){ + +63  +Œue +){ + +64 +MemOp + + `tmpOp +( +çl£ +); + +65  +cu¼’tTimeSmp + = ()( + `sc_time_¡amp +()/ + `sc_time +(1, +SC_NS +)); + +67 if( +memRe¥Queue +. + `em±y +()){ + +68 +memRe¥ +. + `wr™e +( +tmpOp +); + +74 +¡d +:: +li¡ +< +Reque¡ +>:: +™”©Ü + +™ + = +memRe¥Queue +. + `begš +(); + +75  +™ + !ð +memRe¥Queue +. + `’d +()){ + +76  +»¥R—dyTime + = +™ +-> +d•¬tMemTime +; + +77 if( +»¥R—dyTime + <ð +cu¼’tTimeSmp +){ + +78 +»¥CouÁ” +++; + +79 +tmpOp +. + `MemOpUpd©e +(* +™ +); + +80 +memRe¥ +. + `wr™e +( +tmpOp +); + +81 +memRe¥Queue +. + `”a£ +( +™ +); + +85 +™ +++; + +90 + `wa™ +( +³ClkCyþe +, +SC_NS +); + +92 + } +} + +94  + gMemW¿µ” +:: + $runMemSim +(){ + +96 ià( +¡ªd¬d + == "DDR3") { + +97 +DDR3 +* +ddr3 + = +Ãw + + `DDR3 +( +cÚfigs +["org"], configs["speed"]); + +98 + `¡¬t_run +( +cÚfigs +, +ddr3 +, +fžes +); + +99 } ià( +¡ªd¬d + == "DDR4") { + +100 +DDR4 +* +ddr4 + = +Ãw + + `DDR4 +( +cÚfigs +["org"], configs["speed"]); + +101 + `¡¬t_run +( +cÚfigs +, +ddr4 +, +fžes +); + +102 } ià( +¡ªd¬d + == "SALP-MASA") { + +103 +SALP +* +§Í8 + = +Ãw + + `SALP +( +cÚfigs +["Üg"], cÚfigs["¥“d"], "SALP-MASA", cÚfigs. + `g‘_sub¬¿ys +()); + +104 + `¡¬t_run +( +cÚfigs +, +§Í8 +, +fžes +); + +105 } ià( +¡ªd¬d + == "LPDDR3") { + +106 +LPDDR3 +* +Íddr3 + = +Ãw + + `LPDDR3 +( +cÚfigs +["org"], configs["speed"]); + +107 + `¡¬t_run +( +cÚfigs +, +Íddr3 +, +fžes +); + +108 } ià( +¡ªd¬d + == "LPDDR4") { + +110 +LPDDR4 +* +Íddr4 + = +Ãw + + `LPDDR4 +( +cÚfigs +["org"], configs["speed"]); + +111 + `¡¬t_run +( +cÚfigs +, +Íddr4 +, +fžes +); + +112 } ià( +¡ªd¬d + == "GDDR5") { + +113 +GDDR5 +* +gddr5 + = +Ãw + + `GDDR5 +( +cÚfigs +["org"], configs["speed"]); + +114 + `¡¬t_run +( +cÚfigs +, +gddr5 +, +fžes +); + +115 } ià( +¡ªd¬d + == "HBM") { + +116 +HBM +* +hbm + = +Ãw + + `HBM +( +cÚfigs +["org"], configs["speed"]); + +117 + `¡¬t_run +( +cÚfigs +, +hbm +, +fžes +); + +118 } ià( +¡ªd¬d + == "WideIO") { + +120 +WideIO +* +wio + = +Ãw + + `WideIO +( +cÚfigs +["org"], configs["speed"]); + +121 + `¡¬t_run +( +cÚfigs +, +wio +, +fžes +); + +122 } ià( +¡ªd¬d + == "WideIO2") { + +124 +WideIO2 +* +wio2 + = +Ãw + + `WideIO2 +( +cÚfigs +["Üg"], cÚfigs["¥“d"], cÚfigs. + `g‘_chªÃls +()); + +125 +wio2 +-> +chªÃl_width + *= 2; + +126 + `¡¬t_run +( +cÚfigs +, +wio2 +, +fžes +); + +129 ià( +¡ªd¬d + == "DSARP") { + +130 +DSARP +* +dsddr3_d§½ + = +Ãw + + `DSARP +( +cÚfigs +["Üg"], cÚfigs["¥“d"], DSARP:: +Ty³ +::DSARP, cÚfigs. + `g‘_sub¬¿ys +()); + +131 + `¡¬t_run +( +cÚfigs +, +dsddr3_d§½ +, +fžes +); + +132 } ià( +¡ªd¬d + == "ALDRAM") { + +133 +ALDRAM +* +®d¿m + = +Ãw + + `ALDRAM +( +cÚfigs +["org"], configs["speed"]); + +134 + `¡¬t_run +( +cÚfigs +, +®d¿m +, +fžes +); + +135 } ià( +¡ªd¬d + == "TLDRAM") { + +136 +TLDRAM +* +Žd¿m + = +Ãw + + `TLDRAM +( +cÚfigs +["Üg"], cÚfigs["¥“d"], cÚfigs. + `g‘_sub¬¿ys +()); + +137 + `¡¬t_run +( +cÚfigs +, +Žd¿m +, +fžes +); + +139 + `´štf +("SimuÏtiÚ dÚe. Sti¡ic wr™‹ÀtØ%s\n", +¡©s_out +. + `c_¡r +()); + +141 + } +} + +143  + gMemW¿µ” +:: + $lßdCÚfig +( +¬gc +, * +¬gv +[]){ + +144 ià( +¬gc + < 2) { + +145 + `´štf +("U§ge: %  --mode=ýu,d¿m,acø[--¡© ] <Œaû-fž’ame1> <Œaû-fž’ame2> Exam¶e: % ¿muÏtÜ-cÚfigs.cfg --mode=ýu cpu.Œaû cpu.Œaû\n", +¬gv +[0],‡rgv[0]); + +148 +¡ªd¬d + = +cÚfigs +["standard"]; + +149 + `as£¹ +( +¡ªd¬d + != "" || "DRAM standard should be specified."); + +151 cÚ¡ * +Œaû_ty³ + = + `¡r¡r +( +¬gv +[2], "="); + +152 +Œaû_ty³ +++; + +153 ià( + `¡rcmp +( +Œaû_ty³ +, "acc") == 0){ + +154 +cÚfigs +. + `add +("trace_type", "acc"); + +156 + `´štf +("šv®id¿ûy³: %s\n", +Œaû_ty³ +); + +157 + `as£¹ +( +çl£ +); + +160  +Œaû_¡¬t + = 3; + +161 +Sts +:: +¡©li¡ +. + `ouut +( +¡ªd¬d ++".stats"); + +162 +¡©s_out + = +¡ªd¬d + + + `¡ršg +(".stats"); + +165 if( +¬gc + >=3){ + +166  +i + = +Œaû_¡¬t +; i < +¬gc +; i++){ + +167 +fžes +. + `push_back +( +¬gv +[ +i +]); + +171 +cÚfigs +. + `£t_cÜe_num +( +¬gc + - +Œaû_¡¬t +); + +172 + } +} + +174 + g‹m¶©e +< +ty³Çme + + gT +> + +175  + gMemW¿µ” +:: +¡¬t_run +(cÚ¡ +CÚfig +& +cÚfigs +, +T +* +¥ec +, cÚ¡ +veùÜ +& +fžes +) { + +177  + gC + = +cÚfigs +. +g‘_chªÃls +(), + gR + = cÚfigs. +g‘_¿nks +(); + +179 + g¥ec +-> +£t_chªÃl_numb” +( +C +); + +180 + g¥ec +-> +£t_¿nk_numb” +( +R +); + +181 + g¡d +:: +veùÜ +< +CÚŒÞËr +< +T +>*> +ù¾s +; + +182  + gc + = 0 ; c < + gC + ; c++) { + +183 + gDRAM +< + gT +>* + gchªÃl + = +Ãw + +DRAM +< +T +>( +¥ec +, T:: +Lev– +:: +ChªÃl +); + +184 + gchªÃl +-> + gid + = +c +; + +185 + gchªÃl +-> +»gSts +(""); + +186 + gCÚŒÞËr +< + gT +>* + gù¾ + = +Ãw + +CÚŒÞËr +< +T +>( +cÚfigs +, + gchªÃl +); + +187 + gù¾s +. +push_back +( +ù¾ +); + +189 + gMemÜy +< + gT +, + gCÚŒÞËr +> +memÜy +( +cÚfigs +, +ù¾s +); + +191 ià( + gcÚfigs +["trace_type"] == "acc") { + +192 +run_acc +( +cÚfigs +, +memÜy +); + +195 + g¡d +:: +cout + << "E¼Ü: uÃx³ùed¿ûy³." << +¡d +:: +’dl +; + +196 +ex™ +( +EXIT_FAILURE +); + +208 +boÞ + + gMemW¿µ” +:: + $g‘MemReq +( +MemOp + & +Ý +){ + +209 +¡d +:: +li¡ +< +MemOp +>:: +™”©Ü + +™ +; + +210 if(! +memReqQueue +. + `em±y +()){ + +211 +™ + = +memReqQueue +. + `begš +(); + +212 +Ý + = * +™ +; + +214 +Ý +. +¬riveMemTime + = ()( + `sc_time_¡amp +()/ + `sc_time +(1, +SC_NS +)); + +215 +memReqQueue +. + `pÝ_äÚt +(); + +216  +Œue +; + +219  +çl£ +; + +221 + } +} + +223 + g‹m¶©e +< +ty³Çme + + gT +> + +224  + gMemW¿µ” +:: +run_acc +(cÚ¡ +CÚfig +& +cÚfigs +, +MemÜy +< +T +, +CÚŒÞËr +>& +memÜy +) { + +226 +boÞ + + g¡®l + = +çl£ +, + g’d + = false; + +227  + g»ads + = 0, + gwr™es + = 0, + gþks + = 0; + +228 +MemOp + +Ý +( +çl£ +); + +229 + gm­ +<, > + gÏ‹nc›s +; + +232 autØ + g»ad_com¶‘e + = [ +this +, & +Ï‹nc›s +]( + gReque¡ +& + gr +){ + +233  + gÏ‹ncy + = +r +. +d•¬t + -„. +¬rive +; + +234 + gÏ‹nc›s +[ +Ï‹ncy +]++; + +236 + gr +. + gd•¬tMemTime + = +r +. +¬riveMemTime + + +memClkCyþe + * +Ï‹ncy +; + +237 + gmemRe¥Queue +. +push_back +( +r +); + +240 +Reque¡ + +»q +( +Ý +. +addr +, op. +ty³ +, +»ad_com¶‘e +); + +241 !( + g’d + && (! + gmemÜy +. +³ndšg_»que¡s +()è&& + gnoNewMemReq +)){ + +242 ià(! + g¡®l +){ + +243 + g’d + = ! +g‘MemReq +( +Ý +); + +246 ià(! + g’d +){ + +247 + gÝ +. +cÝyToReq +( +»q +); + +248 + g¡®l + = ! +memÜy +. +£nd +( +»q +); + +249 ià(! + g¡®l +){ + +250 ià( + g»q +. + gty³ + =ð +Reque¡ +:: +Ty³ +:: +READ +) + +251 +»ads +++; + +252 ià( + g»q +. + gty³ + =ð +Reque¡ +:: +Ty³ +:: +WRITE +) + +253 +wr™es +++; + +257 +wa™ +( +memClkCyþe +, +SC_NS +); + +258 + gmemÜy +. +tick +(); + +259 + gþks + ++; + +260 + gSts +:: +curTick +++; + +263 + gmemÜy +. +fšish +(); + +264 + gSts +:: +¡©li¡ +. +´šÎ +(); + + @MemWrapper.h + +1 #iâdeà +__MEM_WRAPPER_H__ + + +2  + #__MEM_WRAPPER_H__ + + + ) + +4  + ~"ProûssÜ.h +" + +5  + ~"CÚfig.h +" + +6  + ~"CÚŒÞËr.h +" + +7  + ~"S³edyCÚŒÞËr.h +" + +8  + ~"MemÜy.h +" + +9  + ~"DRAM.h +" + +10  + ~"Sti¡ics.h +" + +11  + ~ + +12  + ~ + +13  + ~ + +14  + ~<¡dlib.h +> + +15  + ~ + +16  + ~ + +17  + ~<™”©Ü +> + +18  + ~ + +19  + ~"³.h +" + +20  + ~"commÚ.h +" + +23  + ~"Gem5W¿µ”.h +" + +24  + ~"DDR3.h +" + +25  + ~"DDR4.h +" + +26  + ~"DSARP.h +" + +27  + ~"GDDR5.h +" + +28  + ~"LPDDR3.h +" + +29  + ~"LPDDR4.h +" + +30  + ~"WideIO.h +" + +31  + ~"WideIO2.h +" + +32  + ~"HBM.h +" + +33  + ~"SALP.h +" + +34  + ~"ALDRAM.h +" + +35  + ~"TLDRAM.h +" + +37 þas  + cMemW¿µ” + : +public + +sc_moduË +{ + +39 +SC_HAS_PROCESS +( +MemW¿µ” +); + +41 + mpublic +: + +43 +¡d +:: +¡ršg + +Çme +; + +44 + m¡d +:: +¡ršg + +¡ªd¬d +; + +45 +CÚfig + + mcÚfigs +; + +46 +¡ršg + + m¡©s_out +; + +47 + m¡d +:: +veùÜ + +fžes +; + +50 + msc_š + < + mMemOp +> + mmemReq +; + +51 + msc_out + < + mMemOp +> + mmemRe¥ +; + +53  + mmemSize +; + +54 + m¡d +:: +li¡ +< +MemOp +> +memReqQueue +; + +55 + m¡d +:: +li¡ +< +Reque¡ +> +memRe¥Queue +; + +56 +št32_t + * + m¿mD©a +; + +58 +MemW¿µ” +( +sc_moduË_Çme + +_Çme +,  +¬gc +, * +¬gv +[]); + +60 + m‹m¶©e +< +ty³Çme + + mT +> + +61  +run_acc +(cÚ¡ +CÚfig +& +cÚfigs +, +MemÜy +< +T +, +CÚŒÞËr +>& +memÜy +); + +63 + m‹m¶©e +< +ty³Çme + + mT +> + +64  +¡¬t_run +(cÚ¡ +CÚfig +& +cÚfigs +, +T +* +¥ec +, cÚ¡ +veùÜ +& +fžes +); + +66 +boÞ + +g‘MemReq +( +MemOp + & +Ý +); + +67  +runMemSim +(); + +68  +g‘Reque¡ +(); + +69  +£ndRe¥ +(); + +70  +memReqMÚ™Ü +(); + +72 ~ + $MemW¿µ” +(){}; + +74 +´iv©e +: + +75  +»qCouÁ” +; + +76  +»¥CouÁ” +; + +77  +memClkCyþe +; + +78  +³ClkCyþe +; + +79 +boÞ + +noNewMemReq +; + +80  + `lßdCÚfig +( +¬gc +, * +¬gv +[]); + +81 + } +}; + + @Memory.h + +1 #iâdeà +__MEMORY_H + + +2  + #__MEMORY_H + + + ) + +4  + ~"CÚfig.h +" + +5  + ~"DRAM.h +" + +6  + ~"Reque¡.h +" + +7  + ~"CÚŒÞËr.h +" + +8  + ~"S³edyCÚŒÞËr.h +" + +9  + ~"Sti¡ics.h +" + +10  + ~"GDDR5.h +" + +11  + ~"HBM.h +" + +12  + ~"LPDDR3.h +" + +13  + ~"LPDDR4.h +" + +14  + ~"WideIO2.h +" + +15  + ~"DSARP.h +" + +16  + ~ + +17  + ~ + +18  + ~ + +19  + ~<ÿs£¹ +> + +20  + ~ + +22 +usšg + +Çme¥aû + + g¡d +; + +24 +Çme¥aû + + g¿muÏtÜ + + +27 þas  + cMemÜyBa£ +{ + +28 + gpublic +: + +29 +MemÜyBa£ +() {} + +30 +vœtu® + ~ +MemÜyBa£ +() {} + +31 +vœtu® +  +þk_ns +() = 0; + +32 +vœtu® +  +tick +() = 0; + +33 +vœtu® + +boÞ + +£nd +( +Reque¡ + +»q +) = 0; + +34 +vœtu® +  +³ndšg_»que¡s +() = 0; + +35 +vœtu® +  +fšish +() = 0; + +36 +vœtu® +  +·ge_®loÿtÜ +( +addr +,  +cÜeid +) = 0; + +37 +vœtu® +  +»cÜd_cÜe +( +cÜeid +) = 0; + +40 + g‹m¶©e + < +þass + + gT +,em¶©e< + gty³Çme +> cÏs  + gCÚŒÞËr + = +CÚŒÞËr + > + +41 þas  + cMemÜy + : +public + +MemÜyBa£ + + +43 +´Ùeùed +: + +44 +SÿÏrSt + +d¿m_ÿ·c™y +; + +45 +SÿÏrSt + + gnum_d¿m_cyþes +; + +46 +SÿÏrSt + + gnum_šcomšg_»que¡s +; + +47 +VeùÜSt + + gnum_»ad_»que¡s +; + +48 +VeùÜSt + + gnum_wr™e_»que¡s +; + +49 +SÿÏrSt + + g¿muÏtÜ_aùive_cyþes +; + +50 +VeùÜSt + + gšcomšg_»que¡s_³r_chªÃl +; + +51 +VeùÜSt + + gšcomšg_»ad_»qs_³r_chªÃl +; + +53 +SÿÏrSt + + gphysiÿl_·ge_»¶aûm’t +; + +54 +SÿÏrSt + + gmaximum_bªdwidth +; + +55 +SÿÏrSt + + gš_queue_»q_num_sum +; + +56 +SÿÏrSt + + gš_queue_»ad_»q_num_sum +; + +57 +SÿÏrSt + + gš_queue_wr™e_»q_num_sum +; + +58 +SÿÏrSt + + gš_queue_»q_num_avg +; + +59 +SÿÏrSt + + gš_queue_»ad_»q_num_avg +; + +60 +SÿÏrSt + + gš_queue_wr™e_»q_num_avg +; + +62 #iâdeà +INTEGRATED_WITH_GEM5 + + +63 +VeùÜSt + + g»cÜd_»ad_»que¡s +; + +64 +VeùÜSt + + g»cÜd_wr™e_»que¡s +; + +67  + gmax_add»ss +; + +68 + gpublic +: + +69 þas  + cTy³ + { + +70 +ChRaBaRoCo +, + +71 + gRoBaRaCoCh +, + +72 + gMAX +, + +73 } + gty³ + = +Ty³ +:: +RoBaRaCoCh +; + +75 þas  + cT¿n¦©iÚ + { + +76 + gNÚe +, + +77 + gRªdom +, + +78 + gMAX +, + +79 } + gŒª¦©iÚ + = +T¿n¦©iÚ +:: +NÚe +; + +81 + g¡d +:: +m­ +< +¡ršg +, + gT¿n¦©iÚ +> + gÇme_to_Œª¦©iÚ + = { + +82 {"NÚe", +T¿n¦©iÚ +:: +NÚe +}, + +83 {"Rªdom", +T¿n¦©iÚ +:: +Rªdom +}, + +86 + gveùÜ +<> + gä“_physiÿl_·ges +; + +87  + gä“_physiÿl_·ges_»maššg +; + +88 + gm­ +< + g·œ +<, >, > + g·ge_Œª¦©iÚ +; + +90 + gveùÜ +< + gCÚŒÞËr +< + gT +>*> + gù¾s +; + +91 +T + * + g¥ec +; + +92 + gveùÜ +<> + gaddr_b™s +; + +94  + gtx_b™s +; + +96 +MemÜy +(cÚ¡ +CÚfig +& +cÚfigs +, +veùÜ +< +CÚŒÞËr +< +T +>*> +ù¾s +) + +97 : +ù¾s +(ctrls), + +98 +¥ec +( +ù¾s +[0]-> +chªÃl +->spec), + +99 +addr_b™s +(( +T +:: +Lev– +:: +MAX +)) + +103 * +sz + = +¥ec +-> +Üg_’Œy +. +couÁ +; + +104 +as£¹ +(( +sz +[0] & (sz[0] - 1)) == 0); + +105 +as£¹ +(( +sz +[1] & (sz[1] - 1)) == 0); + +107  + gtx + = ( +¥ec +-> +´eãtch_size + * s³c-> +chªÃl_width + / 8); + +108 + gtx_b™s + = +ÿlc_log2 +( +tx +); + +109 +as£¹ +((1<< +tx_b™s +è=ð +tx +); + +112 ià( + gty³ + !ð +Ty³ +:: +RoBaRaCoCh + && +¥ec +-> +¡ªd¬d_Çme +. +sub¡r +(0, 5) == "LPDDR") + +113 +as£¹ +(( +sz +[( +T +:: +Lev– +:: +Row +)] & (sz[(T::Level::Row)] - 1)) == 0); + +115 + gmax_add»ss + = +¥ec +-> +chªÃl_width + / 8; + +117  + gËv + = 0;†ev < + gaddr_b™s +. +size +();†ev++) { + +118 + gaddr_b™s +[ +Ëv +] = +ÿlc_log2 +( +sz +[lev]); + +119 + gmax_add»ss + *ð +sz +[ +Ëv +]; + +122 + gaddr_b™s +[( +T +:: +Lev– +:: +MAX +è- 1] -ð +ÿlc_log2 +( +¥ec +-> +´eãtch_size +); + +125 ià( + gcÚfigs +. +cÚšs +("translation")) { + +126 + gŒª¦©iÚ + = +Çme_to_Œª¦©iÚ +[ +cÚfigs +["translation"]]; + +128 ià( + gŒª¦©iÚ + !ð +T¿n¦©iÚ +:: +NÚe +) { + +131 +ä“_physiÿl_·ges_»maššg + = +max_add»ss + >> 12; + +133 + gä“_physiÿl_·ges +. +»size +( +ä“_physiÿl_·ges_»maššg +, -1); + +136 + gd¿m_ÿ·c™y + + +137 . +Çme +("dram_capacity") + +138 . +desc +("Number of bytes in simulated DRAM") + +139 . +´ecisiÚ +(0) + +141 + gd¿m_ÿ·c™y + = +max_add»ss +; + +143 + gnum_d¿m_cyþes + + +144 . +Çme +("dram_cycles") + +145 . +desc +("Number of DRAM cycles simulated") + +146 . +´ecisiÚ +(0) + +148 + gnum_šcomšg_»que¡s + + +149 . +Çme +("incoming_requests") + +150 . +desc +("Number of incoming„equestso DRAM") + +151 . +´ecisiÚ +(0) + +153 + gnum_»ad_»que¡s + + +154 . +š™ +( +cÚfigs +. +g‘_cÜe_num +()) + +155 . +Çme +("read_requests") + +156 . +desc +("Number of incoming„ead„equestso DRAM…er core") + +157 . +´ecisiÚ +(0) + +159 + gnum_wr™e_»que¡s + + +160 . +š™ +( +cÚfigs +. +g‘_cÜe_num +()) + +161 . +Çme +("write_requests") + +162 . +desc +("Number of incoming write„equestso DRAM…er core") + +163 . +´ecisiÚ +(0) + +165 + gšcomšg_»que¡s_³r_chªÃl + + +166 . +š™ +( +sz +[( +T +:: +Lev– +:: +ChªÃl +)]) + +167 . +Çme +("incoming_requests_per_channel") + +168 . +desc +("Number of incoming„equestsoƒach DRAM channel") + +170 + gšcomšg_»ad_»qs_³r_chªÃl + + +171 . +š™ +( +sz +[( +T +:: +Lev– +:: +ChªÃl +)]) + +172 . +Çme +("incoming_read_reqs_per_channel") + +173 . +desc +("Number of incoming„ead„equestsoƒach DRAM channel") + +176 + g¿muÏtÜ_aùive_cyþes + + +177 . +Çme +("ramulator_active_cycles") + +178 . +desc +("Theotal‚umber of cycleshathe DRAM…art is‡ctive (serving R/W)") + +179 . +´ecisiÚ +(0) + +181 + gphysiÿl_·ge_»¶aûm’t + + +182 . +Çme +("physical_page_replacement") + +183 . +desc +("The‚umber ofimeshat…hysical…age„eplacement happens.") + +184 . +´ecisiÚ +(0) + +186 + gmaximum_bªdwidth + + +187 . +Çme +("maximum_bandwidth") + +188 . +desc +("Theheoretical maximum bandwidth (Bps)") + +189 . +´ecisiÚ +(0) + +191 + gš_queue_»q_num_sum + + +192 . +Çme +("in_queue_req_num_sum") + +193 . +desc +("Sum of„ead/write queue†ength") + +194 . +´ecisiÚ +(0) + +196 + gš_queue_»ad_»q_num_sum + + +197 . +Çme +("in_queue_read_req_num_sum") + +198 . +desc +("Sum of„ead queue†ength") + +199 . +´ecisiÚ +(0) + +201 + gš_queue_wr™e_»q_num_sum + + +202 . +Çme +("in_queue_write_req_num_sum") + +203 . +desc +("Sum of write queue†ength") + +204 . +´ecisiÚ +(0) + +206 + gš_queue_»q_num_avg + + +207 . +Çme +("in_queue_req_num_avg") + +208 . +desc +("Average of„ead/write queue†ength…er memory cycle") + +209 . +´ecisiÚ +(6) + +211 + gš_queue_»ad_»q_num_avg + + +212 . +Çme +("in_queue_read_req_num_avg") + +213 . +desc +("Average of„ead queue†ength…er memory cycle") + +214 . +´ecisiÚ +(6) + +216 + gš_queue_wr™e_»q_num_avg + + +217 . +Çme +("in_queue_write_req_num_avg") + +218 . +desc +("Average of write queue†ength…er memory cycle") + +219 . +´ecisiÚ +(6) + +221 #iâdeà +INTEGRATED_WITH_GEM5 + + +222 + g»cÜd_»ad_»que¡s + + +223 . +š™ +( +cÚfigs +. +g‘_cÜe_num +()) + +224 . +Çme +("record_read_requests") + +225 . +desc +("record„ead„equests forhis core when it„eaches„equest†imit oroheƒnd") + +228 + g»cÜd_wr™e_»que¡s + + +229 . +š™ +( +cÚfigs +. +g‘_cÜe_num +()) + +230 . +Çme +("record_write_requests") + +231 . +desc +("record write„equests forhis core when it„eaches„equest†imit oroheƒnd") + +237 ~ +MemÜy +() + +239 autØ + gù¾ +: +ù¾s +) + +240 +d–‘e + +ù¾ +; + +241 +d–‘e + + g¥ec +; + +244  +þk_ns +() + +246  + g¥ec +-> + g¥“d_’Œy +. + gtCK +; + +249  +»cÜd_cÜe +( +cÜeid +) { + +250 #iâdeà +INTEGRATED_WITH_GEM5 + + +251 + g»cÜd_»ad_»que¡s +[ +cÜeid +] = +num_»ad_»que¡s +[coreid]; + +252 + g»cÜd_wr™e_»que¡s +[ +cÜeid +] = +num_wr™e_»que¡s +[coreid]; + +254 autØ + gù¾ + : +ù¾s +) { + +255 +ù¾ +-> +»cÜd_cÜe +( +cÜeid +); + +259  +tick +() + +261 ++ + gnum_d¿m_cyþes +; + +262  + gcur_que_»q_num + = 0; + +263  + gcur_que_»ad»q_num + = 0; + +264  + gcur_que_wr™”eq_num + = 0; + +265 autØ + gù¾ + : +ù¾s +) { + +266 +cur_que_»q_num + +ð +ù¾ +-> +»adq +. +size +(è+ cŒl-> +wr™eq +.size(è+ cŒl-> +³ndšg +.size(); + +267 + gcur_que_»ad»q_num + +ð +ù¾ +-> +»adq +. +size +(è+ cŒl-> +³ndšg +.size(); + +268 + gcur_que_wr™”eq_num + +ð +ù¾ +-> +wr™eq +. +size +(); + +270 + gš_queue_»q_num_sum + +ð +cur_que_»q_num +; + +271 + gš_queue_»ad_»q_num_sum + +ð +cur_que_»ad»q_num +; + +272 + gš_queue_wr™e_»q_num_sum + +ð +cur_que_wr™”eq_num +; + +274 +boÞ + + gis_aùive + = +çl£ +; + +275 autØ + gù¾ + : +ù¾s +) { + +276 +is_aùive + = is_aùiv|| +ù¾ +->is_active(); + +277 + gù¾ +-> +tick +(); + +279 ià( + gis_aùive +) { + +280 + g¿muÏtÜ_aùive_cyþes +++; + +284 +boÞ + +£nd +( +Reque¡ + +»q +) + +286 + g»q +. + gaddr_vec +. +»size +( +addr_b™s +. +size +()); + +287  + gaddr + = +»q +. +addr +; + +288  + gcÜeid + = +»q +. +cÜeid +; + +291 +þ—r_low”_b™s +( +addr +, +tx_b™s +); + +293 ( + gty³ +)){ + +294 ( + gTy³ +:: +ChRaBaRoCo +): + +295  +i + = +addr_b™s +. +size +(è- 1; + gi + >= 0; i--) + +296 + g»q +. + gaddr_vec +[ +i +] = +¦iû_low”_b™s +( +addr +, +addr_b™s +[i]); + +298 ( + gTy³ +:: +RoBaRaCoCh +): + +299 +»q +. +addr_vec +[0] = +¦iû_low”_b™s +( +addr +, +addr_b™s +[0]); + +300 + g»q +. + gaddr_vec +[ +addr_b™s +. +size +(è- 1] = +¦iû_low”_b™s +( +addr +,‡ddr_bits[addr_bits.size() - 1]); + +301  + gi + = 1; i <ð( +T +:: +Lev– +:: +Row +); i++) + +302 + g»q +. + gaddr_vec +[ +i +] = +¦iû_low”_b™s +( +addr +, +addr_b™s +[i]); + +305 +as£¹ +( +çl£ +); + +308 if( + gù¾s +[ +»q +. +addr_vec +[0]]-> +’queue +(req)) { + +310 ++ + gnum_šcomšg_»que¡s +; + +311 ià( + g»q +. + gty³ + =ð +Reque¡ +:: +Ty³ +:: +READ +) { + +312 ++ +num_»ad_»que¡s +[ +cÜeid +]; + +313  + gtmp + = (è( +T +:: +Lev– +:: +ChªÃl +); + +314 ++ + gšcomšg_»ad_»qs_³r_chªÃl +[ +»q +. +addr_vec +[ +tmp +]]; + +316 ià( + g»q +. + gty³ + =ð +Reque¡ +:: +Ty³ +:: +WRITE +) { + +317 ++ +num_wr™e_»que¡s +[ +cÜeid +]; + +319 ++ + gšcomšg_»que¡s_³r_chªÃl +[ +»q +. +addr_vec +[( +T +:: +Lev– +:: +ChªÃl +)]]; + +320  + gŒue +; + +323  + gçl£ +; + +326  +³ndšg_»que¡s +() + +328  + g»qs + = 0; + +329 autØ + gù¾ +: +ù¾s +) + +330 +»qs + +ð +ù¾ +-> +»adq +. +size +(è+ cŒl-> +wr™eq +.size(è+ cŒl-> +Ùh”q +.size(è+ cŒl-> +³ndšg +.size(); + +331  + g»qs +; + +334  +fšish +() { + +335 + gd¿m_ÿ·c™y + = +max_add»ss +; + +336 * + gsz + = +¥ec +-> +Üg_’Œy +. +couÁ +; + +337 + gmaximum_bªdwidth + = +¥ec +-> +¥“d_’Œy +. +¿‹ + * 1e6 * s³c-> +chªÃl_width + * +sz +[( +T +:: +Lev– +:: +ChªÃl +)] / 8; + +338  + gd¿m_cyþes + = +num_d¿m_cyþes +. +v®ue +(); + +339 autØ + gù¾ + : +ù¾s +) { + +340  +»ad_»q + = ( +šcomšg_»ad_»qs_³r_chªÃl +[ +ù¾ +-> +chªÃl +-> +id +]. +v®ue +()); + +341 + gù¾ +-> +fšish +( +»ad_»q +, +d¿m_cyþes +); + +345 + gš_queue_»q_num_avg + = +š_queue_»q_num_sum +. +v®ue +(è/ +d¿m_cyþes +; + +346 + gš_queue_»ad_»q_num_avg + = +š_queue_»ad_»q_num_sum +. +v®ue +(è/ +d¿m_cyþes +; + +347 + gš_queue_wr™e_»q_num_avg + = +š_queue_wr™e_»q_num_sum +. +v®ue +(è/ +d¿m_cyþes +; + +350  +·ge_®loÿtÜ +( +addr +,  +cÜeid +) { + +351  + gvœtu®_·ge_numb” + = +addr + >> 12; + +353 ( + gŒª¦©iÚ +)) { + +354 ( + gT¿n¦©iÚ +:: +NÚe +): { + +355  +addr +; + +357 ( + gT¿n¦©iÚ +:: +Rªdom +): { + +358 autØ +rg‘ + = +make_·œ +( +cÜeid +, +vœtu®_·ge_numb” +); + +359 if( + g·ge_Œª¦©iÚ +. +fšd +( +rg‘ +è=ð +·ge_Œª¦©iÚ +. +’d +()) { + +365 ià(! +ä“_physiÿl_·ges_»maššg +) { + +366 +physiÿl_·ge_»¶aûm’t +++; + +367  + gphys_·ge_to_»ad + = +̪d +(è% +ä“_physiÿl_·ges +. +size +(); + +368 +as£¹ +( +ä“_physiÿl_·ges +[ +phys_·ge_to_»ad +] != -1); + +369 + g·ge_Œª¦©iÚ +[ +rg‘ +] = +phys_·ge_to_»ad +; + +372  + gphys_·ge_to_»ad + = +̪d +(è% +ä“_physiÿl_·ges +. +size +(); + +374 if( + gä“_physiÿl_·ges +[ +phys_·ge_to_»ad +] != -1) { + +375  +¡¬tšg_·ge_of_£¬ch + = +phys_·ge_to_»ad +; + +380 ++ + gphys_·ge_to_»ad +; + +381 + gphys_·ge_to_»ad + %ð +ä“_physiÿl_·ges +. +size +(); + +383 ( + gphys_·ge_to_»ad + !ð +¡¬tšg_·ge_of_£¬ch +è&& +ä“_physiÿl_·ges +[ +phys_·ge_to_»ad +] != -1); + +386 +as£¹ +( +ä“_physiÿl_·ges +[ +phys_·ge_to_»ad +] == -1); + +388 + g·ge_Œª¦©iÚ +[ +rg‘ +] = +phys_·ge_to_»ad +; + +389 + gä“_physiÿl_·ges +[ +phys_·ge_to_»ad +] = +cÜeid +; + +390 -- + gä“_physiÿl_·ges_»maššg +; + +395  ( + g·ge_Œª¦©iÚ +[ +rg‘ +] << 12è| ( + gaddr + & ((1 << 12) - 1)); + +398 +as£¹ +( +çl£ +); + +403 + g´iv©e +: + +405  +ÿlc_log2 +( +v® +){ + +406  +n + = 0; + +407 ( + gv® + >>= 1)) + +408 +n + ++; + +409  + gn +; + +411  +¦iû_low”_b™s +(& +addr +,  +b™s +) + +413  + glb™s + = +addr + & ((1<< +b™s +) - 1); + +414 + gaddr + >>ð +b™s +; + +415  + glb™s +; + +417  +þ—r_low”_b™s +(& +addr +,  +b™s +) + +419 + gaddr + >>ð +b™s +; + +421  +̪d +() { + +423  + g¡©ic_ÿ¡ +<>( +¿nd +()) << (() * 8) |„and(); + +426  +¿nd +(); + + @MemoryFactory.cpp + +1  + ~"MemÜyFaùÜy.h +" + +2  + ~"LPDDR4.h +" + +3  + ~"WideIO.h +" + +4  + ~"WideIO2.h +" + +5  + ~"HBM.h +" + +6  + ~"SALP.h +" + +8 +usšg + +Çme¥aû + + g¿muÏtÜ +; + +10 +Çme¥aû + + g¿muÏtÜ + + +13 + g‹m¶©e + <> + +14  + gMemÜyFaùÜy +< + gLPDDR4 +>:: +v®id©e +( +chªÃls +,  +¿nks +, cÚ¡ +CÚfig +& +cÚfigs +) { + +15 +as£¹ +( +chªÃls + >= 2 && "LPDDR4„equires 2, 4, 8 ... channels"); + +18 + g‹m¶©e + <> + +19  + gMemÜyFaùÜy +< + gWideIO +>:: +v®id©e +( +chªÃls +,  +¿nks +, cÚ¡ +CÚfig +& +cÚfigs +) { + +20 +as£¹ +( +chªÃls + == 4 && "WideIO comes with 4 channels"); + +23 + g‹m¶©e + <> + +24  + gMemÜyFaùÜy +< + gWideIO2 +>:: +v®id©e +( +chªÃls +,  +¿nks +, cÚ¡ +CÚfig +& +cÚfigs +) { + +25 +as£¹ +(( +chªÃls + == 4 || channels == 8) && "WideIO2 comes with 4 or 8 channels"); + +26 +as£¹ +(( +¿nks + == 1 ||„anks == 2) && "WideIO2 comes with 1 or 2„anks"); + +29 + g‹m¶©e + <> + +30  + gMemÜyFaùÜy +< + gHBM +>:: +v®id©e +( +chªÃls +,  +¿nks +, cÚ¡ +CÚfig +& +cÚfigs +) { + +31 +as£¹ +( +chªÃls + == 8 && "HBM comes with 8 channels"); + +34 + g‹m¶©e + <> + +35 +MemÜyBa£ + * + gMemÜyFaùÜy +< + gWideIO2 +>:: +ü—‹ +(cÚ¡ +CÚfig +& +cÚfigs +,  +ÿch–še +) { + +36  + gchªÃls + = +¡oi +( +cÚfigs +["chªÃls"], +NULL +, 0); + +37  + g¿nks + = +¡oi +( +cÚfigs +["¿nks"], +NULL +, 0); + +38 +v®id©e +( +chªÃls +, +¿nks +, +cÚfigs +); + +40 cÚ¡ + g¡ršg +& + gÜg_Çme + = +cÚfigs +["org"]; + +41 cÚ¡ + g¡ršg +& + g¥“d_Çme + = +cÚfigs +["speed"]; + +43 +WideIO2 + * + g¥ec + = +Ãw + WideIO2( +Üg_Çme +, +¥“d_Çme +, +chªÃls +); + +45 +ex‹nd_chªÃl_width +( +¥ec +, +ÿch–še +); + +47  ( + gMemÜyBa£ + *) +pÝuÏ‹_memÜy +( +cÚfigs +, +¥ec +, +chªÃls +, +¿nks +); + +51 + g‹m¶©e + <> + +52 +MemÜyBa£ + * + gMemÜyFaùÜy +< + gSALP +>:: +ü—‹ +(cÚ¡ +CÚfig +& +cÚfigs +,  +ÿch–še +) { + +53  + gchªÃls + = +¡oi +( +cÚfigs +["chªÃls"], +NULL +, 0); + +54  + g¿nks + = +¡oi +( +cÚfigs +["¿nks"], +NULL +, 0); + +55  + gsub¬¿ys + = +¡oi +( +cÚfigs +["sub¬¿ys"], +NULL +, 0); + +56 +v®id©e +( +chªÃls +, +¿nks +, +cÚfigs +); + +58 cÚ¡ + g¡ršg +& + g¡d_Çme + = +cÚfigs +["standard"]; + +59 cÚ¡ + g¡ršg +& + gÜg_Çme + = +cÚfigs +["org"]; + +60 cÚ¡ + g¡ršg +& + g¥“d_Çme + = +cÚfigs +["speed"]; + +62 +SALP + * + g¥ec + = +Ãw + SALP( +Üg_Çme +, +¥“d_Çme +, +¡d_Çme +, +sub¬¿ys +); + +64 +ex‹nd_chªÃl_width +( +¥ec +, +ÿch–še +); + +66  ( + gMemÜyBa£ + *) +pÝuÏ‹_memÜy +( +cÚfigs +, +¥ec +, +chªÃls +, +¿nks +); + +76  +lib¿muÏtÜ_is_´e£Á +() + + @MemoryFactory.h + +1 #iâdeà +__MEMORY_FACTORY_H + + +2  + #__MEMORY_FACTORY_H + + + ) + +4  + ~ + +5  + ~<¡ršg +> + +6  + ~<ÿs£¹ +> + +8  + ~"CÚfig.h +" + +9  + ~"MemÜy.h +" + +11  + ~"WideIO2.h +" + +12  + ~"SALP.h +" + +14 +usšg + +Çme¥aû + + g¡d +; + +16 +Çme¥aû + + g¿muÏtÜ + + +19 + g‹m¶©e + < +ty³Çme + + gT +> + +20 þas  + cMemÜyFaùÜy + { + +21 + gpublic +: + +22  +ex‹nd_chªÃl_width +( +T +* +¥ec +,  +ÿch–še +) + +24  + gchªÃl_un™ + = +¥ec +-> +´eãtch_size + * s³c-> +chªÃl_width + / 8; + +25  + ggªg_numb” + = +ÿch–še + / +chªÃl_un™ +; + +27 +as£¹ +( +gªg_numb” + >= 1 && + +30 +as£¹ +( +ÿch–še + =ð +gªg_numb” + * +chªÃl_un™ + && + +33 + g¥ec +-> + gchªÃl_width + *ð +gªg_numb” +; + +36  + gMemÜy +< + gT +> * +pÝuÏ‹_memÜy +(cÚ¡ +CÚfig +& +cÚfigs +, +T + * +¥ec +,  +chªÃls +,  +¿nks +) { + +37 & + gdeçuÉ_¿nks + = +¥ec +-> +Üg_’Œy +. +couÁ +[( +T +:: +Lev– +:: +Rªk +)]; + +38 & + gdeçuÉ_chªÃls + = +¥ec +-> +Üg_’Œy +. +couÁ +[( +T +:: +Lev– +:: +ChªÃl +)]; + +40 ià( + gdeçuÉ_chªÃls + =ð0è +deçuÉ_chªÃls + = +chªÃls +; + +41 ià( + gdeçuÉ_¿nks + =ð0è +deçuÉ_¿nks + = +¿nks +; + +43 + gveùÜ +< + gCÚŒÞËr +< + gT +> *> + gù¾s +; + +44  + gc + = 0; c < + gchªÃls +; c++){ + +45 + gDRAM +< + gT +>* + gchªÃl + = +Ãw + +DRAM +< +T +>( +¥ec +, T:: +Lev– +:: +ChªÃl +); + +46 + gchªÃl +-> + gid + = +c +; + +47 + gchªÃl +-> +»gSts +(""); + +48 + gù¾s +. +push_back +( +Ãw + +CÚŒÞËr +< +T +>( +cÚfigs +, +chªÃl +)); + +50  +Ãw + + gMemÜy +< + gT +>( + gcÚfigs +, + gù¾s +); + +53  +v®id©e +( +chªÃls +,  +¿nks +, cÚ¡ +CÚfig +& +cÚfigs +) { + +54 +as£¹ +( +chªÃls + > 0 && +¿nks + > 0); + +57  +MemÜyBa£ + * +ü—‹ +(cÚ¡ +CÚfig +& +cÚfigs +,  +ÿch–še +) + +59  + gchªÃls + = +¡oi +( +cÚfigs +["chªÃls"], +NULL +, 0); + +60  + g¿nks + = +¡oi +( +cÚfigs +["¿nks"], +NULL +, 0); + +62 +v®id©e +( +chªÃls +, +¿nks +, +cÚfigs +); + +64 cÚ¡ + g¡ršg +& + gÜg_Çme + = +cÚfigs +["org"]; + +65 cÚ¡ + g¡ršg +& + g¥“d_Çme + = +cÚfigs +["speed"]; + +67 +T + * + g¥ec + = +Ãw + T( +Üg_Çme +, +¥“d_Çme +); + +69 +ex‹nd_chªÃl_width +( +¥ec +, +ÿch–še +); + +71  ( + gMemÜyBa£ + *) +pÝuÏ‹_memÜy +( +cÚfigs +, +¥ec +, +chªÃls +, +¿nks +); + +75 + g‹m¶©e + <> + +76 +MemÜyBa£ + * + gMemÜyFaùÜy +< + gWideIO2 +>:: +ü—‹ +(cÚ¡ +CÚfig +& +cÚfigs +,  +ÿch–še +); + +77 + g‹m¶©e + <> + +78 +MemÜyBa£ + * + gMemÜyFaùÜy +< + gSALP +>:: +ü—‹ +(cÚ¡ +CÚfig +& +cÚfigs +,  +ÿch–še +); + + @Processor.cpp + +1  + ~"ProûssÜ.h +" + +2  + ~<ÿs£¹ +> + +4 +usšg + +Çme¥aû + + g¡d +; + +5 +usšg + +Çme¥aû + + g¿muÏtÜ +; + +7 + gProûssÜ +:: +ProûssÜ +(cÚ¡ +CÚfig +& +cÚfigs +, + +8 +veùÜ + +Œaû_li¡ +, + +9 +funùiÚ +< +boÞ +( +Reque¡ +)> +£nd_memÜy +, + +10 +MemÜyBa£ +& +memÜy +) + +11 : +cs +( +Œaû_li¡ +. +size +(), -1), + +12 +—¾y_ex™ +( +cÚfigs +. +is_—¾y_ex™ +()), + +13 +no_cÜe_ÿches +(! +cÚfigs +. +has_cÜe_ÿches +()), + +14 +no_sh¬ed_ÿche +(! +cÚfigs +. +has_l3_ÿche +()), + +15 +ÿchesys +( +Ãw + +CacheSy¡em +( +cÚfigs +, +£nd_memÜy +)), + +16 +Îc +( +l3_size +, +l3_assoc +, +l3_blocksz +, + +17 +mshr_³r_bªk + * +Œaû_li¡ +. +size +(), + +18 +Cache +:: +Lev– +:: +L3 +, +ÿchesys +) { + +20 +as£¹ +( +ÿchesys + !ð +nuαr +); + +21  + gŒaûnum + = +Œaû_li¡ +. +size +(); + +22 +as£¹ +( +Œaûnum + > 0); + +23 +´štf +("Œaûnum: %d\n", +Œaûnum +); + +24  + gi + = 0 ; i < + gŒaûnum + ; ++i) { + +25 +´štf +("Œaû_li¡[%d]: %s\n", +i +, +Œaû_li¡ +[i]); + +27 ià( + gno_sh¬ed_ÿche +) { + +28  + gi + = 0 ; i < + gŒaûnum + ; ++i) { + +29 + gcÜes +. +em¶aû_back +( +Ãw + +CÜe +( + +30 +cÚfigs +, +i +, +Œaû_li¡ +[i], +£nd_memÜy +, +nuαr +, + +31 +ÿchesys +, +memÜy +)); + +34  + gi + = 0 ; i < + gŒaûnum + ; ++i) { + +35 + gcÜes +. +em¶aû_back +( +Ãw + +CÜe +( +cÚfigs +, +i +, +Œaû_li¡ +[i], + +36 +¡d +:: +bšd +(& +Cache +:: +£nd +, & +Îc +, std:: +¶aûhÞd”s +:: +_1 +), + +37 & +Îc +, +ÿchesys +, +memÜy +)); + +40  + gi + = 0 ; i < + gŒaûnum + ; ++i) { + +41 + gcÜes +[ +i +]-> + gÿÎback + = +¡d +:: +bšd +(& +ProûssÜ +:: +»ûive +, +this +, + +42 +¶aûhÞd”s +:: +_1 +); + +46 + gýu_cyþes +. +Çme +("cpu_cycles") + +47 . +desc +("cpu cycle‚umber") + +48 . +´ecisiÚ +(0) + +50 + gýu_cyþes + = 0; + +53  + gProûssÜ +:: + $tick +() { + +54 +ýu_cyþes +++; + +55 ià(!( +no_cÜe_ÿches + && +no_sh¬ed_ÿche +)) { + +56 +ÿchesys +-> + `tick +(); + +58  +i + = 0 ; i < +cÜes +. + `size +() ; ++i) { + +59 +CÜe +* +cÜe + = +cÜes +[ +i +]. + `g‘ +(); + +60 +cÜe +-> + `tick +(); + +62 + } +} + +64  + gProûssÜ +:: + $»ûive +( +Reque¡ +& +»q +) { + +65 ià(! +no_sh¬ed_ÿche +) { + +66 +Îc +. + `ÿÎback +( +»q +); + +67 } ià(! +cÜes +[0]-> +no_cÜe_ÿches +) { + +70  +i + = 0 ; i < +cÜes +. + `size +() ; ++i) { + +71 +CÜe +* +cÜe + = +cÜes +[ +i +]. + `g‘ +(); + +72 +cÜe +-> +ÿches +[0]-> + `ÿÎback +( +»q +); + +75  +i + = 0 ; i < +cÜes +. + `size +() ; ++i) { + +76 +CÜe +* +cÜe + = +cÜes +[ +i +]. + `g‘ +(); + +77 +cÜe +-> + `»ûive +( +»q +); + +79 + } +} + +81 +boÞ + + gProûssÜ +:: + $fšished +() { + +82 ià( +—¾y_ex™ +) { + +83  +i + = 0 ; i < +cÜes +. + `size +(); ++i) { + +84 ià( +cÜes +[ +i +]-> + `fšished +()) { + +85  +j + = 0 ; j < +cÜes +. + `size +() ; ++j) { + +86 +c + +ð +cÜes +[ +j +]-> + `ÿlc_c +(); + +88  +Œue +; + +91  +çl£ +; + +93  +i + = 0 ; i < +cÜes +. + `size +(); ++i) { + +94 ià(! +cÜes +[ +i +]-> + `fšished +()) { + +95  +çl£ +; + +97 ià( +cs +[ +i +] < 0) { + +98 +cs +[ +i +] = +cÜes +[i]-> + `ÿlc_c +(); + +99 +c + +ð +cs +[ +i +]; + +102  +Œue +; + +104 + } +} + +106 +boÞ + + gProûssÜ +:: + $has_»ached_lim™ +() { + +107  +i + = 0 ; i < +cÜes +. + `size +() ; ++i) { + +108 ià(! +cÜes +[ +i +]-> + `has_»ached_lim™ +()) { + +109  +çl£ +; + +112  +Œue +; + +113 + } +} + +115 + gCÜe +:: +CÜe +(cÚ¡ +CÚfig +& +cÚfigs +,  +cÜeid +, + +116 cÚ¡ * +Œaû_âame +, +funùiÚ +< +boÞ +( +Reque¡ +)> +£nd_Ãxt +, + +117 +Cache +* +Îc +, +¡d +:: +sh¬ed_±r +< +CacheSy¡em +> +ÿchesys +, +MemÜyBa£ +& +memÜy +) + +118 : +id +( +cÜeid +), +no_cÜe_ÿches +(! +cÚfigs +. +has_cÜe_ÿches +()), + +119 +no_sh¬ed_ÿche +(! +cÚfigs +. +has_l3_ÿche +()), + +120 +Îc +Ölc), +Œaû +( +Œaû_âame +), + $memÜy +( +memÜy +) + +123 ià( +no_cÜe_ÿches +) { + +124 +£nd + = +£nd_Ãxt +; + +127 +ÿches +. + `em¶aû_back +( +Ãw + + `Cache +( + +128 +l2_size +, +l2_assoc +, +l2_blocksz +, +l2_mshr_num +, + +129 +Cache +:: +Lev– +:: +L2 +, +ÿchesys +)); + +131 +ÿches +. + `em¶aû_back +( +Ãw + + `Cache +( + +132 +l1_size +, +l1_assoc +, +l1_blocksz +, +l1_mshr_num +, + +133 +Cache +:: +Lev– +:: +L1 +, +ÿchesys +)); + +134 +£nd + = + `bšd +(& +Cache +::£nd, +ÿches +[1]. + `g‘ +(), +¶aûhÞd”s +:: +_1 +); + +135 ià( +Îc + !ð +nuαr +) { + +136 +ÿches +[0]-> + `cÚÿŽow” +( +Îc +); + +138 +ÿches +[1]-> + `cÚÿŽow” +(ÿches[0]. + `g‘ +()); + +140 ià( +no_cÜe_ÿches +) { + +141 +mÜe_»qs + = +Œaû +. + `g‘_fž‹»d_»que¡ +( + +142 +bubbË_út +, +»q_addr +, +»q_ty³ +); + +143 +»q_addr + = +memÜy +. + `·ge_®loÿtÜ +Ôeq_addr, +id +); + +145 +mÜe_»qs + = +Œaû +. + `g‘_unfž‹»d_»que¡ +( + +146 +bubbË_út +, +»q_addr +, +»q_ty³ +); + +147 +»q_addr + = +memÜy +. + `·ge_®loÿtÜ +Ôeq_addr, +id +); + +151 +ex³ùed_lim™_š¡s + = +cÚfigs +. + `g‘_ex³ùed_lim™_š¡s +(); + +154 +»cÜd_cycs +. + `Çme +("»cÜd_cycs_cÜe_" + + `to_¡ršg +( +id +)) + +155 . + `desc +("Record cycle‚umber for calculating weighted speedup. (Only valid whenƒxpected†imit instruction‚umber is‚on zero in config file.)") + +156 . + `´ecisiÚ +(0) + +159 +»cÜd_š¡s +. + `Çme +("»cÜd_š¡s_cÜe_" + + `to_¡ršg +( +id +)) + +160 . + `desc +("Retired instruction‚umber when„ecord cycle‚umber. (Only valid whenƒxpected†imit instruction‚umber is‚on zero in config file.)") + +161 . + `´ecisiÚ +(0) + +164 +memÜy_acûss_cyþes +. + `Çme +("memÜy_acûss_cyþes_cÜe_" + + `to_¡ršg +( +id +)) + +165 . + `desc +("memory‡ccess cycles in memoryime domain") + +166 . + `´ecisiÚ +(0) + +168 +memÜy_acûss_cyþes + = 0; + +169 +ýu_š¡ +. + `Çme +("ýu_š¡ruùiÚs_cÜe_" + + `to_¡ršg +( +id +)) + +170 . + `desc +("cpu instruction‚umber") + +171 . + `´ecisiÚ +(0) + +173 +ýu_š¡ + = 0; + +174 + } +} + +177  + gCÜe +:: + $ÿlc_c +() + +179 + `´štf +("[%d]»tœed: %ld, clk, %ld\n", +id +, +»tœed +, +þk +); + +180  (è +»tœed + / +þk +; + +181 + } +} + +183  + gCÜe +:: + $tick +() + +185 +þk +++; + +187 +»tœed + +ð +wšdow +. + `»tœe +(); + +189 ià( +ex³ùed_lim™_š¡s + =ð0 && ! +mÜe_»qs +) ; + +192  +š£¹ed + = 0; + +193  +bubbË_út + > 0) { + +194 ià( +š£¹ed + =ð +wšdow +. +c +) ; + +195 ià( +wšdow +. + `is_fuÎ +()) ; + +197 +wšdow +. + `š£¹ +( +Œue +, -1); + +198 +š£¹ed +++; + +199 +bubbË_út +--; + +200 +ýu_š¡ +++; + +201 ià(( +ýu_š¡ +. + `v®ue +()è=ð +ex³ùed_lim™_š¡s + && ! +»ached_lim™ +) { + +202 +»cÜd_cycs + = +þk +; + +203 +»cÜd_š¡s + = ( +ýu_š¡ +. + `v®ue +()); + +204 +memÜy +. + `»cÜd_cÜe +( +id +); + +205 +»ached_lim™ + = +Œue +; + +209 ià( +»q_ty³ + =ð +Reque¡ +:: +Ty³ +:: +READ +) { + +211 ià( +š£¹ed + =ð +wšdow +. +c +) ; + +212 ià( +wšdow +. + `is_fuÎ +()) ; + +214 +Reque¡ + + `»q +( +»q_addr +, +»q_ty³ +, +ÿÎback +, +id +); + +215 ià(! + `£nd +( +»q +)) ; + +217 +wšdow +. + `š£¹ +( +çl£ +, +»q_addr +); + +218 +ýu_š¡ +++; + +222 + `as£¹ +( +»q_ty³ + =ð +Reque¡ +:: +Ty³ +:: +WRITE +); + +223 +Reque¡ + + `»q +( +»q_addr +, +»q_ty³ +, +ÿÎback +, +id +); + +224 ià(! + `£nd +( +»q +)) ; + +225 +ýu_š¡ +++; + +227 ià(( +ýu_š¡ +. + `v®ue +()è=ð +ex³ùed_lim™_š¡s + && ! +»ached_lim™ +) { + +228 +»cÜd_cycs + = +þk +; + +229 +»cÜd_š¡s + = ( +ýu_š¡ +. + `v®ue +()); + +230 +memÜy +. + `»cÜd_cÜe +( +id +); + +231 +»ached_lim™ + = +Œue +; + +234 ià( +no_cÜe_ÿches +) { + +235 +mÜe_»qs + = +Œaû +. + `g‘_fž‹»d_»que¡ +( + +236 +bubbË_út +, +»q_addr +, +»q_ty³ +); + +237 ià( +»q_addr + != -1) { + +238 +»q_addr + = +memÜy +. + `·ge_®loÿtÜ +Ôeq_addr, +id +); + +241 +mÜe_»qs + = +Œaû +. + `g‘_unfž‹»d_»que¡ +( + +242 +bubbË_út +, +»q_addr +, +»q_ty³ +); + +243 ià( +»q_addr + != -1) { + +244 +»q_addr + = +memÜy +. + `·ge_®loÿtÜ +Ôeq_addr, +id +); + +247 ià(! +mÜe_»qs +) { + +248 ià(! +»ached_lim™ +) { + +249 +»cÜd_cycs + = +þk +; + +250 +»cÜd_š¡s + = ( +ýu_š¡ +. + `v®ue +()); + +251 +memÜy +. + `»cÜd_cÜe +( +id +); + +252 +»ached_lim™ + = +Œue +; + +255 + } +} + +257 +boÞ + + gCÜe +:: + $fšished +() + +259  ! +mÜe_»qs + && +wšdow +. + `is_em±y +(); + +260 + } +} + +262 +boÞ + + gCÜe +:: + $has_»ached_lim™ +() { + +263  +»ached_lim™ +; + +264 + } +} + +266  + gCÜe +:: + $»ûive +( +Reque¡ +& +»q +) + +268 +wšdow +. + `£t_»ady +( +»q +. +addr +, ~( +l1_blocksz + - 1l)); + +269 ià( +»q +. +¬rive + !ð-1 &&„eq. +d•¬t + > +Ï¡ +) { + +270 +memÜy_acûss_cyþes + +ð( +»q +. +d•¬t + - + `max +( +Ï¡ +,„eq. +¬rive +)); + +271 +Ï¡ + = +»q +. +d•¬t +; + +273 + } +} + +275 +boÞ + + gWšdow +:: + $is_fuÎ +() + +277  +lßd + =ð +d•th +; + +278 + } +} + +280 +boÞ + + gWšdow +:: + $is_em±y +() + +282  +lßd + == 0; + +283 + } +} + +286  + gWšdow +:: + $š£¹ +( +boÞ + +»ady +,  +addr +) + +288 + `as£¹ +( +lßd + <ð +d•th +); + +290 +»ady_li¡ +. + `© +( +h—d +èð +»ady +; + +291 +addr_li¡ +. + `© +( +h—d +èð +addr +; + +293 +h—d + = (h—d + 1è% +d•th +; + +294 +lßd +++; + +295 + } +} + +298  + gWšdow +:: + $»tœe +() + +300 + `as£¹ +( +lßd + <ð +d•th +); + +302 ià( +lßd + == 0)  0; + +304  +»tœed + = 0; + +305  +lßd + > 0 && +»tœed + < +c +) { + +306 ià(! +»ady_li¡ +. + `© +( +ž +)) + +309 +ž + = (ž + 1è% +d•th +; + +310 +lßd +--; + +311 +»tœed +++; + +314  +»tœed +; + +315 + } +} + +318  + gWšdow +:: + $£t_»ady +( +addr +,  +mask +) + +320 ià( +lßd + == 0) ; + +322  +i + = 0; i < +lßd +; i++) { + +323  +šdex + = ( +ž + + +i +è% +d•th +; + +324 ià(( +addr_li¡ +. + `© +( +šdex +è& +mask +è!ð( +addr + & mask)) + +326 +»ady_li¡ +. + `© +( +šdex +èð +Œue +; + +328 + } +} + +332 + gT¿û +:: + $T¿û +(cÚ¡ * +Œaû_âame +è: + `fže +Ñ¿û_âame), + $Œaû_Çme +( +Œaû_âame +) + +334 ià(! +fže +. + `good +()) { + +335 +¡d +:: +û¼ + << "Bad¿û fže: " << +Œaû_âame + << std:: +’dl +; + +336 + `ex™ +(1); + +338 + } +} + +340 +boÞ + + gT¿û +:: + $g‘_unfž‹»d_»que¡ +(& +bubbË_út +, & +»q_addr +, +Reque¡ +:: +Ty³ +& +»q_ty³ +) + +342 +¡ršg + +lše +; + +343 + `g‘lše +( +fže +, +lše +); + +344 ià( +fže +. + `eof +()) { + +345 +fže +. + `þ—r +(); + +346 +fže +. + `£ekg +(0, fže. +beg +); + +347  +çl£ +; + +349 +size_t + +pos +, +’d +; + +350 +bubbË_út + = +¡d +:: + `¡oul +( +lše +, & +pos +, 10); + +351 +pos + = +lše +. + `fšd_fœ¡_nÙ_of +(' ',…os+1); + +352 +»q_addr + = +¡d +:: + `¡oul +( +lše +. + `sub¡r +( +pos +), & +’d +, 0); + +354 +pos + = +lše +. + `fšd_fœ¡_nÙ_of +(' ',…os+ +’d +); + +356 ià( +pos + =ð +¡ršg +:: +Åos + || +lše +. + `sub¡r +(pos)[0] == 'R') + +357 +»q_ty³ + = +Reque¡ +:: +Ty³ +:: +READ +; + +358 ià( +lše +. + `sub¡r +( +pos +)[0] == 'W') + +359 +»q_ty³ + = +Reque¡ +:: +Ty³ +:: +WRITE +; + +360 + `as£¹ +( +çl£ +); + +361  +Œue +; + +362 + } +} + +364 +boÞ + + gT¿û +:: + $g‘_fž‹»d_»que¡ +(& +bubbË_út +, & +»q_addr +, +Reque¡ +:: +Ty³ +& +»q_ty³ +) + +366  +boÞ + +has_wr™e + = +çl£ +; + +367  +wr™e_addr +; + +368  +lše_num + = 0; + +369 ià( +has_wr™e +){ + +370 +bubbË_út + = 0; + +371 +»q_addr + = +wr™e_addr +; + +372 +»q_ty³ + = +Reque¡ +:: +Ty³ +:: +WRITE +; + +373 +has_wr™e + = +çl£ +; + +374  +Œue +; + +376 +¡ršg + +lše +; + +377 + `g‘lše +( +fže +, +lše +); + +378 +lše_num + ++; + +379 ià( +fže +. + `eof +(è|| +lše +. + `size +() == 0) { + +380 +fže +. + `þ—r +(); + +381 +fže +. + `£ekg +(0, fže. +beg +); + +382 +has_wr™e + = +çl£ +; + +383 +lše_num + = 0; + +384  +çl£ +; + +387 +size_t + +pos +, +’d +; + +388 +bubbË_út + = +¡d +:: + `¡oul +( +lše +, & +pos +, 10); + +390 +pos + = +lše +. + `fšd_fœ¡_nÙ_of +(' ',…os+1); + +391 +»q_addr + = + `¡oul +( +lše +. + `sub¡r +( +pos +), & +’d +, 0); + +392 +»q_ty³ + = +Reque¡ +:: +Ty³ +:: +READ +; + +394 +pos + = +lše +. + `fšd_fœ¡_nÙ_of +(' ',…os+ +’d +); + +395 ià( +pos + !ð +¡ršg +:: +Åos +){ + +396 +has_wr™e + = +Œue +; + +397 +wr™e_addr + = + `¡oul +( +lše +. + `sub¡r +( +pos +), +NULL +, 0); + +399  +Œue +; + +400 + } +} + +402 +boÞ + + gT¿û +:: + $g‘_d¿mŒaû_»que¡ +(& +»q_addr +, +Reque¡ +:: +Ty³ +& +»q_ty³ +) + +404 +¡ršg + +lše +; + +405 + `g‘lše +( +fže +, +lše +); + +406 ià( +fže +. + `eof +()) { + +407  +çl£ +; + +409 +size_t + +pos +; + +410 +»q_addr + = +¡d +:: + `¡oul +( +lše +, & +pos +, 16); + +412 +pos + = +lše +. + `fšd_fœ¡_nÙ_of +(' ',…os+1); + +414 ià( +pos + =ð +¡ršg +:: +Åos + || +lše +. + `sub¡r +(pos)[0] == 'R') + +415 +»q_ty³ + = +Reque¡ +:: +Ty³ +:: +READ +; + +416 ià( +lše +. + `sub¡r +( +pos +)[0] == 'W') + +417 +»q_ty³ + = +Reque¡ +:: +Ty³ +:: +WRITE +; + +418 + `as£¹ +( +çl£ +); + +419  +Œue +; + +420 + } +} + + @Processor.h + +1 #iâdeà +__PROCESSOR_H + + +2  + #__PROCESSOR_H + + + ) + +4  + ~"Cache.h +" + +5  + ~"CÚfig.h +" + +6  + ~"MemÜy.h +" + +7  + ~"Reque¡.h +" + +8  + ~"Sti¡ics.h +" + +9  + ~ + +10  + ~ + +11  + ~ + +12  + ~<¡ršg +> + +13  + ~<ùy³.h +> + +14  + ~ + +16 +Çme¥aû + + g¿muÏtÜ + + +19 þas  + cT¿û + { + +20 + gpublic +: + +21 +T¿û +(cÚ¡ * +Œaû_âame +); + +24 +boÞ + +g‘_unfž‹»d_»que¡ +(& +bubbË_út +, & +»q_addr +, +Reque¡ +:: +Ty³ +& +»q_ty³ +); + +25 +boÞ + +g‘_fž‹»d_»que¡ +(& +bubbË_út +, & +»q_addr +, +Reque¡ +:: +Ty³ +& +»q_ty³ +); + +28 +boÞ + +g‘_d¿mŒaû_»que¡ +(& +»q_addr +, +Reque¡ +:: +Ty³ +& +»q_ty³ +); + +30 + g´iv©e +: + +31 +¡d +:: +if¡»am + +fže +; + +32 + g¡d +:: +¡ršg + +Œaû_Çme +; + +36 þas  + cWšdow + { + +37 + gpublic +: + +38  +c + = 4; + +39  + gd•th + = 128; + +41 +Wšdow +(è: +»ady_li¡ +( +d•th +), +addr_li¡ +(depth, -1) {} + +42 +boÞ + +is_fuÎ +(); + +43 +boÞ + +is_em±y +(); + +44  +š£¹ +( +boÞ + +»ady +,  +addr +); + +45  +»tœe +(); + +46  +£t_»ady +( +addr +,  +mask +); + +48 + g´iv©e +: + +49  +lßd + = 0; + +50  + gh—d + = 0; + +51  + gž + = 0; + +52 + g¡d +:: +veùÜ +< +boÞ +> +»ady_li¡ +; + +53 + g¡d +:: +veùÜ +<> +addr_li¡ +; + +57 þas  + cCÜe + { + +58 + gpublic +: + +59  +þk + = 0; + +60  + g»tœed + = 0; + +61  + gid + = 0; + +62 + gfunùiÚ +< +boÞ +( +Reque¡ +)> + g£nd +; + +64 +CÜe +(cÚ¡ +CÚfig +& +cÚfigs +,  +cÜeid +, + +65 cÚ¡ * +Œaû_âame +, + +66 +funùiÚ +< +boÞ +( +Reque¡ +)> +£nd_Ãxt +, +Cache +* +Îc +, + +67 +¡d +:: +sh¬ed_±r +< +CacheSy¡em +> +ÿchesys +, +MemÜyBa£ +& +memÜy +); + +68  +tick +(); + +69  +»ûive +( +Reque¡ +& +»q +); + +70  +ÿlc_c +(); + +71 +boÞ + +fšished +(); + +72 +boÞ + +has_»ached_lim™ +(); + +73 + gfunùiÚ +<( + gReque¡ +&)> + gÿÎback +; + +75 +boÞ + + gno_cÜe_ÿches + = +Œue +; + +76 +boÞ + + gno_sh¬ed_ÿche + = +Œue +; + +77  + gl1_size + = 1 << 15; + +78  + gl1_assoc + = 1 << 3; + +79  + gl1_blocksz + = 1 << 6; + +80  + gl1_mshr_num + = 16; + +82  + gl2_size + = 1 << 18; + +83  + gl2_assoc + = 1 << 3; + +84  + gl2_blocksz + = 1 << 6; + +85  + gl2_mshr_num + = 16; + +86 + g¡d +:: +veùÜ +< +¡d +:: +sh¬ed_±r +< +Cache +>> +ÿches +; + +87 +Cache +* + gÎc +; + +89 +SÿÏrSt + + g»cÜd_cycs +; + +90 +SÿÏrSt + + g»cÜd_š¡s +; + +91  + gex³ùed_lim™_š¡s +; + +93 +boÞ + + g»ached_lim™ + = +çl£ +; + +95 + g´iv©e +: + +96 +T¿û + +Œaû +; + +97 +Wšdow + + gwšdow +; + +99  + gbubbË_út +; + +100  + g»q_addr + = -1; + +101 + gReque¡ +:: +Ty³ + +»q_ty³ +; + +102 +boÞ + + gmÜe_»qs +; + +103  + gÏ¡ + = 0; + +105 +SÿÏrSt + + gmemÜy_acûss_cyþes +; + +106 +SÿÏrSt + + gýu_š¡ +; + +107 + gMemÜyBa£ +& + gmemÜy +; + +110 þas  + cProûssÜ + { + +111 + gpublic +: + +112 +ProûssÜ +(cÚ¡ +CÚfig +& +cÚfigs +, +veùÜ + +Œaû_li¡ +, + +113 +funùiÚ +< +boÞ +( +Reque¡ +)> +£nd +, +MemÜyBa£ +& +memÜy +); + +114  +tick +(); + +115  +»ûive +( +Reque¡ +& +»q +); + +116 +boÞ + +fšished +(); + +117 +boÞ + +has_»ached_lim™ +(); + +119 + g¡d +:: +veùÜ +< +¡d +:: +unique_±r +< +CÜe +>> +cÜes +; + +120 + g¡d +:: +veùÜ +<> +cs +; + +121  + gc + = 0; + +124 +boÞ + + g—¾y_ex™ +; + +126 +boÞ + + gno_cÜe_ÿches + = +Œue +; + +127 +boÞ + + gno_sh¬ed_ÿche + = +Œue +; + +129  + gl3_size + = 1 << 23; + +130  + gl3_assoc + = 1 << 3; + +131  + gl3_blocksz + = 1 << 6; + +132  + gmshr_³r_bªk + = 16; + +134 + g¡d +:: +sh¬ed_±r +< +CacheSy¡em +> +ÿchesys +; + +135 +Cache + + gÎc +; + +137 +SÿÏrSt + + gýu_cyþes +; + + @Refresh.cpp + +10  + ~<¡dlib.h +> + +12  + ~"Reäesh.h +" + +13  + ~"CÚŒÞËr.h +" + +14  + ~"DRAM.h +" + +15  + ~"DSARP.h +" + +17 +usšg + +Çme¥aû + + g¡d +; + +18 +usšg + +Çme¥aû + + g¿muÏtÜ +; + +20 +Çme¥aû + + g¿muÏtÜ + { + +23 + g‹m¶©e +<> + +24 + gReäesh +< + gDSARP +>:: +Reäesh +( +CÚŒÞËr +< +DSARP +>* +ù¾ +) : ctrl(ctrl) { + +25 +þk + = +»äeshed + = 0; + +26 + gmax_¿nk_couÁ + = +ù¾ +-> +chªÃl +-> +chžd»n +. +size +(); + +27 + gmax_bªk_couÁ + = +ù¾ +-> +chªÃl +-> +¥ec +-> +Üg_’Œy +. +couÁ +[() +DSARP +:: +Lev– +:: +Bªk +]; + +28 + gmax_§_couÁ + = +ù¾ +-> +chªÃl +-> +¥ec +-> +Üg_’Œy +. +couÁ +[() +DSARP +:: +Lev– +:: +SubA¼ay +]; + +31  + gr + = 0;„ < + gmax_¿nk_couÁ +;„++) { + +32 + gbªk_»f_couÁ”s +. +push_back +(0); + +33 + gbªk_»äesh_backlog +. +push_back +( +Ãw + +veùÜ +<>( +max_bªk_couÁ +, 0)); + +34 + gveùÜ +<> +§_couÁ”s +( +ù¾ +-> +chªÃl +-> +¥ec +-> +Üg_’Œy +. +couÁ +[() +DSARP +:: +Lev– +:: +SubA¼ay +], 0); + +35 + gsub¬¿y_»f_couÁ”s +. +push_back +( +§_couÁ”s +); + +38 + gËv–_chª + = () +DSARP +:: +Lev– +:: +ChªÃl +; + +39 + gËv–_¿nk + = () +DSARP +:: +Lev– +:: +Rªk +; + +40 + gËv–_bªk + = () +DSARP +:: +Lev– +:: +Bªk +; + +41 + gËv–_§ + = () +DSARP +:: +Lev– +:: +SubA¼ay +; + +44 + g‹m¶©e +<> + +45  + gReäesh +< + gDSARP +>:: +—¾y_šjeù_»äesh +() { + +47 ià( +ù¾ +-> +wr™e_mode +) + +51 + gveùÜ +< + gboÞ +> +is_bªk_occup›d +( +max_¿nk_couÁ + * +max_bªk_couÁ +, +çl£ +); + +52 + gCÚŒÞËr +< + gDSARP +>:: +Queue +& +rdq + = +ù¾ +-> +»adq +; + +55 autØ + g»q +: +rdq +. +q +) + +57 +as£¹ +( +»q +. +addr_vec +[ +Ëv–_chª +] =ð +ù¾ +-> +chªÃl +-> +id +); + +58  + gridx + = +»q +. +addr_vec +[ +Ëv–_¿nk +] * +max_bªk_couÁ +; + +59  + gbidx + = +»q +. +addr_vec +[ +Ëv–_bªk +]; + +60 + gis_bªk_occup›d +[ +ridx ++ +bidx +] = +Œue +; + +64  + gr + = 0;„ < + gmax_¿nk_couÁ +;„++) { + +66  + gbidx_¡¬t + = +¿nd +(è% +max_bªk_couÁ +; + +68  + gb + = 0; b < + gmax_bªk_couÁ +; b++) + +70  + gbidx + = ( +bidx_¡¬t + + +b +è% +max_bªk_couÁ +; + +72 ià( + gis_bªk_occup›d +[( +r + * +max_bªk_couÁ +è+ +bidx +]) + +76 +boÞ + + g³ndšg_»f + = +çl£ +; + +77  +Reque¡ + + g»q + : +ù¾ +-> +Ùh”q +. +q +) + +78 ià( +»q +. +ty³ + =ð +Reque¡ +:: +Ty³ +:: +REFRESH + + +79 && +»q +. +addr_vec +[ +Ëv–_chª +] =ð +ù¾ +-> +chªÃl +-> +id + + +80 && +»q +. +addr_vec +[ +Ëv–_¿nk +] =ð +r + &&„eq.addr_vec[ +Ëv–_bªk +] =ð +bidx +) + +81 +³ndšg_»f + = +Œue +; + +82 ià( + g³ndšg_»f +) + +86 ià((*( + gbªk_»äesh_backlog +[ +r +]))[ +bidx +] >ð +backlog_—¾y_puÎ_th»shÞd + || + +87 +ù¾ +-> +Ùh”q +. +q +. +size +(è>ðù¾->Ùh”q. +max +) + +91 +»äesh_rg‘ +( +ù¾ +, +r +, +bidx +, +sub¬¿y_»f_couÁ”s +[r][bidx]); + +93 (*( + gbªk_»äesh_backlog +[ +r +]))[ +bidx +]++; + +94 + gsub¬¿y_»f_couÁ”s +[ +r +][ +bidx +] = ( +sub¬¿y_»f_couÁ”s +[r][bidx]+1è% +max_§_couÁ +; + +100 + g‹m¶©e +<> + +101  + gReäesh +< + gDSARP +>:: +šjeù_»äesh +( +boÞ + +b_»f_¿nk +) { + +103 ià( +b_»f_¿nk +) + +104 autØ +¿nk + : +ù¾ +-> +chªÃl +-> +chžd»n +) + +105 +»äesh_rg‘ +( +ù¾ +, +¿nk +-> +id +, -1, -1); + +108 autØ + g¿nk + : +ù¾ +-> +chªÃl +-> +chžd»n +) { + +109  +rid + = +¿nk +-> +id +; + +110  + gbid + = +bªk_»f_couÁ”s +[ +rid +]; + +113 (*( + gbªk_»äesh_backlog +[ +rid +]))[ +bid +]--; + +116 + gbªk_»f_couÁ”s +[ +rid +] = ( +bªk_»f_couÁ”s +[rid] + 1è% +max_bªk_couÁ +; + +119 ià( + gù¾ +-> + gchªÃl +-> + g¥ec +-> + gty³ + =ð +DSARP +:: +Ty³ +:: +DARP + || + +120 +ù¾ +-> +chªÃl +-> +¥ec +-> +ty³ + =ð +DSARP +:: +Ty³ +::DSARP) { + +122 +boÞ + +»f_now + = +çl£ +; + +124 +boÞ + + g³ndšg_»f + = +çl£ +; + +125  +Reque¡ + + g»q + : +ù¾ +-> +Ùh”q +. +q +) { + +126 ià( +»q +. +ty³ + =ð +Reque¡ +:: +Ty³ +:: +REFRESH +) { + +127 +³ndšg_»f + = +Œue +; + +133 ià(! + g³ndšg_»f + && + gù¾ +-> + g»adq +. +size +() == 0) + +134 +»f_now + = +Œue +; + +137 ià((*( + gbªk_»äesh_backlog +[ +rid +]))[ +bid +] <ð +backlog_mš +) + +138 +»f_now + = +Œue +; + +141 ià(! + g»f_now +) + +145 +»äesh_rg‘ +( +ù¾ +, +rid +, +bid +, +sub¬¿y_»f_couÁ”s +[rid][bid]); + +147 (*( + gbªk_»äesh_backlog +[ +rid +]))[ +bid +]++; + +149 + gsub¬¿y_»f_couÁ”s +[ +rid +][ +bid +] = ( +sub¬¿y_»f_couÁ”s +[rid][bid]+1è% +max_§_couÁ +; + +152 + g»äeshed + = +þk +; + +156  + g·œ +<, > + twrq_idx +; + +157 +boÞ + +wrq_comp + ( +wrq_idx + +l +, wrq_idx +r +) + +159  + gl +. + gfœ¡ + < + gr +.first; + +163 + g‹m¶©e +<> + +164  + gReäesh +< + gDSARP +>:: +w½ +() { + +165  +»f_rid + = 0; + g»f_rid + < + gmax_¿nk_couÁ +;„ef_rid++) + +168 +boÞ + + g³ndšg_»f + = +çl£ +; + +169  +Reque¡ + + g»q + : +ù¾ +-> +Ùh”q +. +q +) { + +170 ià( +»q +. +ty³ + =ð +Reque¡ +:: +Ty³ +:: +REFRESH + &&„eq. +addr_vec +[ +Ëv–_¿nk +] =ð +»f_rid +) { + +171 +³ndšg_»f + = +Œue +; + +175 ià( + g³ndšg_»f +) + +179 + gveùÜ +< + gwrq_idx +> + gsÜ‹d_bªk_demªd +; + +180  + gb + = 0; b < + gmax_bªk_couÁ +; b++) + +181 + gsÜ‹d_bªk_demªd +. +push_back +( +wrq_idx +(0, +b +)); + +183  + gtÙ®_wr + = 0; + +184 autØ + g»q + : +ù¾ +-> +wr™eq +. +q +) { + +185 ià( +»q +. +addr_vec +[ +Ëv–_¿nk +] =ð +»f_rid +) { + +186 +sÜ‹d_bªk_demªd +[ +»q +. +addr_vec +[ +Ëv–_bªk +]]. +fœ¡ +++; + +187 + gtÙ®_wr +++; + +191 ià( + gtÙ®_wr + == 0) + +195 autØ + g»q + : +ù¾ +-> +»adq +. +q +) + +196 ià( +»q +. +addr_vec +[ +Ëv–_¿nk +] =ð +»f_rid +) + +197 +sÜ‹d_bªk_demªd +[ +»q +. +addr_vec +[ +Ëv–_bªk +]]. +fœ¡ +++; + +200 + g¡d +:: +sÜt +( +sÜ‹d_bªk_demªd +. +begš +(), sÜ‹d_bªk_demªd. +’d +(), +wrq_comp +); + +203  + gtÝ_idË_idx + = 0; + +204  + gi + = 0; i < + gmax_bªk_couÁ +; i++) { + +205 ià( + gsÜ‹d_bªk_demªd +[ +i +]. + g£cÚd + != 0) { + +206 +tÝ_idË_idx + = +i +; + +212  + g»f_bid_idx + = ( +tÝ_idË_idx + =ð0è? 0 : +¿nd +() %op_idle_idx; + +213  + g»f_bid + = +sÜ‹d_bªk_demªd +[ +»f_bid_idx +]. +£cÚd +; + +216 ià((*( + gbªk_»äesh_backlog +[ +»f_rid +]))[ +»f_bid +] < + gbacklog_max + + +217 && + gù¾ +-> + gÙh”q +. + gq +. +size +(è< cŒl->Ùh”q. + gmax +) { + +218 +»äesh_rg‘ +( +ù¾ +, +»f_rid +, +»f_bid +, +sub¬¿y_»f_couÁ”s +[ref_rid][ref_bid]); + +220 (*( + gbªk_»äesh_backlog +[ +»f_rid +]))[ +»f_bid +]++; + +221 + gsub¬¿y_»f_couÁ”s +[ +»f_rid +][ +»f_bid +] = ( +sub¬¿y_»f_couÁ”s +[»f_rid][»f_bid]+1è% +max_§_couÁ +; + +227 + g‹m¶©e +<> + +228  + gReäesh +< + gDSARP +>:: +tick_»f +() { + +229 +þk +++; + +231 +boÞ + + gb_»f_¿nk + = +ù¾ +-> +chªÃl +-> +¥ec +-> +b_»f_¿nk +; + +232  + g»äesh_š‹rv® + = + +233 ( +b_»f_¿nk +) ? + +234 +ù¾ +-> +chªÃl +-> +¥ec +-> +¥“d_’Œy +. +nREFI + : + +235 +ù¾ +-> +chªÃl +-> +¥ec +-> +¥“d_’Œy +. +nREFIpb +; + +238 ià( + gù¾ +-> + gchªÃl +-> + g¥ec +-> + gty³ + =ð +DSARP +:: +Ty³ +:: +DARP + || + +239 +ù¾ +-> +chªÃl +-> +¥ec +-> +ty³ + =ð +DSARP +:: +Ty³ +::DSARP) { + +241 ià(! +ù¾_wr™e_mode + && +ù¾ +-> +wr™e_mode +) + +242 +w½ +(); + +244 + gù¾_wr™e_mode + = +ù¾ +-> +wr™e_mode +; + +246 +—¾y_šjeù_»äesh +(); + +250 ià(( + gþk + - + g»äeshed +è>ð +»äesh_š‹rv® +) + +251 +šjeù_»äesh +( +b_»f_¿nk +); + + @Refresh.h + +16 #iâdeà +__REFRESH_H_ + + +17  + #__REFRESH_H_ + + + ) + +19  + ~<¡ddef.h +> + +20  + ~<ÿs£¹ +> + +21  + ~ + +22  + ~ + +24  + ~"Reque¡.h +" + +25  + ~"DSARP.h +" + +26  + ~"ALDRAM.h +" + +28 +usšg + +Çme¥aû + + g¡d +; + +29 +usšg + +Çme¥aû + + g¿muÏtÜ +; + +31 +Çme¥aû + + g¿muÏtÜ + { + +33 + g‹m¶©e + < +ty³Çme + + gT +> + +34 +þass + + gCÚŒÞËr +; + +36 + g‹m¶©e + < +ty³Çme + + gT +> + +37 þas  + cReäesh + { + +38 + gpublic +: + +39 +CÚŒÞËr +< +T +>* +ù¾ +; + +40  + gþk +, + g»äeshed +; + +42 + gveùÜ +<> + gbªk_»f_couÁ”s +; + +43  + gmax_¿nk_couÁ +, + gmax_bªk_couÁ +; + +44  + gËv–_chª +, + gËv–_¿nk +, + gËv–_bªk +, + gËv–_§ +; + +47 +Reäesh +( +CÚŒÞËr +< +T +>* +ù¾ +) : ctrl(ctrl) { + +48 +þk + = +»äeshed + = 0; + +49 + gmax_¿nk_couÁ + = +ù¾ +-> +chªÃl +-> +chžd»n +. +size +(); + +50 + gmax_bªk_couÁ + = +ù¾ +-> +chªÃl +-> +¥ec +-> +Üg_’Œy +. +couÁ +[() +T +:: +Lev– +:: +Bªk +]; + +53  + gr + = 0;„ < + gmax_¿nk_couÁ +;„++) { + +54 + gbªk_»f_couÁ”s +. +push_back +(0); + +55 + gbªk_»äesh_backlog +. +push_back +( +Ãw + +veùÜ +<>( +max_bªk_couÁ +, 0)); + +58 + gËv–_chª + = () +T +:: +Lev– +:: +ChªÃl +; + +59 + gËv–_¿nk + = () +T +:: +Lev– +:: +Rªk +; + +60 + gËv–_bªk + = () +T +:: +Lev– +:: +Bªk +; + +61 + gËv–_§ + = -1; + +65 + gvœtu® + ~ +Reäesh +() { + +67  + gi + = 0; i < + gbªk_»äesh_backlog +. +size +(); i++) + +68 +d–‘e + + gbªk_»äesh_backlog +[ +i +]; + +72  +tick_»f +() { + +73 + gþk +++; + +75  + g»äesh_š‹rv® + = +ù¾ +-> +chªÃl +-> +¥ec +-> +¥“d_’Œy +. +nREFI +; + +78 ià(( + gþk + - + g»äeshed +è>ð +»äesh_š‹rv® +) { + +79 +šjeù_»äesh +( +Œue +); + +81 + gALDRAM +:: +Temp + +cu¼’t_‹m³¿tu» + = +ALDRAM +::Temp:: +COLD +; + +82 + gù¾ +-> +upd©e_‹mp +( +cu¼’t_‹m³¿tu» +); + +86 + g´iv©e +: + +88 +veùÜ +*> +bªk_»äesh_backlog +; + +90 + gveùÜ +> + gsub¬¿y_»f_couÁ”s +; + +91  + gmax_§_couÁ + = 0; + +93  + gbacklog_max + = 8; + +94  + gbacklog_mš + = -8; + +95  + gbacklog_—¾y_puÎ_th»shÞd + = -6; + +96 +boÞ + + gù¾_wr™e_mode + = +çl£ +; + +99  +»äesh_rg‘ +( +CÚŒÞËr +< +T +>* +ù¾ +,  +¿nk +,  +bªk +,  +§ +) + +101 + gveùÜ +<> +addr_vec +(( +T +:: +Lev– +:: +MAX +), -1); + +102 + gaddr_vec +[0] = +ù¾ +-> +chªÃl +-> +id +; + +103 + gaddr_vec +[1] = +¿nk +; + +104 + gaddr_vec +[2] = +bªk +; + +105 + gaddr_vec +[3] = +§ +; + +106 +Reque¡ + +»q +( +addr_vec +, Reque¡:: +Ty³ +:: +REFRESH +, +NULL +); + +107 +boÞ + + g»s + = +ù¾ +-> +’queue +( +»q +); + +108 +as£¹ +( +»s +); + +112  +šjeù_»äesh +( +boÞ + +b_»f_¿nk +) { + +114 ià( + gb_»f_¿nk +) { + +115 autØ + g¿nk + : +ù¾ +-> +chªÃl +-> +chžd»n +) + +116 +»äesh_rg‘ +( +ù¾ +, +¿nk +-> +id +, -1, -1); + +120 autØ + g¿nk + : +ù¾ +-> +chªÃl +-> +chžd»n +) + +121 +»äesh_rg‘ +( +ù¾ +, +¿nk +-> +id +, +bªk_»f_couÁ”s +[rank->id], -1); + +123 + g»äeshed + = +þk +; + +127  +—¾y_šjeù_»äesh +(); + +128  +w½ +(); + +133 + g‹m¶©e +<> + gReäesh +< + gDSARP +>:: +Reäesh +( +CÚŒÞËr +< +DSARP +>* +ù¾ +); + +134 + g‹m¶©e +<>  + gReäesh +< + gDSARP +>:: +tick_»f +(); + + @Request.h + +1 #iâdeà +__REQUEST_H + + +2  + #__REQUEST_H + + + ) + +4  + ~ + +5  + ~ + +6  + ~ + +8 +usšg + +Çme¥aû + + g¡d +; + +10 +Çme¥aû + + g¿muÏtÜ + + +13 þas  + cReque¡ + + +15 + gpublic +: + +16 +boÞ + +is_fœ¡_commªd +; + +17  + gaddr +; + +20 + gveùÜ +<> + gaddr_vec +; + +23  + gcÜeid +; + +31  + gÝIdx +; + +34  + gd•¬tPeTime +; + +35  + g¬riveMemTime +; + +36  + gd•¬tMemTime +; + +37  + g¬rivePeTime +; + +39  + g»qNum +; + +40  + gËngth +; + +47  + g³Idx +; + +49 þas  + cTy³ + + +51 + gREAD +, + +52 + gWRITE +, + +53 + gREFRESH +, + +54 + gPOWERDOWN +, + +55 + gSELFREFRESH +, + +56 + gEXTENSION +, + +57 + gMAX + + +58 } + gty³ +; + +60  + g¬rive + = -1; + +61  + gd•¬t +; + +62 + gfunùiÚ +<( + gReque¡ +&)> + gÿÎback +; + +64 +Reque¡ +( +addr +, +Ty³ + +ty³ +,  +cÜeid + = 0) + +65 : +is_fœ¡_commªd +( +Œue +), +addr +×ddr), +cÜeid +(cÜeid), +ty³ +(type), + +66 +ÿÎback +([]( +Reque¡ +& +»q +){}) { + +69 +Reque¡ +( +addr +, +Ty³ + +ty³ +, +funùiÚ +<(Reque¡&)> +ÿÎback +,  +cÜeid + = 0) + +70 : +is_fœ¡_commªd +( +Œue +), +addr +×ddr), +cÜeid +(cÜeid), +ty³ +Ñy³), +ÿÎback +(callback) { + +73 +Reque¡ +( +veùÜ +<>& +addr_vec +, +Ty³ + +ty³ +, +funùiÚ +<(Reque¡&)> +ÿÎback +,  +cÜeid + = 0) + +74 : +is_fœ¡_commªd +( +Œue +), +addr_vec +×ddr_vec), +cÜeid +(cÜeid), +ty³ +Ñy³), +ÿÎback +(callback) { + +77 +Reque¡ +() + +78 : +is_fœ¡_commªd +( +Œue +), +cÜeid +(0) { + + @SALP.cpp + +1  + ~"SALP.h +" + +2  + ~"DRAM.h +" + +3  + ~ + +4  + ~ + +5  + ~<ÿs£¹ +> + +7 +usšg + +Çme¥aû + + g¿muÏtÜ +; + +9 + gm­ +< + g¡ršg +, + gSALP +:: +Org +> +SALP +:: +Üg_m­ + = { + +10 {"SALP_512Mb_x4", +SALP +:: +Org +:: +SALP_512Mb_x4 +}, {"SALP_512Mb_x8", SALP::Org:: +SALP_512Mb_x8 +}, {"SALP_512Mb_x16", SALP::Org:: +SALP_512Mb_x16 +}, + +11 {"SALP_1Gb_x4", +SALP +:: +Org +:: +SALP_1Gb_x4 +}, {"SALP_1Gb_x8", SALP::Org:: +SALP_1Gb_x8 +}, {"SALP_1Gb_x16", SALP::Org:: +SALP_1Gb_x16 +}, + +12 {"SALP_2Gb_x4", +SALP +:: +Org +:: +SALP_2Gb_x4 +}, {"SALP_2Gb_x8", SALP::Org:: +SALP_2Gb_x8 +}, {"SALP_2Gb_x16", SALP::Org:: +SALP_2Gb_x16 +}, + +13 {"SALP_4Gb_x4", +SALP +:: +Org +:: +SALP_4Gb_x4 +}, {"SALP_4Gb_x8", SALP::Org:: +SALP_4Gb_x8 +}, {"SALP_4Gb_x16", SALP::Org:: +SALP_4Gb_x16 +}, + +14 {"SALP_8Gb_x4", +SALP +:: +Org +:: +SALP_8Gb_x4 +}, {"SALP_8Gb_x8", SALP::Org:: +SALP_8Gb_x8 +}, {"SALP_8Gb_x16", SALP::Org:: +SALP_8Gb_x16 +}, + +17 + gm­ +< + g¡ršg +, + gSALP +:: +S³ed +> +SALP +:: +¥“d_m­ + = { + +18 {"SALP_800D", +SALP +:: +S³ed +:: +SALP_800D +}, {"SALP_800E", SALP::S³ed:: +SALP_800E +}, + +19 {"SALP_1066E", +SALP +:: +S³ed +:: +SALP_1066E +}, {"SALP_1066F", SALP::S³ed:: +SALP_1066F +}, {"SALP_1066G", SALP::S³ed:: +SALP_1066G +}, + +20 {"SALP_1333G", +SALP +:: +S³ed +:: +SALP_1333G +}, {"SALP_1333H", SALP::S³ed:: +SALP_1333H +}, + +21 {"SALP_1600H", +SALP +:: +S³ed +:: +SALP_1600H +}, {"SALP_1600J", SALP::S³ed:: +SALP_1600J +}, {"SALP_1600K", SALP::S³ed:: +SALP_1600K +}, + +22 {"SALP_1866K", +SALP +:: +S³ed +:: +SALP_1866K +}, {"SALP_1866L", SALP::S³ed:: +SALP_1866L +}, + +23 {"SALP_2133L", +SALP +:: +S³ed +:: +SALP_2133L +}, {"SALP_2133M", SALP::S³ed:: +SALP_2133M +}, + +26 + gm­ +< + g¡ršg +, + gSALP +:: +Ty³ +> +SALP +:: +ty³_m­ + = { + +27 {"SALP-1", +SALP +:: +Ty³ +:: +SALP_1 +}, + +28 {"SALP-2", +SALP +:: +Ty³ +:: +SALP_2 +}, + +29 {"SALP-MASA", +SALP +:: +Ty³ +:: +MASA +}, + +32 + gSALP +:: + $SALP +( +Org + +Üg +, +S³ed + +¥“d +, +Ty³ + +ty³ +,  +n_§ +) : + +33 + `ty³ +( +ty³ +), + +34 + `n_§ +( +n_§ +), + +35 + `Üg_’Œy +( +Üg_bË +[( +Üg +)]), + +36 + `¥“d_’Œy +( +¥“d_bË +[( +¥“d +)]), + +37 + `»ad_Ï‹ncy +( +¥“d_’Œy +. +nCL + + s³ed_’Œy. +nBL +) + +39 ( +ty³ +)){ + +40 ( +Ty³ +:: +SALP_1 +): +¡ªd¬d_Çme + = "SALP-1"; ; + +41 ( +Ty³ +:: +SALP_2 +): +¡ªd¬d_Çme + = "SALP-2"; ; + +42 ( +Ty³ +:: +MASA +): +¡ªd¬d_Çme + = "SALP-MASA"; ; + +44 ià( +ty³ + =ð +Ty³ +:: +SALP_1 +) { + +45 +scÝe +[( +Commªd +:: +PRE +)] = +Lev– +:: +Bªk +; + +47 + `as£¹ +( +n_§ + &&‚_sa <= 128 && (n_sa & (n_sa-1)) == 0); + +48 +Üg_’Œy +. +couÁ +[( +Lev– +:: +SubA¼ay +)] = +n_§ +; + +49  +tmp + = ( +Üg_’Œy +. +dq +è* org_’Œy. +couÁ +[( +Lev– +:: +Bªk +)] * +n_§ + * org_’Œy.couÁ[(Lev–:: +CÞumn +)]; + +50 +Üg_’Œy +. +couÁ +[( +Lev– +:: +Row +)] = (Üg_’Œy. +size +è* (1<<20è/ +tmp +; + +51 + `š™_¥“d +(); + +52 + `š™_´”eq +(); + +53 + `š™_rowh™ +(); + +54 + `š™_rowÝ’ +(); + +55 + `š™_Ïmbda +(); + +56 + `š™_timšg +(); + +57 + } +} + +59 + gSALP +:: + $SALP +(cÚ¡ +¡ršg +& +Üg_¡r +, cÚ¡ sŒšg& +¥“d_¡r +, cÚ¡ sŒšg& +ty³_¡r +,  +n_§ +) : + +60 + $SALP +( +Üg_m­ +[ +Üg_¡r +], +¥“d_m­ +[ +¥“d_¡r +], +ty³_m­ +[ +ty³_¡r +], +n_§ +) + +62 + } +} + +64  + gSALP +:: + $£t_chªÃl_numb” +( +chªÃl +) { + +65 +Üg_’Œy +. +couÁ +[( +Lev– +:: +ChªÃl +)] = +chªÃl +; + +66 + } +} + +68  + gSALP +:: + $£t_¿nk_numb” +( +¿nk +) { + +69 +Üg_’Œy +. +couÁ +[( +Lev– +:: +Rªk +)] = +¿nk +; + +70 + } +} + +72  + gSALP +:: + $š™_¥“d +() + +75  +·ge + = ( +Üg_’Œy +. +dq + * org_’Œy. +couÁ +[( +Lev– +:: +CÞumn +)]) >> 13; + +76  +¥“d_’Œy +. +¿‹ +) { + +77 800: +¥“d_’Œy +. +nRRD + = ( +·ge +==1è? 4 : 4; s³ed_’Œy. +nFAW + = (page==1) ? 16 : 20; ; + +78 1066: +¥“d_’Œy +. +nRRD + = ( +·ge +==1è? 4 : 6; s³ed_’Œy. +nFAW + = (page==1) ? 20 : 27; ; + +79 1333: +¥“d_’Œy +. +nRRD + = ( +·ge +==1è? 4 : 5; s³ed_’Œy. +nFAW + = (page==1) ? 20 : 30; ; + +80 1600: +¥“d_’Œy +. +nRRD + = ( +·ge +==1è? 5 : 6; s³ed_’Œy. +nFAW + = (page==1) ? 24 : 32; ; + +81 1866: +¥“d_’Œy +. +nRRD + = ( +·ge +==1è? 5 : 6; s³ed_’Œy. +nFAW + = (page==1) ? 26 : 33; ; + +82 2133: +¥“d_’Œy +. +nRRD + = ( +·ge +==1è? 5 : 6; s³ed_’Œy. +nFAW + = (page==1) ? 27 : 34; ; + +83 : + `as£¹ +( +çl£ +); + +87  +ch + = +Üg_’Œy +. +size +; + +88  +¥“d_’Œy +. +¿‹ +) { + +89 800: +¥“d_’Œy +. +nRFC + = ( +ch +==512) ? 36 : (chip==1<<10) ? 44 : (chip==1<<11) ? 64 : (chip==1<<12) ? 104 : 140; ; + +90 1066: +¥“d_’Œy +. +nRFC + = ( +ch +==512) ? 48 : (chip==1<<10) ? 59 : (chip==1<<11) ? 86 : (chip==1<<12) ? 139 : 187; ; + +91 1333: +¥“d_’Œy +. +nRFC + = ( +ch +==512) ? 60 : (chip==1<<10) ? 74 : (chip==1<<11) ? 107 : (chip==1<<12) ? 174 : 234; ; + +92 1600: +¥“d_’Œy +. +nRFC + = ( +ch +==512) ? 72 : (chip==1<<10) ? 88 : (chip==1<<11) ? 128 : (chip==1<<12) ? 208 : 280; ; + +93 1866: +¥“d_’Œy +. +nRFC + = ( +ch +==512) ? 84 : (chip==1<<10) ? 103 : (chip==1<<11) ? 150 : (chip==1<<12) ? 243 : 327; ; + +94 2133: +¥“d_’Œy +. +nRFC + = ( +ch +==512) ? 96 : (chip==1<<10) ? 118 : (chip==1<<11) ? 171 : (chip==1<<12) ? 278 : 374; ; + +95 : + `as£¹ +( +çl£ +); + +97  +¥“d_’Œy +. +¿‹ +) { + +98 800: +¥“d_’Œy +. +nXS + = ( +ch +==512) ? 40 : (chip==1<<10) ? 48 : (chip==1<<11) ? 68 : (chip==1<<12) ? 108 : 144; ; + +99 1066: +¥“d_’Œy +. +nXS + = ( +ch +==512) ? 54 : (chip==1<<10) ? 64 : (chip==1<<11) ? 91 : (chip==1<<12) ? 144 : 192; ; + +100 1333: +¥“d_’Œy +. +nXS + = ( +ch +==512) ? 67 : (chip==1<<10) ? 80 : (chip==1<<11) ? 114 : (chip==1<<12) ? 180 : 240; ; + +101 1600: +¥“d_’Œy +. +nXS + = ( +ch +==512) ? 80 : (chip==1<<10) ? 96 : (chip==1<<11) ? 136 : (chip==1<<12) ? 216 : 288; ; + +102 1866: +¥“d_’Œy +. +nXS + = ( +ch +==512) ? 94 : (chip==1<<10) ? 112 : (chip==1<<11) ? 159 : (chip==1<<12) ? 252 : 336; ; + +103 2133: +¥“d_’Œy +. +nXS + = ( +ch +==512) ? 107 : (chip==1<<10) ? 128 : (chip==1<<11) ? 182 : (chip==1<<12) ? 288 : 384; ; + +104 : + `as£¹ +( +çl£ +); + +106 + } +} + +109  + gSALP +:: + $š™_´”eq +() + +111 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +SALP +>* +node +, Commªd +cmd +,  +id +) { + +112 ( +node +-> +¡©e +)) { + +113 ( +S‹ +:: +Pow”Up +):  +Commªd +:: +MAX +; + +114 ( +S‹ +:: +AùPow”Down +):  +Commªd +:: +PDX +; + +115 ( +S‹ +:: +P»Pow”Down +):  +Commªd +:: +PDX +; + +116 ( +S‹ +:: +S–fReäesh +):  +Commªd +:: +SRX +; + +117 : + `as£¹ +( +çl£ +); + +119 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +WR +)] =…»»q[(Lev–::Rªk)][(Commªd:: +RD +)]; + +121 ( +ty³ +)){ + +122 ( +Ty³ +:: +SALP_1 +): + +123 +´”eq +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +SALP +>* +node +, Commªd +cmd +,  +id +) { + +124 ( +node +-> +¡©e +)){ + +125 ( +S‹ +:: +Clo£d +):  +Commªd +:: +ACT +; + +126 ( +S‹ +:: +O³Ãd +): + +127  +Commªd +:: +MAX +; + +128 : + `as£¹ +( +çl£ +);}}; + +129 +´”eq +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] =…»»q[(Lev–::Bªk)][(Commªd:: +RD +)]; + +130 +´”eq +[( +Lev– +:: +SubA¼ay +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +SALP +>* +node +, Commªd +cmd +,  +id +) { + +131 ià( +node +-> +row_¡©e +. + `fšd +( +id +è!ðnode->row_¡©e. + `’d +()) { + +132  +cmd +; + +133 } ià( +node +-> +row_¡©e +. + `size +()) { + +134  +Commªd +:: +PRE +; + +136  +Commªd +:: +PRE_OTHER +; + +139 +´”eq +[( +Lev– +:: +SubA¼ay +)][( +Commªd +:: +WR +)] =…»»q[(Lev–::SubA¼ay)][(Commªd:: +RD +)]; + +140 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +REF +)] = [] ( +DRAM +< +SALP +>* +node +, Commªd +cmd +,  +id +) { + +141 autØ +bªk + : +node +-> +chžd»n +) { + +142 ià( +bªk +-> +¡©e + =ð +S‹ +:: +Clo£d +) + +144  +Commªd +:: +PRER +; + +146  +Commªd +:: +REF +;}; + +148 ( +Ty³ +:: +SALP_2 +): + +149 +´”eq +[( +Lev– +:: +SubA¼ay +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +SALP +>* +node +, Commªd +cmd +,  +id +) { + +150 ( +node +-> +¡©e +)){ + +151 ( +S‹ +:: +Clo£d +):  +Commªd +:: +ACT +; + +152 ( +S‹ +:: +O³Ãd +): + +153 ià( +node +-> +row_¡©e +. + `fšd +( +id +è!ðnode->row_¡©e. + `’d +()) { + +154 autØ +§ + : +node +-> +·»Á +-> +chžd»n +) { + +155 ià( +§ + !ð +node + && sa-> +¡©e + =ð +S‹ +:: +O³Ãd +) { + +156  +Commªd +:: +PRE_OTHER +; + +159  +cmd +; + +163  +Commªd +:: +PRE +; + +165 : + `as£¹ +( +çl£ +);}}; + +166 +´”eq +[( +Lev– +:: +SubA¼ay +)][( +Commªd +:: +WR +)] =…»»q[(Lev–::SubA¼ay)][(Commªd:: +RD +)]; + +167 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +REF +)] = [] ( +DRAM +< +SALP +>* +node +, Commªd +cmd +,  +id +) { + +168 autØ +bªk + : +node +-> +chžd»n +) + +169 autØ +§ + : +bªk +-> +chžd»n +) { + +170 ià( +§ +-> +¡©e + =ð +S‹ +:: +Clo£d +) + +172  +Commªd +:: +PRER +; + +174  +Commªd +:: +REF +;}; + +176 ( +Ty³ +:: +MASA +): + +177 +´”eq +[( +Lev– +:: +SubA¼ay +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +SALP +>* +node +, Commªd +cmd +,  +id +) { + +178 ( +node +-> +¡©e +)){ + +179 ( +S‹ +:: +Clo£d +):  +Commªd +:: +ACT +; + +180 ( +S‹ +:: +O³Ãd +): + +181 ià( +node +-> +row_¡©e +. + `fšd +( +id +è!ðnode->row_¡©e. + `’d +()è +Commªd +:: +SASEL +; + +182  +Commªd +:: +PRE +; + +183 ( +S‹ +:: +S–eùed +): + +184 ià( +node +-> +row_¡©e +. + `fšd +( +id +è!ðnode->row_¡©e. + `’d +()è +cmd +; + +185  +Commªd +:: +PRE +; + +186 : + `as£¹ +( +çl£ +); + +188 +´”eq +[( +Lev– +:: +SubA¼ay +)][( +Commªd +:: +WR +)] =…»»q[(Lev–::SubA¼ay)][(Commªd:: +RD +)]; + +189 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +REF +)] = [] ( +DRAM +< +SALP +>* +node +, Commªd +cmd +,  +id +) { + +190 autØ +bªk + : +node +-> +chžd»n +) + +191 autØ +§ + : +bªk +-> +chžd»n +){ + +192 ià( +§ +-> +¡©e + =ð +S‹ +:: +Clo£d +) + +194  +Commªd +:: +PRER +; + +196  +Commªd +:: +REF +;}; + +198 : + `as£¹ +( +çl£ +); + +201 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PDE +)] = [] ( +DRAM +< +SALP +>* +node +, Commªd +cmd +,  +id +) { + +202 ( +node +-> +¡©e +)) { + +203 ( +S‹ +:: +Pow”Up +):  +Commªd +:: +PDE +; + +204 ( +S‹ +:: +AùPow”Down +):  +Commªd +:: +PDE +; + +205 ( +S‹ +:: +P»Pow”Down +):  +Commªd +:: +PDE +; + +206 ( +S‹ +:: +S–fReäesh +):  +Commªd +:: +SRX +; + +207 : + `as£¹ +( +çl£ +); + +211 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +SRE +)] = [] ( +DRAM +< +SALP +>* +node +, Commªd +cmd +,  +id +) { + +212 ( +node +-> +¡©e +)) { + +213 ( +S‹ +:: +Pow”Up +):  +Commªd +:: +SRE +; + +214 ( +S‹ +:: +AùPow”Down +):  +Commªd +:: +PDX +; + +215 ( +S‹ +:: +P»Pow”Down +):  +Commªd +:: +PDX +; + +216 ( +S‹ +:: +S–fReäesh +):  +Commªd +:: +SRE +; + +217 : + `as£¹ +( +çl£ +); + +219 + } +} + +222  + gSALP +:: + $š™_rowh™ +() + +224 ( +ty³ +)) { + +225 ( +Ty³ +:: +SALP_1 +): + +227 +rowh™ +[( +Lev– +:: +SubA¼ay +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +SALP +>* +node +, Commªd +cmd +,  +id +) { + +228 ( +node +-> +¡©e +)) { + +229 ( +S‹ +:: +Clo£d +):  +çl£ +; + +230 ( +S‹ +:: +O³Ãd +): + +231 ià( +node +-> +row_¡©e +. + `fšd +( +id +è!ðnode->row_¡©e. + `’d +()è +Œue +; + +232  +çl£ +; + +233 : + `as£¹ +( +çl£ +); + +237 +rowh™ +[( +Lev– +:: +SubA¼ay +)][( +Commªd +:: +WR +)] =„owh™[(Lev–::SubA¼ay)][(Commªd:: +RD +)]; + +239 ( +Ty³ +:: +SALP_2 +): + +241 +rowh™ +[( +Lev– +:: +SubA¼ay +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +SALP +>* +node +, Commªd +cmd +,  +id +) { + +242 ( +node +-> +¡©e +)){ + +243 ( +S‹ +:: +Clo£d +):  +çl£ +; + +244 ( +S‹ +:: +O³Ãd +): + +245 ià( +node +-> +row_¡©e +. + `fšd +( +id +è!ðnode->row_¡©e. + `’d +()è +Œue +; + +246  +çl£ +; + +247 : + `as£¹ +( +çl£ +); + +250 +rowh™ +[( +Lev– +:: +SubA¼ay +)][( +Commªd +:: +WR +)] =„owh™[(Lev–::SubA¼ay)][(Commªd:: +RD +)]; + +252 ( +Ty³ +:: +MASA +): + +254 +rowh™ +[( +Lev– +:: +SubA¼ay +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +SALP +>* +node +, Commªd +cmd +,  +id +) { + +255 ( +node +-> +¡©e +)){ + +256 ( +S‹ +:: +Clo£d +):  +çl£ +; + +257 ( +S‹ +:: +O³Ãd +): + +259 ià( +node +-> +row_¡©e +. + `fšd +( +id +è!ðnode->row_¡©e. + `’d +()è +Œue +; + +260  +çl£ +; + +261 ( +S‹ +:: +S–eùed +): + +262 ià( +node +-> +row_¡©e +. + `fšd +( +id +è!ðnode->row_¡©e. + `’d +()è +Œue +; + +263  +çl£ +; + +264 : + `as£¹ +( +çl£ +); + +267 +rowh™ +[( +Lev– +:: +SubA¼ay +)][( +Commªd +:: +WR +)] =„owh™[(Lev–::SubA¼ay)][(Commªd:: +RD +)]; + +269 : + `as£¹ +( +çl£ +); + +271 + } +} + +273  + gSALP +:: + $š™_rowÝ’ +() + +275 ( +ty³ +)) { + +276 ( +Ty³ +:: +SALP_1 +): + +278 +rowÝ’ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +SALP +>* +node +, Commªd +cmd +,  +id +) { + +279 ( +node +-> +¡©e +)){ + +280 ( +S‹ +:: +Clo£d +):  +çl£ +; + +281 ( +S‹ +:: +O³Ãd +):  +Œue +; + +282 : + `as£¹ +( +çl£ +); + +285 +rowÝ’ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] =„owÝ’[(Lev–::Bªk)][(Commªd:: +RD +)]; + +287 ( +Ty³ +:: +SALP_2 +): + +289 +rowÝ’ +[( +Lev– +:: +SubA¼ay +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +SALP +>* +node +, Commªd +cmd +,  +id +) { + +290 ( +node +-> +¡©e +)){ + +291 ( +S‹ +:: +Clo£d +):  +çl£ +; + +292 ( +S‹ +:: +O³Ãd +):  +Œue +; + +293 : + `as£¹ +( +çl£ +); + +296 +rowÝ’ +[( +Lev– +:: +SubA¼ay +)][( +Commªd +:: +WR +)] =„owÝ’[(Lev–::SubA¼ay)][(Commªd:: +RD +)]; + +298 ( +Ty³ +:: +MASA +): + +300 +rowÝ’ +[( +Lev– +:: +SubA¼ay +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +SALP +>* +node +, Commªd +cmd +,  +id +) { + +301 ( +node +-> +¡©e +)){ + +302 ( +S‹ +:: +Clo£d +):  +çl£ +; + +303 ( +S‹ +:: +O³Ãd +):  +Œue +; + +304 ( +S‹ +:: +S–eùed +):  +Œue +; + +305 : + `as£¹ +( +çl£ +); + +308 +rowÝ’ +[( +Lev– +:: +SubA¼ay +)][( +Commªd +:: +WR +)] =„owÝ’[(Lev–::SubA¼ay)][(Commªd:: +RD +)]; + +310 : + `as£¹ +( +çl£ +); + +312 + } +} + +314  + gSALP +:: + $š™_Ïmbda +() + +316 ( +ty³ +)){ + +317 ( +Ty³ +:: +SALP_1 +): + +318 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +ACT +)] = [] ( +DRAM +< +SALP +>* +node +,  +id +) { + +319 +node +-> +¡©e + = +S‹ +:: +O³Ãd +; + +321 +Ïmbda +[( +Lev– +:: +SubA¼ay +)][( +Commªd +:: +ACT +)] = [] ( +DRAM +< +SALP +>* +node +,  +id +) { + +322 +node +-> +¡©e + = +S‹ +:: +O³Ãd +; + +323 +node +-> +row_¡©e +[ +id +] = +S‹ +:: +O³Ãd +; + +325 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +PRE +)] = [] ( +DRAM +< +SALP +>* +node +,  +id +) { + +326 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +330 +node +-> +chžd»n +[ +id +]-> +¡©e + = +S‹ +:: +Clo£d +; + +331 +node +-> +chžd»n +[ +id +]-> +row_¡©e +. + `þ—r +(); + +333 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +PRE_OTHER +)] =†ambda[(Lev–::Bªk)][(Commªd:: +PRE +)]; + +334 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PRER +)] = [] ( +DRAM +< +SALP +>* +node +,  +id +) { + +335 autØ +bªk + : +node +-> +chžd»n +) { + +336 +bªk +-> +¡©e + = +S‹ +:: +Clo£d +; + +337 autØ +§ + : +bªk +-> +chžd»n +){ + +338 +§ +-> +¡©e + = +S‹ +:: +Clo£d +; + +339 +§ +-> +row_¡©e +. + `þ—r +();}}}; + +340 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RDA +)] = [] ( +DRAM +< +SALP +>* +node +,  +id +) { + +341 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +342 +node +-> +chžd»n +[ +id +]-> +¡©e + = +S‹ +:: +Clo£d +; + +343 +node +-> +chžd»n +[ +id +]-> +row_¡©e +. + `þ—r +();}; + +344 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WRA +)] =†ambda[(Lev–::Bªk)][(Commªd:: +RDA +)]; + +345 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PDE +)] = [] ( +DRAM +< +SALP +>* +node +,  +id +) { + +346 autØ +bªk + : +node +-> +chžd»n +) { + +347 ià( +bªk +-> +¡©e + =ð +S‹ +:: +Clo£d +) + +349 +node +-> +¡©e + = +S‹ +:: +AùPow”Down +; + +352 +node +-> +¡©e + = +S‹ +:: +P»Pow”Down +;}; + +354 ( +Ty³ +:: +SALP_2 +): + +355 +Ïmbda +[( +Lev– +:: +SubA¼ay +)][( +Commªd +:: +ACT +)] = [] ( +DRAM +< +SALP +>* +node +,  +id +) { + +356 +node +-> +¡©e + = +S‹ +:: +O³Ãd +; + +357 +node +-> +row_¡©e +[ +id +] = +S‹ +:: +O³Ãd +;}; + +358 +Ïmbda +[( +Lev– +:: +SubA¼ay +)][( +Commªd +:: +PRE +)] = [] ( +DRAM +< +SALP +>* +node +,  +id +) { + +359 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +360 +node +-> +row_¡©e +. + `þ—r +();}; + +361 +Ïmbda +[( +Lev– +:: +SubA¼ay +)][( +Commªd +:: +PRE_OTHER +)] =†ambda[(Lev–::SubA¼ay)][(Commªd:: +PRE +)]; + +362 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PRER +)] = [] ( +DRAM +< +SALP +>* +node +,  +id +) { + +363 autØ +bªk + : +node +-> +chžd»n +) + +364 autØ +§ + : +bªk +-> +chžd»n +) { + +365 +§ +-> +¡©e + = +S‹ +:: +Clo£d +; + +366 +§ +-> +row_¡©e +. + `þ—r +();}}; + +367 +Ïmbda +[( +Lev– +:: +SubA¼ay +)][( +Commªd +:: +RDA +)] = [] ( +DRAM +< +SALP +>* +node +,  +id +) { + +368 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +369 +node +-> +row_¡©e +. + `þ—r +();}; + +370 +Ïmbda +[( +Lev– +:: +SubA¼ay +)][( +Commªd +:: +WRA +)] = [] ( +DRAM +< +SALP +>* +node +,  +id +) { + +371 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +372 +node +-> +row_¡©e +. + `þ—r +();}; + +373 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PDE +)] = [] ( +DRAM +< +SALP +>* +node +,  +id +) { + +374 autØ +bªk + : +node +-> +chžd»n +) + +375 autØ +§ + : +bªk +-> +chžd»n +) { + +376 ià( +§ +-> +¡©e + =ð +S‹ +:: +Clo£d +) + +378 +node +-> +¡©e + = +S‹ +:: +AùPow”Down +; + +381 +node +-> +¡©e + = +S‹ +:: +P»Pow”Down +;}; + +383 ( +Ty³ +:: +MASA +): + +384 +Ïmbda +[( +Lev– +:: +SubA¼ay +)][( +Commªd +:: +ACT +)] = [] ( +DRAM +< +SALP +>* +node +,  +id +) { + +385 +node +-> +¡©e + = +S‹ +:: +S–eùed +; + +386 +node +-> +row_¡©e +[ +id +] = +S‹ +:: +O³Ãd +; + +387 autØ +§ + : +node +-> +·»Á +-> +chžd»n +) + +388 ià( +§ + !ð +node + && sa-> +¡©e + =ð +S‹ +:: +S–eùed +) { + +389 +§ +-> +¡©e + = +S‹ +:: +O³Ãd +; + +391 +Ïmbda +[( +Lev– +:: +SubA¼ay +)][( +Commªd +:: +SASEL +)] = [] ( +DRAM +< +SALP +>* +node +,  +id +) { + +392 +node +-> +¡©e + = +S‹ +:: +S–eùed +; + +393 autØ +§ + : +node +-> +·»Á +-> +chžd»n +) + +394 ià( +§ + !ð +node + && sa-> +¡©e + =ð +S‹ +:: +S–eùed +) { + +395 +§ +-> +¡©e + = +S‹ +:: +O³Ãd +; + +397 +Ïmbda +[( +Lev– +:: +SubA¼ay +)][( +Commªd +:: +PRE +)] = [] ( +DRAM +< +SALP +>* +node +,  +id +) { + +398 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +399 +node +-> +row_¡©e +. + `þ—r +();}; + +401 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PRER +)] = [] ( +DRAM +< +SALP +>* +node +,  +id +) { + +402 autØ +bªk + : +node +-> +chžd»n +) + +403 autØ +§ + : +bªk +-> +chžd»n +) { + +404 +§ +-> +¡©e + = +S‹ +:: +Clo£d +; + +405 +§ +-> +row_¡©e +. + `þ—r +();}}; + +406 +Ïmbda +[( +Lev– +:: +SubA¼ay +)][( +Commªd +:: +RDA +)] = [] ( +DRAM +< +SALP +>* +node +,  +id +) { + +407 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +408 +node +-> +row_¡©e +. + `þ—r +();}; + +409 +Ïmbda +[( +Lev– +:: +SubA¼ay +)][( +Commªd +:: +WRA +)] = [] ( +DRAM +< +SALP +>* +node +,  +id +) { + +410 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +411 +node +-> +row_¡©e +. + `þ—r +();}; + +412 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PDE +)] = [] ( +DRAM +< +SALP +>* +node +,  +id +) { + +413 autØ +bªk + : +node +-> +chžd»n +) + +414 autØ +§ + : +bªk +-> +chžd»n +) { + +415 ià( +§ +-> +¡©e + =ð +S‹ +:: +Clo£d +) + +417 +node +-> +¡©e + = +S‹ +:: +AùPow”Down +; + +420 +node +-> +¡©e + = +S‹ +:: +P»Pow”Down +;}; + +422 : + `as£¹ +( +çl£ +); + +424 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PDX +)] = [] ( +DRAM +< +SALP +>* +node +,  +id +) { + +425 +node +-> +¡©e + = +S‹ +:: +Pow”Up +;}; + +426 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +SRE +)] = [] ( +DRAM +< +SALP +>* +node +,  +id +) { + +427 +node +-> +¡©e + = +S‹ +:: +S–fReäesh +;}; + +428 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +SRX +)] = [] ( +DRAM +< +SALP +>* +node +,  +id +) { + +429 +node +-> +¡©e + = +S‹ +:: +Pow”Up +;}; + +430 + } +} + +432  + gSALP +:: + $š™_timšg +() + +434 +S³edEÁry +& +s + = +¥“d_’Œy +; + +435 +veùÜ +< +TimšgEÁry +> * +t +; + +438 +t + = +timšg +[( +Lev– +:: +ChªÃl +)]; + +441 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nBL +}); + +442 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nBL +}); + +443 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nBL +}); + +444 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd::RDA, 1, +s +. +nBL +}); + +445 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd::WR, 1, +s +. +nBL +}); + +446 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nBL +}); + +447 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nBL +}); + +448 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd::WRA, 1, +s +. +nBL +}); + +452 +t + = +timšg +[( +Lev– +:: +Rªk +)]; + +455 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nCCD +}); + +456 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCCD +}); + +457 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCCD +}); + +458 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd::RDA, 1, +s +. +nCCD +}); + +459 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd::WR, 1, +s +. +nCCD +}); + +460 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCCD +}); + +461 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCCD +}); + +462 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd::WRA, 1, +s +. +nCCD +}); + +463 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nCCD + + 2 - s. +nCWL +}); + +464 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCL + + s. +nCCD + + 2 - s. +nCWL +}); + +465 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nCCD + + 2 - s. +nCWL +}); + +466 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCL + + s. +nCCD + + 2 - s. +nCWL +}); + +467 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTR +}); + +468 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTR +}); + +469 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTR +}); + +470 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTR +}); + +473 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +474 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +475 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +476 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd::RDA, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +477 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +478 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +479 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +480 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +481 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nBL + + s. +nRTRS + - s. +nCWL +, +Œue +}); + +482 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCL + + s. +nBL + + s. +nRTRS + - s. +nCWL +, +Œue +}); + +483 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nBL + + s. +nRTRS + - s. +nCWL +, +Œue +}); + +484 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCL + + s. +nBL + + s. +nRTRS + - s. +nCWL +, +Œue +}); + +485 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nRTRS + - s. +nCL +, +Œue +}); + +486 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nRTRS + - s. +nCL +, +Œue +}); + +487 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nRTRS + - s. +nCL +, +Œue +}); + +488 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nRTRS + - s. +nCL +, +Œue +}); + +491 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PRER +, 1, +s +. +nRTP +}); + +492 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PRER +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +}); + +497 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nCL + + s. +nBL + + 1}); + +498 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nCL + + s. +nBL + + 1}); + +499 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +}); + +500 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR + + 1}); + +501 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nXP +}); + +502 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nXP +}); + +503 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nXP +}); + +504 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nXP +}); + +509 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 1, +s +. +nRRD +}); + +510 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 4, +s +. +nFAW +}); + +512 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PRER +, 1, +s +. +nRAS +}); + +513 +t +[( +Commªd +:: +PRER +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRP +}); + +516 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nRP +}); + +517 +t +[( +Commªd +:: +PRER +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nRP +}); + +518 +t +[( +Commªd +:: +PRE_OTHER +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nRP +}); + +519 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRFC +}); + +522 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PDE +, 1, 1}); + +523 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nXP +}); + +524 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nXP +}); + +525 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PRER +, 1, +s +. +nXP +}); + +528 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nRP +}); + +529 +t +[( +Commªd +:: +PRER +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nRP +}); + +530 +t +[( +Commªd +:: +PRE_OTHER +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nRP +}); + +531 +t +[( +Commªd +:: +SRX +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nXS +}); + +534 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd::REF, 1, +s +. +nRFC +}); + +537 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd:: +PDE +, 1, 1}); + +538 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nXP +}); + +541 +t +[( +Commªd +:: +SRX +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nXS +}); + +544 +t +[( +Commªd +:: +PDE +)]. + `push_back +({Commªd:: +PDX +, 1, +s +. +nPD +}); + +545 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nXP +}); + +548 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nXP +}); + +549 +t +[( +Commªd +:: +SRX +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nXS +}); + +552 +t +[( +Commªd +:: +SRE +)]. + `push_back +({Commªd:: +SRX +, 1, +s +. +nCKESR +}); + +553 +t +[( +Commªd +:: +SRX +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nXS +}); + +557 +t + = +timšg +[( +Lev– +:: +Bªk +)]; + +559 ( +ty³ +)) { + +560 ( +Ty³ +:: +SALP_1 +): + +564 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nRAS +}); + +565 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nRTP +}); + +566 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +,}); + +567 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PRE_OTHER +, 1, +s +. +nRAS +}); + +568 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PRE_OTHER +, 1, +s +. +nRTP +}); + +569 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PRE_OTHER +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +,}); + +570 ( +Ty³ +:: +SALP_2 +): + +571 ( +Ty³ +:: +MASA +): + +573 : + `as£¹ +( +çl£ +); + +577 +t + = +timšg +[( +Lev– +:: +SubA¼ay +)]; + +580 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nRCD +}); + +581 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nRCD +}); + +582 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nRCD +}); + +583 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nRCD +}); + +585 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nRTP +}); + +586 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +}); + +588 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRTP + + s. +nRP +}); + +589 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR + + s. +nRP +}); + +592 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 1, +s +. +nRC +}); + +593 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nRAS +}); + +594 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRP +}); + +596 ( +ty³ +)) { + +597 ( +Ty³ +:: +SALP_1 +): + +598 ( +Ty³ +:: +SALP_2 +): + +600 ( +Ty³ +:: +MASA +): + +601 +t +[( +Commªd +:: +SASEL +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nSCD +}); + +602 +t +[( +Commªd +:: +SASEL +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nSCD +}); + +603 +t +[( +Commªd +:: +SASEL +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nSCD +}); + +604 +t +[( +Commªd +:: +SASEL +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nSCD +}); + +606 : + `as£¹ +( +çl£ +); + +610 ( +ty³ +)) { + +611 ( +Ty³ +:: +SALP_1 +): + +612 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nPA +, +Œue +}); + +613 +t +[( +Commªd +:: +PRE_OTHER +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nPA +, +Œue +}); + +615 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 1, +s +. +nRC + - s. +nRP + + s. +nPA +, +Œue +}); + +616 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRTP + + s. +nPA +, +Œue +}); + +617 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR + + s. +nPA +, +Œue +}); + +620 ( +Ty³ +:: +SALP_2 +): + +621 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 1, +s +. +nRCD + + s. +nRA +, +Œue +}); + +622 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRA +, +Œue +}); + +623 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRA +, +Œue +}); + +624 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nWA +, +Œue +}); + +625 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nWA +, +Œue +}); + +627 ( +Ty³ +:: +MASA +): + +628 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRA +, +Œue +}); + +629 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRA +, +Œue +}); + +630 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nWA +, +Œue +}); + +631 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nWA +, +Œue +}); + +633 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +SASEL +, 1, +s +. +nRA +, +Œue +}); + +634 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +SASEL +, 1, +s +. +nRA +, +Œue +}); + +635 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +SASEL +, 1, +s +. +nWA +, +Œue +}); + +636 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +SASEL +, 1, +s +. +nWA +, +Œue +}); + +638 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nRA +, +Œue +}); + +639 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd::RDA, 1, +s +. +nRA +, +Œue +}); + +640 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd::WR, 1, +s +. +nWA +, +Œue +}); + +641 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd::WRA, 1, +s +. +nWA +, +Œue +}); + +643 : + `as£¹ +( +çl£ +); + +646 + } +} + + @SALP.h + +1 #iâdeà +__SALP_H + + +2  + #__SALP_H + + + ) + +4  + ~"DRAM.h +" + +5  + ~"Reque¡.h +" + +6  + ~ + +7  + ~ + +9 +usšg + +Çme¥aû + + g¡d +; + +11 +Çme¥aû + + g¿muÏtÜ + + +14 þas  + cSALP + + +16 + gpublic +: + +17 +¡ršg + +¡ªd¬d_Çme +; + +18 +þass + + gOrg +; + +19 +þass + + gS³ed +; + +20 +þass + + gTy³ +; + +21 +SALP +( +Org + +Üg +, +S³ed + +¥“d +, +Ty³ + +ty³ + = Ty³:: +MASA +,  +n_§ + = 8); + +22 +SALP +(cÚ¡ +¡ršg +& +Üg_¡r +, cÚ¡ sŒšg& +¥“d_¡r +, cÚ¡ sŒšg& +ty³_¡r + = "SALP-MASA",  +n_§ + = 8); + +24  + gm­ +< + g¡ršg +, + gOrg +> + gÜg_m­ +; + +25  + gm­ +< + g¡ršg +, + gS³ed +> + g¥“d_m­ +; + +26  + gm­ +< + g¡ršg +, + gTy³ +> + gty³_m­ +; + +28 þas  + cTy³ + :  + +30 +SALP_1 +, + gSALP_2 +, + gMASA +, + gMAX + + +31 } + gty³ +; + +33 þas  + cLev– + :  + +35 +ChªÃl +, + gRªk +, + gBªk +, + gSubA¼ay +, + gRow +, + gCÞumn +, + gMAX + + +39 þas  + cCommªd + :  + +41 +ACT +, + gSASEL +, + gPRE +, + gPRER +, + +42 + gRD +, + gWR +, + gRDA +, + gWRA +, + +43 + gREF +, + gPDE +, + gPDX +, + gSRE +, + gSRX +, + +44 + gPRE_OTHER +, + +45 + gMAX + + +48 +¡ršg + + gcommªd_Çme +[( +Commªd +:: +MAX +)] = { + +55 +Lev– + + gscÝe +[( +Commªd +:: +MAX +)] = { + +56 +Lev– +:: +Row +, Lev–:: +SubA¼ay +, Lev–::SubA¼ay, Lev–:: +Rªk +, + +57 +Lev– +:: +CÞumn +, Level::Column, Level::Column, Level::Column, + +58 +Lev– +:: +Rªk +, Lev–::Rªk, Lev–::Rªk, Lev–::Rªk, Lev–::Rªk, Lev–:: +SubA¼ay + + +61 +boÞ + +is_Ý’šg +( +Commªd + +cmd +) + +63 ( + gcmd +)) { + +64 ( + gCommªd +:: +ACT +): + +65  +Œue +; + +67  +çl£ +; + +71 +boÞ + +is_acûssšg +( +Commªd + +cmd +) + +73 ( + gcmd +)) { + +74 ( + gCommªd +:: +RD +): + +75 ( +Commªd +:: +WR +): + +76 ( +Commªd +:: +RDA +): + +77 ( +Commªd +:: +WRA +): + +78  +Œue +; + +80  +çl£ +; + +84 +boÞ + +is_þosšg +( +Commªd + +cmd +) + +86 ( + gcmd +)) { + +87 ( + gCommªd +:: +RDA +): + +88 ( +Commªd +:: +WRA +): + +89 ( +Commªd +:: +PRE +): + +90 ( +Commªd +:: +PRER +): + +91 ( +Commªd +:: +PRE_OTHER +): + +92  +Œue +; + +94  +çl£ +; + +98 +boÞ + +is_»äeshšg +( +Commªd + +cmd +) + +100 ( + gcmd +)) { + +101 ( + gCommªd +:: +REF +): + +102  +Œue +; + +104  +çl£ +; + +110 þas  + cS‹ + :  + +112 +O³Ãd +, + gClo£d +, + gS–eùed +, + gPow”Up +, + gAùPow”Down +, + gP»Pow”Down +, + gS–fReäesh +, + gMAX + + +113 } + g¡¬t +[( +Lev– +:: +MAX +)] = { + +114 +S‹ +:: +MAX +, S‹:: +Pow”Up +, S‹:: +Clo£d +, State::Closed, State::Closed, State::MAX + +118 +Commªd + + gŒª¦©e +[( +Reque¡ +:: +Ty³ +:: +MAX +)] = { + +119 +Commªd +:: +RD +, Commªd:: +WR +, + +120 +Commªd +:: +REF +, Commªd:: +PDE +, Commªd:: +SRE + + +124 + gfunùiÚ +< +Commªd +( +DRAM +< +SALP +>*, Commªd +cmd +, )> + g´”eq +[( +Lev– +:: +MAX +)][(Command::MAX)]; + +128 + gfunùiÚ +< +boÞ +( +DRAM +< +SALP +>*, +Commªd + +cmd +, )> + growh™ +[( +Lev– +:: +MAX +)][(Command::MAX)]; + +129 + gfunùiÚ +< +boÞ +( +DRAM +< +SALP +>*, +Commªd + +cmd +, )> + growÝ’ +[( +Lev– +:: +MAX +)][(Command::MAX)]; + +132  + sTimšgEÁry + + +134 +Commªd + + gcmd +; + +135  + gdi¡ +; + +136  + gv® +; + +137 +boÞ + + gsiblšg +; + +139 + gveùÜ +< + gTimšgEÁry +> + gtimšg +[( +Lev– +:: +MAX +)][( +Commªd +::MAX)]; + +142 + gfunùiÚ +<( + gDRAM +< + gSALP +>*, )> + gÏmbda +[( +Lev– +:: +MAX +)][( +Commªd +::MAX)]; + +145 þas  + cOrg + :  + +147 +SALP_512Mb_x4 +, + gSALP_512Mb_x8 +, + gSALP_512Mb_x16 +, + +148 + gSALP_1Gb_x4 +, + gSALP_1Gb_x8 +, + gSALP_1Gb_x16 +, + +149 + gSALP_2Gb_x4 +, + gSALP_2Gb_x8 +, + gSALP_2Gb_x16 +, + +150 + gSALP_4Gb_x4 +, + gSALP_4Gb_x8 +, + gSALP_4Gb_x16 +, + +151 + gSALP_8Gb_x4 +, + gSALP_8Gb_x8 +, + gSALP_8Gb_x16 +, + +152 + gMAX + + +155  + gn_§ +; + +157  + sOrgEÁry + { + +158  + gsize +; + +159  + gdq +; + +160  + gcouÁ +[( +Lev– +:: +MAX +)]; + +161 } + gÜg_bË +[( +Org +:: +MAX +)] = { + +167 }, + gÜg_’Œy +; + +169  +£t_chªÃl_numb” +( +chªÃl +); + +170  +£t_¿nk_numb” +( +¿nk +); + +173 þas  + cS³ed + :  + +175 +SALP_800D +, + gSALP_800E +, + +176 + gSALP_1066E +, + gSALP_1066F +, + gSALP_1066G +, + +177 + gSALP_1333G +, + gSALP_1333H +, + +178 + gSALP_1600H +, + gSALP_1600J +, + gSALP_1600K +, + +179 + gSALP_1866K +, + gSALP_1866L +, + +180 + gSALP_2133L +, + gSALP_2133M +, + +181 + gMAX + + +184  + g´eãtch_size + = 8; + +185  + gchªÃl_width + = 64; + +187  + sS³edEÁry + { + +188  + g¿‹ +; + +189  + gäeq +, + gtCK +; + +190  + gnBL +, + gnCCD +, + gnRTRS +; + +191  + gnCL +, + gnRCD +, + gnRP +, + gnPA +, + gnCWL +; + +192  + gnRAS +, + gnRC +; + +193  + gnRTP +, + gnWTR +, + gnWR +, + gnRA +, + gnWA +; + +194  + gnRRD +, + gnFAW +; + +195  + gnRFC +, + gnREFI +; + +196  + gnPD +, + gnXP +, + gnXPDLL +; + +197  + gnCKESR +, + gnXS +, + gnXSDLL +; + +198  + gnSCD +; + +199 } + g¥“d_bË +[( +S³ed +:: +MAX +)] = { + +214 }, + g¥“d_’Œy +; + +216  + g»ad_Ï‹ncy +; + +218 + g´iv©e +: + +219  +š™_¥“d +(); + +220  +š™_Ïmbda +(); + +221  +š™_´”eq +(); + +222  +š™_rowh™ +(); + +223  +š™_rowÝ’ +(); + +224  +š™_timšg +(); + + @Scheduler.h + +1 #iâdeà +__SCHEDULER_H + + +2  + #__SCHEDULER_H + + + ) + +4  + ~"DRAM.h +" + +5  + ~"Reque¡.h +" + +6  + ~"CÚŒÞËr.h +" + +7  + ~ + +8  + ~ + +9  + ~ + +10  + ~ + +11  + ~<ÿs£¹ +> + +13 +usšg + +Çme¥aû + + g¡d +; + +15 +Çme¥aû + + g¿muÏtÜ + + +18 + g‹m¶©e + < +ty³Çme + + gT +> + +19 +þass + + gCÚŒÞËr +; + +21 + g‹m¶©e + < +ty³Çme + + gT +> + +22 þas  + cScheduËr + + +24 + gpublic +: + +25 +CÚŒÞËr +< +T +>* +ù¾ +; + +27 þas  + cTy³ + { + +28 + gFCFS +, + gFRFCFS +, + gFRFCFS_C­ +, + gFRFCFS_PriÜH™ +, + gMAX + + +29 } + gty³ + = +Ty³ +:: +FRFCFS_PriÜH™ +; + +31  + gÿp + = 16; + +33 +ScheduËr +( +CÚŒÞËr +< +T +>* +ù¾ +) : ctrl(ctrl) {} + +35 +li¡ +< +Reque¡ +>:: +™”©Ü + +g‘_h—d +Öi¡& +q +) + +38 ià( +ty³ + !ð +Ty³ +:: +FRFCFS_PriÜH™ +) { + +39 ià(! +q +. +size +()) + +40  +q +. +’d +(); + +42 autØ + gh—d + = +q +. +begš +(); + +43 autØ + g™r + = +Ãxt +( +q +. +begš +(), 1); iŒ !ðq. +’d +(); itr++) + +44 + gh—d + = +com·» +[( +ty³ +)]( +h—d +, + g™r +); + +46  + gh—d +; + +48 ià(! + gq +. +size +()) + +49  + gq +. +’d +(); + +51 autØ + gh—d + = +q +. +begš +(); + +52 autØ + g™r + = +Ãxt +( +q +. +begš +(), 1); iŒ !ðq. +’d +(); itr++) { + +53 + gh—d + = +com·» +[( +Ty³ +:: +FRFCFS_PriÜH™ +)]( +h—d +, + g™r +); + +56 ià( + gthis +-> + gù¾ +-> +is_»ady +( +h—d +è&&his->ù¾-> +is_row_h™ +(head)) { + +57  + gh—d +; + +61 + gveùÜ +> + gh™_»qs +; + +62 autØ + g™r + = +q +. +begš +(è; iŒ !ðq. +’d +() ; ++itr) { + +63 ià( + gthis +-> + gù¾ +-> +is_row_h™ +( +™r +)) { + +64 autØ + gbegš + = +™r +-> +addr_vec +. +begš +(); + +67 autØ + g’d + = +begš + + ( +ù¾ +-> +chªÃl +-> +¥ec +-> +scÝe +[( +T +:: +Commªd +:: +PRE +)]) + 1; + +68 + gveùÜ +<> +rowgroup +( +begš +, +’d +); + +69 + gh™_»qs +. +push_back +( +rowgroup +); + +74 + gh—d + = +q +. +’d +(); + +75 autØ + g™r + = +q +. +begš +(); iŒ !ðq. +’d +(); itr++) { + +76 +boÞ + + gviÞ©e_h™ + = +çl£ +; + +77 ià((! + gthis +-> + gù¾ +-> +is_row_h™ +( +™r +)è&&his->ù¾-> +is_row_Ý’ +(itr)) { + +79 autØ + gbegš + = +™r +-> +addr_vec +. +begš +(); + +82 autØ + g’d + = +begš + + ( +ù¾ +-> +chªÃl +-> +¥ec +-> +scÝe +[( +T +:: +Commªd +:: +PRE +)]) + 1; + +83 + gveùÜ +<> +rowgroup +( +begš +, +’d +); + +84 cÚ¡‡uto& + gh™_»q_rowgroup + : +h™_»qs +) { + +85 ià( +rowgroup + =ð +h™_»q_rowgroup +) { + +86 +viÞ©e_h™ + = +Œue +; + +91 ià( + gviÞ©e_h™ +) { + +95 ià( + gh—d + =ð +q +. +’d +()) { + +96 +h—d + = +™r +; + +98 + gh—d + = +com·» +[( +Ty³ +:: +FRFCFS +)]( +h—d +, + g™r +); + +102  + gh—d +; + +106 + g´iv©e +: + +107  +li¡ +< + tReque¡ +>:: + t™”©Ü + + tReqI‹r +; + +108 + gfunùiÚ +< +ReqI‹r +(ReqI‹r, ReqI‹r)> + gcom·» +[( +Ty³ +:: +MAX +)] = { + +110 [ +this +] ( +ReqI‹r + +»q1 +, ReqI‹¸ +»q2 +) { + +111 ià( +»q1 +-> +¬rive + <ð +»q2 +->arrive) „eq1; + +112  + g»q2 +;}, + +115 [ +this +] ( +ReqI‹r + + g»q1 +, ReqI‹¸ + g»q2 +) { + +116 +boÞ + + g»ady1 + = +this +-> +ù¾ +-> +is_»ady +( +»q1 +); + +117 +boÞ + + g»ady2 + = +this +-> +ù¾ +-> +is_»ady +( +»q2 +); + +119 ià( + g»ady1 + ^ + g»ady2 +) { + +120 ià( + g»ady1 +è + g»q1 +; + +121  + g»q2 +; + +124 ià( + g»q1 +-> + g¬rive + <ð +»q2 +-> +¬rive +è +»q1 +; + +125  + g»q2 +;}, + +128 [ +this +] ( +ReqI‹r + + g»q1 +, ReqI‹¸ + g»q2 +) { + +129 +boÞ + + g»ady1 + = +this +-> +ù¾ +-> +is_»ady +( +»q1 +); + +130 +boÞ + + g»ady2 + = +this +-> +ù¾ +-> +is_»ady +( +»q2 +); + +132 + g»ady1 + = +»ady1 + && ( +this +-> +ù¾ +-> +rowbË +-> +g‘_h™s +( +»q1 +-> +addr_vec +è<ðthis-> +ÿp +); + +133 + g»ady2 + = +»ady2 + && ( +this +-> +ù¾ +-> +rowbË +-> +g‘_h™s +( +»q2 +-> +addr_vec +è<ðthis-> +ÿp +); + +135 ià( + g»ady1 + ^ + g»ady2 +) { + +136 ià( + g»ady1 +è + g»q1 +; + +137  + g»q2 +; + +140 ià( + g»q1 +-> + g¬rive + <ð +»q2 +-> +¬rive +è +»q1 +; + +141  + g»q2 +;}, + +143 [ +this +] ( +ReqI‹r + + g»q1 +, ReqI‹¸ + g»q2 +) { + +144 +boÞ + + g»ady1 + = +this +-> +ù¾ +-> +is_»ady +( +»q1 +è&&his->ù¾-> +is_row_h™ +(req1); + +145 +boÞ + + g»ady2 + = +this +-> +ù¾ +-> +is_»ady +( +»q2 +è&&his->ù¾-> +is_row_h™ +(req2); + +147 ià( + g»ady1 + ^ + g»ady2 +) { + +148 ià( + g»ady1 +è + g»q1 +; + +149  + g»q2 +; + +152 ià( + g»q1 +-> + g¬rive + <ð +»q2 +-> +¬rive +è +»q1 +; + +153  + g»q2 +;} + +158 + g‹m¶©e + < +ty³Çme + + gT +> + +159 þas  + cRowPÞicy + + +161 + gpublic +: + +162 +CÚŒÞËr +< +T +>* +ù¾ +; + +164 þas  + cTy³ + { + +165 + gClo£d +, + gO³Ãd +, + gTimeout +, + gMAX + + +166 } + gty³ + = +Ty³ +:: +O³Ãd +; + +168  + gtimeout + = 50; + +170 +RowPÞicy +( +CÚŒÞËr +< +T +>* +ù¾ +) : ctrl(ctrl) {} + +172 +veùÜ +<> +g‘_viùim +( +ty³Çme + +T +:: +Commªd + +cmd +) + +174  +pÞicy +[( +ty³ +)]( +cmd +); + +177 + g´iv©e +: + +178 +funùiÚ +< +veùÜ +<>( +ty³Çme + +T +:: +Commªd +)> +pÞicy +[( +Ty³ +:: +MAX +)] = { + +180 [ +this +] ( +ty³Çme + +T +:: +Commªd + +cmd +è-> +veùÜ +<> { + +181 auto& +kv + : +this +-> +ù¾ +-> +rowbË +-> +bË +) { + +182 ià(! +this +-> +ù¾ +-> +is_»ady +( +cmd +, +kv +. +fœ¡ +)) + +184  + gkv +. + gfœ¡ +; + +186  + gveùÜ +<>();}, + +189 [ +this +] ( +ty³Çme + + gT +:: +Commªd + +cmd +) { + +190  +veùÜ +<>();}, + +193 [ +this +] ( +ty³Çme + + gT +:: +Commªd + +cmd +è-> +veùÜ +<> { + +194 auto& +kv + : +this +-> +ù¾ +-> +rowbË +-> +bË +) { + +195 auto& +’Œy + = +kv +. +£cÚd +; + +196 ià( + gthis +-> + gù¾ +-> + gþk + - + g’Œy +. + gtime¡amp + < + gtimeout +) + +198 ià(! + gthis +-> + gù¾ +-> +is_»ady +( +cmd +, +kv +. +fœ¡ +)) + +200  + gkv +. + gfœ¡ +; + +202  + gveùÜ +<>();} + +208 + g‹m¶©e + < +ty³Çme + + gT +> + +209 þas  + cRowTabË + + +211 + gpublic +: + +212 +CÚŒÞËr +< +T +>* +ù¾ +; + +214  + sEÁry + { + +215  + grow +; + +216  + gh™s +; + +217  + gtime¡amp +; + +220 + gm­ +< + gveùÜ +<>, + gEÁry +> + gbË +; + +222 +RowTabË +( +CÚŒÞËr +< +T +>* +ù¾ +) : ctrl(ctrl) {} + +224  +upd©e +( +ty³Çme + +T +:: +Commªd + +cmd +, cÚ¡ +veùÜ +<>& +addr_vec +,  +þk +) + +226 autØ + gbegš + = +addr_vec +. +begš +(); + +227 autØ + g’d + = +begš + + ( +T +:: +Lev– +:: +Row +); + +228 + gveùÜ +<> +rowgroup +( +begš +, +’d +); + +229  + grow + = * +’d +; + +231 +T +* + g¥ec + = +ù¾ +-> +chªÃl +-> +¥ec +; + +233 ià( + g¥ec +-> +is_Ý’šg +( +cmd +)) + +234 + gbË +. +š£¹ +({ +rowgroup +, { +row +, 0, +þk +}}); + +236 ià( + g¥ec +-> +is_acûssšg +( +cmd +)) { + +238 autØ + gm©ch + = +bË +. +fšd +( +rowgroup +); + +239 +as£¹ +( +m©ch + !ð +bË +. +’d +()); + +240 +as£¹ +( +m©ch +-> +£cÚd +. +row + ==„ow); + +241 + gm©ch +-> + g£cÚd +. + gh™s +++; + +242 + gm©ch +-> + g£cÚd +. + gtime¡amp + = +þk +; + +245 ià( + g¥ec +-> +is_þosšg +( +cmd +)) { + +247  + gn_rm + = 0; + +248  + gscÝe + = ( +¥ec +-> +scÝe +[( +cmd +)]); + +249 autØ + g™ + = +bË +. +begš +(); iˆ!ðbË. +’d +();) { + +250 ià( +equ® +( +begš +, begš + +scÝe + + 1, +™ +-> +fœ¡ +.begin())) { + +251 + gn_rm +++; + +252 + g™ + = +bË +. +”a£ +( +™ +); + +255 + g™ +++; + +257 +as£¹ +( +n_rm + > 0); + +261  +g‘_h™s +( +veùÜ +<>& +addr_vec +) + +263 autØ + gbegš + = +addr_vec +. +begš +(); + +264 autØ + g’d + = +begš + + ( +T +:: +Lev– +:: +Row +); + +266 + gveùÜ +<> +rowgroup +( +begš +, +’d +); + +267  + grow + = * +’d +; + +269 autØ + g™r + = +bË +. +fšd +( +rowgroup +); + +270 ià( + g™r + =ð +bË +. +’d +(è|| +™r +-> +£cÚd +. +row + !=„ow) + +273  + g™r +-> + g£cÚd +. + gh™s +; + + @SpeedyController.h + +1 #iâdeà +__SPEEDYCONTROLLER_H + + +2  + #__SPEEDYCONTROLLER_H + + + ) + +4  + ~"CÚfig.h +" + +5  + ~"DRAM.h +" + +6  + ~"Reque¡.h +" + +7  + ~"Sti¡ics.h +" + +8  + ~ + +9  + ~ + +10  + ~ + +11  + ~<¡ršg +> + +12  + ~<®gÜ™hm +> + +13  + ~<ÿs£¹ +> + +14  + ~ + +15  + ~ + +17 +usšg + +Çme¥aû + + g¡d +; + +19 +Çme¥aû + + g¿muÏtÜ + + +22 + g‹m¶©e + < +ty³Çme + + gT +> + +23 þas  + cS³edyCÚŒÞËr + + +27 + g´Ùeùed +: + +28 +SÿÏrSt + +row_h™s +; + +29 +SÿÏrSt + + grow_mis£s +; + +30 + g´iv©e +: + +31 þas  + ccom·œ_d•¬t_þk +{ + +32 +public +: + +33 +boÞ + +Ý”©Ü +()(cÚ¡ +Reque¡ +& +lhs +, cÚ¡ + gReque¡ +& + grhs +) { + +34  + glhs +. + gd•¬t + > + grhs +.depart; + +37 + gpublic +: + +39 +¡ršg + +cmd_Œaû_´efix + = "cmd-trace-"; + +40 + gveùÜ +< + gof¡»am +> + gcmd_Œaû_fžes +; + +41 +boÞ + + g»cÜd_cmd_Œaû + = +çl£ +; + +43 +boÞ + + g´št_cmd_Œaû + = +çl£ +; + +45 cÚ¡  + gqueue_ÿ·c™y + = 32; + +46  + gþk + = 0; + +47 + gDRAM +< + gT +>* + gchªÃl +; + +49  + gwr™e_hi + = 0.875; + +50  + gwr™e_low + = 0.5; + +53  + gtu¶e +< + tReque¡ +, + tty³Çme + + tT +:: + tCommªd +, > + t»que¡_šfo +; + +54  + gveùÜ +< + t»que¡_šfo +> + t»que¡_queue +; + +55 +»que¡_queue + + g»adq +; + +56 +»que¡_queue + + gwr™eq +; + +57 +»que¡_queue + + gÙh”q +; + +60 + g´iÜ™y_queue +< + gReque¡ +, + gveùÜ +, + gcom·œ_d•¬t_þk +> + g³ndšg +; + +62 +boÞ + + gwr™e_mode + = +çl£ +; + +63  + g»äeshed + = 0; + +66 +S³edyCÚŒÞËr +(cÚ¡ +CÚfig +& +cÚfigs +, +DRAM +< +T +>* +chªÃl +) : + +67 +chªÃl +(channel) + +69 +»cÜd_cmd_Œaû + = +cÚfigs +.record_cmd_trace(); + +70 + g´št_cmd_Œaû + = +cÚfigs +. +´št_cmd_Œaû +(); + +71 ià( + g»cÜd_cmd_Œaû +){ + +72 +¡ršg + + g´efix + = +cmd_Œaû_´efix + + "chª-" + +to_¡ršg +( +chªÃl +-> +id +) + "-rank-"; + +73 +¡ršg + + gsuffix + = ".cmdtrace"; + +74  + gi + = 0; i < + gchªÃl +-> + gchžd»n +. +size +(); i++) + +75 + gcmd_Œaû_fžes +. +em¶aû_back +( +´efix + + +to_¡ršg +( +i +è+ +suffix +); + +77 + g»adq +. +»£rve +( +queue_ÿ·c™y +); + +78 + gwr™eq +. +»£rve +( +queue_ÿ·c™y +); + +79 + gÙh”q +. +»£rve +( +queue_ÿ·c™y +); + +83 + grow_h™s + + +84 . +Çme +("row_h™s_chªÃl_"+ +to_¡ršg +( +chªÃl +-> +id +)) + +85 . +desc +("Number of„ow hits") + +86 . +´ecisiÚ +(0) + +88 + grow_mis£s + + +89 . +Çme +("row_mis£s_chªÃl_"+ +to_¡ršg +( +chªÃl +-> +id +)) + +90 . +desc +("Number of„ow misses") + +91 . +´ecisiÚ +(0) + +95 ~ +S³edyCÚŒÞËr +(){ + +96 +d–‘e + + gchªÃl +; + +97 auto& + gfže + : +cmd_Œaû_fžes +) + +98 +fže +. +þo£ +(); + +103  +fšish +( +»ad_»q +,  +wr™e_»q +,  +d¿m_cyþes +) { + +105 + gchªÃl +-> +fšish +( +d¿m_cyþes +); + +108 +boÞ + +’queue +( +Reque¡ +& +»q +) + +110 + g»que¡_queue +& + gq + = + +111 +»q +. +ty³ + =ð +Reque¡ +:: +Ty³ +:: +READ +? +»adq +: + +112 +»q +. +ty³ + =ð +Reque¡ +:: +Ty³ +:: +WRITE +? +wr™eq +: + +113 +Ùh”q +; + +114 ià( + gqueue_ÿ·c™y + =ð +q +. +size +()) + +115  +çl£ +; + +117 + g»q +. + g¬rive + = +þk +; + +118 ià( + g»q +. + gty³ + =ð +Reque¡ +:: +Ty³ +:: +READ +){ + +119 auto& +šfo + : +wr™eq +) + +120 ià( +»q +. +addr + =ð +g‘ +<0>( +šfo +).addr){ + +121 +»q +. +d•¬t + = +þk + + 1; + +122 + g³ndšg +. +push +( +»q +); + +123  + gŒue +; + +126 +ty³Çme + + gT +:: +Commªd + +fœ¡_cmd + = +g‘_fœ¡_cmd +( +»q +); + +127  + gfœ¡_þk + = +chªÃl +-> +g‘_Ãxt +( +fœ¡_cmd +, +»q +. +addr_vec +. +d©a +()); + +128 + gq +. +em¶aû_back +( +»q +, +fœ¡_cmd +, +fœ¡_þk +); + +129 +push_h—p +( +q +. +begš +(), q. +’d +(), +com·œ_fœ¡_þk +);; + +130  + gŒue +; + +133  +tick +() + +135 + gþk +++; + +138 ià( + g³ndšg +. +size +()) { + +139 +Reque¡ + + g»q + = +³ndšg +. +tÝ +(); + +140 ià( + g»q +. + gd•¬t + <ð +þk +) { + +141 +»q +. +d•¬t + = +þk +; + +142 + g»q +. +ÿÎback +( +»q +); + +143 + g³ndšg +. +pÝ +(); + +148  + g»äesh_š‹rv® + = +chªÃl +-> +¥ec +-> +¥“d_’Œy +. +nREFI +; + +149 ià( + gþk + - + g»äeshed + >ð +»äesh_š‹rv® +) { + +150 autØ +»q_ty³ + = +Reque¡ +:: +Ty³ +:: +REFRESH +; + +151 + gveùÜ +<> +addr_vec +(( +T +:: +Lev– +:: +MAX +), -1); + +152 + gaddr_vec +[0] = +chªÃl +-> +id +; + +153 autØ + gchžd + : +chªÃl +-> +chžd»n +) { + +154 +addr_vec +[1] = +chžd +-> +id +; + +155 +Reque¡ + +»q +( +addr_vec +, +»q_ty³ +, +NULL +); + +156 +boÞ + + g»s + = +’queue +( +»q +); + +157 +as£¹ +( +»s +); + +160 + g»äeshed + = +þk +; + +164 ià(! + gwr™e_mode +) { + +166 ià( + gwr™eq +. +size +(è>ð()( +wr™e_hi + * +queue_ÿ·c™y +è|| +»adq +.size() == 0) + +167 +wr™e_mode + = +Œue +; + +171 ià( + gwr™eq +. +size +(è<ð()( +wr™e_low + * +queue_ÿ·c™y +è&& +»adq +.size() != 0) + +172 +wr™e_mode + = +çl£ +; + +176 + g»que¡_queue +& + gq + = +Ùh”q +. +size +()? oth”q: +wr™e_mode + ? +wr™eq + : +»adq +; + +178 +scheduË +( +q +); + +181 +boÞ + +is_row_h™ +( +Reque¡ +& +»q +) + +183 +ty³Çme + + gT +:: +Commªd + +cmd + = +g‘_fœ¡_cmd +( +»q +); + +184  + gchªÃl +-> +check_row_h™ +( +cmd +, +»q +. +addr_vec +. +d©a +()); + +187 + g´iv©e +: + +189  +boÞ + +com·œ_fœ¡_þk +(cÚ¡ +»que¡_šfo +& +lhs +, cÚ¡„eque¡_šfo& +rhs +) { + +190  ( + gg‘ +<2>( + glhs +è> g‘<2>( + grhs +)); + +193 +ty³Çme + + gT +:: +Commªd + +g‘_fœ¡_cmd +( +Reque¡ +& +»q +) + +195 +ty³Çme + +T +:: +Commªd + +cmd + = +chªÃl +-> +¥ec +-> +Œª¦©e +[( +»q +. +ty³ +)]; + +196 ( + g»q +. + gty³ +)){ + +197 ( + gReque¡ +:: +Ty³ +:: +READ +): + +198 ( +Reque¡ +:: +Ty³ +:: +WRITE +):{ + +199 autØ +node + = +chªÃl +; + +200  + gi + = 1; i < ( + gT +:: +Lev– +:: +Row +); i++) + +201 + gnode + = +node +-> +chžd»n +[ +»q +. +addr_vec +[ +i +]]; + +202 +as£¹ +(( +node +-> +Ëv– +è=ð( +T +:: +Lev– +:: +Row +) - 1); + +203 ià( + gnode +-> + g¡©e + =ð +T +:: +S‹ +:: +Clo£d +è T:: +Commªd +:: +ACT +; + +204 ià( + gnode +-> + grow_¡©e +. +fšd +( +»q +. +addr_vec +[( +T +:: +Lev– +:: +Row +)]è!ð +node +-> +row_¡©e +. +’d +()è +cmd +; + +205  + gT +:: +Commªd +:: +PRE +; + +207 ( + gReque¡ +:: +Ty³ +:: +REFRESH +): + +208  +chªÃl +-> +decode +( +cmd +, +»q +. +addr_vec +. +d©a +()); + +210 +as£¹ +( +çl£ +); + +214  +upd©e +( +ty³Çme + +T +:: +Commªd + +cmd +, +boÞ + +¡©e_chªge +, +veùÜ +<>:: +™”©Ü +& +begš +, veùÜ<>::™”©Ü& +’d +, +»que¡_queue +& +q +){ + +215 ià( + gq +. +em±y +()) ; + +217 auto& + gšfo + : +q +) { + +218 +boÞ + +addr_eq + = +equ® +( +begš +, +’d +, +g‘ +<0>( +šfo +). +addr_vec +.begin()); + +219 ià( + g¡©e_chªge + && + gaddr_eq +) + +220 + gg‘ +<1>( + gšfo +èð +g‘_fœ¡_cmd +( +g‘ +<0>( +šfo +)); + +221 ià(( + gcmd + =ð +T +:: +Commªd +:: +RD + || +cmd + =ðT::Commªd:: +WR +) + +222 && +g‘ +<1>( +šfo +è=ð +T +:: +Commªd +:: +ACT +) + +224 + gg‘ +<2>( + gšfo +èð +chªÃl +-> +g‘_Ãxt +( +g‘ +<1>( +šfo +), g‘<0>(šfo). +addr_vec +. +d©a +()); + +226 +make_h—p +( +q +. +begš +(), q. +’d +(), +com·œ_fœ¡_þk +); + +229  +scheduË +( +»que¡_queue +& +q +){ + +230 ià( + gq +. +em±y +()) ; + +232 + gReque¡ +& + g»q + = +g‘ +<0>( +q +[0]); + +233 +ty³Çme + + gT +:: +Commªd +& +fœ¡_cmd + = +g‘ +<1>( +q +[0]); + +234  + gfœ¡_þk + = +g‘ +<2>( +q +[0]); + +236 ià( + gfœ¡_þk + > + gþk +) ; + +238 ià( + g»q +. + gis_fœ¡_commªd +) { + +239 + g»q +. + gis_fœ¡_commªd + = +çl£ +; + +240 ià( + g»q +. + gty³ + =ð +Reque¡ +:: +Ty³ +:: +READ + || +»q +. +ty³ + =ðReque¡::Ty³:: +WRITE +) { + +241 ià( +is_row_h™ +( +»q +)) + +242 ++ +row_h™s +; + +244 ++ + grow_mis£s +; + +248 +issue_cmd +( +fœ¡_cmd +, +»q +. +addr_vec +. +d©a +()); + +250 ià( + gfœ¡_cmd + =ð +chªÃl +-> +¥ec +-> +Œª¦©e +[( +»q +. +ty³ +)]){ + +251 ià( +»q +. +ty³ + =ð +Reque¡ +:: +Ty³ +:: +READ +) { + +252 +»q +. +d•¬t + = +þk + + +chªÃl +-> +¥ec +-> +»ad_Ï‹ncy +; + +253 + g³ndšg +. +push +( +»q +); + +255 +pÝ_h—p +( +q +. +begš +(), q. +’d +(), +com·œ_fœ¡_þk +); + +256 + gq +. +pÝ_back +(); + +259 +boÞ + + g¡©e_chªge + = +chªÃl +-> +¥ec +-> +is_Ý’šg +( +fœ¡_cmd +) + +260 || +chªÃl +-> +¥ec +-> +is_þosšg +( +fœ¡_cmd +) + +261 || +chªÃl +-> +¥ec +-> +is_»äeshšg +( +fœ¡_cmd +); + +263 autØ + gbegš + = +»q +. +addr_vec +. +begš +(); + +264 autØ + g’d + = +begš + + 1; + +265 ; + g’d + < + gbegš + + ( + gT +:: +Lev– +:: +Row +è&& * +’d + >= 0;ƒnd++); + +267 +upd©e +( +fœ¡_cmd +, +¡©e_chªge +, +begš +, +’d +, +»adq +); + +268 +upd©e +( +fœ¡_cmd +, +¡©e_chªge +, +begš +, +’d +, +wr™eq +); + +269 +upd©e +( +fœ¡_cmd +, +¡©e_chªge +, +begš +, +’d +, +Ùh”q +); + +272  +issue_cmd +( +ty³Çme + +T +:: +Commªd + +cmd +, * +addr_vec +) + +275 + gchªÃl +-> +upd©e +( +cmd +, +addr_vec +, +þk +); + +277 ià( + g»cÜd_cmd_Œaû +){ + +279 auto& + gfže + = +cmd_Œaû_fžes +[ +addr_vec +[1]]; + +280 + g¡ršg +& + gcmd_Çme + = +chªÃl +-> +¥ec +-> +commªd_Çme +[( +cmd +)]; + +281 + gfže +<< + gþk +<<','<< + gcmd_Çme +; + +283 ià( + gcmd_Çme + =ð"PREA" || +cmd_Çme + == "REF") + +284 +fže +<< +’dl +; + +286  + gbªk_id + = +addr_vec +[( +T +:: +Lev– +:: +Bªk +)]; + +287 ià( + gchªÃl +-> + g¥ec +-> + g¡ªd¬d_Çme + =ð"DDR4" || +chªÃl +-> +¥ec +-> +¡ªd¬d_Çme + == "GDDR5") + +288 +bªk_id + +ð +addr_vec +[( +T +:: +Lev– +:: +Bªk +) - 1] * + +289 +chªÃl +-> +¥ec +-> +Üg_’Œy +. +couÁ +[( +T +:: +Lev– +:: +Bªk +)]; + +290 + gfže +<<','<< + gbªk_id +<< + g’dl +; + +293 ià( + g´št_cmd_Œaû +){ + +294 +´štf +("%5 %10ld:", +chªÃl +-> +¥ec +-> +commªd_Çme +[( +cmd +)]. +c_¡r +(), +þk +); + +295  + gËv + = 0;†ev < ( + gT +:: +Lev– +:: +MAX +);†ev++) + +296 +´štf +(" %5d", +addr_vec +[ +Ëv +]); + +297 +´štf +("\n"); + + @StatType.cpp + +1  + ~"StTy³.h +" + +3 +Çme¥aû + + gSts + { + +6 +StLi¡ + + g¡©li¡ +; + +9 +Tick + + gcurTick + = 0; + +12 + gHi¡og¿m +:: +grow_out +() + +14  +size + = +cvec +.size(); + +15  + gz”o + = +size + / 2; + +16  + gtÝ_h®f + = +z”o + + ( +size + - zero + 1) / 2; + +17  + gbÙtom_h®f + = ( +size + - +z”o +) / 2; + +20  + glow_·œ + = +z”o + - 1; + +21  + gi + = +z”o + - 1; i >ð +bÙtom_h®f +; i--) { + +22 + gcvec +[ +i +] = +cvec +[ +low_·œ +]; + +23 ià( + glow_·œ + - 1 >= 0) + +24 +cvec +[ +i +] +ðcvec[ +low_·œ + - 1]; + +25 + glow_·œ + -= 2; + +27 +as£¹ +( +low_·œ + == 0 ||†ow_pair == -1 ||†ow_pair == -2); + +29  + gi + = +bÙtom_h®f + - 1; i >= 0; i--) + +30 + gcvec +[ +i +] = +CouÁ” +(); + +33  + ghigh_·œ + = +z”o +; + +34  + gi + = +z”o +; i < + gtÝ_h®f +; i++) { + +35 + gcvec +[ +i +] = +cvec +[ +high_·œ +]; + +36 ià( + ghigh_·œ + + 1 < + gsize +) + +37 + gcvec +[ +i +] +ð +cvec +[ +high_·œ + + 1]; + +38 + ghigh_·œ + += 2; + +40 +as£¹ +( +high_·œ + =ð +size + || high_pair == size + 1); + +42  + gi + = +tÝ_h®f +; i < + gsize +; i++) + +43 + gcvec +[ +i +] = +CouÁ” +(); + +45 + gmax_buck‘ + *= 2; + +46 + gmš_buck‘ + *= 2; + +47 + gbuck‘_size + *= 2; + +51 + gHi¡og¿m +:: +grow_cÚv”t +() + +53  +size + = +cvec +.size(); + +54  + gh®f + = ( +size + + 1) / 2; + +57  + g·œ + = +size + - 1; + +58  + gi + = +size + - 1; i >ð +h®f +; --i) { + +59 + gcvec +[ +i +] = +cvec +[ +·œ +]; + +60 ià( + g·œ + - 1 >= 0) + +61 +cvec +[ +i +] +ðcvec[ +·œ + - 1]; + +62 + g·œ + -= 2; + +65  + gi + = +h®f + - 1; i >= 0; i--) + +66 + gcvec +[ +i +] = +CouÁ” +(); + +68 + gmš_buck‘ + = - +max_buck‘ +; + +69 + gbuck‘_size + *= 2; + +73 + gHi¡og¿m +:: +grow_up +() + +75  +size + = +cvec +.size(); + +76  + gh®f + = ( +size + + 1) / 2; + +78  + g·œ + = 0; + +79  + gi + = 0; i < + gh®f +; i++) { + +80 + gcvec +[ +i +] = +cvec +[ +·œ +]; + +81 ià( + g·œ + + 1 < + gsize +) + +82 + gcvec +[ +i +] +ð +cvec +[ +·œ + + 1]; + +83 + g·œ + += 2; + +85 +as£¹ +( +·œ + =ð +size + ||…air == size + 1); + +87  + gi + = +h®f +; i < + gsize +; i++) + +88 + gcvec +[ +i +] = +CouÁ” +(); + +90 + gmax_buck‘ + *= 2; + +91 + gbuck‘_size + *= 2; + +95 + gHi¡og¿m +:: +add +( +Hi¡og¿m + & +hs +) + +97 +size_ty³ + +b_size + = +hs +. +size +(); + +98 +as£¹ +( +size +(è=ð +b_size +); + +99 +as£¹ +( +mš_buck‘ + =ð +hs +.min_bucket); + +101 + gsum + +ð +hs +. +sum +; + +102 + glogs + +ð +hs +. +logs +; + +103 + gsqu¬es + +ð +hs +. +squ¬es +; + +104 + g§m¶es + +ð +hs +. +§m¶es +; + +106  + gbuck‘_size + > + ghs +.bucket_size) + +107 + ghs +. +grow_up +(); + +108  + gbuck‘_size + < + ghs +.bucket_size) + +109 +grow_up +(); + +111  +ušt32_t + + gi + = 0; i < + gb_size +; i++) + +112 + gcvec +[ +i +] +ð +hs +. +cvec +[i]; + +116 + gHi¡og¿m +:: +§m¶e +( +CouÁ” + +v® +,  +numb” +) + +118 +as£¹ +( +mš_buck‘ + < +max_buck‘ +); + +119 ià( + gv® + < + gmš_buck‘ +) { + +120 ià( + gmš_buck‘ + == 0) + +121 +grow_cÚv”t +(); + +123  + gv® + < + gmš_buck‘ +) + +124 +grow_out +(); + +125 } ià( + gv® + >ð +max_buck‘ + + +buck‘_size +) { + +126 ià( +mš_buck‘ + == 0) { + +127  +v® + >ð +max_buck‘ + + +buck‘_size +) + +128 +grow_up +(); + +130  + gv® + >ð +max_buck‘ + + +buck‘_size +) + +131 +grow_out +(); + +135 +size_ty³ + + gšdex + = + +136 ( +št64_t +) +¡d +:: +æoÜ +(( +v® + - +mš_buck‘ +è/ +buck‘_size +); + +138 +as£¹ +( +šdex + >ð0 && index < +size +()); + +139 + gcvec +[ +šdex +] +ð +numb” +; + +141 + gsum + +ð +v® + * +numb” +; + +142 + gsqu¬es + +ð +v® + * v® * +numb” +; + +143 + glogs + +ð +log +( +v® +è* +numb” +; + +144 + g§m¶es + +ð +numb” +; + + @StatType.h + +1 #iâdeà +__STATTYPE_H + + +2  + #__STATTYPE_H + + + ) + +4  + ~ + +5  + ~ + +6  + ~<¡ršg +> + +7  + ~ + +9  + ~<ÿs£¹ +> + +10  + ~ + +11  + ~ + +13 +Çme¥aû + + g¿muÏtÜ + { + +15 +þass + + gSÿÏrSt +; + +16 +þass + + gAv”ageSt +; + +17 +þass + + gVeùÜSt +; + +18 +þass + + gAv”ageVeùÜSt +; + +21 +Çme¥aû + + gSts + { + +23 cÚ¡  + g•s + = 1e-8; + +25  + tsize_ty³ +; + +26  + toff_ty³ +; + +27  + tCouÁ” +; + +28  + tResuÉ +; + +29  +ušt64_t + + tTick +; + +30  + g¡d +:: + tveùÜ +< + tCouÁ” +> + tVCouÁ” +; + +31  + g¡d +:: + tveùÜ +< + tResuÉ +> + tVResuÉ +; + +32  + g¡d +:: + tnum”ic_lim™s +< + tCouÁ” +> + tCouÁ”Lim™s +; + +35 cÚ¡ +ušt16_t + + gš™ + = 0x00000001; + +36 cÚ¡ +ušt16_t + + gdi¥Ïy + = 0x00000002; + +37 cÚ¡ +ušt16_t + + gtÙ® + = 0x00000010; + +38 cÚ¡ +ušt16_t + + gpdf + = 0x00000020; + +39 cÚ¡ +ušt16_t + + gcdf + = 0x00000040; + +40 cÚ¡ +ušt16_t + + gdi¡ + = 0x00000080; + +41 cÚ¡ +ušt16_t + + gnoz”o + = 0x00000100; + +42 cÚ¡ +ušt16_t + + gnÚª + = 0x00000200; + +44 þas  + cFÏgs + { + +45 + g´Ùeùed +: + +46 +ušt16_t + +æags +; + +47 + gpublic +: + +48 +FÏgs +(){} + +49 +FÏgs +( +ušt16_t + +æags +):flags(flags){} + +50  +Ý”©Ü +=( +ušt16_t + +_æags +){ +æags + = _flags;} + +51 +boÞ + +is_tÙ® +(ècÚ¡ { + gæags + & + gtÙ® +;} + +52 +boÞ + +is_pdf +(ècÚ¡ { + gæags + & + gpdf +;} + +53 +boÞ + +is_noz”o +(ècÚ¡ { + gæags + & + gnoz”o +;} + +54 +boÞ + +is_nÚª +(ècÚ¡ { + gæags + & + gnÚª +;} + +55 +boÞ + +is_cdf +(ècÚ¡ { + gæags + & + gcdf +;} + +56 +boÞ + +is_di¥Ïy +(ècÚ¡ { + gæags + & + gdi¥Ïy +;} + +59 þas  + cStBa£ + { + +60 + gpublic +: + +63 +vœtu® +  +´št +( +¡d +:: +of¡»am +& +fže +) = 0; + +65 +vœtu® + +size_ty³ + +size +() const = 0; + +66 +vœtu® + +boÞ + +z”o +() const = 0; + +67 +vœtu® +  +´•¬e +() = 0; + +68 +vœtu® +  +»£t +() = 0; + +70 +vœtu® + +VResuÉ + +v»suÉ +() const {  VResult(); }; + +71 +vœtu® + +ResuÉ + +tÙ® +() const {  Result(); }; + +73 +vœtu® + +boÞ + +is_di¥Ïy +() const = 0; + +74 +vœtu® + +boÞ + +is_noz”o +() const = 0; + +77 þas  + cStLi¡ + { + +78 + g´Ùeùed +: + +79 +¡d +:: +veùÜ +< +StBa£ +*> +li¡ +; + +80 + g¡d +:: +of¡»am + +¡©_ouut +; + +81 + gpublic +: + +82  +add +( +StBa£ +* +¡© +) { + +83 +li¡ +. +push_back +( +¡© +); + +85  +ouut +( +¡d +:: +¡ršg + +fž’ame +) { + +86 +¡©_ouut +. +Ý’ +( +fž’ame +. +c_¡r +(), +¡d +:: +ios_ba£ +:: +out +); + +87 ià(! + g¡©_ouut +. +good +()) { + +88 +as£¹ +( +çl£ + && "!stat_output.good()"); + +91  +´šÎ +() { + +92  +off_ty³ + + gi + = 0 ; i < + gli¡ +. +size +() ; ++i) { + +93 ià(! + gli¡ +[ +i +]) { + +96 ià( + gli¡ +[ +i +]-> +is_noz”o +(è&&†i¡[i]-> +z”o +()) { + +99 ià( + gli¡ +[ +i +]-> +is_di¥Ïy +()) { + +100 + gli¡ +[ +i +]-> +´•¬e +(); + +101 + gli¡ +[ +i +]-> +´št +( +¡©_ouut +); + +105 ~ +StLi¡ +() { + +106 + g¡©_ouut +. +þo£ +(); + +110 +StLi¡ + +¡©li¡ +; + +112 + g‹m¶©e +< +þass + + gD”ived +> + +113 þas  + cSt + : +public + +StBa£ + { + +114 +´Ùeùed +: + +115 +¡d +:: +¡ršg + +_Çme +; + +116 + g¡d +:: +¡ršg + +_desc +; + +117  + g_´ecisiÚ + = 1; + +118 +FÏgs + + g_æags + = +di¥Ïy +; + +119 + g¡d +:: +¡ršg + +£·¿tÜSŒšg +; + +120 + gpublic +: + +121 +St +() { + +122 +¡©li¡ +. +add +( +£låŒ +()); + +124 + gD”ived + & +£lf +(è{ * + g¡©ic_ÿ¡ +( + gthis +);} + +125 +D”ived + * +£låŒ +(è{ + g¡©ic_ÿ¡ +< + gD”ived +*>( + gthis +);} + +126 + gD”ived + & +Çme +(cÚ¡ +¡d +:: +¡ršg + & +__Çme +) { + +127 +_Çme + = +__Çme +; + +128  +£lf +(); + +130 + gD”ived + & +desc +(cÚ¡ +¡d +:: +¡ršg + & +__desc +) { + +131 +_desc + = +__desc +; + +132  +£lf +(); + +134 + gD”ived + & +´ecisiÚ +( +__´ecisiÚ +) { + +135 + g_´ecisiÚ + = +__´ecisiÚ +; + +136  +£lf +(); + +138 + gD”ived + & +æags +( +FÏgs + +__æags +) { + +139 + g_æags + = +__æags +; + +140  +£lf +(); + +143 + g‹m¶©e + < +þass + + gG’”icSt +> + +144 + gD”ived + & +´”eq +(cÚ¡ +G’”icSt + &…rereq) { + +147  +£lf +(); + +150 + gD”ived + & +£tS•¬©Ü +( +¡d +:: +¡ršg + +¡r +) { + +151 +£·¿tÜSŒšg + = +¡r +; + +152  +£lf +(); + +154 cÚ¡ + g¡d +:: +¡ršg +& +£tS•¬©Ü +(ècÚ¡ { +£·¿tÜSŒšg +;} + +156 +size_ty³ + +size +() const {  0; } + +158 +vœtu® +  +´št +( +¡d +:: +of¡»am +& +fže +) {}; + +159 +vœtu® +  +´šŠame +( +¡d +:: +of¡»am +& +fže +) { + +160 +fže +. +width +(40); + +161 + gfže + << + g_Çme +; + +164 +vœtu® +  +´štdesc +( +¡d +:: +of¡»am +& +fže +) { + +165 +fže +. +width +(40); + +166 + gfže + << "# " << + g_desc + << + g¡d +:: +’dl +; + +169 +vœtu® + +boÞ + +is_di¥Ïy +() const { + +170  + g_æags +. +is_di¥Ïy +(); + +173 +vœtu® + +boÞ + +is_noz”o +() const { + +174  + g_æags +. +is_noz”o +(); + +178 + g‹m¶©e + < +þass + + gSÿÏrTy³ +> + +179 +þass + + gSÿÏrBa£ +: +public + +St +< +SÿÏrTy³ +> { + +180 +public +: + +181 +vœtu® + +CouÁ” + +v®ue +() const = 0; + +182 +vœtu® + +ResuÉ + +»suÉ +() const = 0; + +183 +vœtu® + +ResuÉ + +tÙ® +() const = 0; + +185 +size_ty³ + +size +() const { 1;} + +186 +VResuÉ + +v»suÉ +(ècÚ¡ { VResuÉ(1, +»suÉ +());} + +188 +vœtu® +  +´št +( +¡d +:: +of¡»am +& +fže +) { + +189 +St +< +SÿÏrTy³ +>:: +´šŠame +( +fže +); + +191 + gfže +. +´ecisiÚ +( +St +< +SÿÏrTy³ +>:: +_´ecisiÚ +); + +192 + gfže +. +width +(20); + +193 +ResuÉ + + g»s + = +St +< +SÿÏrTy³ +>:: +£lf +(). +»suÉ +(); + +194 + gfže + << + g¡d +:: +fixed + << +»s +; + +195 + gSt +< + gSÿÏrTy³ +>:: +´štdesc +( +fže +); + +199 +þass + + gCÚ¡V®ue +: +public + +SÿÏrBa£ +< +CÚ¡V®ue +> { + +200 +´iv©e +: + +201 +CouÁ” + +_v®ue +; + +202 + gpublic +: + +203 +CÚ¡V®ue +( +CouÁ” + +__v®ue +): +_v®ue +(__value){} + +205  +Ý”©Ü + ++ (è{ ++ +_v®ue +; } + +206  + gÝ”©Ü + -- (è{ -- + g_v®ue +; } + +207  + gÝ”©Ü + ++ (è{ + g_v®ue +++; } + +208  + gÝ”©Ü + -- (è{ + g_v®ue +--; } + +210 + g‹m¶©e + < +ty³Çme + + gU +> + +211  + gÝ”©Ü + = (cÚ¡ +U + & +v +è{ +_v®ue + = v; } + +213 + g‹m¶©e + < +ty³Çme + + gU +> + +214  + gÝ”©Ü + +ð(cÚ¡ +U + & +v +è{ +_v®ue + += v;} + +216 + g‹m¶©e + < +ty³Çme + + gU +> + +217  + gÝ”©Ü + -ð(cÚ¡ +U + & +v +è{ +_v®ue + -= v;} + +220 +CouÁ” + +v®ue +(ècÚ¡ { + g_v®ue +;} + +221 +ResuÉ + +»suÉ +(ècÚ¡ { ( + gResuÉ +) + g_v®ue +;} + +222 +ResuÉ + +tÙ® +(ècÚ¡ { +»suÉ +();} + +223 +boÞ + +z”o +(ècÚ¡ { ( +çbs +( +_v®ue +è< + g•s +);} + +224  +´•¬e +() {} + +225  +»£t +() {} + +228 +þass + + gSÿÏr +: +public + +SÿÏrBa£ +< +SÿÏr +> { + +229 +´iv©e +: + +230 +CouÁ” + +_v®ue +; + +231 + gpublic +: + +232 +SÿÏr +(): +_v®ue +(0) {} + +233 +CouÁ” + +v®ue +(ècÚ¡ { +_v®ue +;} + +234 +ResuÉ + +»suÉ +(ècÚ¡ { ( + gResuÉ +) + g_v®ue +;} + +235 +ResuÉ + +tÙ® +(ècÚ¡ { ( + gResuÉ +) + g_v®ue +;} + +237  + gÝ”©Ü + ++ (è{ ++ + g_v®ue +; } + +238  + gÝ”©Ü + -- (è{ -- + g_v®ue +; } + +239  + gÝ”©Ü + ++ (è{ + g_v®ue +++; } + +240  + gÝ”©Ü + -- (è{ + g_v®ue +--; } + +242 + g‹m¶©e + < +ty³Çme + + gU +> + +243  + gÝ”©Ü + = (cÚ¡ +U + & +v +è{ +_v®ue + = v; } + +245 + g‹m¶©e + < +ty³Çme + + gU +> + +246  + gÝ”©Ü + +ð(cÚ¡ +U + & +v +è{ +_v®ue + += v;} + +248 + g‹m¶©e + < +ty³Çme + + gU +> + +249  + gÝ”©Ü + -ð(cÚ¡ +U + & +v +è{ +_v®ue + -= v;} + +252 +vœtu® + +boÞ + +z”o +(ècÚ¡ { ( +çbs +( +_v®ue +è< + g•s +);} + +253  +´•¬e +() {} + +254  +»£t +(è{ + g_v®ue + = +CouÁ” +();} + +258 +Tick + +curTick +; + +260 +þass + + gAv”age +: +public + +SÿÏrBa£ +< +Av”age +> { + +261 +´iv©e +: + +262 +CouÁ” + +cu¼’t +; + +263 +Tick + + gÏ¡Re£t +; + +264 +ResuÉ + + gtÙ®_v® +; + +265 +Tick + + gÏ¡ +; + +266 + gpublic +: + +267 +Av”age +(): +cu¼’t +(0), +Ï¡Re£t +(0), +tÙ®_v® +(0), +Ï¡ +(0){} + +269  +£t +( +CouÁ” + +v® +) { + +270 + gtÙ®_v® + +ð +cu¼’t + * ( +curTick + - +Ï¡ +); + +271 + gÏ¡ + = +curTick +; + +272 + gcu¼’t + = +v® +; + +274  +šc +( +CouÁ” + +v® +) { + +275 +£t +( +cu¼’t + + +v® +); + +277  +dec +( +CouÁ” + +v® +) { + +278 +£t +( +cu¼’t + - +v® +); + +280  + gÝ”©Ü + ++ (è{ +šc +(1); } + +281  + gÝ”©Ü + -- (è{ +dec +(1); } + +282  + gÝ”©Ü + ++ (è{ +šc +(1); } + +283  + gÝ”©Ü + -- (è{ +dec +(1); } + +285 + g‹m¶©e + < +ty³Çme + + gU +> + +286  + gÝ”©Ü + = (cÚ¡ +U + & +v +è{ +£t +(v); } + +288 + g‹m¶©e + < +ty³Çme + + gU +> + +289  + gÝ”©Ü + +ð(cÚ¡ +U + & +v +è{ +šc +(v);} + +291 + g‹m¶©e + < +ty³Çme + + gU +> + +292  + gÝ”©Ü + -ð(cÚ¡ +U + & +v +è{ +dec +(v);} + +295 +boÞ + +z”o +(ècÚ¡ {  ( +çbs +( +tÙ®_v® +è< + g•s +); } + +296  +´•¬e +() { + +297 + gtÙ®_v® + +ð +cu¼’t + * ( +curTick + - +Ï¡ +); + +298 + gÏ¡ + = +curTick +; + +300  +»£t +() { + +301 + gtÙ®_v® + = 0.0; + +302 + gÏ¡ + = +curTick +; + +303 + gÏ¡Re£t + = +curTick +; + +306 +CouÁ” + +v®ue +(ècÚ¡ {  + gcu¼’t +; } + +307 +ResuÉ + +»suÉ +() const { + +308 +as£¹ +( +Ï¡ + =ð +curTick +); + +309  ( + gResuÉ +)( + gtÙ®_v® + + + gcu¼’t +)/ (ResuÉ)( + gcurTick + - + gÏ¡Re£t + + 1); + +311 +ResuÉ + +tÙ® +(ècÚ¡ { +»suÉ +();} + +314 + g‹m¶©e +< +þass + + gD”ived +, cÏs  + gEËm’t +> + +315 +þass + + gVeùÜBa£ +: +public + +St +< +D”ived +> { + +316 +´iv©e +: + +317 +size_ty³ + +_size + = 0; + +318 + g¡d +:: +veùÜ +< +EËm’t +> +d©a +; + +320 + gpublic +: + +321  +š™ +( +size_ty³ + +__size +) { + +322 +_size + = +__size +; + +323 + gd©a +. +»size +( +size +()); + +324  +off_ty³ + + gi + = 0 ; i < +size +() ; ++i) { + +325 + gd©a +[ +i +]. +æags +(0) + +326 . +Çme +("[" + +¡d +:: +¡ršg +(1, ( +i + + '0')) + "]"); + +329 +size_ty³ + +size +(ècÚ¡ { + g_size +;} + +331  +v®ue +( +VCouÁ” +& +vec +) const { + +332 + gvec +. +»size +( +size +()); + +333  +off_ty³ + + gi + = 0 ; i < +size +() ; ++i) { + +334 + gvec +[ +i +] = +d©a +[i]. +v®ue +(); + +338  +»suÉ +( +VResuÉ +& +vec +) const { + +339 + gvec +. +»size +( +size +()); + +340  +off_ty³ + + gi + = 0 ; i < +size +() ; ++i) { + +341 + gvec +[ +i +] = +d©a +[i]. +»suÉ +(); + +345 +ResuÉ + +tÙ® +() const { + +346 +ResuÉ + + gsum + = 0.0; + +347  +off_ty³ + + gi + = 0 ; i < +size +() ; ++i) { + +348 + gsum + +ð +d©a +[ +i +]. +»suÉ +(); + +350  + gsum +; + +353 +VResuÉ + +v»suÉ +() const { + +354 +VResuÉ + + gv»s +; + +355  +off_ty³ + + gi + = 0 ; i < +size +() ; ++i) { + +356 + gv»s +[ +i +] = +d©a +[i]. +»suÉ +(); + +358  + gv»s +; + +361 +boÞ + +check +() const { + +364  + gŒue +; + +367 + gEËm’t + & + gÝ”©Ü +[]( +off_ty³ + + gšdex +) { + +368 +as£¹ +( +šdex + >ð0 && index < +size +()); + +369  + gd©a +[ +šdex +]; + +372 +boÞ + +z”o +() const { + +373  ( +çbs +( +tÙ® +()è< + g•s +); + +376  +´•¬e +() { + +377  +off_ty³ + + gi + = 0 ; i < +size +() ; ++i) { + +378 + gd©a +[ +i +]. +´•¬e +(); + +381  +»£t +() { + +382  +off_ty³ + + gi + = 0 ; i < +size +() ; ++i) { + +383 + gd©a +[ +i +]. +»£t +(); + +386  +´št +( +¡d +:: +of¡»am +& +fže +) { + +387 +St +< +D”ived +>:: +´šŠame +( +fže +); + +388 + gfže +. +´ecisiÚ +( +St +< +D”ived +>:: +_´ecisiÚ +); + +389 + gfže +. +width +(20); + +390 + gfže + << + g¡d +:: +fixed + << +tÙ® +(); + +391 + gSt +< + gD”ived +>:: +´štdesc +( +fže +); + +392  +off_ty³ + + gi + = 0 ; i < +size +() ; ++i) { + +393 + gd©a +[ +i +]. +´št +( +fže +); + +398 +þass + + gVeùÜ +: +public + +VeùÜBa£ +< +VeùÜ +, + gSÿÏr +> { + +401 +þass + + gAv”ageVeùÜ +: +public + +VeùÜBa£ +< +Av”ageVeùÜ +, + gAv”age +> { + +404 +þass + + gDi¡ributiÚ +: +public + +St +< +Di¡ributiÚ +> { + +405 +´iv©e +: + +407 +CouÁ” + +·¿m_mš +; + +408 +CouÁ” + + g·¿m_max +; + +409 +CouÁ” + + g·¿m_buck‘_size +; + +410 +CouÁ” + + g·¿m_buck‘s +; + +413 +CouÁ” + + gmš_Œack +; + +415 +CouÁ” + + gmax_Œack +; + +417 +CouÁ” + + gbuck‘_size +; + +419 +CouÁ” + + gmš_v® +; + +420 +CouÁ” + + gmax_v® +; + +422 +CouÁ” + + gund”æow +; + +424 +CouÁ” + + gov”æow +; + +426 +CouÁ” + + gsum +; + +428 +CouÁ” + + gsqu¬es +; + +430 +CouÁ” + + g§m¶es +; + +432 +VCouÁ” + + gcvec +; + +434 + gpublic +: + +435 +Di¡ributiÚ +(): +·¿m_mš +( +CouÁ” +()), +·¿m_max +(Counter()), + +436 +·¿m_buck‘_size +( +CouÁ” +()è{ +»£t +(); } + +437  +š™ +( +CouÁ” + +mš +, CouÁ” +max +, CouÁ” +bkt +) { + +438 + g·¿m_mš + = +mš +; + +439 + g·¿m_max + = +max +; + +440 + g·¿m_buck‘_size + = +bkt +; + +441 + g·¿m_buck‘s + = ( +size_ty³ +) +ûž +(( +max + - +mš + + 1.0è/ +bkt +); + +442 + gcvec +. +»size +( +·¿m_buck‘s +); + +444 +»£t +(); + +446  +§m¶e +( +CouÁ” + +v® +,  +numb” +) { + +447 ià( + gv® + < + gmš_Œack +) + +448 + gund”æow + +ð +numb” +; + +449 ià( + gv® + > + gmax_Œack +) + +450 + gov”æow + +ð +numb” +; + +452 +size_ty³ + + gšdex + = + +453 ( +size_ty³ +) +¡d +:: +æoÜ +(( +v® + - +mš_Œack +è/ +buck‘_size +); + +454 +as£¹ +( +šdex + < +size +()); + +455 + gcvec +[ +šdex +] +ð +numb” +; + +458 ià( + gv® + < + gmš_v® +) + +459 + gmš_v® + = +v® +; + +461 ià( + gv® + > + gmax_v® +) + +462 + gmax_v® + = +v® +; + +464 + gsum + +ð +v® + * +numb” +; + +465 + gsqu¬es + +ð +v® + * v® * +numb” +; + +466 + g§m¶es + +ð +numb” +; + +469 +size_ty³ + +size +(ècÚ¡ { + gcvec +.size();} + +470 +boÞ + +z”o +() const { + +471  ( +çbs +( +§m¶es +è< + g•s +); + +473  +´•¬e +() {}; + +474  +»£t +() { + +475 + gmš_Œack + = +·¿m_mš +; + +476 + gmax_Œack + = +·¿m_max +; + +477 + gbuck‘_size + = +·¿m_buck‘_size +; + +479 + gmš_v® + = +CouÁ”Lim™s +:: +max +(); + +480 + gmax_v® + = +CouÁ”Lim™s +:: +mš +(); + +481 + gund”æow + = +CouÁ” +(); + +482 + gov”æow + = +CouÁ” +(); + +484 +size_ty³ + + g_size + = +cvec +. +size +(); + +485  +off_ty³ + + gi + = 0 ; i < + g_size + ; ++i) { + +486 + gcvec +[ +i +] = +CouÁ” +(); + +489 + gsum + = +CouÁ” +(); + +490 + gsqu¬es + = +CouÁ” +(); + +491 + g§m¶es + = +CouÁ” +(); + +493  +add +( +Di¡ributiÚ + & +d +) { + +494 +size_ty³ + + gd_size + = +d +. +size +(); + +495 +as£¹ +( +size +(è=ð +d_size +); + +496 +as£¹ +( +mš_Œack + =ð +d +.min_track); + +497 +as£¹ +( +max_Œack + =ð +d +.max_track); + +499 + gund”æow + +ð +d +. +und”æow +; + +500 + gov”æow + +ð +d +. +ov”æow +; + +502 + gsum + +ð +d +. +sum +; + +503 + gsqu¬es + +ð +d +. +squ¬es +; + +504 + g§m¶es + +ð +d +. +§m¶es +; + +506 ià( + gd +. + gmš_v® + < min_val) { + +507 + gmš_v® + = +d +. +mš_v® +; + +510 ià( + gd +. + gmax_v® + > max_val) { + +511 + gmax_v® + = +d +. +max_v® +; + +514  +off_ty³ + + gi + = 0 ; i < + gd_size + ; ++i) { + +515 + gcvec +[ +i +] +ð +d +. +cvec +[i]; + +520 +þass + + gHi¡og¿m +: +public + +St +< +Hi¡og¿m +> { + +521 +´iv©e +: + +522 +size_ty³ + +·¿m_buck‘s +; + +524 +CouÁ” + + gmš_buck‘ +; + +525 +CouÁ” + + gmax_buck‘ +; + +526 +CouÁ” + + gbuck‘_size +; + +528 +CouÁ” + + gsum +; + +529 +CouÁ” + + glogs +; + +530 +CouÁ” + + gsqu¬es +; + +531 +CouÁ” + + g§m¶es +; + +532 +VCouÁ” + + gcvec +; + +534 + gpublic +: + +535 +Hi¡og¿m +(): +·¿m_buck‘s +(0è{ +»£t +(); } + +536 +Hi¡og¿m +( +size_ty³ + +__buck‘s +): +cvec +(__buckets) { + +537 +š™ +( +__buck‘s +); + +539  +š™ +( +size_ty³ + +__buck‘s +) { + +540 + gcvec +. +»size +( +__buck‘s +); + +541 + g·¿m_buck‘s + = +__buck‘s +; + +542 +»£t +(); + +545  +grow_up +(); + +546  +grow_out +(); + +547  +grow_cÚv”t +(); + +548  +add +( +Hi¡og¿m +& +hs +); + +549  +§m¶e +( +CouÁ” + +v® +,  +numb” +); + +551 +boÞ + +z”o +() const { + +552  ( +çbs +( +§m¶es +è< + g•s +); + +554  +´•¬e +() {} + +555  +»£t +() { + +556 + gmš_buck‘ + = 0; + +557 + gmax_buck‘ + = +·¿m_buck‘s + - 1; + +558 + gbuck‘_size + = 1; + +560 +size_ty³ + + gsize + = +·¿m_buck‘s +; + +561  +off_ty³ + + gi + = 0 ; i < + gsize + ; ++i) { + +562 + gcvec +[ +i +] = +CouÁ” +(); + +565 + gsum + = +CouÁ” +(); + +566 + gsqu¬es + = +CouÁ” +(); + +567 + g§m¶es + = +CouÁ” +(); + +568 + glogs + = +CouÁ” +(); + +571 +size_ty³ + +size +(ècÚ¡ { + g·¿m_buck‘s +;} + +574 +þass + + gSnd¬dDevŸtiÚ +: +public + +St +< +Snd¬dDevŸtiÚ +> { + +575 +´iv©e +: + +576 +CouÁ” + +sum +; + +577 +CouÁ” + + gsqu¬es +; + +578 +CouÁ” + + g§m¶es +; + +580 + gpublic +: + +581 +Snd¬dDevŸtiÚ +(): +sum +( +CouÁ” +()), +squ¬es +(Counter()), + +582 +§m¶es +( +CouÁ” +()) {} + +583  +§m¶e +( +CouÁ” + +v® +,  +numb” +) { + +584 +CouÁ” + + gv®ue + = +v® + * +numb” +; + +585 + gsum + +ð +v®ue +; + +586 + gsqu¬es + +ð +v®ue + * value; + +587 + g§m¶es + +ð +numb” +; + +589 +size_ty³ + +size +() const { 1;} + +590 +boÞ + +z”o +(ècÚ¡ { ( +çbs +( +§m¶es +è< + g•s +);} + +591  +´•¬e +() {} + +592  +»£t +() { + +593 + gsum + = +CouÁ” +(); + +594 + gsqu¬es + = +CouÁ” +(); + +595 + g§m¶es + = +CouÁ” +(); + +597  +add +( +Snd¬dDevŸtiÚ +& +sd +) { + +598 + gsum + +ð +sd +. +sum +; + +599 + gsqu¬es + +ð +sd +. +squ¬es +; + +600 + g§m¶es + +ð +sd +. +§m¶es +; + +604 +þass + + gAv”ageDevŸtiÚ +: +public + +St +< +Av”ageDevŸtiÚ +> { + +605 +´iv©e +: + +606 +CouÁ” + +sum +; + +607 +CouÁ” + + gsqu¬es +; + +609 + gpublic +: + +610 +Av”ageDevŸtiÚ +(): +sum +( +CouÁ” +()), +squ¬es +(Counter()) {} + +611  +§m¶e +( +CouÁ” + +v® +,  +numb” +) { + +612 +CouÁ” + + gv®ue + = +v® + * +numb” +; + +613 + gsum + +ð +v®ue +; + +614 + gsqu¬es + +ð +v®ue + * value; + +616 +size_ty³ + +size +() const { 1;} + +617 +boÞ + +z”o +(ècÚ¡ { ( +çbs +( +sum +è< + g•s +);} + +618  +´•¬e +() {} + +619  +»£t +() { + +620 + gsum + = +CouÁ” +(); + +621 + gsqu¬es + = +CouÁ” +(); + +623  +add +( +Av”ageDevŸtiÚ +& +ad +) { + +624 + gsum + +ð +ad +. +sum +; + +625 + gsqu¬es + +ð +ad +. +squ¬es +; + +629 þas  + cOp + { + +630 + g´iv©e +: + +631 +¡d +:: +¡ršg + +Ý¡ršg +; + +632 + gpublic +: + +633 +Op +() {} + +634 +Op +( +¡d +:: +¡ršg + +__Ý¡ršg +): +Ý¡ršg +(__opstring){} + +635 +ResuÉ + +Ý”©Ü +(è(ResuÉ +r +) const { + +636 ià( +Ý¡ršg + == "-") { + +637  - +r +; + +639 +as£¹ +("UÇry o³¿tiÚ cª oÆy buÇry‚eg©iÚ." && +çl£ +); + +642 +ResuÉ + +Ý”©Ü +(è(ResuÉ + gl +, ResuÉ + gr +) const { + +643 ià( + gÝ¡ršg + == "+") { + +644  +l + + +r +; + +645 } ià( + gÝ¡ršg + == "-") { + +646  +l + - +r +; + +647 } ià( + gÝ¡ršg + == "*") { + +648  +l + * +r +; + +649 } ià( + gÝ¡ršg + == "/") { + +650 +as£¹ +( +çbs +( +r +) > 1e-8 || "divide zeroƒrror"); + +651  + gl + / + gr +; + +653 +as£¹ +("šv®id bš¬y op¡ršg " && +çl£ +); + + @Statistics.h + +1 #iâdeà +__STATISTICS_H + + +2  + #__STATISTICS_H + + + ) + +4  + ~<¡ršg +> + +7 #ià! +defšed +( +RAMULATOR +) + +8  + #INTEGRATED_WITH_GEM5 + + + ) + +11 #ifdeà +INTEGRATED_WITH_GEM5 + + +12  + ~"ba£/¡©i¡ics.hh +" + +14  + ~"StTy³.h +" + +43 +Çme¥aû + + g¿muÏtÜ + { + +45 + g‹m¶©e +< +þass + + gStTy³ +> + +46 þas  + cStBa£ + { + +47 + g´Ùeùed +: + +48 +StTy³ + +¡© +; + +49 + g¡d +:: +¡ršg + +¡©Name +; + +51 + gStBa£ +< + gStTy³ +> & +£lf +(è{  * + gthis +; } + +52 + gpublic +: + +53 +StBa£ +() {} + +55 #iâdeà +INTEGRATED_WITH_GEM5 + + +56 cÚ¡ +StTy³ +* +g‘_¡© +() const { + +57  & +¡© +; + +61 +StBa£ +( +¡d +:: +¡ršg + +_Çme +) { + +62 +Çme +( +_Çme +); + +65 +StBa£ +( +¡d +:: +¡ršg + +_Çme +, std::¡ršg +_desc +) { + +66 +Çme +( +_Çme +); + +67 +desc +( +_desc +); + +70 + gStBa£ +< + gStTy³ +> & +Çme +( +¡d +:: +¡ršg + +_Çme +) { + +71 +¡©Name + = +_Çme +; + +72 + g¡© +. +Çme +("¿muÏtÜ." + +_Çme +); + +74  +£lf +(); + +77 cÚ¡ + g¡d +:: +¡ršg + & +Çme +(ècÚ¡ {  +¡©Name +; } + +79 + gStBa£ +< + gStTy³ +> & +£tS•¬©Ü +(cÚ¡ +¡d +:: +¡ršg + & +_£p +) { + +80 +¡© +. +£tS•¬©Ü +( +_£p +); + +81  +£lf +(); + +84 cÚ¡ + g¡d +:: +¡ršg + & +£tS•¬©Ü +(ècÚ¡ {  +¡© +.setSeparator(); } + +86 + gStBa£ +< + gStTy³ +> & +desc +( +¡d +:: +¡ršg + +_desc +) { + +87 +¡© +. +desc +( +_desc +); + +88  +£lf +(); + +91 + gStBa£ +< + gStTy³ +> & +´ecisiÚ +( +_´ecisiÚ +) { + +92 + g¡© +. +´ecisiÚ +( +_´ecisiÚ +); + +93  +£lf +(); + +96 + gStBa£ +< + gStTy³ +> & +æags +( +Sts +:: +FÏgs + +_æags +) { + +97 +¡© +. +æags +( +_æags +); + +98  +£lf +(); + +101 + g‹m¶©e + < +þass + + gSt +> + +102 + gStBa£ +< + gStTy³ +> & +´”eq +(cÚ¡ +St + & +_´”eq +) { + +103 + g¡© +. +´”eq +( +_´”eq +); + +104  +£lf +(); + +107 + gSts +:: +size_ty³ + +size +(ècÚ¡ {  +¡© +.size(); } + +108 +boÞ + +z”o +(ècÚ¡ {  + g¡© +.zero(); } + +109  +´•¬e +(è{ + g¡© +.prepare(); } + +110  +»£t +(è{ + g¡© +.reset(); } + +113 + g‹m¶©e +< +þass + + gStTy³ +> + +114 +þass + + gStBa£Vec + : +public + +StBa£ +< +StTy³ +> { + +115 +´Ùeùed +: + +116 +StBa£Vec +< +StTy³ +> & +£lf +(è{  * +this +; } + +118 + gpublic +: + +119 +StBa£Vec +< +StTy³ +> & +subÇme +( +Sts +:: +off_ty³ + +šdex +, cÚ¡ +¡d +:: +¡ršg + & +Çme +) { + +120 +StBa£ +< +StTy³ +>:: +¡© +. +subÇme +( +šdex +, +Çme +); + +121  +£lf +(); + +124 + gStBa£Vec +< + gStTy³ +> & +subdesc +( +Sts +:: +off_ty³ + +šdex +, cÚ¡ +¡d +:: +¡ršg + & +desc +) { + +125 +StBa£ +< +StTy³ +>:: +¡© +. +subdesc +( +šdex +, +desc +); + +126  +£lf +(); + +130 + g‹m¶©e +< +þass + + gStTy³ +> + +131 +þass + + gSÿÏrStBa£ + : +public + +StBa£ +< +StTy³ +> { + +132 +public +: + +133 +Sts +:: +CouÁ” + +v®ue +(ècÚ¡ {  +StBa£ +< +StTy³ +>:: +¡© +.value(); }; + +134  + gÝ”©Ü +++(è{ ++ + gStBa£ +< + gStTy³ +>:: +¡© +; } + +135  + gÝ”©Ü +--(è{ -- + gStBa£ +< + gStTy³ +>:: +¡© +; } + +137  + gÝ”©Ü +++(è{ + gStBa£ +< + gStTy³ +>:: +¡© +++; } + +138  + gÝ”©Ü +--(è{ + gStBa£ +< + gStTy³ +>:: +¡© +--; } + +140 + g‹m¶©e + < +ty³Çme + + gU +> + +141  + gÝ”©Ü +=(cÚ¡ +U + & +v +è{ +StBa£ +< +StTy³ +>:: +¡© + = v; } + +143 + g‹m¶©e + < +ty³Çme + + gU +> + +144  + gÝ”©Ü ++=(cÚ¡ +U + & +v +è{ +StBa£ +< +StTy³ +>:: +¡© + += v; } + +146 + g‹m¶©e + < +ty³Çme + + gU +> + +147  + gÝ”©Ü +-=(cÚ¡ +U + & +v +è{ +StBa£ +< +StTy³ +>:: +¡© + -= v; } + +150 + g‹m¶©e +< +þass + + gStTy³ +, cÏs  + gEËm’t +> + +151 +þass + + gVeùÜStBa£ + : +public + +StBa£Vec +< +StTy³ +> { + +152 +´Ùeùed +: + +153 +VeùÜStBa£ +< +StTy³ +, + gEËm’t +> & +£lf +(è{  * + gthis +; } + +155 + gpublic +: + +156  +v®ue +( +Sts +:: +VCouÁ” + & +vec +ècÚ¡ { +StBa£ +< +StTy³ +>:: +¡© +.value(vec); } + +157  +»suÉ +( +Sts +:: +VResuÉ + & +vec +ècÚ¡ { +StBa£ +< +StTy³ +>:: +¡© +.result(vec); } + +158 + gSts +:: +ResuÉ + +tÙ® +(ècÚ¡ {  +StBa£ +< +StTy³ +>:: +¡© +.total(); } + +160 +boÞ + +check +(ècÚ¡ {  + gStBa£ +< + gStTy³ +>:: +¡© +.check(); } + +162 + gVeùÜStBa£ +< + gStTy³ +, + gEËm’t +> & +š™ +( +Sts +:: +size_ty³ + +size +) { + +163 +StBa£ +< +StTy³ +>:: +¡© +. +š™ +( +size +); + +164  +£lf +(); + +167 #ifdeà +INTEGRATED_WITH_GEM5 + + +168 + gSts +:: +SÿÏrProxy +< +StTy³ +> +Ý”©Ü +[]( +Sts +:: +off_ty³ + +šdex +è{  +StBa£ +:: +¡© +[index]; } + +170 + gEËm’t + & + gÝ”©Ü +[]( + gSts +:: +off_ty³ + +šdex +è{  +StBa£ +< +StTy³ +>:: +¡© +[index]; } + +175 + g‹m¶©e +< +þass + + gStTy³ +> + +176 +þass + + gDi¡StBa£ + : +public + +StBa£ +< +StTy³ +> { + +177 +public +: + +178 +‹m¶©e +< +ty³Çme + +U +> + +179  +§m¶e +(cÚ¡ +U + & +v +,  +n + = 1è{ +StBa£ +< +StTy³ +>:: +¡© +.sample(v,‚); } + +181  +add +( +Di¡StBa£ + & +d +è{ + gStBa£ +< + gStTy³ +>:: +¡© +.add(d. +StBa£ +< +StTy³ +>::stat); } + +189 +þass + + gSÿÏrSt + : +public + +SÿÏrStBa£ +< +Sts +:: +SÿÏr +> { + +190 +public +: + +191 +usšg + +SÿÏrStBa£ +< +Sts +:: +SÿÏr +>:: +Ý”©Ü +=; + +194 +þass + + gAv”ageSt + : +public + +SÿÏrStBa£ +< +Sts +:: +Av”age +> { + +195 +public +: + +196 +usšg + +SÿÏrStBa£ +< +Sts +:: +Av”age +>:: +Ý”©Ü +=; + +199 +þass + + gVeùÜSt + : +public + +VeùÜStBa£ +< +Sts +:: +VeùÜ +, + gSts +:: +SÿÏr +> { + +202 +þass + + gAv”ageVeùÜSt + : +public + +VeùÜStBa£ +< +Sts +:: +Av”ageVeùÜ +, + gSts +:: +Av”age +> { + +205 +þass + + gDi¡ributiÚSt + : +public + +Di¡StBa£ +< +Sts +:: +Di¡ributiÚ +> { + +206 +´Ùeùed +: + +207 +Di¡ributiÚSt + & +£lf +(è{  * +this +; } + +209 + gpublic +: + +210 +Di¡ributiÚSt + & +š™ +( +Sts +:: +CouÁ” + +mš +, Sts::CouÁ” +max +, Sts::CouÁ” +bkt +) { + +211 +StBa£ +< +Sts +:: +Di¡ributiÚ +>:: +¡© +. +š™ +( +mš +, +max +, +bkt +); + +212  +£lf +(); + +217 +þass + + gHi¡og¿mSt + : +public + +Di¡StBa£ +< +Sts +:: +Hi¡og¿m +> { + +218 +´Ùeùed +: + +219 +Hi¡og¿mSt + & +£lf +(è{  * +this +; } + +221 + gpublic +: + +222 +Hi¡og¿mSt + & +š™ +( +Sts +:: +size_ty³ + +size +) { + +223 +StBa£ +< +Sts +:: +Hi¡og¿m +>:: +¡© +. +š™ +( +size +); + +224  +£lf +(); + +228 +þass + + gSnd¬dDevŸtiÚSt + : +public + +Di¡StBa£ +< +Sts +:: +Snd¬dDevŸtiÚ +> { + +231 +þass + + gAv”ageDevŸtiÚSt + : +public + +Di¡StBa£ +< +Sts +:: +Av”ageDevŸtiÚ +> { + + @TLDRAM.cpp + +1  + ~"TLDRAM.h +" + +2  + ~"DRAM.h +" + +3  + ~ + +4  + ~ + +5  + ~<ÿs£¹ +> + +7  + ~ + +9 +usšg + +Çme¥aû + + g¡d +; + +10 +usšg + +Çme¥aû + + g¿muÏtÜ +; + +12 +¡ršg + + gTLDRAM +:: +¡ªd¬d_Çme + = "TLDRAM"; + +14 + gm­ +< + g¡ršg +, + gTLDRAM +:: +Org +> +TLDRAM +:: +Üg_m­ + = { + +15 {"TLDRAM_512Mb_x4", +TLDRAM +:: +Org +:: +TLDRAM_512Mb_x4 +}, + +16 {"TLDRAM_512Mb_x8", +TLDRAM +:: +Org +:: +TLDRAM_512Mb_x8 +}, + +17 {"TLDRAM_512Mb_x16", +TLDRAM +:: +Org +:: +TLDRAM_512Mb_x16 +}, + +18 {"TLDRAM_1Gb_x4", +TLDRAM +:: +Org +:: +TLDRAM_1Gb_x4 +}, + +19 {"TLDRAM_1Gb_x8", +TLDRAM +:: +Org +:: +TLDRAM_1Gb_x8 +}, + +20 {"TLDRAM_1Gb_x16", +TLDRAM +:: +Org +:: +TLDRAM_1Gb_x16 +}, + +21 {"TLDRAM_2Gb_x4", +TLDRAM +:: +Org +:: +TLDRAM_2Gb_x4 +}, + +22 {"TLDRAM_2Gb_x8", +TLDRAM +:: +Org +:: +TLDRAM_2Gb_x8 +}, + +23 {"TLDRAM_2Gb_x16", +TLDRAM +:: +Org +:: +TLDRAM_2Gb_x16 +}, + +24 {"TLDRAM_4Gb_x4", +TLDRAM +:: +Org +:: +TLDRAM_4Gb_x4 +}, + +25 {"TLDRAM_4Gb_x8", +TLDRAM +:: +Org +:: +TLDRAM_4Gb_x8 +}, + +26 {"TLDRAM_4Gb_x16", +TLDRAM +:: +Org +:: +TLDRAM_4Gb_x16 +}, + +27 {"TLDRAM_8Gb_x4", +TLDRAM +:: +Org +:: +TLDRAM_8Gb_x4 +}, + +28 {"TLDRAM_8Gb_x8", +TLDRAM +:: +Org +:: +TLDRAM_8Gb_x8 +}, + +29 {"TLDRAM_8Gb_x16", +TLDRAM +:: +Org +:: +TLDRAM_8Gb_x16 +}, + +32 + gm­ +< + g¡ršg +, + gTLDRAM +:: +S³ed +> +TLDRAM +:: +¥“d_m­ + = { + +33 {"TLDRAM_800D", +TLDRAM +:: +S³ed +:: +TLDRAM_800D +}, + +34 {"TLDRAM_800E", +TLDRAM +:: +S³ed +:: +TLDRAM_800E +}, + +35 {"TLDRAM_1066E", +TLDRAM +:: +S³ed +:: +TLDRAM_1066E +}, + +36 {"TLDRAM_1066F", +TLDRAM +:: +S³ed +:: +TLDRAM_1066F +}, + +37 {"TLDRAM_1066G", +TLDRAM +:: +S³ed +:: +TLDRAM_1066G +}, + +38 {"TLDRAM_1333G", +TLDRAM +:: +S³ed +:: +TLDRAM_1333G +}, + +39 {"TLDRAM_1333H", +TLDRAM +:: +S³ed +:: +TLDRAM_1333H +}, + +40 {"TLDRAM_1600H", +TLDRAM +:: +S³ed +:: +TLDRAM_1600H +}, + +41 {"TLDRAM_1600J", +TLDRAM +:: +S³ed +:: +TLDRAM_1600J +}, + +42 {"TLDRAM_1600K", +TLDRAM +:: +S³ed +:: +TLDRAM_1600K +}, + +43 {"TLDRAM_1866K", +TLDRAM +:: +S³ed +:: +TLDRAM_1866K +}, + +44 {"TLDRAM_1866L", +TLDRAM +:: +S³ed +:: +TLDRAM_1866L +}, + +45 {"TLDRAM_2133L", +TLDRAM +:: +S³ed +:: +TLDRAM_2133L +}, + +46 {"TLDRAM_2133M", +TLDRAM +:: +S³ed +:: +TLDRAM_2133M +}, + +50 + gTLDRAM +:: + $TLDRAM +( +Org + +Üg +, +S³ed + +¥“d +,  +£gm’t_¿tio +) : + +51 + `£gm’t_¿tio +( +£gm’t_¿tio +), + +52 + `Üg_’Œy +( +Üg_bË +[( +Üg +)]), + +53 + `¥“d_’Œy +( +¥“d_bË +[( +¥“d +)]), + +54 + `»ad_Ï‹ncy +( +¥“d_’Œy +. +nCL + + s³ed_’Œy. +nBL +) + +56 +this +-> +£gm’t_¿tio + = segment_ratio; + +57 + `š™_¥“d +(); + +58 + `š™_´”eq +(); + +59 + `š™_rowh™ +(); + +60 + `š™_rowÝ’ +(); + +61 + `š™_Ïmbda +(); + +62 + `š™_timšg +(); + +63 + } +} + +65 + gTLDRAM +:: + $TLDRAM +(cÚ¡ +¡ršg +& +Üg_¡r +, cÚ¡ sŒšg& +¥“d_¡r +,  +£gm’t_¿tio +) : + +66 + $TLDRAM +( +Üg_m­ +[ +Üg_¡r +], +¥“d_m­ +[ +¥“d_¡r +], +£gm’t_¿tio +) + +68 +this +-> +£gm’t_¿tio + = segment_ratio; + +69 + } +} + +71  + gTLDRAM +:: + $£t_chªÃl_numb” +( +chªÃl +) { + +72 +Üg_’Œy +. +couÁ +[( +Lev– +:: +ChªÃl +)] = +chªÃl +; + +73 + } +} + +75  + gTLDRAM +:: + $£t_¿nk_numb” +( +¿nk +) { + +76 +Üg_’Œy +. +couÁ +[( +Lev– +:: +Rªk +)] = +¿nk +; + +77 + } +} + +79  + gTLDRAM +:: + $š™_¥“d +() + +82  +·ge + = ( +Üg_’Œy +. +dq + * org_’Œy. +couÁ +[( +Lev– +:: +CÞumn +)]) >> 13; + +83  +¥“d_’Œy +. +¿‹ +) { + +84 800: +¥“d_’Œy +. +nRRD + = ( +·ge +==1) ? 4 : 4; + +85 +¥“d_’Œy +. +nFAW + = ( +·ge +==1) ? 16 : 20; + +87 1066: +¥“d_’Œy +. +nRRD + = ( +·ge +==1) ? 4 : 6; + +88 +¥“d_’Œy +. +nFAW + = ( +·ge +==1) ? 20 : 27; + +91 +¥“d_’Œy +. +nRRD + = ( +·ge +==1) ? 4 : 5; + +92 +¥“d_’Œy +. +nFAW + = ( +·ge +==1) ? 20 : 30; + +95 +¥“d_’Œy +. +nRRD + = ( +·ge +==1) ? 5 : 6; + +96 +¥“d_’Œy +. +nFAW + = ( +·ge +==1) ? 24 : 32; + +99 +¥“d_’Œy +. +nRRD + = ( +·ge +==1) ? 5 : 6; + +100 +¥“d_’Œy +. +nFAW + = ( +·ge +==1) ? 26 : 33; + +103 +¥“d_’Œy +. +nRRD + = ( +·ge +==1) ? 5 : 6; + +104 +¥“d_’Œy +. +nFAW + = ( +·ge +==1) ? 27 : 34; + +106 : + `as£¹ +( +çl£ +); + +110  +ch + = +Üg_’Œy +. +size +; + +111  +¥“d_’Œy +. +¿‹ +) { + +112 800: +¥“d_’Œy +. +nRFC + = ( +ch +==512) ? 36 : (chip==1<<10) ? 44 + +113 : ( +ch +==1<<11) ? 64 : (chip==1<<12) ? 104 : 140; ; + +114 1066: +¥“d_’Œy +. +nRFC + = ( +ch +==512) ? 48 : (chip==1<<10) ? 59 + +115 : ( +ch +==1<<11) ? 86 : (chip==1<<12) ? 139 : 187; ; + +116 1333: +¥“d_’Œy +. +nRFC + = ( +ch +==512) ? 60 : (chip==1<<10) ? 74 + +117 : ( +ch +==1<<11) ? 107 : (chip==1<<12) ? 174 : 234; ; + +118 1600: +¥“d_’Œy +. +nRFC + = ( +ch +==512) ? 72 : (chip==1<<10) ? 88 + +119 : ( +ch +==1<<11) ? 128 : (chip==1<<12) ? 208 : 280; ; + +120 1866: +¥“d_’Œy +. +nRFC + = ( +ch +==512) ? 84 : (chip==1<<10) ? 103 + +121 : ( +ch +==1<<11) ? 150 : (chip==1<<12) ? 243 : 327; ; + +122 2133: +¥“d_’Œy +. +nRFC + = ( +ch +==512) ? 96 : (chip==1<<10) ? 118 + +123 : ( +ch +==1<<11) ? 171 : (chip==1<<12) ? 278 : 374; ; + +124 : + `as£¹ +( +çl£ +); + +126  +¥“d_’Œy +. +¿‹ +) { + +127 800: +¥“d_’Œy +. +nXS + = ( +ch +==512) ? 40 : (chip==1<<10) ? 48 + +128 : ( +ch +==1<<11) ? 68 : (chip==1<<12) ? 108 : 144; ; + +129 1066: +¥“d_’Œy +. +nXS + = ( +ch +==512) ? 54 : (chip==1<<10) ? 64 + +130 : ( +ch +==1<<11) ? 91 : (chip==1<<12) ? 144 : 192; ; + +131 1333: +¥“d_’Œy +. +nXS + = ( +ch +==512) ? 67 : (chip==1<<10) ? 80 + +132 : ( +ch +==1<<11) ? 114 : (chip==1<<12) ? 180 : 240; ; + +133 1600: +¥“d_’Œy +. +nXS + = ( +ch +==512) ? 80 : (chip==1<<10) ? 96 + +134 : ( +ch +==1<<11) ? 136 : (chip==1<<12) ? 216 : 288; ; + +135 1866: +¥“d_’Œy +. +nXS + = ( +ch +==512) ? 94 : (chip==1<<10) ? 112 + +136 : ( +ch +==1<<11) ? 159 : (chip==1<<12) ? 252 : 336; ; + +137 2133: +¥“d_’Œy +. +nXS + = ( +ch +==512) ? 107 : (chip==1<<10) ? 128 + +138 : ( +ch +==1<<11) ? 182 : (chip==1<<12) ? 288 : 384; ; + +139 : + `as£¹ +( +çl£ +); + +141 + } +} + +144  + gTLDRAM +:: + $š™_´”eq +() + +147 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +TLDRAM +>* +node +, Commªd +cmd +,  +id +) { + +148 ( +node +-> +¡©e +)) { + +149 ( +S‹ +:: +Pow”Up +):  +Commªd +:: +MAX +; + +150 ( +S‹ +:: +AùPow”Down +):  +Commªd +:: +PDX +; + +151 ( +S‹ +:: +P»Pow”Down +):  +Commªd +:: +PDX +; + +152 ( +S‹ +:: +S–fReäesh +):  +Commªd +:: +SRX +; + +153 : + `as£¹ +( +çl£ +); + +156 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +MIG +)] =…»»q[(Lev–::Rªk)][(Commªd:: +RD +)]; + +158 +´”eq +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +TLDRAM +>* +node +, Commªd +cmd +,  +id +) { + +159 ( +node +-> +¡©e +)) { + +160 ( +S‹ +:: +Clo£d +): + +161 ià( +id + % +node +-> +¥ec +-> +£gm’t_¿tio +) + +162  +Commªd +:: +ACT +; + +164  +Commªd +:: +ACTF +; + +165 ( +S‹ +:: +O³Ãd +): + +166 ià( +node +-> +row_¡©e +. + `fšd +( +id +è!ðnode->row_¡©e. + `’d +()) + +167  +cmd +; + +168 ià( +id + % +node +-> +¥ec +-> +£gm’t_¿tio +) + +169  +Commªd +:: +PRE +; + +171  +Commªd +:: +PREF +; + +172 : + `as£¹ +( +çl£ +); + +175 +´”eq +[( +Lev– +:: +Bªk +)][( +Commªd +:: +MIG +)] = [] ( +DRAM +< +TLDRAM +>* +node +, Commªd +cmd +,  +id +) { + +176 ( +node +-> +¡©e +)) { + +177 ( +S‹ +:: +Clo£d +): + +178  +Commªd +:: +ACTM +; + +179 ( +S‹ +:: +O³Ãd +): + +180 ià( +node +-> +row_¡©e +. + `fšd +( +id +è!ðnode->row_¡©e. + `’d +()) + +181  +cmd +; + +182  +Commªd +:: +PREM +; + +183 : + `as£¹ +( +çl£ +); + +188 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +WR +)] =…»»q[(Lev–::Rªk)][(Commªd:: +RD +)]; + +189 +´”eq +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] =…»»q[(Lev–::Bªk)][(Commªd:: +RD +)]; + +192 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +REF +)] = [] ( +DRAM +< +TLDRAM +>* +node +, Commªd +cmd +,  +id +) { + +193 autØ +bªk + : +node +-> +chžd»n +) { + +194 ià( +bªk +-> +¡©e + =ð +S‹ +:: +Clo£d +) + +196 ià( +id + % +node +-> +¥ec +-> +£gm’t_¿tio +) + +197  +Commªd +:: +PREA +; + +199  +Commªd +:: +PREAF +; + +201  +Commªd +:: +REF +; + +205 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PDE +)] = [] ( +DRAM +< +TLDRAM +>* +node +, Commªd +cmd +,  +id +) { + +206 ( +node +-> +¡©e +)) { + +207 ( +S‹ +:: +Pow”Up +):  +Commªd +:: +PDE +; + +208 ( +S‹ +:: +AùPow”Down +):  +Commªd +:: +PDE +; + +209 ( +S‹ +:: +P»Pow”Down +):  +Commªd +:: +PDE +; + +210 ( +S‹ +:: +S–fReäesh +):  +Commªd +:: +SRX +; + +211 : + `as£¹ +( +çl£ +); + +216 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +SRE +)] = [] ( +DRAM +< +TLDRAM +>* +node +, Commªd +cmd +,  +id +) { + +217 ( +node +-> +¡©e +)) { + +218 ( +S‹ +:: +Pow”Up +):  +Commªd +:: +SRE +; + +219 ( +S‹ +:: +AùPow”Down +):  +Commªd +:: +PDX +; + +220 ( +S‹ +:: +P»Pow”Down +):  +Commªd +:: +PDX +; + +221 ( +S‹ +:: +S–fReäesh +):  +Commªd +:: +SRE +; + +222 : + `as£¹ +( +çl£ +); + +225 + } +} + +228  + gTLDRAM +:: + $š™_rowh™ +() + +231 +rowh™ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +TLDRAM +>* +node +, Commªd +cmd +,  +id +) { + +232 ( +node +-> +¡©e +)) { + +233 ( +S‹ +:: +Clo£d +):  +çl£ +; + +234 ( +S‹ +:: +O³Ãd +): + +235 ià( +node +-> +row_¡©e +. + `fšd +( +id +è!ðnode->row_¡©e. + `’d +()) + +236  +Œue +; + +237  +çl£ +; + +238 : + `as£¹ +( +çl£ +); + +242 +rowh™ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] =„owh™[(Lev–::Bªk)][(Commªd:: +RD +)]; + +243 + } +} + +245  + gTLDRAM +:: + $š™_rowÝ’ +() + +248 +rowÝ’ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +TLDRAM +>* +node +, Commªd +cmd +,  +id +) { + +249 ( +node +-> +¡©e +)) { + +250 ( +S‹ +:: +Clo£d +):  +çl£ +; + +251 ( +S‹ +:: +O³Ãd +):  +Œue +; + +252 : + `as£¹ +( +çl£ +); + +256 +rowÝ’ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] =„owÝ’[(Lev–::Bªk)][(Commªd:: +RD +)]; + +257 + } +} + +259  + gTLDRAM +:: + $š™_Ïmbda +() + +261 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +ACT +)] = [] ( +DRAM +< +TLDRAM +>* +node +,  +id +) { + +262 +node +-> +¡©e + = +S‹ +:: +O³Ãd +; + +263 +node +-> +row_¡©e +[ +id +] = +S‹ +:: +O³Ãd +; + +265 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +ACTF +)] = [] ( +DRAM +< +TLDRAM +>* +node +,  +id +) { + +266 +node +-> +¡©e + = +S‹ +:: +O³Ãd +; + +267 +node +-> +row_¡©e +[ +id +] = +S‹ +:: +O³Ãd +; + +269 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +ACTM +)] = [] ( +DRAM +< +TLDRAM +>* +node +,  +id +) { + +270 +node +-> +¡©e + = +S‹ +:: +O³Ãd +; + +271 +node +-> +row_¡©e +[ +id +] = +S‹ +:: +O³Ãd +; + +273 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +PRE +)] = [] ( +DRAM +< +TLDRAM +>* +node +,  +id +) { + +274 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +275 +node +-> +row_¡©e +. + `þ—r +(); + +277 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +PREF +)] = [] ( +DRAM +< +TLDRAM +>* +node +,  +id +) { + +278 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +279 +node +-> +row_¡©e +. + `þ—r +(); + +281 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +PREM +)] = [] ( +DRAM +< +TLDRAM +>* +node +,  +id +) { + +282 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +283 +node +-> +row_¡©e +. + `þ—r +(); + +285 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PREA +)] = [] ( +DRAM +< +TLDRAM +>* +node +,  +id +) { + +286 autØ +bªk + : +node +-> +chžd»n +) { + +287 +bªk +-> +¡©e + = +S‹ +:: +Clo£d +; + +288 +bªk +-> +row_¡©e +. + `þ—r +(); + +291 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PREAF +)] = [] ( +DRAM +< +TLDRAM +>* +node +,  +id +) { + +292 autØ +bªk + : +node +-> +chžd»n +) { + +293 +bªk +-> +¡©e + = +S‹ +:: +Clo£d +; + +294 +bªk +-> +row_¡©e +. + `þ—r +(); + +297 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PREAM +)] = [] ( +DRAM +< +TLDRAM +>* +node +,  +id +) { + +298 autØ +bªk + : +node +-> +chžd»n +) { + +299 +bªk +-> +¡©e + = +S‹ +:: +Clo£d +; + +300 +bªk +-> +row_¡©e +. + `þ—r +(); + +303 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +REF +)] = [] ( +DRAM +< +TLDRAM +>* +node +,  +id +) {}; + +304 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +REF +)] = [] ( +DRAM +< +TLDRAM +>* +node +,  +id +) {}; + +305 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +TLDRAM +>* +node +,  +id +) {}; + +306 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] = [] ( +DRAM +< +TLDRAM +>* +node +,  +id +) {}; + +307 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +MIG +)] = [] ( +DRAM +< +TLDRAM +>* +node +,  +id +) {}; + +308 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PDE +)] = [] ( +DRAM +< +TLDRAM +>* +node +,  +id +) { + +309 autØ +bªk + : +node +-> +chžd»n +) { + +310 ià( +bªk +-> +¡©e + =ð +S‹ +:: +Clo£d +) + +312 +node +-> +¡©e + = +S‹ +:: +AùPow”Down +; + +315 +node +-> +¡©e + = +S‹ +:: +P»Pow”Down +; + +317 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PDX +)] = [] ( +DRAM +< +TLDRAM +>* +node +,  +id +) { + +318 +node +-> +¡©e + = +S‹ +:: +Pow”Up +; + +320 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +SRE +)] = [] ( +DRAM +< +TLDRAM +>* +node +,  +id +) { + +321 +node +-> +¡©e + = +S‹ +:: +S–fReäesh +; + +323 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +SRX +)] = [] ( +DRAM +< +TLDRAM +>* +node +,  +id +) { + +324 +node +-> +¡©e + = +S‹ +:: +Pow”Up +; + +326 + } +} + +329  + gTLDRAM +:: + $š™_timšg +() + +331 +S³edEÁry +& +s + = +¥“d_’Œy +; + +332 +veùÜ +< +TimšgEÁry +> * +t +; + +335 +t + = +timšg +[( +Lev– +:: +ChªÃl +)]; + +338 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nBL +}); + +339 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +MIG +, 1, +s +. +nBL +}); + +340 +t +[( +Commªd +:: +MIG +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nBL +}); + +341 +t +[( +Commªd +:: +MIG +)]. + `push_back +({Commªd::MIG, 1, +s +. +nBL +}); + +342 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd::WR, 1, +s +. +nBL +}); + +346 +t + = +timšg +[( +Lev– +:: +Rªk +)]; + +349 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nCCD +}); + +350 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +MIG +, 1, +s +. +nCCD +}); + +351 +t +[( +Commªd +:: +MIG +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCCD +}); + +352 +t +[( +Commªd +:: +MIG +)]. + `push_back +({Commªd::MIG, 1, +s +. +nCCD +}); + +354 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nCCD + + 2 - s. +nCWL +}); + +355 +t +[( +Commªd +:: +MIG +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nCCD + + 2 - s. +nCWL +}); + +356 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTR +}); + +357 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +MIG +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTR +}); + +359 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd::WR, 1, +s +. +nCCD +}); + +362 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +363 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +MIG +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +364 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +365 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nBL + + s. +nRTRS + - s. +nCWL +, +Œue +}); + +366 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PREA +, 1, +s +. +nRTP +}); + +367 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PREAF +, 1, +s +. +nRTP +}); + +368 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PREAM +, 1, +s +. +nRTP +}); + +370 +t +[( +Commªd +:: +MIG +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +371 +t +[( +Commªd +:: +MIG +)]. + `push_back +({Commªd::MIG, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +372 +t +[( +Commªd +:: +MIG +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +373 +t +[( +Commªd +:: +MIG +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nBL + + s. +nRTRS + - s. +nCWL +, +Œue +}); + +374 +t +[( +Commªd +:: +MIG +)]. + `push_back +({Commªd:: +PREA +, 1, +s +. +nRTP +}); + +375 +t +[( +Commªd +:: +MIG +)]. + `push_back +({Commªd:: +PREAF +, 1, +s +. +nRTP +}); + +376 +t +[( +Commªd +:: +MIG +)]. + `push_back +({Commªd:: +PREAM +, 1, +s +. +nRTP +}); + +378 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nRTRS + - s. +nCL +, +Œue +}); + +379 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +MIG +, 1, +s +. +nCWL + + s. +nBL + + s. +nRTRS + - s. +nCL +, +Œue +}); + +380 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PREA +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +}); + +381 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PREAF +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +}); + +382 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PREAM +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +}); + +385 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nCL + + s. +nBL + + 1}); + +386 +t +[( +Commªd +:: +MIG +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nCL + + s. +nBL + + 1}); + +387 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +}); + +388 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nXP +}); + +389 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +MIG +, 1, +s +. +nXP +}); + +390 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nXP +}); + +395 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 1, +s +. +nRRD +}); + +396 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 4, +s +. +nFAW +}); + +397 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +ACTF +, 1, +s +. +nRRD +}); + +398 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +ACTF +, 4, +s +. +nFAW +}); + +399 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +ACTM +, 1, +s +. +nRRD +}); + +400 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +ACTM +, 4, +s +. +nFAW +}); + +401 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nRAS +}); + +402 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PREA +, 1, +s +. +nRAS +}); + +403 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PREF +, 1, +s +. +nRAS +}); + +404 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PREAF +, 1, +s +. +nRAS +}); + +405 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PREM +, 1, +s +. +nRAS +}); + +406 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PREAM +, 1, +s +. +nRAS +}); + +408 +t +[( +Commªd +:: +ACTF +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRRD +}); + +409 +t +[( +Commªd +:: +ACTF +)]. + `push_back +({Commªd:: +ACT +, 4, +s +. +nFAW +}); + +410 +t +[( +Commªd +:: +ACTF +)]. + `push_back +({Commªd::ACTF, 1, +s +. +nRRD +}); + +411 +t +[( +Commªd +:: +ACTF +)]. + `push_back +({Commªd::ACTF, 4, +s +. +nFAW +}); + +412 +t +[( +Commªd +:: +ACTF +)]. + `push_back +({Commªd:: +ACTM +, 1, +s +. +nRRD +}); + +413 +t +[( +Commªd +:: +ACTF +)]. + `push_back +({Commªd:: +ACTM +, 4, +s +. +nFAW +}); + +414 +t +[( +Commªd +:: +ACTF +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nRASF +}); + +415 +t +[( +Commªd +:: +ACTF +)]. + `push_back +({Commªd:: +PREA +, 1, +s +. +nRASF +}); + +416 +t +[( +Commªd +:: +ACTF +)]. + `push_back +({Commªd:: +PREF +, 1, +s +. +nRASF +}); + +417 +t +[( +Commªd +:: +ACTF +)]. + `push_back +({Commªd:: +PREAF +, 1, +s +. +nRASF +}); + +418 +t +[( +Commªd +:: +ACTF +)]. + `push_back +({Commªd:: +PREM +, 1, +s +. +nRASF +}); + +419 +t +[( +Commªd +:: +ACTF +)]. + `push_back +({Commªd:: +PREAM +, 1, +s +. +nRASF +}); + +421 +t +[( +Commªd +:: +ACTM +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRRD +}); + +422 +t +[( +Commªd +:: +ACTM +)]. + `push_back +({Commªd:: +ACT +, 4, +s +. +nFAW +}); + +423 +t +[( +Commªd +:: +ACTM +)]. + `push_back +({Commªd:: +ACTF +, 1, +s +. +nRRD +}); + +424 +t +[( +Commªd +:: +ACTM +)]. + `push_back +({Commªd:: +ACTF +, 4, +s +. +nFAW +}); + +425 +t +[( +Commªd +:: +ACTM +)]. + `push_back +({Commªd::ACTM, 1, +s +. +nRRD +}); + +426 +t +[( +Commªd +:: +ACTM +)]. + `push_back +({Commªd::ACTM, 4, +s +. +nFAW +}); + +427 +t +[( +Commªd +:: +ACTM +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nRASM +}); + +428 +t +[( +Commªd +:: +ACTM +)]. + `push_back +({Commªd:: +PREA +, 1, +s +. +nRASM +}); + +429 +t +[( +Commªd +:: +ACTM +)]. + `push_back +({Commªd:: +PREF +, 1, +s +. +nRASM +}); + +430 +t +[( +Commªd +:: +ACTM +)]. + `push_back +({Commªd:: +PREAF +, 1, +s +. +nRASM +}); + +431 +t +[( +Commªd +:: +ACTM +)]. + `push_back +({Commªd:: +PREM +, 1, +s +. +nRASM +}); + +432 +t +[( +Commªd +:: +ACTM +)]. + `push_back +({Commªd:: +PREAM +, 1, +s +. +nRASM +}); + +434 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRP +}); + +435 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +ACTF +, 1, +s +. +nRP +}); + +436 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +ACTM +, 1, +s +. +nRP +}); + +438 +t +[( +Commªd +:: +PREF +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRPF +}); + +439 +t +[( +Commªd +:: +PREF +)]. + `push_back +({Commªd:: +ACTF +, 1, +s +. +nRPF +}); + +440 +t +[( +Commªd +:: +PREF +)]. + `push_back +({Commªd:: +ACTM +, 1, +s +. +nRPF +}); + +442 +t +[( +Commªd +:: +PREM +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRPM +}); + +443 +t +[( +Commªd +:: +PREM +)]. + `push_back +({Commªd:: +ACTF +, 1, +s +. +nRPM +}); + +444 +t +[( +Commªd +:: +PREM +)]. + `push_back +({Commªd:: +ACTM +, 1, +s +. +nRPM +}); + +447 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nRP +}); + +448 +t +[( +Commªd +:: +PREF +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nRPF +}); + +449 +t +[( +Commªd +:: +PREM +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nRPM +}); + +451 +t +[( +Commªd +:: +PREA +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nRP +}); + +452 +t +[( +Commªd +:: +PREAF +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nRPF +}); + +453 +t +[( +Commªd +:: +PREAM +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nRPM +}); + +455 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRFC +}); + +456 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd:: +ACTF +, 1, +s +. +nRFC +}); + +457 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd:: +ACTM +, 1, +s +. +nRFC +}); + +460 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PDE +, 1, 1}); + +461 +t +[( +Commªd +:: +ACTF +)]. + `push_back +({Commªd:: +PDE +, 1, 1}); + +462 +t +[( +Commªd +:: +ACTM +)]. + `push_back +({Commªd:: +PDE +, 1, 1}); + +464 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nXP +}); + +465 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +ACTF +, 1, +s +. +nXP +}); + +466 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +ACTM +, 1, +s +. +nXP +}); + +468 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nXP +}); + +469 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PREF +, 1, +s +. +nXP +}); + +470 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PREM +, 1, +s +. +nXP +}); + +473 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nRP +}); + +474 +t +[( +Commªd +:: +PREF +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nRPF +}); + +475 +t +[( +Commªd +:: +PREM +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nRPM +}); + +476 +t +[( +Commªd +:: +PREA +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nRP +}); + +477 +t +[( +Commªd +:: +PREAF +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nRPF +}); + +478 +t +[( +Commªd +:: +PREAM +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nRPM +}); + +480 +t +[( +Commªd +:: +SRX +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nXS +}); + +481 +t +[( +Commªd +:: +SRX +)]. + `push_back +({Commªd:: +ACTF +, 1, +s +. +nXS +}); + +482 +t +[( +Commªd +:: +SRX +)]. + `push_back +({Commªd:: +ACTM +, 1, +s +. +nXS +}); + +485 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd::REF, 1, +s +. +nRFC +}); + +488 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd:: +PDE +, 1, 1}); + +489 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nXP +}); + +492 +t +[( +Commªd +:: +SRX +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nXS +}); + +495 +t +[( +Commªd +:: +PDE +)]. + `push_back +({Commªd:: +PDX +, 1, +s +. +nPD +}); + +496 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nXP +}); + +499 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nXP +}); + +500 +t +[( +Commªd +:: +SRX +)]. + `push_back +({Commªd:: +PDE +, 1, +s +. +nXS +}); + +503 +t +[( +Commªd +:: +SRE +)]. + `push_back +({Commªd:: +SRX +, 1, +s +. +nCKESR +}); + +504 +t +[( +Commªd +:: +SRX +)]. + `push_back +({Commªd:: +SRE +, 1, +s +. +nXS +}); + +508 +t + = +timšg +[( +Lev– +:: +Bªk +)]; + +511 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nRCD +}); + +512 +t +[( +Commªd +:: +ACTF +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nRCDF +}); + +513 +t +[( +Commªd +:: +ACTM +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nRCDM +}); + +515 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +MIG +, 1, +s +. +nRCD +}); + +516 +t +[( +Commªd +:: +ACTF +)]. + `push_back +({Commªd:: +MIG +, 1, +s +. +nRCDF +}); + +517 +t +[( +Commªd +:: +ACTM +)]. + `push_back +({Commªd:: +MIG +, 1, +s +. +nRCDM +}); + +519 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nRCD +}); + +520 +t +[( +Commªd +:: +ACTF +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nRCDF +}); + +521 +t +[( +Commªd +:: +ACTM +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nRCDM +}); + +523 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nRTP +}); + +524 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PREF +, 1, +s +. +nRTP +}); + +525 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PREM +, 1, +s +. +nRTP +}); + +527 +t +[( +Commªd +:: +MIG +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nRTP +}); + +528 +t +[( +Commªd +:: +MIG +)]. + `push_back +({Commªd:: +PREF +, 1, +s +. +nRTP +}); + +529 +t +[( +Commªd +:: +MIG +)]. + `push_back +({Commªd:: +PREM +, 1, +s +. +nRTP +}); + +531 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +}); + +532 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PREF +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +}); + +536 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 1, +s +. +nRC +}); + +537 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +ACTF +, 1, +s +. +nRC +}); + +538 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +ACTM +, 1, +s +. +nRC +}); + +539 +t +[( +Commªd +:: +ACTF +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRCF +}); + +540 +t +[( +Commªd +:: +ACTF +)]. + `push_back +({Commªd::ACTF, 1, +s +. +nRCF +}); + +541 +t +[( +Commªd +:: +ACTF +)]. + `push_back +({Commªd:: +ACTM +, 1, +s +. +nRCF +}); + +542 +t +[( +Commªd +:: +ACTM +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRCM +}); + +543 +t +[( +Commªd +:: +ACTM +)]. + `push_back +({Commªd:: +ACTF +, 1, +s +. +nRCM +}); + +544 +t +[( +Commªd +:: +ACTM +)]. + `push_back +({Commªd::ACTM, 1, +s +. +nRCM +}); + +546 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nRAS +}); + +547 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PREF +, 1, +s +. +nRAS +}); + +548 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PREM +, 1, +s +. +nRAS +}); + +549 +t +[( +Commªd +:: +ACTF +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nRASF +}); + +550 +t +[( +Commªd +:: +ACTF +)]. + `push_back +({Commªd:: +PREF +, 1, +s +. +nRASF +}); + +551 +t +[( +Commªd +:: +ACTF +)]. + `push_back +({Commªd:: +PREM +, 1, +s +. +nRASF +}); + +552 +t +[( +Commªd +:: +ACTM +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nRASM +}); + +553 +t +[( +Commªd +:: +ACTM +)]. + `push_back +({Commªd:: +PREF +, 1, +s +. +nRASM +}); + +554 +t +[( +Commªd +:: +ACTM +)]. + `push_back +({Commªd:: +PREM +, 1, +s +. +nRASM +}); + +556 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRP +}); + +557 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +ACTF +, 1, +s +. +nRP +}); + +558 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +ACTM +, 1, +s +. +nRP +}); + +559 +t +[( +Commªd +:: +PREF +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRPF +}); + +560 +t +[( +Commªd +:: +PREF +)]. + `push_back +({Commªd:: +ACTF +, 1, +s +. +nRPF +}); + +561 +t +[( +Commªd +:: +PREF +)]. + `push_back +({Commªd:: +ACTM +, 1, +s +. +nRPF +}); + +562 +t +[( +Commªd +:: +PREM +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRPM +}); + +563 +t +[( +Commªd +:: +PREM +)]. + `push_back +({Commªd:: +ACTF +, 1, +s +. +nRPM +}); + +564 +t +[( +Commªd +:: +PREM +)]. + `push_back +({Commªd:: +ACTM +, 1, +s +. +nRPM +}); + +566 + } +} + + @TLDRAM.h + +1 #iâdeà +__TLDRAM_H + + +2  + #__TLDRAM_H + + + ) + +4  + ~"DRAM.h +" + +5  + ~"Reque¡.h +" + +6  + ~ + +7  + ~ + +8  + ~<¡ršg +> + +9  + ~ + +11 +usšg + +Çme¥aû + + g¡d +; + +13 +Çme¥aû + + g¿muÏtÜ + + +16 þas  + cTLDRAM + + +18 + gpublic +: + +19  +£gm’t_¿tio + = 16; + +21  +¡ršg + + g¡ªd¬d_Çme +; + +22 +þass + + gOrg +; + +23 +þass + + gS³ed +; + +24 +TLDRAM +( +Org + +Üg +, +S³ed + +¥“d +,  +£gm’t_¿tio +); + +25 +TLDRAM +(cÚ¡ +¡ršg +& +Üg_¡r +, cÚ¡ sŒšg& +¥“d_¡r +,  +£gm’t_¿tio +); + +27  + gm­ +< + g¡ršg +, + gOrg +> + gÜg_m­ +; + +28  + gm­ +< + g¡ršg +, + gS³ed +> + g¥“d_m­ +; + +30 þas  + cLev– + :  + +32 +ChªÃl +, + gRªk +, + gBªk +, + gRow +, + gCÞumn +, + gMAX + + +36 þas  + cCommªd + :  + +38 +ACT +, + gPRE +, + gPREA +, + +39 + gRD +, + gWR +, + +40 + gREF +, + gPDE +, + gPDX +, + gSRE +, + gSRX +, + +41 + gACTF +, + gPREF +, + gPREAF +, + +42 + gMIG +, + +43 + gACTM +, + gPREM +, + gPREAM +, + +44 + gMAX + + +47 +¡ršg + + gcommªd_Çme +[( +Commªd +:: +MAX +)] = { + +56 +Lev– + + gscÝe +[( +Commªd +:: +MAX +)] = { + +57 +Lev– +:: +Row +, Lev–:: +Bªk +, Lev–:: +Rªk +, + +58 +Lev– +:: +CÞumn +, Level::Column, + +59 +Lev– +:: +Rªk +, Level::Rank, Level::Rank, Level::Rank, Level::Rank, + +60 +Lev– +:: +Row +, Lev–:: +Bªk +, Lev–:: +Rªk +, + +61 +Lev– +:: +CÞumn +, + +62 +Lev– +:: +Row +, Lev–:: +Bªk +, Lev–:: +Rªk + + +65 +boÞ + +is_Ý’šg +( +Commªd + +cmd +) + +67 ( + gcmd +)) { + +68 ( + gCommªd +:: +ACT +): + +69 ( +Commªd +:: +ACTF +): + +70 ( +Commªd +:: +ACTM +): + +71  +Œue +; + +73  +çl£ +; + +77 +boÞ + +is_acûssšg +( +Commªd + +cmd +) + +79 ( + gcmd +)) { + +80 ( + gCommªd +:: +RD +): + +81 ( +Commªd +:: +WR +): + +82 ( +Commªd +:: +MIG +): + +83  +Œue +; + +85  +çl£ +; + +89 +boÞ + +is_þosšg +( +Commªd + +cmd +) + +91 ( + gcmd +)) { + +92 ( + gCommªd +:: +PRE +): + +93 ( +Commªd +:: +PREF +): + +94 ( +Commªd +:: +PREM +): + +95 ( +Commªd +:: +PREA +): + +96 ( +Commªd +:: +PREAF +): + +97 ( +Commªd +:: +PREAM +): + +98  +Œue +; + +100  +çl£ +; + +104 +boÞ + +is_»äeshšg +( +Commªd + +cmd +) + +106 ( + gcmd +)) { + +107 ( + gCommªd +:: +REF +): + +108  +Œue +; + +110  +çl£ +; + +116 þas  + cS‹ + :  + +118 +O³Ãd +, + gClo£d +, + gPow”Up +, + gAùPow”Down +, + gP»Pow”Down +, + gS–fReäesh +, + gMAX + + +119 } + g¡¬t +[( +Lev– +:: +MAX +)] = { + +120 +S‹ +:: +MAX +, S‹:: +Pow”Up +, S‹:: +Clo£d +, State::Closed, State::MAX + +124 +Commªd + + gŒª¦©e +[( +Reque¡ +:: +Ty³ +:: +MAX +)] = { + +125 +Commªd +:: +RD +, Commªd:: +WR +, + +126 +Commªd +:: +REF +, Commªd:: +PDE +, Commªd:: +SRE +, + +127 +Commªd +:: +MIG + + +131 + gfunùiÚ +< +Commªd +( +DRAM +< +TLDRAM +>*, Commªd +cmd +, )> + g´”eq +[( +Lev– +:: +MAX +)][(Command::MAX)]; + +135 + gfunùiÚ +< +boÞ +( +DRAM +< +TLDRAM +>*, +Commªd + +cmd +, )> + growh™ +[( +Lev– +:: +MAX +)][(Command::MAX)]; + +136 + gfunùiÚ +< +boÞ +( +DRAM +< +TLDRAM +>*, +Commªd + +cmd +, )> + growÝ’ +[( +Lev– +:: +MAX +)][(Command::MAX)]; + +139  + sTimšgEÁry + + +141 +Commªd + + gcmd +; + +142  + gdi¡ +; + +143  + gv® +; + +144 +boÞ + + gsiblšg +; + +146 + gveùÜ +< + gTimšgEÁry +> + gtimšg +[( +Lev– +:: +MAX +)][( +Commªd +::MAX)]; + +149 + gfunùiÚ +<( + gDRAM +< + gTLDRAM +>*, )> + gÏmbda +[( +Lev– +:: +MAX +)][( +Commªd +::MAX)]; + +152 þas  + cOrg + :  + +154 +TLDRAM_512Mb_x4 +, + gTLDRAM_512Mb_x8 +, + gTLDRAM_512Mb_x16 +, + +155 + gTLDRAM_1Gb_x4 +, + gTLDRAM_1Gb_x8 +, + gTLDRAM_1Gb_x16 +, + +156 + gTLDRAM_2Gb_x4 +, + gTLDRAM_2Gb_x8 +, + gTLDRAM_2Gb_x16 +, + +157 + gTLDRAM_4Gb_x4 +, + gTLDRAM_4Gb_x8 +, + gTLDRAM_4Gb_x16 +, + +158 + gTLDRAM_8Gb_x4 +, + gTLDRAM_8Gb_x8 +, + gTLDRAM_8Gb_x16 +, + +159 + gMAX + + +162  + sOrgEÁry + { + +163  + gsize +; + +164  + gdq +; + +165  + gcouÁ +[( +Lev– +:: +MAX +)]; + +166 } + gÜg_bË +[( +Org +:: +MAX +)] = { + +182 }, + gÜg_’Œy +; + +184  +£t_chªÃl_numb” +( +chªÃl +); + +185  +£t_¿nk_numb” +( +¿nk +); + +188 þas  + cS³ed + :  + +190 +TLDRAM_800D +, + gTLDRAM_800E +, + +191 + gTLDRAM_1066E +, + gTLDRAM_1066F +, + gTLDRAM_1066G +, + +192 + gTLDRAM_1333G +, + gTLDRAM_1333H +, + +193 + gTLDRAM_1600H +, + gTLDRAM_1600J +, + gTLDRAM_1600K +, + +194 + gTLDRAM_1866K +, + gTLDRAM_1866L +, + +195 + gTLDRAM_2133L +, + gTLDRAM_2133M +, + +196 + gMAX + + +199  + g´eãtch_size + = 8; + +200  + gchªÃl_width + = 64; + +202  + sS³edEÁry + { + +203  + g¿‹ +; + +204  + gäeq +, + gtCK +; + +205  + gnBL +, + gnCCD +, + gnRTRS +; + +206  + gnCL +, + gnRCD +, + gnRP +, + gnCWL +; + +207  + gnRAS +, + gnRC +; + +208  + gnRTP +, + gnWTR +, + gnWR +; + +209  + gnRRD +, + gnFAW +; + +210  + gnRFC +, + gnREFI +; + +211  + gnPD +, + gnXP +, + gnXPDLL +; + +212  + gnCKESR +, + gnXS +, + gnXSDLL +; + +213  + gnRCDF +, + gnRPF +, + gnRASF +, + gnRCF +; + +214  + gnRCDM +, + gnRPM +, + gnRASM +, + gnRCM +; + +215 } + g¥“d_bË +[( +S³ed +:: +MAX +)] = { + +244 }, + g¥“d_’Œy +; + +246  + g»ad_Ï‹ncy +; + +248 + g´iv©e +: + +249  +š™_¥“d +(); + +250  +š™_Ïmbda +(); + +251  +š™_´”eq +(); + +252  +š™_rowh™ +(); + +253  +š™_rowÝ’ +(); + +254  +š™_timšg +(); + + @WideIO.cpp + +1  + ~"WideIO.h +" + +2  + ~"DRAM.h +" + +3  + ~ + +4  + ~ + +5  + ~<ÿs£¹ +> + +7 +usšg + +Çme¥aû + + g¡d +; + +8 +usšg + +Çme¥aû + + g¿muÏtÜ +; + +10 +¡ršg + + gWideIO +:: +¡ªd¬d_Çme + = "WideIO"; + +12 + gm­ +< + g¡ršg +, + gWideIO +:: +Org +> +WideIO +:: +Üg_m­ + = { + +13 {"WideIO_1Gb", +WideIO +:: +Org +:: +WideIO_1Gb +}, + +14 {"WideIO_2Gb", +WideIO +:: +Org +:: +WideIO_2Gb +}, + +15 {"WideIO_4Gb", +WideIO +:: +Org +:: +WideIO_4Gb +}, + +16 {"WideIO_8Gb", +WideIO +:: +Org +:: +WideIO_8Gb +}, + +19 + gm­ +< + g¡ršg +, + gWideIO +:: +S³ed +> +WideIO +:: +¥“d_m­ + = { + +20 {"WideIO_200", +WideIO +:: +S³ed +:: +WideIO_200 +}, + +21 {"WideIO_266", +WideIO +:: +S³ed +:: +WideIO_266 +}, + +24 + gWideIO +:: + $WideIO +( +Org + +Üg +, +S³ed + +¥“d +) : + +25 + `Üg_’Œy +( +Üg_bË +[( +Üg +)]), + +26 + `¥“d_’Œy +( +¥“d_bË +[( +¥“d +)]), + +27 + `»ad_Ï‹ncy +( +¥“d_’Œy +. +nCL + + s³ed_’Œy. +nDQSCK + + s³ed_’Œy. +nBL +) + +29 + `š™_¥“d +(); + +30 + `š™_´”eq +(); + +31 + `š™_rowh™ +(); + +32 + `š™_rowÝ’ +(); + +33 + `š™_Ïmbda +(); + +34 + `š™_timšg +(); + +35 + } +} + +37 + gWideIO +:: + $WideIO +(cÚ¡ +¡ršg +& +Üg_¡r +, cÚ¡ sŒšg& +¥“d_¡r +) : + +38 + $WideIO +( +Üg_m­ +[ +Üg_¡r +], +¥“d_m­ +[ +¥“d_¡r +]) + +40 + } +} + +42  + gWideIO +:: + $£t_chªÃl_numb” +( +chªÃl +) { + +43 + `as£¹ +(( +chªÃl + == 4) && "The Wide I/O interface supports 4…hysical‡nd 4†ogical channels."); + +44 +Üg_’Œy +. +couÁ +[( +Lev– +:: +ChªÃl +)] = +chªÃl +; + +45 + } +} + +47  + gWideIO +:: + $£t_¿nk_numb” +( +¿nk +) { + +48 + `as£¹ +(( +¿nk + == 1) && "WideIO„ank‚umber is fixedo 1."); + +49 +Üg_’Œy +. +couÁ +[( +Lev– +:: +Rªk +)] = +¿nk +; + +50 + } +} + +52  + gWideIO +:: + $š™_¥“d +() + +54 cÚ¡  +RFC_TABLE +[( +S³ed +:: +MAX +)][( +Org +::MAX)] = { + +58 cÚ¡  +REFI_TABLE +[( +S³ed +:: +MAX +)][( +Org +::MAX)] = { + +62  +¥“d + = 0, +d’s™y + = 0; + +63  +¥“d_’Œy +. +¿‹ +){ + +64 200: +¥“d + = 0; ; + +65 266: +¥“d + = 1; ; + +66 : + `as£¹ +( +çl£ +); + +68  +Üg_’Œy +. +size + >> 8){ + +69 1: +d’s™y + = 0; ; + +70 2: +d’s™y + = 1; ; + +71 4: +d’s™y + = 2; ; + +72 8: +d’s™y + = 3; ; + +73 : + `as£¹ +( +çl£ +); + +75 +¥“d_’Œy +. +nRFC + = +RFC_TABLE +[ +¥“d +][ +d’s™y +]; + +76 +¥“d_’Œy +. +nREFI + = +REFI_TABLE +[ +¥“d +][ +d’s™y +]; + +77 + } +} + +80  + gWideIO +:: + $š™_´”eq +() + +83 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +WideIO +>* +node +, Commªd +cmd +,  +id +) { + +84 ( +node +-> +¡©e +)) { + +85 ( +S‹ +:: +Pow”Up +):  +Commªd +:: +MAX +; + +86 ( +S‹ +:: +AùPow”Down +):  +Commªd +:: +PDX +; + +87 ( +S‹ +:: +P»Pow”Down +):  +Commªd +:: +PDX +; + +88 ( +S‹ +:: +S–fReäesh +):  +Commªd +:: +SREFX +; + +89 : + `as£¹ +( +çl£ +); + +91 +´”eq +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +WideIO +>* +node +, Commªd +cmd +,  +id +) { + +92 ( +node +-> +¡©e +)) { + +93 ( +S‹ +:: +Clo£d +):  +Commªd +:: +ACT +; + +94 ( +S‹ +:: +O³Ãd +): + +95 ià( +node +-> +row_¡©e +. + `fšd +( +id +è!ðnode->row_¡©e. + `’d +()) + +96  +cmd +; + +97  +Commªd +:: +PRE +; + +98 : + `as£¹ +( +çl£ +); + +102 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +WR +)] =…»»q[(Lev–::Rªk)][(Commªd:: +RD +)]; + +103 +´”eq +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] =…»»q[(Lev–::Bªk)][(Commªd:: +RD +)]; + +106 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +REF +)] = [] ( +DRAM +< +WideIO +>* +node +, Commªd +cmd +,  +id +) { + +107 autØ +bªk + : +node +-> +chžd»n +) { + +108 ià( +bªk +-> +¡©e + =ð +S‹ +:: +Clo£d +) + +110  +Commªd +:: +PRA +; + +112  +Commªd +:: +REF +;}; + +115 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PD +)] = [] ( +DRAM +< +WideIO +>* +node +, Commªd +cmd +,  +id +) { + +116 ( +node +-> +¡©e +)) { + +117 ( +S‹ +:: +Pow”Up +):  +Commªd +:: +PD +; + +118 ( +S‹ +:: +AùPow”Down +):  +Commªd +:: +PD +; + +119 ( +S‹ +:: +P»Pow”Down +):  +Commªd +:: +PD +; + +120 ( +S‹ +:: +S–fReäesh +):  +Commªd +:: +SREFX +; + +121 : + `as£¹ +( +çl£ +); + +125 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +SREF +)] = [] ( +DRAM +< +WideIO +>* +node +, Commªd +cmd +,  +id +) { + +126 ( +node +-> +¡©e +)) { + +127 ( +S‹ +:: +Pow”Up +):  +Commªd +:: +SREF +; + +128 ( +S‹ +:: +AùPow”Down +):  +Commªd +:: +PDX +; + +129 ( +S‹ +:: +P»Pow”Down +):  +Commªd +:: +PDX +; + +130 ( +S‹ +:: +S–fReäesh +):  +Commªd +:: +SREF +; + +131 : + `as£¹ +( +çl£ +); + +133 + } +} + +136  + gWideIO +:: + $š™_rowh™ +() + +139 +rowh™ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +WideIO +>* +node +, Commªd +cmd +,  +id +) { + +140 ( +node +-> +¡©e +)) { + +141 ( +S‹ +:: +Clo£d +):  +çl£ +; + +142 ( +S‹ +:: +O³Ãd +): + +143 ià( +node +-> +row_¡©e +. + `fšd +( +id +è!ðnode->row_¡©e. + `’d +()) + +144  +Œue +; + +145  +çl£ +; + +146 : + `as£¹ +( +çl£ +); + +150 +rowh™ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] =„owh™[(Lev–::Bªk)][(Commªd:: +RD +)]; + +151 + } +} + +153  + gWideIO +:: + $š™_rowÝ’ +() + +156 +rowÝ’ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +WideIO +>* +node +, Commªd +cmd +,  +id +) { + +157 ( +node +-> +¡©e +)) { + +158 ( +S‹ +:: +Clo£d +):  +çl£ +; + +159 ( +S‹ +:: +O³Ãd +):  +Œue +; + +160 : + `as£¹ +( +çl£ +); + +164 +rowÝ’ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] =„owÝ’[(Lev–::Bªk)][(Commªd:: +RD +)]; + +165 + } +} + +167  + gWideIO +:: + $š™_Ïmbda +() + +169 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +ACT +)] = [] ( +DRAM +< +WideIO +>* +node +,  +id +) { + +170 +node +-> +¡©e + = +S‹ +:: +O³Ãd +; + +171 +node +-> +row_¡©e +[ +id +] = +S‹ +:: +O³Ãd +;}; + +172 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +PRE +)] = [] ( +DRAM +< +WideIO +>* +node +,  +id +) { + +173 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +174 +node +-> +row_¡©e +. + `þ—r +();}; + +175 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PRA +)] = [] ( +DRAM +< +WideIO +>* +node +,  +id +) { + +176 autØ +bªk + : +node +-> +chžd»n +) { + +177 +bªk +-> +¡©e + = +S‹ +:: +Clo£d +; + +178 +bªk +-> +row_¡©e +. + `þ—r +();}}; + +179 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +REF +)] = [] ( +DRAM +< +WideIO +>* +node +,  +id +) {}; + +180 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +WideIO +>* +node +,  +id +) {}; + +181 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] = [] ( +DRAM +< +WideIO +>* +node +,  +id +) {}; + +182 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RDA +)] = [] ( +DRAM +< +WideIO +>* +node +,  +id +) { + +183 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +184 +node +-> +row_¡©e +. + `þ—r +();}; + +185 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WRA +)] = [] ( +DRAM +< +WideIO +>* +node +,  +id +) { + +186 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +187 +node +-> +row_¡©e +. + `þ—r +();}; + +188 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PD +)] = [] ( +DRAM +< +WideIO +>* +node +,  +id +) { + +189 autØ +bªk + : +node +-> +chžd»n +) { + +190 ià( +bªk +-> +¡©e + =ð +S‹ +:: +Clo£d +) + +192 +node +-> +¡©e + = +S‹ +:: +AùPow”Down +; + +195 +node +-> +¡©e + = +S‹ +:: +P»Pow”Down +;}; + +196 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PDX +)] = [] ( +DRAM +< +WideIO +>* +node +,  +id +) { + +197 +node +-> +¡©e + = +S‹ +:: +Pow”Up +;}; + +198 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +SREF +)] = [] ( +DRAM +< +WideIO +>* +node +,  +id +) { + +199 +node +-> +¡©e + = +S‹ +:: +S–fReäesh +;}; + +200 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +SREFX +)] = [] ( +DRAM +< +WideIO +>* +node +,  +id +) { + +201 +node +-> +¡©e + = +S‹ +:: +Pow”Up +;}; + +202 + } +} + +205  + gWideIO +:: + $š™_timšg +() + +207 +S³edEÁry +& +s + = +¥“d_’Œy +; + +208 +veùÜ +< +TimšgEÁry +> * +t +; + +211 +t + = +timšg +[( +Lev– +:: +ChªÃl +)]; + +214 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nBL +}); + +215 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nBL +}); + +216 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nBL +}); + +217 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd::RDA, 1, +s +. +nBL +}); + +218 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd::WR, 1, +s +. +nBL +}); + +219 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nBL +}); + +220 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nBL +}); + +221 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd::WRA, 1, +s +. +nBL +}); + +225 +t + = +timšg +[( +Lev– +:: +Rªk +)]; + +228 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nCCD +}); + +229 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCCD +}); + +230 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCCD +}); + +231 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd::RDA, 1, +s +. +nCCD +}); + +232 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd::WR, 1, +s +. +nCCD +}); + +233 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCCD +}); + +234 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCCD +}); + +235 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd::WRA, 1, +s +. +nCCD +}); + +236 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nRTW +}); + +237 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nRTW +}); + +238 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nRTW +}); + +239 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nRTW +}); + +240 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTR +}); + +241 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTR +}); + +242 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTR +}); + +243 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nWTR +}); + +246 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PRA +, 1, +s +. +nRTP +}); + +247 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PRA +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +}); + +250 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PD +, 1, +s +. +nCL + + s. +nBL + + 1}); + +251 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +PD +, 1, +s +. +nCL + + s. +nBL + + 1}); + +252 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PD +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +}); + +253 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +PD +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR + + 1}); + +254 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nXP +}); + +255 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nXP +}); + +256 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nXP +}); + +257 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nXP +}); + +262 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 1, +s +. +nRRD +}); + +263 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 2, +s +. +nTAW +}); + +264 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PRA +, 1, +s +. +nRAS +}); + +265 +t +[( +Commªd +:: +PRA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRP +}); + +268 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nRP +}); + +269 +t +[( +Commªd +:: +PRA +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nRP +}); + +270 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRFC +}); + +273 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PD +, 1, 1}); + +274 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nXP +}); + +275 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nXP +}); + +276 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PRA +, 1, +s +. +nXP +}); + +279 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +SREF +, 1, +s +. +nRP +}); + +280 +t +[( +Commªd +:: +PRA +)]. + `push_back +({Commªd:: +SREF +, 1, +s +. +nRP +}); + +281 +t +[( +Commªd +:: +SREFX +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nXSR +}); + +284 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd::REF, 1, +s +. +nRFC +}); + +287 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd:: +PD +, 1, 1}); + +288 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nXP +}); + +291 +t +[( +Commªd +:: +SREFX +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nXSR +}); + +294 +t +[( +Commªd +:: +PD +)]. + `push_back +({Commªd:: +PDX +, 1, +s +. +nCKE +}); + +295 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PD +, 1, +s +. +nXP +}); + +298 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +SREF +, 1, +s +. +nXP +}); + +299 +t +[( +Commªd +:: +SREFX +)]. + `push_back +({Commªd:: +PD +, 1, +s +. +nXSR +}); + +302 +t +[( +Commªd +:: +SREF +)]. + `push_back +({Commªd:: +SREFX +, 1, +s +. +nCKESR +}); + +303 +t +[( +Commªd +:: +SREFX +)]. + `push_back +({Commªd:: +SREF +, 1, +s +. +nXSR +}); + +307 +t + = +timšg +[( +Lev– +:: +Bªk +)]; + +310 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nRCD +}); + +311 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nRCD +}); + +312 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nRCD +}); + +313 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nRCD +}); + +315 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nRTP +}); + +316 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR +}); + +318 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRTP + + s. +nRP +}); + +319 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nCWL + + s. +nBL + + s. +nWR + + s. +nRP +}); + +322 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 1, +s +. +nRC +}); + +323 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nRAS +}); + +324 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRP +}); + +325 + } +} + + @WideIO.h + +1 #iâdeà +__WIDEIO_H + + +2  + #__WIDEIO_H + + + ) + +4  + ~"DRAM.h +" + +5  + ~"Reque¡.h +" + +6  + ~ + +7  + ~ + +9 +usšg + +Çme¥aû + + g¡d +; + +11 +Çme¥aû + + g¿muÏtÜ + + +14 þas  + cWideIO + + +16 + gpublic +: + +17  +¡ršg + +¡ªd¬d_Çme +; + +18 +þass + + gOrg +; + +19 +þass + + gS³ed +; + +20 +WideIO +( +Org + +Üg +, +S³ed + +¥“d +); + +21 +WideIO +(cÚ¡ +¡ršg +& +Üg_¡r +, cÚ¡ sŒšg& +¥“d_¡r +); + +23  + gm­ +< + g¡ršg +, + gOrg +> + gÜg_m­ +; + +24  + gm­ +< + g¡ršg +, + gS³ed +> + g¥“d_m­ +; + +27 þas  + cLev– + :  + +29 +ChªÃl +, + gRªk +, + gBªk +, + gRow +, + gCÞumn +, + gMAX + + +33 þas  + cCommªd + :  + +35 +ACT +, + gPRE +, + gPRA +, + +36 + gRD +, + gWR +, + gRDA +, + gWRA +, + +37 + gREF +, + gPD +, + gPDX +, + gSREF +, + gSREFX +, + +38 + gMAX + + +41 +¡ršg + + gcommªd_Çme +[( +Commªd +:: +MAX +)] = { + +47 +Lev– + + gscÝe +[( +Commªd +:: +MAX +)] = { + +48 +Lev– +:: +Row +, Lev–:: +Bªk +, Lev–:: +Rªk +, + +49 +Lev– +:: +CÞumn +, Level::Column, Level::Column, Level::Column, + +50 +Lev– +:: +Rªk +, Level::Rank, Level::Rank, Level::Rank, Level::Rank + +53 +boÞ + +is_Ý’šg +( +Commªd + +cmd +) + +55 ( + gcmd +)) { + +56 ( + gCommªd +:: +ACT +): + +57  +Œue +; + +59  +çl£ +; + +63 +boÞ + +is_acûssšg +( +Commªd + +cmd +) + +65 ( + gcmd +)) { + +66 ( + gCommªd +:: +RD +): + +67 ( +Commªd +:: +WR +): + +68 ( +Commªd +:: +RDA +): + +69 ( +Commªd +:: +WRA +): + +70  +Œue +; + +72  +çl£ +; + +76 +boÞ + +is_þosšg +( +Commªd + +cmd +) + +78 ( + gcmd +)) { + +79 ( + gCommªd +:: +RDA +): + +80 ( +Commªd +:: +WRA +): + +81 ( +Commªd +:: +PRE +): + +82 ( +Commªd +:: +PRA +): + +83  +Œue +; + +85  +çl£ +; + +89 +boÞ + +is_»äeshšg +( +Commªd + +cmd +) + +91 ( + gcmd +)) { + +92 ( + gCommªd +:: +REF +): + +93  +Œue +; + +95  +çl£ +; + +101 þas  + cS‹ + :  + +103 +O³Ãd +, + gClo£d +, + gPow”Up +, + gAùPow”Down +, + gP»Pow”Down +, + gS–fReäesh +, + gMAX + + +104 } + g¡¬t +[( +Lev– +:: +MAX +)] = { + +105 +S‹ +:: +MAX +, S‹:: +Pow”Up +, S‹:: +Clo£d +, State::Closed, State::MAX + +109 +Commªd + + gŒª¦©e +[( +Reque¡ +:: +Ty³ +:: +MAX +)] = { + +110 +Commªd +:: +RD +, Commªd:: +WR +, + +111 +Commªd +:: +REF +, Commªd:: +PD +, Commªd:: +SREF + + +115 + gfunùiÚ +< +Commªd +( +DRAM +< +WideIO +>*, Commªd +cmd +, )> + g´”eq +[( +Lev– +:: +MAX +)][(Command::MAX)]; + +119 + gfunùiÚ +< +boÞ +( +DRAM +< +WideIO +>*, +Commªd + +cmd +, )> + growh™ +[( +Lev– +:: +MAX +)][(Command::MAX)]; + +120 + gfunùiÚ +< +boÞ +( +DRAM +< +WideIO +>*, +Commªd + +cmd +, )> + growÝ’ +[( +Lev– +:: +MAX +)][(Command::MAX)]; + +124  + sTimšgEÁry + + +126 +Commªd + + gcmd +; + +127  + gdi¡ +; + +128  + gv® +; + +129 +boÞ + + gsiblšg +; + +131 + gveùÜ +< + gTimšgEÁry +> + gtimšg +[( +Lev– +:: +MAX +)][( +Commªd +::MAX)]; + +134 + gfunùiÚ +<( + gDRAM +< + gWideIO +>*, )> + gÏmbda +[( +Lev– +:: +MAX +)][( +Commªd +::MAX)]; + +137 þas  + cOrg + :  + +139 +WideIO_1Gb +, + +140 + gWideIO_2Gb +, + +141 + gWideIO_4Gb +, + +142 + gWideIO_8Gb +, + +143 + gMAX + + +146  + sOrgEÁry + { + +147  + gsize +; + +148  + gdq +; + +149  + gcouÁ +[( +Lev– +:: +MAX +)]; + +150 } + gÜg_bË +[( +Org +:: +MAX +)] = { + +156 }, + gÜg_’Œy +; + +158  +£t_chªÃl_numb” +( +chªÃl +); + +159  +£t_¿nk_numb” +( +¿nk +); + +162 þas  + cS³ed + :  + +164 +WideIO_200 +, + +165 + gWideIO_266 +, + +166 + gMAX + + +169  + g´eãtch_size + = 4; + +170  + gchªÃl_width + = 128; + +172  + sS³edEÁry + { + +173  + g¿‹ +; + +174  + gäeq +, + gtCK +; + +175  + gnBL +, + gnCCD +, + gnDQSCK +; + +176  + gnCL +, + gnRCD +, + gnRP +, + gnCWL +; + +177  + gnRAS +, + gnRC +; + +178  + gnRTP +, + gnRTW +, + gnWTR +, + gnWR +; + +179  + gnRRD +, + gnTAW +; + +180  + gnRFC +, + gnREFI +; + +181  + gnCKE +, + gnXP +; + +182  + gnCKESR +, + gnXSR +; + +183 } + g¥“d_bË +[( +S³ed +:: +MAX +)] = { + +186 }, + g¥“d_’Œy +; + +188  + g»ad_Ï‹ncy +; + +190 + g´iv©e +: + +191  +š™_¥“d +(); + +192  +š™_Ïmbda +(); + +193  +š™_´”eq +(); + +194  +š™_rowh™ +(); + +195  +š™_rowÝ’ +(); + +196  +š™_timšg +(); + + @WideIO2.cpp + +1  + ~"WideIO2.h +" + +2  + ~"DRAM.h +" + +3  + ~ + +4  + ~ + +5  + ~<ÿs£¹ +> + +7 +usšg + +Çme¥aû + + g¡d +; + +8 +usšg + +Çme¥aû + + g¿muÏtÜ +; + +10 +¡ršg + + gWideIO2 +:: +¡ªd¬d_Çme + = "WideIO2"; + +12 + gm­ +< + g¡ršg +, + gWideIO2 +:: +Org +> +WideIO2 +:: +Üg_m­ + = { + +13 {"WideIO2_8Gb", +WideIO2 +:: +Org +:: +WideIO2_8Gb +}, + +16 + gm­ +< + g¡ršg +, + gWideIO2 +:: +S³ed +> +WideIO2 +:: +¥“d_m­ + = { + +17 {"WideIO2_800", +WideIO2 +:: +S³ed +:: +WideIO2_800 +}, + +18 {"WideIO2_1066", +WideIO2 +:: +S³ed +:: +WideIO2_1066 +}, + +21 + gWideIO2 +:: + $WideIO2 +( +Org + +Üg +, +S³ed + +¥“d +,  +chªÃls +) : + +22 + `¥“d_’Œy +( +¥“d_bË +[( +¥“d +)]), + +23 + `»ad_Ï‹ncy +( +¥“d_’Œy +. +nCL + + s³ed_’Œy. +nDQSCK + + s³ed_’Œy. +nBL +) + +25 ( +Üg +)){ + +26 ( +Org +:: +WideIO2_8Gb +): + +27 +Üg_’Œy +. +size + = (8<<10è/ +chªÃls +; + +28 +Üg_’Œy +. +dq + = 64; + +29 ià( +chªÃls + == 4) { + +30 +Üg_’Œy +. +size + = 2<<10; + +31 +Üg_’Œy +. +couÁ +[( +Lev– +:: +ChªÃl +)] = +chªÃls +; + +32 +Üg_’Œy +. +couÁ +[( +Lev– +:: +Rªk +)] = 0; + +33 +Üg_’Œy +. +couÁ +[( +Lev– +:: +Bªk +)] = 8; + +34 +Üg_’Œy +. +couÁ +[( +Lev– +:: +Row +)] = 1<<13; + +35 +Üg_’Œy +. +couÁ +[( +Lev– +:: +CÞumn +)] = 1<<9; + +36 } ià( +chªÃls + == 8) { + +37 +Üg_’Œy +. +size + = 1<<10; + +38 +Üg_’Œy +. +couÁ +[( +Lev– +:: +ChªÃl +)] = +chªÃls +; + +39 +Üg_’Œy +. +couÁ +[( +Lev– +:: +Rªk +)] = 0; + +40 +Üg_’Œy +. +couÁ +[( +Lev– +:: +Bªk +)] = 4; + +41 +Üg_’Œy +. +couÁ +[( +Lev– +:: +Row +)] = 1<<14; + +42 +Üg_’Œy +. +couÁ +[( +Lev– +:: +CÞumn +)] = 1<<8; + +43 } + `as£¹ +( +çl£ + && "The WideIO2 interface supports 4 or 8…hysical channels."); + +45 : + `as£¹ +( +çl£ +); + +47 +¥“d_’Œy +. +nRPab + = ( +chªÃls + =ð4)? s³ed_’Œy. +nRP8b +: s³ed_’Œy. +nRPpb +; + +48 + `š™_´”eq +(); + +49 + `š™_rowh™ +(); + +50 + `š™_Ïmbda +(); + +51 + `š™_timšg +(); + +52 + } +} + +54 + gWideIO2 +:: + $WideIO2 +(cÚ¡ +¡ršg +& +Üg_¡r +, cÚ¡ sŒšg& +¥“d_¡r +,  +chªÃls +) : + +55 + $WideIO2 +( +Üg_m­ +[ +Üg_¡r +], +¥“d_m­ +[ +¥“d_¡r +], +chªÃls +) + +57 + } +} + +59  + gWideIO2 +:: + $£t_chªÃl_numb” +( +chªÃl +) { + +60 + `as£¹ +(( +chªÃl + =ð +Üg_’Œy +. +couÁ +[( +Lev– +:: +ChªÃl +)]) && "channel‚umber must be consistent with spec initializaiton configuration."); + +61 +Üg_’Œy +. +couÁ +[( +Lev– +:: +ChªÃl +)] = +chªÃl +; + +62 + } +} + +64  + gWideIO2 +:: + $£t_¿nk_numb” +( +¿nk +) { + +65 + `as£¹ +((( +¿nk + == 1) || (rank == 2)) && "WideIO2 supports single‡nd dual„ank configurations."); + +66 +Üg_’Œy +. +couÁ +[( +Lev– +:: +Rªk +)] = +¿nk +; + +67 + } +} + +69  + gWideIO2 +:: + $š™_´”eq +() + +72 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +WideIO2 +>* +node +, Commªd +cmd +,  +id +) { + +73 ( +node +-> +¡©e +)) { + +74 ( +S‹ +:: +Pow”Up +):  +Commªd +:: +MAX +; + +75 ( +S‹ +:: +AùPow”Down +):  +Commªd +:: +PDX +; + +76 ( +S‹ +:: +P»Pow”Down +):  +Commªd +:: +PDX +; + +77 ( +S‹ +:: +S–fReäesh +):  +Commªd +:: +SREFX +; + +78 : + `as£¹ +( +çl£ +); + +80 +´”eq +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +WideIO2 +>* +node +, Commªd +cmd +,  +id +) { + +81 ( +node +-> +¡©e +)) { + +82 ( +S‹ +:: +Clo£d +):  +Commªd +:: +ACT +; + +83 ( +S‹ +:: +O³Ãd +): + +84 ià( +node +-> +row_¡©e +. + `fšd +( +id +è!ðnode->row_¡©e. + `’d +()) + +85  +cmd +; + +86  +Commªd +:: +PRE +; + +87 : + `as£¹ +( +çl£ +); + +90 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +WR +)] =…»»q[(Lev–::Rªk)][(Commªd:: +RD +)]; + +91 +´”eq +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] =…»»q[(Lev–::Bªk)][(Commªd:: +RD +)]; + +93 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +REF +)] = [] ( +DRAM +< +WideIO2 +>* +node +, Commªd +cmd +,  +id +) { + +94 autØ +bªk + : +node +-> +chžd»n +) { + +95 ià( +bªk +-> +¡©e + =ð +S‹ +:: +Clo£d +) + +97  +Commªd +:: +PRA +; + +99  +Commªd +:: +REF +;}; + +101 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PD +)] = [] ( +DRAM +< +WideIO2 +>* +node +, Commªd +cmd +,  +id +) { + +102 ( +node +-> +¡©e +)) { + +103 ( +S‹ +:: +Pow”Up +):  +Commªd +:: +PD +; + +104 ( +S‹ +:: +AùPow”Down +):  +Commªd +:: +PD +; + +105 ( +S‹ +:: +P»Pow”Down +):  +Commªd +:: +PD +; + +106 ( +S‹ +:: +S–fReäesh +):  +Commªd +:: +SREFX +; + +107 : + `as£¹ +( +çl£ +); + +110 +´”eq +[( +Lev– +:: +Rªk +)][( +Commªd +:: +SREF +)] = [] ( +DRAM +< +WideIO2 +>* +node +, Commªd +cmd +,  +id +) { + +111 ( +node +-> +¡©e +)) { + +112 ( +S‹ +:: +Pow”Up +):  +Commªd +:: +SREF +; + +113 ( +S‹ +:: +AùPow”Down +):  +Commªd +:: +PDX +; + +114 ( +S‹ +:: +P»Pow”Down +):  +Commªd +:: +PDX +; + +115 ( +S‹ +:: +S–fReäesh +):  +Commªd +:: +SREF +; + +116 : + `as£¹ +( +çl£ +); + +118 + } +} + +121  + gWideIO2 +:: + $š™_rowh™ +() + +124 +rowh™ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +WideIO2 +>* +node +, Commªd +cmd +,  +id +) { + +125 ( +node +-> +¡©e +)) { + +126 ( +S‹ +:: +Clo£d +):  +çl£ +; + +127 ( +S‹ +:: +O³Ãd +): + +128 ià( +node +-> +row_¡©e +. + `fšd +( +id +è!ðnode->row_¡©e. + `’d +()) + +129  +Œue +; + +130  +çl£ +; + +131 : + `as£¹ +( +çl£ +); + +135 +rowh™ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] =„owh™[(Lev–::Bªk)][(Commªd:: +RD +)]; + +136 + } +} + +138  + gWideIO2 +:: + $š™_rowÝ’ +() + +141 +rowÝ’ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RD +)] = [] ( +DRAM +< +WideIO2 +>* +node +, Commªd +cmd +,  +id +) { + +142 ( +node +-> +¡©e +)) { + +143 ( +S‹ +:: +Clo£d +):  +çl£ +; + +144 ( +S‹ +:: +O³Ãd +):  +Œue +; + +145 : + `as£¹ +( +çl£ +); + +149 +rowÝ’ +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WR +)] =„owÝ’[(Lev–::Bªk)][(Commªd:: +RD +)]; + +150 + } +} + +152  + gWideIO2 +:: + $š™_Ïmbda +() + +154 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +ACT +)] = [] ( +DRAM +< +WideIO2 +>* +node +,  +id +) { + +155 +node +-> +¡©e + = +S‹ +:: +O³Ãd +; + +156 +node +-> +row_¡©e +[ +id +] = +S‹ +:: +O³Ãd +;}; + +157 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +PRE +)] = [] ( +DRAM +< +WideIO2 +>* +node +,  +id +) { + +158 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +159 +node +-> +row_¡©e +. + `þ—r +();}; + +160 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PRA +)] = [] ( +DRAM +< +WideIO2 +>* +node +,  +id +) { + +161 autØ +bªk + : +node +-> +chžd»n +) { + +162 +bªk +-> +¡©e + = +S‹ +:: +Clo£d +; + +163 +bªk +-> +row_¡©e +. + `þ—r +();}}; + +164 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +RDA +)] = [] ( +DRAM +< +WideIO2 +>* +node +,  +id +) { + +165 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +166 +node +-> +row_¡©e +. + `þ—r +();}; + +167 +Ïmbda +[( +Lev– +:: +Bªk +)][( +Commªd +:: +WRA +)] = [] ( +DRAM +< +WideIO2 +>* +node +,  +id +) { + +168 +node +-> +¡©e + = +S‹ +:: +Clo£d +; + +169 +node +-> +row_¡©e +. + `þ—r +();}; + +170 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PD +)] = [] ( +DRAM +< +WideIO2 +>* +node +,  +id +) { + +171 autØ +bªk + : +node +-> +chžd»n +) { + +172 ià( +bªk +-> +¡©e + =ð +S‹ +:: +Clo£d +) + +174 +node +-> +¡©e + = +S‹ +:: +AùPow”Down +; + +177 +node +-> +¡©e + = +S‹ +:: +P»Pow”Down +;}; + +178 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +PDX +)] = [] ( +DRAM +< +WideIO2 +>* +node +,  +id +) { + +179 +node +-> +¡©e + = +S‹ +:: +Pow”Up +;}; + +180 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +SREF +)] = [] ( +DRAM +< +WideIO2 +>* +node +,  +id +) { + +181 +node +-> +¡©e + = +S‹ +:: +S–fReäesh +;}; + +182 +Ïmbda +[( +Lev– +:: +Rªk +)][( +Commªd +:: +SREFX +)] = [] ( +DRAM +< +WideIO2 +>* +node +,  +id +) { + +183 +node +-> +¡©e + = +S‹ +:: +Pow”Up +;}; + +184 + } +} + +187  + gWideIO2 +:: + $š™_timšg +() + +189 +S³edEÁry +& +s + = +¥“d_’Œy +; + +190 +veùÜ +< +TimšgEÁry +> * +t +; + +193 +t + = +timšg +[( +Lev– +:: +ChªÃl +)]; + +196 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nBL +}); + +197 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nBL +}); + +198 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nBL +}); + +199 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd::RDA, 1, +s +. +nBL +}); + +200 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd::WR, 1, +s +. +nBL +}); + +201 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nBL +}); + +202 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nBL +}); + +203 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd::WRA, 1, +s +. +nBL +}); + +207 +t + = +timšg +[( +Lev– +:: +Rªk +)]; + +210 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nCCD +}); + +211 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCCD +}); + +212 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCCD +}); + +213 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd::RDA, 1, +s +. +nCCD +}); + +214 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd::WR, 1, +s +. +nCCD +}); + +215 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCCD +}); + +216 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCCD +}); + +217 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd::WRA, 1, +s +. +nCCD +}); + +218 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nDQSCK + + s. +nBL + + 1 - s. +nCWL +}); + +219 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCL + + s. +nDQSCK + + s. +nBL + + 1 - s. +nCWL +}); + +220 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nDQSCK + + s. +nBL + + 1 - s. +nCWL +}); + +221 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCL + + s. +nDQSCK + + s. +nBL + + 1 - s. +nCWL +}); + +222 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + 1 + s. +nBL + + s. +nWTR +}); + +223 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + 1 + s. +nBL + + s. +nWTR +}); + +224 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + 1 + s. +nBL + + s. +nWTR +}); + +225 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + 1 + s. +nBL + + s. +nWTR +}); + +228 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd::RD, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +229 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +230 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +231 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd::RDA, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +232 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +233 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +234 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +235 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nBL + + s. +nRTRS +, +Œue +}); + +236 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nBL + + s. +nDQSCK + + 1 + s. +nRTRS + - s. +nCWL +, +Œue +}); + +237 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCL + + s. +nBL + + s. +nDQSCK + + 1 + s. +nRTRS + - s. +nCWL +, +Œue +}); + +238 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nCL + + s. +nBL + + s. +nDQSCK + + 1 + s. +nRTRS + - s. +nCWL +, +Œue +}); + +239 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nCL + + s. +nBL + + s. +nDQSCK + + 1 + s. +nRTRS + - s. +nCWL +, +Œue +}); + +240 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nRTRS + - s. +nCL +, +Œue +}); + +241 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nRTRS + - s. +nCL +, +Œue +}); + +242 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nCWL + + s. +nBL + + s. +nRTRS + - s. +nCL +, +Œue +}); + +243 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nCWL + + s. +nBL + + s. +nRTRS + - s. +nCL +, +Œue +}); + +246 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PRA +, 1, +s +. +nRTP +}); + +247 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PRA +, 1, +s +. +nCWL + + 1 + s. +nBL + + s. +nWR +}); + +250 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PD +, 1, +s +. +nCL + + s. +nDQSCK + + s. +nBL + + 1}); + +251 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +PD +, 1, +s +. +nCL + + s. +nDQSCK + + s. +nBL + + 1}); + +252 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PD +, 1, +s +. +nCWL + + 1 + s. +nBL + + s. +nWR +}); + +253 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +PD +, 1, +s +. +nCWL + + 1 + s. +nBL + + s. +nWR + + 1}); + +254 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nXP +}); + +255 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nXP +}); + +256 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nXP +}); + +257 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nXP +}); + +262 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 1, +s +. +nRRD +}); + +263 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 4, +s +. +nFAW +}); + +264 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PRA +, 1, +s +. +nRAS +}); + +265 +t +[( +Commªd +:: +PRA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRPab +}); + +268 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nRPpb +}); + +269 +t +[( +Commªd +:: +PRA +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nRPab +}); + +270 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRFCab +}); + +273 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PD +, 1, 1}); + +274 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nXP +}); + +275 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nXP +}); + +276 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PRA +, 1, +s +. +nXP +}); + +279 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +SREF +, 1, +s +. +nRPpb +}); + +280 +t +[( +Commªd +:: +PRA +)]. + `push_back +({Commªd:: +SREF +, 1, +s +. +nRPab +}); + +281 +t +[( +Commªd +:: +SREFX +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nXSR +}); + +284 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd::REF, 1, +s +. +nRFCab +}); + +285 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd:: +REFPB +, 1, +s +. +nRFCab +}); + +286 +t +[( +Commªd +:: +REFPB +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nRFCpb +}); + +289 +t +[( +Commªd +:: +REF +)]. + `push_back +({Commªd:: +PD +, 1, 1}); + +290 +t +[( +Commªd +:: +REFPB +)]. + `push_back +({Commªd:: +PD +, 1, 1}); + +291 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nXP +}); + +292 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +REFPB +, 1, +s +. +nXP +}); + +295 +t +[( +Commªd +:: +SREFX +)]. + `push_back +({Commªd:: +REF +, 1, +s +. +nXSR +}); + +296 +t +[( +Commªd +:: +SREFX +)]. + `push_back +({Commªd:: +REFPB +, 1, +s +. +nXSR +}); + +299 +t +[( +Commªd +:: +PD +)]. + `push_back +({Commªd:: +PDX +, 1, +s +. +nCKE +}); + +300 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +PD +, 1, +s +. +nXP +}); + +303 +t +[( +Commªd +:: +PDX +)]. + `push_back +({Commªd:: +SREF +, 1, +s +. +nXP +}); + +304 +t +[( +Commªd +:: +SREFX +)]. + `push_back +({Commªd:: +PD +, 1, +s +. +nXSR +}); + +307 +t +[( +Commªd +:: +SREF +)]. + `push_back +({Commªd:: +SREFX +, 1, +s +. +nCKESR +}); + +308 +t +[( +Commªd +:: +SREFX +)]. + `push_back +({Commªd:: +SREF +, 1, +s +. +nXSR +}); + +311 +t + = +timšg +[( +Lev– +:: +Bªk +)]; + +314 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +RD +, 1, +s +. +nRCD +}); + +315 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +RDA +, 1, +s +. +nRCD +}); + +316 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +WR +, 1, +s +. +nRCD +}); + +317 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +WRA +, 1, +s +. +nRCD +}); + +319 +t +[( +Commªd +:: +RD +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nRTP +}); + +320 +t +[( +Commªd +:: +WR +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nCWL + + 1 + s. +nBL + + s. +nWR +}); + +322 +t +[( +Commªd +:: +RDA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRTP + + s. +nRPpb +}); + +323 +t +[( +Commªd +:: +WRA +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nCWL + + 1 + s. +nBL + + s. +nWR + + s. +nRPpb +}); + +326 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd::ACT, 1, +s +. +nRC +}); + +327 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +PRE +, 1, +s +. +nRAS +}); + +328 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRPpb +}); + +329 +t +[( +Commªd +:: +PRE +)]. + `push_back +({Commªd:: +REFPB +, 1, +s +. +nRPpb +}); + +332 +t +[( +Commªd +:: +ACT +)]. + `push_back +({Commªd:: +REFPB +, 1, +s +. +nRRD +, +Œue +}); + +333 +t +[( +Commªd +:: +REFPB +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRRD +, +Œue +}); + +336 +t +[( +Commªd +:: +REFPB +)]. + `push_back +({Commªd::REFPB, 1, +s +. +nRFCpb +}); + +337 +t +[( +Commªd +:: +REFPB +)]. + `push_back +({Commªd:: +ACT +, 1, +s +. +nRFCpb +}); + +338 + } +} + + @WideIO2.h + +1 #iâdeà +__WIDEIO2_H + + +2  + #__WIDEIO2_H + + + ) + +4  + ~"DRAM.h +" + +5  + ~"Reque¡.h +" + +6  + ~ + +7  + ~ + +9 +usšg + +Çme¥aû + + g¡d +; + +11 +Çme¥aû + + g¿muÏtÜ + + +14 þas  + cWideIO2 + + +16 + gpublic +: + +17  +¡ršg + +¡ªd¬d_Çme +; + +18 +þass + + gOrg +; + +19 +þass + + gS³ed +; + +20 +WideIO2 +( +Org + +Üg +, +S³ed + +¥“d +,  +chªÃls + = 4); + +21 +WideIO2 +(cÚ¡ +¡ršg +& +Üg_¡r +, cÚ¡ sŒšg& +¥“d_¡r +,  +chªÃls + = 4); + +23  + gm­ +< + g¡ršg +, + gOrg +> + gÜg_m­ +; + +24  + gm­ +< + g¡ršg +, + gS³ed +> + g¥“d_m­ +; + +27 þas  + cLev– + :  + +29 +ChªÃl +, + gRªk +, + gBªk +, + gRow +, + gCÞumn +, + gMAX + + +33 þas  + cCommªd + :  + +35 +ACT +, + gPRE +, + gPRA +, + +36 + gRD +, + gWR +, + gRDA +, + gWRA +, + +37 + gREF +, + gREFPB +, + gPD +, + gPDX +, + gSREF +, + gSREFX +, + +38 + gMAX + + +41 +¡ršg + + gcommªd_Çme +[( +Commªd +:: +MAX +)] = { + +47 +Lev– + + gscÝe +[( +Commªd +:: +MAX +)] = { + +48 +Lev– +:: +Row +, Lev–:: +Bªk +, Lev–:: +Rªk +, + +49 +Lev– +:: +CÞumn +, Level::Column, Level::Column, Level::Column, + +50 +Lev– +:: +Rªk +, Lev–:: +Bªk +, Level::Rank, Level::Rank, Level::Rank, Level::Rank + +53 +boÞ + +is_Ý’šg +( +Commªd + +cmd +) + +55 ( + gcmd +)) { + +56 ( + gCommªd +:: +ACT +): + +57  +Œue +; + +59  +çl£ +; + +63 +boÞ + +is_acûssšg +( +Commªd + +cmd +) + +65 ( + gcmd +)) { + +66 ( + gCommªd +:: +RD +): + +67 ( +Commªd +:: +WR +): + +68 ( +Commªd +:: +RDA +): + +69 ( +Commªd +:: +WRA +): + +70  +Œue +; + +72  +çl£ +; + +76 +boÞ + +is_þosšg +( +Commªd + +cmd +) + +78 ( + gcmd +)) { + +79 ( + gCommªd +:: +RDA +): + +80 ( +Commªd +:: +WRA +): + +81 ( +Commªd +:: +PRE +): + +82 ( +Commªd +:: +PRA +): + +83  +Œue +; + +85  +çl£ +; + +89 +boÞ + +is_»äeshšg +( +Commªd + +cmd +) + +91 ( + gcmd +)) { + +92 ( + gCommªd +:: +REF +): + +93 ( +Commªd +:: +REFPB +): + +94  +Œue +; + +96  +çl£ +; + +102 þas  + cS‹ + :  + +104 +O³Ãd +, + gClo£d +, + gPow”Up +, + gAùPow”Down +, + gP»Pow”Down +, + gS–fReäesh +, + gMAX + + +105 } + g¡¬t +[( +Lev– +:: +MAX +)] = { + +106 +S‹ +:: +MAX +, S‹:: +Pow”Up +, S‹:: +Clo£d +, State::Closed, State::MAX + +110 +Commªd + + gŒª¦©e +[( +Reque¡ +:: +Ty³ +:: +MAX +)] = { + +111 +Commªd +:: +RD +, Commªd:: +WR +, + +112 +Commªd +:: +REF +, Commªd:: +PD +, Commªd:: +SREF + + +116 + gfunùiÚ +< +Commªd +( +DRAM +< +WideIO2 +>*, Commªd +cmd +, )> + g´”eq +[( +Lev– +:: +MAX +)][(Command::MAX)]; + +120 + gfunùiÚ +< +boÞ +( +DRAM +< +WideIO2 +>*, +Commªd + +cmd +, )> + growh™ +[( +Lev– +:: +MAX +)][(Command::MAX)]; + +121 + gfunùiÚ +< +boÞ +( +DRAM +< +WideIO2 +>*, +Commªd + +cmd +, )> + growÝ’ +[( +Lev– +:: +MAX +)][(Command::MAX)]; + +124  + sTimšgEÁry + + +126 +Commªd + + gcmd +; + +127  + gdi¡ +; + +128  + gv® +; + +129 +boÞ + + gsiblšg +; + +131 + gveùÜ +< + gTimšgEÁry +> + gtimšg +[( +Lev– +:: +MAX +)][( +Commªd +::MAX)]; + +134 + gfunùiÚ +<( + gDRAM +< + gWideIO2 +>*, )> + gÏmbda +[( +Lev– +:: +MAX +)][( +Commªd +::MAX)]; + +137 þas  + cOrg + :  + +140 +WideIO2_8Gb +, + +145 + gMAX + + +148  + sOrgEÁry + { + +149  + gsize +; + +150  + gdq +; + +151  + gcouÁ +[( +Lev– +:: +MAX +)]; + +152 } + gÜg_’Œy +; + +154  +£t_chªÃl_numb” +( +chªÃl +); + +155  +£t_¿nk_numb” +( +¿nk +); + +158 þas  + cS³ed + :  + +160 +WideIO2_800 +, + +161 + gWideIO2_1066 +, + +162 + gMAX + + +166  + g´eãtch_size + = 4; + +167  + gchªÃl_width + = 64; + +169  + sS³edEÁry + { + +170  + g¿‹ +; + +171  + gäeq +, + gtCK +; + +172  + gnBL +, + gnCCD +, + gnDQSCK +, + gnRTRS +; + +173  + gnCL +, + gnRCD +, + gnRPpb +, + gnRP8b +, + gnRPab +, + gnCWL +; + +174  + gnRAS +, + gnRC +; + +175  + gnRTP +, + gnWTR +, + gnWR +; + +176  + gnRRD +, + gnFAW +; + +177  + gnRFCab +, + gnRFCpb +, + gnREFI +; + +178  + gnCKE +, + gnXP +; + +179  + gnCKESR +, + gnXSR +; + +180 } + g¥“d_bË +[( +S³ed +:: +MAX +)] = { + +183 }, + g¥“d_’Œy +; + +185  + g»ad_Ï‹ncy +; + +187 + g´iv©e +: + +188  +š™_Ïmbda +(); + +189  +š™_´”eq +(); + +190  +š™_rowh™ +(); + +191  +š™_rowÝ’ +(); + +192  +š™_timšg +(); + + @common.cpp + +1  + ~"commÚ.h +" + +3 + g¡d +:: +o¡»am +& +Ý”©Ü +<< ( +¡d +::o¡»am & +os +, cÚ¡ + g¿muÏtÜ +:: +Reque¡ +:: +Ty³ + & +ty³ +){ + +5  +ty³ +){ + +6  +¿muÏtÜ +:: +Reque¡ +:: +Ty³ +:: +READ +: + +7 +os + << "READ"; + +9  + g¿muÏtÜ +:: +Reque¡ +:: +Ty³ +:: +WRITE +: + +10 +os + << "WRITE"; + +12  + g¿muÏtÜ +:: +Reque¡ +:: +Ty³ +:: +REFRESH +: + +13 +os + << "REFRESH"; + +15  + g¿muÏtÜ +:: +Reque¡ +:: +Ty³ +:: +POWERDOWN +: + +16 +os + << "POWERDOWN"; + +18  + g¿muÏtÜ +:: +Reque¡ +:: +Ty³ +:: +SELFREFRESH +: + +19 +os + << "SELFREFRESH"; + +21  + g¿muÏtÜ +:: +Reque¡ +:: +Ty³ +:: +EXTENSION +: + +22 +os + << "EXTENSION"; + +24  + g¿muÏtÜ +:: +Reque¡ +:: +Ty³ +:: +MAX +: + +25 +os + << "MAX"; + +28 +os + << "Unknown Type"; + +32  + gos +; + +35 + g¡d +:: +o¡»am +& +Ý”©Ü +<<( +¡d +::o¡»am & +os +, cÚ¡ + gMemOp + & + gÝ +){ + +37 + gos + << "v®id: " << + gÝ +. + gv®id + << " "; + +38 + gos + << "ty³: " << + gÝ +. + gty³ + << " "; + +39 + gos + << "³Idx: " << + gÝ +. + g³Idx + << " "; + +40 + gos + << "addr: " << + gÝ +. + gaddr + << " "; + +41 + gos + << "ÝIdx: " << + gÝ +. + gÝIdx + << " "; + +42 + gos + << "Ëngth: " << + gÝ +. + gËngth + << " "; + +43 + gos + << "»qNum: " << + gÝ +. + g»qNum + << " "; + +44 + gos + << "d•¬tPeTime: " << + gÝ +. + gd•¬tPeTime + << " "; + +45 + gos + << "¬riveMemTime: " << + gÝ +. + g¬riveMemTime + << " "; + +46 + gos + << "d•¬tMemTime: " << + gÝ +. + gd•¬tMemTime + << " "; + +47 + gos + << "¬rivePeTime: " << + gÝ +. + g¬rivePeTime + << " "; + +49  + gos +; + +52 + gMemOp +:: + $MemOp +( +¿muÏtÜ +:: +Reque¡ +:: +Ty³ + +_ty³ +, + +53  +_³Idx +,  +_addr +, + +54  +_Ëngth +,  +_ÝIdx +) + +56 +v®id + = +Œue +; + +57 +ty³ + = +_ty³ +; + +58 +³Idx + = +_³Idx +; + +59 +addr + = +_addr +; + +60 +ÝIdx + = +_ÝIdx +; + +61 +Ëngth + = +_Ëngth +; + +62 +»qNum + = ( +_Ëngth ++64-1)/64; + +63 +d•¬tPeTime + = 0; + +64 +¬riveMemTime + = 0; + +65 +d•¬tMemTime + = 0; + +66 +¬rivePeTime + = 0; + +67 + } +} + +70 + gMemOp +:: + $MemOp +( +boÞ + +_v®id +){ + +71 +v®id + = +_v®id +; + +72 +ty³ + = +¿muÏtÜ +:: +Reque¡ +:: +Ty³ +:: +READ +; + +73 +³Idx + = 0; + +74 +addr + = 0; + +75 +ÝIdx + = 0; + +76 +Ëngth + = 0; + +77 +»qNum + = 0; + +78 +d•¬tPeTime + = 0; + +79 +¬riveMemTime + = 0; + +80 +d•¬tMemTime + = 0; + +81 +¬rivePeTime + = 0; + +82 + } +} + +85  + gMemOp +:: + $cÝyToReq +( +¿muÏtÜ +:: +Reque¡ + & +»q +){ + +86 +»q +. +ty³ + =ype; + +87 +»q +. +³Idx + =…eIdx; + +88 +»q +. +addr + =‡ddr; + +89 +»q +. +ÝIdx + = opIdx; + +90 +»q +. +Ëngth + =†ength; + +91 +»q +. +»qNum + =„eqNum; + +92 +»q +. +d•¬tPeTime + = departPeTime; + +93 +»q +. +¬riveMemTime + =‡rriveMemTime; + +94 +»q +. +d•¬tMemTime + = departMemTime; + +95 +»q +. +¬rivePeTime + =‡rrivePeTime; + +96 + } +} + +99  + gMemOp +:: + $MemOpUpd©e +(cÚ¡ +¿muÏtÜ +:: +Reque¡ + & +»q +){ + +100 +v®id + = +Œue +; + +101 +ty³ + = +»q +.type; + +102 +³Idx + = +»q +.peIdx; + +103 +addr + = +»q +.addr; + +104 +ÝIdx + = +»q +.opIdx; + +105 +Ëngth + = +»q +.length; + +106 +»qNum + = +»q +.reqNum; + +107 +d•¬tPeTime + = +»q +.departPeTime; + +108 +¬riveMemTime + = +»q +.arriveMemTime; + +109 +d•¬tMemTime + = +»q +.departMemTime; + +110 +¬rivePeTime + = 0; + +111 + } +} + +113 + gMemOp +::~ + $MemOp +(){ + } +} + +115 +MemOp +& MemOp:: +Ý”©Ü +=(cÚ¡ MemO°& +Ý +){ + +117 +v®id + = +Ý +.valid; + +118 + gty³ + = +Ý +. +ty³ +; + +119 + g³Idx + = +Ý +. +³Idx +; + +120 + gaddr + = +Ý +. +addr +; + +121 + gÝIdx + = +Ý +. +ÝIdx +; + +122 + gËngth + = +Ý +. +Ëngth +; + +123 + g»qNum + = +Ý +. +»qNum +; + +124 + gd•¬tPeTime + = +Ý +. +d•¬tPeTime +; + +125 + g¬riveMemTime + = +Ý +. +¬riveMemTime +; + +126 + gd•¬tMemTime + = +Ý +. +d•¬tMemTime +; + +127 + g¬rivePeTime + = +Ý +. +¬rivePeTime +; + +129  * + gthis +; + +133 +boÞ + + gMemOp +:: +Ý”©Ü +==(cÚ¡ +MemOp + & +Ý +) const{ + +135 +boÞ + +equ® + = +Œue +;; + +136 + gequ® + &ð( +v®id + =ð +Ý +.valid); + +137 + gequ® + &ð( +ty³ + =ð +Ý +.type); + +138 + gequ® + &ð( +³Idx + =ð +Ý +.peIdx); + +139 + gequ® + &ð( +addr + =ð +Ý +.addr); + +140 + gequ® + &ð( +ÝIdx + =ð +Ý +.opIdx); + +141 + gequ® + &ð( +Ëngth + =ð +Ý +.length); + +142 + gequ® + &ð( +»qNum + =ð +Ý +.reqNum); + +143 + gequ® + &ð( +d•¬tPeTime + =ð +Ý +.departPeTime); + +144 + gequ® + &ð( +¬riveMemTime + =ð +Ý +.arriveMemTime); + +145 + gequ® + &ð( +d•¬tMemTime + =ð +Ý +.departMemTime); + +146 + gequ® + &ð( +¬rivePeTime + =ð +Ý +.arrivePeTime); + +148  + gequ® +; + +152  + gMemOp +:: + $£tD•¬tPeTime +( +d•¬tTime +){ + +153 +d•¬tPeTime + = +d•¬tTime +; + +154 + } +} + +156  + gMemOp +:: + $£tA¼ivePeTime +( +¬riveTime +){ + +157 +¬rivePeTime + = +¬riveTime +; + +158 + } +} + +160  + gMemOp +:: + $£tD•¬tMemTime +( +d•¬tTime +){ + +161 +d•¬tMemTime + = +d•¬tTime +; + +162 + } +} + +164  + gMemOp +:: + $£tA¼iveMemTime +( +¬riveTime +){ + +165 +¬riveMemTime + = +¬riveTime +; + +166 + } +} + +168  + $sc_Œaû +( +sc_Œaû_fže + * +tf +, cÚ¡ +MemOp + & +Ý +, cÚ¡ +¡d +:: +¡ršg + & +Çme +){ + +170 + `sc_Œaû +( +tf +, +Ý +. +v®id +, +Çme ++".valid"); + +172 + `sc_Œaû +( +tf +, +Ý +. +³Idx +, +Çme ++".peIdx"); + +173 + `sc_Œaû +( +tf +, +Ý +. +addr +, +Çme ++".addr"); + +174 + `sc_Œaû +( +tf +, +Ý +. +ÝIdx +, +Çme ++".opIdx"); + +175 + `sc_Œaû +( +tf +, +Ý +. +Ëngth +, +Çme ++".length"); + +176 + `sc_Œaû +( +tf +, +Ý +. +»qNum +, +Çme ++".reqNum"); + +177 + `sc_Œaû +( +tf +, +Ý +. +d•¬tPeTime +, +Çme ++".departPeTime"); + +178 + `sc_Œaû +( +tf +, +Ý +. +¬riveMemTime +, +Çme ++".arriveMemTime"); + +179 + `sc_Œaû +( +tf +, +Ý +. +d•¬tMemTime +, +Çme ++".departMemTime"); + +180 + `sc_Œaû +( +tf +, +Ý +. +¬rivePeTime +, +Çme ++".arrivePeTime"); + +182 + } +} + + @common.h + +1 #iâdeà +__COMMON_H__ + + +2  + #__COMMON_H__ + + + ) + +4  + ~ + +5  + ~"Reque¡.h +" + +6  + ~"sy¡emc.h +" + +8 + g¡d +:: +o¡»am +& +Ý”©Ü +<< ( +¡d +::o¡»am & +os +, cÚ¡ + g¿muÏtÜ +:: +Reque¡ +:: +Ty³ + & +ty³ +); + +10  + sMemOp + { + +12 + mpublic +: + +13 +boÞ + +v®id +; + +14  + m³Idx +; + +15 + m¿muÏtÜ +:: +Reque¡ +:: +Ty³ + +ty³ +; + +16  + maddr +; + +17  + mÝIdx +; + +18  + mËngth +; + +20  + md•¬tPeTime +; + +21  + m¬riveMemTime +; + +22  + md•¬tMemTime +; + +23  + m¬rivePeTime +; + +28  + m»qNum +; + +30 +MemOp +( +¿muÏtÜ +:: +Reque¡ +:: +Ty³ + +_ty³ +, + +31  +_³Idx +,  +_addr +, + +32  +_Ëngth +,  +_ÝIdx +); + +35 +MemOp +( +boÞ + +_v®id + = +çl£ +); + +36  +cÝyToReq +( +¿muÏtÜ +:: +Reque¡ + & +»q +); + +39  +MemOpUpd©e +(cÚ¡ +¿muÏtÜ +:: +Reque¡ + & +»q +); + +40  +£tD•¬tPeTime +( +d•¬tTime +); + +41  +£tA¼ivePeTime +( +¬riveTime +); + +42  +£tD•¬tMemTime +( +d•¬tTime +); + +43  +£tA¼iveMemTime +( +¬riveTime +); + +45 ~ +MemOp +(); + +47 + mMemOp +& + mÝ”©Ü +=(cÚ¡ +MemOp + & +Ý +); + +48 +boÞ + + mÝ”©Ü +==(cÚ¡ +MemOp + & +Ý +) const; + +49 +ä›nd +  +sc_Œaû +( +sc_Œaû_fže + * +tf +, cÚ¡ +MemOp + & +Ý +, cÚ¡ +¡d +:: +¡ršg + & +Çme +); + +50 +ä›nd + + m¡d +:: +o¡»am +& +Ý”©Ü +<<( +¡d +::o¡»am & +os +, cÚ¡ + mMemOp + & + mÝ +); + + @pe.cpp + +1  + ~"³.h +" + +3  + g³ +:: +ÝIdx + = 0; + +5  + g³ +:: + $g‘OpIdx +(){ + +6  +tmp + = +ÝIdx +; + +7 +ÝIdx +++; + +8  +tmp +; + +9 + } +} + +11  + g³ +:: + $š™ +(){ + +13 +tÙ®R—dReq + = 0; + +14  +addr + = 0; + +15 +¿muÏtÜ +:: +Reque¡ +:: +Ty³ + +ty³ +; + +21  +i + = 0; i < +ÝNum +; i++){ + +22 if( +i +%2 == 0){ + +23 +ty³ + = +¿muÏtÜ +:: +Reque¡ +:: +Ty³ +:: +READ +; + +24 +tÙ®R—dReq +++; + +27 +ty³ + = +¿muÏtÜ +:: +Reque¡ +:: +Ty³ +:: +WRITE +; + +30  +Ëngth + = 64; + +31 +MemOp + + `»qOp +( +ty³ +, +³Idx +, +addr +, +Ëngth +, + `g‘OpIdx +()); + +32 +addr + =‡dd¸+ +Ëngth +; + +33 +memReqQueue +. + `push_back +( +»qOp +); + +36 if(() +memReqQueue +. + `size +(è=ð +ÝNum +){ + +37 +¡d +:: +cout + << +ÝNum + << " memÜy„eque¡ havb“Àg’”©ed." << std:: +’dl +; + +39 + } +} + +41 + g³ +:: + $³ +( +sc_moduË_Çme + +_Çme +,  +_³Idx +,  +_ÝNum +è: + $sc_moduË +( +_Çme +) { + +43 +³Idx + = +_³Idx +; + +44 +ÝNum + = +_ÝNum +; + +45 +³ClkCyþe + = 10; + +47 + `š™ +(); + +50 + `SC_THREAD +( +£ndMemReq +); + +51 + `SC_THREAD +( +g‘MemRe¥ +); + +53 + } +} + +61  + g³ +:: + $£ndMemReq +(){ + +62  +Œue +){ + +63 if(! +memReqQueue +. + `em±y +()){ + +64 +MemOp + +tmpOp + = +memReqQueue +. + `äÚt +(); + +67  +d•¬tTime + = (è( + `sc_time_¡amp +()/ + `sc_time +(1, +SC_NS +)); + +68 +tmpOp +. + `£tD•¬tPeTime +( +d•¬tTime +); + +70 +memReq +. + `wr™e +( +tmpOp +); + +71 +memReqQueue +. + `pÝ_äÚt +(); + +74 +MemOp + + `tmpOp +( +çl£ +); + +75 +memReq +. + `wr™e +( +tmpOp +); + +78 + `wa™ +( +³ClkCyþe +, +SC_NS +); + +80 + } +} + +82  + g³ +:: + $g‘MemRe¥ +(){ + +83  +Œue +){ + +84 +MemOp + +tmpOp + = +memRe¥ +. + `»ad +(); + +85 if( +tmpOp +. +v®id +){ + +88  +¬riveTime + = ()( + `sc_time_¡amp +()/ + `sc_time +(1, +SC_NS +)); + +89 +tmpOp +. + `£tA¼ivePeTime +( +¬riveTime +); + +90 +memRe¥Queue +. + `push_back +( +tmpOp +); + +92 if(() +memRe¥Queue +. + `size +(è=ð +tÙ®R—dReq +){ + +93 +¡d +:: +cout + << "AÎh»ad„eque¡ havb“À»ûived." << std:: +’dl +; + +94 +¡d +:: +cout + << "End oàthsimuÏtiÚ‡ˆ" << + `sc_time_¡amp +(è<< std:: +’dl +; + +95 + `dumpRe¥ +(); + +96 + `sc_¡Ý +(); + +99 + `wa™ +( +³ClkCyþe +, +SC_NS +); + +101 + } +} + +103  + g³ +:: + $£tOpNum +( +_ÝNum +){ + +104 +ÝNum + = +_ÝNum +; + +105 + } +} + +107  + g³ +:: + $£tPeClkCyþe +( +_³ClkCyþe +){ + +108 +³ClkCyþe + = +_³ClkCyþe +; + +109 + } +} + +111  + g³ +:: + $dumpRe¥ +(){ + +112 +¡d +:: +li¡ +< +MemOp +>:: +™”©Ü + +™ +; + +113 autØ +™ + = +memRe¥Queue +. + `begš +(); iˆ!ðmemRe¥Queue. + `’d +(); it++){ + +114 +¡d +:: +cout + << (* +™ +è<< std:: +’dl +; + +116 + } +} + + @pe.h + +1 #iâdeà +__PE_H__ + + +2  + #__PE_H__ + + + ) + +4  + ~ + +5  + ~ + +6  + ~<™”©Ü +> + +7  + ~"Reque¡.h +" + +8  + ~"commÚ.h +" + +9  + ~"sy¡emc.h +" + +11 þas  + c³ + : +public + +sc_moduË +{ + +13 +SC_HAS_PROCESS +( +³ +); + +15 + mpublic +: + +16 +sc_out + < +MemOp +> +memReq +; + +17 + msc_š + < + mMemOp +> + mmemRe¥ +; + +19  + mÝNum +; + +20  + m³Idx +; + +21  + mtÙ®R—dReq +; + +23  +£tOpNum +( +_ÝNum +); + +24  +£tPeClkCyþe +( +_³ClkCyþe +); + +25  +dumpRe¥ +(); + +26 +³ +( +sc_moduË_Çme + +_Çme +,  +_³Idx + = 0,  +_ÝNum + = 10); + +28  +£ndMemReq +(); + +29  +g‘MemRe¥ +(); + +31 ~ + $³ +(){}; + +33 +´iv©e +: + +34  +³ClkCyþe +; + +37 +¡d +:: +li¡ +< +MemOp +> +memReqQueue +; + +38 +¡d +:: +li¡ +< +MemOp +> +memRe¥Queue +; + +40  +ÝIdx +; + +41  + `g‘OpIdx +(); + +42  + `š™ +(); + +43 + } +}; + + @/usr/include/ctype.h + +22 #iâdef +_CTYPE_H + + +23  + #_CTYPE_H + 1 + + ) + +25  + ~<ã©u»s.h +> + +26  + ~ + +28 + g__BEGIN_DECLS + + +30 #iâdeà +_ISb™ + + +39  + ~<’dŸn.h +> + +40 #ià +__BYTE_ORDER + =ð +__BIG_ENDIAN + + +41  + #_ISb™ +( +b™ +è(1 << (b™)) + + ) + +43  + #_ISb™ +( +b™ +è((b™è< 8 ? ((1 << (b™)è<< 8è: ((1 << (b™)è>> 8)) + + ) + +48 + m_ISuµ” + = +_ISb™ + (0), + +49 + m_ISlow” + = +_ISb™ + (1), + +50 + m_IS®pha + = +_ISb™ + (2), + +51 + m_ISdig™ + = +_ISb™ + (3), + +52 + m_ISxdig™ + = +_ISb™ + (4), + +53 + m_IS¥aû + = +_ISb™ + (5), + +54 + m_IS´št + = +_ISb™ + (6), + +55 + m_ISg¿ph + = +_ISb™ + (7), + +56 + m_ISbÏnk + = +_ISb™ + (8), + +57 + m_ISúŒl + = +_ISb™ + (9), + +58 + m_ISpunù + = +_ISb™ + (10), + +59 + m_IS®num + = +_ISb™ + (11) + +79 cÚ¡ ** + $__ùy³_b_loc + () + +80 +__THROW + + `__©Œibu‹__ + (( +__cÚ¡__ +)); + +81 cÚ¡ +__št32_t + ** + $__ùy³_tÞow”_loc + () + +82 +__THROW + + `__©Œibu‹__ + (( +__cÚ¡__ +)); + +83 cÚ¡ +__št32_t + ** + $__ùy³_touµ”_loc + () + +84 +__THROW + + `__©Œibu‹__ + (( +__cÚ¡__ +)); + +87 #iâdeà +__ýlu¥lus + + +88  + #__isùy³ +( +c +, +ty³ +) \ + +89 ((* + `__ùy³_b_loc + ())[(è( +c +)] & (è +ty³ +) + + ) + +90 #–ià +defšed + +__USE_EXTERN_INLINES + + +91  + #__isùy³_f +( +ty³ +) \ + +92 +__ex‹º_šlše + \ + +93 +is +## + `ty³ + ( +__c +è +__THROW + \ + +95  (* + `__ùy³_b_loc + ())[(è( +__c +)] & (è +_IS +## +ty³ +; \ + +96 + } + + ) +} + +99  + #__i§scii +( +c +è(((cè& ~0x7fè=ð0è + + ) + +100  + #__tßscii +( +c +è((cè& 0x7fè + + ) + +102  + #__exùy³ +( +Çme +è  + `Çme + (è +__THROW + + + ) + +104 +__BEGIN_NAMESPACE_STD + + +110 +__exùy³ + ( +i§Êum +); + +111 +__exùy³ + ( +i§Íha +); + +112 +__exùy³ + ( +isúŒl +); + +113 +__exùy³ + ( +isdig™ +); + +114 +__exùy³ + ( +i¦ow” +); + +115 +__exùy³ + ( +isg¿ph +); + +116 +__exùy³ + ( +i¥ršt +); + +117 +__exùy³ + ( +i¥unù +); + +118 +__exùy³ + ( +is¥aû +); + +119 +__exùy³ + ( +isuµ” +); + +120 +__exùy³ + ( +isxdig™ +); + +124  + $tÞow” + ( +__c +è +__THROW +; + +127  + $touµ” + ( +__c +è +__THROW +; + +129 +__END_NAMESPACE_STD + + +133 #ifdef +__USE_ISOC99 + + +134 +__BEGIN_NAMESPACE_C99 + + +136 + `__exùy³ + ( +isbÏnk +); + +138 +__END_NAMESPACE_C99 + + +141 #ifdeà +__USE_GNU + + +143  + $isùy³ + ( +__c +,  +__mask +è +__THROW +; + +146 #ià +defšed + +__USE_MISC + || defšed +__USE_XOPEN + + +150  + $i§scii + ( +__c +è +__THROW +; + +154  + $tßscii + ( +__c +è +__THROW +; + +158 + `__exùy³ + ( +_touµ” +); + +159 + `__exùy³ + ( +_tÞow” +); + +163  + #__tobody +( +c +, +f +, +a +, +¬gs +) \ + +164 ( +__ex‹nsiÚ__ + \ + +165 ({  +__»s +; \ + +166 ià( ( +c +) > 1) \ + +168 ià( + `__bužtš_cÚ¡ªt_p + ( +c +)) \ + +170  +__c + = ( +c +); \ + +171 +__»s + = +__c + < -128 || __ø> 255 ? __ø: ( +a +)[__c]; \ + +174 +__»s + = +f + +¬gs +; \ + +177 +__»s + = ( +a +)[(è( +c +)]; \ + +178 +__»s +; + } +})) + + ) + +180 #ià! +defšed + +__NO_CTYPE + + +181 #ifdeà +__isùy³_f + + +182 + $__isùy³_f + ( +®num +) + +183 + $__isùy³_f + ( +®pha +) + +184 + $__isùy³_f + ( +úŒl +) + +185 + $__isùy³_f + ( +dig™ +) + +186 + $__isùy³_f + ( +low” +) + +187 + $__isùy³_f + ( +g¿ph +) + +188 + $__isùy³_f + ( +´št +) + +189 + $__isùy³_f + ( +punù +) + +190 + $__isùy³_f + ( +¥aû +) + +191 + $__isùy³_f + ( +uµ” +) + +192 + $__isùy³_f + ( +xdig™ +) + +193 #ifdeà +__USE_ISOC99 + + +194 + $__isùy³_f + ( +bÏnk +) + +196 #–ià +defšed + +__isùy³ + + +197  + #i§Êum +( +c +è + `__isùy³ +((c), +_IS®num +) + + ) + +198  + #i§Íha +( +c +è + `__isùy³ +((c), +_IS®pha +) + + ) + +199  + #isúŒl +( +c +è + `__isùy³ +((c), +_ISúŒl +) + + ) + +200  + #isdig™ +( +c +è + `__isùy³ +((c), +_ISdig™ +) + + ) + +201  + #i¦ow” +( +c +è + `__isùy³ +((c), +_ISlow” +) + + ) + +202  + #isg¿ph +( +c +è + `__isùy³ +((c), +_ISg¿ph +) + + ) + +203  + #i¥ršt +( +c +è + `__isùy³ +((c), +_IS´št +) + + ) + +204  + #i¥unù +( +c +è + `__isùy³ +((c), +_ISpunù +) + + ) + +205  + #is¥aû +( +c +è + `__isùy³ +((c), +_IS¥aû +) + + ) + +206  + #isuµ” +( +c +è + `__isùy³ +((c), +_ISuµ” +) + + ) + +207  + #isxdig™ +( +c +è + `__isùy³ +((c), +_ISxdig™ +) + + ) + +208 #ifdeà +__USE_ISOC99 + + +209  + #isbÏnk +( +c +è + `__isùy³ +((c), +_ISbÏnk +) + + ) + +213 #ifdeà +__USE_EXTERN_INLINES + + +214 +__ex‹º_šlše +  + +215 + `__NTH + ( + $tÞow” + ( +__c +)) + +217  +__c + >ð-128 && __ø< 256 ? (* + `__ùy³_tÞow”_loc + ())[__c] : __c; + +218 + } +} + +220 +__ex‹º_šlše +  + +221 +__NTH + ( + $touµ” + ( +__c +)) + +223  +__c + >ð-128 && __ø< 256 ? (* + `__ùy³_touµ”_loc + ())[__c] : __c; + +224 + } +} + +227 #ià +__GNUC__ + >ð2 && +defšed + +__OPTIMIZE__ + && !defšed +__ýlu¥lus + + +228  + #tÞow” +( +c +è + `__tobody + (c, +tÞow” +, * + `__ùy³_tÞow”_loc + (), (c)) + + ) + +229  + #touµ” +( +c +è + `__tobody + (c, +touµ” +, * + `__ùy³_touµ”_loc + (), (c)) + + ) + +232 #ià +defšed + +__USE_MISC + || defšed +__USE_XOPEN + + +233  + #i§scii +( +c +è + `__i§scii + (c) + + ) + +234  + #tßscii +( +c +è + `__tßscii + (c) + + ) + +236  + #_tÞow” +( +c +è((è(* + `__ùy³_tÞow”_loc + ())[(è(c)]) + + ) + +237  + #_touµ” +( +c +è((è(* + `__ùy³_touµ”_loc + ())[(è(c)]) + + ) + +243 #ifdeà +__USE_XOPEN2K8 + + +257  + ~ + +261  + #__isùy³_l +( +c +, +ty³ +, +loÿË +) \ + +262 (( +loÿË +)-> +__ùy³_b +[(è( +c +)] & (è +ty³ +) + + ) + +264  + #__exùy³_l +( +Çme +) \ + +265  + `Çme + (, +__loÿË_t +è +__THROW + + + ) + +271 +__exùy³_l + ( +i§Êum_l +); + +272 +__exùy³_l + ( +i§Íha_l +); + +273 +__exùy³_l + ( +isúŒl_l +); + +274 +__exùy³_l + ( +isdig™_l +); + +275 +__exùy³_l + ( +i¦ow”_l +); + +276 +__exùy³_l + ( +isg¿ph_l +); + +277 +__exùy³_l + ( +i¥ršt_l +); + +278 +__exùy³_l + ( +i¥unù_l +); + +279 +__exùy³_l + ( +is¥aû_l +); + +280 +__exùy³_l + ( +isuµ”_l +); + +281 +__exùy³_l + ( +isxdig™_l +); + +283 +__exùy³_l + ( +isbÏnk_l +); + +287  + $__tÞow”_l + ( +__c +, +__loÿË_t + +__l +è +__THROW +; + +288  + $tÞow”_l + ( +__c +, +__loÿË_t + +__l +è +__THROW +; + +291  + $__touµ”_l + ( +__c +, +__loÿË_t + +__l +è +__THROW +; + +292  + $touµ”_l + ( +__c +, +__loÿË_t + +__l +è +__THROW +; + +294 #ià +__GNUC__ + >ð2 && +defšed + +__OPTIMIZE__ + && !defšed +__ýlu¥lus + + +295  + #__tÞow”_l +( +c +, +loÿË +) \ + +296 + `__tobody + ( +c +, +__tÞow”_l +, ( +loÿË +)-> +__ùy³_tÞow” +, (c,†oÿË)) + + ) + +297  + #__touµ”_l +( +c +, +loÿË +) \ + +298 + `__tobody + ( +c +, +__touµ”_l +, ( +loÿË +)-> +__ùy³_touµ” +, (c,†oÿË)) + + ) + +299  + #tÞow”_l +( +c +, +loÿË +è + `__tÞow”_l + ((c), (loÿË)) + + ) + +300  + #touµ”_l +( +c +, +loÿË +è + `__touµ”_l + ((c), (loÿË)) + + ) + +304 #iâdeà +__NO_CTYPE + + +305  + #__i§Êum_l +( +c +, +l +è + `__isùy³_l +((c), +_IS®num +, (l)) + + ) + +306  + #__i§Íha_l +( +c +, +l +è + `__isùy³_l +((c), +_IS®pha +, (l)) + + ) + +307  + #__isúŒl_l +( +c +, +l +è + `__isùy³_l +((c), +_ISúŒl +, (l)) + + ) + +308  + #__isdig™_l +( +c +, +l +è + `__isùy³_l +((c), +_ISdig™ +, (l)) + + ) + +309  + #__i¦ow”_l +( +c +, +l +è + `__isùy³_l +((c), +_ISlow” +, (l)) + + ) + +310  + #__isg¿ph_l +( +c +, +l +è + `__isùy³_l +((c), +_ISg¿ph +, (l)) + + ) + +311  + #__i¥ršt_l +( +c +, +l +è + `__isùy³_l +((c), +_IS´št +, (l)) + + ) + +312  + #__i¥unù_l +( +c +, +l +è + `__isùy³_l +((c), +_ISpunù +, (l)) + + ) + +313  + #__is¥aû_l +( +c +, +l +è + `__isùy³_l +((c), +_IS¥aû +, (l)) + + ) + +314  + #__isuµ”_l +( +c +, +l +è + `__isùy³_l +((c), +_ISuµ” +, (l)) + + ) + +315  + #__isxdig™_l +( +c +, +l +è + `__isùy³_l +((c), +_ISxdig™ +, (l)) + + ) + +317  + #__isbÏnk_l +( +c +, +l +è + `__isùy³_l +((c), +_ISbÏnk +, (l)) + + ) + +319 #ifdeà +__USE_MISC + + +320  + #__i§scii_l +( +c +, +l +è(Ö), + `__i§scii + (c)) + + ) + +321  + #__tßscii_l +( +c +, +l +è(Ö), + `__tßscii + (c)) + + ) + +324  + #i§Êum_l +( +c +, +l +è + `__i§Êum_l + ((c), (l)) + + ) + +325  + #i§Íha_l +( +c +, +l +è + `__i§Íha_l + ((c), (l)) + + ) + +326  + #isúŒl_l +( +c +, +l +è + `__isúŒl_l + ((c), (l)) + + ) + +327  + #isdig™_l +( +c +, +l +è + `__isdig™_l + ((c), (l)) + + ) + +328  + #i¦ow”_l +( +c +, +l +è + `__i¦ow”_l + ((c), (l)) + + ) + +329  + #isg¿ph_l +( +c +, +l +è + `__isg¿ph_l + ((c), (l)) + + ) + +330  + #i¥ršt_l +( +c +, +l +è + `__i¥ršt_l + ((c), (l)) + + ) + +331  + #i¥unù_l +( +c +, +l +è + `__i¥unù_l + ((c), (l)) + + ) + +332  + #is¥aû_l +( +c +, +l +è + `__is¥aû_l + ((c), (l)) + + ) + +333  + #isuµ”_l +( +c +, +l +è + `__isuµ”_l + ((c), (l)) + + ) + +334  + #isxdig™_l +( +c +, +l +è + `__isxdig™_l + ((c), (l)) + + ) + +336  + #isbÏnk_l +( +c +, +l +è + `__isbÏnk_l + ((c), (l)) + + ) + +338 #ifdeà +__USE_MISC + + +339  + #i§scii_l +( +c +, +l +è + `__i§scii_l + ((c), (l)) + + ) + +340  + #tßscii_l +( +c +, +l +è + `__tßscii_l + ((c), (l)) + + ) + +347 +__END_DECLS + + + @/usr/include/math.h + +23 #iâdef +_MATH_H + + +24  + #_MATH_H + 1 + + ) + +26  + ~<ã©u»s.h +> + +28 + g__BEGIN_DECLS + + +31  + ~ + +35  + ~ + +36 #ifdeà +__USE_ISOC99 + + +37  + ~ + +38  + ~ + +41  + ~ + +44  + ~ + +48  + ~ + +55  + #__SIMD_DECL +( +funùiÚ +è + `__CONCAT + ( +__DECL_SIMD_ +, funùiÚ) + + ) + +57  + #__MATHCALL_VEC +( +funùiÚ +, +suffix +, +¬gs +) \ + +58 + `__SIMD_DECL + ( + `__MATH_PRECNAME + ( +funùiÚ +, +suffix +)) \ + +59 + `__MATHCALL + ( +funùiÚ +, +suffix +, +¬gs +) + + ) + +61  + #__MATHDECL_VEC +( +ty³ +, +funùiÚ +, +suffix +, +¬gs +) \ + +62 + `__SIMD_DECL + ( + `__MATH_PRECNAME + ( +funùiÚ +, +suffix +)) \ + +63 + `__MATHDECL +( +ty³ +, +funùiÚ +, +suffix +, +¬gs +) + + ) + +65  + #__MATHCALL +( +funùiÚ +, +suffix +, +¬gs +) \ + +66 + `__MATHDECL + ( +_MdoubË_ +, +funùiÚ +, +suffix +, +¬gs +) + + ) + +67  + #__MATHDECL +( +ty³ +, +funùiÚ +, +suffix +, +¬gs +) \ + +68 + `__MATHDECL_1 +( +ty³ +, +funùiÚ +, +suffix +, +¬gs +); \ + +69 + `__MATHDECL_1 +( +ty³ +, + `__CONCAT +( +__ +, +funùiÚ +), +suffix +, +¬gs +) + + ) + +70  + #__MATHCALLX +( +funùiÚ +, +suffix +, +¬gs +, +©Œib +) \ + +71 + `__MATHDECLX + ( +_MdoubË_ +, +funùiÚ +, +suffix +, +¬gs +, +©Œib +) + + ) + +72  + #__MATHDECLX +( +ty³ +, +funùiÚ +, +suffix +, +¬gs +, +©Œib +) \ + +73 + `__MATHDECL_1 +( +ty³ +, +funùiÚ +, +suffix +, +¬gs +è + `__©Œibu‹__ + ( +©Œib +); \ + +74 + `__MATHDECL_1 +( +ty³ +, + `__CONCAT +( +__ +, +funùiÚ +), +suffix +, +¬gs +è + `__©Œibu‹__ + ( +©Œib +) + + ) + +75  + #__MATHDECL_1 +( +ty³ +, +funùiÚ +, +suffix +, +¬gs +) \ + +76 +ty³ + + `__MATH_PRECNAME +( +funùiÚ +, +suffix +è +¬gs + +__THROW + + + ) + +78  + #_MdoubË_ +  + + ) + +79  + #__MATH_PRECNAME +( +Çme +, +r +è + `__CONCAT +Òame,r) + + ) + +80  + #__MATH_DECLARING_DOUBLE + 1 + + ) + +81  + #_MdoubË_BEGIN_NAMESPACE + +__BEGIN_NAMESPACE_STD + + + ) + +82  + #_MdoubË_END_NAMESPACE + +__END_NAMESPACE_STD + + + ) + +83  + ~ + +84 #undeà +_MdoubË_ + + +85 #undeà +_MdoubË_BEGIN_NAMESPACE + + +86 #undeà +_MdoubË_END_NAMESPACE + + +87 #undeà +__MATH_PRECNAME + + +88 #undeà +__MATH_DECLARING_DOUBLE + + +90 #ifdeà +__USE_ISOC99 + + +96 #iâdeà +_Mæßt_ + + +97  + #_Mæßt_ +  + + ) + +99  + #_MdoubË_ + +_Mæßt_ + + + ) + +100  + #__MATH_PRECNAME +( +Çme +, +r +èÇme## +f +## + ) +r + +101  + #__MATH_DECLARING_DOUBLE + 0 + + ) + +102  + #_MdoubË_BEGIN_NAMESPACE + +__BEGIN_NAMESPACE_C99 + + + ) + +103  + #_MdoubË_END_NAMESPACE + +__END_NAMESPACE_C99 + + + ) + +104  + ~ + +105 #undeà +_MdoubË_ + + +106 #undeà +_MdoubË_BEGIN_NAMESPACE + + +107 #undeà +_MdoubË_END_NAMESPACE + + +108 #undeà +__MATH_PRECNAME + + +109 #undeà +__MATH_DECLARING_DOUBLE + + +111 #ià!( +defšed + +__NO_LONG_DOUBLE_MATH + && defšed +_LIBC +) \ + +112 || +defšed + +__LDBL_COMPAT + \ + +113 || +defšed + +_LIBC_TEST + + +114 #ifdeà +__LDBL_COMPAT + + +116 #ifdeà +__USE_ISOC99 + + +117  + $__Ædbl_Ãx‰ow¬df + ( +__x +,  +__y +) + +118 +__THROW + + `__©Œibu‹__ + (( +__cÚ¡__ +)); + +119 #ifdeà +__REDIRECT_NTH + + +120  + `__REDIRECT_NTH + ( +Ãx‰ow¬df +, ( +__x +,  +__y +), + +121 +__Ædbl_Ãx‰ow¬df +) + +122 + `__©Œibu‹__ + (( +__cÚ¡__ +)); + +123  + `__REDIRECT_NTH + ( +Ãx‰ow¬d +, ( +__x +,  +__y +), + +124 +Ãxá” +è + `__©Œibu‹__ + (( +__cÚ¡__ +)); + +125  + `__REDIRECT_NTH + ( +Ãx‰ow¬dl +, + +126 ( +__x +,  +__y +), + +127 +Ãxá” +è + `__©Œibu‹__ + (( +__cÚ¡__ +)); + +131 #undeà +__MATHDECL_1 + + +132  + #__MATHDECL_2 +( +ty³ +, +funùiÚ +, +suffix +, +¬gs +, +®Ÿs +) \ + +133 +ty³ + + `__REDIRECT_NTH +( + `__MATH_PRECNAME +( +funùiÚ +, +suffix +), \ + +134 +¬gs +, +®Ÿs +) + + ) + +135  + #__MATHDECL_1 +( +ty³ +, +funùiÚ +, +suffix +, +¬gs +) \ + +136 + `__MATHDECL_2 +( +ty³ +, +funùiÚ +, +suffix +, +¬gs +, + `__CONCAT +(funùiÚ,suffix)) + + ) + +142 #iâdeà +_MlÚg_doubË_ + + +143  + #_MlÚg_doubË_ +  + + ) + +145  + #_MdoubË_ + +_MlÚg_doubË_ + + + ) + +146  + #__MATH_PRECNAME +( +Çme +, +r +èÇme## +l +## + ) +r + +147  + #__MATH_DECLARING_DOUBLE + 0 + + ) + +148  + #_MdoubË_BEGIN_NAMESPACE + +__BEGIN_NAMESPACE_C99 + + + ) + +149  + #_MdoubË_END_NAMESPACE + +__END_NAMESPACE_C99 + + + ) + +150  + #__MATH_DECLARE_LDOUBLE + 1 + + ) + +151  + ~ + +152 #undeà +_MdoubË_ + + +153 #undeà +_MdoubË_BEGIN_NAMESPACE + + +154 #undeà +_MdoubË_END_NAMESPACE + + +155 #undeà +__MATH_PRECNAME + + +156 #undeà +__MATH_DECLARING_DOUBLE + + +161 #undeà +__MATHDECL_1 + + +162 #undeà +__MATHDECL + + +163 #undeà +__MATHCALL + + +166 #ià +defšed + +__USE_MISC + || defšed +__USE_XOPEN + + +168  +signgam +; + +173 #ifdeà +__USE_ISOC99 + + +211 +FP_NAN + = + +212  + #FP_NAN + 0 + + ) + +213 +FP_NAN +, + +214 +FP_INFINITE + = + +215  + #FP_INFINITE + 1 + + ) + +216 +FP_INFINITE +, + +217 +FP_ZERO + = + +218  + #FP_ZERO + 2 + + ) + +219 +FP_ZERO +, + +220 +FP_SUBNORMAL + = + +221  + #FP_SUBNORMAL + 3 + + ) + +222 +FP_SUBNORMAL +, + +223 +FP_NORMAL + = + +224  + #FP_NORMAL + 4 + + ) + +225 +FP_NORMAL + + +233 #ià + `__GNUC_PREREQ + (4,4è&& ! +defšed + +__SUPPORT_SNAN__ + \ + +234 && ! +defšed + +__OPTIMIZE_SIZE__ + + +235  + #åþassify +( +x +è + `__bužtš_åþassify + ( +FP_NAN +, +FP_INFINITE +, \ + +236 +FP_NORMAL +, +FP_SUBNORMAL +, +FP_ZERO +, +x +) + + ) + +237 #–ià +defšed + +__NO_LONG_DOUBLE_MATH + + +238  + #åþassify +( +x +) \ + +239 ( ( +x +è=ð (è? + `__åþassifyf + (xè: + `__åþassify + (x)) + + ) + +241  + #åþassify +( +x +) \ + +242 ( ( +x +) ==  () \ + +243 ? + `__åþassifyf + ( +x +) \ + +244 :  ( +x +) ==  () \ + +245 ? + `__åþassify + ( +x +è: + `__åþassifyl + (x)) + + ) + +249 #ià + `__GNUC_PREREQ + (4,0) + +250  + #signb™ +( +x +) \ + +251 ( ( +x +) ==  () \ + +252 ? + `__bužtš_signb™f + ( +x +) \ + +253 :  ( +x +) ==  () \ + +254 ? + `__bužtš_signb™ + ( +x +è: + `__bužtš_signb™l + (x)) + + ) + +256 #ifdeà +__NO_LONG_DOUBLE_MATH + + +257  + #signb™ +( +x +) \ + +258 ( ( +x +è=ð (è? + `__signb™f + (xè: + `__signb™ + (x)) + + ) + +260  + #signb™ +( +x +) \ + +261 ( ( +x +) ==  () \ + +262 ? + `__signb™f + ( +x +) \ + +263 :  ( +x +) ==  () \ + +264 ? + `__signb™ + ( +x +è: + `__signb™l + (x)) + + ) + +269 #ià + `__GNUC_PREREQ + (4,4è&& ! +defšed + +__SUPPORT_SNAN__ + + +270  + #isfš™e +( +x +è + `__bužtš_isfš™e + (x) + + ) + +271 #–ià +defšed + +__NO_LONG_DOUBLE_MATH + + +272  + #isfš™e +( +x +) \ + +273 ( ( +x +è=ð (è? + `__fš™ef + (xè: + `__fš™e + (x)) + + ) + +275  + #isfš™e +( +x +) \ + +276 ( ( +x +) ==  () \ + +277 ? + `__fš™ef + ( +x +) \ + +278 :  ( +x +) ==  () \ + +279 ? + `__fš™e + ( +x +è: + `__fš™– + (x)) + + ) + +283 #ià + `__GNUC_PREREQ + (4,4è&& ! +defšed + +__SUPPORT_SNAN__ + + +284  + #i¢Üm® +( +x +è + `__bužtš_i¢Üm® + (x) + + ) + +286  + #i¢Üm® +( +x +è( + `åþassify + (xè=ð +FP_NORMAL +) + + ) + +291 #ià + `__GNUC_PREREQ + (4,4è&& ! +defšed + +__SUPPORT_SNAN__ + + +292  + #i¢ª +( +x +è + `__bužtš_i¢ª + (x) + + ) + +293 #–ià +defšed + +__NO_LONG_DOUBLE_MATH + + +294  + #i¢ª +( +x +) \ + +295 ( ( +x +è=ð (è? + `__i¢ªf + (xè: + `__i¢ª + (x)) + + ) + +297  + #i¢ª +( +x +) \ + +298 ( ( +x +) ==  () \ + +299 ? + `__i¢ªf + ( +x +) \ + +300 :  ( +x +) ==  () \ + +301 ? + `__i¢ª + ( +x +è: + `__i¢ªl + (x)) + + ) + +305 #ià + `__GNUC_PREREQ + (4,4è&& ! +defšed + +__SUPPORT_SNAN__ + + +306  + #isšf +( +x +è + `__bužtš_isšf_sign + (x) + + ) + +307 #–ià +defšed + +__NO_LONG_DOUBLE_MATH + + +308  + #isšf +( +x +) \ + +309 ( ( +x +è=ð (è? + `__isšff + (xè: + `__isšf + (x)) + + ) + +311  + #isšf +( +x +) \ + +312 ( ( +x +) ==  () \ + +313 ? + `__isšff + ( +x +) \ + +314 :  ( +x +) ==  () \ + +315 ? + `__isšf + ( +x +è: + `__isšæ + (x)) + + ) + +319  + #MATH_ERRNO + 1 + + ) + +320  + #MATH_ERREXCEPT + 2 + + ) + +325 #iâdeà +__FAST_MATH__ + + +326  + #m©h_”rhªdlšg + ( +MATH_ERRNO + | +MATH_ERREXCEPT +) + + ) + +331 #ifdeà +__USE_GNU + + +333 #ifdeà +__NO_LONG_DOUBLE_MATH + + +334  + #issigÇlšg +( +x +) \ + +335 ( ( +x +è=ð (è? + `__issigÇlšgf + (xè: + `__issigÇlšg + (x)) + + ) + +337  + #issigÇlšg +( +x +) \ + +338 ( ( +x +) ==  () \ + +339 ? + `__issigÇlšgf + ( +x +) \ + +340 :  ( +x +) ==  () \ + +341 ? + `__issigÇlšg + ( +x +è: + `__issigÇlšgl + (x)) + + ) + +345 #ifdef +__USE_MISC + + +349 +_IEEE_ + = -1, + +350 +_SVID_ +, + +351 +_XOPEN_ +, + +352 +_POSIX_ +, + +353 +_ISOC_ + + +354 } + t_LIB_VERSION_TYPE +; + +359 +_LIB_VERSION_TYPE + +_LIB_VERSION +; + +363 #ifdeà +__USE_MISC + + +369 #ifdeà +__ýlu¥lus + + +370  +__exû±iÚ + + +372  +exû±iÚ + + +375  +ty³ +; + +376 * +Çme +; + +377  +¬g1 +; + +378  +¬g2 +; + +379  +»tv® +; + +380 + } +}; + +382 #ifdeà +__ýlu¥lus + + +383  + $m©h”r + ( +__exû±iÚ + * +__exc +è + `throw + (); + +385  + `m©h”r + ( +exû±iÚ + * +__exc +); + +388  + #X_TLOSS + 1.41484755040568800000e+16 + + ) + +391  + #DOMAIN + 1 + + ) + +392  + #SING + 2 + + ) + +393  + #OVERFLOW + 3 + + ) + +394  + #UNDERFLOW + 4 + + ) + +395  + #TLOSS + 5 + + ) + +396  + #PLOSS + 6 + + ) + +399  + #HUGE + 3.40282347e+38F + + ) + +403 #ifdeà +__USE_XOPEN + + +405  + #MAXFLOAT + 3.40282347e+38F + + ) + +412 #ià +defšed + +__USE_MISC + || defšed +__USE_XOPEN + + +413  + #M_E + 2.7182818284590452354 + + ) + +414  + #M_LOG2E + 1.4426950408889634074 + + ) + +415  + #M_LOG10E + 0.43429448190325182765 + + ) + +416  + #M_LN2 + 0.69314718055994530942 + + ) + +417  + #M_LN10 + 2.30258509299404568402 + + ) + +418  + #M_PI + 3.14159265358979323846 + + ) + +419  + #M_PI_2 + 1.57079632679489661923 + + ) + +420  + #M_PI_4 + 0.78539816339744830962 + + ) + +421  + #M_1_PI + 0.31830988618379067154 + + ) + +422  + #M_2_PI + 0.63661977236758134308 + + ) + +423  + #M_2_SQRTPI + 1.12837916709551257390 + + ) + +424  + #M_SQRT2 + 1.41421356237309504880 + + ) + +425  + #M_SQRT1_2 + 0.70710678118654752440 + + ) + +431 #ifdeà +__USE_GNU + + +432  + #M_El + 2.718281828459045235360287471352662498L + + ) + +433  + #M_LOG2El + 1.442695040888963407359924681001892137L + + ) + +434  + #M_LOG10El + 0.434294481903251827651128918916605082L + + ) + +435  + #M_LN2l + 0.693147180559945309417232121458176568L + + ) + +436  + #M_LN10l + 2.302585092994045684017991454684364208L + + ) + +437  + #M_PIl + 3.141592653589793238462643383279502884L + + ) + +438  + #M_PI_2l + 1.570796326794896619231321691639751442L + + ) + +439  + #M_PI_4l + 0.785398163397448309615660845819875721L + + ) + +440  + #M_1_PIl + 0.318309886183790671537767526745028724L + + ) + +441  + #M_2_PIl + 0.636619772367581343075535053490057448L + + ) + +442  + #M_2_SQRTPIl + 1.128379167095512573896158903121545172L + + ) + +443  + #M_SQRT2l + 1.414213562373095048801688724209698079L + + ) + +444  + #M_SQRT1_2l + 0.707106781186547524400844362104849039L + + ) + +451 #ià +defšed + +__STRICT_ANSI__ + && !defšed +__NO_MATH_INLINES + + +452  + #__NO_MATH_INLINES + 1 + + ) + +455 #ià +defšed + +__USE_ISOC99 + && + `__GNUC_PREREQ +(2,97) + +462  + #isg»©” +( +x +, +y +è + `__bužtš_isg»©” +(x, y) + + ) + +463  + #isg»©”equ® +( +x +, +y +è + `__bužtš_isg»©”equ® +(x, y) + + ) + +464  + #i¦ess +( +x +, +y +è + `__bužtš_i¦ess +(x, y) + + ) + +465  + #i¦es£qu® +( +x +, +y +è + `__bužtš_i¦es£qu® +(x, y) + + ) + +466  + #i¦essg»©” +( +x +, +y +è + `__bužtš_i¦essg»©” +(x, y) + + ) + +467  + #isunÜd”ed +( +u +, +v +è + `__bužtš_isunÜd”ed +(u, v) + + ) + +471 #ifdeà +__USE_EXTERN_INLINES + + +472  + ~ + +477 #ià +defšed + +__FINITE_MATH_ONLY__ + && __FINITE_MATH_ONLY__ > 0 + +478  + ~ + +481 #ifdeà +__USE_ISOC99 + + +485 #iâdeà +isg»©” + + +486  + #isg»©” +( +x +, +y +) \ + +487 ( +__ex‹nsiÚ__ + \ + +488 ({ + `__ty³of__ +( +x +è +__x + = (x); __ty³of__( +y +è +__y + = (y); \ + +489 ! + `isunÜd”ed + ( +__x +, +__y +è&& __x > __y; + } +})) + + ) + +493 #iâdeà +isg»©”equ® + + +494  + #isg»©”equ® +( +x +, +y +) \ + +495 ( +__ex‹nsiÚ__ + \ + +496 ({ + `__ty³of__ +( +x +è +__x + = (x); __ty³of__( +y +è +__y + = (y); \ + +497 ! + `isunÜd”ed + ( +__x +, +__y +è&& __x >ð__y; })) + + ) + +501 #iâdeà +i¦ess + + +502  + #i¦ess +( +x +, +y +) \ + +503 ( +__ex‹nsiÚ__ + \ + +504 ({ + `__ty³of__ +( +x +è +__x + = (x); __ty³of__( +y +è +__y + = (y); \ + +505 ! + `isunÜd”ed + ( +__x +, +__y +è&& __x < __y; })) + + ) + +509 #iâdeà +i¦es£qu® + + +510  + #i¦es£qu® +( +x +, +y +) \ + +511 ( +__ex‹nsiÚ__ + \ + +512 ({ + `__ty³of__ +( +x +è +__x + = (x); __ty³of__( +y +è +__y + = (y); \ + +513 ! + `isunÜd”ed + ( +__x +, +__y +è&& __x <ð__y; })) + + ) + +517 #iâdeà +i¦essg»©” + + +518  + #i¦essg»©” +( +x +, +y +) \ + +519 ( +__ex‹nsiÚ__ + \ + +520 ({ + `__ty³of__ +( +x +è +__x + = (x); __ty³of__( +y +è +__y + = (y); \ + +521 ! + `isunÜd”ed + ( +__x +, +__y +è&& (__x < __y || __y < __x); })) + + ) + +525 #iâdeà +isunÜd”ed + + +526  + #isunÜd”ed +( +u +, +v +) \ + +527 ( +__ex‹nsiÚ__ + \ + +528 ({ + `__ty³of__ +( +u +è +__u + = (u); __ty³of__( +v +è +__v + = (v); \ + +529 + `åþassify + ( +__u +è=ð +FP_NAN + || fpþassify ( +__v +è=ðFP_NAN; })) + + ) + +534 + g__END_DECLS + + + @/usr/include/stdlib.h + +22 #iâdef +_STDLIB_H + + +24  + ~<ã©u»s.h +> + +27  + #__Ãed_size_t + + + ) + +28 #iâdeà +__Ãed_m®loc_ªd_ÿÎoc + + +29  + #__Ãed_wch¬_t + + + ) + +30  + #__Ãed_NULL + + + ) + +32  + ~<¡ddef.h +> + +34 + g__BEGIN_DECLS + + +36 #iâdeà +__Ãed_m®loc_ªd_ÿÎoc + + +37  + #_STDLIB_H + 1 + + ) + +39 #ià( +defšed + +__USE_XOPEN + || defšed +__USE_XOPEN2K8 +è&& !defšed +_SYS_WAIT_H + + +41  + ~ + +42  + ~ + +44 #ifdeà +__USE_MISC + + +49 #ià +defšed + +__GNUC__ + && !defšed +__ýlu¥lus + + +50  + #__WAIT_INT +( +¡©us +) \ + +51 ( + `__ex‹nsiÚ__ + (((uniÚ { + `__ty³of +( +¡©us +è +__š +;  +__i +; }) \ + +52 { . +__š + = ( +¡©us +è}). +__i +)) + + ) + +54  + #__WAIT_INT +( +¡©us +è(*(*è&(¡©us)) + + ) + +62 #ià! +defšed + +__GNUC__ + || __GNUC__ < 2 || defšed +__ýlu¥lus + + +63  + #__WAIT_STATUS + * + + ) + +64  + #__WAIT_STATUS_DEFN + * + + ) + +69  +wa™ + * + m__u±r +; + +70 * + m__Œ +; + +71 } + t__WAIT_STATUS + + t__©Œibu‹__ + (( + t__Œª¥¬’t_uniÚ__ +)); + +72  + #__WAIT_STATUS_DEFN + * + + ) + +77  + #__WAIT_INT +( +¡©us +è(¡©us) + + ) + +78  + #__WAIT_STATUS + * + + ) + +79  + #__WAIT_STATUS_DEFN + * + + ) + +84  + #WEXITSTATUS +( +¡©us +è + `__WEXITSTATUS + ( + `__WAIT_INT + (¡©us)) + + ) + +85  + #WTERMSIG +( +¡©us +è + `__WTERMSIG + ( + `__WAIT_INT + (¡©us)) + + ) + +86  + #WSTOPSIG +( +¡©us +è + `__WSTOPSIG + ( + `__WAIT_INT + (¡©us)) + + ) + +87  + #WIFEXITED +( +¡©us +è + `__WIFEXITED + ( + `__WAIT_INT + (¡©us)) + + ) + +88  + #WIFSIGNALED +( +¡©us +è + `__WIFSIGNALED + ( + `__WAIT_INT + (¡©us)) + + ) + +89  + #WIFSTOPPED +( +¡©us +è + `__WIFSTOPPED + ( + `__WAIT_INT + (¡©us)) + + ) + +90 #ifdeà +__WIFCONTINUED + + +91  + #WIFCONTINUED +( +¡©us +è + `__WIFCONTINUED + ( + `__WAIT_INT + (¡©us)) + + ) + +95 +__BEGIN_NAMESPACE_STD + + +99  + mquÙ +; + +100  + m»m +; + +101 } + tdiv_t +; + +104 #iâdeà +__ldiv_t_defšed + + +107  + mquÙ +; + +108  + m»m +; + +109 } + tldiv_t +; + +110  + #__ldiv_t_defšed + 1 + + ) + +112 + g__END_NAMESPACE_STD + + +114 #ià +defšed + +__USE_ISOC99 + && !defšed +__Îdiv_t_defšed + + +115 +__BEGIN_NAMESPACE_C99 + + +117 +__ex‹nsiÚ__ + struct + +119  + mquÙ +; + +120  + m»m +; + +121 } + tÎdiv_t +; + +122  + #__Îdiv_t_defšed + 1 + + ) + +123 + g__END_NAMESPACE_C99 + + +128  + #RAND_MAX + 2147483647 + + ) + +133  + #EXIT_FAILURE + 1 + + ) + +134  + #EXIT_SUCCESS + 0 + + ) + +138  + #MB_CUR_MAX + ( + `__ùy³_g‘_mb_cur_max + ()) + + ) + +139 +size_t + + $__ùy³_g‘_mb_cur_max + (è +__THROW + +__wur +; + +142 +__BEGIN_NAMESPACE_STD + + +144  + $©of + (cÚ¡ * +__ÅŒ +) + +145 +__THROW + +__©Œibu‹_pu»__ + + `__nÚnuÎ + ((1)è +__wur +; + +147  + $©oi + (cÚ¡ * +__ÅŒ +) + +148 +__THROW + +__©Œibu‹_pu»__ + + `__nÚnuÎ + ((1)è +__wur +; + +150  + $©Þ + (cÚ¡ * +__ÅŒ +) + +151 +__THROW + +__©Œibu‹_pu»__ + + `__nÚnuÎ + ((1)è +__wur +; + +152 +__END_NAMESPACE_STD + + +154 #ifdeà +__USE_ISOC99 + + +155 +__BEGIN_NAMESPACE_C99 + + +157 +__ex‹nsiÚ__ +  + $©Þl + (cÚ¡ * +__ÅŒ +) + +158 +__THROW + +__©Œibu‹_pu»__ + + `__nÚnuÎ + ((1)è +__wur +; + +159 +__END_NAMESPACE_C99 + + +162 +__BEGIN_NAMESPACE_STD + + +164  + $¡¹od + (cÚ¡ * +__»¡riù + +__ÅŒ +, + +165 ** +__»¡riù + +__’d±r +) + +166 +__THROW + + `__nÚnuÎ + ((1)); + +167 +__END_NAMESPACE_STD + + +169 #ifdef +__USE_ISOC99 + + +170 +__BEGIN_NAMESPACE_C99 + + +172  + $¡¹of + (cÚ¡ * +__»¡riù + +__ÅŒ +, + +173 ** +__»¡riù + +__’d±r +è +__THROW + + `__nÚnuÎ + ((1)); + +175  + $¡¹Þd + (cÚ¡ * +__»¡riù + +__ÅŒ +, + +176 ** +__»¡riù + +__’d±r +) + +177 +__THROW + + `__nÚnuÎ + ((1)); + +178 +__END_NAMESPACE_C99 + + +181 +__BEGIN_NAMESPACE_STD + + +183  + $¡¹Þ + (cÚ¡ * +__»¡riù + +__ÅŒ +, + +184 ** +__»¡riù + +__’d±r +,  +__ba£ +) + +185 +__THROW + + `__nÚnuÎ + ((1)); + +187  + $¡¹oul + (cÚ¡ * +__»¡riù + +__ÅŒ +, + +188 ** +__»¡riù + +__’d±r +,  +__ba£ +) + +189 +__THROW + + `__nÚnuÎ + ((1)); + +190 +__END_NAMESPACE_STD + + +192 #ifdeà +__USE_MISC + + +194 +__ex‹nsiÚ__ + + +195  + $¡¹oq + (cÚ¡ * +__»¡riù + +__ÅŒ +, + +196 ** +__»¡riù + +__’d±r +,  +__ba£ +) + +197 +__THROW + + `__nÚnuÎ + ((1)); + +199 +__ex‹nsiÚ__ + + +200  + $¡¹ouq + (cÚ¡ * +__»¡riù + +__ÅŒ +, + +201 ** +__»¡riù + +__’d±r +,  +__ba£ +) + +202 +__THROW + + `__nÚnuÎ + ((1)); + +205 #ifdeà +__USE_ISOC99 + + +206 +__BEGIN_NAMESPACE_C99 + + +208 +__ex‹nsiÚ__ + + +209  + $¡¹Þl + (cÚ¡ * +__»¡riù + +__ÅŒ +, + +210 ** +__»¡riù + +__’d±r +,  +__ba£ +) + +211 +__THROW + + `__nÚnuÎ + ((1)); + +213 +__ex‹nsiÚ__ + + +214  + $¡¹ouÎ + (cÚ¡ * +__»¡riù + +__ÅŒ +, + +215 ** +__»¡riù + +__’d±r +,  +__ba£ +) + +216 +__THROW + + `__nÚnuÎ + ((1)); + +217 +__END_NAMESPACE_C99 + + +221 #ifdeà +__USE_GNU + + +235  + ~ + +239  + $¡¹Þ_l + (cÚ¡ * +__»¡riù + +__ÅŒ +, + +240 ** +__»¡riù + +__’d±r +,  +__ba£ +, + +241 +__loÿË_t + +__loc +è +__THROW + + `__nÚnuÎ + ((1, 4)); + +243  + $¡¹oul_l + (cÚ¡ * +__»¡riù + +__ÅŒ +, + +244 ** +__»¡riù + +__’d±r +, + +245  +__ba£ +, +__loÿË_t + +__loc +) + +246 +__THROW + + `__nÚnuÎ + ((1, 4)); + +248 +__ex‹nsiÚ__ + + +249  + $¡¹Þl_l + (cÚ¡ * +__»¡riù + +__ÅŒ +, + +250 ** +__»¡riù + +__’d±r +,  +__ba£ +, + +251 +__loÿË_t + +__loc +) + +252 +__THROW + + `__nÚnuÎ + ((1, 4)); + +254 +__ex‹nsiÚ__ + + +255  + $¡¹ouÎ_l + (cÚ¡ * +__»¡riù + +__ÅŒ +, + +256 ** +__»¡riù + +__’d±r +, + +257  +__ba£ +, +__loÿË_t + +__loc +) + +258 +__THROW + + `__nÚnuÎ + ((1, 4)); + +260  + $¡¹od_l + (cÚ¡ * +__»¡riù + +__ÅŒ +, + +261 ** +__»¡riù + +__’d±r +, +__loÿË_t + +__loc +) + +262 +__THROW + + `__nÚnuÎ + ((1, 3)); + +264  + $¡¹of_l + (cÚ¡ * +__»¡riù + +__ÅŒ +, + +265 ** +__»¡riù + +__’d±r +, +__loÿË_t + +__loc +) + +266 +__THROW + + `__nÚnuÎ + ((1, 3)); + +268  + $¡¹Þd_l + (cÚ¡ * +__»¡riù + +__ÅŒ +, + +269 ** +__»¡riù + +__’d±r +, + +270 +__loÿË_t + +__loc +) + +271 +__THROW + + `__nÚnuÎ + ((1, 3)); + +275 #ifdeà +__USE_EXTERN_INLINES + + +276 +__BEGIN_NAMESPACE_STD + + +277 +__ex‹º_šlše +  + +278 + `__NTH + ( + $©oi + (cÚ¡ * +__ÅŒ +)) + +280  (è + `¡¹Þ + ( +__ÅŒ +, (**è +NULL +, 10); + +281 + } +} + +282 +__ex‹º_šlše +  + +283 +__NTH + ( + $©Þ + (cÚ¡ * +__ÅŒ +)) + +285  + `¡¹Þ + ( +__ÅŒ +, (**è +NULL +, 10); + +286 + } +} + +287 + g__END_NAMESPACE_STD + + +289 #ifdeà +__USE_ISOC99 + + +290 +__BEGIN_NAMESPACE_C99 + + +291 +__ex‹nsiÚ__ + +__ex‹º_šlše +  + +292 +__NTH + ( + $©Þl + (cÚ¡ * +__ÅŒ +)) + +294  + `¡¹Þl + ( +__ÅŒ +, (**è +NULL +, 10); + +295 + } +} + +296 + g__END_NAMESPACE_C99 + + +301 #ià +defšed + +__USE_MISC + || defšed +__USE_XOPEN_EXTENDED + + +305 * + $l64a + ( +__n +è +__THROW + +__wur +; + +308  + $a64l + (cÚ¡ * +__s +) + +309 +__THROW + +__©Œibu‹_pu»__ + + `__nÚnuÎ + ((1)è +__wur +; + +313 #ià +defšed + +__USE_MISC + || defšed +__USE_XOPEN_EXTENDED + + +314  + ~ + +321  + $¿ndom + (è +__THROW +; + +324  + $¤ªdom + ( +__£ed +è +__THROW +; + +330 * + $š™¡©e + ( +__£ed +, * +__¡©ebuf +, + +331 +size_t + +__¡©–’ +è +__THROW + + `__nÚnuÎ + ((2)); + +335 * + $£t¡©e + (* +__¡©ebuf +è +__THROW + + `__nÚnuÎ + ((1)); + +338 #ifdeà +__USE_MISC + + +343  + s¿ndom_d©a + + +345 +št32_t + * +åŒ +; + +346 +št32_t + * +½Œ +; + +347 +št32_t + * +¡©e +; + +348  +¿nd_ty³ +; + +349  +¿nd_deg +; + +350  +¿nd_£p +; + +351 +št32_t + * +’d_±r +; + +354  + $¿ndom_r + ( +¿ndom_d©a + * +__»¡riù + +__buf +, + +355 +št32_t + * +__»¡riù + +__»suÉ +è +__THROW + + `__nÚnuÎ + ((1, 2)); + +357  + $¤ªdom_r + ( +__£ed +,  +¿ndom_d©a + * +__buf +) + +358 +__THROW + + `__nÚnuÎ + ((2)); + +360  + $š™¡©e_r + ( +__£ed +, * +__»¡riù + +__¡©ebuf +, + +361 +size_t + +__¡©–’ +, + +362  +¿ndom_d©a + * +__»¡riù + +__buf +) + +363 +__THROW + + `__nÚnuÎ + ((2, 4)); + +365  + $£t¡©e_r + (* +__»¡riù + +__¡©ebuf +, + +366  +¿ndom_d©a + * +__»¡riù + +__buf +) + +367 +__THROW + + `__nÚnuÎ + ((1, 2)); + +372 +__BEGIN_NAMESPACE_STD + + +374  + $¿nd + (è +__THROW +; + +376  + $¤ªd + ( +__£ed +è +__THROW +; + +377 +__END_NAMESPACE_STD + + +379 #ifdeà +__USE_POSIX + + +381  + $¿nd_r + (* +__£ed +è +__THROW +; + +385 #ià +defšed + +__USE_MISC + || defšed +__USE_XOPEN + + +389  + $d¿nd48 + (è +__THROW +; + +390  + $”ªd48 + ( +__xsubi +[3]è +__THROW + + `__nÚnuÎ + ((1)); + +393  + $̪d48 + (è +__THROW +; + +394  + $Īd48 + ( +__xsubi +[3]) + +395 +__THROW + + `__nÚnuÎ + ((1)); + +398  + $m¿nd48 + (è +__THROW +; + +399  + $j¿nd48 + ( +__xsubi +[3]) + +400 +__THROW + + `__nÚnuÎ + ((1)); + +403  + $¤ªd48 + ( +__£edv® +è +__THROW +; + +404 * + $£ed48 + ( +__£ed16v +[3]) + +405 +__THROW + + `__nÚnuÎ + ((1)); + +406  + $lcÚg48 + ( +__·¿m +[7]è +__THROW + + `__nÚnuÎ + ((1)); + +408 #ifdeà +__USE_MISC + + +412  + sd¿nd48_d©a + + +414  +__x +[3]; + +415  +__Þd_x +[3]; + +416  +__c +; + +417  +__š™ +; + +418 +__ex‹nsiÚ__ +  +__a +; + +423  + $d¿nd48_r + ( +d¿nd48_d©a + * +__»¡riù + +__bufãr +, + +424 * +__»¡riù + +__»suÉ +è +__THROW + + `__nÚnuÎ + ((1, 2)); + +425  + $”ªd48_r + ( +__xsubi +[3], + +426  +d¿nd48_d©a + * +__»¡riù + +__bufãr +, + +427 * +__»¡riù + +__»suÉ +è +__THROW + + `__nÚnuÎ + ((1, 2)); + +430  + $̪d48_r + ( +d¿nd48_d©a + * +__»¡riù + +__bufãr +, + +431 * +__»¡riù + +__»suÉ +) + +432 +__THROW + + `__nÚnuÎ + ((1, 2)); + +433  + $Īd48_r + ( +__xsubi +[3], + +434  +d¿nd48_d©a + * +__»¡riù + +__bufãr +, + +435 * +__»¡riù + +__»suÉ +) + +436 +__THROW + + `__nÚnuÎ + ((1, 2)); + +439  + $m¿nd48_r + ( +d¿nd48_d©a + * +__»¡riù + +__bufãr +, + +440 * +__»¡riù + +__»suÉ +) + +441 +__THROW + + `__nÚnuÎ + ((1, 2)); + +442  + $j¿nd48_r + ( +__xsubi +[3], + +443  +d¿nd48_d©a + * +__»¡riù + +__bufãr +, + +444 * +__»¡riù + +__»suÉ +) + +445 +__THROW + + `__nÚnuÎ + ((1, 2)); + +448  + $¤ªd48_r + ( +__£edv® +,  +d¿nd48_d©a + * +__bufãr +) + +449 +__THROW + + `__nÚnuÎ + ((2)); + +451  + $£ed48_r + ( +__£ed16v +[3], + +452  +d¿nd48_d©a + * +__bufãr +è +__THROW + + `__nÚnuÎ + ((1, 2)); + +454  + $lcÚg48_r + ( +__·¿m +[7], + +455  +d¿nd48_d©a + * +__bufãr +) + +456 +__THROW + + `__nÚnuÎ + ((1, 2)); + +462 #iâdeà +__m®loc_ªd_ÿÎoc_defšed + + +463  + #__m®loc_ªd_ÿÎoc_defšed + + + ) + +464 +__BEGIN_NAMESPACE_STD + + +466 * + $m®loc + ( +size_t + +__size +è +__THROW + +__©Œibu‹_m®loc__ + +__wur +; + +468 * + $ÿÎoc + ( +size_t + +__nmemb +, size_ˆ +__size +) + +469 +__THROW + +__©Œibu‹_m®loc__ + +__wur +; + +470 +__END_NAMESPACE_STD + + +473 #iâdeà +__Ãed_m®loc_ªd_ÿÎoc + + +474 +__BEGIN_NAMESPACE_STD + + +480 * + $»®loc + (* +__±r +, +size_t + +__size +) + +481 +__THROW + +__©Œibu‹_w¬n_unu£d_»suÉ__ +; + +483  + $ä“ + (* +__±r +è +__THROW +; + +484 +__END_NAMESPACE_STD + + +486 #ifdef +__USE_MISC + + +488  + $cä“ + (* +__±r +è +__THROW +; + +491 #ifdeà +__USE_MISC + + +492  + ~<®loÿ.h +> + +495 #ià( +defšed + +__USE_XOPEN_EXTENDED + && !defšed +__USE_XOPEN2K +) \ + +496 || +defšed + +__USE_MISC + + +498 * + $v®loc + ( +size_t + +__size +è +__THROW + +__©Œibu‹_m®loc__ + +__wur +; + +501 #ifdeà +__USE_XOPEN2K + + +503  + $posix_mem®ign + (** +__mem±r +, +size_t + +__®ignm’t +, size_ˆ +__size +) + +504 +__THROW + + `__nÚnuÎ + ((1)è +__wur +; + +507 #ifdeà +__USE_ISOC11 + + +509 * + $®igÃd_®loc + ( +size_t + +__®ignm’t +, size_ˆ +__size +) + +510 +__THROW + +__©Œibu‹_m®loc__ + + `__©Œibu‹_®loc_size__ + ((2)è +__wur +; + +513 +__BEGIN_NAMESPACE_STD + + +515  + $abÜt + (è +__THROW + + `__©Œibu‹__ + (( +__nÜ‘uº__ +)); + +519  + $©ex™ + ((* +__func +è()è +__THROW + + `__nÚnuÎ + ((1)); + +521 #ià +defšed + +__USE_ISOC11 + || defšed +__USE_ISOCXX11 + + +523 #ifdeà +__ýlu¥lus + + +524 "C++"  + $©_quick_ex™ + ((* +__func +) ()) + +525 +__THROW + + `__asm + ("©_quick_ex™"è + `__nÚnuÎ + ((1)); + +527  + $©_quick_ex™ + ((* +__func +è()è +__THROW + + `__nÚnuÎ + ((1)); + +530 +__END_NAMESPACE_STD + + +532 #ifdef +__USE_MISC + + +535  + $Ú_ex™ + ((* +__func +è( +__¡©us +, * +__¬g +), *__arg) + +536 +__THROW + + `__nÚnuÎ + ((1)); + +539 +__BEGIN_NAMESPACE_STD + + +543  + $ex™ + ( +__¡©us +è +__THROW + + `__©Œibu‹__ + (( +__nÜ‘uº__ +)); + +545 #ià +defšed + +__USE_ISOC11 + || defšed +__USE_ISOCXX11 + + +549  + $quick_ex™ + ( +__¡©us +è +__THROW + + `__©Œibu‹__ + (( +__nÜ‘uº__ +)); + +551 +__END_NAMESPACE_STD + + +553 #ifdeà +__USE_ISOC99 + + +554 +__BEGIN_NAMESPACE_C99 + + +557  + $_Ex™ + ( +__¡©us +è +__THROW + + `__©Œibu‹__ + (( +__nÜ‘uº__ +)); + +558 +__END_NAMESPACE_C99 + + +562 +__BEGIN_NAMESPACE_STD + + +564 * + $g‘’v + (cÚ¡ * +__Çme +è +__THROW + + `__nÚnuÎ + ((1)è +__wur +; + +565 +__END_NAMESPACE_STD + + +567 #ifdeà +__USE_GNU + + +570 * + $£cu»_g‘’v + (cÚ¡ * +__Çme +) + +571 +__THROW + + `__nÚnuÎ + ((1)è +__wur +; + +574 #ià +defšed + +__USE_MISC + || defšed +__USE_XOPEN + + +578  + $pu‹nv + (* +__¡ršg +è +__THROW + + `__nÚnuÎ + ((1)); + +581 #ifdeà +__USE_XOPEN2K + + +584  + $£‹nv + (cÚ¡ * +__Çme +, cÚ¡ * +__v®ue +,  +__»¶aû +) + +585 +__THROW + + `__nÚnuÎ + ((2)); + +588  + $un£‹nv + (cÚ¡ * +__Çme +è +__THROW + + `__nÚnuÎ + ((1)); + +591 #ifdef +__USE_MISC + + +595  + $þ—»nv + (è +__THROW +; + +599 #ià +defšed + +__USE_MISC + \ + +600 || ( +defšed + +__USE_XOPEN_EXTENDED + && !defšed +__USE_XOPEN2K8 +) + +606 * + $mk‹mp + (* +__‹m¶©e +è +__THROW + + `__nÚnuÎ + ((1)); + +609 #ià +defšed + +__USE_XOPEN_EXTENDED + || defšed +__USE_XOPEN2K8 + + +618 #iâdeà +__USE_FILE_OFFSET64 + + +619  + $mk¡emp + (* +__‹m¶©e +è + `__nÚnuÎ + ((1)è +__wur +; + +621 #ifdeà +__REDIRECT + + +622  + `__REDIRECT + ( +mk¡emp +, (* +__‹m¶©e +), +mk¡emp64 +) + +623 + `__nÚnuÎ + ((1)è +__wur +; + +625  + #mk¡emp + +mk¡emp64 + + + ) + +628 #ifdeà +__USE_LARGEFILE64 + + +629  + $mk¡emp64 + (* +__‹m¶©e +è + `__nÚnuÎ + ((1)è +__wur +; + +633 #ifdeà +__USE_MISC + + +640 #iâdeà +__USE_FILE_OFFSET64 + + +641  + $mk¡emps + (* +__‹m¶©e +,  +__suffixËn +è + `__nÚnuÎ + ((1)è +__wur +; + +643 #ifdeà +__REDIRECT + + +644  + `__REDIRECT + ( +mk¡emps +, (* +__‹m¶©e +,  +__suffixËn +), + +645 +mk¡emps64 +è + `__nÚnuÎ + ((1)è +__wur +; + +647  + #mk¡emps + +mk¡emps64 + + + ) + +650 #ifdeà +__USE_LARGEFILE64 + + +651  + $mk¡emps64 + (* +__‹m¶©e +,  +__suffixËn +) + +652 + `__nÚnuÎ + ((1)è +__wur +; + +656 #ifdeà +__USE_XOPEN2K8 + + +662 * + $mkd‹mp + (* +__‹m¶©e +è +__THROW + + `__nÚnuÎ + ((1)è +__wur +; + +665 #ifdeà +__USE_GNU + + +672 #iâdeà +__USE_FILE_OFFSET64 + + +673  + $mko¡emp + (* +__‹m¶©e +,  +__æags +è + `__nÚnuÎ + ((1)è +__wur +; + +675 #ifdeà +__REDIRECT + + +676  + `__REDIRECT + ( +mko¡emp +, (* +__‹m¶©e +,  +__æags +), +mko¡emp64 +) + +677 + `__nÚnuÎ + ((1)è +__wur +; + +679  + #mko¡emp + +mko¡emp64 + + + ) + +682 #ifdeà +__USE_LARGEFILE64 + + +683  + $mko¡emp64 + (* +__‹m¶©e +,  +__æags +è + `__nÚnuÎ + ((1)è +__wur +; + +692 #iâdeà +__USE_FILE_OFFSET64 + + +693  + $mko¡emps + (* +__‹m¶©e +,  +__suffixËn +,  +__æags +) + +694 + `__nÚnuÎ + ((1)è +__wur +; + +696 #ifdeà +__REDIRECT + + +697  + `__REDIRECT + ( +mko¡emps +, (* +__‹m¶©e +,  +__suffixËn +, + +698  +__æags +), +mko¡emps64 +) + +699 + `__nÚnuÎ + ((1)è +__wur +; + +701  + #mko¡emps + +mko¡emps64 + + + ) + +704 #ifdeà +__USE_LARGEFILE64 + + +705  + $mko¡emps64 + (* +__‹m¶©e +,  +__suffixËn +,  +__æags +) + +706 + `__nÚnuÎ + ((1)è +__wur +; + +711 +__BEGIN_NAMESPACE_STD + + +716  + $sy¡em + (cÚ¡ * +__commªd +è +__wur +; + +717 +__END_NAMESPACE_STD + + +720 #ifdef +__USE_GNU + + +723 * + $ÿnÚiÿlize_fže_Çme + (cÚ¡ * +__Çme +) + +724 +__THROW + + `__nÚnuÎ + ((1)è +__wur +; + +727 #ià +defšed + +__USE_MISC + || defšed +__USE_XOPEN_EXTENDED + + +733 * + $»®·th + (cÚ¡ * +__»¡riù + +__Çme +, + +734 * +__»¡riù + +__»sÞved +è +__THROW + +__wur +; + +739 #iâdeà +__COMPAR_FN_T + + +740  + #__COMPAR_FN_T + + + ) + +741 (* + t__com·r_â_t +) (const *, const *); + +743 #ifdef +__USE_GNU + + +744  +__com·r_â_t + + tcom·risÚ_â_t +; + +747 #ifdeà +__USE_GNU + + +748 (* + t__com·r_d_â_t +) (const *, const *, *); + +751 +__BEGIN_NAMESPACE_STD + + +754 * + $b£¬ch + (cÚ¡ * +__key +, cÚ¡ * +__ba£ +, + +755 +size_t + +__nmemb +, size_ˆ +__size +, +__com·r_â_t + +__com·r +) + +756 + `__nÚnuÎ + ((1, 2, 5)è +__wur +; + +758 #ifdeà +__USE_EXTERN_INLINES + + +759  + ~ + +764  + $qsÜt + (* +__ba£ +, +size_t + +__nmemb +, size_ˆ +__size +, + +765 +__com·r_â_t + +__com·r +è + `__nÚnuÎ + ((1, 4)); + +766 #ifdeà +__USE_GNU + + +767  + $qsÜt_r + (* +__ba£ +, +size_t + +__nmemb +, size_ˆ +__size +, + +768 +__com·r_d_â_t + +__com·r +, * +__¬g +) + +769 + `__nÚnuÎ + ((1, 4)); + +774  + $abs + ( +__x +è +__THROW + + `__©Œibu‹__ + (( +__cÚ¡__ +)è +__wur +; + +775  + $Ïbs + ( +__x +è +__THROW + + `__©Œibu‹__ + (( +__cÚ¡__ +)è +__wur +; + +776 +__END_NAMESPACE_STD + + +778 #ifdeà +__USE_ISOC99 + + +779 +__ex‹nsiÚ__ +  + $Îabs + ( +__x +) + +780 +__THROW + + `__©Œibu‹__ + (( +__cÚ¡__ +)è +__wur +; + +784 +__BEGIN_NAMESPACE_STD + + +788 +div_t + + $div + ( +__num” +,  +__d’om +) + +789 +__THROW + + `__©Œibu‹__ + (( +__cÚ¡__ +)è +__wur +; + +790 +ldiv_t + + $ldiv + ( +__num” +,  +__d’om +) + +791 +__THROW + + `__©Œibu‹__ + (( +__cÚ¡__ +)è +__wur +; + +792 +__END_NAMESPACE_STD + + +794 #ifdeà +__USE_ISOC99 + + +795 +__BEGIN_NAMESPACE_C99 + + +796 +__ex‹nsiÚ__ + +Îdiv_t + + $Îdiv + ( +__num” +, + +797  +__d’om +) + +798 +__THROW + + `__©Œibu‹__ + (( +__cÚ¡__ +)è +__wur +; + +799 +__END_NAMESPACE_C99 + + +803 #ià( +defšed + +__USE_XOPEN_EXTENDED + && !defšed +__USE_XOPEN2K8 +) \ + +804 || +defšed + +__USE_MISC + + +811 * + $ecvt + ( +__v®ue +,  +__ndig™ +, * +__»¡riù + +__deýt +, + +812 * +__»¡riù + +__sign +è +__THROW + + `__nÚnuÎ + ((3, 4)è +__wur +; + +817 * + $fcvt + ( +__v®ue +,  +__ndig™ +, * +__»¡riù + +__deýt +, + +818 * +__»¡riù + +__sign +è +__THROW + + `__nÚnuÎ + ((3, 4)è +__wur +; + +823 * + $gcvt + ( +__v®ue +,  +__ndig™ +, * +__buf +) + +824 +__THROW + + `__nÚnuÎ + ((3)è +__wur +; + +827 #ifdeà +__USE_MISC + + +829 * + $qecvt + ( +__v®ue +,  +__ndig™ +, + +830 * +__»¡riù + +__deýt +, *__»¡riù +__sign +) + +831 +__THROW + + `__nÚnuÎ + ((3, 4)è +__wur +; + +832 * + $qfcvt + ( +__v®ue +,  +__ndig™ +, + +833 * +__»¡riù + +__deýt +, *__»¡riù +__sign +) + +834 +__THROW + + `__nÚnuÎ + ((3, 4)è +__wur +; + +835 * + $qgcvt + ( +__v®ue +,  +__ndig™ +, * +__buf +) + +836 +__THROW + + `__nÚnuÎ + ((3)è +__wur +; + +841  + $ecvt_r + ( +__v®ue +,  +__ndig™ +, * +__»¡riù + +__deýt +, + +842 * +__»¡riù + +__sign +, *__»¡riù +__buf +, + +843 +size_t + +__Ën +è +__THROW + + `__nÚnuÎ + ((3, 4, 5)); + +844  + $fcvt_r + ( +__v®ue +,  +__ndig™ +, * +__»¡riù + +__deýt +, + +845 * +__»¡riù + +__sign +, *__»¡riù +__buf +, + +846 +size_t + +__Ën +è +__THROW + + `__nÚnuÎ + ((3, 4, 5)); + +848  + $qecvt_r + ( +__v®ue +,  +__ndig™ +, + +849 * +__»¡riù + +__deýt +, *__»¡riù +__sign +, + +850 * +__»¡riù + +__buf +, +size_t + +__Ën +) + +851 +__THROW + + `__nÚnuÎ + ((3, 4, 5)); + +852  + $qfcvt_r + ( +__v®ue +,  +__ndig™ +, + +853 * +__»¡riù + +__deýt +, *__»¡riù +__sign +, + +854 * +__»¡riù + +__buf +, +size_t + +__Ën +) + +855 +__THROW + + `__nÚnuÎ + ((3, 4, 5)); + +859 +__BEGIN_NAMESPACE_STD + + +862  + $mbËn + (cÚ¡ * +__s +, +size_t + +__n +è +__THROW +; + +865  + $mbtowc + ( +wch¬_t + * +__»¡riù + +__pwc +, + +866 cÚ¡ * +__»¡riù + +__s +, +size_t + +__n +è +__THROW +; + +869  + $wùomb + (* +__s +, +wch¬_t + +__wch¬ +è +__THROW +; + +873 +size_t + + $mb¡owcs + ( +wch¬_t + * +__»¡riù + +__pwcs +, + +874 cÚ¡ * +__»¡riù + +__s +, +size_t + +__n +è +__THROW +; + +876 +size_t + + $wc¡ombs + (* +__»¡riù + +__s +, + +877 cÚ¡ +wch¬_t + * +__»¡riù + +__pwcs +, +size_t + +__n +) + +878 +__THROW +; + +879 +__END_NAMESPACE_STD + + +882 #ifdeà +__USE_MISC + + +887  + $½m©ch + (cÚ¡ * +__»¥Ú£ +è +__THROW + + `__nÚnuÎ + ((1)è +__wur +; + +891 #ià +defšed + +__USE_XOPEN_EXTENDED + || defšed +__USE_XOPEN2K8 + + +898  + $g‘subÝt + (** +__»¡riù + +__ÝtiÚp +, + +899 *cÚ¡ * +__»¡riù + +__tok’s +, + +900 ** +__»¡riù + +__v®u• +) + +901 +__THROW + + `__nÚnuÎ + ((1, 2, 3)è +__wur +; + +905 #ifdeà +__USE_XOPEN + + +907  + $£tkey + (cÚ¡ * +__key +è +__THROW + + `__nÚnuÎ + ((1)); + +913 #ifdeà +__USE_XOPEN2KXSI + + +915  + $posix_Ý’± + ( +__oæag +è +__wur +; + +918 #ifdeà +__USE_XOPEN + + +923  + $g¿Á± + ( +__fd +è +__THROW +; + +927  + $uÆock± + ( +__fd +è +__THROW +; + +932 * + $±¢ame + ( +__fd +è +__THROW + +__wur +; + +935 #ifdeà +__USE_GNU + + +939  + $±¢ame_r + ( +__fd +, * +__buf +, +size_t + +__buæ’ +) + +940 +__THROW + + `__nÚnuÎ + ((2)); + +943  + `g‘± + (); + +946 #ifdeà +__USE_MISC + + +950  + $g‘lßdavg + ( +__lßdavg +[],  +__ÃËm +) + +951 +__THROW + + `__nÚnuÎ + ((1)); + +954  + ~ + +957 #ià +__USE_FORTIFY_LEVEL + > 0 && +defšed + +__fÜtify_funùiÚ + + +958  + ~ + +960 #ifdeà +__LDBL_COMPAT + + +961  + ~ + +965 #undeà +__Ãed_m®loc_ªd_ÿÎoc + + +967 +__END_DECLS + + + @/usr/include/alloca.h + +18 #iâdef +_ALLOCA_H + + +19  + #_ALLOCA_H + 1 + + ) + +21  + ~<ã©u»s.h +> + +23  + #__Ãed_size_t + + + ) + +24  + ~<¡ddef.h +> + +26 + g__BEGIN_DECLS + + +29 #undeà +®loÿ + + +32 * + $®loÿ + ( +size_t + +__size +è +__THROW +; + +34 #ifdef +__GNUC__ + + +35  + #®loÿ +( +size +è + `__bužtš_®loÿ + (size) + + ) + +38 +__END_DECLS + + + @/usr/include/bits/huge_val.h + +20 #iâdeà +_MATH_H + + +26 #ià +__GNUC_PREREQ +(3,3) + +27  + #HUGE_VAL + ( + `__bužtš_huge_v® +()) + + ) + +28 #–ià +__GNUC_PREREQ +(2,96) + +29  + #HUGE_VAL + ( +__ex‹nsiÚ__ + 0x1.0 +p2047 +) + + ) + +30 #–ià +defšed + +__GNUC__ + + +32  + #HUGE_VAL + \ + +33 ( +__ex‹nsiÚ__ + \ + +34 ((uniÚ {  +__l + + `__©Œibu‹__ +(( + `__mode__ +( +__DI__ +)));  +__d +; }) \ + +35 { +__l +: 0x7ff0000000000000ULL }). +__d +) + + ) + +39  + ~<’dŸn.h +> + +41 uniÚ {  + m__c +[8];  + m__d +; } + t__huge_v®_t +; + +43 #ià +__BYTE_ORDER + =ð +__BIG_ENDIAN + + +44  + #__HUGE_VAL_by‹s + { 0x7f, 0xf0, 0, 0, 0, 0, 0, 0 } + + ) + +46 #ià +__BYTE_ORDER + =ð +__LITTLE_ENDIAN + + +47  + #__HUGE_VAL_by‹s + { 0, 0, 0, 0, 0, 0, 0xf0, 0x7à} + + ) + +50  +__huge_v®_t + + g__huge_v® + = { +__HUGE_VAL_by‹s + }; + +51  + #HUGE_VAL + ( +__huge_v® +. +__d +) + + ) + + @/usr/include/bits/huge_valf.h + +20 #iâdeà +_MATH_H + + +26 #ià +__GNUC_PREREQ +(3,3) + +27  + #HUGE_VALF + ( + `__bužtš_huge_v®f +()) + + ) + +28 #–ià +__GNUC_PREREQ +(2,96) + +29  + #HUGE_VALF + ( +__ex‹nsiÚ__ + 0x1.0 +p255f +) + + ) + +30 #–ià +defšed + +__GNUC__ + + +32  + #HUGE_VALF + \ + +33 ( +__ex‹nsiÚ__ + \ + +34 ((uniÚ {  +__l + + `__©Œibu‹__ +(( + `__mode__ +( +__SI__ +)));  +__d +; }) \ + +35 { +__l +: 0x7f800000UL }). +__d +) + + ) + +39 uniÚ {  + m__c +[4];  + m__f +; } + t__huge_v®f_t +; + +41 #ià +__BYTE_ORDER + =ð +__BIG_ENDIAN + + +42  + #__HUGE_VALF_by‹s + { 0x7f, 0x80, 0, 0 } + + ) + +44 #ià +__BYTE_ORDER + =ð +__LITTLE_ENDIAN + + +45  + #__HUGE_VALF_by‹s + { 0, 0, 0x80, 0x7à} + + ) + +48  +__huge_v®f_t + + g__huge_v®f + = { +__HUGE_VALF_by‹s + }; + +49  + #HUGE_VALF + ( +__huge_v®f +. +__f +) + + ) + + @/usr/include/bits/huge_vall.h + +20 #iâdeà +_MATH_H + + +24 #ià +__GNUC_PREREQ +(3,3) + +25  + #HUGE_VALL + ( + `__bužtš_huge_v®l +()) + + ) + +26 #–ià +__GNUC_PREREQ +(2,96) + +27  + #HUGE_VALL + ( +__ex‹nsiÚ__ + 0x1.0 +p32767L +) + + ) + +30  + #__HUGE_VALL_by‹s + { 0, 0, 0, 0, 0, 0, 0, 0x80, 0xff, 0x7f, 0, 0 } + + ) + +32  + #__huge_v®l_t + uniÚ {  +__c +[12];  +__ld +; } + + ) + +33 #ifdeà +__GNUC__ + + +34  + #HUGE_VALL + ( +__ex‹nsiÚ__ + \ + +35 (( +__huge_v®l_t +è{ +__c +: +__HUGE_VALL_by‹s + }). +__ld +) + + ) + +37  +__huge_v®l_t + + g__huge_v®l + = { +__HUGE_VALL_by‹s + }; + +38  + #HUGE_VALL + ( +__huge_v®l +. +__ld +) + + ) + + @/usr/include/bits/inf.h + +19 #iâdeà +_MATH_H + + +25 #ià +__GNUC_PREREQ +(3,3) + +26  + #INFINITY + ( + `__bužtš_šff +()) + + ) + +28  + #INFINITY + +HUGE_VALF + + + ) + + @/usr/include/bits/math-finite.h + +19 #iâdeà +_MATH_H + + +24  +__REDIRECT_NTH + ( +acos +, (), +__acos_fš™e +); + +25 #ifdeà +__USE_ISOC99 + + +26  +__REDIRECT_NTH + ( +acosf +, (), +__acosf_fš™e +); + +27 #ifdeà +__MATH_DECLARE_LDOUBLE + + +28 #ifdeà +__NO_LONG_DOUBLE_MATH + + +29  +__REDIRECT_NTH + ( +aco¦ +, (), +__acos_fš™e +); + +31  +__REDIRECT_NTH + ( +aco¦ +, (), +__aco¦_fš™e +); + +36 #ià +defšed + +__USE_XOPEN_EXTENDED + || defšed +__USE_ISOC99 + + +38  +__REDIRECT_NTH + ( +acosh +, (), +__acosh_fš™e +); + +40 #ifdeà +__USE_ISOC99 + + +41  +__REDIRECT_NTH + ( +acoshf +, (), +__acoshf_fš™e +); + +42 #ifdeà +__MATH_DECLARE_LDOUBLE + + +43 #ifdeà +__NO_LONG_DOUBLE_MATH + + +44  +__REDIRECT_NTH + ( +acoshl +, (), +__acosh_fš™e +); + +46  +__REDIRECT_NTH + ( +acoshl +, (), +__acoshl_fš™e +); + +52  +__REDIRECT_NTH + ( +asš +, (), +__asš_fš™e +); + +53 #ifdeà +__USE_ISOC99 + + +54  +__REDIRECT_NTH + ( +asšf +, (), +__asšf_fš™e +); + +55 #ifdeà +__MATH_DECLARE_LDOUBLE + + +56 #ifdeà +__NO_LONG_DOUBLE_MATH + + +57  +__REDIRECT_NTH + ( +asšl +, (), +__asš_fš™e +); + +59  +__REDIRECT_NTH + ( +asšl +, (), +__asšl_fš™e +); + +65  +__REDIRECT_NTH + ( +©ª2 +, (, ), +__©ª2_fš™e +); + +66 #ifdeà +__USE_ISOC99 + + +67  +__REDIRECT_NTH + ( +©ª2f +, (, ), +__©ª2f_fš™e +); + +68 #ifdeà +__MATH_DECLARE_LDOUBLE + + +69 #ifdeà +__NO_LONG_DOUBLE_MATH + + +70  +__REDIRECT_NTH + ( +©ª2l +, (, ), + +71 +__©ª2_fš™e +); + +73  +__REDIRECT_NTH + ( +©ª2l +, (, ), + +74 +__©ª2l_fš™e +); + +79 #ià +defšed + +__USE_XOPEN_EXTENDED + || defšed +__USE_ISOC99 + + +81  +__REDIRECT_NTH + ( +©ªh +, (), +__©ªh_fš™e +); + +83 #ifdeà +__USE_ISOC99 + + +84  +__REDIRECT_NTH + ( +©ªhf +, (), +__©ªhf_fš™e +); + +85 #ifdeà +__MATH_DECLARE_LDOUBLE + + +86 #ifdeà +__NO_LONG_DOUBLE_MATH + + +87  +__REDIRECT_NTH + ( +©ªhl +, (), +__©ªh_fš™e +); + +89  +__REDIRECT_NTH + ( +©ªhl +, (), +__©ªhl_fš™e +); + +95  +__REDIRECT_NTH + ( +cosh +, (), +__cosh_fš™e +); + +96 #ifdeà +__USE_ISOC99 + + +97  +__REDIRECT_NTH + ( +coshf +, (), +__coshf_fš™e +); + +98 #ifdeà +__MATH_DECLARE_LDOUBLE + + +99 #ifdeà +__NO_LONG_DOUBLE_MATH + + +100  +__REDIRECT_NTH + ( +coshl +, (), +__cosh_fš™e +); + +102  +__REDIRECT_NTH + ( +coshl +, (), +__coshl_fš™e +); + +108  +__REDIRECT_NTH + ( +exp +, (), +__exp_fš™e +); + +109 #ifdeà +__USE_ISOC99 + + +110  +__REDIRECT_NTH + ( +expf +, (), +__expf_fš™e +); + +111 #ifdeà +__MATH_DECLARE_LDOUBLE + + +112 #ifdeà +__NO_LONG_DOUBLE_MATH + + +113  +__REDIRECT_NTH + ( +ex¶ +, (), +__exp_fš™e +); + +115  +__REDIRECT_NTH + ( +ex¶ +, (), +__ex¶_fš™e +); + +120 #ifdeà +__USE_GNU + + +122  +__REDIRECT_NTH + ( +exp10 +, (), +__exp10_fš™e +); + +123  +__REDIRECT_NTH + ( +exp10f +, (), +__exp10f_fš™e +); + +124 #ifdeà +__MATH_DECLARE_LDOUBLE + + +125 #ifdeà +__NO_LONG_DOUBLE_MATH + + +126  +__REDIRECT_NTH + ( +exp10l +, (), +__exp10_fš™e +); + +128  +__REDIRECT_NTH + ( +exp10l +, (), +__exp10l_fš™e +); + +133  +__REDIRECT_NTH + ( +pow10 +, (), +__exp10_fš™e +); + +134  +__REDIRECT_NTH + ( +pow10f +, (), +__exp10f_fš™e +); + +135 #ifdeà +__MATH_DECLARE_LDOUBLE + + +136 #ifdeà +__NO_LONG_DOUBLE_MATH + + +137  +__REDIRECT_NTH + ( +pow10l +, (), +__exp10_fš™e +); + +139  +__REDIRECT_NTH + ( +pow10l +, (), +__exp10l_fš™e +); + +144 #ifdeà +__USE_ISOC99 + + +146  +__REDIRECT_NTH + ( +exp2 +, (), +__exp2_fš™e +); + +147  +__REDIRECT_NTH + ( +exp2f +, (), +__exp2f_fš™e +); + +148 #ifdeà +__MATH_DECLARE_LDOUBLE + + +149 #ifdeà +__NO_LONG_DOUBLE_MATH + + +150  +__REDIRECT_NTH + ( +exp2l +, (), +__exp2_fš™e +); + +152  +__REDIRECT_NTH + ( +exp2l +, (), +__exp2l_fš™e +); + +158  +__REDIRECT_NTH + ( +fmod +, (, ), +__fmod_fš™e +); + +159 #ifdeà +__USE_ISOC99 + + +160  +__REDIRECT_NTH + ( +fmodf +, (, ), +__fmodf_fš™e +); + +161 #ifdeà +__MATH_DECLARE_LDOUBLE + + +162 #ifdeà +__NO_LONG_DOUBLE_MATH + + +163  +__REDIRECT_NTH + ( +fmodl +, (, ), + +164 +__fmod_fš™e +); + +166  +__REDIRECT_NTH + ( +fmodl +, (, ), + +167 +__fmodl_fš™e +); + +172 #ià +defšed + +__USE_XOPEN + || defšed +__USE_ISOC99 + + +174  +__REDIRECT_NTH + ( +hypÙ +, (, ), +__hypÙ_fš™e +); + +176 #ifdeà +__USE_ISOC99 + + +177  +__REDIRECT_NTH + ( +hypÙf +, (, ), +__hypÙf_fš™e +); + +178 #ifdeà +__MATH_DECLARE_LDOUBLE + + +179 #ifdeà +__NO_LONG_DOUBLE_MATH + + +180  +__REDIRECT_NTH + ( +hypÙl +, (, ), + +181 +__hypÙ_fš™e +); + +183  +__REDIRECT_NTH + ( +hypÙl +, (, ), + +184 +__hypÙl_fš™e +); + +189 #ià +defšed + +__USE_MISC + || defšed +__USE_XOPEN + + +191  +__REDIRECT_NTH + ( +j0 +, (), +__j0_fš™e +); + +193 #ià +defšed + +__USE_MISC + && defšed +__USE_ISOC99 + + +194  +__REDIRECT_NTH + ( +j0f +, (), +__j0f_fš™e +); + +195 #ifdeà +__MATH_DECLARE_LDOUBLE + + +196 #ifdeà +__NO_LONG_DOUBLE_MATH + + +197  +__REDIRECT_NTH + ( +j0l +, (), +__j0_fš™e +); + +199  +__REDIRECT_NTH + ( +j0l +, (), +__j0l_fš™e +); + +204 #ià +defšed + +__USE_MISC + || defšed +__USE_XOPEN + + +206  +__REDIRECT_NTH + ( +y0 +, (), +__y0_fš™e +); + +208 #ià +defšed + +__USE_MISC + && defšed +__USE_ISOC99 + + +209  +__REDIRECT_NTH + ( +y0f +, (), +__y0f_fš™e +); + +210 #ifdeà +__MATH_DECLARE_LDOUBLE + + +211 #ifdeà +__NO_LONG_DOUBLE_MATH + + +212  +__REDIRECT_NTH + ( +y0l +, (), +__y0_fš™e +); + +214  +__REDIRECT_NTH + ( +y0l +, (), +__y0l_fš™e +); + +219 #ià +defšed + +__USE_MISC + || defšed +__USE_XOPEN + + +221  +__REDIRECT_NTH + ( +j1 +, (), +__j1_fš™e +); + +223 #ià +defšed + +__USE_MISC + && defšed +__USE_ISOC99 + + +224  +__REDIRECT_NTH + ( +j1f +, (), +__j1f_fš™e +); + +225 #ifdeà +__MATH_DECLARE_LDOUBLE + + +226 #ifdeà +__NO_LONG_DOUBLE_MATH + + +227  +__REDIRECT_NTH + ( +j1l +, (), +__j1_fš™e +); + +229  +__REDIRECT_NTH + ( +j1l +, (), +__j1l_fš™e +); + +234 #ià +defšed + +__USE_MISC + || defšed +__USE_XOPEN + + +236  +__REDIRECT_NTH + ( +y1 +, (), +__y1_fš™e +); + +238 #ià +defšed + +__USE_MISC + && defšed +__USE_ISOC99 + + +239  +__REDIRECT_NTH + ( +y1f +, (), +__y1f_fš™e +); + +240 #ifdeà +__MATH_DECLARE_LDOUBLE + + +241 #ifdeà +__NO_LONG_DOUBLE_MATH + + +242  +__REDIRECT_NTH + ( +y1l +, (), +__y1_fš™e +); + +244  +__REDIRECT_NTH + ( +y1l +, (), +__y1l_fš™e +); + +249 #ià +defšed + +__USE_MISC + || defšed +__USE_XOPEN + + +251  +__REDIRECT_NTH + ( +jn +, (, ), +__jn_fš™e +); + +253 #ià +defšed + +__USE_MISC + && defšed +__USE_ISOC99 + + +254  +__REDIRECT_NTH + ( +jnf +, (, ), +__jnf_fš™e +); + +255 #ifdeà +__MATH_DECLARE_LDOUBLE + + +256 #ifdeà +__NO_LONG_DOUBLE_MATH + + +257  +__REDIRECT_NTH + ( +jÆ +, (, ), +__jn_fš™e +); + +259  +__REDIRECT_NTH + ( +jÆ +, (, ), +__jÆ_fš™e +); + +264 #ià +defšed + +__USE_MISC + || defšed +__USE_XOPEN + + +266  +__REDIRECT_NTH + ( +yn +, (, ), +__yn_fš™e +); + +268 #ià +defšed + +__USE_MISC + && defšed +__USE_ISOC99 + + +269  +__REDIRECT_NTH + ( +ynf +, (, ), +__ynf_fš™e +); + +270 #ifdeà +__MATH_DECLARE_LDOUBLE + + +271 #ifdeà +__NO_LONG_DOUBLE_MATH + + +272  +__REDIRECT_NTH + ( +yÆ +, (, ), +__yn_fš™e +); + +274  +__REDIRECT_NTH + ( +yÆ +, (, ), +__yÆ_fš™e +); + +279 #ifdeà +__USE_MISC + + +281  +__REDIRECT_NTH + ( +lgamma_r +, (, *), +__lgamma_r_fš™e +); + +282 #ifdeà +__USE_ISOC99 + + +283  +__REDIRECT_NTH + ( +lgammaf_r +, (, *), +__lgammaf_r_fš™e +); + +284 #ifdeà +__MATH_DECLARE_LDOUBLE + + +285 #ifdeà +__NO_LONG_DOUBLE_MATH + + +286  +__REDIRECT_NTH + ( +lgamm®_r +, (, *), + +287 +__lgamma_r_fš™e +); + +289  +__REDIRECT_NTH + ( +lgamm®_r +, (, *), + +290 +__lgamm®_r_fš™e +); + +296  +__lgamma_r_fš™e + (, *); + +297  +__lgammaf_r_fš™e + (, *); + +298 #ifdeà +__NO_LONG_DOUBLE_MATH + + +299  +__REDIRECT_NTH + ( +__lgamm®_r_fš™e +, (, *), + +300 +__lgamma_r_fš™e +); + +302  +__lgamm®_r_fš™e + (, *); + +305 #ià(( +defšed + +__USE_XOPEN + || defšed +__USE_ISOC99 +) \ + +306 && +defšed + + g__ex‹º_®ways_šlše +) + +308 +__ex‹º_®ways_šlše +  +__NTH + ( + $lgamma + ( +__d +)) + +310 #ià +defšed + +__USE_MISC + || defšed +__USE_XOPEN + + +311  + `__lgamma_r_fš™e + ( +__d +, & +signgam +); + +313  +__loÿl_signgam + = 0; + +314  + `__lgamma_r_fš™e + ( +__d +, & +__loÿl_signgam +); + +316 + } +} + +318 #ià +defšed + +__USE_ISOC99 + && defšed +__ex‹º_®ways_šlše + + +319 +__ex‹º_®ways_šlše +  +__NTH + ( + $lgammaf + ( +__d +)) + +321 #ià +defšed + +__USE_MISC + || defšed +__USE_XOPEN + + +322  + `__lgammaf_r_fš™e + ( +__d +, & +signgam +); + +324  +__loÿl_signgam + = 0; + +325  + `__lgammaf_r_fš™e + ( +__d +, & +__loÿl_signgam +); + +327 + } +} + +328 #ifdeà +__MATH_DECLARE_LDOUBLE + + +329 +__ex‹º_®ways_šlše +  +__NTH + ( + $lgamm® + ( +__d +)) + +331 #ià +defšed + +__USE_MISC + || defšed +__USE_XOPEN + + +332  + `__lgamm®_r_fš™e + ( +__d +, & +signgam +); + +334  +__loÿl_signgam + = 0; + +335  + `__lgamm®_r_fš™e + ( +__d +, & +__loÿl_signgam +); + +337 + } +} + +341 #ià(( +defšed + +__USE_MISC + || (defšed +__USE_XOPEN + && !defšed +__USE_XOPEN2K +)) \ + +342 && +defšed + + g__ex‹º_®ways_šlše +) + +344 +__ex‹º_®ways_šlše +  +__NTH + ( + $gamma + ( +__d +)) + +346  + `__lgamma_r_fš™e + ( +__d +, & +signgam +); + +347 + } +} + +348 #ifdeà +__USE_ISOC99 + + +349 +__ex‹º_®ways_šlše +  +__NTH + ( + $gammaf + ( +__d +)) + +351  + `__lgammaf_r_fš™e + ( +__d +, & +signgam +); + +352 + } +} + +353 #ifdeà +__MATH_DECLARE_LDOUBLE + + +354 +__ex‹º_®ways_šlše +  +__NTH + ( + $gamm® + ( +__d +)) + +356  + `__lgamm®_r_fš™e + ( +__d +, & +signgam +); + +357 + } +} + +363  +__REDIRECT_NTH + ( +log +, (), +__log_fš™e +); + +364 #ifdeà +__USE_ISOC99 + + +365  +__REDIRECT_NTH + ( +logf +, (), +__logf_fš™e +); + +366 #ifdeà +__MATH_DECLARE_LDOUBLE + + +367 #ifdeà +__NO_LONG_DOUBLE_MATH + + +368  +__REDIRECT_NTH + ( +logl +, (), +__log_fš™e +); + +370  +__REDIRECT_NTH + ( +logl +, (), +__logl_fš™e +); + +376  +__REDIRECT_NTH + ( +log10 +, (), +__log10_fš™e +); + +377 #ifdeà +__USE_ISOC99 + + +378  +__REDIRECT_NTH + ( +log10f +, (), +__log10f_fš™e +); + +379 #ifdeà +__MATH_DECLARE_LDOUBLE + + +380 #ifdeà +__NO_LONG_DOUBLE_MATH + + +381  +__REDIRECT_NTH + ( +log10l +, (), +__log10_fš™e +); + +383  +__REDIRECT_NTH + ( +log10l +, (), +__log10l_fš™e +); + +388 #ifdeà +__USE_ISOC99 + + +390  +__REDIRECT_NTH + ( +log2 +, (), +__log2_fš™e +); + +391  +__REDIRECT_NTH + ( +log2f +, (), +__log2f_fš™e +); + +392 #ifdeà +__MATH_DECLARE_LDOUBLE + + +393 #ifdeà +__NO_LONG_DOUBLE_MATH + + +394  +__REDIRECT_NTH + ( +log2l +, (), +__log2_fš™e +); + +396  +__REDIRECT_NTH + ( +log2l +, (), +__log2l_fš™e +); + +402  +__REDIRECT_NTH + ( +pow +, (, ), +__pow_fš™e +); + +403 #ifdeà +__USE_ISOC99 + + +404  +__REDIRECT_NTH + ( +powf +, (, ), +__powf_fš™e +); + +405 #ifdeà +__MATH_DECLARE_LDOUBLE + + +406 #ifdeà +__NO_LONG_DOUBLE_MATH + + +407  +__REDIRECT_NTH + ( +powl +, (, ), + +408 +__pow_fš™e +); + +410  +__REDIRECT_NTH + ( +powl +, (, ), + +411 +__powl_fš™e +); + +416 #ià +defšed + +__USE_XOPEN_EXTENDED + || defšed +__USE_ISOC99 + + +418  +__REDIRECT_NTH + ( +»mašd” +, (, ), +__»mašd”_fš™e +); + +420 #ifdeà +__USE_ISOC99 + + +421  +__REDIRECT_NTH + ( +»mašd”f +, (, ), +__»mašd”f_fš™e +); + +422 #ifdeà +__MATH_DECLARE_LDOUBLE + + +423 #ifdeà +__NO_LONG_DOUBLE_MATH + + +424  +__REDIRECT_NTH + ( +»mašd”l +, (, ), + +425 +__»mašd”_fš™e +); + +427  +__REDIRECT_NTH + ( +»mašd”l +, (, ), + +428 +__»mašd”l_fš™e +); + +433 #ià( +defšed + +__USE_MISC + \ + +434 || ( +defšed + + g__USE_XOPEN_EXTENDED + && !defšed + g__USE_XOPEN2K8 +)) + +436  +__REDIRECT_NTH + ( +sÿlb +, (, ), +__sÿlb_fš™e +); + +438 #ià +defšed + +__USE_MISC + && defšed +__USE_ISOC99 + + +439  +__REDIRECT_NTH + ( +sÿlbf +, (, ), +__sÿlbf_fš™e +); + +440 #ifdeà +__MATH_DECLARE_LDOUBLE + + +441 #ifdeà +__NO_LONG_DOUBLE_MATH + + +442  +__REDIRECT_NTH + ( +sÿlbl +, (, ), + +443 +__sÿlb_fš™e +); + +445  +__REDIRECT_NTH + ( +sÿlbl +, (, ), + +446 +__sÿlbl_fš™e +); + +452  +__REDIRECT_NTH + ( +sšh +, (), +__sšh_fš™e +); + +453 #ifdeà +__USE_ISOC99 + + +454  +__REDIRECT_NTH + ( +sšhf +, (), +__sšhf_fš™e +); + +455 #ifdeà +__MATH_DECLARE_LDOUBLE + + +456 #ifdeà +__NO_LONG_DOUBLE_MATH + + +457  +__REDIRECT_NTH + ( +sšhl +, (), +__sšh_fš™e +); + +459  +__REDIRECT_NTH + ( +sšhl +, (), +__sšhl_fš™e +); + +465  +__REDIRECT_NTH + ( +sq¹ +, (), +__sq¹_fš™e +); + +466 #ifdeà +__USE_ISOC99 + + +467  +__REDIRECT_NTH + ( +sq¹f +, (), +__sq¹f_fš™e +); + +468 #ifdeà +__MATH_DECLARE_LDOUBLE + + +469 #ifdeà +__NO_LONG_DOUBLE_MATH + + +470  +__REDIRECT_NTH + ( +sq¹l +, (), +__sq¹_fš™e +); + +472  +__REDIRECT_NTH + ( +sq¹l +, (), +__sq¹l_fš™e +); + +477 #ià +defšed + +__USE_ISOC99 + && defšed +__ex‹º_®ways_šlše + + +479  +__gamma_r_fš™e + (, *); + +480 +__ex‹º_®ways_šlše +  +__NTH + ( + $tgamma + ( +__d +)) + +482  +__loÿl_signgam + = 0; + +483  +__»s + = + `__gamma_r_fš™e + ( +__d +, & +__loÿl_signgam +); + +484  +__loÿl_signgam + < 0 ? - +__»s + : __res; + +485 + } +} + +486  +__gammaf_r_fš™e + (, *); + +487 +__ex‹º_®ways_šlše +  +__NTH + ( + $tgammaf + ( +__d +)) + +489  +__loÿl_signgam + = 0; + +490  +__»s + = + `__gammaf_r_fš™e + ( +__d +, & +__loÿl_signgam +); + +491  +__loÿl_signgam + < 0 ? - +__»s + : __res; + +492 + } +} + +493 #ifdeà +__MATH_DECLARE_LDOUBLE + + +494  +__gamm®_r_fš™e + (, *); + +495 +__ex‹º_®ways_šlše +  +__NTH + ( + $tgamm® + ( +__d +)) + +497  +__loÿl_signgam + = 0; + +498 #ifdeà +__NO_LONG_DOUBLE_MATH + + +499  +__»s + = + `__gamma_r_fš™e + ( +__d +, & +__loÿl_signgam +); + +501  +__»s + = + `__gamm®_r_fš™e + ( +__d +, & +__loÿl_signgam +); + +503  +__loÿl_signgam + < 0 ? - +__»s + : __res; + +504 + } +} + + @/usr/include/bits/math-vector.h + +19 #iâdeà +_MATH_H + + +25  + ~ + +27 #ià +defšed + +__x86_64__ + && defšed +__FAST_MATH__ + + +28 #ià +defšed + +_OPENMP + && _OPENMP >= 201307 + +30  + #__DECL_SIMD_x86_64 + + `_P¿gma + ("om°deþ¬simd‚Ùšb¿nch") + + ) + +31 #–ià +__GNUC_PREREQ + (6,0) + +33  + #__DECL_SIMD_x86_64 + + `__©Œibu‹__ + (( + `__simd__ + ("nÙšb¿nch"))) + + ) + +36 #ifdeà +__DECL_SIMD_x86_64 + + +37 #undeà +__DECL_SIMD_cos + + +38  + #__DECL_SIMD_cos + +__DECL_SIMD_x86_64 + + + ) + +39 #undeà +__DECL_SIMD_cosf + + +40  + #__DECL_SIMD_cosf + +__DECL_SIMD_x86_64 + + + ) + +41 #undeà +__DECL_SIMD_sš + + +42  + #__DECL_SIMD_sš + +__DECL_SIMD_x86_64 + + + ) + +43 #undeà +__DECL_SIMD_sšf + + +44  + #__DECL_SIMD_sšf + +__DECL_SIMD_x86_64 + + + ) + +45 #undeà +__DECL_SIMD_sšcos + + +46  + #__DECL_SIMD_sšcos + +__DECL_SIMD_x86_64 + + + ) + +47 #undeà +__DECL_SIMD_sšcosf + + +48  + #__DECL_SIMD_sšcosf + +__DECL_SIMD_x86_64 + + + ) + +49 #undeà +__DECL_SIMD_log + + +50  + #__DECL_SIMD_log + +__DECL_SIMD_x86_64 + + + ) + +51 #undeà +__DECL_SIMD_logf + + +52  + #__DECL_SIMD_logf + +__DECL_SIMD_x86_64 + + + ) + +53 #undeà +__DECL_SIMD_exp + + +54  + #__DECL_SIMD_exp + +__DECL_SIMD_x86_64 + + + ) + +55 #undeà +__DECL_SIMD_expf + + +56  + #__DECL_SIMD_expf + +__DECL_SIMD_x86_64 + + + ) + +57 #undeà +__DECL_SIMD_pow + + +58  + #__DECL_SIMD_pow + +__DECL_SIMD_x86_64 + + + ) + +59 #undeà +__DECL_SIMD_powf + + +60  + #__DECL_SIMD_powf + +__DECL_SIMD_x86_64 + + + ) + + @/usr/include/bits/mathcalls.h + +45 #iâdeà +_MATH_H + + +52 +_MdoubË_BEGIN_NAMESPACE + + +54 +__MATHCALL + ( +acos +,, ( +_MdoubË_ + +__x +)); + +56 +__MATHCALL + ( +asš +,, ( +_MdoubË_ + +__x +)); + +58 +__MATHCALL + ( +©ª +,, ( +_MdoubË_ + +__x +)); + +60 +__MATHCALL + ( +©ª2 +,, ( +_MdoubË_ + +__y +, _MdoubË_ +__x +)); + +63 +__MATHCALL_VEC + ( +cos +,, ( +_MdoubË_ + +__x +)); + +65 +__MATHCALL_VEC + ( +sš +,, ( +_MdoubË_ + +__x +)); + +67 +__MATHCALL + ( +n +,, ( +_MdoubË_ + +__x +)); + +72 +__MATHCALL + ( +cosh +,, ( +_MdoubË_ + +__x +)); + +74 +__MATHCALL + ( +sšh +,, ( +_MdoubË_ + +__x +)); + +76 +__MATHCALL + ( +nh +,, ( +_MdoubË_ + +__x +)); + +77 + g_MdoubË_END_NAMESPACE + + +79 #ifdeà +__USE_GNU + + +81 +__MATHDECL_VEC + (, +sšcos +,, + +82 ( +_MdoubË_ + +__x +, _MdoubË_ * +__sšx +, _MdoubË_ * +__cosx +)); + +85 #ià +defšed + +__USE_XOPEN_EXTENDED + || defšed +__USE_ISOC99 + + +86 +__BEGIN_NAMESPACE_C99 + + +88 +__MATHCALL + ( +acosh +,, ( +_MdoubË_ + +__x +)); + +90 +__MATHCALL + ( +asšh +,, ( +_MdoubË_ + +__x +)); + +92 +__MATHCALL + ( +©ªh +,, ( +_MdoubË_ + +__x +)); + +93 + g__END_NAMESPACE_C99 + + +98 +_MdoubË_BEGIN_NAMESPACE + + +100 +__MATHCALL_VEC + ( +exp +,, ( +_MdoubË_ + +__x +)); + +103 +__MATHCALL + ( +äexp +,, ( +_MdoubË_ + +__x +, * +__expÚ’t +)); + +106 +__MATHCALL + ( +ldexp +,, ( +_MdoubË_ + +__x +,  +__expÚ’t +)); + +109 +__MATHCALL_VEC + ( +log +,, ( +_MdoubË_ + +__x +)); + +112 +__MATHCALL + ( +log10 +,, ( +_MdoubË_ + +__x +)); + +115 +__MATHCALL + ( +modf +,, ( +_MdoubË_ + +__x +, _MdoubË_ * +__Œ +)è +__nÚnuÎ + ((2)); + +116 + g_MdoubË_END_NAMESPACE + + +118 #ifdeà +__USE_GNU + + +120 +__MATHCALL + ( +exp10 +,, ( +_MdoubË_ + +__x +)); + +122 +__MATHCALL + ( +pow10 +,, ( +_MdoubË_ + +__x +)); + +125 #ià +defšed + +__USE_XOPEN_EXTENDED + || defšed +__USE_ISOC99 + + +126 +__BEGIN_NAMESPACE_C99 + + +128 +__MATHCALL + ( +expm1 +,, ( +_MdoubË_ + +__x +)); + +131 +__MATHCALL + ( +log1p +,, ( +_MdoubË_ + +__x +)); + +134 +__MATHCALL + ( +logb +,, ( +_MdoubË_ + +__x +)); + +135 + g__END_NAMESPACE_C99 + + +138 #ifdeà +__USE_ISOC99 + + +139 +__BEGIN_NAMESPACE_C99 + + +141 +__MATHCALL + ( +exp2 +,, ( +_MdoubË_ + +__x +)); + +144 +__MATHCALL + ( +log2 +,, ( +_MdoubË_ + +__x +)); + +145 + g__END_NAMESPACE_C99 + + +151 +_MdoubË_BEGIN_NAMESPACE + + +153 +__MATHCALL_VEC + ( +pow +,, ( +_MdoubË_ + +__x +, _MdoubË_ +__y +)); + +156 +__MATHCALL + ( +sq¹ +,, ( +_MdoubË_ + +__x +)); + +157 + g_MdoubË_END_NAMESPACE + + +159 #ià +defšed + +__USE_XOPEN + || defšed +__USE_ISOC99 + + +160 +__BEGIN_NAMESPACE_C99 + + +162 +__MATHCALL + ( +hypÙ +,, ( +_MdoubË_ + +__x +, _MdoubË_ +__y +)); + +163 + g__END_NAMESPACE_C99 + + +166 #ià +defšed + +__USE_XOPEN_EXTENDED + || defšed +__USE_ISOC99 + + +167 +__BEGIN_NAMESPACE_C99 + + +169 +__MATHCALL + ( +cb¹ +,, ( +_MdoubË_ + +__x +)); + +170 + g__END_NAMESPACE_C99 + + +176 +_MdoubË_BEGIN_NAMESPACE + + +178 +__MATHCALLX + ( +ûž +,, ( +_MdoubË_ + +__x +), ( +__cÚ¡__ +)); + +181 +__MATHCALLX + ( +çbs +,, ( +_MdoubË_ + +__x +), ( +__cÚ¡__ +)); + +184 +__MATHCALLX + ( +æoÜ +,, ( +_MdoubË_ + +__x +), ( +__cÚ¡__ +)); + +187 +__MATHCALL + ( +fmod +,, ( +_MdoubË_ + +__x +, _MdoubË_ +__y +)); + +192 +__MATHDECL_1 + (, +__isšf +,, ( +_MdoubË_ + +__v®ue +)è +__©Œibu‹__ + (( +__cÚ¡__ +)); + +195 +__MATHDECL_1 + (, +__fš™e +,, ( +_MdoubË_ + +__v®ue +)è +__©Œibu‹__ + (( +__cÚ¡__ +)); + +196 + g_MdoubË_END_NAMESPACE + + +198 #ifdeà +__USE_MISC + + +199 #ià(! +defšed + +__ýlu¥lus + \ + +200 || + g__ýlu¥lus + < 201103L \ + +201 || + g__MATH_DECLARING_DOUBLE + == 0) + +204 +__MATHDECL_1 + (, +isšf +,, ( +_MdoubË_ + +__v®ue +)è +__©Œibu‹__ + (( +__cÚ¡__ +)); + +208 +__MATHDECL_1 + (, +fš™e +,, ( +_MdoubË_ + +__v®ue +)è +__©Œibu‹__ + (( +__cÚ¡__ +)); + +211 +__MATHCALL + ( +d»m +,, ( +_MdoubË_ + +__x +, _MdoubË_ +__y +)); + +215 +__MATHCALL + ( +signifiÿnd +,, ( +_MdoubË_ + +__x +)); + +218 #ifdeà +__USE_ISOC99 + + +219 +__BEGIN_NAMESPACE_C99 + + +221 +__MATHCALLX + ( +cÝysign +,, ( +_MdoubË_ + +__x +, _MdoubË_ +__y +), ( +__cÚ¡__ +)); + +222 + g__END_NAMESPACE_C99 + + +225 #ifdeà +__USE_ISOC99 + + +226 +__BEGIN_NAMESPACE_C99 + + +228 +__MATHCALLX + ( +Çn +,, (cÚ¡ * +__gb +), ( +__cÚ¡__ +)); + +229 + g__END_NAMESPACE_C99 + + +234 +__MATHDECL_1 + (, +__i¢ª +,, ( +_MdoubË_ + +__v®ue +)è +__©Œibu‹__ + (( +__cÚ¡__ +)); + +236 #ià +defšed + +__USE_MISC + || (defšed +__USE_XOPEN + && !defšed +__USE_XOPEN2K +) + +237 #ià(! +defšed + +__ýlu¥lus + \ + +238 || + g__ýlu¥lus + < 201103L \ + +239 || + g__MATH_DECLARING_DOUBLE + == 0) + +241 +__MATHDECL_1 + (, +i¢ª +,, ( +_MdoubË_ + +__v®ue +)è +__©Œibu‹__ + (( +__cÚ¡__ +)); + +245 #ià +defšed + +__USE_MISC + || (defšed +__USE_XOPEN + && +__MATH_DECLARING_DOUBLE +) + +247 +__MATHCALL + ( +j0 +,, ( +_MdoubË_ +)); + +248 +__MATHCALL + ( +j1 +,, ( +_MdoubË_ +)); + +249 +__MATHCALL + ( +jn +,, (, +_MdoubË_ +)); + +250 +__MATHCALL + ( +y0 +,, ( +_MdoubË_ +)); + +251 +__MATHCALL + ( +y1 +,, ( +_MdoubË_ +)); + +252 +__MATHCALL + ( +yn +,, (, +_MdoubË_ +)); + +256 #ià +defšed + +__USE_XOPEN + || defšed +__USE_ISOC99 + + +257 +__BEGIN_NAMESPACE_C99 + + +259 +__MATHCALL + ( +”f +,, ( +_MdoubË_ +)); + +260 +__MATHCALL + ( +”fc +,, ( +_MdoubË_ +)); + +261 +__MATHCALL + ( +lgamma +,, ( +_MdoubË_ +)); + +262 + g__END_NAMESPACE_C99 + + +265 #ifdeà +__USE_ISOC99 + + +266 +__BEGIN_NAMESPACE_C99 + + +268 +__MATHCALL + ( +tgamma +,, ( +_MdoubË_ +)); + +269 + g__END_NAMESPACE_C99 + + +272 #ià +defšed + +__USE_MISC + || (defšed +__USE_XOPEN + && !defšed +__USE_XOPEN2K +) + +274 +__MATHCALL + ( +gamma +,, ( +_MdoubË_ +)); + +277 #ifdeà +__USE_MISC + + +281 +__MATHCALL + ( +lgamma +, +_r +, ( +_MdoubË_ +, * +__signgamp +)); + +285 #ià +defšed + +__USE_XOPEN_EXTENDED + || defšed +__USE_ISOC99 + + +286 +__BEGIN_NAMESPACE_C99 + + +289 +__MATHCALL + ( +ršt +,, ( +_MdoubË_ + +__x +)); + +292 +__MATHCALLX + ( +Ãxá” +,, ( +_MdoubË_ + +__x +, _MdoubË_ +__y +), ( +__cÚ¡__ +)); + +293 #ià +defšed + +__USE_ISOC99 + && !defšed +__LDBL_COMPAT + + +294 +__MATHCALLX + ( +Ãx‰ow¬d +,, ( +_MdoubË_ + +__x +,  +__y +), ( +__cÚ¡__ +)); + +298 +__MATHCALL + ( +»mašd” +,, ( +_MdoubË_ + +__x +, _MdoubË_ +__y +)); + +300 #ifdeà +__USE_ISOC99 + + +302 +__MATHCALL + ( +sÿlbn +,, ( +_MdoubË_ + +__x +,  +__n +)); + +306 +__MATHDECL + (, +žogb +,, ( +_MdoubË_ + +__x +)); + +309 #ifdeà +__USE_ISOC99 + + +311 +__MATHCALL + ( +sÿlbÊ +,, ( +_MdoubË_ + +__x +,  +__n +)); + +315 +__MATHCALL + ( +ìbyšt +,, ( +_MdoubË_ + +__x +)); + +319 +__MATHCALLX + ( +round +,, ( +_MdoubË_ + +__x +), ( +__cÚ¡__ +)); + +323 +__MATHCALLX + ( +Œunc +,, ( +_MdoubË_ + +__x +), ( +__cÚ¡__ +)); + +328 +__MATHCALL + ( +»mquo +,, ( +_MdoubË_ + +__x +, _MdoubË_ +__y +, * +__quo +)); + +335 +__MATHDECL + (, +Ìšt +,, ( +_MdoubË_ + +__x +)); + +336 +__ex‹nsiÚ__ + + +337 +__MATHDECL + (, +Îršt +,, ( +_MdoubË_ + +__x +)); + +341 +__MATHDECL + (, +Ìound +,, ( +_MdoubË_ + +__x +)); + +342 +__ex‹nsiÚ__ + + +343 +__MATHDECL + (, +Îround +,, ( +_MdoubË_ + +__x +)); + +347 +__MATHCALL + ( +fdim +,, ( +_MdoubË_ + +__x +, _MdoubË_ +__y +)); + +350 +__MATHCALLX + ( +fmax +,, ( +_MdoubË_ + +__x +, _MdoubË_ +__y +), ( +__cÚ¡__ +)); + +353 +__MATHCALLX + ( +fmš +,, ( +_MdoubË_ + +__x +, _MdoubË_ +__y +), ( +__cÚ¡__ +)); + +357 +__MATHDECL_1 + (, +__åþassify +,, ( +_MdoubË_ + +__v®ue +)) + +358 +__©Œibu‹__ + (( +__cÚ¡__ +)); + +361 +__MATHDECL_1 + (, +__signb™ +,, ( +_MdoubË_ + +__v®ue +)) + +362 +__©Œibu‹__ + (( +__cÚ¡__ +)); + +366 +__MATHCALL + ( +fma +,, ( +_MdoubË_ + +__x +, _MdoubË_ +__y +, _MdoubË_ +__z +)); + +369 #ià +defšed + +__USE_XOPEN_EXTENDED + || defšed +__USE_ISOC99 + + +370 + g__END_NAMESPACE_C99 + + +373 #ifdeà +__USE_GNU + + +375 +__MATHDECL_1 + (, +__issigÇlšg +,, ( +_MdoubË_ + +__v®ue +)) + +376 +__©Œibu‹__ + (( +__cÚ¡__ +)); + +379 #ià +defšed + +__USE_MISC + || (defšed +__USE_XOPEN_EXTENDED + \ + +380 && + g__MATH_DECLARING_DOUBLE + \ + +381 && ! +defšed + + g__USE_XOPEN2K8 +) + +383 +__MATHCALL + ( +sÿlb +,, ( +_MdoubË_ + +__x +, _MdoubË_ +__n +)); + + @/usr/include/bits/mathdef.h + +18 #ià! +defšed + +_MATH_H + && !defšed +_COMPLEX_H + + +22 #ià +defšed + +__USE_ISOC99 + && defšed +_MATH_H + && !defšed +_MATH_H_MATHDEF + + +23  + #_MATH_H_MATHDEF + 1 + + ) + +25 #ià +defšed + +__x86_64__ + || (defšed +__FLT_EVAL_METHOD__ + && __FLT_EVAL_METHOD__ == 0) + +28  + tæßt_t +; + +29  + tdoubË_t +; + +35  + tæßt_t +; + +37  + tdoubË_t +; + +42  + #FP_ILOGB0 + (-2147483647 - 1) + + ) + +43  + #FP_ILOGBNAN + (-2147483647 - 1) + + ) + +47 #ifdeà +__FP_FAST_FMA + + +48  + #FP_FAST_FMA + 1 + + ) + +51 #ifdeà +__FP_FAST_FMAF + + +52  + #FP_FAST_FMAF + 1 + + ) + +55 #ifdeà +__FP_FAST_FMAL + + +56  + #FP_FAST_FMAL + 1 + + ) + + @/usr/include/bits/mathinline.h + +19 #iâdeà +_MATH_H + + +23 #iâdeà +__ex‹º_®ways_šlše + + +24  + #__MATH_INLINE + +__šlše + + + ) + +26  + #__MATH_INLINE + +__ex‹º_®ways_šlše + + + ) + +30 #ià +defšed + +__USE_ISOC99 + && defšed +__GNUC__ + && __GNUC__ >= 2 + +32 #ià! +__GNUC_PREREQ + (2,97) + +37 #undeà +isg»©” + + +38 #undeà +isg»©”equ® + + +39 #undeà +i¦ess + + +40 #undeà +i¦es£qu® + + +41 #undeà +i¦essg»©” + + +42 #undeà +isunÜd”ed + + +43 #ifdeà +__i686__ + + +46  + #isg»©” +( +x +, +y +) \ + +47 ({  +__»suÉ +; \ + +48 + `__asm__ + ("fucomip %%st(1), %%st; seta %%al" \ + +49 : "÷" ( +__»suÉ +è: "u" ( +y +), "t" ( +x +) : "cc", "st"); \ + +50 +__»suÉ +; }) + + ) + +51  + #isg»©”equ® +( +x +, +y +) \ + +52 ({  +__»suÉ +; \ + +53 + `__asm__ + ("fucomip %%st(1), %%st; setae %%al" \ + +54 : "÷" ( +__»suÉ +è: "u" ( +y +), "t" ( +x +) : "cc", "st"); \ + +55 +__»suÉ +; }) + + ) + +57  + #i¦ess +( +x +, +y +) \ + +58 ({  +__»suÉ +; \ + +59 + `__asm__ + ("fucomip %%st(1), %%st; seta %%al" \ + +60 : "÷" ( +__»suÉ +è: "u" ( +x +), "t" ( +y +) : "cc", "st"); \ + +61 +__»suÉ +; }) + + ) + +63  + #i¦es£qu® +( +x +, +y +) \ + +64 ({  +__»suÉ +; \ + +65 + `__asm__ + ("fucomip %%st(1), %%st; setae %%al" \ + +66 : "÷" ( +__»suÉ +è: "u" ( +x +), "t" ( +y +) : "cc", "st"); \ + +67 +__»suÉ +; }) + + ) + +69  + #i¦essg»©” +( +x +, +y +) \ + +70 ({  +__»suÉ +; \ + +71 + `__asm__ + ("fucomip %%st(1), %%st; setne %%al" \ + +72 : "÷" ( +__»suÉ +è: "u" ( +y +), "t" ( +x +) : "cc", "st"); \ + +73 +__»suÉ +; }) + + ) + +75  + #isunÜd”ed +( +x +, +y +) \ + +76 ({  +__»suÉ +; \ + +77 + `__asm__ + ("fucomip %%st(1), %%st; setp %%al" \ + +78 : "÷" ( +__»suÉ +è: "u" ( +y +), "t" ( +x +) : "cc", "st"); \ + +79 +__»suÉ +; }) + + ) + +82  + #isg»©” +( +x +, +y +) \ + +83 ({  +__»suÉ +; \ + +84 + `__asm__ + ("fucompp; fnstsw;estb $0x45, %%ah; setz %%al" \ + +85 : "÷" ( +__»suÉ +è: "u" ( +y +), "t" ( +x +) : "cc", "st", "st(1)"); \ + +86 +__»suÉ +; }) + + ) + +88  + #isg»©”equ® +( +x +, +y +) \ + +89 ({  +__»suÉ +; \ + +90 + `__asm__ + ("fucompp; fnstsw;estb $0x05, %%ah; setz %%al" \ + +91 : "÷" ( +__»suÉ +è: "u" ( +y +), "t" ( +x +) : "cc", "st", "st(1)"); \ + +92 +__»suÉ +; }) + + ) + +94  + #i¦ess +( +x +, +y +) \ + +95 ({  +__»suÉ +; \ + +96 + `__asm__ + ("fucompp; fnstsw;estb $0x45, %%ah; setz %%al" \ + +97 : "÷" ( +__»suÉ +è: "u" ( +x +), "t" ( +y +) : "cc", "st", "st(1)"); \ + +98 +__»suÉ +; }) + + ) + +100  + #i¦es£qu® +( +x +, +y +) \ + +101 ({  +__»suÉ +; \ + +102 + `__asm__ + ("fucompp; fnstsw;estb $0x05, %%ah; setz %%al" \ + +103 : "÷" ( +__»suÉ +è: "u" ( +x +), "t" ( +y +) : "cc", "st", "st(1)"); \ + +104 +__»suÉ +; }) + + ) + +106  + #i¦essg»©” +( +x +, +y +) \ + +107 ({  +__»suÉ +; \ + +108 + `__asm__ + ("fucompp; fnstsw;estb $0x44, %%ah; setz %%al" \ + +109 : "÷" ( +__»suÉ +è: "u" ( +y +), "t" ( +x +) : "cc", "st", "st(1)"); \ + +110 +__»suÉ +; }) + + ) + +112  + #isunÜd”ed +( +x +, +y +) \ + +113 ({  +__»suÉ +; \ + +114 + `__asm__ + ("fucompp; fnstsw; sahf; setp %%al" \ + +115 : "÷" ( +__»suÉ +è: "u" ( +y +), "t" ( +x +) : "cc", "st", "st(1)"); \ + +116 +__»suÉ +; }) + + ) + +122 #ià +__GNUC_PREREQ + (2, 8) + +123 +__BEGIN_NAMESPACE_C99 + + +126 +__MATH_INLINE +  + +127 +__NTH + ( + $__signb™f + ( +__x +)) + +129 #ifdeà +__SSE2_MATH__ + + +130  +__m +; + +131 + `__asm + ("pmovmskb %1, %0" : "ô" ( +__m +è: "x" ( +__x +)); + +132  ( +__m + & 0x8) != 0; + +134 +__ex‹nsiÚ__ + uniÚ {  +__f +;  +__i +; } +__u + = { __f: +__x + }; + +135  +__u +. +__i + < 0; + +137 + } +} + +138 +__MATH_INLINE +  + +139 +__NTH + ( + $__signb™ + ( +__x +)) + +141 #ifdeà +__SSE2_MATH__ + + +142  +__m +; + +143 + `__asm + ("pmovmskb %1, %0" : "ô" ( +__m +è: "x" ( +__x +)); + +144  ( +__m + & 0x80) != 0; + +146 +__ex‹nsiÚ__ + uniÚ {  +__d +;  +__i +[2]; } +__u + = { __d: +__x + }; + +147  +__u +. +__i +[1] < 0; + +149 + } +} + +150 +__MATH_INLINE +  + +151 +__NTH + ( + $__signb™l + ( +__x +)) + +153 +__ex‹nsiÚ__ + uniÚ {  +__l +;  +__i +[3]; } +__u + = { __l: +__x + }; + +154  ( +__u +. +__i +[2] & 0x8000) != 0; + +155 + } +} + +157 + g__END_NAMESPACE_C99 + + +164 #ià +__GNUC_PREREQ + (2, 8) + +165 #ià! +__GNUC_PREREQ + (3, 4è&& ! +defšed + +__NO_MATH_INLINES + \ + +166 && +defšed + + g__OPTIMIZE__ + + +170 #ifdeà +__USE_ISOC99 + + +171 + g__BEGIN_NAMESPACE_C99 + + +174 #ifdeà +__SSE_MATH__ + + +175 +__MATH_INLINE +  + +176 +__NTH + ( + $Ìštf + ( +__x +)) + +178  +__»s +; + +183 +__asm + + `__vÞ©že__ + ("cvtss2s˜%1, %0" : "ô" ( +__»s +è: "xm" ( +__x +)); + +184  +__»s +; + +185 + } +} + +187 #ifdeà +__SSE2_MATH__ + + +188 +__MATH_INLINE +  + +189 +__NTH + ( + $Ìšt + ( +__x +)) + +191  +__»s +; + +196 +__asm + + `__vÞ©že__ + ("cvtsd2s˜%1, %0" : "ô" ( +__»s +è: "xm" ( +__x +)); + +197  +__»s +; + +198 + } +} + +200 #ifdeà +__x86_64__ + + +201 +__ex‹nsiÚ__ + + +202 +__MATH_INLINE +  + +203 +__NTH + ( + $Îrštf + ( +__x +)) + +205  +__»s +; + +210 +__asm + + `__vÞ©že__ + ("cvtss2s˜%1, %0" : "ô" ( +__»s +è: "xm" ( +__x +)); + +211  +__»s +; + +212 + } +} + +213 +__ex‹nsiÚ__ + + +214 +__MATH_INLINE +  + +215 +__NTH + ( + $Îršt + ( +__x +)) + +217  +__»s +; + +222 +__asm + + `__vÞ©že__ + ("cvtsd2s˜%1, %0" : "ô" ( +__»s +è: "xm" ( +__x +)); + +223  +__»s +; + +224 + } +} + +227 #ià +defšed + +__FINITE_MATH_ONLY__ + && __FINITE_MATH_ONLY__ > 0 \ + +228 && +defšed + +__SSE2_MATH__ + + +230 +__MATH_INLINE +  + +231 +__NTH + ( + $fmaxf + ( +__x +,  +__y +)) + +233 #ifdeà +__AVX__ + + +234  +__»s +; + +235 + `__asm + ("vmaxs %2, %1, %0" : "=x" ( +__»s +è: "x" ( +x +), "xm" ( +__y +)); + +236  +__»s +; + +238 + `__asm + ("maxs %1, %0" : "+x" ( +__x +è: "xm" ( +__y +)); + +239  +__x +; + +241 + } +} + +242 +__MATH_INLINE +  + +243 +__NTH + ( + $fmax + ( +__x +,  +__y +)) + +245 #ifdeà +__AVX__ + + +246  +__»s +; + +247 + `__asm + ("vmaxsd %2, %1, %0" : "=x" ( +__»s +è: "x" ( +x +), "xm" ( +__y +)); + +248  +__»s +; + +250 + `__asm + ("maxsd %1, %0" : "+x" ( +__x +è: "xm" ( +__y +)); + +251  +__x +; + +253 + } +} + +256 +__MATH_INLINE +  + +257 +__NTH + ( + $fmšf + ( +__x +,  +__y +)) + +259 #ifdeà +__AVX__ + + +260  +__»s +; + +261 + `__asm + ("vmšs %2, %1, %0" : "=x" ( +__»s +è: "x" ( +x +), "xm" ( +__y +)); + +262  +__»s +; + +264 + `__asm + ("mšs %1, %0" : "+x" ( +__x +è: "xm" ( +__y +)); + +265  +__x +; + +267 + } +} + +268 +__MATH_INLINE +  + +269 +__NTH + ( + $fmš + ( +__x +,  +__y +)) + +271 #ifdeà +__AVX__ + + +272  +__»s +; + +273 + `__asm + ("vmšsd %2, %1, %0" : "=x" ( +__»s +è: "x" ( +x +), "xm" ( +__y +)); + +274  +__»s +; + +276 + `__asm + ("mšsd %1, %0" : "+x" ( +__x +è: "xm" ( +__y +)); + +277  +__x +; + +279 + } +} + +282 + g__END_NAMESPACE_C99 + + +285 #ià +defšed + +__SSE4_1__ + && defšed +__SSE2_MATH__ + + +286 #ià +defšed + +__USE_XOPEN_EXTENDED + || defšed +__USE_ISOC99 + + +287 +__BEGIN_NAMESPACE_C99 + + +290 +__MATH_INLINE +  + +291 +__NTH + ( + $ršt + ( +__x +)) + +293  +__»s +; + +298 +__asm + + `__vÞ©že__ + ("roundsd $4, %1, %0" : "=x" ( +__»s +è: "xm" ( +__x +)); + +299  +__»s +; + +300 + } +} + +301 +__MATH_INLINE +  + +302 +__NTH + ( + $rštf + ( +__x +)) + +304  +__»s +; + +309 +__asm + + `__vÞ©že__ + ("rounds $4, %1, %0" : "=x" ( +__»s +è: "xm" ( +__x +)); + +310  +__»s +; + +311 + } +} + +313 #ifdeà +__USE_ISOC99 + + +315 +__MATH_INLINE +  + +316 +__NTH + ( + $ìbyšt + ( +__x +)) + +318  +__»s +; + +323 +__asm + + `__vÞ©že__ + ("roundsd $0xc, %1, %0" : "=x" ( +__»s +è: "xm" ( +__x +)); + +324  +__»s +; + +325 + } +} + +326 +__MATH_INLINE +  + +327 +__NTH + ( + $ìbyštf + ( +__x +)) + +329  +__»s +; + +334 +__asm + + `__vÞ©že__ + ("rounds $0xc, %1, %0" : "=x" ( +__»s +è: "xm" ( +__x +)); + +335  +__»s +; + +336 + } +} + +339 + g__END_NAMESPACE_C99 + + +342 +__BEGIN_NAMESPACE_STD + + +344 +__MATH_INLINE +  + +345 +__NTH + ( + $ûž + ( +__x +)) + +347  +__»s +; + +348 + `__asm + ("roundsd $2, %1, %0" : "=x" ( +__»s +è: "xm" ( +__x +)); + +349  +__»s +; + +350 + } +} + +351 +__END_NAMESPACE_STD + + +353 +__BEGIN_NAMESPACE_C99 + + +354 +__MATH_INLINE +  + +355 +__NTH + ( + $ûžf + ( +__x +)) + +357  +__»s +; + +358 + `__asm + ("rounds $2, %1, %0" : "=x" ( +__»s +è: "xm" ( +__x +)); + +359  +__»s +; + +360 + } +} + +361 +__END_NAMESPACE_C99 + + +363 +__BEGIN_NAMESPACE_STD + + +365 +__MATH_INLINE +  + +366 +__NTH + ( + $æoÜ + ( +__x +)) + +368  +__»s +; + +369 + `__asm + ("roundsd $1, %1, %0" : "=x" ( +__»s +è: "xm" ( +__x +)); + +370  +__»s +; + +371 + } +} + +372 +__END_NAMESPACE_STD + + +374 +__BEGIN_NAMESPACE_C99 + + +375 +__MATH_INLINE +  + +376 +__NTH + ( + $æoÜf + ( +__x +)) + +378  +__»s +; + +379 + `__asm + ("rounds $1, %1, %0" : "=x" ( +__»s +è: "xm" ( +__x +)); + +380  +__»s +; + +381 + } +} + +382 + g__END_NAMESPACE_C99 + + +390 #ià! +defšed + +__SSE2_MATH__ + && !defšed +__x86_64__ + + +391 #ià((! +defšed + +__NO_MATH_INLINES + || defšed +__LIBC_INTERNAL_MATH_INLINES +) \ + +392 && +defšed + + g__OPTIMIZE__ +) + +396 #undeà +m©h_”rhªdlšg + + +405 #ifdeà +__USE_ISOC99 + + +406  + #__šlše_m©hÝ +( +func +, +Ý +) \ + +407 + `__šlše_m©hÝ_ + (, +func +, +Ý +) \ + +408 + `__šlše_m©hÝ_ + (, + `__CONCAT +( +func +, +f +), +Ý +) \ + +409 + `__šlše_m©hÝ_ + (, + `__CONCAT +( +func +, +l +), +Ý +) + + ) + +410  + #__šlše_m©hÝNP +( +func +, +Ý +) \ + +411 + `__šlše_m©hÝNP_ + (, +func +, +Ý +) \ + +412 + `__šlše_m©hÝNP_ + (, + `__CONCAT +( +func +, +f +), +Ý +) \ + +413 + `__šlše_m©hÝNP_ + (, + `__CONCAT +( +func +, +l +), +Ý +) + + ) + +415  + #__šlše_m©hÝ +( +func +, +Ý +) \ + +416 + `__šlše_m©hÝ_ + (, +func +, +Ý +) + + ) + +417  + #__šlše_m©hÝNP +( +func +, +Ý +) \ + +418 + `__šlše_m©hÝNP_ + (, +func +, +Ý +) + + ) + +421  + #__šlše_m©hÝ_ +( +æßt_ty³ +, +func +, +Ý +) \ + +422 + `__šlše_m©hÝ_deþ_ + ( +æßt_ty³ +, +func +, +Ý +, "0" ( +__x +)) + + ) + +423  + #__šlše_m©hÝNP_ +( +æßt_ty³ +, +func +, +Ý +) \ + +424 + `__šlše_m©hÝ_deþNP_ + ( +æßt_ty³ +, +func +, +Ý +, "0" ( +__x +)) + + ) + +427 #ifdeà +__USE_ISOC99 + + +428  + #__šlše_m©hÝ_deþ +( +func +, +Ý +, +·¿ms +...) \ + +429 + `__šlše_m©hÝ_deþ_ + (, +func +, +Ý +, +·¿ms +) \ + +430 + `__šlše_m©hÝ_deþ_ + (, + `__CONCAT +( +func +, +f +), +Ý +, +·¿ms +) \ + +431 + `__šlše_m©hÝ_deþ_ + (, + `__CONCAT +( +func +, +l +), +Ý +, +·¿ms +) + + ) + +432  + #__šlše_m©hÝ_deþNP +( +func +, +Ý +, +·¿ms +...) \ + +433 + `__šlše_m©hÝ_deþNP_ + (, +func +, +Ý +, +·¿ms +) \ + +434 + `__šlše_m©hÝ_deþNP_ + (, + `__CONCAT +( +func +, +f +), +Ý +, +·¿ms +) \ + +435 + `__šlše_m©hÝ_deþNP_ + (, + `__CONCAT +( +func +, +l +), +Ý +, +·¿ms +) + + ) + +437  + #__šlše_m©hÝ_deþ +( +func +, +Ý +, +·¿ms +...) \ + +438 + `__šlše_m©hÝ_deþ_ + (, +func +, +Ý +, +·¿ms +) + + ) + +439  + #__šlše_m©hÝ_deþNP +( +func +, +Ý +, +·¿ms +...) \ + +440 + `__šlše_m©hÝ_deþNP_ + (, +func +, +Ý +, +·¿ms +) + + ) + +443  + #__šlše_m©hÝ_deþ_ +( +æßt_ty³ +, +func +, +Ý +, +·¿ms +...) \ + +444 +__MATH_INLINE + +æßt_ty³ + + `func + (æßt_ty³è +__THROW +; \ + +445 + `__šlše_m©hÝ_deþNP_ + ( +æßt_ty³ +, +func +, +Ý +, +·¿ms +) + + ) + +447  + #__šlše_m©hÝ_deþNP_ +( +æßt_ty³ +, +func +, +Ý +, +·¿ms +...) \ + +448 +__MATH_INLINE + +æßt_ty³ + + `__NTH + ( + `func + (æßt_ty³ +__x +)) \ + +450  +æßt_ty³ + +__»suÉ +; \ + +451 +__asm + + `__vÞ©že__ + ( +Ý + : "ñ" ( +__»suÉ +è: +·¿ms +); \ + +452  +__»suÉ +; \ + +453 } + + ) + +456 #ifdeà +__USE_ISOC99 + + +457  + #__šlše_m©hcode +( +func +, +¬g +, +code +) \ + +458 + `__šlše_m©hcode_ + (, +func +, +¬g +, +code +) \ + +459 + `__šlše_m©hcode_ + (, + `__CONCAT +( +func +, +f +), +¬g +, +code +) \ + +460 + `__šlše_m©hcode_ + (, + `__CONCAT +( +func +, +l +), +¬g +, +code +) + + ) + +461  + #__šlše_m©hcodeNP +( +func +, +¬g +, +code +) \ + +462 + `__šlše_m©hcodeNP_ + (, +func +, +¬g +, +code +) \ + +463 + `__šlše_m©hcodeNP_ + (, + `__CONCAT +( +func +, +f +), +¬g +, +code +) \ + +464 + `__šlše_m©hcodeNP_ + (, + `__CONCAT +( +func +, +l +), +¬g +, +code +) + + ) + +465  + #__šlše_m©hcode2 +( +func +, +¬g1 +, +¬g2 +, +code +) \ + +466 + `__šlše_m©hcode2_ + (, +func +, +¬g1 +, +¬g2 +, +code +) \ + +467 + `__šlše_m©hcode2_ + (, + `__CONCAT +( +func +, +f +), +¬g1 +, +¬g2 +, +code +) \ + +468 + `__šlše_m©hcode2_ + (, + `__CONCAT +( +func +, +l +), +¬g1 +, +¬g2 +, +code +) + + ) + +469  + #__šlše_m©hcodeNP2 +( +func +, +¬g1 +, +¬g2 +, +code +) \ + +470 + `__šlše_m©hcodeNP2_ + (, +func +, +¬g1 +, +¬g2 +, +code +) \ + +471 + `__šlše_m©hcodeNP2_ + (, + `__CONCAT +( +func +, +f +), +¬g1 +, +¬g2 +, +code +) \ + +472 + `__šlše_m©hcodeNP2_ + (, + `__CONCAT +( +func +, +l +), +¬g1 +, +¬g2 +, +code +) + + ) + +473  + #__šlše_m©hcode3 +( +func +, +¬g1 +, +¬g2 +, +¬g3 +, +code +) \ + +474 + `__šlše_m©hcode3_ + (, +func +, +¬g1 +, +¬g2 +, +¬g3 +, +code +) \ + +475 + `__šlše_m©hcode3_ + (, + `__CONCAT +( +func +, +f +), +¬g1 +, +¬g2 +, +¬g3 +, +code +) \ + +476 + `__šlše_m©hcode3_ + (, + `__CONCAT +( +func +, +l +), +¬g1 +, +¬g2 +, +¬g3 +, +code +) + + ) + +477  + #__šlše_m©hcodeNP3 +( +func +, +¬g1 +, +¬g2 +, +¬g3 +, +code +) \ + +478 + `__šlše_m©hcodeNP3_ + (, +func +, +¬g1 +, +¬g2 +, +¬g3 +, +code +) \ + +479 + `__šlše_m©hcodeNP3_ + (, + `__CONCAT +( +func +, +f +), +¬g1 +, +¬g2 +, +¬g3 +, +code +) \ + +480 + `__šlše_m©hcodeNP3_ + (, + `__CONCAT +( +func +, +l +), +¬g1 +, +¬g2 +, +¬g3 +, +code +) + + ) + +482  + #__šlše_m©hcode +( +func +, +¬g +, +code +) \ + +483 + `__šlše_m©hcode_ + (, +func +, ( +¬g +), +code +) + + ) + +484  + #__šlše_m©hcodeNP +( +func +, +¬g +, +code +) \ + +485 + `__šlše_m©hcodeNP_ + (, +func +, ( +¬g +), +code +) + + ) + +486  + #__šlše_m©hcode2 +( +func +, +¬g1 +, +¬g2 +, +code +) \ + +487 + `__šlše_m©hcode2_ + (, +func +, +¬g1 +, +¬g2 +, +code +) + + ) + +488  + #__šlše_m©hcodeNP2 +( +func +, +¬g1 +, +¬g2 +, +code +) \ + +489 + `__šlše_m©hcodeNP2_ + (, +func +, +¬g1 +, +¬g2 +, +code +) + + ) + +490  + #__šlše_m©hcode3 +( +func +, +¬g1 +, +¬g2 +, +¬g3 +, +code +) \ + +491 + `__šlše_m©hcode3_ + (, +func +, +¬g1 +, +¬g2 +, +¬g3 +, +code +) + + ) + +492  + #__šlše_m©hcodeNP3 +( +func +, +¬g1 +, +¬g2 +, +¬g3 +, +code +) \ + +493 + `__šlše_m©hcodeNP3_ + (, +func +, +¬g1 +, +¬g2 +, +¬g3 +, +code +) + + ) + +496  + #__šlše_m©hcode_ +( +æßt_ty³ +, +func +, +¬g +, +code +) \ + +497 +__MATH_INLINE + +æßt_ty³ + + `func + (æßt_ty³è +__THROW +; \ + +498 + `__šlše_m©hcodeNP_ +( +æßt_ty³ +, +func +, +¬g +, +code +) + + ) + +500  + #__šlše_m©hcodeNP_ +( +æßt_ty³ +, +func +, +¬g +, +code +) \ + +501 +__MATH_INLINE + +æßt_ty³ + + `__NTH + ( + `func + (æßt_ty³ +¬g +)) \ + +503 +code +; \ + +504 } + + ) + +507  + #__šlše_m©hcode2_ +( +æßt_ty³ +, +func +, +¬g1 +, +¬g2 +, +code +) \ + +508 +__MATH_INLINE + +æßt_ty³ + + `func + (æßt_ty³, flßt_ty³è +__THROW +; \ + +509 + `__šlše_m©hcodeNP2_ + ( +æßt_ty³ +, +func +, +¬g1 +, +¬g2 +, +code +) + + ) + +511  + #__šlše_m©hcodeNP2_ +( +æßt_ty³ +, +func +, +¬g1 +, +¬g2 +, +code +) \ + +512 +__MATH_INLINE + +æßt_ty³ + + `__NTH + ( + `func + (æßt_ty³ +¬g1 +, flßt_ty³ +¬g2 +)) \ + +514 +code +; \ + +515 } + + ) + +517  + #__šlše_m©hcode3_ +( +æßt_ty³ +, +func +, +¬g1 +, +¬g2 +, +¬g3 +, +code +) \ + +518 +__MATH_INLINE + +æßt_ty³ + + `func + (æßt_ty³, flßt_ty³, flßt_ty³è +__THROW +; \ + +519 + `__šlše_m©hcodeNP3_ +( +æßt_ty³ +, +func +, +¬g1 +, +¬g2 +, +¬g3 +, +code +) + + ) + +521  + #__šlše_m©hcodeNP3_ +( +æßt_ty³ +, +func +, +¬g1 +, +¬g2 +, +¬g3 +, +code +) \ + +522 +__MATH_INLINE + +æßt_ty³ + + `__NTH + ( + `func + (æßt_ty³ +¬g1 +, flßt_ty³ +¬g2 +, \ + +523 +æßt_ty³ + +¬g3 +)) \ + +525 +code +; \ + +526 } + + ) + +530 #ià! +defšed + +__NO_MATH_INLINES + && defšed +__OPTIMIZE__ + + +534 #ifdeà +__FAST_MATH__ + + +535 #ifdeà +__USE_GNU + + +536  + #__sšcos_code + \ + +537  +__co¤ +; \ + +538  +__sšr +; \ + +539  +__swtmp +; \ + +540 +__asm + +__vÞ©že__ + \ + +555 : "ñ" ( +__co¤ +), "=u" ( +__sšr +), "÷" ( +__swtmp +è: "0" ( +__x +)); \ + +556 * +__sšx + = +__sšr +; \ + +557 * +__cosx + = +__co¤ + + + ) + +559 +__MATH_INLINE +  + +560 +__NTH + ( + $__sšcos + ( +__x +, * +__sšx +, * +__cosx +)) + +562 +__sšcos_code +; + +563 + } +} + +565 +__MATH_INLINE +  + +566 +__NTH + ( + $__sšcosf + ( +__x +, * +__sšx +, * +__cosx +)) + +568 +__sšcos_code +; + +569 + } +} + +571 +__MATH_INLINE +  + +572 +__NTH + ( + $__sšco¦ + ( +__x +, * +__sšx +, * +__cosx +)) + +574 +__sšcos_code +; + +575 + } +} + +582 #ià +__GNUC_PREREQ + (3, 5) + +583  + #__expm1_code + \ + +584  +__‹mp +; \ + +585 +__‹mp + = + `__bužtš_expm1l + ( +__x +); \ + +586  +__‹mp + ? __‹m°: +__x + + + ) + +588  + #__expm1_code + \ + +589  +__v®ue +; \ + +590  +__expÚ’t +; \ + +591  +__‹mp +; \ + +592 +__asm + +__vÞ©že__ + \ + +601 : "ñ" ( +__v®ue +), "=u" ( +__expÚ’t +è: "0" ( +__x +)); \ + +602 +__asm + +__vÞ©že__ + \ + +604 : "ñ" ( +__‹mp +è: "0" (1.0), "u" ( +__expÚ’t +)); \ + +605 +__‹mp + -= 1.0; \ + +606 +__‹mp + +ð +__v®ue +; \ + +607  +__‹mp + ? __‹m°: +__x + + + ) + +609 + $__šlše_m©hcodeNP_ + (, +__expm1l +, +__x +, +__expm1_code +) + +611 #ià + `__GNUC_PREREQ + (3, 4) + +612 + `__šlše_m©hcodeNP_ + (, +__ex¶ +, +__x +,  + $__bužtš_ex¶ + ( +__x +)) + +614  + #__exp_code + \ + +615  +__v®ue +; \ + +616  +__expÚ’t +; \ + +617 +__asm + +__vÞ©že__ + \ + +625 : "ñ" ( +__v®ue +), "=u" ( +__expÚ’t +è: "0" ( +__x +)); \ + +626 +__v®ue + += 1.0; \ + +627 +__asm + +__vÞ©že__ + \ + +629 : "ñ" ( +__v®ue +è: "0" (__v®ue), "u" ( +__expÚ’t +)); \ + +630  +__v®ue + + + ) + +631 + $__šlše_m©hcodeNP + ( +exp +, +__x +, +__exp_code +) + +632 + $__šlše_m©hcodeNP_ + (, +__ex¶ +, +__x +, +__exp_code +) + +636 #ià! + `__GNUC_PREREQ + (3, 5) + +637 + `__šlše_m©hcodeNP + ( +n +, +__x +, \ + +638  +__v®ue +; \ + +639  +__v®ue2 + + `__©Œibu‹__ + (( +__unu£d__ +)); \ + +640 +__asm + +__vÞ©že__ + \ + +642 : "ñ" ( +__v®ue2 +), "=u" ( +__v®ue +è: "0" ( +__x +)); \ + +643  +__v®ue +) + +648 #ià + `__GNUC_PREREQ + (3, 4) + +649 + `__šlše_m©hcodeNP2_ + (, +__©ª2l +, +__y +, +__x +, + +650  + $__bužtš_©ª2l + ( +__y +, +__x +)) + +652  + #__©ª2_code + \ + +653  +__v®ue +; \ + +654 +__asm + +__vÞ©že__ + \ + +656 : "ñ" ( +__v®ue +è: "0" ( +__x +), "u" ( +__y +) : "st(1)"); \ + +657  +__v®ue + + + ) + +658 #ifdeà +__FAST_MATH__ + + +659 + $__šlše_m©hcodeNP2 + ( +©ª2 +, +__y +, +__x +, +__©ª2_code +) + +661 + $__šlše_m©hcodeNP2_ + (, +__©ª2l +, +__y +, +__x +, +__©ª2_code +) + +665 #ià +defšed + +__FAST_MATH__ + && ! + `__GNUC_PREREQ + (3, 5) + +666 + `__šlše_m©hcodeNP2 + ( +fmod +, +__x +, +__y +, \ + +667  +__v®ue +; \ + +668 +__asm + +__vÞ©že__ + \ + +673 : "ñ" ( +__v®ue +è: "0" ( +__x +), "u" ( +__y +) : "ax", "cc"); \ + +674  +__v®ue +) + +678 #ifdeà +__FAST_MATH__ + + +679 #ià! + `__GNUC_PREREQ + (3,3) + +680 + `__šlše_m©hÝNP + ( +sq¹ +, "fsqrt") + +681 + `__šlše_m©hÝNP_ + (, +__sq¹l +, "fsqrt") + +682  + #__libc_sq¹l +( +n +è + `__sq¹l + (n) + + ) + +684  + #__libc_sq¹l +( +n +è + `__bužtš_sq¹l + (n) + + ) + +688 #ià + `__GNUC_PREREQ + (2, 8) + +689 + `__šlše_m©hcodeNP_ + (, +çbs +, +__x +,  + $__bužtš_çbs + ( +__x +)) + +690 #ifdeà +__USE_ISOC99 + + +691 + `__šlše_m©hcodeNP_ + (, +çbsf +, +__x +,  + $__bužtš_çbsf + ( +__x +)) + +692 + `__šlše_m©hcodeNP_ + (, +çb¦ +, +__x +,  + $__bužtš_çb¦ + ( +__x +)) + +694 + `__šlše_m©hcodeNP_ + (, +__çb¦ +, +__x +,  + $__bužtš_çb¦ + ( +__x +)) + +696 + `__šlše_m©hÝ + ( +çbs +, "fabs") + +697 + `__šlše_m©hÝ_ + (, +__çb¦ +, "fabs") + +700 #ifdeà +__FAST_MATH__ + + +701 #ià! + `__GNUC_PREREQ + (3, 4) + +703 + `__šlše_m©hÝNP + ( +sš +, "fsin") + +705 + `__šlše_m©hÝNP + ( +cos +, "fcos") + +707 + `__šlše_m©hÝ_deþNP + ( +log +, "ædÊ2; fxch; fyl2x", "0" ( +__x +) : "st(1)") + +710 #ià! + `__GNUC_PREREQ + (3, 5) + +711 + `__šlše_m©hÝ_deþNP + ( +log10 +, "ædlg2; fxch; fyl2x", "0" ( +__x +) : "st(1)") + +713 + `__šlše_m©hcodeNP + ( +asš +, +__x +,  + `__©ª2l + (__x, + `__libc_sq¹l + (1.0 - __x * __x))) + +714 + `__šlše_m©hcodeNP + ( +acos +, +__x +,  + `__©ª2l + ( + `__libc_sq¹l + (1.0 - __x * __x), __x)) + +717 #ià! + `__GNUC_PREREQ + (3, 4) + +718 + `__šlše_m©hÝ_deþNP + ( +©ª +, "æd1; f·n", "0" ( +__x +) : "st(1)") + +722 + `__šlše_m©hcode_ + (, +__sgn1l +, +__x +, \ + +723 +__ex‹nsiÚ__ + uniÚ {  +__xld +;  +__xi +[3]; } +__n + = \ + +724 { +__xld +: +__x + + } +}; \ + +725 + g__n +. + g__xi +[2] = ( +__n +. +__xi +[2] & 0x8000) | 0x3fff; \ + +726 + g__n +. + g__xi +[1] = 0x80000000; \ + +727 + g__n +. + g__xi +[0] = 0; \ + +728  + g__n +. + g__xld +) + +731 #ifdeà +__FAST_MATH__ + + +733 +__šlše_m©hcodeNP + ( +sšh +, +__x +, \ + +734  +__exm1 + = +__expm1l + ( +__çb¦ + ( +__x +)); \ + +735  0.5 * ( +__exm1 + / (__exm1 + 1.0è+ __exm1è* + $__sgn1l + ( +__x +)) + +737 + `__šlše_m©hcodeNP + ( +cosh +, +__x +, \ + +738  +__ex + = + `__ex¶ + ( +__x +); \ + +739  0.5 * ( +__ex + + 1.0 / __ex)) + +741 + `__šlše_m©hcodeNP + ( +nh +, +__x +, \ + +742  +__exm1 + = + `__expm1l + (- + `__çb¦ + ( +__x + + __x)); \ + +743  +__exm1 + / (__exm1 + 2.0è* + `__sgn1l + (- +__x +)) + +746 + `__šlše_m©hcodeNP + ( +æoÜ +, +__x +, \ + +747  +__v®ue +; \ + +748  +__ignÜe +; \ + +749  +__cw +; \ + +750  +__cwtmp +; \ + +751 +__asm + + `__vÞ©že + ("fnstcw %3\n\t" \ + +759 : "ñ" ( +__v®ue +), "=&q" ( +__ignÜe +), "=m" ( +__cwtmp +), \ + +760 "=m" ( +__cw +) \ + +761 : "0" ( +__x +)); \ + +762  +__v®ue +) + +764 + `__šlše_m©hcodeNP + ( +ûž +, +__x +, \ + +765  +__v®ue +; \ + +766  +__ignÜe +; \ + +767  +__cw +; \ + +768  +__cwtmp +; \ + +769 +__asm + + `__vÞ©že + ("fnstcw %3\n\t" \ + +777 : "ñ" ( +__v®ue +), "=&q" ( +__ignÜe +), "=m" ( +__cwtmp +), \ + +778 "=m" ( +__cw +) \ + +779 : "0" ( +__x +)); \ + +780  +__v®ue +) + +782 #ifdeà +__FAST_MATH__ + + +783  + #__ldexp_code + \ + +784  +__v®ue +; \ + +785 +__asm + +__vÞ©že__ + \ + +787 : "ñ" ( +__v®ue +è: "0" ( +__x +), "u" ((è +__y +)); \ + +788  +__v®ue + + + ) + +790 +__MATH_INLINE +  + +791 + `__NTH + ( + $ldexp + ( +__x +,  +__y +)) + +793 +__ldexp_code +; + +794 + } +} + +799 #ifdeà +__USE_ISOC99 + + +801 #ifdeà +__FAST_MATH__ + + +802 + $__šlše_m©hcodeNP + ( +expm1 +, +__x +, +__expm1_code +) + +806  + #__M_SQRT2 + 1.41421356237309504880L + + ) + +808 #ià! + `__GNUC_PREREQ + (3, 5) + +809 + `__šlše_m©hcodeNP + ( +log1p +, +__x +, \ + +810  +__v®ue +; \ + +811 ià( + `__çb¦ + ( +__x +è>ð1.0 - 0.5 * +__M_SQRT2 +) \ + +812 +__v®ue + = + `logl + (1.0 + +__x +); \ + +814 +__asm + +__vÞ©že__ + \ + +818 : "ñ" ( +__v®ue +è: "0" ( +__x +) : "st(1)"); \ + +819  +__v®ue +) + +824 + `__šlše_m©hcodeNP + ( +asšh +, +__x +, \ + +825  +__y + = + `__çb¦ + ( +__x +); \ + +826  ( + `log1¶ + ( +__y + * __y / ( + `__libc_sq¹l + (__y * __y + 1.0) + 1.0) + __y) \ + +827 * + $__sgn1l + ( +__x +))) + +829 + `__šlše_m©hcodeNP + ( +acosh +, +__x +, \ + +830  + `logl + ( +__x + + + `__libc_sq¹l + (__x - 1.0) * __libc_sqrtl (__x + 1.0))) + +832 + `__šlše_m©hcodeNP + ( +©ªh +, +__x +, \ + +833  +__y + = + `__çb¦ + ( +__x +); \ + +834  -0.5 * + `log1¶ + (-( +__y + + __yè/ (1.0 + __y)è* + $__sgn1l + ( +__x +)) + +837 + `__šlše_m©hcodeNP2 + ( +hypÙ +, +__x +, +__y +, + +838  + `__libc_sq¹l + ( +__x + * __x + +__y + * __y)) + +840 #ià! + `__GNUC_PREREQ + (3, 5) + +841 + `__šlše_m©hcodeNP +( +logb +, +__x +, \ + +842  +__v®ue +; \ + +843  +__junk +; \ + +844 +__asm + +__vÞ©že__ + \ + +846 : "ñ" ( +__junk +), "=u" ( +__v®ue +è: "0" ( +__x +)); \ + +847  +__v®ue +) + +853 #ifdeà +__USE_ISOC99 + + +854 #ifdeà +__FAST_MATH__ + + +856 #ià! + `__GNUC_PREREQ + (3, 5) + +857 + `__šlše_m©hÝ_deþNP + ( +log2 +, "æd1; fxch; fyl2x", "0" ( +__x +) : "st(1)") + +860 +__MATH_INLINE +  + +861 + `__NTH + ( + $ldexpf + ( +__x +,  +__y +)) + +863 +__ldexp_code +; + +864 + } +} + +866 +__MATH_INLINE +  + +867 +__NTH + ( + $ldex¶ + ( +__x +,  +__y +)) + +869 +__ldexp_code +; + +870 + } +} + +872 +__šlše_m©hÝNP + ( +ršt +, "frndint") + +875  + #__Ìšt_code + \ + +876  +__ÌšŒes +; \ + +877 +__asm__ + +__vÞ©že__ + \ + +879 : "=m" ( +__ÌšŒes +è: "t" ( +__x +) : "st"); \ + +880  +__ÌšŒes + + + ) + +881 +__MATH_INLINE +  + +882 +__NTH + ( + $Ìštf + ( +__x +)) + +884 +__Ìšt_code +; + +885 + } +} + +886 +__MATH_INLINE +  + +887 +__NTH + ( + $Ìšt + ( +__x +)) + +889 +__Ìšt_code +; + +890 + } +} + +891 +__MATH_INLINE +  + +892 +__NTH + ( + $ÌšŽ + ( +__x +)) + +894 +__Ìšt_code +; + +895 + } +} + +896 #undeà +__Ìšt_code + + +898  + #__Îršt_code + \ + +899  +__ÎršŒes +; \ + +900 +__asm__ + +__vÞ©že__ + \ + +902 : "=m" ( +__ÎršŒes +è: "t" ( +__x +) : "st"); \ + +903  +__ÎršŒes + + + ) + +904 +__ex‹nsiÚ__ + + +905 +__MATH_INLINE +  + +906 +__NTH + ( + $Îrštf + ( +__x +)) + +908 +__Îršt_code +; + +909 + } +} + +910 +__ex‹nsiÚ__ + + +911 +__MATH_INLINE +  + +912 +__NTH + ( + $Îršt + ( +__x +)) + +914 +__Îršt_code +; + +915 + } +} + +916 +__ex‹nsiÚ__ + + +917 +__MATH_INLINE +  + +918 +__NTH + ( + $ÎršŽ + ( +__x +)) + +920 +__Îršt_code +; + +921 + } +} + +922 #undeà +__Îršt_code + + +927 #ifdeà +__USE_MISC + + +929 #ià +defšed + +__FAST_MATH__ + && ! +__GNUC_PREREQ + (3, 5) + +930 +__šlše_m©hcodeNP2 + ( +d»m +, +__x +, +__y +, \ + +931  +__v®ue +; \ + +932  +__þobb”ed +; \ + +933 +__asm + +__vÞ©že__ + \ + +938 : "ñ" ( +__v®ue +), "=&a" ( +__þobb”ed +è: "0" ( +__x +), "u" ( +__y +) : "cc"); \ + +939  +__v®ue +) + +944 +__MATH_INLINE +  + +945 +__NTH + ( + $__fš™e + ( +__x +)) + +947  ( +__ex‹nsiÚ__ + + +948 (((((uniÚ {  +__d +;  +__i +[2]; }è{__d: +__x +}).__i[1] + +950 + } +} + +955 #undeà +__©ª2_code + + +956 #ifdeà +__FAST_MATH__ + + +957 #undeà +__expm1_code + + +958 #undeà +__exp_code + + +959 #undeà +__sšcos_code + + +966 #ifdeà +__LIBC_INTERNAL_MATH_INLINES + + +967 +__šlše_m©hÝ + ( +__›“754_sq¹ +, "fsqrt") + +968 +__šlše_m©hcode2_ + (, +__›“754_©ª2l +, +__y +, +__x +, + +969  +__v®ue +; + +970 +__asm + +__vÞ©že__ + ("fpatan\n\t" + +971 : "ñ" ( +__v®ue +) + +972 : "0" ( +__x +), "u" ( +__y +) : "st(1)"); + +973  +__v®ue +;) + + @/usr/include/bits/nan.h + +19 #iâdeà +_MATH_H + + +26 #ià +__GNUC_PREREQ +(3,3) + +28  + #NAN + ( + `__bužtš_Çnf + ("")) + + ) + +30 #–ià +defšed + +__GNUC__ + + +32  + #NAN + \ + +33 ( +__ex‹nsiÚ__ + \ + +34 ((uniÚ {  +__l + + `__©Œibu‹__ + (( + `__mode__ + ( +__SI__ +)));  +__d +; }) \ + +35 { +__l +: 0x7fc00000UL }). +__d +) + + ) + +39  + ~<’dŸn.h +> + +41 #ià +__BYTE_ORDER + =ð +__BIG_ENDIAN + + +42  + #__qÇn_by‹s + { 0x7f, 0xc0, 0, 0 } + + ) + +44 #ià +__BYTE_ORDER + =ð +__LITTLE_ENDIAN + + +45  + #__qÇn_by‹s + { 0, 0, 0xc0, 0x7à} + + ) + +48 uniÚ {  + m__c +[4];  + m__d +; } +__qÇn_uniÚ + + +49 +__©Œibu‹__ + (( +__unu£d__ +)èð{ +__qÇn_by‹s + }; + +50  + #NAN + ( +__qÇn_uniÚ +. +__d +) + + ) + + @/usr/include/bits/stdlib-bsearch.h + +19 +__ex‹º_šlše + * + +20 + $b£¬ch + (cÚ¡ * +__key +, cÚ¡ * +__ba£ +, +size_t + +__nmemb +, size_ˆ +__size +, + +21 +__com·r_â_t + +__com·r +) + +23 +size_t + +__l +, +__u +, +__idx +; + +24 cÚ¡ * +__p +; + +25  +__com·risÚ +; + +27 +__l + = 0; + +28 +__u + = +__nmemb +; + +29  +__l + < +__u +) + +31 +__idx + = ( +__l + + +__u +) / 2; + +32 +__p + = (*è(((cÚ¡ *è +__ba£ +è+ ( +__idx + * +__size +)); + +33 +__com·risÚ + = (* +__com·r +è( +__key +, +__p +); + +34 ià( +__com·risÚ + < 0) + +35 +__u + = +__idx +; + +36 ià( +__com·risÚ + > 0) + +37 +__l + = +__idx + + 1; + +39  (*è +__p +; + +42  +NULL +; + +43 + } +} + + @/usr/include/bits/stdlib-float.h + +19 #iâdeà +_STDLIB_H + + +23 #ifdeà +__USE_EXTERN_INLINES + + +24 +__BEGIN_NAMESPACE_STD + + +25 +__ex‹º_šlše +  + +26 +__NTH + ( + $©of + (cÚ¡ * +__ÅŒ +)) + +28  + `¡¹od + ( +__ÅŒ +, (**è +NULL +); + +29 + } +} + +30 + g__END_NAMESPACE_STD + + + @/usr/include/bits/stdlib-ldbl.h + +19 #iâdeà +_STDLIB_H + + +23 #ifdef +__USE_ISOC99 + + +24 +__BEGIN_NAMESPACE_C99 + + +25 + $__LDBL_REDIR1_DECL + ( +¡¹Þd +, +¡¹od +) + +26 +__END_NAMESPACE_C99 + + +29 #ifdeà +__USE_GNU + + +30 + $__LDBL_REDIR1_DECL + ( +¡¹Þd_l +, +¡¹od_l +) + +33 #ifdeà +__USE_MISC + + +34 + $__LDBL_REDIR1_DECL + ( +qecvt +, +ecvt +) + +35 + $__LDBL_REDIR1_DECL + ( +qfcvt +, +fcvt +) + +36 + $__LDBL_REDIR1_DECL + ( +qgcvt +, +gcvt +) + +37 + $__LDBL_REDIR1_DECL + ( +qecvt_r +, +ecvt_r +) + +38 + $__LDBL_REDIR1_DECL + ( +qfcvt_r +, +fcvt_r +) + + @/usr/include/bits/stdlib.h + +19 #iâdeà +_STDLIB_H + + +23 * + $__»®·th_chk + (cÚ¡ * +__»¡riù + +__Çme +, + +24 * +__»¡riù + +__»sÞved +, + +25 +size_t + +__»sÞvedËn +è +__THROW + +__wur +; + +26 * + `__REDIRECT_NTH + ( +__»®·th_®Ÿs +, + +27 (cÚ¡ * +__»¡riù + +__Çme +, + +28 * +__»¡riù + +__»sÞved +), +»®·th +è +__wur +; + +29 * + `__REDIRECT_NTH + ( +__»®·th_chk_w¬n +, + +30 (cÚ¡ * +__»¡riù + +__Çme +, + +31 * +__»¡riù + +__»sÞved +, + +32 +size_t + +__»sÞvedËn +), +__»®·th_chk +è +__wur + + +33 + `__w¬Ç‰r + ("second‡rgument of„ealpath must beƒither NULL or‡t " + +36 +__fÜtify_funùiÚ + +__wur + * + +37 + `__NTH + ( + $»®·th + (cÚ¡ * +__»¡riù + +__Çme +, *__»¡riù +__»sÞved +)) + +39 ià( + `__bos + ( +__»sÞved +è!ð( +size_t +) -1) + +41 #ià +defšed + +_LIBC_LIMITS_H_ + && defšed +PATH_MAX + + +42 ià( + `__bos + ( +__»sÞved +è< +PATH_MAX +) + +43  + `__»®·th_chk_w¬n + ( +__Çme +, +__»sÞved +, + `__bos + (__resolved)); + +45  + `__»®·th_chk + ( +__Çme +, +__»sÞved +, + `__bos + (__resolved)); + +48  + `__»®·th_®Ÿs + ( +__Çme +, +__»sÞved +); + +49 + } +} + +52  + $__±¢ame_r_chk + ( +__fd +, * +__buf +, +size_t + +__buæ’ +, + +53 +size_t + +__Ä—l +è +__THROW + + `__nÚnuÎ + ((2)); + +54  + `__REDIRECT_NTH + ( +__±¢ame_r_®Ÿs +, ( +__fd +, * +__buf +, + +55 +size_t + +__buæ’ +), +±¢ame_r +) + +56 + `__nÚnuÎ + ((2)); + +57  + `__REDIRECT_NTH + ( +__±¢ame_r_chk_w¬n +, + +58 ( +__fd +, * +__buf +, +size_t + +__buæ’ +, + +59 +size_t + +__Ä—l +), +__±¢ame_r_chk +) + +60 + `__nÚnuÎ + ((2)è + `__w¬Ç‰r + ("ptsname_r called with buflen biggerhan " + +63 +__fÜtify_funùiÚ +  + +64 + `__NTH + ( + $±¢ame_r + ( +__fd +, * +__buf +, +size_t + +__buæ’ +)) + +66 ià( + `__bos + ( +__buf +è!ð( +size_t +) -1) + +68 ià(! + `__bužtš_cÚ¡ªt_p + ( +__buæ’ +)) + +69  + `__±¢ame_r_chk + ( +__fd +, +__buf +, +__buæ’ +, + `__bos + (__buf)); + +70 ià( +__buæ’ + > + `__bos + ( +__buf +)) + +71  + `__±¢ame_r_chk_w¬n + ( +__fd +, +__buf +, +__buæ’ +, + `__bos + (__buf)); + +73  + `__±¢ame_r_®Ÿs + ( +__fd +, +__buf +, +__buæ’ +); + +74 + } +} + +77  + $__wùomb_chk + (* +__s +, +wch¬_t + +__wch¬ +, +size_t + +__buæ’ +) + +78 +__THROW + +__wur +; + +79  + `__REDIRECT_NTH + ( +__wùomb_®Ÿs +, (* +__s +, +wch¬_t + +__wch¬ +), + +80 +wùomb +è +__wur +; + +82 +__fÜtify_funùiÚ + +__wur +  + +83 + `__NTH + ( + $wùomb + (* +__s +, +wch¬_t + +__wch¬ +)) + +88  + #__STDLIB_MB_LEN_MAX + 16 + + ) + +89 #ià +defšed + +MB_LEN_MAX + && MB_LEN_MAX !ð +__STDLIB_MB_LEN_MAX + + +92 ià( + `__bos + ( +__s +è!ð( +size_t +è-1 && +__STDLIB_MB_LEN_MAX + > __bos (__s)) + +93  + `__wùomb_chk + ( +__s +, +__wch¬ +, + `__bos + (__s)); + +94  + `__wùomb_®Ÿs + ( +__s +, +__wch¬ +); + +95 + } +} + +98 +size_t + + $__mb¡owcs_chk + ( +wch¬_t + * +__»¡riù + +__d¡ +, + +99 cÚ¡ * +__»¡riù + +__¤c +, + +100 +size_t + +__Ën +, size_ˆ +__d¡Ën +è +__THROW +; + +101 +size_t + + `__REDIRECT_NTH + ( +__mb¡owcs_®Ÿs +, + +102 ( +wch¬_t + * +__»¡riù + +__d¡ +, + +103 cÚ¡ * +__»¡riù + +__¤c +, + +104 +size_t + +__Ën +), +mb¡owcs +); + +105 +size_t + + `__REDIRECT_NTH + ( +__mb¡owcs_chk_w¬n +, + +106 ( +wch¬_t + * +__»¡riù + +__d¡ +, + +107 cÚ¡ * +__»¡riù + +__¤c +, + +108 +size_t + +__Ën +, size_ˆ +__d¡Ën +), +__mb¡owcs_chk +) + +109 + `__w¬Ç‰r + ("mbstowcs called with dst buffer smallerhan†en " + +112 +__fÜtify_funùiÚ + +size_t + + +113 + `__NTH + ( + $mb¡owcs + ( +wch¬_t + * +__»¡riù + +__d¡ +, cÚ¡ *__»¡riù +__¤c +, + +114 +size_t + +__Ën +)) + +116 ià( + `__bos + ( +__d¡ +è!ð( +size_t +) -1) + +118 ià(! + `__bužtš_cÚ¡ªt_p + ( +__Ën +)) + +119  + `__mb¡owcs_chk + ( +__d¡ +, +__¤c +, +__Ën +, + +120 + `__bos + ( +__d¡ +è/  ( +wch¬_t +)); + +122 ià( +__Ën + > + `__bos + ( +__d¡ +è/  ( +wch¬_t +)) + +123  + `__mb¡owcs_chk_w¬n + ( +__d¡ +, +__¤c +, +__Ën +, + +124 + `__bos + ( +__d¡ +è/  ( +wch¬_t +)); + +126  + `__mb¡owcs_®Ÿs + ( +__d¡ +, +__¤c +, +__Ën +); + +127 + } +} + +130 +size_t + + $__wc¡ombs_chk + (* +__»¡riù + +__d¡ +, + +131 cÚ¡ +wch¬_t + * +__»¡riù + +__¤c +, + +132 +size_t + +__Ën +, size_ˆ +__d¡Ën +è +__THROW +; + +133 +size_t + + `__REDIRECT_NTH + ( +__wc¡ombs_®Ÿs +, + +134 (* +__»¡riù + +__d¡ +, + +135 cÚ¡ +wch¬_t + * +__»¡riù + +__¤c +, + +136 +size_t + +__Ën +), +wc¡ombs +); + +137 +size_t + + `__REDIRECT_NTH + ( +__wc¡ombs_chk_w¬n +, + +138 (* +__»¡riù + +__d¡ +, + +139 cÚ¡ +wch¬_t + * +__»¡riù + +__¤c +, + +140 +size_t + +__Ën +, size_ˆ +__d¡Ën +), +__wc¡ombs_chk +) + +141 + `__w¬Ç‰r + ("wcstombs called with dst buffer smallerhan†en"); + +143 +__fÜtify_funùiÚ + +size_t + + +144 + `__NTH + ( + $wc¡ombs + (* +__»¡riù + +__d¡ +, cÚ¡ +wch¬_t + *__»¡riù +__¤c +, + +145 +size_t + +__Ën +)) + +147 ià( + `__bos + ( +__d¡ +è!ð( +size_t +) -1) + +149 ià(! + `__bužtš_cÚ¡ªt_p + ( +__Ën +)) + +150  + `__wc¡ombs_chk + ( +__d¡ +, +__¤c +, +__Ën +, + `__bos + (__dst)); + +151 ià( +__Ën + > + `__bos + ( +__d¡ +)) + +152  + `__wc¡ombs_chk_w¬n + ( +__d¡ +, +__¤c +, +__Ën +, + `__bos + (__dst)); + +154  + `__wc¡ombs_®Ÿs + ( +__d¡ +, +__¤c +, +__Ën +); + +155 + } +} + + @/usr/include/bits/types.h + +23 #iâdef +_BITS_TYPES_H + + +24  + #_BITS_TYPES_H + 1 + + ) + +26  + ~<ã©u»s.h +> + +27  + ~ + +30  + t__u_ch¬ +; + +31  + t__u_shÜt +; + +32  + t__u_št +; + +33  + t__u_lÚg +; + +36 sigÃd  + t__št8_t +; + +37  + t__ušt8_t +; + +38 sigÃd  + t__št16_t +; + +39  + t__ušt16_t +; + +40 sigÃd  + t__št32_t +; + +41  + t__ušt32_t +; + +42 #ià +__WORDSIZE + == 64 + +43 sigÃd  + t__št64_t +; + +44  + t__ušt64_t +; + +46 +__ex‹nsiÚ__ + sigÃd  + t__št64_t +; + +47 +__ex‹nsiÚ__ +  + t__ušt64_t +; + +51 #ià +__WORDSIZE + == 64 + +52  + t__quad_t +; + +53  + t__u_quad_t +; + +55 +__ex‹nsiÚ__ +  + t__quad_t +; + +56 +__ex‹nsiÚ__ +  + t__u_quad_t +; + +89  + #__S16_TYPE +  + + ) + +90  + #__U16_TYPE +  + + ) + +91  + #__S32_TYPE +  + + ) + +92  + #__U32_TYPE +  + + ) + +93  + #__SLONGWORD_TYPE +  + + ) + +94  + #__ULONGWORD_TYPE +  + + ) + +95 #ià +__WORDSIZE + == 32 + +96  + #__SQUAD_TYPE + +__quad_t + + + ) + +97  + #__UQUAD_TYPE + +__u_quad_t + + + ) + +98  + #__SWORD_TYPE +  + + ) + +99  + #__UWORD_TYPE +  + + ) + +100  + #__SLONG32_TYPE +  + + ) + +101  + #__ULONG32_TYPE +  + + ) + +102  + #__S64_TYPE + +__quad_t + + + ) + +103  + #__U64_TYPE + +__u_quad_t + + + ) + +106  + #__STD_TYPE + +__ex‹nsiÚ__ +  + + ) + +107 #–ià +__WORDSIZE + == 64 + +108  + t__SQUAD_TYPE +  + + ) + +109  + t__UQUAD_TYPE +  + + ) + +110  + t__SWORD_TYPE +  + + ) + +111  + t__UWORD_TYPE +  + + ) + +112  + t__SLONG32_TYPE +  + + ) + +113  + t__ULONG32_TYPE +  + + ) + +114  + t__S64_TYPE +  + + ) + +115  + t__U64_TYPE +  + + ) + +117  + t__STD_TYPE +  + + ) + +121  + ~ + +124 +__STD_TYPE + + t__DEV_T_TYPE + + t__dev_t +; + +125 +__STD_TYPE + +__UID_T_TYPE + + g__uid_t +; + +126 +__STD_TYPE + +__GID_T_TYPE + + g__gid_t +; + +127 +__STD_TYPE + +__INO_T_TYPE + + g__šo_t +; + +128 +__STD_TYPE + +__INO64_T_TYPE + + g__šo64_t +; + +129 +__STD_TYPE + +__MODE_T_TYPE + + g__mode_t +; + +130 +__STD_TYPE + +__NLINK_T_TYPE + + g__Æšk_t +; + +131 +__STD_TYPE + +__OFF_T_TYPE + + g__off_t +; + +132 +__STD_TYPE + +__OFF64_T_TYPE + + g__off64_t +; + +133 +__STD_TYPE + +__PID_T_TYPE + + g__pid_t +; + +134 +__STD_TYPE + +__FSID_T_TYPE + + g__fsid_t +; + +135 +__STD_TYPE + +__CLOCK_T_TYPE + + g__þock_t +; + +136 +__STD_TYPE + +__RLIM_T_TYPE + + g__¾im_t +; + +137 +__STD_TYPE + +__RLIM64_T_TYPE + + g__¾im64_t +; + +138 +__STD_TYPE + +__ID_T_TYPE + + g__id_t +; + +139 +__STD_TYPE + +__TIME_T_TYPE + + g__time_t +; + +140 +__STD_TYPE + +__USECONDS_T_TYPE + + g__u£cÚds_t +; + +141 +__STD_TYPE + +__SUSECONDS_T_TYPE + + g__su£cÚds_t +; + +143 +__STD_TYPE + +__DADDR_T_TYPE + + g__daddr_t +; + +144 +__STD_TYPE + +__KEY_T_TYPE + + g__key_t +; + +147 +__STD_TYPE + +__CLOCKID_T_TYPE + + g__þockid_t +; + +150 +__STD_TYPE + +__TIMER_T_TYPE + + g__tim”_t +; + +153 +__STD_TYPE + +__BLKSIZE_T_TYPE + + g__blksize_t +; + +158 +__STD_TYPE + +__BLKCNT_T_TYPE + + g__blkút_t +; + +159 +__STD_TYPE + +__BLKCNT64_T_TYPE + + g__blkút64_t +; + +162 +__STD_TYPE + +__FSBLKCNT_T_TYPE + + g__fsblkút_t +; + +163 +__STD_TYPE + +__FSBLKCNT64_T_TYPE + + g__fsblkút64_t +; + +166 +__STD_TYPE + +__FSFILCNT_T_TYPE + + g__fsfžút_t +; + +167 +__STD_TYPE + +__FSFILCNT64_T_TYPE + + g__fsfžút64_t +; + +170 +__STD_TYPE + +__FSWORD_T_TYPE + + g__fswÜd_t +; + +172 +__STD_TYPE + +__SSIZE_T_TYPE + + g__ssize_t +; + +175 +__STD_TYPE + +__SYSCALL_SLONG_TYPE + + g__sysÿÎ_¦Úg_t +; + +177 +__STD_TYPE + +__SYSCALL_ULONG_TYPE + + g__sysÿÎ_ulÚg_t +; + +181  +__off64_t + + t__loff_t +; + +182  +__quad_t + * + t__qaddr_t +; + +183 * + t__ÿddr_t +; + +186 +__STD_TYPE + +__SWORD_TYPE + + g__šŒ_t +; + +189 +__STD_TYPE + +__U32_TYPE + + g__sockËn_t +; + +192 #undeà +__STD_TYPE + + + @/usr/include/bits/waitflags.h + +19 #ià! +defšed + +_SYS_WAIT_H + && !defšed +_STDLIB_H + + +25  + #WNOHANG + 1 + + ) + +26  + #WUNTRACED + 2 + + ) + +29  + #WSTOPPED + 2 + + ) + +30  + #WEXITED + 4 + + ) + +31  + #WCONTINUED + 8 + + ) + +32  + #WNOWAIT + 0x01000000 + + ) + +34  + #__WNOTHREAD + 0x20000000 + + ) + +36  + #__WALL + 0x40000000 + + ) + +37  + #__WCLONE + 0x80000000 + + ) + +40 #ià +defšed + +__USE_XOPEN + || defšed +__USE_XOPEN2K8 + + +41 #iâdeà +__ENUM_IDTYPE_T + + +42  + #__ENUM_IDTYPE_T + 1 + + ) + +46 #undeà +P_ALL + + +47 #undeà +P_PID + + +48 #undeà +P_PGID + + +52 + mP_ALL +, + +53 + mP_PID +, + +54 + mP_PGID + + +55 } + tidty³_t +; + + @/usr/include/bits/waitstatus.h + +19 #ià! +defšed + +_SYS_WAIT_H + && !defšed +_STDLIB_H + + +28  + #__WEXITSTATUS +( +¡©us +è(((¡©usè& 0xff00è>> 8) + + ) + +31  + #__WTERMSIG +( +¡©us +è((¡©usè& 0x7f) + + ) + +34  + #__WSTOPSIG +( +¡©us +è + `__WEXITSTATUS +(¡©us) + + ) + +37  + #__WIFEXITED +( +¡©us +è( + `__WTERMSIG +(¡©usè=ð0) + + ) + +40  + #__WIFSIGNALED +( +¡©us +) \ + +41 (((sigÃd è((( +¡©us +è& 0x7fè+ 1è>> 1è> 0) + + ) + +44  + #__WIFSTOPPED +( +¡©us +è(((¡©usè& 0xffè=ð0x7f) + + ) + +48 #ifdeà +WCONTINUED + + +49  + #__WIFCONTINUED +( +¡©us +è((¡©usè=ð +__W_CONTINUED +) + + ) + +53  + #__WCOREDUMP +( +¡©us +è((¡©usè& +__WCOREFLAG +) + + ) + +56  + #__W_EXITCODE +( +»t +, +sig +è(Ô‘è<< 8 | (sig)) + + ) + +57  + #__W_STOPCODE +( +sig +è((sigè<< 8 | 0x7f) + + ) + +58  + #__W_CONTINUED + 0xffff + + ) + +59  + #__WCOREFLAG + 0x80 + + ) + +62 #ifdef +__USE_MISC + + +64  + ~<’dŸn.h +> + +66  + uwa™ + + +68  + mw_¡©us +; + +71 #if +__BYTE_ORDER + =ð +__LITTLE_ENDIAN + + +72  + m__w_‹rmsig +:7; + +73  + m__w_cÜedump +:1; + +74  + m__w_»tcode +:8; + +77 #if +__BYTE_ORDER + =ð +__BIG_ENDIAN + + +79  + m__w_»tcode +:8; + +80  + m__w_cÜedump +:1; + +81  + m__w_‹rmsig +:7; + +83 } + m__wa™_‹rmš©ed +; + +86 #if +__BYTE_ORDER + =ð +__LITTLE_ENDIAN + + +87  + m__w_¡Ýv® +:8; + +88  + m__w_¡Ýsig +:8; + +91 #if +__BYTE_ORDER + =ð +__BIG_ENDIAN + + +93  + m__w_¡Ýsig +:8; + +94  + m__w_¡Ýv® +:8; + +96 } + m__wa™_¡Ý³d +; + +99  + #w_‹rmsig + +__wa™_‹rmš©ed +. +__w_‹rmsig + + + ) + +100  + #w_cÜedump + +__wa™_‹rmš©ed +. +__w_cÜedump + + + ) + +101  + #w_»tcode + +__wa™_‹rmš©ed +. +__w_»tcode + + + ) + +102  + #w_¡Ýsig + +__wa™_¡Ý³d +. +__w_¡Ýsig + + + ) + +103  + #w_¡Ýv® + +__wa™_¡Ý³d +. +__w_¡Ýv® + + + ) + + @/usr/include/endian.h + +18 #iâdef +_ENDIAN_H + + +19  + #_ENDIAN_H + 1 + + ) + +21  + ~<ã©u»s.h +> + +31  + #__LITTLE_ENDIAN + 1234 + + ) + +32  + #__BIG_ENDIAN + 4321 + + ) + +33  + #__PDP_ENDIAN + 3412 + + ) + +36  + ~ + +40 #iâdeà +__FLOAT_WORD_ORDER + + +41  + #__FLOAT_WORD_ORDER + +__BYTE_ORDER + + + ) + +44 #ifdef +__USE_MISC + + +45  + #LITTLE_ENDIAN + +__LITTLE_ENDIAN + + + ) + +46  + #BIG_ENDIAN + +__BIG_ENDIAN + + + ) + +47  + #PDP_ENDIAN + +__PDP_ENDIAN + + + ) + +48  + #BYTE_ORDER + +__BYTE_ORDER + + + ) + +51 #ià +__BYTE_ORDER + =ð +__LITTLE_ENDIAN + + +52  + #__LONG_LONG_PAIR +( +HI +, +LO +èLO, + ) +HI + +53 #–ià +__BYTE_ORDER + =ð +__BIG_ENDIAN + + +54  + #__LONG_LONG_PAIR +( +HI +, +LO +èHI, + ) +LO + +58 #ià +defšed + +__USE_MISC + && !defšed +__ASSEMBLER__ + + +60  + ~ + +62 #ià +__BYTE_ORDER + =ð +__LITTLE_ENDIAN + + +63  + #htobe16 +( +x +è + `__bsw­_16 + (x) + + ) + +64  + #htÞe16 +( +x +è(x) + + ) + +65  + #be16toh +( +x +è + `__bsw­_16 + (x) + + ) + +66  + #Ë16toh +( +x +è(x) + + ) + +68  + #htobe32 +( +x +è + `__bsw­_32 + (x) + + ) + +69  + #htÞe32 +( +x +è(x) + + ) + +70  + #be32toh +( +x +è + `__bsw­_32 + (x) + + ) + +71  + #Ë32toh +( +x +è(x) + + ) + +73  + #htobe64 +( +x +è + `__bsw­_64 + (x) + + ) + +74  + #htÞe64 +( +x +è(x) + + ) + +75  + #be64toh +( +x +è + `__bsw­_64 + (x) + + ) + +76  + #Ë64toh +( +x +è(x) + + ) + +79  + #htobe16 +( +x +è(x) + + ) + +80  + #htÞe16 +( +x +è + `__bsw­_16 + (x) + + ) + +81  + #be16toh +( +x +è(x) + + ) + +82  + #Ë16toh +( +x +è + `__bsw­_16 + (x) + + ) + +84  + #htobe32 +( +x +è(x) + + ) + +85  + #htÞe32 +( +x +è + `__bsw­_32 + (x) + + ) + +86  + #be32toh +( +x +è(x) + + ) + +87  + #Ë32toh +( +x +è + `__bsw­_32 + (x) + + ) + +89  + #htobe64 +( +x +è(x) + + ) + +90  + #htÞe64 +( +x +è + `__bsw­_64 + (x) + + ) + +91  + #be64toh +( +x +è(x) + + ) + +92  + #Ë64toh +( +x +è + `__bsw­_64 + (x) + + ) + + @/usr/include/features.h + +18 #iâdef +_FEATURES_H + + +19  + #_FEATURES_H + 1 + + ) + +97 #undeà +__USE_ISOC11 + + +98 #undeà +__USE_ISOC99 + + +99 #undeà +__USE_ISOC95 + + +100 #undeà +__USE_ISOCXX11 + + +101 #undeà +__USE_POSIX + + +102 #undeà +__USE_POSIX2 + + +103 #undeà +__USE_POSIX199309 + + +104 #undeà +__USE_POSIX199506 + + +105 #undeà +__USE_XOPEN + + +106 #undeà +__USE_XOPEN_EXTENDED + + +107 #undeà +__USE_UNIX98 + + +108 #undeà +__USE_XOPEN2K + + +109 #undeà +__USE_XOPEN2KXSI + + +110 #undeà +__USE_XOPEN2K8 + + +111 #undeà +__USE_XOPEN2K8XSI + + +112 #undeà +__USE_LARGEFILE + + +113 #undeà +__USE_LARGEFILE64 + + +114 #undeà +__USE_FILE_OFFSET64 + + +115 #undeà +__USE_MISC + + +116 #undeà +__USE_ATFILE + + +117 #undeà +__USE_GNU + + +118 #undeà +__USE_REENTRANT + + +119 #undeà +__USE_FORTIFY_LEVEL + + +120 #undeà +__KERNEL_STRICT_NAMES + + +124 #iâdeà +_LOOSE_KERNEL_NAMES + + +125  + #__KERNEL_STRICT_NAMES + + + ) + +135 #ià +defšed + +__GNUC__ + && defšed +__GNUC_MINOR__ + + +136  + #__GNUC_PREREQ +( +maj +, +mš +) \ + +137 (( +__GNUC__ + << 16è+ +__GNUC_MINOR__ + >ð(( +maj +è<< 16è+ ( +mš +)) + + ) + +139  + #__GNUC_PREREQ +( +maj +, +mš +è0 + + ) + +146 #ià( +defšed + +_BSD_SOURCE + || defšed +_SVID_SOURCE +) \ + +147 && ! +defšed + + g_DEFAULT_SOURCE + + +152 #undeà +_DEFAULT_SOURCE + + +153  + #_DEFAULT_SOURCE + 1 + + ) + +157 #ifdeà +_GNU_SOURCE + + +158 #undeà +_ISOC95_SOURCE + + +159  + #_ISOC95_SOURCE + 1 + + ) + +160 #undeà +_ISOC99_SOURCE + + +161  + #_ISOC99_SOURCE + 1 + + ) + +162 #undeà +_ISOC11_SOURCE + + +163  + #_ISOC11_SOURCE + 1 + + ) + +164 #undeà +_POSIX_SOURCE + + +165  + #_POSIX_SOURCE + 1 + + ) + +166 #undeà +_POSIX_C_SOURCE + + +167  + #_POSIX_C_SOURCE + 200809L + + ) + +168 #undeà +_XOPEN_SOURCE + + +169  + #_XOPEN_SOURCE + 700 + + ) + +170 #undeà +_XOPEN_SOURCE_EXTENDED + + +171  + #_XOPEN_SOURCE_EXTENDED + 1 + + ) + +172 #undeà +_LARGEFILE64_SOURCE + + +173  + #_LARGEFILE64_SOURCE + 1 + + ) + +174 #undeà +_DEFAULT_SOURCE + + +175  + #_DEFAULT_SOURCE + 1 + + ) + +176 #undeà +_ATFILE_SOURCE + + +177  + #_ATFILE_SOURCE + 1 + + ) + +182 #ià( +defšed + +_DEFAULT_SOURCE + \ + +183 || (! +defšed + + g__STRICT_ANSI__ + \ + +184 && ! +defšed + + g_ISOC99_SOURCE + \ + +185 && ! +defšed + + g_POSIX_SOURCE + && !defšed + g_POSIX_C_SOURCE + \ + +186 && ! +defšed + + g_XOPEN_SOURCE +)) + +187 #undeà +_DEFAULT_SOURCE + + +188  + #_DEFAULT_SOURCE + 1 + + ) + +192 #ià( +defšed + +_ISOC11_SOURCE + \ + +193 || ( +defšed + + g__STDC_VERSION__ + && __STDC_VERSION__ >= 201112L)) + +194  + #__USE_ISOC11 + 1 + + ) + +198 #ià( +defšed + +_ISOC99_SOURCE + || defšed +_ISOC11_SOURCE + \ + +199 || ( +defšed + +__STDC_VERSION__ + && __STDC_VERSION__ >= 199901L)) + +200  + #__USE_ISOC99 + 1 + + ) + +204 #ià( +defšed + +_ISOC99_SOURCE + || defšed +_ISOC11_SOURCE + \ + +205 || ( +defšed + +__STDC_VERSION__ + && __STDC_VERSION__ >= 199409L)) + +206  + #__USE_ISOC95 + 1 + + ) + +213 #ià(( +defšed + +__ýlu¥lus + && __cplusplus >= 201103L) \ + +214 || +defšed + +__GXX_EXPERIMENTAL_CXX0X__ +) + +215  + #__USE_ISOCXX11 + 1 + + ) + +221 #ifdeà +_DEFAULT_SOURCE + + +222 #ià! +defšed + +_POSIX_SOURCE + && !defšed +_POSIX_C_SOURCE + + +223  + #__USE_POSIX_IMPLICITLY + 1 + + ) + +225 #undeà +_POSIX_SOURCE + + +226  + #_POSIX_SOURCE + 1 + + ) + +227 #undeà +_POSIX_C_SOURCE + + +228  + #_POSIX_C_SOURCE + 200809L + + ) + +230 #ià((! +defšed + +__STRICT_ANSI__ + \ + +231 || ( +defšed + +_XOPEN_SOURCE + && (_XOPEN_SOURCE - 0) >= 500)) \ + +232 && ! +defšed + +_POSIX_SOURCE + && !defšed +_POSIX_C_SOURCE +) + +233  + #_POSIX_SOURCE + 1 + + ) + +234 #ià +defšed + +_XOPEN_SOURCE + && (_XOPEN_SOURCE - 0) < 500 + +235  + #_POSIX_C_SOURCE + 2 + + ) + +236 #–ià +defšed + +_XOPEN_SOURCE + && (_XOPEN_SOURCE - 0) < 600 + +237  + #_POSIX_C_SOURCE + 199506L + + ) + +238 #–ià +defšed + +_XOPEN_SOURCE + && (_XOPEN_SOURCE - 0) < 700 + +239  + #_POSIX_C_SOURCE + 200112L + + ) + +241  + #_POSIX_C_SOURCE + 200809L + + ) + +243  + #__USE_POSIX_IMPLICITLY + 1 + + ) + +246 #ià( +defšed + +_POSIX_SOURCE + \ + +247 || ( +defšed + +_POSIX_C_SOURCE + && _POSIX_C_SOURCE >= 1) \ + +248 || +defšed + +_XOPEN_SOURCE +) + +249  + #__USE_POSIX + 1 + + ) + +252 #ià +defšed + +_POSIX_C_SOURCE + && _POSIX_C_SOURCE >ð2 || defšed +_XOPEN_SOURCE + + +253  + #__USE_POSIX2 + 1 + + ) + +256 #ià +defšed + +_POSIX_C_SOURCE + && (_POSIX_C_SOURCE - 0) >= 199309L + +257  + #__USE_POSIX199309 + 1 + + ) + +260 #ià +defšed + +_POSIX_C_SOURCE + && (_POSIX_C_SOURCE - 0) >= 199506L + +261  + #__USE_POSIX199506 + 1 + + ) + +264 #ià +defšed + +_POSIX_C_SOURCE + && (_POSIX_C_SOURCE - 0) >= 200112L + +265  + #__USE_XOPEN2K + 1 + + ) + +266 #undeà +__USE_ISOC95 + + +267  + #__USE_ISOC95 + 1 + + ) + +268 #undeà +__USE_ISOC99 + + +269  + #__USE_ISOC99 + 1 + + ) + +272 #ià +defšed + +_POSIX_C_SOURCE + && (_POSIX_C_SOURCE - 0) >= 200809L + +273  + #__USE_XOPEN2K8 + 1 + + ) + +274 #undeà +_ATFILE_SOURCE + + +275  + #_ATFILE_SOURCE + 1 + + ) + +278 #ifdef +_XOPEN_SOURCE + + +279  + #__USE_XOPEN + 1 + + ) + +280 #ià( +_XOPEN_SOURCE + - 0) >= 500 + +281  + #__USE_XOPEN_EXTENDED + 1 + + ) + +282  + #__USE_UNIX98 + 1 + + ) + +283 #undeà +_LARGEFILE_SOURCE + + +284  + #_LARGEFILE_SOURCE + 1 + + ) + +285 #ià( +_XOPEN_SOURCE + - 0) >= 600 + +286 #ià( +_XOPEN_SOURCE + - 0) >= 700 + +287  + #__USE_XOPEN2K8 + 1 + + ) + +288  + #__USE_XOPEN2K8XSI + 1 + + ) + +290  + #__USE_XOPEN2K + 1 + + ) + +291  + #__USE_XOPEN2KXSI + 1 + + ) + +292 #undeà +__USE_ISOC95 + + +293  + #__USE_ISOC95 + 1 + + ) + +294 #undeà +__USE_ISOC99 + + +295  + #__USE_ISOC99 + 1 + + ) + +298 #ifdeà +_XOPEN_SOURCE_EXTENDED + + +299  + #__USE_XOPEN_EXTENDED + 1 + + ) + +304 #ifdeà +_LARGEFILE_SOURCE + + +305  + #__USE_LARGEFILE + 1 + + ) + +308 #ifdeà +_LARGEFILE64_SOURCE + + +309  + #__USE_LARGEFILE64 + 1 + + ) + +312 #ià +defšed + +_FILE_OFFSET_BITS + && _FILE_OFFSET_BITS == 64 + +313  + #__USE_FILE_OFFSET64 + 1 + + ) + +316 #ià +defšed + +_DEFAULT_SOURCE + + +317  + #__USE_MISC + 1 + + ) + +320 #ifdef +_ATFILE_SOURCE + + +321  + #__USE_ATFILE + 1 + + ) + +324 #ifdef +_GNU_SOURCE + + +325  + #__USE_GNU + 1 + + ) + +328 #ià +defšed + +_REENTRANT + || defšed +_THREAD_SAFE + + +329  + #__USE_REENTRANT + 1 + + ) + +332 #ià +defšed + +_FORTIFY_SOURCE + && _FORTIFY_SOURCE > 0 \ + +333 && +__GNUC_PREREQ + (4, 1è&& +defšed + + g__OPTIMIZE__ + && __OPTIMIZE__ > 0 + +334 #ià +_FORTIFY_SOURCE + > 1 + +335  + #__USE_FORTIFY_LEVEL + 2 + + ) + +337  + #__USE_FORTIFY_LEVEL + 1 + + ) + +340  + #__USE_FORTIFY_LEVEL + 0 + + ) + +345  + ~<¡dc-´edef.h +> + +353 #undeà +__GNU_LIBRARY__ + + +354  + #__GNU_LIBRARY__ + 6 + + ) + +358  + #__GLIBC__ + 2 + + ) + +359  + #__GLIBC_MINOR__ + 23 + + ) + +361  + #__GLIBC_PREREQ +( +maj +, +mš +) \ + +362 (( +__GLIBC__ + << 16è+ +__GLIBC_MINOR__ + >ð(( +maj +è<< 16è+ ( +mš +)) + + ) + +365 #iâdeà +__ASSEMBLER__ + + +366 #iâdeà +_SYS_CDEFS_H + + +367  + ~ + +372 #ià +defšed + +__USE_FILE_OFFSET64 + && !defšed +__REDIRECT + + +373  + #__USE_LARGEFILE + 1 + + ) + +374  + #__USE_LARGEFILE64 + 1 + + ) + +380 #ià +__GNUC_PREREQ + (2, 7è&& +defšed + +__OPTIMIZE__ + \ + +381 && ! +defšed + + g__OPTIMIZE_SIZE__ + && !defšed + g__NO_INLINE__ + \ + +382 && +defšed + + g__ex‹º_šlše + + +383  + #__USE_EXTERN_INLINES + 1 + + ) + +391  + ~ + + @/usr/include/sys/types.h + +22 #iâdef +_SYS_TYPES_H + + +23  + #_SYS_TYPES_H + 1 + + ) + +25  + ~<ã©u»s.h +> + +27 + g__BEGIN_DECLS + + +29  + ~ + +31 #ifdef +__USE_MISC + + +32 #iâdeà +__u_ch¬_defšed + + +33  +__u_ch¬ + + tu_ch¬ +; + +34  +__u_shÜt + + tu_shÜt +; + +35  +__u_št + + tu_št +; + +36  +__u_lÚg + + tu_lÚg +; + +37  +__quad_t + + tquad_t +; + +38  +__u_quad_t + + tu_quad_t +; + +39  +__fsid_t + + tfsid_t +; + +40  + #__u_ch¬_defšed + + + ) + +44  +__loff_t + + tloff_t +; + +46 #iâdeà +__šo_t_defšed + + +47 #iâdeà +__USE_FILE_OFFSET64 + + +48  +__šo_t + + tšo_t +; + +50  +__šo64_t + + tšo_t +; + +52  + #__šo_t_defšed + + + ) + +54 #ià +defšed + +__USE_LARGEFILE64 + && !defšed +__šo64_t_defšed + + +55  +__šo64_t + + tšo64_t +; + +56  + #__šo64_t_defšed + + + ) + +59 #iâdeà +__dev_t_defšed + + +60  +__dev_t + + tdev_t +; + +61  + #__dev_t_defšed + + + ) + +64 #iâdeà +__gid_t_defšed + + +65  +__gid_t + + tgid_t +; + +66  + #__gid_t_defšed + + + ) + +69 #iâdeà +__mode_t_defšed + + +70  +__mode_t + + tmode_t +; + +71  + #__mode_t_defšed + + + ) + +74 #iâdeà +__Æšk_t_defšed + + +75  +__Æšk_t + + tÆšk_t +; + +76  + #__Æšk_t_defšed + + + ) + +79 #iâdeà +__uid_t_defšed + + +80  +__uid_t + + tuid_t +; + +81  + #__uid_t_defšed + + + ) + +84 #iâdeà +__off_t_defšed + + +85 #iâdeà +__USE_FILE_OFFSET64 + + +86  +__off_t + + toff_t +; + +88  +__off64_t + + toff_t +; + +90  + #__off_t_defšed + + + ) + +92 #ià +defšed + +__USE_LARGEFILE64 + && !defšed +__off64_t_defšed + + +93  +__off64_t + + toff64_t +; + +94  + #__off64_t_defšed + + + ) + +97 #iâdeà +__pid_t_defšed + + +98  +__pid_t + + tpid_t +; + +99  + #__pid_t_defšed + + + ) + +102 #ià( +defšed + +__USE_XOPEN + || defšed +__USE_XOPEN2K8 +) \ + +103 && ! +defšed + +__id_t_defšed + + +104  +__id_t + + tid_t +; + +105  + #__id_t_defšed + + + ) + +108 #iâdeà +__ssize_t_defšed + + +109  +__ssize_t + + tssize_t +; + +110  + #__ssize_t_defšed + + + ) + +113 #ifdef +__USE_MISC + + +114 #iâdeà +__daddr_t_defšed + + +115  +__daddr_t + + tdaddr_t +; + +116  +__ÿddr_t + + tÿddr_t +; + +117  + #__daddr_t_defšed + + + ) + +121 #ià( +defšed + +__USE_MISC + || defšed +__USE_XOPEN +è&& !defšed +__key_t_defšed + + +122  +__key_t + + tkey_t +; + +123  + #__key_t_defšed + + + ) + +126 #ià +defšed + +__USE_XOPEN + || defšed +__USE_XOPEN2K8 + + +127  + #__Ãed_þock_t + + + ) + +129  + #__Ãed_time_t + + + ) + +130  + #__Ãed_tim”_t + + + ) + +131  + #__Ãed_þockid_t + + + ) + +132  + ~ + +134 #ifdeà +__USE_XOPEN + + +135 #iâdeà +__u£cÚds_t_defšed + + +136  +__u£cÚds_t + + tu£cÚds_t +; + +137  + #__u£cÚds_t_defšed + + + ) + +139 #iâdeà +__su£cÚds_t_defšed + + +140  +__su£cÚds_t + + tsu£cÚds_t +; + +141  + #__su£cÚds_t_defšed + + + ) + +145  + #__Ãed_size_t + + + ) + +146  + ~<¡ddef.h +> + +148 #ifdeà +__USE_MISC + + +150  + tulÚg +; + +151  + tushÜt +; + +152  + tušt +; + +157 #ià! +__GNUC_PREREQ + (2, 7) + +160 #iâdeà +__št8_t_defšed + + +161  + #__št8_t_defšed + + + ) + +162  + tšt8_t +; + +163  + tšt16_t +; + +164  + tšt32_t +; + +165 #ià +__WORDSIZE + == 64 + +166  + tšt64_t +; + +168 +__ex‹nsiÚ__ +  + tšt64_t +; + +173  + tu_št8_t +; + +174  + tu_št16_t +; + +175  + tu_št32_t +; + +176 #ià +__WORDSIZE + == 64 + +177  + tu_št64_t +; + +179 +__ex‹nsiÚ__ +  + tu_št64_t +; + +182  + t»gi¡”_t +; + +187  + #__štN_t +( +N +, +MODE +) \ + +188 ## + tN +## + t_t + + t__©Œibu‹__ + (( + t__mode__ + ( + tMODE +))) + + ) + +189  + t__u_štN_t +( + tN +, + tMODE +) \ + +190  + tu_št +## + tN +## + t_t + + t__©Œibu‹__ + (( + t__mode__ + ( + tMODE +))) + + ) + +192 #iâdeà + t__št8_t_defšed + + +193  + t__št8_t_defšed + + + ) + +194 + t__štN_t + (8, + t__QI__ +); + +195 +__štN_t + (16, +__HI__ +); + +196 +__štN_t + (32, +__SI__ +); + +197 +__štN_t + (64, +__DI__ +); + +200 +__u_štN_t + (8, +__QI__ +); + +201 +__u_štN_t + (16, +__HI__ +); + +202 +__u_štN_t + (32, +__SI__ +); + +203 +__u_štN_t + (64, +__DI__ +); + +205  + t»gi¡”_t + + t__©Œibu‹__ + (( + t__mode__ + ( + t__wÜd__ +))); + +211  + #__BIT_TYPES_DEFINED__ + 1 + + ) + +214 #ifdef +__USE_MISC + + +216  + ~<’dŸn.h +> + +219  + ~ + +222  + ~ + +226 #ià( +defšed + +__USE_UNIX98 + || defšed +__USE_XOPEN2K8 +) \ + +227 && ! +defšed + +__blksize_t_defšed + + +228  +__blksize_t + + tblksize_t +; + +229  + #__blksize_t_defšed + + + ) + +233 #iâdeà +__USE_FILE_OFFSET64 + + +234 #iâdeà +__blkút_t_defšed + + +235  +__blkút_t + + tblkút_t +; + +236  + #__blkút_t_defšed + + + ) + +238 #iâdeà +__fsblkút_t_defšed + + +239  +__fsblkút_t + + tfsblkút_t +; + +240  + #__fsblkút_t_defšed + + + ) + +242 #iâdeà +__fsfžút_t_defšed + + +243  +__fsfžút_t + + tfsfžút_t +; + +244  + #__fsfžút_t_defšed + + + ) + +247 #iâdeà +__blkút_t_defšed + + +248  +__blkút64_t + + tblkút_t +; + +249  + #__blkút_t_defšed + + + ) + +251 #iâdeà +__fsblkút_t_defšed + + +252  +__fsblkút64_t + + tfsblkút_t +; + +253  + #__fsblkút_t_defšed + + + ) + +255 #iâdeà +__fsfžút_t_defšed + + +256  +__fsfžút64_t + + tfsfžút_t +; + +257  + #__fsfžút_t_defšed + + + ) + +261 #ifdeà +__USE_LARGEFILE64 + + +262  +__blkút64_t + + tblkút64_t +; + +263  +__fsblkút64_t + + tfsblkút64_t +; + +264  +__fsfžút64_t + + tfsfžút64_t +; + +269 #ià +defšed + +__USE_POSIX199506 + || defšed +__USE_UNIX98 + + +270  + ~ + +273 + g__END_DECLS + + + @/usr/include/xlocale.h + +20 #iâdeà +_XLOCALE_H + + +21  + #_XLOCALE_H + 1 + + ) + +27  + s__loÿË_¡ruù + + +30  +__loÿË_d©a + * + m__loÿËs +[13]; + +33 cÚ¡ * + m__ùy³_b +; + +34 cÚ¡ * + m__ùy³_tÞow” +; + +35 cÚ¡ * + m__ùy³_touµ” +; + +38 cÚ¡ * + m__Çmes +[13]; + +39 } * + t__loÿË_t +; + +42  +__loÿË_t + + tloÿË_t +; + + @/usr/include/bits/byteswap.h + +19 #ià! +defšed + +_BYTESWAP_H + && !defšed +_NETINET_IN_H + && !defšed +_ENDIAN_H + + +23 #iâdeà +_BITS_BYTESWAP_H + + +24  + #_BITS_BYTESWAP_H + 1 + + ) + +26  + ~<ã©u»s.h +> + +27  + ~ + +28  + ~ + +31  + #__bsw­_cÚ¡ªt_16 +( +x +) \ + +32 ((è(((( +x +è>> 8è& 0xffè| (((xè& 0xffè<< 8))) + + ) + +35  + ~ + +38  + #__bsw­_cÚ¡ªt_32 +( +x +) \ + +39 (((( +x +) & 0xff000000) >> 24) | (((x) & 0x00ff0000) >> 8) | \ + +40 ((( +x +è& 0x0000ff00è<< 8è| (((xè& 0x000000ffè<< 24)) + + ) + +42 #ifdeà +__GNUC__ + + +43 #ià +__GNUC_PREREQ + (4, 3) + +44  +__šlše +  + +45 + $__bsw­_32 + ( +__bsx +) + +47  + `__bužtš_bsw­32 + ( +__bsx +); + +48 + } +} + +49 #–ià +__GNUC__ + >= 2 + +50 #ià +__WORDSIZE + =ð64 || ( +defšed + +__i486__ + || defšed +__³Áium__ + \ + +51 || +defšed + + g__³Áium´o__ + || defšed + g__³Áium4__ + \ + +52 || +defšed + + g__k8__ + || defšed + g__©hlÚ__ + \ + +53 || +defšed + + g__k6__ + || defšed + g__nocÚa__ + \ + +54 || +defšed + + g__cÜe2__ + || defšed + g__geode__ + \ + +55 || +defšed + + g__amdçm10__ +) + +58  + #__bsw­_32 +( +x +) \ + +59 ( +__ex‹nsiÚ__ + \ + +60 ({  +__v +, +__x + = ( +x +); \ + +61 ià( + `__bužtš_cÚ¡ªt_p + ( +__x +)) \ + +62 +__v + = + `__bsw­_cÚ¡ªt_32 + ( +__x +); \ + +64 + `__asm__ + ("bsw­ %0" : "ô" ( +__v +è: "0" ( +__x +)); \ + +65 +__v +; })) + + ) + +67  + #__bsw­_32 +( +x +) \ + +68 ( +__ex‹nsiÚ__ + \ + +69 ({  +__v +, +__x + = ( +x +); \ + +70 ià( + `__bužtš_cÚ¡ªt_p + ( +__x +)) \ + +71 +__v + = + `__bsw­_cÚ¡ªt_32 + ( +__x +); \ + +73 + `__asm__ + ("rorw $8, %w0;" \ + +76 : "ô" ( +__v +) \ + +77 : "0" ( +__x +) \ + +79 +__v +; })) + + ) + +82  + #__bsw­_32 +( +x +) \ + +83 ( +__ex‹nsiÚ__ + \ + +84 ({  +__x + = ( +x +); + `__bsw­_cÚ¡ªt_32 + (__x); })) + + ) + +87  +__šlše +  + +88 + $__bsw­_32 + ( +__bsx +) + +90  + `__bsw­_cÚ¡ªt_32 + ( +__bsx +); + +91 + } +} + +95 #ià +__GNUC_PREREQ + (2, 0) + +97  + #__bsw­_cÚ¡ªt_64 +( +x +) \ + +98 ( + `__ex‹nsiÚ__ + (((( +x +) & 0xff00000000000000ull) >> 56) \ + +99 | ((( +x +) & 0x00ff000000000000ull) >> 40) \ + +100 | ((( +x +) & 0x0000ff0000000000ull) >> 24) \ + +101 | ((( +x +) & 0x000000ff00000000ull) >> 8) \ + +102 | ((( +x +) & 0x00000000ff000000ull) << 8) \ + +103 | ((( +x +) & 0x0000000000ff0000ull) << 24) \ + +104 | ((( +x +) & 0x000000000000ff00ull) << 40) \ + +105 | ((( +x +è& 0x00000000000000ffuÎè<< 56))) + + ) + +107 #ià +__GNUC_PREREQ + (4, 3) + +108  +__šlše + +__ušt64_t + + +109 + $__bsw­_64 + ( +__ušt64_t + +__bsx +) + +111  + `__bužtš_bsw­64 + ( +__bsx +); + +112 + } +} + +113 #–ià +__WORDSIZE + == 64 + +114  + #__bsw­_64 +( +x +) \ + +115 ( +__ex‹nsiÚ__ + \ + +116 ({ +__ušt64_t + +__v +, +__x + = ( +x +); \ + +117 ià( + `__bužtš_cÚ¡ªt_p + ( +__x +)) \ + +118 +__v + = + `__bsw­_cÚ¡ªt_64 + ( +__x +); \ + +120 + `__asm__ + ("bsw­ %q0" : "ô" ( +__v +è: "0" ( +__x +)); \ + +121 +__v +; })) + + ) + +123  + #__bsw­_64 +( +x +) \ + +124 ( +__ex‹nsiÚ__ + \ + +125 ({ uniÚ { +__ex‹nsiÚ__ + +__ušt64_t + +__Î +; \ + +126  +__l +[2]; } +__w +, +__r +; \ + +127 ià( + `__bužtš_cÚ¡ªt_p + ( +x +)) \ + +128 +__r +. +__Î + = + `__bsw­_cÚ¡ªt_64 + ( +x +); \ + +131 +__w +. +__Î + = ( +x +); \ + +132 +__r +. +__l +[0] = + `__bsw­_32 + ( +__w +.__l[1]); \ + +133 +__r +. +__l +[1] = + `__bsw­_32 + ( +__w +.__l[0]); \ + +135 +__r +. +__Î +; })) + + ) + +138  + #__bsw­_cÚ¡ªt_64 +( +x +) \ + +139 (((( +x +) & 0xff00000000000000ull) >> 56) \ + +140 | ((( +x +) & 0x00ff000000000000ull) >> 40) \ + +141 | ((( +x +) & 0x0000ff0000000000ull) >> 24) \ + +142 | ((( +x +) & 0x000000ff00000000ull) >> 8) \ + +143 | ((( +x +) & 0x00000000ff000000ull) << 8) \ + +144 | ((( +x +) & 0x0000000000ff0000ull) << 24) \ + +145 | ((( +x +) & 0x000000000000ff00ull) << 40) \ + +146 | ((( +x +è& 0x00000000000000ffuÎè<< 56)) + + ) + +148  +__šlše + +__ušt64_t + + +149 + $__bsw­_64 + ( +__ušt64_t + +__bsx +) + +151  + `__bsw­_cÚ¡ªt_64 + ( +__bsx +); + +152 + } +} + + @/usr/include/bits/endian.h + +3 #iâdeà +_ENDIAN_H + + +7  + #__BYTE_ORDER + +__LITTLE_ENDIAN + + + ) + + @/usr/include/bits/libm-simd-decl-stubs.h + +19 #iâdeà +_MATH_H + + +33 #iâdeà +_BITS_LIBM_SIMD_DECL_STUBS_H + + +34  + #_BITS_LIBM_SIMD_DECL_STUBS_H + 1 + + ) + +36  + #__DECL_SIMD_cos + + + ) + +37  + #__DECL_SIMD_cosf + + + ) + +38  + #__DECL_SIMD_co¦ + + + ) + +40  + #__DECL_SIMD_sš + + + ) + +41  + #__DECL_SIMD_sšf + + + ) + +42  + #__DECL_SIMD_sšl + + + ) + +44  + #__DECL_SIMD_sšcos + + + ) + +45  + #__DECL_SIMD_sšcosf + + + ) + +46  + #__DECL_SIMD_sšco¦ + + + ) + +48  + #__DECL_SIMD_log + + + ) + +49  + #__DECL_SIMD_logf + + + ) + +50  + #__DECL_SIMD_logl + + + ) + +52  + #__DECL_SIMD_exp + + + ) + +53  + #__DECL_SIMD_expf + + + ) + +54  + #__DECL_SIMD_ex¶ + + + ) + +56  + #__DECL_SIMD_pow + + + ) + +57  + #__DECL_SIMD_powf + + + ) + +58  + #__DECL_SIMD_powl + + + ) + + @/usr/include/bits/pthreadtypes.h + +18 #iâdeà +_BITS_PTHREADTYPES_H + + +19  + #_BITS_PTHREADTYPES_H + 1 + + ) + +21  + ~ + +23 #ifdeà +__x86_64__ + + +24 #ià +__WORDSIZE + == 64 + +25  + #__SIZEOF_PTHREAD_ATTR_T + 56 + + ) + +26  + #__SIZEOF_PTHREAD_MUTEX_T + 40 + + ) + +27  + #__SIZEOF_PTHREAD_MUTEXATTR_T + 4 + + ) + +28  + #__SIZEOF_PTHREAD_COND_T + 48 + + ) + +29  + #__SIZEOF_PTHREAD_CONDATTR_T + 4 + + ) + +30  + #__SIZEOF_PTHREAD_RWLOCK_T + 56 + + ) + +31  + #__SIZEOF_PTHREAD_RWLOCKATTR_T + 8 + + ) + +32  + #__SIZEOF_PTHREAD_BARRIER_T + 32 + + ) + +33  + #__SIZEOF_PTHREAD_BARRIERATTR_T + 4 + + ) + +35  + #__SIZEOF_PTHREAD_ATTR_T + 32 + + ) + +36  + #__SIZEOF_PTHREAD_MUTEX_T + 32 + + ) + +37  + #__SIZEOF_PTHREAD_MUTEXATTR_T + 4 + + ) + +38  + #__SIZEOF_PTHREAD_COND_T + 48 + + ) + +39  + #__SIZEOF_PTHREAD_CONDATTR_T + 4 + + ) + +40  + #__SIZEOF_PTHREAD_RWLOCK_T + 44 + + ) + +41  + #__SIZEOF_PTHREAD_RWLOCKATTR_T + 8 + + ) + +42  + #__SIZEOF_PTHREAD_BARRIER_T + 20 + + ) + +43  + #__SIZEOF_PTHREAD_BARRIERATTR_T + 4 + + ) + +46  + #__SIZEOF_PTHREAD_ATTR_T + 36 + + ) + +47  + #__SIZEOF_PTHREAD_MUTEX_T + 24 + + ) + +48  + #__SIZEOF_PTHREAD_MUTEXATTR_T + 4 + + ) + +49  + #__SIZEOF_PTHREAD_COND_T + 48 + + ) + +50  + #__SIZEOF_PTHREAD_CONDATTR_T + 4 + + ) + +51  + #__SIZEOF_PTHREAD_RWLOCK_T + 32 + + ) + +52  + #__SIZEOF_PTHREAD_RWLOCKATTR_T + 8 + + ) + +53  + #__SIZEOF_PTHREAD_BARRIER_T + 20 + + ) + +54  + #__SIZEOF_PTHREAD_BARRIERATTR_T + 4 + + ) + +60  + t±h»ad_t +; + +63  + u±h»ad_©Œ_t + + +65  + m__size +[ +__SIZEOF_PTHREAD_ATTR_T +]; + +66  + m__®ign +; + +68 #iâdeà +__have_±h»ad_©Œ_t + + +69  +±h»ad_©Œ_t + + t±h»ad_©Œ_t +; + +70  + #__have_±h»ad_©Œ_t + 1 + + ) + +74 #ifdeà +__x86_64__ + + +75  + s__±h»ad_š‹º®_li¡ + + +77  +__±h»ad_š‹º®_li¡ + * + m__´ev +; + +78  +__±h»ad_š‹º®_li¡ + * + m__Ãxt +; + +79 } + t__±h»ad_li¡_t +; + +81  + s__±h»ad_š‹º®_¦i¡ + + +83  +__±h»ad_š‹º®_¦i¡ + * + m__Ãxt +; + +84 } + t__±h»ad_¦i¡_t +; + +92  + s__±h»ad_mu‹x_s + + +94  + m__lock +; + +95  + m__couÁ +; + +96  + m__owÃr +; + +97 #ifdeà +__x86_64__ + + +98  + m__nu£rs +; + +102  + m__kšd +; + +103 #ifdeà +__x86_64__ + + +104  + m__¥šs +; + +105  + m__–isiÚ +; + +106 +__±h»ad_li¡_t + + m__li¡ +; + +107  + #__PTHREAD_MUTEX_HAVE_PREV + 1 + + ) + +109  + #__PTHREAD_SPINS + 0, 0 + + ) + +111  + m__nu£rs +; + +112 +__ex‹nsiÚ__ + union + +116  + m__e¥šs +; + +117  + m__–isiÚ +; + +118  + #__¥šs + +__–isiÚ_d©a +. +__e¥šs + + + ) + +119  + #__–isiÚ + +__–isiÚ_d©a +. +__–isiÚ + + + ) + +120  + #__PTHREAD_SPINS + { 0, 0 } + + ) + +121 } + m__–isiÚ_d©a +; + +122 +__±h»ad_¦i¡_t + + m__li¡ +; + +125 } + m__d©a +; + +126  + m__size +[ +__SIZEOF_PTHREAD_MUTEX_T +]; + +127  + m__®ign +; + +128 } + t±h»ad_mu‹x_t +; + +132  + m__size +[ +__SIZEOF_PTHREAD_MUTEXATTR_T +]; + +133  + m__®ign +; + +134 } + t±h»ad_mu‹x©Œ_t +; + +143  + m__lock +; + +144  + m__fu‹x +; + +145 +__ex‹nsiÚ__ +  + m__tÙ®_£q +; + +146 +__ex‹nsiÚ__ +  + m__wakeup_£q +; + +147 +__ex‹nsiÚ__ +  + m__wok’_£q +; + +148 * + m__mu‹x +; + +149  + m__nwa™”s +; + +150  + m__brßdÿ¡_£q +; + +151 } + m__d©a +; + +152  + m__size +[ +__SIZEOF_PTHREAD_COND_T +]; + +153 +__ex‹nsiÚ__ +  + m__®ign +; + +154 } + t±h»ad_cÚd_t +; + +158  + m__size +[ +__SIZEOF_PTHREAD_CONDATTR_T +]; + +159  + m__®ign +; + +160 } + t±h»ad_cÚd©Œ_t +; + +164  + t±h»ad_key_t +; + +168  + t±h»ad_Úû_t +; + +171 #ià +defšed + +__USE_UNIX98 + || defšed +__USE_XOPEN2K + + +176 #ifdeà +__x86_64__ + + +179  + m__lock +; + +180  + m__Ä_»ad”s +; + +181  + m__»ad”s_wakeup +; + +182  + m__wr™”_wakeup +; + +183  + m__Ä_»ad”s_queued +; + +184  + m__Ä_wr™”s_queued +; + +185  + m__wr™” +; + +186  + m__sh¬ed +; + +187 sigÃd  + m__rw–isiÚ +; + +188 #ifdeà +__ILP32__ + + +189  + m__·d1 +[3]; + +190  + #__PTHREAD_RWLOCK_ELISION_EXTRA + 0, { 0, 0, 0 } + + ) + +192  + m__·d1 +[7]; + +193  + #__PTHREAD_RWLOCK_ELISION_EXTRA + 0, { 0, 0, 0, 0, 0, 0, 0 } + + ) + +195  + m__·d2 +; + +198  + m__æags +; + +199  + #__PTHREAD_RWLOCK_INT_FLAGS_SHARED + 1 + + ) + +200 } + m__d©a +; + +204  + m__lock +; + +205  + m__Ä_»ad”s +; + +206  + m__»ad”s_wakeup +; + +207  + m__wr™”_wakeup +; + +208  + m__Ä_»ad”s_queued +; + +209  + m__Ä_wr™”s_queued +; + +212  + m__æags +; + +213  + m__sh¬ed +; + +214 sigÃd  + m__rw–isiÚ +; + +215  + #__PTHREAD_RWLOCK_ELISION_EXTRA + 0 + + ) + +216  + m__·d2 +; + +217  + m__wr™” +; + +218 } + m__d©a +; + +220  + m__size +[ +__SIZEOF_PTHREAD_RWLOCK_T +]; + +221  + m__®ign +; + +222 } + t±h»ad_rwlock_t +; + +226  + m__size +[ +__SIZEOF_PTHREAD_RWLOCKATTR_T +]; + +227  + m__®ign +; + +228 } + t±h»ad_rwlock©Œ_t +; + +232 #ifdeà +__USE_XOPEN2K + + +234 vÞ©ž + t±h»ad_¥šlock_t +; + +241  + m__size +[ +__SIZEOF_PTHREAD_BARRIER_T +]; + +242  + m__®ign +; + +243 } + t±h»ad_b¬r›r_t +; + +247  + m__size +[ +__SIZEOF_PTHREAD_BARRIERATTR_T +]; + +248  + m__®ign +; + +249 } + t±h»ad_b¬r›¿‰r_t +; + +253 #iâdeà +__x86_64__ + + +255  + #__þ—nup_fù_©Œibu‹ + + `__©Œibu‹__ + (( + `__»g·rm__ + (1))) + + ) + + @/usr/include/bits/typesizes.h + +19 #iâdeà +_BITS_TYPES_H + + +23 #iâdef +_BITS_TYPESIZES_H + + +24  + #_BITS_TYPESIZES_H + 1 + + ) + +30 #ià +defšed + +__x86_64__ + && defšed +__ILP32__ + + +31  + #__SYSCALL_SLONG_TYPE + +__SQUAD_TYPE + + + ) + +32  + #__SYSCALL_ULONG_TYPE + +__UQUAD_TYPE + + + ) + +34  + #__SYSCALL_SLONG_TYPE + +__SLONGWORD_TYPE + + + ) + +35  + #__SYSCALL_ULONG_TYPE + +__ULONGWORD_TYPE + + + ) + +38  + #__DEV_T_TYPE + +__UQUAD_TYPE + + + ) + +39  + #__UID_T_TYPE + +__U32_TYPE + + + ) + +40  + #__GID_T_TYPE + +__U32_TYPE + + + ) + +41  + #__INO_T_TYPE + +__SYSCALL_ULONG_TYPE + + + ) + +42  + #__INO64_T_TYPE + +__UQUAD_TYPE + + + ) + +43  + #__MODE_T_TYPE + +__U32_TYPE + + + ) + +44 #ifdeà +__x86_64__ + + +45  + #__NLINK_T_TYPE + +__SYSCALL_ULONG_TYPE + + + ) + +46  + #__FSWORD_T_TYPE + +__SYSCALL_SLONG_TYPE + + + ) + +48  + #__NLINK_T_TYPE + +__UWORD_TYPE + + + ) + +49  + #__FSWORD_T_TYPE + +__SWORD_TYPE + + + ) + +51  + #__OFF_T_TYPE + +__SYSCALL_SLONG_TYPE + + + ) + +52  + #__OFF64_T_TYPE + +__SQUAD_TYPE + + + ) + +53  + #__PID_T_TYPE + +__S32_TYPE + + + ) + +54  + #__RLIM_T_TYPE + +__SYSCALL_ULONG_TYPE + + + ) + +55  + #__RLIM64_T_TYPE + +__UQUAD_TYPE + + + ) + +56  + #__BLKCNT_T_TYPE + +__SYSCALL_SLONG_TYPE + + + ) + +57  + #__BLKCNT64_T_TYPE + +__SQUAD_TYPE + + + ) + +58  + #__FSBLKCNT_T_TYPE + +__SYSCALL_ULONG_TYPE + + + ) + +59  + #__FSBLKCNT64_T_TYPE + +__UQUAD_TYPE + + + ) + +60  + #__FSFILCNT_T_TYPE + +__SYSCALL_ULONG_TYPE + + + ) + +61  + #__FSFILCNT64_T_TYPE + +__UQUAD_TYPE + + + ) + +62  + #__ID_T_TYPE + +__U32_TYPE + + + ) + +63  + #__CLOCK_T_TYPE + +__SYSCALL_SLONG_TYPE + + + ) + +64  + #__TIME_T_TYPE + +__SYSCALL_SLONG_TYPE + + + ) + +65  + #__USECONDS_T_TYPE + +__U32_TYPE + + + ) + +66  + #__SUSECONDS_T_TYPE + +__SYSCALL_SLONG_TYPE + + + ) + +67  + #__DADDR_T_TYPE + +__S32_TYPE + + + ) + +68  + #__KEY_T_TYPE + +__S32_TYPE + + + ) + +69  + #__CLOCKID_T_TYPE + +__S32_TYPE + + + ) + +70  + #__TIMER_T_TYPE + * + + ) + +71  + #__BLKSIZE_T_TYPE + +__SYSCALL_SLONG_TYPE + + + ) + +72  + #__FSID_T_TYPE + sŒuù {  +__v® +[2]; } + + ) + +73  + #__SSIZE_T_TYPE + +__SWORD_TYPE + + + ) + +74  + #__CPU_MASK_TYPE + +__SYSCALL_ULONG_TYPE + + + ) + +76 #ifdeà +__x86_64__ + + +80  + #__OFF_T_MATCHES_OFF64_T + 1 + + ) + +83  + #__INO_T_MATCHES_INO64_T + 1 + + ) + +87  + #__FD_SETSIZE + 1024 + + ) + + @/usr/include/bits/wordsize.h + +3 #ià +defšed + +__x86_64__ + && !defšed +__ILP32__ + + +4  + #__WORDSIZE + 64 + + ) + +6  + #__WORDSIZE + 32 + + ) + +9 #ifdeà +__x86_64__ + + +10  + #__WORDSIZE_TIME64_COMPAT32 + 1 + + ) + +12  + #__SYSCALL_WORDSIZE + 64 + + ) + + @/usr/include/gnu/stubs.h + +6 #ià! +defšed + +__x86_64__ + + +7  + ~ + +9 #ià +defšed + +__x86_64__ + && defšed +__LP64__ + + +10  + ~ + +12 #ià +defšed + +__x86_64__ + && defšed +__ILP32__ + + +13  + ~ + + @/usr/include/stdc-predef.h + +18 #iâdef +_STDC_PREDEF_H + + +19  + #_STDC_PREDEF_H + 1 + + ) + +36 #ifdeà +__GCC_IEC_559 + + +37 #ià +__GCC_IEC_559 + > 0 + +38  + #__STDC_IEC_559__ + 1 + + ) + +41  + #__STDC_IEC_559__ + 1 + + ) + +44 #ifdeà +__GCC_IEC_559_COMPLEX + + +45 #ià +__GCC_IEC_559_COMPLEX + > 0 + +46  + #__STDC_IEC_559_COMPLEX__ + 1 + + ) + +49  + #__STDC_IEC_559_COMPLEX__ + 1 + + ) + +55  + #__STDC_ISO_10646__ + 201505L + + ) + +58  + #__STDC_NO_THREADS__ + 1 + + ) + + @/usr/include/sys/cdefs.h + +18 #iâdef +_SYS_CDEFS_H + + +19  + #_SYS_CDEFS_H + 1 + + ) + +22 #iâdeà +_FEATURES_H + + +23  + ~<ã©u»s.h +> + +29 #ià +defšed + +__GNUC__ + && !defšed +__STDC__ + + +34 #undeà +__P + + +35 #undeà +__PMT + + +37 #ifdeà +__GNUC__ + + +41 #ià +__GNUC_PREREQ + (4, 6è&& ! +defšed + +_LIBC + + +42  + #__LEAF + , +__Ëaf__ + + + ) + +43  + #__LEAF_ATTR + + `__©Œibu‹__ + (( +__Ëaf__ +)) + + ) + +45  + #__LEAF + + + ) + +46  + #__LEAF_ATTR + + + ) + +54 #ià! +defšed + +__ýlu¥lus + && +__GNUC_PREREQ + (3, 3) + +55  + #__THROW + + `__©Œibu‹__ + (( +__nÙhrow__ + +__LEAF +)) + + ) + +56  + #__THROWNL + + `__©Œibu‹__ + (( +__nÙhrow__ +)) + + ) + +57  + #__NTH +( +fù +è + `__©Œibu‹__ + (( +__nÙhrow__ + +__LEAF +)è + ) +fct + +59 #ià +defšed + +__ýlu¥lus + && +__GNUC_PREREQ + (2,8) + +60  + #__THROW + + `throw + () + + ) + +61  + #__THROWNL + + `throw + () + + ) + +62  + #__NTH +( +fù +è +__LEAF_ATTR + fù + `throw + () + + ) + +64  + #__THROW + + + ) + +65  + #__THROWNL + + + ) + +66  + #__NTH +( +fù +è + ) +fct + +72  + #__šlše + + + ) + +74  + #__THROW + + + ) + +75  + #__THROWNL + + + ) + +76  + #__NTH +( +fù +è + ) +fct + +82  + #__P +( +¬gs +è + ) +args + +83  + #__PMT +( +¬gs +è + ) +args + +88  + #__CONCAT +( +x +, +y +èx ## + ) +y + +89  + #__STRING +( +x +è#x + + ) + +92  + #__±r_t + * + + ) + +93  + #__lÚg_doubË_t +  + + ) + +97 #ifdef +__ýlu¥lus + + +98  + #__BEGIN_DECLS + "C" { + + ) + +99  + #__END_DECLS + } + + ) + +101  + #__BEGIN_DECLS + + + ) + +102  + #__END_DECLS + + + ) + +111 #ià +defšed + +__ýlu¥lus + && defšed +_GLIBCPP_USE_NAMESPACES + + +112  + #__BEGIN_NAMESPACE_STD + +Çme¥aû + +¡d + { + + ) + +113  + #__END_NAMESPACE_STD + } + + ) + +114  + #__USING_NAMESPACE_STD +( +Çme +è +usšg + +¡d +::Çme; + + ) + +115  + #__BEGIN_NAMESPACE_C99 + +Çme¥aû + +__c99 + { + + ) + +116  + #__END_NAMESPACE_C99 + } + + ) + +117  + #__USING_NAMESPACE_C99 +( +Çme +è +usšg + +__c99 +::Çme; + + ) + +122  + #__BEGIN_NAMESPACE_STD + + + ) + +123  + #__END_NAMESPACE_STD + + + ) + +124  + #__USING_NAMESPACE_STD +( +Çme +) + + ) + +125  + #__BEGIN_NAMESPACE_C99 + + + ) + +126  + #__END_NAMESPACE_C99 + + + ) + +127  + #__USING_NAMESPACE_C99 +( +Çme +) + + ) + +132  + #__bos +( +±r +è + `__bužtš_objeù_size + (±r, +__USE_FORTIFY_LEVEL + > 1) + + ) + +133  + #__bos0 +( +±r +è + `__bužtš_objeù_size + (±r, 0) + + ) + +135 #ià +__GNUC_PREREQ + (4,3) + +136  + #__w¬ndeþ +( +Çme +, +msg +) \ + +137  + `Çme + (è + `__©Œibu‹__ +(( + `__w¬nšg__ + ( +msg +))) + + ) + +138  + #__w¬Ç‰r +( +msg +è + `__©Œibu‹__ +(( + `__w¬nšg__ + (msg))) + + ) + +139  + #__”rÜdeþ +( +Çme +, +msg +) \ + +140  + `Çme + (è + `__©Œibu‹__ +(( + `__”rÜ__ + ( +msg +))) + + ) + +142  + #__w¬ndeþ +( +Çme +, +msg +è  + `Çme + () + + ) + +143  + #__w¬Ç‰r +( +msg +) + + ) + +144  + #__”rÜdeþ +( +Çme +, +msg +è  + `Çme + () + + ) + +148 #ià +__GNUC_PREREQ + (2,97) + +150  + #__æex¬r + [] + + ) + +152 #ifdeà +__GNUC__ + + +153  + #__æex¬r + [0] + + ) + +155 #ià +defšed + +__STDC_VERSION__ + && __STDC_VERSION__ >= 199901L + +156  + #__æex¬r + [] + + ) + +159  + #__æex¬r + [1] + + ) + +175 #ià +defšed + +__GNUC__ + && __GNUC__ >= 2 + +177  + #__REDIRECT +( +Çme +, +´Ùo +, +®Ÿs +èÇm´ÙØ + `__asm__ + ( + `__ASMNAME + (#®Ÿs)) + + ) + +178 #ifdeà +__ýlu¥lus + + +179  + #__REDIRECT_NTH +( +Çme +, +´Ùo +, +®Ÿs +) \ + +180 +Çme + +´Ùo + +__THROW + + `__asm__ + ( + `__ASMNAME + (#®Ÿs)) + + ) + +181  + #__REDIRECT_NTHNL +( +Çme +, +´Ùo +, +®Ÿs +) \ + +182 +Çme + +´Ùo + +__THROWNL + + `__asm__ + ( + `__ASMNAME + (#®Ÿs)) + + ) + +184  + #__REDIRECT_NTH +( +Çme +, +´Ùo +, +®Ÿs +) \ + +185 +Çme + +´Ùo + + `__asm__ + ( + `__ASMNAME + (#®Ÿs)è +__THROW + + + ) + +186  + #__REDIRECT_NTHNL +( +Çme +, +´Ùo +, +®Ÿs +) \ + +187 +Çme + +´Ùo + + `__asm__ + ( + `__ASMNAME + (#®Ÿs)è +__THROWNL + + + ) + +189  + #__ASMNAME +( +úame +è + `__ASMNAME2 + ( +__USER_LABEL_PREFIX__ +, cÇme) + + ) + +190  + #__ASMNAME2 +( +´efix +, +úame +è + `__STRING + (´efixè + ) +cname + +203 #ià! +defšed + +__GNUC__ + || __GNUC__ < 2 + +204  + #__©Œibu‹__ +( +xyz +è + + ) + +210 #ià +__GNUC_PREREQ + (2,96) + +211  + #__©Œibu‹_m®loc__ + + `__©Œibu‹__ + (( +__m®loc__ +)) + + ) + +213  + #__©Œibu‹_m®loc__ + + + ) + +218 #ià +__GNUC_PREREQ + (4, 3) + +219  + #__©Œibu‹_®loc_size__ +( +·¿ms +) \ + +220 + `__©Œibu‹__ + (( +__®loc_size__ + +·¿ms +)) + + ) + +222  + #__©Œibu‹_®loc_size__ +( +·¿ms +è + + ) + +228 #ià +__GNUC_PREREQ + (2,96) + +229  + #__©Œibu‹_pu»__ + + `__©Œibu‹__ + (( +__pu»__ +)) + + ) + +231  + #__©Œibu‹_pu»__ + + + ) + +235 #ià +__GNUC_PREREQ + (2,5) + +236  + #__©Œibu‹_cÚ¡__ + + `__©Œibu‹__ + (( +__cÚ¡__ +)) + + ) + +238  + #__©Œibu‹_cÚ¡__ + + + ) + +244 #ià +__GNUC_PREREQ + (3,1) + +245  + #__©Œibu‹_u£d__ + + `__©Œibu‹__ + (( +__u£d__ +)) + + ) + +246  + #__©Œibu‹_nošlše__ + + `__©Œibu‹__ + (( +__nošlše__ +)) + + ) + +248  + #__©Œibu‹_u£d__ + + `__©Œibu‹__ + (( +__unu£d__ +)) + + ) + +249  + #__©Œibu‹_nošlše__ + + + ) + +253 #ià +__GNUC_PREREQ + (3,2) + +254  + #__©Œibu‹_d•»ÿ‹d__ + + `__©Œibu‹__ + (( +__d•»ÿ‹d__ +)) + + ) + +256  + #__©Œibu‹_d•»ÿ‹d__ + + + ) + +265 #ià +__GNUC_PREREQ + (2,8) + +266  + #__©Œibu‹_fÜm©_¬g__ +( +x +è + `__©Œibu‹__ + (( + `__fÜm©_¬g__ + (x))) + + ) + +268  + #__©Œibu‹_fÜm©_¬g__ +( +x +è + + ) + +275 #ià +__GNUC_PREREQ + (2,97) + +276  + #__©Œibu‹_fÜm©_¡rfmÚ__ +( +a +, +b +) \ + +277 + `__©Œibu‹__ + (( + `__fÜm©__ + ( +__¡rfmÚ__ +, +a +, +b +))) + + ) + +279  + #__©Œibu‹_fÜm©_¡rfmÚ__ +( +a +, +b +è + + ) + +284 #ià +__GNUC_PREREQ + (3,3) + +285  + #__nÚnuÎ +( +·¿ms +è + `__©Œibu‹__ + (( +__nÚnuÎ__ +…¬ams)) + + ) + +287  + #__nÚnuÎ +( +·¿ms +) + + ) + +292 #ià +__GNUC_PREREQ + (3,4) + +293  + #__©Œibu‹_w¬n_unu£d_»suÉ__ + \ + +294 + `__©Œibu‹__ + (( +__w¬n_unu£d_»suÉ__ +)) + + ) + +295 #ià +__USE_FORTIFY_LEVEL + > 0 + +296  + #__wur + +__©Œibu‹_w¬n_unu£d_»suÉ__ + + + ) + +299  + #__©Œibu‹_w¬n_unu£d_»suÉ__ + + + ) + +301 #iâdeà +__wur + + +302  + #__wur + + + ) + +306 #ià +__GNUC_PREREQ + (3,2) + +307  + #__®ways_šlše + +__šlše + + `__©Œibu‹__ + (( +__®ways_šlše__ +)) + + ) + +309  + #__®ways_šlše + +__šlše + + + ) + +314 #ià +__GNUC_PREREQ + (4,3) + +315  + #__©Œibu‹_¬tificŸl__ + + `__©Œibu‹__ + (( +__¬tificŸl__ +)) + + ) + +317  + #__©Œibu‹_¬tificŸl__ + + + ) + +329 #ià(! +defšed + +__ýlu¥lus + || +__GNUC_PREREQ + (4,3) \ + +330 || ( +defšed + +__þªg__ + && (defšed +__GNUC_STDC_INLINE__ + \ + +331 || +defšed + +__GNUC_GNU_INLINE__ +))) + +332 #ià +defšed + +__GNUC_STDC_INLINE__ + || defšed +__ýlu¥lus + + +333  + #__ex‹º_šlše + +__šlše + + `__©Œibu‹__ + (( +__gnu_šlše__ +)) + + ) + +334  + #__ex‹º_®ways_šlše + \ + +335 +__®ways_šlše + + `__©Œibu‹__ + (( +__gnu_šlše__ +)) + + ) + +337  + #__ex‹º_šlše + +__šlše + + + ) + +338  + #__ex‹º_®ways_šlše + +__®ways_šlše + + + ) + +342 #ifdeà +__ex‹º_®ways_šlše + + +343  + #__fÜtify_funùiÚ + +__ex‹º_®ways_šlše + +__©Œibu‹_¬tificŸl__ + + + ) + +348 #ià +__GNUC_PREREQ + (4,3) + +349  + #__va_¬g_·ck +(è + `__bužtš_va_¬g_·ck + () + + ) + +350  + #__va_¬g_·ck_Ën +(è + `__bužtš_va_¬g_·ck_Ën + () + + ) + +357 #ià! +__GNUC_PREREQ + (2,8) + +358  + #__ex‹nsiÚ__ + + + ) + +362 #ià! +__GNUC_PREREQ + (2,92) + +363  + #__»¡riù + + + ) + +369 #ià +__GNUC_PREREQ + (3,1è&& ! +defšed + +__GNUG__ + + +370  + #__»¡riù_¬r + +__»¡riù + + + ) + +372 #ifdeà +__GNUC__ + + +373  + #__»¡riù_¬r + + + ) + +375 #ià +defšed + +__STDC_VERSION__ + && __STDC_VERSION__ >= 199901L + +376  + #__»¡riù_¬r + +»¡riù + + + ) + +379  + #__»¡riù_¬r + + + ) + +384 #ià +__GNUC__ + >= 3 + +385  + #__glibc_uÆik–y +( +cÚd +è + `__bužtš_ex³ù + ((cÚd), 0) + + ) + +386  + #__glibc_lik–y +( +cÚd +è + `__bužtš_ex³ù + ((cÚd), 1) + + ) + +388  + #__glibc_uÆik–y +( +cÚd +è(cÚd) + + ) + +389  + #__glibc_lik–y +( +cÚd +è(cÚd) + + ) + +392 #ià(! +defšed + +_NÜ‘uº + \ + +393 && ( +defšed + +__STDC_VERSION__ + ? __STDC_VERSION__ : 0) < 201112 \ + +394 && ! + $__GNUC_PREREQ + (4,7)) + +395 #ià + `__GNUC_PREREQ + (2,8) + +396  + #_NÜ‘uº + + `__©Œibu‹__ + (( +__nÜ‘uº__ +)) + + ) + +398  + #_NÜ‘uº + + + ) + +402 #ià(! +defšed + +_Stic_as£¹ + && !defšed +__ýlu¥lus + \ + +403 && ( +defšed + +__STDC_VERSION__ + ? __STDC_VERSION__ : 0) < 201112 \ + +404 && (! + `__GNUC_PREREQ + (4, 6è|| +defšed + +__STRICT_ANSI__ +)) + +405  + #_Stic_as£¹ +( +ex´ +, +dŸgno¡ic +) \ + +406 (* + `__Stic_as£¹_funùiÚ + ()) \ + +407 [!! (¡ruù {  +__”rÜ_if_Ãg©ive +: ( +ex´ +è? 2 : -1; })] + + ) + +410  + ~ + +412 #ià +defšed + +__LONG_DOUBLE_MATH_OPTIONAL + && defšed +__NO_LONG_DOUBLE_MATH + + +413  + #__LDBL_COMPAT + 1 + + ) + +414 #ifdeà +__REDIRECT + + +415  + #__LDBL_REDIR1 +( +Çme +, +´Ùo +, +®Ÿs +è + `__REDIRECT + (Çme,…rÙo,‡lŸs) + + ) + +416  + #__LDBL_REDIR +( +Çme +, +´Ùo +) \ + +417 + `__LDBL_REDIR1 + ( +Çme +, +´Ùo +, +__Ædbl_ +##Çme) + + ) + +418  + #__LDBL_REDIR1_NTH +( +Çme +, +´Ùo +, +®Ÿs +è + `__REDIRECT_NTH + (Çme,…rÙo,‡lŸs) + + ) + +419  + #__LDBL_REDIR_NTH +( +Çme +, +´Ùo +) \ + +420 + `__LDBL_REDIR1_NTH + ( +Çme +, +´Ùo +, +__Ædbl_ +##Çme) + + ) + +421  + #__LDBL_REDIR1_DECL +( +Çme +, +®Ÿs +) \ + +422 + `__ty³of + ( +Çme +èÇm + `__asm + ( + `__ASMNAME + (#®Ÿs)); + + ) + +423  + #__LDBL_REDIR_DECL +( +Çme +) \ + +424 + `__ty³of + ( +Çme +èÇm + `__asm + ( + `__ASMNAME + ("__Ædbl_" #Çme)); + + ) + +425  + #__REDIRECT_LDBL +( +Çme +, +´Ùo +, +®Ÿs +) \ + +426 + `__LDBL_REDIR1 + ( +Çme +, +´Ùo +, +__Ædbl_ +## +®Ÿs +) + + ) + +427  + #__REDIRECT_NTH_LDBL +( +Çme +, +´Ùo +, +®Ÿs +) \ + +428 + `__LDBL_REDIR1_NTH + ( +Çme +, +´Ùo +, +__Ædbl_ +## +®Ÿs +) + + ) + +431 #ià! +defšed + +__LDBL_COMPAT + || !defšed +__REDIRECT + + +432  + #__LDBL_REDIR1 +( +Çme +, +´Ùo +, +®Ÿs +èÇm + ) +proto + +433  + #__LDBL_REDIR +( +Çme +, +´Ùo +èÇm + ) +proto + +434  + #__LDBL_REDIR1_NTH +( +Çme +, +´Ùo +, +®Ÿs +èÇm´ÙØ +__THROW + + + ) + +435  + #__LDBL_REDIR_NTH +( +Çme +, +´Ùo +èÇm´ÙØ +__THROW + + + ) + +436  + #__LDBL_REDIR_DECL +( +Çme +) + + ) + +437 #ifdeà +__REDIRECT + + +438  + #__REDIRECT_LDBL +( +Çme +, +´Ùo +, +®Ÿs +è + `__REDIRECT + (Çme,…rÙo,‡lŸs) + + ) + +439  + #__REDIRECT_NTH_LDBL +( +Çme +, +´Ùo +, +®Ÿs +) \ + +440 + `__REDIRECT_NTH + ( +Çme +, +´Ùo +, +®Ÿs +) + + ) + + @/usr/include/sys/select.h + +21 #iâdeà +_SYS_SELECT_H + + +22  + #_SYS_SELECT_H + 1 + + ) + +24  + ~<ã©u»s.h +> + +27  + ~ + +30  + ~ + +33  + ~ + +35 #iâdeà +__sig£t_t_defšed + + +36  + #__sig£t_t_defšed + + + ) + +37  +__sig£t_t + + tsig£t_t +; + +41  + #__Ãed_time_t + + + ) + +42  + #__Ãed_time¥ec + + + ) + +43  + ~ + +44  + #__Ãed_timev® + + + ) + +45  + ~ + +47 #iâdeà +__su£cÚds_t_defšed + + +48  +__su£cÚds_t + + tsu£cÚds_t +; + +49  + #__su£cÚds_t_defšed + + + ) + +54  + t__fd_mask +; + +57 #undeà +__NFDBITS + + +59  + #__NFDBITS + (8 * (è ( +__fd_mask +)) + + ) + +60  + #__FD_ELT +( +d +è((dè/ +__NFDBITS +) + + ) + +61  + #__FD_MASK +( +d +è(( +__fd_mask +è(1UL << ((dè% +__NFDBITS +))) + + ) + +68 #ifdeà +__USE_XOPEN + + +69 +__fd_mask + + mfds_b™s +[ +__FD_SETSIZE + / +__NFDBITS +]; + +70  + #__FDS_BITS +( +£t +è((£t)-> +fds_b™s +) + + ) + +72 +__fd_mask + + m__fds_b™s +[ +__FD_SETSIZE + / +__NFDBITS +]; + +73  + #__FDS_BITS +( +£t +è((£t)-> +__fds_b™s +) + + ) + +75 } + tfd_£t +; + +78  + #FD_SETSIZE + +__FD_SETSIZE + + + ) + +80 #ifdeà +__USE_MISC + + +82  +__fd_mask + + tfd_mask +; + +85  + #NFDBITS + +__NFDBITS + + + ) + +90  + #FD_SET +( +fd +, +fd£ +è + `__FD_SET + (fd, fd£) + + ) + +91  + #FD_CLR +( +fd +, +fd£ +è + `__FD_CLR + (fd, fd£) + + ) + +92  + #FD_ISSET +( +fd +, +fd£ +è + `__FD_ISSET + (fd, fd£) + + ) + +93  + #FD_ZERO +( +fd£ +è + `__FD_ZERO + (fd£) + + ) + +96 +__BEGIN_DECLS + + +106  +£Ëù + ( +__nfds +, +fd_£t + * +__»¡riù + +__»adfds +, + +107 +fd_£t + * +__»¡riù + +__wr™efds +, + +108 +fd_£t + * +__»¡riù + +__exû±fds +, + +109  +timev® + * +__»¡riù + +__timeout +); + +111 #ifdeà +__USE_XOPEN2K + + +118  +p£Ëù + ( +__nfds +, +fd_£t + * +__»¡riù + +__»adfds +, + +119 +fd_£t + * +__»¡riù + +__wr™efds +, + +120 +fd_£t + * +__»¡riù + +__exû±fds +, + +121 cÚ¡  +time¥ec + * +__»¡riù + +__timeout +, + +122 cÚ¡ +__sig£t_t + * +__»¡riù + +__sigmask +); + +127 #ià +__USE_FORTIFY_LEVEL + > 0 && +defšed + +__GNUC__ + + +128  + ~ + +131 + g__END_DECLS + + + @/usr/include/sys/sysmacros.h + +19 #iâdeà +_SYS_SYSMACROS_H + + +20  + #_SYS_SYSMACROS_H + 1 + + ) + +22  + ~<ã©u»s.h +> + +24 +__BEGIN_DECLS + + +26 +__ex‹nsiÚ__ + + +27  + $gnu_dev_majÜ + ( +__dev +) + +28 +__THROW + +__©Œibu‹_cÚ¡__ +; + +29 +__ex‹nsiÚ__ + + +30  + $gnu_dev_mšÜ + ( +__dev +) + +31 +__THROW + +__©Œibu‹_cÚ¡__ +; + +32 +__ex‹nsiÚ__ + + +33  + $gnu_dev_makedev + ( +__majÜ +, + +34  +__mšÜ +) + +35 +__THROW + +__©Œibu‹_cÚ¡__ +; + +37 #ifdeà +__USE_EXTERN_INLINES + + +38 +__ex‹nsiÚ__ + +__ex‹º_šlše + +__©Œibu‹_cÚ¡__ +  + +39 + `__NTH + ( + $gnu_dev_majÜ + ( +__dev +)) + +41  (( +__dev + >> 8) & 0xfff) | (() (__dev >> 32) & ~0xfff); + +42 + } +} + +44 +__ex‹nsiÚ__ + +__ex‹º_šlše + +__©Œibu‹_cÚ¡__ +  + +45 +__NTH + ( + $gnu_dev_mšÜ + ( +__dev +)) + +47  ( +__dev + & 0xff) | (() (__dev >> 12) & ~0xff); + +48 + } +} + +50 +__ex‹nsiÚ__ + +__ex‹º_šlše + +__©Œibu‹_cÚ¡__ +  + +51 +__NTH + ( + $gnu_dev_makedev + ( +__majÜ +,  +__mšÜ +)) + +53  (( +__mšÜ + & 0xffè| (( +__majÜ + & 0xfff) << 8) + +54 | (((è( +__mšÜ + & ~0xff)) << 12) + +55 | (((è( +__majÜ + & ~0xfff)) << 32)); + +56 + } +} + +58 + g__END_DECLS + + +61  + #majÜ +( +dev +è + `gnu_dev_majÜ + (dev) + + ) + +62  + #mšÜ +( +dev +è + `gnu_dev_mšÜ + (dev) + + ) + +63  + #makedev +( +maj +, +mš +è + `gnu_dev_makedev + (maj, mš) + + ) + + @/usr/include/time.h + +22 #iâdef +_TIME_H + + +24 #ià(! +defšed + +__Ãed_time_t + && !defšed +__Ãed_þock_t + && \ + +25 ! +defšed + + g__Ãed_time¥ec +) + +26  + #_TIME_H + 1 + + ) + +27  + ~<ã©u»s.h +> + +29 + g__BEGIN_DECLS + + +33 #ifdef +_TIME_H + + +35  + #__Ãed_size_t + + + ) + +36  + #__Ãed_NULL + + + ) + +37  + ~<¡ddef.h +> + +41  + ~ + +44 #ià! +defšed + +__STRICT_ANSI__ + && !defšed +__USE_XOPEN2K + + +45 #iâdeà +CLK_TCK + + +46  + #CLK_TCK + +CLOCKS_PER_SEC + + + ) + +52 #ià! +defšed + +__þock_t_defšed + && (defšed +_TIME_H + || defšed +__Ãed_þock_t +) + +53  + #__þock_t_defšed + 1 + + ) + +55  + ~ + +57 +__BEGIN_NAMESPACE_STD + + +59  +__þock_t + + tþock_t +; + +60 + g__END_NAMESPACE_STD + + +61 #ià +defšed + +__USE_XOPEN + || defšed +__USE_POSIX + + +62 + $__USING_NAMESPACE_STD +( +þock_t +) + +66 #undeà +__Ãed_þock_t + + +68 #ià! +defšed + +__time_t_defšed + && (defšed +_TIME_H + || defšed +__Ãed_time_t +) + +69  + #__time_t_defšed + 1 + + ) + +71  + ~ + +73 +__BEGIN_NAMESPACE_STD + + +75  +__time_t + + ttime_t +; + +76 +__END_NAMESPACE_STD + + +77 #ifdeà +__USE_POSIX + + +78 + $__USING_NAMESPACE_STD +( +time_t +) + +82 #undeà +__Ãed_time_t + + +84 #ià! +defšed + +__þockid_t_defšed + && \ + +85 (( +defšed + +_TIME_H + && defšed +__USE_POSIX199309 +è|| defšed +__Ãed_þockid_t +) + +86  + #__þockid_t_defšed + 1 + + ) + +88  + ~ + +91  +__þockid_t + + tþockid_t +; + +94 #undeà +__þockid_time_t + + +96 #ià! +defšed + +__tim”_t_defšed + && \ + +97 (( +defšed + +_TIME_H + && defšed +__USE_POSIX199309 +è|| defšed +__Ãed_tim”_t +) + +98  + #__tim”_t_defšed + 1 + + ) + +100  + ~ + +103  +__tim”_t + + ttim”_t +; + +106 #undeà +__Ãed_tim”_t + + +109 #ià(! +defšed + +__time¥ec_defšed + \ + +110 && (( +defšed + +_TIME_H + \ + +111 && ( +defšed + +__USE_POSIX199309 + \ + +112 || +defšed + +__USE_ISOC11 +)) \ + +113 || +defšed + +__Ãed_time¥ec +)) + +114  + #__time¥ec_defšed + 1 + + ) + +116  + ~ + +120  + stime¥ec + + +122 +__time_t + +tv_£c +; + +123 +__sysÿÎ_¦Úg_t + +tv_n£c +; + +127 #undeà +__Ãed_time¥ec + + +130 #ifdef +_TIME_H + + +131 +__BEGIN_NAMESPACE_STD + + +133  + stm + + +135  +tm_£c +; + +136  +tm_mš +; + +137  +tm_hour +; + +138  +tm_mday +; + +139  +tm_mÚ +; + +140  +tm_y—r +; + +141  +tm_wday +; + +142  +tm_yday +; + +143  +tm_isd¡ +; + +145 #ifdef +__USE_MISC + + +146  +tm_gmtoff +; + +147 cÚ¡ * +tm_zÚe +; + +149  +__tm_gmtoff +; + +150 cÚ¡ * +__tm_zÚe +; + +153 +__END_NAMESPACE_STD + + +154 #ià +defšed + +__USE_XOPEN + || defšed +__USE_POSIX + + +155 + $__USING_NAMESPACE_STD +( +tm +) + +159 #ifdeà +__USE_POSIX199309 + + +161  + s™im”¥ec + + +163  +time¥ec + +™_š‹rv® +; + +164  +time¥ec + +™_v®ue +; + +168  +sigev’t +; + +172 #ifdeà +__USE_XOPEN2K + + +173 #iâdeà +__pid_t_defšed + + +174  +__pid_t + + tpid_t +; + +175  + #__pid_t_defšed + + + ) + +180 #ifdeà +__USE_ISOC11 + + +182  + #TIME_UTC + 1 + + ) + +186 +__BEGIN_NAMESPACE_STD + + +189 +þock_t + + $þock + (è +__THROW +; + +192 +time_t + + $time + ( +time_t + * +__tim” +è +__THROW +; + +195  + $difáime + ( +time_t + +__time1 +,ime_ˆ +__time0 +) + +196 +__THROW + + `__©Œibu‹__ + (( +__cÚ¡__ +)); + +199 +time_t + + $mktime + ( +tm + * +__ +è +__THROW +; + +205 +size_t + + $¡ráime + (* +__»¡riù + +__s +, +size_t + +__maxsize +, + +206 cÚ¡ * +__»¡riù + +__fÜm© +, + +207 cÚ¡  +tm + * +__»¡riù + +__ +è +__THROW +; + +208 +__END_NAMESPACE_STD + + +210 #ifdeà +__USE_XOPEN + + +213 * + $¡½time + (cÚ¡ * +__»¡riù + +__s +, + +214 cÚ¡ * +__»¡riù + +__fmt +,  +tm + * +__ +) + +215 +__THROW +; + +218 #ifdeà +__USE_XOPEN2K8 + + +221  + ~ + +223 +size_t + + $¡ráime_l + (* +__»¡riù + +__s +, +size_t + +__maxsize +, + +224 cÚ¡ * +__»¡riù + +__fÜm© +, + +225 cÚ¡  +tm + * +__»¡riù + +__ +, + +226 +__loÿË_t + +__loc +è +__THROW +; + +229 #ifdeà +__USE_GNU + + +230 * + $¡½time_l + (cÚ¡ * +__»¡riù + +__s +, + +231 cÚ¡ * +__»¡riù + +__fmt +,  +tm + * +__ +, + +232 +__loÿË_t + +__loc +è +__THROW +; + +236 +__BEGIN_NAMESPACE_STD + + +239  +tm + * + $gmtime + (cÚ¡ +time_t + * +__tim” +è +__THROW +; + +243  +tm + * + $loÿÉime + (cÚ¡ +time_t + * +__tim” +è +__THROW +; + +244 +__END_NAMESPACE_STD + + +246 #ifdeà +__USE_POSIX + + +249  +tm + * + $gmtime_r + (cÚ¡ +time_t + * +__»¡riù + +__tim” +, + +250  +tm + * +__»¡riù + +__ +è +__THROW +; + +254  +tm + * + $loÿÉime_r + (cÚ¡ +time_t + * +__»¡riù + +__tim” +, + +255  +tm + * +__»¡riù + +__ +è +__THROW +; + +258 +__BEGIN_NAMESPACE_STD + + +261 * + $asùime + (cÚ¡  +tm + * +__ +è +__THROW +; + +264 * + $ùime + (cÚ¡ +time_t + * +__tim” +è +__THROW +; + +265 +__END_NAMESPACE_STD + + +267 #ifdeà +__USE_POSIX + + +272 * + $asùime_r + (cÚ¡  +tm + * +__»¡riù + +__ +, + +273 * +__»¡riù + +__buf +è +__THROW +; + +276 * + $ùime_r + (cÚ¡ +time_t + * +__»¡riù + +__tim” +, + +277 * +__»¡riù + +__buf +è +__THROW +; + +282 * +__tzÇme +[2]; + +283  +__daylight +; + +284  +__timezÚe +; + +287 #ifdef +__USE_POSIX + + +289 * +tzÇme +[2]; + +293  + $tz£t + (è +__THROW +; + +296 #ià +defšed + +__USE_MISC + || defšed +__USE_XOPEN + + +297  +daylight +; + +298  +timezÚe +; + +301 #ifdeà +__USE_MISC + + +304  + $¡ime + (cÚ¡ +time_t + * +__wh’ +è +__THROW +; + +310  + #__i¦—p +( +y—r +) \ + +311 (( +y—r +è% 4 =ð0 && ((y—rè% 100 !ð0 || (y—rè% 400 =ð0)) + + ) + +314 #ifdeà +__USE_MISC + + +319 +time_t + + $timegm + ( +tm + * +__ +è +__THROW +; + +322 +time_t + + $tim–oÿl + ( +tm + * +__ +è +__THROW +; + +325  + $dysize + ( +__y—r +è +__THROW + + `__©Œibu‹__ + (( +__cÚ¡__ +)); + +329 #ifdeà +__USE_POSIX199309 + + +334  + `Çno¦“p + (cÚ¡  +time¥ec + * +__»que¡ed_time +, + +335  +time¥ec + * +__»maššg +); + +339  + $þock_g‘»s + ( +þockid_t + +__þock_id +,  +time¥ec + * +__»s +è +__THROW +; + +342  + $þock_g‘time + ( +þockid_t + +__þock_id +,  +time¥ec + * +__ +è +__THROW +; + +345  + $þock_£‰ime + ( +þockid_t + +__þock_id +, cÚ¡  +time¥ec + * +__ +) + +346 +__THROW +; + +348 #ifdeà +__USE_XOPEN2K + + +353  + `þock_Çno¦“p + ( +þockid_t + +__þock_id +,  +__æags +, + +354 cÚ¡  +time¥ec + * +__»q +, + +355  +time¥ec + * +__»m +); + +358  + $þock_g‘ýuþockid + ( +pid_t + +__pid +, +þockid_t + * +__þock_id +è +__THROW +; + +363  + $tim”_ü—‹ + ( +þockid_t + +__þock_id +, + +364  +sigev’t + * +__»¡riù + +__evp +, + +365 +tim”_t + * +__»¡riù + +__tim”id +è +__THROW +; + +368  + $tim”_d–‘e + ( +tim”_t + +__tim”id +è +__THROW +; + +371  + $tim”_£‰ime + ( +tim”_t + +__tim”id +,  +__æags +, + +372 cÚ¡  +™im”¥ec + * +__»¡riù + +__v®ue +, + +373  +™im”¥ec + * +__»¡riù + +__ov®ue +è +__THROW +; + +376  + $tim”_g‘time + ( +tim”_t + +__tim”id +,  +™im”¥ec + * +__v®ue +) + +377 +__THROW +; + +380  + $tim”_g‘ov”run + ( +tim”_t + +__tim”id +è +__THROW +; + +384 #ifdeà +__USE_ISOC11 + + +386  + $time¥ec_g‘ + ( +time¥ec + * +__ts +,  +__ba£ +) + +387 +__THROW + + `__nÚnuÎ + ((1)); + +391 #ifdeà +__USE_XOPEN_EXTENDED + + +403  +g‘d©e_”r +; + +412  +tm + * + `g‘d©e + (cÚ¡ * +__¡ršg +); + +415 #ifdeà +__USE_GNU + + +426  + `g‘d©e_r + (cÚ¡ * +__»¡riù + +__¡ršg +, + +427  +tm + * +__»¡riù + +__»sbuå +); + +430 +__END_DECLS + + + @/usr/include/bits/byteswap-16.h + +19 #iâdeà +_BITS_BYTESWAP_H + + +23 #ifdeà +__GNUC__ + + +24 #ià +__GNUC__ + >= 2 + +25  + #__bsw­_16 +( +x +) \ + +26 ( +__ex‹nsiÚ__ + \ + +27 ({  +__v +, +__x + = (è( +x +); \ + +28 ià( + `__bužtš_cÚ¡ªt_p + ( +__x +)) \ + +29 +__v + = + `__bsw­_cÚ¡ªt_16 + ( +__x +); \ + +31 + `__asm__ + ("rorw $8, %w0" \ + +32 : "ô" ( +__v +) \ + +33 : "0" ( +__x +) \ + +35 +__v +; })) + + ) + +38  + #__bsw­_16 +( +x +) \ + +39 ( +__ex‹nsiÚ__ + \ + +40 ({  +__x + = (è( +x +); \ + +41 + `__bsw­_cÚ¡ªt_16 + ( +__x +); })) + + ) + +44  +__šlše +  + +45 + $__bsw­_16 + ( +__bsx +) + +47  + `__bsw­_cÚ¡ªt_16 + ( +__bsx +); + +48 + } +} + + @/usr/include/bits/select.h + +18 #iâdeà +_SYS_SELECT_H + + +22  + ~ + +25 #ià +defšed + +__GNUC__ + && __GNUC__ >= 2 + +27 #ià +__WORDSIZE + == 64 + +28  + #__FD_ZERO_STOS + "¡osq" + + ) + +30  + #__FD_ZERO_STOS + "¡o¦" + + ) + +33  + #__FD_ZERO +( +fd¥ +) \ + +35  +__d0 +, +__d1 +; \ + +36 +__asm__ + + `__vÞ©že__ + ("þd;„•; " +__FD_ZERO_STOS + \ + +37 : "=c" ( +__d0 +), "=D" ( +__d1 +) \ + +38 : "a" (0), "0" ( ( +fd_£t +) \ + +39 /  ( +__fd_mask +)), \ + +40 "1" (& + `__FDS_BITS + ( +fd¥ +)[0]) \ + +42 } 0) + + ) + +48  + #__FD_ZERO +( +£t +) \ + +50  +__i +; \ + +51 +fd_£t + * +__¬r + = ( +£t +); \ + +52  +__i + = 0; __˜<  ( +fd_£t +è/  ( +__fd_mask +); ++__i) \ + +53 + `__FDS_BITS + ( +__¬r +)[ +__i +] = 0; \ + +54 } 0) + + ) + +58  + #__FD_SET +( +d +, +£t +) \ + +59 ((è( + `__FDS_BITS + ( +£t +)[ + `__FD_ELT + ( +d +)] |ð + `__FD_MASK + (d))) + + ) + +60  + #__FD_CLR +( +d +, +£t +) \ + +61 ((è( + `__FDS_BITS + ( +£t +)[ + `__FD_ELT + ( +d +)] &ð~ + `__FD_MASK + (d))) + + ) + +62  + #__FD_ISSET +( +d +, +£t +) \ + +63 (( + `__FDS_BITS + ( +£t +)[ + `__FD_ELT + ( +d +)] & + `__FD_MASK + (d)è!ð0) + + ) + + @/usr/include/bits/select2.h + +19 #iâdeà +_SYS_SELECT_H + + +24  +__fd–t_chk + ( +__d +); + +25  + $__fd–t_w¬n + ( +__d +) + +26 + `__w¬Ç‰r + ("bit outside of fd_set selected"); + +27 #undeà +__FD_ELT + + +28  + #__FD_ELT +( +d +) \ + +29 +__ex‹nsiÚ__ + \ + +30 ({  +__d + = ( +d +); \ + +31 ( + `__bužtš_cÚ¡ªt_p + ( +__d +) \ + +32 ? (0 <ð +__d + && __d < +__FD_SETSIZE + \ + +33 ? ( +__d + / +__NFDBITS +) \ + +34 : + `__fd–t_w¬n + ( +__d +)) \ + +35 : + `__fd–t_chk + ( +__d +)); + } +}) + + ) + + @/usr/include/bits/sigset.h + +19 #iâdef +_SIGSET_H_ty³s + + +20  + #_SIGSET_H_ty³s + 1 + + ) + +22  + t__sig_©omic_t +; + +26  + #_SIGSET_NWORDS + (1024 / (8 *  ())) + + ) + +29  + m__v® +[ +_SIGSET_NWORDS +]; + +30 } + t__sig£t_t +; + +41 #ià! +defšed + +_SIGSET_H_âs + && defšed +_SIGNAL_H + + +42  + #_SIGSET_H_âs + 1 + + ) + +44 #iâdeà +_EXTERN_INLINE + + +45  + #_EXTERN_INLINE + +__ex‹º_šlše + + + ) + +49  + #__sigmask +( +sig +) \ + +50 (((è1è<< ((( +sig +è- 1è% (8 *  ()))) + + ) + +53  + #__sigwÜd +( +sig +è(((sigè- 1è/ (8 *  ())) + + ) + +55 #ià +defšed + +__GNUC__ + && __GNUC__ >= 2 + +56  + #__sigem±y£t +( +£t +) \ + +57 ( + `__ex‹nsiÚ__ + ({  +__út + = +_SIGSET_NWORDS +; \ + +58 +sig£t_t + * +__£t + = ( +£t +); \ + +59 -- +__út + >ð0è +__£t +-> +__v® +[__cnt] = 0; \ + +60 0; })) + + ) + +61  + #__sigfžl£t +( +£t +) \ + +62 ( + `__ex‹nsiÚ__ + ({  +__út + = +_SIGSET_NWORDS +; \ + +63 +sig£t_t + * +__£t + = ( +£t +); \ + +64 -- +__út + >ð0è +__£t +-> +__v® +[__cnt] = ~0UL; \ + +65 0; })) + + ) + +67 #ifdeà +__USE_GNU + + +71  + #__sigi£m±y£t +( +£t +) \ + +72 ( + `__ex‹nsiÚ__ + ({  +__út + = +_SIGSET_NWORDS +; \ + +73 cÚ¡ +sig£t_t + * +__£t + = ( +£t +); \ + +74  +__»t + = +__£t +-> +__v® +[-- +__út +]; \ + +75 ! +__»t + && -- +__út + >= 0) \ + +76 +__»t + = +__£t +-> +__v® +[ +__út +]; \ + +77 +__»t + =ð0; })) + + ) + +78  + #__sigªd£t +( +de¡ +, +Ëá +, +right +) \ + +79 ( + `__ex‹nsiÚ__ + ({  +__út + = +_SIGSET_NWORDS +; \ + +80 +sig£t_t + * +__de¡ + = ( +de¡ +); \ + +81 cÚ¡ +sig£t_t + * +__Ëá + = ( +Ëá +); \ + +82 cÚ¡ +sig£t_t + * +__right + = ( +right +); \ + +83 -- +__út + >= 0) \ + +84 +__de¡ +-> +__v® +[ +__út +] = ( +__Ëá +->__val[__cnt] \ + +85 & +__right +-> +__v® +[ +__út +]); \ + +86 0; })) + + ) + +87  + #__sigÜ£t +( +de¡ +, +Ëá +, +right +) \ + +88 ( + `__ex‹nsiÚ__ + ({  +__út + = +_SIGSET_NWORDS +; \ + +89 +sig£t_t + * +__de¡ + = ( +de¡ +); \ + +90 cÚ¡ +sig£t_t + * +__Ëá + = ( +Ëá +); \ + +91 cÚ¡ +sig£t_t + * +__right + = ( +right +); \ + +92 -- +__út + >= 0) \ + +93 +__de¡ +-> +__v® +[ +__út +] = ( +__Ëá +->__val[__cnt] \ + +94 | +__right +-> +__v® +[ +__út +]); \ + +95 0; })) + + ) + +102  +__sigismemb” + (cÚ¡ +__sig£t_t + *, ); + +103  +__sigadd£t + ( +__sig£t_t + *, ); + +104  +__sigd–£t + ( +__sig£t_t + *, ); + +106 #ifdeà +__USE_EXTERN_INLINES + + +107  + #__SIGSETFN +( +NAME +, +BODY +, +CONST +) \ + +108 +_EXTERN_INLINE + \ + +109 + `NAME + ( +CONST + +__sig£t_t + * +__£t +,  +__sig +) \ + +111  +__mask + = + `__sigmask + ( +__sig +); \ + +112  +__wÜd + = + `__sigwÜd + ( +__sig +); \ + +113  +BODY +; \ + +114 } + + ) + +116 +__SIGSETFN + ( +__sigismemb” +, ( +__£t +-> +__v® +[ +__wÜd +] & +__mask +) ? 1 : 0, const) + +117 +__SIGSETFN + ( +__sigadd£t +, (( +__£t +-> +__v® +[ +__wÜd +] |ð +__mask +), 0), ) + +118 +__SIGSETFN + ( +__sigd–£t +, (( +__£t +-> +__v® +[ +__wÜd +] &ð~ +__mask +), 0), ) + +120 #undeà +__SIGSETFN + + + @/usr/include/bits/time.h + +23 #ià +defšed + +__Ãed_timev® + || defšed +__USE_GNU + + +24 #iâdeà +_STRUCT_TIMEVAL + + +25  + #_STRUCT_TIMEVAL + 1 + + ) + +26  + ~ + +30  + stimev® + + +32 +__time_t + + mtv_£c +; + +33 +__su£cÚds_t + + mtv_u£c +; + +38 #iâdeà +__Ãed_timev® + + +39 #iâdeà +_BITS_TIME_H + + +40  + #_BITS_TIME_H + 1 + + ) + +48  + #CLOCKS_PER_SEC + (( +þock_t +è1000000) + + ) + +50 #ià(! +defšed + +__STRICT_ANSI__ + || defšed +__USE_POSIX +) \ + +51 && ! +defšed + + g__USE_XOPEN2K + + +54  + ~ + +55  +__syscÚf + (); + +56  + #CLK_TCK + (( +__þock_t +è + `__syscÚf + (2)è + + ) + +59 #ifdeà +__USE_POSIX199309 + + +61  + #CLOCK_REALTIME + 0 + + ) + +63  + #CLOCK_MONOTONIC + 1 + + ) + +65  + #CLOCK_PROCESS_CPUTIME_ID + 2 + + ) + +67  + #CLOCK_THREAD_CPUTIME_ID + 3 + + ) + +69  + #CLOCK_MONOTONIC_RAW + 4 + + ) + +71  + #CLOCK_REALTIME_COARSE + 5 + + ) + +73  + #CLOCK_MONOTONIC_COARSE + 6 + + ) + +75  + #CLOCK_BOOTTIME + 7 + + ) + +77  + #CLOCK_REALTIME_ALARM + 8 + + ) + +79  + #CLOCK_BOOTTIME_ALARM + 9 + + ) + +81  + #CLOCK_TAI + 11 + + ) + +84  + #TIMER_ABSTIME + 1 + + ) + +87 #ifdeà +__USE_GNU + + +88  + ~ + +90 +__BEGIN_DECLS + + +93  + $þock_adjtime + ( +__þockid_t + +__þock_id +,  +timex + * +__utx +è +__THROW +; + +95 +__END_DECLS + + +101 #undeà +__Ãed_timev® + + + @/usr/include/gnu/stubs-32.h + +6 #ifdeà +_LIBC + + +7 #”rÜ +AµliÿtiÚs + +may + +nÙ + +defše + +the + +maüo + +_LIBC + + +10  + #__¡ub_chæags + + + ) + +11  + #__¡ub_ç‰ach + + + ) + +12  + #__¡ub_fchæags + + + ) + +13  + #__¡ub_fd‘ach + + + ) + +14  + #__¡ub_g‰y + + + ) + +15  + #__¡ub_lchmod + + + ) + +16  + #__¡ub_»voke + + + ) + +17  + #__¡ub_£Žogš + + + ) + +18  + #__¡ub_sig»tuº + + + ) + +19  + #__¡ub_s¡k + + + ) + +20  + #__¡ub_¡ty + + + ) + + @/usr/include/gnu/stubs-64.h + +6 #ifdeà +_LIBC + + +7 #”rÜ +AµliÿtiÚs + +may + +nÙ + +defše + +the + +maüo + +_LIBC + + +10  + #__¡ub___com·t_bdæush + + + ) + +11  + #__¡ub_chæags + + + ) + +12  + #__¡ub_ç‰ach + + + ) + +13  + #__¡ub_fchæags + + + ) + +14  + #__¡ub_fd‘ach + + + ) + +15  + #__¡ub_g‘msg + + + ) + +16  + #__¡ub_g‰y + + + ) + +17  + #__¡ub_lchmod + + + ) + +18  + #__¡ub_putmsg + + + ) + +19  + #__¡ub_»voke + + + ) + +20  + #__¡ub_£Žogš + + + ) + +21  + #__¡ub_sig»tuº + + + ) + +22  + #__¡ub_s¡k + + + ) + +23  + #__¡ub_¡ty + + + ) + + @/usr/include/gnu/stubs-x32.h + +6 #ifdeà +_LIBC + + +7 #”rÜ +AµliÿtiÚs + +may + +nÙ + +defše + +the + +maüo + +_LIBC + + +10  + #__¡ub___com·t_bdæush + + + ) + +11  + #__¡ub___com·t_ü—‹_moduË + + + ) + +12  + #__¡ub___com·t_g‘_k”Ãl_syms + + + ) + +13  + #__¡ub___com·t_qu”y_moduË + + + ) + +14  + #__¡ub___com·t_u£lib + + + ) + +15  + #__¡ub_chæags + + + ) + +16  + #__¡ub_ç‰ach + + + ) + +17  + #__¡ub_fchæags + + + ) + +18  + #__¡ub_fd‘ach + + + ) + +19  + #__¡ub_g‘msg + + + ) + +20  + #__¡ub_g‰y + + + ) + +21  + #__¡ub_lchmod + + + ) + +22  + #__¡ub_nfs£rvùl + + + ) + +23  + #__¡ub_putmsg + + + ) + +24  + #__¡ub_»voke + + + ) + +25  + #__¡ub_£Žogš + + + ) + +26  + #__¡ub_sig»tuº + + + ) + +27  + #__¡ub_s¡k + + + ) + +28  + #__¡ub_¡ty + + + ) + + @/usr/include/bits/timex.h + +18 #iâdef +_BITS_TIMEX_H + + +19  + #_BITS_TIMEX_H + 1 + + ) + +21  + ~ + +25  + stimex + + +27  + mmodes +; + +28 +__sysÿÎ_¦Úg_t + + moff£t +; + +29 +__sysÿÎ_¦Úg_t + + mäeq +; + +30 +__sysÿÎ_¦Úg_t + + mmax”rÜ +; + +31 +__sysÿÎ_¦Úg_t + + me¡”rÜ +; + +32  + m¡©us +; + +33 +__sysÿÎ_¦Úg_t + + mcÚ¡ªt +; + +34 +__sysÿÎ_¦Úg_t + + m´ecisiÚ +; + +35 +__sysÿÎ_¦Úg_t + + mtÞ”ªû +; + +36  +timev® + + mtime +; + +37 +__sysÿÎ_¦Úg_t + + mtick +; + +38 +__sysÿÎ_¦Úg_t + + mµsäeq +; + +39 +__sysÿÎ_¦Úg_t + + mj™‹r +; + +40  + mshiá +; + +41 +__sysÿÎ_¦Úg_t + + m¡abž +; + +42 +__sysÿÎ_¦Úg_t + + mj™út +; + +43 +__sysÿÎ_¦Úg_t + + mÿlút +; + +44 +__sysÿÎ_¦Úg_t + + m”rút +; + +45 +__sysÿÎ_¦Úg_t + + m¡bút +; + +47  + mi +; + +56  + #ADJ_OFFSET + 0x0001 + + ) + +57  + #ADJ_FREQUENCY + 0x0002 + + ) + +58  + #ADJ_MAXERROR + 0x0004 + + ) + +59  + #ADJ_ESTERROR + 0x0008 + + ) + +60  + #ADJ_STATUS + 0x0010 + + ) + +61  + #ADJ_TIMECONST + 0x0020 + + ) + +62  + #ADJ_TAI + 0x0080 + + ) + +63  + #ADJ_SETOFFSET + 0x0100 + + ) + +64  + #ADJ_MICRO + 0x1000 + + ) + +65  + #ADJ_NANO + 0x2000 + + ) + +66  + #ADJ_TICK + 0x4000 + + ) + +67  + #ADJ_OFFSET_SINGLESHOT + 0x8001 + + ) + +68  + #ADJ_OFFSET_SS_READ + 0xa001 + + ) + +71  + #MOD_OFFSET + +ADJ_OFFSET + + + ) + +72  + #MOD_FREQUENCY + +ADJ_FREQUENCY + + + ) + +73  + #MOD_MAXERROR + +ADJ_MAXERROR + + + ) + +74  + #MOD_ESTERROR + +ADJ_ESTERROR + + + ) + +75  + #MOD_STATUS + +ADJ_STATUS + + + ) + +76  + #MOD_TIMECONST + +ADJ_TIMECONST + + + ) + +77  + #MOD_CLKB + +ADJ_TICK + + + ) + +78  + #MOD_CLKA + +ADJ_OFFSET_SINGLESHOT + + + ) + +79  + #MOD_TAI + +ADJ_TAI + + + ) + +80  + #MOD_MICRO + +ADJ_MICRO + + + ) + +81  + #MOD_NANO + +ADJ_NANO + + + ) + +85  + #STA_PLL + 0x0001 + + ) + +86  + #STA_PPSFREQ + 0x0002 + + ) + +87  + #STA_PPSTIME + 0x0004 + + ) + +88  + #STA_FLL + 0x0008 + + ) + +90  + #STA_INS + 0x0010 + + ) + +91  + #STA_DEL + 0x0020 + + ) + +92  + #STA_UNSYNC + 0x0040 + + ) + +93  + #STA_FREQHOLD + 0x0080 + + ) + +95  + #STA_PPSSIGNAL + 0x0100 + + ) + +96  + #STA_PPSJITTER + 0x0200 + + ) + +97  + #STA_PPSWANDER + 0x0400 + + ) + +98  + #STA_PPSERROR + 0x0800 + + ) + +100  + #STA_CLOCKERR + 0x1000 + + ) + +101  + #STA_NANO + 0x2000 + + ) + +102  + #STA_MODE + 0x4000 + + ) + +103  + #STA_CLK + 0x8000 + + ) + +106  + #STA_RONLY + ( +STA_PPSSIGNAL + | +STA_PPSJITTER + | +STA_PPSWANDER + | \ + +107 +STA_PPSERROR + | +STA_CLOCKERR + | +STA_NANO + | +STA_MODE + | +STA_CLK +) + + ) + + @ +1 +. +1 +/usr/include +99 +1835 +ALDRAM.cpp +ALDRAM.h +Cache.cpp +Cache.h +Config.cpp +Config.h +Controller.cpp +Controller.h +DDR3.cpp +DDR3.h +DDR4.cpp +DDR4.h +DRAM.h +DSARP.cpp +DSARP.h +GDDR5.cpp +GDDR5.h +Gem5Wrapper.cpp +Gem5Wrapper.h +HBM.cpp +HBM.h +LPDDR3.cpp +LPDDR3.h +LPDDR4.cpp +LPDDR4.h +Main.cpp +MemWrapper.cpp +MemWrapper.h +Memory.h +MemoryFactory.cpp +MemoryFactory.h +Processor.cpp +Processor.h +Refresh.cpp +Refresh.h +Request.h +SALP.cpp +SALP.h +Scheduler.h +SpeedyController.h +StatType.cpp +StatType.h +Statistics.h +TLDRAM.cpp +TLDRAM.h +WideIO.cpp +WideIO.h +WideIO2.cpp +WideIO2.h +common.cpp +common.h +pe.cpp +pe.h +/usr/include/ctype.h +/usr/include/math.h +/usr/include/stdlib.h +/usr/include/alloca.h +/usr/include/bits/huge_val.h +/usr/include/bits/huge_valf.h +/usr/include/bits/huge_vall.h +/usr/include/bits/inf.h +/usr/include/bits/math-finite.h +/usr/include/bits/math-vector.h +/usr/include/bits/mathcalls.h +/usr/include/bits/mathdef.h +/usr/include/bits/mathinline.h +/usr/include/bits/nan.h +/usr/include/bits/stdlib-bsearch.h +/usr/include/bits/stdlib-float.h +/usr/include/bits/stdlib-ldbl.h +/usr/include/bits/stdlib.h +/usr/include/bits/types.h +/usr/include/bits/waitflags.h +/usr/include/bits/waitstatus.h +/usr/include/endian.h +/usr/include/features.h +/usr/include/sys/types.h +/usr/include/xlocale.h +/usr/include/bits/byteswap.h +/usr/include/bits/endian.h +/usr/include/bits/libm-simd-decl-stubs.h +/usr/include/bits/pthreadtypes.h +/usr/include/bits/typesizes.h +/usr/include/bits/wordsize.h +/usr/include/gnu/stubs.h +/usr/include/stdc-predef.h +/usr/include/sys/cdefs.h +/usr/include/sys/select.h +/usr/include/sys/sysmacros.h +/usr/include/time.h +/usr/include/bits/byteswap-16.h +/usr/include/bits/select.h +/usr/include/bits/select2.h +/usr/include/bits/sigset.h +/usr/include/bits/time.h +/usr/include/gnu/stubs-32.h +/usr/include/gnu/stubs-64.h +/usr/include/gnu/stubs-x32.h +/usr/include/bits/timex.h diff --git a/src/pe.cpp b/src/pe.cpp new file mode 100644 index 0000000..9898b94 --- /dev/null +++ b/src/pe.cpp @@ -0,0 +1,315 @@ +#include "pe.h" + +void pe::init(){ + + allVaReqGenerated = false; + allVbReqGenerated = false; + allVpReqGenerated = false; + allVaRespReceived = false; + allVbRespReceived = false; + allVpRespReceived = false; + + computingDone = false; + + // The capacity of the three buffer is set to be 1024-word. + va.resize(GL::vaBufferDepth); + vb.resize(GL::vbBufferDepth); + vp.resize(GL::vpBufferDepth); + + dataWidth = 4; // 4 bytes +} + +// In order to process the memory request, +// the address sent to the memory must be aligned to burstlen. +pe::pe(sc_module_name _name, + int _peIdx, + int _peClkCycle + ) :sc_module(_name) +{ + peIdx = _peIdx; + peClkCycle = _peClkCycle; + init(); + + // Memory send and receive processes + SC_THREAD(sendMemReq); + SC_THREAD(getMemResp); + SC_THREAD(issueReadReq); + SC_THREAD(issueWriteReq); + SC_THREAD(vecAdd); + SC_THREAD(statusMonitor); +} + +void pe::statusMonitor(){ + while(true){ + // In hardware we may use counter instead of traversing the status container. + // With the counter, we can do it in a single cycle. Thus we have the + // traverse done in a single cycle to simulate the functionality here. + if(allVaReqGenerated){ + allVaRespReceived = true; + for(auto it = vaBurstReqStatus.begin(); it != vaBurstReqStatus.end(); it++){ + if (it->second == false){ + allVaRespReceived = false; + break; + } + } + } + + if(allVbReqGenerated){ + allVbRespReceived = true; + for(auto it = vbBurstReqStatus.begin(); it != vbBurstReqStatus.end(); it++){ + if(it->second == false){ + allVbRespReceived = false; + break; + } + } + } + + if(allVpReqGenerated){ + allVpRespReceived = true; + for(auto it = vpBurstReqStatus.begin(); it != vpBurstReqStatus.end(); it++){ + if(it->second == false){ + allVpRespReceived = false; + } + } + } + + if(allVaRespReceived && allVbRespReceived && allVpRespReceived){ + std::cout << "Simulation ends at " << sc_time_stamp() << std::endl; + std::cout << "The resulting vp : " << std::endl; + for(int i = 0; i < 20; i++){ + std::cout << vp[i] << " "; + } + std::cout << std::endl; + sc_stop(); + } + + wait(peClkCycle, SC_NS); + } +} + +// Dot production when both two input vectors are loaded from memory. +// It may either run with a streaming mode or pre-fetching mode. +void pe::vecAdd(){ + + bool readStage = false; + bool mulStage = false; + bool writeStage = false; + + int vaAddr = 0; + int vbAddr = 0; + int vpAddr = 0; + + int rega; + int regb; + int regp; + + while(true){ + // Computing done detection + if(vpAddr == GL::vpLen){ + computingDone = true; + } + + // Writing stage + writeStage = mulStage; + if(writeStage){ + vp[vpAddr] = regp; + vpAddr++; + } + + // Multiplication stage + mulStage = readStage; + if(mulStage){ + regp = rega + regb; + } + + // Reading pipeline stage + if(allVaRespReceived && allVbRespReceived && vaAddr < GL::vaLen && vbAddr < GL::vbLen){ + rega = va[vaAddr]; + regb = vb[vbAddr]; + vaAddr++; + vbAddr++; + readStage = true; + } + else{ + readStage = false; + } + + wait(peClkCycle, SC_NS); + } +} + +// As it takes time to write data to memory, even though the write requests +// can always be accommodated. Thus we add additional delay here to simulate +// the transmission cost here. +long pe::createWriteBurstReq( + ramulator::Request::Type type, + long addr, + int length, + int localAddr, + std::vector &buffer) +{ + long burstIdx = GL::getBurstIdx(); + BurstOp op(type, burstIdx, peIdx, addr, length, localAddr); + op.updateReqVec(); + op.updateAddrVec(); + op.bufferToBurstReq(buffer, localAddr); + wait(peClkCycle * op.getReqNum() * GL::burstLen/dataWidth, SC_NS); + burstReqQueue.push_back(op); + + return burstIdx; +} + +long pe::createReadBurstReq( + ramulator::Request::Type type, + long addr, + int length, + int localAddr) +{ + long burstIdx = GL::getBurstIdx(); + BurstOp op(type, burstIdx, peIdx, addr, length, localAddr); + op.updateReqVec(); + op.updateAddrVec(); + burstReqQueue.push_back(op); + + return burstIdx; +} + + +void pe::issueWriteReq(){ + long _vpMemAddr = GL::vpMemAddr; + int vpBufferAddr = 0; + long burstIdx; + while(true){ + if(vpBufferAddr == GL::vpLen){ + allVpReqGenerated = true; + } + + if(computingDone == true && vpBufferAddr < GL::vpLen){ + ramulator::Request::Type type = ramulator::Request::Type::WRITE; + burstIdx = createWriteBurstReq(type, _vpMemAddr, 64, vpBufferAddr, vp); + _vpMemAddr += 64; + vpBufferAddr += 64/sizeof(int); + vpBurstReqStatus[burstIdx] = false; + } + else{ + wait(peClkCycle, SC_NS); + } + } +} + +// Generate 1024-byte read memory request from both addrVa and addrVb. +// This process may also be invoked on certain user defined condition. +void pe::issueReadReq(){ + // These are the initial memory address of va, vb and vp. + long _vaMemAddr = GL::vaMemAddr; + int vaBufferAddr = 0; + long _vbMemAddr = GL::vbMemAddr; + int vbBufferAddr = 0; + long burstIdx; + ramulator::Request::Type type = ramulator::Request::Type::READ; + + // Create 128 byte read requests + int len = 64; + for(int i = 0; i < GL::vaLen * (int)(sizeof(int)); i = i + len){ + burstIdx = createReadBurstReq(type, _vaMemAddr, len, vaBufferAddr); + _vaMemAddr += len; + vaBufferAddr += len/sizeof(int); + vaReqQueue.push_back(burstIdx); + vaBurstReqStatus[burstIdx] = false; + + burstIdx = createReadBurstReq(type, _vbMemAddr, len, vbBufferAddr); + _vbMemAddr += len; + vbBufferAddr += len/sizeof(int); + vbReqQueue.push_back(burstIdx); + vbBurstReqStatus[burstIdx] = false; + wait(peClkCycle, SC_NS); + } + + allVaReqGenerated = true; + allVbReqGenerated = true; + + HERE; + std::cout << "All the read burst memory operations have been generated at "; + std::cout << sc_time_stamp() << std::endl; + +} + +/*=----------------------------------------------------------- + * The MemWrapper will have an infinite request queue + * that can always accomodate all the requests from + * PEs. Then the queue will gradually send the requests to the + * ramulator which has the admission control. + *=---------------------------------------------------------*/ +void pe::sendMemReq(){ + while(true){ + if(!burstReqQueue.empty()){ + BurstOp op = burstReqQueue.front(); + long departTime = (long) (sc_time_stamp()/sc_time(1, SC_NS)); + op.setDepartPeTime(departTime); + burstReq.write(op); + burstReqQueue.pop_front(); + std::cout << "burst " << op.burstIdx << " is sent to ramulator. " << std::endl; + + // Update burst request status + } + else{ + BurstOp op(false); + burstReq.write(op); + } + + wait(peClkCycle, SC_NS); + } +} + +void pe::getMemResp(){ + while(true){ + BurstOp op = burstResp.read(); + if(op.valid){ + // update arrivePeTime stamp when a valid memory response is captured. + long arriveTime = (long)(sc_time_stamp()/sc_time(1, SC_NS)); + op.setArrivePeTime(arriveTime); + burstRespQueue.push_back(op); + + // Update resp status + if(vaBurstReqStatus.find(op.burstIdx) != vaBurstReqStatus.end()){ + vaBurstReqStatus[op.burstIdx] = true; + + // copy data back to buffer for read request + op.burstReqToBuffer(va, op.localAddr); + } + + else if(vbBurstReqStatus.find(op.burstIdx) != vbBurstReqStatus.end()){ + vbBurstReqStatus[op.burstIdx] = true; + op.burstReqToBuffer(vb, op.localAddr); + } + + else if(vpBurstReqStatus.find(op.burstIdx) != vpBurstReqStatus.end()){ + vpBurstReqStatus[op.burstIdx] = true; + + // doing nothing for write response. + } + + else { + HERE; + std::cout << "There is no such burst id in this pe." << std::endl; + exit(EXIT_FAILURE); + } + } + + wait(peClkCycle, SC_NS); + } +} + +void pe::setPeClkCycle(int _peClkCycle){ + peClkCycle = _peClkCycle; +} + +void pe::dumpResp(){ + for(auto it = burstRespQueue.begin(); it != burstRespQueue.end(); it++){ + std::cout << (*it) << std::endl; + } +} + +void pe::setDataWidth(int width){ + dataWidth = width; +} diff --git a/src/pe.h b/src/pe.h new file mode 100644 index 0000000..b77eecb --- /dev/null +++ b/src/pe.h @@ -0,0 +1,93 @@ +#ifndef __PE_H__ +#define __PE_H__ + +#include +#include +#include +#include +#include "Request.h" +#include "common.h" +#include "systemc.h" + +class pe : public sc_module{ + + SC_HAS_PROCESS(pe); + + public: + // Even though there may be multiple requests generated at the same time, + // only one of the request goes to the ramulator eventually in each cycle. + sc_out burstReq; + sc_in burstResp; + + // pe parameter + int peIdx; + + pe(sc_module_name _name, int _peIdx, int _peClkCycle); + ~pe(){}; + + // public member function + void sendMemReq(); + void getMemResp(); + void issueReadReq(); + void issueWriteReq(); + void runtimeMonitor(); + void dumpResp(); + void setPeClkCycle(int _peClkCycle); + void vecAdd(); + void statusMonitor(); + long createWriteBurstReq( + ramulator::Request::Type type, + long addr, + int length, + int localAddr, + std::vector &buffer); + + long createReadBurstReq( + ramulator::Request::Type type, + long addr, + int length, + int localAddr); + + void setDataWidth(int width); + + private: + int peClkCycle; + int dataWidth; // # of bytes can be transmitted to/from memory in each cycle + std::vector va; // Input of vector a + std::vector vb; // Input of vector b + std::vector vp; // result of the element-wise production of a and b + + bool allVaReqGenerated; + bool allVaRespReceived; + bool allVbReqGenerated; + bool allVbRespReceived; + bool allVpReqGenerated; + bool allVpRespReceived; + + bool computingDone; + bool vaReady; + bool vbReady; + bool vpReady; + + // The request queue is shared by all the different read/write ports + std::list burstReqQueue; + std::list burstRespQueue; + + // It keeps the status of the burst requests. If a burst with burstIdx is not found + // in the mapper, it doesn't exist. If it is found to be false, the request is generated + // but is not responsed yet. If it is set true, the request is responsed. + // These data structure will remain valid until the end of the object life. + std::map vaBurstReqStatus; + std::map vbBurstReqStatus; + std::map vpBurstReqStatus; + + std::list vaReqQueue; + std::list vbReqQueue; + std::list vpReqQueue; + + bool isBurstReqQueueEmpty(); + bool isMemReqQueueEmpty(); + void init(); +}; + +#endif diff --git a/src/tags b/src/tags new file mode 100644 index 0000000..cdeec94 --- /dev/null +++ b/src/tags @@ -0,0 +1,2354 @@ +!_TAG_FILE_FORMAT 2 /extended format; --format=1 will not append ;" to lines/ +!_TAG_FILE_SORTED 1 /0=unsorted, 1=sorted, 2=foldcase/ +!_TAG_PROGRAM_AUTHOR Darren Hiebert /dhiebert@users.sourceforge.net/ +!_TAG_PROGRAM_NAME Exuberant Ctags // +!_TAG_PROGRAM_URL http://ctags.sourceforge.net /official site/ +!_TAG_PROGRAM_VERSION 5.9~svn20110310 // +ACT ALDRAM.h /^ ACT, PRE, PREA,$/;" m class:ramulator::ALDRAM::Command +ACT DDR3.h /^ ACT, PRE, PREA, $/;" m class:ramulator::DDR3::Command +ACT DDR4.h /^ ACT, PRE, PREA, $/;" m class:ramulator::DDR4::Command +ACT DSARP.h /^ ACT, PRE, PREA,$/;" m class:ramulator::DSARP::Command +ACT GDDR5.h /^ ACT, PRE, PREA, $/;" m class:ramulator::GDDR5::Command +ACT HBM.h /^ ACT, PRE, PREA,$/;" m class:ramulator::HBM::Command +ACT LPDDR3.h /^ ACT, PRE, PRA, $/;" m class:ramulator::LPDDR3::Command +ACT LPDDR4.h /^ ACT, PRE, PREA, $/;" m class:ramulator::LPDDR4::Command +ACT SALP.h /^ ACT, SASEL, PRE, PRER, \/\/ precharge bank\/bank\/rank(SALP-1), subarray\/bank\/rank(SALP-2, MASA)$/;" m class:ramulator::SALP::Command +ACT TLDRAM.h /^ ACT, PRE, PREA,$/;" m class:ramulator::TLDRAM::Command +ACT WideIO.h /^ ACT, PRE, PRA, $/;" m class:ramulator::WideIO::Command +ACT WideIO2.h /^ ACT, PRE, PRA, $/;" m class:ramulator::WideIO2::Command +ACTF TLDRAM.h /^ ACTF, PREF, PREAF,$/;" m class:ramulator::TLDRAM::Command +ACTM TLDRAM.h /^ ACTM, PREM, PREAM,$/;" m class:ramulator::TLDRAM::Command +ALDRAM ALDRAM.cpp /^ALDRAM::ALDRAM(Org org, Speed speed) :$/;" f class:ALDRAM +ALDRAM ALDRAM.cpp /^ALDRAM::ALDRAM(const string& org_str, const string& speed_str) :$/;" f class:ALDRAM +ALDRAM ALDRAM.h /^class ALDRAM$/;" c namespace:ramulator +ALDRAM_1066E ALDRAM.h /^ ALDRAM_1066E, ALDRAM_1066F, ALDRAM_1066G,$/;" m class:ramulator::ALDRAM::Speed +ALDRAM_1066F ALDRAM.h /^ ALDRAM_1066E, ALDRAM_1066F, ALDRAM_1066G,$/;" m class:ramulator::ALDRAM::Speed +ALDRAM_1066G ALDRAM.h /^ ALDRAM_1066E, ALDRAM_1066F, ALDRAM_1066G,$/;" m class:ramulator::ALDRAM::Speed +ALDRAM_1333G ALDRAM.h /^ ALDRAM_1333G, ALDRAM_1333H,$/;" m class:ramulator::ALDRAM::Speed +ALDRAM_1333H ALDRAM.h /^ ALDRAM_1333G, ALDRAM_1333H,$/;" m class:ramulator::ALDRAM::Speed +ALDRAM_1600H ALDRAM.h /^ ALDRAM_1600H, ALDRAM_1600J, ALDRAM_1600K,$/;" m class:ramulator::ALDRAM::Speed +ALDRAM_1600J ALDRAM.h /^ ALDRAM_1600H, ALDRAM_1600J, ALDRAM_1600K,$/;" m class:ramulator::ALDRAM::Speed +ALDRAM_1600K ALDRAM.h /^ ALDRAM_1600H, ALDRAM_1600J, ALDRAM_1600K,$/;" m class:ramulator::ALDRAM::Speed +ALDRAM_1866K ALDRAM.h /^ ALDRAM_1866K, ALDRAM_1866L,$/;" m class:ramulator::ALDRAM::Speed +ALDRAM_1866L ALDRAM.h /^ ALDRAM_1866K, ALDRAM_1866L,$/;" m class:ramulator::ALDRAM::Speed +ALDRAM_1Gb_x16 ALDRAM.h /^ ALDRAM_1Gb_x4, ALDRAM_1Gb_x8, ALDRAM_1Gb_x16,$/;" m class:ramulator::ALDRAM::Org +ALDRAM_1Gb_x4 ALDRAM.h /^ ALDRAM_1Gb_x4, ALDRAM_1Gb_x8, ALDRAM_1Gb_x16,$/;" m class:ramulator::ALDRAM::Org +ALDRAM_1Gb_x8 ALDRAM.h /^ ALDRAM_1Gb_x4, ALDRAM_1Gb_x8, ALDRAM_1Gb_x16,$/;" m class:ramulator::ALDRAM::Org +ALDRAM_2133L ALDRAM.h /^ ALDRAM_2133L, ALDRAM_2133M,$/;" m class:ramulator::ALDRAM::Speed +ALDRAM_2133M ALDRAM.h /^ ALDRAM_2133L, ALDRAM_2133M,$/;" m class:ramulator::ALDRAM::Speed +ALDRAM_2Gb_x16 ALDRAM.h /^ ALDRAM_2Gb_x4, ALDRAM_2Gb_x8, ALDRAM_2Gb_x16,$/;" m class:ramulator::ALDRAM::Org +ALDRAM_2Gb_x4 ALDRAM.h /^ ALDRAM_2Gb_x4, ALDRAM_2Gb_x8, ALDRAM_2Gb_x16,$/;" m class:ramulator::ALDRAM::Org +ALDRAM_2Gb_x8 ALDRAM.h /^ ALDRAM_2Gb_x4, ALDRAM_2Gb_x8, ALDRAM_2Gb_x16,$/;" m class:ramulator::ALDRAM::Org +ALDRAM_4Gb_x16 ALDRAM.h /^ ALDRAM_4Gb_x4, ALDRAM_4Gb_x8, ALDRAM_4Gb_x16,$/;" m class:ramulator::ALDRAM::Org +ALDRAM_4Gb_x4 ALDRAM.h /^ ALDRAM_4Gb_x4, ALDRAM_4Gb_x8, ALDRAM_4Gb_x16,$/;" m class:ramulator::ALDRAM::Org +ALDRAM_4Gb_x8 ALDRAM.h /^ ALDRAM_4Gb_x4, ALDRAM_4Gb_x8, ALDRAM_4Gb_x16,$/;" m class:ramulator::ALDRAM::Org +ALDRAM_512Mb_x16 ALDRAM.h /^ ALDRAM_512Mb_x4, ALDRAM_512Mb_x8, ALDRAM_512Mb_x16,$/;" m class:ramulator::ALDRAM::Org +ALDRAM_512Mb_x4 ALDRAM.h /^ ALDRAM_512Mb_x4, ALDRAM_512Mb_x8, ALDRAM_512Mb_x16,$/;" m class:ramulator::ALDRAM::Org +ALDRAM_512Mb_x8 ALDRAM.h /^ ALDRAM_512Mb_x4, ALDRAM_512Mb_x8, ALDRAM_512Mb_x16,$/;" m class:ramulator::ALDRAM::Org +ALDRAM_800D ALDRAM.h /^ ALDRAM_800D, ALDRAM_800E,$/;" m class:ramulator::ALDRAM::Speed +ALDRAM_800E ALDRAM.h /^ ALDRAM_800D, ALDRAM_800E,$/;" m class:ramulator::ALDRAM::Speed +ALDRAM_8Gb_x16 ALDRAM.h /^ ALDRAM_8Gb_x4, ALDRAM_8Gb_x8, ALDRAM_8Gb_x16,$/;" m class:ramulator::ALDRAM::Org +ALDRAM_8Gb_x4 ALDRAM.h /^ ALDRAM_8Gb_x4, ALDRAM_8Gb_x8, ALDRAM_8Gb_x16,$/;" m class:ramulator::ALDRAM::Org +ALDRAM_8Gb_x8 ALDRAM.h /^ ALDRAM_8Gb_x4, ALDRAM_8Gb_x8, ALDRAM_8Gb_x16,$/;" m class:ramulator::ALDRAM::Org +ActPowerDown ALDRAM.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::ALDRAM::State +ActPowerDown DDR3.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::DDR3::State +ActPowerDown DDR4.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::DDR4::State +ActPowerDown DSARP.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::DSARP::State +ActPowerDown GDDR5.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::GDDR5::State +ActPowerDown HBM.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::HBM::State +ActPowerDown LPDDR3.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::LPDDR3::State +ActPowerDown LPDDR4.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::LPDDR4::State +ActPowerDown SALP.h /^ Opened, Closed, Selected, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::SALP::State +ActPowerDown TLDRAM.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::TLDRAM::State +ActPowerDown WideIO.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::WideIO::State +ActPowerDown WideIO2.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::WideIO2::State +Average StatType.h /^ Average():current(0), lastReset(0), total_val(0), last(0){}$/;" f class:Stats::Average +Average StatType.h /^class Average: public ScalarBase {$/;" c namespace:Stats +AverageDeviation StatType.h /^ AverageDeviation():sum(Counter()), squares(Counter()) {}$/;" f class:Stats::AverageDeviation +AverageDeviation StatType.h /^class AverageDeviation: public Stat {$/;" c namespace:Stats +AverageDeviationStat Statistics.h /^class AverageDeviationStat : public DistStatBase {$/;" c namespace:ramulator +AverageStat Statistics.h /^class AverageStat : public ScalarStatBase {$/;" c namespace:ramulator +AverageVector StatType.h /^class AverageVector: public VectorBase {$/;" c namespace:Stats +AverageVectorStat Statistics.h /^class AverageVectorStat : public VectorStatBase {$/;" c namespace:ramulator +Bank ALDRAM.h /^ Channel, Rank, Bank, Row, Column, MAX$/;" m class:ramulator::ALDRAM::Level +Bank DDR3.h /^ Channel, Rank, Bank, Row, Column, MAX$/;" m class:ramulator::DDR3::Level +Bank DDR4.h /^ Channel, Rank, BankGroup, Bank, Row, Column, MAX$/;" m class:ramulator::DDR4::Level +Bank DSARP.h /^ Channel, Rank, Bank, SubArray, Row, Column, MAX$/;" m class:ramulator::DSARP::Level +Bank GDDR5.h /^ Channel, Rank, BankGroup, Bank, Row, Column, MAX$/;" m class:ramulator::GDDR5::Level +Bank HBM.h /^ Channel, Rank, BankGroup, Bank, Row, Column, MAX$/;" m class:ramulator::HBM::Level +Bank LPDDR3.h /^ Channel, Rank, Bank, Row, Column, MAX$/;" m class:ramulator::LPDDR3::Level +Bank LPDDR4.h /^ Channel, Rank, Bank, Row, Column, MAX$/;" m class:ramulator::LPDDR4::Level +Bank SALP.h /^ Channel, Rank, Bank, SubArray, Row, Column, MAX$/;" m class:ramulator::SALP::Level +Bank TLDRAM.h /^ Channel, Rank, Bank, Row, Column, MAX$/;" m class:ramulator::TLDRAM::Level +Bank WideIO.h /^ Channel, Rank, Bank, Row, Column, MAX$/;" m class:ramulator::WideIO::Level +Bank WideIO2.h /^ Channel, Rank, Bank, Row, Column, MAX$/;" m class:ramulator::WideIO2::Level +BankGroup DDR4.h /^ Channel, Rank, BankGroup, Bank, Row, Column, MAX$/;" m class:ramulator::DDR4::Level +BankGroup GDDR5.h /^ Channel, Rank, BankGroup, Bank, Row, Column, MAX$/;" m class:ramulator::GDDR5::Level +BankGroup HBM.h /^ Channel, Rank, BankGroup, Bank, Row, Column, MAX$/;" m class:ramulator::HBM::Level +COLD ALDRAM.h /^ COLD, HOT, MAX$/;" m class:ramulator::ALDRAM::Temp +Cache Cache.cpp /^Cache::Cache(int size, int assoc, int block_size,$/;" f class:ramulator::Cache +Cache Cache.h /^class Cache {$/;" c namespace:ramulator +CacheSystem Cache.h /^ CacheSystem(const Config& configs, std::function send_memory):$/;" f class:ramulator::CacheSystem +CacheSystem Cache.h /^class CacheSystem {$/;" c namespace:ramulator +ChRaBaRoCo Memory.h /^ ChRaBaRoCo,$/;" m class:ramulator::Memory::Type +Channel ALDRAM.h /^ Channel, Rank, Bank, Row, Column, MAX$/;" m class:ramulator::ALDRAM::Level +Channel DDR3.h /^ Channel, Rank, Bank, Row, Column, MAX$/;" m class:ramulator::DDR3::Level +Channel DDR4.h /^ Channel, Rank, BankGroup, Bank, Row, Column, MAX$/;" m class:ramulator::DDR4::Level +Channel DSARP.h /^ Channel, Rank, Bank, SubArray, Row, Column, MAX$/;" m class:ramulator::DSARP::Level +Channel GDDR5.h /^ Channel, Rank, BankGroup, Bank, Row, Column, MAX$/;" m class:ramulator::GDDR5::Level +Channel HBM.h /^ Channel, Rank, BankGroup, Bank, Row, Column, MAX$/;" m class:ramulator::HBM::Level +Channel LPDDR3.h /^ Channel, Rank, Bank, Row, Column, MAX$/;" m class:ramulator::LPDDR3::Level +Channel LPDDR4.h /^ Channel, Rank, Bank, Row, Column, MAX$/;" m class:ramulator::LPDDR4::Level +Channel SALP.h /^ Channel, Rank, Bank, SubArray, Row, Column, MAX$/;" m class:ramulator::SALP::Level +Channel TLDRAM.h /^ Channel, Rank, Bank, Row, Column, MAX$/;" m class:ramulator::TLDRAM::Level +Channel WideIO.h /^ Channel, Rank, Bank, Row, Column, MAX$/;" m class:ramulator::WideIO::Level +Channel WideIO2.h /^ Channel, Rank, Bank, Row, Column, MAX$/;" m class:ramulator::WideIO2::Level +Closed ALDRAM.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::ALDRAM::State +Closed DDR3.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::DDR3::State +Closed DDR4.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::DDR4::State +Closed DSARP.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::DSARP::State +Closed GDDR5.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::GDDR5::State +Closed HBM.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::HBM::State +Closed LPDDR3.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::LPDDR3::State +Closed LPDDR4.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::LPDDR4::State +Closed SALP.h /^ Opened, Closed, Selected, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::SALP::State +Closed Scheduler.h /^ Closed, Opened, Timeout, MAX$/;" m class:ramulator::RowPolicy::Type +Closed TLDRAM.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::TLDRAM::State +Closed WideIO.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::WideIO::State +Closed WideIO2.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::WideIO2::State +Column ALDRAM.h /^ Channel, Rank, Bank, Row, Column, MAX$/;" m class:ramulator::ALDRAM::Level +Column DDR3.h /^ Channel, Rank, Bank, Row, Column, MAX$/;" m class:ramulator::DDR3::Level +Column DDR4.h /^ Channel, Rank, BankGroup, Bank, Row, Column, MAX$/;" m class:ramulator::DDR4::Level +Column DSARP.h /^ Channel, Rank, Bank, SubArray, Row, Column, MAX$/;" m class:ramulator::DSARP::Level +Column GDDR5.h /^ Channel, Rank, BankGroup, Bank, Row, Column, MAX$/;" m class:ramulator::GDDR5::Level +Column HBM.h /^ Channel, Rank, BankGroup, Bank, Row, Column, MAX$/;" m class:ramulator::HBM::Level +Column LPDDR3.h /^ Channel, Rank, Bank, Row, Column, MAX$/;" m class:ramulator::LPDDR3::Level +Column LPDDR4.h /^ Channel, Rank, Bank, Row, Column, MAX$/;" m class:ramulator::LPDDR4::Level +Column SALP.h /^ Channel, Rank, Bank, SubArray, Row, Column, MAX$/;" m class:ramulator::SALP::Level +Column TLDRAM.h /^ Channel, Rank, Bank, Row, Column, MAX$/;" m class:ramulator::TLDRAM::Level +Column WideIO.h /^ Channel, Rank, Bank, Row, Column, MAX$/;" m class:ramulator::WideIO::Level +Column WideIO2.h /^ Channel, Rank, Bank, Row, Column, MAX$/;" m class:ramulator::WideIO2::Level +Command ALDRAM.h /^ enum class Command : int$/;" c class:ramulator::ALDRAM +Command DDR3.h /^ enum class Command : int$/;" c class:ramulator::DDR3 +Command DDR4.h /^ enum class Command : int$/;" c class:ramulator::DDR4 +Command DSARP.h /^ enum class Command : int$/;" c class:ramulator::DSARP +Command GDDR5.h /^ enum class Command : int$/;" c class:ramulator::GDDR5 +Command HBM.h /^ enum class Command : int$/;" c class:ramulator::HBM +Command LPDDR3.h /^ enum class Command : int$/;" c class:ramulator::LPDDR3 +Command LPDDR4.h /^ enum class Command : int$/;" c class:ramulator::LPDDR4 +Command SALP.h /^ enum class Command : int$/;" c class:ramulator::SALP +Command TLDRAM.h /^ enum class Command : int$/;" c class:ramulator::TLDRAM +Command WideIO.h /^ enum class Command : int$/;" c class:ramulator::WideIO +Command WideIO2.h /^ enum class Command : int$/;" c class:ramulator::WideIO2 +Config Config.cpp /^Config::Config(const std::string& fname) {$/;" f class:Config +Config Config.h /^ Config() {}$/;" f class:ramulator::Config +Config Config.h /^class Config {$/;" c namespace:ramulator +ConstValue StatType.h /^ ConstValue(Counter __value):_value(__value){}$/;" f class:Stats::ConstValue +ConstValue StatType.h /^class ConstValue: public ScalarBase {$/;" c namespace:Stats +Controller Controller.h /^ Controller(const Config& configs, DRAM* channel) :$/;" f class:ramulator::Controller +Controller Controller.h /^class Controller$/;" c namespace:ramulator +Core Processor.cpp /^Core::Core(const Config& configs, int coreid,$/;" f class:Core +Core Processor.h /^class Core {$/;" c namespace:ramulator +Counter StatType.h /^typedef double Counter;$/;" t namespace:Stats +CounterLimits StatType.h /^typedef std::numeric_limits CounterLimits;$/;" t namespace:Stats +DARP DSARP.h /^ REFAB, REFPB, DARP, SARP, DSARP, MAX$/;" m class:ramulator::DSARP::Type +DDR3 DDR3.cpp /^DDR3::DDR3(Org org, Speed speed) :$/;" f class:DDR3 +DDR3 DDR3.cpp /^DDR3::DDR3(const string& org_str, const string& speed_str) :$/;" f class:DDR3 +DDR3 DDR3.h /^class DDR3$/;" c namespace:ramulator +DDR3_1066E DDR3.h /^ DDR3_1066E, DDR3_1066F, DDR3_1066G,$/;" m class:ramulator::DDR3::Speed +DDR3_1066F DDR3.h /^ DDR3_1066E, DDR3_1066F, DDR3_1066G,$/;" m class:ramulator::DDR3::Speed +DDR3_1066G DDR3.h /^ DDR3_1066E, DDR3_1066F, DDR3_1066G,$/;" m class:ramulator::DDR3::Speed +DDR3_1333G DDR3.h /^ DDR3_1333G, DDR3_1333H,$/;" m class:ramulator::DDR3::Speed +DDR3_1333H DDR3.h /^ DDR3_1333G, DDR3_1333H,$/;" m class:ramulator::DDR3::Speed +DDR3_1600H DDR3.h /^ DDR3_1600H, DDR3_1600J, DDR3_1600K,$/;" m class:ramulator::DDR3::Speed +DDR3_1600J DDR3.h /^ DDR3_1600H, DDR3_1600J, DDR3_1600K,$/;" m class:ramulator::DDR3::Speed +DDR3_1600K DDR3.h /^ DDR3_1600H, DDR3_1600J, DDR3_1600K,$/;" m class:ramulator::DDR3::Speed +DDR3_1866K DDR3.h /^ DDR3_1866K, DDR3_1866L,$/;" m class:ramulator::DDR3::Speed +DDR3_1866L DDR3.h /^ DDR3_1866K, DDR3_1866L,$/;" m class:ramulator::DDR3::Speed +DDR3_1Gb_x16 DDR3.h /^ DDR3_1Gb_x4, DDR3_1Gb_x8, DDR3_1Gb_x16,$/;" m class:ramulator::DDR3::Org +DDR3_1Gb_x4 DDR3.h /^ DDR3_1Gb_x4, DDR3_1Gb_x8, DDR3_1Gb_x16,$/;" m class:ramulator::DDR3::Org +DDR3_1Gb_x8 DDR3.h /^ DDR3_1Gb_x4, DDR3_1Gb_x8, DDR3_1Gb_x16,$/;" m class:ramulator::DDR3::Org +DDR3_2133L DDR3.h /^ DDR3_2133L, DDR3_2133M,$/;" m class:ramulator::DDR3::Speed +DDR3_2133M DDR3.h /^ DDR3_2133L, DDR3_2133M,$/;" m class:ramulator::DDR3::Speed +DDR3_2Gb_x16 DDR3.h /^ DDR3_2Gb_x4, DDR3_2Gb_x8, DDR3_2Gb_x16,$/;" m class:ramulator::DDR3::Org +DDR3_2Gb_x4 DDR3.h /^ DDR3_2Gb_x4, DDR3_2Gb_x8, DDR3_2Gb_x16,$/;" m class:ramulator::DDR3::Org +DDR3_2Gb_x8 DDR3.h /^ DDR3_2Gb_x4, DDR3_2Gb_x8, DDR3_2Gb_x16,$/;" m class:ramulator::DDR3::Org +DDR3_4Gb_x16 DDR3.h /^ DDR3_4Gb_x4, DDR3_4Gb_x8, DDR3_4Gb_x16,$/;" m class:ramulator::DDR3::Org +DDR3_4Gb_x4 DDR3.h /^ DDR3_4Gb_x4, DDR3_4Gb_x8, DDR3_4Gb_x16,$/;" m class:ramulator::DDR3::Org +DDR3_4Gb_x8 DDR3.h /^ DDR3_4Gb_x4, DDR3_4Gb_x8, DDR3_4Gb_x16,$/;" m class:ramulator::DDR3::Org +DDR3_512Mb_x16 DDR3.h /^ DDR3_512Mb_x4, DDR3_512Mb_x8, DDR3_512Mb_x16,$/;" m class:ramulator::DDR3::Org +DDR3_512Mb_x4 DDR3.h /^ DDR3_512Mb_x4, DDR3_512Mb_x8, DDR3_512Mb_x16,$/;" m class:ramulator::DDR3::Org +DDR3_512Mb_x8 DDR3.h /^ DDR3_512Mb_x4, DDR3_512Mb_x8, DDR3_512Mb_x16,$/;" m class:ramulator::DDR3::Org +DDR3_800D DDR3.h /^ DDR3_800D, DDR3_800E,$/;" m class:ramulator::DDR3::Speed +DDR3_800E DDR3.h /^ DDR3_800D, DDR3_800E,$/;" m class:ramulator::DDR3::Speed +DDR3_8Gb_x16 DDR3.h /^ DDR3_8Gb_x4, DDR3_8Gb_x8, DDR3_8Gb_x16,$/;" m class:ramulator::DDR3::Org +DDR3_8Gb_x4 DDR3.h /^ DDR3_8Gb_x4, DDR3_8Gb_x8, DDR3_8Gb_x16,$/;" m class:ramulator::DDR3::Org +DDR3_8Gb_x8 DDR3.h /^ DDR3_8Gb_x4, DDR3_8Gb_x8, DDR3_8Gb_x16,$/;" m class:ramulator::DDR3::Org +DDR4 DDR4.cpp /^DDR4::DDR4(Org org, Speed speed)$/;" f class:DDR4 +DDR4 DDR4.cpp /^DDR4::DDR4(const string& org_str, const string& speed_str) :$/;" f class:DDR4 +DDR4 DDR4.h /^class DDR4$/;" c namespace:ramulator +DDR4_1600K DDR4.h /^ DDR4_1600K, DDR4_1600L,$/;" m class:ramulator::DDR4::Speed +DDR4_1600L DDR4.h /^ DDR4_1600K, DDR4_1600L,$/;" m class:ramulator::DDR4::Speed +DDR4_1866M DDR4.h /^ DDR4_1866M, DDR4_1866N,$/;" m class:ramulator::DDR4::Speed +DDR4_1866N DDR4.h /^ DDR4_1866M, DDR4_1866N,$/;" m class:ramulator::DDR4::Speed +DDR4_2133P DDR4.h /^ DDR4_2133P, DDR4_2133R,$/;" m class:ramulator::DDR4::Speed +DDR4_2133R DDR4.h /^ DDR4_2133P, DDR4_2133R,$/;" m class:ramulator::DDR4::Speed +DDR4_2400R DDR4.h /^ DDR4_2400R, DDR4_2400U,$/;" m class:ramulator::DDR4::Speed +DDR4_2400U DDR4.h /^ DDR4_2400R, DDR4_2400U,$/;" m class:ramulator::DDR4::Speed +DDR4_2Gb_x16 DDR4.h /^ DDR4_2Gb_x4, DDR4_2Gb_x8, DDR4_2Gb_x16,$/;" m class:ramulator::DDR4::Org +DDR4_2Gb_x4 DDR4.h /^ DDR4_2Gb_x4, DDR4_2Gb_x8, DDR4_2Gb_x16,$/;" m class:ramulator::DDR4::Org +DDR4_2Gb_x8 DDR4.h /^ DDR4_2Gb_x4, DDR4_2Gb_x8, DDR4_2Gb_x16,$/;" m class:ramulator::DDR4::Org +DDR4_4Gb_x16 DDR4.h /^ DDR4_4Gb_x4, DDR4_4Gb_x8, DDR4_4Gb_x16,$/;" m class:ramulator::DDR4::Org +DDR4_4Gb_x4 DDR4.h /^ DDR4_4Gb_x4, DDR4_4Gb_x8, DDR4_4Gb_x16,$/;" m class:ramulator::DDR4::Org +DDR4_4Gb_x8 DDR4.h /^ DDR4_4Gb_x4, DDR4_4Gb_x8, DDR4_4Gb_x16,$/;" m class:ramulator::DDR4::Org +DDR4_8Gb_x16 DDR4.h /^ DDR4_8Gb_x4, DDR4_8Gb_x8, DDR4_8Gb_x16,$/;" m class:ramulator::DDR4::Org +DDR4_8Gb_x4 DDR4.h /^ DDR4_8Gb_x4, DDR4_8Gb_x8, DDR4_8Gb_x16,$/;" m class:ramulator::DDR4::Org +DDR4_8Gb_x8 DDR4.h /^ DDR4_8Gb_x4, DDR4_8Gb_x8, DDR4_8Gb_x16,$/;" m class:ramulator::DDR4::Org +DRAM DRAM.h /^ DRAM(){}$/;" f class:ramulator::DRAM +DRAM DRAM.h /^DRAM::DRAM(T* spec, typename T::Level level) :$/;" f class:ramulator::DRAM +DRAM DRAM.h /^class DRAM$/;" c namespace:ramulator +DSARP DSARP.cpp /^DSARP::DSARP(Org org, Speed speed, Type type, int n_sa) :$/;" f class:DSARP +DSARP DSARP.cpp /^DSARP::DSARP(const string& org_str, const string& speed_str, Type type, int n_sa) :$/;" f class:DSARP +DSARP DSARP.h /^ REFAB, REFPB, DARP, SARP, DSARP, MAX$/;" m class:ramulator::DSARP::Type +DSARP DSARP.h /^class DSARP$/;" c namespace:ramulator +DSARP_1333 DSARP.h /^ DSARP_1333,$/;" m class:ramulator::DSARP::Speed +DSARP_16Gb_x8 DSARP.h /^ DSARP_16Gb_x8,$/;" m class:ramulator::DSARP::Org +DSARP_32Gb_x8 DSARP.h /^ DSARP_32Gb_x8,$/;" m class:ramulator::DSARP::Org +DSARP_8Gb_x8 DSARP.h /^ DSARP_8Gb_x8,$/;" m class:ramulator::DSARP::Org +DSARP_H_ DSARP.h 36;" d +DistStatBase Statistics.h /^class DistStatBase : public StatBase { \/\/ wrapper for Stats::DistBase$/;" c namespace:ramulator +Distribution StatType.h /^ Distribution():param_min(Counter()), param_max(Counter()),$/;" f class:Stats::Distribution +Distribution StatType.h /^class Distribution: public Stat {$/;" c namespace:Stats +DistributionStat Statistics.h /^class DistributionStat : public DistStatBase {$/;" c namespace:ramulator +EXTENSION Request.h /^ EXTENSION,$/;" m class:ramulator::Request::Type +Entry Scheduler.h /^ struct Entry {$/;" s class:ramulator::RowTable +FCFS Scheduler.h /^ FCFS, FRFCFS, FRFCFS_Cap, FRFCFS_PriorHit, MAX$/;" m class:ramulator::Scheduler::Type +FRFCFS Scheduler.h /^ FCFS, FRFCFS, FRFCFS_Cap, FRFCFS_PriorHit, MAX$/;" m class:ramulator::Scheduler::Type +FRFCFS_Cap Scheduler.h /^ FCFS, FRFCFS, FRFCFS_Cap, FRFCFS_PriorHit, MAX$/;" m class:ramulator::Scheduler::Type +FRFCFS_PriorHit Scheduler.h /^ FCFS, FRFCFS, FRFCFS_Cap, FRFCFS_PriorHit, MAX$/;" m class:ramulator::Scheduler::Type +Flags StatType.h /^ Flags(){}$/;" f class:Stats::Flags +Flags StatType.h /^ Flags(uint16_t flags):flags(flags){}$/;" f class:Stats::Flags +Flags StatType.h /^class Flags {$/;" c namespace:Stats +GDDR5 GDDR5.cpp /^GDDR5::GDDR5(Org org, Speed speed) : $/;" f class:GDDR5 +GDDR5 GDDR5.cpp /^GDDR5::GDDR5(const string& org_str, const string& speed_str) :$/;" f class:GDDR5 +GDDR5 GDDR5.h /^class GDDR5$/;" c namespace:ramulator +GDDR5_1Gb_x16 GDDR5.h /^ GDDR5_1Gb_x16, GDDR5_1Gb_x32,$/;" m class:ramulator::GDDR5::Org +GDDR5_1Gb_x32 GDDR5.h /^ GDDR5_1Gb_x16, GDDR5_1Gb_x32,$/;" m class:ramulator::GDDR5::Org +GDDR5_2Gb_x16 GDDR5.h /^ GDDR5_2Gb_x16, GDDR5_2Gb_x32,$/;" m class:ramulator::GDDR5::Org +GDDR5_2Gb_x32 GDDR5.h /^ GDDR5_2Gb_x16, GDDR5_2Gb_x32,$/;" m class:ramulator::GDDR5::Org +GDDR5_4000 GDDR5.h /^ GDDR5_4000, GDDR5_4500,$/;" m class:ramulator::GDDR5::Speed +GDDR5_4500 GDDR5.h /^ GDDR5_4000, GDDR5_4500,$/;" m class:ramulator::GDDR5::Speed +GDDR5_4Gb_x16 GDDR5.h /^ GDDR5_4Gb_x16, GDDR5_4Gb_x32,$/;" m class:ramulator::GDDR5::Org +GDDR5_4Gb_x32 GDDR5.h /^ GDDR5_4Gb_x16, GDDR5_4Gb_x32,$/;" m class:ramulator::GDDR5::Org +GDDR5_5000 GDDR5.h /^ GDDR5_5000, GDDR5_5500,$/;" m class:ramulator::GDDR5::Speed +GDDR5_512Mb_x16 GDDR5.h /^ GDDR5_512Mb_x16, GDDR5_512Mb_x32,$/;" m class:ramulator::GDDR5::Org +GDDR5_512Mb_x32 GDDR5.h /^ GDDR5_512Mb_x16, GDDR5_512Mb_x32,$/;" m class:ramulator::GDDR5::Org +GDDR5_5500 GDDR5.h /^ GDDR5_5000, GDDR5_5500,$/;" m class:ramulator::GDDR5::Speed +GDDR5_6000 GDDR5.h /^ GDDR5_6000, GDDR5_6500,$/;" m class:ramulator::GDDR5::Speed +GDDR5_6500 GDDR5.h /^ GDDR5_6000, GDDR5_6500,$/;" m class:ramulator::GDDR5::Speed +GDDR5_7000 GDDR5.h /^ GDDR5_7000,$/;" m class:ramulator::GDDR5::Speed +GDDR5_8Gb_x16 GDDR5.h /^ GDDR5_8Gb_x16, GDDR5_8Gb_x32,$/;" m class:ramulator::GDDR5::Org +GDDR5_8Gb_x32 GDDR5.h /^ GDDR5_8Gb_x16, GDDR5_8Gb_x32,$/;" m class:ramulator::GDDR5::Org +Gem5Wrapper Gem5Wrapper.cpp /^Gem5Wrapper::Gem5Wrapper(const Config& configs, int cacheline)$/;" f class:Gem5Wrapper +Gem5Wrapper Gem5Wrapper.h /^class Gem5Wrapper $/;" c namespace:ramulator +HBM HBM.cpp /^HBM::HBM(Org org, Speed speed)$/;" f class:HBM +HBM HBM.cpp /^HBM::HBM(const string& org_str, const string& speed_str) :$/;" f class:HBM +HBM HBM.h /^class HBM$/;" c namespace:ramulator +HBM_1Gb HBM.h /^ HBM_1Gb,$/;" m class:ramulator::HBM::Org +HBM_1Gbps HBM.h /^ HBM_1Gbps,$/;" m class:ramulator::HBM::Speed +HBM_2Gb HBM.h /^ HBM_2Gb,$/;" m class:ramulator::HBM::Org +HBM_4Gb HBM.h /^ HBM_4Gb,$/;" m class:ramulator::HBM::Org +HOT ALDRAM.h /^ COLD, HOT, MAX$/;" m class:ramulator::ALDRAM::Temp +Histogram StatType.h /^ Histogram():param_buckets(0) { reset(); }$/;" f class:Stats::Histogram +Histogram StatType.h /^ Histogram(size_type __buckets):cvec(__buckets) {$/;" f class:Stats::Histogram +Histogram StatType.h /^class Histogram: public Stat {$/;" c namespace:Stats +HistogramStat Statistics.h /^class HistogramStat : public DistStatBase {$/;" c namespace:ramulator +INTEGRATED_WITH_GEM5 Statistics.h 8;" d +L1 Cache.h /^ L1,$/;" m class:ramulator::Cache::Level +L2 Cache.h /^ L2,$/;" m class:ramulator::Cache::Level +L3 Cache.h /^ L3,$/;" m class:ramulator::Cache::Level +LPDDR3 LPDDR3.cpp /^LPDDR3::LPDDR3(Org org, Speed speed)$/;" f class:LPDDR3 +LPDDR3 LPDDR3.cpp /^LPDDR3::LPDDR3(const string& org_str, const string& speed_str) :$/;" f class:LPDDR3 +LPDDR3 LPDDR3.h /^class LPDDR3$/;" c namespace:ramulator +LPDDR3_12Gb_x16 LPDDR3.h /^ LPDDR3_12Gb_x16, LPDDR3_12Gb_x32,$/;" m class:ramulator::LPDDR3::Org +LPDDR3_12Gb_x32 LPDDR3.h /^ LPDDR3_12Gb_x16, LPDDR3_12Gb_x32,$/;" m class:ramulator::LPDDR3::Org +LPDDR3_1333 LPDDR3.h /^ LPDDR3_1333,$/;" m class:ramulator::LPDDR3::Speed +LPDDR3_1600 LPDDR3.h /^ LPDDR3_1600,$/;" m class:ramulator::LPDDR3::Speed +LPDDR3_16Gb_x16 LPDDR3.h /^ LPDDR3_16Gb_x16, LPDDR3_16Gb_x32,$/;" m class:ramulator::LPDDR3::Org +LPDDR3_16Gb_x32 LPDDR3.h /^ LPDDR3_16Gb_x16, LPDDR3_16Gb_x32,$/;" m class:ramulator::LPDDR3::Org +LPDDR3_1866 LPDDR3.h /^ LPDDR3_1866,$/;" m class:ramulator::LPDDR3::Speed +LPDDR3_2133 LPDDR3.h /^ LPDDR3_2133,$/;" m class:ramulator::LPDDR3::Speed +LPDDR3_4Gb_x16 LPDDR3.h /^ LPDDR3_4Gb_x16, LPDDR3_4Gb_x32,$/;" m class:ramulator::LPDDR3::Org +LPDDR3_4Gb_x32 LPDDR3.h /^ LPDDR3_4Gb_x16, LPDDR3_4Gb_x32,$/;" m class:ramulator::LPDDR3::Org +LPDDR3_6Gb_x16 LPDDR3.h /^ LPDDR3_6Gb_x16, LPDDR3_6Gb_x32,$/;" m class:ramulator::LPDDR3::Org +LPDDR3_6Gb_x32 LPDDR3.h /^ LPDDR3_6Gb_x16, LPDDR3_6Gb_x32,$/;" m class:ramulator::LPDDR3::Org +LPDDR3_8Gb_x16 LPDDR3.h /^ LPDDR3_8Gb_x16, LPDDR3_8Gb_x32,$/;" m class:ramulator::LPDDR3::Org +LPDDR3_8Gb_x32 LPDDR3.h /^ LPDDR3_8Gb_x16, LPDDR3_8Gb_x32,$/;" m class:ramulator::LPDDR3::Org +LPDDR4 LPDDR4.cpp /^LPDDR4::LPDDR4(Org org, Speed speed)$/;" f class:LPDDR4 +LPDDR4 LPDDR4.cpp /^LPDDR4::LPDDR4(const string& org_str, const string& speed_str) :$/;" f class:LPDDR4 +LPDDR4 LPDDR4.h /^class LPDDR4$/;" c namespace:ramulator +LPDDR4_1600 LPDDR4.h /^ LPDDR4_1600,$/;" m class:ramulator::LPDDR4::Speed +LPDDR4_2400 LPDDR4.h /^ LPDDR4_2400,$/;" m class:ramulator::LPDDR4::Speed +LPDDR4_3200 LPDDR4.h /^ LPDDR4_3200,$/;" m class:ramulator::LPDDR4::Speed +LPDDR4_4Gb_x16 LPDDR4.h /^ LPDDR4_4Gb_x16,$/;" m class:ramulator::LPDDR4::Org +LPDDR4_6Gb_x16 LPDDR4.h /^ LPDDR4_6Gb_x16,$/;" m class:ramulator::LPDDR4::Org +LPDDR4_8Gb_x16 LPDDR4.h /^ LPDDR4_8Gb_x16,$/;" m class:ramulator::LPDDR4::Org +Level ALDRAM.h /^ enum class Level : int$/;" c class:ramulator::ALDRAM +Level Cache.h /^ enum class Level {$/;" c class:ramulator::Cache +Level DDR3.h /^ enum class Level : int$/;" c class:ramulator::DDR3 +Level DDR4.h /^ enum class Level : int$/;" c class:ramulator::DDR4 +Level DSARP.h /^ enum class Level : int$/;" c class:ramulator::DSARP +Level GDDR5.h /^ enum class Level : int$/;" c class:ramulator::GDDR5 +Level HBM.h /^ enum class Level : int$/;" c class:ramulator::HBM +Level LPDDR3.h /^ enum class Level : int$/;" c class:ramulator::LPDDR3 +Level LPDDR4.h /^ enum class Level : int$/;" c class:ramulator::LPDDR4 +Level SALP.h /^ enum class Level : int$/;" c class:ramulator::SALP +Level TLDRAM.h /^ enum class Level : int$/;" c class:ramulator::TLDRAM +Level WideIO.h /^ enum class Level : int$/;" c class:ramulator::WideIO +Level WideIO2.h /^ enum class Level : int$/;" c class:ramulator::WideIO2 +Line Cache.h /^ Line(long addr, long tag):$/;" f struct:ramulator::Cache::Line +Line Cache.h /^ Line(long addr, long tag, bool lock, bool dirty):$/;" f struct:ramulator::Cache::Line +Line Cache.h /^ struct Line {$/;" s class:ramulator::Cache +MASA SALP.h /^ SALP_1, SALP_2, MASA, MAX$/;" m class:ramulator::SALP::Type +MAX Memory.h /^ MAX,$/;" m class:ramulator::Memory::Type +MAX Memory.h /^ MAX,$/;" m class:ramulator::Memory::Translation +MIG TLDRAM.h /^ MIG,$/;" m class:ramulator::TLDRAM::Command +MemOp common.cpp /^MemOp::MemOp(bool _valid){$/;" f class:MemOp +MemOp common.cpp /^MemOp::MemOp(ramulator::Request::Type _type, $/;" f class:MemOp +MemOp common.h /^struct MemOp {$/;" s +MemOpUpdate common.cpp /^void MemOp::MemOpUpdate(const ramulator::Request &req){$/;" f class:MemOp +MemWrapper MemWrapper.cpp /^MemWrapper::MemWrapper(sc_module_name _name, int argc, char* argv[]) $/;" f class:MemWrapper +MemWrapper MemWrapper.h /^class MemWrapper : public sc_module{$/;" c +Memory Memory.h /^ Memory(const Config& configs, vector*> ctrls)$/;" f class:ramulator::Memory +Memory Memory.h /^class Memory : public MemoryBase$/;" c namespace:ramulator +MemoryBase Memory.h /^ MemoryBase() {}$/;" f class:ramulator::MemoryBase +MemoryBase Memory.h /^class MemoryBase{$/;" c namespace:ramulator +MemoryFactory MemoryFactory.h /^class MemoryFactory {$/;" c namespace:ramulator +None Memory.h /^ None,$/;" m class:ramulator::Memory::Translation +Op StatType.h /^ Op() {}$/;" f class:Stats::Op +Op StatType.h /^ Op(std::string __opstring):opstring(__opstring){}$/;" f class:Stats::Op +Op StatType.h /^class Op {$/;" c namespace:Stats +Opened ALDRAM.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::ALDRAM::State +Opened DDR3.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::DDR3::State +Opened DDR4.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::DDR4::State +Opened DSARP.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::DSARP::State +Opened GDDR5.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::GDDR5::State +Opened HBM.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::HBM::State +Opened LPDDR3.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::LPDDR3::State +Opened LPDDR4.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::LPDDR4::State +Opened SALP.h /^ Opened, Closed, Selected, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::SALP::State +Opened Scheduler.h /^ Closed, Opened, Timeout, MAX$/;" m class:ramulator::RowPolicy::Type +Opened TLDRAM.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::TLDRAM::State +Opened WideIO.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::WideIO::State +Opened WideIO2.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::WideIO2::State +Org ALDRAM.h /^ enum class Org : int$/;" c class:ramulator::ALDRAM +Org DDR3.h /^ enum class Org : int$/;" c class:ramulator::DDR3 +Org DDR4.h /^ enum class Org : int$/;" c class:ramulator::DDR4 +Org DSARP.h /^ enum class Org : int$/;" c class:ramulator::DSARP +Org GDDR5.h /^ enum class Org : int$/;" c class:ramulator::GDDR5 +Org HBM.h /^ enum class Org : int$/;" c class:ramulator::HBM +Org LPDDR3.h /^ enum class Org : int$/;" c class:ramulator::LPDDR3 +Org LPDDR4.h /^ enum class Org : int$/;" c class:ramulator::LPDDR4 +Org SALP.h /^ enum class Org : int$/;" c class:ramulator::SALP +Org TLDRAM.h /^ enum class Org : int$/;" c class:ramulator::TLDRAM +Org WideIO.h /^ enum class Org : int$/;" c class:ramulator::WideIO +Org WideIO2.h /^ enum class Org : int$/;" c class:ramulator::WideIO2 +OrgEntry ALDRAM.h /^ struct OrgEntry {$/;" s class:ramulator::ALDRAM +OrgEntry DDR3.h /^ struct OrgEntry {$/;" s class:ramulator::DDR3 +OrgEntry DDR4.h /^ struct OrgEntry {$/;" s class:ramulator::DDR4 +OrgEntry DSARP.h /^ struct OrgEntry {$/;" s class:ramulator::DSARP +OrgEntry GDDR5.h /^ struct OrgEntry {$/;" s class:ramulator::GDDR5 +OrgEntry HBM.h /^ struct OrgEntry {$/;" s class:ramulator::HBM +OrgEntry LPDDR3.h /^ struct OrgEntry {$/;" s class:ramulator::LPDDR3 +OrgEntry LPDDR4.h /^ struct OrgEntry {$/;" s class:ramulator::LPDDR4 +OrgEntry SALP.h /^ struct OrgEntry {$/;" s class:ramulator::SALP +OrgEntry TLDRAM.h /^ struct OrgEntry {$/;" s class:ramulator::TLDRAM +OrgEntry WideIO.h /^ struct OrgEntry {$/;" s class:ramulator::WideIO +OrgEntry WideIO2.h /^ struct OrgEntry {$/;" s class:ramulator::WideIO2 +PD LPDDR3.h /^ REF, REFPB, PD, PDX, SREF, SREFX, $/;" m class:ramulator::LPDDR3::Command +PD WideIO.h /^ REF, PD, PDX, SREF, SREFX, $/;" m class:ramulator::WideIO::Command +PD WideIO2.h /^ REF, REFPB, PD, PDX, SREF, SREFX, $/;" m class:ramulator::WideIO2::Command +PDE ALDRAM.h /^ REF, PDE, PDX, SRE, SRX,$/;" m class:ramulator::ALDRAM::Command +PDE DDR3.h /^ REF, PDE, PDX, SRE, SRX, $/;" m class:ramulator::DDR3::Command +PDE DDR4.h /^ REF, PDE, PDX, SRE, SRX, $/;" m class:ramulator::DDR4::Command +PDE DSARP.h /^ REF, REFPB, PDE, PDX, SRE, SRX,$/;" m class:ramulator::DSARP::Command +PDE GDDR5.h /^ REF, PDE, PDX, SRE, SRX, $/;" m class:ramulator::GDDR5::Command +PDE HBM.h /^ REF, REFSB, PDE, PDX, SRE, SRX,$/;" m class:ramulator::HBM::Command +PDE LPDDR4.h /^ REF, REFPB, PDE, PDX, SREF, SREFX, $/;" m class:ramulator::LPDDR4::Command +PDE SALP.h /^ REF, PDE, PDX, SRE, SRX, $/;" m class:ramulator::SALP::Command +PDE TLDRAM.h /^ REF, PDE, PDX, SRE, SRX,$/;" m class:ramulator::TLDRAM::Command +PDX ALDRAM.h /^ REF, PDE, PDX, SRE, SRX,$/;" m class:ramulator::ALDRAM::Command +PDX DDR3.h /^ REF, PDE, PDX, SRE, SRX, $/;" m class:ramulator::DDR3::Command +PDX DDR4.h /^ REF, PDE, PDX, SRE, SRX, $/;" m class:ramulator::DDR4::Command +PDX DSARP.h /^ REF, REFPB, PDE, PDX, SRE, SRX,$/;" m class:ramulator::DSARP::Command +PDX GDDR5.h /^ REF, PDE, PDX, SRE, SRX, $/;" m class:ramulator::GDDR5::Command +PDX HBM.h /^ REF, REFSB, PDE, PDX, SRE, SRX,$/;" m class:ramulator::HBM::Command +PDX LPDDR3.h /^ REF, REFPB, PD, PDX, SREF, SREFX, $/;" m class:ramulator::LPDDR3::Command +PDX LPDDR4.h /^ REF, REFPB, PDE, PDX, SREF, SREFX, $/;" m class:ramulator::LPDDR4::Command +PDX SALP.h /^ REF, PDE, PDX, SRE, SRX, $/;" m class:ramulator::SALP::Command +PDX TLDRAM.h /^ REF, PDE, PDX, SRE, SRX,$/;" m class:ramulator::TLDRAM::Command +PDX WideIO.h /^ REF, PD, PDX, SREF, SREFX, $/;" m class:ramulator::WideIO::Command +PDX WideIO2.h /^ REF, REFPB, PD, PDX, SREF, SREFX, $/;" m class:ramulator::WideIO2::Command +POWERDOWN Request.h /^ POWERDOWN,$/;" m class:ramulator::Request::Type +PRA LPDDR3.h /^ ACT, PRE, PRA, $/;" m class:ramulator::LPDDR3::Command +PRA WideIO.h /^ ACT, PRE, PRA, $/;" m class:ramulator::WideIO::Command +PRA WideIO2.h /^ ACT, PRE, PRA, $/;" m class:ramulator::WideIO2::Command +PRE ALDRAM.h /^ ACT, PRE, PREA,$/;" m class:ramulator::ALDRAM::Command +PRE DDR3.h /^ ACT, PRE, PREA, $/;" m class:ramulator::DDR3::Command +PRE DDR4.h /^ ACT, PRE, PREA, $/;" m class:ramulator::DDR4::Command +PRE DSARP.h /^ ACT, PRE, PREA,$/;" m class:ramulator::DSARP::Command +PRE GDDR5.h /^ ACT, PRE, PREA, $/;" m class:ramulator::GDDR5::Command +PRE HBM.h /^ ACT, PRE, PREA,$/;" m class:ramulator::HBM::Command +PRE LPDDR3.h /^ ACT, PRE, PRA, $/;" m class:ramulator::LPDDR3::Command +PRE LPDDR4.h /^ ACT, PRE, PREA, $/;" m class:ramulator::LPDDR4::Command +PRE SALP.h /^ ACT, SASEL, PRE, PRER, \/\/ precharge bank\/bank\/rank(SALP-1), subarray\/bank\/rank(SALP-2, MASA)$/;" m class:ramulator::SALP::Command +PRE TLDRAM.h /^ ACT, PRE, PREA,$/;" m class:ramulator::TLDRAM::Command +PRE WideIO.h /^ ACT, PRE, PRA, $/;" m class:ramulator::WideIO::Command +PRE WideIO2.h /^ ACT, PRE, PRA, $/;" m class:ramulator::WideIO2::Command +PREA ALDRAM.h /^ ACT, PRE, PREA,$/;" m class:ramulator::ALDRAM::Command +PREA DDR3.h /^ ACT, PRE, PREA, $/;" m class:ramulator::DDR3::Command +PREA DDR4.h /^ ACT, PRE, PREA, $/;" m class:ramulator::DDR4::Command +PREA DSARP.h /^ ACT, PRE, PREA,$/;" m class:ramulator::DSARP::Command +PREA GDDR5.h /^ ACT, PRE, PREA, $/;" m class:ramulator::GDDR5::Command +PREA HBM.h /^ ACT, PRE, PREA,$/;" m class:ramulator::HBM::Command +PREA LPDDR4.h /^ ACT, PRE, PREA, $/;" m class:ramulator::LPDDR4::Command +PREA TLDRAM.h /^ ACT, PRE, PREA,$/;" m class:ramulator::TLDRAM::Command +PREAF TLDRAM.h /^ ACTF, PREF, PREAF,$/;" m class:ramulator::TLDRAM::Command +PREAM TLDRAM.h /^ ACTM, PREM, PREAM,$/;" m class:ramulator::TLDRAM::Command +PREF TLDRAM.h /^ ACTF, PREF, PREAF,$/;" m class:ramulator::TLDRAM::Command +PREM TLDRAM.h /^ ACTM, PREM, PREAM,$/;" m class:ramulator::TLDRAM::Command +PRER SALP.h /^ ACT, SASEL, PRE, PRER, \/\/ precharge bank\/bank\/rank(SALP-1), subarray\/bank\/rank(SALP-2, MASA)$/;" m class:ramulator::SALP::Command +PRE_OTHER SALP.h /^ PRE_OTHER,$/;" m class:ramulator::SALP::Command +PowerUp ALDRAM.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::ALDRAM::State +PowerUp DDR3.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::DDR3::State +PowerUp DDR4.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::DDR4::State +PowerUp DSARP.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::DSARP::State +PowerUp GDDR5.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::GDDR5::State +PowerUp HBM.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::HBM::State +PowerUp LPDDR3.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::LPDDR3::State +PowerUp LPDDR4.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::LPDDR4::State +PowerUp SALP.h /^ Opened, Closed, Selected, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::SALP::State +PowerUp TLDRAM.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::TLDRAM::State +PowerUp WideIO.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::WideIO::State +PowerUp WideIO2.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::WideIO2::State +PrePowerDown ALDRAM.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::ALDRAM::State +PrePowerDown DDR3.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::DDR3::State +PrePowerDown DDR4.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::DDR4::State +PrePowerDown DSARP.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::DSARP::State +PrePowerDown GDDR5.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::GDDR5::State +PrePowerDown HBM.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::HBM::State +PrePowerDown LPDDR3.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::LPDDR3::State +PrePowerDown LPDDR4.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::LPDDR4::State +PrePowerDown SALP.h /^ Opened, Closed, Selected, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::SALP::State +PrePowerDown TLDRAM.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::TLDRAM::State +PrePowerDown WideIO.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::WideIO::State +PrePowerDown WideIO2.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::WideIO2::State +Processor Processor.cpp /^Processor::Processor(const Config& configs,$/;" f class:Processor +Processor Processor.h /^class Processor {$/;" c namespace:ramulator +Queue Controller.h /^ struct Queue {$/;" s class:ramulator::Controller +RD ALDRAM.h /^ RD, WR, RDA, WRA,$/;" m class:ramulator::ALDRAM::Command +RD DDR3.h /^ RD, WR, RDA, WRA, $/;" m class:ramulator::DDR3::Command +RD DDR4.h /^ RD, WR, RDA, WRA, $/;" m class:ramulator::DDR4::Command +RD DSARP.h /^ RD, WR, RDA, WRA,$/;" m class:ramulator::DSARP::Command +RD GDDR5.h /^ RD, WR, RDA, WRA, $/;" m class:ramulator::GDDR5::Command +RD HBM.h /^ RD, WR, RDA, WRA,$/;" m class:ramulator::HBM::Command +RD LPDDR3.h /^ RD, WR, RDA, WRA, $/;" m class:ramulator::LPDDR3::Command +RD LPDDR4.h /^ RD, WR, RDA, WRA, $/;" m class:ramulator::LPDDR4::Command +RD SALP.h /^ RD, WR, RDA, WRA, \/\/ auto-precharge: bank(SALP-1), subarray(SALP-2, MASA)$/;" m class:ramulator::SALP::Command +RD TLDRAM.h /^ RD, WR,$/;" m class:ramulator::TLDRAM::Command +RD WideIO.h /^ RD, WR, RDA, WRA, $/;" m class:ramulator::WideIO::Command +RD WideIO2.h /^ RD, WR, RDA, WRA, $/;" m class:ramulator::WideIO2::Command +RDA ALDRAM.h /^ RD, WR, RDA, WRA,$/;" m class:ramulator::ALDRAM::Command +RDA DDR3.h /^ RD, WR, RDA, WRA, $/;" m class:ramulator::DDR3::Command +RDA DDR4.h /^ RD, WR, RDA, WRA, $/;" m class:ramulator::DDR4::Command +RDA DSARP.h /^ RD, WR, RDA, WRA,$/;" m class:ramulator::DSARP::Command +RDA GDDR5.h /^ RD, WR, RDA, WRA, $/;" m class:ramulator::GDDR5::Command +RDA HBM.h /^ RD, WR, RDA, WRA,$/;" m class:ramulator::HBM::Command +RDA LPDDR3.h /^ RD, WR, RDA, WRA, $/;" m class:ramulator::LPDDR3::Command +RDA LPDDR4.h /^ RD, WR, RDA, WRA, $/;" m class:ramulator::LPDDR4::Command +RDA SALP.h /^ RD, WR, RDA, WRA, \/\/ auto-precharge: bank(SALP-1), subarray(SALP-2, MASA)$/;" m class:ramulator::SALP::Command +RDA WideIO.h /^ RD, WR, RDA, WRA, $/;" m class:ramulator::WideIO::Command +RDA WideIO2.h /^ RD, WR, RDA, WRA, $/;" m class:ramulator::WideIO2::Command +READ Request.h /^ READ,$/;" m class:ramulator::Request::Type +REF ALDRAM.h /^ REF, PDE, PDX, SRE, SRX,$/;" m class:ramulator::ALDRAM::Command +REF DDR3.h /^ REF, PDE, PDX, SRE, SRX, $/;" m class:ramulator::DDR3::Command +REF DDR4.h /^ REF, PDE, PDX, SRE, SRX, $/;" m class:ramulator::DDR4::Command +REF DSARP.h /^ REF, REFPB, PDE, PDX, SRE, SRX,$/;" m class:ramulator::DSARP::Command +REF GDDR5.h /^ REF, PDE, PDX, SRE, SRX, $/;" m class:ramulator::GDDR5::Command +REF HBM.h /^ REF, REFSB, PDE, PDX, SRE, SRX,$/;" m class:ramulator::HBM::Command +REF LPDDR3.h /^ REF, REFPB, PD, PDX, SREF, SREFX, $/;" m class:ramulator::LPDDR3::Command +REF LPDDR4.h /^ REF, REFPB, PDE, PDX, SREF, SREFX, $/;" m class:ramulator::LPDDR4::Command +REF SALP.h /^ REF, PDE, PDX, SRE, SRX, $/;" m class:ramulator::SALP::Command +REF TLDRAM.h /^ REF, PDE, PDX, SRE, SRX,$/;" m class:ramulator::TLDRAM::Command +REF WideIO.h /^ REF, PD, PDX, SREF, SREFX, $/;" m class:ramulator::WideIO::Command +REF WideIO2.h /^ REF, REFPB, PD, PDX, SREF, SREFX, $/;" m class:ramulator::WideIO2::Command +REFAB DSARP.h /^ REFAB, REFPB, DARP, SARP, DSARP, MAX$/;" m class:ramulator::DSARP::Type +REFPB DSARP.h /^ REF, REFPB, PDE, PDX, SRE, SRX,$/;" m class:ramulator::DSARP::Command +REFPB DSARP.h /^ REFAB, REFPB, DARP, SARP, DSARP, MAX$/;" m class:ramulator::DSARP::Type +REFPB LPDDR3.h /^ REF, REFPB, PD, PDX, SREF, SREFX, $/;" m class:ramulator::LPDDR3::Command +REFPB LPDDR4.h /^ REF, REFPB, PDE, PDX, SREF, SREFX, $/;" m class:ramulator::LPDDR4::Command +REFPB WideIO2.h /^ REF, REFPB, PD, PDX, SREF, SREFX, $/;" m class:ramulator::WideIO2::Command +REFRESH Request.h /^ REFRESH,$/;" m class:ramulator::Request::Type +REFSB HBM.h /^ REF, REFSB, PDE, PDX, SRE, SRX,$/;" m class:ramulator::HBM::Command +Random Memory.h /^ Random,$/;" m class:ramulator::Memory::Translation +Rank ALDRAM.h /^ Channel, Rank, Bank, Row, Column, MAX$/;" m class:ramulator::ALDRAM::Level +Rank DDR3.h /^ Channel, Rank, Bank, Row, Column, MAX$/;" m class:ramulator::DDR3::Level +Rank DDR4.h /^ Channel, Rank, BankGroup, Bank, Row, Column, MAX$/;" m class:ramulator::DDR4::Level +Rank DSARP.h /^ Channel, Rank, Bank, SubArray, Row, Column, MAX$/;" m class:ramulator::DSARP::Level +Rank GDDR5.h /^ Channel, Rank, BankGroup, Bank, Row, Column, MAX$/;" m class:ramulator::GDDR5::Level +Rank HBM.h /^ Channel, Rank, BankGroup, Bank, Row, Column, MAX$/;" m class:ramulator::HBM::Level +Rank LPDDR3.h /^ Channel, Rank, Bank, Row, Column, MAX$/;" m class:ramulator::LPDDR3::Level +Rank LPDDR4.h /^ Channel, Rank, Bank, Row, Column, MAX$/;" m class:ramulator::LPDDR4::Level +Rank SALP.h /^ Channel, Rank, Bank, SubArray, Row, Column, MAX$/;" m class:ramulator::SALP::Level +Rank TLDRAM.h /^ Channel, Rank, Bank, Row, Column, MAX$/;" m class:ramulator::TLDRAM::Level +Rank WideIO.h /^ Channel, Rank, Bank, Row, Column, MAX$/;" m class:ramulator::WideIO::Level +Rank WideIO2.h /^ Channel, Rank, Bank, Row, Column, MAX$/;" m class:ramulator::WideIO2::Level +Refresh Refresh.cpp /^Refresh::Refresh(Controller* ctrl) : ctrl(ctrl) {$/;" f class:ramulator::Refresh +Refresh Refresh.h /^ Refresh(Controller* ctrl) : ctrl(ctrl) {$/;" f class:ramulator::Refresh +Refresh Refresh.h /^class Refresh {$/;" c namespace:ramulator +RefreshMode DDR4.h /^ enum class RefreshMode : int$/;" c class:ramulator::DDR4 +RefreshMode DSARP.h /^ enum class RefreshMode : int$/;" c class:ramulator::DSARP +RefreshMode LPDDR4.h /^ enum class RefreshMode : int$/;" c class:ramulator::LPDDR4 +Refresh_1X DDR4.h /^ Refresh_1X,$/;" m class:ramulator::DDR4::RefreshMode +Refresh_1X DSARP.h /^ Refresh_1X,$/;" m class:ramulator::DSARP::RefreshMode +Refresh_1X LPDDR4.h /^ Refresh_1X,$/;" m class:ramulator::LPDDR4::RefreshMode +Refresh_2X DDR4.h /^ Refresh_2X,$/;" m class:ramulator::DDR4::RefreshMode +Refresh_2X LPDDR4.h /^ Refresh_2X,$/;" m class:ramulator::LPDDR4::RefreshMode +Refresh_4X DDR4.h /^ Refresh_4X,$/;" m class:ramulator::DDR4::RefreshMode +Refresh_4X LPDDR4.h /^ Refresh_4X,$/;" m class:ramulator::LPDDR4::RefreshMode +ReqIter Scheduler.h /^ typedef list::iterator ReqIter;$/;" t class:ramulator::Scheduler +Request Request.h /^ Request()$/;" f class:ramulator::Request +Request Request.h /^ Request(long addr, Type type, function callback, int coreid = 0)$/;" f class:ramulator::Request +Request Request.h /^ Request(long addr, Type type, int coreid = 0)$/;" f class:ramulator::Request +Request Request.h /^ Request(vector& addr_vec, Type type, function callback, int coreid = 0)$/;" f class:ramulator::Request +Request Request.h /^class Request$/;" c namespace:ramulator +Result StatType.h /^typedef double Result;$/;" t namespace:Stats +RoBaRaCoCh Memory.h /^ RoBaRaCoCh,$/;" m class:ramulator::Memory::Type +Row ALDRAM.h /^ Channel, Rank, Bank, Row, Column, MAX$/;" m class:ramulator::ALDRAM::Level +Row DDR3.h /^ Channel, Rank, Bank, Row, Column, MAX$/;" m class:ramulator::DDR3::Level +Row DDR4.h /^ Channel, Rank, BankGroup, Bank, Row, Column, MAX$/;" m class:ramulator::DDR4::Level +Row DSARP.h /^ Channel, Rank, Bank, SubArray, Row, Column, MAX$/;" m class:ramulator::DSARP::Level +Row GDDR5.h /^ Channel, Rank, BankGroup, Bank, Row, Column, MAX$/;" m class:ramulator::GDDR5::Level +Row HBM.h /^ Channel, Rank, BankGroup, Bank, Row, Column, MAX$/;" m class:ramulator::HBM::Level +Row LPDDR3.h /^ Channel, Rank, Bank, Row, Column, MAX$/;" m class:ramulator::LPDDR3::Level +Row LPDDR4.h /^ Channel, Rank, Bank, Row, Column, MAX$/;" m class:ramulator::LPDDR4::Level +Row SALP.h /^ Channel, Rank, Bank, SubArray, Row, Column, MAX$/;" m class:ramulator::SALP::Level +Row TLDRAM.h /^ Channel, Rank, Bank, Row, Column, MAX$/;" m class:ramulator::TLDRAM::Level +Row WideIO.h /^ Channel, Rank, Bank, Row, Column, MAX$/;" m class:ramulator::WideIO::Level +Row WideIO2.h /^ Channel, Rank, Bank, Row, Column, MAX$/;" m class:ramulator::WideIO2::Level +RowPolicy Scheduler.h /^ RowPolicy(Controller* ctrl) : ctrl(ctrl) {}$/;" f class:ramulator::RowPolicy +RowPolicy Scheduler.h /^class RowPolicy$/;" c namespace:ramulator +RowTable Scheduler.h /^ RowTable(Controller* ctrl) : ctrl(ctrl) {}$/;" f class:ramulator::RowTable +RowTable Scheduler.h /^class RowTable$/;" c namespace:ramulator +SALP SALP.cpp /^SALP::SALP(Org org, Speed speed, Type type, int n_sa) :$/;" f class:SALP +SALP SALP.cpp /^SALP::SALP(const string& org_str, const string& speed_str, const string& type_str, int n_sa) :$/;" f class:SALP +SALP SALP.h /^class SALP$/;" c namespace:ramulator +SALP_1 SALP.h /^ SALP_1, SALP_2, MASA, MAX$/;" m class:ramulator::SALP::Type +SALP_1066E SALP.h /^ SALP_1066E, SALP_1066F, SALP_1066G,$/;" m class:ramulator::SALP::Speed +SALP_1066F SALP.h /^ SALP_1066E, SALP_1066F, SALP_1066G,$/;" m class:ramulator::SALP::Speed +SALP_1066G SALP.h /^ SALP_1066E, SALP_1066F, SALP_1066G,$/;" m class:ramulator::SALP::Speed +SALP_1333G SALP.h /^ SALP_1333G, SALP_1333H,$/;" m class:ramulator::SALP::Speed +SALP_1333H SALP.h /^ SALP_1333G, SALP_1333H,$/;" m class:ramulator::SALP::Speed +SALP_1600H SALP.h /^ SALP_1600H, SALP_1600J, SALP_1600K,$/;" m class:ramulator::SALP::Speed +SALP_1600J SALP.h /^ SALP_1600H, SALP_1600J, SALP_1600K,$/;" m class:ramulator::SALP::Speed +SALP_1600K SALP.h /^ SALP_1600H, SALP_1600J, SALP_1600K,$/;" m class:ramulator::SALP::Speed +SALP_1866K SALP.h /^ SALP_1866K, SALP_1866L,$/;" m class:ramulator::SALP::Speed +SALP_1866L SALP.h /^ SALP_1866K, SALP_1866L,$/;" m class:ramulator::SALP::Speed +SALP_1Gb_x16 SALP.h /^ SALP_1Gb_x4, SALP_1Gb_x8, SALP_1Gb_x16,$/;" m class:ramulator::SALP::Org +SALP_1Gb_x4 SALP.h /^ SALP_1Gb_x4, SALP_1Gb_x8, SALP_1Gb_x16,$/;" m class:ramulator::SALP::Org +SALP_1Gb_x8 SALP.h /^ SALP_1Gb_x4, SALP_1Gb_x8, SALP_1Gb_x16,$/;" m class:ramulator::SALP::Org +SALP_2 SALP.h /^ SALP_1, SALP_2, MASA, MAX$/;" m class:ramulator::SALP::Type +SALP_2133L SALP.h /^ SALP_2133L, SALP_2133M,$/;" m class:ramulator::SALP::Speed +SALP_2133M SALP.h /^ SALP_2133L, SALP_2133M,$/;" m class:ramulator::SALP::Speed +SALP_2Gb_x16 SALP.h /^ SALP_2Gb_x4, SALP_2Gb_x8, SALP_2Gb_x16,$/;" m class:ramulator::SALP::Org +SALP_2Gb_x4 SALP.h /^ SALP_2Gb_x4, SALP_2Gb_x8, SALP_2Gb_x16,$/;" m class:ramulator::SALP::Org +SALP_2Gb_x8 SALP.h /^ SALP_2Gb_x4, SALP_2Gb_x8, SALP_2Gb_x16,$/;" m class:ramulator::SALP::Org +SALP_4Gb_x16 SALP.h /^ SALP_4Gb_x4, SALP_4Gb_x8, SALP_4Gb_x16,$/;" m class:ramulator::SALP::Org +SALP_4Gb_x4 SALP.h /^ SALP_4Gb_x4, SALP_4Gb_x8, SALP_4Gb_x16,$/;" m class:ramulator::SALP::Org +SALP_4Gb_x8 SALP.h /^ SALP_4Gb_x4, SALP_4Gb_x8, SALP_4Gb_x16,$/;" m class:ramulator::SALP::Org +SALP_512Mb_x16 SALP.h /^ SALP_512Mb_x4, SALP_512Mb_x8, SALP_512Mb_x16,$/;" m class:ramulator::SALP::Org +SALP_512Mb_x4 SALP.h /^ SALP_512Mb_x4, SALP_512Mb_x8, SALP_512Mb_x16,$/;" m class:ramulator::SALP::Org +SALP_512Mb_x8 SALP.h /^ SALP_512Mb_x4, SALP_512Mb_x8, SALP_512Mb_x16,$/;" m class:ramulator::SALP::Org +SALP_800D SALP.h /^ SALP_800D, SALP_800E,$/;" m class:ramulator::SALP::Speed +SALP_800E SALP.h /^ SALP_800D, SALP_800E,$/;" m class:ramulator::SALP::Speed +SALP_8Gb_x16 SALP.h /^ SALP_8Gb_x4, SALP_8Gb_x8, SALP_8Gb_x16,$/;" m class:ramulator::SALP::Org +SALP_8Gb_x4 SALP.h /^ SALP_8Gb_x4, SALP_8Gb_x8, SALP_8Gb_x16,$/;" m class:ramulator::SALP::Org +SALP_8Gb_x8 SALP.h /^ SALP_8Gb_x4, SALP_8Gb_x8, SALP_8Gb_x16,$/;" m class:ramulator::SALP::Org +SARP DSARP.h /^ REFAB, REFPB, DARP, SARP, DSARP, MAX$/;" m class:ramulator::DSARP::Type +SASEL SALP.h /^ ACT, SASEL, PRE, PRER, \/\/ precharge bank\/bank\/rank(SALP-1), subarray\/bank\/rank(SALP-2, MASA)$/;" m class:ramulator::SALP::Command +SELFREFRESH Request.h /^ SELFREFRESH,$/;" m class:ramulator::Request::Type +SRE ALDRAM.h /^ REF, PDE, PDX, SRE, SRX,$/;" m class:ramulator::ALDRAM::Command +SRE DDR3.h /^ REF, PDE, PDX, SRE, SRX, $/;" m class:ramulator::DDR3::Command +SRE DDR4.h /^ REF, PDE, PDX, SRE, SRX, $/;" m class:ramulator::DDR4::Command +SRE DSARP.h /^ REF, REFPB, PDE, PDX, SRE, SRX,$/;" m class:ramulator::DSARP::Command +SRE GDDR5.h /^ REF, PDE, PDX, SRE, SRX, $/;" m class:ramulator::GDDR5::Command +SRE HBM.h /^ REF, REFSB, PDE, PDX, SRE, SRX,$/;" m class:ramulator::HBM::Command +SRE SALP.h /^ REF, PDE, PDX, SRE, SRX, $/;" m class:ramulator::SALP::Command +SRE TLDRAM.h /^ REF, PDE, PDX, SRE, SRX,$/;" m class:ramulator::TLDRAM::Command +SREF LPDDR3.h /^ REF, REFPB, PD, PDX, SREF, SREFX, $/;" m class:ramulator::LPDDR3::Command +SREF LPDDR4.h /^ REF, REFPB, PDE, PDX, SREF, SREFX, $/;" m class:ramulator::LPDDR4::Command +SREF WideIO.h /^ REF, PD, PDX, SREF, SREFX, $/;" m class:ramulator::WideIO::Command +SREF WideIO2.h /^ REF, REFPB, PD, PDX, SREF, SREFX, $/;" m class:ramulator::WideIO2::Command +SREFX LPDDR3.h /^ REF, REFPB, PD, PDX, SREF, SREFX, $/;" m class:ramulator::LPDDR3::Command +SREFX LPDDR4.h /^ REF, REFPB, PDE, PDX, SREF, SREFX, $/;" m class:ramulator::LPDDR4::Command +SREFX WideIO.h /^ REF, PD, PDX, SREF, SREFX, $/;" m class:ramulator::WideIO::Command +SREFX WideIO2.h /^ REF, REFPB, PD, PDX, SREF, SREFX, $/;" m class:ramulator::WideIO2::Command +SRX ALDRAM.h /^ REF, PDE, PDX, SRE, SRX,$/;" m class:ramulator::ALDRAM::Command +SRX DDR3.h /^ REF, PDE, PDX, SRE, SRX, $/;" m class:ramulator::DDR3::Command +SRX DDR4.h /^ REF, PDE, PDX, SRE, SRX, $/;" m class:ramulator::DDR4::Command +SRX DSARP.h /^ REF, REFPB, PDE, PDX, SRE, SRX,$/;" m class:ramulator::DSARP::Command +SRX GDDR5.h /^ REF, PDE, PDX, SRE, SRX, $/;" m class:ramulator::GDDR5::Command +SRX HBM.h /^ REF, REFSB, PDE, PDX, SRE, SRX,$/;" m class:ramulator::HBM::Command +SRX SALP.h /^ REF, PDE, PDX, SRE, SRX, $/;" m class:ramulator::SALP::Command +SRX TLDRAM.h /^ REF, PDE, PDX, SRE, SRX,$/;" m class:ramulator::TLDRAM::Command +Scalar StatType.h /^ Scalar():_value(0) {}$/;" f class:Stats::Scalar +Scalar StatType.h /^class Scalar: public ScalarBase {$/;" c namespace:Stats +ScalarBase StatType.h /^class ScalarBase: public Stat {$/;" c namespace:Stats +ScalarStat Statistics.h /^class ScalarStat : public ScalarStatBase {$/;" c namespace:ramulator +ScalarStatBase Statistics.h /^class ScalarStatBase : public StatBase { \/\/ wrapper for Stats::ScalarBase$/;" c namespace:ramulator +Scheduler Scheduler.h /^ Scheduler(Controller* ctrl) : ctrl(ctrl) {}$/;" f class:ramulator::Scheduler +Scheduler Scheduler.h /^class Scheduler$/;" c namespace:ramulator +Selected SALP.h /^ Opened, Closed, Selected, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::SALP::State +SelfRefresh ALDRAM.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::ALDRAM::State +SelfRefresh DDR3.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::DDR3::State +SelfRefresh DDR4.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::DDR4::State +SelfRefresh DSARP.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::DSARP::State +SelfRefresh GDDR5.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::GDDR5::State +SelfRefresh HBM.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::HBM::State +SelfRefresh LPDDR3.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::LPDDR3::State +SelfRefresh LPDDR4.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::LPDDR4::State +SelfRefresh SALP.h /^ Opened, Closed, Selected, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::SALP::State +SelfRefresh TLDRAM.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::TLDRAM::State +SelfRefresh WideIO.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::WideIO::State +SelfRefresh WideIO2.h /^ Opened, Closed, PowerUp, ActPowerDown, PrePowerDown, SelfRefresh, MAX$/;" m class:ramulator::WideIO2::State +Speed ALDRAM.h /^ enum class Speed : int$/;" c class:ramulator::ALDRAM +Speed DDR3.h /^ enum class Speed : int$/;" c class:ramulator::DDR3 +Speed DDR4.h /^ enum class Speed : int$/;" c class:ramulator::DDR4 +Speed DSARP.h /^ enum class Speed : int$/;" c class:ramulator::DSARP +Speed GDDR5.h /^ enum class Speed : int$/;" c class:ramulator::GDDR5 +Speed HBM.h /^ enum class Speed : int$/;" c class:ramulator::HBM +Speed LPDDR3.h /^ enum class Speed : int$/;" c class:ramulator::LPDDR3 +Speed LPDDR4.h /^ enum class Speed : int$/;" c class:ramulator::LPDDR4 +Speed SALP.h /^ enum class Speed : int$/;" c class:ramulator::SALP +Speed TLDRAM.h /^ enum class Speed : int$/;" c class:ramulator::TLDRAM +Speed WideIO.h /^ enum class Speed : int$/;" c class:ramulator::WideIO +Speed WideIO2.h /^ enum class Speed : int$/;" c class:ramulator::WideIO2 +SpeedEntry ALDRAM.h /^ struct SpeedEntry {$/;" s class:ramulator::ALDRAM +SpeedEntry DDR3.h /^ struct SpeedEntry {$/;" s class:ramulator::DDR3 +SpeedEntry DDR4.h /^ struct SpeedEntry {$/;" s class:ramulator::DDR4 +SpeedEntry DSARP.h /^ struct SpeedEntry {$/;" s class:ramulator::DSARP +SpeedEntry GDDR5.h /^ struct SpeedEntry {$/;" s class:ramulator::GDDR5 +SpeedEntry HBM.h /^ struct SpeedEntry {$/;" s class:ramulator::HBM +SpeedEntry LPDDR3.h /^ struct SpeedEntry {$/;" s class:ramulator::LPDDR3 +SpeedEntry LPDDR4.h /^ struct SpeedEntry {$/;" s class:ramulator::LPDDR4 +SpeedEntry SALP.h /^ struct SpeedEntry {$/;" s class:ramulator::SALP +SpeedEntry TLDRAM.h /^ struct SpeedEntry {$/;" s class:ramulator::TLDRAM +SpeedEntry WideIO.h /^ struct SpeedEntry {$/;" s class:ramulator::WideIO +SpeedEntry WideIO2.h /^ struct SpeedEntry {$/;" s class:ramulator::WideIO2 +SpeedyController SpeedyController.h /^ SpeedyController(const Config& configs, DRAM* channel) :$/;" f class:ramulator::SpeedyController +SpeedyController SpeedyController.h /^class SpeedyController$/;" c namespace:ramulator +StandardDeviation StatType.h /^ StandardDeviation():sum(Counter()), squares(Counter()),$/;" f class:Stats::StandardDeviation +StandardDeviation StatType.h /^class StandardDeviation: public Stat {$/;" c namespace:Stats +StandardDeviationStat Statistics.h /^class StandardDeviationStat : public DistStatBase {$/;" c namespace:ramulator +Stat StatType.h /^ Stat() {$/;" f class:Stats::Stat +Stat StatType.h /^class Stat : public StatBase {$/;" c namespace:Stats +StatBase StatType.h /^class StatBase {$/;" c namespace:Stats +StatBase Statistics.h /^ StatBase() {}$/;" f class:ramulator::StatBase +StatBase Statistics.h /^ StatBase(std::string _name) {$/;" f class:ramulator::StatBase +StatBase Statistics.h /^ StatBase(std::string _name, std::string _desc) {$/;" f class:ramulator::StatBase +StatBase Statistics.h /^class StatBase { \/\/ wrapper for Stats::DataWrap$/;" c namespace:ramulator +StatBaseVec Statistics.h /^class StatBaseVec : public StatBase { \/\/ wrapper for Stats::DataWrapVec$/;" c namespace:ramulator +StatList StatType.h /^class StatList {$/;" c namespace:Stats +State ALDRAM.h /^ enum class State : int$/;" c class:ramulator::ALDRAM +State DDR3.h /^ enum class State : int$/;" c class:ramulator::DDR3 +State DDR4.h /^ enum class State : int$/;" c class:ramulator::DDR4 +State DSARP.h /^ enum class State : int$/;" c class:ramulator::DSARP +State GDDR5.h /^ enum class State : int$/;" c class:ramulator::GDDR5 +State HBM.h /^ enum class State : int$/;" c class:ramulator::HBM +State LPDDR3.h /^ enum class State : int$/;" c class:ramulator::LPDDR3 +State LPDDR4.h /^ enum class State : int$/;" c class:ramulator::LPDDR4 +State SALP.h /^ enum class State : int$/;" c class:ramulator::SALP +State TLDRAM.h /^ enum class State : int$/;" c class:ramulator::TLDRAM +State WideIO.h /^ enum class State : int$/;" c class:ramulator::WideIO +State WideIO2.h /^ enum class State : int$/;" c class:ramulator::WideIO2 +Stats StatType.cpp /^namespace Stats {$/;" n file: +Stats StatType.h /^namespace Stats {$/;" n +SubArray DSARP.h /^ Channel, Rank, Bank, SubArray, Row, Column, MAX$/;" m class:ramulator::DSARP::Level +SubArray SALP.h /^ Channel, Rank, Bank, SubArray, Row, Column, MAX$/;" m class:ramulator::SALP::Level +TLDRAM TLDRAM.cpp /^TLDRAM::TLDRAM(Org org, Speed speed, int segment_ratio) :$/;" f class:TLDRAM +TLDRAM TLDRAM.cpp /^TLDRAM::TLDRAM(const string& org_str, const string& speed_str, int segment_ratio) :$/;" f class:TLDRAM +TLDRAM TLDRAM.h /^class TLDRAM$/;" c namespace:ramulator +TLDRAM_1066E TLDRAM.h /^ TLDRAM_1066E, TLDRAM_1066F, TLDRAM_1066G,$/;" m class:ramulator::TLDRAM::Speed +TLDRAM_1066F TLDRAM.h /^ TLDRAM_1066E, TLDRAM_1066F, TLDRAM_1066G,$/;" m class:ramulator::TLDRAM::Speed +TLDRAM_1066G TLDRAM.h /^ TLDRAM_1066E, TLDRAM_1066F, TLDRAM_1066G,$/;" m class:ramulator::TLDRAM::Speed +TLDRAM_1333G TLDRAM.h /^ TLDRAM_1333G, TLDRAM_1333H,$/;" m class:ramulator::TLDRAM::Speed +TLDRAM_1333H TLDRAM.h /^ TLDRAM_1333G, TLDRAM_1333H,$/;" m class:ramulator::TLDRAM::Speed +TLDRAM_1600H TLDRAM.h /^ TLDRAM_1600H, TLDRAM_1600J, TLDRAM_1600K,$/;" m class:ramulator::TLDRAM::Speed +TLDRAM_1600J TLDRAM.h /^ TLDRAM_1600H, TLDRAM_1600J, TLDRAM_1600K,$/;" m class:ramulator::TLDRAM::Speed +TLDRAM_1600K TLDRAM.h /^ TLDRAM_1600H, TLDRAM_1600J, TLDRAM_1600K,$/;" m class:ramulator::TLDRAM::Speed +TLDRAM_1866K TLDRAM.h /^ TLDRAM_1866K, TLDRAM_1866L,$/;" m class:ramulator::TLDRAM::Speed +TLDRAM_1866L TLDRAM.h /^ TLDRAM_1866K, TLDRAM_1866L,$/;" m class:ramulator::TLDRAM::Speed +TLDRAM_1Gb_x16 TLDRAM.h /^ TLDRAM_1Gb_x4, TLDRAM_1Gb_x8, TLDRAM_1Gb_x16,$/;" m class:ramulator::TLDRAM::Org +TLDRAM_1Gb_x4 TLDRAM.h /^ TLDRAM_1Gb_x4, TLDRAM_1Gb_x8, TLDRAM_1Gb_x16,$/;" m class:ramulator::TLDRAM::Org +TLDRAM_1Gb_x8 TLDRAM.h /^ TLDRAM_1Gb_x4, TLDRAM_1Gb_x8, TLDRAM_1Gb_x16,$/;" m class:ramulator::TLDRAM::Org +TLDRAM_2133L TLDRAM.h /^ TLDRAM_2133L, TLDRAM_2133M,$/;" m class:ramulator::TLDRAM::Speed +TLDRAM_2133M TLDRAM.h /^ TLDRAM_2133L, TLDRAM_2133M,$/;" m class:ramulator::TLDRAM::Speed +TLDRAM_2Gb_x16 TLDRAM.h /^ TLDRAM_2Gb_x4, TLDRAM_2Gb_x8, TLDRAM_2Gb_x16,$/;" m class:ramulator::TLDRAM::Org +TLDRAM_2Gb_x4 TLDRAM.h /^ TLDRAM_2Gb_x4, TLDRAM_2Gb_x8, TLDRAM_2Gb_x16,$/;" m class:ramulator::TLDRAM::Org +TLDRAM_2Gb_x8 TLDRAM.h /^ TLDRAM_2Gb_x4, TLDRAM_2Gb_x8, TLDRAM_2Gb_x16,$/;" m class:ramulator::TLDRAM::Org +TLDRAM_4Gb_x16 TLDRAM.h /^ TLDRAM_4Gb_x4, TLDRAM_4Gb_x8, TLDRAM_4Gb_x16,$/;" m class:ramulator::TLDRAM::Org +TLDRAM_4Gb_x4 TLDRAM.h /^ TLDRAM_4Gb_x4, TLDRAM_4Gb_x8, TLDRAM_4Gb_x16,$/;" m class:ramulator::TLDRAM::Org +TLDRAM_4Gb_x8 TLDRAM.h /^ TLDRAM_4Gb_x4, TLDRAM_4Gb_x8, TLDRAM_4Gb_x16,$/;" m class:ramulator::TLDRAM::Org +TLDRAM_512Mb_x16 TLDRAM.h /^ TLDRAM_512Mb_x4, TLDRAM_512Mb_x8, TLDRAM_512Mb_x16,$/;" m class:ramulator::TLDRAM::Org +TLDRAM_512Mb_x4 TLDRAM.h /^ TLDRAM_512Mb_x4, TLDRAM_512Mb_x8, TLDRAM_512Mb_x16,$/;" m class:ramulator::TLDRAM::Org +TLDRAM_512Mb_x8 TLDRAM.h /^ TLDRAM_512Mb_x4, TLDRAM_512Mb_x8, TLDRAM_512Mb_x16,$/;" m class:ramulator::TLDRAM::Org +TLDRAM_800D TLDRAM.h /^ TLDRAM_800D, TLDRAM_800E,$/;" m class:ramulator::TLDRAM::Speed +TLDRAM_800E TLDRAM.h /^ TLDRAM_800D, TLDRAM_800E,$/;" m class:ramulator::TLDRAM::Speed +TLDRAM_8Gb_x16 TLDRAM.h /^ TLDRAM_8Gb_x4, TLDRAM_8Gb_x8, TLDRAM_8Gb_x16,$/;" m class:ramulator::TLDRAM::Org +TLDRAM_8Gb_x4 TLDRAM.h /^ TLDRAM_8Gb_x4, TLDRAM_8Gb_x8, TLDRAM_8Gb_x16,$/;" m class:ramulator::TLDRAM::Org +TLDRAM_8Gb_x8 TLDRAM.h /^ TLDRAM_8Gb_x4, TLDRAM_8Gb_x8, TLDRAM_8Gb_x16,$/;" m class:ramulator::TLDRAM::Org +Temp ALDRAM.h /^ enum class Temp : int$/;" c class:ramulator::ALDRAM +Tick StatType.h /^typedef uint64_t Tick;$/;" t namespace:Stats +Timeout Scheduler.h /^ Closed, Opened, Timeout, MAX$/;" m class:ramulator::RowPolicy::Type +TimingEntry ALDRAM.h /^ struct TimingEntry$/;" s class:ramulator::ALDRAM +TimingEntry DDR3.h /^ struct TimingEntry$/;" s class:ramulator::DDR3 +TimingEntry DDR4.h /^ struct TimingEntry$/;" s class:ramulator::DDR4 +TimingEntry DSARP.h /^ struct TimingEntry$/;" s class:ramulator::DSARP +TimingEntry GDDR5.h /^ struct TimingEntry$/;" s class:ramulator::GDDR5 +TimingEntry HBM.h /^ struct TimingEntry$/;" s class:ramulator::HBM +TimingEntry LPDDR3.h /^ struct TimingEntry$/;" s class:ramulator::LPDDR3 +TimingEntry LPDDR4.h /^ struct TimingEntry$/;" s class:ramulator::LPDDR4 +TimingEntry SALP.h /^ struct TimingEntry$/;" s class:ramulator::SALP +TimingEntry TLDRAM.h /^ struct TimingEntry$/;" s class:ramulator::TLDRAM +TimingEntry WideIO.h /^ struct TimingEntry$/;" s class:ramulator::WideIO +TimingEntry WideIO2.h /^ struct TimingEntry$/;" s class:ramulator::WideIO2 +Trace Processor.cpp /^Trace::Trace(const char* trace_fname) : file(trace_fname), trace_name(trace_fname)$/;" f class:Trace +Trace Processor.h /^class Trace {$/;" c namespace:ramulator +Translation Memory.h /^ enum class Translation {$/;" c class:ramulator::Memory +Type DSARP.h /^ enum class Type : int$/;" c class:ramulator::DSARP +Type Memory.h /^ enum class Type {$/;" c class:ramulator::Memory +Type Request.h /^ enum class Type$/;" c class:ramulator::Request +Type SALP.h /^ enum class Type : int$/;" c class:ramulator::SALP +Type Scheduler.h /^ enum class Type {$/;" c class:ramulator::RowPolicy +Type Scheduler.h /^ enum class Type {$/;" c class:ramulator::Scheduler +VCounter StatType.h /^typedef std::vector VCounter;$/;" t namespace:Stats +VResult StatType.h /^typedef std::vector VResult;$/;" t namespace:Stats +Vector StatType.h /^class Vector: public VectorBase {$/;" c namespace:Stats +VectorBase StatType.h /^class VectorBase: public Stat {$/;" c namespace:Stats +VectorStat Statistics.h /^class VectorStat : public VectorStatBase {$/;" c namespace:ramulator +VectorStatBase Statistics.h /^class VectorStatBase : public StatBaseVec { \/\/ wrapper for Stats::VectorBase$/;" c namespace:ramulator +WR ALDRAM.h /^ RD, WR, RDA, WRA,$/;" m class:ramulator::ALDRAM::Command +WR DDR3.h /^ RD, WR, RDA, WRA, $/;" m class:ramulator::DDR3::Command +WR DDR4.h /^ RD, WR, RDA, WRA, $/;" m class:ramulator::DDR4::Command +WR DSARP.h /^ RD, WR, RDA, WRA,$/;" m class:ramulator::DSARP::Command +WR GDDR5.h /^ RD, WR, RDA, WRA, $/;" m class:ramulator::GDDR5::Command +WR HBM.h /^ RD, WR, RDA, WRA,$/;" m class:ramulator::HBM::Command +WR LPDDR3.h /^ RD, WR, RDA, WRA, $/;" m class:ramulator::LPDDR3::Command +WR LPDDR4.h /^ RD, WR, RDA, WRA, $/;" m class:ramulator::LPDDR4::Command +WR SALP.h /^ RD, WR, RDA, WRA, \/\/ auto-precharge: bank(SALP-1), subarray(SALP-2, MASA)$/;" m class:ramulator::SALP::Command +WR TLDRAM.h /^ RD, WR,$/;" m class:ramulator::TLDRAM::Command +WR WideIO.h /^ RD, WR, RDA, WRA, $/;" m class:ramulator::WideIO::Command +WR WideIO2.h /^ RD, WR, RDA, WRA, $/;" m class:ramulator::WideIO2::Command +WRA ALDRAM.h /^ RD, WR, RDA, WRA,$/;" m class:ramulator::ALDRAM::Command +WRA DDR3.h /^ RD, WR, RDA, WRA, $/;" m class:ramulator::DDR3::Command +WRA DDR4.h /^ RD, WR, RDA, WRA, $/;" m class:ramulator::DDR4::Command +WRA DSARP.h /^ RD, WR, RDA, WRA,$/;" m class:ramulator::DSARP::Command +WRA GDDR5.h /^ RD, WR, RDA, WRA, $/;" m class:ramulator::GDDR5::Command +WRA HBM.h /^ RD, WR, RDA, WRA,$/;" m class:ramulator::HBM::Command +WRA LPDDR3.h /^ RD, WR, RDA, WRA, $/;" m class:ramulator::LPDDR3::Command +WRA LPDDR4.h /^ RD, WR, RDA, WRA, $/;" m class:ramulator::LPDDR4::Command +WRA SALP.h /^ RD, WR, RDA, WRA, \/\/ auto-precharge: bank(SALP-1), subarray(SALP-2, MASA)$/;" m class:ramulator::SALP::Command +WRA WideIO.h /^ RD, WR, RDA, WRA, $/;" m class:ramulator::WideIO::Command +WRA WideIO2.h /^ RD, WR, RDA, WRA, $/;" m class:ramulator::WideIO2::Command +WRITE Request.h /^ WRITE,$/;" m class:ramulator::Request::Type +WideIO WideIO.cpp /^WideIO::WideIO(Org org, Speed speed) : $/;" f class:WideIO +WideIO WideIO.cpp /^WideIO::WideIO(const string& org_str, const string& speed_str) :$/;" f class:WideIO +WideIO WideIO.h /^class WideIO$/;" c namespace:ramulator +WideIO2 WideIO2.cpp /^WideIO2::WideIO2(Org org, Speed speed, int channels) : $/;" f class:WideIO2 +WideIO2 WideIO2.cpp /^WideIO2::WideIO2(const string& org_str, const string& speed_str, int channels) :$/;" f class:WideIO2 +WideIO2 WideIO2.h /^class WideIO2$/;" c namespace:ramulator +WideIO2_1066 WideIO2.h /^ WideIO2_1066,$/;" m class:ramulator::WideIO2::Speed +WideIO2_800 WideIO2.h /^ WideIO2_800,$/;" m class:ramulator::WideIO2::Speed +WideIO2_8Gb WideIO2.h /^ WideIO2_8Gb,$/;" m class:ramulator::WideIO2::Org +WideIO_1Gb WideIO.h /^ WideIO_1Gb,$/;" m class:ramulator::WideIO::Org +WideIO_200 WideIO.h /^ WideIO_200,$/;" m class:ramulator::WideIO::Speed +WideIO_266 WideIO.h /^ WideIO_266,$/;" m class:ramulator::WideIO::Speed +WideIO_2Gb WideIO.h /^ WideIO_2Gb,$/;" m class:ramulator::WideIO::Org +WideIO_4Gb WideIO.h /^ WideIO_4Gb,$/;" m class:ramulator::WideIO::Org +WideIO_8Gb WideIO.h /^ WideIO_8Gb,$/;" m class:ramulator::WideIO::Org +Window Processor.h /^ Window() : ready_list(depth), addr_list(depth, -1) {}$/;" f class:ramulator::Window +Window Processor.h /^class Window {$/;" c namespace:ramulator +__ALDRAM_H ALDRAM.h 2;" d +__CACHE_H Cache.h 2;" d +__COMMON_H__ common.h 2;" d +__CONFIG_H Config.h 2;" d +__CONTROLLER_H Controller.h 2;" d +__DDR3_H DDR3.h 2;" d +__DDR4_H DDR4.h 2;" d +__DRAM_H DRAM.h 2;" d +__GDDR5_H GDDR5.h 2;" d +__GEM5_WRAPPER_H Gem5Wrapper.h 2;" d +__HBM_H HBM.h 2;" d +__LPDDR3_H LPDDR3.h 2;" d +__LPDDR4_H LPDDR4.h 2;" d +__MEMORY_FACTORY_H MemoryFactory.h 2;" d +__MEMORY_H Memory.h 2;" d +__MEM_WRAPPER_H__ MemWrapper.h 2;" d +__PE_H__ pe.h 2;" d +__PROCESSOR_H Processor.h 2;" d +__REFRESH_H_ Refresh.h 17;" d +__REQUEST_H Request.h 2;" d +__SALP_H SALP.h 2;" d +__SCHEDULER_H Scheduler.h 2;" d +__SPEEDYCONTROLLER_H SpeedyController.h 2;" d +__STATISTICS_H Statistics.h 2;" d +__STATTYPE_H StatType.h 2;" d +__TLDRAM_H TLDRAM.h 2;" d +__WIDEIO2_H WideIO2.h 2;" d +__WIDEIO_H WideIO.h 2;" d +_desc StatType.h /^ std::string _desc;$/;" m class:Stats::Stat +_flags StatType.h /^ Flags _flags = display;$/;" m class:Stats::Stat +_name StatType.h /^ std::string _name;$/;" m class:Stats::Stat +_precision StatType.h /^ int _precision = 1;$/;" m class:Stats::Stat +_size StatType.h /^ size_type _size = 0;$/;" m class:Stats::VectorBase +_value StatType.h /^ Counter _value;$/;" m class:Stats::ConstValue +_value StatType.h /^ Counter _value;$/;" m class:Stats::Scalar +active_cycles DRAM.h /^ ScalarStat active_cycles;$/;" m class:ramulator::DRAM +active_refresh_overlap_cycles DRAM.h /^ ScalarStat active_refresh_overlap_cycles;$/;" m class:ramulator::DRAM +add Config.h /^ void add (const std::string& name, const std::string& value) {$/;" f class:ramulator::Config +add StatType.cpp /^Histogram::add(Histogram &hs)$/;" f class:Stats::Histogram +add StatType.h /^ void add(AverageDeviation& ad) {$/;" f class:Stats::AverageDeviation +add StatType.h /^ void add(Distribution &d) {$/;" f class:Stats::Distribution +add StatType.h /^ void add(StandardDeviation& sd) {$/;" f class:Stats::StandardDeviation +add StatType.h /^ void add(StatBase* stat) {$/;" f class:Stats::StatList +add Statistics.h /^ void add(DistStatBase & d) { StatBase::stat.add(d.StatBase::stat); }$/;" f class:ramulator::DistStatBase +addr Cache.h /^ long addr;$/;" m struct:ramulator::Cache::Line +addr Request.h /^ long addr;$/;" m class:ramulator::Request +addr common.h /^ long addr; \/\/ Starting address of the memory operation$/;" m struct:MemOp +addr_bits Memory.h /^ vector addr_bits;$/;" m class:ramulator::Memory +addr_list Processor.h /^ std::vector addr_list;$/;" m class:ramulator::Window +addr_vec Request.h /^ vector addr_vec;$/;" m class:ramulator::Request +aldram_timing ALDRAM.cpp /^void ALDRAM::aldram_timing(Temp current_temperature)$/;" f class:ALDRAM +align Cache.h /^ long align(long addr) {$/;" f class:ramulator::Cache +all_sets_locked Cache.h /^ bool all_sets_locked(const std::list& lines) {$/;" f class:ramulator::Cache +allocate_line Cache.cpp /^std::list::iterator Cache::allocate_line($/;" f class:ramulator::Cache +arrive Request.h /^ long arrive = -1;$/;" m class:ramulator::Request +arriveMemTime Request.h /^ long arriveMemTime;$/;" m class:ramulator::Request +arriveMemTime common.h /^ long arriveMemTime;$/;" m struct:MemOp +arrivePeTime Request.h /^ long arrivePeTime;$/;" m class:ramulator::Request +arrivePeTime common.h /^ long arrivePeTime;$/;" m struct:MemOp +assoc Cache.h /^ unsigned int assoc;$/;" m class:ramulator::Cache +average_serving_requests DRAM.h /^ ScalarStat average_serving_requests;$/;" m class:ramulator::DRAM +b_ref_rank DSARP.h /^ bool b_ref_rank;$/;" m class:ramulator::DSARP +backlog_early_pull_threshold Refresh.h /^ int backlog_early_pull_threshold = -6;$/;" m class:ramulator::Refresh +backlog_max Refresh.h /^ int backlog_max = 8;$/;" m class:ramulator::Refresh +backlog_min Refresh.h /^ int backlog_min = -8;$/;" m class:ramulator::Refresh +bank_ref_counters Refresh.h /^ vector bank_ref_counters;$/;" m class:ramulator::Refresh +bank_refresh_backlog Refresh.h /^ vector*> bank_refresh_backlog;$/;" m class:ramulator::Refresh +begin_of_cur_reqcnt DRAM.h /^ long begin_of_cur_reqcnt = -1;$/;" m class:ramulator::DRAM +begin_of_refreshing DRAM.h /^ long begin_of_refreshing = -1;$/;" m class:ramulator::DRAM +begin_of_serving DRAM.h /^ long begin_of_serving = -1;$/;" m class:ramulator::DRAM +block_num Cache.h /^ unsigned int block_num;$/;" m class:ramulator::Cache +block_size Cache.h /^ unsigned int block_size;$/;" m class:ramulator::Cache +bubble_cnt Processor.h /^ long bubble_cnt;$/;" m class:ramulator::Core +bucket_size StatType.h /^ Counter bucket_size;$/;" m class:Stats::Distribution +bucket_size StatType.h /^ Counter bucket_size;$/;" m class:Stats::Histogram +busy_cycles DRAM.h /^ ScalarStat busy_cycles;$/;" m class:ramulator::DRAM +cache_eviction Cache.h /^ ScalarStat cache_eviction;$/;" m class:ramulator::Cache +cache_lines Cache.h /^ std::map > cache_lines;$/;" m class:ramulator::Cache +cache_mshr_hit Cache.h /^ ScalarStat cache_mshr_hit;$/;" m class:ramulator::Cache +cache_mshr_unavailable Cache.h /^ ScalarStat cache_mshr_unavailable;$/;" m class:ramulator::Cache +cache_read_access Cache.h /^ ScalarStat cache_read_access;$/;" m class:ramulator::Cache +cache_read_miss Cache.h /^ ScalarStat cache_read_miss;$/;" m class:ramulator::Cache +cache_set_unavailable Cache.h /^ ScalarStat cache_set_unavailable;$/;" m class:ramulator::Cache +cache_total_access Cache.h /^ ScalarStat cache_total_access;$/;" m class:ramulator::Cache +cache_total_miss Cache.h /^ ScalarStat cache_total_miss;$/;" m class:ramulator::Cache +cache_write_access Cache.h /^ ScalarStat cache_write_access;$/;" m class:ramulator::Cache +cache_write_miss Cache.h /^ ScalarStat cache_write_miss;$/;" m class:ramulator::Cache +caches Processor.h /^ std::vector> caches;$/;" m class:ramulator::Core +cachesys Cache.h /^ std::shared_ptr cachesys;$/;" m class:ramulator::Cache +cachesys Processor.h /^ std::shared_ptr cachesys;$/;" m class:ramulator::Processor +calc_ipc Processor.cpp /^double Core::calc_ipc()$/;" f class:Core +calc_log2 Cache.h /^ int calc_log2(int val) {$/;" f class:ramulator::Cache +calc_log2 Memory.h /^ int calc_log2(int val){$/;" f class:ramulator::Memory +calc_weighted_speedup Config.h /^ bool calc_weighted_speedup() const {$/;" f class:ramulator::Config +callback Cache.cpp /^void Cache::callback(Request& req) {$/;" f class:ramulator::Cache +callback Processor.h /^ function callback;$/;" m class:ramulator::Core +callback Request.h /^ function callback; \/\/ call back with more info$/;" m class:ramulator::Request +cap Scheduler.h /^ long cap = 16;$/;" m class:ramulator::Scheduler +cdf StatType.h /^const uint16_t cdf = 0x00000040;$/;" m namespace:Stats +channel Controller.h /^ DRAM* channel;$/;" m class:ramulator::Controller +channel SpeedyController.h /^ DRAM* channel;$/;" m class:ramulator::SpeedyController +channel_width ALDRAM.h /^ int channel_width = 64;$/;" m class:ramulator::ALDRAM +channel_width DDR3.h /^ int channel_width = 64;$/;" m class:ramulator::DDR3 +channel_width DDR4.h /^ int channel_width = 64;$/;" m class:ramulator::DDR4 +channel_width DSARP.h /^ int channel_width = 32;$/;" m class:ramulator::DSARP +channel_width GDDR5.h /^ int channel_width = 64;$/;" m class:ramulator::GDDR5 +channel_width HBM.h /^ int channel_width = 128;$/;" m class:ramulator::HBM +channel_width LPDDR3.h /^ int channel_width = 64;$/;" m class:ramulator::LPDDR3 +channel_width LPDDR4.h /^ int channel_width = 32;$/;" m class:ramulator::LPDDR4 +channel_width SALP.h /^ int channel_width = 64;$/;" m class:ramulator::SALP +channel_width TLDRAM.h /^ int channel_width = 64;$/;" m class:ramulator::TLDRAM +channel_width WideIO.h /^ int channel_width = 128;$/;" m class:ramulator::WideIO +channel_width WideIO2.h /^ int channel_width = 64;$/;" m class:ramulator::WideIO2 +channels Config.h /^ int channels;$/;" m class:ramulator::Config +check DRAM.h /^bool DRAM::check(typename T::Command cmd, const int* addr, long clk)$/;" f class:ramulator::DRAM +check StatType.h /^ bool check() const {$/;" f class:Stats::VectorBase +check Statistics.h /^ bool check(void) const { return StatBase::stat.check(); }$/;" f class:ramulator::VectorStatBase +check_row_hit DRAM.h /^bool DRAM::check_row_hit(typename T::Command cmd, const int* addr)$/;" f class:ramulator::DRAM +check_row_open DRAM.h /^bool DRAM::check_row_open(typename T::Command cmd, const int* addr)$/;" f class:ramulator::DRAM +check_unlock Cache.h /^ bool check_unlock(long addr) {$/;" f class:ramulator::Cache +children DRAM.h /^ vector children;$/;" m class:ramulator::DRAM +clear_lower_bits Memory.h /^ void clear_lower_bits(long& addr, int bits)$/;" f class:ramulator::Memory +clk Cache.h /^ long clk = 0;$/;" m class:ramulator::CacheSystem +clk Controller.h /^ long clk = 0;$/;" m class:ramulator::Controller +clk Processor.h /^ long clk = 0;$/;" m class:ramulator::Core +clk Refresh.h /^ long clk, refreshed;$/;" m class:ramulator::Refresh +clk SpeedyController.h /^ long clk = 0;$/;" m class:ramulator::SpeedyController +clk_ns Memory.h /^ double clk_ns()$/;" f class:ramulator::Memory +cmd ALDRAM.h /^ Command cmd;$/;" m struct:ramulator::ALDRAM::TimingEntry +cmd DDR3.h /^ Command cmd;$/;" m struct:ramulator::DDR3::TimingEntry +cmd DDR4.h /^ Command cmd;$/;" m struct:ramulator::DDR4::TimingEntry +cmd DSARP.h /^ Command cmd;$/;" m struct:ramulator::DSARP::TimingEntry +cmd GDDR5.h /^ Command cmd;$/;" m struct:ramulator::GDDR5::TimingEntry +cmd HBM.h /^ Command cmd;$/;" m struct:ramulator::HBM::TimingEntry +cmd LPDDR3.h /^ Command cmd;$/;" m struct:ramulator::LPDDR3::TimingEntry +cmd LPDDR4.h /^ Command cmd;$/;" m struct:ramulator::LPDDR4::TimingEntry +cmd SALP.h /^ Command cmd;$/;" m struct:ramulator::SALP::TimingEntry +cmd TLDRAM.h /^ Command cmd;$/;" m struct:ramulator::TLDRAM::TimingEntry +cmd WideIO.h /^ Command cmd;$/;" m struct:ramulator::WideIO::TimingEntry +cmd WideIO2.h /^ Command cmd;$/;" m struct:ramulator::WideIO2::TimingEntry +cmd_trace_files Controller.h /^ vector cmd_trace_files;$/;" m class:ramulator::Controller +cmd_trace_files SpeedyController.h /^ vector cmd_trace_files;$/;" m class:ramulator::SpeedyController +cmd_trace_prefix Controller.h /^ string cmd_trace_prefix = "cmd-trace-";$/;" m class:ramulator::Controller +cmd_trace_prefix SpeedyController.h /^ string cmd_trace_prefix = "cmd-trace-";$/;" m class:ramulator::SpeedyController +command_name ALDRAM.h /^ string command_name[int(Command::MAX)] = {$/;" m class:ramulator::ALDRAM +command_name DDR3.h /^ string command_name[int(Command::MAX)] = {$/;" m class:ramulator::DDR3 +command_name DDR4.h /^ string command_name[int(Command::MAX)] = {$/;" m class:ramulator::DDR4 +command_name DSARP.h /^ string command_name[int(Command::MAX)] = {$/;" m class:ramulator::DSARP +command_name GDDR5.h /^ string command_name[int(Command::MAX)] = {$/;" m class:ramulator::GDDR5 +command_name HBM.h /^ string command_name[int(Command::MAX)] = {$/;" m class:ramulator::HBM +command_name LPDDR3.h /^ string command_name[int(Command::MAX)] = {$/;" m class:ramulator::LPDDR3 +command_name LPDDR4.h /^ string command_name[int(Command::MAX)] = {$/;" m class:ramulator::LPDDR4 +command_name SALP.h /^ string command_name[int(Command::MAX)] = {$/;" m class:ramulator::SALP +command_name TLDRAM.h /^ string command_name[int(Command::MAX)] = {$/;" m class:ramulator::TLDRAM +command_name WideIO.h /^ string command_name[int(Command::MAX)] = {$/;" m class:ramulator::WideIO +command_name WideIO2.h /^ string command_name[int(Command::MAX)] = {$/;" m class:ramulator::WideIO2 +compair_depart_clk SpeedyController.h /^ class compair_depart_clk{$/;" c class:ramulator::SpeedyController +compair_first_clk SpeedyController.h /^ static bool compair_first_clk(const request_info& lhs, const request_info& rhs) {$/;" f class:ramulator::SpeedyController +compare Scheduler.h /^ function compare[int(Type::MAX)] = {$/;" m class:ramulator::Scheduler +concatlower Cache.cpp /^void Cache::concatlower(Cache* lower) {$/;" f class:ramulator::Cache +configs MemWrapper.h /^ Config configs;$/;" m class:MemWrapper +contains Config.h /^ bool contains(const std::string& name) const {$/;" f class:ramulator::Config +copyToReq common.cpp /^void MemOp::copyToReq(ramulator::Request &req){$/;" f class:MemOp +core_num Config.h /^ int core_num = 0;$/;" m class:ramulator::Config +coreid Request.h /^ int coreid;$/;" m class:ramulator::Request +cores Processor.h /^ std::vector> cores;$/;" m class:ramulator::Processor +count ALDRAM.h /^ int count[int(Level::MAX)];$/;" m struct:ramulator::ALDRAM::OrgEntry +count DDR3.h /^ int count[int(Level::MAX)];$/;" m struct:ramulator::DDR3::OrgEntry +count DDR4.h /^ int count[int(Level::MAX)];$/;" m struct:ramulator::DDR4::OrgEntry +count DSARP.h /^ int count[int(Level::MAX)];$/;" m struct:ramulator::DSARP::OrgEntry +count GDDR5.h /^ int count[int(Level::MAX)];$/;" m struct:ramulator::GDDR5::OrgEntry +count HBM.h /^ int count[int(Level::MAX)];$/;" m struct:ramulator::HBM::OrgEntry +count LPDDR3.h /^ int count[int(Level::MAX)];$/;" m struct:ramulator::LPDDR3::OrgEntry +count LPDDR4.h /^ int count[int(Level::MAX)];$/;" m struct:ramulator::LPDDR4::OrgEntry +count SALP.h /^ int count[int(Level::MAX)];$/;" m struct:ramulator::SALP::OrgEntry +count TLDRAM.h /^ int count[int(Level::MAX)];$/;" m struct:ramulator::TLDRAM::OrgEntry +count WideIO.h /^ int count[int(Level::MAX)];$/;" m struct:ramulator::WideIO::OrgEntry +count WideIO2.h /^ int count[int(Level::MAX)];$/;" m struct:ramulator::WideIO2::OrgEntry +cpu_cycles Processor.h /^ ScalarStat cpu_cycles;$/;" m class:ramulator::Processor +cpu_inst Processor.h /^ ScalarStat cpu_inst;$/;" m class:ramulator::Core +cpu_tick Config.h /^ int cpu_tick;$/;" m class:ramulator::Config +create MemoryFactory.cpp /^MemoryBase *MemoryFactory::create(const Config& configs, int cacheline) {$/;" f class:ramulator::MemoryFactory +create MemoryFactory.cpp /^MemoryBase *MemoryFactory::create(const Config& configs, int cacheline) {$/;" f class:ramulator::MemoryFactory +create MemoryFactory.h /^ static MemoryBase *create(const Config& configs, int cacheline)$/;" f class:ramulator::MemoryFactory +ctrl Refresh.h /^ Controller* ctrl;$/;" m class:ramulator::Refresh +ctrl Scheduler.h /^ Controller* ctrl;$/;" m class:ramulator::RowPolicy +ctrl Scheduler.h /^ Controller* ctrl;$/;" m class:ramulator::RowTable +ctrl Scheduler.h /^ Controller* ctrl;$/;" m class:ramulator::Scheduler +ctrl_write_mode Refresh.h /^ bool ctrl_write_mode = false;$/;" m class:ramulator::Refresh +ctrls Memory.h /^ vector*> ctrls;$/;" m class:ramulator::Memory +curTick StatType.cpp /^Tick curTick = 0;$/;" m namespace:Stats file: +cur_clk DRAM.h /^ long cur_clk = 0;$/;" m class:ramulator::DRAM +cur_serving_requests DRAM.h /^ int cur_serving_requests = 0;$/;" m class:ramulator::DRAM +current StatType.h /^ Counter current;$/;" m class:Stats::Average +current_speed ALDRAM.h /^ Speed current_speed;$/;" m class:ramulator::ALDRAM +cvec StatType.h /^ VCounter cvec;$/;" m class:Stats::Distribution +cvec StatType.h /^ VCounter cvec;$/;" m class:Stats::Histogram +data StatType.h /^ std::vector data;$/;" m class:Stats::VectorBase +debug Cache.cpp 4;" d file: +debug Cache.cpp 6;" d file: +dec StatType.h /^ void dec(Counter val) {$/;" f class:Stats::Average +decode DRAM.h /^typename T::Command DRAM::decode(typename T::Command cmd, const int* addr)$/;" f class:ramulator::DRAM +depart Request.h /^ long depart;$/;" m class:ramulator::Request +departMemTime Request.h /^ long departMemTime;$/;" m class:ramulator::Request +departMemTime common.h /^ long departMemTime;$/;" m struct:MemOp +departPeTime Request.h /^ long departPeTime; $/;" m class:ramulator::Request +departPeTime common.h /^ long departPeTime;$/;" m struct:MemOp +depth Processor.h /^ int depth = 128;$/;" m class:ramulator::Window +desc StatType.h /^ Derived &desc(const std::string &__desc) {$/;" f class:Stats::Stat +desc Statistics.h /^ StatBase & desc(std::string _desc) {$/;" f class:ramulator::StatBase +dirty Cache.h /^ bool dirty;$/;" m struct:ramulator::Cache::Line +display StatType.h /^const uint16_t display = 0x00000002;$/;" m namespace:Stats +dist ALDRAM.h /^ int dist;$/;" m struct:ramulator::ALDRAM::TimingEntry +dist DDR3.h /^ int dist;$/;" m struct:ramulator::DDR3::TimingEntry +dist DDR4.h /^ int dist;$/;" m struct:ramulator::DDR4::TimingEntry +dist DSARP.h /^ int dist;$/;" m struct:ramulator::DSARP::TimingEntry +dist GDDR5.h /^ int dist;$/;" m struct:ramulator::GDDR5::TimingEntry +dist HBM.h /^ int dist;$/;" m struct:ramulator::HBM::TimingEntry +dist LPDDR3.h /^ int dist;$/;" m struct:ramulator::LPDDR3::TimingEntry +dist LPDDR4.h /^ int dist;$/;" m struct:ramulator::LPDDR4::TimingEntry +dist SALP.h /^ int dist;$/;" m struct:ramulator::SALP::TimingEntry +dist StatType.h /^const uint16_t dist = 0x00000080;$/;" m namespace:Stats +dist TLDRAM.h /^ int dist;$/;" m struct:ramulator::TLDRAM::TimingEntry +dist WideIO.h /^ int dist;$/;" m struct:ramulator::WideIO::TimingEntry +dist WideIO2.h /^ int dist;$/;" m struct:ramulator::WideIO2::TimingEntry +dq ALDRAM.h /^ int dq;$/;" m struct:ramulator::ALDRAM::OrgEntry +dq DDR3.h /^ int dq;$/;" m struct:ramulator::DDR3::OrgEntry +dq DDR4.h /^ int dq;$/;" m struct:ramulator::DDR4::OrgEntry +dq DSARP.h /^ int dq;$/;" m struct:ramulator::DSARP::OrgEntry +dq GDDR5.h /^ int dq;$/;" m struct:ramulator::GDDR5::OrgEntry +dq HBM.h /^ int dq;$/;" m struct:ramulator::HBM::OrgEntry +dq LPDDR3.h /^ int dq;$/;" m struct:ramulator::LPDDR3::OrgEntry +dq LPDDR4.h /^ int dq;$/;" m struct:ramulator::LPDDR4::OrgEntry +dq SALP.h /^ int dq;$/;" m struct:ramulator::SALP::OrgEntry +dq TLDRAM.h /^ int dq;$/;" m struct:ramulator::TLDRAM::OrgEntry +dq WideIO.h /^ int dq;$/;" m struct:ramulator::WideIO::OrgEntry +dq WideIO2.h /^ int dq;$/;" m struct:ramulator::WideIO2::OrgEntry +dram_capacity Memory.h /^ ScalarStat dram_capacity;$/;" m class:ramulator::Memory +dumpResp pe.cpp /^void pe::dumpResp(){$/;" f class:pe +early_exit Processor.h /^ bool early_exit;$/;" m class:ramulator::Processor +early_inject_refresh Refresh.cpp /^void Refresh::early_inject_refresh() {$/;" f class:ramulator::Refresh +end_of_refreshing DRAM.h /^ long end_of_refreshing = -1;$/;" m class:ramulator::DRAM +end_of_serving DRAM.h /^ long end_of_serving = -1;$/;" m class:ramulator::DRAM +enqueue Controller.h /^ bool enqueue(Request& req)$/;" f class:ramulator::Controller +enqueue SpeedyController.h /^ bool enqueue(Request& req)$/;" f class:ramulator::SpeedyController +eps StatType.h /^const double eps = 1e-8;$/;" m namespace:Stats +evict Cache.cpp /^void Cache::evict(std::list* lines,$/;" f class:ramulator::Cache +evictline Cache.cpp /^void Cache::evictline(long addr, bool dirty) {$/;" f class:ramulator::Cache +expected_limit_insts Config.h /^ long expected_limit_insts = 0;$/;" m class:ramulator::Config +expected_limit_insts Processor.h /^ long expected_limit_insts;$/;" m class:ramulator::Core +extend_channel_width MemoryFactory.h /^ static void extend_channel_width(T* spec, int cacheline)$/;" f class:ramulator::MemoryFactory +file Processor.h /^ std::ifstream file;$/;" m class:ramulator::Trace +files MemWrapper.h /^ std::vector files;$/;" m class:MemWrapper +finish Controller.h /^ void finish(long read_req, long dram_cycles) {$/;" f class:ramulator::Controller +finish DRAM.h /^void DRAM::finish(long dram_cycles) {$/;" f class:ramulator::DRAM +finish Gem5Wrapper.cpp /^void Gem5Wrapper::finish(void) {$/;" f class:Gem5Wrapper +finish Memory.h /^ void finish(void) {$/;" f class:ramulator::Memory +finish SpeedyController.h /^ void finish(int read_req, int write_req, int dram_cycles) {$/;" f class:ramulator::SpeedyController +finished Processor.cpp /^bool Core::finished()$/;" f class:Core +finished Processor.cpp /^bool Processor::finished() {$/;" f class:Processor +first_level Cache.h /^ Cache::Level first_level;$/;" m class:ramulator::CacheSystem +flags StatType.h /^ Derived &flags(Flags __flags) {$/;" f class:Stats::Stat +flags StatType.h /^ uint16_t flags;$/;" m class:Stats::Flags +flags Statistics.h /^ StatBase & flags(Stats::Flags _flags) {$/;" f class:ramulator::StatBase +free_physical_pages Memory.h /^ vector free_physical_pages;$/;" m class:ramulator::Memory +free_physical_pages_remaining Memory.h /^ long free_physical_pages_remaining;$/;" m class:ramulator::Memory +freq ALDRAM.h /^ double freq, tCK;$/;" m struct:ramulator::ALDRAM::SpeedEntry +freq DDR3.h /^ double freq, tCK;$/;" m struct:ramulator::DDR3::SpeedEntry +freq DDR4.h /^ double freq, tCK;$/;" m struct:ramulator::DDR4::SpeedEntry +freq DSARP.h /^ double freq, tCK;$/;" m struct:ramulator::DSARP::SpeedEntry +freq GDDR5.h /^ double freq, tCK;$/;" m struct:ramulator::GDDR5::SpeedEntry +freq HBM.h /^ double freq, tCK;$/;" m struct:ramulator::HBM::SpeedEntry +freq LPDDR3.h /^ double freq, tCK;$/;" m struct:ramulator::LPDDR3::SpeedEntry +freq LPDDR4.h /^ double freq, tCK;$/;" m struct:ramulator::LPDDR4::SpeedEntry +freq SALP.h /^ double freq, tCK;$/;" m struct:ramulator::SALP::SpeedEntry +freq TLDRAM.h /^ double freq, tCK;$/;" m struct:ramulator::TLDRAM::SpeedEntry +freq WideIO.h /^ double freq, tCK;$/;" m struct:ramulator::WideIO::SpeedEntry +freq WideIO2.h /^ double freq, tCK;$/;" m struct:ramulator::WideIO2::SpeedEntry +getMemReq MemWrapper.cpp /^bool MemWrapper::getMemReq(MemOp &op){$/;" f class:MemWrapper +getMemResp pe.cpp /^void pe::getMemResp(){$/;" f class:pe +getOpIdx pe.cpp /^long pe::getOpIdx(){$/;" f class:pe +getRequest MemWrapper.cpp /^void MemWrapper::getRequest(){$/;" f class:MemWrapper +get_addr_vec Controller.cpp /^vector Controller::get_addr_vec(SALP::Command cmd, list::iterator req){$/;" f class:ramulator::Controller +get_addr_vec Controller.h /^ vector get_addr_vec(typename T::Command cmd, list::iterator req){$/;" f class:ramulator::Controller +get_channels Config.h /^ int get_channels() const {return channels;}$/;" f class:ramulator::Config +get_core_num Config.h /^ int get_core_num() const {return core_num;}$/;" f class:ramulator::Config +get_cpu_tick Config.h /^ int get_cpu_tick() const {return cpu_tick;}$/;" f class:ramulator::Config +get_dramtrace_request Processor.cpp /^bool Trace::get_dramtrace_request(long& req_addr, Request::Type& req_type)$/;" f class:Trace +get_expected_limit_insts Config.h /^ long get_expected_limit_insts() const {return expected_limit_insts;}$/;" f class:ramulator::Config +get_filtered_request Processor.cpp /^bool Trace::get_filtered_request(long& bubble_cnt, long& req_addr, Request::Type& req_type)$/;" f class:Trace +get_first_cmd Controller.h /^ typename T::Command get_first_cmd(list::iterator req)$/;" f class:ramulator::Controller +get_first_cmd SpeedyController.h /^ typename T::Command get_first_cmd(Request& req)$/;" f class:ramulator::SpeedyController +get_head Scheduler.h /^ list::iterator get_head(list& q)$/;" f class:ramulator::Scheduler +get_hits Scheduler.h /^ int get_hits(vector& addr_vec)$/;" f class:ramulator::RowTable +get_index Cache.h /^ int get_index(long addr) {$/;" f class:ramulator::Cache +get_lines Cache.h /^ std::list& get_lines(long addr) {$/;" f class:ramulator::Cache +get_mem_tick Config.h /^ int get_mem_tick() const {return mem_tick;}$/;" f class:ramulator::Config +get_next DRAM.h /^long DRAM::get_next(typename T::Command cmd, const int* addr)$/;" f class:ramulator::DRAM +get_offending_subarray Controller.cpp /^static vector get_offending_subarray(DRAM* channel, vector & addr_vec){$/;" f namespace:ramulator +get_queue Controller.h /^ Queue& get_queue(Request::Type type)$/;" f class:ramulator::Controller +get_ranks Config.h /^ int get_ranks() const {return ranks;}$/;" f class:ramulator::Config +get_stat Statistics.h /^ const StatType* get_stat() const {$/;" f class:ramulator::StatBase +get_subarrays Config.h /^ int get_subarrays() const {return subarrays;}$/;" f class:ramulator::Config +get_tag Cache.h /^ long get_tag(long addr) {$/;" f class:ramulator::Cache +get_unfiltered_request Processor.cpp /^bool Trace::get_unfiltered_request(long& bubble_cnt, long& req_addr, Request::Type& req_type)$/;" f class:Trace +get_victim Scheduler.h /^ vector get_victim(typename T::Command cmd)$/;" f class:ramulator::RowPolicy +grow_convert StatType.cpp /^Histogram::grow_convert()$/;" f class:Stats::Histogram +grow_out StatType.cpp /^Histogram::grow_out()$/;" f class:Stats::Histogram +grow_up StatType.cpp /^Histogram::grow_up()$/;" f class:Stats::Histogram +has_core_caches Config.h /^ bool has_core_caches() const {$/;" f class:ramulator::Config +has_l3_cache Config.h /^ bool has_l3_cache() const {$/;" f class:ramulator::Config +has_reached_limit Processor.cpp /^bool Core::has_reached_limit() {$/;" f class:Core +has_reached_limit Processor.cpp /^bool Processor::has_reached_limit() {$/;" f class:Processor +head Processor.h /^ int head = 0;$/;" m class:ramulator::Window +higher_cache Cache.h /^ std::vector higher_cache;$/;" m class:ramulator::Cache +hit_list Cache.h /^ std::list > hit_list;$/;" m class:ramulator::CacheSystem +hit_mshr Cache.h /^ hit_mshr(long addr) {$/;" f class:ramulator::Cache +hits Scheduler.h /^ int hits;$/;" m struct:ramulator::RowTable::Entry +id DRAM.h /^ int id;$/;" m class:ramulator::DRAM +id Processor.h /^ int id = 0;$/;" m class:ramulator::Core +in_queue_read_req_num_avg Memory.h /^ ScalarStat in_queue_read_req_num_avg;$/;" m class:ramulator::Memory +in_queue_read_req_num_sum Memory.h /^ ScalarStat in_queue_read_req_num_sum;$/;" m class:ramulator::Memory +in_queue_req_num_avg Memory.h /^ ScalarStat in_queue_req_num_avg;$/;" m class:ramulator::Memory +in_queue_req_num_sum Memory.h /^ ScalarStat in_queue_req_num_sum;$/;" m class:ramulator::Memory +in_queue_write_req_num_avg Memory.h /^ ScalarStat in_queue_write_req_num_avg;$/;" m class:ramulator::Memory +in_queue_write_req_num_sum Memory.h /^ ScalarStat in_queue_write_req_num_sum;$/;" m class:ramulator::Memory +inc StatType.h /^ void inc(Counter val) {$/;" f class:Stats::Average +incoming_read_reqs_per_channel Memory.h /^ VectorStat incoming_read_reqs_per_channel;$/;" m class:ramulator::Memory +incoming_requests_per_channel Memory.h /^ VectorStat incoming_requests_per_channel;$/;" m class:ramulator::Memory +index_mask Cache.h /^ unsigned int index_mask;$/;" m class:ramulator::Cache +index_offset Cache.h /^ unsigned int index_offset;$/;" m class:ramulator::Cache +init StatType.h /^ void init(Counter min, Counter max, Counter bkt) {$/;" f class:Stats::Distribution +init StatType.h /^ void init(size_type __buckets) {$/;" f class:Stats::Histogram +init StatType.h /^ void init(size_type __size) {$/;" f class:Stats::VectorBase +init StatType.h /^const uint16_t init = 0x00000001;$/;" m namespace:Stats +init Statistics.h /^ DistributionStat & init(Stats::Counter min, Stats::Counter max, Stats::Counter bkt) {$/;" f class:ramulator::DistributionStat +init Statistics.h /^ HistogramStat & init(Stats::size_type size) {$/;" f class:ramulator::HistogramStat +init Statistics.h /^ VectorStatBase & init(Stats::size_type size) {$/;" f class:ramulator::VectorStatBase +init pe.cpp /^void pe::init(){$/;" f class:pe +init_lambda ALDRAM.cpp /^void ALDRAM::init_lambda()$/;" f class:ALDRAM +init_lambda DDR3.cpp /^void DDR3::init_lambda()$/;" f class:DDR3 +init_lambda DDR4.cpp /^void DDR4::init_lambda()$/;" f class:DDR4 +init_lambda DSARP.cpp /^void DSARP::init_lambda()$/;" f class:DSARP +init_lambda GDDR5.cpp /^void GDDR5::init_lambda()$/;" f class:GDDR5 +init_lambda HBM.cpp /^void HBM::init_lambda()$/;" f class:HBM +init_lambda LPDDR3.cpp /^void LPDDR3::init_lambda()$/;" f class:LPDDR3 +init_lambda LPDDR4.cpp /^void LPDDR4::init_lambda()$/;" f class:LPDDR4 +init_lambda SALP.cpp /^void SALP::init_lambda()$/;" f class:SALP +init_lambda TLDRAM.cpp /^void TLDRAM::init_lambda()$/;" f class:TLDRAM +init_lambda WideIO.cpp /^void WideIO::init_lambda()$/;" f class:WideIO +init_lambda WideIO2.cpp /^void WideIO2::init_lambda()$/;" f class:WideIO2 +init_prereq ALDRAM.cpp /^void ALDRAM::init_prereq()$/;" f class:ALDRAM +init_prereq DDR3.cpp /^void DDR3::init_prereq()$/;" f class:DDR3 +init_prereq DDR4.cpp /^void DDR4::init_prereq()$/;" f class:DDR4 +init_prereq DSARP.cpp /^void DSARP::init_prereq()$/;" f class:DSARP +init_prereq GDDR5.cpp /^void GDDR5::init_prereq()$/;" f class:GDDR5 +init_prereq HBM.cpp /^void HBM::init_prereq()$/;" f class:HBM +init_prereq LPDDR3.cpp /^void LPDDR3::init_prereq()$/;" f class:LPDDR3 +init_prereq LPDDR4.cpp /^void LPDDR4::init_prereq()$/;" f class:LPDDR4 +init_prereq SALP.cpp /^void SALP::init_prereq()$/;" f class:SALP +init_prereq TLDRAM.cpp /^void TLDRAM::init_prereq()$/;" f class:TLDRAM +init_prereq WideIO.cpp /^void WideIO::init_prereq()$/;" f class:WideIO +init_prereq WideIO2.cpp /^void WideIO2::init_prereq()$/;" f class:WideIO2 +init_rowhit ALDRAM.cpp /^void ALDRAM::init_rowhit()$/;" f class:ALDRAM +init_rowhit DDR3.cpp /^void DDR3::init_rowhit()$/;" f class:DDR3 +init_rowhit DDR4.cpp /^void DDR4::init_rowhit()$/;" f class:DDR4 +init_rowhit DSARP.cpp /^void DSARP::init_rowhit()$/;" f class:DSARP +init_rowhit GDDR5.cpp /^void GDDR5::init_rowhit()$/;" f class:GDDR5 +init_rowhit HBM.cpp /^void HBM::init_rowhit()$/;" f class:HBM +init_rowhit LPDDR3.cpp /^void LPDDR3::init_rowhit()$/;" f class:LPDDR3 +init_rowhit LPDDR4.cpp /^void LPDDR4::init_rowhit()$/;" f class:LPDDR4 +init_rowhit SALP.cpp /^void SALP::init_rowhit()$/;" f class:SALP +init_rowhit TLDRAM.cpp /^void TLDRAM::init_rowhit()$/;" f class:TLDRAM +init_rowhit WideIO.cpp /^void WideIO::init_rowhit()$/;" f class:WideIO +init_rowhit WideIO2.cpp /^void WideIO2::init_rowhit()$/;" f class:WideIO2 +init_rowopen DDR3.cpp /^void DDR3::init_rowopen()$/;" f class:DDR3 +init_rowopen DDR4.cpp /^void DDR4::init_rowopen()$/;" f class:DDR4 +init_rowopen DSARP.cpp /^void DSARP::init_rowopen()$/;" f class:DSARP +init_rowopen GDDR5.cpp /^void GDDR5::init_rowopen()$/;" f class:GDDR5 +init_rowopen HBM.cpp /^void HBM::init_rowopen()$/;" f class:HBM +init_rowopen LPDDR3.cpp /^void LPDDR3::init_rowopen()$/;" f class:LPDDR3 +init_rowopen LPDDR4.cpp /^void LPDDR4::init_rowopen()$/;" f class:LPDDR4 +init_rowopen SALP.cpp /^void SALP::init_rowopen()$/;" f class:SALP +init_rowopen TLDRAM.cpp /^void TLDRAM::init_rowopen()$/;" f class:TLDRAM +init_rowopen WideIO.cpp /^void WideIO::init_rowopen()$/;" f class:WideIO +init_rowopen WideIO2.cpp /^void WideIO2::init_rowopen()$/;" f class:WideIO2 +init_speed ALDRAM.cpp /^void ALDRAM::init_speed()$/;" f class:ALDRAM +init_speed DDR3.cpp /^void DDR3::init_speed()$/;" f class:DDR3 +init_speed DDR4.cpp /^void DDR4::init_speed()$/;" f class:DDR4 +init_speed DSARP.cpp /^void DSARP::init_speed()$/;" f class:DSARP +init_speed GDDR5.cpp /^void GDDR5::init_speed()$/;" f class:GDDR5 +init_speed HBM.cpp /^void HBM::init_speed()$/;" f class:HBM +init_speed LPDDR3.cpp /^void LPDDR3::init_speed()$/;" f class:LPDDR3 +init_speed LPDDR4.cpp /^void LPDDR4::init_speed()$/;" f class:LPDDR4 +init_speed SALP.cpp /^void SALP::init_speed()$/;" f class:SALP +init_speed TLDRAM.cpp /^void TLDRAM::init_speed()$/;" f class:TLDRAM +init_speed WideIO.cpp /^void WideIO::init_speed()$/;" f class:WideIO +init_timing ALDRAM.cpp /^void ALDRAM::init_timing(SpeedEntry speed_entry)$/;" f class:ALDRAM +init_timing DDR3.cpp /^void DDR3::init_timing()$/;" f class:DDR3 +init_timing DDR4.cpp /^void DDR4::init_timing()$/;" f class:DDR4 +init_timing DSARP.cpp /^void DSARP::init_timing()$/;" f class:DSARP +init_timing GDDR5.cpp /^void GDDR5::init_timing()$/;" f class:GDDR5 +init_timing HBM.cpp /^void HBM::init_timing()$/;" f class:HBM +init_timing LPDDR3.cpp /^void LPDDR3::init_timing()$/;" f class:LPDDR3 +init_timing LPDDR4.cpp /^void LPDDR4::init_timing()$/;" f class:LPDDR4 +init_timing SALP.cpp /^void SALP::init_timing()$/;" f class:SALP +init_timing TLDRAM.cpp /^void TLDRAM::init_timing()$/;" f class:TLDRAM +init_timing WideIO.cpp /^void WideIO::init_timing()$/;" f class:WideIO +init_timing WideIO2.cpp /^void WideIO2::init_timing()$/;" f class:WideIO2 +inject_refresh Refresh.cpp /^void Refresh::inject_refresh(bool b_ref_rank) {$/;" f class:ramulator::Refresh +inject_refresh Refresh.h /^ void inject_refresh(bool b_ref_rank) {$/;" f class:ramulator::Refresh +insert DRAM.h /^void DRAM::insert(DRAM* child)$/;" f class:ramulator::DRAM +insert Processor.cpp /^void Window::insert(bool ready, long addr)$/;" f class:Window +invalidate Cache.cpp /^std::pair Cache::invalidate(long addr) {$/;" f class:ramulator::Cache +ipc Processor.h /^ double ipc = 0;$/;" m class:ramulator::Processor +ipc Processor.h /^ int ipc = 4;$/;" m class:ramulator::Window +ipcs Processor.h /^ std::vector ipcs;$/;" m class:ramulator::Processor +is_accessing ALDRAM.h /^ bool is_accessing(Command cmd)$/;" f class:ramulator::ALDRAM +is_accessing DDR3.h /^ bool is_accessing(Command cmd) $/;" f class:ramulator::DDR3 +is_accessing DDR4.h /^ bool is_accessing(Command cmd) $/;" f class:ramulator::DDR4 +is_accessing DSARP.h /^ bool is_accessing(Command cmd)$/;" f class:ramulator::DSARP +is_accessing GDDR5.h /^ bool is_accessing(Command cmd) $/;" f class:ramulator::GDDR5 +is_accessing HBM.h /^ bool is_accessing(Command cmd)$/;" f class:ramulator::HBM +is_accessing LPDDR3.h /^ bool is_accessing(Command cmd) $/;" f class:ramulator::LPDDR3 +is_accessing LPDDR4.h /^ bool is_accessing(Command cmd) $/;" f class:ramulator::LPDDR4 +is_accessing SALP.h /^ bool is_accessing(Command cmd) $/;" f class:ramulator::SALP +is_accessing TLDRAM.h /^ bool is_accessing(Command cmd)$/;" f class:ramulator::TLDRAM +is_accessing WideIO.h /^ bool is_accessing(Command cmd) $/;" f class:ramulator::WideIO +is_accessing WideIO2.h /^ bool is_accessing(Command cmd) $/;" f class:ramulator::WideIO2 +is_active Controller.h /^ bool is_active() {$/;" f class:ramulator::Controller +is_cdf StatType.h /^ bool is_cdf() const {return flags & cdf;}$/;" f class:Stats::Flags +is_closing ALDRAM.h /^ bool is_closing(Command cmd)$/;" f class:ramulator::ALDRAM +is_closing DDR3.h /^ bool is_closing(Command cmd) $/;" f class:ramulator::DDR3 +is_closing DDR4.h /^ bool is_closing(Command cmd) $/;" f class:ramulator::DDR4 +is_closing DSARP.h /^ bool is_closing(Command cmd)$/;" f class:ramulator::DSARP +is_closing GDDR5.h /^ bool is_closing(Command cmd) $/;" f class:ramulator::GDDR5 +is_closing HBM.h /^ bool is_closing(Command cmd)$/;" f class:ramulator::HBM +is_closing LPDDR3.h /^ bool is_closing(Command cmd) $/;" f class:ramulator::LPDDR3 +is_closing LPDDR4.h /^ bool is_closing(Command cmd) $/;" f class:ramulator::LPDDR4 +is_closing SALP.h /^ bool is_closing(Command cmd) $/;" f class:ramulator::SALP +is_closing TLDRAM.h /^ bool is_closing(Command cmd)$/;" f class:ramulator::TLDRAM +is_closing WideIO.h /^ bool is_closing(Command cmd) $/;" f class:ramulator::WideIO +is_closing WideIO2.h /^ bool is_closing(Command cmd) $/;" f class:ramulator::WideIO2 +is_display StatType.h /^ bool is_display() const {return flags & display;}$/;" f class:Stats::Flags +is_display StatType.h /^ virtual bool is_display() const {$/;" f class:Stats::Stat +is_early_exit Config.h /^ bool is_early_exit() const {$/;" f class:ramulator::Config +is_empty Processor.cpp /^bool Window::is_empty()$/;" f class:Window +is_first_command Request.h /^ bool is_first_command;$/;" m class:ramulator::Request +is_first_level Cache.h /^ bool is_first_level;$/;" m class:ramulator::Cache +is_full Processor.cpp /^bool Window::is_full()$/;" f class:Window +is_hit Cache.cpp /^bool Cache::is_hit(std::list& lines, long addr,$/;" f class:ramulator::Cache +is_last_level Cache.h /^ bool is_last_level;$/;" m class:ramulator::Cache +is_nonan StatType.h /^ bool is_nonan() const {return flags & nonan;}$/;" f class:Stats::Flags +is_nozero StatType.h /^ bool is_nozero() const {return flags & nozero;}$/;" f class:Stats::Flags +is_nozero StatType.h /^ virtual bool is_nozero() const {$/;" f class:Stats::Stat +is_opening ALDRAM.h /^ bool is_opening(Command cmd)$/;" f class:ramulator::ALDRAM +is_opening DDR3.h /^ bool is_opening(Command cmd) $/;" f class:ramulator::DDR3 +is_opening DDR4.h /^ bool is_opening(Command cmd) $/;" f class:ramulator::DDR4 +is_opening DSARP.h /^ bool is_opening(Command cmd)$/;" f class:ramulator::DSARP +is_opening GDDR5.h /^ bool is_opening(Command cmd) $/;" f class:ramulator::GDDR5 +is_opening HBM.h /^ bool is_opening(Command cmd)$/;" f class:ramulator::HBM +is_opening LPDDR3.h /^ bool is_opening(Command cmd) $/;" f class:ramulator::LPDDR3 +is_opening LPDDR4.h /^ bool is_opening(Command cmd) $/;" f class:ramulator::LPDDR4 +is_opening SALP.h /^ bool is_opening(Command cmd) $/;" f class:ramulator::SALP +is_opening TLDRAM.h /^ bool is_opening(Command cmd)$/;" f class:ramulator::TLDRAM +is_opening WideIO.h /^ bool is_opening(Command cmd) $/;" f class:ramulator::WideIO +is_opening WideIO2.h /^ bool is_opening(Command cmd) $/;" f class:ramulator::WideIO2 +is_pdf StatType.h /^ bool is_pdf() const {return flags & pdf;}$/;" f class:Stats::Flags +is_ready Controller.cpp /^bool Controller::is_ready(list::iterator req){$/;" f class:ramulator::Controller +is_ready Controller.h /^ bool is_ready(list::iterator req)$/;" f class:ramulator::Controller +is_ready Controller.h /^ bool is_ready(typename T::Command cmd, const vector& addr_vec)$/;" f class:ramulator::Controller +is_refresh Controller.h /^ bool is_refresh() {$/;" f class:ramulator::Controller +is_refreshing ALDRAM.h /^ bool is_refreshing(Command cmd)$/;" f class:ramulator::ALDRAM +is_refreshing DDR3.h /^ bool is_refreshing(Command cmd) $/;" f class:ramulator::DDR3 +is_refreshing DDR4.h /^ bool is_refreshing(Command cmd) $/;" f class:ramulator::DDR4 +is_refreshing DSARP.h /^ bool is_refreshing(Command cmd)$/;" f class:ramulator::DSARP +is_refreshing GDDR5.h /^ bool is_refreshing(Command cmd) $/;" f class:ramulator::GDDR5 +is_refreshing HBM.h /^ bool is_refreshing(Command cmd)$/;" f class:ramulator::HBM +is_refreshing LPDDR3.h /^ bool is_refreshing(Command cmd) $/;" f class:ramulator::LPDDR3 +is_refreshing LPDDR4.h /^ bool is_refreshing(Command cmd) $/;" f class:ramulator::LPDDR4 +is_refreshing SALP.h /^ bool is_refreshing(Command cmd) $/;" f class:ramulator::SALP +is_refreshing TLDRAM.h /^ bool is_refreshing(Command cmd)$/;" f class:ramulator::TLDRAM +is_refreshing WideIO.h /^ bool is_refreshing(Command cmd) $/;" f class:ramulator::WideIO +is_refreshing WideIO2.h /^ bool is_refreshing(Command cmd) $/;" f class:ramulator::WideIO2 +is_row_hit Controller.h /^ bool is_row_hit(list::iterator req)$/;" f class:ramulator::Controller +is_row_hit Controller.h /^ bool is_row_hit(typename T::Command cmd, const vector& addr_vec)$/;" f class:ramulator::Controller +is_row_hit SpeedyController.h /^ bool is_row_hit(Request& req)$/;" f class:ramulator::SpeedyController +is_row_open Controller.h /^ bool is_row_open(list::iterator req)$/;" f class:ramulator::Controller +is_row_open Controller.h /^ bool is_row_open(typename T::Command cmd, const vector& addr_vec)$/;" f class:ramulator::Controller +is_total StatType.h /^ bool is_total() const {return flags & total;}$/;" f class:Stats::Flags +issue_cmd Controller.h /^ void issue_cmd(typename T::Command cmd, const vector& addr_vec)$/;" f class:ramulator::Controller +issue_cmd SpeedyController.h /^ void issue_cmd(typename T::Command cmd, int* addr_vec)$/;" f class:ramulator::SpeedyController +l1_assoc Processor.h /^ int l1_assoc = 1 << 3;$/;" m class:ramulator::Core +l1_blocksz Processor.h /^ int l1_blocksz = 1 << 6;$/;" m class:ramulator::Core +l1_mshr_num Processor.h /^ int l1_mshr_num = 16;$/;" m class:ramulator::Core +l1_size Processor.h /^ int l1_size = 1 << 15;$/;" m class:ramulator::Core +l2_assoc Processor.h /^ int l2_assoc = 1 << 3;$/;" m class:ramulator::Core +l2_blocksz Processor.h /^ int l2_blocksz = 1 << 6;$/;" m class:ramulator::Core +l2_mshr_num Processor.h /^ int l2_mshr_num = 16;$/;" m class:ramulator::Core +l2_size Processor.h /^ int l2_size = 1 << 18;$/;" m class:ramulator::Core +l3_assoc Processor.h /^ int l3_assoc = 1 << 3;$/;" m class:ramulator::Processor +l3_blocksz Processor.h /^ int l3_blocksz = 1 << 6;$/;" m class:ramulator::Processor +l3_size Processor.h /^ int l3_size = 1 << 23;$/;" m class:ramulator::Processor +lambda ALDRAM.h /^ function*, int)> lambda[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::ALDRAM +lambda DDR3.h /^ function*, int)> lambda[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::DDR3 +lambda DDR4.h /^ function*, int)> lambda[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::DDR4 +lambda DRAM.h /^ function*, int)>* lambda;$/;" m class:ramulator::DRAM +lambda DSARP.h /^ function*, int)> lambda[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::DSARP +lambda GDDR5.h /^ function*, int)> lambda[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::GDDR5 +lambda HBM.h /^ function*, int)> lambda[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::HBM +lambda LPDDR3.h /^ function*, int)> lambda[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::LPDDR3 +lambda LPDDR4.h /^ function*, int)> lambda[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::LPDDR4 +lambda SALP.h /^ function*, int)> lambda[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::SALP +lambda TLDRAM.h /^ function*, int)> lambda[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::TLDRAM +lambda WideIO.h /^ function*, int)> lambda[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::WideIO +lambda WideIO2.h /^ function*, int)> lambda[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::WideIO2 +last Processor.h /^ long last = 0;$/;" m class:ramulator::Core +last StatType.h /^ Tick last;$/;" m class:Stats::Average +lastReset StatType.h /^ Tick lastReset;$/;" m class:Stats::Average +last_level Cache.h /^ Cache::Level last_level;$/;" m class:ramulator::CacheSystem +latency Cache.h /^ int latency[int(Level::MAX)] = {4, 4 + 12, 4 + 12 + 31};$/;" m class:ramulator::Cache +latency_each Cache.h /^ int latency_each[int(Level::MAX)] = {4, 12, 31};$/;" m class:ramulator::Cache +length Request.h /^ int length;$/;" m class:ramulator::Request +length common.h /^ int length; \/\/ # of bytes of the memory operation.$/;" m struct:MemOp +level Cache.h /^ } level;$/;" m class:ramulator::Cache typeref:class:ramulator::Cache::Level +level DRAM.h /^ typename T::Level level;$/;" m class:ramulator::DRAM +level_bank Refresh.h /^ int level_chan, level_rank, level_bank, level_sa;$/;" m class:ramulator::Refresh +level_chan Refresh.h /^ int level_chan, level_rank, level_bank, level_sa;$/;" m class:ramulator::Refresh +level_rank Refresh.h /^ int level_chan, level_rank, level_bank, level_sa;$/;" m class:ramulator::Refresh +level_sa Refresh.h /^ int level_chan, level_rank, level_bank, level_sa;$/;" m class:ramulator::Refresh +level_string Cache.h /^ std::string level_string;$/;" m class:ramulator::Cache +libramulator_is_present MemoryFactory.cpp /^ void libramulator_is_present(void)$/;" f +list StatType.h /^ std::vector list;$/;" m class:Stats::StatList +llc Processor.h /^ Cache llc;$/;" m class:ramulator::Processor +llc Processor.h /^ Cache* llc;$/;" m class:ramulator::Core +load Processor.h /^ int load = 0;$/;" m class:ramulator::Window +loadConfig MemWrapper.cpp /^void MemWrapper::loadConfig(int argc, char* argv[]){$/;" f class:MemWrapper +lock Cache.h /^ bool lock; \/\/ When the lock is on, the value is not valid yet.$/;" m struct:ramulator::Cache::Line +logs StatType.h /^ Counter logs;$/;" m class:Stats::Histogram +lower_cache Cache.h /^ Cache* lower_cache;$/;" m class:ramulator::Cache +lrand Memory.h /^ long lrand(void) {$/;" f class:ramulator::Memory +max Controller.h /^ unsigned int max = 32;$/;" m struct:ramulator::Controller::Queue +max_address Memory.h /^ long max_address;$/;" m class:ramulator::Memory +max_bank_count Refresh.h /^ int max_rank_count, max_bank_count;$/;" m class:ramulator::Refresh +max_bucket StatType.h /^ Counter max_bucket;$/;" m class:Stats::Histogram +max_rank_count Refresh.h /^ int max_rank_count, max_bank_count;$/;" m class:ramulator::Refresh +max_sa_count Refresh.h /^ int max_sa_count = 0;$/;" m class:ramulator::Refresh +max_track StatType.h /^ Counter max_track;$/;" m class:Stats::Distribution +max_val StatType.h /^ Counter max_val;$/;" m class:Stats::Distribution +maximum_bandwidth Memory.h /^ ScalarStat maximum_bandwidth;$/;" m class:ramulator::Memory +mem Gem5Wrapper.h /^ MemoryBase *mem;$/;" m class:ramulator::Gem5Wrapper +memClkCycle MemWrapper.h /^ int memClkCycle;$/;" m class:MemWrapper +memReq MemWrapper.h /^ sc_in memReq;$/;" m class:MemWrapper +memReq pe.h /^ sc_out memReq; $/;" m class:pe +memReqMonitor MemWrapper.cpp /^void MemWrapper::memReqMonitor(){$/;" f class:MemWrapper +memReqQueue MemWrapper.h /^ std::list memReqQueue;$/;" m class:MemWrapper +memReqQueue pe.h /^ std::list memReqQueue;$/;" m class:pe +memResp MemWrapper.h /^ sc_out memResp;$/;" m class:MemWrapper +memResp pe.h /^ sc_in memResp;$/;" m class:pe +memRespQueue MemWrapper.h /^ std::list memRespQueue;$/;" m class:MemWrapper +memRespQueue pe.h /^ std::list memRespQueue;$/;" m class:pe +memSize MemWrapper.h /^ int memSize;$/;" m class:MemWrapper +mem_tick Config.h /^ int mem_tick;$/;" m class:ramulator::Config +memory Processor.h /^ MemoryBase& memory;$/;" m class:ramulator::Core +memory_access_cycles Processor.h /^ ScalarStat memory_access_cycles;$/;" m class:ramulator::Core +min_bucket StatType.h /^ Counter min_bucket;$/;" m class:Stats::Histogram +min_track StatType.h /^ Counter min_track;$/;" m class:Stats::Distribution +min_val StatType.h /^ Counter min_val;$/;" m class:Stats::Distribution +more_reqs Processor.h /^ bool more_reqs;$/;" m class:ramulator::Core +mshr_entries Cache.h /^ std::vector::iterator>> mshr_entries;$/;" m class:ramulator::Cache +mshr_entry_num Cache.h /^ unsigned int mshr_entry_num;$/;" m class:ramulator::Cache +mshr_per_bank Processor.h /^ int mshr_per_bank = 16;$/;" m class:ramulator::Processor +n32AW GDDR5.h /^ int nRRD, nFAW, n32AW;$/;" m struct:ramulator::GDDR5::SpeedEntry +nBL ALDRAM.h /^ int nBL, nCCD, nRTRS;$/;" m struct:ramulator::ALDRAM::SpeedEntry +nBL DDR3.h /^ int nBL, nCCD, nRTRS;$/;" m struct:ramulator::DDR3::SpeedEntry +nBL DDR4.h /^ int nBL, nCCDS, nCCDL, nRTRS;$/;" m struct:ramulator::DDR4::SpeedEntry +nBL DSARP.h /^ int nBL, nCCD, nRTRS;$/;" m struct:ramulator::DSARP::SpeedEntry +nBL GDDR5.h /^ int nBL, nCCDS, nCCDL;$/;" m struct:ramulator::GDDR5::SpeedEntry +nBL HBM.h /^ int nBL, nCCDS, nCCDL;$/;" m struct:ramulator::HBM::SpeedEntry +nBL LPDDR3.h /^ int nBL, nCCD, nRTRS, nDQSCK;$/;" m struct:ramulator::LPDDR3::SpeedEntry +nBL LPDDR4.h /^ int nBL, nCCD, nRTRS, nDQSCK;$/;" m struct:ramulator::LPDDR4::SpeedEntry +nBL SALP.h /^ int nBL, nCCD, nRTRS;$/;" m struct:ramulator::SALP::SpeedEntry +nBL TLDRAM.h /^ int nBL, nCCD, nRTRS;$/;" m struct:ramulator::TLDRAM::SpeedEntry +nBL WideIO.h /^ int nBL, nCCD, nDQSCK;$/;" m struct:ramulator::WideIO::SpeedEntry +nBL WideIO2.h /^ int nBL, nCCD, nDQSCK, nRTRS; \/\/ 4n prefetch, DDR (although 8n is allowed?)$/;" m struct:ramulator::WideIO2::SpeedEntry +nCCD ALDRAM.h /^ int nBL, nCCD, nRTRS;$/;" m struct:ramulator::ALDRAM::SpeedEntry +nCCD DDR3.h /^ int nBL, nCCD, nRTRS;$/;" m struct:ramulator::DDR3::SpeedEntry +nCCD DSARP.h /^ int nBL, nCCD, nRTRS;$/;" m struct:ramulator::DSARP::SpeedEntry +nCCD LPDDR3.h /^ int nBL, nCCD, nRTRS, nDQSCK;$/;" m struct:ramulator::LPDDR3::SpeedEntry +nCCD LPDDR4.h /^ int nBL, nCCD, nRTRS, nDQSCK;$/;" m struct:ramulator::LPDDR4::SpeedEntry +nCCD SALP.h /^ int nBL, nCCD, nRTRS;$/;" m struct:ramulator::SALP::SpeedEntry +nCCD TLDRAM.h /^ int nBL, nCCD, nRTRS;$/;" m struct:ramulator::TLDRAM::SpeedEntry +nCCD WideIO.h /^ int nBL, nCCD, nDQSCK;$/;" m struct:ramulator::WideIO::SpeedEntry +nCCD WideIO2.h /^ int nBL, nCCD, nDQSCK, nRTRS; \/\/ 4n prefetch, DDR (although 8n is allowed?)$/;" m struct:ramulator::WideIO2::SpeedEntry +nCCDL DDR4.h /^ int nBL, nCCDS, nCCDL, nRTRS;$/;" m struct:ramulator::DDR4::SpeedEntry +nCCDL GDDR5.h /^ int nBL, nCCDS, nCCDL;$/;" m struct:ramulator::GDDR5::SpeedEntry +nCCDL HBM.h /^ int nBL, nCCDS, nCCDL;$/;" m struct:ramulator::HBM::SpeedEntry +nCCDS DDR4.h /^ int nBL, nCCDS, nCCDL, nRTRS;$/;" m struct:ramulator::DDR4::SpeedEntry +nCCDS GDDR5.h /^ int nBL, nCCDS, nCCDL;$/;" m struct:ramulator::GDDR5::SpeedEntry +nCCDS HBM.h /^ int nBL, nCCDS, nCCDL;$/;" m struct:ramulator::HBM::SpeedEntry +nCKE LPDDR3.h /^ int nCKE, nXP; \/\/ CKE is PD, LPDDR3 has no DLL$/;" m struct:ramulator::LPDDR3::SpeedEntry +nCKE LPDDR4.h /^ int nCKE, nXP; \/\/ CKE value n\/a$/;" m struct:ramulator::LPDDR4::SpeedEntry +nCKE WideIO.h /^ int nCKE, nXP;$/;" m struct:ramulator::WideIO::SpeedEntry +nCKE WideIO2.h /^ int nCKE, nXP;$/;" m struct:ramulator::WideIO2::SpeedEntry +nCKESR ALDRAM.h /^ int nCKESR, nXS, nXSDLL;$/;" m struct:ramulator::ALDRAM::SpeedEntry +nCKESR DDR3.h /^ int nCKESR, nXS, nXSDLL;$/;" m struct:ramulator::DDR3::SpeedEntry +nCKESR DDR4.h /^ int nCKESR, nXS, nXSDLL; \/\/ nXSDLL TBD (nDLLK), nXS = (tRFC+10ns)\/tCK$/;" m struct:ramulator::DDR4::SpeedEntry +nCKESR DSARP.h /^ int nCKESR, nXS, nXSDLL;$/;" m struct:ramulator::DSARP::SpeedEntry +nCKESR GDDR5.h /^ int nCKESR, nXS, nXSDLL;$/;" m struct:ramulator::GDDR5::SpeedEntry +nCKESR HBM.h /^ int nCKESR, nXS;$/;" m struct:ramulator::HBM::SpeedEntry +nCKESR LPDDR3.h /^ int nCKESR, nXSR; \/\/ tXSR = tRFCab + 10ns$/;" m struct:ramulator::LPDDR3::SpeedEntry +nCKESR SALP.h /^ int nCKESR, nXS, nXSDLL;$/;" m struct:ramulator::SALP::SpeedEntry +nCKESR TLDRAM.h /^ int nCKESR, nXS, nXSDLL;$/;" m struct:ramulator::TLDRAM::SpeedEntry +nCKESR WideIO.h /^ int nCKESR, nXSR; \/\/ tXSR = tRFC+10$/;" m struct:ramulator::WideIO::SpeedEntry +nCKESR WideIO2.h /^ int nCKESR, nXSR;$/;" m struct:ramulator::WideIO2::SpeedEntry +nCL ALDRAM.h /^ int nCL, nRCD, nRP, nCWL;$/;" m struct:ramulator::ALDRAM::SpeedEntry +nCL DDR3.h /^ int nCL, nRCD, nRP, nCWL;$/;" m struct:ramulator::DDR3::SpeedEntry +nCL DDR4.h /^ int nCL, nRCD, nRP, nCWL;$/;" m struct:ramulator::DDR4::SpeedEntry +nCL DSARP.h /^ int nCL, nRCD, nRPpb, nRPab, nCWL;$/;" m struct:ramulator::DSARP::SpeedEntry +nCL GDDR5.h /^ int nCL, nRCDR, nRCDW, nRP, nCWL;$/;" m struct:ramulator::GDDR5::SpeedEntry +nCL HBM.h /^ int nCL, nRCDR, nRCDW, nRP, nCWL;$/;" m struct:ramulator::HBM::SpeedEntry +nCL LPDDR3.h /^ int nCL, nRCD, nRPpb, nRPab, nCWL;$/;" m struct:ramulator::LPDDR3::SpeedEntry +nCL LPDDR4.h /^ int nCL, nRCD, nRPpb, nRPab, nCWL;$/;" m struct:ramulator::LPDDR4::SpeedEntry +nCL SALP.h /^ int nCL, nRCD, nRP, nPA, nCWL; \/\/ nRP for pre2act same sa, nPA for pre2act diff sa (1 cycle)$/;" m struct:ramulator::SALP::SpeedEntry +nCL TLDRAM.h /^ int nCL, nRCD, nRP, nCWL;$/;" m struct:ramulator::TLDRAM::SpeedEntry +nCL WideIO.h /^ int nCL, nRCD, nRP, nCWL;$/;" m struct:ramulator::WideIO::SpeedEntry +nCL WideIO2.h /^ int nCL, nRCD, nRPpb, nRP8b, nRPab, nCWL;$/;" m struct:ramulator::WideIO2::SpeedEntry +nCWL ALDRAM.h /^ int nCL, nRCD, nRP, nCWL;$/;" m struct:ramulator::ALDRAM::SpeedEntry +nCWL DDR3.h /^ int nCL, nRCD, nRP, nCWL;$/;" m struct:ramulator::DDR3::SpeedEntry +nCWL DDR4.h /^ int nCL, nRCD, nRP, nCWL;$/;" m struct:ramulator::DDR4::SpeedEntry +nCWL DSARP.h /^ int nCL, nRCD, nRPpb, nRPab, nCWL;$/;" m struct:ramulator::DSARP::SpeedEntry +nCWL GDDR5.h /^ int nCL, nRCDR, nRCDW, nRP, nCWL;$/;" m struct:ramulator::GDDR5::SpeedEntry +nCWL HBM.h /^ int nCL, nRCDR, nRCDW, nRP, nCWL;$/;" m struct:ramulator::HBM::SpeedEntry +nCWL LPDDR3.h /^ int nCL, nRCD, nRPpb, nRPab, nCWL;$/;" m struct:ramulator::LPDDR3::SpeedEntry +nCWL LPDDR4.h /^ int nCL, nRCD, nRPpb, nRPab, nCWL;$/;" m struct:ramulator::LPDDR4::SpeedEntry +nCWL SALP.h /^ int nCL, nRCD, nRP, nPA, nCWL; \/\/ nRP for pre2act same sa, nPA for pre2act diff sa (1 cycle)$/;" m struct:ramulator::SALP::SpeedEntry +nCWL TLDRAM.h /^ int nCL, nRCD, nRP, nCWL;$/;" m struct:ramulator::TLDRAM::SpeedEntry +nCWL WideIO.h /^ int nCL, nRCD, nRP, nCWL;$/;" m struct:ramulator::WideIO::SpeedEntry +nCWL WideIO2.h /^ int nCL, nRCD, nRPpb, nRP8b, nRPab, nCWL;$/;" m struct:ramulator::WideIO2::SpeedEntry +nDQSCK LPDDR3.h /^ int nBL, nCCD, nRTRS, nDQSCK;$/;" m struct:ramulator::LPDDR3::SpeedEntry +nDQSCK LPDDR4.h /^ int nBL, nCCD, nRTRS, nDQSCK;$/;" m struct:ramulator::LPDDR4::SpeedEntry +nDQSCK WideIO.h /^ int nBL, nCCD, nDQSCK;$/;" m struct:ramulator::WideIO::SpeedEntry +nDQSCK WideIO2.h /^ int nBL, nCCD, nDQSCK, nRTRS; \/\/ 4n prefetch, DDR (although 8n is allowed?)$/;" m struct:ramulator::WideIO2::SpeedEntry +nFAW ALDRAM.h /^ int nRRD, nFAW;$/;" m struct:ramulator::ALDRAM::SpeedEntry +nFAW DDR3.h /^ int nRRD, nFAW;$/;" m struct:ramulator::DDR3::SpeedEntry +nFAW DDR4.h /^ int nRRDS, nRRDL, nFAW;$/;" m struct:ramulator::DDR4::SpeedEntry +nFAW DSARP.h /^ int nRRD, nFAW;$/;" m struct:ramulator::DSARP::SpeedEntry +nFAW GDDR5.h /^ int nRRD, nFAW, n32AW;$/;" m struct:ramulator::GDDR5::SpeedEntry +nFAW HBM.h /^ int nRRDS, nRRDL, nFAW;$/;" m struct:ramulator::HBM::SpeedEntry +nFAW LPDDR3.h /^ int nRRD, nFAW;$/;" m struct:ramulator::LPDDR3::SpeedEntry +nFAW LPDDR4.h /^ int nPPD, nRRD, nFAW;$/;" m struct:ramulator::LPDDR4::SpeedEntry +nFAW SALP.h /^ int nRRD, nFAW;$/;" m struct:ramulator::SALP::SpeedEntry +nFAW TLDRAM.h /^ int nRRD, nFAW;$/;" m struct:ramulator::TLDRAM::SpeedEntry +nFAW WideIO2.h /^ int nRRD, nFAW;$/;" m struct:ramulator::WideIO2::SpeedEntry +nLK GDDR5.h /^ int nPD, nXPN, nLK;$/;" m struct:ramulator::GDDR5::SpeedEntry +nPA SALP.h /^ int nCL, nRCD, nRP, nPA, nCWL; \/\/ nRP for pre2act same sa, nPA for pre2act diff sa (1 cycle)$/;" m struct:ramulator::SALP::SpeedEntry +nPD ALDRAM.h /^ int nPD, nXP, nXPDLL;$/;" m struct:ramulator::ALDRAM::SpeedEntry +nPD DDR3.h /^ int nPD, nXP, nXPDLL;$/;" m struct:ramulator::DDR3::SpeedEntry +nPD DDR4.h /^ int nPD, nXP, nXPDLL; \/\/ XPDLL not found in DDR4??$/;" m struct:ramulator::DDR4::SpeedEntry +nPD DSARP.h /^ int nPD, nXP, nXPDLL;$/;" m struct:ramulator::DSARP::SpeedEntry +nPD GDDR5.h /^ int nPD, nXPN, nLK;$/;" m struct:ramulator::GDDR5::SpeedEntry +nPD HBM.h /^ int nPD, nXP;$/;" m struct:ramulator::HBM::SpeedEntry +nPD SALP.h /^ int nPD, nXP, nXPDLL;$/;" m struct:ramulator::SALP::SpeedEntry +nPD TLDRAM.h /^ int nPD, nXP, nXPDLL;$/;" m struct:ramulator::TLDRAM::SpeedEntry +nPPD GDDR5.h /^ int nPPD, nRTP, nWTR, nWR;$/;" m struct:ramulator::GDDR5::SpeedEntry +nPPD LPDDR4.h /^ int nPPD, nRRD, nFAW;$/;" m struct:ramulator::LPDDR4::SpeedEntry +nRA SALP.h /^ int nRTP, nWTR, nWR, nRA, nWA; \/\/ nRA = nCL\/2, nWA = nCWL + nBL + nWR\/2$/;" m struct:ramulator::SALP::SpeedEntry +nRAS ALDRAM.h /^ int nRAS, nRC;$/;" m struct:ramulator::ALDRAM::SpeedEntry +nRAS DDR3.h /^ int nRAS, nRC;$/;" m struct:ramulator::DDR3::SpeedEntry +nRAS DDR4.h /^ int nRAS, nRC;$/;" m struct:ramulator::DDR4::SpeedEntry +nRAS DSARP.h /^ int nRAS, nRC;$/;" m struct:ramulator::DSARP::SpeedEntry +nRAS GDDR5.h /^ int nRAS, nRC;$/;" m struct:ramulator::GDDR5::SpeedEntry +nRAS HBM.h /^ int nRAS, nRC;$/;" m struct:ramulator::HBM::SpeedEntry +nRAS LPDDR3.h /^ int nRAS, nRC;$/;" m struct:ramulator::LPDDR3::SpeedEntry +nRAS LPDDR4.h /^ int nRAS, nRC;$/;" m struct:ramulator::LPDDR4::SpeedEntry +nRAS SALP.h /^ int nRAS, nRC;$/;" m struct:ramulator::SALP::SpeedEntry +nRAS TLDRAM.h /^ int nRAS, nRC;$/;" m struct:ramulator::TLDRAM::SpeedEntry +nRAS WideIO.h /^ int nRAS, nRC;$/;" m struct:ramulator::WideIO::SpeedEntry +nRAS WideIO2.h /^ int nRAS, nRC;$/;" m struct:ramulator::WideIO2::SpeedEntry +nRASF TLDRAM.h /^ int nRCDF, nRPF, nRASF, nRCF;$/;" m struct:ramulator::TLDRAM::SpeedEntry +nRASM TLDRAM.h /^ int nRCDM, nRPM, nRASM, nRCM;$/;" m struct:ramulator::TLDRAM::SpeedEntry +nRC ALDRAM.h /^ int nRAS, nRC;$/;" m struct:ramulator::ALDRAM::SpeedEntry +nRC DDR3.h /^ int nRAS, nRC;$/;" m struct:ramulator::DDR3::SpeedEntry +nRC DDR4.h /^ int nRAS, nRC;$/;" m struct:ramulator::DDR4::SpeedEntry +nRC DSARP.h /^ int nRAS, nRC;$/;" m struct:ramulator::DSARP::SpeedEntry +nRC GDDR5.h /^ int nRAS, nRC;$/;" m struct:ramulator::GDDR5::SpeedEntry +nRC HBM.h /^ int nRAS, nRC;$/;" m struct:ramulator::HBM::SpeedEntry +nRC LPDDR3.h /^ int nRAS, nRC;$/;" m struct:ramulator::LPDDR3::SpeedEntry +nRC LPDDR4.h /^ int nRAS, nRC;$/;" m struct:ramulator::LPDDR4::SpeedEntry +nRC SALP.h /^ int nRAS, nRC;$/;" m struct:ramulator::SALP::SpeedEntry +nRC TLDRAM.h /^ int nRAS, nRC;$/;" m struct:ramulator::TLDRAM::SpeedEntry +nRC WideIO.h /^ int nRAS, nRC;$/;" m struct:ramulator::WideIO::SpeedEntry +nRC WideIO2.h /^ int nRAS, nRC;$/;" m struct:ramulator::WideIO2::SpeedEntry +nRCD ALDRAM.h /^ int nCL, nRCD, nRP, nCWL;$/;" m struct:ramulator::ALDRAM::SpeedEntry +nRCD DDR3.h /^ int nCL, nRCD, nRP, nCWL;$/;" m struct:ramulator::DDR3::SpeedEntry +nRCD DDR4.h /^ int nCL, nRCD, nRP, nCWL;$/;" m struct:ramulator::DDR4::SpeedEntry +nRCD DSARP.h /^ int nCL, nRCD, nRPpb, nRPab, nCWL;$/;" m struct:ramulator::DSARP::SpeedEntry +nRCD LPDDR3.h /^ int nCL, nRCD, nRPpb, nRPab, nCWL;$/;" m struct:ramulator::LPDDR3::SpeedEntry +nRCD LPDDR4.h /^ int nCL, nRCD, nRPpb, nRPab, nCWL;$/;" m struct:ramulator::LPDDR4::SpeedEntry +nRCD SALP.h /^ int nCL, nRCD, nRP, nPA, nCWL; \/\/ nRP for pre2act same sa, nPA for pre2act diff sa (1 cycle)$/;" m struct:ramulator::SALP::SpeedEntry +nRCD TLDRAM.h /^ int nCL, nRCD, nRP, nCWL;$/;" m struct:ramulator::TLDRAM::SpeedEntry +nRCD WideIO.h /^ int nCL, nRCD, nRP, nCWL;$/;" m struct:ramulator::WideIO::SpeedEntry +nRCD WideIO2.h /^ int nCL, nRCD, nRPpb, nRP8b, nRPab, nCWL;$/;" m struct:ramulator::WideIO2::SpeedEntry +nRCDF TLDRAM.h /^ int nRCDF, nRPF, nRASF, nRCF;$/;" m struct:ramulator::TLDRAM::SpeedEntry +nRCDM TLDRAM.h /^ int nRCDM, nRPM, nRASM, nRCM;$/;" m struct:ramulator::TLDRAM::SpeedEntry +nRCDR GDDR5.h /^ int nCL, nRCDR, nRCDW, nRP, nCWL;$/;" m struct:ramulator::GDDR5::SpeedEntry +nRCDR HBM.h /^ int nCL, nRCDR, nRCDW, nRP, nCWL;$/;" m struct:ramulator::HBM::SpeedEntry +nRCDW GDDR5.h /^ int nCL, nRCDR, nRCDW, nRP, nCWL;$/;" m struct:ramulator::GDDR5::SpeedEntry +nRCDW HBM.h /^ int nCL, nRCDR, nRCDW, nRP, nCWL;$/;" m struct:ramulator::HBM::SpeedEntry +nRCF TLDRAM.h /^ int nRCDF, nRPF, nRASF, nRCF;$/;" m struct:ramulator::TLDRAM::SpeedEntry +nRCM TLDRAM.h /^ int nRCDM, nRPM, nRASM, nRCM;$/;" m struct:ramulator::TLDRAM::SpeedEntry +nREFI ALDRAM.h /^ int nRFC, nREFI;$/;" m struct:ramulator::ALDRAM::SpeedEntry +nREFI DDR3.h /^ int nRFC, nREFI;$/;" m struct:ramulator::DDR3::SpeedEntry +nREFI DDR4.h /^ int nRFC, nREFI;$/;" m struct:ramulator::DDR4::SpeedEntry +nREFI DSARP.h /^ int nRFCab, nRFCpb, nREFI, nREFIpb;$/;" m struct:ramulator::DSARP::SpeedEntry +nREFI GDDR5.h /^ int nRFC, nREFI;$/;" m struct:ramulator::GDDR5::SpeedEntry +nREFI HBM.h /^ int nRFC, nREFI, nREFI1B;$/;" m struct:ramulator::HBM::SpeedEntry +nREFI LPDDR3.h /^ int nRFCab, nRFCpb, nREFI;$/;" m struct:ramulator::LPDDR3::SpeedEntry +nREFI LPDDR4.h /^ int nRFCab, nRFCpb, nREFI;$/;" m struct:ramulator::LPDDR4::SpeedEntry +nREFI SALP.h /^ int nRFC, nREFI;$/;" m struct:ramulator::SALP::SpeedEntry +nREFI TLDRAM.h /^ int nRFC, nREFI;$/;" m struct:ramulator::TLDRAM::SpeedEntry +nREFI WideIO.h /^ int nRFC, nREFI;$/;" m struct:ramulator::WideIO::SpeedEntry +nREFI WideIO2.h /^ int nRFCab, nRFCpb, nREFI;$/;" m struct:ramulator::WideIO2::SpeedEntry +nREFI1B HBM.h /^ int nRFC, nREFI, nREFI1B;$/;" m struct:ramulator::HBM::SpeedEntry +nREFIpb DSARP.h /^ int nRFCab, nRFCpb, nREFI, nREFIpb;$/;" m struct:ramulator::DSARP::SpeedEntry +nRFC ALDRAM.h /^ int nRFC, nREFI;$/;" m struct:ramulator::ALDRAM::SpeedEntry +nRFC DDR3.h /^ int nRFC, nREFI;$/;" m struct:ramulator::DDR3::SpeedEntry +nRFC DDR4.h /^ int nRFC, nREFI;$/;" m struct:ramulator::DDR4::SpeedEntry +nRFC GDDR5.h /^ int nRFC, nREFI;$/;" m struct:ramulator::GDDR5::SpeedEntry +nRFC HBM.h /^ int nRFC, nREFI, nREFI1B;$/;" m struct:ramulator::HBM::SpeedEntry +nRFC SALP.h /^ int nRFC, nREFI;$/;" m struct:ramulator::SALP::SpeedEntry +nRFC TLDRAM.h /^ int nRFC, nREFI;$/;" m struct:ramulator::TLDRAM::SpeedEntry +nRFC WideIO.h /^ int nRFC, nREFI;$/;" m struct:ramulator::WideIO::SpeedEntry +nRFCab DSARP.h /^ int nRFCab, nRFCpb, nREFI, nREFIpb;$/;" m struct:ramulator::DSARP::SpeedEntry +nRFCab LPDDR3.h /^ int nRFCab, nRFCpb, nREFI;$/;" m struct:ramulator::LPDDR3::SpeedEntry +nRFCab LPDDR4.h /^ int nRFCab, nRFCpb, nREFI;$/;" m struct:ramulator::LPDDR4::SpeedEntry +nRFCab WideIO2.h /^ int nRFCab, nRFCpb, nREFI;$/;" m struct:ramulator::WideIO2::SpeedEntry +nRFCpb DSARP.h /^ int nRFCab, nRFCpb, nREFI, nREFIpb;$/;" m struct:ramulator::DSARP::SpeedEntry +nRFCpb LPDDR3.h /^ int nRFCab, nRFCpb, nREFI;$/;" m struct:ramulator::LPDDR3::SpeedEntry +nRFCpb LPDDR4.h /^ int nRFCab, nRFCpb, nREFI;$/;" m struct:ramulator::LPDDR4::SpeedEntry +nRFCpb WideIO2.h /^ int nRFCab, nRFCpb, nREFI;$/;" m struct:ramulator::WideIO2::SpeedEntry +nRP ALDRAM.h /^ int nCL, nRCD, nRP, nCWL;$/;" m struct:ramulator::ALDRAM::SpeedEntry +nRP DDR3.h /^ int nCL, nRCD, nRP, nCWL;$/;" m struct:ramulator::DDR3::SpeedEntry +nRP DDR4.h /^ int nCL, nRCD, nRP, nCWL;$/;" m struct:ramulator::DDR4::SpeedEntry +nRP GDDR5.h /^ int nCL, nRCDR, nRCDW, nRP, nCWL;$/;" m struct:ramulator::GDDR5::SpeedEntry +nRP HBM.h /^ int nCL, nRCDR, nRCDW, nRP, nCWL;$/;" m struct:ramulator::HBM::SpeedEntry +nRP SALP.h /^ int nCL, nRCD, nRP, nPA, nCWL; \/\/ nRP for pre2act same sa, nPA for pre2act diff sa (1 cycle)$/;" m struct:ramulator::SALP::SpeedEntry +nRP TLDRAM.h /^ int nCL, nRCD, nRP, nCWL;$/;" m struct:ramulator::TLDRAM::SpeedEntry +nRP WideIO.h /^ int nCL, nRCD, nRP, nCWL;$/;" m struct:ramulator::WideIO::SpeedEntry +nRP8b WideIO2.h /^ int nCL, nRCD, nRPpb, nRP8b, nRPab, nCWL;$/;" m struct:ramulator::WideIO2::SpeedEntry +nRPF TLDRAM.h /^ int nRCDF, nRPF, nRASF, nRCF;$/;" m struct:ramulator::TLDRAM::SpeedEntry +nRPM TLDRAM.h /^ int nRCDM, nRPM, nRASM, nRCM;$/;" m struct:ramulator::TLDRAM::SpeedEntry +nRPab DSARP.h /^ int nCL, nRCD, nRPpb, nRPab, nCWL;$/;" m struct:ramulator::DSARP::SpeedEntry +nRPab LPDDR3.h /^ int nCL, nRCD, nRPpb, nRPab, nCWL;$/;" m struct:ramulator::LPDDR3::SpeedEntry +nRPab LPDDR4.h /^ int nCL, nRCD, nRPpb, nRPab, nCWL;$/;" m struct:ramulator::LPDDR4::SpeedEntry +nRPab WideIO2.h /^ int nCL, nRCD, nRPpb, nRP8b, nRPab, nCWL;$/;" m struct:ramulator::WideIO2::SpeedEntry +nRPpb DSARP.h /^ int nCL, nRCD, nRPpb, nRPab, nCWL;$/;" m struct:ramulator::DSARP::SpeedEntry +nRPpb LPDDR3.h /^ int nCL, nRCD, nRPpb, nRPab, nCWL;$/;" m struct:ramulator::LPDDR3::SpeedEntry +nRPpb LPDDR4.h /^ int nCL, nRCD, nRPpb, nRPab, nCWL;$/;" m struct:ramulator::LPDDR4::SpeedEntry +nRPpb WideIO2.h /^ int nCL, nRCD, nRPpb, nRP8b, nRPab, nCWL;$/;" m struct:ramulator::WideIO2::SpeedEntry +nRRD ALDRAM.h /^ int nRRD, nFAW;$/;" m struct:ramulator::ALDRAM::SpeedEntry +nRRD DDR3.h /^ int nRRD, nFAW;$/;" m struct:ramulator::DDR3::SpeedEntry +nRRD DSARP.h /^ int nRRD, nFAW;$/;" m struct:ramulator::DSARP::SpeedEntry +nRRD GDDR5.h /^ int nRRD, nFAW, n32AW;$/;" m struct:ramulator::GDDR5::SpeedEntry +nRRD LPDDR3.h /^ int nRRD, nFAW;$/;" m struct:ramulator::LPDDR3::SpeedEntry +nRRD LPDDR4.h /^ int nPPD, nRRD, nFAW;$/;" m struct:ramulator::LPDDR4::SpeedEntry +nRRD SALP.h /^ int nRRD, nFAW;$/;" m struct:ramulator::SALP::SpeedEntry +nRRD TLDRAM.h /^ int nRRD, nFAW;$/;" m struct:ramulator::TLDRAM::SpeedEntry +nRRD WideIO.h /^ int nRRD, nTAW;$/;" m struct:ramulator::WideIO::SpeedEntry +nRRD WideIO2.h /^ int nRRD, nFAW;$/;" m struct:ramulator::WideIO2::SpeedEntry +nRRDL DDR4.h /^ int nRRDS, nRRDL, nFAW;$/;" m struct:ramulator::DDR4::SpeedEntry +nRRDL HBM.h /^ int nRRDS, nRRDL, nFAW;$/;" m struct:ramulator::HBM::SpeedEntry +nRRDS DDR4.h /^ int nRRDS, nRRDL, nFAW;$/;" m struct:ramulator::DDR4::SpeedEntry +nRRDS HBM.h /^ int nRRDS, nRRDL, nFAW;$/;" m struct:ramulator::HBM::SpeedEntry +nRRD_factor DSARP.h /^ double nRRD_factor = 1.138;$/;" m class:ramulator::DSARP +nRTP ALDRAM.h /^ int nRTP, nWTR, nWR;$/;" m struct:ramulator::ALDRAM::SpeedEntry +nRTP DDR3.h /^ int nRTP, nWTR, nWR;$/;" m struct:ramulator::DDR3::SpeedEntry +nRTP DDR4.h /^ int nRTP, nWTRS, nWTRL, nWR;$/;" m struct:ramulator::DDR4::SpeedEntry +nRTP DSARP.h /^ int nRTP, nWTR, nWR;$/;" m struct:ramulator::DSARP::SpeedEntry +nRTP GDDR5.h /^ int nPPD, nRTP, nWTR, nWR;$/;" m struct:ramulator::GDDR5::SpeedEntry +nRTP HBM.h /^ int nRTP, nWTRS, nWTRL, nWR;$/;" m struct:ramulator::HBM::SpeedEntry +nRTP LPDDR3.h /^ int nRTP, nWTR, nWR;$/;" m struct:ramulator::LPDDR3::SpeedEntry +nRTP LPDDR4.h /^ int nRTP, nWTR, nWR;$/;" m struct:ramulator::LPDDR4::SpeedEntry +nRTP SALP.h /^ int nRTP, nWTR, nWR, nRA, nWA; \/\/ nRA = nCL\/2, nWA = nCWL + nBL + nWR\/2$/;" m struct:ramulator::SALP::SpeedEntry +nRTP TLDRAM.h /^ int nRTP, nWTR, nWR;$/;" m struct:ramulator::TLDRAM::SpeedEntry +nRTP WideIO.h /^ int nRTP, nRTW, nWTR, nWR;$/;" m struct:ramulator::WideIO::SpeedEntry +nRTP WideIO2.h /^ int nRTP, nWTR, nWR;$/;" m struct:ramulator::WideIO2::SpeedEntry +nRTRS ALDRAM.h /^ int nBL, nCCD, nRTRS;$/;" m struct:ramulator::ALDRAM::SpeedEntry +nRTRS DDR3.h /^ int nBL, nCCD, nRTRS;$/;" m struct:ramulator::DDR3::SpeedEntry +nRTRS DDR4.h /^ int nBL, nCCDS, nCCDL, nRTRS;$/;" m struct:ramulator::DDR4::SpeedEntry +nRTRS DSARP.h /^ int nBL, nCCD, nRTRS;$/;" m struct:ramulator::DSARP::SpeedEntry +nRTRS LPDDR3.h /^ int nBL, nCCD, nRTRS, nDQSCK;$/;" m struct:ramulator::LPDDR3::SpeedEntry +nRTRS LPDDR4.h /^ int nBL, nCCD, nRTRS, nDQSCK;$/;" m struct:ramulator::LPDDR4::SpeedEntry +nRTRS SALP.h /^ int nBL, nCCD, nRTRS;$/;" m struct:ramulator::SALP::SpeedEntry +nRTRS TLDRAM.h /^ int nBL, nCCD, nRTRS;$/;" m struct:ramulator::TLDRAM::SpeedEntry +nRTRS WideIO2.h /^ int nBL, nCCD, nDQSCK, nRTRS; \/\/ 4n prefetch, DDR (although 8n is allowed?)$/;" m struct:ramulator::WideIO2::SpeedEntry +nRTW WideIO.h /^ int nRTP, nRTW, nWTR, nWR;$/;" m struct:ramulator::WideIO::SpeedEntry +nSCD SALP.h /^ int nSCD;$/;" m struct:ramulator::SALP::SpeedEntry +nSR LPDDR4.h /^ int nSR, nXSR; \/\/ tXSR = tRFCab + 7.5ns$/;" m struct:ramulator::LPDDR4::SpeedEntry +nTAW WideIO.h /^ int nRRD, nTAW;$/;" m struct:ramulator::WideIO::SpeedEntry +nWA SALP.h /^ int nRTP, nWTR, nWR, nRA, nWA; \/\/ nRA = nCL\/2, nWA = nCWL + nBL + nWR\/2$/;" m struct:ramulator::SALP::SpeedEntry +nWR ALDRAM.h /^ int nRTP, nWTR, nWR;$/;" m struct:ramulator::ALDRAM::SpeedEntry +nWR DDR3.h /^ int nRTP, nWTR, nWR;$/;" m struct:ramulator::DDR3::SpeedEntry +nWR DDR4.h /^ int nRTP, nWTRS, nWTRL, nWR;$/;" m struct:ramulator::DDR4::SpeedEntry +nWR DSARP.h /^ int nRTP, nWTR, nWR;$/;" m struct:ramulator::DSARP::SpeedEntry +nWR GDDR5.h /^ int nPPD, nRTP, nWTR, nWR;$/;" m struct:ramulator::GDDR5::SpeedEntry +nWR HBM.h /^ int nRTP, nWTRS, nWTRL, nWR;$/;" m struct:ramulator::HBM::SpeedEntry +nWR LPDDR3.h /^ int nRTP, nWTR, nWR;$/;" m struct:ramulator::LPDDR3::SpeedEntry +nWR LPDDR4.h /^ int nRTP, nWTR, nWR;$/;" m struct:ramulator::LPDDR4::SpeedEntry +nWR SALP.h /^ int nRTP, nWTR, nWR, nRA, nWA; \/\/ nRA = nCL\/2, nWA = nCWL + nBL + nWR\/2$/;" m struct:ramulator::SALP::SpeedEntry +nWR TLDRAM.h /^ int nRTP, nWTR, nWR;$/;" m struct:ramulator::TLDRAM::SpeedEntry +nWR WideIO.h /^ int nRTP, nRTW, nWTR, nWR;$/;" m struct:ramulator::WideIO::SpeedEntry +nWR WideIO2.h /^ int nRTP, nWTR, nWR;$/;" m struct:ramulator::WideIO2::SpeedEntry +nWTR ALDRAM.h /^ int nRTP, nWTR, nWR;$/;" m struct:ramulator::ALDRAM::SpeedEntry +nWTR DDR3.h /^ int nRTP, nWTR, nWR;$/;" m struct:ramulator::DDR3::SpeedEntry +nWTR DSARP.h /^ int nRTP, nWTR, nWR;$/;" m struct:ramulator::DSARP::SpeedEntry +nWTR GDDR5.h /^ int nPPD, nRTP, nWTR, nWR;$/;" m struct:ramulator::GDDR5::SpeedEntry +nWTR LPDDR3.h /^ int nRTP, nWTR, nWR;$/;" m struct:ramulator::LPDDR3::SpeedEntry +nWTR LPDDR4.h /^ int nRTP, nWTR, nWR;$/;" m struct:ramulator::LPDDR4::SpeedEntry +nWTR SALP.h /^ int nRTP, nWTR, nWR, nRA, nWA; \/\/ nRA = nCL\/2, nWA = nCWL + nBL + nWR\/2$/;" m struct:ramulator::SALP::SpeedEntry +nWTR TLDRAM.h /^ int nRTP, nWTR, nWR;$/;" m struct:ramulator::TLDRAM::SpeedEntry +nWTR WideIO.h /^ int nRTP, nRTW, nWTR, nWR;$/;" m struct:ramulator::WideIO::SpeedEntry +nWTR WideIO2.h /^ int nRTP, nWTR, nWR;$/;" m struct:ramulator::WideIO2::SpeedEntry +nWTRL DDR4.h /^ int nRTP, nWTRS, nWTRL, nWR;$/;" m struct:ramulator::DDR4::SpeedEntry +nWTRL HBM.h /^ int nRTP, nWTRS, nWTRL, nWR;$/;" m struct:ramulator::HBM::SpeedEntry +nWTRS DDR4.h /^ int nRTP, nWTRS, nWTRL, nWR;$/;" m struct:ramulator::DDR4::SpeedEntry +nWTRS HBM.h /^ int nRTP, nWTRS, nWTRL, nWR;$/;" m struct:ramulator::HBM::SpeedEntry +nXP ALDRAM.h /^ int nPD, nXP, nXPDLL;$/;" m struct:ramulator::ALDRAM::SpeedEntry +nXP DDR3.h /^ int nPD, nXP, nXPDLL;$/;" m struct:ramulator::DDR3::SpeedEntry +nXP DDR4.h /^ int nPD, nXP, nXPDLL; \/\/ XPDLL not found in DDR4??$/;" m struct:ramulator::DDR4::SpeedEntry +nXP DSARP.h /^ int nPD, nXP, nXPDLL;$/;" m struct:ramulator::DSARP::SpeedEntry +nXP HBM.h /^ int nPD, nXP;$/;" m struct:ramulator::HBM::SpeedEntry +nXP LPDDR3.h /^ int nCKE, nXP; \/\/ CKE is PD, LPDDR3 has no DLL$/;" m struct:ramulator::LPDDR3::SpeedEntry +nXP LPDDR4.h /^ int nCKE, nXP; \/\/ CKE value n\/a$/;" m struct:ramulator::LPDDR4::SpeedEntry +nXP SALP.h /^ int nPD, nXP, nXPDLL;$/;" m struct:ramulator::SALP::SpeedEntry +nXP TLDRAM.h /^ int nPD, nXP, nXPDLL;$/;" m struct:ramulator::TLDRAM::SpeedEntry +nXP WideIO.h /^ int nCKE, nXP;$/;" m struct:ramulator::WideIO::SpeedEntry +nXP WideIO2.h /^ int nCKE, nXP;$/;" m struct:ramulator::WideIO2::SpeedEntry +nXPDLL ALDRAM.h /^ int nPD, nXP, nXPDLL;$/;" m struct:ramulator::ALDRAM::SpeedEntry +nXPDLL DDR3.h /^ int nPD, nXP, nXPDLL;$/;" m struct:ramulator::DDR3::SpeedEntry +nXPDLL DDR4.h /^ int nPD, nXP, nXPDLL; \/\/ XPDLL not found in DDR4??$/;" m struct:ramulator::DDR4::SpeedEntry +nXPDLL DSARP.h /^ int nPD, nXP, nXPDLL;$/;" m struct:ramulator::DSARP::SpeedEntry +nXPDLL SALP.h /^ int nPD, nXP, nXPDLL;$/;" m struct:ramulator::SALP::SpeedEntry +nXPDLL TLDRAM.h /^ int nPD, nXP, nXPDLL;$/;" m struct:ramulator::TLDRAM::SpeedEntry +nXPN GDDR5.h /^ int nPD, nXPN, nLK;$/;" m struct:ramulator::GDDR5::SpeedEntry +nXS ALDRAM.h /^ int nCKESR, nXS, nXSDLL;$/;" m struct:ramulator::ALDRAM::SpeedEntry +nXS DDR3.h /^ int nCKESR, nXS, nXSDLL;$/;" m struct:ramulator::DDR3::SpeedEntry +nXS DDR4.h /^ int nCKESR, nXS, nXSDLL; \/\/ nXSDLL TBD (nDLLK), nXS = (tRFC+10ns)\/tCK$/;" m struct:ramulator::DDR4::SpeedEntry +nXS DSARP.h /^ int nCKESR, nXS, nXSDLL;$/;" m struct:ramulator::DSARP::SpeedEntry +nXS GDDR5.h /^ int nCKESR, nXS, nXSDLL;$/;" m struct:ramulator::GDDR5::SpeedEntry +nXS HBM.h /^ int nCKESR, nXS;$/;" m struct:ramulator::HBM::SpeedEntry +nXS SALP.h /^ int nCKESR, nXS, nXSDLL;$/;" m struct:ramulator::SALP::SpeedEntry +nXS TLDRAM.h /^ int nCKESR, nXS, nXSDLL;$/;" m struct:ramulator::TLDRAM::SpeedEntry +nXSDLL ALDRAM.h /^ int nCKESR, nXS, nXSDLL;$/;" m struct:ramulator::ALDRAM::SpeedEntry +nXSDLL DDR3.h /^ int nCKESR, nXS, nXSDLL;$/;" m struct:ramulator::DDR3::SpeedEntry +nXSDLL DDR4.h /^ int nCKESR, nXS, nXSDLL; \/\/ nXSDLL TBD (nDLLK), nXS = (tRFC+10ns)\/tCK$/;" m struct:ramulator::DDR4::SpeedEntry +nXSDLL DSARP.h /^ int nCKESR, nXS, nXSDLL;$/;" m struct:ramulator::DSARP::SpeedEntry +nXSDLL GDDR5.h /^ int nCKESR, nXS, nXSDLL;$/;" m struct:ramulator::GDDR5::SpeedEntry +nXSDLL SALP.h /^ int nCKESR, nXS, nXSDLL;$/;" m struct:ramulator::SALP::SpeedEntry +nXSDLL TLDRAM.h /^ int nCKESR, nXS, nXSDLL;$/;" m struct:ramulator::TLDRAM::SpeedEntry +nXSR LPDDR3.h /^ int nCKESR, nXSR; \/\/ tXSR = tRFCab + 10ns$/;" m struct:ramulator::LPDDR3::SpeedEntry +nXSR LPDDR4.h /^ int nSR, nXSR; \/\/ tXSR = tRFCab + 7.5ns$/;" m struct:ramulator::LPDDR4::SpeedEntry +nXSR WideIO.h /^ int nCKESR, nXSR; \/\/ tXSR = tRFC+10$/;" m struct:ramulator::WideIO::SpeedEntry +nXSR WideIO2.h /^ int nCKESR, nXSR;$/;" m struct:ramulator::WideIO2::SpeedEntry +n_sa DSARP.h /^ int n_sa;$/;" m class:ramulator::DSARP +n_sa SALP.h /^ int n_sa; \/\/ number of subarrays per bank$/;" m class:ramulator::SALP +name MemWrapper.h /^ std::string name;$/;" m class:MemWrapper +name StatType.h /^ Derived &name(const std::string &__name) {$/;" f class:Stats::Stat +name Statistics.h /^ StatBase & name(std::string _name) {$/;" f class:ramulator::StatBase +name Statistics.h /^ const std::string &name(void) const { return statName; }$/;" f class:ramulator::StatBase +name_to_func Gem5Wrapper.cpp /^static map > name_to_func = {$/;" v file: +name_to_translation Memory.h /^ std::map name_to_translation = {$/;" m class:ramulator::Memory +need_eviction Cache.cpp /^bool Cache::need_eviction(const std::list& lines, long addr) {$/;" f class:ramulator::Cache +next DRAM.h /^ long next[int(T::Command::MAX)]; \/\/ the earliest time in the future when a command could be ready$/;" m class:ramulator::DRAM +noNewMemReq MemWrapper.h /^ bool noNewMemReq; \/\/ It indicates if there are still requests coming from outside world. $/;" m class:MemWrapper +no_core_caches Processor.h /^ bool no_core_caches = true;$/;" m class:ramulator::Core +no_core_caches Processor.h /^ bool no_core_caches = true;$/;" m class:ramulator::Processor +no_shared_cache Processor.h /^ bool no_shared_cache = true;$/;" m class:ramulator::Core +no_shared_cache Processor.h /^ bool no_shared_cache = true;$/;" m class:ramulator::Processor +nonan StatType.h /^const uint16_t nonan = 0x00000200;$/;" m namespace:Stats +nozero StatType.h /^const uint16_t nozero = 0x00000100;$/;" m namespace:Stats +num_dram_cycles Memory.h /^ ScalarStat num_dram_cycles;$/;" m class:ramulator::Memory +num_incoming_requests Memory.h /^ ScalarStat num_incoming_requests;$/;" m class:ramulator::Memory +num_read_requests Memory.h /^ VectorStat num_read_requests;$/;" m class:ramulator::Memory +num_write_requests Memory.h /^ VectorStat num_write_requests;$/;" m class:ramulator::Memory +off_type StatType.h /^typedef unsigned int off_type;$/;" t namespace:Stats +opIdx Request.h /^ long opIdx; $/;" m class:ramulator::Request +opIdx common.h /^ long opIdx; \/\/ Memory operation index$/;" m struct:MemOp +opIdx pe.cpp /^long pe::opIdx = 0;$/;" m class:pe file: +opIdx pe.h /^ static long opIdx;$/;" m class:pe +opNum pe.h /^ int opNum;$/;" m class:pe +operator () SpeedyController.h /^ bool operator()(const Request& lhs, const Request& rhs) {$/;" f class:ramulator::SpeedyController::compair_depart_clk +operator () StatType.h /^ Result operator() (Result l, Result r) const {$/;" f class:Stats::Op +operator () StatType.h /^ Result operator() (Result r) const {$/;" f class:Stats::Op +operator ++ StatType.h /^ void operator ++ () { ++_value; }$/;" f class:Stats::ConstValue +operator ++ StatType.h /^ void operator ++ () { ++_value; }$/;" f class:Stats::Scalar +operator ++ StatType.h /^ void operator ++ () { inc(1); }$/;" f class:Stats::Average +operator ++ StatType.h /^ void operator ++ (int) { _value++; }$/;" f class:Stats::ConstValue +operator ++ StatType.h /^ void operator ++ (int) { _value++; }$/;" f class:Stats::Scalar +operator ++ StatType.h /^ void operator ++ (int) { inc(1); }$/;" f class:Stats::Average +operator ++ Statistics.h /^ void operator++() { ++StatBase::stat; }$/;" f class:ramulator::ScalarStatBase +operator ++ Statistics.h /^ void operator++(int) { StatBase::stat++; }$/;" f class:ramulator::ScalarStatBase +operator += StatType.h /^ void operator += (const U &v) { _value += v;}$/;" f class:Stats::ConstValue +operator += StatType.h /^ void operator += (const U &v) { _value += v;}$/;" f class:Stats::Scalar +operator += StatType.h /^ void operator += (const U &v) { inc(v);}$/;" f class:Stats::Average +operator += Statistics.h /^ void operator+=(const U &v) { StatBase::stat += v; }$/;" f class:ramulator::ScalarStatBase +operator -- StatType.h /^ void operator -- () { --_value; }$/;" f class:Stats::ConstValue +operator -- StatType.h /^ void operator -- () { --_value; }$/;" f class:Stats::Scalar +operator -- StatType.h /^ void operator -- () { dec(1); }$/;" f class:Stats::Average +operator -- StatType.h /^ void operator -- (int) { _value--; }$/;" f class:Stats::ConstValue +operator -- StatType.h /^ void operator -- (int) { _value--; }$/;" f class:Stats::Scalar +operator -- StatType.h /^ void operator -- (int) { dec(1); }$/;" f class:Stats::Average +operator -- Statistics.h /^ void operator--() { --StatBase::stat; }$/;" f class:ramulator::ScalarStatBase +operator -- Statistics.h /^ void operator--(int) { StatBase::stat--; }$/;" f class:ramulator::ScalarStatBase +operator -= StatType.h /^ void operator -= (const U &v) { _value -= v;}$/;" f class:Stats::ConstValue +operator -= StatType.h /^ void operator -= (const U &v) { _value -= v;}$/;" f class:Stats::Scalar +operator -= StatType.h /^ void operator -= (const U &v) { dec(v);}$/;" f class:Stats::Average +operator -= Statistics.h /^ void operator-=(const U &v) { StatBase::stat -= v; }$/;" f class:ramulator::ScalarStatBase +operator << common.cpp /^std::ostream& operator<< (std::ostream &os, const ramulator::Request::Type &type){$/;" f +operator << common.cpp /^std::ostream& operator<<(std::ostream &os, const MemOp &op){$/;" f +operator = StatType.h /^ void operator = (const U &v) { _value = v; }$/;" f class:Stats::ConstValue +operator = StatType.h /^ void operator = (const U &v) { _value = v; }$/;" f class:Stats::Scalar +operator = StatType.h /^ void operator = (const U &v) { set(v); }$/;" f class:Stats::Average +operator = StatType.h /^ void operator=(uint16_t _flags){flags = _flags;}$/;" f class:Stats::Flags +operator = Statistics.h /^ void operator=(const U &v) { StatBase::stat = v; }$/;" f class:ramulator::ScalarStatBase +operator = common.cpp /^MemOp& MemOp::operator=(const MemOp &op){ $/;" f class:MemOp +operator == common.cpp /^bool MemOp::operator==(const MemOp &op) const{$/;" f class:MemOp +operator [] Config.h /^ std::string operator [] (const std::string& name) const {$/;" f class:ramulator::Config +operator [] StatType.h /^ Element &operator[](off_type index) {$/;" f class:Stats::VectorBase +operator [] Statistics.h /^ Element &operator[](Stats::off_type index) { return StatBase::stat[index]; }$/;" f class:ramulator::VectorStatBase +operator [] Statistics.h /^ Stats::ScalarProxy operator[](Stats::off_type index) { return StatBase::stat[index]; }$/;" f class:ramulator::VectorStatBase +opstring StatType.h /^ std::string opstring;$/;" m class:Stats::Op +options Config.h /^ std::map options;$/;" m class:ramulator::Config +org_entry ALDRAM.h /^ }, org_entry;$/;" m class:ramulator::ALDRAM typeref:struct:ramulator::ALDRAM::OrgEntry +org_entry DDR3.h /^ }, org_entry;$/;" m class:ramulator::DDR3 typeref:struct:ramulator::DDR3::OrgEntry +org_entry DDR4.h /^ }, org_entry;$/;" m class:ramulator::DDR4 typeref:struct:ramulator::DDR4::OrgEntry +org_entry DSARP.h /^ }, org_entry;$/;" m class:ramulator::DSARP typeref:struct:ramulator::DSARP::OrgEntry +org_entry GDDR5.h /^ }, org_entry;$/;" m class:ramulator::GDDR5 typeref:struct:ramulator::GDDR5::OrgEntry +org_entry HBM.h /^ }, org_entry;$/;" m class:ramulator::HBM typeref:struct:ramulator::HBM::OrgEntry +org_entry LPDDR3.h /^ }, org_entry;$/;" m class:ramulator::LPDDR3 typeref:struct:ramulator::LPDDR3::OrgEntry +org_entry LPDDR4.h /^ }, org_entry;$/;" m class:ramulator::LPDDR4 typeref:struct:ramulator::LPDDR4::OrgEntry +org_entry SALP.h /^ }, org_entry;$/;" m class:ramulator::SALP typeref:struct:ramulator::SALP::OrgEntry +org_entry TLDRAM.h /^ }, org_entry;$/;" m class:ramulator::TLDRAM typeref:struct:ramulator::TLDRAM::OrgEntry +org_entry WideIO.h /^ }, org_entry;$/;" m class:ramulator::WideIO typeref:struct:ramulator::WideIO::OrgEntry +org_entry WideIO2.h /^ } org_entry;$/;" m class:ramulator::WideIO2 typeref:struct:ramulator::WideIO2::OrgEntry +org_map ALDRAM.cpp /^map ALDRAM::org_map = {$/;" m class:ALDRAM file: +org_map ALDRAM.h /^ static map org_map;$/;" m class:ramulator::ALDRAM +org_map DDR3.cpp /^map DDR3::org_map = {$/;" m class:DDR3 file: +org_map DDR3.h /^ static map org_map;$/;" m class:ramulator::DDR3 +org_map DDR4.cpp /^map DDR4::org_map = {$/;" m class:DDR4 file: +org_map DDR4.h /^ static map org_map;$/;" m class:ramulator::DDR4 +org_map DSARP.cpp /^map DSARP::org_map = {$/;" m class:DSARP file: +org_map DSARP.h /^ static map org_map;$/;" m class:ramulator::DSARP +org_map GDDR5.cpp /^map GDDR5::org_map = {$/;" m class:GDDR5 file: +org_map GDDR5.h /^ static map org_map;$/;" m class:ramulator::GDDR5 +org_map HBM.cpp /^map HBM::org_map = {$/;" m class:HBM file: +org_map HBM.h /^ static map org_map;$/;" m class:ramulator::HBM +org_map LPDDR3.cpp /^map LPDDR3::org_map = {$/;" m class:LPDDR3 file: +org_map LPDDR3.h /^ static map org_map;$/;" m class:ramulator::LPDDR3 +org_map LPDDR4.cpp /^map LPDDR4::org_map = {$/;" m class:LPDDR4 file: +org_map LPDDR4.h /^ static map org_map;$/;" m class:ramulator::LPDDR4 +org_map SALP.h /^ static map org_map;$/;" m class:ramulator::SALP +org_map TLDRAM.cpp /^map TLDRAM::org_map = {$/;" m class:TLDRAM file: +org_map TLDRAM.h /^ static map org_map;$/;" m class:ramulator::TLDRAM +org_map WideIO.cpp /^map WideIO::org_map = {$/;" m class:WideIO file: +org_map WideIO.h /^ static map org_map;$/;" m class:ramulator::WideIO +org_map WideIO2.cpp /^map WideIO2::org_map = {$/;" m class:WideIO2 file: +org_map WideIO2.h /^ static map org_map;$/;" m class:ramulator::WideIO2 +org_table ALDRAM.h /^ } org_table[int(Org::MAX)] = {$/;" m class:ramulator::ALDRAM typeref:struct:ramulator::ALDRAM::OrgEntry +org_table DDR3.h /^ } org_table[int(Org::MAX)] = {$/;" m class:ramulator::DDR3 typeref:struct:ramulator::DDR3::OrgEntry +org_table DDR4.h /^ } org_table[int(Org::MAX)] = {$/;" m class:ramulator::DDR4 typeref:struct:ramulator::DDR4::OrgEntry +org_table DSARP.h /^ } org_table[int(Org::MAX)] = {$/;" m class:ramulator::DSARP typeref:struct:ramulator::DSARP::OrgEntry +org_table GDDR5.h /^ } org_table[int(Org::MAX)] = {$/;" m class:ramulator::GDDR5 typeref:struct:ramulator::GDDR5::OrgEntry +org_table HBM.h /^ } org_table[int(Org::MAX)] = {$/;" m class:ramulator::HBM typeref:struct:ramulator::HBM::OrgEntry +org_table LPDDR3.h /^ } org_table[int(Org::MAX)] = {$/;" m class:ramulator::LPDDR3 typeref:struct:ramulator::LPDDR3::OrgEntry +org_table LPDDR4.h /^ } org_table[int(Org::MAX)] = {$/;" m class:ramulator::LPDDR4 typeref:struct:ramulator::LPDDR4::OrgEntry +org_table SALP.h /^ } org_table[int(Org::MAX)] = {$/;" m class:ramulator::SALP typeref:struct:ramulator::SALP::OrgEntry +org_table TLDRAM.h /^ } org_table[int(Org::MAX)] = {$/;" m class:ramulator::TLDRAM typeref:struct:ramulator::TLDRAM::OrgEntry +org_table WideIO.h /^ } org_table[int(Org::MAX)] = {$/;" m class:ramulator::WideIO typeref:struct:ramulator::WideIO::OrgEntry +otherq Controller.h /^ Queue otherq; \/\/ queue for all "other" requests (e.g., refresh)$/;" m class:ramulator::Controller +otherq SpeedyController.h /^ request_queue otherq; \/\/ queue for all "other" requests (e.g., refresh)$/;" m class:ramulator::SpeedyController +output StatType.h /^ void output(std::string filename) {$/;" f class:Stats::StatList +overflow StatType.h /^ Counter overflow;$/;" m class:Stats::Distribution +page_allocator Memory.h /^ long page_allocator(long addr, int coreid) {$/;" f class:ramulator::Memory +page_translation Memory.h /^ map, long> page_translation;$/;" m class:ramulator::Memory +param_bucket_size StatType.h /^ Counter param_bucket_size;$/;" m class:Stats::Distribution +param_buckets StatType.h /^ Counter param_buckets;$/;" m class:Stats::Distribution +param_buckets StatType.h /^ size_type param_buckets;$/;" m class:Stats::Histogram +param_max StatType.h /^ Counter param_max;$/;" m class:Stats::Distribution +param_min StatType.h /^ Counter param_min;$/;" m class:Stats::Distribution +parent DRAM.h /^ DRAM* parent;$/;" m class:ramulator::DRAM +parse Config.cpp /^void Config::parse(const string& fname)$/;" f class:Config +pdf StatType.h /^const uint16_t pdf = 0x00000020;$/;" m namespace:Stats +pe pe.cpp /^pe::pe(sc_module_name _name, int _peIdx, int _opNum) :sc_module(_name) {$/;" f class:pe +pe pe.h /^class pe : public sc_module{$/;" c +peClkCycle MemWrapper.h /^ int peClkCycle;$/;" m class:MemWrapper +peClkCycle pe.h /^ int peClkCycle;$/;" m class:pe +peIdx Request.h /^ int peIdx; $/;" m class:ramulator::Request +peIdx common.h /^ int peIdx; \/\/ peIdx which the memory request is issued from.$/;" m struct:MemOp +peIdx pe.h /^ int peIdx;$/;" m class:pe +pending Controller.h /^ deque pending; \/\/ read requests that are about to receive data from DRAM$/;" m class:ramulator::Controller +pending SpeedyController.h /^ priority_queue, compair_depart_clk> pending;$/;" m class:ramulator::SpeedyController +pending_requests Memory.h /^ int pending_requests()$/;" f class:ramulator::Memory +physical_page_replacement Memory.h /^ ScalarStat physical_page_replacement;$/;" m class:ramulator::Memory +policy Scheduler.h /^ function(typename T::Command)> policy[int(Type::MAX)] = {$/;" m class:ramulator::RowPolicy +populate_memory MemoryFactory.h /^ static Memory *populate_memory(const Config& configs, T *spec, int channels, int ranks) {$/;" f class:ramulator::MemoryFactory +precision StatType.h /^ Derived &precision(int __precision) {$/;" f class:Stats::Stat +precision Statistics.h /^ StatBase & precision(int _precision) {$/;" f class:ramulator::StatBase +prefetch_size ALDRAM.h /^ int prefetch_size = 8; \/\/ 8n prefetch DDR$/;" m class:ramulator::ALDRAM +prefetch_size DDR3.h /^ int prefetch_size = 8; \/\/ 8n prefetch DDR$/;" m class:ramulator::DDR3 +prefetch_size DDR4.h /^ int prefetch_size = 8; \/\/ 8n prefetch DDR$/;" m class:ramulator::DDR4 +prefetch_size DSARP.h /^ int prefetch_size = 16; \/\/ 16n prefetch DDR$/;" m class:ramulator::DSARP +prefetch_size GDDR5.h /^ int prefetch_size = 8; \/\/ 8n prefetch QDR$/;" m class:ramulator::GDDR5 +prefetch_size HBM.h /^ int prefetch_size = 4; \/\/ burst length could be 2 and 4 (choose 4 here), 2n prefetch$/;" m class:ramulator::HBM +prefetch_size LPDDR3.h /^ int prefetch_size = 8; \/\/ 16n prefetch DDR$/;" m class:ramulator::LPDDR3 +prefetch_size LPDDR4.h /^ int prefetch_size = 16; \/\/ 16n prefetch DDR$/;" m class:ramulator::LPDDR4 +prefetch_size SALP.h /^ int prefetch_size = 8; \/\/ 8n prefetch DDR$/;" m class:ramulator::SALP +prefetch_size TLDRAM.h /^ int prefetch_size = 8; \/\/ 8n prefetch DDR$/;" m class:ramulator::TLDRAM +prefetch_size WideIO.h /^ int prefetch_size = 4; \/\/ 4n prefetch SDR$/;" m class:ramulator::WideIO +prefetch_size WideIO2.h /^ int prefetch_size = 4;$/;" m class:ramulator::WideIO2 +prepare StatType.h /^ void prepare() {$/;" f class:Stats::Average +prepare StatType.h /^ void prepare() {$/;" f class:Stats::VectorBase +prepare StatType.h /^ void prepare() {}$/;" f class:Stats::AverageDeviation +prepare StatType.h /^ void prepare() {}$/;" f class:Stats::ConstValue +prepare StatType.h /^ void prepare() {}$/;" f class:Stats::Histogram +prepare StatType.h /^ void prepare() {}$/;" f class:Stats::Scalar +prepare StatType.h /^ void prepare() {}$/;" f class:Stats::StandardDeviation +prepare StatType.h /^ void prepare() {};$/;" f class:Stats::Distribution +prepare Statistics.h /^ void prepare(void) { stat.prepare(); }$/;" f class:ramulator::StatBase +prereq ALDRAM.h /^ function*, Command cmd, int)> prereq[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::ALDRAM +prereq DDR3.h /^ function*, Command cmd, int)> prereq[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::DDR3 +prereq DDR4.h /^ function*, Command cmd, int)> prereq[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::DDR4 +prereq DRAM.h /^ function*, typename T::Command cmd, int)>* prereq;$/;" m class:ramulator::DRAM +prereq DSARP.h /^ function*, Command cmd, int)> prereq[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::DSARP +prereq GDDR5.h /^ function*, Command cmd, int)> prereq[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::GDDR5 +prereq HBM.h /^ function*, Command cmd, int)> prereq[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::HBM +prereq LPDDR3.h /^ function*, Command cmd, int)> prereq[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::LPDDR3 +prereq LPDDR4.h /^ function*, Command cmd, int)> prereq[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::LPDDR4 +prereq SALP.h /^ function*, Command cmd, int)> prereq[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::SALP +prereq StatType.h /^ Derived &prereq(const GenericStat & prereq) {$/;" f class:Stats::Stat +prereq Statistics.h /^ StatBase & prereq(const Stat & _prereq) {$/;" f class:ramulator::StatBase +prereq TLDRAM.h /^ function*, Command cmd, int)> prereq[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::TLDRAM +prereq WideIO.h /^ function*, Command cmd, int)> prereq[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::WideIO +prereq WideIO2.h /^ function*, Command cmd, int)> prereq[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::WideIO2 +prev DRAM.h /^ deque prev[int(T::Command::MAX)]; \/\/ the most recent history of when commands were issued$/;" m class:ramulator::DRAM +print StatType.h /^ virtual void print(std::ofstream& file) {$/;" f class:Stats::ScalarBase +print StatType.h /^ virtual void print(std::ofstream& file) {};$/;" f class:Stats::Stat +print StatType.h /^ void print(std::ofstream& file) {$/;" f class:Stats::VectorBase +print_cmd_trace Config.h /^ bool print_cmd_trace() const {$/;" f class:ramulator::Config +print_cmd_trace Controller.h /^ bool print_cmd_trace = false;$/;" m class:ramulator::Controller +print_cmd_trace SpeedyController.h /^ bool print_cmd_trace = false;$/;" m class:ramulator::SpeedyController +printall StatType.h /^ void printall() {$/;" f class:Stats::StatList +printdesc StatType.h /^ virtual void printdesc(std::ofstream& file) {$/;" f class:Stats::Stat +printname StatType.h /^ virtual void printname(std::ofstream& file) {$/;" f class:Stats::Stat +q Controller.h /^ list q;$/;" m struct:ramulator::Controller::Queue +queue_capacity SpeedyController.h /^ const unsigned int queue_capacity = 32;$/;" m class:ramulator::SpeedyController +ramData MemWrapper.h /^ int32_t *ramData; \/\/ word level memory data management.$/;" m class:MemWrapper +ramulator ALDRAM.h /^namespace ramulator$/;" n +ramulator Cache.cpp /^namespace ramulator$/;" n file: +ramulator Cache.h /^namespace ramulator$/;" n +ramulator Config.h /^namespace ramulator$/;" n +ramulator Controller.cpp /^namespace ramulator$/;" n file: +ramulator Controller.h /^namespace ramulator$/;" n +ramulator DDR3.h /^namespace ramulator$/;" n +ramulator DDR4.h /^namespace ramulator$/;" n +ramulator DRAM.h /^namespace ramulator$/;" n +ramulator DSARP.h /^namespace ramulator$/;" n +ramulator GDDR5.h /^namespace ramulator$/;" n +ramulator Gem5Wrapper.h /^namespace ramulator$/;" n +ramulator HBM.h /^namespace ramulator$/;" n +ramulator LPDDR3.h /^namespace ramulator$/;" n +ramulator LPDDR4.h /^namespace ramulator$/;" n +ramulator Memory.h /^namespace ramulator$/;" n +ramulator MemoryFactory.cpp /^namespace ramulator$/;" n file: +ramulator MemoryFactory.h /^namespace ramulator$/;" n +ramulator Processor.h /^namespace ramulator $/;" n +ramulator Refresh.cpp /^namespace ramulator {$/;" n file: +ramulator Refresh.h /^namespace ramulator {$/;" n +ramulator Request.h /^namespace ramulator$/;" n +ramulator SALP.h /^namespace ramulator$/;" n +ramulator Scheduler.h /^namespace ramulator$/;" n +ramulator SpeedyController.h /^namespace ramulator$/;" n +ramulator StatType.h /^namespace ramulator {$/;" n +ramulator Statistics.h /^namespace ramulator {$/;" n +ramulator TLDRAM.h /^namespace ramulator$/;" n +ramulator WideIO.h /^namespace ramulator$/;" n +ramulator WideIO2.h /^namespace ramulator$/;" n +ramulator_active_cycles Memory.h /^ ScalarStat ramulator_active_cycles;$/;" m class:ramulator::Memory +ranks Config.h /^ int ranks;$/;" m class:ramulator::Config +rate ALDRAM.h /^ int rate;$/;" m struct:ramulator::ALDRAM::SpeedEntry +rate DDR3.h /^ int rate;$/;" m struct:ramulator::DDR3::SpeedEntry +rate DDR4.h /^ int rate;$/;" m struct:ramulator::DDR4::SpeedEntry +rate DSARP.h /^ int rate;$/;" m struct:ramulator::DSARP::SpeedEntry +rate GDDR5.h /^ int rate;$/;" m struct:ramulator::GDDR5::SpeedEntry +rate HBM.h /^ int rate;$/;" m struct:ramulator::HBM::SpeedEntry +rate LPDDR3.h /^ int rate;$/;" m struct:ramulator::LPDDR3::SpeedEntry +rate LPDDR4.h /^ int rate;$/;" m struct:ramulator::LPDDR4::SpeedEntry +rate SALP.h /^ int rate;$/;" m struct:ramulator::SALP::SpeedEntry +rate TLDRAM.h /^ int rate;$/;" m struct:ramulator::TLDRAM::SpeedEntry +rate WideIO.h /^ int rate;$/;" m struct:ramulator::WideIO::SpeedEntry +rate WideIO2.h /^ int rate;$/;" m struct:ramulator::WideIO2::SpeedEntry +reached_limit Processor.h /^ bool reached_limit = false;$/;" m class:ramulator::Core +read_latency ALDRAM.h /^ int read_latency;$/;" m class:ramulator::ALDRAM +read_latency DDR3.h /^ int read_latency;$/;" m class:ramulator::DDR3 +read_latency DDR4.h /^ int read_latency;$/;" m class:ramulator::DDR4 +read_latency DSARP.h /^ int read_latency;$/;" m class:ramulator::DSARP +read_latency GDDR5.h /^ int read_latency;$/;" m class:ramulator::GDDR5 +read_latency HBM.h /^ int read_latency;$/;" m class:ramulator::HBM +read_latency LPDDR3.h /^ int read_latency;$/;" m class:ramulator::LPDDR3 +read_latency LPDDR4.h /^ int read_latency;$/;" m class:ramulator::LPDDR4 +read_latency SALP.h /^ int read_latency;$/;" m class:ramulator::SALP +read_latency TLDRAM.h /^ int read_latency;$/;" m class:ramulator::TLDRAM +read_latency WideIO.h /^ int read_latency;$/;" m class:ramulator::WideIO +read_latency WideIO2.h /^ int read_latency;$/;" m class:ramulator::WideIO2 +read_latency_avg Controller.h /^ ScalarStat read_latency_avg;$/;" m class:ramulator::Controller +read_latency_sum Controller.h /^ ScalarStat read_latency_sum;$/;" m class:ramulator::Controller +read_req_queue_length_avg Controller.h /^ ScalarStat read_req_queue_length_avg;$/;" m class:ramulator::Controller +read_req_queue_length_sum Controller.h /^ ScalarStat read_req_queue_length_sum;$/;" m class:ramulator::Controller +read_row_conflicts Controller.h /^ VectorStat read_row_conflicts;$/;" m class:ramulator::Controller +read_row_hits Controller.h /^ VectorStat read_row_hits;$/;" m class:ramulator::Controller +read_row_misses Controller.h /^ VectorStat read_row_misses;$/;" m class:ramulator::Controller +read_transaction_bytes Controller.h /^ ScalarStat read_transaction_bytes;$/;" m class:ramulator::Controller +readq Controller.h /^ Queue readq; \/\/ queue for read requests$/;" m class:ramulator::Controller +readq SpeedyController.h /^ request_queue readq; \/\/ queue for read requests$/;" m class:ramulator::SpeedyController +ready_list Processor.h /^ std::vector ready_list;$/;" m class:ramulator::Window +receive Processor.cpp /^void Core::receive(Request& req)$/;" f class:Core +receive Processor.cpp /^void Processor::receive(Request& req) {$/;" f class:Processor +record_cmd_trace Config.h /^ bool record_cmd_trace() const {$/;" f class:ramulator::Config +record_cmd_trace Controller.h /^ bool record_cmd_trace = false;$/;" m class:ramulator::Controller +record_cmd_trace SpeedyController.h /^ bool record_cmd_trace = false;$/;" m class:ramulator::SpeedyController +record_core Controller.h /^ void record_core(int coreid) {$/;" f class:ramulator::Controller +record_core Memory.h /^ void record_core(int coreid) {$/;" f class:ramulator::Memory +record_cycs Processor.h /^ ScalarStat record_cycs;$/;" m class:ramulator::Core +record_insts Processor.h /^ ScalarStat record_insts;$/;" m class:ramulator::Core +record_read_conflicts Controller.h /^ VectorStat record_read_conflicts;$/;" m class:ramulator::Controller +record_read_hits Controller.h /^ VectorStat record_read_hits;$/;" m class:ramulator::Controller +record_read_misses Controller.h /^ VectorStat record_read_misses;$/;" m class:ramulator::Controller +record_read_requests Memory.h /^ VectorStat record_read_requests;$/;" m class:ramulator::Memory +record_write_conflicts Controller.h /^ VectorStat record_write_conflicts;$/;" m class:ramulator::Controller +record_write_hits Controller.h /^ VectorStat record_write_hits;$/;" m class:ramulator::Controller +record_write_misses Controller.h /^ VectorStat record_write_misses;$/;" m class:ramulator::Controller +record_write_requests Memory.h /^ VectorStat record_write_requests;$/;" m class:ramulator::Memory +refresh Controller.h /^ Refresh* refresh;$/;" m class:ramulator::Controller +refresh_cycles DRAM.h /^ ScalarStat refresh_cycles;$/;" m class:ramulator::DRAM +refresh_intervals DRAM.h /^ std::vector> refresh_intervals;$/;" m class:ramulator::DRAM +refresh_mode DDR4.h /^ } refresh_mode = RefreshMode::Refresh_1X;$/;" m class:ramulator::DDR4 typeref:class:ramulator::DDR4::RefreshMode +refresh_mode DSARP.h /^ } refresh_mode = RefreshMode::Refresh_1X;$/;" m class:ramulator::DSARP typeref:class:ramulator::DSARP::RefreshMode +refresh_mode LPDDR4.h /^ } refresh_mode = RefreshMode::Refresh_1X;$/;" m class:ramulator::LPDDR4 typeref:class:ramulator::LPDDR4::RefreshMode +refresh_target Refresh.h /^ void refresh_target(Controller* ctrl, int rank, int bank, int sa)$/;" f class:ramulator::Refresh +refreshed Refresh.h /^ long clk, refreshed;$/;" m class:ramulator::Refresh +refreshed SpeedyController.h /^ long refreshed = 0; \/\/ last time refresh requests were generated$/;" m class:ramulator::SpeedyController +regStats DRAM.h /^void DRAM::regStats(const std::string& identifier) {$/;" f class:ramulator::DRAM +reqCounter MemWrapper.h /^ long reqCounter;$/;" m class:MemWrapper +reqNum Request.h /^ int reqNum;$/;" m class:ramulator::Request +reqNum common.h /^ int reqNum;$/;" m struct:MemOp +req_addr Processor.h /^ long req_addr = -1;$/;" m class:ramulator::Core +req_queue_length_avg Controller.h /^ ScalarStat req_queue_length_avg;$/;" m class:ramulator::Controller +req_queue_length_sum Controller.h /^ ScalarStat req_queue_length_sum;$/;" m class:ramulator::Controller +req_type Processor.h /^ Request::Type req_type;$/;" m class:ramulator::Core +request_info SpeedyController.h /^ typedef tuple request_info;$/;" t class:ramulator::SpeedyController +request_queue SpeedyController.h /^ typedef vector request_queue;$/;" t class:ramulator::SpeedyController +reset StatType.h /^ void reset() {$/;" f class:Stats::Average +reset StatType.h /^ void reset() {$/;" f class:Stats::AverageDeviation +reset StatType.h /^ void reset() {$/;" f class:Stats::Distribution +reset StatType.h /^ void reset() {$/;" f class:Stats::Histogram +reset StatType.h /^ void reset() {$/;" f class:Stats::StandardDeviation +reset StatType.h /^ void reset() {$/;" f class:Stats::VectorBase +reset StatType.h /^ void reset() {_value = Counter();}$/;" f class:Stats::Scalar +reset StatType.h /^ void reset() {}$/;" f class:Stats::ConstValue +reset Statistics.h /^ void reset(void) { stat.reset(); }$/;" f class:ramulator::StatBase +respCounter MemWrapper.h /^ long respCounter;$/;" m class:MemWrapper +result StatType.h /^ Result result() const {$/;" f class:Stats::Average +result StatType.h /^ Result result() const {return (Result)_value;}$/;" f class:Stats::ConstValue +result StatType.h /^ Result result() const {return (Result)_value;}$/;" f class:Stats::Scalar +result StatType.h /^ void result(VResult& vec) const {$/;" f class:Stats::VectorBase +result Statistics.h /^ void result(Stats::VResult & vec) const { StatBase::stat.result(vec); }$/;" f class:ramulator::VectorStatBase +retire Processor.cpp /^long Window::retire()$/;" f class:Window +retired Processor.h /^ long retired = 0;$/;" m class:ramulator::Core +row Scheduler.h /^ int row;$/;" m struct:ramulator::RowTable::Entry +row_conflicts Controller.h /^ ScalarStat row_conflicts;$/;" m class:ramulator::Controller +row_hits Controller.h /^ ScalarStat row_hits;$/;" m class:ramulator::Controller +row_hits SpeedyController.h /^ ScalarStat row_hits;$/;" m class:ramulator::SpeedyController +row_misses Controller.h /^ ScalarStat row_misses;$/;" m class:ramulator::Controller +row_misses SpeedyController.h /^ ScalarStat row_misses;$/;" m class:ramulator::SpeedyController +row_state DRAM.h /^ map row_state;$/;" m class:ramulator::DRAM +rowhit ALDRAM.h /^ function*, Command cmd, int)> rowhit[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::ALDRAM +rowhit DDR3.h /^ function*, Command cmd, int)> rowhit[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::DDR3 +rowhit DDR4.h /^ function*, Command cmd, int)> rowhit[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::DDR4 +rowhit DRAM.h /^ function*, typename T::Command cmd, int)>* rowhit;$/;" m class:ramulator::DRAM +rowhit DSARP.h /^ function*, Command cmd, int)> rowhit[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::DSARP +rowhit GDDR5.h /^ function*, Command cmd, int)> rowhit[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::GDDR5 +rowhit HBM.h /^ function*, Command cmd, int)> rowhit[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::HBM +rowhit LPDDR3.h /^ function*, Command cmd, int)> rowhit[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::LPDDR3 +rowhit LPDDR4.h /^ function*, Command cmd, int)> rowhit[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::LPDDR4 +rowhit SALP.h /^ function*, Command cmd, int)> rowhit[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::SALP +rowhit TLDRAM.h /^ function*, Command cmd, int)> rowhit[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::TLDRAM +rowhit WideIO.h /^ function*, Command cmd, int)> rowhit[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::WideIO +rowhit WideIO2.h /^ function*, Command cmd, int)> rowhit[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::WideIO2 +rowopen ALDRAM.h /^ function*, Command cmd, int)> rowopen[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::ALDRAM +rowopen DDR3.h /^ function*, Command cmd, int)> rowopen[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::DDR3 +rowopen DDR4.h /^ function*, Command cmd, int)> rowopen[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::DDR4 +rowopen DRAM.h /^ function*, typename T::Command cmd, int)>* rowopen;$/;" m class:ramulator::DRAM +rowopen DSARP.h /^ function*, Command cmd, int)> rowopen[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::DSARP +rowopen GDDR5.h /^ function*, Command cmd, int)> rowopen[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::GDDR5 +rowopen HBM.h /^ function*, Command cmd, int)> rowopen[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::HBM +rowopen LPDDR3.h /^ function*, Command cmd, int)> rowopen[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::LPDDR3 +rowopen LPDDR4.h /^ function*, Command cmd, int)> rowopen[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::LPDDR4 +rowopen SALP.h /^ function*, Command cmd, int)> rowopen[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::SALP +rowopen TLDRAM.h /^ function*, Command cmd, int)> rowopen[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::TLDRAM +rowopen WideIO.h /^ function*, Command cmd, int)> rowopen[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::WideIO +rowopen WideIO2.h /^ function*, Command cmd, int)> rowopen[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::WideIO2 +rowpolicy Controller.h /^ RowPolicy* rowpolicy; \/\/ determines the row-policy (e.g., closed-row vs. open-row)$/;" m class:ramulator::Controller +rowtable Controller.h /^ RowTable* rowtable; \/\/ tracks metadata about rows (e.g., which are open and for how long)$/;" m class:ramulator::Controller +runMemSim MemWrapper.cpp /^void MemWrapper::runMemSim(){$/;" f class:MemWrapper +run_acc MemWrapper.cpp /^void MemWrapper::run_acc(const Config& configs, Memory& memory) {$/;" f class:MemWrapper +sample StatType.cpp /^Histogram::sample(Counter val, int number)$/;" f class:Stats::Histogram +sample StatType.h /^ void sample(Counter val, int number) {$/;" f class:Stats::AverageDeviation +sample StatType.h /^ void sample(Counter val, int number) {$/;" f class:Stats::Distribution +sample StatType.h /^ void sample(Counter val, int number) {$/;" f class:Stats::StandardDeviation +sample Statistics.h /^ void sample(const U &v, int n = 1) { StatBase::stat.sample(v, n); }$/;" f class:ramulator::DistStatBase +samples StatType.h /^ Counter samples;$/;" m class:Stats::Distribution +samples StatType.h /^ Counter samples;$/;" m class:Stats::Histogram +samples StatType.h /^ Counter samples;$/;" m class:Stats::StandardDeviation +sc_main Main.cpp /^int sc_main(int argc, char *argv[]){$/;" f +sc_trace common.cpp /^void sc_trace(sc_trace_file *tf, const MemOp &op, const std::string &name){$/;" f +schedule SpeedyController.h /^ void schedule(request_queue& q){$/;" f class:ramulator::SpeedyController +scheduler Controller.h /^ Scheduler* scheduler; \/\/ determines the highest priority request whose commands will be issued$/;" m class:ramulator::Controller +scope ALDRAM.h /^ Level scope[int(Command::MAX)] = {$/;" m class:ramulator::ALDRAM +scope DDR3.h /^ Level scope[int(Command::MAX)] = {$/;" m class:ramulator::DDR3 +scope DDR4.h /^ Level scope[int(Command::MAX)] = {$/;" m class:ramulator::DDR4 +scope DSARP.h /^ Level scope[int(Command::MAX)] = {$/;" m class:ramulator::DSARP +scope GDDR5.h /^ Level scope[int(Command::MAX)] = {$/;" m class:ramulator::GDDR5 +scope HBM.h /^ Level scope[int(Command::MAX)] = {$/;" m class:ramulator::HBM +scope LPDDR3.h /^ Level scope[int(Command::MAX)] = {$/;" m class:ramulator::LPDDR3 +scope LPDDR4.h /^ Level scope[int(Command::MAX)] = {$/;" m class:ramulator::LPDDR4 +scope SALP.h /^ Level scope[int(Command::MAX)] = {$/;" m class:ramulator::SALP +scope TLDRAM.h /^ Level scope[int(Command::MAX)] = {$/;" m class:ramulator::TLDRAM +scope WideIO.h /^ Level scope[int(Command::MAX)] = {$/;" m class:ramulator::WideIO +scope WideIO2.h /^ Level scope[int(Command::MAX)] = {$/;" m class:ramulator::WideIO2 +segment_ratio TLDRAM.h /^ int segment_ratio = 16;$/;" m class:ramulator::TLDRAM +self StatType.h /^ Derived &self() {return *static_cast(this);}$/;" f class:Stats::Stat +self Statistics.h /^ DistributionStat & self() { return *this; }$/;" f class:ramulator::DistributionStat +self Statistics.h /^ HistogramStat & self() { return *this; }$/;" f class:ramulator::HistogramStat +self Statistics.h /^ StatBase & self() { return *this; }$/;" f class:ramulator::StatBase +self Statistics.h /^ StatBaseVec & self() { return *this; }$/;" f class:ramulator::StatBaseVec +self Statistics.h /^ VectorStatBase & self() { return *this; }$/;" f class:ramulator::VectorStatBase +selfptr StatType.h /^ Derived *selfptr() {return static_cast(this);}$/;" f class:Stats::Stat +send Cache.cpp /^bool Cache::send(Request req) {$/;" f class:ramulator::Cache +send Gem5Wrapper.cpp /^bool Gem5Wrapper::send(Request req)$/;" f class:Gem5Wrapper +send Memory.h /^ bool send(Request req)$/;" f class:ramulator::Memory +send Processor.h /^ function send;$/;" m class:ramulator::Core +sendMemReq pe.cpp /^void pe::sendMemReq(){ $/;" f class:pe +sendResp MemWrapper.cpp /^void MemWrapper::sendResp(){$/;" f class:MemWrapper +send_memory Cache.h /^ std::function send_memory;$/;" m class:ramulator::CacheSystem +separatorString StatType.h /^ std::string separatorString;$/;" m class:Stats::Stat +serving_requests DRAM.h /^ ScalarStat serving_requests;$/;" m class:ramulator::DRAM +set StatType.h /^ void set(Counter val) {$/;" f class:Stats::Average +setArriveMemTime common.cpp /^void MemOp::setArriveMemTime(long arriveTime){$/;" f class:MemOp +setArrivePeTime common.cpp /^void MemOp::setArrivePeTime(long arriveTime){$/;" f class:MemOp +setDepartMemTime common.cpp /^void MemOp::setDepartMemTime(long departTime){$/;" f class:MemOp +setDepartPeTime common.cpp /^void MemOp::setDepartPeTime(long departTime){$/;" f class:MemOp +setOpNum pe.cpp /^void pe::setOpNum(int _opNum){$/;" f class:pe +setPeClkCycle pe.cpp /^void pe::setPeClkCycle(int _peClkCycle){$/;" f class:pe +setSeparator StatType.h /^ Derived &setSeparator(std::string str) {$/;" f class:Stats::Stat +setSeparator StatType.h /^ const std::string& setSeparator() const {return separatorString;}$/;" f class:Stats::Stat +setSeparator Statistics.h /^ StatBase & setSeparator(const std::string & _sep) {$/;" f class:ramulator::StatBase +setSeparator Statistics.h /^ const std::string &setSeparator() const { return stat.setSeparator(); }$/;" f class:ramulator::StatBase +set_channel_number ALDRAM.cpp /^void ALDRAM::set_channel_number(int channel) {$/;" f class:ALDRAM +set_channel_number DDR3.cpp /^void DDR3::set_channel_number(int channel) {$/;" f class:DDR3 +set_channel_number DDR4.cpp /^void DDR4::set_channel_number(int channel) {$/;" f class:DDR4 +set_channel_number DSARP.cpp /^void DSARP::set_channel_number(int channel) {$/;" f class:DSARP +set_channel_number GDDR5.cpp /^void GDDR5::set_channel_number(int channel) {$/;" f class:GDDR5 +set_channel_number HBM.cpp /^void HBM::set_channel_number(int channel) {$/;" f class:HBM +set_channel_number LPDDR3.cpp /^void LPDDR3::set_channel_number(int channel) {$/;" f class:LPDDR3 +set_channel_number LPDDR4.cpp /^void LPDDR4::set_channel_number(int channel) {$/;" f class:LPDDR4 +set_channel_number SALP.cpp /^void SALP::set_channel_number(int channel) {$/;" f class:SALP +set_channel_number TLDRAM.cpp /^void TLDRAM::set_channel_number(int channel) {$/;" f class:TLDRAM +set_channel_number WideIO.cpp /^void WideIO::set_channel_number(int channel) {$/;" f class:WideIO +set_channel_number WideIO2.cpp /^void WideIO2::set_channel_number(int channel) {$/;" f class:WideIO2 +set_core_num Config.h /^ void set_core_num(int _core_num) {core_num = _core_num;}$/;" f class:ramulator::Config +set_rank_number ALDRAM.cpp /^void ALDRAM::set_rank_number(int rank) {$/;" f class:ALDRAM +set_rank_number DDR3.cpp /^void DDR3::set_rank_number(int rank) {$/;" f class:DDR3 +set_rank_number DDR4.cpp /^void DDR4::set_rank_number(int rank) {$/;" f class:DDR4 +set_rank_number DSARP.cpp /^void DSARP::set_rank_number(int rank) {$/;" f class:DSARP +set_rank_number GDDR5.cpp /^void GDDR5::set_rank_number(int rank) {$/;" f class:GDDR5 +set_rank_number HBM.cpp /^void HBM::set_rank_number(int rank) {$/;" f class:HBM +set_rank_number LPDDR3.cpp /^void LPDDR3::set_rank_number(int rank) {$/;" f class:LPDDR3 +set_rank_number LPDDR4.cpp /^void LPDDR4::set_rank_number(int rank) {$/;" f class:LPDDR4 +set_rank_number SALP.cpp /^void SALP::set_rank_number(int rank) {$/;" f class:SALP +set_rank_number TLDRAM.cpp /^void TLDRAM::set_rank_number(int rank) {$/;" f class:TLDRAM +set_rank_number WideIO.cpp /^void WideIO::set_rank_number(int rank) {$/;" f class:WideIO +set_rank_number WideIO2.cpp /^void WideIO2::set_rank_number(int rank) {$/;" f class:WideIO2 +set_ready Processor.cpp /^void Window::set_ready(long addr, int mask)$/;" f class:Window +sibling ALDRAM.h /^ bool sibling;$/;" m struct:ramulator::ALDRAM::TimingEntry +sibling DDR3.h /^ bool sibling;$/;" m struct:ramulator::DDR3::TimingEntry +sibling DDR4.h /^ bool sibling;$/;" m struct:ramulator::DDR4::TimingEntry +sibling DSARP.h /^ bool sibling;$/;" m struct:ramulator::DSARP::TimingEntry +sibling GDDR5.h /^ bool sibling;$/;" m struct:ramulator::GDDR5::TimingEntry +sibling HBM.h /^ bool sibling;$/;" m struct:ramulator::HBM::TimingEntry +sibling LPDDR3.h /^ bool sibling;$/;" m struct:ramulator::LPDDR3::TimingEntry +sibling LPDDR4.h /^ bool sibling;$/;" m struct:ramulator::LPDDR4::TimingEntry +sibling SALP.h /^ bool sibling;$/;" m struct:ramulator::SALP::TimingEntry +sibling TLDRAM.h /^ bool sibling;$/;" m struct:ramulator::TLDRAM::TimingEntry +sibling WideIO.h /^ bool sibling;$/;" m struct:ramulator::WideIO::TimingEntry +sibling WideIO2.h /^ bool sibling;$/;" m struct:ramulator::WideIO2::TimingEntry +size ALDRAM.h /^ int size;$/;" m struct:ramulator::ALDRAM::OrgEntry +size Cache.h /^ size_t size;$/;" m class:ramulator::Cache +size Controller.h /^ unsigned int size() {return q.size();}$/;" f struct:ramulator::Controller::Queue +size DDR3.h /^ int size;$/;" m struct:ramulator::DDR3::OrgEntry +size DDR4.h /^ int size;$/;" m struct:ramulator::DDR4::OrgEntry +size DRAM.h /^ long size;$/;" m class:ramulator::DRAM +size DSARP.h /^ int size;$/;" m struct:ramulator::DSARP::OrgEntry +size GDDR5.h /^ int size;$/;" m struct:ramulator::GDDR5::OrgEntry +size HBM.h /^ int size;$/;" m struct:ramulator::HBM::OrgEntry +size LPDDR3.h /^ int size;$/;" m struct:ramulator::LPDDR3::OrgEntry +size LPDDR4.h /^ int size;$/;" m struct:ramulator::LPDDR4::OrgEntry +size SALP.h /^ int size;$/;" m struct:ramulator::SALP::OrgEntry +size StatType.h /^ size_type size() const { return 0; }$/;" f class:Stats::Stat +size StatType.h /^ size_type size() const {return 1;}$/;" f class:Stats::AverageDeviation +size StatType.h /^ size_type size() const {return 1;}$/;" f class:Stats::ScalarBase +size StatType.h /^ size_type size() const {return 1;}$/;" f class:Stats::StandardDeviation +size StatType.h /^ size_type size() const {return _size;}$/;" f class:Stats::VectorBase +size StatType.h /^ size_type size() const {return cvec.size();}$/;" f class:Stats::Distribution +size StatType.h /^ size_type size() const {return param_buckets;}$/;" f class:Stats::Histogram +size Statistics.h /^ Stats::size_type size(void) const { return stat.size(); }$/;" f class:ramulator::StatBase +size TLDRAM.h /^ int size;$/;" m struct:ramulator::TLDRAM::OrgEntry +size WideIO.h /^ int size;$/;" m struct:ramulator::WideIO::OrgEntry +size WideIO2.h /^ int size; \/\/ per-channel density$/;" m struct:ramulator::WideIO2::OrgEntry +size_type StatType.h /^typedef unsigned int size_type;$/;" t namespace:Stats +slice_lower_bits Memory.h /^ int slice_lower_bits(long& addr, int bits)$/;" f class:ramulator::Memory +spec DRAM.h /^ T* spec;$/;" m class:ramulator::DRAM +spec Memory.h /^ T * spec;$/;" m class:ramulator::Memory +speed_entry ALDRAM.h /^ }, speed_entry;$/;" m class:ramulator::ALDRAM typeref:struct:ramulator::ALDRAM::SpeedEntry +speed_entry DDR3.h /^ }, speed_entry;$/;" m class:ramulator::DDR3 typeref:struct:ramulator::DDR3::SpeedEntry +speed_entry DDR4.h /^ }, speed_entry;$/;" m class:ramulator::DDR4 typeref:struct:ramulator::DDR4::SpeedEntry +speed_entry DSARP.h /^ }, speed_entry;$/;" m class:ramulator::DSARP typeref:struct:ramulator::DSARP::SpeedEntry +speed_entry GDDR5.h /^ }, speed_entry;$/;" m class:ramulator::GDDR5 typeref:struct:ramulator::GDDR5::SpeedEntry +speed_entry HBM.h /^ }, speed_entry;$/;" m class:ramulator::HBM typeref:struct:ramulator::HBM::SpeedEntry +speed_entry LPDDR3.h /^ }, speed_entry;$/;" m class:ramulator::LPDDR3 typeref:struct:ramulator::LPDDR3::SpeedEntry +speed_entry LPDDR4.h /^ }, speed_entry;$/;" m class:ramulator::LPDDR4 typeref:struct:ramulator::LPDDR4::SpeedEntry +speed_entry SALP.h /^ }, speed_entry;$/;" m class:ramulator::SALP typeref:struct:ramulator::SALP::SpeedEntry +speed_entry TLDRAM.h /^ }, speed_entry;$/;" m class:ramulator::TLDRAM typeref:struct:ramulator::TLDRAM::SpeedEntry +speed_entry WideIO.h /^ }, speed_entry;$/;" m class:ramulator::WideIO typeref:struct:ramulator::WideIO::SpeedEntry +speed_entry WideIO2.h /^ }, speed_entry;$/;" m class:ramulator::WideIO2 typeref:struct:ramulator::WideIO2::SpeedEntry +speed_map ALDRAM.cpp /^map ALDRAM::speed_map = {$/;" m class:ALDRAM file: +speed_map ALDRAM.h /^ static map speed_map;$/;" m class:ramulator::ALDRAM +speed_map DDR3.cpp /^map DDR3::speed_map = {$/;" m class:DDR3 file: +speed_map DDR3.h /^ static map speed_map;$/;" m class:ramulator::DDR3 +speed_map DDR4.cpp /^map DDR4::speed_map = {$/;" m class:DDR4 file: +speed_map DDR4.h /^ static map speed_map;$/;" m class:ramulator::DDR4 +speed_map DSARP.cpp /^map DSARP::speed_map = {$/;" m class:DSARP file: +speed_map DSARP.h /^ static map speed_map;$/;" m class:ramulator::DSARP +speed_map GDDR5.cpp /^map GDDR5::speed_map = {$/;" m class:GDDR5 file: +speed_map GDDR5.h /^ static map speed_map;$/;" m class:ramulator::GDDR5 +speed_map HBM.cpp /^map HBM::speed_map = {$/;" m class:HBM file: +speed_map HBM.h /^ static map speed_map;$/;" m class:ramulator::HBM +speed_map LPDDR3.cpp /^map LPDDR3::speed_map = {$/;" m class:LPDDR3 file: +speed_map LPDDR3.h /^ static map speed_map;$/;" m class:ramulator::LPDDR3 +speed_map LPDDR4.cpp /^map LPDDR4::speed_map = {$/;" m class:LPDDR4 file: +speed_map LPDDR4.h /^ static map speed_map;$/;" m class:ramulator::LPDDR4 +speed_map SALP.cpp /^map SALP::speed_map = {$/;" m class:SALP file: +speed_map SALP.h /^ static map speed_map;$/;" m class:ramulator::SALP +speed_map TLDRAM.cpp /^map TLDRAM::speed_map = {$/;" m class:TLDRAM file: +speed_map TLDRAM.h /^ static map speed_map;$/;" m class:ramulator::TLDRAM +speed_map WideIO.cpp /^map WideIO::speed_map = {$/;" m class:WideIO file: +speed_map WideIO.h /^ static map speed_map;$/;" m class:ramulator::WideIO +speed_map WideIO2.cpp /^map WideIO2::speed_map = {$/;" m class:WideIO2 file: +speed_map WideIO2.h /^ static map speed_map;$/;" m class:ramulator::WideIO2 +speed_table ALDRAM.h /^ } speed_table[int(Temp::MAX)][int(Speed::MAX)] = {$/;" m class:ramulator::ALDRAM typeref:struct:ramulator::ALDRAM::SpeedEntry +speed_table DDR3.h /^ } speed_table[int(Speed::MAX)] = {$/;" m class:ramulator::DDR3 typeref:struct:ramulator::DDR3::SpeedEntry +speed_table DDR4.h /^ } speed_table[int(Speed::MAX)] = {$/;" m class:ramulator::DDR4 typeref:struct:ramulator::DDR4::SpeedEntry +speed_table DSARP.h /^ } speed_table[int(Speed::MAX)] = {$/;" m class:ramulator::DSARP typeref:struct:ramulator::DSARP::SpeedEntry +speed_table GDDR5.h /^ } speed_table[int(Speed::MAX)] = {$/;" m class:ramulator::GDDR5 typeref:struct:ramulator::GDDR5::SpeedEntry +speed_table HBM.h /^ } speed_table[int(Speed::MAX)] = {$/;" m class:ramulator::HBM typeref:struct:ramulator::HBM::SpeedEntry +speed_table LPDDR3.h /^ } speed_table[int(Speed::MAX)] = {$/;" m class:ramulator::LPDDR3 typeref:struct:ramulator::LPDDR3::SpeedEntry +speed_table LPDDR4.h /^ } speed_table[int(Speed::MAX)] = {$/;" m class:ramulator::LPDDR4 typeref:struct:ramulator::LPDDR4::SpeedEntry +speed_table SALP.h /^ } speed_table[int(Speed::MAX)] = {$/;" m class:ramulator::SALP typeref:struct:ramulator::SALP::SpeedEntry +speed_table TLDRAM.h /^ } speed_table[int(Speed::MAX)] = {$/;" m class:ramulator::TLDRAM typeref:struct:ramulator::TLDRAM::SpeedEntry +speed_table WideIO.h /^ } speed_table[int(Speed::MAX)] = {$/;" m class:ramulator::WideIO typeref:struct:ramulator::WideIO::SpeedEntry +speed_table WideIO2.h /^ } speed_table[int(Speed::MAX)] = {$/;" m class:ramulator::WideIO2 typeref:struct:ramulator::WideIO2::SpeedEntry +squares StatType.h /^ Counter squares;$/;" m class:Stats::AverageDeviation +squares StatType.h /^ Counter squares;$/;" m class:Stats::Distribution +squares StatType.h /^ Counter squares;$/;" m class:Stats::Histogram +squares StatType.h /^ Counter squares;$/;" m class:Stats::StandardDeviation +standard MemWrapper.h /^ std::string standard;$/;" m class:MemWrapper +standard_name ALDRAM.h /^ static string standard_name;$/;" m class:ramulator::ALDRAM +standard_name DDR3.h /^ static string standard_name;$/;" m class:ramulator::DDR3 +standard_name DDR4.h /^ static string standard_name;$/;" m class:ramulator::DDR4 +standard_name DSARP.h /^ static string standard_name;$/;" m class:ramulator::DSARP +standard_name GDDR5.h /^ static string standard_name;$/;" m class:ramulator::GDDR5 +standard_name HBM.h /^ static string standard_name;$/;" m class:ramulator::HBM +standard_name LPDDR3.h /^ static string standard_name;$/;" m class:ramulator::LPDDR3 +standard_name LPDDR4.h /^ static string standard_name;$/;" m class:ramulator::LPDDR4 +standard_name SALP.h /^ string standard_name;$/;" m class:ramulator::SALP +standard_name TLDRAM.h /^ static string standard_name;$/;" m class:ramulator::TLDRAM +standard_name WideIO.h /^ static string standard_name;$/;" m class:ramulator::WideIO +standard_name WideIO2.h /^ static string standard_name;$/;" m class:ramulator::WideIO2 +start ALDRAM.h /^ } start[int(Level::MAX)] = {$/;" m class:ramulator::ALDRAM typeref:class:ramulator::ALDRAM::State +start DDR3.h /^ } start[int(Level::MAX)] = {$/;" m class:ramulator::DDR3 typeref:class:ramulator::DDR3::State +start DDR4.h /^ } start[int(Level::MAX)] = {$/;" m class:ramulator::DDR4 typeref:class:ramulator::DDR4::State +start DSARP.h /^ } start[int(Level::MAX)] = {$/;" m class:ramulator::DSARP typeref:class:ramulator::DSARP::State +start GDDR5.h /^ } start[int(Level::MAX)] = {$/;" m class:ramulator::GDDR5 typeref:class:ramulator::GDDR5::State +start HBM.h /^ } start[int(Level::MAX)] = {$/;" m class:ramulator::HBM typeref:class:ramulator::HBM::State +start LPDDR3.h /^ } start[int(Level::MAX)] = {$/;" m class:ramulator::LPDDR3 typeref:class:ramulator::LPDDR3::State +start LPDDR4.h /^ } start[int(Level::MAX)] = {$/;" m class:ramulator::LPDDR4 typeref:class:ramulator::LPDDR4::State +start SALP.h /^ } start[int(Level::MAX)] = {$/;" m class:ramulator::SALP typeref:class:ramulator::SALP::State +start TLDRAM.h /^ } start[int(Level::MAX)] = {$/;" m class:ramulator::TLDRAM typeref:class:ramulator::TLDRAM::State +start WideIO.h /^ } start[int(Level::MAX)] = {$/;" m class:ramulator::WideIO typeref:class:ramulator::WideIO::State +start WideIO2.h /^ } start[int(Level::MAX)] = {$/;" m class:ramulator::WideIO2 typeref:class:ramulator::WideIO2::State +start_run MemWrapper.cpp /^void MemWrapper::start_run(const Config& configs, T* spec, const vector& files) {$/;" f class:MemWrapper +stat Statistics.h /^ StatType stat;$/;" m class:ramulator::StatBase +statName Statistics.h /^ std::string statName;$/;" m class:ramulator::StatBase +stat_output StatType.h /^ std::ofstream stat_output;$/;" m class:Stats::StatList +state DRAM.h /^ typename T::State state;$/;" m class:ramulator::DRAM +statlist StatType.cpp /^StatList statlist;$/;" m namespace:Stats file: +stats_out MemWrapper.h /^ string stats_out;$/;" m class:MemWrapper +subarray_ref_counters Refresh.h /^ vector> subarray_ref_counters;$/;" m class:ramulator::Refresh +subarrays Config.h /^ int subarrays;$/;" m class:ramulator::Config +subdesc Statistics.h /^ StatBaseVec & subdesc(Stats::off_type index, const std::string & desc) {$/;" f class:ramulator::StatBaseVec +subname Statistics.h /^ StatBaseVec & subname(Stats::off_type index, const std::string & name) {$/;" f class:ramulator::StatBaseVec +sum StatType.h /^ Counter sum;$/;" m class:Stats::AverageDeviation +sum StatType.h /^ Counter sum;$/;" m class:Stats::Distribution +sum StatType.h /^ Counter sum;$/;" m class:Stats::Histogram +sum StatType.h /^ Counter sum;$/;" m class:Stats::StandardDeviation +tCK ALDRAM.h /^ double freq, tCK;$/;" m struct:ramulator::ALDRAM::SpeedEntry +tCK DDR3.h /^ double freq, tCK;$/;" m struct:ramulator::DDR3::SpeedEntry +tCK DDR4.h /^ double freq, tCK;$/;" m struct:ramulator::DDR4::SpeedEntry +tCK DSARP.h /^ double freq, tCK;$/;" m struct:ramulator::DSARP::SpeedEntry +tCK GDDR5.h /^ double freq, tCK;$/;" m struct:ramulator::GDDR5::SpeedEntry +tCK Gem5Wrapper.h /^ double tCK;$/;" m class:ramulator::Gem5Wrapper +tCK HBM.h /^ double freq, tCK;$/;" m struct:ramulator::HBM::SpeedEntry +tCK LPDDR3.h /^ double freq, tCK;$/;" m struct:ramulator::LPDDR3::SpeedEntry +tCK LPDDR4.h /^ double freq, tCK;$/;" m struct:ramulator::LPDDR4::SpeedEntry +tCK SALP.h /^ double freq, tCK;$/;" m struct:ramulator::SALP::SpeedEntry +tCK TLDRAM.h /^ double freq, tCK;$/;" m struct:ramulator::TLDRAM::SpeedEntry +tCK WideIO.h /^ double freq, tCK;$/;" m struct:ramulator::WideIO::SpeedEntry +tCK WideIO2.h /^ double freq, tCK;$/;" m struct:ramulator::WideIO2::SpeedEntry +table Scheduler.h /^ map, Entry> table;$/;" m class:ramulator::RowTable +tag Cache.h /^ long tag;$/;" m struct:ramulator::Cache::Line +tag_offset Cache.h /^ unsigned int tag_offset;$/;" m class:ramulator::Cache +tail Processor.h /^ int tail = 0;$/;" m class:ramulator::Window +temperature ALDRAM.h /^ Temp temperature = Temp::HOT; \/\/ DHL$/;" m class:ramulator::ALDRAM +tick Cache.cpp /^void CacheSystem::tick() {$/;" f class:ramulator::CacheSystem +tick Controller.cpp /^void Controller::tick(){$/;" f class:ramulator::Controller +tick Controller.h /^ void tick()$/;" f class:ramulator::Controller +tick Gem5Wrapper.cpp /^void Gem5Wrapper::tick()$/;" f class:Gem5Wrapper +tick Memory.h /^ void tick()$/;" f class:ramulator::Memory +tick Processor.cpp /^void Core::tick()$/;" f class:Core +tick Processor.cpp /^void Processor::tick() {$/;" f class:Processor +tick SpeedyController.h /^ void tick()$/;" f class:ramulator::SpeedyController +tick_ref Refresh.cpp /^void Refresh::tick_ref() {$/;" f class:ramulator::Refresh +tick_ref Refresh.h /^ void tick_ref() {$/;" f class:ramulator::Refresh +timeout Scheduler.h /^ int timeout = 50;$/;" m class:ramulator::RowPolicy +timestamp Scheduler.h /^ long timestamp;$/;" m struct:ramulator::RowTable::Entry +timing ALDRAM.h /^ vector timing[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::ALDRAM +timing DDR3.h /^ vector timing[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::DDR3 +timing DDR4.h /^ vector timing[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::DDR4 +timing DRAM.h /^ vector* timing;$/;" m class:ramulator::DRAM +timing DSARP.h /^ vector timing[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::DSARP +timing GDDR5.h /^ vector timing[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::GDDR5 +timing HBM.h /^ vector timing[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::HBM +timing LPDDR3.h /^ vector timing[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::LPDDR3 +timing LPDDR4.h /^ vector timing[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::LPDDR4 +timing SALP.h /^ vector timing[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::SALP +timing TLDRAM.h /^ vector timing[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::TLDRAM +timing WideIO.h /^ vector timing[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::WideIO +timing WideIO2.h /^ vector timing[int(Level::MAX)][int(Command::MAX)];$/;" m class:ramulator::WideIO2 +total StatType.h /^ Result total() const {$/;" f class:Stats::VectorBase +total StatType.h /^ Result total() const {return (Result)_value;}$/;" f class:Stats::Scalar +total StatType.h /^ Result total() const {return result();}$/;" f class:Stats::Average +total StatType.h /^ Result total() const {return result();}$/;" f class:Stats::ConstValue +total StatType.h /^ virtual Result total() const { return Result(); };$/;" f class:Stats::StatBase +total StatType.h /^const uint16_t total = 0x00000010;$/;" m namespace:Stats +total Statistics.h /^ Stats::Result total(void) const { return StatBase::stat.total(); }$/;" f class:ramulator::VectorStatBase +totalReadReq pe.h /^ int totalReadReq;$/;" m class:pe +total_val StatType.h /^ Result total_val;$/;" m class:Stats::Average +trace Processor.h /^ Trace trace;$/;" m class:ramulator::Core +trace_name Processor.h /^ std::string trace_name;$/;" m class:ramulator::Trace +translate ALDRAM.h /^ Command translate[int(Request::Type::MAX)] = {$/;" m class:ramulator::ALDRAM +translate DDR3.h /^ Command translate[int(Request::Type::MAX)] = {$/;" m class:ramulator::DDR3 +translate DDR4.h /^ Command translate[int(Request::Type::MAX)] = {$/;" m class:ramulator::DDR4 +translate DSARP.h /^ Command translate[int(Request::Type::MAX)] = {$/;" m class:ramulator::DSARP +translate GDDR5.h /^ Command translate[int(Request::Type::MAX)] = {$/;" m class:ramulator::GDDR5 +translate HBM.h /^ Command translate[int(Request::Type::MAX)] = {$/;" m class:ramulator::HBM +translate LPDDR3.h /^ Command translate[int(Request::Type::MAX)] = {$/;" m class:ramulator::LPDDR3 +translate LPDDR4.h /^ Command translate[int(Request::Type::MAX)] = {$/;" m class:ramulator::LPDDR4 +translate SALP.h /^ Command translate[int(Request::Type::MAX)] = {$/;" m class:ramulator::SALP +translate TLDRAM.h /^ Command translate[int(Request::Type::MAX)] = {$/;" m class:ramulator::TLDRAM +translate WideIO.h /^ Command translate[int(Request::Type::MAX)] = {$/;" m class:ramulator::WideIO +translate WideIO2.h /^ Command translate[int(Request::Type::MAX)] = {$/;" m class:ramulator::WideIO2 +translation Memory.h /^ } translation = Translation::None;$/;" m class:ramulator::Memory typeref:class:ramulator::Memory::Translation +tx_bits Memory.h /^ int tx_bits;$/;" m class:ramulator::Memory +type DSARP.h /^ } type;$/;" m class:ramulator::DSARP typeref:class:ramulator::DSARP::Type +type Memory.h /^ } type = Type::RoBaRaCoCh;$/;" m class:ramulator::Memory typeref:class:ramulator::Memory::Type +type Request.h /^ } type;$/;" m class:ramulator::Request typeref:class:ramulator::Request::Type +type SALP.h /^ } type;$/;" m class:ramulator::SALP typeref:class:ramulator::SALP::Type +type Scheduler.h /^ } type = Type::FRFCFS_PriorHit;$/;" m class:ramulator::Scheduler typeref:class:ramulator::Scheduler::Type +type Scheduler.h /^ } type = Type::Opened;$/;" m class:ramulator::RowPolicy typeref:class:ramulator::RowPolicy::Type +type common.h /^ ramulator::Request::Type type; \/\/ Basically we have only read and write status.$/;" m struct:MemOp +type_map SALP.cpp /^map SALP::type_map = {$/;" m class:SALP file: +type_map SALP.h /^ static map type_map;$/;" m class:ramulator::SALP +underflow StatType.h /^ Counter underflow;$/;" m class:Stats::Distribution +update DRAM.h /^void DRAM::update(typename T::Command cmd, const int* addr, long clk)$/;" f class:ramulator::DRAM +update Scheduler.h /^ void update(typename T::Command cmd, const vector& addr_vec, long clk)$/;" f class:ramulator::RowTable +update SpeedyController.h /^ void update(typename T::Command cmd, bool state_change, vector::iterator& begin, vector::iterator& end, request_queue& q){$/;" f class:ramulator::SpeedyController +update_serving_requests DRAM.h /^void DRAM::update_serving_requests(const int* addr, int delta, long clk) {$/;" f class:ramulator::DRAM +update_state DRAM.h /^void DRAM::update_state(typename T::Command cmd, const int* addr)$/;" f class:ramulator::DRAM +update_temp Controller.cpp /^void Controller::update_temp(ALDRAM::Temp current_temperature){$/;" f class:ramulator::Controller +update_temp Controller.h /^ void update_temp(ALDRAM::Temp current_temperature)$/;" f class:ramulator::Controller +update_timing DRAM.h /^void DRAM::update_timing(typename T::Command cmd, const int* addr, long clk)$/;" f class:ramulator::DRAM +val ALDRAM.h /^ int val;$/;" m struct:ramulator::ALDRAM::TimingEntry +val DDR3.h /^ int val;$/;" m struct:ramulator::DDR3::TimingEntry +val DDR4.h /^ int val;$/;" m struct:ramulator::DDR4::TimingEntry +val DSARP.h /^ int val;$/;" m struct:ramulator::DSARP::TimingEntry +val GDDR5.h /^ int val;$/;" m struct:ramulator::GDDR5::TimingEntry +val HBM.h /^ int val;$/;" m struct:ramulator::HBM::TimingEntry +val LPDDR3.h /^ int val;$/;" m struct:ramulator::LPDDR3::TimingEntry +val LPDDR4.h /^ int val;$/;" m struct:ramulator::LPDDR4::TimingEntry +val SALP.h /^ int val;$/;" m struct:ramulator::SALP::TimingEntry +val TLDRAM.h /^ int val;$/;" m struct:ramulator::TLDRAM::TimingEntry +val WideIO.h /^ int val;$/;" m struct:ramulator::WideIO::TimingEntry +val WideIO2.h /^ int val;$/;" m struct:ramulator::WideIO2::TimingEntry +valid common.h /^ bool valid; $/;" m struct:MemOp +validate MemoryFactory.cpp /^void MemoryFactory::validate(int channels, int ranks, const Config& configs) {$/;" f class:ramulator::MemoryFactory +validate MemoryFactory.cpp /^void MemoryFactory::validate(int channels, int ranks, const Config& configs) {$/;" f class:ramulator::MemoryFactory +validate MemoryFactory.cpp /^void MemoryFactory::validate(int channels, int ranks, const Config& configs) {$/;" f class:ramulator::MemoryFactory +validate MemoryFactory.cpp /^void MemoryFactory::validate(int channels, int ranks, const Config& configs) {$/;" f class:ramulator::MemoryFactory +validate MemoryFactory.h /^ static void validate(int channels, int ranks, const Config& configs) {$/;" f class:ramulator::MemoryFactory +value StatType.h /^ Counter value() const { return current; }$/;" f class:Stats::Average +value StatType.h /^ Counter value() const {return _value;}$/;" f class:Stats::ConstValue +value StatType.h /^ Counter value() const {return _value;}$/;" f class:Stats::Scalar +value StatType.h /^ void value(VCounter& vec) const {$/;" f class:Stats::VectorBase +value Statistics.h /^ Stats::Counter value() const { return StatBase::stat.value(); };$/;" f class:ramulator::ScalarStatBase +value Statistics.h /^ void value(Stats::VCounter & vec) const { StatBase::stat.value(vec); }$/;" f class:ramulator::VectorStatBase +vresult StatType.h /^ VResult vresult() const {$/;" f class:Stats::VectorBase +vresult StatType.h /^ VResult vresult() const {return VResult(1, result());}$/;" f class:Stats::ScalarBase +vresult StatType.h /^ virtual VResult vresult() const { return VResult(); };$/;" f class:Stats::StatBase +wait_list Cache.h /^ std::list > wait_list;$/;" m class:ramulator::CacheSystem +window Processor.h /^ Window window;$/;" m class:ramulator::Core +write_hi SpeedyController.h /^ double write_hi = 0.875;$/;" m class:ramulator::SpeedyController +write_low SpeedyController.h /^ double write_low = 0.5;$/;" m class:ramulator::SpeedyController +write_mode Controller.h /^ bool write_mode = false; \/\/ whether write requests should be prioritized over reads$/;" m class:ramulator::Controller +write_mode SpeedyController.h /^ bool write_mode = false; \/\/ whether write requests should be prioritized over reads$/;" m class:ramulator::SpeedyController +write_req_queue_length_avg Controller.h /^ ScalarStat write_req_queue_length_avg;$/;" m class:ramulator::Controller +write_req_queue_length_sum Controller.h /^ ScalarStat write_req_queue_length_sum;$/;" m class:ramulator::Controller +write_row_conflicts Controller.h /^ VectorStat write_row_conflicts;$/;" m class:ramulator::Controller +write_row_hits Controller.h /^ VectorStat write_row_hits;$/;" m class:ramulator::Controller +write_row_misses Controller.h /^ VectorStat write_row_misses;$/;" m class:ramulator::Controller +write_transaction_bytes Controller.h /^ ScalarStat write_transaction_bytes;$/;" m class:ramulator::Controller +writeq Controller.h /^ Queue writeq; \/\/ queue for write requests$/;" m class:ramulator::Controller +writeq SpeedyController.h /^ request_queue writeq; \/\/ queue for write requests$/;" m class:ramulator::SpeedyController +wrp Refresh.cpp /^void Refresh::wrp() {$/;" f class:ramulator::Refresh +wrq_comp Refresh.cpp /^bool wrq_comp (wrq_idx l, wrq_idx r)$/;" f namespace:ramulator +wrq_idx Refresh.cpp /^typedef pair wrq_idx;$/;" t namespace:ramulator file: +zero StatType.h /^ bool zero() const { return (fabs(total_val) < eps); }$/;" f class:Stats::Average +zero StatType.h /^ bool zero() const {$/;" f class:Stats::Distribution +zero StatType.h /^ bool zero() const {$/;" f class:Stats::Histogram +zero StatType.h /^ bool zero() const {$/;" f class:Stats::VectorBase +zero StatType.h /^ bool zero() const {return (fabs(_value) < eps);}$/;" f class:Stats::ConstValue +zero StatType.h /^ bool zero() const {return (fabs(samples) < eps);}$/;" f class:Stats::StandardDeviation +zero StatType.h /^ bool zero() const {return (fabs(sum) < eps);}$/;" f class:Stats::AverageDeviation +zero StatType.h /^ virtual bool zero() const {return (fabs(_value) < eps);}$/;" f class:Stats::Scalar +zero Statistics.h /^ bool zero(void) const { return stat.zero(); }$/;" f class:ramulator::StatBase +~Controller Controller.h /^ ~Controller(){$/;" f class:ramulator::Controller +~DRAM DRAM.h /^DRAM::~DRAM()$/;" f class:ramulator::DRAM +~Gem5Wrapper Gem5Wrapper.cpp /^Gem5Wrapper::~Gem5Wrapper() {$/;" f class:Gem5Wrapper +~MemOp common.cpp /^MemOp::~MemOp(){}$/;" f class:MemOp +~MemWrapper MemWrapper.h /^ ~MemWrapper(){};$/;" f class:MemWrapper +~Memory Memory.h /^ ~Memory()$/;" f class:ramulator::Memory +~MemoryBase Memory.h /^ virtual ~MemoryBase() {}$/;" f class:ramulator::MemoryBase +~Refresh Refresh.h /^ virtual ~Refresh() {$/;" f class:ramulator::Refresh +~SpeedyController SpeedyController.h /^ ~SpeedyController(){$/;" f class:ramulator::SpeedyController +~StatList StatType.h /^ ~StatList() {$/;" f class:Stats::StatList +~pe pe.h /^ ~pe(){};$/;" f class:pe diff --git a/src/temp.txt b/src/temp.txt new file mode 100644 index 0000000..2e48992 --- /dev/null +++ b/src/temp.txt @@ -0,0 +1,113 @@ + + +#include "ALDRAM.h" +#include "TLDRAM.h" + + + ALDRAM* aldram = new ALDRAM(ALDRAM::Org::ALDRAM_4Gb_x8, ALDRAM::Speed::ALDRAM_1600K); + IPC = run_simulation(aldram, argv[1], 1, 1, 4); + printf("ALDRAM: %.5lf %.5lf\n", IPC, IPC / baseIPC); + + TLDRAM* tldram = new TLDRAM(TLDRAM::Org::TLDRAM_4Gb_x8, TLDRAM::Speed::TLDRAM_1600K, 16); + IPC = run_simulation(tldram, argv[1], 1, 1, 4); + printf("TLDRAM: %.5lf %.5lf\n", IPC, IPC / baseIPC); + + + // ALDRAM: update timing parameters based on temperatures + ALDRAM::Temp current_temperature = ALDRAM::Temp::COLD; + update_temp(current_temperature); + + + void update_temp(ALDRAM::Temp current_temperature) + { + } + + +template <> +void Controller::update_temp(ALDRAM::Temp current_temperature){ + channel->spec->aldram_timing(current_temperature); +} + + +template <> +void Controller::tick(){ + clk++; + + /*** 1. Serve completed reads ***/ + if (pending.size()) { + Request& req = pending[0]; + if (req.depart <= clk) { + req.callback(req); + pending.pop_front(); + } + } + + /*** 2. Should we schedule refreshes? ***/ + int refresh_interval = channel->spec->speed_entry.nREFI; + if (clk - refreshed >= refresh_interval) { + auto req_type = Request::Type::REFRESH; + + vector addr_vec(int(TLDRAM::Level::MAX), -1); + addr_vec[0] = channel->id; + for (auto child : channel->children) { + addr_vec[1] = child->id; + Request req(addr_vec, req_type, NULL); + bool res = enqueue(req); + assert(res); + } + refreshed = clk; + } + + /*** 3. Should we schedule writes? ***/ + if (!write_mode) { + // yes -- write queue is almost full or read queue is empty + if (writeq.size() >= int(0.8 * writeq.max) || readq.size() == 0) + write_mode = true; + } + else { + // no -- write queue is almost empty and read queue is not empty + if (writeq.size() <= int(0.2 * writeq.max) && readq.size() != 0) + write_mode = false; + } + + /*** 4. Find the best command to schedule, if any ***/ + Queue* queue = !write_mode ? &readq : &writeq; + if (otherq.size()) + queue = &otherq; // "other" requests are rare, so we give them precedence over reads/writes + + auto req = scheduler->get_head(queue->q); + if (req == queue->q.end() || !is_ready(req)) { + // we couldn't find a command to schedule -- let's try to be speculative + auto cmd = TLDRAM::Command::PRE; + vector victim = rowpolicy->get_victim(cmd); + if (!victim.empty()){ + issue_cmd(cmd, victim); + } + return; // nothing more to be done this cycle + } + + /*** 5. Change a read request to a migration request ***/ + if (req->type == Request::Type::READ) { + req->type = Request::Type::EXTENSION; + } + + // issue command on behalf of request + auto cmd = get_first_cmd(req); + issue_cmd(cmd, get_addr_vec(cmd, req)); + + // check whether this is the last command (which finishes the request) + if (cmd != channel->spec->translate[int(req->type)]) + return; + + // set a future completion time for read requests + if (req->type == Request::Type::READ || req->type == Request::Type::EXTENSION) { + req->depart = clk + channel->spec->read_latency; + pending.push_back(*req); + } + + // remove request from queue + queue->q.erase(req); +} + + + EXTENSION, // DHL: supporting extended functionality