riscv: add option RISCV_RELAXED_ALLOC_RWX

Author: scpcom

arch/riscv/Kconfig

@@ -33,8 +33,8 @@ config RISCV
 	select ARCH_HAS_PTE_SPECIAL
 	select ARCH_HAS_SET_DIRECT_MAP if MMU
 	select ARCH_HAS_SET_MEMORY if MMU
-	select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
-	select ARCH_HAS_STRICT_MODULE_RWX if MMU && !XIP_KERNEL
+	select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !RISCV_RELAXED_RWX
+	select ARCH_HAS_STRICT_MODULE_RWX if MMU && !RISCV_RELAXED_RWX
 	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
 	select ARCH_HAS_UBSAN_SANITIZE_ALL
 	select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
@@ -529,13 +529,23 @@ config PHYS_RAM_BASE
 	  explicitly specified to run early relocations of read-write data
 	  from flash to RAM.
 
+config RISCV_RELAXED_RWX
+	bool
+	default n
+
+config RISCV_RELAXED_ALLOC_RWX
+	bool
+	select RISCV_RELAXED_RWX
+	default n
+
 config XIP_KERNEL
 	bool "Kernel Execute-In-Place from ROM"
 	depends on MMU && SPARSEMEM
 	# This prevents XIP from being enabled by all{yes,mod}config, which
 	# fail to build since XIP doesn't support large kernels.
 	depends on !COMPILE_TEST
 	select PHYS_RAM_BASE_FIXED
+	select RISCV_RELAXED_RWX
 	help
 	  Execute-In-Place allows the kernel to run from non-volatile storage
 	  directly addressable by the CPU, such as NOR flash. This saves RAM

arch/riscv/Kconfig.socs

@@ -81,6 +81,7 @@ config ARCH_SUNXI
        select RISCV_SUNXI
        select RISCV_XUANTIE
        select RISCV_FIXMAP_DTB
+       select RISCV_RELAXED_ALLOC_RWX
        help
          This enables support for SUNXI SoC platform hardware.
 

arch/riscv/include/asm/pgtable.h

@@ -150,6 +150,11 @@
 					 | _PAGE_EXEC)
 #define PAGE_KERNEL_SO		__pgprot((_PAGE_KERNEL | _PAGE_SO) & \
 					~(_PAGE_CACHE | _PAGE_BUF))
+#ifdef CONFIG_RISCV_RELAXED_ALLOC_RWX
+#define PAGE_KERNEL_MAY_EXEC	PAGE_KERNEL_EXEC
+#else
+#define PAGE_KERNEL_MAY_EXEC	PAGE_KERNEL
+#endif
 
 #define PAGE_TABLE		__pgprot(_PAGE_TABLE)
 

arch/riscv/kernel/module.c

@@ -423,7 +423,7 @@ void *module_alloc(unsigned long size)
 {
 	return __vmalloc_node_range(size, 1, MODULES_VADDR,
 				    MODULES_END, GFP_KERNEL,
-				    PAGE_KERNEL, 0, NUMA_NO_NODE,
+				    PAGE_KERNEL_MAY_EXEC, 0, NUMA_NO_NODE,
 				    __builtin_return_address(0));
 }
 #endif

arch/riscv/net/bpf_jit_core.c

@@ -153,7 +153,9 @@ struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
 	bpf_flush_icache(jit_data->header, ctx->insns + ctx->ninsns);
 
 	if (!prog->is_func || extra_pass) {
+#ifndef CONFIG_RISCV_RELAXED_ALLOC_RWX
 		bpf_jit_binary_lock_ro(jit_data->header);
+#endif
 out_offset:
 		kfree(ctx->offset);
 		kfree(jit_data);
@@ -176,7 +178,7 @@ void *bpf_jit_alloc_exec(unsigned long size)
 {
 	return __vmalloc_node_range(size, PAGE_SIZE, BPF_JIT_REGION_START,
 				    BPF_JIT_REGION_END, GFP_KERNEL,
-				    PAGE_KERNEL, 0, NUMA_NO_NODE,
+				    PAGE_KERNEL_MAY_EXEC, 0, NUMA_NO_NODE,
 				    __builtin_return_address(0));
 }