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drm: rockchip: Add 162MHz pixel clock for 1600x1200
1 parent c0f69f9 commit ac7af46

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-0
lines changed

2 files changed

+7
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lines changed

drivers/clk/rockchip/clk-rk3399.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -93,6 +93,7 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
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RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
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RK3036_PLL_RATE( 297000000, 1, 99, 4, 2, 1, 0),
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RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
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RK3036_PLL_RATE( 162000000, 1, 54, 4, 2, 1, 0),
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RK3036_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0),
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RK3036_PLL_RATE( 106500000, 1, 71, 4, 4, 1, 0),
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RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0),

drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -153,6 +153,12 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
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{ 0x214c, 0x0003},
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{ 0x4064, 0x0003}
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},
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}, {
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162000000, {
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{ 0x0051, 0x0002 },
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{ 0x214c, 0x0003 },
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{ 0x4064, 0x0003 },
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},
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}, {
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~0UL, {
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{ 0x00a0, 0x000a },

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