RISC-V: doc: Updated status and clarification

Some extensions are ratified at least on the ISA specification version
20240411.  This commit moves such extensions.

This commit also changes that:

1.  Lower indentation of "Zk*" and "Zbk*" extensions to avoid extension
    groups from being misleading inside this section.
2.  Raise indentation of "Zfhmin" and "Zhinxmin" extensions to show that
    they are a strict subset of "Zfh" and "Zhinx" (respectively).
3.  Clarify that "s" is not an extension but a feature notifying
    the existence of the supervisor-level ISA.
4.  Clarify that "h" is not just an existence of the hypervisor-level ISA
    but is also an extension name ("H").

Author: a4lg

crates/std_detect/src/detect/arch/riscv.rs

@@ -44,34 +44,31 @@ features! {
     /// * Zifencei: `"zifencei"`
     /// * Zihintpause: `"zihintpause"`
     /// * Zihpm: `"zihpm"`
-    /// * Zk: `"zk"`
-    ///   * Zbkb: `"zbkb"`
-    ///   * Zbkc: `"zbkc"`
-    ///   * Zbkx: `"zbkx"`
-    ///   * Zkn: `"zkn"`
-    ///     * Zknd: `"zknd"`
-    ///     * Zkne: `"zkne"`
-    ///     * Zknh: `"zknh"`
-    ///   * Zkr: `"zkr"`
-    ///   * Zks: `"zks"`
-    ///     * Zksed: `"zksed"`
-    ///     * Zksh: `"zksh"`
-    ///   * Zkt: `"zkt"`
-    ///
-    /// There's also bases and extensions marked as standard instruction set,
-    /// but they are in frozen or draft state. These instruction sets are also
-    /// reserved by this macro and can be detected in the future platforms.
-    ///
-    /// Frozen RISC-V instruction sets:
-    ///
     /// * Zfh: `"zfh"`
-    /// * Zfhmin: `"zfhmin"`
+    ///   * Zfhmin: `"zfhmin"`
     /// * Zfinx: `"zfinx"`
     /// * Zdinx: `"zdinx"`
     /// * Zhinx: `"zhinx"`
-    /// * Zhinxmin: `"zhinxmin"`
+    ///   * Zhinxmin: `"zhinxmin"`
+    /// * Zbkb: `"zbkb"`
+    /// * Zbkc: `"zbkc"`
+    /// * Zbkx: `"zbkx"`
+    /// * Zk: `"zk"`
+    /// * Zkn: `"zkn"`
+    ///   * Zknd: `"zknd"`
+    ///   * Zkne: `"zkne"`
+    ///   * Zknh: `"zknh"`
+    /// * Zkr: `"zkr"`
+    /// * Zks: `"zks"`
+    ///   * Zksed: `"zksed"`
+    ///   * Zksh: `"zksh"`
+    /// * Zkt: `"zkt"`
     /// * Ztso: `"ztso"`
     ///
+    /// There's also bases and extensions marked as standard instruction set,
+    /// but they are in frozen or draft state. These instruction sets are also
+    /// reserved by this macro and can be detected in the future platforms.
+    ///
     /// Draft RISC-V instruction sets:
     ///
     /// * RV128I: `"rv128i"`
@@ -81,11 +78,11 @@ features! {
     ///
     /// Defined by Privileged Specification:
     ///
-    /// * Supervisor: `"s"`
+    /// * *Supervisor-Level ISA* (not "S" extension): `"s"`
+    /// * H (hypervisor): `"h"`
     /// * Svnapot: `"svnapot"`
     /// * Svpbmt: `"svpbmt"`
     /// * Svinval: `"svinval"`
-    /// * Hypervisor: `"h"`
     ///
     /// [ISA manual]: https://github.com/riscv/riscv-isa-manual/
     #[stable(feature = "riscv_ratified", since = "1.78.0")]