From 94c0ac4a1c663bccd76163db457d96dca0104ebf Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jakub=20Ber=C3=A1nek?= <berykubik@gmail.com>
Date: Wed, 30 Apr 2025 09:19:28 +0200
Subject: [PATCH] Remove `cranelift-codegen-0.82.1` benchmark

---
 collector/compile-benchmarks/README.md        |     2 -
 collector/compile-benchmarks/REUSE.toml       |     5 -
 .../.cargo_vcs_info.json                      |     6 -
 .../cranelift-codegen-0.82.1/0-println.patch  |    12 -
 .../cranelift-codegen-0.82.1/Cargo.lock       |   966 --
 .../cranelift-codegen-0.82.1/Cargo.toml       |   107 -
 .../cranelift-codegen-0.82.1/Cargo.toml.orig  |   103 -
 .../cranelift-codegen-0.82.1/LICENSE          |   220 -
 .../cranelift-codegen-0.82.1/README.md        |     2 -
 .../benches/x64-evex-encoding.rs              |    55 -
 .../cranelift-codegen-0.82.1/build.rs         |   495 -
 .../cranelift-codegen-0.82.1/perf-config.json |     4 -
 .../src/binemit/mod.rs                        |    95 -
 .../src/binemit/stack_map.rs                  |   152 -
 .../cranelift-codegen-0.82.1/src/bitset.rs    |   163 -
 .../src/cfg_printer.rs                        |    83 -
 .../cranelift-codegen-0.82.1/src/clif.isle    |  1700 --
 .../src/constant_hash.rs                      |    62 -
 .../cranelift-codegen-0.82.1/src/context.rs   |   352 -
 .../cranelift-codegen-0.82.1/src/cursor.rs    |   665 -
 .../src/data_value.rs                         |   309 -
 .../cranelift-codegen-0.82.1/src/dbg.rs       |    28 -
 .../cranelift-codegen-0.82.1/src/dce.rs       |    36 -
 .../src/divconst_magic_numbers.rs             |  1083 --
 .../src/dominator_tree.rs                     |   837 -
 .../cranelift-codegen-0.82.1/src/flowgraph.rs |   350 -
 .../cranelift-codegen-0.82.1/src/fx.rs        |   111 -
 .../src/inst_predicates.rs                    |    80 -
 .../src/ir/atomic_rmw_op.rs                   |    72 -
 .../src/ir/builder.rs                         |   265 -
 .../src/ir/condcodes.rs                       |   410 -
 .../src/ir/constant.rs                        |   460 -
 .../cranelift-codegen-0.82.1/src/ir/dfg.rs    |  1324 --
 .../src/ir/entities.rs                        |   533 -
 .../src/ir/extfunc.rs                         |   474 -
 .../src/ir/extname.rs                         |   167 -
 .../src/ir/function.rs                        |   356 -
 .../src/ir/globalvalue.rs                     |   159 -
 .../cranelift-codegen-0.82.1/src/ir/heap.rs   |    67 -
 .../src/ir/immediates.rs                      |  1330 --
 .../src/ir/instructions.rs                    |   924 --
 .../src/ir/jumptable.rs                       |   128 -
 .../cranelift-codegen-0.82.1/src/ir/layout.rs |  1324 --
 .../src/ir/libcall.rs                         |   215 -
 .../src/ir/memflags.rs                        |   169 -
 .../cranelift-codegen-0.82.1/src/ir/mod.rs    |   102 -
 .../src/ir/progpoint.rs                       |   164 -
 .../src/ir/sourceloc.rs                       |    66 -
 .../src/ir/stackslot.rs                       |   125 -
 .../cranelift-codegen-0.82.1/src/ir/table.rs  |    40 -
 .../src/ir/trapcode.rs                        |   134 -
 .../cranelift-codegen-0.82.1/src/ir/types.rs  |   625 -
 .../src/isa/aarch64/abi.rs                    |  1346 --
 .../src/isa/aarch64/inst.isle                 |  1999 ---
 .../src/isa/aarch64/inst/args.rs              |   755 -
 .../src/isa/aarch64/inst/emit.rs              |  2828 ----
 .../src/isa/aarch64/inst/emit_tests.rs        |  6742 --------
 .../src/isa/aarch64/inst/imms.rs              |  1257 --
 .../src/isa/aarch64/inst/mod.rs               |  3676 -----
 .../src/isa/aarch64/inst/regs.rs              |   351 -
 .../src/isa/aarch64/inst/unwind.rs            |     2 -
 .../src/isa/aarch64/inst/unwind/systemv.rs    |   177 -
 .../src/isa/aarch64/lower.isle                |  1126 --
 .../src/isa/aarch64/lower.rs                  |  1581 --
 .../src/isa/aarch64/lower/isle.rs             |   289 -
 .../lower/isle/generated_code.manifest        |     4 -
 .../isa/aarch64/lower/isle/generated_code.rs  |  6490 --------
 .../src/isa/aarch64/lower_inst.rs             |  2787 ----
 .../src/isa/aarch64/mod.rs                    |   297 -
 .../src/isa/aarch64/settings.rs               |     9 -
 .../src/isa/call_conv.rs                      |   148 -
 .../cranelift-codegen-0.82.1/src/isa/mod.rs   |   359 -
 .../src/isa/s390x/abi.rs                      |   803 -
 .../src/isa/s390x/inst.isle                   |  3249 ----
 .../src/isa/s390x/inst/args.rs                |   267 -
 .../src/isa/s390x/inst/emit.rs                |  2159 ---
 .../src/isa/s390x/inst/emit_tests.rs          |  8278 ----------
 .../src/isa/s390x/inst/imms.rs                |   231 -
 .../src/isa/s390x/inst/mod.rs                 |  2884 ----
 .../src/isa/s390x/inst/regs.rs                |   168 -
 .../src/isa/s390x/inst/unwind.rs              |     2 -
 .../src/isa/s390x/inst/unwind/systemv.rs      |   199 -
 .../src/isa/s390x/lower.isle                  |  2210 ---
 .../src/isa/s390x/lower.rs                    |   448 -
 .../src/isa/s390x/lower/isle.rs               |   533 -
 .../s390x/lower/isle/generated_code.manifest  |     4 -
 .../isa/s390x/lower/isle/generated_code.rs    | 13743 ----------------
 .../src/isa/s390x/mod.rs                      |   307 -
 .../src/isa/s390x/settings.rs                 |     9 -
 .../src/isa/unwind.rs                         |   182 -
 .../src/isa/unwind/systemv.rs                 |   271 -
 .../src/isa/unwind/winx64.rs                  |   334 -
 .../src/isa/x64/abi.rs                        |  1041 --
 .../src/isa/x64/encoding/evex.rs              |   403 -
 .../src/isa/x64/encoding/mod.rs               |    60 -
 .../src/isa/x64/encoding/rex.rs               |   506 -
 .../src/isa/x64/encoding/vex.rs               |     2 -
 .../src/isa/x64/inst.isle                     |  2579 ---
 .../src/isa/x64/inst/args.rs                  |  1862 ---
 .../src/isa/x64/inst/emit.rs                  |  2915 ----
 .../src/isa/x64/inst/emit_tests.rs            |  4747 ------
 .../src/isa/x64/inst/mod.rs                   |  3053 ----
 .../src/isa/x64/inst/regs.rs                  |   304 -
 .../src/isa/x64/inst/unwind.rs                |     5 -
 .../src/isa/x64/inst/unwind/systemv.rs        |   201 -
 .../src/isa/x64/inst/unwind/winx64.rs         |    16 -
 .../src/isa/x64/lower.isle                    |  2252 ---
 .../src/isa/x64/lower.rs                      |  4022 -----
 .../src/isa/x64/lower/isle.rs                 |   572 -
 .../x64/lower/isle/generated_code.manifest    |     4 -
 .../src/isa/x64/lower/isle/generated_code.rs  |  9338 -----------
 .../src/isa/x64/mod.rs                        |   367 -
 .../src/isa/x64/settings.rs                   |     9 -
 .../cranelift-codegen-0.82.1/src/iterators.rs |    93 -
 .../src/legalizer/globalvalue.rs              |   127 -
 .../src/legalizer/heap.rs                     |   259 -
 .../src/legalizer/mod.rs                      |   363 -
 .../src/legalizer/table.rs                    |    87 -
 .../cranelift-codegen-0.82.1/src/lib.rs       |   119 -
 .../cranelift-codegen-0.82.1/src/licm.rs      |   245 -
 .../cranelift-codegen-0.82.1/src/log.rs       |    39 -
 .../src/loop_analysis.rs                      |   349 -
 .../src/machinst/abi.rs                       |   245 -
 .../src/machinst/abi_impl.rs                  |  1736 --
 .../src/machinst/blockorder.rs                |   634 -
 .../src/machinst/buffer.rs                    |  2096 ---
 .../src/machinst/compile.rs                   |   114 -
 .../src/machinst/debug.rs                     |   525 -
 .../src/machinst/helpers.rs                   |    43 -
 .../src/machinst/inst_common.rs               |    94 -
 .../src/machinst/isle.rs                      |   545 -
 .../src/machinst/lower.rs                     |  1375 --
 .../src/machinst/mod.rs                       |   423 -
 .../src/machinst/regmapping.rs                |   108 -
 .../src/machinst/valueregs.rs                 |   130 -
 .../src/machinst/vcode.rs                     |   962 --
 .../src/nan_canonicalization.rs               |   106 -
 .../cranelift-codegen-0.82.1/src/prelude.isle |   562 -
 .../src/preopt.peepmatic                      |   196 -
 .../src/print_errors.rs                       |   220 -
 .../src/remove_constant_phis.rs               |   391 -
 .../cranelift-codegen-0.82.1/src/result.rs    |    76 -
 .../src/scoped_hash_map.rs                    |   233 -
 .../cranelift-codegen-0.82.1/src/settings.rs  |   581 -
 .../src/simple_gvn.rs                         |   152 -
 .../src/simple_preopt.rs                      |  1054 --
 .../src/souper_harvest.rs                     |   581 -
 .../cranelift-codegen-0.82.1/src/timing.rs    |   260 -
 .../src/unreachable_code.rs                   |    58 -
 .../src/value_label.rs                        |    69 -
 .../src/verifier/flags.rs                     |   161 -
 .../src/verifier/mod.rs                       |  1885 ---
 .../cranelift-codegen-0.82.1/src/write.rs     |   697 -
 153 files changed, 138471 deletions(-)
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/.cargo_vcs_info.json
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/0-println.patch
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/Cargo.lock
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/Cargo.toml
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/Cargo.toml.orig
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/LICENSE
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/README.md
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/benches/x64-evex-encoding.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/build.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/perf-config.json
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/binemit/mod.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/binemit/stack_map.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/bitset.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/cfg_printer.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/clif.isle
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/constant_hash.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/context.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/cursor.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/data_value.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/dbg.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/dce.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/divconst_magic_numbers.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/dominator_tree.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/flowgraph.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/fx.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/inst_predicates.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/atomic_rmw_op.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/builder.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/condcodes.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/constant.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/dfg.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/entities.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/extfunc.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/extname.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/function.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/globalvalue.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/heap.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/immediates.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/instructions.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/jumptable.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/layout.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/libcall.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/memflags.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/mod.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/progpoint.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/sourceloc.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/stackslot.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/table.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/trapcode.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/types.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/abi.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/inst.isle
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/inst/args.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/inst/emit.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/inst/emit_tests.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/inst/imms.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/inst/mod.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/inst/regs.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/inst/unwind.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/inst/unwind/systemv.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/lower.isle
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/lower.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/lower/isle.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/lower/isle/generated_code.manifest
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/lower/isle/generated_code.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/lower_inst.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/mod.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/settings.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/call_conv.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/mod.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/abi.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/inst.isle
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/inst/args.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/inst/emit.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/inst/emit_tests.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/inst/imms.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/inst/mod.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/inst/regs.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/inst/unwind.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/inst/unwind/systemv.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/lower.isle
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/lower.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/lower/isle.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/lower/isle/generated_code.manifest
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/lower/isle/generated_code.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/mod.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/settings.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/unwind.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/unwind/systemv.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/unwind/winx64.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/abi.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/encoding/evex.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/encoding/mod.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/encoding/rex.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/encoding/vex.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/inst.isle
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/inst/args.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/inst/emit.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/inst/emit_tests.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/inst/mod.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/inst/regs.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/inst/unwind.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/inst/unwind/systemv.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/inst/unwind/winx64.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/lower.isle
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/lower.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/lower/isle.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/lower/isle/generated_code.manifest
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/lower/isle/generated_code.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/mod.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/settings.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/iterators.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/legalizer/globalvalue.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/legalizer/heap.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/legalizer/mod.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/legalizer/table.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/lib.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/licm.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/log.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/loop_analysis.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/abi.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/abi_impl.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/blockorder.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/buffer.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/compile.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/debug.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/helpers.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/inst_common.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/isle.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/lower.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/mod.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/regmapping.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/valueregs.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/vcode.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/nan_canonicalization.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/prelude.isle
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/preopt.peepmatic
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/print_errors.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/remove_constant_phis.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/result.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/scoped_hash_map.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/settings.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/simple_gvn.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/simple_preopt.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/souper_harvest.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/timing.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/unreachable_code.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/value_label.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/verifier/flags.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/verifier/mod.rs
 delete mode 100644 collector/compile-benchmarks/cranelift-codegen-0.82.1/src/write.rs

diff --git a/collector/compile-benchmarks/README.md b/collector/compile-benchmarks/README.md
index 3e8164423..0bc715bc6 100644
--- a/collector/compile-benchmarks/README.md
+++ b/collector/compile-benchmarks/README.md
@@ -22,8 +22,6 @@ They mostly consist of real-world crates.
   part of the Rust ecosystem.
 - **clap-3.1.6**: A command line argument parser library. A crate used by many Rust programs.
 - **clap_derive-4.5.32**: The proc macro sub-crate of a command line argument parser library that is used by many Rust programs.
-- **cranelift-codegen-0.82.1**: The largest crate from a code generator. Used by
-  wasmtime. Stresses obligation processing.
 - **cranelift-codegen-0.119.0**: The largest crate from a code generator. Used by wasmtime. Stresses obligation processing.
 - **diesel-1.4.8**: A type-safe SQL query builder. Utilizes the type system to ensure a lot of invariants. Stresses anything related to resolving trait bounds, by having a lot of trait impls for a large number of different types.
 - **diesel-2.2:10**: A type-safe SQL query builder. Utilizes the type system to ensure a lot of invariants. Stresses anything related to resolving trait bounds, by having a lot of trait impls for a large number of different types.
diff --git a/collector/compile-benchmarks/REUSE.toml b/collector/compile-benchmarks/REUSE.toml
index bc9a75cca..4ae8bf6a2 100644
--- a/collector/compile-benchmarks/REUSE.toml
+++ b/collector/compile-benchmarks/REUSE.toml
@@ -42,11 +42,6 @@ path = "coercions/**"
 SPDX-FileCopyrightText = "The Rust Project Developers (see https://thanks.rust-lang.org)"
 SPDX-License-Identifier = "MIT"
 
-[[annotations]]
-path = "cranelift-codegen-0.82.1/**"
-SPDX-FileCopyrightText = "The Cranelift Project Developers"
-SPDX-License-Identifier = "Apache-2.0 WITH LLVM-exception"
-
 [[annotations]]
 path = "cranelift-codegen-0.119.0/**"
 SPDX-FileCopyrightText = "The Cranelift Project Developers"
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/.cargo_vcs_info.json b/collector/compile-benchmarks/cranelift-codegen-0.82.1/.cargo_vcs_info.json
deleted file mode 100644
index 9bc20ffe4..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/.cargo_vcs_info.json
+++ /dev/null
@@ -1,6 +0,0 @@
-{
-  "git": {
-    "sha1": "5b09b74f4c5e0fd817febd3263947ee3682759bd"
-  },
-  "path_in_vcs": "cranelift/codegen"
-}
\ No newline at end of file
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/0-println.patch b/collector/compile-benchmarks/cranelift-codegen-0.82.1/0-println.patch
deleted file mode 100644
index 970f57deb..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/0-println.patch
+++ /dev/null
@@ -1,12 +0,0 @@
-diff --git a/src/loop_analysis.rs b/src/loop_analysis.rs
-index 0e8715ae..4e44b2bd 100644
---- a/src/loop_analysis.rs
-+++ b/src/loop_analysis.rs
-@@ -163,6 +163,7 @@ impl LoopAnalysis {
-         domtree: &DominatorTree,
-         layout: &Layout,
-     ) {
-+        println!("testing");
-         let mut stack: Vec<Block> = Vec::new();
-         // We handle each loop header in reverse order, corresponding to a pseudo postorder
-         // traversal of the graph.
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/Cargo.lock b/collector/compile-benchmarks/cranelift-codegen-0.82.1/Cargo.lock
deleted file mode 100644
index 1706bd2d5..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/Cargo.lock
+++ /dev/null
@@ -1,966 +0,0 @@
-# This file is automatically @generated by Cargo.
-# It is not intended for manual editing.
-version = 3
-
-[[package]]
-name = "addr2line"
-version = "0.17.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "b9ecd88a8c8378ca913a680cd98f0f13ac67383d35993f86c90a70e3f137816b"
-dependencies = [
- "gimli",
-]
-
-[[package]]
-name = "adler"
-version = "1.0.2"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "f26201604c87b1e01bd3d98f8d5d9a8fcbb815e8cedb41ffccbeb4bf593a35fe"
-
-[[package]]
-name = "ahash"
-version = "0.4.7"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "739f4a8db6605981345c5654f3a85b056ce52f37a39d34da03f25bf2151ea16e"
-
-[[package]]
-name = "aho-corasick"
-version = "0.7.18"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "1e37cfd5e7657ada45f742d6e99ca5788580b5c529dc78faf11ece6dc702656f"
-dependencies = [
- "memchr",
-]
-
-[[package]]
-name = "atty"
-version = "0.2.14"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "d9b39be18770d11421cdb1b9947a45dd3f37e93092cbf377614828a319d5fee8"
-dependencies = [
- "hermit-abi",
- "libc",
- "winapi",
-]
-
-[[package]]
-name = "autocfg"
-version = "1.1.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "d468802bab17cbc0cc575e9b053f41e72aa36bfa6b7f55e3529ffa43161b97fa"
-
-[[package]]
-name = "backtrace"
-version = "0.3.64"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "5e121dee8023ce33ab248d9ce1493df03c3b38a659b240096fcbd7048ff9c31f"
-dependencies = [
- "addr2line",
- "cc",
- "cfg-if",
- "libc",
- "miniz_oxide",
- "object",
- "rustc-demangle",
-]
-
-[[package]]
-name = "bincode"
-version = "1.3.3"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "b1f45e9417d87227c7a56d22e471c6206462cba514c7590c09aff4cf6d1ddcad"
-dependencies = [
- "serde",
-]
-
-[[package]]
-name = "bitflags"
-version = "1.3.2"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "bef38d45163c2f1dde094a7dfd33ccf595c92905c8f8f4fdc18d06fb1037718a"
-
-[[package]]
-name = "bstr"
-version = "0.2.17"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "ba3569f383e8f1598449f1a423e72e99569137b47740b1da11ef19af3d5c3223"
-dependencies = [
- "lazy_static",
- "memchr",
- "regex-automata",
- "serde",
-]
-
-[[package]]
-name = "bumpalo"
-version = "3.9.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "a4a45a46ab1f2412e53d3a0ade76ffad2025804294569aae387231a0cd6e0899"
-
-[[package]]
-name = "cast"
-version = "0.2.7"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "4c24dab4283a142afa2fdca129b80ad2c6284e073930f964c3a1293c225ee39a"
-dependencies = [
- "rustc_version",
-]
-
-[[package]]
-name = "cc"
-version = "1.0.73"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "2fff2a6927b3bb87f9595d67196a70493f627687a71d87a0d692242c33f58c11"
-
-[[package]]
-name = "cfg-if"
-version = "1.0.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "baf1de4339761588bc0619e3cbc0120ee582ebb74b53b4efbf79117bd2da40fd"
-
-[[package]]
-name = "clap"
-version = "2.34.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "a0610544180c38b88101fecf2dd634b174a62eef6946f84dfc6a7127512b381c"
-dependencies = [
- "bitflags",
- "textwrap 0.11.0",
- "unicode-width",
-]
-
-[[package]]
-name = "cranelift-bforest"
-version = "0.82.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "d16922317bd7dd104d509a373887822caa0242fc1def00de66abb538db221db4"
-dependencies = [
- "cranelift-entity",
-]
-
-[[package]]
-name = "cranelift-codegen"
-version = "0.82.1"
-dependencies = [
- "bincode",
- "cranelift-bforest",
- "cranelift-codegen-meta",
- "cranelift-codegen-shared",
- "cranelift-entity",
- "cranelift-isle",
- "criterion",
- "gimli",
- "hashbrown 0.9.1",
- "log",
- "miette",
- "regalloc",
- "serde",
- "smallvec",
- "souper-ir",
- "target-lexicon",
-]
-
-[[package]]
-name = "cranelift-codegen-meta"
-version = "0.82.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "703d0ed7d3bc6c7a814ca12858175bf4e93167a3584127858c686e4b5dd6e432"
-dependencies = [
- "cranelift-codegen-shared",
-]
-
-[[package]]
-name = "cranelift-codegen-shared"
-version = "0.82.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "80f52311e1c90de12dcf8c4b9999c6ebfd1ed360373e88c357160936844511f6"
-
-[[package]]
-name = "cranelift-entity"
-version = "0.82.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "66bc82ef522c1f643baf7d4d40b7c52643ee4549d8960b0e6a047daacb83f897"
-dependencies = [
- "serde",
-]
-
-[[package]]
-name = "cranelift-isle"
-version = "0.82.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "48f787aaa065700a108f9f62764f5e1224f97ff8a2e2f86ddf7071ab2981639c"
-dependencies = [
- "log",
- "miette",
- "thiserror",
-]
-
-[[package]]
-name = "criterion"
-version = "0.3.5"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "1604dafd25fba2fe2d5895a9da139f8dc9b319a5fe5354ca137cbbce4e178d10"
-dependencies = [
- "atty",
- "cast",
- "clap",
- "criterion-plot",
- "csv",
- "itertools",
- "lazy_static",
- "num-traits",
- "oorandom",
- "plotters",
- "rayon",
- "regex",
- "serde",
- "serde_cbor",
- "serde_derive",
- "serde_json",
- "tinytemplate",
- "walkdir",
-]
-
-[[package]]
-name = "criterion-plot"
-version = "0.4.4"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "d00996de9f2f7559f7f4dc286073197f83e92256a59ed395f9aac01fe717da57"
-dependencies = [
- "cast",
- "itertools",
-]
-
-[[package]]
-name = "crossbeam-channel"
-version = "0.5.4"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "5aaa7bd5fb665c6864b5f963dd9097905c54125909c7aa94c9e18507cdbe6c53"
-dependencies = [
- "cfg-if",
- "crossbeam-utils",
-]
-
-[[package]]
-name = "crossbeam-deque"
-version = "0.8.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "6455c0ca19f0d2fbf751b908d5c55c1f5cbc65e03c4225427254b46890bdde1e"
-dependencies = [
- "cfg-if",
- "crossbeam-epoch",
- "crossbeam-utils",
-]
-
-[[package]]
-name = "crossbeam-epoch"
-version = "0.9.8"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "1145cf131a2c6ba0615079ab6a638f7e1973ac9c2634fcbeaaad6114246efe8c"
-dependencies = [
- "autocfg",
- "cfg-if",
- "crossbeam-utils",
- "lazy_static",
- "memoffset",
- "scopeguard",
-]
-
-[[package]]
-name = "crossbeam-utils"
-version = "0.8.8"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "0bf124c720b7686e3c2663cf54062ab0f68a88af2fb6a030e87e30bf721fcb38"
-dependencies = [
- "cfg-if",
- "lazy_static",
-]
-
-[[package]]
-name = "csv"
-version = "1.1.6"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "22813a6dc45b335f9bade10bf7271dc477e81113e89eb251a0bc2a8a81c536e1"
-dependencies = [
- "bstr",
- "csv-core",
- "itoa 0.4.8",
- "ryu",
- "serde",
-]
-
-[[package]]
-name = "csv-core"
-version = "0.1.10"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "2b2466559f260f48ad25fe6317b3c8dac77b5bdb5763ac7d9d6103530663bc90"
-dependencies = [
- "memchr",
-]
-
-[[package]]
-name = "either"
-version = "1.6.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "e78d4f1cc4ae33bbfc157ed5d5a5ef3bc29227303d595861deb238fcec4e9457"
-
-[[package]]
-name = "gimli"
-version = "0.26.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "78cc372d058dcf6d5ecd98510e7fbc9e5aec4d21de70f65fea8fecebcd881bd4"
-dependencies = [
- "indexmap",
-]
-
-[[package]]
-name = "half"
-version = "1.8.2"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "eabb4a44450da02c90444cf74558da904edde8fb4e9035a9a6a4e15445af0bd7"
-
-[[package]]
-name = "hashbrown"
-version = "0.9.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "d7afe4a420e3fe79967a00898cc1f4db7c8a49a9333a29f8a4bd76a253d5cd04"
-dependencies = [
- "ahash",
-]
-
-[[package]]
-name = "hashbrown"
-version = "0.11.2"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "ab5ef0d4909ef3724cc8cce6ccc8572c5c817592e9285f5464f8e86f8bd3726e"
-
-[[package]]
-name = "hermit-abi"
-version = "0.1.19"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "62b467343b94ba476dcb2500d242dadbb39557df889310ac77c5d99100aaac33"
-dependencies = [
- "libc",
-]
-
-[[package]]
-name = "id-arena"
-version = "2.2.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "25a2bc672d1148e28034f176e01fffebb08b35768468cc954630da77a1449005"
-
-[[package]]
-name = "indexmap"
-version = "1.8.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "282a6247722caba404c065016bbfa522806e51714c34f5dfc3e4a3a46fcb4223"
-dependencies = [
- "autocfg",
- "hashbrown 0.11.2",
-]
-
-[[package]]
-name = "is_ci"
-version = "1.1.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "616cde7c720bb2bb5824a224687d8f77bfd38922027f01d825cd7453be5099fb"
-
-[[package]]
-name = "itertools"
-version = "0.10.3"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "a9a9d19fa1e79b6215ff29b9d6880b706147f16e9b1dbb1e4e5947b5b02bc5e3"
-dependencies = [
- "either",
-]
-
-[[package]]
-name = "itoa"
-version = "0.4.8"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "b71991ff56294aa922b450139ee08b3bfc70982c6b2c7562771375cf73542dd4"
-
-[[package]]
-name = "itoa"
-version = "1.0.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "1aab8fc367588b89dcee83ab0fd66b72b50b72fa1904d7095045ace2b0c81c35"
-
-[[package]]
-name = "js-sys"
-version = "0.3.56"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "a38fc24e30fd564ce974c02bf1d337caddff65be6cc4735a1f7eab22a7440f04"
-dependencies = [
- "wasm-bindgen",
-]
-
-[[package]]
-name = "lazy_static"
-version = "1.4.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "e2abad23fbc42b3700f2f279844dc832adb2b2eb069b2df918f455c4e18cc646"
-
-[[package]]
-name = "libc"
-version = "0.2.121"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "efaa7b300f3b5fe8eb6bf21ce3895e1751d9665086af2d64b42f19701015ff4f"
-
-[[package]]
-name = "log"
-version = "0.4.14"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "51b9bbe6c47d51fc3e1a9b945965946b4c44142ab8792c50835a980d362c2710"
-dependencies = [
- "cfg-if",
-]
-
-[[package]]
-name = "memchr"
-version = "2.4.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "308cc39be01b73d0d18f82a0e7b2a3df85245f84af96fdddc5d202d27e47b86a"
-
-[[package]]
-name = "memoffset"
-version = "0.6.5"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "5aa361d4faea93603064a027415f07bd8e1d5c88c9fbf68bf56a285428fd79ce"
-dependencies = [
- "autocfg",
-]
-
-[[package]]
-name = "miette"
-version = "3.3.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "cd2adcfcced5d625bf90a958a82ae5b93231f57f3df1383fee28c9b5096d35ed"
-dependencies = [
- "atty",
- "backtrace",
- "miette-derive",
- "once_cell",
- "owo-colors",
- "supports-color",
- "supports-hyperlinks",
- "supports-unicode",
- "terminal_size",
- "textwrap 0.14.2",
- "thiserror",
-]
-
-[[package]]
-name = "miette-derive"
-version = "3.3.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "5c01a8b61312d367ce87956bb686731f87e4c6dd5dbc550e8f06e3c24fb1f67f"
-dependencies = [
- "proc-macro2",
- "quote",
- "syn",
-]
-
-[[package]]
-name = "miniz_oxide"
-version = "0.4.4"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "a92518e98c078586bc6c934028adcca4c92a53d6a958196de835170a01d84e4b"
-dependencies = [
- "adler",
- "autocfg",
-]
-
-[[package]]
-name = "num-traits"
-version = "0.2.14"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "9a64b1ec5cda2586e284722486d802acf1f7dbdc623e2bfc57e65ca1cd099290"
-dependencies = [
- "autocfg",
-]
-
-[[package]]
-name = "num_cpus"
-version = "1.13.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "19e64526ebdee182341572e50e9ad03965aa510cd94427a4549448f285e957a1"
-dependencies = [
- "hermit-abi",
- "libc",
-]
-
-[[package]]
-name = "object"
-version = "0.27.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "67ac1d3f9a1d3616fd9a60c8d74296f22406a238b6a72f5cc1e6f314df4ffbf9"
-dependencies = [
- "memchr",
-]
-
-[[package]]
-name = "once_cell"
-version = "1.10.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "87f3e037eac156d1775da914196f0f37741a274155e34a0b7e427c35d2a2ecb9"
-
-[[package]]
-name = "oorandom"
-version = "11.1.3"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "0ab1bc2a289d34bd04a330323ac98a1b4bc82c9d9fcb1e66b63caa84da26b575"
-
-[[package]]
-name = "owo-colors"
-version = "3.3.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "5e72e30578e0d0993c8ae20823dd9cff2bc5517d2f586a8aef462a581e8a03eb"
-
-[[package]]
-name = "plotters"
-version = "0.3.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "32a3fd9ec30b9749ce28cd91f255d569591cdf937fe280c312143e3c4bad6f2a"
-dependencies = [
- "num-traits",
- "plotters-backend",
- "plotters-svg",
- "wasm-bindgen",
- "web-sys",
-]
-
-[[package]]
-name = "plotters-backend"
-version = "0.3.2"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "d88417318da0eaf0fdcdb51a0ee6c3bed624333bff8f946733049380be67ac1c"
-
-[[package]]
-name = "plotters-svg"
-version = "0.3.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "521fa9638fa597e1dc53e9412a4f9cefb01187ee1f7413076f9e6749e2885ba9"
-dependencies = [
- "plotters-backend",
-]
-
-[[package]]
-name = "proc-macro2"
-version = "1.0.36"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "c7342d5883fbccae1cc37a2353b09c87c9b0f3afd73f5fb9bba687a1f733b029"
-dependencies = [
- "unicode-xid",
-]
-
-[[package]]
-name = "quote"
-version = "1.0.16"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "b4af2ec4714533fcdf07e886f17025ace8b997b9ce51204ee69b6da831c3da57"
-dependencies = [
- "proc-macro2",
-]
-
-[[package]]
-name = "rayon"
-version = "1.5.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "c06aca804d41dbc8ba42dfd964f0d01334eceb64314b9ecf7c5fad5188a06d90"
-dependencies = [
- "autocfg",
- "crossbeam-deque",
- "either",
- "rayon-core",
-]
-
-[[package]]
-name = "rayon-core"
-version = "1.9.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "d78120e2c850279833f1dd3582f730c4ab53ed95aeaaaa862a2a5c71b1656d8e"
-dependencies = [
- "crossbeam-channel",
- "crossbeam-deque",
- "crossbeam-utils",
- "lazy_static",
- "num_cpus",
-]
-
-[[package]]
-name = "regalloc"
-version = "0.0.34"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "62446b1d3ebf980bdc68837700af1d77b37bc430e524bf95319c6eada2a4cc02"
-dependencies = [
- "log",
- "rustc-hash",
- "serde",
- "smallvec",
-]
-
-[[package]]
-name = "regex"
-version = "1.5.5"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "1a11647b6b25ff05a515cb92c365cec08801e83423a235b51e231e1808747286"
-dependencies = [
- "aho-corasick",
- "memchr",
- "regex-syntax",
-]
-
-[[package]]
-name = "regex-automata"
-version = "0.1.10"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "6c230d73fb8d8c1b9c0b3135c5142a8acee3a0558fb8db5cf1cb65f8d7862132"
-
-[[package]]
-name = "regex-syntax"
-version = "0.6.25"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "f497285884f3fcff424ffc933e56d7cbca511def0c9831a7f9b5f6153e3cc89b"
-
-[[package]]
-name = "rustc-demangle"
-version = "0.1.21"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "7ef03e0a2b150c7a90d01faf6254c9c48a41e95fb2a8c2ac1c6f0d2b9aefc342"
-
-[[package]]
-name = "rustc-hash"
-version = "1.1.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "08d43f7aa6b08d49f382cde6a7982047c3426db949b1424bc4b7ec9ae12c6ce2"
-
-[[package]]
-name = "rustc_version"
-version = "0.4.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "bfa0f585226d2e68097d4f95d113b15b83a82e819ab25717ec0590d9584ef366"
-dependencies = [
- "semver",
-]
-
-[[package]]
-name = "ryu"
-version = "1.0.9"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "73b4b750c782965c211b42f022f59af1fbceabdd026623714f104152f1ec149f"
-
-[[package]]
-name = "same-file"
-version = "1.0.6"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "93fc1dc3aaa9bfed95e02e6eadabb4baf7e3078b0bd1b4d7b6b0b68378900502"
-dependencies = [
- "winapi-util",
-]
-
-[[package]]
-name = "scopeguard"
-version = "1.1.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "d29ab0c6d3fc0ee92fe66e2d99f700eab17a8d57d1c1d3b748380fb20baa78cd"
-
-[[package]]
-name = "semver"
-version = "1.0.6"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "a4a3381e03edd24287172047536f20cabde766e2cd3e65e6b00fb3af51c4f38d"
-
-[[package]]
-name = "serde"
-version = "1.0.136"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "ce31e24b01e1e524df96f1c2fdd054405f8d7376249a5110886fb4b658484789"
-dependencies = [
- "serde_derive",
-]
-
-[[package]]
-name = "serde_cbor"
-version = "0.11.2"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "2bef2ebfde456fb76bbcf9f59315333decc4fda0b2b44b420243c11e0f5ec1f5"
-dependencies = [
- "half",
- "serde",
-]
-
-[[package]]
-name = "serde_derive"
-version = "1.0.136"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "08597e7152fcd306f41838ed3e37be9eaeed2b61c42e2117266a554fab4662f9"
-dependencies = [
- "proc-macro2",
- "quote",
- "syn",
-]
-
-[[package]]
-name = "serde_json"
-version = "1.0.79"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "8e8d9fa5c3b304765ce1fd9c4c8a3de2c8db365a5b91be52f186efc675681d95"
-dependencies = [
- "itoa 1.0.1",
- "ryu",
- "serde",
-]
-
-[[package]]
-name = "smallvec"
-version = "1.8.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "f2dd574626839106c320a323308629dcb1acfc96e32a8cba364ddc61ac23ee83"
-
-[[package]]
-name = "smawk"
-version = "0.3.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "f67ad224767faa3c7d8b6d91985b78e70a1324408abcb1cfcc2be4c06bc06043"
-
-[[package]]
-name = "souper-ir"
-version = "2.1.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "a50c18ce33988e1973003afbaa66e6a465ad7a614dc33f246879ccc209c2c044"
-dependencies = [
- "id-arena",
-]
-
-[[package]]
-name = "supports-color"
-version = "1.3.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "4872ced36b91d47bae8a214a683fe54e7078875b399dfa251df346c9b547d1f9"
-dependencies = [
- "atty",
- "is_ci",
-]
-
-[[package]]
-name = "supports-hyperlinks"
-version = "1.2.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "590b34f7c5f01ecc9d78dba4b3f445f31df750a67621cf31626f3b7441ce6406"
-dependencies = [
- "atty",
-]
-
-[[package]]
-name = "supports-unicode"
-version = "1.0.2"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "a8b945e45b417b125a8ec51f1b7df2f8df7920367700d1f98aedd21e5735f8b2"
-dependencies = [
- "atty",
-]
-
-[[package]]
-name = "syn"
-version = "1.0.89"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "ea297be220d52398dcc07ce15a209fce436d361735ac1db700cab3b6cdfb9f54"
-dependencies = [
- "proc-macro2",
- "quote",
- "unicode-xid",
-]
-
-[[package]]
-name = "target-lexicon"
-version = "0.12.3"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "d7fa7e55043acb85fca6b3c01485a2eeb6b69c5d21002e273c79e465f43b7ac1"
-
-[[package]]
-name = "terminal_size"
-version = "0.1.17"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "633c1a546cee861a1a6d0dc69ebeca693bf4296661ba7852b9d21d159e0506df"
-dependencies = [
- "libc",
- "winapi",
-]
-
-[[package]]
-name = "textwrap"
-version = "0.11.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "d326610f408c7a4eb6f51c37c330e496b08506c9457c9d34287ecc38809fb060"
-dependencies = [
- "unicode-width",
-]
-
-[[package]]
-name = "textwrap"
-version = "0.14.2"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "0066c8d12af8b5acd21e00547c3797fde4e8677254a7ee429176ccebbe93dd80"
-dependencies = [
- "smawk",
- "unicode-linebreak",
- "unicode-width",
-]
-
-[[package]]
-name = "thiserror"
-version = "1.0.30"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "854babe52e4df1653706b98fcfc05843010039b406875930a70e4d9644e5c417"
-dependencies = [
- "thiserror-impl",
-]
-
-[[package]]
-name = "thiserror-impl"
-version = "1.0.30"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "aa32fd3f627f367fe16f893e2597ae3c05020f8bba2666a4e6ea73d377e5714b"
-dependencies = [
- "proc-macro2",
- "quote",
- "syn",
-]
-
-[[package]]
-name = "tinytemplate"
-version = "1.2.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "be4d6b5f19ff7664e8c98d03e2139cb510db9b0a60b55f8e8709b689d939b6bc"
-dependencies = [
- "serde",
- "serde_json",
-]
-
-[[package]]
-name = "unicode-linebreak"
-version = "0.1.2"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "3a52dcaab0c48d931f7cc8ef826fa51690a08e1ea55117ef26f89864f532383f"
-dependencies = [
- "regex",
-]
-
-[[package]]
-name = "unicode-width"
-version = "0.1.9"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "3ed742d4ea2bd1176e236172c8429aaf54486e7ac098db29ffe6529e0ce50973"
-
-[[package]]
-name = "unicode-xid"
-version = "0.2.2"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "8ccb82d61f80a663efe1f787a51b16b5a51e3314d6ac365b08639f52387b33f3"
-
-[[package]]
-name = "walkdir"
-version = "2.3.2"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "808cf2735cd4b6866113f648b791c6adc5714537bc222d9347bb203386ffda56"
-dependencies = [
- "same-file",
- "winapi",
- "winapi-util",
-]
-
-[[package]]
-name = "wasm-bindgen"
-version = "0.2.79"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "25f1af7423d8588a3d840681122e72e6a24ddbcb3f0ec385cac0d12d24256c06"
-dependencies = [
- "cfg-if",
- "wasm-bindgen-macro",
-]
-
-[[package]]
-name = "wasm-bindgen-backend"
-version = "0.2.79"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "8b21c0df030f5a177f3cba22e9bc4322695ec43e7257d865302900290bcdedca"
-dependencies = [
- "bumpalo",
- "lazy_static",
- "log",
- "proc-macro2",
- "quote",
- "syn",
- "wasm-bindgen-shared",
-]
-
-[[package]]
-name = "wasm-bindgen-macro"
-version = "0.2.79"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "2f4203d69e40a52ee523b2529a773d5ffc1dc0071801c87b3d270b471b80ed01"
-dependencies = [
- "quote",
- "wasm-bindgen-macro-support",
-]
-
-[[package]]
-name = "wasm-bindgen-macro-support"
-version = "0.2.79"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "bfa8a30d46208db204854cadbb5d4baf5fcf8071ba5bf48190c3e59937962ebc"
-dependencies = [
- "proc-macro2",
- "quote",
- "syn",
- "wasm-bindgen-backend",
- "wasm-bindgen-shared",
-]
-
-[[package]]
-name = "wasm-bindgen-shared"
-version = "0.2.79"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "3d958d035c4438e28c70e4321a2911302f10135ce78a9c7834c0cab4123d06a2"
-
-[[package]]
-name = "web-sys"
-version = "0.3.56"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "c060b319f29dd25724f09a2ba1418f142f539b2be99fbf4d2d5a8f7330afb8eb"
-dependencies = [
- "js-sys",
- "wasm-bindgen",
-]
-
-[[package]]
-name = "winapi"
-version = "0.3.9"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "5c839a674fcd7a98952e593242ea400abe93992746761e38641405d28b00f419"
-dependencies = [
- "winapi-i686-pc-windows-gnu",
- "winapi-x86_64-pc-windows-gnu",
-]
-
-[[package]]
-name = "winapi-i686-pc-windows-gnu"
-version = "0.4.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "ac3b87c63620426dd9b991e5ce0329eff545bccbbb34f3be09ff6fb6ab51b7b6"
-
-[[package]]
-name = "winapi-util"
-version = "0.1.5"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "70ec6ce85bb158151cae5e5c87f95a8e97d2c0c4b001223f33a334e3ce5de178"
-dependencies = [
- "winapi",
-]
-
-[[package]]
-name = "winapi-x86_64-pc-windows-gnu"
-version = "0.4.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "712e227841d057c1ee1cd2fb22fa7e5a5461ae8e48fa2ca79ec42cfc1931183f"
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/Cargo.toml b/collector/compile-benchmarks/cranelift-codegen-0.82.1/Cargo.toml
deleted file mode 100644
index 73f3b7a00..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/Cargo.toml
+++ /dev/null
@@ -1,107 +0,0 @@
-# THIS FILE IS AUTOMATICALLY GENERATED BY CARGO
-#
-# When uploading crates to the registry Cargo will automatically
-# "normalize" Cargo.toml files for maximal compatibility
-# with all versions of Cargo and also rewrite `path` dependencies
-# to registry (e.g., crates.io) dependencies.
-#
-# If you are reading this file be aware that the original Cargo.toml
-# will likely look very different (and much more reasonable).
-# See Cargo.toml.orig for the original contents.
-
-[package]
-edition = "2018"
-name = "cranelift-codegen"
-version = "0.82.1"
-authors = ["The Cranelift Project Developers"]
-build = "build.rs"
-description = "Low-level code generator library"
-documentation = "https://docs.rs/cranelift-codegen"
-readme = "README.md"
-keywords = ["compile", "compiler", "jit"]
-categories = ["no-std"]
-license = "Apache-2.0 WITH LLVM-exception"
-repository = "https://github.com/bytecodealliance/wasmtime"
-resolver = "2"
-
-[[bench]]
-name = "x64-evex-encoding"
-harness = false
-[dependencies.bincode]
-version = "1.2.1"
-optional = true
-
-[dependencies.cranelift-bforest]
-version = "0.82.1"
-
-[dependencies.cranelift-codegen-shared]
-version = "0.82.1"
-
-[dependencies.cranelift-entity]
-version = "0.82.1"
-
-[dependencies.gimli]
-version = "0.26.0"
-features = ["write"]
-optional = true
-default-features = false
-
-[dependencies.hashbrown]
-version = "0.9.1"
-optional = true
-
-[dependencies.log]
-version = "0.4.6"
-default-features = false
-
-[dependencies.regalloc]
-version = "0.0.34"
-
-[dependencies.serde]
-version = "1.0.94"
-features = ["derive"]
-optional = true
-
-[dependencies.smallvec]
-version = "1.6.1"
-
-[dependencies.souper-ir]
-version = "2.1.0"
-optional = true
-
-[dependencies.target-lexicon]
-version = "0.12"
-[dev-dependencies.criterion]
-version = "0.3"
-[build-dependencies.cranelift-codegen-meta]
-version = "0.82.1"
-
-[build-dependencies.cranelift-isle]
-version = "=0.82.1"
-optional = true
-
-[build-dependencies.miette]
-version = "3"
-features = ["fancy"]
-optional = true
-
-[features]
-all-arch = ["x86", "arm64", "s390x"]
-arm64 = []
-completely-skip-isle-for-ci-deterministic-check = []
-core = ["hashbrown"]
-default = ["std", "unwind"]
-enable-serde = ["serde", "regalloc/enable-serde", "cranelift-entity/enable-serde"]
-experimental_x64 = []
-rebuild-isle = ["cranelift-isle", "miette", "cranelift-codegen-meta/rebuild-isle"]
-regalloc-snapshot = ["bincode", "regalloc/enable-serde"]
-s390x = []
-souper-harvest = ["souper-ir", "souper-ir/stringify"]
-std = []
-testing_hooks = []
-unwind = ["gimli"]
-x86 = []
-[badges.maintenance]
-status = "experimental"
-
-[workspace]
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/Cargo.toml.orig b/collector/compile-benchmarks/cranelift-codegen-0.82.1/Cargo.toml.orig
deleted file mode 100644
index de3fabfee..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/Cargo.toml.orig
+++ /dev/null
@@ -1,103 +0,0 @@
-[package]
-authors = ["The Cranelift Project Developers"]
-name = "cranelift-codegen"
-version = "0.82.1"
-description = "Low-level code generator library"
-license = "Apache-2.0 WITH LLVM-exception"
-documentation = "https://docs.rs/cranelift-codegen"
-repository = "https://github.com/bytecodealliance/wasmtime"
-categories = ["no-std"]
-readme = "README.md"
-keywords = ["compile", "compiler", "jit"]
-build = "build.rs"
-edition = "2018"
-
-[dependencies]
-cranelift-codegen-shared = { path = "./shared", version = "0.82.1" }
-cranelift-entity = { path = "../entity", version = "0.82.1" }
-cranelift-bforest = { path = "../bforest", version = "0.82.1" }
-hashbrown = { version = "0.9.1", optional = true }
-target-lexicon = "0.12"
-log = { version = "0.4.6", default-features = false }
-serde = { version = "1.0.94", features = ["derive"], optional = true }
-bincode = { version = "1.2.1", optional = true }
-gimli = { version = "0.26.0", default-features = false, features = ["write"], optional = true }
-smallvec = { version = "1.6.1" }
-regalloc = "0.0.34"
-souper-ir = { version = "2.1.0", optional = true }
-# It is a goal of the cranelift-codegen crate to have minimal external dependencies.
-# Please don't add any unless they are essential to the task of creating binary
-# machine code. Integration tests that need external dependencies can be
-# accomodated in `tests`.
-
-[dev-dependencies]
-criterion = "0.3"
-
-[build-dependencies]
-cranelift-codegen-meta = { path = "meta", version = "0.82.1" }
-cranelift-isle = { path = "../isle/isle", version = "=0.82.1", optional = true }
-miette = { version = "3", features = ["fancy"], optional = true }
-
-[features]
-default = ["std", "unwind"]
-
-# The "std" feature enables use of libstd. The "core" feature enables use
-# of some minimal std-like replacement libraries. At least one of these two
-# features need to be enabled.
-std = []
-
-# The "core" features enables use of "hashbrown" since core doesn't have
-# a HashMap implementation, and a workaround for Cargo #4866.
-core = ["hashbrown"]
-
-# This enables some additional functions useful for writing tests, but which
-# can significantly increase the size of the library.
-testing_hooks = []
-
-# This enables unwind info generation functionality.
-unwind = ["gimli"]
-
-# ISA targets for which we should build.
-# If no ISA targets are explicitly enabled, the ISA target for the host machine is enabled.
-x86 = []
-arm64 = []
-s390x = []
-
-# Stub feature that does nothing, for Cargo-features compatibility: the new
-# backend is the default now.
-experimental_x64 = []
-
-# Option to enable all architectures.
-all-arch = [
-    "x86",
-    "arm64",
-    "s390x"
-]
-
-# For dependent crates that want to serialize some parts of cranelift
-enable-serde = [
-    "serde",
-    "regalloc/enable-serde",
-    "cranelift-entity/enable-serde",
-]
-
-# Allow snapshotting regalloc test cases. Useful only to report bad register
-# allocation failures, or for regalloc.rs developers.
-regalloc-snapshot = ["bincode", "regalloc/enable-serde"]
-
-# Enable support for the Souper harvester.
-souper-harvest = ["souper-ir", "souper-ir/stringify"]
-
-# Recompile ISLE DSL source files into their generated Rust code.
-rebuild-isle = ["cranelift-isle", "miette", "cranelift-codegen-meta/rebuild-isle"]
-
-# A hack to skip the ISLE-rebuild logic when testing for determinism
-# with the "Meta deterministic check" CI job.
-completely-skip-isle-for-ci-deterministic-check = []
-
-[badges]
-maintenance = { status = "experimental" }
-
-[[bench]]
-name = "x64-evex-encoding"
-harness = false
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/LICENSE b/collector/compile-benchmarks/cranelift-codegen-0.82.1/LICENSE
deleted file mode 100644
index f9d81955f..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/LICENSE
+++ /dev/null
@@ -1,220 +0,0 @@
-
-                                 Apache License
-                           Version 2.0, January 2004
-                        http://www.apache.org/licenses/
-
-   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
-
-   1. Definitions.
-
-      "License" shall mean the terms and conditions for use, reproduction,
-      and distribution as defined by Sections 1 through 9 of this document.
-
-      "Licensor" shall mean the copyright owner or entity authorized by
-      the copyright owner that is granting the License.
-
-      "Legal Entity" shall mean the union of the acting entity and all
-      other entities that control, are controlled by, or are under common
-      control with that entity. For the purposes of this definition,
-      "control" means (i) the power, direct or indirect, to cause the
-      direction or management of such entity, whether by contract or
-      otherwise, or (ii) ownership of fifty percent (50%) or more of the
-      outstanding shares, or (iii) beneficial ownership of such entity.
-
-      "You" (or "Your") shall mean an individual or Legal Entity
-      exercising permissions granted by this License.
-
-      "Source" form shall mean the preferred form for making modifications,
-      including but not limited to software source code, documentation
-      source, and configuration files.
-
-      "Object" form shall mean any form resulting from mechanical
-      transformation or translation of a Source form, including but
-      not limited to compiled object code, generated documentation,
-      and conversions to other media types.
-
-      "Work" shall mean the work of authorship, whether in Source or
-      Object form, made available under the License, as indicated by a
-      copyright notice that is included in or attached to the work
-      (an example is provided in the Appendix below).
-
-      "Derivative Works" shall mean any work, whether in Source or Object
-      form, that is based on (or derived from) the Work and for which the
-      editorial revisions, annotations, elaborations, or other modifications
-      represent, as a whole, an original work of authorship. For the purposes
-      of this License, Derivative Works shall not include works that remain
-      separable from, or merely link (or bind by name) to the interfaces of,
-      the Work and Derivative Works thereof.
-
-      "Contribution" shall mean any work of authorship, including
-      the original version of the Work and any modifications or additions
-      to that Work or Derivative Works thereof, that is intentionally
-      submitted to Licensor for inclusion in the Work by the copyright owner
-      or by an individual or Legal Entity authorized to submit on behalf of
-      the copyright owner. For the purposes of this definition, "submitted"
-      means any form of electronic, verbal, or written communication sent
-      to the Licensor or its representatives, including but not limited to
-      communication on electronic mailing lists, source code control systems,
-      and issue tracking systems that are managed by, or on behalf of, the
-      Licensor for the purpose of discussing and improving the Work, but
-      excluding communication that is conspicuously marked or otherwise
-      designated in writing by the copyright owner as "Not a Contribution."
-
-      "Contributor" shall mean Licensor and any individual or Legal Entity
-      on behalf of whom a Contribution has been received by Licensor and
-      subsequently incorporated within the Work.
-
-   2. Grant of Copyright License. Subject to the terms and conditions of
-      this License, each Contributor hereby grants to You a perpetual,
-      worldwide, non-exclusive, no-charge, royalty-free, irrevocable
-      copyright license to reproduce, prepare Derivative Works of,
-      publicly display, publicly perform, sublicense, and distribute the
-      Work and such Derivative Works in Source or Object form.
-
-   3. Grant of Patent License. Subject to the terms and conditions of
-      this License, each Contributor hereby grants to You a perpetual,
-      worldwide, non-exclusive, no-charge, royalty-free, irrevocable
-      (except as stated in this section) patent license to make, have made,
-      use, offer to sell, sell, import, and otherwise transfer the Work,
-      where such license applies only to those patent claims licensable
-      by such Contributor that are necessarily infringed by their
-      Contribution(s) alone or by combination of their Contribution(s)
-      with the Work to which such Contribution(s) was submitted. If You
-      institute patent litigation against any entity (including a
-      cross-claim or counterclaim in a lawsuit) alleging that the Work
-      or a Contribution incorporated within the Work constitutes direct
-      or contributory patent infringement, then any patent licenses
-      granted to You under this License for that Work shall terminate
-      as of the date such litigation is filed.
-
-   4. Redistribution. You may reproduce and distribute copies of the
-      Work or Derivative Works thereof in any medium, with or without
-      modifications, and in Source or Object form, provided that You
-      meet the following conditions:
-
-      (a) You must give any other recipients of the Work or
-          Derivative Works a copy of this License; and
-
-      (b) You must cause any modified files to carry prominent notices
-          stating that You changed the files; and
-
-      (c) You must retain, in the Source form of any Derivative Works
-          that You distribute, all copyright, patent, trademark, and
-          attribution notices from the Source form of the Work,
-          excluding those notices that do not pertain to any part of
-          the Derivative Works; and
-
-      (d) If the Work includes a "NOTICE" text file as part of its
-          distribution, then any Derivative Works that You distribute must
-          include a readable copy of the attribution notices contained
-          within such NOTICE file, excluding those notices that do not
-          pertain to any part of the Derivative Works, in at least one
-          of the following places: within a NOTICE text file distributed
-          as part of the Derivative Works; within the Source form or
-          documentation, if provided along with the Derivative Works; or,
-          within a display generated by the Derivative Works, if and
-          wherever such third-party notices normally appear. The contents
-          of the NOTICE file are for informational purposes only and
-          do not modify the License. You may add Your own attribution
-          notices within Derivative Works that You distribute, alongside
-          or as an addendum to the NOTICE text from the Work, provided
-          that such additional attribution notices cannot be construed
-          as modifying the License.
-
-      You may add Your own copyright statement to Your modifications and
-      may provide additional or different license terms and conditions
-      for use, reproduction, or distribution of Your modifications, or
-      for any such Derivative Works as a whole, provided Your use,
-      reproduction, and distribution of the Work otherwise complies with
-      the conditions stated in this License.
-
-   5. Submission of Contributions. Unless You explicitly state otherwise,
-      any Contribution intentionally submitted for inclusion in the Work
-      by You to the Licensor shall be under the terms and conditions of
-      this License, without any additional terms or conditions.
-      Notwithstanding the above, nothing herein shall supersede or modify
-      the terms of any separate license agreement you may have executed
-      with Licensor regarding such Contributions.
-
-   6. Trademarks. This License does not grant permission to use the trade
-      names, trademarks, service marks, or product names of the Licensor,
-      except as required for reasonable and customary use in describing the
-      origin of the Work and reproducing the content of the NOTICE file.
-
-   7. Disclaimer of Warranty. Unless required by applicable law or
-      agreed to in writing, Licensor provides the Work (and each
-      Contributor provides its Contributions) on an "AS IS" BASIS,
-      WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-      implied, including, without limitation, any warranties or conditions
-      of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A
-      PARTICULAR PURPOSE. You are solely responsible for determining the
-      appropriateness of using or redistributing the Work and assume any
-      risks associated with Your exercise of permissions under this License.
-
-   8. Limitation of Liability. In no event and under no legal theory,
-      whether in tort (including negligence), contract, or otherwise,
-      unless required by applicable law (such as deliberate and grossly
-      negligent acts) or agreed to in writing, shall any Contributor be
-      liable to You for damages, including any direct, indirect, special,
-      incidental, or consequential damages of any character arising as a
-      result of this License or out of the use or inability to use the
-      Work (including but not limited to damages for loss of goodwill,
-      work stoppage, computer failure or malfunction, or any and all
-      other commercial damages or losses), even if such Contributor
-      has been advised of the possibility of such damages.
-
-   9. Accepting Warranty or Additional Liability. While redistributing
-      the Work or Derivative Works thereof, You may choose to offer,
-      and charge a fee for, acceptance of support, warranty, indemnity,
-      or other liability obligations and/or rights consistent with this
-      License. However, in accepting such obligations, You may act only
-      on Your own behalf and on Your sole responsibility, not on behalf
-      of any other Contributor, and only if You agree to indemnify,
-      defend, and hold each Contributor harmless for any liability
-      incurred by, or claims asserted against, such Contributor by reason
-      of your accepting any such warranty or additional liability.
-
-   END OF TERMS AND CONDITIONS
-
-   APPENDIX: How to apply the Apache License to your work.
-
-      To apply the Apache License to your work, attach the following
-      boilerplate notice, with the fields enclosed by brackets "[]"
-      replaced with your own identifying information. (Don't include
-      the brackets!)  The text should be enclosed in the appropriate
-      comment syntax for the file format. We also recommend that a
-      file or class name and description of purpose be included on the
-      same "printed page" as the copyright notice for easier
-      identification within third-party archives.
-
-   Copyright [yyyy] [name of copyright owner]
-
-   Licensed under the Apache License, Version 2.0 (the "License");
-   you may not use this file except in compliance with the License.
-   You may obtain a copy of the License at
-
-       http://www.apache.org/licenses/LICENSE-2.0
-
-   Unless required by applicable law or agreed to in writing, software
-   distributed under the License is distributed on an "AS IS" BASIS,
-   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-   See the License for the specific language governing permissions and
-   limitations under the License.
-
-
---- LLVM Exceptions to the Apache 2.0 License ----
-
-As an exception, if, as a result of your compiling your source code, portions
-of this Software are embedded into an Object form of such source code, you
-may redistribute such embedded portions in such Object form without complying
-with the conditions of Sections 4(a), 4(b) and 4(d) of the License.
-
-In addition, if you combine or link compiled forms of this Software with
-software that is licensed under the GPLv2 ("Combined Software") and if a
-court of competent jurisdiction determines that the patent provision (Section
-3), the indemnity provision (Section 9) or other Section of the License
-conflicts with the conditions of the GPLv2, you may retroactively and
-prospectively choose to deem waived or otherwise exclude such Section(s) of
-the License, but only in their entirety and only with respect to the Combined
-Software.
-
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/README.md b/collector/compile-benchmarks/cranelift-codegen-0.82.1/README.md
deleted file mode 100644
index 18b9756aa..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/README.md
+++ /dev/null
@@ -1,2 +0,0 @@
-This crate contains the core Cranelift code generator. It translates code from an
-intermediate representation into executable machine code.
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/benches/x64-evex-encoding.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/benches/x64-evex-encoding.rs
deleted file mode 100644
index 550e88a0d..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/benches/x64-evex-encoding.rs
+++ /dev/null
@@ -1,55 +0,0 @@
-//! Measure instruction encoding latency using various approaches; the
-//! benchmarking is feature-gated on `x86` since it only measures the encoding
-//! mechanism of that backend.
-
-#[cfg(feature = "x86")]
-mod x86 {
-    use cranelift_codegen::isa::x64::encoding::{
-        evex::{EvexInstruction, EvexVectorLength, Register},
-        rex::{LegacyPrefixes, OpcodeMap},
-    };
-    use criterion::{criterion_group, Criterion};
-
-    // Define the benchmarks.
-    fn x64_evex_encoding_benchmarks(c: &mut Criterion) {
-        let mut group = c.benchmark_group("x64 EVEX encoding");
-        let rax = Register::from(0);
-        let rdx = Register::from(2);
-
-        group.bench_function("EvexInstruction (builder pattern)", |b| {
-            let mut sink = vec![];
-            b.iter(|| {
-                sink.clear();
-                EvexInstruction::new()
-                    .prefix(LegacyPrefixes::_66)
-                    .map(OpcodeMap::_0F38)
-                    .w(true)
-                    .opcode(0x1F)
-                    .reg(rax)
-                    .rm(rdx)
-                    .length(EvexVectorLength::V128)
-                    .encode(&mut sink);
-            });
-        });
-    }
-    criterion_group!(benches, x64_evex_encoding_benchmarks);
-
-    /// Using an inner module to feature-gate the benchmarks means that we must
-    /// manually specify how to run the benchmarks (see `criterion_main!`).
-    pub fn run_benchmarks() {
-        criterion::__warn_about_html_reports_feature();
-        criterion::__warn_about_cargo_bench_support_feature();
-        benches();
-        Criterion::default().configure_from_args().final_summary();
-    }
-}
-
-fn main() {
-    #[cfg(feature = "x86")]
-    x86::run_benchmarks();
-
-    #[cfg(not(feature = "x86"))]
-    println!(
-        "Unable to run the x64-evex-encoding benchmark; the `x86` feature must be enabled in Cargo.",
-    );
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/build.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/build.rs
deleted file mode 100644
index 1b95bf02a..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/build.rs
+++ /dev/null
@@ -1,495 +0,0 @@
-// Build script.
-//
-// This program is run by Cargo when building cranelift-codegen. It is used to generate Rust code from
-// the language definitions in the cranelift-codegen/meta directory.
-//
-// Environment:
-//
-// OUT_DIR
-//     Directory where generated files should be placed.
-//
-// TARGET
-//     Target triple provided by Cargo.
-//
-// The build script expects to be run from the directory where this build.rs file lives. The
-// current directory is used to find the sources.
-
-use cranelift_codegen_meta as meta;
-
-use std::env;
-use std::io::Read;
-use std::process;
-use std::time::Instant;
-
-fn main() {
-    let start_time = Instant::now();
-
-    let out_dir = env::var("OUT_DIR").expect("The OUT_DIR environment variable must be set");
-    let target_triple = env::var("TARGET").expect("The TARGET environment variable must be set");
-
-    let isa_targets = meta::isa::Isa::all()
-        .iter()
-        .cloned()
-        .filter(|isa| {
-            let env_key = format!("CARGO_FEATURE_{}", isa.to_string().to_uppercase());
-            env::var(env_key).is_ok()
-        })
-        .collect::<Vec<_>>();
-
-    let isas = if isa_targets.is_empty() {
-        // Try to match native target.
-        let target_name = target_triple.split('-').next().unwrap();
-        let isa = meta::isa_from_arch(&target_name).expect("error when identifying target");
-        println!("cargo:rustc-cfg=feature=\"{}\"", isa);
-        vec![isa]
-    } else {
-        isa_targets
-    };
-
-    let cur_dir = env::current_dir().expect("Can't access current working directory");
-    let crate_dir = cur_dir.as_path();
-
-    println!("cargo:rerun-if-changed=build.rs");
-
-    if let Err(err) = meta::generate(&isas, &out_dir, crate_dir) {
-        eprintln!("Error: {}", err);
-        process::exit(1);
-    }
-
-    if env::var("CRANELIFT_VERBOSE").is_ok() {
-        for isa in &isas {
-            println!("cargo:warning=Includes support for {} ISA", isa.to_string());
-        }
-        println!(
-            "cargo:warning=Build step took {:?}.",
-            Instant::now() - start_time
-        );
-        println!("cargo:warning=Generated files are in {}", out_dir);
-    }
-
-    // The "Meta deterministic check" CI job runs this build script N
-    // times to ensure it produces the same output
-    // consistently. However, it runs the script in a fresh directory,
-    // without any of the source tree present; this breaks our
-    // manifest check (we need the ISLE source to be present). To keep
-    // things simple, we just disable all ISLE-related logic for this
-    // specific CI job.
-    #[cfg(not(feature = "completely-skip-isle-for-ci-deterministic-check"))]
-    {
-        maybe_rebuild_isle(crate_dir).expect("Unhandled failure in ISLE rebuild");
-    }
-
-    let pkg_version = env::var("CARGO_PKG_VERSION").unwrap();
-    let mut cmd = std::process::Command::new("git");
-    cmd.arg("rev-parse")
-        .arg("HEAD")
-        .stdout(std::process::Stdio::piped())
-        .current_dir(env::var("CARGO_MANIFEST_DIR").unwrap());
-    let version = if let Ok(mut child) = cmd.spawn() {
-        let mut git_rev = String::new();
-        child
-            .stdout
-            .as_mut()
-            .unwrap()
-            .read_to_string(&mut git_rev)
-            .unwrap();
-        let status = child.wait().unwrap();
-        if status.success() {
-            let git_rev = git_rev.trim().chars().take(9).collect::<String>();
-            format!("{}-{}", pkg_version, git_rev)
-        } else {
-            // not a git repo
-            pkg_version
-        }
-    } else {
-        // git not available
-        pkg_version
-    };
-    std::fs::write(
-        std::path::Path::new(&out_dir).join("version.rs"),
-        format!(
-            "/// Version number of this crate. \n\
-            pub const VERSION: &str = \"{}\";",
-            version
-        ),
-    )
-    .unwrap();
-}
-
-/// Strip the current directory from the file paths, because `islec`
-/// includes them in the generated source, and this helps us maintain
-/// deterministic builds that don't include those local file paths.
-fn make_isle_source_path_relative(
-    cur_dir: &std::path::PathBuf,
-    filename: std::path::PathBuf,
-) -> std::path::PathBuf {
-    if let Ok(suffix) = filename.strip_prefix(&cur_dir) {
-        suffix.to_path_buf()
-    } else {
-        filename
-    }
-}
-
-/// A list of compilations (transformations from ISLE source to
-/// generated Rust source) that exist in the repository.
-///
-/// This list is used either to regenerate the Rust source in-tree (if
-/// the `rebuild-isle` feature is enabled), or to verify that the ISLE
-/// source in-tree corresponds to the ISLE source that was last used
-/// to rebuild the Rust source (if the `rebuild-isle` feature is not
-/// enabled).
-#[derive(Clone, Debug)]
-struct IsleCompilations {
-    items: Vec<IsleCompilation>,
-}
-
-#[derive(Clone, Debug)]
-struct IsleCompilation {
-    output: std::path::PathBuf,
-    inputs: Vec<std::path::PathBuf>,
-}
-
-impl IsleCompilation {
-    /// Compute the manifest filename for the given generated Rust file.
-    fn manifest_filename(&self) -> std::path::PathBuf {
-        self.output.with_extension("manifest")
-    }
-
-    /// Compute the content of the source manifest for all ISLE source
-    /// files that go into the compilation of one Rust file.
-    ///
-    /// We store this alongside the `<generated_filename>.rs` file as
-    /// `<generated_filename>.manifest` and use it to verify that a
-    /// rebuild was done if necessary.
-    fn compute_manifest(&self) -> Result<String, Box<dyn std::error::Error + 'static>> {
-        // We use the deprecated SipHasher from std::hash in order to verify
-        // that ISLE sources haven't changed since the generated source was
-        // last regenerated.
-        //
-        // We use this instead of a stronger and more usual content hash, like
-        // SHA-{160,256,512}, because it's built into the standard library and
-        // we don't want to pull in a separate crate. We try to keep Cranelift
-        // crate dependencies as intentionally small as possible. In fact, we
-        // used to use the `sha2` crate for SHA-512 and this turns out to be
-        // undesirable for downstream consumers (see #3609).
-        //
-        // Why not the recommended replacement
-        // `std::collections::hash_map::DefaultHasher`? Because we need the
-        // hash to be deterministic, both between runs (i.e., not seeded with
-        // random state) and across Rust versions.
-        //
-        // If `SipHasher` is ever actually removed from `std`, we'll need to
-        // find a new option, either a very small crate or something else
-        // that's built-in.
-        #![allow(deprecated)]
-        use std::fmt::Write;
-        use std::hash::{Hasher, SipHasher};
-
-        let mut manifest = String::new();
-
-        for filename in &self.inputs {
-            // Our source must be valid UTF-8 for this to work, else user
-            // will get an error on build. This is not expected to be an
-            // issue.
-            let content = std::fs::read_to_string(filename)?;
-            // On Windows, source is checked out with line-endings changed
-            // to `\r\n`; canonicalize the source that we hash to
-            // Unix-style (`\n`) so hashes will match.
-            let content = content.replace("\r\n", "\n");
-            // One line in the manifest: <filename> <siphash>.
-            let mut hasher = SipHasher::new_with_keys(0, 0); // fixed keys for determinism
-            hasher.write(content.as_bytes());
-            let filename = format!("{}", filename.display()).replace("\\", "/");
-            writeln!(&mut manifest, "{} {:x}", filename, hasher.finish())?;
-        }
-
-        Ok(manifest)
-    }
-}
-
-/// Construct the list of compilations (transformations from ISLE
-/// source to generated Rust source) that exist in the repository.
-fn get_isle_compilations(crate_dir: &std::path::Path) -> Result<IsleCompilations, std::io::Error> {
-    let cur_dir = std::env::current_dir()?;
-
-    let clif_isle =
-        make_isle_source_path_relative(&cur_dir, crate_dir.join("src").join("clif.isle"));
-    let prelude_isle =
-        make_isle_source_path_relative(&cur_dir, crate_dir.join("src").join("prelude.isle"));
-    let src_isa_x64 =
-        make_isle_source_path_relative(&cur_dir, crate_dir.join("src").join("isa").join("x64"));
-    let src_isa_aarch64 =
-        make_isle_source_path_relative(&cur_dir, crate_dir.join("src").join("isa").join("aarch64"));
-    let src_isa_s390x =
-        make_isle_source_path_relative(&cur_dir, crate_dir.join("src").join("isa").join("s390x"));
-
-    // This is a set of ISLE compilation units.
-    //
-    // The format of each entry is:
-    //
-    //     (output Rust code file, input ISLE source files)
-    //
-    // There should be one entry for each backend that uses ISLE for lowering,
-    // and if/when we replace our peephole optimization passes with ISLE, there
-    // should be an entry for each of those as well.
-    Ok(IsleCompilations {
-        items: vec![
-            // The x86-64 instruction selector.
-            IsleCompilation {
-                output: src_isa_x64
-                    .join("lower")
-                    .join("isle")
-                    .join("generated_code.rs"),
-                inputs: vec![
-                    clif_isle.clone(),
-                    prelude_isle.clone(),
-                    src_isa_x64.join("inst.isle"),
-                    src_isa_x64.join("lower.isle"),
-                ],
-            },
-            // The aarch64 instruction selector.
-            IsleCompilation {
-                output: src_isa_aarch64
-                    .join("lower")
-                    .join("isle")
-                    .join("generated_code.rs"),
-                inputs: vec![
-                    clif_isle.clone(),
-                    prelude_isle.clone(),
-                    src_isa_aarch64.join("inst.isle"),
-                    src_isa_aarch64.join("lower.isle"),
-                ],
-            },
-            // The s390x instruction selector.
-            IsleCompilation {
-                output: src_isa_s390x
-                    .join("lower")
-                    .join("isle")
-                    .join("generated_code.rs"),
-                inputs: vec![
-                    clif_isle.clone(),
-                    prelude_isle.clone(),
-                    src_isa_s390x.join("inst.isle"),
-                    src_isa_s390x.join("lower.isle"),
-                ],
-            },
-        ],
-    })
-}
-
-/// Check the manifest for the ISLE generated code, which documents
-/// what ISLE source went into generating the Rust, and if there is a
-/// mismatch, either invoke the ISLE compiler (if we have the
-/// `rebuild-isle` feature) or exit with an error (if not).
-///
-/// We do this by computing a hash of the ISLE source and checking it
-/// against a "manifest" that is also checked into git, alongside the
-/// generated Rust.
-///
-/// (Why not include the `rebuild-isle` feature by default? Because
-/// the build process must not modify the checked-in source by
-/// default; any checked-in source is a human-managed bit of data, and
-/// we can only act as an agent of the human developer when explicitly
-/// requested to do so. This manifest check is a middle ground that
-/// ensures this explicit control while also avoiding the easy footgun
-/// of "I changed the ISLE, why isn't the compiler updated?!".)
-fn maybe_rebuild_isle(
-    crate_dir: &std::path::Path,
-) -> Result<(), Box<dyn std::error::Error + 'static>> {
-    let isle_compilations = get_isle_compilations(crate_dir)?;
-    let mut rebuild_compilations = vec![];
-
-    for compilation in &isle_compilations.items {
-        for file in &compilation.inputs {
-            println!("cargo:rerun-if-changed={}", file.display());
-        }
-
-        let manifest =
-            std::fs::read_to_string(compilation.manifest_filename()).unwrap_or(String::new());
-        // Canonicalize Windows line-endings into Unix line-endings in
-        // the manifest text itself.
-        let manifest = manifest.replace("\r\n", "\n");
-        let expected_manifest = compilation.compute_manifest()?.replace("\r\n", "\n");
-        if manifest != expected_manifest {
-            rebuild_compilations.push((compilation, expected_manifest));
-        }
-    }
-
-    #[cfg(feature = "rebuild-isle")]
-    {
-        if !rebuild_compilations.is_empty() {
-            set_miette_hook();
-        }
-        let mut had_error = false;
-        for (compilation, expected_manifest) in rebuild_compilations {
-            if let Err(e) = rebuild_isle(compilation, &expected_manifest) {
-                eprintln!("Error building ISLE files: {:?}", e);
-                let mut source = e.source();
-                while let Some(e) = source {
-                    eprintln!("{:?}", e);
-                    source = e.source();
-                }
-                had_error = true;
-            }
-        }
-
-        if had_error {
-            std::process::exit(1);
-        }
-    }
-
-    #[cfg(not(feature = "rebuild-isle"))]
-    {
-        if !rebuild_compilations.is_empty() {
-            for (compilation, _) in rebuild_compilations {
-                eprintln!("");
-                eprintln!(
-                    "Error: the ISLE source files that resulted in the generated Rust source"
-                );
-                eprintln!("");
-                eprintln!("      * {}", compilation.output.display());
-                eprintln!("");
-                eprintln!(
-                    "have changed but the generated source was not rebuilt! These ISLE source"
-                );
-                eprintln!("files are:");
-                eprintln!("");
-                for file in &compilation.inputs {
-                    eprintln!("       * {}", file.display());
-                }
-            }
-
-            eprintln!("");
-            eprintln!("Please add `--features rebuild-isle` to your `cargo build` command");
-            eprintln!("if you wish to rebuild the generated source, then include these changes");
-            eprintln!("in any git commits you make that include the changes to the ISLE.");
-            eprintln!("");
-            eprintln!("For example:");
-            eprintln!("");
-            eprintln!("  $ cargo build -p cranelift-codegen --features rebuild-isle");
-            eprintln!("");
-            eprintln!("(This build script cannot do this for you by default because we cannot");
-            eprintln!("modify checked-into-git source without your explicit opt-in.)");
-            eprintln!("");
-            std::process::exit(1);
-        }
-    }
-
-    Ok(())
-}
-
-#[cfg(feature = "rebuild-isle")]
-fn set_miette_hook() {
-    use std::sync::Once;
-    static SET_MIETTE_HOOK: Once = Once::new();
-    SET_MIETTE_HOOK.call_once(|| {
-        let _ = miette::set_hook(Box::new(|_| {
-            Box::new(
-                miette::MietteHandlerOpts::new()
-                    // This is necessary for `miette` to properly display errors
-                    // until https://github.com/zkat/miette/issues/93 is fixed.
-                    .force_graphical(true)
-                    .build(),
-            )
-        }));
-    });
-}
-
-/// Rebuild ISLE DSL source text into generated Rust code.
-///
-/// NB: This must happen *after* the `cranelift-codegen-meta` functions, since
-/// it consumes files generated by them.
-#[cfg(feature = "rebuild-isle")]
-fn rebuild_isle(
-    compilation: &IsleCompilation,
-    manifest: &str,
-) -> Result<(), Box<dyn std::error::Error + 'static>> {
-    use cranelift_isle as isle;
-
-    println!("Rebuilding {}", compilation.output.display());
-
-    // First, remove the manifest, if any; we will recreate it
-    // below if the compilation is successful. Ignore error if no
-    // manifest was present.
-    let manifest_filename = compilation.manifest_filename();
-    let _ = std::fs::remove_file(&manifest_filename);
-
-    let code = (|| {
-        let lexer = isle::lexer::Lexer::from_files(&compilation.inputs[..])?;
-        let defs = isle::parser::parse(lexer)?;
-        isle::compile::compile(&defs)
-    })()
-    .map_err(|e| {
-        // Make sure to include the source snippets location info along with
-        // the error messages.
-
-        let report = miette::Report::new(e);
-        return DebugReport(report);
-
-        struct DebugReport(miette::Report);
-
-        impl std::fmt::Display for DebugReport {
-            fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result {
-                self.0.handler().debug(&*self.0, f)
-            }
-        }
-
-        impl std::fmt::Debug for DebugReport {
-            fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result {
-                std::fmt::Display::fmt(self, f)
-            }
-        }
-
-        impl std::error::Error for DebugReport {}
-    })?;
-
-    let code = rustfmt(&code).unwrap_or_else(|e| {
-        println!(
-            "cargo:warning=Failed to run `rustfmt` on ISLE-generated code: {:?}",
-            e
-        );
-        code
-    });
-
-    println!(
-        "Writing ISLE-generated Rust code to {}",
-        compilation.output.display()
-    );
-    std::fs::write(&compilation.output, code)?;
-
-    // Write the manifest so that, in the default build configuration
-    // without the `rebuild-isle` feature, we can at least verify that
-    // no changes were made that will not be picked up. Note that we
-    // only write this *after* we write the source above, so no
-    // manifest is produced if there was an error.
-    std::fs::write(&manifest_filename, manifest)?;
-
-    return Ok(());
-
-    fn rustfmt(code: &str) -> std::io::Result<String> {
-        use std::io::Write;
-
-        let mut rustfmt = std::process::Command::new("rustfmt")
-            .stdin(std::process::Stdio::piped())
-            .stdout(std::process::Stdio::piped())
-            .spawn()?;
-
-        let mut stdin = rustfmt.stdin.take().unwrap();
-        stdin.write_all(code.as_bytes())?;
-        drop(stdin);
-
-        let mut stdout = rustfmt.stdout.take().unwrap();
-        let mut data = vec![];
-        stdout.read_to_end(&mut data)?;
-
-        let status = rustfmt.wait()?;
-        if !status.success() {
-            return Err(std::io::Error::new(
-                std::io::ErrorKind::Other,
-                format!("`rustfmt` exited with status {}", status),
-            ));
-        }
-
-        Ok(String::from_utf8(data).expect("rustfmt always writs utf-8 to stdout"))
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/perf-config.json b/collector/compile-benchmarks/cranelift-codegen-0.82.1/perf-config.json
deleted file mode 100644
index f5204c638..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/perf-config.json
+++ /dev/null
@@ -1,4 +0,0 @@
-{
-    "category": "primary",
-    "artifact": "library"
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/binemit/mod.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/binemit/mod.rs
deleted file mode 100644
index 750eaa2a2..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/binemit/mod.rs
+++ /dev/null
@@ -1,95 +0,0 @@
-//! Binary machine code emission.
-//!
-//! The `binemit` module contains code for translating Cranelift's intermediate representation into
-//! binary machine code.
-
-mod stack_map;
-
-pub use self::stack_map::StackMap;
-use core::fmt;
-#[cfg(feature = "enable-serde")]
-use serde::{Deserialize, Serialize};
-
-/// Offset in bytes from the beginning of the function.
-///
-/// Cranelift can be used as a cross compiler, so we don't want to use a type like `usize` which
-/// depends on the *host* platform, not the *target* platform.
-pub type CodeOffset = u32;
-
-/// Addend to add to the symbol value.
-pub type Addend = i64;
-
-/// Relocation kinds for every ISA
-#[derive(Copy, Clone, Debug, PartialEq, Eq)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub enum Reloc {
-    /// absolute 4-byte
-    Abs4,
-    /// absolute 8-byte
-    Abs8,
-    /// x86 PC-relative 4-byte
-    X86PCRel4,
-    /// x86 call to PC-relative 4-byte
-    X86CallPCRel4,
-    /// x86 call to PLT-relative 4-byte
-    X86CallPLTRel4,
-    /// x86 GOT PC-relative 4-byte
-    X86GOTPCRel4,
-    /// Arm32 call target
-    Arm32Call,
-    /// Arm64 call target. Encoded as bottom 26 bits of instruction. This
-    /// value is sign-extended, multiplied by 4, and added to the PC of
-    /// the call instruction to form the destination address.
-    Arm64Call,
-    /// s390x PC-relative 4-byte offset
-    S390xPCRel32Dbl,
-
-    /// Elf x86_64 32 bit signed PC relative offset to two GOT entries for GD symbol.
-    ElfX86_64TlsGd,
-
-    /// Mach-O x86_64 32 bit signed PC relative offset to a `__thread_vars` entry.
-    MachOX86_64Tlv,
-
-    /// AArch64 TLS GD
-    /// Set an ADRP immediate field to the top 21 bits of the final address. Checks for overflow.
-    /// This is equivalent to `R_AARCH64_TLSGD_ADR_PAGE21` in the [aaelf64](https://github.com/ARM-software/abi-aa/blob/2bcab1e3b22d55170c563c3c7940134089176746/aaelf64/aaelf64.rst#relocations-for-thread-local-storage)
-    Aarch64TlsGdAdrPage21,
-
-    /// AArch64 TLS GD
-    /// Set the add immediate field to the low 12 bits of the final address. Does not check for overflow.
-    /// This is equivalent to `R_AARCH64_TLSGD_ADD_LO12_NC` in the [aaelf64](https://github.com/ARM-software/abi-aa/blob/2bcab1e3b22d55170c563c3c7940134089176746/aaelf64/aaelf64.rst#relocations-for-thread-local-storage)
-    Aarch64TlsGdAddLo12Nc,
-}
-
-impl fmt::Display for Reloc {
-    /// Display trait implementation drops the arch, since its used in contexts where the arch is
-    /// already unambiguous, e.g. clif syntax with isa specified. In other contexts, use Debug.
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        match *self {
-            Self::Abs4 => write!(f, "Abs4"),
-            Self::Abs8 => write!(f, "Abs8"),
-            Self::S390xPCRel32Dbl => write!(f, "PCRel32Dbl"),
-            Self::X86PCRel4 => write!(f, "PCRel4"),
-            Self::X86CallPCRel4 => write!(f, "CallPCRel4"),
-            Self::X86CallPLTRel4 => write!(f, "CallPLTRel4"),
-            Self::X86GOTPCRel4 => write!(f, "GOTPCRel4"),
-            Self::Arm32Call | Self::Arm64Call => write!(f, "Call"),
-
-            Self::ElfX86_64TlsGd => write!(f, "ElfX86_64TlsGd"),
-            Self::MachOX86_64Tlv => write!(f, "MachOX86_64Tlv"),
-            Self::Aarch64TlsGdAdrPage21 => write!(f, "Aarch64TlsGdAdrPage21"),
-            Self::Aarch64TlsGdAddLo12Nc => write!(f, "Aarch64TlsGdAddLo12Nc"),
-        }
-    }
-}
-
-/// Container for information about a vector of compiled code and its supporting read-only data.
-///
-/// The code starts at offset 0 and is followed optionally by relocatable jump tables and copyable
-/// (raw binary) read-only data.  Any padding between sections is always part of the section that
-/// precedes the boundary between the sections.
-#[derive(PartialEq)]
-pub struct CodeInfo {
-    /// Number of bytes in total.
-    pub total_size: CodeOffset,
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/binemit/stack_map.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/binemit/stack_map.rs
deleted file mode 100644
index f9b99269a..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/binemit/stack_map.rs
+++ /dev/null
@@ -1,152 +0,0 @@
-use crate::bitset::BitSet;
-use alloc::vec::Vec;
-
-type Num = u32;
-const NUM_BITS: usize = core::mem::size_of::<Num>() * 8;
-
-/// Stack maps record which words in a stack frame contain live GC references at
-/// a given instruction pointer.
-///
-/// Logically, a set of stack maps for a function record a table of the form:
-///
-/// ```text
-/// +---------------------+-------------------------------------------+
-/// | Instruction Pointer | SP-Relative Offsets of Live GC References |
-/// +---------------------+-------------------------------------------+
-/// | 0x12345678          | 2, 6, 12                                  |
-/// | 0x1234abcd          | 2, 6                                      |
-/// | ...                 | ...                                       |
-/// +---------------------+-------------------------------------------+
-/// ```
-///
-/// Where "instruction pointer" is an instruction pointer within the function,
-/// and "offsets of live GC references" contains the offsets (in units of words)
-/// from the frame's stack pointer where live GC references are stored on the
-/// stack. Instruction pointers within the function that do not have an entry in
-/// this table are not GC safepoints.
-///
-/// Because
-///
-/// * offsets of live GC references are relative from the stack pointer, and
-/// * stack frames grow down from higher addresses to lower addresses,
-///
-/// to get a pointer to a live reference at offset `x` within a stack frame, you
-/// add `x` from the frame's stack pointer.
-///
-/// For example, to calculate the pointer to the live GC reference inside "frame
-/// 1" below, you would do `frame_1_sp + x`:
-///
-/// ```text
-///           Stack
-///         +-------------------+
-///         | Frame 0           |
-///         |                   |
-///    |    |                   |
-///    |    +-------------------+ <--- Frame 0's SP
-///    |    | Frame 1           |
-///  Grows  |                   |
-///  down   |                   |
-///    |    | Live GC reference | --+--
-///    |    |                   |   |
-///    |    |                   |   |
-///    V    |                   |   x = offset of live GC reference
-///         |                   |   |
-///         |                   |   |
-///         +-------------------+ --+--  <--- Frame 1's SP
-///         | Frame 2           |
-///         | ...               |
-/// ```
-///
-/// An individual `StackMap` is associated with just one instruction pointer
-/// within the function, contains the size of the stack frame, and represents
-/// the stack frame as a bitmap. There is one bit per word in the stack frame,
-/// and if the bit is set, then the word contains a live GC reference.
-///
-/// Note that a caller's `OutgoingArg` stack slots and callee's `IncomingArg`
-/// stack slots overlap, so we must choose which function's stack maps record
-/// live GC references in these slots. We record the `IncomingArg`s in the
-/// callee's stack map.
-#[derive(Clone, Debug, PartialEq, Eq)]
-#[cfg_attr(feature = "enable-serde", derive(serde::Deserialize, serde::Serialize))]
-pub struct StackMap {
-    bitmap: Vec<BitSet<Num>>,
-    mapped_words: u32,
-}
-
-impl StackMap {
-    /// Create a vec of Bitsets from a slice of bools.
-    pub fn from_slice(vec: &[bool]) -> Self {
-        let len = vec.len();
-        let num_word = len / NUM_BITS + (len % NUM_BITS != 0) as usize;
-        let mut bitmap = Vec::with_capacity(num_word);
-
-        for segment in vec.chunks(NUM_BITS) {
-            let mut curr_word = 0;
-            for (i, set) in segment.iter().enumerate() {
-                if *set {
-                    curr_word |= 1 << i;
-                }
-            }
-            bitmap.push(BitSet(curr_word));
-        }
-        Self {
-            mapped_words: len as u32,
-            bitmap,
-        }
-    }
-
-    /// Returns a specified bit.
-    pub fn get_bit(&self, bit_index: usize) -> bool {
-        assert!(bit_index < NUM_BITS * self.bitmap.len());
-        let word_index = bit_index / NUM_BITS;
-        let word_offset = (bit_index % NUM_BITS) as u8;
-        self.bitmap[word_index].contains(word_offset)
-    }
-
-    /// Returns the raw bitmap that represents this stack map.
-    pub fn as_slice(&self) -> &[BitSet<u32>] {
-        &self.bitmap
-    }
-
-    /// Returns the number of words represented by this stack map.
-    pub fn mapped_words(&self) -> u32 {
-        self.mapped_words
-    }
-}
-
-#[cfg(test)]
-mod tests {
-    use super::*;
-
-    #[test]
-    fn stack_maps() {
-        let vec: Vec<bool> = Vec::new();
-        assert!(StackMap::from_slice(&vec).bitmap.is_empty());
-
-        let mut vec: [bool; NUM_BITS] = Default::default();
-        let set_true_idx = [5, 7, 24, 31];
-
-        for &idx in &set_true_idx {
-            vec[idx] = true;
-        }
-
-        let mut vec = vec.to_vec();
-        assert_eq!(
-            vec![BitSet::<Num>(2164261024)],
-            StackMap::from_slice(&vec).bitmap
-        );
-
-        vec.push(false);
-        vec.push(true);
-        let res = StackMap::from_slice(&vec);
-        assert_eq!(
-            vec![BitSet::<Num>(2164261024), BitSet::<Num>(2)],
-            res.bitmap
-        );
-
-        assert!(res.get_bit(5));
-        assert!(res.get_bit(31));
-        assert!(res.get_bit(33));
-        assert!(!res.get_bit(1));
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/bitset.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/bitset.rs
deleted file mode 100644
index 2cb0194b5..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/bitset.rs
+++ /dev/null
@@ -1,163 +0,0 @@
-//! Small Bitset
-//!
-//! This module defines a struct `BitSet<T>` encapsulating a bitset built over the type T.
-//! T is intended to be a primitive unsigned type. Currently it can be any type between u8 and u32
-//!
-//! If you would like to add support for larger bitsets in the future, you need to change the trait
-//! bound Into<u32> and the u32 in the implementation of `max_bits()`.
-
-use core::convert::{From, Into};
-use core::mem::size_of;
-use core::ops::{Add, BitOr, Shl, Sub};
-
-/// A small bitset built on a single primitive integer type
-#[derive(Clone, Copy, Debug, PartialEq, Eq)]
-#[cfg_attr(feature = "enable-serde", derive(serde::Serialize, serde::Deserialize))]
-pub struct BitSet<T>(pub T);
-
-impl<T> BitSet<T>
-where
-    T: Into<u32>
-        + From<u8>
-        + BitOr<T, Output = T>
-        + Shl<u8, Output = T>
-        + Sub<T, Output = T>
-        + Add<T, Output = T>
-        + PartialEq
-        + Copy,
-{
-    /// Maximum number of bits supported by this BitSet instance
-    pub fn bits() -> usize {
-        size_of::<T>() * 8
-    }
-
-    /// Maximum number of bits supported by any bitset instance atm.
-    pub fn max_bits() -> usize {
-        size_of::<u32>() * 8
-    }
-
-    /// Check if this BitSet contains the number num
-    pub fn contains(&self, num: u8) -> bool {
-        debug_assert!((num as usize) < Self::bits());
-        debug_assert!((num as usize) < Self::max_bits());
-        self.0.into() & (1 << num) != 0
-    }
-
-    /// Return the smallest number contained in the bitset or None if empty
-    pub fn min(&self) -> Option<u8> {
-        if self.0.into() == 0 {
-            None
-        } else {
-            Some(self.0.into().trailing_zeros() as u8)
-        }
-    }
-
-    /// Return the largest number contained in the bitset or None if empty
-    pub fn max(&self) -> Option<u8> {
-        if self.0.into() == 0 {
-            None
-        } else {
-            let leading_zeroes = self.0.into().leading_zeros() as usize;
-            Some((Self::max_bits() - leading_zeroes - 1) as u8)
-        }
-    }
-
-    /// Construct a BitSet with the half-open range [lo,hi) filled in
-    pub fn from_range(lo: u8, hi: u8) -> Self {
-        debug_assert!(lo <= hi);
-        debug_assert!((hi as usize) <= Self::bits());
-        let one: T = T::from(1);
-        // I can't just do (one << hi) - one here as the shift may overflow
-        let hi_rng = if hi >= 1 {
-            (one << (hi - 1)) + ((one << (hi - 1)) - one)
-        } else {
-            T::from(0)
-        };
-
-        let lo_rng = (one << lo) - one;
-
-        Self(hi_rng - lo_rng)
-    }
-}
-
-#[cfg(test)]
-mod tests {
-    use super::*;
-
-    #[test]
-    fn contains() {
-        let s = BitSet::<u8>(255);
-        for i in 0..7 {
-            assert!(s.contains(i));
-        }
-
-        let s1 = BitSet::<u8>(0);
-        for i in 0..7 {
-            assert!(!s1.contains(i));
-        }
-
-        let s2 = BitSet::<u8>(127);
-        for i in 0..6 {
-            assert!(s2.contains(i));
-        }
-        assert!(!s2.contains(7));
-
-        let s3 = BitSet::<u8>(2 | 4 | 64);
-        assert!(!s3.contains(0) && !s3.contains(3) && !s3.contains(4));
-        assert!(!s3.contains(5) && !s3.contains(7));
-        assert!(s3.contains(1) && s3.contains(2) && s3.contains(6));
-
-        let s4 = BitSet::<u16>(4 | 8 | 256 | 1024);
-        assert!(
-            !s4.contains(0)
-                && !s4.contains(1)
-                && !s4.contains(4)
-                && !s4.contains(5)
-                && !s4.contains(6)
-                && !s4.contains(7)
-                && !s4.contains(9)
-                && !s4.contains(11)
-        );
-        assert!(s4.contains(2) && s4.contains(3) && s4.contains(8) && s4.contains(10));
-    }
-
-    #[test]
-    fn minmax() {
-        let s = BitSet::<u8>(255);
-        assert_eq!(s.min(), Some(0));
-        assert_eq!(s.max(), Some(7));
-        assert!(s.min() == Some(0) && s.max() == Some(7));
-        let s1 = BitSet::<u8>(0);
-        assert!(s1.min() == None && s1.max() == None);
-        let s2 = BitSet::<u8>(127);
-        assert!(s2.min() == Some(0) && s2.max() == Some(6));
-        let s3 = BitSet::<u8>(2 | 4 | 64);
-        assert!(s3.min() == Some(1) && s3.max() == Some(6));
-        let s4 = BitSet::<u16>(4 | 8 | 256 | 1024);
-        assert!(s4.min() == Some(2) && s4.max() == Some(10));
-    }
-
-    #[test]
-    fn from_range() {
-        let s = BitSet::<u8>::from_range(5, 5);
-        assert!(s.0 == 0);
-
-        let s = BitSet::<u8>::from_range(0, 8);
-        assert!(s.0 == 255);
-
-        let s = BitSet::<u16>::from_range(0, 8);
-        assert!(s.0 == 255u16);
-
-        let s = BitSet::<u16>::from_range(0, 16);
-        assert!(s.0 == 65535u16);
-
-        let s = BitSet::<u8>::from_range(5, 6);
-        assert!(s.0 == 32u8);
-
-        let s = BitSet::<u8>::from_range(3, 7);
-        assert!(s.0 == 8 | 16 | 32 | 64);
-
-        let s = BitSet::<u16>::from_range(5, 11);
-        assert!(s.0 == 32 | 64 | 128 | 256 | 512 | 1024);
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/cfg_printer.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/cfg_printer.rs
deleted file mode 100644
index 843b66f27..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/cfg_printer.rs
+++ /dev/null
@@ -1,83 +0,0 @@
-//! The `CFGPrinter` utility.
-
-use alloc::vec::Vec;
-use core::fmt::{Display, Formatter, Result, Write};
-
-use crate::entity::SecondaryMap;
-use crate::flowgraph::{BlockPredecessor, ControlFlowGraph};
-use crate::ir::Function;
-use crate::write::{FuncWriter, PlainWriter};
-
-/// A utility for pretty-printing the CFG of a `Function`.
-pub struct CFGPrinter<'a> {
-    func: &'a Function,
-    cfg: ControlFlowGraph,
-}
-
-/// A utility for pretty-printing the CFG of a `Function`.
-impl<'a> CFGPrinter<'a> {
-    /// Create a new CFGPrinter.
-    pub fn new(func: &'a Function) -> Self {
-        Self {
-            func,
-            cfg: ControlFlowGraph::with_function(func),
-        }
-    }
-
-    /// Write the CFG for this function to `w`.
-    pub fn write(&self, w: &mut dyn Write) -> Result {
-        self.header(w)?;
-        self.block_nodes(w)?;
-        self.cfg_connections(w)?;
-        writeln!(w, "}}")
-    }
-
-    fn header(&self, w: &mut dyn Write) -> Result {
-        writeln!(w, "digraph \"{}\" {{", self.func.name)?;
-        if let Some(entry) = self.func.layout.entry_block() {
-            writeln!(w, "    {{rank=min; {}}}", entry)?;
-        }
-        Ok(())
-    }
-
-    fn block_nodes(&self, w: &mut dyn Write) -> Result {
-        let mut aliases = SecondaryMap::<_, Vec<_>>::new();
-        for v in self.func.dfg.values() {
-            // VADFS returns the immediate target of an alias
-            if let Some(k) = self.func.dfg.value_alias_dest_for_serialization(v) {
-                aliases[k].push(v);
-            }
-        }
-
-        for block in &self.func.layout {
-            write!(w, "    {} [shape=record, label=\"{{", block)?;
-            crate::write::write_block_header(w, self.func, block, 4)?;
-            // Add all outgoing branch instructions to the label.
-            for inst in self.func.layout.block_likely_branches(block) {
-                write!(w, " | <{}>", inst)?;
-                PlainWriter.write_instruction(w, self.func, &aliases, inst, 0)?;
-            }
-            writeln!(w, "}}\"]")?
-        }
-        Ok(())
-    }
-
-    fn cfg_connections(&self, w: &mut dyn Write) -> Result {
-        for block in &self.func.layout {
-            for BlockPredecessor {
-                block: parent,
-                inst,
-            } in self.cfg.pred_iter(block)
-            {
-                writeln!(w, "    {}:{} -> {}", parent, inst, block)?;
-            }
-        }
-        Ok(())
-    }
-}
-
-impl<'a> Display for CFGPrinter<'a> {
-    fn fmt(&self, f: &mut Formatter) -> Result {
-        self.write(f)
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/clif.isle b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/clif.isle
deleted file mode 100644
index afeadf23c..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/clif.isle
+++ /dev/null
@@ -1,1700 +0,0 @@
-;; GENERATED BY `gen_isle`. DO NOT EDIT!!!
-;;
-;; This ISLE file defines all the external type declarations for Cranelift's
-;; data structures that ISLE will process, such as `InstructionData` and
-;; `Opcode`.
-
-;;;; Extern type declarations for immediates ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(type Block (primitive Block))
-(type Constant (primitive Constant))
-(type FuncRef (primitive FuncRef))
-(type GlobalValue (primitive GlobalValue))
-(type Heap (primitive Heap))
-(type Ieee32 (primitive Ieee32))
-(type Ieee64 (primitive Ieee64))
-(type Imm64 (primitive Imm64))
-(type Immediate (primitive Immediate))
-(type JumpTable (primitive JumpTable))
-(type MemFlags (primitive MemFlags))
-(type Offset32 (primitive Offset32))
-(type SigRef (primitive SigRef))
-(type StackSlot (primitive StackSlot))
-(type Table (primitive Table))
-(type Uimm32 (primitive Uimm32))
-(type Uimm8 (primitive Uimm8))
-(type bool (primitive bool))
-
-;;;; Enumerated Immediate: AtomicRmwOp ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(type AtomicRmwOp extern
-    (enum
-        Add
-        And
-        Nand
-        Or
-        Smax
-        Smin
-        Sub
-        Umax
-        Umin
-        Xchg
-        Xor
-    )
-)
-
-;;;; Enumerated Immediate: FloatCC ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(type FloatCC extern
-    (enum
-        Equal
-        GreaterThan
-        GreaterThanOrEqual
-        LessThan
-        LessThanOrEqual
-        NotEqual
-        Ordered
-        OrderedNotEqual
-        Unordered
-        UnorderedOrEqual
-        UnorderedOrGreaterThan
-        UnorderedOrGreaterThanOrEqual
-        UnorderedOrLessThan
-        UnorderedOrLessThanOrEqual
-    )
-)
-
-;;;; Enumerated Immediate: IntCC ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(type IntCC extern
-    (enum
-        Equal
-        NotEqual
-        NotOverflow
-        Overflow
-        SignedGreaterThan
-        SignedGreaterThanOrEqual
-        SignedLessThan
-        SignedLessThanOrEqual
-        UnsignedGreaterThan
-        UnsignedGreaterThanOrEqual
-        UnsignedLessThan
-        UnsignedLessThanOrEqual
-    )
-)
-
-;;;; Enumerated Immediate: TrapCode ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(type TrapCode extern
-    (enum
-        HeapOutOfBounds
-        IntegerDivisionByZero
-        IntegerOverflow
-        StackOverflow
-    )
-)
-
-;;;; Value Arrays ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; ISLE representation of `[Value; 2]`.
-(type ValueArray2 extern (enum))
-
-(decl value_array_2 (Value Value) ValueArray2)
-(extern constructor value_array_2 pack_value_array_2)
-(extern extractor infallible value_array_2 unpack_value_array_2)
-
-;; ISLE representation of `[Value; 3]`.
-(type ValueArray3 extern (enum))
-
-(decl value_array_3 (Value Value Value) ValueArray3)
-(extern constructor value_array_3 pack_value_array_3)
-(extern extractor infallible value_array_3 unpack_value_array_3)
-
-;;;; `Opcode` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(type Opcode extern
-    (enum
-        Jump
-        Brz
-        Brnz
-        BrIcmp
-        Brif
-        Brff
-        BrTable
-        Debugtrap
-        Trap
-        Trapz
-        ResumableTrap
-        Trapnz
-        ResumableTrapnz
-        Trapif
-        Trapff
-        Return
-        FallthroughReturn
-        Call
-        CallIndirect
-        FuncAddr
-        Splat
-        Swizzle
-        Insertlane
-        Extractlane
-        Imin
-        Umin
-        Imax
-        Umax
-        AvgRound
-        UaddSat
-        SaddSat
-        UsubSat
-        SsubSat
-        Load
-        LoadComplex
-        Store
-        StoreComplex
-        Uload8
-        Uload8Complex
-        Sload8
-        Sload8Complex
-        Istore8
-        Istore8Complex
-        Uload16
-        Uload16Complex
-        Sload16
-        Sload16Complex
-        Istore16
-        Istore16Complex
-        Uload32
-        Uload32Complex
-        Sload32
-        Sload32Complex
-        Istore32
-        Istore32Complex
-        Uload8x8
-        Uload8x8Complex
-        Sload8x8
-        Sload8x8Complex
-        Uload16x4
-        Uload16x4Complex
-        Sload16x4
-        Sload16x4Complex
-        Uload32x2
-        Uload32x2Complex
-        Sload32x2
-        Sload32x2Complex
-        StackLoad
-        StackStore
-        StackAddr
-        GlobalValue
-        SymbolValue
-        TlsValue
-        HeapAddr
-        GetPinnedReg
-        SetPinnedReg
-        TableAddr
-        Iconst
-        F32const
-        F64const
-        Bconst
-        Vconst
-        ConstAddr
-        Shuffle
-        Null
-        Nop
-        Select
-        Selectif
-        SelectifSpectreGuard
-        Bitselect
-        Copy
-        IfcmpSp
-        Vsplit
-        Vconcat
-        Vselect
-        VanyTrue
-        VallTrue
-        VhighBits
-        Icmp
-        IcmpImm
-        Ifcmp
-        IfcmpImm
-        Iadd
-        Isub
-        Ineg
-        Iabs
-        Imul
-        Umulhi
-        Smulhi
-        SqmulRoundSat
-        Udiv
-        Sdiv
-        Urem
-        Srem
-        IaddImm
-        ImulImm
-        UdivImm
-        SdivImm
-        UremImm
-        SremImm
-        IrsubImm
-        IaddCin
-        IaddIfcin
-        IaddCout
-        IaddIfcout
-        IaddCarry
-        IaddIfcarry
-        IsubBin
-        IsubIfbin
-        IsubBout
-        IsubIfbout
-        IsubBorrow
-        IsubIfborrow
-        Band
-        Bor
-        Bxor
-        Bnot
-        BandNot
-        BorNot
-        BxorNot
-        BandImm
-        BorImm
-        BxorImm
-        Rotl
-        Rotr
-        RotlImm
-        RotrImm
-        Ishl
-        Ushr
-        Sshr
-        IshlImm
-        UshrImm
-        SshrImm
-        Bitrev
-        Clz
-        Cls
-        Ctz
-        Popcnt
-        Fcmp
-        Ffcmp
-        Fadd
-        Fsub
-        Fmul
-        Fdiv
-        Sqrt
-        Fma
-        Fneg
-        Fabs
-        Fcopysign
-        Fmin
-        FminPseudo
-        Fmax
-        FmaxPseudo
-        Ceil
-        Floor
-        Trunc
-        Nearest
-        IsNull
-        IsInvalid
-        Trueif
-        Trueff
-        Bitcast
-        RawBitcast
-        ScalarToVector
-        Breduce
-        Bextend
-        Bint
-        Bmask
-        Ireduce
-        Snarrow
-        Unarrow
-        Uunarrow
-        SwidenLow
-        SwidenHigh
-        UwidenLow
-        UwidenHigh
-        IaddPairwise
-        WideningPairwiseDotProductS
-        Uextend
-        Sextend
-        Fpromote
-        Fdemote
-        Fvdemote
-        FvpromoteLow
-        FcvtToUint
-        FcvtToUintSat
-        FcvtToSint
-        FcvtToSintSat
-        FcvtFromUint
-        FcvtFromSint
-        FcvtLowFromSint
-        Isplit
-        Iconcat
-        AtomicRmw
-        AtomicCas
-        AtomicLoad
-        AtomicStore
-        Fence
-    )
-)
-
-;;;; `InstructionData` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(type InstructionData extern
-    (enum
-        (AtomicCas (opcode Opcode) (args ValueArray3) (flags MemFlags))
-        (AtomicRmw (opcode Opcode) (args ValueArray2) (flags MemFlags) (op AtomicRmwOp))
-        (Binary (opcode Opcode) (args ValueArray2))
-        (BinaryImm64 (opcode Opcode) (arg Value) (imm Imm64))
-        (BinaryImm8 (opcode Opcode) (arg Value) (imm Uimm8))
-        (Branch (opcode Opcode) (args ValueList) (destination Block))
-        (BranchFloat (opcode Opcode) (args ValueList) (cond FloatCC) (destination Block))
-        (BranchIcmp (opcode Opcode) (args ValueList) (cond IntCC) (destination Block))
-        (BranchInt (opcode Opcode) (args ValueList) (cond IntCC) (destination Block))
-        (BranchTable (opcode Opcode) (arg Value) (destination Block) (table JumpTable))
-        (Call (opcode Opcode) (args ValueList) (func_ref FuncRef))
-        (CallIndirect (opcode Opcode) (args ValueList) (sig_ref SigRef))
-        (CondTrap (opcode Opcode) (arg Value) (code TrapCode))
-        (FloatCompare (opcode Opcode) (args ValueArray2) (cond FloatCC))
-        (FloatCond (opcode Opcode) (arg Value) (cond FloatCC))
-        (FloatCondTrap (opcode Opcode) (arg Value) (cond FloatCC) (code TrapCode))
-        (FuncAddr (opcode Opcode) (func_ref FuncRef))
-        (HeapAddr (opcode Opcode) (arg Value) (heap Heap) (imm Uimm32))
-        (IntCompare (opcode Opcode) (args ValueArray2) (cond IntCC))
-        (IntCompareImm (opcode Opcode) (arg Value) (cond IntCC) (imm Imm64))
-        (IntCond (opcode Opcode) (arg Value) (cond IntCC))
-        (IntCondTrap (opcode Opcode) (arg Value) (cond IntCC) (code TrapCode))
-        (IntSelect (opcode Opcode) (args ValueArray3) (cond IntCC))
-        (Jump (opcode Opcode) (args ValueList) (destination Block))
-        (Load (opcode Opcode) (arg Value) (flags MemFlags) (offset Offset32))
-        (LoadComplex (opcode Opcode) (args ValueList) (flags MemFlags) (offset Offset32))
-        (LoadNoOffset (opcode Opcode) (arg Value) (flags MemFlags))
-        (MultiAry (opcode Opcode) (args ValueList))
-        (NullAry (opcode Opcode))
-        (Shuffle (opcode Opcode) (args ValueArray2) (imm Immediate))
-        (StackLoad (opcode Opcode) (stack_slot StackSlot) (offset Offset32))
-        (StackStore (opcode Opcode) (arg Value) (stack_slot StackSlot) (offset Offset32))
-        (Store (opcode Opcode) (args ValueArray2) (flags MemFlags) (offset Offset32))
-        (StoreComplex (opcode Opcode) (args ValueList) (flags MemFlags) (offset Offset32))
-        (StoreNoOffset (opcode Opcode) (args ValueArray2) (flags MemFlags))
-        (TableAddr (opcode Opcode) (arg Value) (table Table) (offset Offset32))
-        (Ternary (opcode Opcode) (args ValueArray3))
-        (TernaryImm8 (opcode Opcode) (args ValueArray2) (imm Uimm8))
-        (Trap (opcode Opcode) (code TrapCode))
-        (Unary (opcode Opcode) (arg Value))
-        (UnaryBool (opcode Opcode) (imm bool))
-        (UnaryConst (opcode Opcode) (constant_handle Constant))
-        (UnaryGlobalValue (opcode Opcode) (global_value GlobalValue))
-        (UnaryIeee32 (opcode Opcode) (imm Ieee32))
-        (UnaryIeee64 (opcode Opcode) (imm Ieee64))
-        (UnaryImm (opcode Opcode) (imm Imm64))
-    )
-)
-
-;;;; Extracting Opcode, Operands, and Immediates from `InstructionData` ;;;;;;;;
-
-(decl jump (Block ValueSlice) Inst)
-(extractor
-    (jump block args)
-    (inst_data (InstructionData.Jump (Opcode.Jump) (value_list_slice args) block))
-)
-
-(decl brz (Value Block ValueSlice) Inst)
-(extractor
-    (brz c block args)
-    (inst_data (InstructionData.Branch (Opcode.Brz) (unwrap_head_value_list_1 c args) block))
-)
-
-(decl brnz (Value Block ValueSlice) Inst)
-(extractor
-    (brnz c block args)
-    (inst_data (InstructionData.Branch (Opcode.Brnz) (unwrap_head_value_list_1 c args) block))
-)
-
-(decl br_icmp (IntCC Value Value Block ValueSlice) Inst)
-(extractor
-    (br_icmp Cond x y block args)
-    (inst_data (InstructionData.BranchIcmp (Opcode.BrIcmp) (unwrap_head_value_list_2 x y args) Cond block))
-)
-
-(decl brif (IntCC Value Block ValueSlice) Inst)
-(extractor
-    (brif Cond f block args)
-    (inst_data (InstructionData.BranchInt (Opcode.Brif) (unwrap_head_value_list_1 f args) Cond block))
-)
-
-(decl brff (FloatCC Value Block ValueSlice) Inst)
-(extractor
-    (brff Cond f block args)
-    (inst_data (InstructionData.BranchFloat (Opcode.Brff) (unwrap_head_value_list_1 f args) Cond block))
-)
-
-(decl br_table (Value Block JumpTable) Inst)
-(extractor
-    (br_table x block JT)
-    (inst_data (InstructionData.BranchTable (Opcode.BrTable) x block JT))
-)
-
-(decl debugtrap () Inst)
-(extractor
-    (debugtrap )
-    (inst_data (InstructionData.NullAry (Opcode.Debugtrap)))
-)
-
-(decl trap (TrapCode) Inst)
-(extractor
-    (trap code)
-    (inst_data (InstructionData.Trap (Opcode.Trap) code))
-)
-
-(decl trapz (Value TrapCode) Inst)
-(extractor
-    (trapz c code)
-    (inst_data (InstructionData.CondTrap (Opcode.Trapz) c code))
-)
-
-(decl resumable_trap (TrapCode) Inst)
-(extractor
-    (resumable_trap code)
-    (inst_data (InstructionData.Trap (Opcode.ResumableTrap) code))
-)
-
-(decl trapnz (Value TrapCode) Inst)
-(extractor
-    (trapnz c code)
-    (inst_data (InstructionData.CondTrap (Opcode.Trapnz) c code))
-)
-
-(decl resumable_trapnz (Value TrapCode) Inst)
-(extractor
-    (resumable_trapnz c code)
-    (inst_data (InstructionData.CondTrap (Opcode.ResumableTrapnz) c code))
-)
-
-(decl trapif (IntCC Value TrapCode) Inst)
-(extractor
-    (trapif Cond f code)
-    (inst_data (InstructionData.IntCondTrap (Opcode.Trapif) f Cond code))
-)
-
-(decl trapff (FloatCC Value TrapCode) Inst)
-(extractor
-    (trapff Cond f code)
-    (inst_data (InstructionData.FloatCondTrap (Opcode.Trapff) f Cond code))
-)
-
-(decl return (ValueSlice) Inst)
-(extractor
-    (return rvals)
-    (inst_data (InstructionData.MultiAry (Opcode.Return) (value_list_slice rvals)))
-)
-
-(decl fallthrough_return (ValueSlice) Inst)
-(extractor
-    (fallthrough_return rvals)
-    (inst_data (InstructionData.MultiAry (Opcode.FallthroughReturn) (value_list_slice rvals)))
-)
-
-(decl call (FuncRef ValueSlice) Inst)
-(extractor
-    (call FN args)
-    (inst_data (InstructionData.Call (Opcode.Call) (value_list_slice args) FN))
-)
-
-(decl call_indirect (SigRef Value ValueSlice) Inst)
-(extractor
-    (call_indirect SIG callee args)
-    (inst_data (InstructionData.CallIndirect (Opcode.CallIndirect) (unwrap_head_value_list_1 callee args) SIG))
-)
-
-(decl func_addr (FuncRef) Inst)
-(extractor
-    (func_addr FN)
-    (inst_data (InstructionData.FuncAddr (Opcode.FuncAddr) FN))
-)
-
-(decl splat (Value) Inst)
-(extractor
-    (splat x)
-    (inst_data (InstructionData.Unary (Opcode.Splat) x))
-)
-
-(decl swizzle (Value Value) Inst)
-(extractor
-    (swizzle x y)
-    (inst_data (InstructionData.Binary (Opcode.Swizzle) (value_array_2 x y)))
-)
-
-(decl insertlane (Value Value Uimm8) Inst)
-(extractor
-    (insertlane x y Idx)
-    (inst_data (InstructionData.TernaryImm8 (Opcode.Insertlane) (value_array_2 x y) Idx))
-)
-
-(decl extractlane (Value Uimm8) Inst)
-(extractor
-    (extractlane x Idx)
-    (inst_data (InstructionData.BinaryImm8 (Opcode.Extractlane) x Idx))
-)
-
-(decl imin (Value Value) Inst)
-(extractor
-    (imin x y)
-    (inst_data (InstructionData.Binary (Opcode.Imin) (value_array_2 x y)))
-)
-
-(decl umin (Value Value) Inst)
-(extractor
-    (umin x y)
-    (inst_data (InstructionData.Binary (Opcode.Umin) (value_array_2 x y)))
-)
-
-(decl imax (Value Value) Inst)
-(extractor
-    (imax x y)
-    (inst_data (InstructionData.Binary (Opcode.Imax) (value_array_2 x y)))
-)
-
-(decl umax (Value Value) Inst)
-(extractor
-    (umax x y)
-    (inst_data (InstructionData.Binary (Opcode.Umax) (value_array_2 x y)))
-)
-
-(decl avg_round (Value Value) Inst)
-(extractor
-    (avg_round x y)
-    (inst_data (InstructionData.Binary (Opcode.AvgRound) (value_array_2 x y)))
-)
-
-(decl uadd_sat (Value Value) Inst)
-(extractor
-    (uadd_sat x y)
-    (inst_data (InstructionData.Binary (Opcode.UaddSat) (value_array_2 x y)))
-)
-
-(decl sadd_sat (Value Value) Inst)
-(extractor
-    (sadd_sat x y)
-    (inst_data (InstructionData.Binary (Opcode.SaddSat) (value_array_2 x y)))
-)
-
-(decl usub_sat (Value Value) Inst)
-(extractor
-    (usub_sat x y)
-    (inst_data (InstructionData.Binary (Opcode.UsubSat) (value_array_2 x y)))
-)
-
-(decl ssub_sat (Value Value) Inst)
-(extractor
-    (ssub_sat x y)
-    (inst_data (InstructionData.Binary (Opcode.SsubSat) (value_array_2 x y)))
-)
-
-(decl load (MemFlags Value Offset32) Inst)
-(extractor
-    (load MemFlags p Offset)
-    (inst_data (InstructionData.Load (Opcode.Load) p MemFlags Offset))
-)
-
-(decl load_complex (MemFlags ValueSlice Offset32) Inst)
-(extractor
-    (load_complex MemFlags args Offset)
-    (inst_data (InstructionData.LoadComplex (Opcode.LoadComplex) (value_list_slice args) MemFlags Offset))
-)
-
-(decl store (MemFlags Value Value Offset32) Inst)
-(extractor
-    (store MemFlags x p Offset)
-    (inst_data (InstructionData.Store (Opcode.Store) (value_array_2 x p) MemFlags Offset))
-)
-
-(decl store_complex (MemFlags Value ValueSlice Offset32) Inst)
-(extractor
-    (store_complex MemFlags x args Offset)
-    (inst_data (InstructionData.StoreComplex (Opcode.StoreComplex) (unwrap_head_value_list_1 x args) MemFlags Offset))
-)
-
-(decl uload8 (MemFlags Value Offset32) Inst)
-(extractor
-    (uload8 MemFlags p Offset)
-    (inst_data (InstructionData.Load (Opcode.Uload8) p MemFlags Offset))
-)
-
-(decl uload8_complex (MemFlags ValueSlice Offset32) Inst)
-(extractor
-    (uload8_complex MemFlags args Offset)
-    (inst_data (InstructionData.LoadComplex (Opcode.Uload8Complex) (value_list_slice args) MemFlags Offset))
-)
-
-(decl sload8 (MemFlags Value Offset32) Inst)
-(extractor
-    (sload8 MemFlags p Offset)
-    (inst_data (InstructionData.Load (Opcode.Sload8) p MemFlags Offset))
-)
-
-(decl sload8_complex (MemFlags ValueSlice Offset32) Inst)
-(extractor
-    (sload8_complex MemFlags args Offset)
-    (inst_data (InstructionData.LoadComplex (Opcode.Sload8Complex) (value_list_slice args) MemFlags Offset))
-)
-
-(decl istore8 (MemFlags Value Value Offset32) Inst)
-(extractor
-    (istore8 MemFlags x p Offset)
-    (inst_data (InstructionData.Store (Opcode.Istore8) (value_array_2 x p) MemFlags Offset))
-)
-
-(decl istore8_complex (MemFlags Value ValueSlice Offset32) Inst)
-(extractor
-    (istore8_complex MemFlags x args Offset)
-    (inst_data (InstructionData.StoreComplex (Opcode.Istore8Complex) (unwrap_head_value_list_1 x args) MemFlags Offset))
-)
-
-(decl uload16 (MemFlags Value Offset32) Inst)
-(extractor
-    (uload16 MemFlags p Offset)
-    (inst_data (InstructionData.Load (Opcode.Uload16) p MemFlags Offset))
-)
-
-(decl uload16_complex (MemFlags ValueSlice Offset32) Inst)
-(extractor
-    (uload16_complex MemFlags args Offset)
-    (inst_data (InstructionData.LoadComplex (Opcode.Uload16Complex) (value_list_slice args) MemFlags Offset))
-)
-
-(decl sload16 (MemFlags Value Offset32) Inst)
-(extractor
-    (sload16 MemFlags p Offset)
-    (inst_data (InstructionData.Load (Opcode.Sload16) p MemFlags Offset))
-)
-
-(decl sload16_complex (MemFlags ValueSlice Offset32) Inst)
-(extractor
-    (sload16_complex MemFlags args Offset)
-    (inst_data (InstructionData.LoadComplex (Opcode.Sload16Complex) (value_list_slice args) MemFlags Offset))
-)
-
-(decl istore16 (MemFlags Value Value Offset32) Inst)
-(extractor
-    (istore16 MemFlags x p Offset)
-    (inst_data (InstructionData.Store (Opcode.Istore16) (value_array_2 x p) MemFlags Offset))
-)
-
-(decl istore16_complex (MemFlags Value ValueSlice Offset32) Inst)
-(extractor
-    (istore16_complex MemFlags x args Offset)
-    (inst_data (InstructionData.StoreComplex (Opcode.Istore16Complex) (unwrap_head_value_list_1 x args) MemFlags Offset))
-)
-
-(decl uload32 (MemFlags Value Offset32) Inst)
-(extractor
-    (uload32 MemFlags p Offset)
-    (inst_data (InstructionData.Load (Opcode.Uload32) p MemFlags Offset))
-)
-
-(decl uload32_complex (MemFlags ValueSlice Offset32) Inst)
-(extractor
-    (uload32_complex MemFlags args Offset)
-    (inst_data (InstructionData.LoadComplex (Opcode.Uload32Complex) (value_list_slice args) MemFlags Offset))
-)
-
-(decl sload32 (MemFlags Value Offset32) Inst)
-(extractor
-    (sload32 MemFlags p Offset)
-    (inst_data (InstructionData.Load (Opcode.Sload32) p MemFlags Offset))
-)
-
-(decl sload32_complex (MemFlags ValueSlice Offset32) Inst)
-(extractor
-    (sload32_complex MemFlags args Offset)
-    (inst_data (InstructionData.LoadComplex (Opcode.Sload32Complex) (value_list_slice args) MemFlags Offset))
-)
-
-(decl istore32 (MemFlags Value Value Offset32) Inst)
-(extractor
-    (istore32 MemFlags x p Offset)
-    (inst_data (InstructionData.Store (Opcode.Istore32) (value_array_2 x p) MemFlags Offset))
-)
-
-(decl istore32_complex (MemFlags Value ValueSlice Offset32) Inst)
-(extractor
-    (istore32_complex MemFlags x args Offset)
-    (inst_data (InstructionData.StoreComplex (Opcode.Istore32Complex) (unwrap_head_value_list_1 x args) MemFlags Offset))
-)
-
-(decl uload8x8 (MemFlags Value Offset32) Inst)
-(extractor
-    (uload8x8 MemFlags p Offset)
-    (inst_data (InstructionData.Load (Opcode.Uload8x8) p MemFlags Offset))
-)
-
-(decl uload8x8_complex (MemFlags ValueSlice Offset32) Inst)
-(extractor
-    (uload8x8_complex MemFlags args Offset)
-    (inst_data (InstructionData.LoadComplex (Opcode.Uload8x8Complex) (value_list_slice args) MemFlags Offset))
-)
-
-(decl sload8x8 (MemFlags Value Offset32) Inst)
-(extractor
-    (sload8x8 MemFlags p Offset)
-    (inst_data (InstructionData.Load (Opcode.Sload8x8) p MemFlags Offset))
-)
-
-(decl sload8x8_complex (MemFlags ValueSlice Offset32) Inst)
-(extractor
-    (sload8x8_complex MemFlags args Offset)
-    (inst_data (InstructionData.LoadComplex (Opcode.Sload8x8Complex) (value_list_slice args) MemFlags Offset))
-)
-
-(decl uload16x4 (MemFlags Value Offset32) Inst)
-(extractor
-    (uload16x4 MemFlags p Offset)
-    (inst_data (InstructionData.Load (Opcode.Uload16x4) p MemFlags Offset))
-)
-
-(decl uload16x4_complex (MemFlags ValueSlice Offset32) Inst)
-(extractor
-    (uload16x4_complex MemFlags args Offset)
-    (inst_data (InstructionData.LoadComplex (Opcode.Uload16x4Complex) (value_list_slice args) MemFlags Offset))
-)
-
-(decl sload16x4 (MemFlags Value Offset32) Inst)
-(extractor
-    (sload16x4 MemFlags p Offset)
-    (inst_data (InstructionData.Load (Opcode.Sload16x4) p MemFlags Offset))
-)
-
-(decl sload16x4_complex (MemFlags ValueSlice Offset32) Inst)
-(extractor
-    (sload16x4_complex MemFlags args Offset)
-    (inst_data (InstructionData.LoadComplex (Opcode.Sload16x4Complex) (value_list_slice args) MemFlags Offset))
-)
-
-(decl uload32x2 (MemFlags Value Offset32) Inst)
-(extractor
-    (uload32x2 MemFlags p Offset)
-    (inst_data (InstructionData.Load (Opcode.Uload32x2) p MemFlags Offset))
-)
-
-(decl uload32x2_complex (MemFlags ValueSlice Offset32) Inst)
-(extractor
-    (uload32x2_complex MemFlags args Offset)
-    (inst_data (InstructionData.LoadComplex (Opcode.Uload32x2Complex) (value_list_slice args) MemFlags Offset))
-)
-
-(decl sload32x2 (MemFlags Value Offset32) Inst)
-(extractor
-    (sload32x2 MemFlags p Offset)
-    (inst_data (InstructionData.Load (Opcode.Sload32x2) p MemFlags Offset))
-)
-
-(decl sload32x2_complex (MemFlags ValueSlice Offset32) Inst)
-(extractor
-    (sload32x2_complex MemFlags args Offset)
-    (inst_data (InstructionData.LoadComplex (Opcode.Sload32x2Complex) (value_list_slice args) MemFlags Offset))
-)
-
-(decl stack_load (StackSlot Offset32) Inst)
-(extractor
-    (stack_load SS Offset)
-    (inst_data (InstructionData.StackLoad (Opcode.StackLoad) SS Offset))
-)
-
-(decl stack_store (Value StackSlot Offset32) Inst)
-(extractor
-    (stack_store x SS Offset)
-    (inst_data (InstructionData.StackStore (Opcode.StackStore) x SS Offset))
-)
-
-(decl stack_addr (StackSlot Offset32) Inst)
-(extractor
-    (stack_addr SS Offset)
-    (inst_data (InstructionData.StackLoad (Opcode.StackAddr) SS Offset))
-)
-
-(decl global_value (GlobalValue) Inst)
-(extractor
-    (global_value GV)
-    (inst_data (InstructionData.UnaryGlobalValue (Opcode.GlobalValue) GV))
-)
-
-(decl symbol_value (GlobalValue) Inst)
-(extractor
-    (symbol_value GV)
-    (inst_data (InstructionData.UnaryGlobalValue (Opcode.SymbolValue) GV))
-)
-
-(decl tls_value (GlobalValue) Inst)
-(extractor
-    (tls_value GV)
-    (inst_data (InstructionData.UnaryGlobalValue (Opcode.TlsValue) GV))
-)
-
-(decl heap_addr (Heap Value Uimm32) Inst)
-(extractor
-    (heap_addr H p Size)
-    (inst_data (InstructionData.HeapAddr (Opcode.HeapAddr) p H Size))
-)
-
-(decl get_pinned_reg () Inst)
-(extractor
-    (get_pinned_reg )
-    (inst_data (InstructionData.NullAry (Opcode.GetPinnedReg)))
-)
-
-(decl set_pinned_reg (Value) Inst)
-(extractor
-    (set_pinned_reg addr)
-    (inst_data (InstructionData.Unary (Opcode.SetPinnedReg) addr))
-)
-
-(decl table_addr (Table Value Offset32) Inst)
-(extractor
-    (table_addr T p Offset)
-    (inst_data (InstructionData.TableAddr (Opcode.TableAddr) p T Offset))
-)
-
-(decl iconst (Imm64) Inst)
-(extractor
-    (iconst N)
-    (inst_data (InstructionData.UnaryImm (Opcode.Iconst) N))
-)
-
-(decl f32const (Ieee32) Inst)
-(extractor
-    (f32const N)
-    (inst_data (InstructionData.UnaryIeee32 (Opcode.F32const) N))
-)
-
-(decl f64const (Ieee64) Inst)
-(extractor
-    (f64const N)
-    (inst_data (InstructionData.UnaryIeee64 (Opcode.F64const) N))
-)
-
-(decl bconst (bool) Inst)
-(extractor
-    (bconst N)
-    (inst_data (InstructionData.UnaryBool (Opcode.Bconst) N))
-)
-
-(decl vconst (Constant) Inst)
-(extractor
-    (vconst N)
-    (inst_data (InstructionData.UnaryConst (Opcode.Vconst) N))
-)
-
-(decl const_addr (Constant) Inst)
-(extractor
-    (const_addr constant)
-    (inst_data (InstructionData.UnaryConst (Opcode.ConstAddr) constant))
-)
-
-(decl shuffle (Value Value Immediate) Inst)
-(extractor
-    (shuffle a b mask)
-    (inst_data (InstructionData.Shuffle (Opcode.Shuffle) (value_array_2 a b) mask))
-)
-
-(decl null () Inst)
-(extractor
-    (null )
-    (inst_data (InstructionData.NullAry (Opcode.Null)))
-)
-
-(decl nop () Inst)
-(extractor
-    (nop )
-    (inst_data (InstructionData.NullAry (Opcode.Nop)))
-)
-
-(decl select (Value Value Value) Inst)
-(extractor
-    (select c x y)
-    (inst_data (InstructionData.Ternary (Opcode.Select) (value_array_3 c x y)))
-)
-
-(decl selectif (IntCC Value Value Value) Inst)
-(extractor
-    (selectif cc flags x y)
-    (inst_data (InstructionData.IntSelect (Opcode.Selectif) (value_array_3 flags x y) cc))
-)
-
-(decl selectif_spectre_guard (IntCC Value Value Value) Inst)
-(extractor
-    (selectif_spectre_guard cc flags x y)
-    (inst_data (InstructionData.IntSelect (Opcode.SelectifSpectreGuard) (value_array_3 flags x y) cc))
-)
-
-(decl bitselect (Value Value Value) Inst)
-(extractor
-    (bitselect c x y)
-    (inst_data (InstructionData.Ternary (Opcode.Bitselect) (value_array_3 c x y)))
-)
-
-(decl copy (Value) Inst)
-(extractor
-    (copy x)
-    (inst_data (InstructionData.Unary (Opcode.Copy) x))
-)
-
-(decl ifcmp_sp (Value) Inst)
-(extractor
-    (ifcmp_sp addr)
-    (inst_data (InstructionData.Unary (Opcode.IfcmpSp) addr))
-)
-
-(decl vsplit (Value) Inst)
-(extractor
-    (vsplit x)
-    (inst_data (InstructionData.Unary (Opcode.Vsplit) x))
-)
-
-(decl vconcat (Value Value) Inst)
-(extractor
-    (vconcat x y)
-    (inst_data (InstructionData.Binary (Opcode.Vconcat) (value_array_2 x y)))
-)
-
-(decl vselect (Value Value Value) Inst)
-(extractor
-    (vselect c x y)
-    (inst_data (InstructionData.Ternary (Opcode.Vselect) (value_array_3 c x y)))
-)
-
-(decl vany_true (Value) Inst)
-(extractor
-    (vany_true a)
-    (inst_data (InstructionData.Unary (Opcode.VanyTrue) a))
-)
-
-(decl vall_true (Value) Inst)
-(extractor
-    (vall_true a)
-    (inst_data (InstructionData.Unary (Opcode.VallTrue) a))
-)
-
-(decl vhigh_bits (Value) Inst)
-(extractor
-    (vhigh_bits a)
-    (inst_data (InstructionData.Unary (Opcode.VhighBits) a))
-)
-
-(decl icmp (IntCC Value Value) Inst)
-(extractor
-    (icmp Cond x y)
-    (inst_data (InstructionData.IntCompare (Opcode.Icmp) (value_array_2 x y) Cond))
-)
-
-(decl icmp_imm (IntCC Value Imm64) Inst)
-(extractor
-    (icmp_imm Cond x Y)
-    (inst_data (InstructionData.IntCompareImm (Opcode.IcmpImm) x Cond Y))
-)
-
-(decl ifcmp (Value Value) Inst)
-(extractor
-    (ifcmp x y)
-    (inst_data (InstructionData.Binary (Opcode.Ifcmp) (value_array_2 x y)))
-)
-
-(decl ifcmp_imm (Value Imm64) Inst)
-(extractor
-    (ifcmp_imm x Y)
-    (inst_data (InstructionData.BinaryImm64 (Opcode.IfcmpImm) x Y))
-)
-
-(decl iadd (Value Value) Inst)
-(extractor
-    (iadd x y)
-    (inst_data (InstructionData.Binary (Opcode.Iadd) (value_array_2 x y)))
-)
-
-(decl isub (Value Value) Inst)
-(extractor
-    (isub x y)
-    (inst_data (InstructionData.Binary (Opcode.Isub) (value_array_2 x y)))
-)
-
-(decl ineg (Value) Inst)
-(extractor
-    (ineg x)
-    (inst_data (InstructionData.Unary (Opcode.Ineg) x))
-)
-
-(decl iabs (Value) Inst)
-(extractor
-    (iabs x)
-    (inst_data (InstructionData.Unary (Opcode.Iabs) x))
-)
-
-(decl imul (Value Value) Inst)
-(extractor
-    (imul x y)
-    (inst_data (InstructionData.Binary (Opcode.Imul) (value_array_2 x y)))
-)
-
-(decl umulhi (Value Value) Inst)
-(extractor
-    (umulhi x y)
-    (inst_data (InstructionData.Binary (Opcode.Umulhi) (value_array_2 x y)))
-)
-
-(decl smulhi (Value Value) Inst)
-(extractor
-    (smulhi x y)
-    (inst_data (InstructionData.Binary (Opcode.Smulhi) (value_array_2 x y)))
-)
-
-(decl sqmul_round_sat (Value Value) Inst)
-(extractor
-    (sqmul_round_sat x y)
-    (inst_data (InstructionData.Binary (Opcode.SqmulRoundSat) (value_array_2 x y)))
-)
-
-(decl udiv (Value Value) Inst)
-(extractor
-    (udiv x y)
-    (inst_data (InstructionData.Binary (Opcode.Udiv) (value_array_2 x y)))
-)
-
-(decl sdiv (Value Value) Inst)
-(extractor
-    (sdiv x y)
-    (inst_data (InstructionData.Binary (Opcode.Sdiv) (value_array_2 x y)))
-)
-
-(decl urem (Value Value) Inst)
-(extractor
-    (urem x y)
-    (inst_data (InstructionData.Binary (Opcode.Urem) (value_array_2 x y)))
-)
-
-(decl srem (Value Value) Inst)
-(extractor
-    (srem x y)
-    (inst_data (InstructionData.Binary (Opcode.Srem) (value_array_2 x y)))
-)
-
-(decl iadd_imm (Value Imm64) Inst)
-(extractor
-    (iadd_imm x Y)
-    (inst_data (InstructionData.BinaryImm64 (Opcode.IaddImm) x Y))
-)
-
-(decl imul_imm (Value Imm64) Inst)
-(extractor
-    (imul_imm x Y)
-    (inst_data (InstructionData.BinaryImm64 (Opcode.ImulImm) x Y))
-)
-
-(decl udiv_imm (Value Imm64) Inst)
-(extractor
-    (udiv_imm x Y)
-    (inst_data (InstructionData.BinaryImm64 (Opcode.UdivImm) x Y))
-)
-
-(decl sdiv_imm (Value Imm64) Inst)
-(extractor
-    (sdiv_imm x Y)
-    (inst_data (InstructionData.BinaryImm64 (Opcode.SdivImm) x Y))
-)
-
-(decl urem_imm (Value Imm64) Inst)
-(extractor
-    (urem_imm x Y)
-    (inst_data (InstructionData.BinaryImm64 (Opcode.UremImm) x Y))
-)
-
-(decl srem_imm (Value Imm64) Inst)
-(extractor
-    (srem_imm x Y)
-    (inst_data (InstructionData.BinaryImm64 (Opcode.SremImm) x Y))
-)
-
-(decl irsub_imm (Value Imm64) Inst)
-(extractor
-    (irsub_imm x Y)
-    (inst_data (InstructionData.BinaryImm64 (Opcode.IrsubImm) x Y))
-)
-
-(decl iadd_cin (Value Value Value) Inst)
-(extractor
-    (iadd_cin x y c_in)
-    (inst_data (InstructionData.Ternary (Opcode.IaddCin) (value_array_3 x y c_in)))
-)
-
-(decl iadd_ifcin (Value Value Value) Inst)
-(extractor
-    (iadd_ifcin x y c_in)
-    (inst_data (InstructionData.Ternary (Opcode.IaddIfcin) (value_array_3 x y c_in)))
-)
-
-(decl iadd_cout (Value Value) Inst)
-(extractor
-    (iadd_cout x y)
-    (inst_data (InstructionData.Binary (Opcode.IaddCout) (value_array_2 x y)))
-)
-
-(decl iadd_ifcout (Value Value) Inst)
-(extractor
-    (iadd_ifcout x y)
-    (inst_data (InstructionData.Binary (Opcode.IaddIfcout) (value_array_2 x y)))
-)
-
-(decl iadd_carry (Value Value Value) Inst)
-(extractor
-    (iadd_carry x y c_in)
-    (inst_data (InstructionData.Ternary (Opcode.IaddCarry) (value_array_3 x y c_in)))
-)
-
-(decl iadd_ifcarry (Value Value Value) Inst)
-(extractor
-    (iadd_ifcarry x y c_in)
-    (inst_data (InstructionData.Ternary (Opcode.IaddIfcarry) (value_array_3 x y c_in)))
-)
-
-(decl isub_bin (Value Value Value) Inst)
-(extractor
-    (isub_bin x y b_in)
-    (inst_data (InstructionData.Ternary (Opcode.IsubBin) (value_array_3 x y b_in)))
-)
-
-(decl isub_ifbin (Value Value Value) Inst)
-(extractor
-    (isub_ifbin x y b_in)
-    (inst_data (InstructionData.Ternary (Opcode.IsubIfbin) (value_array_3 x y b_in)))
-)
-
-(decl isub_bout (Value Value) Inst)
-(extractor
-    (isub_bout x y)
-    (inst_data (InstructionData.Binary (Opcode.IsubBout) (value_array_2 x y)))
-)
-
-(decl isub_ifbout (Value Value) Inst)
-(extractor
-    (isub_ifbout x y)
-    (inst_data (InstructionData.Binary (Opcode.IsubIfbout) (value_array_2 x y)))
-)
-
-(decl isub_borrow (Value Value Value) Inst)
-(extractor
-    (isub_borrow x y b_in)
-    (inst_data (InstructionData.Ternary (Opcode.IsubBorrow) (value_array_3 x y b_in)))
-)
-
-(decl isub_ifborrow (Value Value Value) Inst)
-(extractor
-    (isub_ifborrow x y b_in)
-    (inst_data (InstructionData.Ternary (Opcode.IsubIfborrow) (value_array_3 x y b_in)))
-)
-
-(decl band (Value Value) Inst)
-(extractor
-    (band x y)
-    (inst_data (InstructionData.Binary (Opcode.Band) (value_array_2 x y)))
-)
-
-(decl bor (Value Value) Inst)
-(extractor
-    (bor x y)
-    (inst_data (InstructionData.Binary (Opcode.Bor) (value_array_2 x y)))
-)
-
-(decl bxor (Value Value) Inst)
-(extractor
-    (bxor x y)
-    (inst_data (InstructionData.Binary (Opcode.Bxor) (value_array_2 x y)))
-)
-
-(decl bnot (Value) Inst)
-(extractor
-    (bnot x)
-    (inst_data (InstructionData.Unary (Opcode.Bnot) x))
-)
-
-(decl band_not (Value Value) Inst)
-(extractor
-    (band_not x y)
-    (inst_data (InstructionData.Binary (Opcode.BandNot) (value_array_2 x y)))
-)
-
-(decl bor_not (Value Value) Inst)
-(extractor
-    (bor_not x y)
-    (inst_data (InstructionData.Binary (Opcode.BorNot) (value_array_2 x y)))
-)
-
-(decl bxor_not (Value Value) Inst)
-(extractor
-    (bxor_not x y)
-    (inst_data (InstructionData.Binary (Opcode.BxorNot) (value_array_2 x y)))
-)
-
-(decl band_imm (Value Imm64) Inst)
-(extractor
-    (band_imm x Y)
-    (inst_data (InstructionData.BinaryImm64 (Opcode.BandImm) x Y))
-)
-
-(decl bor_imm (Value Imm64) Inst)
-(extractor
-    (bor_imm x Y)
-    (inst_data (InstructionData.BinaryImm64 (Opcode.BorImm) x Y))
-)
-
-(decl bxor_imm (Value Imm64) Inst)
-(extractor
-    (bxor_imm x Y)
-    (inst_data (InstructionData.BinaryImm64 (Opcode.BxorImm) x Y))
-)
-
-(decl rotl (Value Value) Inst)
-(extractor
-    (rotl x y)
-    (inst_data (InstructionData.Binary (Opcode.Rotl) (value_array_2 x y)))
-)
-
-(decl rotr (Value Value) Inst)
-(extractor
-    (rotr x y)
-    (inst_data (InstructionData.Binary (Opcode.Rotr) (value_array_2 x y)))
-)
-
-(decl rotl_imm (Value Imm64) Inst)
-(extractor
-    (rotl_imm x Y)
-    (inst_data (InstructionData.BinaryImm64 (Opcode.RotlImm) x Y))
-)
-
-(decl rotr_imm (Value Imm64) Inst)
-(extractor
-    (rotr_imm x Y)
-    (inst_data (InstructionData.BinaryImm64 (Opcode.RotrImm) x Y))
-)
-
-(decl ishl (Value Value) Inst)
-(extractor
-    (ishl x y)
-    (inst_data (InstructionData.Binary (Opcode.Ishl) (value_array_2 x y)))
-)
-
-(decl ushr (Value Value) Inst)
-(extractor
-    (ushr x y)
-    (inst_data (InstructionData.Binary (Opcode.Ushr) (value_array_2 x y)))
-)
-
-(decl sshr (Value Value) Inst)
-(extractor
-    (sshr x y)
-    (inst_data (InstructionData.Binary (Opcode.Sshr) (value_array_2 x y)))
-)
-
-(decl ishl_imm (Value Imm64) Inst)
-(extractor
-    (ishl_imm x Y)
-    (inst_data (InstructionData.BinaryImm64 (Opcode.IshlImm) x Y))
-)
-
-(decl ushr_imm (Value Imm64) Inst)
-(extractor
-    (ushr_imm x Y)
-    (inst_data (InstructionData.BinaryImm64 (Opcode.UshrImm) x Y))
-)
-
-(decl sshr_imm (Value Imm64) Inst)
-(extractor
-    (sshr_imm x Y)
-    (inst_data (InstructionData.BinaryImm64 (Opcode.SshrImm) x Y))
-)
-
-(decl bitrev (Value) Inst)
-(extractor
-    (bitrev x)
-    (inst_data (InstructionData.Unary (Opcode.Bitrev) x))
-)
-
-(decl clz (Value) Inst)
-(extractor
-    (clz x)
-    (inst_data (InstructionData.Unary (Opcode.Clz) x))
-)
-
-(decl cls (Value) Inst)
-(extractor
-    (cls x)
-    (inst_data (InstructionData.Unary (Opcode.Cls) x))
-)
-
-(decl ctz (Value) Inst)
-(extractor
-    (ctz x)
-    (inst_data (InstructionData.Unary (Opcode.Ctz) x))
-)
-
-(decl popcnt (Value) Inst)
-(extractor
-    (popcnt x)
-    (inst_data (InstructionData.Unary (Opcode.Popcnt) x))
-)
-
-(decl fcmp (FloatCC Value Value) Inst)
-(extractor
-    (fcmp Cond x y)
-    (inst_data (InstructionData.FloatCompare (Opcode.Fcmp) (value_array_2 x y) Cond))
-)
-
-(decl ffcmp (Value Value) Inst)
-(extractor
-    (ffcmp x y)
-    (inst_data (InstructionData.Binary (Opcode.Ffcmp) (value_array_2 x y)))
-)
-
-(decl fadd (Value Value) Inst)
-(extractor
-    (fadd x y)
-    (inst_data (InstructionData.Binary (Opcode.Fadd) (value_array_2 x y)))
-)
-
-(decl fsub (Value Value) Inst)
-(extractor
-    (fsub x y)
-    (inst_data (InstructionData.Binary (Opcode.Fsub) (value_array_2 x y)))
-)
-
-(decl fmul (Value Value) Inst)
-(extractor
-    (fmul x y)
-    (inst_data (InstructionData.Binary (Opcode.Fmul) (value_array_2 x y)))
-)
-
-(decl fdiv (Value Value) Inst)
-(extractor
-    (fdiv x y)
-    (inst_data (InstructionData.Binary (Opcode.Fdiv) (value_array_2 x y)))
-)
-
-(decl sqrt (Value) Inst)
-(extractor
-    (sqrt x)
-    (inst_data (InstructionData.Unary (Opcode.Sqrt) x))
-)
-
-(decl fma (Value Value Value) Inst)
-(extractor
-    (fma x y z)
-    (inst_data (InstructionData.Ternary (Opcode.Fma) (value_array_3 x y z)))
-)
-
-(decl fneg (Value) Inst)
-(extractor
-    (fneg x)
-    (inst_data (InstructionData.Unary (Opcode.Fneg) x))
-)
-
-(decl fabs (Value) Inst)
-(extractor
-    (fabs x)
-    (inst_data (InstructionData.Unary (Opcode.Fabs) x))
-)
-
-(decl fcopysign (Value Value) Inst)
-(extractor
-    (fcopysign x y)
-    (inst_data (InstructionData.Binary (Opcode.Fcopysign) (value_array_2 x y)))
-)
-
-(decl fmin (Value Value) Inst)
-(extractor
-    (fmin x y)
-    (inst_data (InstructionData.Binary (Opcode.Fmin) (value_array_2 x y)))
-)
-
-(decl fmin_pseudo (Value Value) Inst)
-(extractor
-    (fmin_pseudo x y)
-    (inst_data (InstructionData.Binary (Opcode.FminPseudo) (value_array_2 x y)))
-)
-
-(decl fmax (Value Value) Inst)
-(extractor
-    (fmax x y)
-    (inst_data (InstructionData.Binary (Opcode.Fmax) (value_array_2 x y)))
-)
-
-(decl fmax_pseudo (Value Value) Inst)
-(extractor
-    (fmax_pseudo x y)
-    (inst_data (InstructionData.Binary (Opcode.FmaxPseudo) (value_array_2 x y)))
-)
-
-(decl ceil (Value) Inst)
-(extractor
-    (ceil x)
-    (inst_data (InstructionData.Unary (Opcode.Ceil) x))
-)
-
-(decl floor (Value) Inst)
-(extractor
-    (floor x)
-    (inst_data (InstructionData.Unary (Opcode.Floor) x))
-)
-
-(decl trunc (Value) Inst)
-(extractor
-    (trunc x)
-    (inst_data (InstructionData.Unary (Opcode.Trunc) x))
-)
-
-(decl nearest (Value) Inst)
-(extractor
-    (nearest x)
-    (inst_data (InstructionData.Unary (Opcode.Nearest) x))
-)
-
-(decl is_null (Value) Inst)
-(extractor
-    (is_null x)
-    (inst_data (InstructionData.Unary (Opcode.IsNull) x))
-)
-
-(decl is_invalid (Value) Inst)
-(extractor
-    (is_invalid x)
-    (inst_data (InstructionData.Unary (Opcode.IsInvalid) x))
-)
-
-(decl trueif (IntCC Value) Inst)
-(extractor
-    (trueif Cond f)
-    (inst_data (InstructionData.IntCond (Opcode.Trueif) f Cond))
-)
-
-(decl trueff (FloatCC Value) Inst)
-(extractor
-    (trueff Cond f)
-    (inst_data (InstructionData.FloatCond (Opcode.Trueff) f Cond))
-)
-
-(decl bitcast (Value) Inst)
-(extractor
-    (bitcast x)
-    (inst_data (InstructionData.Unary (Opcode.Bitcast) x))
-)
-
-(decl raw_bitcast (Value) Inst)
-(extractor
-    (raw_bitcast x)
-    (inst_data (InstructionData.Unary (Opcode.RawBitcast) x))
-)
-
-(decl scalar_to_vector (Value) Inst)
-(extractor
-    (scalar_to_vector s)
-    (inst_data (InstructionData.Unary (Opcode.ScalarToVector) s))
-)
-
-(decl breduce (Value) Inst)
-(extractor
-    (breduce x)
-    (inst_data (InstructionData.Unary (Opcode.Breduce) x))
-)
-
-(decl bextend (Value) Inst)
-(extractor
-    (bextend x)
-    (inst_data (InstructionData.Unary (Opcode.Bextend) x))
-)
-
-(decl bint (Value) Inst)
-(extractor
-    (bint x)
-    (inst_data (InstructionData.Unary (Opcode.Bint) x))
-)
-
-(decl bmask (Value) Inst)
-(extractor
-    (bmask x)
-    (inst_data (InstructionData.Unary (Opcode.Bmask) x))
-)
-
-(decl ireduce (Value) Inst)
-(extractor
-    (ireduce x)
-    (inst_data (InstructionData.Unary (Opcode.Ireduce) x))
-)
-
-(decl snarrow (Value Value) Inst)
-(extractor
-    (snarrow x y)
-    (inst_data (InstructionData.Binary (Opcode.Snarrow) (value_array_2 x y)))
-)
-
-(decl unarrow (Value Value) Inst)
-(extractor
-    (unarrow x y)
-    (inst_data (InstructionData.Binary (Opcode.Unarrow) (value_array_2 x y)))
-)
-
-(decl uunarrow (Value Value) Inst)
-(extractor
-    (uunarrow x y)
-    (inst_data (InstructionData.Binary (Opcode.Uunarrow) (value_array_2 x y)))
-)
-
-(decl swiden_low (Value) Inst)
-(extractor
-    (swiden_low x)
-    (inst_data (InstructionData.Unary (Opcode.SwidenLow) x))
-)
-
-(decl swiden_high (Value) Inst)
-(extractor
-    (swiden_high x)
-    (inst_data (InstructionData.Unary (Opcode.SwidenHigh) x))
-)
-
-(decl uwiden_low (Value) Inst)
-(extractor
-    (uwiden_low x)
-    (inst_data (InstructionData.Unary (Opcode.UwidenLow) x))
-)
-
-(decl uwiden_high (Value) Inst)
-(extractor
-    (uwiden_high x)
-    (inst_data (InstructionData.Unary (Opcode.UwidenHigh) x))
-)
-
-(decl iadd_pairwise (Value Value) Inst)
-(extractor
-    (iadd_pairwise x y)
-    (inst_data (InstructionData.Binary (Opcode.IaddPairwise) (value_array_2 x y)))
-)
-
-(decl widening_pairwise_dot_product_s (Value Value) Inst)
-(extractor
-    (widening_pairwise_dot_product_s x y)
-    (inst_data (InstructionData.Binary (Opcode.WideningPairwiseDotProductS) (value_array_2 x y)))
-)
-
-(decl uextend (Value) Inst)
-(extractor
-    (uextend x)
-    (inst_data (InstructionData.Unary (Opcode.Uextend) x))
-)
-
-(decl sextend (Value) Inst)
-(extractor
-    (sextend x)
-    (inst_data (InstructionData.Unary (Opcode.Sextend) x))
-)
-
-(decl fpromote (Value) Inst)
-(extractor
-    (fpromote x)
-    (inst_data (InstructionData.Unary (Opcode.Fpromote) x))
-)
-
-(decl fdemote (Value) Inst)
-(extractor
-    (fdemote x)
-    (inst_data (InstructionData.Unary (Opcode.Fdemote) x))
-)
-
-(decl fvdemote (Value) Inst)
-(extractor
-    (fvdemote x)
-    (inst_data (InstructionData.Unary (Opcode.Fvdemote) x))
-)
-
-(decl fvpromote_low (Value) Inst)
-(extractor
-    (fvpromote_low a)
-    (inst_data (InstructionData.Unary (Opcode.FvpromoteLow) a))
-)
-
-(decl fcvt_to_uint (Value) Inst)
-(extractor
-    (fcvt_to_uint x)
-    (inst_data (InstructionData.Unary (Opcode.FcvtToUint) x))
-)
-
-(decl fcvt_to_uint_sat (Value) Inst)
-(extractor
-    (fcvt_to_uint_sat x)
-    (inst_data (InstructionData.Unary (Opcode.FcvtToUintSat) x))
-)
-
-(decl fcvt_to_sint (Value) Inst)
-(extractor
-    (fcvt_to_sint x)
-    (inst_data (InstructionData.Unary (Opcode.FcvtToSint) x))
-)
-
-(decl fcvt_to_sint_sat (Value) Inst)
-(extractor
-    (fcvt_to_sint_sat x)
-    (inst_data (InstructionData.Unary (Opcode.FcvtToSintSat) x))
-)
-
-(decl fcvt_from_uint (Value) Inst)
-(extractor
-    (fcvt_from_uint x)
-    (inst_data (InstructionData.Unary (Opcode.FcvtFromUint) x))
-)
-
-(decl fcvt_from_sint (Value) Inst)
-(extractor
-    (fcvt_from_sint x)
-    (inst_data (InstructionData.Unary (Opcode.FcvtFromSint) x))
-)
-
-(decl fcvt_low_from_sint (Value) Inst)
-(extractor
-    (fcvt_low_from_sint x)
-    (inst_data (InstructionData.Unary (Opcode.FcvtLowFromSint) x))
-)
-
-(decl isplit (Value) Inst)
-(extractor
-    (isplit x)
-    (inst_data (InstructionData.Unary (Opcode.Isplit) x))
-)
-
-(decl iconcat (Value Value) Inst)
-(extractor
-    (iconcat lo hi)
-    (inst_data (InstructionData.Binary (Opcode.Iconcat) (value_array_2 lo hi)))
-)
-
-(decl atomic_rmw (MemFlags AtomicRmwOp Value Value) Inst)
-(extractor
-    (atomic_rmw MemFlags AtomicRmwOp p x)
-    (inst_data (InstructionData.AtomicRmw (Opcode.AtomicRmw) (value_array_2 p x) MemFlags AtomicRmwOp))
-)
-
-(decl atomic_cas (MemFlags Value Value Value) Inst)
-(extractor
-    (atomic_cas MemFlags p e x)
-    (inst_data (InstructionData.AtomicCas (Opcode.AtomicCas) (value_array_3 p e x) MemFlags))
-)
-
-(decl atomic_load (MemFlags Value) Inst)
-(extractor
-    (atomic_load MemFlags p)
-    (inst_data (InstructionData.LoadNoOffset (Opcode.AtomicLoad) p MemFlags))
-)
-
-(decl atomic_store (MemFlags Value Value) Inst)
-(extractor
-    (atomic_store MemFlags x p)
-    (inst_data (InstructionData.StoreNoOffset (Opcode.AtomicStore) (value_array_2 x p) MemFlags))
-)
-
-(decl fence () Inst)
-(extractor
-    (fence )
-    (inst_data (InstructionData.NullAry (Opcode.Fence)))
-)
-
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/constant_hash.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/constant_hash.rs
deleted file mode 100644
index 1de2a2edb..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/constant_hash.rs
+++ /dev/null
@@ -1,62 +0,0 @@
-//! Runtime support for precomputed constant hash tables.
-//!
-//! The shared module with the same name can generate constant hash tables using open addressing
-//! and quadratic probing.
-//!
-//! The hash tables are arrays that are guaranteed to:
-//!
-//! - Have a power-of-two size.
-//! - Contain at least one empty slot.
-//!
-//! This module provides runtime support for lookups in these tables.
-
-// Re-export entities from constant_hash for simplicity of use.
-pub use cranelift_codegen_shared::constant_hash::*;
-
-/// Trait that must be implemented by the entries in a constant hash table.
-pub trait Table<K: Copy + Eq> {
-    /// Get the number of entries in this table which must be a power of two.
-    fn len(&self) -> usize;
-
-    /// Get the key corresponding to the entry at `idx`, or `None` if the entry is empty.
-    /// The `idx` must be in range.
-    fn key(&self, idx: usize) -> Option<K>;
-}
-
-/// Look for `key` in `table`.
-///
-/// The provided `hash` value must have been computed from `key` using the same hash function that
-/// was used to construct the table.
-///
-/// Returns `Ok(idx)` with the table index containing the found entry, or `Err(idx)` with the empty
-/// sentinel entry if no entry could be found.
-pub fn probe<K: Copy + Eq, T: Table<K> + ?Sized>(
-    table: &T,
-    key: K,
-    hash: usize,
-) -> Result<usize, usize> {
-    debug_assert!(table.len().is_power_of_two());
-    let mask = table.len() - 1;
-
-    let mut idx = hash;
-    let mut step = 0;
-
-    loop {
-        idx &= mask;
-
-        match table.key(idx) {
-            None => return Err(idx),
-            Some(k) if k == key => return Ok(idx),
-            _ => {}
-        }
-
-        // Quadratic probing.
-        step += 1;
-
-        // When `table.len()` is a power of two, it can be proven that `idx` will visit all
-        // entries. This means that this loop will always terminate if the hash table has even
-        // one unused entry.
-        debug_assert!(step < table.len());
-        idx += step;
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/context.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/context.rs
deleted file mode 100644
index 91781d189..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/context.rs
+++ /dev/null
@@ -1,352 +0,0 @@
-//! Cranelift compilation context and main entry point.
-//!
-//! When compiling many small functions, it is important to avoid repeatedly allocating and
-//! deallocating the data structures needed for compilation. The `Context` struct is used to hold
-//! on to memory allocations between function compilations.
-//!
-//! The context does not hold a `TargetIsa` instance which has to be provided as an argument
-//! instead. This is because an ISA instance is immutable and can be used by multiple compilation
-//! contexts concurrently. Typically, you would have one context per compilation thread and only a
-//! single ISA instance.
-
-use crate::binemit::CodeInfo;
-use crate::dce::do_dce;
-use crate::dominator_tree::DominatorTree;
-use crate::flowgraph::ControlFlowGraph;
-use crate::ir::Function;
-use crate::isa::TargetIsa;
-use crate::legalizer::simple_legalize;
-use crate::licm::do_licm;
-use crate::loop_analysis::LoopAnalysis;
-use crate::machinst::MachCompileResult;
-use crate::nan_canonicalization::do_nan_canonicalization;
-use crate::remove_constant_phis::do_remove_constant_phis;
-use crate::result::CodegenResult;
-use crate::settings::{FlagsOrIsa, OptLevel};
-use crate::simple_gvn::do_simple_gvn;
-use crate::simple_preopt::do_preopt;
-use crate::timing;
-use crate::unreachable_code::eliminate_unreachable_code;
-use crate::verifier::{verify_context, VerifierErrors, VerifierResult};
-#[cfg(feature = "souper-harvest")]
-use alloc::string::String;
-use alloc::vec::Vec;
-
-#[cfg(feature = "souper-harvest")]
-use crate::souper_harvest::do_souper_harvest;
-
-/// Persistent data structures and compilation pipeline.
-pub struct Context {
-    /// The function we're compiling.
-    pub func: Function,
-
-    /// The control flow graph of `func`.
-    pub cfg: ControlFlowGraph,
-
-    /// Dominator tree for `func`.
-    pub domtree: DominatorTree,
-
-    /// Loop analysis of `func`.
-    pub loop_analysis: LoopAnalysis,
-
-    /// Result of MachBackend compilation, if computed.
-    pub mach_compile_result: Option<MachCompileResult>,
-
-    /// Flag: do we want a disassembly with the MachCompileResult?
-    pub want_disasm: bool,
-}
-
-impl Context {
-    /// Allocate a new compilation context.
-    ///
-    /// The returned instance should be reused for compiling multiple functions in order to avoid
-    /// needless allocator thrashing.
-    pub fn new() -> Self {
-        Self::for_function(Function::new())
-    }
-
-    /// Allocate a new compilation context with an existing Function.
-    ///
-    /// The returned instance should be reused for compiling multiple functions in order to avoid
-    /// needless allocator thrashing.
-    pub fn for_function(func: Function) -> Self {
-        Self {
-            func,
-            cfg: ControlFlowGraph::new(),
-            domtree: DominatorTree::new(),
-            loop_analysis: LoopAnalysis::new(),
-            mach_compile_result: None,
-            want_disasm: false,
-        }
-    }
-
-    /// Clear all data structures in this context.
-    pub fn clear(&mut self) {
-        self.func.clear();
-        self.cfg.clear();
-        self.domtree.clear();
-        self.loop_analysis.clear();
-        self.mach_compile_result = None;
-        self.want_disasm = false;
-    }
-
-    /// Set the flag to request a disassembly when compiling with a
-    /// `MachBackend` backend.
-    pub fn set_disasm(&mut self, val: bool) {
-        self.want_disasm = val;
-    }
-
-    /// Compile the function, and emit machine code into a `Vec<u8>`.
-    ///
-    /// Run the function through all the passes necessary to generate code for the target ISA
-    /// represented by `isa`, as well as the final step of emitting machine code into a
-    /// `Vec<u8>`. The machine code is not relocated. Instead, any relocations are emitted
-    /// into `relocs`.
-    ///
-    /// This function calls `compile` and `emit_to_memory`, taking care to resize `mem` as
-    /// needed, so it provides a safe interface.
-    ///
-    /// Returns information about the function's code and read-only data.
-    pub fn compile_and_emit(
-        &mut self,
-        isa: &dyn TargetIsa,
-        mem: &mut Vec<u8>,
-    ) -> CodegenResult<()> {
-        let info = self.compile(isa)?;
-        let old_len = mem.len();
-        mem.resize(old_len + info.total_size as usize, 0);
-        let new_info = unsafe { self.emit_to_memory(mem.as_mut_ptr().add(old_len)) };
-        debug_assert!(new_info == info);
-        Ok(())
-    }
-
-    /// Compile the function.
-    ///
-    /// Run the function through all the passes necessary to generate code for the target ISA
-    /// represented by `isa`. This does not include the final step of emitting machine code into a
-    /// code sink.
-    ///
-    /// Returns information about the function's code and read-only data.
-    pub fn compile(&mut self, isa: &dyn TargetIsa) -> CodegenResult<CodeInfo> {
-        let _tt = timing::compile();
-        self.verify_if(isa)?;
-
-        let opt_level = isa.flags().opt_level();
-        log::debug!(
-            "Compiling (opt level {:?}):\n{}",
-            opt_level,
-            self.func.display()
-        );
-
-        self.compute_cfg();
-        if opt_level != OptLevel::None {
-            self.preopt(isa)?;
-        }
-        if isa.flags().enable_nan_canonicalization() {
-            self.canonicalize_nans(isa)?;
-        }
-
-        self.legalize(isa)?;
-        if opt_level != OptLevel::None {
-            self.compute_domtree();
-            self.compute_loop_analysis();
-            self.licm(isa)?;
-            self.simple_gvn(isa)?;
-        }
-
-        self.compute_domtree();
-        self.eliminate_unreachable_code(isa)?;
-        if opt_level != OptLevel::None {
-            self.dce(isa)?;
-        }
-
-        self.remove_constant_phis(isa)?;
-
-        let result = isa.compile_function(&self.func, self.want_disasm)?;
-        let info = result.code_info();
-        self.mach_compile_result = Some(result);
-        Ok(info)
-    }
-
-    /// Emit machine code directly into raw memory.
-    ///
-    /// Write all of the function's machine code to the memory at `mem`. The size of the machine
-    /// code is returned by `compile` above.
-    ///
-    /// The machine code is not relocated. Instead, any relocations are emitted into `relocs`.
-    ///
-    /// # Safety
-    ///
-    /// This function is unsafe since it does not perform bounds checking on the memory buffer,
-    /// and it can't guarantee that the `mem` pointer is valid.
-    ///
-    /// Returns information about the emitted code and data.
-    #[deny(unsafe_op_in_unsafe_fn)]
-    pub unsafe fn emit_to_memory(&self, mem: *mut u8) -> CodeInfo {
-        let _tt = timing::binemit();
-        let result = self
-            .mach_compile_result
-            .as_ref()
-            .expect("only using mach backend now");
-        let info = result.code_info();
-
-        let mem = unsafe { std::slice::from_raw_parts_mut(mem, info.total_size as usize) };
-        mem.copy_from_slice(result.buffer.data());
-
-        info
-    }
-
-    /// If available, return information about the code layout in the
-    /// final machine code: the offsets (in bytes) of each basic-block
-    /// start, and all basic-block edges.
-    pub fn get_code_bb_layout(&self) -> Option<(Vec<usize>, Vec<(usize, usize)>)> {
-        if let Some(result) = self.mach_compile_result.as_ref() {
-            Some((
-                result.bb_starts.iter().map(|&off| off as usize).collect(),
-                result
-                    .bb_edges
-                    .iter()
-                    .map(|&(from, to)| (from as usize, to as usize))
-                    .collect(),
-            ))
-        } else {
-            None
-        }
-    }
-
-    /// Creates unwind information for the function.
-    ///
-    /// Returns `None` if the function has no unwind information.
-    #[cfg(feature = "unwind")]
-    pub fn create_unwind_info(
-        &self,
-        isa: &dyn TargetIsa,
-    ) -> CodegenResult<Option<crate::isa::unwind::UnwindInfo>> {
-        let unwind_info_kind = isa.unwind_info_kind();
-        let result = self.mach_compile_result.as_ref().unwrap();
-        isa.emit_unwind_info(result, unwind_info_kind)
-    }
-
-    /// Run the verifier on the function.
-    ///
-    /// Also check that the dominator tree and control flow graph are consistent with the function.
-    pub fn verify<'a, FOI: Into<FlagsOrIsa<'a>>>(&self, fisa: FOI) -> VerifierResult<()> {
-        let mut errors = VerifierErrors::default();
-        let _ = verify_context(&self.func, &self.cfg, &self.domtree, fisa, &mut errors);
-
-        if errors.is_empty() {
-            Ok(())
-        } else {
-            Err(errors)
-        }
-    }
-
-    /// Run the verifier only if the `enable_verifier` setting is true.
-    pub fn verify_if<'a, FOI: Into<FlagsOrIsa<'a>>>(&self, fisa: FOI) -> CodegenResult<()> {
-        let fisa = fisa.into();
-        if fisa.flags.enable_verifier() {
-            self.verify(fisa)?;
-        }
-        Ok(())
-    }
-
-    /// Perform dead-code elimination on the function.
-    pub fn dce<'a, FOI: Into<FlagsOrIsa<'a>>>(&mut self, fisa: FOI) -> CodegenResult<()> {
-        do_dce(&mut self.func, &mut self.domtree);
-        self.verify_if(fisa)?;
-        Ok(())
-    }
-
-    /// Perform constant-phi removal on the function.
-    pub fn remove_constant_phis<'a, FOI: Into<FlagsOrIsa<'a>>>(
-        &mut self,
-        fisa: FOI,
-    ) -> CodegenResult<()> {
-        do_remove_constant_phis(&mut self.func, &mut self.domtree);
-        self.verify_if(fisa)?;
-        Ok(())
-    }
-
-    /// Perform pre-legalization rewrites on the function.
-    pub fn preopt(&mut self, isa: &dyn TargetIsa) -> CodegenResult<()> {
-        do_preopt(&mut self.func, &mut self.cfg, isa);
-        self.verify_if(isa)?;
-        Ok(())
-    }
-
-    /// Perform NaN canonicalizing rewrites on the function.
-    pub fn canonicalize_nans(&mut self, isa: &dyn TargetIsa) -> CodegenResult<()> {
-        do_nan_canonicalization(&mut self.func);
-        self.verify_if(isa)
-    }
-
-    /// Run the legalizer for `isa` on the function.
-    pub fn legalize(&mut self, isa: &dyn TargetIsa) -> CodegenResult<()> {
-        // Legalization invalidates the domtree and loop_analysis by mutating the CFG.
-        // TODO: Avoid doing this when legalization doesn't actually mutate the CFG.
-        self.domtree.clear();
-        self.loop_analysis.clear();
-
-        // Run some specific legalizations only.
-        simple_legalize(&mut self.func, &mut self.cfg, isa);
-        self.verify_if(isa)
-    }
-
-    /// Compute the control flow graph.
-    pub fn compute_cfg(&mut self) {
-        self.cfg.compute(&self.func)
-    }
-
-    /// Compute dominator tree.
-    pub fn compute_domtree(&mut self) {
-        self.domtree.compute(&self.func, &self.cfg)
-    }
-
-    /// Compute the loop analysis.
-    pub fn compute_loop_analysis(&mut self) {
-        self.loop_analysis
-            .compute(&self.func, &self.cfg, &self.domtree)
-    }
-
-    /// Compute the control flow graph and dominator tree.
-    pub fn flowgraph(&mut self) {
-        self.compute_cfg();
-        self.compute_domtree()
-    }
-
-    /// Perform simple GVN on the function.
-    pub fn simple_gvn<'a, FOI: Into<FlagsOrIsa<'a>>>(&mut self, fisa: FOI) -> CodegenResult<()> {
-        do_simple_gvn(&mut self.func, &mut self.domtree);
-        self.verify_if(fisa)
-    }
-
-    /// Perform LICM on the function.
-    pub fn licm(&mut self, isa: &dyn TargetIsa) -> CodegenResult<()> {
-        do_licm(
-            &mut self.func,
-            &mut self.cfg,
-            &mut self.domtree,
-            &mut self.loop_analysis,
-        );
-        self.verify_if(isa)
-    }
-
-    /// Perform unreachable code elimination.
-    pub fn eliminate_unreachable_code<'a, FOI>(&mut self, fisa: FOI) -> CodegenResult<()>
-    where
-        FOI: Into<FlagsOrIsa<'a>>,
-    {
-        eliminate_unreachable_code(&mut self.func, &mut self.cfg, &self.domtree);
-        self.verify_if(fisa)
-    }
-
-    /// Harvest candidate left-hand sides for superoptimization with Souper.
-    #[cfg(feature = "souper-harvest")]
-    pub fn souper_harvest(
-        &mut self,
-        out: &mut std::sync::mpsc::Sender<String>,
-    ) -> CodegenResult<()> {
-        do_souper_harvest(&self.func, out);
-        Ok(())
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/cursor.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/cursor.rs
deleted file mode 100644
index 2dc8ce7a2..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/cursor.rs
+++ /dev/null
@@ -1,665 +0,0 @@
-//! Cursor library.
-//!
-//! This module defines cursor data types that can be used for inserting instructions.
-
-use crate::ir;
-
-/// The possible positions of a cursor.
-#[derive(Clone, Copy, PartialEq, Eq, Debug)]
-pub enum CursorPosition {
-    /// Cursor is not pointing anywhere. No instructions can be inserted.
-    Nowhere,
-    /// Cursor is pointing at an existing instruction.
-    /// New instructions will be inserted *before* the current instruction.
-    At(ir::Inst),
-    /// Cursor is before the beginning of a block. No instructions can be inserted. Calling
-    /// `next_inst()` will move to the first instruction in the block.
-    Before(ir::Block),
-    /// Cursor is pointing after the end of a block.
-    /// New instructions will be appended to the block.
-    After(ir::Block),
-}
-
-/// All cursor types implement the `Cursor` which provides common navigation operations.
-pub trait Cursor {
-    /// Get the current cursor position.
-    fn position(&self) -> CursorPosition;
-
-    /// Set the current position.
-    fn set_position(&mut self, pos: CursorPosition);
-
-    /// Get the source location that should be assigned to new instructions.
-    fn srcloc(&self) -> ir::SourceLoc;
-
-    /// Set the source location that should be assigned to new instructions.
-    fn set_srcloc(&mut self, srcloc: ir::SourceLoc);
-
-    /// Borrow a reference to the function layout that this cursor is navigating.
-    fn layout(&self) -> &ir::Layout;
-
-    /// Borrow a mutable reference to the function layout that this cursor is navigating.
-    fn layout_mut(&mut self) -> &mut ir::Layout;
-
-    /// Exchange this cursor for one with a set source location.
-    ///
-    /// This is intended to be used as a builder method:
-    ///
-    /// ```
-    /// # use cranelift_codegen::ir::{Function, Block, SourceLoc};
-    /// # use cranelift_codegen::cursor::{Cursor, FuncCursor};
-    /// fn edit_func(func: &mut Function, srcloc: SourceLoc) {
-    ///     let mut pos = FuncCursor::new(func).with_srcloc(srcloc);
-    ///
-    ///     // Use `pos`...
-    /// }
-    /// ```
-    fn with_srcloc(mut self, srcloc: ir::SourceLoc) -> Self
-    where
-        Self: Sized,
-    {
-        self.set_srcloc(srcloc);
-        self
-    }
-
-    /// Rebuild this cursor positioned at `pos`.
-    fn at_position(mut self, pos: CursorPosition) -> Self
-    where
-        Self: Sized,
-    {
-        self.set_position(pos);
-        self
-    }
-
-    /// Rebuild this cursor positioned at `inst`.
-    ///
-    /// This is intended to be used as a builder method:
-    ///
-    /// ```
-    /// # use cranelift_codegen::ir::{Function, Block, Inst};
-    /// # use cranelift_codegen::cursor::{Cursor, FuncCursor};
-    /// fn edit_func(func: &mut Function, inst: Inst) {
-    ///     let mut pos = FuncCursor::new(func).at_inst(inst);
-    ///
-    ///     // Use `pos`...
-    /// }
-    /// ```
-    fn at_inst(mut self, inst: ir::Inst) -> Self
-    where
-        Self: Sized,
-    {
-        self.goto_inst(inst);
-        self
-    }
-
-    /// Rebuild this cursor positioned at the first insertion point for `block`.
-    /// This differs from `at_first_inst` in that it doesn't assume that any
-    /// instructions have been inserted into `block` yet.
-    ///
-    /// This is intended to be used as a builder method:
-    ///
-    /// ```
-    /// # use cranelift_codegen::ir::{Function, Block, Inst};
-    /// # use cranelift_codegen::cursor::{Cursor, FuncCursor};
-    /// fn edit_func(func: &mut Function, block: Block) {
-    ///     let mut pos = FuncCursor::new(func).at_first_insertion_point(block);
-    ///
-    ///     // Use `pos`...
-    /// }
-    /// ```
-    fn at_first_insertion_point(mut self, block: ir::Block) -> Self
-    where
-        Self: Sized,
-    {
-        self.goto_first_insertion_point(block);
-        self
-    }
-
-    /// Rebuild this cursor positioned at the first instruction in `block`.
-    ///
-    /// This is intended to be used as a builder method:
-    ///
-    /// ```
-    /// # use cranelift_codegen::ir::{Function, Block, Inst};
-    /// # use cranelift_codegen::cursor::{Cursor, FuncCursor};
-    /// fn edit_func(func: &mut Function, block: Block) {
-    ///     let mut pos = FuncCursor::new(func).at_first_inst(block);
-    ///
-    ///     // Use `pos`...
-    /// }
-    /// ```
-    fn at_first_inst(mut self, block: ir::Block) -> Self
-    where
-        Self: Sized,
-    {
-        self.goto_first_inst(block);
-        self
-    }
-
-    /// Rebuild this cursor positioned at the last instruction in `block`.
-    ///
-    /// This is intended to be used as a builder method:
-    ///
-    /// ```
-    /// # use cranelift_codegen::ir::{Function, Block, Inst};
-    /// # use cranelift_codegen::cursor::{Cursor, FuncCursor};
-    /// fn edit_func(func: &mut Function, block: Block) {
-    ///     let mut pos = FuncCursor::new(func).at_last_inst(block);
-    ///
-    ///     // Use `pos`...
-    /// }
-    /// ```
-    fn at_last_inst(mut self, block: ir::Block) -> Self
-    where
-        Self: Sized,
-    {
-        self.goto_last_inst(block);
-        self
-    }
-
-    /// Rebuild this cursor positioned after `inst`.
-    ///
-    /// This is intended to be used as a builder method:
-    ///
-    /// ```
-    /// # use cranelift_codegen::ir::{Function, Block, Inst};
-    /// # use cranelift_codegen::cursor::{Cursor, FuncCursor};
-    /// fn edit_func(func: &mut Function, inst: Inst) {
-    ///     let mut pos = FuncCursor::new(func).after_inst(inst);
-    ///
-    ///     // Use `pos`...
-    /// }
-    /// ```
-    fn after_inst(mut self, inst: ir::Inst) -> Self
-    where
-        Self: Sized,
-    {
-        self.goto_after_inst(inst);
-        self
-    }
-
-    /// Rebuild this cursor positioned at the top of `block`.
-    ///
-    /// This is intended to be used as a builder method:
-    ///
-    /// ```
-    /// # use cranelift_codegen::ir::{Function, Block, Inst};
-    /// # use cranelift_codegen::cursor::{Cursor, FuncCursor};
-    /// fn edit_func(func: &mut Function, block: Block) {
-    ///     let mut pos = FuncCursor::new(func).at_top(block);
-    ///
-    ///     // Use `pos`...
-    /// }
-    /// ```
-    fn at_top(mut self, block: ir::Block) -> Self
-    where
-        Self: Sized,
-    {
-        self.goto_top(block);
-        self
-    }
-
-    /// Rebuild this cursor positioned at the bottom of `block`.
-    ///
-    /// This is intended to be used as a builder method:
-    ///
-    /// ```
-    /// # use cranelift_codegen::ir::{Function, Block, Inst};
-    /// # use cranelift_codegen::cursor::{Cursor, FuncCursor};
-    /// fn edit_func(func: &mut Function, block: Block) {
-    ///     let mut pos = FuncCursor::new(func).at_bottom(block);
-    ///
-    ///     // Use `pos`...
-    /// }
-    /// ```
-    fn at_bottom(mut self, block: ir::Block) -> Self
-    where
-        Self: Sized,
-    {
-        self.goto_bottom(block);
-        self
-    }
-
-    /// Get the block corresponding to the current position.
-    fn current_block(&self) -> Option<ir::Block> {
-        use self::CursorPosition::*;
-        match self.position() {
-            Nowhere => None,
-            At(inst) => self.layout().inst_block(inst),
-            Before(block) | After(block) => Some(block),
-        }
-    }
-
-    /// Get the instruction corresponding to the current position, if any.
-    fn current_inst(&self) -> Option<ir::Inst> {
-        use self::CursorPosition::*;
-        match self.position() {
-            At(inst) => Some(inst),
-            _ => None,
-        }
-    }
-
-    /// Go to the position after a specific instruction, which must be inserted
-    /// in the layout. New instructions will be inserted after `inst`.
-    fn goto_after_inst(&mut self, inst: ir::Inst) {
-        debug_assert!(self.layout().inst_block(inst).is_some());
-        let new_pos = if let Some(next) = self.layout().next_inst(inst) {
-            CursorPosition::At(next)
-        } else {
-            CursorPosition::After(
-                self.layout()
-                    .inst_block(inst)
-                    .expect("current instruction removed?"),
-            )
-        };
-        self.set_position(new_pos);
-    }
-
-    /// Go to a specific instruction which must be inserted in the layout.
-    /// New instructions will be inserted before `inst`.
-    fn goto_inst(&mut self, inst: ir::Inst) {
-        debug_assert!(self.layout().inst_block(inst).is_some());
-        self.set_position(CursorPosition::At(inst));
-    }
-
-    /// Go to the position for inserting instructions at the beginning of `block`,
-    /// which unlike `goto_first_inst` doesn't assume that any instructions have
-    /// been inserted into `block` yet.
-    fn goto_first_insertion_point(&mut self, block: ir::Block) {
-        if let Some(inst) = self.layout().first_inst(block) {
-            self.goto_inst(inst);
-        } else {
-            self.goto_bottom(block);
-        }
-    }
-
-    /// Go to the first instruction in `block`.
-    fn goto_first_inst(&mut self, block: ir::Block) {
-        let inst = self.layout().first_inst(block).expect("Empty block");
-        self.goto_inst(inst);
-    }
-
-    /// Go to the last instruction in `block`.
-    fn goto_last_inst(&mut self, block: ir::Block) {
-        let inst = self.layout().last_inst(block).expect("Empty block");
-        self.goto_inst(inst);
-    }
-
-    /// Go to the top of `block` which must be inserted into the layout.
-    /// At this position, instructions cannot be inserted, but `next_inst()` will move to the first
-    /// instruction in `block`.
-    fn goto_top(&mut self, block: ir::Block) {
-        debug_assert!(self.layout().is_block_inserted(block));
-        self.set_position(CursorPosition::Before(block));
-    }
-
-    /// Go to the bottom of `block` which must be inserted into the layout.
-    /// At this position, inserted instructions will be appended to `block`.
-    fn goto_bottom(&mut self, block: ir::Block) {
-        debug_assert!(self.layout().is_block_inserted(block));
-        self.set_position(CursorPosition::After(block));
-    }
-
-    /// Go to the top of the next block in layout order and return it.
-    ///
-    /// - If the cursor wasn't pointing at anything, go to the top of the first block in the
-    ///   function.
-    /// - If there are no more blocks, leave the cursor pointing at nothing and return `None`.
-    ///
-    /// # Examples
-    ///
-    /// The `next_block()` method is intended for iterating over the blocks in layout order:
-    ///
-    /// ```
-    /// # use cranelift_codegen::ir::{Function, Block};
-    /// # use cranelift_codegen::cursor::{Cursor, FuncCursor};
-    /// fn edit_func(func: &mut Function) {
-    ///     let mut cursor = FuncCursor::new(func);
-    ///     while let Some(block) = cursor.next_block() {
-    ///         // Edit block.
-    ///     }
-    /// }
-    /// ```
-    fn next_block(&mut self) -> Option<ir::Block> {
-        let next = if let Some(block) = self.current_block() {
-            self.layout().next_block(block)
-        } else {
-            self.layout().entry_block()
-        };
-        self.set_position(match next {
-            Some(block) => CursorPosition::Before(block),
-            None => CursorPosition::Nowhere,
-        });
-        next
-    }
-
-    /// Go to the bottom of the previous block in layout order and return it.
-    ///
-    /// - If the cursor wasn't pointing at anything, go to the bottom of the last block in the
-    ///   function.
-    /// - If there are no more blocks, leave the cursor pointing at nothing and return `None`.
-    ///
-    /// # Examples
-    ///
-    /// The `prev_block()` method is intended for iterating over the blocks in backwards layout order:
-    ///
-    /// ```
-    /// # use cranelift_codegen::ir::{Function, Block};
-    /// # use cranelift_codegen::cursor::{Cursor, FuncCursor};
-    /// fn edit_func(func: &mut Function) {
-    ///     let mut cursor = FuncCursor::new(func);
-    ///     while let Some(block) = cursor.prev_block() {
-    ///         // Edit block.
-    ///     }
-    /// }
-    /// ```
-    fn prev_block(&mut self) -> Option<ir::Block> {
-        let prev = if let Some(block) = self.current_block() {
-            self.layout().prev_block(block)
-        } else {
-            self.layout().last_block()
-        };
-        self.set_position(match prev {
-            Some(block) => CursorPosition::After(block),
-            None => CursorPosition::Nowhere,
-        });
-        prev
-    }
-
-    /// Move to the next instruction in the same block and return it.
-    ///
-    /// - If the cursor was positioned before a block, go to the first instruction in that block.
-    /// - If there are no more instructions in the block, go to the `After(block)` position and return
-    ///   `None`.
-    /// - If the cursor wasn't pointing anywhere, keep doing that.
-    ///
-    /// This method will never move the cursor to a different block.
-    ///
-    /// # Examples
-    ///
-    /// The `next_inst()` method is intended for iterating over the instructions in a block like
-    /// this:
-    ///
-    /// ```
-    /// # use cranelift_codegen::ir::{Function, Block};
-    /// # use cranelift_codegen::cursor::{Cursor, FuncCursor};
-    /// fn edit_block(func: &mut Function, block: Block) {
-    ///     let mut cursor = FuncCursor::new(func).at_top(block);
-    ///     while let Some(inst) = cursor.next_inst() {
-    ///         // Edit instructions...
-    ///     }
-    /// }
-    /// ```
-    /// The loop body can insert and remove instructions via the cursor.
-    ///
-    /// Iterating over all the instructions in a function looks like this:
-    ///
-    /// ```
-    /// # use cranelift_codegen::ir::{Function, Block};
-    /// # use cranelift_codegen::cursor::{Cursor, FuncCursor};
-    /// fn edit_func(func: &mut Function) {
-    ///     let mut cursor = FuncCursor::new(func);
-    ///     while let Some(block) = cursor.next_block() {
-    ///         while let Some(inst) = cursor.next_inst() {
-    ///             // Edit instructions...
-    ///         }
-    ///     }
-    /// }
-    /// ```
-    fn next_inst(&mut self) -> Option<ir::Inst> {
-        use self::CursorPosition::*;
-        match self.position() {
-            Nowhere | After(..) => None,
-            At(inst) => {
-                if let Some(next) = self.layout().next_inst(inst) {
-                    self.set_position(At(next));
-                    Some(next)
-                } else {
-                    let pos = After(
-                        self.layout()
-                            .inst_block(inst)
-                            .expect("current instruction removed?"),
-                    );
-                    self.set_position(pos);
-                    None
-                }
-            }
-            Before(block) => {
-                if let Some(next) = self.layout().first_inst(block) {
-                    self.set_position(At(next));
-                    Some(next)
-                } else {
-                    self.set_position(After(block));
-                    None
-                }
-            }
-        }
-    }
-
-    /// Move to the previous instruction in the same block and return it.
-    ///
-    /// - If the cursor was positioned after a block, go to the last instruction in that block.
-    /// - If there are no more instructions in the block, go to the `Before(block)` position and return
-    ///   `None`.
-    /// - If the cursor wasn't pointing anywhere, keep doing that.
-    ///
-    /// This method will never move the cursor to a different block.
-    ///
-    /// # Examples
-    ///
-    /// The `prev_inst()` method is intended for iterating backwards over the instructions in an
-    /// block like this:
-    ///
-    /// ```
-    /// # use cranelift_codegen::ir::{Function, Block};
-    /// # use cranelift_codegen::cursor::{Cursor, FuncCursor};
-    /// fn edit_block(func: &mut Function, block: Block) {
-    ///     let mut cursor = FuncCursor::new(func).at_bottom(block);
-    ///     while let Some(inst) = cursor.prev_inst() {
-    ///         // Edit instructions...
-    ///     }
-    /// }
-    /// ```
-    fn prev_inst(&mut self) -> Option<ir::Inst> {
-        use self::CursorPosition::*;
-        match self.position() {
-            Nowhere | Before(..) => None,
-            At(inst) => {
-                if let Some(prev) = self.layout().prev_inst(inst) {
-                    self.set_position(At(prev));
-                    Some(prev)
-                } else {
-                    let pos = Before(
-                        self.layout()
-                            .inst_block(inst)
-                            .expect("current instruction removed?"),
-                    );
-                    self.set_position(pos);
-                    None
-                }
-            }
-            After(block) => {
-                if let Some(prev) = self.layout().last_inst(block) {
-                    self.set_position(At(prev));
-                    Some(prev)
-                } else {
-                    self.set_position(Before(block));
-                    None
-                }
-            }
-        }
-    }
-
-    /// Insert an instruction at the current position.
-    ///
-    /// - If pointing at an instruction, the new instruction is inserted before the current
-    ///   instruction.
-    /// - If pointing at the bottom of a block, the new instruction is appended to the block.
-    /// - Otherwise panic.
-    ///
-    /// In either case, the cursor is not moved, such that repeated calls to `insert_inst()` causes
-    /// instructions to appear in insertion order in the block.
-    fn insert_inst(&mut self, inst: ir::Inst) {
-        use self::CursorPosition::*;
-        match self.position() {
-            Nowhere | Before(..) => panic!("Invalid insert_inst position"),
-            At(cur) => self.layout_mut().insert_inst(inst, cur),
-            After(block) => self.layout_mut().append_inst(inst, block),
-        }
-    }
-
-    /// Remove the instruction under the cursor.
-    ///
-    /// The cursor is left pointing at the position following the current instruction.
-    ///
-    /// Return the instruction that was removed.
-    fn remove_inst(&mut self) -> ir::Inst {
-        let inst = self.current_inst().expect("No instruction to remove");
-        self.next_inst();
-        self.layout_mut().remove_inst(inst);
-        inst
-    }
-
-    /// Remove the instruction under the cursor.
-    ///
-    /// The cursor is left pointing at the position preceding the current instruction.
-    ///
-    /// Return the instruction that was removed.
-    fn remove_inst_and_step_back(&mut self) -> ir::Inst {
-        let inst = self.current_inst().expect("No instruction to remove");
-        self.prev_inst();
-        self.layout_mut().remove_inst(inst);
-        inst
-    }
-
-    /// Insert a block at the current position and switch to it.
-    ///
-    /// As far as possible, this method behaves as if the block header were an instruction inserted
-    /// at the current position.
-    ///
-    /// - If the cursor is pointing at an existing instruction, *the current block is split in two*
-    ///   and the current instruction becomes the first instruction in the inserted block.
-    /// - If the cursor points at the bottom of a block, the new block is inserted after the current
-    ///   one, and moved to the bottom of the new block where instructions can be appended.
-    /// - If the cursor points to the top of a block, the new block is inserted above the current one.
-    /// - If the cursor is not pointing at anything, the new block is placed last in the layout.
-    ///
-    /// This means that it is always valid to call this method, and it always leaves the cursor in
-    /// a state that will insert instructions into the new block.
-    fn insert_block(&mut self, new_block: ir::Block) {
-        use self::CursorPosition::*;
-        match self.position() {
-            At(inst) => {
-                self.layout_mut().split_block(new_block, inst);
-                // All other cases move to `After(block)`, but in this case we'll stay `At(inst)`.
-                return;
-            }
-            Nowhere => self.layout_mut().append_block(new_block),
-            Before(block) => self.layout_mut().insert_block(new_block, block),
-            After(block) => self.layout_mut().insert_block_after(new_block, block),
-        }
-        // For everything but `At(inst)` we end up appending to the new block.
-        self.set_position(After(new_block));
-    }
-}
-
-/// Function cursor.
-///
-/// A `FuncCursor` holds a mutable reference to a whole `ir::Function` while keeping a position
-/// too. The function can be re-borrowed by accessing the public `cur.func` member.
-///
-/// This cursor is for use before legalization. The inserted instructions are not given an
-/// encoding.
-pub struct FuncCursor<'f> {
-    pos: CursorPosition,
-    srcloc: ir::SourceLoc,
-
-    /// The referenced function.
-    pub func: &'f mut ir::Function,
-}
-
-impl<'f> FuncCursor<'f> {
-    /// Create a new `FuncCursor` pointing nowhere.
-    pub fn new(func: &'f mut ir::Function) -> Self {
-        Self {
-            pos: CursorPosition::Nowhere,
-            srcloc: Default::default(),
-            func,
-        }
-    }
-
-    /// Use the source location of `inst` for future instructions.
-    pub fn use_srcloc(&mut self, inst: ir::Inst) {
-        self.srcloc = self.func.srclocs[inst];
-    }
-
-    /// Create an instruction builder that inserts an instruction at the current position.
-    pub fn ins(&mut self) -> ir::InsertBuilder<&mut FuncCursor<'f>> {
-        ir::InsertBuilder::new(self)
-    }
-}
-
-impl<'f> Cursor for FuncCursor<'f> {
-    fn position(&self) -> CursorPosition {
-        self.pos
-    }
-
-    fn set_position(&mut self, pos: CursorPosition) {
-        self.pos = pos
-    }
-
-    fn srcloc(&self) -> ir::SourceLoc {
-        self.srcloc
-    }
-
-    fn set_srcloc(&mut self, srcloc: ir::SourceLoc) {
-        self.srcloc = srcloc;
-    }
-
-    fn layout(&self) -> &ir::Layout {
-        &self.func.layout
-    }
-
-    fn layout_mut(&mut self) -> &mut ir::Layout {
-        &mut self.func.layout
-    }
-}
-
-impl<'c, 'f> ir::InstInserterBase<'c> for &'c mut FuncCursor<'f> {
-    fn data_flow_graph(&self) -> &ir::DataFlowGraph {
-        &self.func.dfg
-    }
-
-    fn data_flow_graph_mut(&mut self) -> &mut ir::DataFlowGraph {
-        &mut self.func.dfg
-    }
-
-    fn insert_built_inst(self, inst: ir::Inst) -> &'c mut ir::DataFlowGraph {
-        // TODO: Remove this assertion once #796 is fixed.
-        #[cfg(debug_assertions)]
-        {
-            if let CursorPosition::At(_) = self.position() {
-                if let Some(curr) = self.current_inst() {
-                    if let Some(prev) = self.layout().prev_inst(curr) {
-                        let prev_op = self.data_flow_graph()[prev].opcode();
-                        let inst_op = self.data_flow_graph()[inst].opcode();
-                        let curr_op = self.data_flow_graph()[curr].opcode();
-                        if prev_op.is_branch()
-                            && !prev_op.is_terminator()
-                            && !inst_op.is_terminator()
-                        {
-                            panic!(
-                                "Inserting instruction {} after {}, and before {}",
-                                inst_op, prev_op, curr_op
-                            )
-                        }
-                    };
-                };
-            };
-        }
-        self.insert_inst(inst);
-        if !self.srcloc.is_default() {
-            self.func.srclocs[inst] = self.srcloc;
-        }
-        &mut self.func.dfg
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/data_value.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/data_value.rs
deleted file mode 100644
index 13aa23767..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/data_value.rs
+++ /dev/null
@@ -1,309 +0,0 @@
-//! This module gives users to instantiate values that Cranelift understands. These values are used,
-//! for example, during interpretation and for wrapping immediates.
-use crate::ir::immediates::{Ieee32, Ieee64, Offset32};
-use crate::ir::{types, ConstantData, Type};
-use core::convert::TryInto;
-use core::fmt::{self, Display, Formatter};
-
-/// Represent a data value. Where [Value] is an SSA reference, [DataValue] is the type + value
-/// that would be referred to by a [Value].
-///
-/// [Value]: crate::ir::Value
-#[allow(missing_docs)]
-#[derive(Clone, Debug, PartialEq, PartialOrd)]
-pub enum DataValue {
-    B(bool),
-    I8(i8),
-    I16(i16),
-    I32(i32),
-    I64(i64),
-    I128(i128),
-    U8(u8),
-    U16(u16),
-    U32(u32),
-    U64(u64),
-    U128(u128),
-    F32(Ieee32),
-    F64(Ieee64),
-    V128([u8; 16]),
-}
-
-impl DataValue {
-    /// Try to cast an immediate integer (a wrapped `i64` on most Cranelift instructions) to the
-    /// given Cranelift [Type].
-    pub fn from_integer(imm: i128, ty: Type) -> Result<DataValue, DataValueCastFailure> {
-        match ty {
-            types::I8 => Ok(DataValue::I8(imm as i8)),
-            types::I16 => Ok(DataValue::I16(imm as i16)),
-            types::I32 => Ok(DataValue::I32(imm as i32)),
-            types::I64 => Ok(DataValue::I64(imm as i64)),
-            types::I128 => Ok(DataValue::I128(imm)),
-            _ => Err(DataValueCastFailure::FromInteger(imm, ty)),
-        }
-    }
-
-    /// Return the Cranelift IR [Type] for this [DataValue].
-    pub fn ty(&self) -> Type {
-        match self {
-            DataValue::B(_) => types::B8, // A default type.
-            DataValue::I8(_) | DataValue::U8(_) => types::I8,
-            DataValue::I16(_) | DataValue::U16(_) => types::I16,
-            DataValue::I32(_) | DataValue::U32(_) => types::I32,
-            DataValue::I64(_) | DataValue::U64(_) => types::I64,
-            DataValue::I128(_) | DataValue::U128(_) => types::I128,
-            DataValue::F32(_) => types::F32,
-            DataValue::F64(_) => types::F64,
-            DataValue::V128(_) => types::I8X16, // A default type.
-        }
-    }
-
-    /// Return true if the value is a vector (i.e. `DataValue::V128`).
-    pub fn is_vector(&self) -> bool {
-        match self {
-            DataValue::V128(_) => true,
-            _ => false,
-        }
-    }
-
-    /// Return true if the value is a bool (i.e. `DataValue::B`).
-    pub fn is_bool(&self) -> bool {
-        match self {
-            DataValue::B(_) => true,
-            _ => false,
-        }
-    }
-
-    /// Write a [DataValue] to a slice.
-    ///
-    /// # Panics:
-    ///
-    /// Panics if the slice does not have enough space to accommodate the [DataValue]
-    pub fn write_to_slice(&self, dst: &mut [u8]) {
-        match self {
-            DataValue::B(true) => dst[..16].copy_from_slice(&[u8::MAX; 16][..]),
-            DataValue::B(false) => dst[..16].copy_from_slice(&[0; 16][..]),
-            DataValue::I8(i) => dst[..1].copy_from_slice(&i.to_ne_bytes()[..]),
-            DataValue::I16(i) => dst[..2].copy_from_slice(&i.to_ne_bytes()[..]),
-            DataValue::I32(i) => dst[..4].copy_from_slice(&i.to_ne_bytes()[..]),
-            DataValue::I64(i) => dst[..8].copy_from_slice(&i.to_ne_bytes()[..]),
-            DataValue::I128(i) => dst[..16].copy_from_slice(&i.to_ne_bytes()[..]),
-            DataValue::F32(f) => dst[..4].copy_from_slice(&f.bits().to_ne_bytes()[..]),
-            DataValue::F64(f) => dst[..8].copy_from_slice(&f.bits().to_ne_bytes()[..]),
-            DataValue::V128(v) => dst[..16].copy_from_slice(&v[..]),
-            _ => unimplemented!(),
-        };
-    }
-
-    /// Read a [DataValue] from a slice using a given [Type].
-    ///
-    /// # Panics:
-    ///
-    /// Panics if the slice does not have enough space to accommodate the [DataValue]
-    pub fn read_from_slice(src: &[u8], ty: Type) -> Self {
-        match ty {
-            types::I8 => DataValue::I8(i8::from_ne_bytes(src[..1].try_into().unwrap())),
-            types::I16 => DataValue::I16(i16::from_ne_bytes(src[..2].try_into().unwrap())),
-            types::I32 => DataValue::I32(i32::from_ne_bytes(src[..4].try_into().unwrap())),
-            types::I64 => DataValue::I64(i64::from_ne_bytes(src[..8].try_into().unwrap())),
-            types::I128 => DataValue::I128(i128::from_ne_bytes(src[..16].try_into().unwrap())),
-            types::F32 => DataValue::F32(Ieee32::with_bits(u32::from_ne_bytes(
-                src[..4].try_into().unwrap(),
-            ))),
-            types::F64 => DataValue::F64(Ieee64::with_bits(u64::from_ne_bytes(
-                src[..8].try_into().unwrap(),
-            ))),
-            _ if ty.is_bool() => {
-                // Only `ty.bytes()` are guaranteed to be written
-                // so we can only test the first n bytes of `src`
-
-                let size = ty.bytes() as usize;
-                DataValue::B(src[..size].iter().any(|&i| i != 0))
-            }
-            _ if ty.is_vector() && ty.bytes() == 16 => {
-                DataValue::V128(src[..16].try_into().unwrap())
-            }
-            _ => unimplemented!(),
-        }
-    }
-
-    /// Write a [DataValue] to a memory location.
-    pub unsafe fn write_value_to(&self, p: *mut u128) {
-        // Since `DataValue` does not have type info for bools we always
-        // write out a full 16 byte slot.
-        let size = match self.ty() {
-            ty if ty.is_bool() => 16,
-            ty => ty.bytes() as usize,
-        };
-
-        self.write_to_slice(std::slice::from_raw_parts_mut(p as *mut u8, size));
-    }
-
-    /// Read a [DataValue] from a memory location using a given [Type].
-    pub unsafe fn read_value_from(p: *const u128, ty: Type) -> Self {
-        DataValue::read_from_slice(
-            std::slice::from_raw_parts(p as *const u8, ty.bytes() as usize),
-            ty,
-        )
-    }
-}
-
-/// Record failures to cast [DataValue].
-#[derive(Debug, PartialEq)]
-#[allow(missing_docs)]
-pub enum DataValueCastFailure {
-    TryInto(Type, Type),
-    FromInteger(i128, Type),
-}
-
-// This is manually implementing Error and Display instead of using thiserror to reduce the amount
-// of dependencies used by Cranelift.
-impl std::error::Error for DataValueCastFailure {}
-
-impl Display for DataValueCastFailure {
-    fn fmt(&self, f: &mut Formatter) -> fmt::Result {
-        match self {
-            DataValueCastFailure::TryInto(from, to) => {
-                write!(
-                    f,
-                    "unable to cast data value of type {} to type {}",
-                    from, to
-                )
-            }
-            DataValueCastFailure::FromInteger(val, to) => {
-                write!(
-                    f,
-                    "unable to cast i64({}) to a data value of type {}",
-                    val, to
-                )
-            }
-        }
-    }
-}
-
-/// Helper for creating conversion implementations for [DataValue].
-macro_rules! build_conversion_impl {
-    ( $rust_ty:ty, $data_value_ty:ident, $cranelift_ty:ident ) => {
-        impl From<$rust_ty> for DataValue {
-            fn from(data: $rust_ty) -> Self {
-                DataValue::$data_value_ty(data)
-            }
-        }
-
-        impl TryInto<$rust_ty> for DataValue {
-            type Error = DataValueCastFailure;
-            fn try_into(self) -> Result<$rust_ty, Self::Error> {
-                if let DataValue::$data_value_ty(v) = self {
-                    Ok(v)
-                } else {
-                    Err(DataValueCastFailure::TryInto(
-                        self.ty(),
-                        types::$cranelift_ty,
-                    ))
-                }
-            }
-        }
-    };
-}
-build_conversion_impl!(bool, B, B8);
-build_conversion_impl!(i8, I8, I8);
-build_conversion_impl!(i16, I16, I16);
-build_conversion_impl!(i32, I32, I32);
-build_conversion_impl!(i64, I64, I64);
-build_conversion_impl!(i128, I128, I128);
-build_conversion_impl!(u8, U8, I8);
-build_conversion_impl!(u16, U16, I16);
-build_conversion_impl!(u32, U32, I32);
-build_conversion_impl!(u64, U64, I64);
-build_conversion_impl!(u128, U128, I128);
-build_conversion_impl!(Ieee32, F32, F32);
-build_conversion_impl!(Ieee64, F64, F64);
-build_conversion_impl!([u8; 16], V128, I8X16);
-impl From<Offset32> for DataValue {
-    fn from(o: Offset32) -> Self {
-        DataValue::from(Into::<i32>::into(o))
-    }
-}
-
-impl Display for DataValue {
-    fn fmt(&self, f: &mut Formatter<'_>) -> fmt::Result {
-        match self {
-            DataValue::B(dv) => write!(f, "{}", dv),
-            DataValue::I8(dv) => write!(f, "{}", dv),
-            DataValue::I16(dv) => write!(f, "{}", dv),
-            DataValue::I32(dv) => write!(f, "{}", dv),
-            DataValue::I64(dv) => write!(f, "{}", dv),
-            DataValue::I128(dv) => write!(f, "{}", dv),
-            DataValue::U8(dv) => write!(f, "{}", dv),
-            DataValue::U16(dv) => write!(f, "{}", dv),
-            DataValue::U32(dv) => write!(f, "{}", dv),
-            DataValue::U64(dv) => write!(f, "{}", dv),
-            DataValue::U128(dv) => write!(f, "{}", dv),
-            // The Ieee* wrappers here print the expected syntax.
-            DataValue::F32(dv) => write!(f, "{}", dv),
-            DataValue::F64(dv) => write!(f, "{}", dv),
-            // Again, for syntax consistency, use ConstantData, which in this case displays as hex.
-            DataValue::V128(dv) => write!(f, "{}", ConstantData::from(&dv[..])),
-        }
-    }
-}
-
-/// Helper structure for printing bracket-enclosed vectors of [DataValue]s.
-/// - for empty vectors, display `[]`
-/// - for single item vectors, display `42`, e.g.
-/// - for multiple item vectors, display `[42, 43, 44]`, e.g.
-pub struct DisplayDataValues<'a>(pub &'a [DataValue]);
-
-impl<'a> Display for DisplayDataValues<'a> {
-    fn fmt(&self, f: &mut Formatter<'_>) -> fmt::Result {
-        if self.0.len() == 1 {
-            write!(f, "{}", self.0[0])
-        } else {
-            write!(f, "[")?;
-            write_data_value_list(f, &self.0)?;
-            write!(f, "]")
-        }
-    }
-}
-
-/// Helper function for displaying `Vec<DataValue>`.
-pub fn write_data_value_list(f: &mut Formatter<'_>, list: &[DataValue]) -> fmt::Result {
-    match list.len() {
-        0 => Ok(()),
-        1 => write!(f, "{}", list[0]),
-        _ => {
-            write!(f, "{}", list[0])?;
-            for dv in list.iter().skip(1) {
-                write!(f, ", {}", dv)?;
-            }
-            Ok(())
-        }
-    }
-}
-
-#[cfg(test)]
-mod test {
-    use super::*;
-
-    #[test]
-    fn type_conversions() {
-        assert_eq!(DataValue::B(true).ty(), types::B8);
-        assert_eq!(
-            TryInto::<bool>::try_into(DataValue::B(false)).unwrap(),
-            false
-        );
-        assert_eq!(
-            TryInto::<i32>::try_into(DataValue::B(false)).unwrap_err(),
-            DataValueCastFailure::TryInto(types::B8, types::I32)
-        );
-
-        assert_eq!(DataValue::V128([0; 16]).ty(), types::I8X16);
-        assert_eq!(
-            TryInto::<[u8; 16]>::try_into(DataValue::V128([0; 16])).unwrap(),
-            [0; 16]
-        );
-        assert_eq!(
-            TryInto::<i32>::try_into(DataValue::V128([0; 16])).unwrap_err(),
-            DataValueCastFailure::TryInto(types::I8X16, types::I32)
-        );
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/dbg.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/dbg.rs
deleted file mode 100644
index 1d814ceed..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/dbg.rs
+++ /dev/null
@@ -1,28 +0,0 @@
-//! Debug tracing helpers.
-use core::fmt;
-
-/// Prefix added to the log file names, just before the thread name or id.
-pub static LOG_FILENAME_PREFIX: &str = "cranelift.dbg.";
-
-/// Helper for printing lists.
-pub struct DisplayList<'a, T>(pub &'a [T])
-where
-    T: 'a + fmt::Display;
-
-impl<'a, T> fmt::Display for DisplayList<'a, T>
-where
-    T: 'a + fmt::Display,
-{
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        match self.0.split_first() {
-            None => write!(f, "[]"),
-            Some((first, rest)) => {
-                write!(f, "[{}", first)?;
-                for x in rest {
-                    write!(f, ", {}", x)?;
-                }
-                write!(f, "]")
-            }
-        }
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/dce.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/dce.rs
deleted file mode 100644
index e3e855806..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/dce.rs
+++ /dev/null
@@ -1,36 +0,0 @@
-//! A Dead-Code Elimination (DCE) pass.
-//!
-//! Dead code here means instructions that have no side effects and have no
-//! result values used by other instructions.
-
-use crate::cursor::{Cursor, FuncCursor};
-use crate::dominator_tree::DominatorTree;
-use crate::entity::EntityRef;
-use crate::inst_predicates::{any_inst_results_used, has_side_effect};
-use crate::ir::Function;
-use crate::timing;
-
-/// Perform DCE on `func`.
-pub fn do_dce(func: &mut Function, domtree: &mut DominatorTree) {
-    let _tt = timing::dce();
-    debug_assert!(domtree.is_valid());
-
-    let mut live = vec![false; func.dfg.num_values()];
-    for &block in domtree.cfg_postorder() {
-        let mut pos = FuncCursor::new(func).at_bottom(block);
-        while let Some(inst) = pos.prev_inst() {
-            {
-                if has_side_effect(pos.func, inst)
-                    || any_inst_results_used(inst, &live, &pos.func.dfg)
-                {
-                    for arg in pos.func.dfg.inst_args(inst) {
-                        let v = pos.func.dfg.resolve_aliases(*arg);
-                        live[v.index()] = true;
-                    }
-                    continue;
-                }
-            }
-            pos.remove_inst();
-        }
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/divconst_magic_numbers.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/divconst_magic_numbers.rs
deleted file mode 100644
index af45444c4..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/divconst_magic_numbers.rs
+++ /dev/null
@@ -1,1083 +0,0 @@
-//! Compute "magic numbers" for division-by-constants transformations.
-//!
-//! Math helpers for division by (non-power-of-2) constants. This is based
-//! on the presentation in "Hacker's Delight" by Henry Warren, 2003. There
-//! are four cases: {unsigned, signed} x {32 bit, 64 bit}. The word size
-//! makes little difference, but the signed-vs-unsigned aspect has a large
-//! effect. Therefore everything is presented in the order U32 U64 S32 S64
-//! so as to emphasise the similarity of the U32 and U64 cases and the S32
-//! and S64 cases.
-
-// Structures to hold the "magic numbers" computed.
-
-#[derive(PartialEq, Debug)]
-pub struct MU32 {
-    pub mul_by: u32,
-    pub do_add: bool,
-    pub shift_by: i32,
-}
-
-#[derive(PartialEq, Debug)]
-pub struct MU64 {
-    pub mul_by: u64,
-    pub do_add: bool,
-    pub shift_by: i32,
-}
-
-#[derive(PartialEq, Debug)]
-pub struct MS32 {
-    pub mul_by: i32,
-    pub shift_by: i32,
-}
-
-#[derive(PartialEq, Debug)]
-pub struct MS64 {
-    pub mul_by: i64,
-    pub shift_by: i32,
-}
-
-// The actual "magic number" generators follow.
-
-pub fn magic_u32(d: u32) -> MU32 {
-    debug_assert_ne!(d, 0);
-    debug_assert_ne!(d, 1); // d==1 generates out of range shifts.
-
-    let mut do_add: bool = false;
-    let mut p: i32 = 31;
-    let nc: u32 = 0xFFFFFFFFu32 - u32::wrapping_neg(d) % d;
-    let mut q1: u32 = 0x80000000u32 / nc;
-    let mut r1: u32 = 0x80000000u32 - q1 * nc;
-    let mut q2: u32 = 0x7FFFFFFFu32 / d;
-    let mut r2: u32 = 0x7FFFFFFFu32 - q2 * d;
-    loop {
-        p = p + 1;
-        if r1 >= nc - r1 {
-            q1 = u32::wrapping_add(u32::wrapping_mul(2, q1), 1);
-            r1 = u32::wrapping_sub(u32::wrapping_mul(2, r1), nc);
-        } else {
-            q1 = u32::wrapping_mul(2, q1);
-            r1 = 2 * r1;
-        }
-        if r2 + 1 >= d - r2 {
-            if q2 >= 0x7FFFFFFFu32 {
-                do_add = true;
-            }
-            q2 = 2 * q2 + 1;
-            r2 = u32::wrapping_sub(u32::wrapping_add(u32::wrapping_mul(2, r2), 1), d);
-        } else {
-            if q2 >= 0x80000000u32 {
-                do_add = true;
-            }
-            q2 = u32::wrapping_mul(2, q2);
-            r2 = 2 * r2 + 1;
-        }
-        let delta: u32 = d - 1 - r2;
-        if !(p < 64 && (q1 < delta || (q1 == delta && r1 == 0))) {
-            break;
-        }
-    }
-
-    MU32 {
-        mul_by: q2 + 1,
-        do_add,
-        shift_by: p - 32,
-    }
-}
-
-pub fn magic_u64(d: u64) -> MU64 {
-    debug_assert_ne!(d, 0);
-    debug_assert_ne!(d, 1); // d==1 generates out of range shifts.
-
-    let mut do_add: bool = false;
-    let mut p: i32 = 63;
-    let nc: u64 = 0xFFFFFFFFFFFFFFFFu64 - u64::wrapping_neg(d) % d;
-    let mut q1: u64 = 0x8000000000000000u64 / nc;
-    let mut r1: u64 = 0x8000000000000000u64 - q1 * nc;
-    let mut q2: u64 = 0x7FFFFFFFFFFFFFFFu64 / d;
-    let mut r2: u64 = 0x7FFFFFFFFFFFFFFFu64 - q2 * d;
-    loop {
-        p = p + 1;
-        if r1 >= nc - r1 {
-            q1 = u64::wrapping_add(u64::wrapping_mul(2, q1), 1);
-            r1 = u64::wrapping_sub(u64::wrapping_mul(2, r1), nc);
-        } else {
-            q1 = u64::wrapping_mul(2, q1);
-            r1 = 2 * r1;
-        }
-        if r2 + 1 >= d - r2 {
-            if q2 >= 0x7FFFFFFFFFFFFFFFu64 {
-                do_add = true;
-            }
-            q2 = 2 * q2 + 1;
-            r2 = u64::wrapping_sub(u64::wrapping_add(u64::wrapping_mul(2, r2), 1), d);
-        } else {
-            if q2 >= 0x8000000000000000u64 {
-                do_add = true;
-            }
-            q2 = u64::wrapping_mul(2, q2);
-            r2 = 2 * r2 + 1;
-        }
-        let delta: u64 = d - 1 - r2;
-        if !(p < 128 && (q1 < delta || (q1 == delta && r1 == 0))) {
-            break;
-        }
-    }
-
-    MU64 {
-        mul_by: q2 + 1,
-        do_add,
-        shift_by: p - 64,
-    }
-}
-
-pub fn magic_s32(d: i32) -> MS32 {
-    debug_assert_ne!(d, -1);
-    debug_assert_ne!(d, 0);
-    debug_assert_ne!(d, 1);
-    let two31: u32 = 0x80000000u32;
-    let mut p: i32 = 31;
-    let ad: u32 = i32::wrapping_abs(d) as u32;
-    let t: u32 = two31 + ((d as u32) >> 31);
-    let anc: u32 = u32::wrapping_sub(t - 1, t % ad);
-    let mut q1: u32 = two31 / anc;
-    let mut r1: u32 = two31 - q1 * anc;
-    let mut q2: u32 = two31 / ad;
-    let mut r2: u32 = two31 - q2 * ad;
-    loop {
-        p = p + 1;
-        q1 = 2 * q1;
-        r1 = 2 * r1;
-        if r1 >= anc {
-            q1 = q1 + 1;
-            r1 = r1 - anc;
-        }
-        q2 = 2 * q2;
-        r2 = 2 * r2;
-        if r2 >= ad {
-            q2 = q2 + 1;
-            r2 = r2 - ad;
-        }
-        let delta: u32 = ad - r2;
-        if !(q1 < delta || (q1 == delta && r1 == 0)) {
-            break;
-        }
-    }
-
-    MS32 {
-        mul_by: (if d < 0 {
-            u32::wrapping_neg(q2 + 1)
-        } else {
-            q2 + 1
-        }) as i32,
-        shift_by: p - 32,
-    }
-}
-
-pub fn magic_s64(d: i64) -> MS64 {
-    debug_assert_ne!(d, -1);
-    debug_assert_ne!(d, 0);
-    debug_assert_ne!(d, 1);
-    let two63: u64 = 0x8000000000000000u64;
-    let mut p: i32 = 63;
-    let ad: u64 = i64::wrapping_abs(d) as u64;
-    let t: u64 = two63 + ((d as u64) >> 63);
-    let anc: u64 = u64::wrapping_sub(t - 1, t % ad);
-    let mut q1: u64 = two63 / anc;
-    let mut r1: u64 = two63 - q1 * anc;
-    let mut q2: u64 = two63 / ad;
-    let mut r2: u64 = two63 - q2 * ad;
-    loop {
-        p = p + 1;
-        q1 = 2 * q1;
-        r1 = 2 * r1;
-        if r1 >= anc {
-            q1 = q1 + 1;
-            r1 = r1 - anc;
-        }
-        q2 = 2 * q2;
-        r2 = 2 * r2;
-        if r2 >= ad {
-            q2 = q2 + 1;
-            r2 = r2 - ad;
-        }
-        let delta: u64 = ad - r2;
-        if !(q1 < delta || (q1 == delta && r1 == 0)) {
-            break;
-        }
-    }
-
-    MS64 {
-        mul_by: (if d < 0 {
-            u64::wrapping_neg(q2 + 1)
-        } else {
-            q2 + 1
-        }) as i64,
-        shift_by: p - 64,
-    }
-}
-
-#[cfg(test)]
-mod tests {
-    use super::{magic_s32, magic_s64, magic_u32, magic_u64};
-    use super::{MS32, MS64, MU32, MU64};
-
-    fn make_mu32(mul_by: u32, do_add: bool, shift_by: i32) -> MU32 {
-        MU32 {
-            mul_by,
-            do_add,
-            shift_by,
-        }
-    }
-
-    fn make_mu64(mul_by: u64, do_add: bool, shift_by: i32) -> MU64 {
-        MU64 {
-            mul_by,
-            do_add,
-            shift_by,
-        }
-    }
-
-    fn make_ms32(mul_by: i32, shift_by: i32) -> MS32 {
-        MS32 { mul_by, shift_by }
-    }
-
-    fn make_ms64(mul_by: i64, shift_by: i32) -> MS64 {
-        MS64 { mul_by, shift_by }
-    }
-
-    #[test]
-    fn test_magic_u32() {
-        assert_eq!(magic_u32(2u32), make_mu32(0x80000000u32, false, 0));
-        assert_eq!(magic_u32(3u32), make_mu32(0xaaaaaaabu32, false, 1));
-        assert_eq!(magic_u32(4u32), make_mu32(0x40000000u32, false, 0));
-        assert_eq!(magic_u32(5u32), make_mu32(0xcccccccdu32, false, 2));
-        assert_eq!(magic_u32(6u32), make_mu32(0xaaaaaaabu32, false, 2));
-        assert_eq!(magic_u32(7u32), make_mu32(0x24924925u32, true, 3));
-        assert_eq!(magic_u32(9u32), make_mu32(0x38e38e39u32, false, 1));
-        assert_eq!(magic_u32(10u32), make_mu32(0xcccccccdu32, false, 3));
-        assert_eq!(magic_u32(11u32), make_mu32(0xba2e8ba3u32, false, 3));
-        assert_eq!(magic_u32(12u32), make_mu32(0xaaaaaaabu32, false, 3));
-        assert_eq!(magic_u32(25u32), make_mu32(0x51eb851fu32, false, 3));
-        assert_eq!(magic_u32(125u32), make_mu32(0x10624dd3u32, false, 3));
-        assert_eq!(magic_u32(625u32), make_mu32(0xd1b71759u32, false, 9));
-        assert_eq!(magic_u32(1337u32), make_mu32(0x88233b2bu32, true, 11));
-        assert_eq!(magic_u32(65535u32), make_mu32(0x80008001u32, false, 15));
-        assert_eq!(magic_u32(65536u32), make_mu32(0x00010000u32, false, 0));
-        assert_eq!(magic_u32(65537u32), make_mu32(0xffff0001u32, false, 16));
-        assert_eq!(magic_u32(31415927u32), make_mu32(0x445b4553u32, false, 23));
-        assert_eq!(
-            magic_u32(0xdeadbeefu32),
-            make_mu32(0x93275ab3u32, false, 31)
-        );
-        assert_eq!(
-            magic_u32(0xfffffffdu32),
-            make_mu32(0x40000001u32, false, 30)
-        );
-        assert_eq!(magic_u32(0xfffffffeu32), make_mu32(0x00000003u32, true, 32));
-        assert_eq!(
-            magic_u32(0xffffffffu32),
-            make_mu32(0x80000001u32, false, 31)
-        );
-    }
-
-    #[test]
-    fn test_magic_u64() {
-        assert_eq!(magic_u64(2u64), make_mu64(0x8000000000000000u64, false, 0));
-        assert_eq!(magic_u64(3u64), make_mu64(0xaaaaaaaaaaaaaaabu64, false, 1));
-        assert_eq!(magic_u64(4u64), make_mu64(0x4000000000000000u64, false, 0));
-        assert_eq!(magic_u64(5u64), make_mu64(0xcccccccccccccccdu64, false, 2));
-        assert_eq!(magic_u64(6u64), make_mu64(0xaaaaaaaaaaaaaaabu64, false, 2));
-        assert_eq!(magic_u64(7u64), make_mu64(0x2492492492492493u64, true, 3));
-        assert_eq!(magic_u64(9u64), make_mu64(0xe38e38e38e38e38fu64, false, 3));
-        assert_eq!(magic_u64(10u64), make_mu64(0xcccccccccccccccdu64, false, 3));
-        assert_eq!(magic_u64(11u64), make_mu64(0x2e8ba2e8ba2e8ba3u64, false, 1));
-        assert_eq!(magic_u64(12u64), make_mu64(0xaaaaaaaaaaaaaaabu64, false, 3));
-        assert_eq!(magic_u64(25u64), make_mu64(0x47ae147ae147ae15u64, true, 5));
-        assert_eq!(magic_u64(125u64), make_mu64(0x0624dd2f1a9fbe77u64, true, 7));
-        assert_eq!(
-            magic_u64(625u64),
-            make_mu64(0x346dc5d63886594bu64, false, 7)
-        );
-        assert_eq!(
-            magic_u64(1337u64),
-            make_mu64(0xc4119d952866a139u64, false, 10)
-        );
-        assert_eq!(
-            magic_u64(31415927u64),
-            make_mu64(0x116d154b9c3d2f85u64, true, 25)
-        );
-        assert_eq!(
-            magic_u64(0x00000000deadbeefu64),
-            make_mu64(0x93275ab2dfc9094bu64, false, 31)
-        );
-        assert_eq!(
-            magic_u64(0x00000000fffffffdu64),
-            make_mu64(0x8000000180000005u64, false, 31)
-        );
-        assert_eq!(
-            magic_u64(0x00000000fffffffeu64),
-            make_mu64(0x0000000200000005u64, true, 32)
-        );
-        assert_eq!(
-            magic_u64(0x00000000ffffffffu64),
-            make_mu64(0x8000000080000001u64, false, 31)
-        );
-        assert_eq!(
-            magic_u64(0x0000000100000000u64),
-            make_mu64(0x0000000100000000u64, false, 0)
-        );
-        assert_eq!(
-            magic_u64(0x0000000100000001u64),
-            make_mu64(0xffffffff00000001u64, false, 32)
-        );
-        assert_eq!(
-            magic_u64(0x0ddc0ffeebadf00du64),
-            make_mu64(0x2788e9d394b77da1u64, true, 60)
-        );
-        assert_eq!(
-            magic_u64(0xfffffffffffffffdu64),
-            make_mu64(0x4000000000000001u64, false, 62)
-        );
-        assert_eq!(
-            magic_u64(0xfffffffffffffffeu64),
-            make_mu64(0x0000000000000003u64, true, 64)
-        );
-        assert_eq!(
-            magic_u64(0xffffffffffffffffu64),
-            make_mu64(0x8000000000000001u64, false, 63)
-        );
-    }
-
-    #[test]
-    fn test_magic_s32() {
-        assert_eq!(
-            magic_s32(-0x80000000i32),
-            make_ms32(0x7fffffffu32 as i32, 30)
-        );
-        assert_eq!(
-            magic_s32(-0x7FFFFFFFi32),
-            make_ms32(0xbfffffffu32 as i32, 29)
-        );
-        assert_eq!(
-            magic_s32(-0x7FFFFFFEi32),
-            make_ms32(0x7ffffffdu32 as i32, 30)
-        );
-        assert_eq!(magic_s32(-31415927i32), make_ms32(0xbba4baadu32 as i32, 23));
-        assert_eq!(magic_s32(-1337i32), make_ms32(0x9df73135u32 as i32, 9));
-        assert_eq!(magic_s32(-256i32), make_ms32(0x7fffffffu32 as i32, 7));
-        assert_eq!(magic_s32(-5i32), make_ms32(0x99999999u32 as i32, 1));
-        assert_eq!(magic_s32(-3i32), make_ms32(0x55555555u32 as i32, 1));
-        assert_eq!(magic_s32(-2i32), make_ms32(0x7fffffffu32 as i32, 0));
-        assert_eq!(magic_s32(2i32), make_ms32(0x80000001u32 as i32, 0));
-        assert_eq!(magic_s32(3i32), make_ms32(0x55555556u32 as i32, 0));
-        assert_eq!(magic_s32(4i32), make_ms32(0x80000001u32 as i32, 1));
-        assert_eq!(magic_s32(5i32), make_ms32(0x66666667u32 as i32, 1));
-        assert_eq!(magic_s32(6i32), make_ms32(0x2aaaaaabu32 as i32, 0));
-        assert_eq!(magic_s32(7i32), make_ms32(0x92492493u32 as i32, 2));
-        assert_eq!(magic_s32(9i32), make_ms32(0x38e38e39u32 as i32, 1));
-        assert_eq!(magic_s32(10i32), make_ms32(0x66666667u32 as i32, 2));
-        assert_eq!(magic_s32(11i32), make_ms32(0x2e8ba2e9u32 as i32, 1));
-        assert_eq!(magic_s32(12i32), make_ms32(0x2aaaaaabu32 as i32, 1));
-        assert_eq!(magic_s32(25i32), make_ms32(0x51eb851fu32 as i32, 3));
-        assert_eq!(magic_s32(125i32), make_ms32(0x10624dd3u32 as i32, 3));
-        assert_eq!(magic_s32(625i32), make_ms32(0x68db8badu32 as i32, 8));
-        assert_eq!(magic_s32(1337i32), make_ms32(0x6208cecbu32 as i32, 9));
-        assert_eq!(magic_s32(31415927i32), make_ms32(0x445b4553u32 as i32, 23));
-        assert_eq!(
-            magic_s32(0x7ffffffei32),
-            make_ms32(0x80000003u32 as i32, 30)
-        );
-        assert_eq!(
-            magic_s32(0x7fffffffi32),
-            make_ms32(0x40000001u32 as i32, 29)
-        );
-    }
-
-    #[test]
-    fn test_magic_s64() {
-        assert_eq!(
-            magic_s64(-0x8000000000000000i64),
-            make_ms64(0x7fffffffffffffffu64 as i64, 62)
-        );
-        assert_eq!(
-            magic_s64(-0x7FFFFFFFFFFFFFFFi64),
-            make_ms64(0xbfffffffffffffffu64 as i64, 61)
-        );
-        assert_eq!(
-            magic_s64(-0x7FFFFFFFFFFFFFFEi64),
-            make_ms64(0x7ffffffffffffffdu64 as i64, 62)
-        );
-        assert_eq!(
-            magic_s64(-0x0ddC0ffeeBadF00di64),
-            make_ms64(0x6c3b8b1635a4412fu64 as i64, 59)
-        );
-        assert_eq!(
-            magic_s64(-0x100000001i64),
-            make_ms64(0x800000007fffffffu64 as i64, 31)
-        );
-        assert_eq!(
-            magic_s64(-0x100000000i64),
-            make_ms64(0x7fffffffffffffffu64 as i64, 31)
-        );
-        assert_eq!(
-            magic_s64(-0xFFFFFFFFi64),
-            make_ms64(0x7fffffff7fffffffu64 as i64, 31)
-        );
-        assert_eq!(
-            magic_s64(-0xFFFFFFFEi64),
-            make_ms64(0x7ffffffefffffffdu64 as i64, 31)
-        );
-        assert_eq!(
-            magic_s64(-0xFFFFFFFDi64),
-            make_ms64(0x7ffffffe7ffffffbu64 as i64, 31)
-        );
-        assert_eq!(
-            magic_s64(-0xDeadBeefi64),
-            make_ms64(0x6cd8a54d2036f6b5u64 as i64, 31)
-        );
-        assert_eq!(
-            magic_s64(-31415927i64),
-            make_ms64(0x7749755a31e1683du64 as i64, 24)
-        );
-        assert_eq!(
-            magic_s64(-1337i64),
-            make_ms64(0x9df731356bccaf63u64 as i64, 9)
-        );
-        assert_eq!(
-            magic_s64(-256i64),
-            make_ms64(0x7fffffffffffffffu64 as i64, 7)
-        );
-        assert_eq!(magic_s64(-5i64), make_ms64(0x9999999999999999u64 as i64, 1));
-        assert_eq!(magic_s64(-3i64), make_ms64(0x5555555555555555u64 as i64, 1));
-        assert_eq!(magic_s64(-2i64), make_ms64(0x7fffffffffffffffu64 as i64, 0));
-        assert_eq!(magic_s64(2i64), make_ms64(0x8000000000000001u64 as i64, 0));
-        assert_eq!(magic_s64(3i64), make_ms64(0x5555555555555556u64 as i64, 0));
-        assert_eq!(magic_s64(4i64), make_ms64(0x8000000000000001u64 as i64, 1));
-        assert_eq!(magic_s64(5i64), make_ms64(0x6666666666666667u64 as i64, 1));
-        assert_eq!(magic_s64(6i64), make_ms64(0x2aaaaaaaaaaaaaabu64 as i64, 0));
-        assert_eq!(magic_s64(7i64), make_ms64(0x4924924924924925u64 as i64, 1));
-        assert_eq!(magic_s64(9i64), make_ms64(0x1c71c71c71c71c72u64 as i64, 0));
-        assert_eq!(magic_s64(10i64), make_ms64(0x6666666666666667u64 as i64, 2));
-        assert_eq!(magic_s64(11i64), make_ms64(0x2e8ba2e8ba2e8ba3u64 as i64, 1));
-        assert_eq!(magic_s64(12i64), make_ms64(0x2aaaaaaaaaaaaaabu64 as i64, 1));
-        assert_eq!(magic_s64(25i64), make_ms64(0xa3d70a3d70a3d70bu64 as i64, 4));
-        assert_eq!(
-            magic_s64(125i64),
-            make_ms64(0x20c49ba5e353f7cfu64 as i64, 4)
-        );
-        assert_eq!(
-            magic_s64(625i64),
-            make_ms64(0x346dc5d63886594bu64 as i64, 7)
-        );
-        assert_eq!(
-            magic_s64(1337i64),
-            make_ms64(0x6208ceca9433509du64 as i64, 9)
-        );
-        assert_eq!(
-            magic_s64(31415927i64),
-            make_ms64(0x88b68aa5ce1e97c3u64 as i64, 24)
-        );
-        assert_eq!(
-            magic_s64(0x00000000deadbeefi64),
-            make_ms64(0x93275ab2dfc9094bu64 as i64, 31)
-        );
-        assert_eq!(
-            magic_s64(0x00000000fffffffdi64),
-            make_ms64(0x8000000180000005u64 as i64, 31)
-        );
-        assert_eq!(
-            magic_s64(0x00000000fffffffei64),
-            make_ms64(0x8000000100000003u64 as i64, 31)
-        );
-        assert_eq!(
-            magic_s64(0x00000000ffffffffi64),
-            make_ms64(0x8000000080000001u64 as i64, 31)
-        );
-        assert_eq!(
-            magic_s64(0x0000000100000000i64),
-            make_ms64(0x8000000000000001u64 as i64, 31)
-        );
-        assert_eq!(
-            magic_s64(0x0000000100000001i64),
-            make_ms64(0x7fffffff80000001u64 as i64, 31)
-        );
-        assert_eq!(
-            magic_s64(0x0ddc0ffeebadf00di64),
-            make_ms64(0x93c474e9ca5bbed1u64 as i64, 59)
-        );
-        assert_eq!(
-            magic_s64(0x7ffffffffffffffdi64),
-            make_ms64(0x2000000000000001u64 as i64, 60)
-        );
-        assert_eq!(
-            magic_s64(0x7ffffffffffffffei64),
-            make_ms64(0x8000000000000003u64 as i64, 62)
-        );
-        assert_eq!(
-            magic_s64(0x7fffffffffffffffi64),
-            make_ms64(0x4000000000000001u64 as i64, 61)
-        );
-    }
-
-    #[test]
-    fn test_magic_generators_dont_panic() {
-        // The point of this is to check that the magic number generators
-        // don't panic with integer wraparounds, especially at boundary cases
-        // for their arguments. The actual results are thrown away, although
-        // we force `total` to be used, so that rustc can't optimise the
-        // entire computation away.
-
-        // Testing UP magic_u32
-        let mut total: u64 = 0;
-        for x in 2..(200 * 1000u32) {
-            let m = magic_u32(x);
-            total = total ^ (m.mul_by as u64);
-            total = total + (m.shift_by as u64);
-            total = total + (if m.do_add { 123 } else { 456 });
-        }
-        assert_eq!(total, 2481999609);
-
-        total = 0;
-        // Testing MIDPOINT magic_u32
-        for x in 0x8000_0000u32 - 10 * 1000u32..0x8000_0000u32 + 10 * 1000u32 {
-            let m = magic_u32(x);
-            total = total ^ (m.mul_by as u64);
-            total = total + (m.shift_by as u64);
-            total = total + (if m.do_add { 123 } else { 456 });
-        }
-        assert_eq!(total, 2399809723);
-
-        total = 0;
-        // Testing DOWN magic_u32
-        for x in 0..(200 * 1000u32) {
-            let m = magic_u32(0xFFFF_FFFFu32 - x);
-            total = total ^ (m.mul_by as u64);
-            total = total + (m.shift_by as u64);
-            total = total + (if m.do_add { 123 } else { 456 });
-        }
-        assert_eq!(total, 271138267);
-
-        // Testing UP magic_u64
-        total = 0;
-        for x in 2..(200 * 1000u64) {
-            let m = magic_u64(x);
-            total = total ^ m.mul_by;
-            total = total + (m.shift_by as u64);
-            total = total + (if m.do_add { 123 } else { 456 });
-        }
-        assert_eq!(total, 7430004086976261161);
-
-        total = 0;
-        // Testing MIDPOINT magic_u64
-        for x in 0x8000_0000_0000_0000u64 - 10 * 1000u64..0x8000_0000_0000_0000u64 + 10 * 1000u64 {
-            let m = magic_u64(x);
-            total = total ^ m.mul_by;
-            total = total + (m.shift_by as u64);
-            total = total + (if m.do_add { 123 } else { 456 });
-        }
-        assert_eq!(total, 10312117246769520603);
-
-        // Testing DOWN magic_u64
-        total = 0;
-        for x in 0..(200 * 1000u64) {
-            let m = magic_u64(0xFFFF_FFFF_FFFF_FFFFu64 - x);
-            total = total ^ m.mul_by;
-            total = total + (m.shift_by as u64);
-            total = total + (if m.do_add { 123 } else { 456 });
-        }
-        assert_eq!(total, 1126603594357269734);
-
-        // Testing UP magic_s32
-        total = 0;
-        for x in 0..(200 * 1000i32) {
-            let m = magic_s32(-0x8000_0000i32 + x);
-            total = total ^ (m.mul_by as u64);
-            total = total + (m.shift_by as u64);
-        }
-        assert_eq!(total, 18446744069953376812);
-
-        total = 0;
-        // Testing MIDPOINT magic_s32
-        for x in 0..(200 * 1000i32) {
-            let x2 = -100 * 1000i32 + x;
-            if x2 != -1 && x2 != 0 && x2 != 1 {
-                let m = magic_s32(x2);
-                total = total ^ (m.mul_by as u64);
-                total = total + (m.shift_by as u64);
-            }
-        }
-        assert_eq!(total, 351839350);
-
-        // Testing DOWN magic_s32
-        total = 0;
-        for x in 0..(200 * 1000i32) {
-            let m = magic_s32(0x7FFF_FFFFi32 - x);
-            total = total ^ (m.mul_by as u64);
-            total = total + (m.shift_by as u64);
-        }
-        assert_eq!(total, 18446744072916880714);
-
-        // Testing UP magic_s64
-        total = 0;
-        for x in 0..(200 * 1000i64) {
-            let m = magic_s64(-0x8000_0000_0000_0000i64 + x);
-            total = total ^ (m.mul_by as u64);
-            total = total + (m.shift_by as u64);
-        }
-        assert_eq!(total, 17929885647724831014);
-
-        total = 0;
-        // Testing MIDPOINT magic_s64
-        for x in 0..(200 * 1000i64) {
-            let x2 = -100 * 1000i64 + x;
-            if x2 != -1 && x2 != 0 && x2 != 1 {
-                let m = magic_s64(x2);
-                total = total ^ (m.mul_by as u64);
-                total = total + (m.shift_by as u64);
-            }
-        }
-        assert_eq!(total, 18106042338125661964);
-
-        // Testing DOWN magic_s64
-        total = 0;
-        for x in 0..(200 * 1000i64) {
-            let m = magic_s64(0x7FFF_FFFF_FFFF_FFFFi64 - x);
-            total = total ^ (m.mul_by as u64);
-            total = total + (m.shift_by as u64);
-        }
-        assert_eq!(total, 563301797155560970);
-    }
-
-    #[test]
-    fn test_magic_generators_give_correct_numbers() {
-        // For a variety of values for both `n` and `d`, compute the magic
-        // numbers for `d`, and in effect interpret them so as to compute
-        // `n / d`.  Check that that equals the value of `n / d` computed
-        // directly by the hardware.  This serves to check that the magic
-        // number generates work properly.  In total, 50,148,000 tests are
-        // done.
-
-        // Some constants
-        const MIN_U32: u32 = 0;
-        const MAX_U32: u32 = 0xFFFF_FFFFu32;
-        const MAX_U32_HALF: u32 = 0x8000_0000u32; // more or less
-
-        const MIN_S32: i32 = 0x8000_0000u32 as i32;
-        const MAX_S32: i32 = 0x7FFF_FFFFu32 as i32;
-
-        const MIN_U64: u64 = 0;
-        const MAX_U64: u64 = 0xFFFF_FFFF_FFFF_FFFFu64;
-        const MAX_U64_HALF: u64 = 0x8000_0000_0000_0000u64; // ditto
-
-        const MIN_S64: i64 = 0x8000_0000_0000_0000u64 as i64;
-        const MAX_S64: i64 = 0x7FFF_FFFF_FFFF_FFFFu64 as i64;
-
-        // These generate reference results for signed/unsigned 32/64 bit
-        // division, rounding towards zero.
-        fn div_u32(x: u32, y: u32) -> u32 {
-            return x / y;
-        }
-        fn div_s32(x: i32, y: i32) -> i32 {
-            return x / y;
-        }
-        fn div_u64(x: u64, y: u64) -> u64 {
-            return x / y;
-        }
-        fn div_s64(x: i64, y: i64) -> i64 {
-            return x / y;
-        }
-
-        // Returns the high half of a 32 bit unsigned widening multiply.
-        fn mulhw_u32(x: u32, y: u32) -> u32 {
-            let x64: u64 = x as u64;
-            let y64: u64 = y as u64;
-            let r64: u64 = x64 * y64;
-            (r64 >> 32) as u32
-        }
-
-        // Returns the high half of a 32 bit signed widening multiply.
-        fn mulhw_s32(x: i32, y: i32) -> i32 {
-            let x64: i64 = x as i64;
-            let y64: i64 = y as i64;
-            let r64: i64 = x64 * y64;
-            (r64 >> 32) as i32
-        }
-
-        // Returns the high half of a 64 bit unsigned widening multiply.
-        fn mulhw_u64(x: u64, y: u64) -> u64 {
-            let t0: u64 = x & 0xffffffffu64;
-            let t1: u64 = x >> 32;
-            let t2: u64 = y & 0xffffffffu64;
-            let t3: u64 = y >> 32;
-            let t4: u64 = t0 * t2;
-            let t5: u64 = t1 * t2 + (t4 >> 32);
-            let t6: u64 = t5 & 0xffffffffu64;
-            let t7: u64 = t5 >> 32;
-            let t8: u64 = t0 * t3 + t6;
-            let t9: u64 = t1 * t3 + t7 + (t8 >> 32);
-            t9
-        }
-
-        // Returns the high half of a 64 bit signed widening multiply.
-        fn mulhw_s64(x: i64, y: i64) -> i64 {
-            let t0: u64 = x as u64 & 0xffffffffu64;
-            let t1: i64 = x >> 32;
-            let t2: u64 = y as u64 & 0xffffffffu64;
-            let t3: i64 = y >> 32;
-            let t4: u64 = t0 * t2;
-            let t5: i64 = t1 * t2 as i64 + (t4 >> 32) as i64;
-            let t6: u64 = t5 as u64 & 0xffffffffu64;
-            let t7: i64 = t5 >> 32;
-            let t8: i64 = t0 as i64 * t3 + t6 as i64;
-            let t9: i64 = t1 * t3 + t7 + (t8 >> 32);
-            t9
-        }
-
-        // Compute the magic numbers for `d` and then use them to compute and
-        // check `n / d` for around 1000 values of `n`, using unsigned 32-bit
-        // division.
-        fn test_magic_u32_inner(d: u32, n_tests_done: &mut i32) {
-            // Advance the numerator (the `n` in `n / d`) so as to test
-            // densely near the range ends (and, in the signed variants, near
-            // zero) but not so densely away from those regions.
-            fn advance_n_u32(x: u32) -> u32 {
-                if x < MIN_U32 + 110 {
-                    return x + 1;
-                }
-                if x < MIN_U32 + 1700 {
-                    return x + 23;
-                }
-                if x < MAX_U32 - 1700 {
-                    let xd: f64 = (x as f64) * 1.06415927;
-                    return if xd >= (MAX_U32 - 1700) as f64 {
-                        MAX_U32 - 1700
-                    } else {
-                        xd as u32
-                    };
-                }
-                if x < MAX_U32 - 110 {
-                    return x + 23;
-                }
-                u32::wrapping_add(x, 1)
-            }
-
-            let magic: MU32 = magic_u32(d);
-            let mut n: u32 = MIN_U32;
-            loop {
-                *n_tests_done += 1;
-                // Compute and check `q = n / d` using `magic`.
-                let mut q: u32 = mulhw_u32(n, magic.mul_by);
-                if magic.do_add {
-                    assert!(magic.shift_by >= 1 && magic.shift_by <= 32);
-                    let mut t: u32 = n - q;
-                    t >>= 1;
-                    t = t + q;
-                    q = t >> (magic.shift_by - 1);
-                } else {
-                    assert!(magic.shift_by >= 0 && magic.shift_by <= 31);
-                    q >>= magic.shift_by;
-                }
-
-                assert_eq!(q, div_u32(n, d));
-
-                n = advance_n_u32(n);
-                if n == MIN_U32 {
-                    break;
-                }
-            }
-        }
-
-        // Compute the magic numbers for `d` and then use them to compute and
-        // check `n / d` for around 1000 values of `n`, using signed 32-bit
-        // division.
-        fn test_magic_s32_inner(d: i32, n_tests_done: &mut i32) {
-            // See comment on advance_n_u32 above.
-            fn advance_n_s32(x: i32) -> i32 {
-                if x >= 0 && x <= 29 {
-                    return x + 1;
-                }
-                if x < MIN_S32 + 110 {
-                    return x + 1;
-                }
-                if x < MIN_S32 + 1700 {
-                    return x + 23;
-                }
-                if x < MAX_S32 - 1700 {
-                    let mut xd: f64 = x as f64;
-                    xd = if xd < 0.0 {
-                        xd / 1.06415927
-                    } else {
-                        xd * 1.06415927
-                    };
-                    return if xd >= (MAX_S32 - 1700) as f64 {
-                        MAX_S32 - 1700
-                    } else {
-                        xd as i32
-                    };
-                }
-                if x < MAX_S32 - 110 {
-                    return x + 23;
-                }
-                if x == MAX_S32 {
-                    return MIN_S32;
-                }
-                x + 1
-            }
-
-            let magic: MS32 = magic_s32(d);
-            let mut n: i32 = MIN_S32;
-            loop {
-                *n_tests_done += 1;
-                // Compute and check `q = n / d` using `magic`.
-                let mut q: i32 = mulhw_s32(n, magic.mul_by);
-                if d > 0 && magic.mul_by < 0 {
-                    q = q + n;
-                } else if d < 0 && magic.mul_by > 0 {
-                    q = q - n;
-                }
-                assert!(magic.shift_by >= 0 && magic.shift_by <= 31);
-                q = q >> magic.shift_by;
-                let mut t: u32 = q as u32;
-                t = t >> 31;
-                q = q + (t as i32);
-
-                assert_eq!(q, div_s32(n, d));
-
-                n = advance_n_s32(n);
-                if n == MIN_S32 {
-                    break;
-                }
-            }
-        }
-
-        // Compute the magic numbers for `d` and then use them to compute and
-        // check `n / d` for around 1000 values of `n`, using unsigned 64-bit
-        // division.
-        fn test_magic_u64_inner(d: u64, n_tests_done: &mut i32) {
-            // See comment on advance_n_u32 above.
-            fn advance_n_u64(x: u64) -> u64 {
-                if x < MIN_U64 + 110 {
-                    return x + 1;
-                }
-                if x < MIN_U64 + 1700 {
-                    return x + 23;
-                }
-                if x < MAX_U64 - 1700 {
-                    let xd: f64 = (x as f64) * 1.06415927;
-                    return if xd >= (MAX_U64 - 1700) as f64 {
-                        MAX_U64 - 1700
-                    } else {
-                        xd as u64
-                    };
-                }
-                if x < MAX_U64 - 110 {
-                    return x + 23;
-                }
-                u64::wrapping_add(x, 1)
-            }
-
-            let magic: MU64 = magic_u64(d);
-            let mut n: u64 = MIN_U64;
-            loop {
-                *n_tests_done += 1;
-                // Compute and check `q = n / d` using `magic`.
-                let mut q = mulhw_u64(n, magic.mul_by);
-                if magic.do_add {
-                    assert!(magic.shift_by >= 1 && magic.shift_by <= 64);
-                    let mut t: u64 = n - q;
-                    t >>= 1;
-                    t = t + q;
-                    q = t >> (magic.shift_by - 1);
-                } else {
-                    assert!(magic.shift_by >= 0 && magic.shift_by <= 63);
-                    q >>= magic.shift_by;
-                }
-
-                assert_eq!(q, div_u64(n, d));
-
-                n = advance_n_u64(n);
-                if n == MIN_U64 {
-                    break;
-                }
-            }
-        }
-
-        // Compute the magic numbers for `d` and then use them to compute and
-        // check `n / d` for around 1000 values of `n`, using signed 64-bit
-        // division.
-        fn test_magic_s64_inner(d: i64, n_tests_done: &mut i32) {
-            // See comment on advance_n_u32 above.
-            fn advance_n_s64(x: i64) -> i64 {
-                if x >= 0 && x <= 29 {
-                    return x + 1;
-                }
-                if x < MIN_S64 + 110 {
-                    return x + 1;
-                }
-                if x < MIN_S64 + 1700 {
-                    return x + 23;
-                }
-                if x < MAX_S64 - 1700 {
-                    let mut xd: f64 = x as f64;
-                    xd = if xd < 0.0 {
-                        xd / 1.06415927
-                    } else {
-                        xd * 1.06415927
-                    };
-                    return if xd >= (MAX_S64 - 1700) as f64 {
-                        MAX_S64 - 1700
-                    } else {
-                        xd as i64
-                    };
-                }
-                if x < MAX_S64 - 110 {
-                    return x + 23;
-                }
-                if x == MAX_S64 {
-                    return MIN_S64;
-                }
-                x + 1
-            }
-
-            let magic: MS64 = magic_s64(d);
-            let mut n: i64 = MIN_S64;
-            loop {
-                *n_tests_done += 1;
-                // Compute and check `q = n / d` using `magic`. */
-                let mut q: i64 = mulhw_s64(n, magic.mul_by);
-                if d > 0 && magic.mul_by < 0 {
-                    q = q + n;
-                } else if d < 0 && magic.mul_by > 0 {
-                    q = q - n;
-                }
-                assert!(magic.shift_by >= 0 && magic.shift_by <= 63);
-                q = q >> magic.shift_by;
-                let mut t: u64 = q as u64;
-                t = t >> 63;
-                q = q + (t as i64);
-
-                assert_eq!(q, div_s64(n, d));
-
-                n = advance_n_s64(n);
-                if n == MIN_S64 {
-                    break;
-                }
-            }
-        }
-
-        // Using all the above support machinery, actually run the tests.
-
-        let mut n_tests_done: i32 = 0;
-
-        // u32 division tests
-        {
-            // 2 .. 3k
-            let mut d: u32 = 2;
-            for _ in 0..3 * 1000 {
-                test_magic_u32_inner(d, &mut n_tests_done);
-                d += 1;
-            }
-
-            // across the midpoint: midpoint - 3k .. midpoint + 3k
-            d = MAX_U32_HALF - 3 * 1000;
-            for _ in 0..2 * 3 * 1000 {
-                test_magic_u32_inner(d, &mut n_tests_done);
-                d += 1;
-            }
-
-            // MAX_U32 - 3k .. MAX_U32 (in reverse order)
-            d = MAX_U32;
-            for _ in 0..3 * 1000 {
-                test_magic_u32_inner(d, &mut n_tests_done);
-                d -= 1;
-            }
-        }
-
-        // s32 division tests
-        {
-            // MIN_S32 .. MIN_S32 + 3k
-            let mut d: i32 = MIN_S32;
-            for _ in 0..3 * 1000 {
-                test_magic_s32_inner(d, &mut n_tests_done);
-                d += 1;
-            }
-
-            // -3k .. -2 (in reverse order)
-            d = -2;
-            for _ in 0..3 * 1000 {
-                test_magic_s32_inner(d, &mut n_tests_done);
-                d -= 1;
-            }
-
-            // 2 .. 3k
-            d = 2;
-            for _ in 0..3 * 1000 {
-                test_magic_s32_inner(d, &mut n_tests_done);
-                d += 1;
-            }
-
-            // MAX_S32 - 3k .. MAX_S32 (in reverse order)
-            d = MAX_S32;
-            for _ in 0..3 * 1000 {
-                test_magic_s32_inner(d, &mut n_tests_done);
-                d -= 1;
-            }
-        }
-
-        // u64 division tests
-        {
-            // 2 .. 3k
-            let mut d: u64 = 2;
-            for _ in 0..3 * 1000 {
-                test_magic_u64_inner(d, &mut n_tests_done);
-                d += 1;
-            }
-
-            // across the midpoint: midpoint - 3k .. midpoint + 3k
-            d = MAX_U64_HALF - 3 * 1000;
-            for _ in 0..2 * 3 * 1000 {
-                test_magic_u64_inner(d, &mut n_tests_done);
-                d += 1;
-            }
-
-            // mAX_U64 - 3000 .. mAX_U64 (in reverse order)
-            d = MAX_U64;
-            for _ in 0..3 * 1000 {
-                test_magic_u64_inner(d, &mut n_tests_done);
-                d -= 1;
-            }
-        }
-
-        // s64 division tests
-        {
-            // MIN_S64 .. MIN_S64 + 3k
-            let mut d: i64 = MIN_S64;
-            for _ in 0..3 * 1000 {
-                test_magic_s64_inner(d, &mut n_tests_done);
-                d += 1;
-            }
-
-            // -3k .. -2 (in reverse order)
-            d = -2;
-            for _ in 0..3 * 1000 {
-                test_magic_s64_inner(d, &mut n_tests_done);
-                d -= 1;
-            }
-
-            // 2 .. 3k
-            d = 2;
-            for _ in 0..3 * 1000 {
-                test_magic_s64_inner(d, &mut n_tests_done);
-                d += 1;
-            }
-
-            // MAX_S64 - 3k .. MAX_S64 (in reverse order)
-            d = MAX_S64;
-            for _ in 0..3 * 1000 {
-                test_magic_s64_inner(d, &mut n_tests_done);
-                d -= 1;
-            }
-        }
-        assert_eq!(n_tests_done, 50_148_000);
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/dominator_tree.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/dominator_tree.rs
deleted file mode 100644
index 5077354f7..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/dominator_tree.rs
+++ /dev/null
@@ -1,837 +0,0 @@
-//! A Dominator Tree represented as mappings of Blocks to their immediate dominator.
-
-use crate::entity::SecondaryMap;
-use crate::flowgraph::{BlockPredecessor, ControlFlowGraph};
-use crate::ir::instructions::BranchInfo;
-use crate::ir::{Block, ExpandedProgramPoint, Function, Inst, Layout, ProgramOrder, Value};
-use crate::packed_option::PackedOption;
-use crate::timing;
-use alloc::vec::Vec;
-use core::cmp;
-use core::cmp::Ordering;
-use core::mem;
-
-/// RPO numbers are not first assigned in a contiguous way but as multiples of STRIDE, to leave
-/// room for modifications of the dominator tree.
-const STRIDE: u32 = 4;
-
-/// Special RPO numbers used during `compute_postorder`.
-const DONE: u32 = 1;
-const SEEN: u32 = 2;
-
-/// Dominator tree node. We keep one of these per block.
-#[derive(Clone, Default)]
-struct DomNode {
-    /// Number of this node in a reverse post-order traversal of the CFG, starting from 1.
-    /// This number is monotonic in the reverse postorder but not contiguous, since we leave
-    /// holes for later localized modifications of the dominator tree.
-    /// Unreachable nodes get number 0, all others are positive.
-    rpo_number: u32,
-
-    /// The immediate dominator of this block, represented as the branch or jump instruction at the
-    /// end of the dominating basic block.
-    ///
-    /// This is `None` for unreachable blocks and the entry block which doesn't have an immediate
-    /// dominator.
-    idom: PackedOption<Inst>,
-}
-
-/// The dominator tree for a single function.
-pub struct DominatorTree {
-    nodes: SecondaryMap<Block, DomNode>,
-
-    /// CFG post-order of all reachable blocks.
-    postorder: Vec<Block>,
-
-    /// Scratch memory used by `compute_postorder()`.
-    stack: Vec<Block>,
-
-    valid: bool,
-}
-
-/// Methods for querying the dominator tree.
-impl DominatorTree {
-    /// Is `block` reachable from the entry block?
-    pub fn is_reachable(&self, block: Block) -> bool {
-        self.nodes[block].rpo_number != 0
-    }
-
-    /// Get the CFG post-order of blocks that was used to compute the dominator tree.
-    ///
-    /// Note that this post-order is not updated automatically when the CFG is modified. It is
-    /// computed from scratch and cached by `compute()`.
-    pub fn cfg_postorder(&self) -> &[Block] {
-        debug_assert!(self.is_valid());
-        &self.postorder
-    }
-
-    /// Returns the immediate dominator of `block`.
-    ///
-    /// The immediate dominator of a basic block is a basic block which we represent by
-    /// the branch or jump instruction at the end of the basic block. This does not have to be the
-    /// terminator of its block.
-    ///
-    /// A branch or jump is said to *dominate* `block` if all control flow paths from the function
-    /// entry to `block` must go through the branch.
-    ///
-    /// The *immediate dominator* is the dominator that is closest to `block`. All other dominators
-    /// also dominate the immediate dominator.
-    ///
-    /// This returns `None` if `block` is not reachable from the entry block, or if it is the entry block
-    /// which has no dominators.
-    pub fn idom(&self, block: Block) -> Option<Inst> {
-        self.nodes[block].idom.into()
-    }
-
-    /// Compare two blocks relative to the reverse post-order.
-    fn rpo_cmp_block(&self, a: Block, b: Block) -> Ordering {
-        self.nodes[a].rpo_number.cmp(&self.nodes[b].rpo_number)
-    }
-
-    /// Compare two program points relative to a reverse post-order traversal of the control-flow
-    /// graph.
-    ///
-    /// Return `Ordering::Less` if `a` comes before `b` in the RPO.
-    ///
-    /// If `a` and `b` belong to the same block, compare their relative position in the block.
-    pub fn rpo_cmp<A, B>(&self, a: A, b: B, layout: &Layout) -> Ordering
-    where
-        A: Into<ExpandedProgramPoint>,
-        B: Into<ExpandedProgramPoint>,
-    {
-        let a = a.into();
-        let b = b.into();
-        self.rpo_cmp_block(layout.pp_block(a), layout.pp_block(b))
-            .then(layout.cmp(a, b))
-    }
-
-    /// Returns `true` if `a` dominates `b`.
-    ///
-    /// This means that every control-flow path from the function entry to `b` must go through `a`.
-    ///
-    /// Dominance is ill defined for unreachable blocks. This function can always determine
-    /// dominance for instructions in the same block, but otherwise returns `false` if either block
-    /// is unreachable.
-    ///
-    /// An instruction is considered to dominate itself.
-    pub fn dominates<A, B>(&self, a: A, b: B, layout: &Layout) -> bool
-    where
-        A: Into<ExpandedProgramPoint>,
-        B: Into<ExpandedProgramPoint>,
-    {
-        let a = a.into();
-        let b = b.into();
-        match a {
-            ExpandedProgramPoint::Block(block_a) => {
-                a == b || self.last_dominator(block_a, b, layout).is_some()
-            }
-            ExpandedProgramPoint::Inst(inst_a) => {
-                let block_a = layout
-                    .inst_block(inst_a)
-                    .expect("Instruction not in layout.");
-                match self.last_dominator(block_a, b, layout) {
-                    Some(last) => layout.cmp(inst_a, last) != Ordering::Greater,
-                    None => false,
-                }
-            }
-        }
-    }
-
-    /// Find the last instruction in `a` that dominates `b`.
-    /// If no instructions in `a` dominate `b`, return `None`.
-    pub fn last_dominator<B>(&self, a: Block, b: B, layout: &Layout) -> Option<Inst>
-    where
-        B: Into<ExpandedProgramPoint>,
-    {
-        let (mut block_b, mut inst_b) = match b.into() {
-            ExpandedProgramPoint::Block(block) => (block, None),
-            ExpandedProgramPoint::Inst(inst) => (
-                layout.inst_block(inst).expect("Instruction not in layout."),
-                Some(inst),
-            ),
-        };
-        let rpo_a = self.nodes[a].rpo_number;
-
-        // Run a finger up the dominator tree from b until we see a.
-        // Do nothing if b is unreachable.
-        while rpo_a < self.nodes[block_b].rpo_number {
-            let idom = match self.idom(block_b) {
-                Some(idom) => idom,
-                None => return None, // a is unreachable, so we climbed past the entry
-            };
-            block_b = layout.inst_block(idom).expect("Dominator got removed.");
-            inst_b = Some(idom);
-        }
-        if a == block_b {
-            inst_b
-        } else {
-            None
-        }
-    }
-
-    /// Compute the common dominator of two basic blocks.
-    ///
-    /// Both basic blocks are assumed to be reachable.
-    pub fn common_dominator(
-        &self,
-        mut a: BlockPredecessor,
-        mut b: BlockPredecessor,
-        layout: &Layout,
-    ) -> BlockPredecessor {
-        loop {
-            match self.rpo_cmp_block(a.block, b.block) {
-                Ordering::Less => {
-                    // `a` comes before `b` in the RPO. Move `b` up.
-                    let idom = self.nodes[b.block].idom.expect("Unreachable basic block?");
-                    b = BlockPredecessor::new(
-                        layout.inst_block(idom).expect("Dangling idom instruction"),
-                        idom,
-                    );
-                }
-                Ordering::Greater => {
-                    // `b` comes before `a` in the RPO. Move `a` up.
-                    let idom = self.nodes[a.block].idom.expect("Unreachable basic block?");
-                    a = BlockPredecessor::new(
-                        layout.inst_block(idom).expect("Dangling idom instruction"),
-                        idom,
-                    );
-                }
-                Ordering::Equal => break,
-            }
-        }
-
-        debug_assert_eq!(
-            a.block, b.block,
-            "Unreachable block passed to common_dominator?"
-        );
-
-        // We're in the same block. The common dominator is the earlier instruction.
-        if layout.cmp(a.inst, b.inst) == Ordering::Less {
-            a
-        } else {
-            b
-        }
-    }
-}
-
-impl DominatorTree {
-    /// Allocate a new blank dominator tree. Use `compute` to compute the dominator tree for a
-    /// function.
-    pub fn new() -> Self {
-        Self {
-            nodes: SecondaryMap::new(),
-            postorder: Vec::new(),
-            stack: Vec::new(),
-            valid: false,
-        }
-    }
-
-    /// Allocate and compute a dominator tree.
-    pub fn with_function(func: &Function, cfg: &ControlFlowGraph) -> Self {
-        let block_capacity = func.layout.block_capacity();
-        let mut domtree = Self {
-            nodes: SecondaryMap::with_capacity(block_capacity),
-            postorder: Vec::with_capacity(block_capacity),
-            stack: Vec::new(),
-            valid: false,
-        };
-        domtree.compute(func, cfg);
-        domtree
-    }
-
-    /// Reset and compute a CFG post-order and dominator tree.
-    pub fn compute(&mut self, func: &Function, cfg: &ControlFlowGraph) {
-        let _tt = timing::domtree();
-        debug_assert!(cfg.is_valid());
-        self.compute_postorder(func);
-        self.compute_domtree(func, cfg);
-        self.valid = true;
-    }
-
-    /// Clear the data structures used to represent the dominator tree. This will leave the tree in
-    /// a state where `is_valid()` returns false.
-    pub fn clear(&mut self) {
-        self.nodes.clear();
-        self.postorder.clear();
-        debug_assert!(self.stack.is_empty());
-        self.valid = false;
-    }
-
-    /// Check if the dominator tree is in a valid state.
-    ///
-    /// Note that this doesn't perform any kind of validity checks. It simply checks if the
-    /// `compute()` method has been called since the last `clear()`. It does not check that the
-    /// dominator tree is consistent with the CFG.
-    pub fn is_valid(&self) -> bool {
-        self.valid
-    }
-
-    /// Reset all internal data structures and compute a post-order of the control flow graph.
-    ///
-    /// This leaves `rpo_number == 1` for all reachable blocks, 0 for unreachable ones.
-    fn compute_postorder(&mut self, func: &Function) {
-        self.clear();
-        self.nodes.resize(func.dfg.num_blocks());
-
-        // This algorithm is a depth first traversal (DFT) of the control flow graph, computing a
-        // post-order of the blocks that are reachable form the entry block. A DFT post-order is not
-        // unique. The specific order we get is controlled by two factors:
-        //
-        // 1. The order each node's children are visited, and
-        // 2. The method used for pruning graph edges to get a tree.
-        //
-        // There are two ways of viewing the CFG as a graph:
-        //
-        // 1. Each block is a node, with outgoing edges for all the branches in the block.
-        // 2. Each basic block is a node, with outgoing edges for the single branch at the end of
-        //    the BB. (A block is a linear sequence of basic blocks).
-        //
-        // The first graph is a contraction of the second one. We want to compute a block post-order
-        // that is compatible both graph interpretations. That is, if you compute a BB post-order
-        // and then remove those BBs that do not correspond to block headers, you get a post-order of
-        // the block graph.
-        //
-        // Node child order:
-        //
-        //     In the BB graph, we always go down the fall-through path first and follow the branch
-        //     destination second.
-        //
-        //     In the block graph, this is equivalent to visiting block successors in a bottom-up
-        //     order, starting from the destination of the block's terminating jump, ending at the
-        //     destination of the first branch in the block.
-        //
-        // Edge pruning:
-        //
-        //     In the BB graph, we keep an edge to a block the first time we visit the *source* side
-        //     of the edge. Any subsequent edges to the same block are pruned.
-        //
-        //     The equivalent tree is reached in the block graph by keeping the first edge to a block
-        //     in a top-down traversal of the successors. (And then visiting edges in a bottom-up
-        //     order).
-        //
-        // This pruning method makes it possible to compute the DFT without storing lots of
-        // information about the progress through a block.
-
-        // During this algorithm only, use `rpo_number` to hold the following state:
-        //
-        //   0:    block has not yet been reached in the pre-order.
-        //   SEEN: block has been pushed on the stack but successors not yet pushed.
-        //   DONE: Successors pushed.
-
-        match func.layout.entry_block() {
-            Some(block) => {
-                self.stack.push(block);
-                self.nodes[block].rpo_number = SEEN;
-            }
-            None => return,
-        }
-
-        while let Some(block) = self.stack.pop() {
-            match self.nodes[block].rpo_number {
-                SEEN => {
-                    // This is the first time we pop the block, so we need to scan its successors and
-                    // then revisit it.
-                    self.nodes[block].rpo_number = DONE;
-                    self.stack.push(block);
-                    self.push_successors(func, block);
-                }
-                DONE => {
-                    // This is the second time we pop the block, so all successors have been
-                    // processed.
-                    self.postorder.push(block);
-                }
-                _ => unreachable!(),
-            }
-        }
-    }
-
-    /// Push `block` successors onto `self.stack`, filtering out those that have already been seen.
-    ///
-    /// The successors are pushed in program order which is important to get a split-invariant
-    /// post-order. Split-invariant means that if a block is split in two, we get the same
-    /// post-order except for the insertion of the new block header at the split point.
-    fn push_successors(&mut self, func: &Function, block: Block) {
-        for inst in func.layout.block_likely_branches(block) {
-            match func.dfg.analyze_branch(inst) {
-                BranchInfo::SingleDest(succ, _) => self.push_if_unseen(succ),
-                BranchInfo::Table(jt, dest) => {
-                    for succ in func.jump_tables[jt].iter() {
-                        self.push_if_unseen(*succ);
-                    }
-                    if let Some(dest) = dest {
-                        self.push_if_unseen(dest);
-                    }
-                }
-                BranchInfo::NotABranch => {}
-            }
-        }
-    }
-
-    /// Push `block` onto `self.stack` if it has not already been seen.
-    fn push_if_unseen(&mut self, block: Block) {
-        if self.nodes[block].rpo_number == 0 {
-            self.nodes[block].rpo_number = SEEN;
-            self.stack.push(block);
-        }
-    }
-
-    /// Build a dominator tree from a control flow graph using Keith D. Cooper's
-    /// "Simple, Fast Dominator Algorithm."
-    fn compute_domtree(&mut self, func: &Function, cfg: &ControlFlowGraph) {
-        // During this algorithm, `rpo_number` has the following values:
-        //
-        // 0: block is not reachable.
-        // 1: block is reachable, but has not yet been visited during the first pass. This is set by
-        // `compute_postorder`.
-        // 2+: block is reachable and has an assigned RPO number.
-
-        // We'll be iterating over a reverse post-order of the CFG, skipping the entry block.
-        let (entry_block, postorder) = match self.postorder.as_slice().split_last() {
-            Some((&eb, rest)) => (eb, rest),
-            None => return,
-        };
-        debug_assert_eq!(Some(entry_block), func.layout.entry_block());
-
-        // Do a first pass where we assign RPO numbers to all reachable nodes.
-        self.nodes[entry_block].rpo_number = 2 * STRIDE;
-        for (rpo_idx, &block) in postorder.iter().rev().enumerate() {
-            // Update the current node and give it an RPO number.
-            // The entry block got 2, the rest start at 3 by multiples of STRIDE to leave
-            // room for future dominator tree modifications.
-            //
-            // Since `compute_idom` will only look at nodes with an assigned RPO number, the
-            // function will never see an uninitialized predecessor.
-            //
-            // Due to the nature of the post-order traversal, every node we visit will have at
-            // least one predecessor that has previously been visited during this RPO.
-            self.nodes[block] = DomNode {
-                idom: self.compute_idom(block, cfg, &func.layout).into(),
-                rpo_number: (rpo_idx as u32 + 3) * STRIDE,
-            }
-        }
-
-        // Now that we have RPO numbers for everything and initial immediate dominator estimates,
-        // iterate until convergence.
-        //
-        // If the function is free of irreducible control flow, this will exit after one iteration.
-        let mut changed = true;
-        while changed {
-            changed = false;
-            for &block in postorder.iter().rev() {
-                let idom = self.compute_idom(block, cfg, &func.layout).into();
-                if self.nodes[block].idom != idom {
-                    self.nodes[block].idom = idom;
-                    changed = true;
-                }
-            }
-        }
-    }
-
-    // Compute the immediate dominator for `block` using the current `idom` states for the reachable
-    // nodes.
-    fn compute_idom(&self, block: Block, cfg: &ControlFlowGraph, layout: &Layout) -> Inst {
-        // Get an iterator with just the reachable, already visited predecessors to `block`.
-        // Note that during the first pass, `rpo_number` is 1 for reachable blocks that haven't
-        // been visited yet, 0 for unreachable blocks.
-        let mut reachable_preds = cfg
-            .pred_iter(block)
-            .filter(|&BlockPredecessor { block: pred, .. }| self.nodes[pred].rpo_number > 1);
-
-        // The RPO must visit at least one predecessor before this node.
-        let mut idom = reachable_preds
-            .next()
-            .expect("block node must have one reachable predecessor");
-
-        for pred in reachable_preds {
-            idom = self.common_dominator(idom, pred, layout);
-        }
-
-        idom.inst
-    }
-}
-
-/// Optional pre-order information that can be computed for a dominator tree.
-///
-/// This data structure is computed from a `DominatorTree` and provides:
-///
-/// - A forward traversable dominator tree through the `children()` iterator.
-/// - An ordering of blocks according to a dominator tree pre-order.
-/// - Constant time dominance checks at the block granularity.
-///
-/// The information in this auxiliary data structure is not easy to update when the control flow
-/// graph changes, which is why it is kept separate.
-pub struct DominatorTreePreorder {
-    nodes: SecondaryMap<Block, ExtraNode>,
-
-    // Scratch memory used by `compute_postorder()`.
-    stack: Vec<Block>,
-}
-
-#[derive(Default, Clone)]
-struct ExtraNode {
-    /// First child node in the domtree.
-    child: PackedOption<Block>,
-
-    /// Next sibling node in the domtree. This linked list is ordered according to the CFG RPO.
-    sibling: PackedOption<Block>,
-
-    /// Sequence number for this node in a pre-order traversal of the dominator tree.
-    /// Unreachable blocks have number 0, the entry block is 1.
-    pre_number: u32,
-
-    /// Maximum `pre_number` for the sub-tree of the dominator tree that is rooted at this node.
-    /// This is always >= `pre_number`.
-    pre_max: u32,
-}
-
-/// Creating and computing the dominator tree pre-order.
-impl DominatorTreePreorder {
-    /// Create a new blank `DominatorTreePreorder`.
-    pub fn new() -> Self {
-        Self {
-            nodes: SecondaryMap::new(),
-            stack: Vec::new(),
-        }
-    }
-
-    /// Recompute this data structure to match `domtree`.
-    pub fn compute(&mut self, domtree: &DominatorTree, layout: &Layout) {
-        self.nodes.clear();
-        debug_assert_eq!(self.stack.len(), 0);
-
-        // Step 1: Populate the child and sibling links.
-        //
-        // By following the CFG post-order and pushing to the front of the lists, we make sure that
-        // sibling lists are ordered according to the CFG reverse post-order.
-        for &block in domtree.cfg_postorder() {
-            if let Some(idom_inst) = domtree.idom(block) {
-                let idom = layout.pp_block(idom_inst);
-                let sib = mem::replace(&mut self.nodes[idom].child, block.into());
-                self.nodes[block].sibling = sib;
-            } else {
-                // The only block without an immediate dominator is the entry.
-                self.stack.push(block);
-            }
-        }
-
-        // Step 2. Assign pre-order numbers from a DFS of the dominator tree.
-        debug_assert!(self.stack.len() <= 1);
-        let mut n = 0;
-        while let Some(block) = self.stack.pop() {
-            n += 1;
-            let node = &mut self.nodes[block];
-            node.pre_number = n;
-            node.pre_max = n;
-            if let Some(n) = node.sibling.expand() {
-                self.stack.push(n);
-            }
-            if let Some(n) = node.child.expand() {
-                self.stack.push(n);
-            }
-        }
-
-        // Step 3. Propagate the `pre_max` numbers up the tree.
-        // The CFG post-order is topologically ordered w.r.t. dominance so a node comes after all
-        // its dominator tree children.
-        for &block in domtree.cfg_postorder() {
-            if let Some(idom_inst) = domtree.idom(block) {
-                let idom = layout.pp_block(idom_inst);
-                let pre_max = cmp::max(self.nodes[block].pre_max, self.nodes[idom].pre_max);
-                self.nodes[idom].pre_max = pre_max;
-            }
-        }
-    }
-}
-
-/// An iterator that enumerates the direct children of a block in the dominator tree.
-pub struct ChildIter<'a> {
-    dtpo: &'a DominatorTreePreorder,
-    next: PackedOption<Block>,
-}
-
-impl<'a> Iterator for ChildIter<'a> {
-    type Item = Block;
-
-    fn next(&mut self) -> Option<Block> {
-        let n = self.next.expand();
-        if let Some(block) = n {
-            self.next = self.dtpo.nodes[block].sibling;
-        }
-        n
-    }
-}
-
-/// Query interface for the dominator tree pre-order.
-impl DominatorTreePreorder {
-    /// Get an iterator over the direct children of `block` in the dominator tree.
-    ///
-    /// These are the block's whose immediate dominator is an instruction in `block`, ordered according
-    /// to the CFG reverse post-order.
-    pub fn children(&self, block: Block) -> ChildIter {
-        ChildIter {
-            dtpo: self,
-            next: self.nodes[block].child,
-        }
-    }
-
-    /// Fast, constant time dominance check with block granularity.
-    ///
-    /// This computes the same result as `domtree.dominates(a, b)`, but in guaranteed fast constant
-    /// time. This is less general than the `DominatorTree` method because it only works with block
-    /// program points.
-    ///
-    /// A block is considered to dominate itself.
-    pub fn dominates(&self, a: Block, b: Block) -> bool {
-        let na = &self.nodes[a];
-        let nb = &self.nodes[b];
-        na.pre_number <= nb.pre_number && na.pre_max >= nb.pre_max
-    }
-
-    /// Compare two blocks according to the dominator pre-order.
-    pub fn pre_cmp_block(&self, a: Block, b: Block) -> Ordering {
-        self.nodes[a].pre_number.cmp(&self.nodes[b].pre_number)
-    }
-
-    /// Compare two program points according to the dominator tree pre-order.
-    ///
-    /// This ordering of program points have the property that given a program point, pp, all the
-    /// program points dominated by pp follow immediately and contiguously after pp in the order.
-    pub fn pre_cmp<A, B>(&self, a: A, b: B, layout: &Layout) -> Ordering
-    where
-        A: Into<ExpandedProgramPoint>,
-        B: Into<ExpandedProgramPoint>,
-    {
-        let a = a.into();
-        let b = b.into();
-        self.pre_cmp_block(layout.pp_block(a), layout.pp_block(b))
-            .then(layout.cmp(a, b))
-    }
-
-    /// Compare two value defs according to the dominator tree pre-order.
-    ///
-    /// Two values defined at the same program point are compared according to their parameter or
-    /// result order.
-    ///
-    /// This is a total ordering of the values in the function.
-    pub fn pre_cmp_def(&self, a: Value, b: Value, func: &Function) -> Ordering {
-        let da = func.dfg.value_def(a);
-        let db = func.dfg.value_def(b);
-        self.pre_cmp(da, db, &func.layout)
-            .then_with(|| da.num().cmp(&db.num()))
-    }
-}
-
-#[cfg(test)]
-mod tests {
-    use super::*;
-    use crate::cursor::{Cursor, FuncCursor};
-    use crate::flowgraph::ControlFlowGraph;
-    use crate::ir::types::*;
-    use crate::ir::{Function, InstBuilder, TrapCode};
-
-    #[test]
-    fn empty() {
-        let func = Function::new();
-        let cfg = ControlFlowGraph::with_function(&func);
-        debug_assert!(cfg.is_valid());
-        let dtree = DominatorTree::with_function(&func, &cfg);
-        assert_eq!(0, dtree.nodes.keys().count());
-        assert_eq!(dtree.cfg_postorder(), &[]);
-
-        let mut dtpo = DominatorTreePreorder::new();
-        dtpo.compute(&dtree, &func.layout);
-    }
-
-    #[test]
-    fn unreachable_node() {
-        let mut func = Function::new();
-        let block0 = func.dfg.make_block();
-        let v0 = func.dfg.append_block_param(block0, I32);
-        let block1 = func.dfg.make_block();
-        let block2 = func.dfg.make_block();
-
-        let mut cur = FuncCursor::new(&mut func);
-
-        cur.insert_block(block0);
-        cur.ins().brnz(v0, block2, &[]);
-        cur.ins().trap(TrapCode::User(0));
-
-        cur.insert_block(block1);
-        let v1 = cur.ins().iconst(I32, 1);
-        let v2 = cur.ins().iadd(v0, v1);
-        cur.ins().jump(block0, &[v2]);
-
-        cur.insert_block(block2);
-        cur.ins().return_(&[v0]);
-
-        let cfg = ControlFlowGraph::with_function(cur.func);
-        let dt = DominatorTree::with_function(cur.func, &cfg);
-
-        // Fall-through-first, prune-at-source DFT:
-        //
-        // block0 {
-        //   brnz block2 {
-        //     trap
-        //     block2 {
-        //       return
-        //     } block2
-        // } block0
-        assert_eq!(dt.cfg_postorder(), &[block2, block0]);
-
-        let v2_def = cur.func.dfg.value_def(v2).unwrap_inst();
-        assert!(!dt.dominates(v2_def, block0, &cur.func.layout));
-        assert!(!dt.dominates(block0, v2_def, &cur.func.layout));
-
-        let mut dtpo = DominatorTreePreorder::new();
-        dtpo.compute(&dt, &cur.func.layout);
-        assert!(dtpo.dominates(block0, block0));
-        assert!(!dtpo.dominates(block0, block1));
-        assert!(dtpo.dominates(block0, block2));
-        assert!(!dtpo.dominates(block1, block0));
-        assert!(dtpo.dominates(block1, block1));
-        assert!(!dtpo.dominates(block1, block2));
-        assert!(!dtpo.dominates(block2, block0));
-        assert!(!dtpo.dominates(block2, block1));
-        assert!(dtpo.dominates(block2, block2));
-    }
-
-    #[test]
-    fn non_zero_entry_block() {
-        let mut func = Function::new();
-        let block0 = func.dfg.make_block();
-        let block1 = func.dfg.make_block();
-        let block2 = func.dfg.make_block();
-        let block3 = func.dfg.make_block();
-        let cond = func.dfg.append_block_param(block3, I32);
-
-        let mut cur = FuncCursor::new(&mut func);
-
-        cur.insert_block(block3);
-        let jmp_block3_block1 = cur.ins().jump(block1, &[]);
-
-        cur.insert_block(block1);
-        let br_block1_block0 = cur.ins().brnz(cond, block0, &[]);
-        let jmp_block1_block2 = cur.ins().jump(block2, &[]);
-
-        cur.insert_block(block2);
-        cur.ins().jump(block0, &[]);
-
-        cur.insert_block(block0);
-
-        let cfg = ControlFlowGraph::with_function(cur.func);
-        let dt = DominatorTree::with_function(cur.func, &cfg);
-
-        // Fall-through-first, prune-at-source DFT:
-        //
-        // block3 {
-        //   block3:jump block1 {
-        //     block1 {
-        //       block1:brnz block0 {
-        //         block1:jump block2 {
-        //           block2 {
-        //             block2:jump block0 (seen)
-        //           } block2
-        //         } block1:jump block2
-        //         block0 {
-        //         } block0
-        //       } block1:brnz block0
-        //     } block1
-        //   } block3:jump block1
-        // } block3
-
-        assert_eq!(dt.cfg_postorder(), &[block2, block0, block1, block3]);
-
-        assert_eq!(cur.func.layout.entry_block().unwrap(), block3);
-        assert_eq!(dt.idom(block3), None);
-        assert_eq!(dt.idom(block1).unwrap(), jmp_block3_block1);
-        assert_eq!(dt.idom(block2).unwrap(), jmp_block1_block2);
-        assert_eq!(dt.idom(block0).unwrap(), br_block1_block0);
-
-        assert!(dt.dominates(br_block1_block0, br_block1_block0, &cur.func.layout));
-        assert!(!dt.dominates(br_block1_block0, jmp_block3_block1, &cur.func.layout));
-        assert!(dt.dominates(jmp_block3_block1, br_block1_block0, &cur.func.layout));
-
-        assert_eq!(
-            dt.rpo_cmp(block3, block3, &cur.func.layout),
-            Ordering::Equal
-        );
-        assert_eq!(dt.rpo_cmp(block3, block1, &cur.func.layout), Ordering::Less);
-        assert_eq!(
-            dt.rpo_cmp(block3, jmp_block3_block1, &cur.func.layout),
-            Ordering::Less
-        );
-        assert_eq!(
-            dt.rpo_cmp(jmp_block3_block1, jmp_block1_block2, &cur.func.layout),
-            Ordering::Less
-        );
-    }
-
-    #[test]
-    fn backwards_layout() {
-        let mut func = Function::new();
-        let block0 = func.dfg.make_block();
-        let block1 = func.dfg.make_block();
-        let block2 = func.dfg.make_block();
-
-        let mut cur = FuncCursor::new(&mut func);
-
-        cur.insert_block(block0);
-        let jmp02 = cur.ins().jump(block2, &[]);
-
-        cur.insert_block(block1);
-        let trap = cur.ins().trap(TrapCode::User(5));
-
-        cur.insert_block(block2);
-        let jmp21 = cur.ins().jump(block1, &[]);
-
-        let cfg = ControlFlowGraph::with_function(cur.func);
-        let dt = DominatorTree::with_function(cur.func, &cfg);
-
-        assert_eq!(cur.func.layout.entry_block(), Some(block0));
-        assert_eq!(dt.idom(block0), None);
-        assert_eq!(dt.idom(block1), Some(jmp21));
-        assert_eq!(dt.idom(block2), Some(jmp02));
-
-        assert!(dt.dominates(block0, block0, &cur.func.layout));
-        assert!(dt.dominates(block0, jmp02, &cur.func.layout));
-        assert!(dt.dominates(block0, block1, &cur.func.layout));
-        assert!(dt.dominates(block0, trap, &cur.func.layout));
-        assert!(dt.dominates(block0, block2, &cur.func.layout));
-        assert!(dt.dominates(block0, jmp21, &cur.func.layout));
-
-        assert!(!dt.dominates(jmp02, block0, &cur.func.layout));
-        assert!(dt.dominates(jmp02, jmp02, &cur.func.layout));
-        assert!(dt.dominates(jmp02, block1, &cur.func.layout));
-        assert!(dt.dominates(jmp02, trap, &cur.func.layout));
-        assert!(dt.dominates(jmp02, block2, &cur.func.layout));
-        assert!(dt.dominates(jmp02, jmp21, &cur.func.layout));
-
-        assert!(!dt.dominates(block1, block0, &cur.func.layout));
-        assert!(!dt.dominates(block1, jmp02, &cur.func.layout));
-        assert!(dt.dominates(block1, block1, &cur.func.layout));
-        assert!(dt.dominates(block1, trap, &cur.func.layout));
-        assert!(!dt.dominates(block1, block2, &cur.func.layout));
-        assert!(!dt.dominates(block1, jmp21, &cur.func.layout));
-
-        assert!(!dt.dominates(trap, block0, &cur.func.layout));
-        assert!(!dt.dominates(trap, jmp02, &cur.func.layout));
-        assert!(!dt.dominates(trap, block1, &cur.func.layout));
-        assert!(dt.dominates(trap, trap, &cur.func.layout));
-        assert!(!dt.dominates(trap, block2, &cur.func.layout));
-        assert!(!dt.dominates(trap, jmp21, &cur.func.layout));
-
-        assert!(!dt.dominates(block2, block0, &cur.func.layout));
-        assert!(!dt.dominates(block2, jmp02, &cur.func.layout));
-        assert!(dt.dominates(block2, block1, &cur.func.layout));
-        assert!(dt.dominates(block2, trap, &cur.func.layout));
-        assert!(dt.dominates(block2, block2, &cur.func.layout));
-        assert!(dt.dominates(block2, jmp21, &cur.func.layout));
-
-        assert!(!dt.dominates(jmp21, block0, &cur.func.layout));
-        assert!(!dt.dominates(jmp21, jmp02, &cur.func.layout));
-        assert!(dt.dominates(jmp21, block1, &cur.func.layout));
-        assert!(dt.dominates(jmp21, trap, &cur.func.layout));
-        assert!(!dt.dominates(jmp21, block2, &cur.func.layout));
-        assert!(dt.dominates(jmp21, jmp21, &cur.func.layout));
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/flowgraph.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/flowgraph.rs
deleted file mode 100644
index 9c6ccbaea..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/flowgraph.rs
+++ /dev/null
@@ -1,350 +0,0 @@
-//! A control flow graph represented as mappings of basic blocks to their predecessors
-//! and successors.
-//!
-//! Successors are represented as basic blocks while predecessors are represented by basic
-//! blocks. Basic blocks are denoted by tuples of block and branch/jump instructions. Each
-//! predecessor tuple corresponds to the end of a basic block.
-//!
-//! ```c
-//!     Block0:
-//!         ...          ; beginning of basic block
-//!
-//!         ...
-//!
-//!         brz vx, Block1 ; end of basic block
-//!
-//!         ...          ; beginning of basic block
-//!
-//!         ...
-//!
-//!         jmp Block2     ; end of basic block
-//! ```
-//!
-//! Here `Block1` and `Block2` would each have a single predecessor denoted as `(Block0, brz)`
-//! and `(Block0, jmp Block2)` respectively.
-
-use crate::bforest;
-use crate::entity::SecondaryMap;
-use crate::ir::instructions::BranchInfo;
-use crate::ir::{Block, Function, Inst};
-use crate::timing;
-use core::mem;
-
-/// A basic block denoted by its enclosing Block and last instruction.
-#[derive(Debug, PartialEq, Eq)]
-pub struct BlockPredecessor {
-    /// Enclosing Block key.
-    pub block: Block,
-    /// Last instruction in the basic block.
-    pub inst: Inst,
-}
-
-impl BlockPredecessor {
-    /// Convenient method to construct new BlockPredecessor.
-    pub fn new(block: Block, inst: Inst) -> Self {
-        Self { block, inst }
-    }
-}
-
-/// A container for the successors and predecessors of some Block.
-#[derive(Clone, Default)]
-struct CFGNode {
-    /// Instructions that can branch or jump to this block.
-    ///
-    /// This maps branch instruction -> predecessor block which is redundant since the block containing
-    /// the branch instruction is available from the `layout.inst_block()` method. We store the
-    /// redundant information because:
-    ///
-    /// 1. Many `pred_iter()` consumers want the block anyway, so it is handily available.
-    /// 2. The `invalidate_block_successors()` may be called *after* branches have been removed from
-    ///    their block, but we still need to remove them form the old block predecessor map.
-    ///
-    /// The redundant block stored here is always consistent with the CFG successor lists, even after
-    /// the IR has been edited.
-    pub predecessors: bforest::Map<Inst, Block>,
-
-    /// Set of blocks that are the targets of branches and jumps in this block.
-    /// The set is ordered by block number, indicated by the `()` comparator type.
-    pub successors: bforest::Set<Block>,
-}
-
-/// The Control Flow Graph maintains a mapping of blocks to their predecessors
-/// and successors where predecessors are basic blocks and successors are
-/// basic blocks.
-pub struct ControlFlowGraph {
-    data: SecondaryMap<Block, CFGNode>,
-    pred_forest: bforest::MapForest<Inst, Block>,
-    succ_forest: bforest::SetForest<Block>,
-    valid: bool,
-}
-
-impl ControlFlowGraph {
-    /// Allocate a new blank control flow graph.
-    pub fn new() -> Self {
-        Self {
-            data: SecondaryMap::new(),
-            valid: false,
-            pred_forest: bforest::MapForest::new(),
-            succ_forest: bforest::SetForest::new(),
-        }
-    }
-
-    /// Clear all data structures in this control flow graph.
-    pub fn clear(&mut self) {
-        self.data.clear();
-        self.pred_forest.clear();
-        self.succ_forest.clear();
-        self.valid = false;
-    }
-
-    /// Allocate and compute the control flow graph for `func`.
-    pub fn with_function(func: &Function) -> Self {
-        let mut cfg = Self::new();
-        cfg.compute(func);
-        cfg
-    }
-
-    /// Compute the control flow graph of `func`.
-    ///
-    /// This will clear and overwrite any information already stored in this data structure.
-    pub fn compute(&mut self, func: &Function) {
-        let _tt = timing::flowgraph();
-        self.clear();
-        self.data.resize(func.dfg.num_blocks());
-
-        for block in &func.layout {
-            self.compute_block(func, block);
-        }
-
-        self.valid = true;
-    }
-
-    fn compute_block(&mut self, func: &Function, block: Block) {
-        for inst in func.layout.block_likely_branches(block) {
-            match func.dfg.analyze_branch(inst) {
-                BranchInfo::SingleDest(dest, _) => {
-                    self.add_edge(block, inst, dest);
-                }
-                BranchInfo::Table(jt, dest) => {
-                    if let Some(dest) = dest {
-                        self.add_edge(block, inst, dest);
-                    }
-                    for dest in func.jump_tables[jt].iter() {
-                        self.add_edge(block, inst, *dest);
-                    }
-                }
-                BranchInfo::NotABranch => {}
-            }
-        }
-    }
-
-    fn invalidate_block_successors(&mut self, block: Block) {
-        // Temporarily take ownership because we need mutable access to self.data inside the loop.
-        // Unfortunately borrowck cannot see that our mut accesses to predecessors don't alias
-        // our iteration over successors.
-        let mut successors = mem::replace(&mut self.data[block].successors, Default::default());
-        for succ in successors.iter(&self.succ_forest) {
-            self.data[succ]
-                .predecessors
-                .retain(&mut self.pred_forest, |_, &mut e| e != block);
-        }
-        successors.clear(&mut self.succ_forest);
-    }
-
-    /// Recompute the control flow graph of `block`.
-    ///
-    /// This is for use after modifying instructions within a specific block. It recomputes all edges
-    /// from `block` while leaving edges to `block` intact. Its functionality a subset of that of the
-    /// more expensive `compute`, and should be used when we know we don't need to recompute the CFG
-    /// from scratch, but rather that our changes have been restricted to specific blocks.
-    pub fn recompute_block(&mut self, func: &Function, block: Block) {
-        debug_assert!(self.is_valid());
-        self.invalidate_block_successors(block);
-        self.compute_block(func, block);
-    }
-
-    fn add_edge(&mut self, from: Block, from_inst: Inst, to: Block) {
-        self.data[from]
-            .successors
-            .insert(to, &mut self.succ_forest, &());
-        self.data[to]
-            .predecessors
-            .insert(from_inst, from, &mut self.pred_forest, &());
-    }
-
-    /// Get an iterator over the CFG predecessors to `block`.
-    pub fn pred_iter(&self, block: Block) -> PredIter {
-        PredIter(self.data[block].predecessors.iter(&self.pred_forest))
-    }
-
-    /// Get an iterator over the CFG successors to `block`.
-    pub fn succ_iter(&self, block: Block) -> SuccIter {
-        debug_assert!(self.is_valid());
-        self.data[block].successors.iter(&self.succ_forest)
-    }
-
-    /// Check if the CFG is in a valid state.
-    ///
-    /// Note that this doesn't perform any kind of validity checks. It simply checks if the
-    /// `compute()` method has been called since the last `clear()`. It does not check that the
-    /// CFG is consistent with the function.
-    pub fn is_valid(&self) -> bool {
-        self.valid
-    }
-}
-
-/// An iterator over block predecessors. The iterator type is `BlockPredecessor`.
-///
-/// Each predecessor is an instruction that branches to the block.
-pub struct PredIter<'a>(bforest::MapIter<'a, Inst, Block>);
-
-impl<'a> Iterator for PredIter<'a> {
-    type Item = BlockPredecessor;
-
-    fn next(&mut self) -> Option<BlockPredecessor> {
-        self.0.next().map(|(i, e)| BlockPredecessor::new(e, i))
-    }
-}
-
-/// An iterator over block successors. The iterator type is `Block`.
-pub type SuccIter<'a> = bforest::SetIter<'a, Block>;
-
-#[cfg(test)]
-mod tests {
-    use super::*;
-    use crate::cursor::{Cursor, FuncCursor};
-    use crate::ir::{types, Function, InstBuilder};
-    use alloc::vec::Vec;
-
-    #[test]
-    fn empty() {
-        let func = Function::new();
-        ControlFlowGraph::with_function(&func);
-    }
-
-    #[test]
-    fn no_predecessors() {
-        let mut func = Function::new();
-        let block0 = func.dfg.make_block();
-        let block1 = func.dfg.make_block();
-        let block2 = func.dfg.make_block();
-        func.layout.append_block(block0);
-        func.layout.append_block(block1);
-        func.layout.append_block(block2);
-
-        let cfg = ControlFlowGraph::with_function(&func);
-
-        let mut fun_blocks = func.layout.blocks();
-        for block in func.layout.blocks() {
-            assert_eq!(block, fun_blocks.next().unwrap());
-            assert_eq!(cfg.pred_iter(block).count(), 0);
-            assert_eq!(cfg.succ_iter(block).count(), 0);
-        }
-    }
-
-    #[test]
-    fn branches_and_jumps() {
-        let mut func = Function::new();
-        let block0 = func.dfg.make_block();
-        let cond = func.dfg.append_block_param(block0, types::I32);
-        let block1 = func.dfg.make_block();
-        let block2 = func.dfg.make_block();
-
-        let br_block0_block2;
-        let br_block1_block1;
-        let jmp_block0_block1;
-        let jmp_block1_block2;
-
-        {
-            let mut cur = FuncCursor::new(&mut func);
-
-            cur.insert_block(block0);
-            br_block0_block2 = cur.ins().brnz(cond, block2, &[]);
-            jmp_block0_block1 = cur.ins().jump(block1, &[]);
-
-            cur.insert_block(block1);
-            br_block1_block1 = cur.ins().brnz(cond, block1, &[]);
-            jmp_block1_block2 = cur.ins().jump(block2, &[]);
-
-            cur.insert_block(block2);
-        }
-
-        let mut cfg = ControlFlowGraph::with_function(&func);
-
-        {
-            let block0_predecessors = cfg.pred_iter(block0).collect::<Vec<_>>();
-            let block1_predecessors = cfg.pred_iter(block1).collect::<Vec<_>>();
-            let block2_predecessors = cfg.pred_iter(block2).collect::<Vec<_>>();
-
-            let block0_successors = cfg.succ_iter(block0).collect::<Vec<_>>();
-            let block1_successors = cfg.succ_iter(block1).collect::<Vec<_>>();
-            let block2_successors = cfg.succ_iter(block2).collect::<Vec<_>>();
-
-            assert_eq!(block0_predecessors.len(), 0);
-            assert_eq!(block1_predecessors.len(), 2);
-            assert_eq!(block2_predecessors.len(), 2);
-
-            assert_eq!(
-                block1_predecessors.contains(&BlockPredecessor::new(block0, jmp_block0_block1)),
-                true
-            );
-            assert_eq!(
-                block1_predecessors.contains(&BlockPredecessor::new(block1, br_block1_block1)),
-                true
-            );
-            assert_eq!(
-                block2_predecessors.contains(&BlockPredecessor::new(block0, br_block0_block2)),
-                true
-            );
-            assert_eq!(
-                block2_predecessors.contains(&BlockPredecessor::new(block1, jmp_block1_block2)),
-                true
-            );
-
-            assert_eq!(block0_successors, [block1, block2]);
-            assert_eq!(block1_successors, [block1, block2]);
-            assert_eq!(block2_successors, []);
-        }
-
-        // Change some instructions and recompute block0
-        func.dfg.replace(br_block0_block2).brnz(cond, block1, &[]);
-        func.dfg.replace(jmp_block0_block1).return_(&[]);
-        cfg.recompute_block(&mut func, block0);
-        let br_block0_block1 = br_block0_block2;
-
-        {
-            let block0_predecessors = cfg.pred_iter(block0).collect::<Vec<_>>();
-            let block1_predecessors = cfg.pred_iter(block1).collect::<Vec<_>>();
-            let block2_predecessors = cfg.pred_iter(block2).collect::<Vec<_>>();
-
-            let block0_successors = cfg.succ_iter(block0);
-            let block1_successors = cfg.succ_iter(block1);
-            let block2_successors = cfg.succ_iter(block2);
-
-            assert_eq!(block0_predecessors.len(), 0);
-            assert_eq!(block1_predecessors.len(), 2);
-            assert_eq!(block2_predecessors.len(), 1);
-
-            assert_eq!(
-                block1_predecessors.contains(&BlockPredecessor::new(block0, br_block0_block1)),
-                true
-            );
-            assert_eq!(
-                block1_predecessors.contains(&BlockPredecessor::new(block1, br_block1_block1)),
-                true
-            );
-            assert_eq!(
-                block2_predecessors.contains(&BlockPredecessor::new(block0, br_block0_block2)),
-                false
-            );
-            assert_eq!(
-                block2_predecessors.contains(&BlockPredecessor::new(block1, jmp_block1_block2)),
-                true
-            );
-
-            assert_eq!(block0_successors.collect::<Vec<_>>(), [block1]);
-            assert_eq!(block1_successors.collect::<Vec<_>>(), [block1, block2]);
-            assert_eq!(block2_successors.collect::<Vec<_>>(), []);
-        }
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/fx.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/fx.rs
deleted file mode 100644
index 36eb62df9..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/fx.rs
+++ /dev/null
@@ -1,111 +0,0 @@
-// This file is taken from the Rust compiler: src/librustc_data_structures/fx.rs
-
-// Copyright 2015 The Rust Project Developers. See the COPYRIGHT
-// file at the top-level directory of this distribution and at
-// http://rust-lang.org/COPYRIGHT.
-//
-// Licensed under the Apache License, Version 2.0 <LICENSE-APACHE or
-// http://www.apache.org/licenses/LICENSE-2.0> or the MIT license
-// <LICENSE-MIT or http://opensource.org/licenses/MIT>, at your
-// option. This file may not be copied, modified, or distributed
-// except according to those terms.
-
-use super::{HashMap, HashSet};
-use core::default::Default;
-use core::hash::{BuildHasherDefault, Hash, Hasher};
-use core::ops::BitXor;
-
-pub type FxHashMap<K, V> = HashMap<K, V, BuildHasherDefault<FxHasher>>;
-pub type FxHashSet<V> = HashSet<V, BuildHasherDefault<FxHasher>>;
-
-#[allow(non_snake_case)]
-pub fn FxHashMap<K: Hash + Eq, V>() -> FxHashMap<K, V> {
-    HashMap::default()
-}
-
-#[allow(non_snake_case)]
-pub fn FxHashSet<V: Hash + Eq>() -> FxHashSet<V> {
-    HashSet::default()
-}
-
-/// A speedy hash algorithm for use within rustc. The hashmap in liballoc
-/// by default uses SipHash which isn't quite as speedy as we want. In the
-/// compiler we're not really worried about DOS attempts, so we use a fast
-/// non-cryptographic hash.
-///
-/// This is the same as the algorithm used by Firefox -- which is a homespun
-/// one not based on any widely-known algorithm -- though modified to produce
-/// 64-bit hash values instead of 32-bit hash values. It consistently
-/// out-performs an FNV-based hash within rustc itself -- the collision rate is
-/// similar or slightly worse than FNV, but the speed of the hash function
-/// itself is much higher because it works on up to 8 bytes at a time.
-pub struct FxHasher {
-    hash: usize,
-}
-
-#[cfg(target_pointer_width = "32")]
-const K: usize = 0x9e3779b9;
-#[cfg(target_pointer_width = "64")]
-const K: usize = 0x517cc1b727220a95;
-
-impl Default for FxHasher {
-    #[inline]
-    fn default() -> Self {
-        Self { hash: 0 }
-    }
-}
-
-impl FxHasher {
-    #[inline]
-    fn add_to_hash(&mut self, i: usize) {
-        self.hash = self.hash.rotate_left(5).bitxor(i).wrapping_mul(K);
-    }
-}
-
-impl Hasher for FxHasher {
-    #[inline]
-    fn write(&mut self, bytes: &[u8]) {
-        for byte in bytes {
-            let i = *byte;
-            self.add_to_hash(i as usize);
-        }
-    }
-
-    #[inline]
-    fn write_u8(&mut self, i: u8) {
-        self.add_to_hash(i as usize);
-    }
-
-    #[inline]
-    fn write_u16(&mut self, i: u16) {
-        self.add_to_hash(i as usize);
-    }
-
-    #[inline]
-    fn write_u32(&mut self, i: u32) {
-        self.add_to_hash(i as usize);
-    }
-
-    #[cfg(target_pointer_width = "32")]
-    #[inline]
-    fn write_u64(&mut self, i: u64) {
-        self.add_to_hash(i as usize);
-        self.add_to_hash((i >> 32) as usize);
-    }
-
-    #[cfg(target_pointer_width = "64")]
-    #[inline]
-    fn write_u64(&mut self, i: u64) {
-        self.add_to_hash(i as usize);
-    }
-
-    #[inline]
-    fn write_usize(&mut self, i: usize) {
-        self.add_to_hash(i);
-    }
-
-    #[inline]
-    fn finish(&self) -> u64 {
-        self.hash as u64
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/inst_predicates.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/inst_predicates.rs
deleted file mode 100644
index 518487af2..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/inst_predicates.rs
+++ /dev/null
@@ -1,80 +0,0 @@
-//! Instruction predicates/properties, shared by various analyses.
-
-use crate::ir::{DataFlowGraph, Function, Inst, InstructionData, Opcode};
-use crate::machinst::ty_bits;
-use cranelift_entity::EntityRef;
-
-/// Preserve instructions with used result values.
-pub fn any_inst_results_used(inst: Inst, live: &[bool], dfg: &DataFlowGraph) -> bool {
-    dfg.inst_results(inst).iter().any(|v| live[v.index()])
-}
-
-/// Test whether the given opcode is unsafe to even consider as side-effect-free.
-fn trivially_has_side_effects(opcode: Opcode) -> bool {
-    opcode.is_call()
-        || opcode.is_branch()
-        || opcode.is_terminator()
-        || opcode.is_return()
-        || opcode.can_trap()
-        || opcode.other_side_effects()
-        || opcode.can_store()
-}
-
-/// Load instructions without the `notrap` flag are defined to trap when
-/// operating on inaccessible memory, so we can't treat them as side-effect-free even if the loaded
-/// value is unused.
-fn is_load_with_defined_trapping(opcode: Opcode, data: &InstructionData) -> bool {
-    if !opcode.can_load() {
-        return false;
-    }
-    match *data {
-        InstructionData::StackLoad { .. } => false,
-        InstructionData::Load { flags, .. } => !flags.notrap(),
-        _ => true,
-    }
-}
-
-/// Does the given instruction have any side-effect that would preclude it from being removed when
-/// its value is unused?
-pub fn has_side_effect(func: &Function, inst: Inst) -> bool {
-    let data = &func.dfg[inst];
-    let opcode = data.opcode();
-    trivially_has_side_effects(opcode) || is_load_with_defined_trapping(opcode, data)
-}
-
-/// Does the given instruction have any side-effect as per [has_side_effect], or else is a load,
-/// but not the get_pinned_reg opcode?
-pub fn has_lowering_side_effect(func: &Function, inst: Inst) -> bool {
-    let op = func.dfg[inst].opcode();
-    op != Opcode::GetPinnedReg && (has_side_effect(func, inst) || op.can_load())
-}
-
-/// Is the given instruction a constant value (`iconst`, `fconst`, `bconst`) that can be
-/// represented in 64 bits?
-pub fn is_constant_64bit(func: &Function, inst: Inst) -> Option<u64> {
-    let data = &func.dfg[inst];
-    if data.opcode() == Opcode::Null {
-        return Some(0);
-    }
-    match data {
-        &InstructionData::UnaryImm { imm, .. } => Some(imm.bits() as u64),
-        &InstructionData::UnaryIeee32 { imm, .. } => Some(imm.bits() as u64),
-        &InstructionData::UnaryIeee64 { imm, .. } => Some(imm.bits()),
-        &InstructionData::UnaryBool { imm, .. } => {
-            let imm = if imm {
-                let bits = ty_bits(func.dfg.value_type(func.dfg.inst_results(inst)[0]));
-
-                if bits < 64 {
-                    (1u64 << bits) - 1
-                } else {
-                    u64::MAX
-                }
-            } else {
-                0
-            };
-
-            Some(imm)
-        }
-        _ => None,
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/atomic_rmw_op.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/atomic_rmw_op.rs
deleted file mode 100644
index e9873e55d..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/atomic_rmw_op.rs
+++ /dev/null
@@ -1,72 +0,0 @@
-/// Describes the arithmetic operation in an atomic memory read-modify-write operation.
-use core::fmt::{self, Display, Formatter};
-use core::str::FromStr;
-#[cfg(feature = "enable-serde")]
-use serde::{Deserialize, Serialize};
-
-#[derive(Clone, Copy, PartialEq, Eq, Debug, Hash)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-/// Describes the arithmetic operation in an atomic memory read-modify-write operation.
-pub enum AtomicRmwOp {
-    /// Add
-    Add,
-    /// Sub
-    Sub,
-    /// And
-    And,
-    /// Nand
-    Nand,
-    /// Or
-    Or,
-    /// Xor
-    Xor,
-    /// Exchange
-    Xchg,
-    /// Unsigned min
-    Umin,
-    /// Unsigned max
-    Umax,
-    /// Signed min
-    Smin,
-    /// Signed max
-    Smax,
-}
-
-impl Display for AtomicRmwOp {
-    fn fmt(&self, f: &mut Formatter) -> fmt::Result {
-        let s = match self {
-            AtomicRmwOp::Add => "add",
-            AtomicRmwOp::Sub => "sub",
-            AtomicRmwOp::And => "and",
-            AtomicRmwOp::Nand => "nand",
-            AtomicRmwOp::Or => "or",
-            AtomicRmwOp::Xor => "xor",
-            AtomicRmwOp::Xchg => "xchg",
-            AtomicRmwOp::Umin => "umin",
-            AtomicRmwOp::Umax => "umax",
-            AtomicRmwOp::Smin => "smin",
-            AtomicRmwOp::Smax => "smax",
-        };
-        f.write_str(s)
-    }
-}
-
-impl FromStr for AtomicRmwOp {
-    type Err = ();
-    fn from_str(s: &str) -> Result<Self, Self::Err> {
-        match s {
-            "add" => Ok(AtomicRmwOp::Add),
-            "sub" => Ok(AtomicRmwOp::Sub),
-            "and" => Ok(AtomicRmwOp::And),
-            "nand" => Ok(AtomicRmwOp::Nand),
-            "or" => Ok(AtomicRmwOp::Or),
-            "xor" => Ok(AtomicRmwOp::Xor),
-            "xchg" => Ok(AtomicRmwOp::Xchg),
-            "umin" => Ok(AtomicRmwOp::Umin),
-            "umax" => Ok(AtomicRmwOp::Umax),
-            "smin" => Ok(AtomicRmwOp::Smin),
-            "smax" => Ok(AtomicRmwOp::Smax),
-            _ => Err(()),
-        }
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/builder.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/builder.rs
deleted file mode 100644
index 3191f9dae..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/builder.rs
+++ /dev/null
@@ -1,265 +0,0 @@
-//! Cranelift instruction builder.
-//!
-//! A `Builder` provides a convenient interface for inserting instructions into a Cranelift
-//! function. Many of its methods are generated from the meta language instruction definitions.
-
-use crate::ir;
-use crate::ir::types;
-use crate::ir::{DataFlowGraph, InstructionData};
-use crate::ir::{Inst, Opcode, Type, Value};
-
-/// Base trait for instruction builders.
-///
-/// The `InstBuilderBase` trait provides the basic functionality required by the methods of the
-/// generated `InstBuilder` trait. These methods should not normally be used directly. Use the
-/// methods in the `InstBuilder` trait instead.
-///
-/// Any data type that implements `InstBuilderBase` also gets all the methods of the `InstBuilder`
-/// trait.
-pub trait InstBuilderBase<'f>: Sized {
-    /// Get an immutable reference to the data flow graph that will hold the constructed
-    /// instructions.
-    fn data_flow_graph(&self) -> &DataFlowGraph;
-    /// Get a mutable reference to the data flow graph that will hold the constructed
-    /// instructions.
-    fn data_flow_graph_mut(&mut self) -> &mut DataFlowGraph;
-
-    /// Insert an instruction and return a reference to it, consuming the builder.
-    ///
-    /// The result types may depend on a controlling type variable. For non-polymorphic
-    /// instructions with multiple results, pass `INVALID` for the `ctrl_typevar` argument.
-    fn build(self, data: InstructionData, ctrl_typevar: Type) -> (Inst, &'f mut DataFlowGraph);
-}
-
-// Include trait code generated by `cranelift-codegen/meta/src/gen_inst.rs`.
-//
-// This file defines the `InstBuilder` trait as an extension of `InstBuilderBase` with methods per
-// instruction format and per opcode.
-include!(concat!(env!("OUT_DIR"), "/inst_builder.rs"));
-
-/// Any type implementing `InstBuilderBase` gets all the `InstBuilder` methods for free.
-impl<'f, T: InstBuilderBase<'f>> InstBuilder<'f> for T {}
-
-/// Base trait for instruction inserters.
-///
-/// This is an alternative base trait for an instruction builder to implement.
-///
-/// An instruction inserter can be adapted into an instruction builder by wrapping it in an
-/// `InsertBuilder`. This provides some common functionality for instruction builders that insert
-/// new instructions, as opposed to the `ReplaceBuilder` which overwrites existing instructions.
-pub trait InstInserterBase<'f>: Sized {
-    /// Get an immutable reference to the data flow graph.
-    fn data_flow_graph(&self) -> &DataFlowGraph;
-
-    /// Get a mutable reference to the data flow graph.
-    fn data_flow_graph_mut(&mut self) -> &mut DataFlowGraph;
-
-    /// Insert a new instruction which belongs to the DFG.
-    fn insert_built_inst(self, inst: Inst) -> &'f mut DataFlowGraph;
-}
-
-use core::marker::PhantomData;
-
-/// Builder that inserts an instruction at the current position.
-///
-/// An `InsertBuilder` is a wrapper for an `InstInserterBase` that turns it into an instruction
-/// builder with some additional facilities for creating instructions that reuse existing values as
-/// their results.
-pub struct InsertBuilder<'f, IIB: InstInserterBase<'f>> {
-    inserter: IIB,
-    unused: PhantomData<&'f u32>,
-}
-
-impl<'f, IIB: InstInserterBase<'f>> InsertBuilder<'f, IIB> {
-    /// Create a new builder which inserts instructions at `pos`.
-    /// The `dfg` and `pos.layout` references should be from the same `Function`.
-    pub fn new(inserter: IIB) -> Self {
-        Self {
-            inserter,
-            unused: PhantomData,
-        }
-    }
-
-    /// Reuse result values in `reuse`.
-    ///
-    /// Convert this builder into one that will reuse the provided result values instead of
-    /// allocating new ones. The provided values for reuse must not be attached to anything. Any
-    /// missing result values will be allocated as normal.
-    ///
-    /// The `reuse` argument is expected to be an array of `Option<Value>`.
-    pub fn with_results<Array>(self, reuse: Array) -> InsertReuseBuilder<'f, IIB, Array>
-    where
-        Array: AsRef<[Option<Value>]>,
-    {
-        InsertReuseBuilder {
-            inserter: self.inserter,
-            reuse,
-            unused: PhantomData,
-        }
-    }
-
-    /// Reuse a single result value.
-    ///
-    /// Convert this into a builder that will reuse `v` as the single result value. The reused
-    /// result value `v` must not be attached to anything.
-    ///
-    /// This method should only be used when building an instruction with exactly one result. Use
-    /// `with_results()` for the more general case.
-    pub fn with_result(self, v: Value) -> InsertReuseBuilder<'f, IIB, [Option<Value>; 1]> {
-        // TODO: Specialize this to return a different builder that just attaches `v` instead of
-        // calling `make_inst_results_reusing()`.
-        self.with_results([Some(v)])
-    }
-}
-
-impl<'f, IIB: InstInserterBase<'f>> InstBuilderBase<'f> for InsertBuilder<'f, IIB> {
-    fn data_flow_graph(&self) -> &DataFlowGraph {
-        self.inserter.data_flow_graph()
-    }
-
-    fn data_flow_graph_mut(&mut self) -> &mut DataFlowGraph {
-        self.inserter.data_flow_graph_mut()
-    }
-
-    fn build(mut self, data: InstructionData, ctrl_typevar: Type) -> (Inst, &'f mut DataFlowGraph) {
-        let inst;
-        {
-            let dfg = self.inserter.data_flow_graph_mut();
-            inst = dfg.make_inst(data);
-            dfg.make_inst_results(inst, ctrl_typevar);
-        }
-        (inst, self.inserter.insert_built_inst(inst))
-    }
-}
-
-/// Builder that inserts a new instruction like `InsertBuilder`, but reusing result values.
-pub struct InsertReuseBuilder<'f, IIB, Array>
-where
-    IIB: InstInserterBase<'f>,
-    Array: AsRef<[Option<Value>]>,
-{
-    inserter: IIB,
-    reuse: Array,
-    unused: PhantomData<&'f u32>,
-}
-
-impl<'f, IIB, Array> InstBuilderBase<'f> for InsertReuseBuilder<'f, IIB, Array>
-where
-    IIB: InstInserterBase<'f>,
-    Array: AsRef<[Option<Value>]>,
-{
-    fn data_flow_graph(&self) -> &DataFlowGraph {
-        self.inserter.data_flow_graph()
-    }
-
-    fn data_flow_graph_mut(&mut self) -> &mut DataFlowGraph {
-        self.inserter.data_flow_graph_mut()
-    }
-
-    fn build(mut self, data: InstructionData, ctrl_typevar: Type) -> (Inst, &'f mut DataFlowGraph) {
-        let inst;
-        {
-            let dfg = self.inserter.data_flow_graph_mut();
-            inst = dfg.make_inst(data);
-            // Make an `Iterator<Item = Option<Value>>`.
-            let ru = self.reuse.as_ref().iter().cloned();
-            dfg.make_inst_results_reusing(inst, ctrl_typevar, ru);
-        }
-        (inst, self.inserter.insert_built_inst(inst))
-    }
-}
-
-/// Instruction builder that replaces an existing instruction.
-///
-/// The inserted instruction will have the same `Inst` number as the old one.
-///
-/// If the old instruction still has result values attached, it is assumed that the new instruction
-/// produces the same number and types of results. The old result values are preserved. If the
-/// replacement instruction format does not support multiple results, the builder panics. It is a
-/// bug to leave result values dangling.
-pub struct ReplaceBuilder<'f> {
-    dfg: &'f mut DataFlowGraph,
-    inst: Inst,
-}
-
-impl<'f> ReplaceBuilder<'f> {
-    /// Create a `ReplaceBuilder` that will overwrite `inst`.
-    pub fn new(dfg: &'f mut DataFlowGraph, inst: Inst) -> Self {
-        Self { dfg, inst }
-    }
-}
-
-impl<'f> InstBuilderBase<'f> for ReplaceBuilder<'f> {
-    fn data_flow_graph(&self) -> &DataFlowGraph {
-        self.dfg
-    }
-
-    fn data_flow_graph_mut(&mut self) -> &mut DataFlowGraph {
-        self.dfg
-    }
-
-    fn build(self, data: InstructionData, ctrl_typevar: Type) -> (Inst, &'f mut DataFlowGraph) {
-        // Splat the new instruction on top of the old one.
-        self.dfg[self.inst] = data;
-
-        if !self.dfg.has_results(self.inst) {
-            // The old result values were either detached or non-existent.
-            // Construct new ones.
-            self.dfg.make_inst_results(self.inst, ctrl_typevar);
-        }
-
-        (self.inst, self.dfg)
-    }
-}
-
-#[cfg(test)]
-mod tests {
-    use crate::cursor::{Cursor, FuncCursor};
-    use crate::ir::condcodes::*;
-    use crate::ir::types::*;
-    use crate::ir::{Function, InstBuilder, ValueDef};
-
-    #[test]
-    fn types() {
-        let mut func = Function::new();
-        let block0 = func.dfg.make_block();
-        let arg0 = func.dfg.append_block_param(block0, I32);
-        let mut pos = FuncCursor::new(&mut func);
-        pos.insert_block(block0);
-
-        // Explicit types.
-        let v0 = pos.ins().iconst(I32, 3);
-        assert_eq!(pos.func.dfg.value_type(v0), I32);
-
-        // Inferred from inputs.
-        let v1 = pos.ins().iadd(arg0, v0);
-        assert_eq!(pos.func.dfg.value_type(v1), I32);
-
-        // Formula.
-        let cmp = pos.ins().icmp(IntCC::Equal, arg0, v0);
-        assert_eq!(pos.func.dfg.value_type(cmp), B1);
-    }
-
-    #[test]
-    fn reuse_results() {
-        let mut func = Function::new();
-        let block0 = func.dfg.make_block();
-        let arg0 = func.dfg.append_block_param(block0, I32);
-        let mut pos = FuncCursor::new(&mut func);
-        pos.insert_block(block0);
-
-        let v0 = pos.ins().iadd_imm(arg0, 17);
-        assert_eq!(pos.func.dfg.value_type(v0), I32);
-        let iadd = pos.prev_inst().unwrap();
-        assert_eq!(pos.func.dfg.value_def(v0), ValueDef::Result(iadd, 0));
-
-        // Detach v0 and reuse it for a different instruction.
-        pos.func.dfg.clear_results(iadd);
-        let v0b = pos.ins().with_result(v0).iconst(I32, 3);
-        assert_eq!(v0, v0b);
-        assert_eq!(pos.current_inst(), Some(iadd));
-        let iconst = pos.prev_inst().unwrap();
-        assert!(iadd != iconst);
-        assert_eq!(pos.func.dfg.value_def(v0), ValueDef::Result(iconst, 0));
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/condcodes.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/condcodes.rs
deleted file mode 100644
index 00e9717ca..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/condcodes.rs
+++ /dev/null
@@ -1,410 +0,0 @@
-//! Condition codes for the Cranelift code generator.
-//!
-//! A condition code here is an enumerated type that determined how to compare two numbers. There
-//! are different rules for comparing integers and floating point numbers, so they use different
-//! condition codes.
-
-use core::fmt::{self, Display, Formatter};
-use core::str::FromStr;
-
-#[cfg(feature = "enable-serde")]
-use serde::{Deserialize, Serialize};
-
-/// Common traits of condition codes.
-pub trait CondCode: Copy {
-    /// Get the inverse condition code of `self`.
-    ///
-    /// The inverse condition code produces the opposite result for all comparisons.
-    /// That is, `cmp CC, x, y` is true if and only if `cmp CC.inverse(), x, y` is false.
-    #[must_use]
-    fn inverse(self) -> Self;
-
-    /// Get the reversed condition code for `self`.
-    ///
-    /// The reversed condition code produces the same result as swapping `x` and `y` in the
-    /// comparison. That is, `cmp CC, x, y` is the same as `cmp CC.reverse(), y, x`.
-    #[must_use]
-    fn reverse(self) -> Self;
-}
-
-/// Condition code for comparing integers.
-///
-/// This condition code is used by the `icmp` instruction to compare integer values. There are
-/// separate codes for comparing the integers as signed or unsigned numbers where it makes a
-/// difference.
-#[derive(Clone, Copy, PartialEq, Eq, Debug, Hash)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub enum IntCC {
-    /// `==`.
-    Equal,
-    /// `!=`.
-    NotEqual,
-    /// Signed `<`.
-    SignedLessThan,
-    /// Signed `>=`.
-    SignedGreaterThanOrEqual,
-    /// Signed `>`.
-    SignedGreaterThan,
-    /// Signed `<=`.
-    SignedLessThanOrEqual,
-    /// Unsigned `<`.
-    UnsignedLessThan,
-    /// Unsigned `>=`.
-    UnsignedGreaterThanOrEqual,
-    /// Unsigned `>`.
-    UnsignedGreaterThan,
-    /// Unsigned `<=`.
-    UnsignedLessThanOrEqual,
-    /// Signed Overflow.
-    Overflow,
-    /// Signed No Overflow.
-    NotOverflow,
-}
-
-impl CondCode for IntCC {
-    fn inverse(self) -> Self {
-        use self::IntCC::*;
-        match self {
-            Equal => NotEqual,
-            NotEqual => Equal,
-            SignedLessThan => SignedGreaterThanOrEqual,
-            SignedGreaterThanOrEqual => SignedLessThan,
-            SignedGreaterThan => SignedLessThanOrEqual,
-            SignedLessThanOrEqual => SignedGreaterThan,
-            UnsignedLessThan => UnsignedGreaterThanOrEqual,
-            UnsignedGreaterThanOrEqual => UnsignedLessThan,
-            UnsignedGreaterThan => UnsignedLessThanOrEqual,
-            UnsignedLessThanOrEqual => UnsignedGreaterThan,
-            Overflow => NotOverflow,
-            NotOverflow => Overflow,
-        }
-    }
-
-    fn reverse(self) -> Self {
-        use self::IntCC::*;
-        match self {
-            Equal => Equal,
-            NotEqual => NotEqual,
-            SignedGreaterThan => SignedLessThan,
-            SignedGreaterThanOrEqual => SignedLessThanOrEqual,
-            SignedLessThan => SignedGreaterThan,
-            SignedLessThanOrEqual => SignedGreaterThanOrEqual,
-            UnsignedGreaterThan => UnsignedLessThan,
-            UnsignedGreaterThanOrEqual => UnsignedLessThanOrEqual,
-            UnsignedLessThan => UnsignedGreaterThan,
-            UnsignedLessThanOrEqual => UnsignedGreaterThanOrEqual,
-            Overflow => Overflow,
-            NotOverflow => NotOverflow,
-        }
-    }
-}
-
-impl IntCC {
-    /// Get the corresponding IntCC with the equal component removed.
-    /// For conditions without a zero component, this is a no-op.
-    pub fn without_equal(self) -> Self {
-        use self::IntCC::*;
-        match self {
-            SignedGreaterThan | SignedGreaterThanOrEqual => SignedGreaterThan,
-            SignedLessThan | SignedLessThanOrEqual => SignedLessThan,
-            UnsignedGreaterThan | UnsignedGreaterThanOrEqual => UnsignedGreaterThan,
-            UnsignedLessThan | UnsignedLessThanOrEqual => UnsignedLessThan,
-            _ => self,
-        }
-    }
-
-    /// Get the corresponding IntCC with the signed component removed.
-    /// For conditions without a signed component, this is a no-op.
-    pub fn unsigned(self) -> Self {
-        use self::IntCC::*;
-        match self {
-            SignedGreaterThan | UnsignedGreaterThan => UnsignedGreaterThan,
-            SignedGreaterThanOrEqual | UnsignedGreaterThanOrEqual => UnsignedGreaterThanOrEqual,
-            SignedLessThan | UnsignedLessThan => UnsignedLessThan,
-            SignedLessThanOrEqual | UnsignedLessThanOrEqual => UnsignedLessThanOrEqual,
-            _ => self,
-        }
-    }
-
-    /// Get the corresponding string condition code for the IntCC object.
-    pub fn to_static_str(self) -> &'static str {
-        use self::IntCC::*;
-        match self {
-            Equal => "eq",
-            NotEqual => "ne",
-            SignedGreaterThan => "sgt",
-            SignedGreaterThanOrEqual => "sge",
-            SignedLessThan => "slt",
-            SignedLessThanOrEqual => "sle",
-            UnsignedGreaterThan => "ugt",
-            UnsignedGreaterThanOrEqual => "uge",
-            UnsignedLessThan => "ult",
-            UnsignedLessThanOrEqual => "ule",
-            Overflow => "of",
-            NotOverflow => "nof",
-        }
-    }
-}
-
-impl Display for IntCC {
-    fn fmt(&self, f: &mut Formatter) -> fmt::Result {
-        f.write_str(self.to_static_str())
-    }
-}
-
-impl FromStr for IntCC {
-    type Err = ();
-
-    fn from_str(s: &str) -> Result<Self, Self::Err> {
-        use self::IntCC::*;
-        match s {
-            "eq" => Ok(Equal),
-            "ne" => Ok(NotEqual),
-            "sge" => Ok(SignedGreaterThanOrEqual),
-            "sgt" => Ok(SignedGreaterThan),
-            "sle" => Ok(SignedLessThanOrEqual),
-            "slt" => Ok(SignedLessThan),
-            "uge" => Ok(UnsignedGreaterThanOrEqual),
-            "ugt" => Ok(UnsignedGreaterThan),
-            "ule" => Ok(UnsignedLessThanOrEqual),
-            "ult" => Ok(UnsignedLessThan),
-            "of" => Ok(Overflow),
-            "nof" => Ok(NotOverflow),
-            _ => Err(()),
-        }
-    }
-}
-
-/// Condition code for comparing floating point numbers.
-///
-/// This condition code is used by the `fcmp` instruction to compare floating point values. Two
-/// IEEE floating point values relate in exactly one of four ways:
-///
-/// 1. `UN` - unordered when either value is NaN.
-/// 2. `EQ` - equal numerical value.
-/// 3. `LT` - `x` is less than `y`.
-/// 4. `GT` - `x` is greater than `y`.
-///
-/// Note that `0.0` and `-0.0` relate as `EQ` because they both represent the number 0.
-///
-/// The condition codes described here are used to produce a single boolean value from the
-/// comparison. The 14 condition codes here cover every possible combination of the relation above
-/// except the impossible `!UN & !EQ & !LT & !GT` and the always true `UN | EQ | LT | GT`.
-#[derive(Clone, Copy, PartialEq, Eq, Debug, Hash)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub enum FloatCC {
-    /// EQ | LT | GT
-    Ordered,
-    /// UN
-    Unordered,
-
-    /// EQ
-    Equal,
-    /// The C '!=' operator is the inverse of '==': `NotEqual`.
-    /// UN | LT | GT
-    NotEqual,
-    /// LT | GT
-    OrderedNotEqual,
-    /// UN | EQ
-    UnorderedOrEqual,
-
-    /// LT
-    LessThan,
-    /// LT | EQ
-    LessThanOrEqual,
-    /// GT
-    GreaterThan,
-    /// GT | EQ
-    GreaterThanOrEqual,
-
-    /// UN | LT
-    UnorderedOrLessThan,
-    /// UN | LT | EQ
-    UnorderedOrLessThanOrEqual,
-    /// UN | GT
-    UnorderedOrGreaterThan,
-    /// UN | GT | EQ
-    UnorderedOrGreaterThanOrEqual,
-}
-
-impl CondCode for FloatCC {
-    fn inverse(self) -> Self {
-        use self::FloatCC::*;
-        match self {
-            Ordered => Unordered,
-            Unordered => Ordered,
-            Equal => NotEqual,
-            NotEqual => Equal,
-            OrderedNotEqual => UnorderedOrEqual,
-            UnorderedOrEqual => OrderedNotEqual,
-            LessThan => UnorderedOrGreaterThanOrEqual,
-            LessThanOrEqual => UnorderedOrGreaterThan,
-            GreaterThan => UnorderedOrLessThanOrEqual,
-            GreaterThanOrEqual => UnorderedOrLessThan,
-            UnorderedOrLessThan => GreaterThanOrEqual,
-            UnorderedOrLessThanOrEqual => GreaterThan,
-            UnorderedOrGreaterThan => LessThanOrEqual,
-            UnorderedOrGreaterThanOrEqual => LessThan,
-        }
-    }
-    fn reverse(self) -> Self {
-        use self::FloatCC::*;
-        match self {
-            Ordered => Ordered,
-            Unordered => Unordered,
-            Equal => Equal,
-            NotEqual => NotEqual,
-            OrderedNotEqual => OrderedNotEqual,
-            UnorderedOrEqual => UnorderedOrEqual,
-            LessThan => GreaterThan,
-            LessThanOrEqual => GreaterThanOrEqual,
-            GreaterThan => LessThan,
-            GreaterThanOrEqual => LessThanOrEqual,
-            UnorderedOrLessThan => UnorderedOrGreaterThan,
-            UnorderedOrLessThanOrEqual => UnorderedOrGreaterThanOrEqual,
-            UnorderedOrGreaterThan => UnorderedOrLessThan,
-            UnorderedOrGreaterThanOrEqual => UnorderedOrLessThanOrEqual,
-        }
-    }
-}
-
-impl Display for FloatCC {
-    fn fmt(&self, f: &mut Formatter) -> fmt::Result {
-        use self::FloatCC::*;
-        f.write_str(match *self {
-            Ordered => "ord",
-            Unordered => "uno",
-            Equal => "eq",
-            NotEqual => "ne",
-            OrderedNotEqual => "one",
-            UnorderedOrEqual => "ueq",
-            LessThan => "lt",
-            LessThanOrEqual => "le",
-            GreaterThan => "gt",
-            GreaterThanOrEqual => "ge",
-            UnorderedOrLessThan => "ult",
-            UnorderedOrLessThanOrEqual => "ule",
-            UnorderedOrGreaterThan => "ugt",
-            UnorderedOrGreaterThanOrEqual => "uge",
-        })
-    }
-}
-
-impl FromStr for FloatCC {
-    type Err = ();
-
-    fn from_str(s: &str) -> Result<Self, Self::Err> {
-        use self::FloatCC::*;
-        match s {
-            "ord" => Ok(Ordered),
-            "uno" => Ok(Unordered),
-            "eq" => Ok(Equal),
-            "ne" => Ok(NotEqual),
-            "one" => Ok(OrderedNotEqual),
-            "ueq" => Ok(UnorderedOrEqual),
-            "lt" => Ok(LessThan),
-            "le" => Ok(LessThanOrEqual),
-            "gt" => Ok(GreaterThan),
-            "ge" => Ok(GreaterThanOrEqual),
-            "ult" => Ok(UnorderedOrLessThan),
-            "ule" => Ok(UnorderedOrLessThanOrEqual),
-            "ugt" => Ok(UnorderedOrGreaterThan),
-            "uge" => Ok(UnorderedOrGreaterThanOrEqual),
-            _ => Err(()),
-        }
-    }
-}
-
-#[cfg(test)]
-mod tests {
-    use super::*;
-    use std::string::ToString;
-
-    static INT_ALL: [IntCC; 12] = [
-        IntCC::Equal,
-        IntCC::NotEqual,
-        IntCC::SignedLessThan,
-        IntCC::SignedGreaterThanOrEqual,
-        IntCC::SignedGreaterThan,
-        IntCC::SignedLessThanOrEqual,
-        IntCC::UnsignedLessThan,
-        IntCC::UnsignedGreaterThanOrEqual,
-        IntCC::UnsignedGreaterThan,
-        IntCC::UnsignedLessThanOrEqual,
-        IntCC::Overflow,
-        IntCC::NotOverflow,
-    ];
-
-    #[test]
-    fn int_inverse() {
-        for r in &INT_ALL {
-            let cc = *r;
-            let inv = cc.inverse();
-            assert!(cc != inv);
-            assert_eq!(inv.inverse(), cc);
-        }
-    }
-
-    #[test]
-    fn int_reverse() {
-        for r in &INT_ALL {
-            let cc = *r;
-            let rev = cc.reverse();
-            assert_eq!(rev.reverse(), cc);
-        }
-    }
-
-    #[test]
-    fn int_display() {
-        for r in &INT_ALL {
-            let cc = *r;
-            assert_eq!(cc.to_string().parse(), Ok(cc));
-        }
-        assert_eq!("bogus".parse::<IntCC>(), Err(()));
-    }
-
-    static FLOAT_ALL: [FloatCC; 14] = [
-        FloatCC::Ordered,
-        FloatCC::Unordered,
-        FloatCC::Equal,
-        FloatCC::NotEqual,
-        FloatCC::OrderedNotEqual,
-        FloatCC::UnorderedOrEqual,
-        FloatCC::LessThan,
-        FloatCC::LessThanOrEqual,
-        FloatCC::GreaterThan,
-        FloatCC::GreaterThanOrEqual,
-        FloatCC::UnorderedOrLessThan,
-        FloatCC::UnorderedOrLessThanOrEqual,
-        FloatCC::UnorderedOrGreaterThan,
-        FloatCC::UnorderedOrGreaterThanOrEqual,
-    ];
-
-    #[test]
-    fn float_inverse() {
-        for r in &FLOAT_ALL {
-            let cc = *r;
-            let inv = cc.inverse();
-            assert!(cc != inv);
-            assert_eq!(inv.inverse(), cc);
-        }
-    }
-
-    #[test]
-    fn float_reverse() {
-        for r in &FLOAT_ALL {
-            let cc = *r;
-            let rev = cc.reverse();
-            assert_eq!(rev.reverse(), cc);
-        }
-    }
-
-    #[test]
-    fn float_display() {
-        for r in &FLOAT_ALL {
-            let cc = *r;
-            assert_eq!(cc.to_string().parse(), Ok(cc));
-        }
-        assert_eq!("bogus".parse::<FloatCC>(), Err(()));
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/constant.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/constant.rs
deleted file mode 100644
index 3cd88d554..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/constant.rs
+++ /dev/null
@@ -1,460 +0,0 @@
-//! Constants
-//!
-//! The constant pool defined here allows Cranelift to avoid emitting the same constant multiple
-//! times. As constants are inserted in the pool, a handle is returned; the handle is a Cranelift
-//! Entity. Inserting the same data multiple times will always return the same handle.
-//!
-//! Future work could include:
-//! - ensuring alignment of constants within the pool,
-//! - bucketing constants by size.
-
-use crate::ir::immediates::{IntoBytes, V128Imm};
-use crate::ir::Constant;
-use crate::HashMap;
-use alloc::collections::BTreeMap;
-use alloc::vec::Vec;
-use core::fmt;
-use core::iter::FromIterator;
-use core::slice::Iter;
-use core::str::{from_utf8, FromStr};
-use cranelift_entity::EntityRef;
-
-#[cfg(feature = "enable-serde")]
-use serde::{Deserialize, Serialize};
-
-/// This type describes the actual constant data. Note that the bytes stored in this structure are
-/// expected to be in little-endian order; this is due to ease-of-use when interacting with
-/// WebAssembly values, which are [little-endian by design].
-///
-/// [little-endian by design]: https://github.com/WebAssembly/design/blob/master/Portability.md
-#[derive(Clone, Hash, Eq, PartialEq, Debug, Default)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub struct ConstantData(Vec<u8>);
-
-impl FromIterator<u8> for ConstantData {
-    fn from_iter<T: IntoIterator<Item = u8>>(iter: T) -> Self {
-        let v = iter.into_iter().collect();
-        Self(v)
-    }
-}
-
-impl From<Vec<u8>> for ConstantData {
-    fn from(v: Vec<u8>) -> Self {
-        Self(v)
-    }
-}
-
-impl From<&[u8]> for ConstantData {
-    fn from(v: &[u8]) -> Self {
-        Self(v.to_vec())
-    }
-}
-
-impl From<V128Imm> for ConstantData {
-    fn from(v: V128Imm) -> Self {
-        Self(v.to_vec())
-    }
-}
-
-impl ConstantData {
-    /// Return the number of bytes in the constant.
-    pub fn len(&self) -> usize {
-        self.0.len()
-    }
-
-    /// Check if the constant contains any bytes.
-    pub fn is_empty(&self) -> bool {
-        self.0.is_empty()
-    }
-
-    /// Return the data as a slice.
-    pub fn as_slice(&self) -> &[u8] {
-        self.0.as_slice()
-    }
-
-    /// Convert the data to a vector.
-    pub fn into_vec(self) -> Vec<u8> {
-        self.0
-    }
-
-    /// Iterate over the constant's bytes.
-    pub fn iter(&self) -> Iter<u8> {
-        self.0.iter()
-    }
-
-    /// Add new bytes to the constant data.
-    pub fn append(mut self, bytes: impl IntoBytes) -> Self {
-        let mut to_add = bytes.into_bytes();
-        self.0.append(&mut to_add);
-        self
-    }
-
-    /// Expand the size of the constant data to `expected_size` number of bytes by adding zeroes
-    /// in the high-order byte slots.
-    pub fn expand_to(mut self, expected_size: usize) -> Self {
-        if self.len() > expected_size {
-            panic!(
-                "The constant data is already expanded beyond {} bytes",
-                expected_size
-            )
-        }
-        self.0.resize(expected_size, 0);
-        self
-    }
-}
-
-impl fmt::Display for ConstantData {
-    /// Print the constant data in hexadecimal format, e.g. 0x000102030405060708090a0b0c0d0e0f.
-    /// This function will flip the stored order of bytes--little-endian--to the more readable
-    /// big-endian ordering.
-    ///
-    /// ```
-    /// use cranelift_codegen::ir::ConstantData;
-    /// let data = ConstantData::from([3, 2, 1, 0, 0].as_ref()); // note the little-endian order
-    /// assert_eq!(data.to_string(), "0x0000010203");
-    /// ```
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        if !self.is_empty() {
-            write!(f, "0x")?;
-            for b in self.0.iter().rev() {
-                write!(f, "{:02x}", b)?;
-            }
-        }
-        Ok(())
-    }
-}
-
-impl FromStr for ConstantData {
-    type Err = &'static str;
-
-    /// Parse a hexadecimal string to `ConstantData`. This is the inverse of `Display::fmt`.
-    ///
-    /// ```
-    /// use cranelift_codegen::ir::ConstantData;
-    /// let c: ConstantData = "0x000102".parse().unwrap();
-    /// assert_eq!(c.into_vec(), [2, 1, 0]);
-    /// ```
-    fn from_str(s: &str) -> Result<Self, &'static str> {
-        if s.len() <= 2 || &s[0..2] != "0x" {
-            return Err("Expected a hexadecimal string, e.g. 0x1234");
-        }
-
-        // clean and check the string
-        let cleaned: Vec<u8> = s[2..]
-            .as_bytes()
-            .iter()
-            .filter(|&&b| b as char != '_')
-            .cloned()
-            .collect(); // remove 0x prefix and any intervening _ characters
-
-        if cleaned.is_empty() {
-            Err("Hexadecimal string must have some digits")
-        } else if cleaned.len() % 2 != 0 {
-            Err("Hexadecimal string must have an even number of digits")
-        } else if cleaned.len() > 32 {
-            Err("Hexadecimal string has too many digits to fit in a 128-bit vector")
-        } else {
-            let mut buffer = Vec::with_capacity((s.len() - 2) / 2);
-            for i in (0..cleaned.len()).step_by(2) {
-                let pair = from_utf8(&cleaned[i..i + 2])
-                    .or_else(|_| Err("Unable to parse hexadecimal pair as UTF-8"))?;
-                let byte = u8::from_str_radix(pair, 16)
-                    .or_else(|_| Err("Unable to parse as hexadecimal"))?;
-                buffer.insert(0, byte);
-            }
-            Ok(Self(buffer))
-        }
-    }
-}
-
-/// Maintains the mapping between a constant handle (i.e.  [`Constant`](crate::ir::Constant)) and
-/// its constant data (i.e.  [`ConstantData`](crate::ir::ConstantData)).
-#[derive(Clone)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub struct ConstantPool {
-    /// This mapping maintains the insertion order as long as Constants are created with
-    /// sequentially increasing integers.
-    handles_to_values: BTreeMap<Constant, ConstantData>,
-
-    /// This mapping is unordered (no need for lexicographic ordering) but allows us to map
-    /// constant data back to handles.
-    values_to_handles: HashMap<ConstantData, Constant>,
-}
-
-impl ConstantPool {
-    /// Create a new constant pool instance.
-    pub fn new() -> Self {
-        Self {
-            handles_to_values: BTreeMap::new(),
-            values_to_handles: HashMap::new(),
-        }
-    }
-
-    /// Empty the constant pool of all data.
-    pub fn clear(&mut self) {
-        self.handles_to_values.clear();
-        self.values_to_handles.clear();
-    }
-
-    /// Insert constant data into the pool, returning a handle for later referencing; when constant
-    /// data is inserted that is a duplicate of previous constant data, the existing handle will be
-    /// returned.
-    pub fn insert(&mut self, constant_value: ConstantData) -> Constant {
-        if self.values_to_handles.contains_key(&constant_value) {
-            *self.values_to_handles.get(&constant_value).unwrap()
-        } else {
-            let constant_handle = Constant::new(self.len());
-            self.set(constant_handle, constant_value);
-            constant_handle
-        }
-    }
-
-    /// Retrieve the constant data given a handle.
-    pub fn get(&self, constant_handle: Constant) -> &ConstantData {
-        assert!(self.handles_to_values.contains_key(&constant_handle));
-        self.handles_to_values.get(&constant_handle).unwrap()
-    }
-
-    /// Link a constant handle to its value. This does not de-duplicate data but does avoid
-    /// replacing any existing constant values. use `set` to tie a specific `const42` to its value;
-    /// use `insert` to add a value and return the next available `const` entity.
-    pub fn set(&mut self, constant_handle: Constant, constant_value: ConstantData) {
-        let replaced = self
-            .handles_to_values
-            .insert(constant_handle, constant_value.clone());
-        assert!(
-            replaced.is_none(),
-            "attempted to overwrite an existing constant {:?}: {:?} => {:?}",
-            constant_handle,
-            &constant_value,
-            replaced.unwrap()
-        );
-        self.values_to_handles
-            .insert(constant_value, constant_handle);
-    }
-
-    /// Iterate over the constants in insertion order.
-    pub fn iter(&self) -> impl Iterator<Item = (&Constant, &ConstantData)> {
-        self.handles_to_values.iter()
-    }
-
-    /// Iterate over mutable entries in the constant pool in insertion order.
-    pub fn entries_mut(&mut self) -> impl Iterator<Item = &mut ConstantData> {
-        self.handles_to_values.values_mut()
-    }
-
-    /// Return the number of constants in the pool.
-    pub fn len(&self) -> usize {
-        self.handles_to_values.len()
-    }
-
-    /// Return the combined size of all of the constant values in the pool.
-    pub fn byte_size(&self) -> usize {
-        self.values_to_handles.keys().map(|c| c.len()).sum()
-    }
-}
-
-#[cfg(test)]
-mod tests {
-    use super::*;
-    use std::string::ToString;
-
-    #[test]
-    fn empty() {
-        let sut = ConstantPool::new();
-        assert_eq!(sut.len(), 0);
-    }
-
-    #[test]
-    fn insert() {
-        let mut sut = ConstantPool::new();
-        sut.insert(vec![1, 2, 3].into());
-        sut.insert(vec![4, 5, 6].into());
-        assert_eq!(sut.len(), 2);
-    }
-
-    #[test]
-    fn insert_duplicate() {
-        let mut sut = ConstantPool::new();
-        let a = sut.insert(vec![1, 2, 3].into());
-        sut.insert(vec![4, 5, 6].into());
-        let b = sut.insert(vec![1, 2, 3].into());
-        assert_eq!(a, b);
-    }
-
-    #[test]
-    fn clear() {
-        let mut sut = ConstantPool::new();
-        sut.insert(vec![1, 2, 3].into());
-        assert_eq!(sut.len(), 1);
-
-        sut.clear();
-        assert_eq!(sut.len(), 0);
-    }
-
-    #[test]
-    fn iteration_order() {
-        let mut sut = ConstantPool::new();
-        sut.insert(vec![1, 2, 3].into());
-        sut.insert(vec![4, 5, 6].into());
-        sut.insert(vec![1, 2, 3].into());
-        let data = sut.iter().map(|(_, v)| v).collect::<Vec<&ConstantData>>();
-        assert_eq!(data, vec![&vec![1, 2, 3].into(), &vec![4, 5, 6].into()]);
-    }
-
-    #[test]
-    fn get() {
-        let mut sut = ConstantPool::new();
-        let data = vec![1, 2, 3];
-        let handle = sut.insert(data.clone().into());
-        assert_eq!(sut.get(handle), &data.into());
-    }
-
-    #[test]
-    fn set() {
-        let mut sut = ConstantPool::new();
-        let handle = Constant::with_number(42).unwrap();
-        let data = vec![1, 2, 3];
-        sut.set(handle, data.clone().into());
-        assert_eq!(sut.get(handle), &data.into());
-    }
-
-    #[test]
-    #[should_panic]
-    fn disallow_overwriting_constant() {
-        let mut sut = ConstantPool::new();
-        let handle = Constant::with_number(42).unwrap();
-        sut.set(handle, vec![].into());
-        sut.set(handle, vec![1].into());
-    }
-
-    #[test]
-    #[should_panic]
-    fn get_nonexistent_constant() {
-        let sut = ConstantPool::new();
-        let a = Constant::with_number(42).unwrap();
-        sut.get(a); // panics, only use constants returned by ConstantPool
-    }
-
-    #[test]
-    fn display_constant_data() {
-        assert_eq!(ConstantData::from([0].as_ref()).to_string(), "0x00");
-        assert_eq!(ConstantData::from([42].as_ref()).to_string(), "0x2a");
-        assert_eq!(
-            ConstantData::from([3, 2, 1, 0].as_ref()).to_string(),
-            "0x00010203"
-        );
-        assert_eq!(
-            ConstantData::from(3735928559u32.to_le_bytes().as_ref()).to_string(),
-            "0xdeadbeef"
-        );
-        assert_eq!(
-            ConstantData::from(0x0102030405060708u64.to_le_bytes().as_ref()).to_string(),
-            "0x0102030405060708"
-        );
-    }
-
-    #[test]
-    fn iterate_over_constant_data() {
-        let c = ConstantData::from([1, 2, 3].as_ref());
-        let mut iter = c.iter();
-        assert_eq!(iter.next(), Some(&1));
-        assert_eq!(iter.next(), Some(&2));
-        assert_eq!(iter.next(), Some(&3));
-        assert_eq!(iter.next(), None);
-    }
-
-    #[test]
-    fn add_to_constant_data() {
-        let d = ConstantData::from([1, 2].as_ref());
-        let e = d.append(i16::from(3u8));
-        assert_eq!(e.into_vec(), vec![1, 2, 3, 0])
-    }
-
-    #[test]
-    fn extend_constant_data() {
-        let d = ConstantData::from([1, 2].as_ref());
-        assert_eq!(d.expand_to(4).into_vec(), vec![1, 2, 0, 0])
-    }
-
-    #[test]
-    #[should_panic]
-    fn extend_constant_data_to_invalid_length() {
-        ConstantData::from([1, 2].as_ref()).expand_to(1);
-    }
-
-    #[test]
-    fn parse_constant_data_and_restringify() {
-        // Verify that parsing of `from` succeeds and stringifies to `to`.
-        fn parse_ok(from: &str, to: &str) {
-            let parsed = from.parse::<ConstantData>().unwrap();
-            assert_eq!(parsed.to_string(), to);
-        }
-
-        // Verify that parsing of `from` fails with `error_msg`.
-        fn parse_err(from: &str, error_msg: &str) {
-            let parsed = from.parse::<ConstantData>();
-            assert!(
-                parsed.is_err(),
-                "Expected a parse error but parsing succeeded: {}",
-                from
-            );
-            assert_eq!(parsed.err().unwrap(), error_msg);
-        }
-
-        parse_ok("0x00", "0x00");
-        parse_ok("0x00000042", "0x00000042");
-        parse_ok(
-            "0x0102030405060708090a0b0c0d0e0f00",
-            "0x0102030405060708090a0b0c0d0e0f00",
-        );
-        parse_ok("0x_0000_0043_21", "0x0000004321");
-
-        parse_err("", "Expected a hexadecimal string, e.g. 0x1234");
-        parse_err("0x", "Expected a hexadecimal string, e.g. 0x1234");
-        parse_err(
-            "0x042",
-            "Hexadecimal string must have an even number of digits",
-        );
-        parse_err(
-            "0x00000000000000000000000000000000000000000000000000",
-            "Hexadecimal string has too many digits to fit in a 128-bit vector",
-        );
-        parse_err("0xrstu", "Unable to parse as hexadecimal");
-        parse_err("0x__", "Hexadecimal string must have some digits");
-    }
-
-    #[test]
-    fn verify_stored_bytes_in_constant_data() {
-        assert_eq!("0x01".parse::<ConstantData>().unwrap().into_vec(), [1]);
-        assert_eq!(ConstantData::from([1, 0].as_ref()).0, [1, 0]);
-        assert_eq!(ConstantData::from(vec![1, 0, 0, 0]).0, [1, 0, 0, 0]);
-    }
-
-    #[test]
-    fn check_constant_data_endianness_as_uimm128() {
-        fn parse_to_uimm128(from: &str) -> Vec<u8> {
-            from.parse::<ConstantData>()
-                .unwrap()
-                .expand_to(16)
-                .into_vec()
-        }
-
-        assert_eq!(
-            parse_to_uimm128("0x42"),
-            [0x42, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
-        );
-        assert_eq!(
-            parse_to_uimm128("0x00"),
-            [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
-        );
-        assert_eq!(
-            parse_to_uimm128("0x12345678"),
-            [0x78, 0x56, 0x34, 0x12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
-        );
-        assert_eq!(
-            parse_to_uimm128("0x1234_5678"),
-            [0x78, 0x56, 0x34, 0x12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
-        );
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/dfg.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/dfg.rs
deleted file mode 100644
index 7c424e2d7..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/dfg.rs
+++ /dev/null
@@ -1,1324 +0,0 @@
-//! Data flow graph tracking Instructions, Values, and blocks.
-
-use crate::entity::{self, PrimaryMap, SecondaryMap};
-use crate::ir;
-use crate::ir::builder::ReplaceBuilder;
-use crate::ir::extfunc::ExtFuncData;
-use crate::ir::instructions::{BranchInfo, CallInfo, InstructionData};
-use crate::ir::{types, ConstantData, ConstantPool, Immediate};
-use crate::ir::{
-    Block, FuncRef, Inst, SigRef, Signature, SourceLoc, Type, Value, ValueLabelAssignments,
-    ValueList, ValueListPool,
-};
-use crate::packed_option::ReservedValue;
-use crate::write::write_operands;
-use crate::HashMap;
-use alloc::vec::Vec;
-use core::fmt;
-use core::iter;
-use core::mem;
-use core::ops::{Index, IndexMut};
-use core::u16;
-
-#[cfg(feature = "enable-serde")]
-use serde::{Deserialize, Serialize};
-
-/// A data flow graph defines all instructions and basic blocks in a function as well as
-/// the data flow dependencies between them. The DFG also tracks values which can be either
-/// instruction results or block parameters.
-///
-/// The layout of blocks in the function and of instructions in each block is recorded by the
-/// `Layout` data structure which forms the other half of the function representation.
-///
-#[derive(Clone)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub struct DataFlowGraph {
-    /// Data about all of the instructions in the function, including opcodes and operands.
-    /// The instructions in this map are not in program order. That is tracked by `Layout`, along
-    /// with the block containing each instruction.
-    insts: PrimaryMap<Inst, InstructionData>,
-
-    /// List of result values for each instruction.
-    ///
-    /// This map gets resized automatically by `make_inst()` so it is always in sync with the
-    /// primary `insts` map.
-    results: SecondaryMap<Inst, ValueList>,
-
-    /// basic blocks in the function and their parameters.
-    ///
-    /// This map is not in program order. That is handled by `Layout`, and so is the sequence of
-    /// instructions contained in each block.
-    blocks: PrimaryMap<Block, BlockData>,
-
-    /// Memory pool of value lists.
-    ///
-    /// The `ValueList` references into this pool appear in many places:
-    ///
-    /// - Instructions in `insts` that don't have room for their entire argument list inline.
-    /// - Instruction result values in `results`.
-    /// - block parameters in `blocks`.
-    pub value_lists: ValueListPool,
-
-    /// Primary value table with entries for all values.
-    values: PrimaryMap<Value, ValueData>,
-
-    /// Function signature table. These signatures are referenced by indirect call instructions as
-    /// well as the external function references.
-    pub signatures: PrimaryMap<SigRef, Signature>,
-
-    /// The pre-legalization signature for each entry in `signatures`, if any.
-    pub old_signatures: SecondaryMap<SigRef, Option<Signature>>,
-
-    /// External function references. These are functions that can be called directly.
-    pub ext_funcs: PrimaryMap<FuncRef, ExtFuncData>,
-
-    /// Saves Value labels.
-    pub values_labels: Option<HashMap<Value, ValueLabelAssignments>>,
-
-    /// Constants used within the function
-    pub constants: ConstantPool,
-
-    /// Stores large immediates that otherwise will not fit on InstructionData
-    pub immediates: PrimaryMap<Immediate, ConstantData>,
-}
-
-impl DataFlowGraph {
-    /// Create a new empty `DataFlowGraph`.
-    pub fn new() -> Self {
-        Self {
-            insts: PrimaryMap::new(),
-            results: SecondaryMap::new(),
-            blocks: PrimaryMap::new(),
-            value_lists: ValueListPool::new(),
-            values: PrimaryMap::new(),
-            signatures: PrimaryMap::new(),
-            old_signatures: SecondaryMap::new(),
-            ext_funcs: PrimaryMap::new(),
-            values_labels: None,
-            constants: ConstantPool::new(),
-            immediates: PrimaryMap::new(),
-        }
-    }
-
-    /// Clear everything.
-    pub fn clear(&mut self) {
-        self.insts.clear();
-        self.results.clear();
-        self.blocks.clear();
-        self.value_lists.clear();
-        self.values.clear();
-        self.signatures.clear();
-        self.old_signatures.clear();
-        self.ext_funcs.clear();
-        self.values_labels = None;
-        self.constants.clear();
-        self.immediates.clear();
-    }
-
-    /// Get the total number of instructions created in this function, whether they are currently
-    /// inserted in the layout or not.
-    ///
-    /// This is intended for use with `SecondaryMap::with_capacity`.
-    pub fn num_insts(&self) -> usize {
-        self.insts.len()
-    }
-
-    /// Returns `true` if the given instruction reference is valid.
-    pub fn inst_is_valid(&self, inst: Inst) -> bool {
-        self.insts.is_valid(inst)
-    }
-
-    /// Get the total number of basic blocks created in this function, whether they are
-    /// currently inserted in the layout or not.
-    ///
-    /// This is intended for use with `SecondaryMap::with_capacity`.
-    pub fn num_blocks(&self) -> usize {
-        self.blocks.len()
-    }
-
-    /// Returns `true` if the given block reference is valid.
-    pub fn block_is_valid(&self, block: Block) -> bool {
-        self.blocks.is_valid(block)
-    }
-
-    /// Get the total number of values.
-    pub fn num_values(&self) -> usize {
-        self.values.len()
-    }
-
-    /// Starts collection of debug information.
-    pub fn collect_debug_info(&mut self) {
-        if self.values_labels.is_none() {
-            self.values_labels = Some(HashMap::new());
-        }
-    }
-
-    /// Inserts a `ValueLabelAssignments::Alias` for `to_alias` if debug info
-    /// collection is enabled.
-    pub fn add_value_label_alias(&mut self, to_alias: Value, from: SourceLoc, value: Value) {
-        if let Some(values_labels) = self.values_labels.as_mut() {
-            values_labels.insert(to_alias, ir::ValueLabelAssignments::Alias { from, value });
-        }
-    }
-}
-
-/// Resolve value aliases.
-///
-/// Find the original SSA value that `value` aliases, or None if an
-/// alias cycle is detected.
-fn maybe_resolve_aliases(values: &PrimaryMap<Value, ValueData>, value: Value) -> Option<Value> {
-    let mut v = value;
-
-    // Note that values may be empty here.
-    for _ in 0..=values.len() {
-        if let ValueData::Alias { original, .. } = values[v] {
-            v = original;
-        } else {
-            return Some(v);
-        }
-    }
-
-    None
-}
-
-/// Resolve value aliases.
-///
-/// Find the original SSA value that `value` aliases.
-fn resolve_aliases(values: &PrimaryMap<Value, ValueData>, value: Value) -> Value {
-    if let Some(v) = maybe_resolve_aliases(values, value) {
-        v
-    } else {
-        panic!("Value alias loop detected for {}", value);
-    }
-}
-
-/// Iterator over all Values in a DFG
-pub struct Values<'a> {
-    inner: entity::Iter<'a, Value, ValueData>,
-}
-
-/// Check for non-values
-fn valid_valuedata(data: &ValueData) -> bool {
-    if let ValueData::Alias {
-        ty: types::INVALID,
-        original,
-    } = *data
-    {
-        if original == Value::reserved_value() {
-            return false;
-        }
-    }
-    true
-}
-
-impl<'a> Iterator for Values<'a> {
-    type Item = Value;
-
-    fn next(&mut self) -> Option<Self::Item> {
-        self.inner
-            .by_ref()
-            .find(|kv| valid_valuedata(kv.1))
-            .map(|kv| kv.0)
-    }
-}
-
-/// Handling values.
-///
-/// Values are either block parameters or instruction results.
-impl DataFlowGraph {
-    /// Allocate an extended value entry.
-    fn make_value(&mut self, data: ValueData) -> Value {
-        self.values.push(data)
-    }
-
-    /// Get an iterator over all values.
-    pub fn values<'a>(&'a self) -> Values {
-        Values {
-            inner: self.values.iter(),
-        }
-    }
-
-    /// Check if a value reference is valid.
-    pub fn value_is_valid(&self, v: Value) -> bool {
-        self.values.is_valid(v)
-    }
-
-    /// Get the type of a value.
-    pub fn value_type(&self, v: Value) -> Type {
-        self.values[v].ty()
-    }
-
-    /// Get the definition of a value.
-    ///
-    /// This is either the instruction that defined it or the Block that has the value as an
-    /// parameter.
-    pub fn value_def(&self, v: Value) -> ValueDef {
-        match self.values[v] {
-            ValueData::Inst { inst, num, .. } => ValueDef::Result(inst, num as usize),
-            ValueData::Param { block, num, .. } => ValueDef::Param(block, num as usize),
-            ValueData::Alias { original, .. } => {
-                // Make sure we only recurse one level. `resolve_aliases` has safeguards to
-                // detect alias loops without overrunning the stack.
-                self.value_def(self.resolve_aliases(original))
-            }
-        }
-    }
-
-    /// Determine if `v` is an attached instruction result / block parameter.
-    ///
-    /// An attached value can't be attached to something else without first being detached.
-    ///
-    /// Value aliases are not considered to be attached to anything. Use `resolve_aliases()` to
-    /// determine if the original aliased value is attached.
-    pub fn value_is_attached(&self, v: Value) -> bool {
-        use self::ValueData::*;
-        match self.values[v] {
-            Inst { inst, num, .. } => Some(&v) == self.inst_results(inst).get(num as usize),
-            Param { block, num, .. } => Some(&v) == self.block_params(block).get(num as usize),
-            Alias { .. } => false,
-        }
-    }
-
-    /// Resolve value aliases.
-    ///
-    /// Find the original SSA value that `value` aliases.
-    pub fn resolve_aliases(&self, value: Value) -> Value {
-        resolve_aliases(&self.values, value)
-    }
-
-    /// Resolve all aliases among inst's arguments.
-    ///
-    /// For each argument of inst which is defined by an alias, replace the
-    /// alias with the aliased value.
-    pub fn resolve_aliases_in_arguments(&mut self, inst: Inst) {
-        for arg in self.insts[inst].arguments_mut(&mut self.value_lists) {
-            let resolved = resolve_aliases(&self.values, *arg);
-            if resolved != *arg {
-                *arg = resolved;
-            }
-        }
-    }
-
-    /// Turn a value into an alias of another.
-    ///
-    /// Change the `dest` value to behave as an alias of `src`. This means that all uses of `dest`
-    /// will behave as if they used that value `src`.
-    ///
-    /// The `dest` value can't be attached to an instruction or block.
-    pub fn change_to_alias(&mut self, dest: Value, src: Value) {
-        debug_assert!(!self.value_is_attached(dest));
-        // Try to create short alias chains by finding the original source value.
-        // This also avoids the creation of loops.
-        let original = self.resolve_aliases(src);
-        debug_assert_ne!(
-            dest, original,
-            "Aliasing {} to {} would create a loop",
-            dest, src
-        );
-        let ty = self.value_type(original);
-        debug_assert_eq!(
-            self.value_type(dest),
-            ty,
-            "Aliasing {} to {} would change its type {} to {}",
-            dest,
-            src,
-            self.value_type(dest),
-            ty
-        );
-        debug_assert_ne!(ty, types::INVALID);
-
-        self.values[dest] = ValueData::Alias { ty, original };
-    }
-
-    /// Replace the results of one instruction with aliases to the results of another.
-    ///
-    /// Change all the results of `dest_inst` to behave as aliases of
-    /// corresponding results of `src_inst`, as if calling change_to_alias for
-    /// each.
-    ///
-    /// After calling this instruction, `dest_inst` will have had its results
-    /// cleared, so it likely needs to be removed from the graph.
-    ///
-    pub fn replace_with_aliases(&mut self, dest_inst: Inst, src_inst: Inst) {
-        debug_assert_ne!(
-            dest_inst, src_inst,
-            "Replacing {} with itself would create a loop",
-            dest_inst
-        );
-        debug_assert_eq!(
-            self.results[dest_inst].len(&self.value_lists),
-            self.results[src_inst].len(&self.value_lists),
-            "Replacing {} with {} would produce a different number of results.",
-            dest_inst,
-            src_inst
-        );
-
-        for (&dest, &src) in self.results[dest_inst]
-            .as_slice(&self.value_lists)
-            .iter()
-            .zip(self.results[src_inst].as_slice(&self.value_lists))
-        {
-            let original = src;
-            let ty = self.value_type(original);
-            debug_assert_eq!(
-                self.value_type(dest),
-                ty,
-                "Aliasing {} to {} would change its type {} to {}",
-                dest,
-                src,
-                self.value_type(dest),
-                ty
-            );
-            debug_assert_ne!(ty, types::INVALID);
-
-            self.values[dest] = ValueData::Alias { ty, original };
-        }
-
-        self.clear_results(dest_inst);
-    }
-}
-
-/// Where did a value come from?
-#[derive(Clone, Copy, Debug, PartialEq, Eq)]
-pub enum ValueDef {
-    /// Value is the n'th result of an instruction.
-    Result(Inst, usize),
-    /// Value is the n'th parameter to a block.
-    Param(Block, usize),
-}
-
-impl ValueDef {
-    /// Unwrap the instruction where the value was defined, or panic.
-    pub fn unwrap_inst(&self) -> Inst {
-        self.inst().expect("Value is not an instruction result")
-    }
-
-    /// Get the instruction where the value was defined, if any.
-    pub fn inst(&self) -> Option<Inst> {
-        match *self {
-            Self::Result(inst, _) => Some(inst),
-            _ => None,
-        }
-    }
-
-    /// Unwrap the block there the parameter is defined, or panic.
-    pub fn unwrap_block(&self) -> Block {
-        match *self {
-            Self::Param(block, _) => block,
-            _ => panic!("Value is not a block parameter"),
-        }
-    }
-
-    /// Get the program point where the value was defined.
-    pub fn pp(self) -> ir::ExpandedProgramPoint {
-        self.into()
-    }
-
-    /// Get the number component of this definition.
-    ///
-    /// When multiple values are defined at the same program point, this indicates the index of
-    /// this value.
-    pub fn num(self) -> usize {
-        match self {
-            Self::Result(_, n) | Self::Param(_, n) => n,
-        }
-    }
-}
-
-/// Internal table storage for extended values.
-#[derive(Clone, Debug)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-enum ValueData {
-    /// Value is defined by an instruction.
-    Inst { ty: Type, num: u16, inst: Inst },
-
-    /// Value is a block parameter.
-    Param { ty: Type, num: u16, block: Block },
-
-    /// Value is an alias of another value.
-    /// An alias value can't be linked as an instruction result or block parameter. It is used as a
-    /// placeholder when the original instruction or block has been rewritten or modified.
-    Alias { ty: Type, original: Value },
-}
-
-impl ValueData {
-    fn ty(&self) -> Type {
-        match *self {
-            ValueData::Inst { ty, .. }
-            | ValueData::Param { ty, .. }
-            | ValueData::Alias { ty, .. } => ty,
-        }
-    }
-}
-
-/// Instructions.
-///
-impl DataFlowGraph {
-    /// Create a new instruction.
-    ///
-    /// The type of the first result is indicated by `data.ty`. If the instruction produces
-    /// multiple results, also call `make_inst_results` to allocate value table entries.
-    pub fn make_inst(&mut self, data: InstructionData) -> Inst {
-        let n = self.num_insts() + 1;
-        self.results.resize(n);
-        self.insts.push(data)
-    }
-
-    /// Returns an object that displays `inst`.
-    pub fn display_inst<'a>(&'a self, inst: Inst) -> DisplayInst<'a> {
-        DisplayInst(self, inst)
-    }
-
-    /// Get all value arguments on `inst` as a slice.
-    pub fn inst_args(&self, inst: Inst) -> &[Value] {
-        self.insts[inst].arguments(&self.value_lists)
-    }
-
-    /// Get all value arguments on `inst` as a mutable slice.
-    pub fn inst_args_mut(&mut self, inst: Inst) -> &mut [Value] {
-        self.insts[inst].arguments_mut(&mut self.value_lists)
-    }
-
-    /// Get the fixed value arguments on `inst` as a slice.
-    pub fn inst_fixed_args(&self, inst: Inst) -> &[Value] {
-        let num_fixed_args = self[inst]
-            .opcode()
-            .constraints()
-            .num_fixed_value_arguments();
-        &self.inst_args(inst)[..num_fixed_args]
-    }
-
-    /// Get the fixed value arguments on `inst` as a mutable slice.
-    pub fn inst_fixed_args_mut(&mut self, inst: Inst) -> &mut [Value] {
-        let num_fixed_args = self[inst]
-            .opcode()
-            .constraints()
-            .num_fixed_value_arguments();
-        &mut self.inst_args_mut(inst)[..num_fixed_args]
-    }
-
-    /// Get the variable value arguments on `inst` as a slice.
-    pub fn inst_variable_args(&self, inst: Inst) -> &[Value] {
-        let num_fixed_args = self[inst]
-            .opcode()
-            .constraints()
-            .num_fixed_value_arguments();
-        &self.inst_args(inst)[num_fixed_args..]
-    }
-
-    /// Get the variable value arguments on `inst` as a mutable slice.
-    pub fn inst_variable_args_mut(&mut self, inst: Inst) -> &mut [Value] {
-        let num_fixed_args = self[inst]
-            .opcode()
-            .constraints()
-            .num_fixed_value_arguments();
-        &mut self.inst_args_mut(inst)[num_fixed_args..]
-    }
-
-    /// Create result values for an instruction that produces multiple results.
-    ///
-    /// Instructions that produce no result values only need to be created with `make_inst`,
-    /// otherwise call `make_inst_results` to allocate value table entries for the results.
-    ///
-    /// The result value types are determined from the instruction's value type constraints and the
-    /// provided `ctrl_typevar` type for polymorphic instructions. For non-polymorphic
-    /// instructions, `ctrl_typevar` is ignored, and `INVALID` can be used.
-    ///
-    /// The type of the first result value is also set, even if it was already set in the
-    /// `InstructionData` passed to `make_inst`. If this function is called with a single-result
-    /// instruction, that is the only effect.
-    pub fn make_inst_results(&mut self, inst: Inst, ctrl_typevar: Type) -> usize {
-        self.make_inst_results_reusing(inst, ctrl_typevar, iter::empty())
-    }
-
-    /// Create result values for `inst`, reusing the provided detached values.
-    ///
-    /// Create a new set of result values for `inst` using `ctrl_typevar` to determine the result
-    /// types. Any values provided by `reuse` will be reused. When `reuse` is exhausted or when it
-    /// produces `None`, a new value is created.
-    pub fn make_inst_results_reusing<I>(
-        &mut self,
-        inst: Inst,
-        ctrl_typevar: Type,
-        reuse: I,
-    ) -> usize
-    where
-        I: Iterator<Item = Option<Value>>,
-    {
-        let mut reuse = reuse.fuse();
-
-        self.results[inst].clear(&mut self.value_lists);
-
-        // Get the call signature if this is a function call.
-        if let Some(sig) = self.call_signature(inst) {
-            // Create result values corresponding to the call return types.
-            debug_assert_eq!(
-                self.insts[inst].opcode().constraints().num_fixed_results(),
-                0
-            );
-            let num_results = self.signatures[sig].returns.len();
-            for res_idx in 0..num_results {
-                let ty = self.signatures[sig].returns[res_idx].value_type;
-                if let Some(Some(v)) = reuse.next() {
-                    debug_assert_eq!(self.value_type(v), ty, "Reused {} is wrong type", ty);
-                    self.attach_result(inst, v);
-                } else {
-                    self.append_result(inst, ty);
-                }
-            }
-            num_results
-        } else {
-            // Create result values corresponding to the opcode's constraints.
-            let constraints = self.insts[inst].opcode().constraints();
-            let num_results = constraints.num_fixed_results();
-            for res_idx in 0..num_results {
-                let ty = constraints.result_type(res_idx, ctrl_typevar);
-                if let Some(Some(v)) = reuse.next() {
-                    debug_assert_eq!(self.value_type(v), ty, "Reused {} is wrong type", ty);
-                    self.attach_result(inst, v);
-                } else {
-                    self.append_result(inst, ty);
-                }
-            }
-            num_results
-        }
-    }
-
-    /// Create a `ReplaceBuilder` that will replace `inst` with a new instruction in place.
-    pub fn replace(&mut self, inst: Inst) -> ReplaceBuilder {
-        ReplaceBuilder::new(self, inst)
-    }
-
-    /// Detach the list of result values from `inst` and return it.
-    ///
-    /// This leaves `inst` without any result values. New result values can be created by calling
-    /// `make_inst_results` or by using a `replace(inst)` builder.
-    pub fn detach_results(&mut self, inst: Inst) -> ValueList {
-        self.results[inst].take()
-    }
-
-    /// Clear the list of result values from `inst`.
-    ///
-    /// This leaves `inst` without any result values. New result values can be created by calling
-    /// `make_inst_results` or by using a `replace(inst)` builder.
-    pub fn clear_results(&mut self, inst: Inst) {
-        self.results[inst].clear(&mut self.value_lists)
-    }
-
-    /// Attach an existing value to the result value list for `inst`.
-    ///
-    /// The `res` value is appended to the end of the result list.
-    ///
-    /// This is a very low-level operation. Usually, instruction results with the correct types are
-    /// created automatically. The `res` value must not be attached to anything else.
-    pub fn attach_result(&mut self, inst: Inst, res: Value) {
-        debug_assert!(!self.value_is_attached(res));
-        let num = self.results[inst].push(res, &mut self.value_lists);
-        debug_assert!(num <= u16::MAX as usize, "Too many result values");
-        let ty = self.value_type(res);
-        self.values[res] = ValueData::Inst {
-            ty,
-            num: num as u16,
-            inst,
-        };
-    }
-
-    /// Replace an instruction result with a new value of type `new_type`.
-    ///
-    /// The `old_value` must be an attached instruction result.
-    ///
-    /// The old value is left detached, so it should probably be changed into something else.
-    ///
-    /// Returns the new value.
-    pub fn replace_result(&mut self, old_value: Value, new_type: Type) -> Value {
-        let (num, inst) = match self.values[old_value] {
-            ValueData::Inst { num, inst, .. } => (num, inst),
-            _ => panic!("{} is not an instruction result value", old_value),
-        };
-        let new_value = self.make_value(ValueData::Inst {
-            ty: new_type,
-            num,
-            inst,
-        });
-        let num = num as usize;
-        let attached = mem::replace(
-            self.results[inst]
-                .get_mut(num, &mut self.value_lists)
-                .expect("Replacing detached result"),
-            new_value,
-        );
-        debug_assert_eq!(
-            attached,
-            old_value,
-            "{} wasn't detached from {}",
-            old_value,
-            self.display_inst(inst)
-        );
-        new_value
-    }
-
-    /// Append a new instruction result value to `inst`.
-    pub fn append_result(&mut self, inst: Inst, ty: Type) -> Value {
-        let res = self.values.next_key();
-        let num = self.results[inst].push(res, &mut self.value_lists);
-        debug_assert!(num <= u16::MAX as usize, "Too many result values");
-        self.make_value(ValueData::Inst {
-            ty,
-            inst,
-            num: num as u16,
-        })
-    }
-
-    /// Append a new value argument to an instruction.
-    ///
-    /// Panics if the instruction doesn't support arguments.
-    pub fn append_inst_arg(&mut self, inst: Inst, new_arg: Value) {
-        let mut branch_values = self.insts[inst]
-            .take_value_list()
-            .expect("the instruction doesn't have value arguments");
-        branch_values.push(new_arg, &mut self.value_lists);
-        self.insts[inst].put_value_list(branch_values)
-    }
-
-    /// Get the first result of an instruction.
-    ///
-    /// This function panics if the instruction doesn't have any result.
-    pub fn first_result(&self, inst: Inst) -> Value {
-        self.results[inst]
-            .first(&self.value_lists)
-            .expect("Instruction has no results")
-    }
-
-    /// Test if `inst` has any result values currently.
-    pub fn has_results(&self, inst: Inst) -> bool {
-        !self.results[inst].is_empty()
-    }
-
-    /// Return all the results of an instruction.
-    pub fn inst_results(&self, inst: Inst) -> &[Value] {
-        self.results[inst].as_slice(&self.value_lists)
-    }
-
-    /// Return all the results of an instruction as ValueList.
-    pub fn inst_results_list(&self, inst: Inst) -> ValueList {
-        self.results[inst]
-    }
-
-    /// Get the call signature of a direct or indirect call instruction.
-    /// Returns `None` if `inst` is not a call instruction.
-    pub fn call_signature(&self, inst: Inst) -> Option<SigRef> {
-        match self.insts[inst].analyze_call(&self.value_lists) {
-            CallInfo::NotACall => None,
-            CallInfo::Direct(f, _) => Some(self.ext_funcs[f].signature),
-            CallInfo::Indirect(s, _) => Some(s),
-        }
-    }
-
-    /// Check if `inst` is a branch.
-    pub fn analyze_branch(&self, inst: Inst) -> BranchInfo {
-        self.insts[inst].analyze_branch(&self.value_lists)
-    }
-
-    /// Compute the type of an instruction result from opcode constraints and call signatures.
-    ///
-    /// This computes the same sequence of result types that `make_inst_results()` above would
-    /// assign to the created result values, but it does not depend on `make_inst_results()` being
-    /// called first.
-    ///
-    /// Returns `None` if asked about a result index that is too large.
-    pub fn compute_result_type(
-        &self,
-        inst: Inst,
-        result_idx: usize,
-        ctrl_typevar: Type,
-    ) -> Option<Type> {
-        let constraints = self.insts[inst].opcode().constraints();
-        let num_fixed_results = constraints.num_fixed_results();
-
-        if result_idx < num_fixed_results {
-            return Some(constraints.result_type(result_idx, ctrl_typevar));
-        }
-
-        // Not a fixed result, try to extract a return type from the call signature.
-        self.call_signature(inst).and_then(|sigref| {
-            self.signatures[sigref]
-                .returns
-                .get(result_idx - num_fixed_results)
-                .map(|&arg| arg.value_type)
-        })
-    }
-
-    /// Get the controlling type variable, or `INVALID` if `inst` isn't polymorphic.
-    pub fn ctrl_typevar(&self, inst: Inst) -> Type {
-        let constraints = self[inst].opcode().constraints();
-
-        if !constraints.is_polymorphic() {
-            types::INVALID
-        } else if constraints.requires_typevar_operand() {
-            // Not all instruction formats have a designated operand, but in that case
-            // `requires_typevar_operand()` should never be true.
-            self.value_type(
-                self[inst]
-                    .typevar_operand(&self.value_lists)
-                    .expect("Instruction format doesn't have a designated operand, bad opcode."),
-            )
-        } else {
-            self.value_type(self.first_result(inst))
-        }
-    }
-}
-
-/// Allow immutable access to instructions via indexing.
-impl Index<Inst> for DataFlowGraph {
-    type Output = InstructionData;
-
-    fn index(&self, inst: Inst) -> &InstructionData {
-        &self.insts[inst]
-    }
-}
-
-/// Allow mutable access to instructions via indexing.
-impl IndexMut<Inst> for DataFlowGraph {
-    fn index_mut(&mut self, inst: Inst) -> &mut InstructionData {
-        &mut self.insts[inst]
-    }
-}
-
-/// basic blocks.
-impl DataFlowGraph {
-    /// Create a new basic block.
-    pub fn make_block(&mut self) -> Block {
-        self.blocks.push(BlockData::new())
-    }
-
-    /// Get the number of parameters on `block`.
-    pub fn num_block_params(&self, block: Block) -> usize {
-        self.blocks[block].params.len(&self.value_lists)
-    }
-
-    /// Get the parameters on `block`.
-    pub fn block_params(&self, block: Block) -> &[Value] {
-        self.blocks[block].params.as_slice(&self.value_lists)
-    }
-
-    /// Get the types of the parameters on `block`.
-    pub fn block_param_types(&self, block: Block) -> Vec<Type> {
-        self.block_params(block)
-            .iter()
-            .map(|&v| self.value_type(v))
-            .collect()
-    }
-
-    /// Append a parameter with type `ty` to `block`.
-    pub fn append_block_param(&mut self, block: Block, ty: Type) -> Value {
-        let param = self.values.next_key();
-        let num = self.blocks[block].params.push(param, &mut self.value_lists);
-        debug_assert!(num <= u16::MAX as usize, "Too many parameters on block");
-        self.make_value(ValueData::Param {
-            ty,
-            num: num as u16,
-            block,
-        })
-    }
-
-    /// Removes `val` from `block`'s parameters by swapping it with the last parameter on `block`.
-    /// Returns the position of `val` before removal.
-    ///
-    /// *Important*: to ensure O(1) deletion, this method swaps the removed parameter with the
-    /// last `block` parameter. This can disrupt all the branch instructions jumping to this
-    /// `block` for which you have to change the branch argument order if necessary.
-    ///
-    /// Panics if `val` is not a block parameter.
-    pub fn swap_remove_block_param(&mut self, val: Value) -> usize {
-        let (block, num) = if let ValueData::Param { num, block, .. } = self.values[val] {
-            (block, num)
-        } else {
-            panic!("{} must be a block parameter", val);
-        };
-        self.blocks[block]
-            .params
-            .swap_remove(num as usize, &mut self.value_lists);
-        if let Some(last_arg_val) = self.blocks[block]
-            .params
-            .get(num as usize, &self.value_lists)
-        {
-            // We update the position of the old last arg.
-            if let ValueData::Param {
-                num: ref mut old_num,
-                ..
-            } = self.values[last_arg_val]
-            {
-                *old_num = num;
-            } else {
-                panic!("{} should be a Block parameter", last_arg_val);
-            }
-        }
-        num as usize
-    }
-
-    /// Removes `val` from `block`'s parameters by a standard linear time list removal which
-    /// preserves ordering. Also updates the values' data.
-    pub fn remove_block_param(&mut self, val: Value) {
-        let (block, num) = if let ValueData::Param { num, block, .. } = self.values[val] {
-            (block, num)
-        } else {
-            panic!("{} must be a block parameter", val);
-        };
-        self.blocks[block]
-            .params
-            .remove(num as usize, &mut self.value_lists);
-        for index in num..(self.num_block_params(block) as u16) {
-            match self.values[self.blocks[block]
-                .params
-                .get(index as usize, &self.value_lists)
-                .unwrap()]
-            {
-                ValueData::Param { ref mut num, .. } => {
-                    *num -= 1;
-                }
-                _ => panic!(
-                    "{} must be a block parameter",
-                    self.blocks[block]
-                        .params
-                        .get(index as usize, &self.value_lists)
-                        .unwrap()
-                ),
-            }
-        }
-    }
-
-    /// Append an existing value to `block`'s parameters.
-    ///
-    /// The appended value can't already be attached to something else.
-    ///
-    /// In almost all cases, you should be using `append_block_param()` instead of this method.
-    pub fn attach_block_param(&mut self, block: Block, param: Value) {
-        debug_assert!(!self.value_is_attached(param));
-        let num = self.blocks[block].params.push(param, &mut self.value_lists);
-        debug_assert!(num <= u16::MAX as usize, "Too many parameters on block");
-        let ty = self.value_type(param);
-        self.values[param] = ValueData::Param {
-            ty,
-            num: num as u16,
-            block,
-        };
-    }
-
-    /// Replace a block parameter with a new value of type `ty`.
-    ///
-    /// The `old_value` must be an attached block parameter. It is removed from its place in the list
-    /// of parameters and replaced by a new value of type `new_type`. The new value gets the same
-    /// position in the list, and other parameters are not disturbed.
-    ///
-    /// The old value is left detached, so it should probably be changed into something else.
-    ///
-    /// Returns the new value.
-    pub fn replace_block_param(&mut self, old_value: Value, new_type: Type) -> Value {
-        // Create new value identical to the old one except for the type.
-        let (block, num) = if let ValueData::Param { num, block, .. } = self.values[old_value] {
-            (block, num)
-        } else {
-            panic!("{} must be a block parameter", old_value);
-        };
-        let new_arg = self.make_value(ValueData::Param {
-            ty: new_type,
-            num,
-            block,
-        });
-
-        self.blocks[block]
-            .params
-            .as_mut_slice(&mut self.value_lists)[num as usize] = new_arg;
-        new_arg
-    }
-
-    /// Detach all the parameters from `block` and return them as a `ValueList`.
-    ///
-    /// This is a quite low-level operation. Sensible things to do with the detached block parameters
-    /// is to put them back on the same block with `attach_block_param()` or change them into aliases
-    /// with `change_to_alias()`.
-    pub fn detach_block_params(&mut self, block: Block) -> ValueList {
-        self.blocks[block].params.take()
-    }
-}
-
-/// Contents of a basic block.
-///
-/// Parameters on a basic block are values that dominate everything in the block. All
-/// branches to this block must provide matching arguments, and the arguments to the entry block must
-/// match the function arguments.
-#[derive(Clone)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-struct BlockData {
-    /// List of parameters to this block.
-    params: ValueList,
-}
-
-impl BlockData {
-    fn new() -> Self {
-        Self {
-            params: ValueList::new(),
-        }
-    }
-}
-
-/// Object that can display an instruction.
-pub struct DisplayInst<'a>(&'a DataFlowGraph, Inst);
-
-impl<'a> fmt::Display for DisplayInst<'a> {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        let dfg = self.0;
-        let inst = self.1;
-
-        if let Some((first, rest)) = dfg.inst_results(inst).split_first() {
-            write!(f, "{}", first)?;
-            for v in rest {
-                write!(f, ", {}", v)?;
-            }
-            write!(f, " = ")?;
-        }
-
-        let typevar = dfg.ctrl_typevar(inst);
-        if typevar.is_invalid() {
-            write!(f, "{}", dfg[inst].opcode())?;
-        } else {
-            write!(f, "{}.{}", dfg[inst].opcode(), typevar)?;
-        }
-        write_operands(f, dfg, inst)
-    }
-}
-
-/// Parser routines. These routines should not be used outside the parser.
-impl DataFlowGraph {
-    /// Set the type of a value. This is only for use in the parser, which needs
-    /// to create invalid values for index padding which may be reassigned later.
-    #[cold]
-    fn set_value_type_for_parser(&mut self, v: Value, t: Type) {
-        assert_eq!(
-            self.value_type(v),
-            types::INVALID,
-            "this function is only for assigning types to previously invalid values"
-        );
-        match self.values[v] {
-            ValueData::Inst { ref mut ty, .. }
-            | ValueData::Param { ref mut ty, .. }
-            | ValueData::Alias { ref mut ty, .. } => *ty = t,
-        }
-    }
-
-    /// Create result values for `inst`, reusing the provided detached values.
-    /// This is similar to `make_inst_results_reusing` except it's only for use
-    /// in the parser, which needs to reuse previously invalid values.
-    #[cold]
-    pub fn make_inst_results_for_parser(
-        &mut self,
-        inst: Inst,
-        ctrl_typevar: Type,
-        reuse: &[Value],
-    ) -> usize {
-        // Get the call signature if this is a function call.
-        if let Some(sig) = self.call_signature(inst) {
-            assert_eq!(
-                self.insts[inst].opcode().constraints().num_fixed_results(),
-                0
-            );
-            for res_idx in 0..self.signatures[sig].returns.len() {
-                let ty = self.signatures[sig].returns[res_idx].value_type;
-                if let Some(v) = reuse.get(res_idx) {
-                    self.set_value_type_for_parser(*v, ty);
-                }
-            }
-        } else {
-            let constraints = self.insts[inst].opcode().constraints();
-            for res_idx in 0..constraints.num_fixed_results() {
-                let ty = constraints.result_type(res_idx, ctrl_typevar);
-                if let Some(v) = reuse.get(res_idx) {
-                    self.set_value_type_for_parser(*v, ty);
-                }
-            }
-        }
-
-        self.make_inst_results_reusing(inst, ctrl_typevar, reuse.iter().map(|x| Some(*x)))
-    }
-
-    /// Similar to `append_block_param`, append a parameter with type `ty` to
-    /// `block`, but using value `val`. This is only for use by the parser to
-    /// create parameters with specific values.
-    #[cold]
-    pub fn append_block_param_for_parser(&mut self, block: Block, ty: Type, val: Value) {
-        let num = self.blocks[block].params.push(val, &mut self.value_lists);
-        assert!(num <= u16::MAX as usize, "Too many parameters on block");
-        self.values[val] = ValueData::Param {
-            ty,
-            num: num as u16,
-            block,
-        };
-    }
-
-    /// Create a new value alias. This is only for use by the parser to create
-    /// aliases with specific values, and the printer for testing.
-    #[cold]
-    pub fn make_value_alias_for_serialization(&mut self, src: Value, dest: Value) {
-        assert_ne!(src, Value::reserved_value());
-        assert_ne!(dest, Value::reserved_value());
-
-        let ty = if self.values.is_valid(src) {
-            self.value_type(src)
-        } else {
-            // As a special case, if we can't resolve the aliasee yet, use INVALID
-            // temporarily. It will be resolved later in parsing.
-            types::INVALID
-        };
-        let data = ValueData::Alias { ty, original: src };
-        self.values[dest] = data;
-    }
-
-    /// If `v` is already defined as an alias, return its destination value.
-    /// Otherwise return None. This allows the parser to coalesce identical
-    /// alias definitions, and the printer to identify an alias's immediate target.
-    #[cold]
-    pub fn value_alias_dest_for_serialization(&self, v: Value) -> Option<Value> {
-        if let ValueData::Alias { original, .. } = self.values[v] {
-            Some(original)
-        } else {
-            None
-        }
-    }
-
-    /// Compute the type of an alias. This is only for use in the parser.
-    /// Returns false if an alias cycle was encountered.
-    #[cold]
-    pub fn set_alias_type_for_parser(&mut self, v: Value) -> bool {
-        if let Some(resolved) = maybe_resolve_aliases(&self.values, v) {
-            let old_ty = self.value_type(v);
-            let new_ty = self.value_type(resolved);
-            if old_ty == types::INVALID {
-                self.set_value_type_for_parser(v, new_ty);
-            } else {
-                assert_eq!(old_ty, new_ty);
-            }
-            true
-        } else {
-            false
-        }
-    }
-
-    /// Create an invalid value, to pad the index space. This is only for use by
-    /// the parser to pad out the value index space.
-    #[cold]
-    pub fn make_invalid_value_for_parser(&mut self) {
-        let data = ValueData::Alias {
-            ty: types::INVALID,
-            original: Value::reserved_value(),
-        };
-        self.make_value(data);
-    }
-
-    /// Check if a value reference is valid, while being aware of aliases which
-    /// may be unresolved while parsing.
-    #[cold]
-    pub fn value_is_valid_for_parser(&self, v: Value) -> bool {
-        if !self.value_is_valid(v) {
-            return false;
-        }
-        if let ValueData::Alias { ty, .. } = self.values[v] {
-            ty != types::INVALID
-        } else {
-            true
-        }
-    }
-}
-
-#[cfg(test)]
-mod tests {
-    use super::*;
-    use crate::cursor::{Cursor, FuncCursor};
-    use crate::ir::types;
-    use crate::ir::{Function, InstructionData, Opcode, TrapCode};
-    use alloc::string::ToString;
-
-    #[test]
-    fn make_inst() {
-        let mut dfg = DataFlowGraph::new();
-
-        let idata = InstructionData::UnaryImm {
-            opcode: Opcode::Iconst,
-            imm: 0.into(),
-        };
-        let inst = dfg.make_inst(idata);
-
-        dfg.make_inst_results(inst, types::I32);
-        assert_eq!(inst.to_string(), "inst0");
-        assert_eq!(dfg.display_inst(inst).to_string(), "v0 = iconst.i32 0");
-
-        // Immutable reference resolution.
-        {
-            let immdfg = &dfg;
-            let ins = &immdfg[inst];
-            assert_eq!(ins.opcode(), Opcode::Iconst);
-        }
-
-        // Results.
-        let val = dfg.first_result(inst);
-        assert_eq!(dfg.inst_results(inst), &[val]);
-
-        assert_eq!(dfg.value_def(val), ValueDef::Result(inst, 0));
-        assert_eq!(dfg.value_type(val), types::I32);
-
-        // Replacing results.
-        assert!(dfg.value_is_attached(val));
-        let v2 = dfg.replace_result(val, types::F64);
-        assert!(!dfg.value_is_attached(val));
-        assert!(dfg.value_is_attached(v2));
-        assert_eq!(dfg.inst_results(inst), &[v2]);
-        assert_eq!(dfg.value_def(v2), ValueDef::Result(inst, 0));
-        assert_eq!(dfg.value_type(v2), types::F64);
-    }
-
-    #[test]
-    fn no_results() {
-        let mut dfg = DataFlowGraph::new();
-
-        let idata = InstructionData::Trap {
-            opcode: Opcode::Trap,
-            code: TrapCode::User(0),
-        };
-        let inst = dfg.make_inst(idata);
-        assert_eq!(dfg.display_inst(inst).to_string(), "trap user0");
-
-        // Result slice should be empty.
-        assert_eq!(dfg.inst_results(inst), &[]);
-    }
-
-    #[test]
-    fn block() {
-        let mut dfg = DataFlowGraph::new();
-
-        let block = dfg.make_block();
-        assert_eq!(block.to_string(), "block0");
-        assert_eq!(dfg.num_block_params(block), 0);
-        assert_eq!(dfg.block_params(block), &[]);
-        assert!(dfg.detach_block_params(block).is_empty());
-        assert_eq!(dfg.num_block_params(block), 0);
-        assert_eq!(dfg.block_params(block), &[]);
-
-        let arg1 = dfg.append_block_param(block, types::F32);
-        assert_eq!(arg1.to_string(), "v0");
-        assert_eq!(dfg.num_block_params(block), 1);
-        assert_eq!(dfg.block_params(block), &[arg1]);
-
-        let arg2 = dfg.append_block_param(block, types::I16);
-        assert_eq!(arg2.to_string(), "v1");
-        assert_eq!(dfg.num_block_params(block), 2);
-        assert_eq!(dfg.block_params(block), &[arg1, arg2]);
-
-        assert_eq!(dfg.value_def(arg1), ValueDef::Param(block, 0));
-        assert_eq!(dfg.value_def(arg2), ValueDef::Param(block, 1));
-        assert_eq!(dfg.value_type(arg1), types::F32);
-        assert_eq!(dfg.value_type(arg2), types::I16);
-
-        // Swap the two block parameters.
-        let vlist = dfg.detach_block_params(block);
-        assert_eq!(dfg.num_block_params(block), 0);
-        assert_eq!(dfg.block_params(block), &[]);
-        assert_eq!(vlist.as_slice(&dfg.value_lists), &[arg1, arg2]);
-        dfg.attach_block_param(block, arg2);
-        let arg3 = dfg.append_block_param(block, types::I32);
-        dfg.attach_block_param(block, arg1);
-        assert_eq!(dfg.block_params(block), &[arg2, arg3, arg1]);
-    }
-
-    #[test]
-    fn replace_block_params() {
-        let mut dfg = DataFlowGraph::new();
-
-        let block = dfg.make_block();
-        let arg1 = dfg.append_block_param(block, types::F32);
-
-        let new1 = dfg.replace_block_param(arg1, types::I64);
-        assert_eq!(dfg.value_type(arg1), types::F32);
-        assert_eq!(dfg.value_type(new1), types::I64);
-        assert_eq!(dfg.block_params(block), &[new1]);
-
-        dfg.attach_block_param(block, arg1);
-        assert_eq!(dfg.block_params(block), &[new1, arg1]);
-
-        let new2 = dfg.replace_block_param(arg1, types::I8);
-        assert_eq!(dfg.value_type(arg1), types::F32);
-        assert_eq!(dfg.value_type(new2), types::I8);
-        assert_eq!(dfg.block_params(block), &[new1, new2]);
-
-        dfg.attach_block_param(block, arg1);
-        assert_eq!(dfg.block_params(block), &[new1, new2, arg1]);
-
-        let new3 = dfg.replace_block_param(new2, types::I16);
-        assert_eq!(dfg.value_type(new1), types::I64);
-        assert_eq!(dfg.value_type(new2), types::I8);
-        assert_eq!(dfg.value_type(new3), types::I16);
-        assert_eq!(dfg.block_params(block), &[new1, new3, arg1]);
-    }
-
-    #[test]
-    fn swap_remove_block_params() {
-        let mut dfg = DataFlowGraph::new();
-
-        let block = dfg.make_block();
-        let arg1 = dfg.append_block_param(block, types::F32);
-        let arg2 = dfg.append_block_param(block, types::F32);
-        let arg3 = dfg.append_block_param(block, types::F32);
-        assert_eq!(dfg.block_params(block), &[arg1, arg2, arg3]);
-
-        dfg.swap_remove_block_param(arg1);
-        assert_eq!(dfg.value_is_attached(arg1), false);
-        assert_eq!(dfg.value_is_attached(arg2), true);
-        assert_eq!(dfg.value_is_attached(arg3), true);
-        assert_eq!(dfg.block_params(block), &[arg3, arg2]);
-        dfg.swap_remove_block_param(arg2);
-        assert_eq!(dfg.value_is_attached(arg2), false);
-        assert_eq!(dfg.value_is_attached(arg3), true);
-        assert_eq!(dfg.block_params(block), &[arg3]);
-        dfg.swap_remove_block_param(arg3);
-        assert_eq!(dfg.value_is_attached(arg3), false);
-        assert_eq!(dfg.block_params(block), &[]);
-    }
-
-    #[test]
-    fn aliases() {
-        use crate::ir::InstBuilder;
-
-        let mut func = Function::new();
-        let block0 = func.dfg.make_block();
-        let mut pos = FuncCursor::new(&mut func);
-        pos.insert_block(block0);
-
-        // Build a little test program.
-        let v1 = pos.ins().iconst(types::I32, 42);
-
-        // Make sure we can resolve value aliases even when values is empty.
-        assert_eq!(pos.func.dfg.resolve_aliases(v1), v1);
-
-        let arg0 = pos.func.dfg.append_block_param(block0, types::I32);
-        let (s, c) = pos.ins().iadd_ifcout(v1, arg0);
-        let iadd = match pos.func.dfg.value_def(s) {
-            ValueDef::Result(i, 0) => i,
-            _ => panic!(),
-        };
-
-        // Remove `c` from the result list.
-        pos.func.dfg.clear_results(iadd);
-        pos.func.dfg.attach_result(iadd, s);
-
-        // Replace `iadd_ifcout` with a normal `iadd` and an `ifcmp`.
-        pos.func.dfg.replace(iadd).iadd(v1, arg0);
-        let c2 = pos.ins().ifcmp(s, v1);
-        pos.func.dfg.change_to_alias(c, c2);
-
-        assert_eq!(pos.func.dfg.resolve_aliases(c2), c2);
-        assert_eq!(pos.func.dfg.resolve_aliases(c), c2);
-
-        // Make a copy of the alias.
-        let c3 = pos.ins().copy(c);
-        // This does not see through copies.
-        assert_eq!(pos.func.dfg.resolve_aliases(c3), c3);
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/entities.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/entities.rs
deleted file mode 100644
index d8ca7cef3..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/entities.rs
+++ /dev/null
@@ -1,533 +0,0 @@
-//! Cranelift IR entity references.
-//!
-//! Instructions in Cranelift IR need to reference other entities in the function. This can be other
-//! parts of the function like basic blocks or stack slots, or it can be external entities
-//! that are declared in the function preamble in the text format.
-//!
-//! These entity references in instruction operands are not implemented as Rust references both
-//! because Rust's ownership and mutability rules make it difficult, and because 64-bit pointers
-//! take up a lot of space, and we want a compact in-memory representation. Instead, entity
-//! references are structs wrapping a `u32` index into a table in the `Function` main data
-//! structure. There is a separate index type for each entity type, so we don't lose type safety.
-//!
-//! The `entities` module defines public types for the entity references along with constants
-//! representing an invalid reference. We prefer to use `Option<EntityRef>` whenever possible, but
-//! unfortunately that type is twice as large as the 32-bit index type on its own. Thus, compact
-//! data structures use the `PackedOption<EntityRef>` representation, while function arguments and
-//! return values prefer the more Rust-like `Option<EntityRef>` variant.
-//!
-//! The entity references all implement the `Display` trait in a way that matches the textual IR
-//! format.
-
-use crate::entity::entity_impl;
-use core::fmt;
-use core::u32;
-#[cfg(feature = "enable-serde")]
-use serde::{Deserialize, Serialize};
-
-/// An opaque reference to a [basic block](https://en.wikipedia.org/wiki/Basic_block) in a
-/// [`Function`](super::function::Function).
-///
-/// You can get a `Block` using
-/// [`FunctionBuilder::create_block`](https://docs.rs/cranelift-frontend/*/cranelift_frontend/struct.FunctionBuilder.html#method.create_block)
-///
-/// While the order is stable, it is arbitrary and does not necessarily resemble the layout order.
-#[derive(Copy, Clone, PartialEq, Eq, Hash, PartialOrd, Ord)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub struct Block(u32);
-entity_impl!(Block, "block");
-
-impl Block {
-    /// Create a new block reference from its number. This corresponds to the `blockNN` representation.
-    ///
-    /// This method is for use by the parser.
-    pub fn with_number(n: u32) -> Option<Self> {
-        if n < u32::MAX {
-            Some(Self(n))
-        } else {
-            None
-        }
-    }
-}
-
-/// An opaque reference to an SSA value.
-///
-/// You can get a constant `Value` from the following
-/// [`InstBuilder`](super::InstBuilder) instructions:
-///
-/// - [`iconst`](super::InstBuilder::iconst) for integer constants
-/// - [`f32const`](super::InstBuilder::f32const) for 32-bit float constants
-/// - [`f64const`](super::InstBuilder::f64const) for 64-bit float constants
-/// - [`bconst`](super::InstBuilder::bconst) for boolean constants
-/// - [`vconst`](super::InstBuilder::vconst) for vector constants
-/// - [`null`](super::InstBuilder::null) for null reference constants
-///
-/// Any `InstBuilder` instruction that has an output will also return a `Value`.
-///
-/// While the order is stable, it is arbitrary.
-#[derive(Copy, Clone, PartialEq, Eq, Hash, PartialOrd, Ord)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub struct Value(u32);
-entity_impl!(Value, "v");
-
-impl Value {
-    /// Create a value from its number representation.
-    /// This is the number in the `vNN` notation.
-    ///
-    /// This method is for use by the parser.
-    pub fn with_number(n: u32) -> Option<Self> {
-        if n < u32::MAX / 2 {
-            Some(Self(n))
-        } else {
-            None
-        }
-    }
-}
-
-/// An opaque reference to an instruction in a [`Function`](super::Function).
-///
-/// Most usage of `Inst` is internal. `Inst`ructions are returned by
-/// [`InstBuilder`](super::InstBuilder) instructions that do not return a
-/// [`Value`], such as control flow and trap instructions.
-///
-/// If you look around the API, you can find many inventive uses for `Inst`,
-/// such as [annotating specific instructions with a comment][inst_comment]
-/// or [performing reflection at compile time](super::DataFlowGraph::analyze_branch)
-/// on the type of instruction.
-///
-/// [inst_comment]: https://github.com/bjorn3/rustc_codegen_cranelift/blob/0f8814fd6da3d436a90549d4bb19b94034f2b19c/src/pretty_clif.rs
-///
-/// While the order is stable, it is arbitrary and does not necessarily resemble the layout order.
-#[derive(Copy, Clone, PartialEq, Eq, Hash, PartialOrd, Ord)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub struct Inst(u32);
-entity_impl!(Inst, "inst");
-
-/// An opaque reference to a stack slot.
-///
-/// Stack slots represent an address on the
-/// [call stack](https://en.wikipedia.org/wiki/Call_stack).
-///
-/// `StackSlot`s can be created with
-/// [`FunctionBuilder::create_stackslot`](https://docs.rs/cranelift-frontend/*/cranelift_frontend/struct.FunctionBuilder.html#method.create_stack_slot).
-///
-/// `StackSlot`s are most often used with
-/// [`stack_addr`](super::InstBuilder::stack_addr),
-/// [`stack_load`](super::InstBuilder::stack_load), and
-/// [`stack_store`](super::InstBuilder::stack_store).
-///
-/// While the order is stable, it is arbitrary and does not necessarily resemble the stack order.
-#[derive(Copy, Clone, PartialEq, Eq, Hash, PartialOrd, Ord)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub struct StackSlot(u32);
-entity_impl!(StackSlot, "ss");
-
-impl StackSlot {
-    /// Create a new stack slot reference from its number.
-    ///
-    /// This method is for use by the parser.
-    pub fn with_number(n: u32) -> Option<Self> {
-        if n < u32::MAX {
-            Some(Self(n))
-        } else {
-            None
-        }
-    }
-}
-
-/// An opaque reference to a global value.
-///
-/// A `GlobalValue` is a [`Value`](Value) that will be live across the entire
-/// function lifetime. It can be preloaded from other global values.
-///
-/// You can create a `GlobalValue` in the following ways:
-///
-/// - When compiling to WASM, you can use it to load values from a
-/// [`VmContext`](super::GlobalValueData::VMContext) using
-/// [`FuncEnvironment::make_global`](https://docs.rs/cranelift-wasm/*/cranelift_wasm/trait.FuncEnvironment.html#tymethod.make_global).
-/// - When compiling to native code, you can use it for objects in static memory with
-/// [`Module::declare_data_in_func`](https://docs.rs/cranelift-module/*/cranelift_module/trait.Module.html#method.declare_data_in_func).
-/// - For any compilation target, it can be registered with
-/// [`FunctionBuilder::create_global_value`](https://docs.rs/cranelift-frontend/*/cranelift_frontend/struct.FunctionBuilder.html#method.create_global_value).
-///
-/// `GlobalValue`s can be retrieved with
-/// [`InstBuilder:global_value`](super::InstBuilder::global_value).
-///
-/// While the order is stable, it is arbitrary.
-#[derive(Copy, Clone, PartialEq, Eq, Hash, PartialOrd, Ord)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub struct GlobalValue(u32);
-entity_impl!(GlobalValue, "gv");
-
-impl GlobalValue {
-    /// Create a new global value reference from its number.
-    ///
-    /// This method is for use by the parser.
-    pub fn with_number(n: u32) -> Option<Self> {
-        if n < u32::MAX {
-            Some(Self(n))
-        } else {
-            None
-        }
-    }
-}
-
-/// An opaque reference to a constant.
-///
-/// You can store [`ConstantData`](super::ConstantData) in a
-/// [`ConstantPool`](super::ConstantPool) for efficient storage and retrieval.
-/// See [`ConstantPool::insert`](super::ConstantPool::insert).
-///
-/// While the order is stable, it is arbitrary and does not necessarily resemble the order in which
-/// the constants are written in the constant pool.
-#[derive(Copy, Clone, PartialEq, Eq, Hash, Ord, PartialOrd)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub struct Constant(u32);
-entity_impl!(Constant, "const");
-
-impl Constant {
-    /// Create a const reference from its number.
-    ///
-    /// This method is for use by the parser.
-    pub fn with_number(n: u32) -> Option<Self> {
-        if n < u32::MAX {
-            Some(Self(n))
-        } else {
-            None
-        }
-    }
-}
-
-/// An opaque reference to an immediate.
-///
-/// Some immediates (e.g. SIMD shuffle masks) are too large to store in the
-/// [`InstructionData`](super::instructions::InstructionData) struct and therefore must be
-/// tracked separately in [`DataFlowGraph::immediates`](super::dfg::DataFlowGraph). `Immediate`
-/// provides a way to reference values stored there.
-///
-/// While the order is stable, it is arbitrary.
-#[derive(Copy, Clone, PartialEq, Eq, Hash, PartialOrd, Ord)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub struct Immediate(u32);
-entity_impl!(Immediate, "imm");
-
-impl Immediate {
-    /// Create an immediate reference from its number.
-    ///
-    /// This method is for use by the parser.
-    pub fn with_number(n: u32) -> Option<Self> {
-        if n < u32::MAX {
-            Some(Self(n))
-        } else {
-            None
-        }
-    }
-}
-
-/// An opaque reference to a [jump table](https://en.wikipedia.org/wiki/Branch_table).
-///
-/// `JumpTable`s are used for indirect branching and are specialized for dense,
-/// 0-based jump offsets. If you want a jump table which doesn't start at 0,
-/// or is not contiguous, consider using a [`Switch`](https://docs.rs/cranelift-frontend/*/cranelift_frontend/struct.Switch.html) instead.
-///
-/// `JumpTable` are used with [`br_table`](super::InstBuilder::br_table).
-///
-/// `JumpTable`s can be created with
-/// [`create_jump_table`](https://docs.rs/cranelift-frontend/*/cranelift_frontend/struct.FunctionBuilder.html#method.create_jump_table).
-///
-/// While the order is stable, it is arbitrary.
-#[derive(Copy, Clone, PartialEq, Eq, Hash, PartialOrd, Ord)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub struct JumpTable(u32);
-entity_impl!(JumpTable, "jt");
-
-impl JumpTable {
-    /// Create a new jump table reference from its number.
-    ///
-    /// This method is for use by the parser.
-    pub fn with_number(n: u32) -> Option<Self> {
-        if n < u32::MAX {
-            Some(Self(n))
-        } else {
-            None
-        }
-    }
-}
-
-/// An opaque reference to another [`Function`](super::Function).
-///
-/// `FuncRef`s are used for [direct](super::InstBuilder::call) function calls
-/// and by [`func_addr`](super::InstBuilder::func_addr) for use in
-/// [indirect](super::InstBuilder::call_indirect) function calls.
-///
-/// `FuncRef`s can be created with
-///
-/// - [`FunctionBuilder::import_function`](https://docs.rs/cranelift-frontend/*/cranelift_frontend/struct.FunctionBuilder.html#method.import_function)
-/// for external functions
-/// - [`Module::declare_func_in_func`](https://docs.rs/cranelift-module/*/cranelift_module/trait.Module.html#method.declare_func_in_func)
-/// for functions declared elsewhere in the same native
-/// [`Module`](https://docs.rs/cranelift-module/*/cranelift_module/trait.Module.html)
-/// - [`FuncEnvironment::make_direct_func`](https://docs.rs/cranelift-wasm/*/cranelift_wasm/trait.FuncEnvironment.html#tymethod.make_direct_func)
-/// for functions declared in the same WebAssembly
-/// [`FuncEnvironment`](https://docs.rs/cranelift-wasm/*/cranelift_wasm/trait.FuncEnvironment.html#tymethod.make_direct_func)
-///
-/// While the order is stable, it is arbitrary.
-#[derive(Copy, Clone, PartialEq, Eq, Hash, PartialOrd, Ord)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub struct FuncRef(u32);
-entity_impl!(FuncRef, "fn");
-
-impl FuncRef {
-    /// Create a new external function reference from its number.
-    ///
-    /// This method is for use by the parser.
-    pub fn with_number(n: u32) -> Option<Self> {
-        if n < u32::MAX {
-            Some(Self(n))
-        } else {
-            None
-        }
-    }
-}
-
-/// An opaque reference to a function [`Signature`](super::Signature).
-///
-/// `SigRef`s are used to declare a function with
-/// [`FunctionBuiler::import_function`](https://docs.rs/cranelift-frontend/*/cranelift_frontend/struct.FunctionBuilder.html#method.import_function)
-/// as well as to make an [indirect function call](super::InstBuilder::call_indirect).
-///
-/// `SigRef`s can be created with
-/// [`FunctionBuilder::import_signature`](https://docs.rs/cranelift-frontend/*/cranelift_frontend/struct.FunctionBuilder.html#method.import_signature).
-///
-/// You can retrieve the [`Signature`](super::Signature) that was used to create a `SigRef` with
-/// [`FunctionBuilder::signature`](https://docs.rs/cranelift-frontend/*/cranelift_frontend/struct.FunctionBuilder.html#method.signature) or
-/// [`func.dfg.signatures`](super::dfg::DataFlowGraph::signatures).
-///
-/// While the order is stable, it is arbitrary.
-#[derive(Copy, Clone, PartialEq, Eq, Hash, PartialOrd, Ord)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub struct SigRef(u32);
-entity_impl!(SigRef, "sig");
-
-impl SigRef {
-    /// Create a new function signature reference from its number.
-    ///
-    /// This method is for use by the parser.
-    pub fn with_number(n: u32) -> Option<Self> {
-        if n < u32::MAX {
-            Some(Self(n))
-        } else {
-            None
-        }
-    }
-}
-
-/// An opaque reference to a [heap](https://en.wikipedia.org/wiki/Memory_management#DYNAMIC).
-///
-/// Heaps are used to access dynamically allocated memory through
-/// [`heap_addr`](super::InstBuilder::heap_addr).
-///
-/// To create a heap, use [`FunctionBuilder::create_heap`](https://docs.rs/cranelift-frontend/*/cranelift_frontend/struct.FunctionBuilder.html#method.create_heap).
-///
-/// While the order is stable, it is arbitrary.
-#[derive(Copy, Clone, PartialEq, Eq, Hash, PartialOrd, Ord)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub struct Heap(u32);
-entity_impl!(Heap, "heap");
-
-impl Heap {
-    /// Create a new heap reference from its number.
-    ///
-    /// This method is for use by the parser.
-    pub fn with_number(n: u32) -> Option<Self> {
-        if n < u32::MAX {
-            Some(Self(n))
-        } else {
-            None
-        }
-    }
-}
-
-/// An opaque reference to a [WebAssembly
-/// table](https://developer.mozilla.org/en-US/docs/WebAssembly/Understanding_the_text_format#WebAssembly_tables).
-///
-/// `Table`s are used to store a list of function references.
-/// They can be created with [`FuncEnvironment::make_table`](https://docs.rs/cranelift-wasm/*/cranelift_wasm/trait.FuncEnvironment.html#tymethod.make_table).
-/// They can be used with
-/// [`FuncEnvironment::translate_call_indirect`](https://docs.rs/cranelift-wasm/*/cranelift_wasm/trait.FuncEnvironment.html#tymethod.translate_call_indirect).
-///
-/// While the order is stable, it is arbitrary.
-#[derive(Copy, Clone, PartialEq, Eq, Hash, PartialOrd, Ord)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub struct Table(u32);
-entity_impl!(Table, "table");
-
-impl Table {
-    /// Create a new table reference from its number.
-    ///
-    /// This method is for use by the parser.
-    pub fn with_number(n: u32) -> Option<Self> {
-        if n < u32::MAX {
-            Some(Self(n))
-        } else {
-            None
-        }
-    }
-}
-
-/// An opaque reference to any of the entities defined in this module that can appear in CLIF IR.
-#[derive(Copy, Clone, PartialEq, Eq, Hash, PartialOrd, Ord)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub enum AnyEntity {
-    /// The whole function.
-    Function,
-    /// a basic block.
-    Block(Block),
-    /// An instruction.
-    Inst(Inst),
-    /// An SSA value.
-    Value(Value),
-    /// A stack slot.
-    StackSlot(StackSlot),
-    /// A Global value.
-    GlobalValue(GlobalValue),
-    /// A jump table.
-    JumpTable(JumpTable),
-    /// A constant.
-    Constant(Constant),
-    /// An external function.
-    FuncRef(FuncRef),
-    /// A function call signature.
-    SigRef(SigRef),
-    /// A heap.
-    Heap(Heap),
-    /// A table.
-    Table(Table),
-    /// A function's stack limit
-    StackLimit,
-}
-
-impl fmt::Display for AnyEntity {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        match *self {
-            Self::Function => write!(f, "function"),
-            Self::Block(r) => r.fmt(f),
-            Self::Inst(r) => r.fmt(f),
-            Self::Value(r) => r.fmt(f),
-            Self::StackSlot(r) => r.fmt(f),
-            Self::GlobalValue(r) => r.fmt(f),
-            Self::JumpTable(r) => r.fmt(f),
-            Self::Constant(r) => r.fmt(f),
-            Self::FuncRef(r) => r.fmt(f),
-            Self::SigRef(r) => r.fmt(f),
-            Self::Heap(r) => r.fmt(f),
-            Self::Table(r) => r.fmt(f),
-            Self::StackLimit => write!(f, "stack_limit"),
-        }
-    }
-}
-
-impl fmt::Debug for AnyEntity {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        (self as &dyn fmt::Display).fmt(f)
-    }
-}
-
-impl From<Block> for AnyEntity {
-    fn from(r: Block) -> Self {
-        Self::Block(r)
-    }
-}
-
-impl From<Inst> for AnyEntity {
-    fn from(r: Inst) -> Self {
-        Self::Inst(r)
-    }
-}
-
-impl From<Value> for AnyEntity {
-    fn from(r: Value) -> Self {
-        Self::Value(r)
-    }
-}
-
-impl From<StackSlot> for AnyEntity {
-    fn from(r: StackSlot) -> Self {
-        Self::StackSlot(r)
-    }
-}
-
-impl From<GlobalValue> for AnyEntity {
-    fn from(r: GlobalValue) -> Self {
-        Self::GlobalValue(r)
-    }
-}
-
-impl From<JumpTable> for AnyEntity {
-    fn from(r: JumpTable) -> Self {
-        Self::JumpTable(r)
-    }
-}
-
-impl From<Constant> for AnyEntity {
-    fn from(r: Constant) -> Self {
-        Self::Constant(r)
-    }
-}
-
-impl From<FuncRef> for AnyEntity {
-    fn from(r: FuncRef) -> Self {
-        Self::FuncRef(r)
-    }
-}
-
-impl From<SigRef> for AnyEntity {
-    fn from(r: SigRef) -> Self {
-        Self::SigRef(r)
-    }
-}
-
-impl From<Heap> for AnyEntity {
-    fn from(r: Heap) -> Self {
-        Self::Heap(r)
-    }
-}
-
-impl From<Table> for AnyEntity {
-    fn from(r: Table) -> Self {
-        Self::Table(r)
-    }
-}
-
-#[cfg(test)]
-mod tests {
-    use super::*;
-    use alloc::string::ToString;
-    use core::u32;
-
-    #[test]
-    fn value_with_number() {
-        assert_eq!(Value::with_number(0).unwrap().to_string(), "v0");
-        assert_eq!(Value::with_number(1).unwrap().to_string(), "v1");
-
-        assert_eq!(Value::with_number(u32::MAX / 2), None);
-        assert!(Value::with_number(u32::MAX / 2 - 1).is_some());
-    }
-
-    #[test]
-    fn memory() {
-        use crate::packed_option::PackedOption;
-        use core::mem;
-        // This is the whole point of `PackedOption`.
-        assert_eq!(
-            mem::size_of::<Value>(),
-            mem::size_of::<PackedOption<Value>>()
-        );
-    }
-
-    #[test]
-    fn constant_with_number() {
-        assert_eq!(Constant::with_number(0).unwrap().to_string(), "const0");
-        assert_eq!(Constant::with_number(1).unwrap().to_string(), "const1");
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/extfunc.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/extfunc.rs
deleted file mode 100644
index 1a623095a..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/extfunc.rs
+++ /dev/null
@@ -1,474 +0,0 @@
-//! External function calls.
-//!
-//! To a Cranelift function, all functions are "external". Directly called functions must be
-//! declared in the preamble, and all function calls must have a signature.
-//!
-//! This module declares the data types used to represent external functions and call signatures.
-
-use crate::ir::{ExternalName, SigRef, Type};
-use crate::isa::CallConv;
-use crate::machinst::RelocDistance;
-use alloc::vec::Vec;
-use core::fmt;
-use core::str::FromStr;
-#[cfg(feature = "enable-serde")]
-use serde::{Deserialize, Serialize};
-
-/// Function signature.
-///
-/// The function signature describes the types of formal parameters and return values along with
-/// other details that are needed to call a function correctly.
-///
-/// A signature can optionally include ISA-specific ABI information which specifies exactly how
-/// arguments and return values are passed.
-#[derive(Clone, Debug, PartialEq, Eq, Hash)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub struct Signature {
-    /// The arguments passed to the function.
-    pub params: Vec<AbiParam>,
-    /// Values returned from the function.
-    pub returns: Vec<AbiParam>,
-
-    /// Calling convention.
-    pub call_conv: CallConv,
-}
-
-impl Signature {
-    /// Create a new blank signature.
-    pub fn new(call_conv: CallConv) -> Self {
-        Self {
-            params: Vec::new(),
-            returns: Vec::new(),
-            call_conv,
-        }
-    }
-
-    /// Clear the signature so it is identical to a fresh one returned by `new()`.
-    pub fn clear(&mut self, call_conv: CallConv) {
-        self.params.clear();
-        self.returns.clear();
-        self.call_conv = call_conv;
-    }
-
-    /// Find the index of a presumed unique special-purpose parameter.
-    pub fn special_param_index(&self, purpose: ArgumentPurpose) -> Option<usize> {
-        self.params.iter().rposition(|arg| arg.purpose == purpose)
-    }
-
-    /// Find the index of a presumed unique special-purpose parameter.
-    pub fn special_return_index(&self, purpose: ArgumentPurpose) -> Option<usize> {
-        self.returns.iter().rposition(|arg| arg.purpose == purpose)
-    }
-
-    /// Does this signature have a parameter whose `ArgumentPurpose` is
-    /// `purpose`?
-    pub fn uses_special_param(&self, purpose: ArgumentPurpose) -> bool {
-        self.special_param_index(purpose).is_some()
-    }
-
-    /// Does this signature have a return whose `ArgumentPurpose` is `purpose`?
-    pub fn uses_special_return(&self, purpose: ArgumentPurpose) -> bool {
-        self.special_return_index(purpose).is_some()
-    }
-
-    /// How many special parameters does this function have?
-    pub fn num_special_params(&self) -> usize {
-        self.params
-            .iter()
-            .filter(|p| p.purpose != ArgumentPurpose::Normal)
-            .count()
-    }
-
-    /// How many special returns does this function have?
-    pub fn num_special_returns(&self) -> usize {
-        self.returns
-            .iter()
-            .filter(|r| r.purpose != ArgumentPurpose::Normal)
-            .count()
-    }
-
-    /// Does this signature take an struct return pointer parameter?
-    pub fn uses_struct_return_param(&self) -> bool {
-        self.uses_special_param(ArgumentPurpose::StructReturn)
-    }
-
-    /// Does this return more than one normal value? (Pre-struct return
-    /// legalization)
-    pub fn is_multi_return(&self) -> bool {
-        self.returns
-            .iter()
-            .filter(|r| r.purpose == ArgumentPurpose::Normal)
-            .count()
-            > 1
-    }
-}
-
-fn write_list(f: &mut fmt::Formatter, args: &[AbiParam]) -> fmt::Result {
-    match args.split_first() {
-        None => {}
-        Some((first, rest)) => {
-            write!(f, "{}", first)?;
-            for arg in rest {
-                write!(f, ", {}", arg)?;
-            }
-        }
-    }
-    Ok(())
-}
-
-impl fmt::Display for Signature {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        write!(f, "(")?;
-        write_list(f, &self.params)?;
-        write!(f, ")")?;
-        if !self.returns.is_empty() {
-            write!(f, " -> ")?;
-            write_list(f, &self.returns)?;
-        }
-        write!(f, " {}", self.call_conv)
-    }
-}
-
-/// Function parameter or return value descriptor.
-///
-/// This describes the value type being passed to or from a function along with flags that affect
-/// how the argument is passed.
-#[derive(Copy, Clone, Debug, PartialEq, Eq, Hash)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub struct AbiParam {
-    /// Type of the argument value.
-    pub value_type: Type,
-    /// Special purpose of argument, or `Normal`.
-    pub purpose: ArgumentPurpose,
-    /// Method for extending argument to a full register.
-    pub extension: ArgumentExtension,
-
-    /// Was the argument converted to pointer during legalization?
-    pub legalized_to_pointer: bool,
-}
-
-impl AbiParam {
-    /// Create a parameter with default flags.
-    pub fn new(vt: Type) -> Self {
-        Self {
-            value_type: vt,
-            extension: ArgumentExtension::None,
-            purpose: ArgumentPurpose::Normal,
-            legalized_to_pointer: false,
-        }
-    }
-
-    /// Create a special-purpose parameter that is not (yet) bound to a specific register.
-    pub fn special(vt: Type, purpose: ArgumentPurpose) -> Self {
-        Self {
-            value_type: vt,
-            extension: ArgumentExtension::None,
-            purpose,
-            legalized_to_pointer: false,
-        }
-    }
-
-    /// Convert `self` to a parameter with the `uext` flag set.
-    pub fn uext(self) -> Self {
-        debug_assert!(self.value_type.is_int(), "uext on {} arg", self.value_type);
-        Self {
-            extension: ArgumentExtension::Uext,
-            ..self
-        }
-    }
-
-    /// Convert `self` to a parameter type with the `sext` flag set.
-    pub fn sext(self) -> Self {
-        debug_assert!(self.value_type.is_int(), "sext on {} arg", self.value_type);
-        Self {
-            extension: ArgumentExtension::Sext,
-            ..self
-        }
-    }
-}
-
-impl fmt::Display for AbiParam {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        write!(f, "{}", self.value_type)?;
-        if self.legalized_to_pointer {
-            write!(f, " ptr")?;
-        }
-        match self.extension {
-            ArgumentExtension::None => {}
-            ArgumentExtension::Uext => write!(f, " uext")?,
-            ArgumentExtension::Sext => write!(f, " sext")?,
-        }
-        if self.purpose != ArgumentPurpose::Normal {
-            write!(f, " {}", self.purpose)?;
-        }
-        Ok(())
-    }
-}
-
-/// Function argument extension options.
-///
-/// On some architectures, small integer function arguments and/or return values are extended to
-/// the width of a general-purpose register.
-///
-/// This attribute specifies how an argument or return value should be extended *if the platform
-/// and ABI require it*. Because the frontend (CLIF generator) does not know anything about the
-/// particulars of the target's ABI, and the CLIF should be platform-independent, these attributes
-/// specify *how* to extend (according to the signedness of the original program) rather than
-/// *whether* to extend.
-///
-/// For example, on x86-64, the SystemV ABI does not require extensions of narrow values, so these
-/// `ArgumentExtension` attributes are ignored; but in the Baldrdash (SpiderMonkey) ABI on the same
-/// platform, all narrow values *are* extended, so these attributes may lead to extra
-/// zero/sign-extend instructions in the generated machine code.
-#[derive(Copy, Clone, PartialEq, Eq, Debug, Hash)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub enum ArgumentExtension {
-    /// No extension, high bits are indeterminate.
-    None,
-    /// Unsigned extension: high bits in register are 0.
-    Uext,
-    /// Signed extension: high bits in register replicate sign bit.
-    Sext,
-}
-
-/// The special purpose of a function argument.
-///
-/// Function arguments and return values are used to pass user program values between functions,
-/// but they are also used to represent special registers with significance to the ABI such as
-/// frame pointers and callee-saved registers.
-///
-/// The argument purpose is used to indicate any special meaning of an argument or return value.
-#[derive(Copy, Clone, PartialEq, Eq, Debug, Hash)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub enum ArgumentPurpose {
-    /// A normal user program value passed to or from a function.
-    Normal,
-
-    /// A C struct passed as argument.
-    StructArgument(u32),
-
-    /// Struct return pointer.
-    ///
-    /// When a function needs to return more data than will fit in registers, the caller passes a
-    /// pointer to a memory location where the return value can be written. In some ABIs, this
-    /// struct return pointer is passed in a specific register.
-    ///
-    /// This argument kind can also appear as a return value for ABIs that require a function with
-    /// a `StructReturn` pointer argument to also return that pointer in a register.
-    StructReturn,
-
-    /// The link register.
-    ///
-    /// Most RISC architectures implement calls by saving the return address in a designated
-    /// register rather than pushing it on the stack. This is represented with a `Link` argument.
-    ///
-    /// Similarly, some return instructions expect the return address in a register represented as
-    /// a `Link` return value.
-    Link,
-
-    /// The frame pointer.
-    ///
-    /// This indicates the frame pointer register which has a special meaning in some ABIs.
-    ///
-    /// The frame pointer appears as an argument and as a return value since it is a callee-saved
-    /// register.
-    FramePointer,
-
-    /// A callee-saved register.
-    ///
-    /// Some calling conventions have registers that must be saved by the callee. These registers
-    /// are represented as `CalleeSaved` arguments and return values.
-    CalleeSaved,
-
-    /// A VM context pointer.
-    ///
-    /// This is a pointer to a context struct containing details about the current sandbox. It is
-    /// used as a base pointer for `vmctx` global values.
-    VMContext,
-
-    /// A signature identifier.
-    ///
-    /// This is a special-purpose argument used to identify the calling convention expected by the
-    /// caller in an indirect call. The callee can verify that the expected signature ID matches.
-    SignatureId,
-
-    /// A stack limit pointer.
-    ///
-    /// This is a pointer to a stack limit. It is used to check the current stack pointer
-    /// against. Can only appear once in a signature.
-    StackLimit,
-
-    /// A callee TLS value.
-    ///
-    /// In the Baldrdash-2020 calling convention, the stack upon entry to the callee contains the
-    /// TLS-register values for the caller and the callee. This argument is used to provide the
-    /// value for the callee.
-    CalleeTLS,
-
-    /// A caller TLS value.
-    ///
-    /// In the Baldrdash-2020 calling convention, the stack upon entry to the callee contains the
-    /// TLS-register values for the caller and the callee. This argument is used to provide the
-    /// value for the caller.
-    CallerTLS,
-}
-
-impl fmt::Display for ArgumentPurpose {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        f.write_str(match self {
-            Self::Normal => "normal",
-            Self::StructArgument(size) => return write!(f, "sarg({})", size),
-            Self::StructReturn => "sret",
-            Self::Link => "link",
-            Self::FramePointer => "fp",
-            Self::CalleeSaved => "csr",
-            Self::VMContext => "vmctx",
-            Self::SignatureId => "sigid",
-            Self::StackLimit => "stack_limit",
-            Self::CalleeTLS => "callee_tls",
-            Self::CallerTLS => "caller_tls",
-        })
-    }
-}
-
-impl FromStr for ArgumentPurpose {
-    type Err = ();
-    fn from_str(s: &str) -> Result<Self, ()> {
-        match s {
-            "normal" => Ok(Self::Normal),
-            "sret" => Ok(Self::StructReturn),
-            "link" => Ok(Self::Link),
-            "fp" => Ok(Self::FramePointer),
-            "csr" => Ok(Self::CalleeSaved),
-            "vmctx" => Ok(Self::VMContext),
-            "sigid" => Ok(Self::SignatureId),
-            "stack_limit" => Ok(Self::StackLimit),
-            _ if s.starts_with("sarg(") => {
-                if !s.ends_with(")") {
-                    return Err(());
-                }
-                // Parse 'sarg(size)'
-                let size: u32 = s["sarg(".len()..s.len() - 1].parse().map_err(|_| ())?;
-                Ok(Self::StructArgument(size))
-            }
-            _ => Err(()),
-        }
-    }
-}
-
-/// An external function.
-///
-/// Information about a function that can be called directly with a direct `call` instruction.
-#[derive(Clone, Debug)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub struct ExtFuncData {
-    /// Name of the external function.
-    pub name: ExternalName,
-    /// Call signature of function.
-    pub signature: SigRef,
-    /// Will this function be defined nearby, such that it will always be a certain distance away,
-    /// after linking? If so, references to it can avoid going through a GOT or PLT. Note that
-    /// symbols meant to be preemptible cannot be considered colocated.
-    ///
-    /// If `true`, some backends may use relocation forms that have limited range. The exact
-    /// distance depends on the code model in use. Currently on AArch64, for example, Cranelift
-    /// uses a custom code model supporting up to +/- 128MB displacements. If it is unknown how
-    /// far away the target will be, it is best not to set the `colocated` flag; in general, this
-    /// flag is best used when the target is known to be in the same unit of code generation, such
-    /// as a Wasm module.
-    ///
-    /// See the documentation for [`RelocDistance`](crate::machinst::RelocDistance) for more details. A
-    /// `colocated` flag value of `true` implies `RelocDistance::Near`.
-    pub colocated: bool,
-}
-
-impl fmt::Display for ExtFuncData {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        if self.colocated {
-            write!(f, "colocated ")?;
-        }
-        write!(f, "{} {}", self.name, self.signature)
-    }
-}
-
-impl ExtFuncData {
-    /// Return an estimate of the distance to the referred-to function symbol.
-    pub fn reloc_distance(&self) -> RelocDistance {
-        if self.colocated {
-            RelocDistance::Near
-        } else {
-            RelocDistance::Far
-        }
-    }
-}
-
-#[cfg(test)]
-mod tests {
-    use super::*;
-    use crate::ir::types::{B8, F32, I32};
-    use alloc::string::ToString;
-
-    #[test]
-    fn argument_type() {
-        let t = AbiParam::new(I32);
-        assert_eq!(t.to_string(), "i32");
-        let mut t = t.uext();
-        assert_eq!(t.to_string(), "i32 uext");
-        assert_eq!(t.sext().to_string(), "i32 sext");
-        t.purpose = ArgumentPurpose::StructReturn;
-        assert_eq!(t.to_string(), "i32 uext sret");
-        t.legalized_to_pointer = true;
-        assert_eq!(t.to_string(), "i32 ptr uext sret");
-    }
-
-    #[test]
-    fn argument_purpose() {
-        let all_purpose = [
-            (ArgumentPurpose::Normal, "normal"),
-            (ArgumentPurpose::StructReturn, "sret"),
-            (ArgumentPurpose::Link, "link"),
-            (ArgumentPurpose::FramePointer, "fp"),
-            (ArgumentPurpose::CalleeSaved, "csr"),
-            (ArgumentPurpose::VMContext, "vmctx"),
-            (ArgumentPurpose::SignatureId, "sigid"),
-            (ArgumentPurpose::StackLimit, "stack_limit"),
-            (ArgumentPurpose::StructArgument(42), "sarg(42)"),
-        ];
-        for &(e, n) in &all_purpose {
-            assert_eq!(e.to_string(), n);
-            assert_eq!(Ok(e), n.parse());
-        }
-    }
-
-    #[test]
-    fn call_conv() {
-        for &cc in &[
-            CallConv::Fast,
-            CallConv::Cold,
-            CallConv::SystemV,
-            CallConv::WindowsFastcall,
-            CallConv::BaldrdashSystemV,
-            CallConv::BaldrdashWindows,
-            CallConv::Baldrdash2020,
-        ] {
-            assert_eq!(Ok(cc), cc.to_string().parse())
-        }
-    }
-
-    #[test]
-    fn signatures() {
-        let mut sig = Signature::new(CallConv::BaldrdashSystemV);
-        assert_eq!(sig.to_string(), "() baldrdash_system_v");
-        sig.params.push(AbiParam::new(I32));
-        assert_eq!(sig.to_string(), "(i32) baldrdash_system_v");
-        sig.returns.push(AbiParam::new(F32));
-        assert_eq!(sig.to_string(), "(i32) -> f32 baldrdash_system_v");
-        sig.params.push(AbiParam::new(I32.by(4).unwrap()));
-        assert_eq!(sig.to_string(), "(i32, i32x4) -> f32 baldrdash_system_v");
-        sig.returns.push(AbiParam::new(B8));
-        assert_eq!(
-            sig.to_string(),
-            "(i32, i32x4) -> f32, b8 baldrdash_system_v"
-        );
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/extname.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/extname.rs
deleted file mode 100644
index 362cf8c67..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/extname.rs
+++ /dev/null
@@ -1,167 +0,0 @@
-//! External names.
-//!
-//! These are identifiers for declaring entities defined outside the current
-//! function. The name of an external declaration doesn't have any meaning to
-//! Cranelift, which compiles functions independently.
-
-use crate::ir::LibCall;
-use core::cmp;
-use core::fmt::{self, Write};
-use core::str::FromStr;
-
-#[cfg(feature = "enable-serde")]
-use serde::{Deserialize, Serialize};
-
-const TESTCASE_NAME_LENGTH: usize = 16;
-
-/// The name of an external is either a reference to a user-defined symbol
-/// table, or a short sequence of ascii bytes so that test cases do not have
-/// to keep track of a symbol table.
-///
-/// External names are primarily used as keys by code using Cranelift to map
-/// from a `cranelift_codegen::ir::FuncRef` or similar to additional associated
-/// data.
-///
-/// External names can also serve as a primitive testing and debugging tool.
-/// In particular, many `.clif` test files use function names to identify
-/// functions.
-#[derive(Debug, Clone, PartialEq, Eq)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub enum ExternalName {
-    /// A name in a user-defined symbol table. Cranelift does not interpret
-    /// these numbers in any way.
-    User {
-        /// Arbitrary.
-        namespace: u32,
-        /// Arbitrary.
-        index: u32,
-    },
-    /// A test case function name of up to a hardcoded amount of ascii
-    /// characters. This is not intended to be used outside test cases.
-    TestCase {
-        /// How many of the bytes in `ascii` are valid?
-        length: u8,
-        /// Ascii bytes of the name.
-        ascii: [u8; TESTCASE_NAME_LENGTH],
-    },
-    /// A well-known runtime library function.
-    LibCall(LibCall),
-}
-
-impl ExternalName {
-    /// Creates a new external name from a sequence of bytes. Caller is expected
-    /// to guarantee bytes are only ascii alphanumeric or `_`.
-    ///
-    /// # Examples
-    ///
-    /// ```rust
-    /// # use cranelift_codegen::ir::ExternalName;
-    /// // Create `ExternalName` from a string.
-    /// let name = ExternalName::testcase("hello");
-    /// assert_eq!(name.to_string(), "%hello");
-    /// ```
-    pub fn testcase<T: AsRef<[u8]>>(v: T) -> Self {
-        let vec = v.as_ref();
-        let len = cmp::min(vec.len(), TESTCASE_NAME_LENGTH);
-        let mut bytes = [0u8; TESTCASE_NAME_LENGTH];
-        bytes[0..len].copy_from_slice(&vec[0..len]);
-
-        Self::TestCase {
-            length: len as u8,
-            ascii: bytes,
-        }
-    }
-
-    /// Create a new external name from user-provided integer indices.
-    ///
-    /// # Examples
-    /// ```rust
-    /// # use cranelift_codegen::ir::ExternalName;
-    /// // Create `ExternalName` from integer indices
-    /// let name = ExternalName::user(123, 456);
-    /// assert_eq!(name.to_string(), "u123:456");
-    /// ```
-    pub fn user(namespace: u32, index: u32) -> Self {
-        Self::User { namespace, index }
-    }
-}
-
-impl Default for ExternalName {
-    fn default() -> Self {
-        Self::user(0, 0)
-    }
-}
-
-impl fmt::Display for ExternalName {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        match *self {
-            Self::User { namespace, index } => write!(f, "u{}:{}", namespace, index),
-            Self::TestCase { length, ascii } => {
-                f.write_char('%')?;
-                for byte in ascii.iter().take(length as usize) {
-                    f.write_char(*byte as char)?;
-                }
-                Ok(())
-            }
-            Self::LibCall(lc) => write!(f, "%{}", lc),
-        }
-    }
-}
-
-impl FromStr for ExternalName {
-    type Err = ();
-
-    fn from_str(s: &str) -> Result<Self, Self::Err> {
-        // Try to parse as a libcall name, otherwise it's a test case.
-        match s.parse() {
-            Ok(lc) => Ok(Self::LibCall(lc)),
-            Err(_) => Ok(Self::testcase(s.as_bytes())),
-        }
-    }
-}
-
-#[cfg(test)]
-mod tests {
-    use super::ExternalName;
-    use crate::ir::LibCall;
-    use alloc::string::ToString;
-    use core::u32;
-
-    #[test]
-    fn display_testcase() {
-        assert_eq!(ExternalName::testcase("").to_string(), "%");
-        assert_eq!(ExternalName::testcase("x").to_string(), "%x");
-        assert_eq!(ExternalName::testcase("x_1").to_string(), "%x_1");
-        assert_eq!(
-            ExternalName::testcase("longname12345678").to_string(),
-            "%longname12345678"
-        );
-        // Constructor will silently drop bytes beyond the 16th
-        assert_eq!(
-            ExternalName::testcase("longname123456789").to_string(),
-            "%longname12345678"
-        );
-    }
-
-    #[test]
-    fn display_user() {
-        assert_eq!(ExternalName::user(0, 0).to_string(), "u0:0");
-        assert_eq!(ExternalName::user(1, 1).to_string(), "u1:1");
-        assert_eq!(
-            ExternalName::user(u32::MAX, u32::MAX).to_string(),
-            "u4294967295:4294967295"
-        );
-    }
-
-    #[test]
-    fn parsing() {
-        assert_eq!(
-            "FloorF32".parse(),
-            Ok(ExternalName::LibCall(LibCall::FloorF32))
-        );
-        assert_eq!(
-            ExternalName::LibCall(LibCall::FloorF32).to_string(),
-            "%FloorF32"
-        );
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/function.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/function.rs
deleted file mode 100644
index 0092a3330..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/function.rs
+++ /dev/null
@@ -1,356 +0,0 @@
-//! Intermediate representation of a function.
-//!
-//! The `Function` struct defined in this module owns all of its basic blocks and
-//! instructions.
-
-use crate::entity::{PrimaryMap, SecondaryMap};
-use crate::ir;
-use crate::ir::JumpTables;
-use crate::ir::{
-    instructions::BranchInfo, Block, ExtFuncData, FuncRef, GlobalValue, GlobalValueData, Heap,
-    HeapData, Inst, InstructionData, JumpTable, JumpTableData, Opcode, SigRef, StackSlot,
-    StackSlotData, Table, TableData,
-};
-use crate::ir::{DataFlowGraph, ExternalName, Layout, Signature};
-use crate::ir::{SourceLocs, StackSlots};
-use crate::isa::CallConv;
-use crate::value_label::ValueLabelsRanges;
-use crate::write::write_function;
-#[cfg(feature = "enable-serde")]
-use alloc::string::String;
-use core::fmt;
-
-#[cfg(feature = "enable-serde")]
-use serde::de::{Deserializer, Error};
-#[cfg(feature = "enable-serde")]
-use serde::ser::Serializer;
-#[cfg(feature = "enable-serde")]
-use serde::{Deserialize, Serialize};
-
-/// A version marker used to ensure that serialized clif ir is never deserialized with a
-/// different version of Cranelift.
-#[derive(Copy, Clone, Debug)]
-pub struct VersionMarker;
-
-#[cfg(feature = "enable-serde")]
-impl Serialize for VersionMarker {
-    fn serialize<S>(&self, serializer: S) -> Result<S::Ok, S::Error>
-    where
-        S: Serializer,
-    {
-        crate::VERSION.serialize(serializer)
-    }
-}
-
-#[cfg(feature = "enable-serde")]
-impl<'de> Deserialize<'de> for VersionMarker {
-    fn deserialize<D>(deserializer: D) -> Result<Self, D::Error>
-    where
-        D: Deserializer<'de>,
-    {
-        let version = String::deserialize(deserializer)?;
-        if version != crate::VERSION {
-            return Err(D::Error::custom(&format!(
-                "Expected a clif ir function for version {}, found one for version {}",
-                crate::VERSION,
-                version,
-            )));
-        }
-        Ok(VersionMarker)
-    }
-}
-
-///
-/// Functions can be cloned, but it is not a very fast operation.
-/// The clone will have all the same entity numbers as the original.
-#[derive(Clone)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub struct Function {
-    /// A version marker used to ensure that serialized clif ir is never deserialized with a
-    /// different version of Cranelift.
-    // Note: This must be the first field to ensure that Serde will deserialize it before
-    // attempting to deserialize other fields that are potentially changed between versions.
-    pub version_marker: VersionMarker,
-
-    /// Name of this function. Mostly used by `.clif` files.
-    pub name: ExternalName,
-
-    /// Signature of this function.
-    pub signature: Signature,
-
-    /// Stack slots allocated in this function.
-    pub stack_slots: StackSlots,
-
-    /// Global values referenced.
-    pub global_values: PrimaryMap<ir::GlobalValue, ir::GlobalValueData>,
-
-    /// Heaps referenced.
-    pub heaps: PrimaryMap<ir::Heap, ir::HeapData>,
-
-    /// Tables referenced.
-    pub tables: PrimaryMap<ir::Table, ir::TableData>,
-
-    /// Jump tables used in this function.
-    pub jump_tables: JumpTables,
-
-    /// Data flow graph containing the primary definition of all instructions, blocks and values.
-    pub dfg: DataFlowGraph,
-
-    /// Layout of blocks and instructions in the function body.
-    pub layout: Layout,
-
-    /// Source locations.
-    ///
-    /// Track the original source location for each instruction. The source locations are not
-    /// interpreted by Cranelift, only preserved.
-    pub srclocs: SourceLocs,
-
-    /// An optional global value which represents an expression evaluating to
-    /// the stack limit for this function. This `GlobalValue` will be
-    /// interpreted in the prologue, if necessary, to insert a stack check to
-    /// ensure that a trap happens if the stack pointer goes below the
-    /// threshold specified here.
-    pub stack_limit: Option<ir::GlobalValue>,
-}
-
-impl Function {
-    /// Create a function with the given name and signature.
-    pub fn with_name_signature(name: ExternalName, sig: Signature) -> Self {
-        Self {
-            version_marker: VersionMarker,
-            name,
-            signature: sig,
-            stack_slots: StackSlots::new(),
-            global_values: PrimaryMap::new(),
-            heaps: PrimaryMap::new(),
-            tables: PrimaryMap::new(),
-            jump_tables: PrimaryMap::new(),
-            dfg: DataFlowGraph::new(),
-            layout: Layout::new(),
-            srclocs: SecondaryMap::new(),
-            stack_limit: None,
-        }
-    }
-
-    /// Clear all data structures in this function.
-    pub fn clear(&mut self) {
-        self.signature.clear(CallConv::Fast);
-        self.stack_slots.clear();
-        self.global_values.clear();
-        self.heaps.clear();
-        self.tables.clear();
-        self.jump_tables.clear();
-        self.dfg.clear();
-        self.layout.clear();
-        self.srclocs.clear();
-        self.stack_limit = None;
-    }
-
-    /// Create a new empty, anonymous function with a Fast calling convention.
-    pub fn new() -> Self {
-        Self::with_name_signature(ExternalName::default(), Signature::new(CallConv::Fast))
-    }
-
-    /// Creates a jump table in the function, to be used by `br_table` instructions.
-    pub fn create_jump_table(&mut self, data: JumpTableData) -> JumpTable {
-        self.jump_tables.push(data)
-    }
-
-    /// Creates a stack slot in the function, to be used by `stack_load`, `stack_store` and
-    /// `stack_addr` instructions.
-    pub fn create_stack_slot(&mut self, data: StackSlotData) -> StackSlot {
-        self.stack_slots.push(data)
-    }
-
-    /// Adds a signature which can later be used to declare an external function import.
-    pub fn import_signature(&mut self, signature: Signature) -> SigRef {
-        self.dfg.signatures.push(signature)
-    }
-
-    /// Declare an external function import.
-    pub fn import_function(&mut self, data: ExtFuncData) -> FuncRef {
-        self.dfg.ext_funcs.push(data)
-    }
-
-    /// Declares a global value accessible to the function.
-    pub fn create_global_value(&mut self, data: GlobalValueData) -> GlobalValue {
-        self.global_values.push(data)
-    }
-
-    /// Declares a heap accessible to the function.
-    pub fn create_heap(&mut self, data: HeapData) -> Heap {
-        self.heaps.push(data)
-    }
-
-    /// Declares a table accessible to the function.
-    pub fn create_table(&mut self, data: TableData) -> Table {
-        self.tables.push(data)
-    }
-
-    /// Return an object that can display this function with correct ISA-specific annotations.
-    pub fn display(&self) -> DisplayFunction<'_> {
-        DisplayFunction(self, Default::default())
-    }
-
-    /// Return an object that can display this function with correct ISA-specific annotations.
-    pub fn display_with<'a>(
-        &'a self,
-        annotations: DisplayFunctionAnnotations<'a>,
-    ) -> DisplayFunction<'a> {
-        DisplayFunction(self, annotations)
-    }
-
-    /// Find a presumed unique special-purpose function parameter value.
-    ///
-    /// Returns the value of the last `purpose` parameter, or `None` if no such parameter exists.
-    pub fn special_param(&self, purpose: ir::ArgumentPurpose) -> Option<ir::Value> {
-        let entry = self.layout.entry_block().expect("Function is empty");
-        self.signature
-            .special_param_index(purpose)
-            .map(|i| self.dfg.block_params(entry)[i])
-    }
-
-    /// Starts collection of debug information.
-    pub fn collect_debug_info(&mut self) {
-        self.dfg.collect_debug_info();
-    }
-
-    /// Changes the destination of a jump or branch instruction.
-    /// Does nothing if called with a non-jump or non-branch instruction.
-    ///
-    /// Note that this method ignores multi-destination branches like `br_table`.
-    pub fn change_branch_destination(&mut self, inst: Inst, new_dest: Block) {
-        match self.dfg[inst].branch_destination_mut() {
-            None => (),
-            Some(inst_dest) => *inst_dest = new_dest,
-        }
-    }
-
-    /// Rewrite the branch destination to `new_dest` if the destination matches `old_dest`.
-    /// Does nothing if called with a non-jump or non-branch instruction.
-    ///
-    /// Unlike [change_branch_destination](Function::change_branch_destination), this method rewrite the destinations of
-    /// multi-destination branches like `br_table`.
-    pub fn rewrite_branch_destination(&mut self, inst: Inst, old_dest: Block, new_dest: Block) {
-        match self.dfg.analyze_branch(inst) {
-            BranchInfo::SingleDest(dest, ..) => {
-                if dest == old_dest {
-                    self.change_branch_destination(inst, new_dest);
-                }
-            }
-
-            BranchInfo::Table(table, default_dest) => {
-                self.jump_tables[table].iter_mut().for_each(|entry| {
-                    if *entry == old_dest {
-                        *entry = new_dest;
-                    }
-                });
-
-                if default_dest == Some(old_dest) {
-                    match &mut self.dfg[inst] {
-                        InstructionData::BranchTable { destination, .. } => {
-                            *destination = new_dest;
-                        }
-                        _ => panic!(
-                            "Unexpected instruction {} having default destination",
-                            self.dfg.display_inst(inst)
-                        ),
-                    }
-                }
-            }
-
-            BranchInfo::NotABranch => {}
-        }
-    }
-
-    /// Checks that the specified block can be encoded as a basic block.
-    ///
-    /// On error, returns the first invalid instruction and an error message.
-    pub fn is_block_basic(&self, block: Block) -> Result<(), (Inst, &'static str)> {
-        let dfg = &self.dfg;
-        let inst_iter = self.layout.block_insts(block);
-
-        // Ignore all instructions prior to the first branch.
-        let mut inst_iter = inst_iter.skip_while(|&inst| !dfg[inst].opcode().is_branch());
-
-        // A conditional branch is permitted in a basic block only when followed
-        // by a terminal jump instruction.
-        if let Some(_branch) = inst_iter.next() {
-            if let Some(next) = inst_iter.next() {
-                match dfg[next].opcode() {
-                    Opcode::Jump => (),
-                    _ => return Err((next, "post-branch instruction not jump")),
-                }
-            }
-        }
-
-        Ok(())
-    }
-
-    /// Returns true if the function is function that doesn't call any other functions. This is not
-    /// to be confused with a "leaf function" in Windows terminology.
-    pub fn is_leaf(&self) -> bool {
-        // Conservative result: if there's at least one function signature referenced in this
-        // function, assume it is not a leaf.
-        self.dfg.signatures.is_empty()
-    }
-
-    /// Replace the `dst` instruction's data with the `src` instruction's data
-    /// and then remove `src`.
-    ///
-    /// `src` and its result values should not be used at all, as any uses would
-    /// be left dangling after calling this method.
-    ///
-    /// `src` and `dst` must have the same number of resulting values, and
-    /// `src`'s i^th value must have the same type as `dst`'s i^th value.
-    pub fn transplant_inst(&mut self, dst: Inst, src: Inst) {
-        debug_assert_eq!(
-            self.dfg.inst_results(dst).len(),
-            self.dfg.inst_results(src).len()
-        );
-        debug_assert!(self
-            .dfg
-            .inst_results(dst)
-            .iter()
-            .zip(self.dfg.inst_results(src))
-            .all(|(a, b)| self.dfg.value_type(*a) == self.dfg.value_type(*b)));
-
-        self.dfg[dst] = self.dfg[src].clone();
-        self.layout.remove_inst(src);
-    }
-
-    /// Size occupied by all stack slots associated with this function.
-    ///
-    /// Does not include any padding necessary due to offsets
-    pub fn stack_size(&self) -> u32 {
-        self.stack_slots.values().map(|ss| ss.size).sum()
-    }
-}
-
-/// Additional annotations for function display.
-#[derive(Default)]
-pub struct DisplayFunctionAnnotations<'a> {
-    /// Enable value labels annotations.
-    pub value_ranges: Option<&'a ValueLabelsRanges>,
-}
-
-/// Wrapper type capable of displaying a `Function` with correct ISA annotations.
-pub struct DisplayFunction<'a>(&'a Function, DisplayFunctionAnnotations<'a>);
-
-impl<'a> fmt::Display for DisplayFunction<'a> {
-    fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result {
-        write_function(fmt, self.0)
-    }
-}
-
-impl fmt::Display for Function {
-    fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result {
-        write_function(fmt, self)
-    }
-}
-
-impl fmt::Debug for Function {
-    fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result {
-        write_function(fmt, self)
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/globalvalue.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/globalvalue.rs
deleted file mode 100644
index e70f8221f..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/globalvalue.rs
+++ /dev/null
@@ -1,159 +0,0 @@
-//! Global values.
-
-use crate::ir::immediates::{Imm64, Offset32};
-use crate::ir::{ExternalName, GlobalValue, Type};
-use crate::isa::TargetIsa;
-use crate::machinst::RelocDistance;
-use core::fmt;
-
-#[cfg(feature = "enable-serde")]
-use serde::{Deserialize, Serialize};
-
-/// Information about a global value declaration.
-#[derive(Clone)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub enum GlobalValueData {
-    /// Value is the address of the VM context struct.
-    VMContext,
-
-    /// Value is pointed to by another global value.
-    ///
-    /// The `base` global value is assumed to contain a pointer. This global value is computed
-    /// by loading from memory at that pointer value. The memory must be accessible, and
-    /// naturally aligned to hold a value of the type. The data at this address is assumed
-    /// to never change while the current function is executing.
-    Load {
-        /// The base pointer global value.
-        base: GlobalValue,
-
-        /// Offset added to the base pointer before doing the load.
-        offset: Offset32,
-
-        /// Type of the loaded value.
-        global_type: Type,
-
-        /// Specifies whether the memory that this refers to is readonly, allowing for the
-        /// elimination of redundant loads.
-        readonly: bool,
-    },
-
-    /// Value is an offset from another global value.
-    IAddImm {
-        /// The base pointer global value.
-        base: GlobalValue,
-
-        /// Byte offset to be added to the value.
-        offset: Imm64,
-
-        /// Type of the iadd.
-        global_type: Type,
-    },
-
-    /// Value is symbolic, meaning it's a name which will be resolved to an
-    /// actual value later (eg. by linking). Cranelift itself does not interpret
-    /// this name; it's used by embedders to link with other data structures.
-    ///
-    /// For now, symbolic values always have pointer type, and represent
-    /// addresses, however in the future they could be used to represent other
-    /// things as well.
-    Symbol {
-        /// The symbolic name.
-        name: ExternalName,
-
-        /// Offset from the symbol. This can be used instead of IAddImm to represent folding an
-        /// offset into a symbol.
-        offset: Imm64,
-
-        /// Will this symbol be defined nearby, such that it will always be a certain distance
-        /// away, after linking? If so, references to it can avoid going through a GOT. Note that
-        /// symbols meant to be preemptible cannot be colocated.
-        ///
-        /// If `true`, some backends may use relocation forms that have limited range: for example,
-        /// a +/- 2^27-byte range on AArch64. See the documentation for
-        /// [`RelocDistance`](crate::machinst::RelocDistance) for more details.
-        colocated: bool,
-
-        /// Does this symbol refer to a thread local storage value?
-        tls: bool,
-    },
-}
-
-impl GlobalValueData {
-    /// Assume that `self` is an `GlobalValueData::Symbol` and return its name.
-    pub fn symbol_name(&self) -> &ExternalName {
-        match *self {
-            Self::Symbol { ref name, .. } => name,
-            _ => panic!("only symbols have names"),
-        }
-    }
-
-    /// Return the type of this global.
-    pub fn global_type(&self, isa: &dyn TargetIsa) -> Type {
-        match *self {
-            Self::VMContext { .. } | Self::Symbol { .. } => isa.pointer_type(),
-            Self::IAddImm { global_type, .. } | Self::Load { global_type, .. } => global_type,
-        }
-    }
-
-    /// If this global references a symbol, return an estimate of the relocation distance,
-    /// based on the `colocated` flag.
-    pub fn maybe_reloc_distance(&self) -> Option<RelocDistance> {
-        match self {
-            &GlobalValueData::Symbol {
-                colocated: true, ..
-            } => Some(RelocDistance::Near),
-            &GlobalValueData::Symbol {
-                colocated: false, ..
-            } => Some(RelocDistance::Far),
-            _ => None,
-        }
-    }
-}
-
-impl fmt::Display for GlobalValueData {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        match *self {
-            Self::VMContext => write!(f, "vmctx"),
-            Self::Load {
-                base,
-                offset,
-                global_type,
-                readonly,
-            } => write!(
-                f,
-                "load.{} notrap aligned {}{}{}",
-                global_type,
-                if readonly { "readonly " } else { "" },
-                base,
-                offset
-            ),
-            Self::IAddImm {
-                global_type,
-                base,
-                offset,
-            } => write!(f, "iadd_imm.{} {}, {}", global_type, base, offset),
-            Self::Symbol {
-                ref name,
-                offset,
-                colocated,
-                tls,
-            } => {
-                write!(
-                    f,
-                    "symbol {}{}{}",
-                    if colocated { "colocated " } else { "" },
-                    if tls { "tls " } else { "" },
-                    name
-                )?;
-                let offset_val: i64 = offset.into();
-                if offset_val > 0 {
-                    write!(f, "+")?;
-                }
-                if offset_val != 0 {
-                    write!(f, "{}", offset)?;
-                }
-                Ok(())
-            }
-        }
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/heap.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/heap.rs
deleted file mode 100644
index 91aabccaa..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/heap.rs
+++ /dev/null
@@ -1,67 +0,0 @@
-//! Heaps.
-
-use crate::ir::immediates::Uimm64;
-use crate::ir::{GlobalValue, Type};
-use core::fmt;
-
-#[cfg(feature = "enable-serde")]
-use serde::{Deserialize, Serialize};
-
-/// Information about a heap declaration.
-#[derive(Clone)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub struct HeapData {
-    /// The address of the start of the heap's storage.
-    pub base: GlobalValue,
-
-    /// Guaranteed minimum heap size in bytes. Heap accesses before `min_size` don't need bounds
-    /// checking.
-    pub min_size: Uimm64,
-
-    /// Size in bytes of the offset-guard pages following the heap.
-    pub offset_guard_size: Uimm64,
-
-    /// Heap style, with additional style-specific info.
-    pub style: HeapStyle,
-
-    /// The index type for the heap.
-    pub index_type: Type,
-}
-
-/// Style of heap including style-specific information.
-#[derive(Clone)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub enum HeapStyle {
-    /// A dynamic heap can be relocated to a different base address when it is grown.
-    Dynamic {
-        /// Global value providing the current bound of the heap in bytes.
-        bound_gv: GlobalValue,
-    },
-
-    /// A static heap has a fixed base address and a number of not-yet-allocated pages before the
-    /// offset-guard pages.
-    Static {
-        /// Heap bound in bytes. The offset-guard pages are allocated after the bound.
-        bound: Uimm64,
-    },
-}
-
-impl fmt::Display for HeapData {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        f.write_str(match self.style {
-            HeapStyle::Dynamic { .. } => "dynamic",
-            HeapStyle::Static { .. } => "static",
-        })?;
-
-        write!(f, " {}, min {}", self.base, self.min_size)?;
-        match self.style {
-            HeapStyle::Dynamic { bound_gv } => write!(f, ", bound {}", bound_gv)?,
-            HeapStyle::Static { bound } => write!(f, ", bound {}", bound)?,
-        }
-        write!(
-            f,
-            ", offset_guard {}, index_type {}",
-            self.offset_guard_size, self.index_type
-        )
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/immediates.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/immediates.rs
deleted file mode 100644
index ca9f8a978..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/immediates.rs
+++ /dev/null
@@ -1,1330 +0,0 @@
-//! Immediate operands for Cranelift instructions
-//!
-//! This module defines the types of immediate operands that can appear on Cranelift instructions.
-//! Each type here should have a corresponding definition in the
-//! `cranelift-codegen/meta/src/shared/immediates` crate in the meta language.
-
-use alloc::vec::Vec;
-use core::cmp::Ordering;
-use core::convert::TryFrom;
-use core::fmt::{self, Display, Formatter};
-use core::str::FromStr;
-use core::{i32, u32};
-#[cfg(feature = "enable-serde")]
-use serde::{Deserialize, Serialize};
-
-/// Convert a type into a vector of bytes; all implementors in this file must use little-endian
-/// orderings of bytes to match WebAssembly's little-endianness.
-pub trait IntoBytes {
-    /// Return the little-endian byte representation of the implementing type.
-    fn into_bytes(self) -> Vec<u8>;
-}
-
-impl IntoBytes for u8 {
-    fn into_bytes(self) -> Vec<u8> {
-        vec![self]
-    }
-}
-
-impl IntoBytes for i8 {
-    fn into_bytes(self) -> Vec<u8> {
-        vec![self as u8]
-    }
-}
-
-impl IntoBytes for i16 {
-    fn into_bytes(self) -> Vec<u8> {
-        self.to_le_bytes().to_vec()
-    }
-}
-
-impl IntoBytes for i32 {
-    fn into_bytes(self) -> Vec<u8> {
-        self.to_le_bytes().to_vec()
-    }
-}
-
-impl IntoBytes for Vec<u8> {
-    fn into_bytes(self) -> Vec<u8> {
-        self
-    }
-}
-
-/// 64-bit immediate signed integer operand.
-///
-/// An `Imm64` operand can also be used to represent immediate values of smaller integer types by
-/// sign-extending to `i64`.
-#[derive(Copy, Clone, PartialEq, Eq, Debug, Hash)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub struct Imm64(i64);
-
-impl Imm64 {
-    /// Create a new `Imm64` representing the signed number `x`.
-    pub fn new(x: i64) -> Self {
-        Self(x)
-    }
-
-    /// Return self negated.
-    pub fn wrapping_neg(self) -> Self {
-        Self(self.0.wrapping_neg())
-    }
-
-    /// Returns the value of this immediate.
-    pub fn bits(&self) -> i64 {
-        self.0
-    }
-
-    /// Sign extend this immediate as if it were a signed integer of the given
-    /// power-of-two width.
-    pub fn sign_extend_from_width(&mut self, bit_width: u16) {
-        debug_assert!(bit_width.is_power_of_two());
-
-        if bit_width >= 64 {
-            return;
-        }
-
-        let bit_width = i64::from(bit_width);
-        let delta = 64 - bit_width;
-        let sign_extended = (self.0 << delta) >> delta;
-        *self = Imm64(sign_extended);
-    }
-}
-
-impl From<Imm64> for i64 {
-    fn from(val: Imm64) -> i64 {
-        val.0
-    }
-}
-
-impl IntoBytes for Imm64 {
-    fn into_bytes(self) -> Vec<u8> {
-        self.0.to_le_bytes().to_vec()
-    }
-}
-
-impl From<i64> for Imm64 {
-    fn from(x: i64) -> Self {
-        Self(x)
-    }
-}
-
-impl Display for Imm64 {
-    fn fmt(&self, f: &mut Formatter) -> fmt::Result {
-        let x = self.0;
-        if -10_000 < x && x < 10_000 {
-            // Use decimal for small numbers.
-            write!(f, "{}", x)
-        } else {
-            write_hex(x as u64, f)
-        }
-    }
-}
-
-/// Parse a 64-bit signed number.
-fn parse_i64(s: &str) -> Result<i64, &'static str> {
-    let negative = s.starts_with('-');
-    let s2 = if negative || s.starts_with('+') {
-        &s[1..]
-    } else {
-        s
-    };
-
-    let mut value = parse_u64(s2)?;
-
-    // We support the range-and-a-half from -2^63 .. 2^64-1.
-    if negative {
-        value = value.wrapping_neg();
-        // Don't allow large negative values to wrap around and become positive.
-        if value as i64 > 0 {
-            return Err("Negative number too small");
-        }
-    }
-    Ok(value as i64)
-}
-
-impl FromStr for Imm64 {
-    type Err = &'static str;
-
-    // Parse a decimal or hexadecimal `Imm64`, formatted as above.
-    fn from_str(s: &str) -> Result<Self, &'static str> {
-        parse_i64(s).map(Self::new)
-    }
-}
-
-/// 64-bit immediate unsigned integer operand.
-///
-/// A `Uimm64` operand can also be used to represent immediate values of smaller integer types by
-/// zero-extending to `i64`.
-#[derive(Copy, Clone, PartialEq, Eq, Debug, Hash)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub struct Uimm64(u64);
-
-impl Uimm64 {
-    /// Create a new `Uimm64` representing the unsigned number `x`.
-    pub fn new(x: u64) -> Self {
-        Self(x)
-    }
-
-    /// Return self negated.
-    pub fn wrapping_neg(self) -> Self {
-        Self(self.0.wrapping_neg())
-    }
-}
-
-impl From<Uimm64> for u64 {
-    fn from(val: Uimm64) -> u64 {
-        val.0
-    }
-}
-
-impl From<u64> for Uimm64 {
-    fn from(x: u64) -> Self {
-        Self(x)
-    }
-}
-
-/// Hexadecimal with a multiple of 4 digits and group separators:
-///
-///   0xfff0
-///   0x0001_ffff
-///   0xffff_ffff_fff8_4400
-///
-fn write_hex(x: u64, f: &mut Formatter) -> fmt::Result {
-    let mut pos = (64 - x.leading_zeros() - 1) & 0xf0;
-    write!(f, "0x{:04x}", (x >> pos) & 0xffff)?;
-    while pos > 0 {
-        pos -= 16;
-        write!(f, "_{:04x}", (x >> pos) & 0xffff)?;
-    }
-    Ok(())
-}
-
-impl Display for Uimm64 {
-    fn fmt(&self, f: &mut Formatter) -> fmt::Result {
-        let x = self.0;
-        if x < 10_000 {
-            // Use decimal for small numbers.
-            write!(f, "{}", x)
-        } else {
-            write_hex(x, f)
-        }
-    }
-}
-
-/// Parse a 64-bit unsigned number.
-fn parse_u64(s: &str) -> Result<u64, &'static str> {
-    let mut value: u64 = 0;
-    let mut digits = 0;
-
-    if s.starts_with("-0x") {
-        return Err("Invalid character in hexadecimal number");
-    } else if s.starts_with("0x") {
-        // Hexadecimal.
-        for ch in s[2..].chars() {
-            match ch.to_digit(16) {
-                Some(digit) => {
-                    digits += 1;
-                    if digits > 16 {
-                        return Err("Too many hexadecimal digits");
-                    }
-                    // This can't overflow given the digit limit.
-                    value = (value << 4) | u64::from(digit);
-                }
-                None => {
-                    // Allow embedded underscores, but fail on anything else.
-                    if ch != '_' {
-                        return Err("Invalid character in hexadecimal number");
-                    }
-                }
-            }
-        }
-    } else {
-        // Decimal number, possibly negative.
-        for ch in s.chars() {
-            match ch.to_digit(16) {
-                Some(digit) => {
-                    digits += 1;
-                    match value.checked_mul(10) {
-                        None => return Err("Too large decimal number"),
-                        Some(v) => value = v,
-                    }
-                    match value.checked_add(u64::from(digit)) {
-                        None => return Err("Too large decimal number"),
-                        Some(v) => value = v,
-                    }
-                }
-                None => {
-                    // Allow embedded underscores, but fail on anything else.
-                    if ch != '_' {
-                        return Err("Invalid character in decimal number");
-                    }
-                }
-            }
-        }
-    }
-
-    if digits == 0 {
-        return Err("No digits in number");
-    }
-
-    Ok(value)
-}
-
-impl FromStr for Uimm64 {
-    type Err = &'static str;
-
-    // Parse a decimal or hexadecimal `Uimm64`, formatted as above.
-    fn from_str(s: &str) -> Result<Self, &'static str> {
-        parse_u64(s).map(Self::new)
-    }
-}
-
-/// 8-bit unsigned integer immediate operand.
-///
-/// This is used to indicate lane indexes typically.
-pub type Uimm8 = u8;
-
-/// A 32-bit unsigned integer immediate operand.
-///
-/// This is used to represent sizes of memory objects.
-#[derive(Copy, Clone, PartialEq, Eq, Debug, Hash)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub struct Uimm32(u32);
-
-impl From<Uimm32> for u32 {
-    fn from(val: Uimm32) -> u32 {
-        val.0
-    }
-}
-
-impl From<Uimm32> for u64 {
-    fn from(val: Uimm32) -> u64 {
-        val.0.into()
-    }
-}
-
-impl From<Uimm32> for i64 {
-    fn from(val: Uimm32) -> i64 {
-        i64::from(val.0)
-    }
-}
-
-impl From<u32> for Uimm32 {
-    fn from(x: u32) -> Self {
-        Self(x)
-    }
-}
-
-impl Display for Uimm32 {
-    fn fmt(&self, f: &mut Formatter) -> fmt::Result {
-        if self.0 < 10_000 {
-            write!(f, "{}", self.0)
-        } else {
-            write_hex(u64::from(self.0), f)
-        }
-    }
-}
-
-impl FromStr for Uimm32 {
-    type Err = &'static str;
-
-    // Parse a decimal or hexadecimal `Uimm32`, formatted as above.
-    fn from_str(s: &str) -> Result<Self, &'static str> {
-        parse_i64(s).and_then(|x| {
-            if 0 <= x && x <= i64::from(u32::MAX) {
-                Ok(Self(x as u32))
-            } else {
-                Err("Uimm32 out of range")
-            }
-        })
-    }
-}
-
-/// A 128-bit immediate operand.
-///
-/// This is used as an immediate value in SIMD instructions.
-#[derive(Copy, Clone, PartialEq, Eq, Debug, Hash)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub struct V128Imm(pub [u8; 16]);
-
-impl V128Imm {
-    /// Iterate over the bytes in the constant.
-    pub fn bytes(&self) -> impl Iterator<Item = &u8> {
-        self.0.iter()
-    }
-
-    /// Convert the immediate into a vector.
-    pub fn to_vec(self) -> Vec<u8> {
-        self.0.to_vec()
-    }
-
-    /// Convert the immediate into a slice.
-    pub fn as_slice(&self) -> &[u8] {
-        &self.0[..]
-    }
-}
-
-impl From<&[u8]> for V128Imm {
-    fn from(slice: &[u8]) -> Self {
-        assert_eq!(slice.len(), 16);
-        let mut buffer = [0; 16];
-        buffer.copy_from_slice(slice);
-        Self(buffer)
-    }
-}
-
-impl From<u128> for V128Imm {
-    fn from(val: u128) -> Self {
-        V128Imm(val.to_le_bytes())
-    }
-}
-
-/// 32-bit signed immediate offset.
-///
-/// This is used to encode an immediate offset for load/store instructions. All supported ISAs have
-/// a maximum load/store offset that fits in an `i32`.
-#[derive(Copy, Clone, PartialEq, Eq, Debug, Hash)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub struct Offset32(i32);
-
-impl Offset32 {
-    /// Create a new `Offset32` representing the signed number `x`.
-    pub fn new(x: i32) -> Self {
-        Self(x)
-    }
-
-    /// Create a new `Offset32` representing the signed number `x` if possible.
-    pub fn try_from_i64(x: i64) -> Option<Self> {
-        let x = i32::try_from(x).ok()?;
-        Some(Self::new(x))
-    }
-
-    /// Add in the signed number `x` if possible.
-    pub fn try_add_i64(self, x: i64) -> Option<Self> {
-        let x = i32::try_from(x).ok()?;
-        let ret = self.0.checked_add(x)?;
-        Some(Self::new(ret))
-    }
-}
-
-impl From<Offset32> for i32 {
-    fn from(val: Offset32) -> i32 {
-        val.0
-    }
-}
-
-impl From<Offset32> for i64 {
-    fn from(val: Offset32) -> i64 {
-        i64::from(val.0)
-    }
-}
-
-impl From<i32> for Offset32 {
-    fn from(x: i32) -> Self {
-        Self(x)
-    }
-}
-
-impl Display for Offset32 {
-    fn fmt(&self, f: &mut Formatter) -> fmt::Result {
-        // 0 displays as an empty offset.
-        if self.0 == 0 {
-            return Ok(());
-        }
-
-        // Always include a sign.
-        write!(f, "{}", if self.0 < 0 { '-' } else { '+' })?;
-
-        let val = i64::from(self.0).abs();
-        if val < 10_000 {
-            write!(f, "{}", val)
-        } else {
-            write_hex(val as u64, f)
-        }
-    }
-}
-
-impl FromStr for Offset32 {
-    type Err = &'static str;
-
-    // Parse a decimal or hexadecimal `Offset32`, formatted as above.
-    fn from_str(s: &str) -> Result<Self, &'static str> {
-        if !(s.starts_with('-') || s.starts_with('+')) {
-            return Err("Offset must begin with sign");
-        }
-        parse_i64(s).and_then(|x| {
-            if i64::from(i32::MIN) <= x && x <= i64::from(i32::MAX) {
-                Ok(Self::new(x as i32))
-            } else {
-                Err("Offset out of range")
-            }
-        })
-    }
-}
-
-/// An IEEE binary32 immediate floating point value, represented as a u32
-/// containing the bit pattern.
-///
-/// All bit patterns are allowed.
-#[derive(Copy, Clone, Debug, Eq, PartialEq, Hash)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-#[repr(C)]
-pub struct Ieee32(u32);
-
-/// An IEEE binary64 immediate floating point value, represented as a u64
-/// containing the bit pattern.
-///
-/// All bit patterns are allowed.
-#[derive(Copy, Clone, Debug, Eq, PartialEq, Hash)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-#[repr(C)]
-pub struct Ieee64(u64);
-
-/// Format a floating point number in a way that is reasonably human-readable, and that can be
-/// converted back to binary without any rounding issues. The hexadecimal formatting of normal and
-/// subnormal numbers is compatible with C99 and the `printf "%a"` format specifier. The NaN and Inf
-/// formats are not supported by C99.
-///
-/// The encoding parameters are:
-///
-/// w - exponent field width in bits
-/// t - trailing significand field width in bits
-///
-fn format_float(bits: u64, w: u8, t: u8, f: &mut Formatter) -> fmt::Result {
-    debug_assert!(w > 0 && w <= 16, "Invalid exponent range");
-    debug_assert!(1 + w + t <= 64, "Too large IEEE format for u64");
-    debug_assert!((t + w + 1).is_power_of_two(), "Unexpected IEEE format size");
-
-    let max_e_bits = (1u64 << w) - 1;
-    let t_bits = bits & ((1u64 << t) - 1); // Trailing significand.
-    let e_bits = (bits >> t) & max_e_bits; // Biased exponent.
-    let sign_bit = (bits >> (w + t)) & 1;
-
-    let bias: i32 = (1 << (w - 1)) - 1;
-    let e = e_bits as i32 - bias; // Unbiased exponent.
-    let emin = 1 - bias; // Minimum exponent.
-
-    // How many hexadecimal digits are needed for the trailing significand?
-    let digits = (t + 3) / 4;
-    // Trailing significand left-aligned in `digits` hexadecimal digits.
-    let left_t_bits = t_bits << (4 * digits - t);
-
-    // All formats share the leading sign.
-    if sign_bit != 0 {
-        write!(f, "-")?;
-    }
-
-    if e_bits == 0 {
-        if t_bits == 0 {
-            // Zero.
-            write!(f, "0.0")
-        } else {
-            // Subnormal.
-            write!(
-                f,
-                "0x0.{0:01$x}p{2}",
-                left_t_bits,
-                usize::from(digits),
-                emin
-            )
-        }
-    } else if e_bits == max_e_bits {
-        // Always print a `+` or `-` sign for these special values.
-        // This makes them easier to parse as they can't be confused as identifiers.
-        if sign_bit == 0 {
-            write!(f, "+")?;
-        }
-        if t_bits == 0 {
-            // Infinity.
-            write!(f, "Inf")
-        } else {
-            // NaN.
-            let payload = t_bits & ((1 << (t - 1)) - 1);
-            if t_bits & (1 << (t - 1)) != 0 {
-                // Quiet NaN.
-                if payload != 0 {
-                    write!(f, "NaN:0x{:x}", payload)
-                } else {
-                    write!(f, "NaN")
-                }
-            } else {
-                // Signaling NaN.
-                write!(f, "sNaN:0x{:x}", payload)
-            }
-        }
-    } else {
-        // Normal number.
-        write!(f, "0x1.{0:01$x}p{2}", left_t_bits, usize::from(digits), e)
-    }
-}
-
-/// Parse a float using the same format as `format_float` above.
-///
-/// The encoding parameters are:
-///
-/// w - exponent field width in bits
-/// t - trailing significand field width in bits
-///
-fn parse_float(s: &str, w: u8, t: u8) -> Result<u64, &'static str> {
-    debug_assert!(w > 0 && w <= 16, "Invalid exponent range");
-    debug_assert!(1 + w + t <= 64, "Too large IEEE format for u64");
-    debug_assert!((t + w + 1).is_power_of_two(), "Unexpected IEEE format size");
-
-    let (sign_bit, s2) = if s.starts_with('-') {
-        (1u64 << (t + w), &s[1..])
-    } else if s.starts_with('+') {
-        (0, &s[1..])
-    } else {
-        (0, s)
-    };
-
-    if !s2.starts_with("0x") {
-        let max_e_bits = ((1u64 << w) - 1) << t;
-        let quiet_bit = 1u64 << (t - 1);
-
-        // The only decimal encoding allowed is 0.
-        if s2 == "0.0" {
-            return Ok(sign_bit);
-        }
-
-        if s2 == "Inf" {
-            // +/- infinity: e = max, t = 0.
-            return Ok(sign_bit | max_e_bits);
-        }
-        if s2 == "NaN" {
-            // Canonical quiet NaN: e = max, t = quiet.
-            return Ok(sign_bit | max_e_bits | quiet_bit);
-        }
-        if s2.starts_with("NaN:0x") {
-            // Quiet NaN with payload.
-            return match u64::from_str_radix(&s2[6..], 16) {
-                Ok(payload) if payload < quiet_bit => {
-                    Ok(sign_bit | max_e_bits | quiet_bit | payload)
-                }
-                _ => Err("Invalid NaN payload"),
-            };
-        }
-        if s2.starts_with("sNaN:0x") {
-            // Signaling NaN with payload.
-            return match u64::from_str_radix(&s2[7..], 16) {
-                Ok(payload) if 0 < payload && payload < quiet_bit => {
-                    Ok(sign_bit | max_e_bits | payload)
-                }
-                _ => Err("Invalid sNaN payload"),
-            };
-        }
-
-        return Err("Float must be hexadecimal");
-    }
-    let s3 = &s2[2..];
-
-    let mut digits = 0u8;
-    let mut digits_before_period: Option<u8> = None;
-    let mut significand = 0u64;
-    let mut exponent = 0i32;
-
-    for (idx, ch) in s3.char_indices() {
-        match ch {
-            '.' => {
-                // This is the radix point. There can only be one.
-                if digits_before_period != None {
-                    return Err("Multiple radix points");
-                } else {
-                    digits_before_period = Some(digits);
-                }
-            }
-            'p' => {
-                // The following exponent is a decimal number.
-                let exp_str = &s3[1 + idx..];
-                match exp_str.parse::<i16>() {
-                    Ok(e) => {
-                        exponent = i32::from(e);
-                        break;
-                    }
-                    Err(_) => return Err("Bad exponent"),
-                }
-            }
-            _ => match ch.to_digit(16) {
-                Some(digit) => {
-                    digits += 1;
-                    if digits > 16 {
-                        return Err("Too many digits");
-                    }
-                    significand = (significand << 4) | u64::from(digit);
-                }
-                None => return Err("Invalid character"),
-            },
-        }
-    }
-
-    if digits == 0 {
-        return Err("No digits");
-    }
-
-    if significand == 0 {
-        // This is +/- 0.0.
-        return Ok(sign_bit);
-    }
-
-    // Number of bits appearing after the radix point.
-    match digits_before_period {
-        None => {} // No radix point present.
-        Some(d) => exponent -= 4 * i32::from(digits - d),
-    };
-
-    // Normalize the significand and exponent.
-    let significant_bits = (64 - significand.leading_zeros()) as u8;
-    if significant_bits > t + 1 {
-        let adjust = significant_bits - (t + 1);
-        if significand & ((1u64 << adjust) - 1) != 0 {
-            return Err("Too many significant bits");
-        }
-        // Adjust significand down.
-        significand >>= adjust;
-        exponent += i32::from(adjust);
-    } else {
-        let adjust = t + 1 - significant_bits;
-        significand <<= adjust;
-        exponent -= i32::from(adjust);
-    }
-    debug_assert_eq!(significand >> t, 1);
-
-    // Trailing significand excludes the high bit.
-    let t_bits = significand & ((1 << t) - 1);
-
-    let max_exp = (1i32 << w) - 2;
-    let bias: i32 = (1 << (w - 1)) - 1;
-    exponent += bias + i32::from(t);
-
-    if exponent > max_exp {
-        Err("Magnitude too large")
-    } else if exponent > 0 {
-        // This is a normal number.
-        let e_bits = (exponent as u64) << t;
-        Ok(sign_bit | e_bits | t_bits)
-    } else if 1 - exponent <= i32::from(t) {
-        // This is a subnormal number: e = 0, t = significand bits.
-        // Renormalize significand for exponent = 1.
-        let adjust = 1 - exponent;
-        if significand & ((1u64 << adjust) - 1) != 0 {
-            Err("Subnormal underflow")
-        } else {
-            significand >>= adjust;
-            Ok(sign_bit | significand)
-        }
-    } else {
-        Err("Magnitude too small")
-    }
-}
-
-impl Ieee32 {
-    /// Create a new `Ieee32` containing the bits of `x`.
-    pub fn with_bits(x: u32) -> Self {
-        Self(x)
-    }
-
-    /// Create an `Ieee32` number representing `2.0^n`.
-    pub fn pow2<I: Into<i32>>(n: I) -> Self {
-        let n = n.into();
-        let w = 8;
-        let t = 23;
-        let bias = (1 << (w - 1)) - 1;
-        let exponent = (n + bias) as u32;
-        assert!(exponent > 0, "Underflow n={}", n);
-        assert!(exponent < (1 << w) + 1, "Overflow n={}", n);
-        Self(exponent << t)
-    }
-
-    /// Create an `Ieee32` number representing the greatest negative value
-    /// not convertable from f32 to a signed integer with width n.
-    pub fn fcvt_to_sint_negative_overflow<I: Into<i32>>(n: I) -> Self {
-        let n = n.into();
-        debug_assert!(n < 32);
-        debug_assert!(23 + 1 - n < 32);
-        Self::with_bits((1u32 << (32 - 1)) | Self::pow2(n - 1).0 | (1u32 << (23 + 1 - n)))
-    }
-
-    /// Return self negated.
-    pub fn neg(self) -> Self {
-        Self(self.0 ^ (1 << 31))
-    }
-
-    /// Create a new `Ieee32` representing the number `x`.
-    pub fn with_float(x: f32) -> Self {
-        Self(x.to_bits())
-    }
-
-    /// Get the bitwise representation.
-    pub fn bits(self) -> u32 {
-        self.0
-    }
-
-    /// Check if the value is a NaN.
-    pub fn is_nan(&self) -> bool {
-        f32::from_bits(self.0).is_nan()
-    }
-}
-
-impl PartialOrd for Ieee32 {
-    fn partial_cmp(&self, other: &Self) -> Option<Ordering> {
-        f32::from_bits(self.0).partial_cmp(&f32::from_bits(other.0))
-    }
-}
-
-impl Display for Ieee32 {
-    fn fmt(&self, f: &mut Formatter) -> fmt::Result {
-        let bits: u32 = self.0;
-        format_float(u64::from(bits), 8, 23, f)
-    }
-}
-
-impl FromStr for Ieee32 {
-    type Err = &'static str;
-
-    fn from_str(s: &str) -> Result<Self, &'static str> {
-        match parse_float(s, 8, 23) {
-            Ok(b) => Ok(Self(b as u32)),
-            Err(s) => Err(s),
-        }
-    }
-}
-
-impl From<f32> for Ieee32 {
-    fn from(x: f32) -> Self {
-        Self::with_float(x)
-    }
-}
-
-impl IntoBytes for Ieee32 {
-    fn into_bytes(self) -> Vec<u8> {
-        self.0.to_le_bytes().to_vec()
-    }
-}
-
-impl Ieee64 {
-    /// Create a new `Ieee64` containing the bits of `x`.
-    pub fn with_bits(x: u64) -> Self {
-        Self(x)
-    }
-
-    /// Create an `Ieee64` number representing `2.0^n`.
-    pub fn pow2<I: Into<i64>>(n: I) -> Self {
-        let n = n.into();
-        let w = 11;
-        let t = 52;
-        let bias = (1 << (w - 1)) - 1;
-        let exponent = (n + bias) as u64;
-        assert!(exponent > 0, "Underflow n={}", n);
-        assert!(exponent < (1 << w) + 1, "Overflow n={}", n);
-        Self(exponent << t)
-    }
-
-    /// Create an `Ieee64` number representing the greatest negative value
-    /// not convertable from f64 to a signed integer with width n.
-    pub fn fcvt_to_sint_negative_overflow<I: Into<i64>>(n: I) -> Self {
-        let n = n.into();
-        debug_assert!(n < 64);
-        debug_assert!(52 + 1 - n < 64);
-        Self::with_bits((1u64 << (64 - 1)) | Self::pow2(n - 1).0 | (1u64 << (52 + 1 - n)))
-    }
-
-    /// Return self negated.
-    pub fn neg(self) -> Self {
-        Self(self.0 ^ (1 << 63))
-    }
-
-    /// Create a new `Ieee64` representing the number `x`.
-    pub fn with_float(x: f64) -> Self {
-        Self(x.to_bits())
-    }
-
-    /// Get the bitwise representation.
-    pub fn bits(self) -> u64 {
-        self.0
-    }
-
-    /// Check if the value is a NaN. For [Ieee64], this means checking that the 11 exponent bits are
-    /// all set.
-    pub fn is_nan(&self) -> bool {
-        f64::from_bits(self.0).is_nan()
-    }
-}
-
-impl PartialOrd for Ieee64 {
-    fn partial_cmp(&self, other: &Self) -> Option<Ordering> {
-        f64::from_bits(self.0).partial_cmp(&f64::from_bits(other.0))
-    }
-}
-
-impl Display for Ieee64 {
-    fn fmt(&self, f: &mut Formatter) -> fmt::Result {
-        let bits: u64 = self.0;
-        format_float(bits, 11, 52, f)
-    }
-}
-
-impl FromStr for Ieee64 {
-    type Err = &'static str;
-
-    fn from_str(s: &str) -> Result<Self, &'static str> {
-        match parse_float(s, 11, 52) {
-            Ok(b) => Ok(Self(b)),
-            Err(s) => Err(s),
-        }
-    }
-}
-
-impl From<f64> for Ieee64 {
-    fn from(x: f64) -> Self {
-        Self::with_float(x)
-    }
-}
-
-impl From<u64> for Ieee64 {
-    fn from(x: u64) -> Self {
-        Self::with_float(f64::from_bits(x))
-    }
-}
-
-impl IntoBytes for Ieee64 {
-    fn into_bytes(self) -> Vec<u8> {
-        self.0.to_le_bytes().to_vec()
-    }
-}
-
-#[cfg(test)]
-mod tests {
-    use super::*;
-    use alloc::string::ToString;
-    use core::fmt::Display;
-    use core::mem;
-    use core::str::FromStr;
-    use core::{f32, f64};
-
-    #[test]
-    fn format_imm64() {
-        assert_eq!(Imm64(0).to_string(), "0");
-        assert_eq!(Imm64(9999).to_string(), "9999");
-        assert_eq!(Imm64(10000).to_string(), "0x2710");
-        assert_eq!(Imm64(-9999).to_string(), "-9999");
-        assert_eq!(Imm64(-10000).to_string(), "0xffff_ffff_ffff_d8f0");
-        assert_eq!(Imm64(0xffff).to_string(), "0xffff");
-        assert_eq!(Imm64(0x10000).to_string(), "0x0001_0000");
-    }
-
-    #[test]
-    fn format_uimm64() {
-        assert_eq!(Uimm64(0).to_string(), "0");
-        assert_eq!(Uimm64(9999).to_string(), "9999");
-        assert_eq!(Uimm64(10000).to_string(), "0x2710");
-        assert_eq!(Uimm64(-9999i64 as u64).to_string(), "0xffff_ffff_ffff_d8f1");
-        assert_eq!(
-            Uimm64(-10000i64 as u64).to_string(),
-            "0xffff_ffff_ffff_d8f0"
-        );
-        assert_eq!(Uimm64(0xffff).to_string(), "0xffff");
-        assert_eq!(Uimm64(0x10000).to_string(), "0x0001_0000");
-    }
-
-    // Verify that `text` can be parsed as a `T` into a value that displays as `want`.
-    fn parse_ok<T: FromStr + Display>(text: &str, want: &str)
-    where
-        <T as FromStr>::Err: Display,
-    {
-        match text.parse::<T>() {
-            Err(s) => panic!("\"{}\".parse() error: {}", text, s),
-            Ok(x) => assert_eq!(x.to_string(), want),
-        }
-    }
-
-    // Verify that `text` fails to parse as `T` with the error `msg`.
-    fn parse_err<T: FromStr + Display>(text: &str, msg: &str)
-    where
-        <T as FromStr>::Err: Display,
-    {
-        match text.parse::<T>() {
-            Err(s) => assert_eq!(s.to_string(), msg),
-            Ok(x) => panic!("Wanted Err({}), but got {}", msg, x),
-        }
-    }
-
-    #[test]
-    fn parse_imm64() {
-        parse_ok::<Imm64>("0", "0");
-        parse_ok::<Imm64>("1", "1");
-        parse_ok::<Imm64>("-0", "0");
-        parse_ok::<Imm64>("-1", "-1");
-        parse_ok::<Imm64>("0x0", "0");
-        parse_ok::<Imm64>("0xf", "15");
-        parse_ok::<Imm64>("-0x9", "-9");
-
-        // Probe limits.
-        parse_ok::<Imm64>("0xffffffff_ffffffff", "-1");
-        parse_ok::<Imm64>("0x80000000_00000000", "0x8000_0000_0000_0000");
-        parse_ok::<Imm64>("-0x80000000_00000000", "0x8000_0000_0000_0000");
-        parse_err::<Imm64>("-0x80000000_00000001", "Negative number too small");
-        parse_ok::<Imm64>("18446744073709551615", "-1");
-        parse_ok::<Imm64>("-9223372036854775808", "0x8000_0000_0000_0000");
-        // Overflow both the `checked_add` and `checked_mul`.
-        parse_err::<Imm64>("18446744073709551616", "Too large decimal number");
-        parse_err::<Imm64>("184467440737095516100", "Too large decimal number");
-        parse_err::<Imm64>("-9223372036854775809", "Negative number too small");
-
-        // Underscores are allowed where digits go.
-        parse_ok::<Imm64>("0_0", "0");
-        parse_ok::<Imm64>("-_10_0", "-100");
-        parse_ok::<Imm64>("_10_", "10");
-        parse_ok::<Imm64>("0x97_88_bb", "0x0097_88bb");
-        parse_ok::<Imm64>("0x_97_", "151");
-
-        parse_err::<Imm64>("", "No digits in number");
-        parse_err::<Imm64>("-", "No digits in number");
-        parse_err::<Imm64>("_", "No digits in number");
-        parse_err::<Imm64>("0x", "No digits in number");
-        parse_err::<Imm64>("0x_", "No digits in number");
-        parse_err::<Imm64>("-0x", "No digits in number");
-        parse_err::<Imm64>(" ", "Invalid character in decimal number");
-        parse_err::<Imm64>("0 ", "Invalid character in decimal number");
-        parse_err::<Imm64>(" 0", "Invalid character in decimal number");
-        parse_err::<Imm64>("--", "Invalid character in decimal number");
-        parse_err::<Imm64>("-0x-", "Invalid character in hexadecimal number");
-
-        // Hex count overflow.
-        parse_err::<Imm64>("0x0_0000_0000_0000_0000", "Too many hexadecimal digits");
-    }
-
-    #[test]
-    fn parse_uimm64() {
-        parse_ok::<Uimm64>("0", "0");
-        parse_ok::<Uimm64>("1", "1");
-        parse_ok::<Uimm64>("0x0", "0");
-        parse_ok::<Uimm64>("0xf", "15");
-        parse_ok::<Uimm64>("0xffffffff_fffffff7", "0xffff_ffff_ffff_fff7");
-
-        // Probe limits.
-        parse_ok::<Uimm64>("0xffffffff_ffffffff", "0xffff_ffff_ffff_ffff");
-        parse_ok::<Uimm64>("0x80000000_00000000", "0x8000_0000_0000_0000");
-        parse_ok::<Uimm64>("18446744073709551615", "0xffff_ffff_ffff_ffff");
-        // Overflow both the `checked_add` and `checked_mul`.
-        parse_err::<Uimm64>("18446744073709551616", "Too large decimal number");
-        parse_err::<Uimm64>("184467440737095516100", "Too large decimal number");
-
-        // Underscores are allowed where digits go.
-        parse_ok::<Uimm64>("0_0", "0");
-        parse_ok::<Uimm64>("_10_", "10");
-        parse_ok::<Uimm64>("0x97_88_bb", "0x0097_88bb");
-        parse_ok::<Uimm64>("0x_97_", "151");
-
-        parse_err::<Uimm64>("", "No digits in number");
-        parse_err::<Uimm64>("_", "No digits in number");
-        parse_err::<Uimm64>("0x", "No digits in number");
-        parse_err::<Uimm64>("0x_", "No digits in number");
-        parse_err::<Uimm64>("-", "Invalid character in decimal number");
-        parse_err::<Uimm64>("-0x", "Invalid character in hexadecimal number");
-        parse_err::<Uimm64>(" ", "Invalid character in decimal number");
-        parse_err::<Uimm64>("0 ", "Invalid character in decimal number");
-        parse_err::<Uimm64>(" 0", "Invalid character in decimal number");
-        parse_err::<Uimm64>("--", "Invalid character in decimal number");
-        parse_err::<Uimm64>("-0x-", "Invalid character in hexadecimal number");
-        parse_err::<Uimm64>("-0", "Invalid character in decimal number");
-        parse_err::<Uimm64>("-1", "Invalid character in decimal number");
-
-        // Hex count overflow.
-        parse_err::<Uimm64>("0x0_0000_0000_0000_0000", "Too many hexadecimal digits");
-    }
-
-    #[test]
-    fn format_offset32() {
-        assert_eq!(Offset32(0).to_string(), "");
-        assert_eq!(Offset32(1).to_string(), "+1");
-        assert_eq!(Offset32(-1).to_string(), "-1");
-        assert_eq!(Offset32(9999).to_string(), "+9999");
-        assert_eq!(Offset32(10000).to_string(), "+0x2710");
-        assert_eq!(Offset32(-9999).to_string(), "-9999");
-        assert_eq!(Offset32(-10000).to_string(), "-0x2710");
-        assert_eq!(Offset32(0xffff).to_string(), "+0xffff");
-        assert_eq!(Offset32(0x10000).to_string(), "+0x0001_0000");
-    }
-
-    #[test]
-    fn parse_offset32() {
-        parse_ok::<Offset32>("+0", "");
-        parse_ok::<Offset32>("+1", "+1");
-        parse_ok::<Offset32>("-0", "");
-        parse_ok::<Offset32>("-1", "-1");
-        parse_ok::<Offset32>("+0x0", "");
-        parse_ok::<Offset32>("+0xf", "+15");
-        parse_ok::<Offset32>("-0x9", "-9");
-        parse_ok::<Offset32>("-0x8000_0000", "-0x8000_0000");
-
-        parse_err::<Offset32>("+0x8000_0000", "Offset out of range");
-    }
-
-    #[test]
-    fn format_ieee32() {
-        assert_eq!(Ieee32::with_float(0.0).to_string(), "0.0");
-        assert_eq!(Ieee32::with_float(-0.0).to_string(), "-0.0");
-        assert_eq!(Ieee32::with_float(1.0).to_string(), "0x1.000000p0");
-        assert_eq!(Ieee32::with_float(1.5).to_string(), "0x1.800000p0");
-        assert_eq!(Ieee32::with_float(0.5).to_string(), "0x1.000000p-1");
-        assert_eq!(
-            Ieee32::with_float(f32::EPSILON).to_string(),
-            "0x1.000000p-23"
-        );
-        assert_eq!(Ieee32::with_float(f32::MIN).to_string(), "-0x1.fffffep127");
-        assert_eq!(Ieee32::with_float(f32::MAX).to_string(), "0x1.fffffep127");
-        // Smallest positive normal number.
-        assert_eq!(
-            Ieee32::with_float(f32::MIN_POSITIVE).to_string(),
-            "0x1.000000p-126"
-        );
-        // Subnormals.
-        assert_eq!(
-            Ieee32::with_float(f32::MIN_POSITIVE / 2.0).to_string(),
-            "0x0.800000p-126"
-        );
-        assert_eq!(
-            Ieee32::with_float(f32::MIN_POSITIVE * f32::EPSILON).to_string(),
-            "0x0.000002p-126"
-        );
-        assert_eq!(Ieee32::with_float(f32::INFINITY).to_string(), "+Inf");
-        assert_eq!(Ieee32::with_float(f32::NEG_INFINITY).to_string(), "-Inf");
-        assert_eq!(Ieee32::with_float(f32::NAN).to_string(), "+NaN");
-        assert_eq!(Ieee32::with_float(-f32::NAN).to_string(), "-NaN");
-        // Construct some qNaNs with payloads.
-        assert_eq!(Ieee32(0x7fc00001).to_string(), "+NaN:0x1");
-        assert_eq!(Ieee32(0x7ff00001).to_string(), "+NaN:0x300001");
-        // Signaling NaNs.
-        assert_eq!(Ieee32(0x7f800001).to_string(), "+sNaN:0x1");
-        assert_eq!(Ieee32(0x7fa00001).to_string(), "+sNaN:0x200001");
-    }
-
-    #[test]
-    fn parse_ieee32() {
-        parse_ok::<Ieee32>("0.0", "0.0");
-        parse_ok::<Ieee32>("+0.0", "0.0");
-        parse_ok::<Ieee32>("-0.0", "-0.0");
-        parse_ok::<Ieee32>("0x0", "0.0");
-        parse_ok::<Ieee32>("0x0.0", "0.0");
-        parse_ok::<Ieee32>("0x.0", "0.0");
-        parse_ok::<Ieee32>("0x0.", "0.0");
-        parse_ok::<Ieee32>("0x1", "0x1.000000p0");
-        parse_ok::<Ieee32>("+0x1", "0x1.000000p0");
-        parse_ok::<Ieee32>("-0x1", "-0x1.000000p0");
-        parse_ok::<Ieee32>("0x10", "0x1.000000p4");
-        parse_ok::<Ieee32>("0x10.0", "0x1.000000p4");
-        parse_err::<Ieee32>("0.", "Float must be hexadecimal");
-        parse_err::<Ieee32>(".0", "Float must be hexadecimal");
-        parse_err::<Ieee32>("0", "Float must be hexadecimal");
-        parse_err::<Ieee32>("-0", "Float must be hexadecimal");
-        parse_err::<Ieee32>(".", "Float must be hexadecimal");
-        parse_err::<Ieee32>("", "Float must be hexadecimal");
-        parse_err::<Ieee32>("-", "Float must be hexadecimal");
-        parse_err::<Ieee32>("0x", "No digits");
-        parse_err::<Ieee32>("0x..", "Multiple radix points");
-
-        // Check significant bits.
-        parse_ok::<Ieee32>("0x0.ffffff", "0x1.fffffep-1");
-        parse_ok::<Ieee32>("0x1.fffffe", "0x1.fffffep0");
-        parse_ok::<Ieee32>("0x3.fffffc", "0x1.fffffep1");
-        parse_ok::<Ieee32>("0x7.fffff8", "0x1.fffffep2");
-        parse_ok::<Ieee32>("0xf.fffff0", "0x1.fffffep3");
-        parse_err::<Ieee32>("0x1.ffffff", "Too many significant bits");
-        parse_err::<Ieee32>("0x1.fffffe0000000000", "Too many digits");
-
-        // Exponents.
-        parse_ok::<Ieee32>("0x1p3", "0x1.000000p3");
-        parse_ok::<Ieee32>("0x1p-3", "0x1.000000p-3");
-        parse_ok::<Ieee32>("0x1.0p3", "0x1.000000p3");
-        parse_ok::<Ieee32>("0x2.0p3", "0x1.000000p4");
-        parse_ok::<Ieee32>("0x1.0p127", "0x1.000000p127");
-        parse_ok::<Ieee32>("0x1.0p-126", "0x1.000000p-126");
-        parse_ok::<Ieee32>("0x0.1p-122", "0x1.000000p-126");
-        parse_err::<Ieee32>("0x2.0p127", "Magnitude too large");
-
-        // Subnormals.
-        parse_ok::<Ieee32>("0x1.0p-127", "0x0.800000p-126");
-        parse_ok::<Ieee32>("0x1.0p-149", "0x0.000002p-126");
-        parse_ok::<Ieee32>("0x0.000002p-126", "0x0.000002p-126");
-        parse_err::<Ieee32>("0x0.100001p-126", "Subnormal underflow");
-        parse_err::<Ieee32>("0x1.8p-149", "Subnormal underflow");
-        parse_err::<Ieee32>("0x1.0p-150", "Magnitude too small");
-
-        // NaNs and Infs.
-        parse_ok::<Ieee32>("Inf", "+Inf");
-        parse_ok::<Ieee32>("+Inf", "+Inf");
-        parse_ok::<Ieee32>("-Inf", "-Inf");
-        parse_ok::<Ieee32>("NaN", "+NaN");
-        parse_ok::<Ieee32>("+NaN", "+NaN");
-        parse_ok::<Ieee32>("-NaN", "-NaN");
-        parse_ok::<Ieee32>("NaN:0x0", "+NaN");
-        parse_err::<Ieee32>("NaN:", "Float must be hexadecimal");
-        parse_err::<Ieee32>("NaN:0", "Float must be hexadecimal");
-        parse_err::<Ieee32>("NaN:0x", "Invalid NaN payload");
-        parse_ok::<Ieee32>("NaN:0x000001", "+NaN:0x1");
-        parse_ok::<Ieee32>("NaN:0x300001", "+NaN:0x300001");
-        parse_err::<Ieee32>("NaN:0x400001", "Invalid NaN payload");
-        parse_ok::<Ieee32>("sNaN:0x1", "+sNaN:0x1");
-        parse_err::<Ieee32>("sNaN:0x0", "Invalid sNaN payload");
-        parse_ok::<Ieee32>("sNaN:0x200001", "+sNaN:0x200001");
-        parse_err::<Ieee32>("sNaN:0x400001", "Invalid sNaN payload");
-    }
-
-    #[test]
-    fn pow2_ieee32() {
-        assert_eq!(Ieee32::pow2(0).to_string(), "0x1.000000p0");
-        assert_eq!(Ieee32::pow2(1).to_string(), "0x1.000000p1");
-        assert_eq!(Ieee32::pow2(-1).to_string(), "0x1.000000p-1");
-        assert_eq!(Ieee32::pow2(127).to_string(), "0x1.000000p127");
-        assert_eq!(Ieee32::pow2(-126).to_string(), "0x1.000000p-126");
-
-        assert_eq!(Ieee32::pow2(1).neg().to_string(), "-0x1.000000p1");
-    }
-
-    #[test]
-    fn fcvt_to_sint_negative_overflow_ieee32() {
-        for n in &[8, 16] {
-            assert_eq!(-((1u32 << (n - 1)) as f32) - 1.0, unsafe {
-                mem::transmute(Ieee32::fcvt_to_sint_negative_overflow(*n))
-            });
-        }
-    }
-
-    #[test]
-    fn format_ieee64() {
-        assert_eq!(Ieee64::with_float(0.0).to_string(), "0.0");
-        assert_eq!(Ieee64::with_float(-0.0).to_string(), "-0.0");
-        assert_eq!(Ieee64::with_float(1.0).to_string(), "0x1.0000000000000p0");
-        assert_eq!(Ieee64::with_float(1.5).to_string(), "0x1.8000000000000p0");
-        assert_eq!(Ieee64::with_float(0.5).to_string(), "0x1.0000000000000p-1");
-        assert_eq!(
-            Ieee64::with_float(f64::EPSILON).to_string(),
-            "0x1.0000000000000p-52"
-        );
-        assert_eq!(
-            Ieee64::with_float(f64::MIN).to_string(),
-            "-0x1.fffffffffffffp1023"
-        );
-        assert_eq!(
-            Ieee64::with_float(f64::MAX).to_string(),
-            "0x1.fffffffffffffp1023"
-        );
-        // Smallest positive normal number.
-        assert_eq!(
-            Ieee64::with_float(f64::MIN_POSITIVE).to_string(),
-            "0x1.0000000000000p-1022"
-        );
-        // Subnormals.
-        assert_eq!(
-            Ieee64::with_float(f64::MIN_POSITIVE / 2.0).to_string(),
-            "0x0.8000000000000p-1022"
-        );
-        assert_eq!(
-            Ieee64::with_float(f64::MIN_POSITIVE * f64::EPSILON).to_string(),
-            "0x0.0000000000001p-1022"
-        );
-        assert_eq!(Ieee64::with_float(f64::INFINITY).to_string(), "+Inf");
-        assert_eq!(Ieee64::with_float(f64::NEG_INFINITY).to_string(), "-Inf");
-        assert_eq!(Ieee64::with_float(f64::NAN).to_string(), "+NaN");
-        assert_eq!(Ieee64::with_float(-f64::NAN).to_string(), "-NaN");
-        // Construct some qNaNs with payloads.
-        assert_eq!(Ieee64(0x7ff8000000000001).to_string(), "+NaN:0x1");
-        assert_eq!(
-            Ieee64(0x7ffc000000000001).to_string(),
-            "+NaN:0x4000000000001"
-        );
-        // Signaling NaNs.
-        assert_eq!(Ieee64(0x7ff0000000000001).to_string(), "+sNaN:0x1");
-        assert_eq!(
-            Ieee64(0x7ff4000000000001).to_string(),
-            "+sNaN:0x4000000000001"
-        );
-    }
-
-    #[test]
-    fn parse_ieee64() {
-        parse_ok::<Ieee64>("0.0", "0.0");
-        parse_ok::<Ieee64>("-0.0", "-0.0");
-        parse_ok::<Ieee64>("0x0", "0.0");
-        parse_ok::<Ieee64>("0x0.0", "0.0");
-        parse_ok::<Ieee64>("0x.0", "0.0");
-        parse_ok::<Ieee64>("0x0.", "0.0");
-        parse_ok::<Ieee64>("0x1", "0x1.0000000000000p0");
-        parse_ok::<Ieee64>("-0x1", "-0x1.0000000000000p0");
-        parse_ok::<Ieee64>("0x10", "0x1.0000000000000p4");
-        parse_ok::<Ieee64>("0x10.0", "0x1.0000000000000p4");
-        parse_err::<Ieee64>("0.", "Float must be hexadecimal");
-        parse_err::<Ieee64>(".0", "Float must be hexadecimal");
-        parse_err::<Ieee64>("0", "Float must be hexadecimal");
-        parse_err::<Ieee64>("-0", "Float must be hexadecimal");
-        parse_err::<Ieee64>(".", "Float must be hexadecimal");
-        parse_err::<Ieee64>("", "Float must be hexadecimal");
-        parse_err::<Ieee64>("-", "Float must be hexadecimal");
-        parse_err::<Ieee64>("0x", "No digits");
-        parse_err::<Ieee64>("0x..", "Multiple radix points");
-
-        // Check significant bits.
-        parse_ok::<Ieee64>("0x0.fffffffffffff8", "0x1.fffffffffffffp-1");
-        parse_ok::<Ieee64>("0x1.fffffffffffff", "0x1.fffffffffffffp0");
-        parse_ok::<Ieee64>("0x3.ffffffffffffe", "0x1.fffffffffffffp1");
-        parse_ok::<Ieee64>("0x7.ffffffffffffc", "0x1.fffffffffffffp2");
-        parse_ok::<Ieee64>("0xf.ffffffffffff8", "0x1.fffffffffffffp3");
-        parse_err::<Ieee64>("0x3.fffffffffffff", "Too many significant bits");
-        parse_err::<Ieee64>("0x001.fffffe00000000", "Too many digits");
-
-        // Exponents.
-        parse_ok::<Ieee64>("0x1p3", "0x1.0000000000000p3");
-        parse_ok::<Ieee64>("0x1p-3", "0x1.0000000000000p-3");
-        parse_ok::<Ieee64>("0x1.0p3", "0x1.0000000000000p3");
-        parse_ok::<Ieee64>("0x2.0p3", "0x1.0000000000000p4");
-        parse_ok::<Ieee64>("0x1.0p1023", "0x1.0000000000000p1023");
-        parse_ok::<Ieee64>("0x1.0p-1022", "0x1.0000000000000p-1022");
-        parse_ok::<Ieee64>("0x0.1p-1018", "0x1.0000000000000p-1022");
-        parse_err::<Ieee64>("0x2.0p1023", "Magnitude too large");
-
-        // Subnormals.
-        parse_ok::<Ieee64>("0x1.0p-1023", "0x0.8000000000000p-1022");
-        parse_ok::<Ieee64>("0x1.0p-1074", "0x0.0000000000001p-1022");
-        parse_ok::<Ieee64>("0x0.0000000000001p-1022", "0x0.0000000000001p-1022");
-        parse_err::<Ieee64>("0x0.10000000000008p-1022", "Subnormal underflow");
-        parse_err::<Ieee64>("0x1.8p-1074", "Subnormal underflow");
-        parse_err::<Ieee64>("0x1.0p-1075", "Magnitude too small");
-
-        // NaNs and Infs.
-        parse_ok::<Ieee64>("Inf", "+Inf");
-        parse_ok::<Ieee64>("-Inf", "-Inf");
-        parse_ok::<Ieee64>("NaN", "+NaN");
-        parse_ok::<Ieee64>("-NaN", "-NaN");
-        parse_ok::<Ieee64>("NaN:0x0", "+NaN");
-        parse_err::<Ieee64>("NaN:", "Float must be hexadecimal");
-        parse_err::<Ieee64>("NaN:0", "Float must be hexadecimal");
-        parse_err::<Ieee64>("NaN:0x", "Invalid NaN payload");
-        parse_ok::<Ieee64>("NaN:0x000001", "+NaN:0x1");
-        parse_ok::<Ieee64>("NaN:0x4000000000001", "+NaN:0x4000000000001");
-        parse_err::<Ieee64>("NaN:0x8000000000001", "Invalid NaN payload");
-        parse_ok::<Ieee64>("sNaN:0x1", "+sNaN:0x1");
-        parse_err::<Ieee64>("sNaN:0x0", "Invalid sNaN payload");
-        parse_ok::<Ieee64>("sNaN:0x4000000000001", "+sNaN:0x4000000000001");
-        parse_err::<Ieee64>("sNaN:0x8000000000001", "Invalid sNaN payload");
-    }
-
-    #[test]
-    fn pow2_ieee64() {
-        assert_eq!(Ieee64::pow2(0).to_string(), "0x1.0000000000000p0");
-        assert_eq!(Ieee64::pow2(1).to_string(), "0x1.0000000000000p1");
-        assert_eq!(Ieee64::pow2(-1).to_string(), "0x1.0000000000000p-1");
-        assert_eq!(Ieee64::pow2(1023).to_string(), "0x1.0000000000000p1023");
-        assert_eq!(Ieee64::pow2(-1022).to_string(), "0x1.0000000000000p-1022");
-
-        assert_eq!(Ieee64::pow2(1).neg().to_string(), "-0x1.0000000000000p1");
-    }
-
-    #[test]
-    fn fcvt_to_sint_negative_overflow_ieee64() {
-        for n in &[8, 16, 32] {
-            assert_eq!(-((1u64 << (n - 1)) as f64) - 1.0, unsafe {
-                mem::transmute(Ieee64::fcvt_to_sint_negative_overflow(*n))
-            });
-        }
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/instructions.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/instructions.rs
deleted file mode 100644
index 63a17bf9b..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/instructions.rs
+++ /dev/null
@@ -1,924 +0,0 @@
-//! Instruction formats and opcodes.
-//!
-//! The `instructions` module contains definitions for instruction formats, opcodes, and the
-//! in-memory representation of IR instructions.
-//!
-//! A large part of this module is auto-generated from the instruction descriptions in the meta
-//! directory.
-
-use alloc::vec::Vec;
-use core::convert::{TryFrom, TryInto};
-use core::fmt::{self, Display, Formatter};
-use core::num::NonZeroU32;
-use core::ops::{Deref, DerefMut};
-use core::str::FromStr;
-
-#[cfg(feature = "enable-serde")]
-use serde::{Deserialize, Serialize};
-
-use crate::bitset::BitSet;
-use crate::data_value::DataValue;
-use crate::entity;
-use crate::ir::{
-    self,
-    condcodes::{FloatCC, IntCC},
-    trapcode::TrapCode,
-    types, Block, FuncRef, JumpTable, MemFlags, SigRef, StackSlot, Type, Value,
-};
-
-/// Some instructions use an external list of argument values because there is not enough space in
-/// the 16-byte `InstructionData` struct. These value lists are stored in a memory pool in
-/// `dfg.value_lists`.
-pub type ValueList = entity::EntityList<Value>;
-
-/// Memory pool for holding value lists. See `ValueList`.
-pub type ValueListPool = entity::ListPool<Value>;
-
-// Include code generated by `cranelift-codegen/meta/src/gen_inst.rs`. This file contains:
-//
-// - The `pub enum InstructionFormat` enum with all the instruction formats.
-// - The `pub enum InstructionData` enum with all the instruction data fields.
-// - The `pub enum Opcode` definition with all known opcodes,
-// - The `const OPCODE_FORMAT: [InstructionFormat; N]` table.
-// - The private `fn opcode_name(Opcode) -> &'static str` function, and
-// - The hash table `const OPCODE_HASH_TABLE: [Opcode; N]`.
-//
-// For value type constraints:
-//
-// - The `const OPCODE_CONSTRAINTS : [OpcodeConstraints; N]` table.
-// - The `const TYPE_SETS : [ValueTypeSet; N]` table.
-// - The `const OPERAND_CONSTRAINTS : [OperandConstraint; N]` table.
-//
-include!(concat!(env!("OUT_DIR"), "/opcodes.rs"));
-
-impl Display for Opcode {
-    fn fmt(&self, f: &mut Formatter) -> fmt::Result {
-        write!(f, "{}", opcode_name(*self))
-    }
-}
-
-impl Opcode {
-    /// Get the instruction format for this opcode.
-    pub fn format(self) -> InstructionFormat {
-        OPCODE_FORMAT[self as usize - 1]
-    }
-
-    /// Get the constraint descriptor for this opcode.
-    /// Panic if this is called on `NotAnOpcode`.
-    pub fn constraints(self) -> OpcodeConstraints {
-        OPCODE_CONSTRAINTS[self as usize - 1]
-    }
-
-    /// Returns true if the instruction is a resumable trap.
-    pub fn is_resumable_trap(&self) -> bool {
-        match self {
-            Opcode::ResumableTrap | Opcode::ResumableTrapnz => true,
-            _ => false,
-        }
-    }
-}
-
-impl TryFrom<NonZeroU32> for Opcode {
-    type Error = ();
-
-    #[inline]
-    fn try_from(x: NonZeroU32) -> Result<Self, ()> {
-        let x: u16 = x.get().try_into().map_err(|_| ())?;
-        Self::try_from(x)
-    }
-}
-
-impl From<Opcode> for NonZeroU32 {
-    #[inline]
-    fn from(op: Opcode) -> NonZeroU32 {
-        let x = op as u8;
-        NonZeroU32::new(x as u32).unwrap()
-    }
-}
-
-// This trait really belongs in cranelift-reader where it is used by the `.clif` file parser, but since
-// it critically depends on the `opcode_name()` function which is needed here anyway, it lives in
-// this module. This also saves us from running the build script twice to generate code for the two
-// separate crates.
-impl FromStr for Opcode {
-    type Err = &'static str;
-
-    /// Parse an Opcode name from a string.
-    fn from_str(s: &str) -> Result<Self, &'static str> {
-        use crate::constant_hash::{probe, simple_hash, Table};
-
-        impl<'a> Table<&'a str> for [Option<Opcode>] {
-            fn len(&self) -> usize {
-                self.len()
-            }
-
-            fn key(&self, idx: usize) -> Option<&'a str> {
-                self[idx].map(opcode_name)
-            }
-        }
-
-        match probe::<&str, [Option<Self>]>(&OPCODE_HASH_TABLE, s, simple_hash(s)) {
-            Err(_) => Err("Unknown opcode"),
-            // We unwrap here because probe() should have ensured that the entry
-            // at this index is not None.
-            Ok(i) => Ok(OPCODE_HASH_TABLE[i].unwrap()),
-        }
-    }
-}
-
-/// A variable list of `Value` operands used for function call arguments and passing arguments to
-/// basic blocks.
-#[derive(Clone, Debug)]
-pub struct VariableArgs(Vec<Value>);
-
-impl VariableArgs {
-    /// Create an empty argument list.
-    pub fn new() -> Self {
-        Self(Vec::new())
-    }
-
-    /// Add an argument to the end.
-    pub fn push(&mut self, v: Value) {
-        self.0.push(v)
-    }
-
-    /// Check if the list is empty.
-    pub fn is_empty(&self) -> bool {
-        self.0.is_empty()
-    }
-
-    /// Convert this to a value list in `pool` with `fixed` prepended.
-    pub fn into_value_list(self, fixed: &[Value], pool: &mut ValueListPool) -> ValueList {
-        let mut vlist = ValueList::default();
-        vlist.extend(fixed.iter().cloned(), pool);
-        vlist.extend(self.0, pool);
-        vlist
-    }
-}
-
-// Coerce `VariableArgs` into a `&[Value]` slice.
-impl Deref for VariableArgs {
-    type Target = [Value];
-
-    fn deref(&self) -> &[Value] {
-        &self.0
-    }
-}
-
-impl DerefMut for VariableArgs {
-    fn deref_mut(&mut self) -> &mut [Value] {
-        &mut self.0
-    }
-}
-
-impl Display for VariableArgs {
-    fn fmt(&self, fmt: &mut Formatter) -> fmt::Result {
-        for (i, val) in self.0.iter().enumerate() {
-            if i == 0 {
-                write!(fmt, "{}", val)?;
-            } else {
-                write!(fmt, ", {}", val)?;
-            }
-        }
-        Ok(())
-    }
-}
-
-impl Default for VariableArgs {
-    fn default() -> Self {
-        Self::new()
-    }
-}
-
-/// Analyzing an instruction.
-///
-/// Avoid large matches on instruction formats by using the methods defined here to examine
-/// instructions.
-impl InstructionData {
-    /// Return information about the destination of a branch or jump instruction.
-    ///
-    /// Any instruction that can transfer control to another block reveals its possible destinations
-    /// here.
-    pub fn analyze_branch<'a>(&'a self, pool: &'a ValueListPool) -> BranchInfo<'a> {
-        match *self {
-            Self::Jump {
-                destination,
-                ref args,
-                ..
-            } => BranchInfo::SingleDest(destination, args.as_slice(pool)),
-            Self::BranchInt {
-                destination,
-                ref args,
-                ..
-            }
-            | Self::BranchFloat {
-                destination,
-                ref args,
-                ..
-            }
-            | Self::Branch {
-                destination,
-                ref args,
-                ..
-            } => BranchInfo::SingleDest(destination, &args.as_slice(pool)[1..]),
-            Self::BranchIcmp {
-                destination,
-                ref args,
-                ..
-            } => BranchInfo::SingleDest(destination, &args.as_slice(pool)[2..]),
-            Self::BranchTable {
-                table, destination, ..
-            } => BranchInfo::Table(table, Some(destination)),
-            _ => {
-                debug_assert!(!self.opcode().is_branch());
-                BranchInfo::NotABranch
-            }
-        }
-    }
-
-    /// Get the single destination of this branch instruction, if it is a single destination
-    /// branch or jump.
-    ///
-    /// Multi-destination branches like `br_table` return `None`.
-    pub fn branch_destination(&self) -> Option<Block> {
-        match *self {
-            Self::Jump { destination, .. }
-            | Self::Branch { destination, .. }
-            | Self::BranchInt { destination, .. }
-            | Self::BranchFloat { destination, .. }
-            | Self::BranchIcmp { destination, .. } => Some(destination),
-            Self::BranchTable { .. } => None,
-            _ => {
-                debug_assert!(!self.opcode().is_branch());
-                None
-            }
-        }
-    }
-
-    /// Get a mutable reference to the single destination of this branch instruction, if it is a
-    /// single destination branch or jump.
-    ///
-    /// Multi-destination branches like `br_table` return `None`.
-    pub fn branch_destination_mut(&mut self) -> Option<&mut Block> {
-        match *self {
-            Self::Jump {
-                ref mut destination,
-                ..
-            }
-            | Self::Branch {
-                ref mut destination,
-                ..
-            }
-            | Self::BranchInt {
-                ref mut destination,
-                ..
-            }
-            | Self::BranchFloat {
-                ref mut destination,
-                ..
-            }
-            | Self::BranchIcmp {
-                ref mut destination,
-                ..
-            } => Some(destination),
-            Self::BranchTable { .. } => None,
-            _ => {
-                debug_assert!(!self.opcode().is_branch());
-                None
-            }
-        }
-    }
-
-    /// Return the value of an immediate if the instruction has one or `None` otherwise. Only
-    /// immediate values are considered, not global values, constant handles, condition codes, etc.
-    pub fn imm_value(&self) -> Option<DataValue> {
-        match self {
-            &InstructionData::UnaryBool { imm, .. } => Some(DataValue::from(imm)),
-            // 8-bit.
-            &InstructionData::BinaryImm8 { imm, .. }
-            | &InstructionData::TernaryImm8 { imm, .. } => Some(DataValue::from(imm as i8)), // Note the switch from unsigned to signed.
-            // 32-bit
-            &InstructionData::UnaryIeee32 { imm, .. } => Some(DataValue::from(imm)),
-            &InstructionData::HeapAddr { imm, .. } => {
-                let imm: u32 = imm.into();
-                Some(DataValue::from(imm as i32)) // Note the switch from unsigned to signed.
-            }
-            &InstructionData::Load { offset, .. }
-            | &InstructionData::LoadComplex { offset, .. }
-            | &InstructionData::Store { offset, .. }
-            | &InstructionData::StoreComplex { offset, .. }
-            | &InstructionData::StackLoad { offset, .. }
-            | &InstructionData::StackStore { offset, .. }
-            | &InstructionData::TableAddr { offset, .. } => Some(DataValue::from(offset)),
-            // 64-bit.
-            &InstructionData::UnaryImm { imm, .. }
-            | &InstructionData::BinaryImm64 { imm, .. }
-            | &InstructionData::IntCompareImm { imm, .. } => Some(DataValue::from(imm.bits())),
-            &InstructionData::UnaryIeee64 { imm, .. } => Some(DataValue::from(imm)),
-            // 128-bit; though these immediates are present logically in the IR they are not
-            // included in the `InstructionData` for memory-size reasons. This case, returning
-            // `None`, is left here to alert users of this method that they should retrieve the
-            // value using the `DataFlowGraph`.
-            &InstructionData::Shuffle { imm: _, .. } => None,
-            _ => None,
-        }
-    }
-
-    /// If this is a trapping instruction, get its trap code. Otherwise, return
-    /// `None`.
-    pub fn trap_code(&self) -> Option<TrapCode> {
-        match *self {
-            Self::CondTrap { code, .. }
-            | Self::FloatCondTrap { code, .. }
-            | Self::IntCondTrap { code, .. }
-            | Self::Trap { code, .. } => Some(code),
-            _ => None,
-        }
-    }
-
-    /// If this is a control-flow instruction depending on an integer condition, gets its
-    /// condition.  Otherwise, return `None`.
-    pub fn cond_code(&self) -> Option<IntCC> {
-        match self {
-            &InstructionData::IntCond { cond, .. }
-            | &InstructionData::BranchIcmp { cond, .. }
-            | &InstructionData::IntCompare { cond, .. }
-            | &InstructionData::IntCondTrap { cond, .. }
-            | &InstructionData::BranchInt { cond, .. }
-            | &InstructionData::IntSelect { cond, .. }
-            | &InstructionData::IntCompareImm { cond, .. } => Some(cond),
-            _ => None,
-        }
-    }
-
-    /// If this is a control-flow instruction depending on a floating-point condition, gets its
-    /// condition.  Otherwise, return `None`.
-    pub fn fp_cond_code(&self) -> Option<FloatCC> {
-        match self {
-            &InstructionData::BranchFloat { cond, .. }
-            | &InstructionData::FloatCompare { cond, .. }
-            | &InstructionData::FloatCond { cond, .. }
-            | &InstructionData::FloatCondTrap { cond, .. } => Some(cond),
-            _ => None,
-        }
-    }
-
-    /// If this is a trapping instruction, get an exclusive reference to its
-    /// trap code. Otherwise, return `None`.
-    pub fn trap_code_mut(&mut self) -> Option<&mut TrapCode> {
-        match self {
-            Self::CondTrap { code, .. }
-            | Self::FloatCondTrap { code, .. }
-            | Self::IntCondTrap { code, .. }
-            | Self::Trap { code, .. } => Some(code),
-            _ => None,
-        }
-    }
-
-    /// If this is an atomic read/modify/write instruction, return its subopcode.
-    pub fn atomic_rmw_op(&self) -> Option<ir::AtomicRmwOp> {
-        match self {
-            &InstructionData::AtomicRmw { op, .. } => Some(op),
-            _ => None,
-        }
-    }
-
-    /// If this is a load/store instruction, returns its immediate offset.
-    pub fn load_store_offset(&self) -> Option<i32> {
-        match self {
-            &InstructionData::Load { offset, .. }
-            | &InstructionData::StackLoad { offset, .. }
-            | &InstructionData::LoadComplex { offset, .. }
-            | &InstructionData::Store { offset, .. }
-            | &InstructionData::StackStore { offset, .. }
-            | &InstructionData::StoreComplex { offset, .. } => Some(offset.into()),
-            _ => None,
-        }
-    }
-
-    /// If this is a load/store instruction, return its memory flags.
-    pub fn memflags(&self) -> Option<MemFlags> {
-        match self {
-            &InstructionData::Load { flags, .. }
-            | &InstructionData::LoadComplex { flags, .. }
-            | &InstructionData::LoadNoOffset { flags, .. }
-            | &InstructionData::Store { flags, .. }
-            | &InstructionData::StoreComplex { flags, .. }
-            | &InstructionData::StoreNoOffset { flags, .. } => Some(flags),
-            _ => None,
-        }
-    }
-
-    /// If this instruction references a stack slot, return it
-    pub fn stack_slot(&self) -> Option<StackSlot> {
-        match self {
-            &InstructionData::StackStore { stack_slot, .. }
-            | &InstructionData::StackLoad { stack_slot, .. } => Some(stack_slot),
-            _ => None,
-        }
-    }
-
-    /// Return information about a call instruction.
-    ///
-    /// Any instruction that can call another function reveals its call signature here.
-    pub fn analyze_call<'a>(&'a self, pool: &'a ValueListPool) -> CallInfo<'a> {
-        match *self {
-            Self::Call {
-                func_ref, ref args, ..
-            } => CallInfo::Direct(func_ref, args.as_slice(pool)),
-            Self::CallIndirect {
-                sig_ref, ref args, ..
-            } => CallInfo::Indirect(sig_ref, &args.as_slice(pool)[1..]),
-            _ => {
-                debug_assert!(!self.opcode().is_call());
-                CallInfo::NotACall
-            }
-        }
-    }
-
-    #[inline]
-    pub(crate) fn sign_extend_immediates(&mut self, ctrl_typevar: Type) {
-        if ctrl_typevar.is_invalid() {
-            return;
-        }
-
-        let bit_width = ctrl_typevar.bits();
-
-        match self {
-            Self::BinaryImm64 {
-                opcode,
-                arg: _,
-                imm,
-            } => {
-                if *opcode == Opcode::SdivImm || *opcode == Opcode::SremImm {
-                    imm.sign_extend_from_width(bit_width);
-                }
-            }
-            Self::IntCompareImm {
-                opcode,
-                arg: _,
-                cond,
-                imm,
-            } => {
-                debug_assert_eq!(*opcode, Opcode::IcmpImm);
-                if cond.unsigned() != *cond {
-                    imm.sign_extend_from_width(bit_width);
-                }
-            }
-            _ => {}
-        }
-    }
-}
-
-/// Information about branch and jump instructions.
-pub enum BranchInfo<'a> {
-    /// This is not a branch or jump instruction.
-    /// This instruction will not transfer control to another block in the function, but it may still
-    /// affect control flow by returning or trapping.
-    NotABranch,
-
-    /// This is a branch or jump to a single destination block, possibly taking value arguments.
-    SingleDest(Block, &'a [Value]),
-
-    /// This is a jump table branch which can have many destination blocks and maybe one default block.
-    Table(JumpTable, Option<Block>),
-}
-
-/// Information about call instructions.
-pub enum CallInfo<'a> {
-    /// This is not a call instruction.
-    NotACall,
-
-    /// This is a direct call to an external function declared in the preamble. See
-    /// `DataFlowGraph.ext_funcs`.
-    Direct(FuncRef, &'a [Value]),
-
-    /// This is an indirect call with the specified signature. See `DataFlowGraph.signatures`.
-    Indirect(SigRef, &'a [Value]),
-}
-
-/// Value type constraints for a given opcode.
-///
-/// The `InstructionFormat` determines the constraints on most operands, but `Value` operands and
-/// results are not determined by the format. Every `Opcode` has an associated
-/// `OpcodeConstraints` object that provides the missing details.
-#[derive(Clone, Copy)]
-pub struct OpcodeConstraints {
-    /// Flags for this opcode encoded as a bit field:
-    ///
-    /// Bits 0-2:
-    ///     Number of fixed result values. This does not include `variable_args` results as are
-    ///     produced by call instructions.
-    ///
-    /// Bit 3:
-    ///     This opcode is polymorphic and the controlling type variable can be inferred from the
-    ///     designated input operand. This is the `typevar_operand` index given to the
-    ///     `InstructionFormat` meta language object. When this bit is not set, the controlling
-    ///     type variable must be the first output value instead.
-    ///
-    /// Bit 4:
-    ///     This opcode is polymorphic and the controlling type variable does *not* appear as the
-    ///     first result type.
-    ///
-    /// Bits 5-7:
-    ///     Number of fixed value arguments. The minimum required number of value operands.
-    flags: u8,
-
-    /// Permitted set of types for the controlling type variable as an index into `TYPE_SETS`.
-    typeset_offset: u8,
-
-    /// Offset into `OPERAND_CONSTRAINT` table of the descriptors for this opcode. The first
-    /// `num_fixed_results()` entries describe the result constraints, then follows constraints for
-    /// the fixed `Value` input operands. (`num_fixed_value_arguments()` of them).
-    constraint_offset: u16,
-}
-
-impl OpcodeConstraints {
-    /// Can the controlling type variable for this opcode be inferred from the designated value
-    /// input operand?
-    /// This also implies that this opcode is polymorphic.
-    pub fn use_typevar_operand(self) -> bool {
-        (self.flags & 0x8) != 0
-    }
-
-    /// Is it necessary to look at the designated value input operand in order to determine the
-    /// controlling type variable, or is it good enough to use the first return type?
-    ///
-    /// Most polymorphic instructions produce a single result with the type of the controlling type
-    /// variable. A few polymorphic instructions either don't produce any results, or produce
-    /// results with a fixed type. These instructions return `true`.
-    pub fn requires_typevar_operand(self) -> bool {
-        (self.flags & 0x10) != 0
-    }
-
-    /// Get the number of *fixed* result values produced by this opcode.
-    /// This does not include `variable_args` produced by calls.
-    pub fn num_fixed_results(self) -> usize {
-        (self.flags & 0x7) as usize
-    }
-
-    /// Get the number of *fixed* input values required by this opcode.
-    ///
-    /// This does not include `variable_args` arguments on call and branch instructions.
-    ///
-    /// The number of fixed input values is usually implied by the instruction format, but
-    /// instruction formats that use a `ValueList` put both fixed and variable arguments in the
-    /// list. This method returns the *minimum* number of values required in the value list.
-    pub fn num_fixed_value_arguments(self) -> usize {
-        ((self.flags >> 5) & 0x7) as usize
-    }
-
-    /// Get the offset into `TYPE_SETS` for the controlling type variable.
-    /// Returns `None` if the instruction is not polymorphic.
-    fn typeset_offset(self) -> Option<usize> {
-        let offset = usize::from(self.typeset_offset);
-        if offset < TYPE_SETS.len() {
-            Some(offset)
-        } else {
-            None
-        }
-    }
-
-    /// Get the offset into OPERAND_CONSTRAINTS where the descriptors for this opcode begin.
-    fn constraint_offset(self) -> usize {
-        self.constraint_offset as usize
-    }
-
-    /// Get the value type of result number `n`, having resolved the controlling type variable to
-    /// `ctrl_type`.
-    pub fn result_type(self, n: usize, ctrl_type: Type) -> Type {
-        debug_assert!(n < self.num_fixed_results(), "Invalid result index");
-        if let ResolvedConstraint::Bound(t) =
-            OPERAND_CONSTRAINTS[self.constraint_offset() + n].resolve(ctrl_type)
-        {
-            t
-        } else {
-            panic!("Result constraints can't be free");
-        }
-    }
-
-    /// Get the value type of input value number `n`, having resolved the controlling type variable
-    /// to `ctrl_type`.
-    ///
-    /// Unlike results, it is possible for some input values to vary freely within a specific
-    /// `ValueTypeSet`. This is represented with the `ArgumentConstraint::Free` variant.
-    pub fn value_argument_constraint(self, n: usize, ctrl_type: Type) -> ResolvedConstraint {
-        debug_assert!(
-            n < self.num_fixed_value_arguments(),
-            "Invalid value argument index"
-        );
-        let offset = self.constraint_offset() + self.num_fixed_results();
-        OPERAND_CONSTRAINTS[offset + n].resolve(ctrl_type)
-    }
-
-    /// Get the typeset of allowed types for the controlling type variable in a polymorphic
-    /// instruction.
-    pub fn ctrl_typeset(self) -> Option<ValueTypeSet> {
-        self.typeset_offset().map(|offset| TYPE_SETS[offset])
-    }
-
-    /// Is this instruction polymorphic?
-    pub fn is_polymorphic(self) -> bool {
-        self.ctrl_typeset().is_some()
-    }
-}
-
-type BitSet8 = BitSet<u8>;
-type BitSet16 = BitSet<u16>;
-
-/// A value type set describes the permitted set of types for a type variable.
-#[derive(Clone, Copy, Debug, PartialEq, Eq)]
-pub struct ValueTypeSet {
-    /// Allowed lane sizes
-    pub lanes: BitSet16,
-    /// Allowed int widths
-    pub ints: BitSet8,
-    /// Allowed float widths
-    pub floats: BitSet8,
-    /// Allowed bool widths
-    pub bools: BitSet8,
-    /// Allowed ref widths
-    pub refs: BitSet8,
-}
-
-impl ValueTypeSet {
-    /// Is `scalar` part of the base type set?
-    ///
-    /// Note that the base type set does not have to be included in the type set proper.
-    fn is_base_type(self, scalar: Type) -> bool {
-        let l2b = scalar.log2_lane_bits();
-        if scalar.is_int() {
-            self.ints.contains(l2b)
-        } else if scalar.is_float() {
-            self.floats.contains(l2b)
-        } else if scalar.is_bool() {
-            self.bools.contains(l2b)
-        } else if scalar.is_ref() {
-            self.refs.contains(l2b)
-        } else {
-            false
-        }
-    }
-
-    /// Does `typ` belong to this set?
-    pub fn contains(self, typ: Type) -> bool {
-        let l2l = typ.log2_lane_count();
-        self.lanes.contains(l2l) && self.is_base_type(typ.lane_type())
-    }
-
-    /// Get an example member of this type set.
-    ///
-    /// This is used for error messages to avoid suggesting invalid types.
-    pub fn example(self) -> Type {
-        let t = if self.ints.max().unwrap_or(0) > 5 {
-            types::I32
-        } else if self.floats.max().unwrap_or(0) > 5 {
-            types::F32
-        } else if self.bools.max().unwrap_or(0) > 5 {
-            types::B32
-        } else {
-            types::B1
-        };
-        t.by(1 << self.lanes.min().unwrap()).unwrap()
-    }
-}
-
-/// Operand constraints. This describes the value type constraints on a single `Value` operand.
-enum OperandConstraint {
-    /// This operand has a concrete value type.
-    Concrete(Type),
-
-    /// This operand can vary freely within the given type set.
-    /// The type set is identified by its index into the TYPE_SETS constant table.
-    Free(u8),
-
-    /// This operand is the same type as the controlling type variable.
-    Same,
-
-    /// This operand is `ctrlType.lane_of()`.
-    LaneOf,
-
-    /// This operand is `ctrlType.as_bool()`.
-    AsBool,
-
-    /// This operand is `ctrlType.half_width()`.
-    HalfWidth,
-
-    /// This operand is `ctrlType.double_width()`.
-    DoubleWidth,
-
-    /// This operand is `ctrlType.half_vector()`.
-    HalfVector,
-
-    /// This operand is `ctrlType.double_vector()`.
-    DoubleVector,
-
-    /// This operand is `ctrlType.split_lanes()`.
-    SplitLanes,
-
-    /// This operand is `ctrlType.merge_lanes()`.
-    MergeLanes,
-}
-
-impl OperandConstraint {
-    /// Resolve this operand constraint into a concrete value type, given the value of the
-    /// controlling type variable.
-    pub fn resolve(&self, ctrl_type: Type) -> ResolvedConstraint {
-        use self::OperandConstraint::*;
-        use self::ResolvedConstraint::Bound;
-        match *self {
-            Concrete(t) => Bound(t),
-            Free(vts) => ResolvedConstraint::Free(TYPE_SETS[vts as usize]),
-            Same => Bound(ctrl_type),
-            LaneOf => Bound(ctrl_type.lane_of()),
-            AsBool => Bound(ctrl_type.as_bool()),
-            HalfWidth => Bound(ctrl_type.half_width().expect("invalid type for half_width")),
-            DoubleWidth => Bound(
-                ctrl_type
-                    .double_width()
-                    .expect("invalid type for double_width"),
-            ),
-            HalfVector => Bound(
-                ctrl_type
-                    .half_vector()
-                    .expect("invalid type for half_vector"),
-            ),
-            DoubleVector => Bound(ctrl_type.by(2).expect("invalid type for double_vector")),
-            SplitLanes => Bound(
-                ctrl_type
-                    .split_lanes()
-                    .expect("invalid type for split_lanes"),
-            ),
-            MergeLanes => Bound(
-                ctrl_type
-                    .merge_lanes()
-                    .expect("invalid type for merge_lanes"),
-            ),
-        }
-    }
-}
-
-/// The type constraint on a value argument once the controlling type variable is known.
-#[derive(Copy, Clone, Debug, PartialEq, Eq)]
-pub enum ResolvedConstraint {
-    /// The operand is bound to a known type.
-    Bound(Type),
-    /// The operand type can vary freely within the given set.
-    Free(ValueTypeSet),
-}
-
-#[cfg(test)]
-mod tests {
-    use super::*;
-    use alloc::string::ToString;
-
-    #[test]
-    fn opcodes() {
-        use core::mem;
-
-        let x = Opcode::Iadd;
-        let mut y = Opcode::Isub;
-
-        assert!(x != y);
-        y = Opcode::Iadd;
-        assert_eq!(x, y);
-        assert_eq!(x.format(), InstructionFormat::Binary);
-
-        assert_eq!(format!("{:?}", Opcode::IaddImm), "IaddImm");
-        assert_eq!(Opcode::IaddImm.to_string(), "iadd_imm");
-
-        // Check the matcher.
-        assert_eq!("iadd".parse::<Opcode>(), Ok(Opcode::Iadd));
-        assert_eq!("iadd_imm".parse::<Opcode>(), Ok(Opcode::IaddImm));
-        assert_eq!("iadd\0".parse::<Opcode>(), Err("Unknown opcode"));
-        assert_eq!("".parse::<Opcode>(), Err("Unknown opcode"));
-        assert_eq!("\0".parse::<Opcode>(), Err("Unknown opcode"));
-
-        // Opcode is a single byte, and because Option<Opcode> originally came to 2 bytes, early on
-        // Opcode included a variant NotAnOpcode to avoid the unnecessary bloat. Since then the Rust
-        // compiler has brought in NonZero optimization, meaning that an enum not using the 0 value
-        // can be optional for no size cost. We want to ensure Option<Opcode> remains small.
-        assert_eq!(mem::size_of::<Opcode>(), mem::size_of::<Option<Opcode>>());
-    }
-
-    #[test]
-    fn instruction_data() {
-        use core::mem;
-        // The size of the `InstructionData` enum is important for performance. It should not
-        // exceed 16 bytes. Use `Box<FooData>` out-of-line payloads for instruction formats that
-        // require more space than that. It would be fine with a data structure smaller than 16
-        // bytes, but what are the odds of that?
-        assert_eq!(mem::size_of::<InstructionData>(), 16);
-    }
-
-    #[test]
-    fn constraints() {
-        let a = Opcode::Iadd.constraints();
-        assert!(a.use_typevar_operand());
-        assert!(!a.requires_typevar_operand());
-        assert_eq!(a.num_fixed_results(), 1);
-        assert_eq!(a.num_fixed_value_arguments(), 2);
-        assert_eq!(a.result_type(0, types::I32), types::I32);
-        assert_eq!(a.result_type(0, types::I8), types::I8);
-        assert_eq!(
-            a.value_argument_constraint(0, types::I32),
-            ResolvedConstraint::Bound(types::I32)
-        );
-        assert_eq!(
-            a.value_argument_constraint(1, types::I32),
-            ResolvedConstraint::Bound(types::I32)
-        );
-
-        let b = Opcode::Bitcast.constraints();
-        assert!(!b.use_typevar_operand());
-        assert!(!b.requires_typevar_operand());
-        assert_eq!(b.num_fixed_results(), 1);
-        assert_eq!(b.num_fixed_value_arguments(), 1);
-        assert_eq!(b.result_type(0, types::I32), types::I32);
-        assert_eq!(b.result_type(0, types::I8), types::I8);
-        match b.value_argument_constraint(0, types::I32) {
-            ResolvedConstraint::Free(vts) => assert!(vts.contains(types::F32)),
-            _ => panic!("Unexpected constraint from value_argument_constraint"),
-        }
-
-        let c = Opcode::Call.constraints();
-        assert_eq!(c.num_fixed_results(), 0);
-        assert_eq!(c.num_fixed_value_arguments(), 0);
-
-        let i = Opcode::CallIndirect.constraints();
-        assert_eq!(i.num_fixed_results(), 0);
-        assert_eq!(i.num_fixed_value_arguments(), 1);
-
-        let cmp = Opcode::Icmp.constraints();
-        assert!(cmp.use_typevar_operand());
-        assert!(cmp.requires_typevar_operand());
-        assert_eq!(cmp.num_fixed_results(), 1);
-        assert_eq!(cmp.num_fixed_value_arguments(), 2);
-    }
-
-    #[test]
-    fn value_set() {
-        use crate::ir::types::*;
-
-        let vts = ValueTypeSet {
-            lanes: BitSet16::from_range(0, 8),
-            ints: BitSet8::from_range(4, 7),
-            floats: BitSet8::from_range(0, 0),
-            bools: BitSet8::from_range(3, 7),
-            refs: BitSet8::from_range(5, 7),
-        };
-        assert!(!vts.contains(I8));
-        assert!(vts.contains(I32));
-        assert!(vts.contains(I64));
-        assert!(vts.contains(I32X4));
-        assert!(!vts.contains(F32));
-        assert!(!vts.contains(B1));
-        assert!(vts.contains(B8));
-        assert!(vts.contains(B64));
-        assert!(vts.contains(R32));
-        assert!(vts.contains(R64));
-        assert_eq!(vts.example().to_string(), "i32");
-
-        let vts = ValueTypeSet {
-            lanes: BitSet16::from_range(0, 8),
-            ints: BitSet8::from_range(0, 0),
-            floats: BitSet8::from_range(5, 7),
-            bools: BitSet8::from_range(3, 7),
-            refs: BitSet8::from_range(0, 0),
-        };
-        assert_eq!(vts.example().to_string(), "f32");
-
-        let vts = ValueTypeSet {
-            lanes: BitSet16::from_range(1, 8),
-            ints: BitSet8::from_range(0, 0),
-            floats: BitSet8::from_range(5, 7),
-            bools: BitSet8::from_range(3, 7),
-            refs: BitSet8::from_range(0, 0),
-        };
-        assert_eq!(vts.example().to_string(), "f32x2");
-
-        let vts = ValueTypeSet {
-            lanes: BitSet16::from_range(2, 8),
-            ints: BitSet8::from_range(0, 0),
-            floats: BitSet8::from_range(0, 0),
-            bools: BitSet8::from_range(3, 7),
-            refs: BitSet8::from_range(0, 0),
-        };
-        assert!(!vts.contains(B32X2));
-        assert!(vts.contains(B32X4));
-        assert_eq!(vts.example().to_string(), "b32x4");
-
-        let vts = ValueTypeSet {
-            // TypeSet(lanes=(1, 256), ints=(8, 64))
-            lanes: BitSet16::from_range(0, 9),
-            ints: BitSet8::from_range(3, 7),
-            floats: BitSet8::from_range(0, 0),
-            bools: BitSet8::from_range(0, 0),
-            refs: BitSet8::from_range(0, 0),
-        };
-        assert!(vts.contains(I32));
-        assert!(vts.contains(I32X4));
-        assert!(!vts.contains(R32));
-        assert!(!vts.contains(R64));
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/jumptable.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/jumptable.rs
deleted file mode 100644
index bf05169d3..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/jumptable.rs
+++ /dev/null
@@ -1,128 +0,0 @@
-//! Jump table representation.
-//!
-//! Jump tables are declared in the preamble and assigned an `ir::entities::JumpTable` reference.
-//! The actual table of destinations is stored in a `JumpTableData` struct defined in this module.
-
-use crate::ir::entities::Block;
-use alloc::vec::Vec;
-use core::fmt::{self, Display, Formatter};
-use core::slice::{Iter, IterMut};
-
-#[cfg(feature = "enable-serde")]
-use serde::{Deserialize, Serialize};
-
-/// Contents of a jump table.
-///
-/// All jump tables use 0-based indexing and are densely populated.
-#[derive(Clone)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub struct JumpTableData {
-    // Table entries.
-    table: Vec<Block>,
-}
-
-impl JumpTableData {
-    /// Create a new empty jump table.
-    pub fn new() -> Self {
-        Self { table: Vec::new() }
-    }
-
-    /// Create a new empty jump table with the specified capacity.
-    pub fn with_capacity(capacity: usize) -> Self {
-        Self {
-            table: Vec::with_capacity(capacity),
-        }
-    }
-
-    /// Get the number of table entries.
-    pub fn len(&self) -> usize {
-        self.table.len()
-    }
-
-    /// Append a table entry.
-    pub fn push_entry(&mut self, dest: Block) {
-        self.table.push(dest)
-    }
-
-    /// Checks if any of the entries branch to `block`.
-    pub fn branches_to(&self, block: Block) -> bool {
-        self.table.iter().any(|target_block| *target_block == block)
-    }
-
-    /// Access the whole table as a slice.
-    pub fn as_slice(&self) -> &[Block] {
-        self.table.as_slice()
-    }
-
-    /// Access the whole table as a mutable slice.
-    pub fn as_mut_slice(&mut self) -> &mut [Block] {
-        self.table.as_mut_slice()
-    }
-
-    /// Returns an iterator over the table.
-    pub fn iter(&self) -> Iter<Block> {
-        self.table.iter()
-    }
-
-    /// Returns an iterator that allows modifying each value.
-    pub fn iter_mut(&mut self) -> IterMut<Block> {
-        self.table.iter_mut()
-    }
-
-    /// Clears all entries in this jump table.
-    pub fn clear(&mut self) {
-        self.table.clear();
-    }
-}
-
-impl Display for JumpTableData {
-    fn fmt(&self, fmt: &mut Formatter) -> fmt::Result {
-        write!(fmt, "jump_table [")?;
-        match self.table.first() {
-            None => (),
-            Some(first) => write!(fmt, "{}", first)?,
-        }
-        for block in self.table.iter().skip(1) {
-            write!(fmt, ", {}", block)?;
-        }
-        write!(fmt, "]")
-    }
-}
-
-#[cfg(test)]
-mod tests {
-    use super::JumpTableData;
-    use crate::entity::EntityRef;
-    use crate::ir::Block;
-    use alloc::string::ToString;
-
-    #[test]
-    fn empty() {
-        let jt = JumpTableData::new();
-
-        assert_eq!(jt.as_slice().get(0), None);
-        assert_eq!(jt.as_slice().get(10), None);
-
-        assert_eq!(jt.to_string(), "jump_table []");
-
-        let v = jt.as_slice();
-        assert_eq!(v, []);
-    }
-
-    #[test]
-    fn insert() {
-        let e1 = Block::new(1);
-        let e2 = Block::new(2);
-
-        let mut jt = JumpTableData::new();
-
-        jt.push_entry(e1);
-        jt.push_entry(e2);
-        jt.push_entry(e1);
-
-        assert_eq!(jt.to_string(), "jump_table [block1, block2, block1]");
-
-        let v = jt.as_slice();
-        assert_eq!(v, [e1, e2, e1]);
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/layout.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/layout.rs
deleted file mode 100644
index 47ec6b1fd..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/layout.rs
+++ /dev/null
@@ -1,1324 +0,0 @@
-//! Function layout.
-//!
-//! The order of basic blocks in a function and the order of instructions in a block is
-//! determined by the `Layout` data structure defined in this module.
-
-use crate::entity::SecondaryMap;
-use crate::ir::dfg::DataFlowGraph;
-use crate::ir::progpoint::{ExpandedProgramPoint, ProgramOrder};
-use crate::ir::{Block, Inst};
-use crate::packed_option::PackedOption;
-use crate::timing;
-use core::cmp;
-use core::iter::{IntoIterator, Iterator};
-
-/// The `Layout` struct determines the layout of blocks and instructions in a function. It does not
-/// contain definitions of instructions or blocks, but depends on `Inst` and `Block` entity references
-/// being defined elsewhere.
-///
-/// This data structure determines:
-///
-/// - The order of blocks in the function.
-/// - Which block contains a given instruction.
-/// - The order of instructions with a block.
-///
-/// While data dependencies are not recorded, instruction ordering does affect control
-/// dependencies, so part of the semantics of the program are determined by the layout.
-///
-#[derive(Clone)]
-pub struct Layout {
-    /// Linked list nodes for the layout order of blocks Forms a doubly linked list, terminated in
-    /// both ends by `None`.
-    blocks: SecondaryMap<Block, BlockNode>,
-
-    /// Linked list nodes for the layout order of instructions. Forms a double linked list per block,
-    /// terminated in both ends by `None`.
-    insts: SecondaryMap<Inst, InstNode>,
-
-    /// First block in the layout order, or `None` when no blocks have been laid out.
-    first_block: Option<Block>,
-
-    /// Last block in the layout order, or `None` when no blocks have been laid out.
-    last_block: Option<Block>,
-}
-
-impl Layout {
-    /// Create a new empty `Layout`.
-    pub fn new() -> Self {
-        Self {
-            blocks: SecondaryMap::new(),
-            insts: SecondaryMap::new(),
-            first_block: None,
-            last_block: None,
-        }
-    }
-
-    /// Clear the layout.
-    pub fn clear(&mut self) {
-        self.blocks.clear();
-        self.insts.clear();
-        self.first_block = None;
-        self.last_block = None;
-    }
-
-    /// Returns the capacity of the `BlockData` map.
-    pub fn block_capacity(&self) -> usize {
-        self.blocks.capacity()
-    }
-}
-
-/// Sequence numbers.
-///
-/// All instructions and blocks are given a sequence number that can be used to quickly determine
-/// their relative position in the layout. The sequence numbers are not contiguous, but are assigned
-/// like line numbers in BASIC: 10, 20, 30, ...
-///
-/// The block sequence numbers are strictly increasing, and so are the instruction sequence numbers
-/// within a block. The instruction sequence numbers are all between the sequence number of their
-/// containing block and the following block.
-///
-/// The result is that sequence numbers work like BASIC line numbers for the textual form of the IR.
-type SequenceNumber = u32;
-
-/// Initial stride assigned to new sequence numbers.
-const MAJOR_STRIDE: SequenceNumber = 10;
-
-/// Secondary stride used when renumbering locally.
-const MINOR_STRIDE: SequenceNumber = 2;
-
-/// Limit on the sequence number range we'll renumber locally. If this limit is exceeded, we'll
-/// switch to a full function renumbering.
-const LOCAL_LIMIT: SequenceNumber = 100 * MINOR_STRIDE;
-
-/// Compute the midpoint between `a` and `b`.
-/// Return `None` if the midpoint would be equal to either.
-fn midpoint(a: SequenceNumber, b: SequenceNumber) -> Option<SequenceNumber> {
-    debug_assert!(a < b);
-    // Avoid integer overflow.
-    let m = a + (b - a) / 2;
-    if m > a {
-        Some(m)
-    } else {
-        None
-    }
-}
-
-#[test]
-fn test_midpoint() {
-    assert_eq!(midpoint(0, 1), None);
-    assert_eq!(midpoint(0, 2), Some(1));
-    assert_eq!(midpoint(0, 3), Some(1));
-    assert_eq!(midpoint(0, 4), Some(2));
-    assert_eq!(midpoint(1, 4), Some(2));
-    assert_eq!(midpoint(2, 4), Some(3));
-    assert_eq!(midpoint(3, 4), None);
-    assert_eq!(midpoint(3, 4), None);
-}
-
-impl ProgramOrder for Layout {
-    fn cmp<A, B>(&self, a: A, b: B) -> cmp::Ordering
-    where
-        A: Into<ExpandedProgramPoint>,
-        B: Into<ExpandedProgramPoint>,
-    {
-        let a_seq = self.seq(a);
-        let b_seq = self.seq(b);
-        a_seq.cmp(&b_seq)
-    }
-
-    fn is_block_gap(&self, inst: Inst, block: Block) -> bool {
-        let i = &self.insts[inst];
-        let e = &self.blocks[block];
-
-        i.next.is_none() && i.block == e.prev
-    }
-}
-
-// Private methods for dealing with sequence numbers.
-impl Layout {
-    /// Get the sequence number of a program point that must correspond to an entity in the layout.
-    fn seq<PP: Into<ExpandedProgramPoint>>(&self, pp: PP) -> SequenceNumber {
-        // When `PP = Inst` or `PP = Block`, we expect this dynamic type check to be optimized out.
-        match pp.into() {
-            ExpandedProgramPoint::Block(block) => self.blocks[block].seq,
-            ExpandedProgramPoint::Inst(inst) => self.insts[inst].seq,
-        }
-    }
-
-    /// Get the last sequence number in `block`.
-    fn last_block_seq(&self, block: Block) -> SequenceNumber {
-        // Get the seq of the last instruction if it exists, otherwise use the block header seq.
-        self.blocks[block]
-            .last_inst
-            .map(|inst| self.insts[inst].seq)
-            .unwrap_or(self.blocks[block].seq)
-    }
-
-    /// Assign a valid sequence number to `block` such that the numbers are still monotonic. This may
-    /// require renumbering.
-    fn assign_block_seq(&mut self, block: Block) {
-        debug_assert!(self.is_block_inserted(block));
-
-        // Get the sequence number immediately before `block`, or 0.
-        let prev_seq = self.blocks[block]
-            .prev
-            .map(|prev_block| self.last_block_seq(prev_block))
-            .unwrap_or(0);
-
-        // Get the sequence number immediately following `block`.
-        let next_seq = if let Some(inst) = self.blocks[block].first_inst.expand() {
-            self.insts[inst].seq
-        } else if let Some(next_block) = self.blocks[block].next.expand() {
-            self.blocks[next_block].seq
-        } else {
-            // There is nothing after `block`. We can just use a major stride.
-            self.blocks[block].seq = prev_seq + MAJOR_STRIDE;
-            return;
-        };
-
-        // Check if there is room between these sequence numbers.
-        if let Some(seq) = midpoint(prev_seq, next_seq) {
-            self.blocks[block].seq = seq;
-        } else {
-            // No available integers between `prev_seq` and `next_seq`. We have to renumber.
-            self.renumber_from_block(block, prev_seq + MINOR_STRIDE, prev_seq + LOCAL_LIMIT);
-        }
-    }
-
-    /// Assign a valid sequence number to `inst` such that the numbers are still monotonic. This may
-    /// require renumbering.
-    fn assign_inst_seq(&mut self, inst: Inst) {
-        let block = self
-            .inst_block(inst)
-            .expect("inst must be inserted before assigning an seq");
-
-        // Get the sequence number immediately before `inst`.
-        let prev_seq = match self.insts[inst].prev.expand() {
-            Some(prev_inst) => self.insts[prev_inst].seq,
-            None => self.blocks[block].seq,
-        };
-
-        // Get the sequence number immediately following `inst`.
-        let next_seq = if let Some(next_inst) = self.insts[inst].next.expand() {
-            self.insts[next_inst].seq
-        } else if let Some(next_block) = self.blocks[block].next.expand() {
-            self.blocks[next_block].seq
-        } else {
-            // There is nothing after `inst`. We can just use a major stride.
-            self.insts[inst].seq = prev_seq + MAJOR_STRIDE;
-            return;
-        };
-
-        // Check if there is room between these sequence numbers.
-        if let Some(seq) = midpoint(prev_seq, next_seq) {
-            self.insts[inst].seq = seq;
-        } else {
-            // No available integers between `prev_seq` and `next_seq`. We have to renumber.
-            self.renumber_from_inst(inst, prev_seq + MINOR_STRIDE, prev_seq + LOCAL_LIMIT);
-        }
-    }
-
-    /// Renumber instructions starting from `inst` until the end of the block or until numbers catch
-    /// up.
-    ///
-    /// Return `None` if renumbering has caught up and the sequence is monotonic again. Otherwise
-    /// return the last used sequence number.
-    ///
-    /// If sequence numbers exceed `limit`, switch to a full function renumbering and return `None`.
-    fn renumber_insts(
-        &mut self,
-        inst: Inst,
-        seq: SequenceNumber,
-        limit: SequenceNumber,
-    ) -> Option<SequenceNumber> {
-        let mut inst = inst;
-        let mut seq = seq;
-
-        loop {
-            self.insts[inst].seq = seq;
-
-            // Next instruction.
-            inst = match self.insts[inst].next.expand() {
-                None => return Some(seq),
-                Some(next) => next,
-            };
-
-            if seq < self.insts[inst].seq {
-                // Sequence caught up.
-                return None;
-            }
-
-            if seq > limit {
-                // We're pushing too many instructions in front of us.
-                // Switch to a full function renumbering to make some space.
-                self.full_renumber();
-                return None;
-            }
-
-            seq += MINOR_STRIDE;
-        }
-    }
-
-    /// Renumber starting from `block` to `seq` and continuing until the sequence numbers are
-    /// monotonic again.
-    fn renumber_from_block(
-        &mut self,
-        block: Block,
-        first_seq: SequenceNumber,
-        limit: SequenceNumber,
-    ) {
-        let mut block = block;
-        let mut seq = first_seq;
-
-        loop {
-            self.blocks[block].seq = seq;
-
-            // Renumber instructions in `block`. Stop when the numbers catch up.
-            if let Some(inst) = self.blocks[block].first_inst.expand() {
-                seq = match self.renumber_insts(inst, seq + MINOR_STRIDE, limit) {
-                    Some(s) => s,
-                    None => return,
-                }
-            }
-
-            // Advance to the next block.
-            block = match self.blocks[block].next.expand() {
-                Some(next) => next,
-                None => return,
-            };
-
-            // Stop renumbering once the numbers catch up.
-            if seq < self.blocks[block].seq {
-                return;
-            }
-
-            seq += MINOR_STRIDE;
-        }
-    }
-
-    /// Renumber starting from `inst` to `seq` and continuing until the sequence numbers are
-    /// monotonic again.
-    fn renumber_from_inst(&mut self, inst: Inst, first_seq: SequenceNumber, limit: SequenceNumber) {
-        if let Some(seq) = self.renumber_insts(inst, first_seq, limit) {
-            // Renumbering spills over into next block.
-            if let Some(next_block) = self.blocks[self.inst_block(inst).unwrap()].next.expand() {
-                self.renumber_from_block(next_block, seq + MINOR_STRIDE, limit);
-            }
-        }
-    }
-
-    /// Renumber all blocks and instructions in the layout.
-    ///
-    /// This doesn't affect the position of anything, but it gives more room in the internal
-    /// sequence numbers for inserting instructions later.
-    fn full_renumber(&mut self) {
-        let _tt = timing::layout_renumber();
-        let mut seq = 0;
-        let mut next_block = self.first_block;
-        while let Some(block) = next_block {
-            self.blocks[block].seq = seq;
-            seq += MAJOR_STRIDE;
-            next_block = self.blocks[block].next.expand();
-
-            let mut next_inst = self.blocks[block].first_inst.expand();
-            while let Some(inst) = next_inst {
-                self.insts[inst].seq = seq;
-                seq += MAJOR_STRIDE;
-                next_inst = self.insts[inst].next.expand();
-            }
-        }
-        log::trace!("Renumbered {} program points", seq / MAJOR_STRIDE);
-    }
-}
-
-/// Methods for laying out blocks.
-///
-/// An unknown block starts out as *not inserted* in the block layout. The layout is a linear order of
-/// inserted blocks. Once a block has been inserted in the layout, instructions can be added. A block
-/// can only be removed from the layout when it is empty.
-///
-/// Since every block must end with a terminator instruction which cannot fall through, the layout of
-/// blocks do not affect the semantics of the program.
-///
-impl Layout {
-    /// Is `block` currently part of the layout?
-    pub fn is_block_inserted(&self, block: Block) -> bool {
-        Some(block) == self.first_block || self.blocks[block].prev.is_some()
-    }
-
-    /// Insert `block` as the last block in the layout.
-    pub fn append_block(&mut self, block: Block) {
-        debug_assert!(
-            !self.is_block_inserted(block),
-            "Cannot append block that is already in the layout"
-        );
-        {
-            let node = &mut self.blocks[block];
-            debug_assert!(node.first_inst.is_none() && node.last_inst.is_none());
-            node.prev = self.last_block.into();
-            node.next = None.into();
-        }
-        if let Some(last) = self.last_block {
-            self.blocks[last].next = block.into();
-        } else {
-            self.first_block = Some(block);
-        }
-        self.last_block = Some(block);
-        self.assign_block_seq(block);
-    }
-
-    /// Insert `block` in the layout before the existing block `before`.
-    pub fn insert_block(&mut self, block: Block, before: Block) {
-        debug_assert!(
-            !self.is_block_inserted(block),
-            "Cannot insert block that is already in the layout"
-        );
-        debug_assert!(
-            self.is_block_inserted(before),
-            "block Insertion point not in the layout"
-        );
-        let after = self.blocks[before].prev;
-        {
-            let node = &mut self.blocks[block];
-            node.next = before.into();
-            node.prev = after;
-        }
-        self.blocks[before].prev = block.into();
-        match after.expand() {
-            None => self.first_block = Some(block),
-            Some(a) => self.blocks[a].next = block.into(),
-        }
-        self.assign_block_seq(block);
-    }
-
-    /// Insert `block` in the layout *after* the existing block `after`.
-    pub fn insert_block_after(&mut self, block: Block, after: Block) {
-        debug_assert!(
-            !self.is_block_inserted(block),
-            "Cannot insert block that is already in the layout"
-        );
-        debug_assert!(
-            self.is_block_inserted(after),
-            "block Insertion point not in the layout"
-        );
-        let before = self.blocks[after].next;
-        {
-            let node = &mut self.blocks[block];
-            node.next = before;
-            node.prev = after.into();
-        }
-        self.blocks[after].next = block.into();
-        match before.expand() {
-            None => self.last_block = Some(block),
-            Some(b) => self.blocks[b].prev = block.into(),
-        }
-        self.assign_block_seq(block);
-    }
-
-    /// Remove `block` from the layout.
-    pub fn remove_block(&mut self, block: Block) {
-        debug_assert!(self.is_block_inserted(block), "block not in the layout");
-        debug_assert!(self.first_inst(block).is_none(), "block must be empty.");
-
-        // Clear the `block` node and extract links.
-        let prev;
-        let next;
-        {
-            let n = &mut self.blocks[block];
-            prev = n.prev;
-            next = n.next;
-            n.prev = None.into();
-            n.next = None.into();
-        }
-        // Fix up links to `block`.
-        match prev.expand() {
-            None => self.first_block = next.expand(),
-            Some(p) => self.blocks[p].next = next,
-        }
-        match next.expand() {
-            None => self.last_block = prev.expand(),
-            Some(n) => self.blocks[n].prev = prev,
-        }
-    }
-
-    /// Return an iterator over all blocks in layout order.
-    pub fn blocks(&self) -> Blocks {
-        Blocks {
-            layout: self,
-            next: self.first_block,
-        }
-    }
-
-    /// Get the function's entry block.
-    /// This is simply the first block in the layout order.
-    pub fn entry_block(&self) -> Option<Block> {
-        self.first_block
-    }
-
-    /// Get the last block in the layout.
-    pub fn last_block(&self) -> Option<Block> {
-        self.last_block
-    }
-
-    /// Get the block preceding `block` in the layout order.
-    pub fn prev_block(&self, block: Block) -> Option<Block> {
-        self.blocks[block].prev.expand()
-    }
-
-    /// Get the block following `block` in the layout order.
-    pub fn next_block(&self, block: Block) -> Option<Block> {
-        self.blocks[block].next.expand()
-    }
-
-    /// Mark a block as "cold".
-    ///
-    /// This will try to move it out of the ordinary path of execution
-    /// when lowered to machine code.
-    pub fn set_cold(&mut self, block: Block) {
-        self.blocks[block].cold = true;
-    }
-
-    /// Is the given block cold?
-    pub fn is_cold(&self, block: Block) -> bool {
-        self.blocks[block].cold
-    }
-}
-
-#[derive(Clone, Debug, Default)]
-struct BlockNode {
-    prev: PackedOption<Block>,
-    next: PackedOption<Block>,
-    first_inst: PackedOption<Inst>,
-    last_inst: PackedOption<Inst>,
-    seq: SequenceNumber,
-    cold: bool,
-}
-
-/// Iterate over blocks in layout order. See [crate::ir::layout::Layout::blocks].
-pub struct Blocks<'f> {
-    layout: &'f Layout,
-    next: Option<Block>,
-}
-
-impl<'f> Iterator for Blocks<'f> {
-    type Item = Block;
-
-    fn next(&mut self) -> Option<Block> {
-        match self.next {
-            Some(block) => {
-                self.next = self.layout.next_block(block);
-                Some(block)
-            }
-            None => None,
-        }
-    }
-}
-
-/// Use a layout reference in a for loop.
-impl<'f> IntoIterator for &'f Layout {
-    type Item = Block;
-    type IntoIter = Blocks<'f>;
-
-    fn into_iter(self) -> Blocks<'f> {
-        self.blocks()
-    }
-}
-
-/// Methods for arranging instructions.
-///
-/// An instruction starts out as *not inserted* in the layout. An instruction can be inserted into
-/// a block at a given position.
-impl Layout {
-    /// Get the block containing `inst`, or `None` if `inst` is not inserted in the layout.
-    pub fn inst_block(&self, inst: Inst) -> Option<Block> {
-        self.insts[inst].block.into()
-    }
-
-    /// Get the block containing the program point `pp`. Panic if `pp` is not in the layout.
-    pub fn pp_block<PP>(&self, pp: PP) -> Block
-    where
-        PP: Into<ExpandedProgramPoint>,
-    {
-        match pp.into() {
-            ExpandedProgramPoint::Block(block) => block,
-            ExpandedProgramPoint::Inst(inst) => {
-                self.inst_block(inst).expect("Program point not in layout")
-            }
-        }
-    }
-
-    /// Append `inst` to the end of `block`.
-    pub fn append_inst(&mut self, inst: Inst, block: Block) {
-        debug_assert_eq!(self.inst_block(inst), None);
-        debug_assert!(
-            self.is_block_inserted(block),
-            "Cannot append instructions to block not in layout"
-        );
-        {
-            let block_node = &mut self.blocks[block];
-            {
-                let inst_node = &mut self.insts[inst];
-                inst_node.block = block.into();
-                inst_node.prev = block_node.last_inst;
-                debug_assert!(inst_node.next.is_none());
-            }
-            if block_node.first_inst.is_none() {
-                block_node.first_inst = inst.into();
-            } else {
-                self.insts[block_node.last_inst.unwrap()].next = inst.into();
-            }
-            block_node.last_inst = inst.into();
-        }
-        self.assign_inst_seq(inst);
-    }
-
-    /// Fetch a block's first instruction.
-    pub fn first_inst(&self, block: Block) -> Option<Inst> {
-        self.blocks[block].first_inst.into()
-    }
-
-    /// Fetch a block's last instruction.
-    pub fn last_inst(&self, block: Block) -> Option<Inst> {
-        self.blocks[block].last_inst.into()
-    }
-
-    /// Fetch the instruction following `inst`.
-    pub fn next_inst(&self, inst: Inst) -> Option<Inst> {
-        self.insts[inst].next.expand()
-    }
-
-    /// Fetch the instruction preceding `inst`.
-    pub fn prev_inst(&self, inst: Inst) -> Option<Inst> {
-        self.insts[inst].prev.expand()
-    }
-
-    /// Fetch the first instruction in a block's terminal branch group.
-    pub fn canonical_branch_inst(&self, dfg: &DataFlowGraph, block: Block) -> Option<Inst> {
-        // Basic blocks permit at most two terminal branch instructions.
-        // If two, the former is conditional and the latter is unconditional.
-        let last = self.last_inst(block)?;
-        if let Some(prev) = self.prev_inst(last) {
-            if dfg[prev].opcode().is_branch() {
-                return Some(prev);
-            }
-        }
-        Some(last)
-    }
-
-    /// Insert `inst` before the instruction `before` in the same block.
-    pub fn insert_inst(&mut self, inst: Inst, before: Inst) {
-        debug_assert_eq!(self.inst_block(inst), None);
-        let block = self
-            .inst_block(before)
-            .expect("Instruction before insertion point not in the layout");
-        let after = self.insts[before].prev;
-        {
-            let inst_node = &mut self.insts[inst];
-            inst_node.block = block.into();
-            inst_node.next = before.into();
-            inst_node.prev = after;
-        }
-        self.insts[before].prev = inst.into();
-        match after.expand() {
-            None => self.blocks[block].first_inst = inst.into(),
-            Some(a) => self.insts[a].next = inst.into(),
-        }
-        self.assign_inst_seq(inst);
-    }
-
-    /// Remove `inst` from the layout.
-    pub fn remove_inst(&mut self, inst: Inst) {
-        let block = self.inst_block(inst).expect("Instruction already removed.");
-        // Clear the `inst` node and extract links.
-        let prev;
-        let next;
-        {
-            let n = &mut self.insts[inst];
-            prev = n.prev;
-            next = n.next;
-            n.block = None.into();
-            n.prev = None.into();
-            n.next = None.into();
-        }
-        // Fix up links to `inst`.
-        match prev.expand() {
-            None => self.blocks[block].first_inst = next,
-            Some(p) => self.insts[p].next = next,
-        }
-        match next.expand() {
-            None => self.blocks[block].last_inst = prev,
-            Some(n) => self.insts[n].prev = prev,
-        }
-    }
-
-    /// Iterate over the instructions in `block` in layout order.
-    pub fn block_insts(&self, block: Block) -> Insts {
-        Insts {
-            layout: self,
-            head: self.blocks[block].first_inst.into(),
-            tail: self.blocks[block].last_inst.into(),
-        }
-    }
-
-    /// Iterate over a limited set of instruction which are likely the branches of `block` in layout
-    /// order. Any instruction not visited by this iterator is not a branch, but an instruction visited by this may not be a branch.
-    pub fn block_likely_branches(&self, block: Block) -> Insts {
-        // Note: Checking whether an instruction is a branch or not while walking backward might add
-        // extra overhead. However, we know that the number of branches is limited to 2 at the end of
-        // each block, and therefore we can just iterate over the last 2 instructions.
-        let mut iter = self.block_insts(block);
-        let head = iter.head;
-        let tail = iter.tail;
-        iter.next_back();
-        let head = iter.next_back().or(head);
-        Insts {
-            layout: self,
-            head,
-            tail,
-        }
-    }
-
-    /// Split the block containing `before` in two.
-    ///
-    /// Insert `new_block` after the old block and move `before` and the following instructions to
-    /// `new_block`:
-    ///
-    /// ```text
-    /// old_block:
-    ///     i1
-    ///     i2
-    ///     i3 << before
-    ///     i4
-    /// ```
-    /// becomes:
-    ///
-    /// ```text
-    /// old_block:
-    ///     i1
-    ///     i2
-    /// new_block:
-    ///     i3 << before
-    ///     i4
-    /// ```
-    pub fn split_block(&mut self, new_block: Block, before: Inst) {
-        let old_block = self
-            .inst_block(before)
-            .expect("The `before` instruction must be in the layout");
-        debug_assert!(!self.is_block_inserted(new_block));
-
-        // Insert new_block after old_block.
-        let next_block = self.blocks[old_block].next;
-        let last_inst = self.blocks[old_block].last_inst;
-        {
-            let node = &mut self.blocks[new_block];
-            node.prev = old_block.into();
-            node.next = next_block;
-            node.first_inst = before.into();
-            node.last_inst = last_inst;
-        }
-        self.blocks[old_block].next = new_block.into();
-
-        // Fix backwards link.
-        if Some(old_block) == self.last_block {
-            self.last_block = Some(new_block);
-        } else {
-            self.blocks[next_block.unwrap()].prev = new_block.into();
-        }
-
-        // Disconnect the instruction links.
-        let prev_inst = self.insts[before].prev;
-        self.insts[before].prev = None.into();
-        self.blocks[old_block].last_inst = prev_inst;
-        match prev_inst.expand() {
-            None => self.blocks[old_block].first_inst = None.into(),
-            Some(pi) => self.insts[pi].next = None.into(),
-        }
-
-        // Fix the instruction -> block pointers.
-        let mut opt_i = Some(before);
-        while let Some(i) = opt_i {
-            debug_assert_eq!(self.insts[i].block.expand(), Some(old_block));
-            self.insts[i].block = new_block.into();
-            opt_i = self.insts[i].next.into();
-        }
-
-        self.assign_block_seq(new_block);
-    }
-}
-
-#[derive(Clone, Debug, Default)]
-struct InstNode {
-    /// The Block containing this instruction, or `None` if the instruction is not yet inserted.
-    block: PackedOption<Block>,
-    prev: PackedOption<Inst>,
-    next: PackedOption<Inst>,
-    seq: SequenceNumber,
-}
-
-/// Iterate over instructions in a block in layout order. See `Layout::block_insts()`.
-pub struct Insts<'f> {
-    layout: &'f Layout,
-    head: Option<Inst>,
-    tail: Option<Inst>,
-}
-
-impl<'f> Iterator for Insts<'f> {
-    type Item = Inst;
-
-    fn next(&mut self) -> Option<Inst> {
-        let rval = self.head;
-        if let Some(inst) = rval {
-            if self.head == self.tail {
-                self.head = None;
-                self.tail = None;
-            } else {
-                self.head = self.layout.insts[inst].next.into();
-            }
-        }
-        rval
-    }
-}
-
-impl<'f> DoubleEndedIterator for Insts<'f> {
-    fn next_back(&mut self) -> Option<Inst> {
-        let rval = self.tail;
-        if let Some(inst) = rval {
-            if self.head == self.tail {
-                self.head = None;
-                self.tail = None;
-            } else {
-                self.tail = self.layout.insts[inst].prev.into();
-            }
-        }
-        rval
-    }
-}
-
-/// A custom serialize and deserialize implementation for [`Layout`].
-///
-/// This doesn't use a derived implementation as [`Layout`] is a manual implementation of a linked
-/// list. Storing it directly as a regular list saves a lot of space.
-///
-/// The following format is used. (notated in EBNF form)
-///
-/// ```plain
-/// data = block_data * ;
-/// block_data = "block_id" , "inst_count" , ( "inst_id" * ) ;
-/// ```
-#[cfg(feature = "enable-serde")]
-mod serde {
-    use ::serde::de::{Deserializer, Error, SeqAccess, Visitor};
-    use ::serde::ser::{SerializeSeq, Serializer};
-    use ::serde::{Deserialize, Serialize};
-    use core::convert::TryFrom;
-    use core::fmt;
-    use core::marker::PhantomData;
-
-    use super::*;
-
-    impl Serialize for Layout {
-        fn serialize<S>(&self, serializer: S) -> Result<S::Ok, S::Error>
-        where
-            S: Serializer,
-        {
-            let size = self.blocks().count() * 2
-                + self
-                    .blocks()
-                    .map(|block| self.block_insts(block).count())
-                    .sum::<usize>();
-            let mut seq = serializer.serialize_seq(Some(size))?;
-            for block in self.blocks() {
-                seq.serialize_element(&block)?;
-                seq.serialize_element(&u32::try_from(self.block_insts(block).count()).unwrap())?;
-                for inst in self.block_insts(block) {
-                    seq.serialize_element(&inst)?;
-                }
-            }
-            seq.end()
-        }
-    }
-
-    impl<'de> Deserialize<'de> for Layout {
-        fn deserialize<D>(deserializer: D) -> Result<Self, D::Error>
-        where
-            D: Deserializer<'de>,
-        {
-            deserializer.deserialize_seq(LayoutVisitor {
-                marker: PhantomData,
-            })
-        }
-    }
-
-    struct LayoutVisitor {
-        marker: PhantomData<fn() -> Layout>,
-    }
-
-    impl<'de> Visitor<'de> for LayoutVisitor {
-        type Value = Layout;
-
-        fn expecting(&self, formatter: &mut fmt::Formatter) -> fmt::Result {
-            write!(formatter, "a `cranelift_codegen::ir::Layout`")
-        }
-
-        fn visit_seq<M>(self, mut access: M) -> Result<Self::Value, M::Error>
-        where
-            M: SeqAccess<'de>,
-        {
-            let mut layout = Layout::new();
-
-            while let Some(block) = access.next_element::<Block>()? {
-                layout.append_block(block);
-
-                let count = access
-                    .next_element::<u32>()?
-                    .ok_or_else(|| Error::missing_field("count"))?;
-                for _ in 0..count {
-                    let inst = access
-                        .next_element::<Inst>()?
-                        .ok_or_else(|| Error::missing_field("inst"))?;
-                    layout.append_inst(inst, block);
-                }
-            }
-
-            Ok(layout)
-        }
-    }
-}
-
-#[cfg(test)]
-mod tests {
-    use super::Layout;
-    use crate::cursor::{Cursor, CursorPosition};
-    use crate::entity::EntityRef;
-    use crate::ir::{Block, Inst, ProgramOrder, SourceLoc};
-    use alloc::vec::Vec;
-    use core::cmp::Ordering;
-
-    struct LayoutCursor<'f> {
-        /// Borrowed function layout. Public so it can be re-borrowed from this cursor.
-        pub layout: &'f mut Layout,
-        pos: CursorPosition,
-    }
-
-    impl<'f> Cursor for LayoutCursor<'f> {
-        fn position(&self) -> CursorPosition {
-            self.pos
-        }
-
-        fn set_position(&mut self, pos: CursorPosition) {
-            self.pos = pos;
-        }
-
-        fn srcloc(&self) -> SourceLoc {
-            unimplemented!()
-        }
-
-        fn set_srcloc(&mut self, _srcloc: SourceLoc) {
-            unimplemented!()
-        }
-
-        fn layout(&self) -> &Layout {
-            self.layout
-        }
-
-        fn layout_mut(&mut self) -> &mut Layout {
-            self.layout
-        }
-    }
-
-    impl<'f> LayoutCursor<'f> {
-        /// Create a new `LayoutCursor` for `layout`.
-        /// The cursor holds a mutable reference to `layout` for its entire lifetime.
-        pub fn new(layout: &'f mut Layout) -> Self {
-            Self {
-                layout,
-                pos: CursorPosition::Nowhere,
-            }
-        }
-    }
-
-    fn verify(layout: &mut Layout, blocks: &[(Block, &[Inst])]) {
-        // Check that blocks are inserted and instructions belong the right places.
-        // Check forward linkage with iterators.
-        // Check that layout sequence numbers are strictly monotonic.
-        {
-            let mut seq = 0;
-            let mut block_iter = layout.blocks();
-            for &(block, insts) in blocks {
-                assert!(layout.is_block_inserted(block));
-                assert_eq!(block_iter.next(), Some(block));
-                assert!(layout.blocks[block].seq > seq);
-                seq = layout.blocks[block].seq;
-
-                let mut inst_iter = layout.block_insts(block);
-                for &inst in insts {
-                    assert_eq!(layout.inst_block(inst), Some(block));
-                    assert_eq!(inst_iter.next(), Some(inst));
-                    assert!(layout.insts[inst].seq > seq);
-                    seq = layout.insts[inst].seq;
-                }
-                assert_eq!(inst_iter.next(), None);
-            }
-            assert_eq!(block_iter.next(), None);
-        }
-
-        // Check backwards linkage with a cursor.
-        let mut cur = LayoutCursor::new(layout);
-        for &(block, insts) in blocks.into_iter().rev() {
-            assert_eq!(cur.prev_block(), Some(block));
-            for &inst in insts.into_iter().rev() {
-                assert_eq!(cur.prev_inst(), Some(inst));
-            }
-            assert_eq!(cur.prev_inst(), None);
-        }
-        assert_eq!(cur.prev_block(), None);
-    }
-
-    #[test]
-    fn append_block() {
-        let mut layout = Layout::new();
-        let e0 = Block::new(0);
-        let e1 = Block::new(1);
-        let e2 = Block::new(2);
-
-        {
-            let imm = &layout;
-            assert!(!imm.is_block_inserted(e0));
-            assert!(!imm.is_block_inserted(e1));
-        }
-        verify(&mut layout, &[]);
-
-        layout.append_block(e1);
-        assert!(!layout.is_block_inserted(e0));
-        assert!(layout.is_block_inserted(e1));
-        assert!(!layout.is_block_inserted(e2));
-        let v: Vec<Block> = layout.blocks().collect();
-        assert_eq!(v, [e1]);
-
-        layout.append_block(e2);
-        assert!(!layout.is_block_inserted(e0));
-        assert!(layout.is_block_inserted(e1));
-        assert!(layout.is_block_inserted(e2));
-        let v: Vec<Block> = layout.blocks().collect();
-        assert_eq!(v, [e1, e2]);
-
-        layout.append_block(e0);
-        assert!(layout.is_block_inserted(e0));
-        assert!(layout.is_block_inserted(e1));
-        assert!(layout.is_block_inserted(e2));
-        let v: Vec<Block> = layout.blocks().collect();
-        assert_eq!(v, [e1, e2, e0]);
-
-        {
-            let imm = &layout;
-            let mut v = Vec::new();
-            for e in imm {
-                v.push(e);
-            }
-            assert_eq!(v, [e1, e2, e0]);
-        }
-
-        // Test cursor positioning.
-        let mut cur = LayoutCursor::new(&mut layout);
-        assert_eq!(cur.position(), CursorPosition::Nowhere);
-        assert_eq!(cur.next_inst(), None);
-        assert_eq!(cur.position(), CursorPosition::Nowhere);
-        assert_eq!(cur.prev_inst(), None);
-        assert_eq!(cur.position(), CursorPosition::Nowhere);
-
-        assert_eq!(cur.next_block(), Some(e1));
-        assert_eq!(cur.position(), CursorPosition::Before(e1));
-        assert_eq!(cur.next_inst(), None);
-        assert_eq!(cur.position(), CursorPosition::After(e1));
-        assert_eq!(cur.next_inst(), None);
-        assert_eq!(cur.position(), CursorPosition::After(e1));
-        assert_eq!(cur.next_block(), Some(e2));
-        assert_eq!(cur.prev_inst(), None);
-        assert_eq!(cur.position(), CursorPosition::Before(e2));
-        assert_eq!(cur.next_block(), Some(e0));
-        assert_eq!(cur.next_block(), None);
-        assert_eq!(cur.position(), CursorPosition::Nowhere);
-
-        // Backwards through the blocks.
-        assert_eq!(cur.prev_block(), Some(e0));
-        assert_eq!(cur.position(), CursorPosition::After(e0));
-        assert_eq!(cur.prev_block(), Some(e2));
-        assert_eq!(cur.prev_block(), Some(e1));
-        assert_eq!(cur.prev_block(), None);
-        assert_eq!(cur.position(), CursorPosition::Nowhere);
-    }
-
-    #[test]
-    fn insert_block() {
-        let mut layout = Layout::new();
-        let e0 = Block::new(0);
-        let e1 = Block::new(1);
-        let e2 = Block::new(2);
-
-        {
-            let imm = &layout;
-            assert!(!imm.is_block_inserted(e0));
-            assert!(!imm.is_block_inserted(e1));
-
-            let v: Vec<Block> = layout.blocks().collect();
-            assert_eq!(v, []);
-        }
-
-        layout.append_block(e1);
-        assert!(!layout.is_block_inserted(e0));
-        assert!(layout.is_block_inserted(e1));
-        assert!(!layout.is_block_inserted(e2));
-        verify(&mut layout, &[(e1, &[])]);
-
-        layout.insert_block(e2, e1);
-        assert!(!layout.is_block_inserted(e0));
-        assert!(layout.is_block_inserted(e1));
-        assert!(layout.is_block_inserted(e2));
-        verify(&mut layout, &[(e2, &[]), (e1, &[])]);
-
-        layout.insert_block(e0, e1);
-        assert!(layout.is_block_inserted(e0));
-        assert!(layout.is_block_inserted(e1));
-        assert!(layout.is_block_inserted(e2));
-        verify(&mut layout, &[(e2, &[]), (e0, &[]), (e1, &[])]);
-    }
-
-    #[test]
-    fn insert_block_after() {
-        let mut layout = Layout::new();
-        let e0 = Block::new(0);
-        let e1 = Block::new(1);
-        let e2 = Block::new(2);
-
-        layout.append_block(e1);
-        layout.insert_block_after(e2, e1);
-        verify(&mut layout, &[(e1, &[]), (e2, &[])]);
-
-        layout.insert_block_after(e0, e1);
-        verify(&mut layout, &[(e1, &[]), (e0, &[]), (e2, &[])]);
-    }
-
-    #[test]
-    fn append_inst() {
-        let mut layout = Layout::new();
-        let e1 = Block::new(1);
-
-        layout.append_block(e1);
-        let v: Vec<Inst> = layout.block_insts(e1).collect();
-        assert_eq!(v, []);
-
-        let i0 = Inst::new(0);
-        let i1 = Inst::new(1);
-        let i2 = Inst::new(2);
-
-        assert_eq!(layout.inst_block(i0), None);
-        assert_eq!(layout.inst_block(i1), None);
-        assert_eq!(layout.inst_block(i2), None);
-
-        layout.append_inst(i1, e1);
-        assert_eq!(layout.inst_block(i0), None);
-        assert_eq!(layout.inst_block(i1), Some(e1));
-        assert_eq!(layout.inst_block(i2), None);
-        let v: Vec<Inst> = layout.block_insts(e1).collect();
-        assert_eq!(v, [i1]);
-
-        layout.append_inst(i2, e1);
-        assert_eq!(layout.inst_block(i0), None);
-        assert_eq!(layout.inst_block(i1), Some(e1));
-        assert_eq!(layout.inst_block(i2), Some(e1));
-        let v: Vec<Inst> = layout.block_insts(e1).collect();
-        assert_eq!(v, [i1, i2]);
-
-        // Test double-ended instruction iterator.
-        let v: Vec<Inst> = layout.block_insts(e1).rev().collect();
-        assert_eq!(v, [i2, i1]);
-
-        layout.append_inst(i0, e1);
-        verify(&mut layout, &[(e1, &[i1, i2, i0])]);
-
-        // Test cursor positioning.
-        let mut cur = LayoutCursor::new(&mut layout).at_top(e1);
-        assert_eq!(cur.position(), CursorPosition::Before(e1));
-        assert_eq!(cur.prev_inst(), None);
-        assert_eq!(cur.position(), CursorPosition::Before(e1));
-        assert_eq!(cur.next_inst(), Some(i1));
-        assert_eq!(cur.position(), CursorPosition::At(i1));
-        assert_eq!(cur.next_inst(), Some(i2));
-        assert_eq!(cur.next_inst(), Some(i0));
-        assert_eq!(cur.prev_inst(), Some(i2));
-        assert_eq!(cur.position(), CursorPosition::At(i2));
-        assert_eq!(cur.next_inst(), Some(i0));
-        assert_eq!(cur.position(), CursorPosition::At(i0));
-        assert_eq!(cur.next_inst(), None);
-        assert_eq!(cur.position(), CursorPosition::After(e1));
-        assert_eq!(cur.next_inst(), None);
-        assert_eq!(cur.position(), CursorPosition::After(e1));
-        assert_eq!(cur.prev_inst(), Some(i0));
-        assert_eq!(cur.prev_inst(), Some(i2));
-        assert_eq!(cur.prev_inst(), Some(i1));
-        assert_eq!(cur.prev_inst(), None);
-        assert_eq!(cur.position(), CursorPosition::Before(e1));
-
-        // Test remove_inst.
-        cur.goto_inst(i2);
-        assert_eq!(cur.remove_inst(), i2);
-        verify(cur.layout, &[(e1, &[i1, i0])]);
-        assert_eq!(cur.layout.inst_block(i2), None);
-        assert_eq!(cur.remove_inst(), i0);
-        verify(cur.layout, &[(e1, &[i1])]);
-        assert_eq!(cur.layout.inst_block(i0), None);
-        assert_eq!(cur.position(), CursorPosition::After(e1));
-        cur.layout.remove_inst(i1);
-        verify(cur.layout, &[(e1, &[])]);
-        assert_eq!(cur.layout.inst_block(i1), None);
-    }
-
-    #[test]
-    fn insert_inst() {
-        let mut layout = Layout::new();
-        let e1 = Block::new(1);
-
-        layout.append_block(e1);
-        let v: Vec<Inst> = layout.block_insts(e1).collect();
-        assert_eq!(v, []);
-
-        let i0 = Inst::new(0);
-        let i1 = Inst::new(1);
-        let i2 = Inst::new(2);
-
-        assert_eq!(layout.inst_block(i0), None);
-        assert_eq!(layout.inst_block(i1), None);
-        assert_eq!(layout.inst_block(i2), None);
-
-        layout.append_inst(i1, e1);
-        assert_eq!(layout.inst_block(i0), None);
-        assert_eq!(layout.inst_block(i1), Some(e1));
-        assert_eq!(layout.inst_block(i2), None);
-        let v: Vec<Inst> = layout.block_insts(e1).collect();
-        assert_eq!(v, [i1]);
-
-        layout.insert_inst(i2, i1);
-        assert_eq!(layout.inst_block(i0), None);
-        assert_eq!(layout.inst_block(i1), Some(e1));
-        assert_eq!(layout.inst_block(i2), Some(e1));
-        let v: Vec<Inst> = layout.block_insts(e1).collect();
-        assert_eq!(v, [i2, i1]);
-
-        layout.insert_inst(i0, i1);
-        verify(&mut layout, &[(e1, &[i2, i0, i1])]);
-    }
-
-    #[test]
-    fn multiple_blocks() {
-        let mut layout = Layout::new();
-
-        let e0 = Block::new(0);
-        let e1 = Block::new(1);
-
-        assert_eq!(layout.entry_block(), None);
-        layout.append_block(e0);
-        assert_eq!(layout.entry_block(), Some(e0));
-        layout.append_block(e1);
-        assert_eq!(layout.entry_block(), Some(e0));
-
-        let i0 = Inst::new(0);
-        let i1 = Inst::new(1);
-        let i2 = Inst::new(2);
-        let i3 = Inst::new(3);
-
-        layout.append_inst(i0, e0);
-        layout.append_inst(i1, e0);
-        layout.append_inst(i2, e1);
-        layout.append_inst(i3, e1);
-
-        let v0: Vec<Inst> = layout.block_insts(e0).collect();
-        let v1: Vec<Inst> = layout.block_insts(e1).collect();
-        assert_eq!(v0, [i0, i1]);
-        assert_eq!(v1, [i2, i3]);
-    }
-
-    #[test]
-    fn split_block() {
-        let mut layout = Layout::new();
-
-        let e0 = Block::new(0);
-        let e1 = Block::new(1);
-        let e2 = Block::new(2);
-
-        let i0 = Inst::new(0);
-        let i1 = Inst::new(1);
-        let i2 = Inst::new(2);
-        let i3 = Inst::new(3);
-
-        layout.append_block(e0);
-        layout.append_inst(i0, e0);
-        assert_eq!(layout.inst_block(i0), Some(e0));
-        layout.split_block(e1, i0);
-        assert_eq!(layout.inst_block(i0), Some(e1));
-
-        {
-            let mut cur = LayoutCursor::new(&mut layout);
-            assert_eq!(cur.next_block(), Some(e0));
-            assert_eq!(cur.next_inst(), None);
-            assert_eq!(cur.next_block(), Some(e1));
-            assert_eq!(cur.next_inst(), Some(i0));
-            assert_eq!(cur.next_inst(), None);
-            assert_eq!(cur.next_block(), None);
-
-            // Check backwards links.
-            assert_eq!(cur.prev_block(), Some(e1));
-            assert_eq!(cur.prev_inst(), Some(i0));
-            assert_eq!(cur.prev_inst(), None);
-            assert_eq!(cur.prev_block(), Some(e0));
-            assert_eq!(cur.prev_inst(), None);
-            assert_eq!(cur.prev_block(), None);
-        }
-
-        layout.append_inst(i1, e0);
-        layout.append_inst(i2, e0);
-        layout.append_inst(i3, e0);
-        layout.split_block(e2, i2);
-
-        assert_eq!(layout.inst_block(i0), Some(e1));
-        assert_eq!(layout.inst_block(i1), Some(e0));
-        assert_eq!(layout.inst_block(i2), Some(e2));
-        assert_eq!(layout.inst_block(i3), Some(e2));
-
-        {
-            let mut cur = LayoutCursor::new(&mut layout);
-            assert_eq!(cur.next_block(), Some(e0));
-            assert_eq!(cur.next_inst(), Some(i1));
-            assert_eq!(cur.next_inst(), None);
-            assert_eq!(cur.next_block(), Some(e2));
-            assert_eq!(cur.next_inst(), Some(i2));
-            assert_eq!(cur.next_inst(), Some(i3));
-            assert_eq!(cur.next_inst(), None);
-            assert_eq!(cur.next_block(), Some(e1));
-            assert_eq!(cur.next_inst(), Some(i0));
-            assert_eq!(cur.next_inst(), None);
-            assert_eq!(cur.next_block(), None);
-
-            assert_eq!(cur.prev_block(), Some(e1));
-            assert_eq!(cur.prev_inst(), Some(i0));
-            assert_eq!(cur.prev_inst(), None);
-            assert_eq!(cur.prev_block(), Some(e2));
-            assert_eq!(cur.prev_inst(), Some(i3));
-            assert_eq!(cur.prev_inst(), Some(i2));
-            assert_eq!(cur.prev_inst(), None);
-            assert_eq!(cur.prev_block(), Some(e0));
-            assert_eq!(cur.prev_inst(), Some(i1));
-            assert_eq!(cur.prev_inst(), None);
-            assert_eq!(cur.prev_block(), None);
-        }
-
-        // Check `ProgramOrder`.
-        assert_eq!(layout.cmp(e2, e2), Ordering::Equal);
-        assert_eq!(layout.cmp(e2, i2), Ordering::Less);
-        assert_eq!(layout.cmp(i3, i2), Ordering::Greater);
-
-        assert_eq!(layout.is_block_gap(i1, e2), true);
-        assert_eq!(layout.is_block_gap(i3, e1), true);
-        assert_eq!(layout.is_block_gap(i1, e1), false);
-        assert_eq!(layout.is_block_gap(i2, e1), false);
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/libcall.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/libcall.rs
deleted file mode 100644
index 5dbbd7232..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/libcall.rs
+++ /dev/null
@@ -1,215 +0,0 @@
-//! Naming well-known routines in the runtime library.
-
-use crate::ir::{types, ExternalName, FuncRef, Function, Opcode, Type};
-use core::fmt;
-use core::str::FromStr;
-#[cfg(feature = "enable-serde")]
-use serde::{Deserialize, Serialize};
-
-/// The name of a runtime library routine.
-///
-/// Runtime library calls are generated for Cranelift IR instructions that don't have an equivalent
-/// ISA instruction or an easy macro expansion. A `LibCall` is used as a well-known name to refer to
-/// the runtime library routine. This way, Cranelift doesn't have to know about the naming
-/// convention in the embedding VM's runtime library.
-///
-/// This list is likely to grow over time.
-#[derive(Copy, Clone, Debug, PartialEq, Eq, Hash)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub enum LibCall {
-    /// probe for stack overflow. These are emitted for functions which need
-    /// when the `enable_probestack` setting is true.
-    Probestack,
-    /// udiv.i64
-    UdivI64,
-    /// sdiv.i64
-    SdivI64,
-    /// urem.i64
-    UremI64,
-    /// srem.i64
-    SremI64,
-    /// ishl.i64
-    IshlI64,
-    /// ushr.i64
-    UshrI64,
-    /// sshr.i64
-    SshrI64,
-    /// ceil.f32
-    CeilF32,
-    /// ceil.f64
-    CeilF64,
-    /// floor.f32
-    FloorF32,
-    /// floor.f64
-    FloorF64,
-    /// trunc.f32
-    TruncF32,
-    /// frunc.f64
-    TruncF64,
-    /// nearest.f32
-    NearestF32,
-    /// nearest.f64
-    NearestF64,
-    /// libc.memcpy
-    Memcpy,
-    /// libc.memset
-    Memset,
-    /// libc.memmove
-    Memmove,
-    /// libc.memcmp
-    Memcmp,
-
-    /// Elf __tls_get_addr
-    ElfTlsGetAddr,
-    // When adding a new variant make sure to add it to `all_libcalls` too.
-}
-
-impl fmt::Display for LibCall {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        fmt::Debug::fmt(self, f)
-    }
-}
-
-impl FromStr for LibCall {
-    type Err = ();
-
-    fn from_str(s: &str) -> Result<Self, Self::Err> {
-        match s {
-            "Probestack" => Ok(Self::Probestack),
-            "UdivI64" => Ok(Self::UdivI64),
-            "SdivI64" => Ok(Self::SdivI64),
-            "UremI64" => Ok(Self::UremI64),
-            "SremI64" => Ok(Self::SremI64),
-            "IshlI64" => Ok(Self::IshlI64),
-            "UshrI64" => Ok(Self::UshrI64),
-            "SshrI64" => Ok(Self::SshrI64),
-            "CeilF32" => Ok(Self::CeilF32),
-            "CeilF64" => Ok(Self::CeilF64),
-            "FloorF32" => Ok(Self::FloorF32),
-            "FloorF64" => Ok(Self::FloorF64),
-            "TruncF32" => Ok(Self::TruncF32),
-            "TruncF64" => Ok(Self::TruncF64),
-            "NearestF32" => Ok(Self::NearestF32),
-            "NearestF64" => Ok(Self::NearestF64),
-            "Memcpy" => Ok(Self::Memcpy),
-            "Memset" => Ok(Self::Memset),
-            "Memmove" => Ok(Self::Memmove),
-            "Memcmp" => Ok(Self::Memcmp),
-
-            "ElfTlsGetAddr" => Ok(Self::ElfTlsGetAddr),
-            _ => Err(()),
-        }
-    }
-}
-
-impl LibCall {
-    /// Get the well-known library call name to use as a replacement for an instruction with the
-    /// given opcode and controlling type variable.
-    ///
-    /// Returns `None` if no well-known library routine name exists for that instruction.
-    pub fn for_inst(opcode: Opcode, ctrl_type: Type) -> Option<Self> {
-        Some(match ctrl_type {
-            types::I64 => match opcode {
-                Opcode::Udiv => Self::UdivI64,
-                Opcode::Sdiv => Self::SdivI64,
-                Opcode::Urem => Self::UremI64,
-                Opcode::Srem => Self::SremI64,
-                Opcode::Ishl => Self::IshlI64,
-                Opcode::Ushr => Self::UshrI64,
-                Opcode::Sshr => Self::SshrI64,
-                _ => return None,
-            },
-            types::F32 => match opcode {
-                Opcode::Ceil => Self::CeilF32,
-                Opcode::Floor => Self::FloorF32,
-                Opcode::Trunc => Self::TruncF32,
-                Opcode::Nearest => Self::NearestF32,
-                _ => return None,
-            },
-            types::F64 => match opcode {
-                Opcode::Ceil => Self::CeilF64,
-                Opcode::Floor => Self::FloorF64,
-                Opcode::Trunc => Self::TruncF64,
-                Opcode::Nearest => Self::NearestF64,
-                _ => return None,
-            },
-            _ => return None,
-        })
-    }
-
-    /// Get a list of all known `LibCall`'s.
-    pub fn all_libcalls() -> &'static [LibCall] {
-        use LibCall::*;
-        &[
-            Probestack,
-            UdivI64,
-            SdivI64,
-            UremI64,
-            SremI64,
-            IshlI64,
-            UshrI64,
-            SshrI64,
-            CeilF32,
-            CeilF64,
-            FloorF32,
-            FloorF64,
-            TruncF32,
-            TruncF64,
-            NearestF32,
-            NearestF64,
-            Memcpy,
-            Memset,
-            Memmove,
-            Memcmp,
-            ElfTlsGetAddr,
-        ]
-    }
-}
-
-/// Get a function reference for the probestack function in `func`.
-///
-/// If there is an existing reference, use it, otherwise make a new one.
-pub fn get_probestack_funcref(func: &mut Function) -> Option<FuncRef> {
-    find_funcref(LibCall::Probestack, func)
-}
-
-/// Get the existing function reference for `libcall` in `func` if it exists.
-fn find_funcref(libcall: LibCall, func: &Function) -> Option<FuncRef> {
-    // We're assuming that all libcall function decls are at the end.
-    // If we get this wrong, worst case we'll have duplicate libcall decls which is harmless.
-    for (fref, func_data) in func.dfg.ext_funcs.iter().rev() {
-        match func_data.name {
-            ExternalName::LibCall(lc) => {
-                if lc == libcall {
-                    return Some(fref);
-                }
-            }
-            _ => break,
-        }
-    }
-    None
-}
-
-#[cfg(test)]
-mod tests {
-    use super::*;
-    use alloc::string::ToString;
-
-    #[test]
-    fn display() {
-        assert_eq!(LibCall::CeilF32.to_string(), "CeilF32");
-        assert_eq!(LibCall::NearestF64.to_string(), "NearestF64");
-    }
-
-    #[test]
-    fn parsing() {
-        assert_eq!("FloorF32".parse(), Ok(LibCall::FloorF32));
-    }
-
-    #[test]
-    fn all_libcalls_to_from_string() {
-        for &libcall in LibCall::all_libcalls() {
-            assert_eq!(libcall.to_string().parse(), Ok(libcall));
-        }
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/memflags.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/memflags.rs
deleted file mode 100644
index 4ff76b623..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/memflags.rs
+++ /dev/null
@@ -1,169 +0,0 @@
-//! Memory operation flags.
-
-use core::fmt;
-
-#[cfg(feature = "enable-serde")]
-use serde::{Deserialize, Serialize};
-
-enum FlagBit {
-    Notrap,
-    Aligned,
-    Readonly,
-    LittleEndian,
-    BigEndian,
-}
-
-const NAMES: [&str; 5] = ["notrap", "aligned", "readonly", "little", "big"];
-
-/// Endianness of a memory access.
-#[derive(Clone, Copy, PartialEq, Eq, Debug, Hash)]
-pub enum Endianness {
-    /// Little-endian
-    Little,
-    /// Big-endian
-    Big,
-}
-
-/// Flags for memory operations like load/store.
-///
-/// Each of these flags introduce a limited form of undefined behavior. The flags each enable
-/// certain optimizations that need to make additional assumptions. Generally, the semantics of a
-/// program does not change when a flag is removed, but adding a flag will.
-///
-/// In addition, the flags determine the endianness of the memory access.  By default,
-/// any memory access uses the native endianness determined by the target ISA.  This can
-/// be overridden for individual accesses by explicitly specifying little- or big-endian
-/// semantics via the flags.
-#[derive(Clone, Copy, Debug, Hash, PartialEq, Eq)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub struct MemFlags {
-    bits: u8,
-}
-
-impl MemFlags {
-    /// Create a new empty set of flags.
-    pub fn new() -> Self {
-        Self { bits: 0 }
-    }
-
-    /// Create a set of flags representing an access from a "trusted" address, meaning it's
-    /// known to be aligned and non-trapping.
-    pub fn trusted() -> Self {
-        let mut result = Self::new();
-        result.set_notrap();
-        result.set_aligned();
-        result
-    }
-
-    /// Read a flag bit.
-    fn read(self, bit: FlagBit) -> bool {
-        self.bits & (1 << bit as usize) != 0
-    }
-
-    /// Set a flag bit.
-    fn set(&mut self, bit: FlagBit) {
-        self.bits |= 1 << bit as usize
-    }
-
-    /// Set a flag bit by name.
-    ///
-    /// Returns true if the flag was found and set, false for an unknown flag name.
-    /// Will also return false when trying to set inconsistent endianness flags.
-    pub fn set_by_name(&mut self, name: &str) -> bool {
-        match NAMES.iter().position(|&s| s == name) {
-            Some(bit) => {
-                let bits = self.bits | 1 << bit;
-                if (bits & (1 << FlagBit::LittleEndian as usize)) != 0
-                    && (bits & (1 << FlagBit::BigEndian as usize)) != 0
-                {
-                    false
-                } else {
-                    self.bits = bits;
-                    true
-                }
-            }
-            None => false,
-        }
-    }
-
-    /// Return endianness of the memory access.  This will return the endianness
-    /// explicitly specified by the flags if any, and will default to the native
-    /// endianness otherwise.  The native endianness has to be provided by the
-    /// caller since it is not explicitly encoded in CLIF IR -- this allows a
-    /// front end to create IR without having to know the target endianness.
-    pub fn endianness(self, native_endianness: Endianness) -> Endianness {
-        if self.read(FlagBit::LittleEndian) {
-            Endianness::Little
-        } else if self.read(FlagBit::BigEndian) {
-            Endianness::Big
-        } else {
-            native_endianness
-        }
-    }
-
-    /// Set endianness of the memory access.
-    pub fn set_endianness(&mut self, endianness: Endianness) {
-        match endianness {
-            Endianness::Little => self.set(FlagBit::LittleEndian),
-            Endianness::Big => self.set(FlagBit::BigEndian),
-        };
-        assert!(!(self.read(FlagBit::LittleEndian) && self.read(FlagBit::BigEndian)));
-    }
-
-    /// Test if the `notrap` flag is set.
-    ///
-    /// Normally, trapping is part of the semantics of a load/store operation. If the platform
-    /// would cause a trap when accessing the effective address, the Cranelift memory operation is
-    /// also required to trap.
-    ///
-    /// The `notrap` flag tells Cranelift that the memory is *accessible*, which means that
-    /// accesses will not trap. This makes it possible to delete an unused load or a dead store
-    /// instruction.
-    pub fn notrap(self) -> bool {
-        self.read(FlagBit::Notrap)
-    }
-
-    /// Set the `notrap` flag.
-    pub fn set_notrap(&mut self) {
-        self.set(FlagBit::Notrap)
-    }
-
-    /// Test if the `aligned` flag is set.
-    ///
-    /// By default, Cranelift memory instructions work with any unaligned effective address. If the
-    /// `aligned` flag is set, the instruction is permitted to trap or return a wrong result if the
-    /// effective address is misaligned.
-    pub fn aligned(self) -> bool {
-        self.read(FlagBit::Aligned)
-    }
-
-    /// Set the `aligned` flag.
-    pub fn set_aligned(&mut self) {
-        self.set(FlagBit::Aligned)
-    }
-
-    /// Test if the `readonly` flag is set.
-    ///
-    /// Loads with this flag have no memory dependencies.
-    /// This results in undefined behavior if the dereferenced memory is mutated at any time
-    /// between when the function is called and when it is exited.
-    pub fn readonly(self) -> bool {
-        self.read(FlagBit::Readonly)
-    }
-
-    /// Set the `readonly` flag.
-    pub fn set_readonly(&mut self) {
-        self.set(FlagBit::Readonly)
-    }
-}
-
-impl fmt::Display for MemFlags {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        for (i, n) in NAMES.iter().enumerate() {
-            if self.bits & (1 << i) != 0 {
-                write!(f, " {}", n)?;
-            }
-        }
-        Ok(())
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/mod.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/mod.rs
deleted file mode 100644
index 713d2fd37..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/mod.rs
+++ /dev/null
@@ -1,102 +0,0 @@
-//! Representation of Cranelift IR functions.
-
-mod atomic_rmw_op;
-mod builder;
-pub mod condcodes;
-pub mod constant;
-pub mod dfg;
-pub mod entities;
-mod extfunc;
-mod extname;
-pub mod function;
-mod globalvalue;
-mod heap;
-pub mod immediates;
-pub mod instructions;
-pub mod jumptable;
-pub mod layout;
-pub(crate) mod libcall;
-mod memflags;
-mod progpoint;
-mod sourceloc;
-pub mod stackslot;
-mod table;
-mod trapcode;
-pub mod types;
-
-#[cfg(feature = "enable-serde")]
-use serde::{Deserialize, Serialize};
-
-pub use crate::ir::atomic_rmw_op::AtomicRmwOp;
-pub use crate::ir::builder::{
-    InsertBuilder, InstBuilder, InstBuilderBase, InstInserterBase, ReplaceBuilder,
-};
-pub use crate::ir::constant::{ConstantData, ConstantPool};
-pub use crate::ir::dfg::{DataFlowGraph, ValueDef};
-pub use crate::ir::entities::{
-    Block, Constant, FuncRef, GlobalValue, Heap, Immediate, Inst, JumpTable, SigRef, StackSlot,
-    Table, Value,
-};
-pub use crate::ir::extfunc::{
-    AbiParam, ArgumentExtension, ArgumentPurpose, ExtFuncData, Signature,
-};
-pub use crate::ir::extname::ExternalName;
-pub use crate::ir::function::{DisplayFunctionAnnotations, Function};
-pub use crate::ir::globalvalue::GlobalValueData;
-pub use crate::ir::heap::{HeapData, HeapStyle};
-pub use crate::ir::instructions::{
-    InstructionData, Opcode, ValueList, ValueListPool, VariableArgs,
-};
-pub use crate::ir::jumptable::JumpTableData;
-pub use crate::ir::layout::Layout;
-pub use crate::ir::libcall::{get_probestack_funcref, LibCall};
-pub use crate::ir::memflags::{Endianness, MemFlags};
-pub use crate::ir::progpoint::{ExpandedProgramPoint, ProgramOrder, ProgramPoint};
-pub use crate::ir::sourceloc::SourceLoc;
-pub use crate::ir::stackslot::{StackSlotData, StackSlotKind, StackSlots};
-pub use crate::ir::table::TableData;
-pub use crate::ir::trapcode::TrapCode;
-pub use crate::ir::types::Type;
-pub use crate::value_label::LabelValueLoc;
-
-use crate::entity::{entity_impl, PrimaryMap, SecondaryMap};
-
-/// Map of jump tables.
-pub type JumpTables = PrimaryMap<JumpTable, JumpTableData>;
-
-/// Source locations for instructions.
-pub type SourceLocs = SecondaryMap<Inst, SourceLoc>;
-
-/// Marked with a label value.
-#[derive(Copy, Clone, PartialEq, Eq, Hash)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub struct ValueLabel(u32);
-entity_impl!(ValueLabel, "val");
-
-/// A label of a Value.
-#[derive(Debug, Clone)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub struct ValueLabelStart {
-    /// Source location when it is in effect
-    pub from: SourceLoc,
-
-    /// The label index.
-    pub label: ValueLabel,
-}
-
-/// Value label assignements: label starts or value aliases.
-#[derive(Debug, Clone)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub enum ValueLabelAssignments {
-    /// Original value labels assigned at transform.
-    Starts(alloc::vec::Vec<ValueLabelStart>),
-
-    /// A value alias to original value.
-    Alias {
-        /// Source location when it is in effect
-        from: SourceLoc,
-
-        /// The label index.
-        value: Value,
-    },
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/progpoint.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/progpoint.rs
deleted file mode 100644
index 0152949e7..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/progpoint.rs
+++ /dev/null
@@ -1,164 +0,0 @@
-//! Program points.
-
-use crate::entity::EntityRef;
-use crate::ir::{Block, Inst, ValueDef};
-use core::cmp;
-use core::fmt;
-use core::u32;
-
-/// A `ProgramPoint` represents a position in a function where the live range of an SSA value can
-/// begin or end. It can be either:
-///
-/// 1. An instruction or
-/// 2. A block header.
-///
-/// This corresponds more or less to the lines in the textual form of Cranelift IR.
-#[derive(PartialEq, Eq, Clone, Copy)]
-pub struct ProgramPoint(u32);
-
-impl From<Inst> for ProgramPoint {
-    fn from(inst: Inst) -> Self {
-        let idx = inst.index();
-        debug_assert!(idx < (u32::MAX / 2) as usize);
-        Self((idx * 2) as u32)
-    }
-}
-
-impl From<Block> for ProgramPoint {
-    fn from(block: Block) -> Self {
-        let idx = block.index();
-        debug_assert!(idx < (u32::MAX / 2) as usize);
-        Self((idx * 2 + 1) as u32)
-    }
-}
-
-impl From<ValueDef> for ProgramPoint {
-    fn from(def: ValueDef) -> Self {
-        match def {
-            ValueDef::Result(inst, _) => inst.into(),
-            ValueDef::Param(block, _) => block.into(),
-        }
-    }
-}
-
-/// An expanded program point directly exposes the variants, but takes twice the space to
-/// represent.
-#[derive(PartialEq, Eq, Clone, Copy)]
-pub enum ExpandedProgramPoint {
-    /// An instruction in the function.
-    Inst(Inst),
-    /// A block header.
-    Block(Block),
-}
-
-impl ExpandedProgramPoint {
-    /// Get the instruction we know is inside.
-    pub fn unwrap_inst(self) -> Inst {
-        match self {
-            Self::Inst(x) => x,
-            Self::Block(x) => panic!("expected inst: {}", x),
-        }
-    }
-}
-
-impl From<Inst> for ExpandedProgramPoint {
-    fn from(inst: Inst) -> Self {
-        Self::Inst(inst)
-    }
-}
-
-impl From<Block> for ExpandedProgramPoint {
-    fn from(block: Block) -> Self {
-        Self::Block(block)
-    }
-}
-
-impl From<ValueDef> for ExpandedProgramPoint {
-    fn from(def: ValueDef) -> Self {
-        match def {
-            ValueDef::Result(inst, _) => inst.into(),
-            ValueDef::Param(block, _) => block.into(),
-        }
-    }
-}
-
-impl From<ProgramPoint> for ExpandedProgramPoint {
-    fn from(pp: ProgramPoint) -> Self {
-        if pp.0 & 1 == 0 {
-            Self::Inst(Inst::from_u32(pp.0 / 2))
-        } else {
-            Self::Block(Block::from_u32(pp.0 / 2))
-        }
-    }
-}
-
-impl fmt::Display for ExpandedProgramPoint {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        match *self {
-            Self::Inst(x) => write!(f, "{}", x),
-            Self::Block(x) => write!(f, "{}", x),
-        }
-    }
-}
-
-impl fmt::Display for ProgramPoint {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        let epp: ExpandedProgramPoint = (*self).into();
-        epp.fmt(f)
-    }
-}
-
-impl fmt::Debug for ExpandedProgramPoint {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        write!(f, "ExpandedProgramPoint({})", self)
-    }
-}
-
-impl fmt::Debug for ProgramPoint {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        write!(f, "ProgramPoint({})", self)
-    }
-}
-
-/// Context for ordering program points.
-///
-/// `ProgramPoint` objects don't carry enough information to be ordered independently, they need a
-/// context providing the program order.
-pub trait ProgramOrder {
-    /// Compare the program points `a` and `b` relative to this program order.
-    ///
-    /// Return `Less` if `a` appears in the program before `b`.
-    ///
-    /// This is declared as a generic such that it can be called with `Inst` and `Block` arguments
-    /// directly. Depending on the implementation, there is a good chance performance will be
-    /// improved for those cases where the type of either argument is known statically.
-    fn cmp<A, B>(&self, a: A, b: B) -> cmp::Ordering
-    where
-        A: Into<ExpandedProgramPoint>,
-        B: Into<ExpandedProgramPoint>;
-
-    /// Is the range from `inst` to `block` just the gap between consecutive blocks?
-    ///
-    /// This returns true if `inst` is the terminator in the block immediately before `block`.
-    fn is_block_gap(&self, inst: Inst, block: Block) -> bool;
-}
-
-#[cfg(test)]
-mod tests {
-    use super::*;
-    use crate::entity::EntityRef;
-    use crate::ir::{Block, Inst};
-    use alloc::string::ToString;
-
-    #[test]
-    fn convert() {
-        let i5 = Inst::new(5);
-        let b3 = Block::new(3);
-
-        let pp1: ProgramPoint = i5.into();
-        let pp2: ProgramPoint = b3.into();
-
-        assert_eq!(pp1.to_string(), "inst5");
-        assert_eq!(pp2.to_string(), "block3");
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/sourceloc.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/sourceloc.rs
deleted file mode 100644
index ccab62f89..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/sourceloc.rs
+++ /dev/null
@@ -1,66 +0,0 @@
-//! Source locations.
-//!
-//! Cranelift tracks the original source location of each instruction, and preserves the source
-//! location when instructions are transformed.
-
-use core::fmt;
-#[cfg(feature = "enable-serde")]
-use serde::{Deserialize, Serialize};
-
-/// A source location.
-///
-/// This is an opaque 32-bit number attached to each Cranelift IR instruction. Cranelift does not
-/// interpret source locations in any way, they are simply preserved from the input to the output.
-///
-/// The default source location uses the all-ones bit pattern `!0`. It is used for instructions
-/// that can't be given a real source location.
-#[derive(Clone, Copy, Debug, PartialEq, Eq)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub struct SourceLoc(u32);
-
-impl SourceLoc {
-    /// Create a new source location with the given bits.
-    pub fn new(bits: u32) -> Self {
-        Self(bits)
-    }
-
-    /// Is this the default source location?
-    pub fn is_default(self) -> bool {
-        self == Default::default()
-    }
-
-    /// Read the bits of this source location.
-    pub fn bits(self) -> u32 {
-        self.0
-    }
-}
-
-impl Default for SourceLoc {
-    fn default() -> Self {
-        Self(!0)
-    }
-}
-
-impl fmt::Display for SourceLoc {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        if self.is_default() {
-            write!(f, "@-")
-        } else {
-            write!(f, "@{:04x}", self.0)
-        }
-    }
-}
-
-#[cfg(test)]
-mod tests {
-    use crate::ir::SourceLoc;
-    use alloc::string::ToString;
-
-    #[test]
-    fn display() {
-        assert_eq!(SourceLoc::default().to_string(), "@-");
-        assert_eq!(SourceLoc::new(0).to_string(), "@0000");
-        assert_eq!(SourceLoc::new(16).to_string(), "@0010");
-        assert_eq!(SourceLoc::new(0xabcdef).to_string(), "@abcdef");
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/stackslot.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/stackslot.rs
deleted file mode 100644
index 4c30eb48b..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/stackslot.rs
+++ /dev/null
@@ -1,125 +0,0 @@
-//! Stack slots.
-//!
-//! The `StackSlotData` struct keeps track of a single stack slot in a function.
-//!
-
-use crate::entity::PrimaryMap;
-use crate::ir::StackSlot;
-use core::fmt;
-use core::str::FromStr;
-
-#[cfg(feature = "enable-serde")]
-use serde::{Deserialize, Serialize};
-
-/// The size of an object on the stack, or the size of a stack frame.
-///
-/// We don't use `usize` to represent object sizes on the target platform because Cranelift supports
-/// cross-compilation, and `usize` is a type that depends on the host platform, not the target
-/// platform.
-pub type StackSize = u32;
-
-/// The kind of a stack slot.
-#[derive(Clone, Copy, Debug, PartialEq, Eq)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub enum StackSlotKind {
-    /// An explicit stack slot. This is a chunk of stack memory for use by the `stack_load`
-    /// and `stack_store` instructions.
-    ExplicitSlot,
-}
-
-impl FromStr for StackSlotKind {
-    type Err = ();
-
-    fn from_str(s: &str) -> Result<Self, ()> {
-        use self::StackSlotKind::*;
-        match s {
-            "explicit_slot" => Ok(ExplicitSlot),
-            _ => Err(()),
-        }
-    }
-}
-
-impl fmt::Display for StackSlotKind {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        use self::StackSlotKind::*;
-        f.write_str(match *self {
-            ExplicitSlot => "explicit_slot",
-        })
-    }
-}
-
-/// Contents of a stack slot.
-#[derive(Clone, Debug, PartialEq, Eq)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub struct StackSlotData {
-    /// The kind of stack slot.
-    pub kind: StackSlotKind,
-
-    /// Size of stack slot in bytes.
-    pub size: StackSize,
-}
-
-impl StackSlotData {
-    /// Create a stack slot with the specified byte size.
-    pub fn new(kind: StackSlotKind, size: StackSize) -> Self {
-        Self { kind, size }
-    }
-
-    /// Get the alignment in bytes of this stack slot given the stack pointer alignment.
-    pub fn alignment(&self, max_align: StackSize) -> StackSize {
-        debug_assert!(max_align.is_power_of_two());
-        // We want to find the largest power of two that divides both `self.size` and `max_align`.
-        // That is the same as isolating the rightmost bit in `x`.
-        let x = self.size | max_align;
-        // C.f. Hacker's delight.
-        x & x.wrapping_neg()
-    }
-}
-
-impl fmt::Display for StackSlotData {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        write!(f, "{} {}", self.kind, self.size)
-    }
-}
-
-/// All allocated stack slots.
-pub type StackSlots = PrimaryMap<StackSlot, StackSlotData>;
-
-#[cfg(test)]
-mod tests {
-    use super::*;
-    use crate::ir::Function;
-    use alloc::string::ToString;
-
-    #[test]
-    fn stack_slot() {
-        let mut func = Function::new();
-
-        let ss0 = func.create_stack_slot(StackSlotData::new(StackSlotKind::ExplicitSlot, 4));
-        let ss1 = func.create_stack_slot(StackSlotData::new(StackSlotKind::ExplicitSlot, 8));
-        assert_eq!(ss0.to_string(), "ss0");
-        assert_eq!(ss1.to_string(), "ss1");
-
-        assert_eq!(func.stack_slots[ss0].size, 4);
-        assert_eq!(func.stack_slots[ss1].size, 8);
-
-        assert_eq!(func.stack_slots[ss0].to_string(), "explicit_slot 4");
-        assert_eq!(func.stack_slots[ss1].to_string(), "explicit_slot 8");
-    }
-
-    #[test]
-    fn alignment() {
-        let slot = StackSlotData::new(StackSlotKind::ExplicitSlot, 8);
-
-        assert_eq!(slot.alignment(4), 4);
-        assert_eq!(slot.alignment(8), 8);
-        assert_eq!(slot.alignment(16), 8);
-
-        let slot2 = StackSlotData::new(StackSlotKind::ExplicitSlot, 24);
-
-        assert_eq!(slot2.alignment(4), 4);
-        assert_eq!(slot2.alignment(8), 8);
-        assert_eq!(slot2.alignment(16), 8);
-        assert_eq!(slot2.alignment(32), 8);
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/table.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/table.rs
deleted file mode 100644
index 713d1f5df..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/table.rs
+++ /dev/null
@@ -1,40 +0,0 @@
-//! Tables.
-
-use crate::ir::immediates::Uimm64;
-use crate::ir::{GlobalValue, Type};
-use core::fmt;
-
-#[cfg(feature = "enable-serde")]
-use serde::{Deserialize, Serialize};
-
-/// Information about a table declaration.
-#[derive(Clone)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub struct TableData {
-    /// Global value giving the address of the start of the table.
-    pub base_gv: GlobalValue,
-
-    /// Guaranteed minimum table size in elements. Table accesses before `min_size` don't need
-    /// bounds checking.
-    pub min_size: Uimm64,
-
-    /// Global value giving the current bound of the table, in elements.
-    pub bound_gv: GlobalValue,
-
-    /// The size of a table element, in bytes.
-    pub element_size: Uimm64,
-
-    /// The index type for the table.
-    pub index_type: Type,
-}
-
-impl fmt::Display for TableData {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        f.write_str("dynamic")?;
-        write!(
-            f,
-            " {}, min {}, bound {}, element_size {}, index_type {}",
-            self.base_gv, self.min_size, self.bound_gv, self.element_size, self.index_type
-        )
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/trapcode.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/trapcode.rs
deleted file mode 100644
index 3114114f6..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/trapcode.rs
+++ /dev/null
@@ -1,134 +0,0 @@
-//! Trap codes describing the reason for a trap.
-
-use core::fmt::{self, Display, Formatter};
-use core::str::FromStr;
-#[cfg(feature = "enable-serde")]
-use serde::{Deserialize, Serialize};
-
-/// A trap code describing the reason for a trap.
-///
-/// All trap instructions have an explicit trap code.
-#[derive(Clone, Copy, PartialEq, Eq, Debug, Hash)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub enum TrapCode {
-    /// The current stack space was exhausted.
-    StackOverflow,
-
-    /// A `heap_addr` instruction detected an out-of-bounds error.
-    ///
-    /// Note that not all out-of-bounds heap accesses are reported this way;
-    /// some are detected by a segmentation fault on the heap unmapped or
-    /// offset-guard pages.
-    HeapOutOfBounds,
-
-    /// A wasm atomic operation was presented with a not-naturally-aligned linear-memory address.
-    HeapMisaligned,
-
-    /// A `table_addr` instruction detected an out-of-bounds error.
-    TableOutOfBounds,
-
-    /// Indirect call to a null table entry.
-    IndirectCallToNull,
-
-    /// Signature mismatch on indirect call.
-    BadSignature,
-
-    /// An integer arithmetic operation caused an overflow.
-    IntegerOverflow,
-
-    /// An integer division by zero.
-    IntegerDivisionByZero,
-
-    /// Failed float-to-int conversion.
-    BadConversionToInteger,
-
-    /// Code that was supposed to have been unreachable was reached.
-    UnreachableCodeReached,
-
-    /// Execution has potentially run too long and may be interrupted.
-    /// This trap is resumable.
-    Interrupt,
-
-    /// A user-defined trap code.
-    User(u16),
-}
-
-impl Display for TrapCode {
-    fn fmt(&self, f: &mut Formatter) -> fmt::Result {
-        use self::TrapCode::*;
-        let identifier = match *self {
-            StackOverflow => "stk_ovf",
-            HeapOutOfBounds => "heap_oob",
-            HeapMisaligned => "heap_misaligned",
-            TableOutOfBounds => "table_oob",
-            IndirectCallToNull => "icall_null",
-            BadSignature => "bad_sig",
-            IntegerOverflow => "int_ovf",
-            IntegerDivisionByZero => "int_divz",
-            BadConversionToInteger => "bad_toint",
-            UnreachableCodeReached => "unreachable",
-            Interrupt => "interrupt",
-            User(x) => return write!(f, "user{}", x),
-        };
-        f.write_str(identifier)
-    }
-}
-
-impl FromStr for TrapCode {
-    type Err = ();
-
-    fn from_str(s: &str) -> Result<Self, Self::Err> {
-        use self::TrapCode::*;
-        match s {
-            "stk_ovf" => Ok(StackOverflow),
-            "heap_oob" => Ok(HeapOutOfBounds),
-            "heap_misaligned" => Ok(HeapMisaligned),
-            "table_oob" => Ok(TableOutOfBounds),
-            "icall_null" => Ok(IndirectCallToNull),
-            "bad_sig" => Ok(BadSignature),
-            "int_ovf" => Ok(IntegerOverflow),
-            "int_divz" => Ok(IntegerDivisionByZero),
-            "bad_toint" => Ok(BadConversionToInteger),
-            "unreachable" => Ok(UnreachableCodeReached),
-            "interrupt" => Ok(Interrupt),
-            _ if s.starts_with("user") => s[4..].parse().map(User).map_err(|_| ()),
-            _ => Err(()),
-        }
-    }
-}
-
-#[cfg(test)]
-mod tests {
-    use super::*;
-    use alloc::string::ToString;
-
-    // Everything but user-defined codes.
-    const CODES: [TrapCode; 11] = [
-        TrapCode::StackOverflow,
-        TrapCode::HeapOutOfBounds,
-        TrapCode::HeapMisaligned,
-        TrapCode::TableOutOfBounds,
-        TrapCode::IndirectCallToNull,
-        TrapCode::BadSignature,
-        TrapCode::IntegerOverflow,
-        TrapCode::IntegerDivisionByZero,
-        TrapCode::BadConversionToInteger,
-        TrapCode::UnreachableCodeReached,
-        TrapCode::Interrupt,
-    ];
-
-    #[test]
-    fn display() {
-        for r in &CODES {
-            let tc = *r;
-            assert_eq!(tc.to_string().parse(), Ok(tc));
-        }
-        assert_eq!("bogus".parse::<TrapCode>(), Err(()));
-
-        assert_eq!(TrapCode::User(17).to_string(), "user17");
-        assert_eq!("user22".parse(), Ok(TrapCode::User(22)));
-        assert_eq!("user".parse::<TrapCode>(), Err(()));
-        assert_eq!("user-1".parse::<TrapCode>(), Err(()));
-        assert_eq!("users".parse::<TrapCode>(), Err(()));
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/types.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/types.rs
deleted file mode 100644
index 59e6a871b..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/ir/types.rs
+++ /dev/null
@@ -1,625 +0,0 @@
-//! Common types for the Cranelift code generator.
-
-use core::default::Default;
-use core::fmt::{self, Debug, Display, Formatter};
-use cranelift_codegen_shared::constants;
-#[cfg(feature = "enable-serde")]
-use serde::{Deserialize, Serialize};
-use target_lexicon::{PointerWidth, Triple};
-
-/// The type of an SSA value.
-///
-/// The `INVALID` type isn't a real type, and is used as a placeholder in the IR where a type
-/// field is present put no type is needed, such as the controlling type variable for a
-/// non-polymorphic instruction.
-///
-/// Basic integer types: `I8`, `I16`, `I32`, `I64`, and `I128`. These types are sign-agnostic.
-///
-/// Basic floating point types: `F32` and `F64`. IEEE single and double precision.
-///
-/// Boolean types: `B1`, `B8`, `B16`, `B32`, `B64`, and `B128`. These all encode 'true' or 'false'. The
-/// larger types use redundant bits.
-///
-/// SIMD vector types have power-of-two lanes, up to 256. Lanes can be any int/float/bool type.
-///
-#[derive(Copy, Clone, PartialEq, Eq, Hash)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub struct Type(u8);
-
-/// Not a valid type. Can't be loaded or stored. Can't be part of a SIMD vector.
-pub const INVALID: Type = Type(0);
-
-// Include code generated by `cranelift-codegen/meta/gen_types.rs`. This file contains constant
-// definitions for all the scalar types as well as common vector types for 64, 128, 256, and
-// 512-bit SIMD vectors.
-include!(concat!(env!("OUT_DIR"), "/types.rs"));
-
-impl Type {
-    /// Get the lane type of this SIMD vector type.
-    ///
-    /// A lane type is the same as a SIMD vector type with one lane, so it returns itself.
-    pub fn lane_type(self) -> Self {
-        if self.0 < constants::VECTOR_BASE {
-            self
-        } else {
-            Self(constants::LANE_BASE | (self.0 & 0x0f))
-        }
-    }
-
-    /// The type transformation that returns the lane type of a type variable; it is just a
-    /// renaming of lane_type() to be used in context where we think in terms of type variable
-    /// transformations.
-    pub fn lane_of(self) -> Self {
-        self.lane_type()
-    }
-
-    /// Get log_2 of the number of bits in a lane.
-    pub fn log2_lane_bits(self) -> u8 {
-        match self.lane_type() {
-            B1 => 0,
-            B8 | I8 => 3,
-            B16 | I16 => 4,
-            B32 | I32 | F32 | R32 => 5,
-            B64 | I64 | F64 | R64 => 6,
-            B128 | I128 => 7,
-            _ => 0,
-        }
-    }
-
-    /// Get the number of bits in a lane.
-    pub fn lane_bits(self) -> u8 {
-        match self.lane_type() {
-            B1 => 1,
-            B8 | I8 => 8,
-            B16 | I16 => 16,
-            B32 | I32 | F32 | R32 => 32,
-            B64 | I64 | F64 | R64 => 64,
-            B128 | I128 => 128,
-            _ => 0,
-        }
-    }
-
-    /// Get the (minimum, maximum) values represented by each lane in the type.
-    /// Note that these are returned as unsigned 'bit patterns'.
-    pub fn bounds(self, signed: bool) -> (u128, u128) {
-        if signed {
-            match self.lane_type() {
-                I8 => (i8::MIN as u128, i8::MAX as u128),
-                I16 => (i16::MIN as u128, i16::MAX as u128),
-                I32 => (i32::MIN as u128, i32::MAX as u128),
-                I64 => (i64::MIN as u128, i64::MAX as u128),
-                I128 => (i128::MIN as u128, i128::MAX as u128),
-                _ => unimplemented!(),
-            }
-        } else {
-            match self.lane_type() {
-                I8 => (u8::MIN as u128, u8::MAX as u128),
-                I16 => (u16::MIN as u128, u16::MAX as u128),
-                I32 => (u32::MIN as u128, u32::MAX as u128),
-                I64 => (u64::MIN as u128, u64::MAX as u128),
-                I128 => (u128::MIN, u128::MAX),
-                _ => unimplemented!(),
-            }
-        }
-    }
-
-    /// Get an integer type with the requested number of bits.
-    ///
-    /// For the same thing but in *bytes*, use [`Self::int_with_byte_size`].
-    pub fn int(bits: u16) -> Option<Self> {
-        match bits {
-            8 => Some(I8),
-            16 => Some(I16),
-            32 => Some(I32),
-            64 => Some(I64),
-            128 => Some(I128),
-            _ => None,
-        }
-    }
-
-    /// Get an integer type with the requested number of bytes.
-    ///
-    /// For the same thing but in *bits*, use [`Self::int`].
-    pub fn int_with_byte_size(bytes: u16) -> Option<Self> {
-        Self::int(bytes.checked_mul(8)?)
-    }
-
-    /// Get a type with the same number of lanes as `self`, but using `lane` as the lane type.
-    fn replace_lanes(self, lane: Self) -> Self {
-        debug_assert!(lane.is_lane() && !self.is_special());
-        Self((lane.0 & 0x0f) | (self.0 & 0xf0))
-    }
-
-    /// Get a type with the same number of lanes as this type, but with the lanes replaced by
-    /// booleans of the same size.
-    ///
-    /// Lane types are treated as vectors with one lane, so they are converted to the multi-bit
-    /// boolean types.
-    pub fn as_bool_pedantic(self) -> Self {
-        // Replace the low 4 bits with the boolean version, preserve the high 4 bits.
-        self.replace_lanes(match self.lane_type() {
-            B8 | I8 => B8,
-            B16 | I16 => B16,
-            B32 | I32 | F32 => B32,
-            B64 | I64 | F64 => B64,
-            R32 | R64 => panic!("Reference types should not convert to bool"),
-            B128 | I128 => B128,
-            _ => B1,
-        })
-    }
-
-    /// Get a type with the same number of lanes as this type, but with the lanes replaced by
-    /// booleans of the same size.
-    ///
-    /// Scalar types are all converted to `b1` which is usually what you want.
-    pub fn as_bool(self) -> Self {
-        if !self.is_vector() {
-            B1
-        } else {
-            self.as_bool_pedantic()
-        }
-    }
-
-    /// Get a type with the same number of lanes as this type, but with the lanes replaced by
-    /// integers of the same size.
-    ///
-    /// Scalar types follow this same rule, but `b1` is converted into `i8`
-    pub fn as_int(self) -> Self {
-        self.replace_lanes(match self.lane_type() {
-            I8 | B1 | B8 => I8,
-            I16 | B16 => I16,
-            I32 | B32 => I32,
-            I64 | B64 => I64,
-            I128 | B128 => I128,
-            _ => unimplemented!(),
-        })
-    }
-
-    /// Get a type with the same number of lanes as this type, but with lanes that are half the
-    /// number of bits.
-    pub fn half_width(self) -> Option<Self> {
-        Some(self.replace_lanes(match self.lane_type() {
-            I16 => I8,
-            I32 => I16,
-            I64 => I32,
-            I128 => I64,
-            F64 => F32,
-            B16 => B8,
-            B32 => B16,
-            B64 => B32,
-            B128 => B64,
-            _ => return None,
-        }))
-    }
-
-    /// Get a type with the same number of lanes as this type, but with lanes that are twice the
-    /// number of bits.
-    pub fn double_width(self) -> Option<Self> {
-        Some(self.replace_lanes(match self.lane_type() {
-            I8 => I16,
-            I16 => I32,
-            I32 => I64,
-            I64 => I128,
-            F32 => F64,
-            B8 => B16,
-            B16 => B32,
-            B32 => B64,
-            B64 => B128,
-            _ => return None,
-        }))
-    }
-
-    /// Is this the INVALID type?
-    pub fn is_invalid(self) -> bool {
-        self == INVALID
-    }
-
-    /// Is this a special type?
-    pub fn is_special(self) -> bool {
-        self.0 < constants::LANE_BASE
-    }
-
-    /// Is this a lane type?
-    ///
-    /// This is a scalar type that can also appear as the lane type of a SIMD vector.
-    pub fn is_lane(self) -> bool {
-        constants::LANE_BASE <= self.0 && self.0 < constants::VECTOR_BASE
-    }
-
-    /// Is this a SIMD vector type?
-    ///
-    /// A vector type has 2 or more lanes.
-    pub fn is_vector(self) -> bool {
-        self.0 >= constants::VECTOR_BASE
-    }
-
-    /// Is this a scalar boolean type?
-    pub fn is_bool(self) -> bool {
-        match self {
-            B1 | B8 | B16 | B32 | B64 | B128 => true,
-            _ => false,
-        }
-    }
-
-    /// Is this a vector boolean type?
-    pub fn is_bool_vector(self) -> bool {
-        self.is_vector() && self.lane_type().is_bool()
-    }
-
-    /// Is this a scalar integer type?
-    pub fn is_int(self) -> bool {
-        match self {
-            I8 | I16 | I32 | I64 | I128 => true,
-            _ => false,
-        }
-    }
-
-    /// Is this a scalar floating point type?
-    pub fn is_float(self) -> bool {
-        match self {
-            F32 | F64 => true,
-            _ => false,
-        }
-    }
-
-    /// Is this a CPU flags type?
-    pub fn is_flags(self) -> bool {
-        match self {
-            IFLAGS | FFLAGS => true,
-            _ => false,
-        }
-    }
-
-    /// Is this a ref type?
-    pub fn is_ref(self) -> bool {
-        match self {
-            R32 | R64 => true,
-            _ => false,
-        }
-    }
-
-    /// Get log_2 of the number of lanes in this SIMD vector type.
-    ///
-    /// All SIMD types have a lane count that is a power of two and no larger than 256, so this
-    /// will be a number in the range 0-8.
-    ///
-    /// A scalar type is the same as a SIMD vector type with one lane, so it returns 0.
-    pub fn log2_lane_count(self) -> u8 {
-        self.0.saturating_sub(constants::LANE_BASE) >> 4
-    }
-
-    /// Get the number of lanes in this SIMD vector type.
-    ///
-    /// A scalar type is the same as a SIMD vector type with one lane, so it returns 1.
-    pub fn lane_count(self) -> u16 {
-        1 << self.log2_lane_count()
-    }
-
-    /// Get the total number of bits used to represent this type.
-    pub fn bits(self) -> u16 {
-        u16::from(self.lane_bits()) * self.lane_count()
-    }
-
-    /// Get the number of bytes used to store this type in memory.
-    pub fn bytes(self) -> u32 {
-        (u32::from(self.bits()) + 7) / 8
-    }
-
-    /// Get a SIMD vector type with `n` times more lanes than this one.
-    ///
-    /// If this is a scalar type, this produces a SIMD type with this as a lane type and `n` lanes.
-    ///
-    /// If this is already a SIMD vector type, this produces a SIMD vector type with `n *
-    /// self.lane_count()` lanes.
-    pub fn by(self, n: u16) -> Option<Self> {
-        if self.lane_bits() == 0 || !n.is_power_of_two() {
-            return None;
-        }
-        let log2_lanes: u32 = n.trailing_zeros();
-        let new_type = u32::from(self.0) + (log2_lanes << 4);
-        if new_type < 0x100 {
-            Some(Self(new_type as u8))
-        } else {
-            None
-        }
-    }
-
-    /// Get a SIMD vector with half the number of lanes.
-    ///
-    /// There is no `double_vector()` method. Use `t.by(2)` instead.
-    pub fn half_vector(self) -> Option<Self> {
-        if self.is_vector() {
-            Some(Self(self.0 - 0x10))
-        } else {
-            None
-        }
-    }
-
-    /// Split the lane width in half and double the number of lanes to maintain the same bit-width.
-    ///
-    /// If this is a scalar type of `n` bits, it produces a SIMD vector type of `(n/2)x2`.
-    pub fn split_lanes(self) -> Option<Self> {
-        match self.half_width() {
-            Some(half_width) => half_width.by(2),
-            None => None,
-        }
-    }
-
-    /// Merge lanes to half the number of lanes and double the lane width to maintain the same
-    /// bit-width.
-    ///
-    /// If this is a scalar type, it will return `None`.
-    pub fn merge_lanes(self) -> Option<Self> {
-        match self.double_width() {
-            Some(double_width) => double_width.half_vector(),
-            None => None,
-        }
-    }
-
-    /// Index of this type, for use with hash tables etc.
-    pub fn index(self) -> usize {
-        usize::from(self.0)
-    }
-
-    /// True iff:
-    ///
-    /// 1. `self.lane_count() == other.lane_count()` and
-    /// 2. `self.lane_bits() >= other.lane_bits()`
-    pub fn wider_or_equal(self, other: Self) -> bool {
-        self.lane_count() == other.lane_count() && self.lane_bits() >= other.lane_bits()
-    }
-
-    /// Return the pointer type for the given target triple.
-    pub fn triple_pointer_type(triple: &Triple) -> Self {
-        match triple.pointer_width() {
-            Ok(PointerWidth::U16) => I16,
-            Ok(PointerWidth::U32) => I32,
-            Ok(PointerWidth::U64) => I64,
-            Err(()) => panic!("unable to determine architecture pointer width"),
-        }
-    }
-
-    /// Coerces boolean types (scalar and vectors) into their integer counterparts.
-    /// B1 is converted into I8.
-    pub fn coerce_bools_to_ints(self) -> Self {
-        let is_scalar_bool = self.is_bool();
-        let is_vector_bool = self.is_vector() && self.lane_type().is_bool();
-
-        if is_scalar_bool || is_vector_bool {
-            self.as_int()
-        } else {
-            self
-        }
-    }
-}
-
-impl Display for Type {
-    fn fmt(&self, f: &mut Formatter) -> fmt::Result {
-        if self.is_bool() {
-            write!(f, "b{}", self.lane_bits())
-        } else if self.is_int() {
-            write!(f, "i{}", self.lane_bits())
-        } else if self.is_float() {
-            write!(f, "f{}", self.lane_bits())
-        } else if self.is_vector() {
-            write!(f, "{}x{}", self.lane_type(), self.lane_count())
-        } else if self.is_ref() {
-            write!(f, "r{}", self.lane_bits())
-        } else {
-            f.write_str(match *self {
-                IFLAGS => "iflags",
-                FFLAGS => "fflags",
-                INVALID => panic!("INVALID encountered"),
-                _ => panic!("Unknown Type(0x{:x})", self.0),
-            })
-        }
-    }
-}
-
-impl Debug for Type {
-    fn fmt(&self, f: &mut Formatter) -> fmt::Result {
-        if self.is_bool() {
-            write!(f, "types::B{}", self.lane_bits())
-        } else if self.is_int() {
-            write!(f, "types::I{}", self.lane_bits())
-        } else if self.is_float() {
-            write!(f, "types::F{}", self.lane_bits())
-        } else if self.is_vector() {
-            write!(f, "{:?}X{}", self.lane_type(), self.lane_count())
-        } else if self.is_ref() {
-            write!(f, "types::R{}", self.lane_bits())
-        } else {
-            match *self {
-                INVALID => write!(f, "types::INVALID"),
-                IFLAGS => write!(f, "types::IFLAGS"),
-                FFLAGS => write!(f, "types::FFLAGS"),
-                _ => write!(f, "Type(0x{:x})", self.0),
-            }
-        }
-    }
-}
-
-impl Default for Type {
-    fn default() -> Self {
-        INVALID
-    }
-}
-
-#[cfg(test)]
-mod tests {
-    use super::*;
-    use alloc::string::ToString;
-
-    #[test]
-    fn basic_scalars() {
-        assert_eq!(INVALID, INVALID.lane_type());
-        assert_eq!(0, INVALID.bits());
-        assert_eq!(IFLAGS, IFLAGS.lane_type());
-        assert_eq!(0, IFLAGS.bits());
-        assert_eq!(FFLAGS, FFLAGS.lane_type());
-        assert_eq!(0, FFLAGS.bits());
-        assert_eq!(B1, B1.lane_type());
-        assert_eq!(B8, B8.lane_type());
-        assert_eq!(B16, B16.lane_type());
-        assert_eq!(B32, B32.lane_type());
-        assert_eq!(B64, B64.lane_type());
-        assert_eq!(B128, B128.lane_type());
-        assert_eq!(I8, I8.lane_type());
-        assert_eq!(I16, I16.lane_type());
-        assert_eq!(I32, I32.lane_type());
-        assert_eq!(I64, I64.lane_type());
-        assert_eq!(I128, I128.lane_type());
-        assert_eq!(F32, F32.lane_type());
-        assert_eq!(F64, F64.lane_type());
-        assert_eq!(B1, B1.by(8).unwrap().lane_type());
-        assert_eq!(I32, I32X4.lane_type());
-        assert_eq!(F64, F64X2.lane_type());
-        assert_eq!(R32, R32.lane_type());
-        assert_eq!(R64, R64.lane_type());
-
-        assert_eq!(INVALID.lane_bits(), 0);
-        assert_eq!(IFLAGS.lane_bits(), 0);
-        assert_eq!(FFLAGS.lane_bits(), 0);
-        assert_eq!(B1.lane_bits(), 1);
-        assert_eq!(B8.lane_bits(), 8);
-        assert_eq!(B16.lane_bits(), 16);
-        assert_eq!(B32.lane_bits(), 32);
-        assert_eq!(B64.lane_bits(), 64);
-        assert_eq!(B128.lane_bits(), 128);
-        assert_eq!(I8.lane_bits(), 8);
-        assert_eq!(I16.lane_bits(), 16);
-        assert_eq!(I32.lane_bits(), 32);
-        assert_eq!(I64.lane_bits(), 64);
-        assert_eq!(I128.lane_bits(), 128);
-        assert_eq!(F32.lane_bits(), 32);
-        assert_eq!(F64.lane_bits(), 64);
-        assert_eq!(R32.lane_bits(), 32);
-        assert_eq!(R64.lane_bits(), 64);
-    }
-
-    #[test]
-    fn typevar_functions() {
-        assert_eq!(INVALID.half_width(), None);
-        assert_eq!(INVALID.half_width(), None);
-        assert_eq!(FFLAGS.half_width(), None);
-        assert_eq!(B1.half_width(), None);
-        assert_eq!(B8.half_width(), None);
-        assert_eq!(B16.half_width(), Some(B8));
-        assert_eq!(B32.half_width(), Some(B16));
-        assert_eq!(B64.half_width(), Some(B32));
-        assert_eq!(B128.half_width(), Some(B64));
-        assert_eq!(I8.half_width(), None);
-        assert_eq!(I16.half_width(), Some(I8));
-        assert_eq!(I32.half_width(), Some(I16));
-        assert_eq!(I32X4.half_width(), Some(I16X4));
-        assert_eq!(I64.half_width(), Some(I32));
-        assert_eq!(I128.half_width(), Some(I64));
-        assert_eq!(F32.half_width(), None);
-        assert_eq!(F64.half_width(), Some(F32));
-
-        assert_eq!(INVALID.double_width(), None);
-        assert_eq!(IFLAGS.double_width(), None);
-        assert_eq!(FFLAGS.double_width(), None);
-        assert_eq!(B1.double_width(), None);
-        assert_eq!(B8.double_width(), Some(B16));
-        assert_eq!(B16.double_width(), Some(B32));
-        assert_eq!(B32.double_width(), Some(B64));
-        assert_eq!(B64.double_width(), Some(B128));
-        assert_eq!(B128.double_width(), None);
-        assert_eq!(I8.double_width(), Some(I16));
-        assert_eq!(I16.double_width(), Some(I32));
-        assert_eq!(I32.double_width(), Some(I64));
-        assert_eq!(I32X4.double_width(), Some(I64X4));
-        assert_eq!(I64.double_width(), Some(I128));
-        assert_eq!(I128.double_width(), None);
-        assert_eq!(F32.double_width(), Some(F64));
-        assert_eq!(F64.double_width(), None);
-    }
-
-    #[test]
-    fn vectors() {
-        let big = F64.by(256).unwrap();
-        assert_eq!(big.lane_bits(), 64);
-        assert_eq!(big.lane_count(), 256);
-        assert_eq!(big.bits(), 64 * 256);
-
-        assert_eq!(big.half_vector().unwrap().to_string(), "f64x128");
-        assert_eq!(B1.by(2).unwrap().half_vector().unwrap().to_string(), "b1");
-        assert_eq!(I32.half_vector(), None);
-        assert_eq!(INVALID.half_vector(), None);
-
-        // Check that the generated constants match the computed vector types.
-        assert_eq!(I32.by(4), Some(I32X4));
-        assert_eq!(F64.by(8), Some(F64X8));
-    }
-
-    #[test]
-    fn format_scalars() {
-        assert_eq!(IFLAGS.to_string(), "iflags");
-        assert_eq!(FFLAGS.to_string(), "fflags");
-        assert_eq!(B1.to_string(), "b1");
-        assert_eq!(B8.to_string(), "b8");
-        assert_eq!(B16.to_string(), "b16");
-        assert_eq!(B32.to_string(), "b32");
-        assert_eq!(B64.to_string(), "b64");
-        assert_eq!(B128.to_string(), "b128");
-        assert_eq!(I8.to_string(), "i8");
-        assert_eq!(I16.to_string(), "i16");
-        assert_eq!(I32.to_string(), "i32");
-        assert_eq!(I64.to_string(), "i64");
-        assert_eq!(I128.to_string(), "i128");
-        assert_eq!(F32.to_string(), "f32");
-        assert_eq!(F64.to_string(), "f64");
-        assert_eq!(R32.to_string(), "r32");
-        assert_eq!(R64.to_string(), "r64");
-    }
-
-    #[test]
-    fn format_vectors() {
-        assert_eq!(B1.by(8).unwrap().to_string(), "b1x8");
-        assert_eq!(B8.by(1).unwrap().to_string(), "b8");
-        assert_eq!(B16.by(256).unwrap().to_string(), "b16x256");
-        assert_eq!(B32.by(4).unwrap().by(2).unwrap().to_string(), "b32x8");
-        assert_eq!(B64.by(8).unwrap().to_string(), "b64x8");
-        assert_eq!(I8.by(64).unwrap().to_string(), "i8x64");
-        assert_eq!(F64.by(2).unwrap().to_string(), "f64x2");
-        assert_eq!(I8.by(3), None);
-        assert_eq!(I8.by(512), None);
-        assert_eq!(INVALID.by(4), None);
-    }
-
-    #[test]
-    fn as_bool() {
-        assert_eq!(I32X4.as_bool(), B32X4);
-        assert_eq!(I32.as_bool(), B1);
-        assert_eq!(I32X4.as_bool_pedantic(), B32X4);
-        assert_eq!(I32.as_bool_pedantic(), B32);
-    }
-
-    #[test]
-    fn as_int() {
-        assert_eq!(B32X4.as_int(), I32X4);
-        assert_eq!(B8X8.as_int(), I8X8);
-        assert_eq!(B1.as_int(), I8);
-        assert_eq!(B8.as_int(), I8);
-        assert_eq!(B128.as_int(), I128);
-    }
-
-    #[test]
-    fn int_from_size() {
-        assert_eq!(Type::int(0), None);
-        assert_eq!(Type::int(8), Some(I8));
-        assert_eq!(Type::int(33), None);
-        assert_eq!(Type::int(64), Some(I64));
-
-        assert_eq!(Type::int_with_byte_size(0), None);
-        assert_eq!(Type::int_with_byte_size(2), Some(I16));
-        assert_eq!(Type::int_with_byte_size(6), None);
-        assert_eq!(Type::int_with_byte_size(16), Some(I128));
-
-        // Ensure `int_with_byte_size` handles overflow properly
-        let evil = 0xE001_u16;
-        assert_eq!(evil.wrapping_mul(8), 8, "check the constant is correct");
-        assert_eq!(Type::int_with_byte_size(evil), None);
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/abi.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/abi.rs
deleted file mode 100644
index 3fbfc8356..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/abi.rs
+++ /dev/null
@@ -1,1346 +0,0 @@
-//! Implementation of a standard AArch64 ABI.
-
-use crate::ir;
-use crate::ir::types;
-use crate::ir::types::*;
-use crate::ir::MemFlags;
-use crate::ir::Opcode;
-use crate::ir::{ExternalName, LibCall};
-use crate::isa;
-use crate::isa::aarch64::{inst::EmitState, inst::*};
-use crate::isa::unwind::UnwindInst;
-use crate::machinst::*;
-use crate::settings;
-use crate::{CodegenError, CodegenResult};
-use alloc::boxed::Box;
-use alloc::vec::Vec;
-use regalloc::{RealReg, Reg, RegClass, Set, Writable};
-use smallvec::{smallvec, SmallVec};
-
-// We use a generic implementation that factors out AArch64 and x64 ABI commonalities, because
-// these ABIs are very similar.
-
-/// Support for the AArch64 ABI from the callee side (within a function body).
-pub(crate) type AArch64ABICallee = ABICalleeImpl<AArch64MachineDeps>;
-
-/// Support for the AArch64 ABI from the caller side (at a callsite).
-pub(crate) type AArch64ABICaller = ABICallerImpl<AArch64MachineDeps>;
-
-// Spidermonkey specific ABI convention.
-
-/// This is SpiderMonkey's `WasmTableCallSigReg`.
-static BALDRDASH_SIG_REG: u8 = 10;
-
-/// This is SpiderMonkey's `WasmTlsReg`.
-static BALDRDASH_TLS_REG: u8 = 23;
-
-/// Offset in stack-arg area to callee-TLS slot in Baldrdash-2020 calling convention.
-static BALDRDASH_CALLEE_TLS_OFFSET: i64 = 0;
-/// Offset in stack-arg area to caller-TLS slot in Baldrdash-2020 calling convention.
-static BALDRDASH_CALLER_TLS_OFFSET: i64 = 8;
-
-// These two lists represent the registers the JIT may *not* use at any point in generated code.
-//
-// So these are callee-preserved from the JIT's point of view, and every register not in this list
-// has to be caller-preserved by definition.
-//
-// Keep these lists in sync with the NonAllocatableMask set in Spidermonkey's
-// Architecture-arm64.cpp.
-
-// Indexed by physical register number.
-#[rustfmt::skip]
-static BALDRDASH_JIT_CALLEE_SAVED_GPR: &[bool] = &[
-    /* 0 = */ false, false, false, false, false, false, false, false,
-    /* 8 = */ false, false, false, false, false, false, false, false,
-    /* 16 = */ true /* x16 / ip1 */, true /* x17 / ip2 */, true /* x18 / TLS */, false,
-    /* 20 = */ false, false, false, false,
-    /* 24 = */ false, false, false, false,
-    // There should be 28, the pseudo stack pointer in this list, however the wasm stubs trash it
-    // gladly right now.
-    /* 28 = */ false, false, true /* x30 = FP */, false /* x31 = SP */
-];
-
-#[rustfmt::skip]
-static BALDRDASH_JIT_CALLEE_SAVED_FPU: &[bool] = &[
-    /* 0 = */ false, false, false, false, false, false, false, false,
-    /* 8 = */ false, false, false, false, false, false, false, false,
-    /* 16 = */ false, false, false, false, false, false, false, false,
-    /* 24 = */ false, false, false, false, false, false, false, true /* v31 / d31 */
-];
-
-/// This is the limit for the size of argument and return-value areas on the
-/// stack. We place a reasonable limit here to avoid integer overflow issues
-/// with 32-bit arithmetic: for now, 128 MB.
-static STACK_ARG_RET_SIZE_LIMIT: u64 = 128 * 1024 * 1024;
-
-/// Try to fill a Baldrdash register, returning it if it was found.
-fn try_fill_baldrdash_reg(call_conv: isa::CallConv, param: &ir::AbiParam) -> Option<ABIArg> {
-    if call_conv.extends_baldrdash() {
-        match &param.purpose {
-            &ir::ArgumentPurpose::VMContext => {
-                // This is SpiderMonkey's `WasmTlsReg`.
-                Some(ABIArg::reg(
-                    xreg(BALDRDASH_TLS_REG).to_real_reg(),
-                    ir::types::I64,
-                    param.extension,
-                    param.purpose,
-                ))
-            }
-            &ir::ArgumentPurpose::SignatureId => {
-                // This is SpiderMonkey's `WasmTableCallSigReg`.
-                Some(ABIArg::reg(
-                    xreg(BALDRDASH_SIG_REG).to_real_reg(),
-                    ir::types::I64,
-                    param.extension,
-                    param.purpose,
-                ))
-            }
-            &ir::ArgumentPurpose::CalleeTLS => {
-                // This is SpiderMonkey's callee TLS slot in the extended frame of Wasm's ABI-2020.
-                assert!(call_conv == isa::CallConv::Baldrdash2020);
-                Some(ABIArg::stack(
-                    BALDRDASH_CALLEE_TLS_OFFSET,
-                    ir::types::I64,
-                    ir::ArgumentExtension::None,
-                    param.purpose,
-                ))
-            }
-            &ir::ArgumentPurpose::CallerTLS => {
-                // This is SpiderMonkey's caller TLS slot in the extended frame of Wasm's ABI-2020.
-                assert!(call_conv == isa::CallConv::Baldrdash2020);
-                Some(ABIArg::stack(
-                    BALDRDASH_CALLER_TLS_OFFSET,
-                    ir::types::I64,
-                    ir::ArgumentExtension::None,
-                    param.purpose,
-                ))
-            }
-            _ => None,
-        }
-    } else {
-        None
-    }
-}
-
-impl Into<AMode> for StackAMode {
-    fn into(self) -> AMode {
-        match self {
-            StackAMode::FPOffset(off, ty) => AMode::FPOffset(off, ty),
-            StackAMode::NominalSPOffset(off, ty) => AMode::NominalSPOffset(off, ty),
-            StackAMode::SPOffset(off, ty) => AMode::SPOffset(off, ty),
-        }
-    }
-}
-
-// Returns the size of stack space needed to store the
-// `int_reg` and `vec_reg`.
-fn saved_reg_stack_size(
-    call_conv: isa::CallConv,
-    int_reg: &[Writable<RealReg>],
-    vec_reg: &[Writable<RealReg>],
-) -> (usize, usize) {
-    // Round up to multiple of 2, to keep 16-byte stack alignment.
-    let int_save_bytes = (int_reg.len() + (int_reg.len() & 1)) * 8;
-    // The Baldrdash ABIs require saving and restoring the whole 16-byte
-    // SIMD & FP registers, so the necessary stack space is always a
-    // multiple of the mandatory 16-byte stack alignment. However, the
-    // Procedure Call Standard for the Arm 64-bit Architecture (AAPCS64,
-    // including several related ABIs such as the one used by Windows)
-    // mandates saving only the bottom 8 bytes of the vector registers,
-    // so in that case we round up the number of registers to ensure proper
-    // stack alignment (similarly to the situation with `int_reg`).
-    let vec_reg_size = if call_conv.extends_baldrdash() { 16 } else { 8 };
-    let vec_save_padding = if call_conv.extends_baldrdash() {
-        0
-    } else {
-        vec_reg.len() & 1
-    };
-    let vec_save_bytes = (vec_reg.len() + vec_save_padding) * vec_reg_size;
-
-    (int_save_bytes, vec_save_bytes)
-}
-
-/// AArch64-specific ABI behavior. This struct just serves as an implementation
-/// point for the trait; it is never actually instantiated.
-pub(crate) struct AArch64MachineDeps;
-
-impl ABIMachineSpec for AArch64MachineDeps {
-    type I = Inst;
-
-    fn word_bits() -> u32 {
-        64
-    }
-
-    /// Return required stack alignment in bytes.
-    fn stack_align(_call_conv: isa::CallConv) -> u32 {
-        16
-    }
-
-    fn compute_arg_locs(
-        call_conv: isa::CallConv,
-        _flags: &settings::Flags,
-        params: &[ir::AbiParam],
-        args_or_rets: ArgsOrRets,
-        add_ret_area_ptr: bool,
-    ) -> CodegenResult<(Vec<ABIArg>, i64, Option<usize>)> {
-        let is_apple_cc = call_conv.extends_apple_aarch64();
-        let is_baldrdash = call_conv.extends_baldrdash();
-        let has_baldrdash_tls = call_conv == isa::CallConv::Baldrdash2020;
-
-        // See AArch64 ABI (https://github.com/ARM-software/abi-aa/blob/2021Q1/aapcs64/aapcs64.rst#64parameter-passing), sections 6.4.
-        //
-        // MacOS aarch64 is slightly different, see also
-        // https://developer.apple.com/documentation/xcode/writing_arm64_code_for_apple_platforms.
-        // We are diverging from the MacOS aarch64 implementation in the
-        // following ways:
-        // - sign- and zero- extensions of data types less than 32 bits are not
-        // implemented yet.
-        // - we align the arguments stack space to a 16-bytes boundary, while
-        // the MacOS allows aligning only on 8 bytes. In practice it means we're
-        // slightly overallocating when calling, which is fine, and doesn't
-        // break our other invariants that the stack is always allocated in
-        // 16-bytes chunks.
-
-        let mut next_xreg = 0;
-        let mut next_vreg = 0;
-        let mut next_stack: u64 = 0;
-        let mut ret = vec![];
-
-        if args_or_rets == ArgsOrRets::Args && has_baldrdash_tls {
-            // Baldrdash ABI-2020 always has two stack-arg slots reserved, for the callee and
-            // caller TLS-register values, respectively.
-            next_stack = 16;
-        }
-
-        let (max_per_class_reg_vals, mut remaining_reg_vals) = match args_or_rets {
-            ArgsOrRets::Args => (8, 16), // x0-x7 and v0-v7
-
-            // Note on return values: on the regular ABI, we may return values
-            // in 8 registers for V128 and I64 registers independently of the
-            // number of register values returned in the other class. That is,
-            // we can return values in up to 8 integer and
-            // 8 vector registers at once.
-            //
-            // In Baldrdash and Wasmtime, we can only use one register for
-            // return value for all the register classes. That is, we can't
-            // return values in both one integer and one vector register; only
-            // one return value may be in a register.
-            ArgsOrRets::Rets => {
-                if is_baldrdash || call_conv.extends_wasmtime() {
-                    (1, 1) // x0 or v0, but not both
-                } else {
-                    (8, 16) // x0-x7 and v0-v7
-                }
-            }
-        };
-
-        for i in 0..params.len() {
-            // Process returns backward, according to the SpiderMonkey ABI (which we
-            // adopt internally if `is_baldrdash` is set).
-            let param = match (args_or_rets, is_baldrdash) {
-                (ArgsOrRets::Args, _) => &params[i],
-                (ArgsOrRets::Rets, false) => &params[i],
-                (ArgsOrRets::Rets, true) => &params[params.len() - 1 - i],
-            };
-
-            // Validate "purpose".
-            match &param.purpose {
-                &ir::ArgumentPurpose::VMContext
-                | &ir::ArgumentPurpose::Normal
-                | &ir::ArgumentPurpose::StackLimit
-                | &ir::ArgumentPurpose::SignatureId
-                | &ir::ArgumentPurpose::CallerTLS
-                | &ir::ArgumentPurpose::CalleeTLS
-                | &ir::ArgumentPurpose::StructReturn
-                | &ir::ArgumentPurpose::StructArgument(_) => {}
-                _ => panic!(
-                    "Unsupported argument purpose {:?} in signature: {:?}",
-                    param.purpose, params
-                ),
-            }
-
-            assert!(
-                legal_type_for_machine(param.value_type),
-                "Invalid type for AArch64: {:?}",
-                param.value_type
-            );
-
-            let (rcs, reg_types) = Inst::rc_for_type(param.value_type)?;
-
-            if let Some(param) = try_fill_baldrdash_reg(call_conv, param) {
-                assert!(rcs[0] == RegClass::I64);
-                ret.push(param);
-                continue;
-            }
-
-            if let ir::ArgumentPurpose::StructArgument(size) = param.purpose {
-                let offset = next_stack as i64;
-                let size = size as u64;
-                assert!(size % 8 == 0, "StructArgument size is not properly aligned");
-                next_stack += size;
-                ret.push(ABIArg::StructArg {
-                    offset,
-                    size,
-                    purpose: param.purpose,
-                });
-                continue;
-            }
-
-            // Handle multi register params
-            //
-            // See AArch64 ABI (https://github.com/ARM-software/abi-aa/blob/2021Q1/aapcs64/aapcs64.rst#642parameter-passing-rules), (Section 6.4.2 Stage C).
-            //
-            // For arguments with alignment of 16 we round up the the register number
-            // to the next even value. So we can never allocate for example an i128
-            // to X1 and X2, we have to skip one register and do X2, X3
-            // (Stage C.8)
-            // Note: The Apple ABI deviates a bit here. They don't respect Stage C.8
-            // and will happily allocate a i128 to X1 and X2
-            //
-            // For integer types with alignment of 16 we also have the additional
-            // restriction of passing the lower half in Xn and the upper half in Xn+1
-            // (Stage C.9)
-            //
-            // For examples of how LLVM handles this: https://godbolt.org/z/bhd3vvEfh
-            //
-            // On the Apple ABI it is unspecified if we can spill half the value into the stack
-            // i.e load the lower half into x7 and the upper half into the stack
-            // LLVM does not seem to do this, so we are going to replicate that behaviour
-            let is_multi_reg = rcs.len() >= 2;
-            if is_multi_reg {
-                assert!(
-                    rcs.len() == 2,
-                    "Unable to handle multi reg params with more than 2 regs"
-                );
-                assert!(
-                    rcs == &[RegClass::I64, RegClass::I64],
-                    "Unable to handle non i64 regs"
-                );
-
-                let reg_class_space = max_per_class_reg_vals - next_xreg;
-                let reg_space = remaining_reg_vals;
-
-                if reg_space >= 2 && reg_class_space >= 2 {
-                    // The aarch64 ABI does not allow us to start a split argument
-                    // at an odd numbered register. So we need to skip one register
-                    //
-                    // TODO: The Fast ABI should probably not skip the register
-                    if !is_apple_cc && next_xreg % 2 != 0 {
-                        next_xreg += 1;
-                    }
-
-                    let lower_reg = xreg(next_xreg);
-                    let upper_reg = xreg(next_xreg + 1);
-
-                    ret.push(ABIArg::Slots {
-                        slots: vec![
-                            ABIArgSlot::Reg {
-                                reg: lower_reg.to_real_reg(),
-                                ty: param.value_type,
-                                extension: param.extension,
-                            },
-                            ABIArgSlot::Reg {
-                                reg: upper_reg.to_real_reg(),
-                                ty: param.value_type,
-                                extension: param.extension,
-                            },
-                        ],
-                        purpose: param.purpose,
-                    });
-
-                    next_xreg += 2;
-                    remaining_reg_vals -= 2;
-                    continue;
-                }
-            } else {
-                // Single Register parameters
-                let rc = rcs[0];
-                let next_reg = match rc {
-                    RegClass::I64 => &mut next_xreg,
-                    RegClass::V128 => &mut next_vreg,
-                    _ => panic!("Invalid register class: {:?}", rc),
-                };
-
-                if *next_reg < max_per_class_reg_vals && remaining_reg_vals > 0 {
-                    let reg = match rc {
-                        RegClass::I64 => xreg(*next_reg),
-                        RegClass::V128 => vreg(*next_reg),
-                        _ => unreachable!(),
-                    };
-                    ret.push(ABIArg::reg(
-                        reg.to_real_reg(),
-                        param.value_type,
-                        param.extension,
-                        param.purpose,
-                    ));
-                    *next_reg += 1;
-                    remaining_reg_vals -= 1;
-                    continue;
-                }
-            }
-
-            // Spill to the stack
-
-            // Compute the stack slot's size.
-            let size = (ty_bits(param.value_type) / 8) as u64;
-
-            let size = if is_apple_cc
-                || (call_conv.extends_wasmtime() && args_or_rets == ArgsOrRets::Rets)
-            {
-                // MacOS aarch64 and Wasmtime allow stack slots with
-                // sizes less than 8 bytes. They still need to be
-                // properly aligned on their natural data alignment,
-                // though.
-                size
-            } else {
-                // Every arg takes a minimum slot of 8 bytes. (16-byte stack
-                // alignment happens separately after all args.)
-                std::cmp::max(size, 8)
-            };
-
-            // Align the stack slot.
-            debug_assert!(size.is_power_of_two());
-            next_stack = align_to(next_stack, size);
-
-            let slots = reg_types
-                .iter()
-                .copied()
-                // Build the stack locations from each slot
-                .scan(next_stack, |next_stack, ty| {
-                    let slot_offset = *next_stack as i64;
-                    *next_stack += (ty_bits(ty) / 8) as u64;
-
-                    Some((ty, slot_offset))
-                })
-                .map(|(ty, offset)| ABIArgSlot::Stack {
-                    offset,
-                    ty,
-                    extension: param.extension,
-                })
-                .collect();
-
-            ret.push(ABIArg::Slots {
-                slots,
-                purpose: param.purpose,
-            });
-
-            next_stack += size;
-        }
-
-        if args_or_rets == ArgsOrRets::Rets && is_baldrdash {
-            ret.reverse();
-        }
-
-        let extra_arg = if add_ret_area_ptr {
-            debug_assert!(args_or_rets == ArgsOrRets::Args);
-            if next_xreg < max_per_class_reg_vals && remaining_reg_vals > 0 {
-                ret.push(ABIArg::reg(
-                    xreg(next_xreg).to_real_reg(),
-                    I64,
-                    ir::ArgumentExtension::None,
-                    ir::ArgumentPurpose::Normal,
-                ));
-            } else {
-                ret.push(ABIArg::stack(
-                    next_stack as i64,
-                    I64,
-                    ir::ArgumentExtension::None,
-                    ir::ArgumentPurpose::Normal,
-                ));
-                next_stack += 8;
-            }
-            Some(ret.len() - 1)
-        } else {
-            None
-        };
-
-        next_stack = align_to(next_stack, 16);
-
-        // To avoid overflow issues, limit the arg/return size to something
-        // reasonable -- here, 128 MB.
-        if next_stack > STACK_ARG_RET_SIZE_LIMIT {
-            return Err(CodegenError::ImplLimitExceeded);
-        }
-
-        Ok((ret, next_stack as i64, extra_arg))
-    }
-
-    fn fp_to_arg_offset(call_conv: isa::CallConv, flags: &settings::Flags) -> i64 {
-        if call_conv.extends_baldrdash() {
-            let num_words = flags.baldrdash_prologue_words() as i64;
-            debug_assert!(num_words > 0, "baldrdash must set baldrdash_prologue_words");
-            debug_assert_eq!(num_words % 2, 0, "stack must be 16-aligned");
-            num_words * 8
-        } else {
-            16 // frame pointer + return address.
-        }
-    }
-
-    fn gen_load_stack(mem: StackAMode, into_reg: Writable<Reg>, ty: Type) -> Inst {
-        Inst::gen_load(into_reg, mem.into(), ty, MemFlags::trusted())
-    }
-
-    fn gen_store_stack(mem: StackAMode, from_reg: Reg, ty: Type) -> Inst {
-        Inst::gen_store(mem.into(), from_reg, ty, MemFlags::trusted())
-    }
-
-    fn gen_move(to_reg: Writable<Reg>, from_reg: Reg, ty: Type) -> Inst {
-        Inst::gen_move(to_reg, from_reg, ty)
-    }
-
-    fn gen_extend(
-        to_reg: Writable<Reg>,
-        from_reg: Reg,
-        signed: bool,
-        from_bits: u8,
-        to_bits: u8,
-    ) -> Inst {
-        assert!(from_bits < to_bits);
-        Inst::Extend {
-            rd: to_reg,
-            rn: from_reg,
-            signed,
-            from_bits,
-            to_bits,
-        }
-    }
-
-    fn gen_ret() -> Inst {
-        Inst::Ret
-    }
-
-    fn gen_add_imm(into_reg: Writable<Reg>, from_reg: Reg, imm: u32) -> SmallInstVec<Inst> {
-        let imm = imm as u64;
-        let mut insts = SmallVec::new();
-        if let Some(imm12) = Imm12::maybe_from_u64(imm) {
-            insts.push(Inst::AluRRImm12 {
-                alu_op: ALUOp::Add,
-                size: OperandSize::Size64,
-                rd: into_reg,
-                rn: from_reg,
-                imm12,
-            });
-        } else {
-            let scratch2 = writable_tmp2_reg();
-            assert_ne!(scratch2.to_reg(), from_reg);
-            insts.extend(Inst::load_constant(scratch2, imm.into()));
-            insts.push(Inst::AluRRRExtend {
-                alu_op: ALUOp::Add,
-                size: OperandSize::Size64,
-                rd: into_reg,
-                rn: from_reg,
-                rm: scratch2.to_reg(),
-                extendop: ExtendOp::UXTX,
-            });
-        }
-        insts
-    }
-
-    fn gen_stack_lower_bound_trap(limit_reg: Reg) -> SmallInstVec<Inst> {
-        let mut insts = SmallVec::new();
-        insts.push(Inst::AluRRRExtend {
-            alu_op: ALUOp::SubS,
-            size: OperandSize::Size64,
-            rd: writable_zero_reg(),
-            rn: stack_reg(),
-            rm: limit_reg,
-            extendop: ExtendOp::UXTX,
-        });
-        insts.push(Inst::TrapIf {
-            trap_code: ir::TrapCode::StackOverflow,
-            // Here `Lo` == "less than" when interpreting the two
-            // operands as unsigned integers.
-            kind: CondBrKind::Cond(Cond::Lo),
-        });
-        insts
-    }
-
-    fn gen_epilogue_placeholder() -> Inst {
-        Inst::EpiloguePlaceholder
-    }
-
-    fn gen_get_stack_addr(mem: StackAMode, into_reg: Writable<Reg>, _ty: Type) -> Inst {
-        let mem = mem.into();
-        Inst::LoadAddr { rd: into_reg, mem }
-    }
-
-    fn get_stacklimit_reg() -> Reg {
-        spilltmp_reg()
-    }
-
-    fn gen_load_base_offset(into_reg: Writable<Reg>, base: Reg, offset: i32, ty: Type) -> Inst {
-        let mem = AMode::RegOffset(base, offset as i64, ty);
-        Inst::gen_load(into_reg, mem, ty, MemFlags::trusted())
-    }
-
-    fn gen_store_base_offset(base: Reg, offset: i32, from_reg: Reg, ty: Type) -> Inst {
-        let mem = AMode::RegOffset(base, offset as i64, ty);
-        Inst::gen_store(mem, from_reg, ty, MemFlags::trusted())
-    }
-
-    fn gen_sp_reg_adjust(amount: i32) -> SmallInstVec<Inst> {
-        if amount == 0 {
-            return SmallVec::new();
-        }
-
-        let (amount, is_sub) = if amount > 0 {
-            (amount as u64, false)
-        } else {
-            (-amount as u64, true)
-        };
-
-        let alu_op = if is_sub { ALUOp::Sub } else { ALUOp::Add };
-
-        let mut ret = SmallVec::new();
-        if let Some(imm12) = Imm12::maybe_from_u64(amount) {
-            let adj_inst = Inst::AluRRImm12 {
-                alu_op,
-                size: OperandSize::Size64,
-                rd: writable_stack_reg(),
-                rn: stack_reg(),
-                imm12,
-            };
-            ret.push(adj_inst);
-        } else {
-            let tmp = writable_spilltmp_reg();
-            let const_inst = Inst::load_constant(tmp, amount);
-            let adj_inst = Inst::AluRRRExtend {
-                alu_op,
-                size: OperandSize::Size64,
-                rd: writable_stack_reg(),
-                rn: stack_reg(),
-                rm: tmp.to_reg(),
-                extendop: ExtendOp::UXTX,
-            };
-            ret.extend(const_inst);
-            ret.push(adj_inst);
-        }
-        ret
-    }
-
-    fn gen_nominal_sp_adj(offset: i32) -> Inst {
-        Inst::VirtualSPOffsetAdj {
-            offset: offset as i64,
-        }
-    }
-
-    fn gen_debug_frame_info(
-        flags: &settings::Flags,
-        _isa_flags: &Vec<settings::Value>,
-    ) -> SmallInstVec<Inst> {
-        let mut insts = SmallVec::new();
-        if flags.unwind_info() {
-            insts.push(Inst::Unwind {
-                inst: UnwindInst::Aarch64SetPointerAuth {
-                    return_addresses: false,
-                },
-            });
-        }
-        insts
-    }
-
-    fn gen_prologue_frame_setup(flags: &settings::Flags) -> SmallInstVec<Inst> {
-        let mut insts = SmallVec::new();
-
-        // stp fp (x29), lr (x30), [sp, #-16]!
-        insts.push(Inst::StoreP64 {
-            rt: fp_reg(),
-            rt2: link_reg(),
-            mem: PairAMode::PreIndexed(
-                writable_stack_reg(),
-                SImm7Scaled::maybe_from_i64(-16, types::I64).unwrap(),
-            ),
-            flags: MemFlags::trusted(),
-        });
-
-        if flags.unwind_info() {
-            insts.push(Inst::Unwind {
-                inst: UnwindInst::PushFrameRegs {
-                    offset_upward_to_caller_sp: 16, // FP, LR
-                },
-            });
-        }
-
-        // mov fp (x29), sp. This uses the ADDI rd, rs, 0 form of `MOV` because
-        // the usual encoding (`ORR`) does not work with SP.
-        insts.push(Inst::AluRRImm12 {
-            alu_op: ALUOp::Add,
-            size: OperandSize::Size64,
-            rd: writable_fp_reg(),
-            rn: stack_reg(),
-            imm12: Imm12 {
-                bits: 0,
-                shift12: false,
-            },
-        });
-        insts
-    }
-
-    fn gen_epilogue_frame_restore(_: &settings::Flags) -> SmallInstVec<Inst> {
-        let mut insts = SmallVec::new();
-
-        // N.B.: sp is already adjusted to the appropriate place by the
-        // clobber-restore code (which also frees the fixed frame). Hence, there
-        // is no need for the usual `mov sp, fp` here.
-
-        // `ldp fp, lr, [sp], #16`
-        insts.push(Inst::LoadP64 {
-            rt: writable_fp_reg(),
-            rt2: writable_link_reg(),
-            mem: PairAMode::PostIndexed(
-                writable_stack_reg(),
-                SImm7Scaled::maybe_from_i64(16, types::I64).unwrap(),
-            ),
-            flags: MemFlags::trusted(),
-        });
-        insts
-    }
-
-    fn gen_probestack(_: u32) -> SmallInstVec<Self::I> {
-        // TODO: implement if we ever require stack probes on an AArch64 host
-        // (unlikely unless Lucet is ported)
-        smallvec![]
-    }
-
-    // Returns stack bytes used as well as instructions. Does not adjust
-    // nominal SP offset; abi_impl generic code will do that.
-    fn gen_clobber_save(
-        call_conv: isa::CallConv,
-        setup_frame: bool,
-        flags: &settings::Flags,
-        clobbered_callee_saves: &Vec<Writable<RealReg>>,
-        fixed_frame_storage_size: u32,
-        _outgoing_args_size: u32,
-    ) -> (u64, SmallVec<[Inst; 16]>) {
-        let mut clobbered_int = vec![];
-        let mut clobbered_vec = vec![];
-
-        for &reg in clobbered_callee_saves.iter() {
-            match reg.to_reg().get_class() {
-                RegClass::I64 => clobbered_int.push(reg),
-                RegClass::V128 => clobbered_vec.push(reg),
-                class => panic!("Unexpected RegClass: {:?}", class),
-            }
-        }
-
-        let (int_save_bytes, vec_save_bytes) =
-            saved_reg_stack_size(call_conv, &clobbered_int, &clobbered_vec);
-        let total_save_bytes = int_save_bytes + vec_save_bytes;
-        let clobber_size = total_save_bytes as i32;
-        let mut insts = SmallVec::new();
-
-        if flags.unwind_info() && setup_frame {
-            // The *unwind* frame (but not the actual frame) starts at the
-            // clobbers, just below the saved FP/LR pair.
-            insts.push(Inst::Unwind {
-                inst: UnwindInst::DefineNewFrame {
-                    offset_downward_to_clobbers: clobber_size as u32,
-                    offset_upward_to_caller_sp: 16, // FP, LR
-                },
-            });
-        }
-
-        // We use pre-indexed addressing modes here, rather than the possibly
-        // more efficient "subtract sp once then used fixed offsets" scheme,
-        // because (i) we cannot necessarily guarantee that the offset of a
-        // clobber-save slot will be within a SImm7Scaled (+504-byte) offset
-        // range of the whole frame including other slots, it is more complex to
-        // conditionally generate a two-stage SP adjustment (clobbers then fixed
-        // frame) otherwise, and generally we just want to maintain simplicity
-        // here for maintainability.  Because clobbers are at the top of the
-        // frame, just below FP, all that is necessary is to use the pre-indexed
-        // "push" `[sp, #-16]!` addressing mode.
-        //
-        // `frame_offset` tracks offset above start-of-clobbers for unwind-info
-        // purposes.
-        let mut clobber_offset = clobber_size as u32;
-        let clobber_offset_change = 16;
-        let iter = clobbered_int.chunks_exact(2);
-
-        if let [rd] = iter.remainder() {
-            let rd = rd.to_reg().to_reg();
-
-            debug_assert_eq!(rd.get_class(), RegClass::I64);
-            // str rd, [sp, #-16]!
-            insts.push(Inst::Store64 {
-                rd,
-                mem: AMode::PreIndexed(
-                    writable_stack_reg(),
-                    SImm9::maybe_from_i64(-clobber_offset_change).unwrap(),
-                ),
-                flags: MemFlags::trusted(),
-            });
-
-            if flags.unwind_info() {
-                clobber_offset -= clobber_offset_change as u32;
-                insts.push(Inst::Unwind {
-                    inst: UnwindInst::SaveReg {
-                        clobber_offset,
-                        reg: rd.to_real_reg(),
-                    },
-                });
-            }
-        }
-
-        let mut iter = iter.rev();
-
-        while let Some([rt, rt2]) = iter.next() {
-            // .to_reg().to_reg(): Writable<RealReg> --> RealReg --> Reg
-            let rt = rt.to_reg().to_reg();
-            let rt2 = rt2.to_reg().to_reg();
-
-            debug_assert!(rt.get_class() == RegClass::I64);
-            debug_assert!(rt2.get_class() == RegClass::I64);
-
-            // stp rt, rt2, [sp, #-16]!
-            insts.push(Inst::StoreP64 {
-                rt,
-                rt2,
-                mem: PairAMode::PreIndexed(
-                    writable_stack_reg(),
-                    SImm7Scaled::maybe_from_i64(-clobber_offset_change, types::I64).unwrap(),
-                ),
-                flags: MemFlags::trusted(),
-            });
-
-            if flags.unwind_info() {
-                clobber_offset -= clobber_offset_change as u32;
-                insts.push(Inst::Unwind {
-                    inst: UnwindInst::SaveReg {
-                        clobber_offset,
-                        reg: rt.to_real_reg(),
-                    },
-                });
-                insts.push(Inst::Unwind {
-                    inst: UnwindInst::SaveReg {
-                        clobber_offset: clobber_offset + (clobber_offset_change / 2) as u32,
-                        reg: rt2.to_real_reg(),
-                    },
-                });
-            }
-        }
-
-        let store_vec_reg = |rd| {
-            if call_conv.extends_baldrdash() {
-                Inst::FpuStore128 {
-                    rd,
-                    mem: AMode::PreIndexed(
-                        writable_stack_reg(),
-                        SImm9::maybe_from_i64(-clobber_offset_change).unwrap(),
-                    ),
-                    flags: MemFlags::trusted(),
-                }
-            } else {
-                Inst::FpuStore64 {
-                    rd,
-                    mem: AMode::PreIndexed(
-                        writable_stack_reg(),
-                        SImm9::maybe_from_i64(-clobber_offset_change).unwrap(),
-                    ),
-                    flags: MemFlags::trusted(),
-                }
-            }
-        };
-        let iter = clobbered_vec.chunks_exact(2);
-
-        if let [rd] = iter.remainder() {
-            let rd = rd.to_reg().to_reg();
-
-            debug_assert_eq!(rd.get_class(), RegClass::V128);
-            insts.push(store_vec_reg(rd));
-
-            if flags.unwind_info() {
-                clobber_offset -= clobber_offset_change as u32;
-                insts.push(Inst::Unwind {
-                    inst: UnwindInst::SaveReg {
-                        clobber_offset,
-                        reg: rd.to_real_reg(),
-                    },
-                });
-            }
-        }
-
-        let store_vec_reg_pair = |rt, rt2| {
-            if call_conv.extends_baldrdash() {
-                let clobber_offset_change = 32;
-
-                (
-                    Inst::FpuStoreP128 {
-                        rt,
-                        rt2,
-                        mem: PairAMode::PreIndexed(
-                            writable_stack_reg(),
-                            SImm7Scaled::maybe_from_i64(-clobber_offset_change, I8X16).unwrap(),
-                        ),
-                        flags: MemFlags::trusted(),
-                    },
-                    clobber_offset_change as u32,
-                )
-            } else {
-                let clobber_offset_change = 16;
-
-                (
-                    Inst::FpuStoreP64 {
-                        rt,
-                        rt2,
-                        mem: PairAMode::PreIndexed(
-                            writable_stack_reg(),
-                            SImm7Scaled::maybe_from_i64(-clobber_offset_change, F64).unwrap(),
-                        ),
-                        flags: MemFlags::trusted(),
-                    },
-                    clobber_offset_change as u32,
-                )
-            }
-        };
-        let mut iter = iter.rev();
-
-        while let Some([rt, rt2]) = iter.next() {
-            let rt = rt.to_reg().to_reg();
-            let rt2 = rt2.to_reg().to_reg();
-
-            debug_assert_eq!(rt.get_class(), RegClass::V128);
-            debug_assert_eq!(rt2.get_class(), RegClass::V128);
-
-            let (inst, clobber_offset_change) = store_vec_reg_pair(rt, rt2);
-
-            insts.push(inst);
-
-            if flags.unwind_info() {
-                clobber_offset -= clobber_offset_change;
-                insts.push(Inst::Unwind {
-                    inst: UnwindInst::SaveReg {
-                        clobber_offset,
-                        reg: rt.to_real_reg(),
-                    },
-                });
-                insts.push(Inst::Unwind {
-                    inst: UnwindInst::SaveReg {
-                        clobber_offset: clobber_offset + clobber_offset_change / 2,
-                        reg: rt2.to_real_reg(),
-                    },
-                });
-            }
-        }
-
-        // Allocate the fixed frame below the clobbers if necessary.
-        if fixed_frame_storage_size > 0 {
-            insts.extend(Self::gen_sp_reg_adjust(-(fixed_frame_storage_size as i32)));
-        }
-
-        (total_save_bytes as u64, insts)
-    }
-
-    fn gen_clobber_restore(
-        call_conv: isa::CallConv,
-        flags: &settings::Flags,
-        clobbers: &Set<Writable<RealReg>>,
-        fixed_frame_storage_size: u32,
-        _outgoing_args_size: u32,
-    ) -> SmallVec<[Inst; 16]> {
-        let mut insts = SmallVec::new();
-        let (clobbered_int, clobbered_vec) = get_regs_restored_in_epilogue(call_conv, clobbers);
-
-        // Free the fixed frame if necessary.
-        if fixed_frame_storage_size > 0 {
-            insts.extend(Self::gen_sp_reg_adjust(fixed_frame_storage_size as i32));
-        }
-
-        let load_vec_reg = |rd| {
-            if call_conv.extends_baldrdash() {
-                Inst::FpuLoad128 {
-                    rd,
-                    mem: AMode::PostIndexed(
-                        writable_stack_reg(),
-                        SImm9::maybe_from_i64(16).unwrap(),
-                    ),
-                    flags: MemFlags::trusted(),
-                }
-            } else {
-                Inst::FpuLoad64 {
-                    rd,
-                    mem: AMode::PostIndexed(
-                        writable_stack_reg(),
-                        SImm9::maybe_from_i64(16).unwrap(),
-                    ),
-                    flags: MemFlags::trusted(),
-                }
-            }
-        };
-        let load_vec_reg_pair = |rt, rt2| {
-            if call_conv.extends_baldrdash() {
-                Inst::FpuLoadP128 {
-                    rt,
-                    rt2,
-                    mem: PairAMode::PostIndexed(
-                        writable_stack_reg(),
-                        SImm7Scaled::maybe_from_i64(32, I8X16).unwrap(),
-                    ),
-                    flags: MemFlags::trusted(),
-                }
-            } else {
-                Inst::FpuLoadP64 {
-                    rt,
-                    rt2,
-                    mem: PairAMode::PostIndexed(
-                        writable_stack_reg(),
-                        SImm7Scaled::maybe_from_i64(16, F64).unwrap(),
-                    ),
-                    flags: MemFlags::trusted(),
-                }
-            }
-        };
-
-        let mut iter = clobbered_vec.chunks_exact(2);
-
-        while let Some([rt, rt2]) = iter.next() {
-            let rt = rt.map(|r| r.to_reg());
-            let rt2 = rt2.map(|r| r.to_reg());
-
-            debug_assert_eq!(rt.to_reg().get_class(), RegClass::V128);
-            debug_assert_eq!(rt2.to_reg().get_class(), RegClass::V128);
-            insts.push(load_vec_reg_pair(rt, rt2));
-        }
-
-        debug_assert!(iter.remainder().len() <= 1);
-
-        if let [rd] = iter.remainder() {
-            let rd = rd.map(|r| r.to_reg());
-
-            debug_assert_eq!(rd.to_reg().get_class(), RegClass::V128);
-            insts.push(load_vec_reg(rd));
-        }
-
-        let mut iter = clobbered_int.chunks_exact(2);
-
-        while let Some([rt, rt2]) = iter.next() {
-            let rt = rt.map(|r| r.to_reg());
-            let rt2 = rt2.map(|r| r.to_reg());
-
-            debug_assert_eq!(rt.to_reg().get_class(), RegClass::I64);
-            debug_assert_eq!(rt2.to_reg().get_class(), RegClass::I64);
-            // ldp rt, rt2, [sp], #16
-            insts.push(Inst::LoadP64 {
-                rt,
-                rt2,
-                mem: PairAMode::PostIndexed(
-                    writable_stack_reg(),
-                    SImm7Scaled::maybe_from_i64(16, I64).unwrap(),
-                ),
-                flags: MemFlags::trusted(),
-            });
-        }
-
-        debug_assert!(iter.remainder().len() <= 1);
-
-        if let [rd] = iter.remainder() {
-            let rd = rd.map(|r| r.to_reg());
-
-            debug_assert_eq!(rd.to_reg().get_class(), RegClass::I64);
-            // ldr rd, [sp], #16
-            insts.push(Inst::ULoad64 {
-                rd,
-                mem: AMode::PostIndexed(writable_stack_reg(), SImm9::maybe_from_i64(16).unwrap()),
-                flags: MemFlags::trusted(),
-            });
-        }
-
-        // If this is Baldrdash-2020, restore the callee (i.e., our) TLS
-        // register. We may have allocated it for something else and clobbered
-        // it, but the ABI expects us to leave the TLS register unchanged.
-        if call_conv == isa::CallConv::Baldrdash2020 {
-            let off = BALDRDASH_CALLEE_TLS_OFFSET + Self::fp_to_arg_offset(call_conv, flags);
-            insts.push(Inst::gen_load(
-                writable_xreg(BALDRDASH_TLS_REG),
-                AMode::UnsignedOffset(fp_reg(), UImm12Scaled::maybe_from_i64(off, I64).unwrap()),
-                I64,
-                MemFlags::trusted(),
-            ));
-        }
-
-        insts
-    }
-
-    fn gen_call(
-        dest: &CallDest,
-        uses: Vec<Reg>,
-        defs: Vec<Writable<Reg>>,
-        opcode: ir::Opcode,
-        tmp: Writable<Reg>,
-        callee_conv: isa::CallConv,
-        caller_conv: isa::CallConv,
-    ) -> SmallVec<[(InstIsSafepoint, Inst); 2]> {
-        let mut insts = SmallVec::new();
-        match &dest {
-            &CallDest::ExtName(ref name, RelocDistance::Near) => insts.push((
-                InstIsSafepoint::Yes,
-                Inst::Call {
-                    info: Box::new(CallInfo {
-                        dest: name.clone(),
-                        uses,
-                        defs,
-                        opcode,
-                        caller_callconv: caller_conv,
-                        callee_callconv: callee_conv,
-                    }),
-                },
-            )),
-            &CallDest::ExtName(ref name, RelocDistance::Far) => {
-                insts.push((
-                    InstIsSafepoint::No,
-                    Inst::LoadExtName {
-                        rd: tmp,
-                        name: Box::new(name.clone()),
-                        offset: 0,
-                    },
-                ));
-                insts.push((
-                    InstIsSafepoint::Yes,
-                    Inst::CallInd {
-                        info: Box::new(CallIndInfo {
-                            rn: tmp.to_reg(),
-                            uses,
-                            defs,
-                            opcode,
-                            caller_callconv: caller_conv,
-                            callee_callconv: callee_conv,
-                        }),
-                    },
-                ));
-            }
-            &CallDest::Reg(reg) => insts.push((
-                InstIsSafepoint::Yes,
-                Inst::CallInd {
-                    info: Box::new(CallIndInfo {
-                        rn: *reg,
-                        uses,
-                        defs,
-                        opcode,
-                        caller_callconv: caller_conv,
-                        callee_callconv: callee_conv,
-                    }),
-                },
-            )),
-        }
-
-        insts
-    }
-
-    fn gen_memcpy(
-        call_conv: isa::CallConv,
-        dst: Reg,
-        src: Reg,
-        size: usize,
-    ) -> SmallVec<[Self::I; 8]> {
-        // Baldrdash should not use struct args.
-        assert!(!call_conv.extends_baldrdash());
-        let mut insts = SmallVec::new();
-        let arg0 = writable_xreg(0);
-        let arg1 = writable_xreg(1);
-        let arg2 = writable_xreg(2);
-        insts.push(Inst::gen_move(arg0, dst, I64));
-        insts.push(Inst::gen_move(arg1, src, I64));
-        insts.extend(Inst::load_constant(arg2, size as u64).into_iter());
-        insts.push(Inst::Call {
-            info: Box::new(CallInfo {
-                dest: ExternalName::LibCall(LibCall::Memcpy),
-                uses: vec![arg0.to_reg(), arg1.to_reg(), arg2.to_reg()],
-                defs: Self::get_regs_clobbered_by_call(call_conv),
-                opcode: Opcode::Call,
-                caller_callconv: call_conv,
-                callee_callconv: call_conv,
-            }),
-        });
-        insts
-    }
-
-    fn get_number_of_spillslots_for_value(rc: RegClass) -> u32 {
-        // We allocate in terms of 8-byte slots.
-        match rc {
-            RegClass::I64 => 1,
-            RegClass::V128 => 2,
-            _ => panic!("Unexpected register class!"),
-        }
-    }
-
-    /// Get the current virtual-SP offset from an instruction-emission state.
-    fn get_virtual_sp_offset_from_state(s: &EmitState) -> i64 {
-        s.virtual_sp_offset
-    }
-
-    /// Get the nominal-SP-to-FP offset from an instruction-emission state.
-    fn get_nominal_sp_to_fp(s: &EmitState) -> i64 {
-        s.nominal_sp_to_fp
-    }
-
-    fn get_regs_clobbered_by_call(call_conv_of_callee: isa::CallConv) -> Vec<Writable<Reg>> {
-        let mut caller_saved = Vec::new();
-        for i in 0..29 {
-            let x = writable_xreg(i);
-            if is_reg_clobbered_by_call(call_conv_of_callee, x.to_reg().to_real_reg()) {
-                caller_saved.push(x);
-            }
-        }
-        for i in 0..32 {
-            let v = writable_vreg(i);
-            if is_reg_clobbered_by_call(call_conv_of_callee, v.to_reg().to_real_reg()) {
-                caller_saved.push(v);
-            }
-        }
-        caller_saved
-    }
-
-    fn get_ext_mode(
-        call_conv: isa::CallConv,
-        specified: ir::ArgumentExtension,
-    ) -> ir::ArgumentExtension {
-        if call_conv.extends_baldrdash() {
-            // Baldrdash (SpiderMonkey) always extends args and return values to the full register.
-            specified
-        } else {
-            // No other supported ABI on AArch64 does so.
-            ir::ArgumentExtension::None
-        }
-    }
-
-    fn get_clobbered_callee_saves(
-        call_conv: isa::CallConv,
-        regs: &Set<Writable<RealReg>>,
-    ) -> Vec<Writable<RealReg>> {
-        let mut regs: Vec<Writable<RealReg>> = regs
-            .iter()
-            .cloned()
-            .filter(|r| is_reg_saved_in_prologue(call_conv, r.to_reg()))
-            .collect();
-
-        // Sort registers for deterministic code output. We can do an unstable
-        // sort because the registers will be unique (there are no dups).
-        regs.sort_unstable_by_key(|r| r.to_reg().get_index());
-        regs
-    }
-
-    fn is_frame_setup_needed(
-        is_leaf: bool,
-        stack_args_size: u32,
-        num_clobbered_callee_saves: usize,
-        fixed_frame_storage_size: u32,
-    ) -> bool {
-        !is_leaf
-            // The function arguments that are passed on the stack are addressed
-            // relative to the Frame Pointer.
-            || stack_args_size > 0
-            || num_clobbered_callee_saves > 0
-            || fixed_frame_storage_size > 0
-    }
-}
-
-/// Is this type supposed to be seen on this machine? E.g. references of the
-/// wrong width are invalid.
-fn legal_type_for_machine(ty: Type) -> bool {
-    match ty {
-        R32 => false,
-        _ => true,
-    }
-}
-
-/// Is the given register saved in the prologue if clobbered, i.e., is it a
-/// callee-save?
-fn is_reg_saved_in_prologue(call_conv: isa::CallConv, r: RealReg) -> bool {
-    if call_conv.extends_baldrdash() {
-        match r.get_class() {
-            RegClass::I64 => {
-                let enc = r.get_hw_encoding();
-                return BALDRDASH_JIT_CALLEE_SAVED_GPR[enc];
-            }
-            RegClass::V128 => {
-                let enc = r.get_hw_encoding();
-                return BALDRDASH_JIT_CALLEE_SAVED_FPU[enc];
-            }
-            _ => unimplemented!("baldrdash callee saved on non-i64 reg classes"),
-        };
-    }
-
-    match r.get_class() {
-        RegClass::I64 => {
-            // x19 - x28 inclusive are callee-saves.
-            r.get_hw_encoding() >= 19 && r.get_hw_encoding() <= 28
-        }
-        RegClass::V128 => {
-            // v8 - v15 inclusive are callee-saves.
-            r.get_hw_encoding() >= 8 && r.get_hw_encoding() <= 15
-        }
-        _ => panic!("Unexpected RegClass"),
-    }
-}
-
-/// Return the set of all integer and vector registers that must be saved in the
-/// prologue and restored in the epilogue, given the set of all registers
-/// written by the function's body.
-fn get_regs_restored_in_epilogue(
-    call_conv: isa::CallConv,
-    regs: &Set<Writable<RealReg>>,
-) -> (Vec<Writable<RealReg>>, Vec<Writable<RealReg>>) {
-    let mut int_saves = vec![];
-    let mut vec_saves = vec![];
-    for &reg in regs.iter() {
-        if is_reg_saved_in_prologue(call_conv, reg.to_reg()) {
-            match reg.to_reg().get_class() {
-                RegClass::I64 => int_saves.push(reg),
-                RegClass::V128 => vec_saves.push(reg),
-                _ => panic!("Unexpected RegClass"),
-            }
-        }
-    }
-    // Sort registers for deterministic code output. We can do an unstable sort because the
-    // registers will be unique (there are no dups).
-    int_saves.sort_unstable_by_key(|r| r.to_reg().get_index());
-    vec_saves.sort_unstable_by_key(|r| r.to_reg().get_index());
-    (int_saves, vec_saves)
-}
-
-fn is_reg_clobbered_by_call(call_conv_of_callee: isa::CallConv, r: RealReg) -> bool {
-    if call_conv_of_callee.extends_baldrdash() {
-        match r.get_class() {
-            RegClass::I64 => {
-                let enc = r.get_hw_encoding();
-                if !BALDRDASH_JIT_CALLEE_SAVED_GPR[enc] {
-                    return true;
-                }
-                // Otherwise, fall through to preserve native's ABI caller-saved.
-            }
-            RegClass::V128 => {
-                let enc = r.get_hw_encoding();
-                if !BALDRDASH_JIT_CALLEE_SAVED_FPU[enc] {
-                    return true;
-                }
-                // Otherwise, fall through to preserve native's ABI caller-saved.
-            }
-            _ => unimplemented!("baldrdash callee saved on non-i64 reg classes"),
-        };
-    }
-
-    match r.get_class() {
-        RegClass::I64 => {
-            // x0 - x17 inclusive are caller-saves.
-            r.get_hw_encoding() <= 17
-        }
-        RegClass::V128 => {
-            // v0 - v7 inclusive and v16 - v31 inclusive are caller-saves. The
-            // upper 64 bits of v8 - v15 inclusive are also caller-saves.
-            // However, because we cannot currently represent partial registers
-            // to regalloc.rs, we indicate here that every vector register is
-            // caller-save. Because this function is used at *callsites*,
-            // approximating in this direction (save more than necessary) is
-            // conservative and thus safe.
-            //
-            // Note that we set the 'not included in clobber set' flag in the
-            // regalloc.rs API when a call instruction's callee has the same ABI
-            // as the caller (the current function body); this is safe (anything
-            // clobbered by callee can be clobbered by caller as well) and
-            // avoids unnecessary saves of v8-v15 in the prologue even though we
-            // include them as defs here.
-            true
-        }
-        _ => panic!("Unexpected RegClass"),
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/inst.isle b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/inst.isle
deleted file mode 100644
index 91fe89825..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/inst.isle
+++ /dev/null
@@ -1,1999 +0,0 @@
-;; Instruction formats.
-(type MInst
-  (enum
-    ;; A no-op of zero size.
-    (Nop0)
-
-    ;; A no-op that is one instruction large.
-    (Nop4)
-
-    ;; An ALU operation with two register sources and a register destination.
-    (AluRRR
-      (alu_op ALUOp)
-      (size OperandSize)
-      (rd WritableReg)
-      (rn Reg)
-      (rm Reg))
-
-    ;; An ALU operation with three register sources and a register destination.
-    (AluRRRR
-      (alu_op ALUOp3)
-      (rd WritableReg)
-      (rn Reg)
-      (rm Reg)
-      (ra Reg))
-
-    ;; An ALU operation with a register source and an immediate-12 source, and a register
-    ;; destination.
-    (AluRRImm12
-      (alu_op ALUOp)
-      (size OperandSize)
-      (rd WritableReg)
-      (rn Reg)
-      (imm12 Imm12))
-
-    ;; An ALU operation with a register source and an immediate-logic source, and a register destination.
-    (AluRRImmLogic
-      (alu_op ALUOp)
-      (size OperandSize)
-      (rd WritableReg)
-      (rn Reg)
-      (imml ImmLogic))
-
-    ;; An ALU operation with a register source and an immediate-shiftamt source, and a register destination.
-    (AluRRImmShift
-      (alu_op ALUOp)
-      (size OperandSize)
-      (rd WritableReg)
-      (rn Reg)
-      (immshift ImmShift))
-
-    ;; An ALU operation with two register sources, one of which can be shifted, and a register
-    ;; destination.
-    (AluRRRShift
-      (alu_op ALUOp)
-      (size OperandSize)
-      (rd WritableReg)
-      (rn Reg)
-      (rm Reg)
-      (shiftop ShiftOpAndAmt))
-
-    ;; An ALU operation with two register sources, one of which can be {zero,sign}-extended and
-    ;; shifted, and a register destination.
-    (AluRRRExtend
-      (alu_op ALUOp)
-      (size OperandSize)
-      (rd WritableReg)
-      (rn Reg)
-      (rm Reg)
-      (extendop ExtendOp))
-
-    ;; A bit op instruction with a single register source.
-    (BitRR
-      (op BitOp)
-      (size OperandSize)
-      (rd WritableReg)
-      (rn Reg))
-
-    ;; An unsigned (zero-extending) 8-bit load.
-    (ULoad8
-      (rd WritableReg)
-      (mem AMode)
-      (flags MemFlags))
-
-    ;; A signed (sign-extending) 8-bit load.
-    (SLoad8
-      (rd WritableReg)
-      (mem AMode)
-      (flags MemFlags))
-
-    ;; An unsigned (zero-extending) 16-bit load.
-    (ULoad16
-      (rd WritableReg)
-      (mem AMode)
-      (flags MemFlags))
-
-    ;; A signed (sign-extending) 16-bit load.
-    (SLoad16
-      (rd WritableReg)
-      (mem AMode)
-      (flags MemFlags))
-
-    ;; An unsigned (zero-extending) 32-bit load.
-    (ULoad32
-      (rd WritableReg)
-      (mem AMode)
-      (flags MemFlags))
-
-    ;; A signed (sign-extending) 32-bit load.
-    (SLoad32
-      (rd WritableReg)
-      (mem AMode)
-      (flags MemFlags))
-
-    ;; A 64-bit load.
-    (ULoad64
-      (rd WritableReg)
-      (mem AMode)
-      (flags MemFlags))
-
-    ;; An 8-bit store.
-    (Store8
-      (rd Reg)
-      (mem AMode)
-      (flags MemFlags))
-
-    ;; A 16-bit store.
-    (Store16
-      (rd Reg)
-      (mem AMode)
-      (flags MemFlags))
-
-    ;; A 32-bit store.
-    (Store32
-      (rd Reg)
-      (mem AMode)
-      (flags MemFlags))
-
-    ;; A 64-bit store.
-    (Store64
-      (rd Reg)
-      (mem AMode)
-      (flags MemFlags))
-
-    ;; A store of a pair of registers.
-    (StoreP64
-      (rt Reg)
-      (rt2 Reg)
-      (mem PairAMode)
-      (flags MemFlags))
-
-    ;; A load of a pair of registers.
-    (LoadP64
-      (rt WritableReg)
-      (rt2 WritableReg)
-      (mem PairAMode)
-      (flags MemFlags))
-
-    ;; A MOV instruction. These are encoded as ORR's (AluRRR form) but we
-    ;; keep them separate at the `Inst` level for better pretty-printing
-    ;; and faster `is_move()` logic.
-    (Mov64
-      (rd WritableReg)
-      (rm Reg))
-
-    ;; A 32-bit MOV. Zeroes the top 32 bits of the destination. This is
-    ;; effectively an alias for an unsigned 32-to-64-bit extension.
-    (Mov32
-      (rd WritableReg)
-      (rm Reg))
-
-    ;; A MOVZ with a 16-bit immediate.
-    (MovZ
-      (rd WritableReg)
-      (imm MoveWideConst)
-      (size OperandSize))
-
-    ;; A MOVN with a 16-bit immediate.
-    (MovN
-      (rd WritableReg)
-      (imm MoveWideConst)
-      (size OperandSize))
-
-    ;; A MOVK with a 16-bit immediate.
-    (MovK
-      (rd WritableReg)
-      (imm MoveWideConst)
-      (size OperandSize))
-
-    ;; A sign- or zero-extend operation.
-    (Extend
-      (rd WritableReg)
-      (rn Reg)
-      (signed bool)
-      (from_bits u8)
-      (to_bits u8))
-
-    ;; A conditional-select operation.
-    (CSel
-      (rd WritableReg)
-      (cond Cond)
-      (rn Reg)
-      (rm Reg))
-
-    ;; A conditional-set operation.
-    (CSet
-      (rd WritableReg)
-      (cond Cond))
-
-    ;; A conditional-set-mask operation.
-    (CSetm
-      (rd WritableReg)
-      (cond Cond))
-
-    ;; A conditional comparison with an immediate.
-    (CCmpImm
-      (size OperandSize)
-      (rn Reg)
-      (imm UImm5)
-      (nzcv NZCV)
-      (cond Cond))
-
-    ;; A synthetic insn, which is a load-linked store-conditional loop, that has the overall
-    ;; effect of atomically modifying a memory location in a particular way.  Because we have
-    ;; no way to explain to the regalloc about earlyclobber registers, this instruction has
-    ;; completely fixed operand registers, and we rely on the RA's coalescing to remove copies
-    ;; in the surrounding code to the extent it can.  The sequence is both preceded and
-    ;; followed by a fence which is at least as comprehensive as that of the `Fence`
-    ;; instruction below.  This instruction is sequentially consistent.  The operand
-    ;; conventions are:
-    ;;
-    ;; x25   (rd) address
-    ;; x26   (rd) second operand for `op`
-    ;; x27   (wr) old value
-    ;; x24   (wr) scratch reg; value afterwards has no meaning
-    ;; x28   (wr) scratch reg; value afterwards has no meaning
-    (AtomicRMWLoop
-      (ty Type) ;; I8, I16, I32 or I64
-      (op AtomicRmwOp))
-
-    ;; An atomic read-modify-write operation. These instructions require the
-    ;; Large System Extension (LSE) ISA support (FEAT_LSE). The instructions have
-    ;; acquire-release semantics.
-    (AtomicRMW
-      (op AtomicRMWOp)
-      (rs Reg)
-      (rt WritableReg)
-      (rn Reg)
-      (ty Type))
-
-    ;; An atomic compare-and-swap operation. This instruction is sequentially consistent.
-    (AtomicCAS
-      (rs WritableReg)
-      (rt Reg)
-      (rn Reg)
-      (ty Type))
-
-    ;; Similar to AtomicRMWLoop, a compare-and-swap operation implemented using a load-linked
-    ;; store-conditional loop.
-    ;; This instruction is sequentially consistent.
-    ;; Note that the operand conventions, although very similar to AtomicRMWLoop, are different:
-    ;;
-    ;; x25   (rd) address
-    ;; x26   (rd) expected value
-    ;; x28   (rd) replacement value
-    ;; x27   (wr) old value
-    ;; x24   (wr) scratch reg; value afterwards has no meaning
-    (AtomicCASLoop
-        (ty Type) ;; I8, I16, I32 or I64
-    )
-
-    ;; Read `access_ty` bits from address `rt`, either 8, 16, 32 or 64-bits, and put
-    ;; it in `rn`, optionally zero-extending to fill a word or double word result.
-    ;; This instruction is sequentially consistent.
-    (LoadAcquire
-      (access_ty Type) ;; I8, I16, I32 or I64
-      (rt WritableReg)
-      (rn Reg))
-
-    ;; Write the lowest `ty` bits of `rt` to address `rn`.
-    ;; This instruction is sequentially consistent.
-    (StoreRelease
-      (access_ty Type) ;; I8, I16, I32 or I64
-      (rt Reg)
-      (rn Reg))
-
-    ;; A memory fence.  This must provide ordering to ensure that, at a minimum, neither loads
-    ;; nor stores may move forwards or backwards across the fence.  Currently emitted as "dmb
-    ;; ish".  This instruction is sequentially consistent.
-    (Fence)
-
-    ;; FPU move. Note that this is distinct from a vector-register
-    ;; move; moving just 64 bits seems to be significantly faster.
-    (FpuMove64
-      (rd WritableReg)
-      (rn Reg))
-
-    ;; Vector register move.
-    (FpuMove128
-      (rd WritableReg)
-      (rn Reg))
-
-    ;; Move to scalar from a vector element.
-    (FpuMoveFromVec
-      (rd WritableReg)
-      (rn Reg)
-      (idx u8)
-      (size VectorSize))
-
-    ;; Zero-extend a SIMD & FP scalar to the full width of a vector register.
-    ;; 16-bit scalars require half-precision floating-point support (FEAT_FP16).
-    (FpuExtend
-      (rd WritableReg)
-      (rn Reg)
-      (size ScalarSize))
-
-    ;; 1-op FPU instruction.
-    (FpuRR
-      (fpu_op FPUOp1)
-      (rd WritableReg)
-      (rn Reg))
-
-    ;; 2-op FPU instruction.
-    (FpuRRR
-      (fpu_op FPUOp2)
-      (rd WritableReg)
-      (rn Reg)
-      (rm Reg))
-
-    (FpuRRI
-      (fpu_op FPUOpRI)
-      (rd WritableReg)
-      (rn Reg))
-
-    ;; 3-op FPU instruction.
-    (FpuRRRR
-      (fpu_op FPUOp3)
-      (rd WritableReg)
-      (rn Reg)
-      (rm Reg)
-      (ra Reg))
-
-    ;; FPU comparison, single-precision (32 bit).
-    (FpuCmp32
-      (rn Reg)
-      (rm Reg))
-
-    ;; FPU comparison, double-precision (64 bit).
-    (FpuCmp64
-      (rn Reg)
-      (rm Reg))
-
-    ;; Floating-point load, single-precision (32 bit).
-    (FpuLoad32
-      (rd WritableReg)
-      (mem AMode)
-      (flags MemFlags))
-
-    ;; Floating-point store, single-precision (32 bit).
-    (FpuStore32
-      (rd Reg)
-      (mem AMode)
-      (flags MemFlags))
-
-    ;; Floating-point load, double-precision (64 bit).
-    (FpuLoad64
-      (rd WritableReg)
-      (mem AMode)
-      (flags MemFlags))
-
-    ;; Floating-point store, double-precision (64 bit).
-    (FpuStore64
-      (rd Reg)
-      (mem AMode)
-      (flags MemFlags))
-
-    ;; Floating-point/vector load, 128 bit.
-    (FpuLoad128
-      (rd WritableReg)
-      (mem AMode)
-      (flags MemFlags))
-
-    ;; Floating-point/vector store, 128 bit.
-    (FpuStore128
-      (rd Reg)
-      (mem AMode)
-      (flags MemFlags))
-
-    ;; A load of a pair of floating-point registers, double precision (64-bit).
-    (FpuLoadP64
-      (rt WritableReg)
-      (rt2 WritableReg)
-      (mem PairAMode)
-      (flags MemFlags))
-
-    ;; A store of a pair of floating-point registers, double precision (64-bit).
-    (FpuStoreP64
-      (rt Reg)
-      (rt2 Reg)
-      (mem PairAMode)
-      (flags MemFlags))
-
-    ;; A load of a pair of floating-point registers, 128-bit.
-    (FpuLoadP128
-      (rt WritableReg)
-      (rt2 WritableReg)
-      (mem PairAMode)
-      (flags MemFlags))
-
-    ;; A store of a pair of floating-point registers, 128-bit.
-    (FpuStoreP128
-      (rt Reg)
-      (rt2 Reg)
-      (mem PairAMode)
-      (flags MemFlags))
-
-    (LoadFpuConst64
-      (rd WritableReg)
-      (const_data u64))
-
-    (LoadFpuConst128
-      (rd WritableReg)
-      (const_data u128))
-
-    ;; Conversion: FP -> integer.
-    (FpuToInt
-      (op FpuToIntOp)
-      (rd WritableReg)
-      (rn Reg))
-
-    ;; Conversion: integer -> FP.
-    (IntToFpu
-      (op IntToFpuOp)
-      (rd WritableReg)
-      (rn Reg))
-
-    ;; FP conditional select, 32 bit.
-    (FpuCSel32
-      (rd WritableReg)
-      (rn Reg)
-      (rm Reg)
-      (cond Cond))
-
-    ;; FP conditional select, 64 bit.
-    (FpuCSel64
-      (rd WritableReg)
-      (rn Reg)
-      (rm Reg)
-      (cond Cond))
-
-    ;; Round to integer.
-    (FpuRound
-      (op FpuRoundMode)
-      (rd WritableReg)
-      (rn Reg))
-
-    ;; Move from a GPR to a vector register.  The scalar value is parked in the lowest lane
-    ;; of the destination, and all other lanes are zeroed out.  Currently only 32- and 64-bit
-    ;; transactions are supported.
-    (MovToFpu
-      (rd WritableReg)
-      (rn Reg)
-      (size ScalarSize))
-
-    ;; Loads a floating-point immediate.
-    (FpuMoveFPImm
-      (rd WritableReg)
-      (imm ASIMDFPModImm)
-      (size ScalarSize))
-
-    ;; Move to a vector element from a GPR.
-    (MovToVec
-      (rd WritableReg)
-      (rn Reg)
-      (idx u8)
-      (size VectorSize))
-
-    ;; Unsigned move from a vector element to a GPR.
-    (MovFromVec
-      (rd WritableReg)
-      (rn Reg)
-      (idx u8)
-      (size VectorSize))
-
-    ;; Signed move from a vector element to a GPR.
-    (MovFromVecSigned
-      (rd WritableReg)
-      (rn Reg)
-      (idx u8)
-      (size VectorSize)
-      (scalar_size OperandSize))
-
-    ;; Duplicate general-purpose register to vector.
-    (VecDup
-      (rd WritableReg)
-      (rn Reg)
-      (size VectorSize))
-
-    ;; Duplicate scalar to vector.
-    (VecDupFromFpu
-      (rd WritableReg)
-      (rn Reg)
-      (size VectorSize))
-
-    ;; Duplicate FP immediate to vector.
-    (VecDupFPImm
-      (rd WritableReg)
-      (imm ASIMDFPModImm)
-      (size VectorSize))
-
-    ;; Duplicate immediate to vector.
-    (VecDupImm
-      (rd WritableReg)
-      (imm ASIMDMovModImm)
-      (invert bool)
-      (size VectorSize))
-
-    ;; Vector extend.
-    (VecExtend
-      (t VecExtendOp)
-      (rd WritableReg)
-      (rn Reg)
-      (high_half bool))
-
-    ;; Move vector element to another vector element.
-    (VecMovElement
-      (rd WritableReg)
-      (rn Reg)
-      (dest_idx u8)
-      (src_idx u8)
-      (size VectorSize))
-
-    ;; Vector widening operation.
-    (VecRRLong
-      (op VecRRLongOp)
-      (rd WritableReg)
-      (rn Reg)
-      (high_half bool))
-
-    ;; Vector narrowing operation.
-    (VecRRNarrow
-      (op VecRRNarrowOp)
-      (rd WritableReg)
-      (rn Reg)
-      (high_half bool))
-
-    ;; 1-operand vector instruction that operates on a pair of elements.
-    (VecRRPair
-      (op VecPairOp)
-      (rd WritableReg)
-      (rn Reg))
-
-    ;; 2-operand vector instruction that produces a result with twice the
-    ;; lane width and half the number of lanes.
-    (VecRRRLong
-      (alu_op VecRRRLongOp)
-      (rd WritableReg)
-      (rn Reg)
-      (rm Reg)
-      (high_half bool))
-
-    ;; 1-operand vector instruction that extends elements of the input
-    ;; register and operates on a pair of elements. The output lane width
-    ;; is double that of the input.
-    (VecRRPairLong
-      (op VecRRPairLongOp)
-      (rd WritableReg)
-      (rn Reg))
-
-    ;; A vector ALU op.
-    (VecRRR
-      (alu_op VecALUOp)
-      (rd WritableReg)
-      (rn Reg)
-      (rm Reg)
-      (size VectorSize))
-
-    ;; Vector two register miscellaneous instruction.
-    (VecMisc
-      (op VecMisc2)
-      (rd WritableReg)
-      (rn Reg)
-      (size VectorSize))
-
-    ;; Vector instruction across lanes.
-    (VecLanes
-      (op VecLanesOp)
-      (rd WritableReg)
-      (rn Reg)
-      (size VectorSize))
-
-    ;; Vector shift by immediate Shift Left (immediate), Unsigned Shift Right (immediate)
-    ;; Signed Shift Right (immediate).  These are somewhat unusual in that, for right shifts,
-    ;; the allowed range of `imm` values is 1 to lane-size-in-bits, inclusive.  A zero
-    ;; right-shift cannot be encoded.  Left shifts are "normal", though, having valid `imm`
-    ;; values from 0 to lane-size-in-bits - 1 inclusive.
-    (VecShiftImm
-      (op VecShiftImmOp)
-      (rd WritableReg)
-      (rn Reg)
-      (size VectorSize)
-      (imm u8))
-
-    ;; Vector extract - create a new vector, being the concatenation of the lowest `imm4` bytes
-    ;; of `rm` followed by the uppermost `16 - imm4` bytes of `rn`.
-    (VecExtract
-      (rd WritableReg)
-      (rn Reg)
-      (rm Reg)
-      (imm4 u8))
-
-    ;; Table vector lookup - single register table. The table consists of 8-bit elements and is
-    ;; stored in `rn`, while `rm` contains 8-bit element indices. `is_extension` specifies whether
-    ;; to emit a TBX or a TBL instruction, i.e. whether to leave the elements in the destination
-    ;; vector that correspond to out-of-range indices (greater than 15) unmodified or to set them
-    ;; to 0.
-    (VecTbl
-      (rd WritableReg)
-      (rn Reg)
-      (rm Reg)
-      (is_extension bool))
-
-    ;; Table vector lookup - two register table. The table consists of 8-bit elements and is
-    ;; stored in `rn` and `rn2`, while `rm` contains 8-bit element indices. `is_extension`
-    ;; specifies whether to emit a TBX or a TBL instruction, i.e. whether to leave the elements in
-    ;; the destination vector that correspond to out-of-range indices (greater than 31) unmodified
-    ;; or to set them to 0. The table registers `rn` and `rn2` must have consecutive numbers
-    ;; modulo 32, that is v31 and v0 (in that order) are consecutive registers.
-    (VecTbl2
-      (rd WritableReg)
-      (rn Reg)
-      (rn2 Reg)
-      (rm Reg)
-      (is_extension bool))
-
-    ;; Load an element and replicate to all lanes of a vector.
-    (VecLoadReplicate
-      (rd WritableReg)
-      (rn Reg)
-      (size VectorSize))
-
-    ;; Vector conditional select, 128 bit.  A synthetic instruction, which generates a 4-insn
-    ;; control-flow diamond.
-    (VecCSel
-      (rd WritableReg)
-      (rn Reg)
-      (rm Reg)
-      (cond Cond))
-
-    ;; Move to the NZCV flags (actually a `MSR NZCV, Xn` insn).
-    (MovToNZCV
-      (rn Reg))
-
-    ;; Move from the NZCV flags (actually a `MRS Xn, NZCV` insn).
-    (MovFromNZCV
-      (rd WritableReg))
-
-    ;; A machine call instruction. N.B.: this allows only a +/- 128MB offset (it uses a relocation
-    ;; of type `Reloc::Arm64Call`); if the destination distance is not `RelocDistance::Near`, the
-    ;; code should use a `LoadExtName` / `CallInd` sequence instead, allowing an arbitrary 64-bit
-    ;; target.
-    (Call
-      (info BoxCallInfo))
-
-    ;; A machine indirect-call instruction.
-    (CallInd
-      (info BoxCallIndInfo))
-
-    ;; ---- branches (exactly one must appear at end of BB) ----
-
-    ;; A machine return instruction.
-    (Ret)
-
-    ;; A placeholder instruction, generating no code, meaning that a function epilogue must be
-    ;; inserted there.
-    (EpiloguePlaceholder)
-
-    ;; An unconditional branch.
-    (Jump
-      (dest BranchTarget))
-
-    ;; A conditional branch. Contains two targets; at emission time, both are emitted, but
-    ;; the MachBuffer knows to truncate the trailing branch if fallthrough. We optimize the
-    ;; choice of taken/not_taken (inverting the branch polarity as needed) based on the
-    ;; fallthrough at the time of lowering.
-    (CondBr
-      (taken BranchTarget)
-      (not_taken BranchTarget)
-      (kind CondBrKind))
-
-    ;; A conditional trap: execute a `udf` if the condition is true. This is
-    ;; one VCode instruction because it uses embedded control flow; it is
-    ;; logically a single-in, single-out region, but needs to appear as one
-    ;; unit to the register allocator.
-    ;;
-    ;; The `CondBrKind` gives the conditional-branch condition that will
-    ;; *execute* the embedded `Inst`. (In the emitted code, we use the inverse
-    ;; of this condition in a branch that skips the trap instruction.)
-    (TrapIf
-      (kind CondBrKind)
-      (trap_code TrapCode))
-
-    ;; An indirect branch through a register, augmented with set of all
-    ;; possible successors.
-    (IndirectBr
-      (rn Reg)
-      (targets VecMachLabel))
-
-    ;; A "break" instruction, used for e.g. traps and debug breakpoints.
-    (Brk)
-
-    ;; An instruction guaranteed to always be undefined and to trigger an illegal instruction at
-    ;; runtime.
-    (Udf
-      (trap_code TrapCode))
-
-    ;; Compute the address (using a PC-relative offset) of a memory location, using the `ADR`
-    ;; instruction. Note that we take a simple offset, not a `MemLabel`, here, because `Adr` is
-    ;; only used for now in fixed lowering sequences with hardcoded offsets. In the future we may
-    ;; need full `MemLabel` support.
-    (Adr
-      (rd WritableReg)
-      ;; Offset in range -2^20 .. 2^20.
-      (off i32))
-
-    ;; Raw 32-bit word, used for inline constants and jump-table entries.
-    (Word4
-      (data u32))
-
-    ;; Raw 64-bit word, used for inline constants.
-    (Word8
-      (data u64))
-
-    ;; Jump-table sequence, as one compound instruction (see note in lower_inst.rs for rationale).
-    (JTSequence
-      (info BoxJTSequenceInfo)
-      (ridx Reg)
-      (rtmp1 WritableReg)
-      (rtmp2 WritableReg))
-
-    ;; Load an inline symbol reference.
-    (LoadExtName
-      (rd WritableReg)
-      (name BoxExternalName)
-      (offset i64))
-
-    ;; Load address referenced by `mem` into `rd`.
-    (LoadAddr
-      (rd WritableReg)
-      (mem AMode))
-
-    ;; Marker, no-op in generated code: SP "virtual offset" is adjusted. This
-    ;; controls how AMode::NominalSPOffset args are lowered.
-    (VirtualSPOffsetAdj
-      (offset i64))
-
-    ;; Meta-insn, no-op in generated code: emit constant/branch veneer island
-    ;; at this point (with a guard jump around it) if less than the needed
-    ;; space is available before the next branch deadline. See the `MachBuffer`
-    ;; implementation in `machinst/buffer.rs` for the overall algorithm. In
-    ;; brief, we retain a set of "pending/unresolved label references" from
-    ;; branches as we scan forward through instructions to emit machine code;
-    ;; if we notice we're about to go out of range on an unresolved reference,
-    ;; we stop, emit a bunch of "veneers" (branches in a form that has a longer
-    ;; range, e.g. a 26-bit-offset unconditional jump), and point the original
-    ;; label references to those. This is an "island" because it comes in the
-    ;; middle of the code.
-    ;;
-    ;; This meta-instruction is a necessary part of the logic that determines
-    ;; where to place islands. Ordinarily, we want to place them between basic
-    ;; blocks, so we compute the worst-case size of each block, and emit the
-    ;; island before starting a block if we would exceed a deadline before the
-    ;; end of the block. However, some sequences (such as an inline jumptable)
-    ;; are variable-length and not accounted for by this logic; so these
-    ;; lowered sequences include an `EmitIsland` to trigger island generation
-    ;; where necessary.
-    (EmitIsland
-      ;; The needed space before the next deadline.
-      (needed_space CodeOffset))
-
-    ;; A call to the `ElfTlsGetAddr` libcall. Returns address of TLS symbol in x0.
-    (ElfTlsGetAddr
-      (symbol ExternalName))
-
-    ;; A definition of a value label.
-    (ValueLabelMarker
-      (reg Reg)
-      (label ValueLabel))
-
-    ;; An unwind pseudo-instruction.
-    (Unwind
-      (inst UnwindInst))
-))
-
-;; An ALU operation. This can be paired with several instruction formats
-;; below (see `Inst`) in any combination.
-(type ALUOp
-  (enum
-    (Add)
-    (Sub)
-    (Orr)
-    (OrrNot)
-    (And)
-    (AndS)
-    (AndNot)
-    ;; XOR (AArch64 calls this "EOR")
-    (Eor)
-    ;; XNOR (AArch64 calls this "EOR-NOT")
-    (EorNot)
-    ;; Add, setting flags
-    (AddS)
-    ;; Sub, setting flags
-    (SubS)
-    ;; Signed multiply, high-word result
-    (SMulH)
-    ;; Unsigned multiply, high-word result
-    (UMulH)
-    (SDiv)
-    (UDiv)
-    (RotR)
-    (Lsr)
-    (Asr)
-    (Lsl)
-    ;; Add with carry
-    (Adc)
-    ;; Add with carry, settings flags
-    (AdcS)
-    ;; Subtract with carry
-    (Sbc)
-    ;; Subtract with carry, settings flags
-    (SbcS)
-))
-
-;; An ALU operation with three arguments.
-(type ALUOp3
-  (enum
-    ;; Multiply-add
-    (MAdd32)
-    ;; Multiply-add
-    (MAdd64)
-    ;; Multiply-sub
-    (MSub32)
-    ;; Multiply-sub
-    (MSub64)
-))
-
-(type UImm5 (primitive UImm5))
-(type Imm12 (primitive Imm12))
-(type ImmLogic (primitive ImmLogic))
-(type ImmShift (primitive ImmShift))
-(type ShiftOpAndAmt (primitive ShiftOpAndAmt))
-(type MoveWideConst (primitive MoveWideConst))
-(type NZCV (primitive NZCV))
-(type ASIMDFPModImm (primitive ASIMDFPModImm))
-(type ASIMDMovModImm (primitive ASIMDMovModImm))
-
-(type BoxCallInfo (primitive BoxCallInfo))
-(type BoxCallIndInfo (primitive BoxCallIndInfo))
-(type CondBrKind (primitive CondBrKind))
-(type BranchTarget (primitive BranchTarget))
-(type BoxJTSequenceInfo (primitive BoxJTSequenceInfo))
-(type CodeOffset (primitive CodeOffset))
-
-(type ExtendOp extern
-  (enum
-    (UXTB)
-    (UXTH)
-    (UXTW)
-    (UXTX)
-    (SXTB)
-    (SXTH)
-    (SXTW)
-    (SXTX)
-))
-
-;; An operation on the bits of a register. This can be paired with several instruction formats
-;; below (see `Inst`) in any combination.
-(type BitOp
-  (enum
-    ;; Bit reverse
-    (RBit)
-    (Clz)
-    (Cls)
-))
-
-(type AMode extern (enum))
-(type PairAMode extern (enum))
-(type FPUOpRI extern (enum))
-
-(type OperandSize extern
-      (enum Size32
-            Size64))
-
-;; Helper for calculating the `OperandSize` corresponding to a type
-(decl operand_size (Type) OperandSize)
-(rule (operand_size (fits_in_32 _ty)) (OperandSize.Size32))
-(rule (operand_size (fits_in_64 _ty)) (OperandSize.Size64))
-
-(type ScalarSize extern
-      (enum Size8
-            Size16
-            Size32
-            Size64
-            Size128))
-
-(type Cond extern
-  (enum
-    (Eq)
-    (Ne)
-    (Hs)
-    (Lo)
-    (Mi)
-    (Pl)
-    (Vs)
-    (Vc)
-    (Hi)
-    (Ls)
-    (Ge)
-    (Lt)
-    (Gt)
-    (Le)
-    (Al)
-    (Nv)
-))
-
-(type VectorSize extern
-  (enum
-    (Size8x8)
-    (Size8x16)
-    (Size16x4)
-    (Size16x8)
-    (Size32x2)
-    (Size32x4)
-    (Size64x2)
-))
-
-;; Helper for calculating the `VectorSize` corresponding to a type
-(decl vector_size (Type) VectorSize)
-(rule (vector_size (multi_lane 8 16)) (VectorSize.Size8x16))
-(rule (vector_size (multi_lane 16 8)) (VectorSize.Size16x8))
-(rule (vector_size (multi_lane 32 4)) (VectorSize.Size32x4))
-(rule (vector_size (multi_lane 64 2)) (VectorSize.Size64x2))
-
-;; A floating-point unit (FPU) operation with one arg.
-(type FPUOp1
-  (enum
-    (Abs32)
-    (Abs64)
-    (Neg32)
-    (Neg64)
-    (Sqrt32)
-    (Sqrt64)
-    (Cvt32To64)
-    (Cvt64To32)
-))
-
-;; A floating-point unit (FPU) operation with two args.
-(type FPUOp2
-  (enum
-    (Add32)
-    (Add64)
-    (Sub32)
-    (Sub64)
-    (Mul32)
-    (Mul64)
-    (Div32)
-    (Div64)
-    (Max32)
-    (Max64)
-    (Min32)
-    (Min64)
-    ;; Signed saturating add
-    (Sqadd64)
-    ;; Unsigned saturating add
-    (Uqadd64)
-    ;; Signed saturating subtract
-    (Sqsub64)
-    ;; Unsigned saturating subtract
-    (Uqsub64)
-))
-
-;; A floating-point unit (FPU) operation with three args.
-(type FPUOp3
-  (enum
-    (MAdd32)
-    (MAdd64)
-))
-
-;; A conversion from an FP to an integer value.
-(type FpuToIntOp
-  (enum
-    (F32ToU32)
-    (F32ToI32)
-    (F32ToU64)
-    (F32ToI64)
-    (F64ToU32)
-    (F64ToI32)
-    (F64ToU64)
-    (F64ToI64)
-))
-
-;; A conversion from an integer to an FP value.
-(type IntToFpuOp
-  (enum
-    (U32ToF32)
-    (I32ToF32)
-    (U32ToF64)
-    (I32ToF64)
-    (U64ToF32)
-    (I64ToF32)
-    (U64ToF64)
-    (I64ToF64)
-))
-
-;; Modes for FP rounding ops: round down (floor) or up (ceil), or toward zero (trunc), or to
-;; nearest, and for 32- or 64-bit FP values.
-(type FpuRoundMode
-  (enum
-    (Minus32)
-    (Minus64)
-    (Plus32)
-    (Plus64)
-    (Zero32)
-    (Zero64)
-    (Nearest32)
-    (Nearest64)
-))
-
-;; Type of vector element extensions.
-(type VecExtendOp
-  (enum
-    ;; Signed extension of 8-bit elements
-    (Sxtl8)
-    ;; Signed extension of 16-bit elements
-    (Sxtl16)
-    ;; Signed extension of 32-bit elements
-    (Sxtl32)
-    ;; Unsigned extension of 8-bit elements
-    (Uxtl8)
-    ;; Unsigned extension of 16-bit elements
-    (Uxtl16)
-    ;; Unsigned extension of 32-bit elements
-    (Uxtl32)
-))
-
-;; A vector ALU operation.
-(type VecALUOp
-  (enum
-    ;; Signed saturating add
-    (Sqadd)
-    ;; Unsigned saturating add
-    (Uqadd)
-    ;; Signed saturating subtract
-    (Sqsub)
-    ;; Unsigned saturating subtract
-    (Uqsub)
-    ;; Compare bitwise equal
-    (Cmeq)
-    ;; Compare signed greater than or equal
-    (Cmge)
-    ;; Compare signed greater than
-    (Cmgt)
-    ;; Compare unsigned higher
-    (Cmhs)
-    ;; Compare unsigned higher or same
-    (Cmhi)
-    ;; Floating-point compare equal
-    (Fcmeq)
-    ;; Floating-point compare greater than
-    (Fcmgt)
-    ;; Floating-point compare greater than or equal
-    (Fcmge)
-    ;; Bitwise and
-    (And)
-    ;; Bitwise bit clear
-    (Bic)
-    ;; Bitwise inclusive or
-    (Orr)
-    ;; Bitwise exclusive or
-    (Eor)
-    ;; Bitwise select
-    (Bsl)
-    ;; Unsigned maximum pairwise
-    (Umaxp)
-    ;; Add
-    (Add)
-    ;; Subtract
-    (Sub)
-    ;; Multiply
-    (Mul)
-    ;; Signed shift left
-    (Sshl)
-    ;; Unsigned shift left
-    (Ushl)
-    ;; Unsigned minimum
-    (Umin)
-    ;; Signed minimum
-    (Smin)
-    ;; Unsigned maximum
-    (Umax)
-    ;; Signed maximum
-    (Smax)
-    ;; Unsigned rounding halving add
-    (Urhadd)
-    ;; Floating-point add
-    (Fadd)
-    ;; Floating-point subtract
-    (Fsub)
-    ;; Floating-point divide
-    (Fdiv)
-    ;; Floating-point maximum
-    (Fmax)
-    ;; Floating-point minimum
-    (Fmin)
-    ;; Floating-point multiply
-    (Fmul)
-    ;; Add pairwise
-    (Addp)
-    ;; Zip vectors (primary) [meaning, high halves]
-    (Zip1)
-    ;; Signed saturating rounding doubling multiply returning high half
-    (Sqrdmulh)
-))
-
-;; A Vector miscellaneous operation with two registers.
-(type VecMisc2
-  (enum
-    ;; Bitwise NOT
-    (Not)
-    ;; Negate
-    (Neg)
-    ;; Absolute value
-    (Abs)
-    ;; Floating-point absolute value
-    (Fabs)
-    ;; Floating-point negate
-    (Fneg)
-    ;; Floating-point square root
-    (Fsqrt)
-    ;; Reverse elements in 64-bit doublewords
-    (Rev64)
-    ;; Floating-point convert to signed integer, rounding toward zero
-    (Fcvtzs)
-    ;; Floating-point convert to unsigned integer, rounding toward zero
-    (Fcvtzu)
-    ;; Signed integer convert to floating-point
-    (Scvtf)
-    ;; Unsigned integer convert to floating-point
-    (Ucvtf)
-    ;; Floating point round to integral, rounding towards nearest
-    (Frintn)
-    ;; Floating point round to integral, rounding towards zero
-    (Frintz)
-    ;; Floating point round to integral, rounding towards minus infinity
-    (Frintm)
-    ;; Floating point round to integral, rounding towards plus infinity
-    (Frintp)
-    ;; Population count per byte
-    (Cnt)
-    ;; Compare bitwise equal to 0
-    (Cmeq0)
-))
-
-;; A vector widening operation with one argument.
-(type VecRRLongOp
-  (enum
-    ;; Floating-point convert to higher precision long, 16-bit elements
-    (Fcvtl16)
-    ;; Floating-point convert to higher precision long, 32-bit elements
-    (Fcvtl32)
-    ;; Shift left long (by element size), 8-bit elements
-    (Shll8)
-    ;; Shift left long (by element size), 16-bit elements
-    (Shll16)
-    ;; Shift left long (by element size), 32-bit elements
-    (Shll32)
-))
-
-;; A vector narrowing operation with one argument.
-(type VecRRNarrowOp
-  (enum
-    ;; Extract narrow, 16-bit elements
-    (Xtn16)
-    ;; Extract narrow, 32-bit elements
-    (Xtn32)
-    ;; Extract narrow, 64-bit elements
-    (Xtn64)
-    ;; Signed saturating extract narrow, 16-bit elements
-    (Sqxtn16)
-    ;; Signed saturating extract narrow, 32-bit elements
-    (Sqxtn32)
-    ;; Signed saturating extract narrow, 64-bit elements
-    (Sqxtn64)
-    ;; Signed saturating extract unsigned narrow, 16-bit elements
-    (Sqxtun16)
-    ;; Signed saturating extract unsigned narrow, 32-bit elements
-    (Sqxtun32)
-    ;; Signed saturating extract unsigned narrow, 64-bit elements
-    (Sqxtun64)
-    ;; Unsigned saturating extract narrow, 16-bit elements
-    (Uqxtn16)
-    ;; Unsigned saturating extract narrow, 32-bit elements
-    (Uqxtn32)
-    ;; Unsigned saturating extract narrow, 64-bit elements
-    (Uqxtn64)
-    ;; Floating-point convert to lower precision narrow, 32-bit elements
-    (Fcvtn32)
-    ;; Floating-point convert to lower precision narrow, 64-bit elements
-    (Fcvtn64)
-))
-
-(type VecRRRLongOp
-  (enum
-    ;; Signed multiply long.
-    (Smull8)
-    (Smull16)
-    (Smull32)
-    ;; Unsigned multiply long.
-    (Umull8)
-    (Umull16)
-    (Umull32)
-    ;; Unsigned multiply add long
-    (Umlal8)
-    (Umlal16)
-    (Umlal32)
-))
-
-;; A vector operation on a pair of elements with one register.
-(type VecPairOp
-  (enum
-    ;; Add pair of elements
-    (Addp)
-))
-
-;; 1-operand vector instruction that extends elements of the input register
-;; and operates on a pair of elements.
-(type VecRRPairLongOp
-  (enum
-    ;; Sign extend and add pair of elements
-    (Saddlp8)
-    (Saddlp16)
-    ;; Unsigned extend and add pair of elements
-    (Uaddlp8)
-    (Uaddlp16)
-))
-
-;; An operation across the lanes of vectors.
-(type VecLanesOp
-  (enum
-    ;; Integer addition across a vector
-    (Addv)
-    ;; Unsigned minimum across a vector
-    (Uminv)
-))
-
-;; A shift-by-immediate operation on each lane of a vector.
-(type VecShiftImmOp
-  (enum
-    ;; Unsigned shift left
-    (Shl)
-    ;; Unsigned shift right
-    (Ushr)
-    ;; Signed shift right
-    (Sshr)
-))
-
-;; Atomic read-modify-write operations with acquire-release semantics
-(type AtomicRMWOp
-  (enum
-    (Add)
-    (Clr)
-    (Eor)
-    (Set)
-    (Smax)
-    (Smin)
-    (Umax)
-    (Umin)
-))
-
-;; Extractor helpers for various immmediate constants ;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl move_wide_const_from_u64 (MoveWideConst) u64)
-(extern extractor move_wide_const_from_u64 move_wide_const_from_u64)
-
-(decl move_wide_const_from_negated_u64 (MoveWideConst) u64)
-(extern extractor move_wide_const_from_negated_u64 move_wide_const_from_negated_u64)
-
-(decl imm_logic_from_u64 (Type ImmLogic) u64)
-(extern extractor imm_logic_from_u64 imm_logic_from_u64 (in out))
-
-(decl imm_logic_from_imm64 (Type ImmLogic) Imm64)
-(extern extractor imm_logic_from_imm64 imm_logic_from_imm64 (in out))
-
-(decl imm_shift_from_imm64 (Type ImmShift) Imm64)
-(extern extractor imm_shift_from_imm64 imm_shift_from_imm64 (in out))
-
-(decl imm_shift_from_u8 (u8) ImmShift)
-(extern constructor imm_shift_from_u8 imm_shift_from_u8)
-
-(decl imm12_from_u64 (Imm12) u64)
-(extern extractor imm12_from_u64 imm12_from_u64)
-
-(decl u8_into_uimm5 (u8) UImm5)
-(extern constructor u8_into_uimm5 u8_into_uimm5)
-
-(decl u8_into_imm12 (u8) Imm12)
-(extern constructor u8_into_imm12 u8_into_imm12)
-
-(decl u64_into_imm_logic (Type u64) ImmLogic)
-(extern constructor u64_into_imm_logic u64_into_imm_logic)
-
-(decl imm12_from_negated_u64 (Imm12) u64)
-(extern extractor imm12_from_negated_u64 imm12_from_negated_u64)
-
-(decl lshl_from_imm64 (Type ShiftOpAndAmt) Imm64)
-(extern extractor lshl_from_imm64 lshl_from_imm64 (in out))
-
-(decl integral_ty (Type) Type)
-(extern extractor integral_ty integral_ty)
-
-;; Helper to go directly from a `Value`, when it's an `iconst`, to an `Imm12`.
-(decl imm12_from_value (Imm12) Value)
-(extractor
-  (imm12_from_value n)
-  (def_inst (iconst (u64_from_imm64 (imm12_from_u64 n)))))
-
-;; Same as `imm12_from_value`, but tries negating the constant value.
-(decl imm12_from_negated_value (Imm12) Value)
-(extractor
-  (imm12_from_negated_value n)
-  (def_inst (iconst (u64_from_imm64 (imm12_from_negated_u64 n)))))
-
-;; Helper type to represent a value and an extend operation fused together.
-(type ExtendedValue extern (enum))
-(decl extended_value_from_value (ExtendedValue) Value)
-(extern extractor extended_value_from_value extended_value_from_value)
-
-;; Constructors used to poke at the fields of an `ExtendedValue`.
-(decl put_extended_in_reg (ExtendedValue) Reg)
-(extern constructor put_extended_in_reg put_extended_in_reg)
-(decl get_extended_op (ExtendedValue) ExtendOp)
-(extern constructor get_extended_op get_extended_op)
-
-(decl nzcv (bool bool bool bool) NZCV)
-(extern constructor nzcv nzcv)
-
-(decl cond_br_zero (Reg) CondBrKind)
-(extern constructor cond_br_zero cond_br_zero)
-
-(decl cond_br_cond (Cond) CondBrKind)
-(extern constructor cond_br_cond cond_br_cond)
-
-;; Instruction creation helpers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Helper for creating the zero register.
-(decl zero_reg () Reg)
-(extern constructor zero_reg zero_reg)
-
-(decl writable_zero_reg () WritableReg)
-(extern constructor writable_zero_reg writable_zero_reg)
-
-;; Helper for emitting `MInst.MovZ` instructions.
-(decl movz (MoveWideConst OperandSize) Reg)
-(rule (movz imm size)
-      (let ((dst WritableReg (temp_writable_reg $I64))
-            (_ Unit (emit (MInst.MovZ dst imm size))))
-        dst))
-
-;; Helper for emitting `MInst.MovN` instructions.
-(decl movn (MoveWideConst OperandSize) Reg)
-(rule (movn imm size)
-      (let ((dst WritableReg (temp_writable_reg $I64))
-            (_ Unit (emit (MInst.MovN dst imm size))))
-        dst))
-
-;; Helper for emitting `MInst.AluRRImmLogic` instructions.
-(decl alu_rr_imm_logic (ALUOp Type Reg ImmLogic) Reg)
-(rule (alu_rr_imm_logic op ty src imm)
-      (let ((dst WritableReg (temp_writable_reg $I64))
-            (_ Unit (emit (MInst.AluRRImmLogic op (operand_size ty) dst src imm))))
-        dst))
-
-;; Helper for emitting `MInst.AluRRImmShift` instructions.
-(decl alu_rr_imm_shift (ALUOp Type Reg ImmShift) Reg)
-(rule (alu_rr_imm_shift op ty src imm)
-      (let ((dst WritableReg (temp_writable_reg $I64))
-            (_ Unit (emit (MInst.AluRRImmShift op (operand_size ty) dst src imm))))
-        dst))
-
-;; Helper for emitting `MInst.AluRRR` instructions.
-(decl alu_rrr (ALUOp Type Reg Reg) Reg)
-(rule (alu_rrr op ty src1 src2)
-      (let ((dst WritableReg (temp_writable_reg $I64))
-            (_ Unit (emit (MInst.AluRRR op (operand_size ty) dst src1 src2))))
-        dst))
-
-;; Helper for emitting `MInst.VecRRR` instructions.
-(decl vec_rrr (VecALUOp Reg Reg VectorSize) Reg)
-(rule (vec_rrr op src1 src2 size)
-      (let ((dst WritableReg (temp_writable_reg $I8X16))
-            (_ Unit (emit (MInst.VecRRR op dst src1 src2 size))))
-        dst))
-
-;; Helper for emitting `MInst.VecLanes` instructions.
-(decl vec_lanes (VecLanesOp Reg VectorSize) Reg)
-(rule (vec_lanes op src size)
-      (let ((dst WritableReg (temp_writable_reg $I8X16))
-            (_ Unit (emit (MInst.VecLanes op dst src size))))
-        dst))
-
-;; Helper for emitting `MInst.VecDup` instructions.
-(decl vec_dup (Reg VectorSize) Reg)
-(rule (vec_dup src size)
-      (let ((dst WritableReg (temp_writable_reg $I8X16))
-            (_ Unit (emit (MInst.VecDup dst src size))))
-        dst))
-
-;; Helper for emitting `MInst.AluRRImm12` instructions.
-(decl alu_rr_imm12 (ALUOp Type Reg Imm12) Reg)
-(rule (alu_rr_imm12 op ty src imm)
-      (let ((dst WritableReg (temp_writable_reg $I64))
-            (_ Unit (emit (MInst.AluRRImm12 op (operand_size ty) dst src imm))))
-        dst))
-
-;; Helper for emitting `MInst.AluRRRShift` instructions.
-(decl alu_rrr_shift (ALUOp Type Reg Reg ShiftOpAndAmt) Reg)
-(rule (alu_rrr_shift op ty src1 src2 shift)
-      (let ((dst WritableReg (temp_writable_reg $I64))
-            (_ Unit (emit (MInst.AluRRRShift op (operand_size ty) dst src1 src2 shift))))
-        dst))
-
-;; Helper for emitting `MInst.AluRRRExtend` instructions.
-(decl alu_rrr_extend (ALUOp Type Reg Reg ExtendOp) Reg)
-(rule (alu_rrr_extend op ty src1 src2 extend)
-      (let ((dst WritableReg (temp_writable_reg $I64))
-            (_ Unit (emit (MInst.AluRRRExtend op (operand_size ty) dst src1 src2 extend))))
-        dst))
-
-;; Same as `alu_rrr_extend`, but takes an `ExtendedValue` packed "pair" instead
-;; of a `Reg` and an `ExtendOp`.
-(decl alu_rr_extend_reg (ALUOp Type Reg ExtendedValue) Reg)
-(rule (alu_rr_extend_reg op ty src1 extended_reg)
-      (let ((src2 Reg (put_extended_in_reg extended_reg))
-            (extend ExtendOp (get_extended_op extended_reg)))
-        (alu_rrr_extend op ty src1 src2 extend)))
-
-;; Helper for emitting `MInst.AluRRRR` instructions.
-(decl alu_rrrr (ALUOp3 Reg Reg Reg) Reg)
-(rule (alu_rrrr op src1 src2 src3)
-      (let ((dst WritableReg (temp_writable_reg $I64))
-            (_ Unit (emit (MInst.AluRRRR op dst src1 src2 src3))))
-        dst))
-
-;; Helper for emitting `MInst.BitRR` instructions.
-(decl bit_rr (BitOp Type Reg) Reg)
-(rule (bit_rr op ty src)
-      (let ((dst WritableReg (temp_writable_reg $I64))
-            (_ Unit (emit (MInst.BitRR op (operand_size ty) dst src))))
-        dst))
-
-;; Helper for emitting `adds` instructions.
-(decl add_with_flags_paired (Type Reg Reg) ProducesFlags)
-(rule (add_with_flags_paired ty src1 src2)
-      (let ((dst WritableReg (temp_writable_reg $I64)))
-        (ProducesFlags.ProducesFlagsReturnsResultWithConsumer
-         (MInst.AluRRR (ALUOp.AddS) (operand_size ty) dst src1 src2)
-         dst)))
-
-;; Helper for emitting `adc` instructions.
-(decl adc_paired (Type Reg Reg) ConsumesFlags)
-(rule (adc_paired ty src1 src2)
-      (let ((dst WritableReg (temp_writable_reg $I64)))
-        (ConsumesFlags.ConsumesFlagsReturnsResultWithProducer
-         (MInst.AluRRR (ALUOp.Adc) (operand_size ty) dst src1 src2)
-         dst)))
-
-;; Helper for emitting `subs` instructions.
-(decl sub_with_flags_paired (Type Reg Reg) ProducesFlags)
-(rule (sub_with_flags_paired ty src1 src2)
-      (let ((dst WritableReg (temp_writable_reg $I64)))
-        (ProducesFlags.ProducesFlagsReturnsResultWithConsumer
-         (MInst.AluRRR (ALUOp.SubS) (operand_size ty) dst src1 src2)
-         dst)))
-
-(decl cmp64_imm (Reg Imm12) ProducesFlags)
-(rule (cmp64_imm src1 src2)
-      (ProducesFlags.ProducesFlagsSideEffect
-       (MInst.AluRRImm12 (ALUOp.SubS) (OperandSize.Size64) (writable_zero_reg)
-        src1 src2)))
-
-;; Helper for emitting `sbc` instructions.
-(decl sbc_paired (Type Reg Reg) ConsumesFlags)
-(rule (sbc_paired ty src1 src2)
-      (let ((dst WritableReg (temp_writable_reg $I64)))
-        (ConsumesFlags.ConsumesFlagsReturnsResultWithProducer
-         (MInst.AluRRR (ALUOp.Sbc) (operand_size ty) dst src1 src2)
-         dst)))
-
-;; Helper for emitting `MInst.VecMisc` instructions.
-(decl vec_misc (VecMisc2 Reg VectorSize) Reg)
-(rule (vec_misc op src size)
-      (let ((dst WritableReg (temp_writable_reg $I8X16))
-            (_ Unit (emit (MInst.VecMisc op dst src size))))
-        dst))
-
-;; Helper for emitting `MInst.VecRRRLong` instructions.
-(decl vec_rrr_long (VecRRRLongOp Reg Reg bool) Reg)
-(rule (vec_rrr_long op src1 src2 high_half)
-      (let ((dst WritableReg (temp_writable_reg $I8X16))
-            (_ Unit (emit (MInst.VecRRRLong op dst src1 src2 high_half))))
-        dst))
-
-;; Helper for emitting `MInst.VecRRRLong` instructions, but for variants
-;; where the operation both reads and modifies the destination register.
-;;
-;; Currently this is only used for `VecRRRLongOp.Umlal*`
-(decl vec_rrrr_long (VecRRRLongOp Reg Reg Reg bool) Reg)
-(rule (vec_rrrr_long op src1 src2 src3 high_half)
-      (let ((dst WritableReg (temp_writable_reg $I8X16))
-            (_1 Unit (emit (MInst.FpuMove128 dst src1)))
-            (_2 Unit (emit (MInst.VecRRRLong op dst src2 src3 high_half))))
-        dst))
-
-;; Helper for emitting `MInst.VecRRNarrow` instructions.
-(decl vec_rr_narrow (VecRRNarrowOp Reg bool) Reg)
-(rule (vec_rr_narrow op src high_half)
-      (let ((dst WritableReg (temp_writable_reg $I8X16))
-            (_ Unit (emit (MInst.VecRRNarrow op dst src high_half))))
-        dst))
-
-;; Helper for emitting `MInst.VecRRLong` instructions.
-(decl vec_rr_long (VecRRLongOp Reg bool) Reg)
-(rule (vec_rr_long op src high_half)
-      (let ((dst WritableReg (temp_writable_reg $I8X16))
-            (_ Unit (emit (MInst.VecRRLong op dst src high_half))))
-        dst))
-
-;; Helper for emitting `MInst.MovToFpu` instructions.
-(decl mov_to_fpu (Reg ScalarSize) Reg)
-(rule (mov_to_fpu x size)
-      (let ((dst WritableReg (temp_writable_reg $I8X16))
-            (_ Unit (emit (MInst.MovToFpu dst x size))))
-        dst))
-
-;; Helper for emitting `MInst.MovToVec` instructions.
-(decl mov_to_vec (Reg Reg u8 VectorSize) Reg)
-(rule (mov_to_vec src1 src2 lane size)
-      (let ((dst WritableReg (temp_writable_reg $I8X16))
-            (_1 Unit (emit (MInst.FpuMove128 dst src1)))
-            (_2 Unit (emit (MInst.MovToVec dst src2 lane size))))
-        dst))
-
-;; Helper for emitting `MInst.MovFromVec` instructions.
-(decl mov_from_vec (Reg u8 VectorSize) Reg)
-(rule (mov_from_vec rn idx size)
-      (let ((dst WritableReg (temp_writable_reg $I64))
-            (_ Unit (emit (MInst.MovFromVec dst rn idx size))))
-        dst))
-
-;; Helper for emitting `MInst.MovFromVecSigned` instructions.
-(decl mov_from_vec_signed (Reg u8 VectorSize OperandSize) Reg)
-(rule (mov_from_vec_signed rn idx size scalar_size)
-      (let ((dst WritableReg (temp_writable_reg $I64))
-            (_ Unit (emit (MInst.MovFromVecSigned dst rn idx size scalar_size))))
-        dst))
-
-;; Helper for emitting `MInst.Extend` instructions.
-(decl extend (Reg bool u8 u8) Reg)
-(rule (extend rn signed from_bits to_bits)
-      (let ((dst WritableReg (temp_writable_reg $I64))
-            (_ Unit (emit (MInst.Extend dst rn signed from_bits to_bits))))
-        dst))
-
-;; Helper for emitting `MInst.LoadAcquire` instructions.
-(decl load_acquire (Type Reg) Reg)
-(rule (load_acquire ty addr)
-      (let ((dst WritableReg (temp_writable_reg $I64))
-            (_ Unit (emit (MInst.LoadAcquire ty dst addr))))
-        dst))
-
-;; Helper for generating a `tst` instruction.
-;;
-;; Produces a `ProducesFlags` rather than a register or emitted instruction
-;; which must be paired with `with_flags*` helpers.
-(decl tst_imm (Type Reg ImmLogic) ProducesFlags)
-(rule (tst_imm ty reg imm)
-      (ProducesFlags.ProducesFlagsSideEffect
-       (MInst.AluRRImmLogic (ALUOp.AndS)
-                            (operand_size ty)
-                            (writable_zero_reg)
-                            reg
-                            imm)))
-
-;; Helper for generating a `CSel` instruction.
-;;
-;; Note that this doesn't actually emit anything, instead it produces a
-;; `ConsumesFlags` instruction which must be consumed with `with_flags*`
-;; helpers.
-(decl csel (Cond Reg Reg) ConsumesFlags)
-(rule (csel cond if_true if_false)
-      (let ((dst WritableReg (temp_writable_reg $I64)))
-        (ConsumesFlags.ConsumesFlagsReturnsReg
-         (MInst.CSel dst cond if_true if_false)
-         dst)))
-
-;; Helpers for generating `add` instructions.
-
-(decl add (Type Reg Reg) Reg)
-(rule (add ty x y) (alu_rrr (ALUOp.Add) ty x y))
-
-(decl add_imm (Type Reg Imm12) Reg)
-(rule (add_imm ty x y) (alu_rr_imm12 (ALUOp.Add) ty x y))
-
-(decl add_extend (Type Reg ExtendedValue) Reg)
-(rule (add_extend ty x y) (alu_rr_extend_reg (ALUOp.Add) ty x y))
-
-(decl add_shift (Type Reg Reg ShiftOpAndAmt) Reg)
-(rule (add_shift ty x y z) (alu_rrr_shift (ALUOp.Add) ty x y z))
-
-(decl add_vec (Reg Reg VectorSize) Reg)
-(rule (add_vec x y size) (vec_rrr (VecALUOp.Add) x y size))
-
-;; Helpers for generating `sub` instructions.
-
-(decl sub (Type Reg Reg) Reg)
-(rule (sub ty x y) (alu_rrr (ALUOp.Sub) ty x y))
-
-(decl sub_imm (Type Reg Imm12) Reg)
-(rule (sub_imm ty x y) (alu_rr_imm12 (ALUOp.Sub) ty x y))
-
-(decl sub_extend (Type Reg ExtendedValue) Reg)
-(rule (sub_extend ty x y) (alu_rr_extend_reg (ALUOp.Sub) ty x y))
-
-(decl sub_shift (Type Reg Reg ShiftOpAndAmt) Reg)
-(rule (sub_shift ty x y z) (alu_rrr_shift (ALUOp.Sub) ty x y z))
-
-(decl sub_vec (Reg Reg VectorSize) Reg)
-(rule (sub_vec x y size) (vec_rrr (VecALUOp.Sub) x y size))
-
-;; Helpers for generating `madd` instructions.
-
-(decl madd (Type Reg Reg Reg) Reg)
-(rule (madd (fits_in_32 _ty) x y z) (madd32 x y z))
-(rule (madd $I64 x y z) (madd64 x y z))
-
-(decl madd32 (Reg Reg Reg) Reg)
-(rule (madd32 x y z) (alu_rrrr (ALUOp3.MAdd32) x y z))
-
-(decl madd64 (Reg Reg Reg) Reg)
-(rule (madd64 x y z) (alu_rrrr (ALUOp3.MAdd64) x y z))
-
-;; Helpers for generating `msub` instructions.
-
-(decl msub64 (Reg Reg Reg) Reg)
-(rule (msub64 x y z) (alu_rrrr (ALUOp3.MSub64) x y z))
-
-;; Helper for generating `uqadd` instructions.
-(decl uqadd (Reg Reg VectorSize) Reg)
-(rule (uqadd x y size) (vec_rrr (VecALUOp.Uqadd) x y size))
-
-;; Helper for generating `sqadd` instructions.
-(decl sqadd (Reg Reg VectorSize) Reg)
-(rule (sqadd x y size) (vec_rrr (VecALUOp.Sqadd) x y size))
-
-;; Helper for generating `uqsub` instructions.
-(decl uqsub (Reg Reg VectorSize) Reg)
-(rule (uqsub x y size) (vec_rrr (VecALUOp.Uqsub) x y size))
-
-;; Helper for generating `sqsub` instructions.
-(decl sqsub (Reg Reg VectorSize) Reg)
-(rule (sqsub x y size) (vec_rrr (VecALUOp.Sqsub) x y size))
-
-;; Helper for generating `umulh` instructions.
-(decl umulh (Type Reg Reg) Reg)
-(rule (umulh ty x y) (alu_rrr (ALUOp.UMulH) ty x y))
-
-;; Helper for generating `smulh` instructions.
-(decl smulh (Type Reg Reg) Reg)
-(rule (smulh ty x y) (alu_rrr (ALUOp.SMulH) ty x y))
-
-;; Helper for generating `mul` instructions.
-(decl mul (Reg Reg VectorSize) Reg)
-(rule (mul x y size) (vec_rrr (VecALUOp.Mul) x y size))
-
-;; Helper for generating `neg` instructions.
-(decl neg (Reg VectorSize) Reg)
-(rule (neg x size) (vec_misc (VecMisc2.Neg) x size))
-
-;; Helper for generating `rev64` instructions.
-(decl rev64 (Reg VectorSize) Reg)
-(rule (rev64 x size) (vec_misc (VecMisc2.Rev64) x size))
-
-;; Helper for generating `xtn64` instructions.
-(decl xtn64 (Reg bool) Reg)
-(rule (xtn64 x high_half) (vec_rr_narrow (VecRRNarrowOp.Xtn64) x high_half))
-
-;; Helper for generating `addp` instructions.
-(decl addp (Reg Reg VectorSize) Reg)
-(rule (addp x y size) (vec_rrr (VecALUOp.Addp) x y size))
-
-;; Helper for generating `addv` instructions.
-(decl addv (Reg VectorSize) Reg)
-(rule (addv x size) (vec_lanes (VecLanesOp.Addv) x size))
-
-;; Helper for generating `shll32` instructions.
-(decl shll32 (Reg bool) Reg)
-(rule (shll32 x high_half) (vec_rr_long (VecRRLongOp.Shll32) x high_half))
-
-;; Helper for generating `umlal32` instructions.
-(decl umlal32 (Reg Reg Reg bool) Reg)
-(rule (umlal32 x y z high_half) (vec_rrrr_long (VecRRRLongOp.Umlal32) x y z high_half))
-
-;; Helper for generating `smull8` instructions.
-(decl smull8 (Reg Reg bool) Reg)
-(rule (smull8 x y high_half) (vec_rrr_long (VecRRRLongOp.Smull8) x y high_half))
-
-;; Helper for generating `umull8` instructions.
-(decl umull8 (Reg Reg bool) Reg)
-(rule (umull8 x y high_half) (vec_rrr_long (VecRRRLongOp.Umull8) x y high_half))
-
-;; Helper for generating `smull16` instructions.
-(decl smull16 (Reg Reg bool) Reg)
-(rule (smull16 x y high_half) (vec_rrr_long (VecRRRLongOp.Smull16) x y high_half))
-
-;; Helper for generating `umull16` instructions.
-(decl umull16 (Reg Reg bool) Reg)
-(rule (umull16 x y high_half) (vec_rrr_long (VecRRRLongOp.Umull16) x y high_half))
-
-;; Helper for generating `smull32` instructions.
-(decl smull32 (Reg Reg bool) Reg)
-(rule (smull32 x y high_half) (vec_rrr_long (VecRRRLongOp.Smull32) x y high_half))
-
-;; Helper for generating `umull32` instructions.
-(decl umull32 (Reg Reg bool) Reg)
-(rule (umull32 x y high_half) (vec_rrr_long (VecRRRLongOp.Umull32) x y high_half))
-
-;; Helper for generating `asr` instructions.
-(decl asr (Type Reg Reg) Reg)
-(rule (asr ty x y) (alu_rrr (ALUOp.Asr) ty x y))
-
-(decl asr_imm (Type Reg ImmShift) Reg)
-(rule (asr_imm ty x imm) (alu_rr_imm_shift (ALUOp.Asr) ty x imm))
-
-;; Helper for generating `lsr` instructions.
-(decl lsr (Type Reg Reg) Reg)
-(rule (lsr ty x y) (alu_rrr (ALUOp.Lsr) ty x y))
-
-(decl lsr_imm (Type Reg ImmShift) Reg)
-(rule (lsr_imm ty x imm) (alu_rr_imm_shift (ALUOp.Lsr) ty x imm))
-
-;; Helper for generating `lsl` instructions.
-(decl lsl (Type Reg Reg) Reg)
-(rule (lsl ty x y) (alu_rrr (ALUOp.Lsl) ty x y))
-
-(decl lsl_imm (Type Reg ImmShift) Reg)
-(rule (lsl_imm ty x imm) (alu_rr_imm_shift (ALUOp.Lsl) ty x imm))
-
-;; Helper for generating `udiv` instructions.
-(decl a64_udiv (Type Reg Reg) Reg)
-(rule (a64_udiv ty x y) (alu_rrr (ALUOp.UDiv) ty x y))
-
-;; Helper for generating `sdiv` instructions.
-(decl a64_sdiv (Type Reg Reg) Reg)
-(rule (a64_sdiv ty x y) (alu_rrr (ALUOp.SDiv) ty x y))
-
-;; Helper for generating `not` instructions.
-(decl not (Reg VectorSize) Reg)
-(rule (not x size) (vec_misc (VecMisc2.Not) x size))
-
-;; Helpers for generating `orr_not` instructions.
-
-(decl orr_not (Type Reg Reg) Reg)
-(rule (orr_not ty x y) (alu_rrr (ALUOp.OrrNot) ty x y))
-
-(decl orr_not_shift (Type Reg Reg ShiftOpAndAmt) Reg)
-(rule (orr_not_shift ty x y shift) (alu_rrr_shift (ALUOp.OrrNot) ty x y shift))
-
-;; Helpers for generating `orr` instructions.
-
-(decl orr (Type Reg Reg) Reg)
-(rule (orr ty x y) (alu_rrr (ALUOp.Orr) ty x y))
-
-(decl orr_imm (Type Reg ImmLogic) Reg)
-(rule (orr_imm ty x y) (alu_rr_imm_logic (ALUOp.Orr) ty x y))
-
-(decl orr_vec (Reg Reg VectorSize) Reg)
-(rule (orr_vec x y size) (vec_rrr (VecALUOp.Orr) x y size))
-
-;; Helpers for generating `and` instructions.
-
-(decl and_imm (Type Reg ImmLogic) Reg)
-(rule (and_imm ty x y) (alu_rr_imm_logic (ALUOp.And) ty x y))
-
-(decl and_vec (Reg Reg VectorSize) Reg)
-(rule (and_vec x y size) (vec_rrr (VecALUOp.And) x y size))
-
-;; Helpers for generating `eor` instructions.
-(decl eor_vec (Reg Reg VectorSize) Reg)
-(rule (eor_vec x y size) (vec_rrr (VecALUOp.Eor) x y size))
-
-;; Helpers for generating `bic` instructions.
-(decl bic_vec (Reg Reg VectorSize) Reg)
-(rule (bic_vec x y size) (vec_rrr (VecALUOp.Bic) x y size))
-
-;; Helpers for generating `sshl` instructions.
-(decl sshl (Reg Reg VectorSize) Reg)
-(rule (sshl x y size) (vec_rrr (VecALUOp.Sshl) x y size))
-
-;; Helpers for generating `ushl` instructions.
-(decl ushl (Reg Reg VectorSize) Reg)
-(rule (ushl x y size) (vec_rrr (VecALUOp.Ushl) x y size))
-
-;; Helpers for generating `rotr` instructions.
-
-(decl a64_rotr (Type Reg Reg) Reg)
-(rule (a64_rotr ty x y) (alu_rrr (ALUOp.RotR) ty x y))
-
-(decl a64_rotr_imm (Type Reg ImmShift) Reg)
-(rule (a64_rotr_imm ty x y) (alu_rr_imm_shift (ALUOp.RotR) ty x y))
-
-;; Helpers for generating `rbit` instructions.
-
-(decl rbit (Type Reg) Reg)
-(rule (rbit ty x) (bit_rr (BitOp.RBit) ty x))
-
-;; Helpers for generating `clz` instructions.
-
-(decl a64_clz (Type Reg) Reg)
-(rule (a64_clz ty x) (bit_rr (BitOp.Clz) ty x))
-
-;; Helpers for generating `cls` instructions.
-
-(decl a64_cls (Type Reg) Reg)
-(rule (a64_cls ty x) (bit_rr (BitOp.Cls) ty x))
-
-;; Helpers for generating `eon` instructions.
-
-(decl eon (Type Reg Reg) Reg)
-(rule (eon ty x y) (alu_rrr (ALUOp.EorNot) ty x y))
-
-;; Helpers for generating `cnt` instructions.
-
-(decl vec_cnt (Reg VectorSize) Reg)
-(rule (vec_cnt x size) (vec_misc (VecMisc2.Cnt) x size))
-
-;; Immediate value helpers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl imm (Type u64) Reg)
-
-;; 16-bit immediate (shifted by 0, 16, 32 or 48 bits) in MOVZ
-(rule (imm (integral_ty _ty) (move_wide_const_from_u64 n))
-      (movz n (OperandSize.Size64)))
-
-;; 16-bit immediate (shifted by 0, 16, 32 or 48 bits) in MOVN
-(rule (imm (integral_ty _ty) (move_wide_const_from_negated_u64 n))
-      (movn n (OperandSize.Size64)))
-
-;; Weird logical-instruction immediate in ORI using zero register
-(rule (imm (integral_ty _ty) (imm_logic_from_u64 <$I64 n))
-      (orr_imm $I64 (zero_reg) n))
-
-(decl load_constant64_full (u64) Reg)
-(extern constructor load_constant64_full load_constant64_full)
-
-;; Fallback for integral 64-bit constants that uses lots of `movk`
-(rule (imm (integral_ty _ty) n)
-      (load_constant64_full n))
-
-;; Sign extension helpers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Place a `Value` into a register, sign extending it to 32-bits
-(decl put_in_reg_sext32 (Value) Reg)
-(rule (put_in_reg_sext32 val @ (value_type (fits_in_32 ty)))
-      (extend val $true (ty_bits ty) 32))
-
-;; 32/64-bit passthrough.
-(rule (put_in_reg_sext32 val @ (value_type $I32)) val)
-(rule (put_in_reg_sext32 val @ (value_type $I64)) val)
-
-;; Place a `Value` into a register, zero extending it to 32-bits
-(decl put_in_reg_zext32 (Value) Reg)
-(rule (put_in_reg_zext32 val @ (value_type (fits_in_32 ty)))
-      (extend val $false (ty_bits ty) 32))
-
-;; 32/64-bit passthrough.
-(rule (put_in_reg_zext32 val @ (value_type $I32)) val)
-(rule (put_in_reg_zext32 val @ (value_type $I64)) val)
-
-;; Place a `Value` into a register, sign extending it to 64-bits
-(decl put_in_reg_sext64 (Value) Reg)
-(rule (put_in_reg_sext64 val @ (value_type (fits_in_32 ty)))
-      (extend val $true (ty_bits ty) 64))
-
-;; 64-bit passthrough.
-(rule (put_in_reg_sext64 val @ (value_type $I64)) val)
-
-;; Place a `Value` into a register, zero extending it to 64-bits
-(decl put_in_reg_zext64 (Value) Reg)
-(rule (put_in_reg_zext64 val @ (value_type (fits_in_32 ty)))
-      (extend val $false (ty_bits ty) 64))
-
-;; 64-bit passthrough.
-(rule (put_in_reg_zext64 val @ (value_type $I64)) val)
-
-;; Misc instruction helpers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl trap_if_zero_divisor (Reg) Reg)
-(rule (trap_if_zero_divisor reg)
-      (let ((_ Unit (emit (MInst.TrapIf (cond_br_zero reg) (trap_code_division_by_zero)))))
-        reg))
-
-(decl size_from_ty (Type) OperandSize)
-(rule (size_from_ty (fits_in_32 _ty)) (OperandSize.Size32))
-(rule (size_from_ty $I64) (OperandSize.Size64))
-
-;; Check for signed overflow. The only case is min_value / -1.
-;; The following checks must be done in 32-bit or 64-bit, depending
-;; on the input type.
-(decl trap_if_div_overflow (Type Reg Reg) Reg)
-(rule (trap_if_div_overflow ty x y)
-      (let (
-          ;; Check RHS is -1.
-          (_1 Unit (emit (MInst.AluRRImm12 (ALUOp.AddS) (operand_size ty) (writable_zero_reg) y (u8_into_imm12 1))))
-
-          ;; Check LHS is min_value, by subtracting 1 and branching if
-          ;; there is overflow.
-          (_2 Unit (emit (MInst.CCmpImm (size_from_ty ty)
-                                        x
-                                        (u8_into_uimm5 1)
-                                        (nzcv $false $false $false $false)
-                                        (Cond.Eq))))
-          (_3 Unit (emit (MInst.TrapIf (cond_br_cond (Cond.Vs))
-                                      (trap_code_integer_overflow))))
-        )
-        x))
-
-;; An atomic load that can be sunk into another operation.
-(type SinkableAtomicLoad extern (enum))
-
-;; Extract a `SinkableAtomicLoad` that works with `Reg` from a value
-;; operand.
-(decl sinkable_atomic_load (SinkableAtomicLoad) Value)
-(extern extractor sinkable_atomic_load sinkable_atomic_load)
-
-;; Sink a `SinkableLoad` into a `Reg`.
-;;
-;; This is a side-effectful operation that notifies the context that the
-;; instruction that produced the `SinkableAtomicLoad` has been sunk into another
-;; instruction, and no longer needs to be lowered.
-(decl sink_atomic_load (SinkableAtomicLoad) Reg)
-(extern constructor sink_atomic_load sink_atomic_load)
-
-;; Helper for generating either an `AluRRR`, `AluRRRShift`, or `AluRRImmLogic`
-;; instruction depending on the input. Note that this requires that the `ALUOp`
-;; specified is commutative.
-(decl alu_rs_imm_logic_commutative (ALUOp Type Value Value) Reg)
-
-;; Base case of operating on registers.
-(rule (alu_rs_imm_logic_commutative op ty x y)
-      (alu_rrr op ty (put_in_reg x) (put_in_reg y)))
-
-;; Special cases for when one operand is a constant.
-(rule (alu_rs_imm_logic_commutative op ty x (def_inst (iconst (imm_logic_from_imm64 <ty imm))))
-      (alu_rr_imm_logic op ty (put_in_reg x) imm))
-(rule (alu_rs_imm_logic_commutative op ty (def_inst (iconst (imm_logic_from_imm64 <ty imm))) x)
-      (alu_rr_imm_logic op ty (put_in_reg x) imm))
-
-;; Special cases for when one operand is shifted left by a constant.
-(rule (alu_rs_imm_logic_commutative op ty x (def_inst (ishl y (def_inst (iconst (lshl_from_imm64 <ty amt))))))
-      (alu_rrr_shift op ty (put_in_reg x) (put_in_reg y) amt))
-(rule (alu_rs_imm_logic_commutative op ty (def_inst (ishl x (def_inst (iconst (lshl_from_imm64 <ty amt))))) y)
-      (alu_rrr_shift op ty (put_in_reg y) (put_in_reg x) amt))
-
-;; Same as `alu_rs_imm_logic_commutative` above, except that it doesn't require
-;; that the operation is commutative.
-(decl alu_rs_imm_logic (ALUOp Type Value Value) Reg)
-(rule (alu_rs_imm_logic op ty x y)
-      (alu_rrr op ty (put_in_reg x) (put_in_reg y)))
-(rule (alu_rs_imm_logic op ty x (def_inst (iconst (imm_logic_from_imm64 <ty imm))))
-      (alu_rr_imm_logic op ty (put_in_reg x) imm))
-(rule (alu_rs_imm_logic op ty x (def_inst (ishl y (def_inst (iconst (lshl_from_imm64 <ty amt))))))
-      (alu_rrr_shift op ty (put_in_reg x) (put_in_reg y) amt))
-
-;; Helper for generating i128 bitops which simply do the same operation to the
-;; hi/lo registers.
-;;
-;; TODO: Support immlogic here
-(decl i128_alu_bitop (ALUOp Type Value Value) ValueRegs)
-(rule (i128_alu_bitop op ty x y)
-      (let (
-          (x_regs ValueRegs (put_in_regs x))
-          (x_lo Reg (value_regs_get x_regs 0))
-          (x_hi Reg (value_regs_get x_regs 1))
-          (y_regs ValueRegs (put_in_regs y))
-          (y_lo Reg (value_regs_get y_regs 0))
-          (y_hi Reg (value_regs_get y_regs 1))
-        )
-        (value_regs
-          (alu_rrr op ty x_lo y_lo)
-          (alu_rrr op ty x_hi y_hi))))
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/inst/args.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/inst/args.rs
deleted file mode 100644
index 1a836f1a7..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/inst/args.rs
+++ /dev/null
@@ -1,755 +0,0 @@
-//! AArch64 ISA definitions: instruction arguments.
-
-// Some variants are never constructed, but we still want them as options in the future.
-#![allow(dead_code)]
-
-use crate::ir::types::*;
-use crate::ir::Type;
-use crate::isa::aarch64::inst::*;
-use crate::machinst::{ty_bits, MachLabel};
-
-use regalloc::{PrettyPrint, RealRegUniverse, Reg, Writable};
-
-use core::convert::Into;
-use std::string::String;
-
-//=============================================================================
-// Instruction sub-components: shift and extend descriptors
-
-/// A shift operator for a register or immediate.
-#[derive(Clone, Copy, Debug)]
-#[repr(u8)]
-pub enum ShiftOp {
-    LSL = 0b00,
-    LSR = 0b01,
-    ASR = 0b10,
-    ROR = 0b11,
-}
-
-impl ShiftOp {
-    /// Get the encoding of this shift op.
-    pub fn bits(self) -> u8 {
-        self as u8
-    }
-}
-
-/// A shift operator amount.
-#[derive(Clone, Copy, Debug)]
-pub struct ShiftOpShiftImm(u8);
-
-impl ShiftOpShiftImm {
-    /// Maximum shift for shifted-register operands.
-    pub const MAX_SHIFT: u64 = 63;
-
-    /// Create a new shiftop shift amount, if possible.
-    pub fn maybe_from_shift(shift: u64) -> Option<ShiftOpShiftImm> {
-        if shift <= Self::MAX_SHIFT {
-            Some(ShiftOpShiftImm(shift as u8))
-        } else {
-            None
-        }
-    }
-
-    /// Return the shift amount.
-    pub fn value(self) -> u8 {
-        self.0
-    }
-
-    /// Mask down to a given number of bits.
-    pub fn mask(self, bits: u8) -> ShiftOpShiftImm {
-        ShiftOpShiftImm(self.0 & (bits - 1))
-    }
-}
-
-/// A shift operator with an amount, guaranteed to be within range.
-#[derive(Copy, Clone, Debug)]
-pub struct ShiftOpAndAmt {
-    op: ShiftOp,
-    shift: ShiftOpShiftImm,
-}
-
-impl ShiftOpAndAmt {
-    pub fn new(op: ShiftOp, shift: ShiftOpShiftImm) -> ShiftOpAndAmt {
-        ShiftOpAndAmt { op, shift }
-    }
-
-    /// Get the shift op.
-    pub fn op(&self) -> ShiftOp {
-        self.op
-    }
-
-    /// Get the shift amount.
-    pub fn amt(&self) -> ShiftOpShiftImm {
-        self.shift
-    }
-}
-
-/// An extend operator for a register.
-#[derive(Clone, Copy, Debug)]
-#[repr(u8)]
-pub enum ExtendOp {
-    UXTB = 0b000,
-    UXTH = 0b001,
-    UXTW = 0b010,
-    UXTX = 0b011,
-    SXTB = 0b100,
-    SXTH = 0b101,
-    SXTW = 0b110,
-    SXTX = 0b111,
-}
-
-impl ExtendOp {
-    /// Encoding of this op.
-    pub fn bits(self) -> u8 {
-        self as u8
-    }
-}
-
-//=============================================================================
-// Instruction sub-components (memory addresses): definitions
-
-/// A reference to some memory address.
-#[derive(Clone, Debug)]
-pub enum MemLabel {
-    /// An address in the code, a constant pool or jumptable, with relative
-    /// offset from this instruction. This form must be used at emission time;
-    /// see `memlabel_finalize()` for how other forms are lowered to this one.
-    PCRel(i32),
-}
-
-/// An addressing mode specified for a load/store operation.
-#[derive(Clone, Debug)]
-pub enum AMode {
-    //
-    // Real ARM64 addressing modes:
-    //
-    /// "post-indexed" mode as per AArch64 docs: postincrement reg after address computation.
-    PostIndexed(Writable<Reg>, SImm9),
-    /// "pre-indexed" mode as per AArch64 docs: preincrement reg before address computation.
-    PreIndexed(Writable<Reg>, SImm9),
-
-    // N.B.: RegReg, RegScaled, and RegScaledExtended all correspond to
-    // what the ISA calls the "register offset" addressing mode. We split out
-    // several options here for more ergonomic codegen.
-    /// Register plus register offset.
-    RegReg(Reg, Reg),
-
-    /// Register plus register offset, scaled by type's size.
-    RegScaled(Reg, Reg, Type),
-
-    /// Register plus register offset, scaled by type's size, with index sign- or zero-extended
-    /// first.
-    RegScaledExtended(Reg, Reg, Type, ExtendOp),
-
-    /// Register plus register offset, with index sign- or zero-extended first.
-    RegExtended(Reg, Reg, ExtendOp),
-
-    /// Unscaled signed 9-bit immediate offset from reg.
-    Unscaled(Reg, SImm9),
-
-    /// Scaled (by size of a type) unsigned 12-bit immediate offset from reg.
-    UnsignedOffset(Reg, UImm12Scaled),
-
-    //
-    // virtual addressing modes that are lowered at emission time:
-    //
-    /// Reference to a "label": e.g., a symbol.
-    Label(MemLabel),
-
-    /// Arbitrary offset from a register. Converted to generation of large
-    /// offsets with multiple instructions as necessary during code emission.
-    RegOffset(Reg, i64, Type),
-
-    /// Offset from the stack pointer.
-    SPOffset(i64, Type),
-
-    /// Offset from the frame pointer.
-    FPOffset(i64, Type),
-
-    /// Offset from the "nominal stack pointer", which is where the real SP is
-    /// just after stack and spill slots are allocated in the function prologue.
-    /// At emission time, this is converted to `SPOffset` with a fixup added to
-    /// the offset constant. The fixup is a running value that is tracked as
-    /// emission iterates through instructions in linear order, and can be
-    /// adjusted up and down with [Inst::VirtualSPOffsetAdj].
-    ///
-    /// The standard ABI is in charge of handling this (by emitting the
-    /// adjustment meta-instructions). It maintains the invariant that "nominal
-    /// SP" is where the actual SP is after the function prologue and before
-    /// clobber pushes. See the diagram in the documentation for
-    /// [crate::isa::aarch64::abi](the ABI module) for more details.
-    NominalSPOffset(i64, Type),
-}
-
-impl AMode {
-    /// Memory reference using an address in a register.
-    pub fn reg(reg: Reg) -> AMode {
-        // Use UnsignedOffset rather than Unscaled to use ldr rather than ldur.
-        // This also does not use PostIndexed / PreIndexed as they update the register.
-        AMode::UnsignedOffset(reg, UImm12Scaled::zero(I64))
-    }
-
-    /// Memory reference using the sum of two registers as an address.
-    pub fn reg_plus_reg(reg1: Reg, reg2: Reg) -> AMode {
-        AMode::RegReg(reg1, reg2)
-    }
-
-    /// Memory reference using `reg1 + sizeof(ty) * reg2` as an address.
-    pub fn reg_plus_reg_scaled(reg1: Reg, reg2: Reg, ty: Type) -> AMode {
-        AMode::RegScaled(reg1, reg2, ty)
-    }
-
-    /// Memory reference using `reg1 + sizeof(ty) * reg2` as an address, with `reg2` sign- or
-    /// zero-extended as per `op`.
-    pub fn reg_plus_reg_scaled_extended(reg1: Reg, reg2: Reg, ty: Type, op: ExtendOp) -> AMode {
-        AMode::RegScaledExtended(reg1, reg2, ty, op)
-    }
-
-    /// Memory reference to a label: a global function or value, or data in the constant pool.
-    pub fn label(label: MemLabel) -> AMode {
-        AMode::Label(label)
-    }
-
-    /// Does the address resolve to just a register value, with no offset or
-    /// other computation?
-    pub fn is_reg(&self) -> Option<Reg> {
-        match self {
-            &AMode::UnsignedOffset(r, uimm12) if uimm12.value() == 0 => Some(r),
-            &AMode::Unscaled(r, imm9) if imm9.value() == 0 => Some(r),
-            &AMode::RegOffset(r, off, _) if off == 0 => Some(r),
-            &AMode::FPOffset(off, _) if off == 0 => Some(fp_reg()),
-            &AMode::SPOffset(off, _) if off == 0 => Some(stack_reg()),
-            _ => None,
-        }
-    }
-}
-
-/// A memory argument to a load/store-pair.
-#[derive(Clone, Debug)]
-pub enum PairAMode {
-    SignedOffset(Reg, SImm7Scaled),
-    PreIndexed(Writable<Reg>, SImm7Scaled),
-    PostIndexed(Writable<Reg>, SImm7Scaled),
-}
-
-//=============================================================================
-// Instruction sub-components (conditions, branches and branch targets):
-// definitions
-
-/// Condition for conditional branches.
-#[derive(Clone, Copy, Debug, PartialEq, Eq)]
-#[repr(u8)]
-pub enum Cond {
-    Eq = 0,
-    Ne = 1,
-    Hs = 2,
-    Lo = 3,
-    Mi = 4,
-    Pl = 5,
-    Vs = 6,
-    Vc = 7,
-    Hi = 8,
-    Ls = 9,
-    Ge = 10,
-    Lt = 11,
-    Gt = 12,
-    Le = 13,
-    Al = 14,
-    Nv = 15,
-}
-
-impl Cond {
-    /// Return the inverted condition.
-    pub fn invert(self) -> Cond {
-        match self {
-            Cond::Eq => Cond::Ne,
-            Cond::Ne => Cond::Eq,
-
-            Cond::Hs => Cond::Lo,
-            Cond::Lo => Cond::Hs,
-
-            Cond::Mi => Cond::Pl,
-            Cond::Pl => Cond::Mi,
-
-            Cond::Vs => Cond::Vc,
-            Cond::Vc => Cond::Vs,
-
-            Cond::Hi => Cond::Ls,
-            Cond::Ls => Cond::Hi,
-
-            Cond::Ge => Cond::Lt,
-            Cond::Lt => Cond::Ge,
-
-            Cond::Gt => Cond::Le,
-            Cond::Le => Cond::Gt,
-
-            Cond::Al => Cond::Nv,
-            Cond::Nv => Cond::Al,
-        }
-    }
-
-    /// Return the machine encoding of this condition.
-    pub fn bits(self) -> u32 {
-        self as u32
-    }
-}
-
-/// The kind of conditional branch: the common-case-optimized "reg-is-zero" /
-/// "reg-is-nonzero" variants, or the generic one that tests the machine
-/// condition codes.
-#[derive(Clone, Copy, Debug)]
-pub enum CondBrKind {
-    /// Condition: given register is zero.
-    Zero(Reg),
-    /// Condition: given register is nonzero.
-    NotZero(Reg),
-    /// Condition: the given condition-code test is true.
-    Cond(Cond),
-}
-
-impl CondBrKind {
-    /// Return the inverted branch condition.
-    pub fn invert(self) -> CondBrKind {
-        match self {
-            CondBrKind::Zero(reg) => CondBrKind::NotZero(reg),
-            CondBrKind::NotZero(reg) => CondBrKind::Zero(reg),
-            CondBrKind::Cond(c) => CondBrKind::Cond(c.invert()),
-        }
-    }
-}
-
-/// A branch target. Either unresolved (basic-block index) or resolved (offset
-/// from end of current instruction).
-#[derive(Clone, Copy, Debug, PartialEq, Eq)]
-pub enum BranchTarget {
-    /// An unresolved reference to a Label, as passed into
-    /// `lower_branch_group()`.
-    Label(MachLabel),
-    /// A fixed PC offset.
-    ResolvedOffset(i32),
-}
-
-impl BranchTarget {
-    /// Return the target's label, if it is a label-based target.
-    pub fn as_label(self) -> Option<MachLabel> {
-        match self {
-            BranchTarget::Label(l) => Some(l),
-            _ => None,
-        }
-    }
-
-    /// Return the target's offset, if specified, or zero if label-based.
-    pub fn as_offset19_or_zero(self) -> u32 {
-        let off = match self {
-            BranchTarget::ResolvedOffset(off) => off >> 2,
-            _ => 0,
-        };
-        assert!(off <= 0x3ffff);
-        assert!(off >= -0x40000);
-        (off as u32) & 0x7ffff
-    }
-
-    /// Return the target's offset, if specified, or zero if label-based.
-    pub fn as_offset26_or_zero(self) -> u32 {
-        let off = match self {
-            BranchTarget::ResolvedOffset(off) => off >> 2,
-            _ => 0,
-        };
-        assert!(off <= 0x1ffffff);
-        assert!(off >= -0x2000000);
-        (off as u32) & 0x3ffffff
-    }
-}
-
-impl PrettyPrint for ShiftOpAndAmt {
-    fn show_rru(&self, _mb_rru: Option<&RealRegUniverse>) -> String {
-        format!("{:?} {}", self.op(), self.amt().value())
-    }
-}
-
-impl PrettyPrint for ExtendOp {
-    fn show_rru(&self, _mb_rru: Option<&RealRegUniverse>) -> String {
-        format!("{:?}", self)
-    }
-}
-
-impl PrettyPrint for MemLabel {
-    fn show_rru(&self, _mb_rru: Option<&RealRegUniverse>) -> String {
-        match self {
-            &MemLabel::PCRel(off) => format!("pc+{}", off),
-        }
-    }
-}
-
-fn shift_for_type(ty: Type) -> usize {
-    match ty.bytes() {
-        1 => 0,
-        2 => 1,
-        4 => 2,
-        8 => 3,
-        16 => 4,
-        _ => panic!("unknown type: {}", ty),
-    }
-}
-
-impl PrettyPrint for AMode {
-    fn show_rru(&self, mb_rru: Option<&RealRegUniverse>) -> String {
-        match self {
-            &AMode::Unscaled(reg, simm9) => {
-                if simm9.value != 0 {
-                    format!("[{}, {}]", reg.show_rru(mb_rru), simm9.show_rru(mb_rru))
-                } else {
-                    format!("[{}]", reg.show_rru(mb_rru))
-                }
-            }
-            &AMode::UnsignedOffset(reg, uimm12) => {
-                if uimm12.value != 0 {
-                    format!("[{}, {}]", reg.show_rru(mb_rru), uimm12.show_rru(mb_rru))
-                } else {
-                    format!("[{}]", reg.show_rru(mb_rru))
-                }
-            }
-            &AMode::RegReg(r1, r2) => {
-                format!("[{}, {}]", r1.show_rru(mb_rru), r2.show_rru(mb_rru),)
-            }
-            &AMode::RegScaled(r1, r2, ty) => {
-                let shift = shift_for_type(ty);
-                format!(
-                    "[{}, {}, LSL #{}]",
-                    r1.show_rru(mb_rru),
-                    r2.show_rru(mb_rru),
-                    shift,
-                )
-            }
-            &AMode::RegScaledExtended(r1, r2, ty, op) => {
-                let shift = shift_for_type(ty);
-                let size = match op {
-                    ExtendOp::SXTW | ExtendOp::UXTW => OperandSize::Size32,
-                    _ => OperandSize::Size64,
-                };
-                let op = op.show_rru(mb_rru);
-                format!(
-                    "[{}, {}, {} #{}]",
-                    r1.show_rru(mb_rru),
-                    show_ireg_sized(r2, mb_rru, size),
-                    op,
-                    shift
-                )
-            }
-            &AMode::RegExtended(r1, r2, op) => {
-                let size = match op {
-                    ExtendOp::SXTW | ExtendOp::UXTW => OperandSize::Size32,
-                    _ => OperandSize::Size64,
-                };
-                let op = op.show_rru(mb_rru);
-                format!(
-                    "[{}, {}, {}]",
-                    r1.show_rru(mb_rru),
-                    show_ireg_sized(r2, mb_rru, size),
-                    op,
-                )
-            }
-            &AMode::Label(ref label) => label.show_rru(mb_rru),
-            &AMode::PreIndexed(r, simm9) => format!(
-                "[{}, {}]!",
-                r.to_reg().show_rru(mb_rru),
-                simm9.show_rru(mb_rru)
-            ),
-            &AMode::PostIndexed(r, simm9) => format!(
-                "[{}], {}",
-                r.to_reg().show_rru(mb_rru),
-                simm9.show_rru(mb_rru)
-            ),
-            // Eliminated by `mem_finalize()`.
-            &AMode::SPOffset(..)
-            | &AMode::FPOffset(..)
-            | &AMode::NominalSPOffset(..)
-            | &AMode::RegOffset(..) => {
-                panic!("Unexpected pseudo mem-arg mode (stack-offset or generic reg-offset)!")
-            }
-        }
-    }
-}
-
-impl PrettyPrint for PairAMode {
-    fn show_rru(&self, mb_rru: Option<&RealRegUniverse>) -> String {
-        match self {
-            &PairAMode::SignedOffset(reg, simm7) => {
-                if simm7.value != 0 {
-                    format!("[{}, {}]", reg.show_rru(mb_rru), simm7.show_rru(mb_rru))
-                } else {
-                    format!("[{}]", reg.show_rru(mb_rru))
-                }
-            }
-            &PairAMode::PreIndexed(reg, simm7) => format!(
-                "[{}, {}]!",
-                reg.to_reg().show_rru(mb_rru),
-                simm7.show_rru(mb_rru)
-            ),
-            &PairAMode::PostIndexed(reg, simm7) => format!(
-                "[{}], {}",
-                reg.to_reg().show_rru(mb_rru),
-                simm7.show_rru(mb_rru)
-            ),
-        }
-    }
-}
-
-impl PrettyPrint for Cond {
-    fn show_rru(&self, _mb_rru: Option<&RealRegUniverse>) -> String {
-        let mut s = format!("{:?}", self);
-        s.make_ascii_lowercase();
-        s
-    }
-}
-
-impl PrettyPrint for BranchTarget {
-    fn show_rru(&self, _mb_rru: Option<&RealRegUniverse>) -> String {
-        match self {
-            &BranchTarget::Label(label) => format!("label{:?}", label.get()),
-            &BranchTarget::ResolvedOffset(off) => format!("{}", off),
-        }
-    }
-}
-
-/// Type used to communicate the operand size of a machine instruction, as AArch64 has 32- and
-/// 64-bit variants of many instructions (and integer registers).
-#[derive(Clone, Copy, Debug, PartialEq, Eq)]
-pub enum OperandSize {
-    Size32,
-    Size64,
-}
-
-impl OperandSize {
-    /// 32-bit case?
-    pub fn is32(self) -> bool {
-        self == OperandSize::Size32
-    }
-    /// 64-bit case?
-    pub fn is64(self) -> bool {
-        self == OperandSize::Size64
-    }
-    /// Convert from an `is32` boolean flag to an `OperandSize`.
-    pub fn from_is32(is32: bool) -> OperandSize {
-        if is32 {
-            OperandSize::Size32
-        } else {
-            OperandSize::Size64
-        }
-    }
-    /// Convert from a needed width to the smallest size that fits.
-    pub fn from_bits<I: Into<usize>>(bits: I) -> OperandSize {
-        let bits: usize = bits.into();
-        assert!(bits <= 64);
-        if bits <= 32 {
-            OperandSize::Size32
-        } else {
-            OperandSize::Size64
-        }
-    }
-
-    /// Convert from an integer type into the smallest size that fits.
-    pub fn from_ty(ty: Type) -> OperandSize {
-        debug_assert!(!ty.is_vector());
-
-        Self::from_bits(ty_bits(ty))
-    }
-
-    /// Convert to I32, I64, or I128.
-    pub fn to_ty(self) -> Type {
-        match self {
-            OperandSize::Size32 => I32,
-            OperandSize::Size64 => I64,
-        }
-    }
-
-    pub fn sf_bit(&self) -> u32 {
-        match self {
-            OperandSize::Size32 => 0,
-            OperandSize::Size64 => 1,
-        }
-    }
-}
-
-/// Type used to communicate the size of a scalar SIMD & FP operand.
-#[derive(Clone, Copy, Debug, PartialEq, Eq)]
-pub enum ScalarSize {
-    Size8,
-    Size16,
-    Size32,
-    Size64,
-    Size128,
-}
-
-impl ScalarSize {
-    /// Convert from a needed width to the smallest size that fits.
-    pub fn from_bits<I: Into<usize>>(bits: I) -> ScalarSize {
-        match bits.into().next_power_of_two() {
-            8 => ScalarSize::Size8,
-            16 => ScalarSize::Size16,
-            32 => ScalarSize::Size32,
-            64 => ScalarSize::Size64,
-            128 => ScalarSize::Size128,
-            w => panic!("Unexpected type width: {}", w),
-        }
-    }
-
-    /// Convert to an integer operand size.
-    pub fn operand_size(&self) -> OperandSize {
-        match self {
-            ScalarSize::Size32 => OperandSize::Size32,
-            ScalarSize::Size64 => OperandSize::Size64,
-            _ => panic!("Unexpected operand_size request for: {:?}", self),
-        }
-    }
-
-    /// Convert from an integer operand size.
-    pub fn from_operand_size(size: OperandSize) -> ScalarSize {
-        match size {
-            OperandSize::Size32 => ScalarSize::Size32,
-            OperandSize::Size64 => ScalarSize::Size64,
-        }
-    }
-
-    /// Convert from a type into the smallest size that fits.
-    pub fn from_ty(ty: Type) -> ScalarSize {
-        debug_assert!(!ty.is_vector());
-
-        Self::from_bits(ty_bits(ty))
-    }
-
-    /// Return the encoding bits that are used by some scalar FP instructions
-    /// for a particular operand size.
-    pub fn ftype(&self) -> u32 {
-        match self {
-            ScalarSize::Size16 => 0b11,
-            ScalarSize::Size32 => 0b00,
-            ScalarSize::Size64 => 0b01,
-            _ => panic!("Unexpected scalar FP operand size: {:?}", self),
-        }
-    }
-}
-
-/// Type used to communicate the size of a vector operand.
-#[derive(Clone, Copy, Debug, PartialEq, Eq)]
-pub enum VectorSize {
-    Size8x8,
-    Size8x16,
-    Size16x4,
-    Size16x8,
-    Size32x2,
-    Size32x4,
-    Size64x2,
-}
-
-impl VectorSize {
-    /// Get the vector operand size with the given scalar size as lane size.
-    pub fn from_lane_size(size: ScalarSize, is_128bit: bool) -> VectorSize {
-        match (size, is_128bit) {
-            (ScalarSize::Size8, false) => VectorSize::Size8x8,
-            (ScalarSize::Size8, true) => VectorSize::Size8x16,
-            (ScalarSize::Size16, false) => VectorSize::Size16x4,
-            (ScalarSize::Size16, true) => VectorSize::Size16x8,
-            (ScalarSize::Size32, false) => VectorSize::Size32x2,
-            (ScalarSize::Size32, true) => VectorSize::Size32x4,
-            (ScalarSize::Size64, true) => VectorSize::Size64x2,
-            _ => panic!("Unexpected scalar FP operand size: {:?}", size),
-        }
-    }
-
-    /// Convert from a type into a vector operand size.
-    pub fn from_ty(ty: Type) -> VectorSize {
-        debug_assert!(ty.is_vector());
-
-        match ty {
-            B8X16 => VectorSize::Size8x16,
-            B16X8 => VectorSize::Size16x8,
-            B32X4 => VectorSize::Size32x4,
-            B64X2 => VectorSize::Size64x2,
-            F32X2 => VectorSize::Size32x2,
-            F32X4 => VectorSize::Size32x4,
-            F64X2 => VectorSize::Size64x2,
-            I8X8 => VectorSize::Size8x8,
-            I8X16 => VectorSize::Size8x16,
-            I16X4 => VectorSize::Size16x4,
-            I16X8 => VectorSize::Size16x8,
-            I32X2 => VectorSize::Size32x2,
-            I32X4 => VectorSize::Size32x4,
-            I64X2 => VectorSize::Size64x2,
-            _ => unimplemented!("Unsupported type: {}", ty),
-        }
-    }
-
-    /// Get the integer operand size that corresponds to a lane of a vector with a certain size.
-    pub fn operand_size(&self) -> OperandSize {
-        match self {
-            VectorSize::Size64x2 => OperandSize::Size64,
-            _ => OperandSize::Size32,
-        }
-    }
-
-    /// Get the scalar operand size that corresponds to a lane of a vector with a certain size.
-    pub fn lane_size(&self) -> ScalarSize {
-        match self {
-            VectorSize::Size8x8 => ScalarSize::Size8,
-            VectorSize::Size8x16 => ScalarSize::Size8,
-            VectorSize::Size16x4 => ScalarSize::Size16,
-            VectorSize::Size16x8 => ScalarSize::Size16,
-            VectorSize::Size32x2 => ScalarSize::Size32,
-            VectorSize::Size32x4 => ScalarSize::Size32,
-            VectorSize::Size64x2 => ScalarSize::Size64,
-        }
-    }
-
-    pub fn is_128bits(&self) -> bool {
-        match self {
-            VectorSize::Size8x8 => false,
-            VectorSize::Size8x16 => true,
-            VectorSize::Size16x4 => false,
-            VectorSize::Size16x8 => true,
-            VectorSize::Size32x2 => false,
-            VectorSize::Size32x4 => true,
-            VectorSize::Size64x2 => true,
-        }
-    }
-
-    /// Produces a `VectorSize` with lanes twice as wide.  Note that if the resulting
-    /// size would exceed 128 bits, then the number of lanes is also halved, so as to
-    /// ensure that the result size is at most 128 bits.
-    pub fn widen(&self) -> VectorSize {
-        match self {
-            VectorSize::Size8x8 => VectorSize::Size16x8,
-            VectorSize::Size8x16 => VectorSize::Size16x8,
-            VectorSize::Size16x4 => VectorSize::Size32x4,
-            VectorSize::Size16x8 => VectorSize::Size32x4,
-            VectorSize::Size32x2 => VectorSize::Size64x2,
-            VectorSize::Size32x4 => VectorSize::Size64x2,
-            VectorSize::Size64x2 => unreachable!(),
-        }
-    }
-
-    /// Produces a `VectorSize` that has the same lane width, but half as many lanes.
-    pub fn halve(&self) -> VectorSize {
-        match self {
-            VectorSize::Size8x16 => VectorSize::Size8x8,
-            VectorSize::Size16x8 => VectorSize::Size16x4,
-            VectorSize::Size32x4 => VectorSize::Size32x2,
-            _ => *self,
-        }
-    }
-
-    /// Return the encoding bits that are used by some SIMD instructions
-    /// for a particular operand size.
-    pub fn enc_size(&self) -> (u32, u32) {
-        let q = self.is_128bits() as u32;
-        let size = match self.lane_size() {
-            ScalarSize::Size8 => 0b00,
-            ScalarSize::Size16 => 0b01,
-            ScalarSize::Size32 => 0b10,
-            ScalarSize::Size64 => 0b11,
-            _ => unreachable!(),
-        };
-
-        (q, size)
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/inst/emit.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/inst/emit.rs
deleted file mode 100644
index d8670f5a1..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/inst/emit.rs
+++ /dev/null
@@ -1,2828 +0,0 @@
-//! AArch64 ISA: binary code emission.
-
-use crate::binemit::{CodeOffset, Reloc, StackMap};
-use crate::ir::constant::ConstantData;
-use crate::ir::types::*;
-use crate::ir::{LibCall, MemFlags, TrapCode};
-use crate::isa::aarch64::inst::*;
-use crate::machinst::ty_bits;
-
-use regalloc::{Reg, RegClass, Writable};
-
-use core::convert::TryFrom;
-
-/// Memory label/reference finalization: convert a MemLabel to a PC-relative
-/// offset, possibly emitting relocation(s) as necessary.
-pub fn memlabel_finalize(_insn_off: CodeOffset, label: &MemLabel) -> i32 {
-    match label {
-        &MemLabel::PCRel(rel) => rel,
-    }
-}
-
-/// Memory addressing mode finalization: convert "special" modes (e.g.,
-/// generic arbitrary stack offset) into real addressing modes, possibly by
-/// emitting some helper instructions that come immediately before the use
-/// of this amode.
-pub fn mem_finalize(
-    insn_off: CodeOffset,
-    mem: &AMode,
-    state: &EmitState,
-) -> (SmallVec<[Inst; 4]>, AMode) {
-    match mem {
-        &AMode::RegOffset(_, off, ty)
-        | &AMode::SPOffset(off, ty)
-        | &AMode::FPOffset(off, ty)
-        | &AMode::NominalSPOffset(off, ty) => {
-            let basereg = match mem {
-                &AMode::RegOffset(reg, _, _) => reg,
-                &AMode::SPOffset(..) | &AMode::NominalSPOffset(..) => stack_reg(),
-                &AMode::FPOffset(..) => fp_reg(),
-                _ => unreachable!(),
-            };
-            let adj = match mem {
-                &AMode::NominalSPOffset(..) => {
-                    log::trace!(
-                        "mem_finalize: nominal SP offset {} + adj {} -> {}",
-                        off,
-                        state.virtual_sp_offset,
-                        off + state.virtual_sp_offset
-                    );
-                    state.virtual_sp_offset
-                }
-                _ => 0,
-            };
-            let off = off + adj;
-
-            if let Some(simm9) = SImm9::maybe_from_i64(off) {
-                let mem = AMode::Unscaled(basereg, simm9);
-                (smallvec![], mem)
-            } else if let Some(uimm12s) = UImm12Scaled::maybe_from_i64(off, ty) {
-                let mem = AMode::UnsignedOffset(basereg, uimm12s);
-                (smallvec![], mem)
-            } else {
-                let tmp = writable_spilltmp_reg();
-                let mut const_insts = Inst::load_constant(tmp, off as u64);
-                // N.B.: we must use AluRRRExtend because AluRRR uses the "shifted register" form
-                // (AluRRRShift) instead, which interprets register 31 as the zero reg, not SP. SP
-                // is a valid base (for SPOffset) which we must handle here.
-                // Also, SP needs to be the first arg, not second.
-                let add_inst = Inst::AluRRRExtend {
-                    alu_op: ALUOp::Add,
-                    size: OperandSize::Size64,
-                    rd: tmp,
-                    rn: basereg,
-                    rm: tmp.to_reg(),
-                    extendop: ExtendOp::UXTX,
-                };
-                const_insts.push(add_inst);
-                (const_insts, AMode::reg(tmp.to_reg()))
-            }
-        }
-
-        &AMode::Label(ref label) => {
-            let off = memlabel_finalize(insn_off, label);
-            (smallvec![], AMode::Label(MemLabel::PCRel(off)))
-        }
-
-        _ => (smallvec![], mem.clone()),
-    }
-}
-
-/// Helper: get a ConstantData from a u64.
-pub fn u64_constant(bits: u64) -> ConstantData {
-    let data = bits.to_le_bytes();
-    ConstantData::from(&data[..])
-}
-
-//=============================================================================
-// Instructions and subcomponents: emission
-
-fn machreg_to_gpr(m: Reg) -> u32 {
-    assert_eq!(m.get_class(), RegClass::I64);
-    u32::try_from(m.to_real_reg().get_hw_encoding()).unwrap()
-}
-
-fn machreg_to_vec(m: Reg) -> u32 {
-    assert_eq!(m.get_class(), RegClass::V128);
-    u32::try_from(m.to_real_reg().get_hw_encoding()).unwrap()
-}
-
-fn machreg_to_gpr_or_vec(m: Reg) -> u32 {
-    u32::try_from(m.to_real_reg().get_hw_encoding()).unwrap()
-}
-
-pub(crate) fn enc_arith_rrr(
-    bits_31_21: u32,
-    bits_15_10: u32,
-    rd: Writable<Reg>,
-    rn: Reg,
-    rm: Reg,
-) -> u32 {
-    (bits_31_21 << 21)
-        | (bits_15_10 << 10)
-        | machreg_to_gpr(rd.to_reg())
-        | (machreg_to_gpr(rn) << 5)
-        | (machreg_to_gpr(rm) << 16)
-}
-
-fn enc_arith_rr_imm12(
-    bits_31_24: u32,
-    immshift: u32,
-    imm12: u32,
-    rn: Reg,
-    rd: Writable<Reg>,
-) -> u32 {
-    (bits_31_24 << 24)
-        | (immshift << 22)
-        | (imm12 << 10)
-        | (machreg_to_gpr(rn) << 5)
-        | machreg_to_gpr(rd.to_reg())
-}
-
-fn enc_arith_rr_imml(bits_31_23: u32, imm_bits: u32, rn: Reg, rd: Writable<Reg>) -> u32 {
-    (bits_31_23 << 23) | (imm_bits << 10) | (machreg_to_gpr(rn) << 5) | machreg_to_gpr(rd.to_reg())
-}
-
-fn enc_arith_rrrr(top11: u32, rm: Reg, bit15: u32, ra: Reg, rn: Reg, rd: Writable<Reg>) -> u32 {
-    (top11 << 21)
-        | (machreg_to_gpr(rm) << 16)
-        | (bit15 << 15)
-        | (machreg_to_gpr(ra) << 10)
-        | (machreg_to_gpr(rn) << 5)
-        | machreg_to_gpr(rd.to_reg())
-}
-
-fn enc_jump26(op_31_26: u32, off_26_0: u32) -> u32 {
-    assert!(off_26_0 < (1 << 26));
-    (op_31_26 << 26) | off_26_0
-}
-
-fn enc_cmpbr(op_31_24: u32, off_18_0: u32, reg: Reg) -> u32 {
-    assert!(off_18_0 < (1 << 19));
-    (op_31_24 << 24) | (off_18_0 << 5) | machreg_to_gpr(reg)
-}
-
-fn enc_cbr(op_31_24: u32, off_18_0: u32, op_4: u32, cond: u32) -> u32 {
-    assert!(off_18_0 < (1 << 19));
-    assert!(cond < (1 << 4));
-    (op_31_24 << 24) | (off_18_0 << 5) | (op_4 << 4) | cond
-}
-
-fn enc_conditional_br(taken: BranchTarget, kind: CondBrKind) -> u32 {
-    match kind {
-        CondBrKind::Zero(reg) => enc_cmpbr(0b1_011010_0, taken.as_offset19_or_zero(), reg),
-        CondBrKind::NotZero(reg) => enc_cmpbr(0b1_011010_1, taken.as_offset19_or_zero(), reg),
-        CondBrKind::Cond(c) => enc_cbr(0b01010100, taken.as_offset19_or_zero(), 0b0, c.bits()),
-    }
-}
-
-const MOVE_WIDE_FIXED: u32 = 0x12800000;
-
-#[repr(u32)]
-enum MoveWideOpcode {
-    MOVN = 0b00,
-    MOVZ = 0b10,
-    MOVK = 0b11,
-}
-
-fn enc_move_wide(
-    op: MoveWideOpcode,
-    rd: Writable<Reg>,
-    imm: MoveWideConst,
-    size: OperandSize,
-) -> u32 {
-    assert!(imm.shift <= 0b11);
-    MOVE_WIDE_FIXED
-        | size.sf_bit() << 31
-        | (op as u32) << 29
-        | u32::from(imm.shift) << 21
-        | u32::from(imm.bits) << 5
-        | machreg_to_gpr(rd.to_reg())
-}
-
-fn enc_ldst_pair(op_31_22: u32, simm7: SImm7Scaled, rn: Reg, rt: Reg, rt2: Reg) -> u32 {
-    (op_31_22 << 22)
-        | (simm7.bits() << 15)
-        | (machreg_to_gpr(rt2) << 10)
-        | (machreg_to_gpr(rn) << 5)
-        | machreg_to_gpr(rt)
-}
-
-fn enc_ldst_simm9(op_31_22: u32, simm9: SImm9, op_11_10: u32, rn: Reg, rd: Reg) -> u32 {
-    (op_31_22 << 22)
-        | (simm9.bits() << 12)
-        | (op_11_10 << 10)
-        | (machreg_to_gpr(rn) << 5)
-        | machreg_to_gpr_or_vec(rd)
-}
-
-fn enc_ldst_uimm12(op_31_22: u32, uimm12: UImm12Scaled, rn: Reg, rd: Reg) -> u32 {
-    (op_31_22 << 22)
-        | (0b1 << 24)
-        | (uimm12.bits() << 10)
-        | (machreg_to_gpr(rn) << 5)
-        | machreg_to_gpr_or_vec(rd)
-}
-
-fn enc_ldst_reg(
-    op_31_22: u32,
-    rn: Reg,
-    rm: Reg,
-    s_bit: bool,
-    extendop: Option<ExtendOp>,
-    rd: Reg,
-) -> u32 {
-    let s_bit = if s_bit { 1 } else { 0 };
-    let extend_bits = match extendop {
-        Some(ExtendOp::UXTW) => 0b010,
-        Some(ExtendOp::SXTW) => 0b110,
-        Some(ExtendOp::SXTX) => 0b111,
-        None => 0b011, // LSL
-        _ => panic!("bad extend mode for ld/st AMode"),
-    };
-    (op_31_22 << 22)
-        | (1 << 21)
-        | (machreg_to_gpr(rm) << 16)
-        | (extend_bits << 13)
-        | (s_bit << 12)
-        | (0b10 << 10)
-        | (machreg_to_gpr(rn) << 5)
-        | machreg_to_gpr_or_vec(rd)
-}
-
-pub(crate) fn enc_ldst_imm19(op_31_24: u32, imm19: u32, rd: Reg) -> u32 {
-    (op_31_24 << 24) | (imm19 << 5) | machreg_to_gpr_or_vec(rd)
-}
-
-fn enc_ldst_vec(q: u32, size: u32, rn: Reg, rt: Writable<Reg>) -> u32 {
-    debug_assert_eq!(q & 0b1, q);
-    debug_assert_eq!(size & 0b11, size);
-    0b0_0_0011010_10_00000_110_0_00_00000_00000
-        | q << 30
-        | size << 10
-        | machreg_to_gpr(rn) << 5
-        | machreg_to_vec(rt.to_reg())
-}
-
-fn enc_ldst_vec_pair(
-    opc: u32,
-    amode: u32,
-    is_load: bool,
-    simm7: SImm7Scaled,
-    rn: Reg,
-    rt: Reg,
-    rt2: Reg,
-) -> u32 {
-    debug_assert_eq!(opc & 0b11, opc);
-    debug_assert_eq!(amode & 0b11, amode);
-
-    0b00_10110_00_0_0000000_00000_00000_00000
-        | opc << 30
-        | amode << 23
-        | (is_load as u32) << 22
-        | simm7.bits() << 15
-        | machreg_to_vec(rt2) << 10
-        | machreg_to_gpr(rn) << 5
-        | machreg_to_vec(rt)
-}
-
-fn enc_vec_rrr(top11: u32, rm: Reg, bit15_10: u32, rn: Reg, rd: Writable<Reg>) -> u32 {
-    (top11 << 21)
-        | (machreg_to_vec(rm) << 16)
-        | (bit15_10 << 10)
-        | (machreg_to_vec(rn) << 5)
-        | machreg_to_vec(rd.to_reg())
-}
-
-fn enc_vec_rrr_long(
-    q: u32,
-    u: u32,
-    size: u32,
-    bit14: u32,
-    rm: Reg,
-    rn: Reg,
-    rd: Writable<Reg>,
-) -> u32 {
-    debug_assert_eq!(q & 0b1, q);
-    debug_assert_eq!(u & 0b1, u);
-    debug_assert_eq!(size & 0b11, size);
-    debug_assert_eq!(bit14 & 0b1, bit14);
-
-    0b0_0_0_01110_00_1_00000_100000_00000_00000
-        | q << 30
-        | u << 29
-        | size << 22
-        | bit14 << 14
-        | (machreg_to_vec(rm) << 16)
-        | (machreg_to_vec(rn) << 5)
-        | machreg_to_vec(rd.to_reg())
-}
-
-fn enc_bit_rr(size: u32, opcode2: u32, opcode1: u32, rn: Reg, rd: Writable<Reg>) -> u32 {
-    (0b01011010110 << 21)
-        | size << 31
-        | opcode2 << 16
-        | opcode1 << 10
-        | machreg_to_gpr(rn) << 5
-        | machreg_to_gpr(rd.to_reg())
-}
-
-pub(crate) fn enc_br(rn: Reg) -> u32 {
-    0b1101011_0000_11111_000000_00000_00000 | (machreg_to_gpr(rn) << 5)
-}
-
-pub(crate) fn enc_adr(off: i32, rd: Writable<Reg>) -> u32 {
-    let off = u32::try_from(off).unwrap();
-    let immlo = off & 3;
-    let immhi = (off >> 2) & ((1 << 19) - 1);
-    (0b00010000 << 24) | (immlo << 29) | (immhi << 5) | machreg_to_gpr(rd.to_reg())
-}
-
-fn enc_csel(rd: Writable<Reg>, rn: Reg, rm: Reg, cond: Cond) -> u32 {
-    0b100_11010100_00000_0000_00_00000_00000
-        | (machreg_to_gpr(rm) << 16)
-        | (machreg_to_gpr(rn) << 5)
-        | machreg_to_gpr(rd.to_reg())
-        | (cond.bits() << 12)
-}
-
-fn enc_fcsel(rd: Writable<Reg>, rn: Reg, rm: Reg, cond: Cond, size: ScalarSize) -> u32 {
-    0b000_11110_00_1_00000_0000_11_00000_00000
-        | (size.ftype() << 22)
-        | (machreg_to_vec(rm) << 16)
-        | (machreg_to_vec(rn) << 5)
-        | machreg_to_vec(rd.to_reg())
-        | (cond.bits() << 12)
-}
-
-fn enc_cset(rd: Writable<Reg>, cond: Cond) -> u32 {
-    0b100_11010100_11111_0000_01_11111_00000
-        | machreg_to_gpr(rd.to_reg())
-        | (cond.invert().bits() << 12)
-}
-
-fn enc_csetm(rd: Writable<Reg>, cond: Cond) -> u32 {
-    0b110_11010100_11111_0000_00_11111_00000
-        | machreg_to_gpr(rd.to_reg())
-        | (cond.invert().bits() << 12)
-}
-
-fn enc_ccmp_imm(size: OperandSize, rn: Reg, imm: UImm5, nzcv: NZCV, cond: Cond) -> u32 {
-    0b0_1_1_11010010_00000_0000_10_00000_0_0000
-        | size.sf_bit() << 31
-        | imm.bits() << 16
-        | cond.bits() << 12
-        | machreg_to_gpr(rn) << 5
-        | nzcv.bits()
-}
-
-fn enc_bfm(opc: u8, size: OperandSize, rd: Writable<Reg>, rn: Reg, immr: u8, imms: u8) -> u32 {
-    match size {
-        OperandSize::Size64 => {
-            debug_assert!(immr <= 63);
-            debug_assert!(imms <= 63);
-        }
-        OperandSize::Size32 => {
-            debug_assert!(immr <= 31);
-            debug_assert!(imms <= 31);
-        }
-    }
-    debug_assert_eq!(opc & 0b11, opc);
-    let n_bit = size.sf_bit();
-    0b0_00_100110_0_000000_000000_00000_00000
-        | size.sf_bit() << 31
-        | u32::from(opc) << 29
-        | n_bit << 22
-        | u32::from(immr) << 16
-        | u32::from(imms) << 10
-        | machreg_to_gpr(rn) << 5
-        | machreg_to_gpr(rd.to_reg())
-}
-
-fn enc_vecmov(is_16b: bool, rd: Writable<Reg>, rn: Reg) -> u32 {
-    0b00001110_101_00000_00011_1_00000_00000
-        | ((is_16b as u32) << 30)
-        | machreg_to_vec(rd.to_reg())
-        | (machreg_to_vec(rn) << 16)
-        | (machreg_to_vec(rn) << 5)
-}
-
-fn enc_fpurr(top22: u32, rd: Writable<Reg>, rn: Reg) -> u32 {
-    (top22 << 10) | (machreg_to_vec(rn) << 5) | machreg_to_vec(rd.to_reg())
-}
-
-fn enc_fpurrr(top22: u32, rd: Writable<Reg>, rn: Reg, rm: Reg) -> u32 {
-    (top22 << 10)
-        | (machreg_to_vec(rm) << 16)
-        | (machreg_to_vec(rn) << 5)
-        | machreg_to_vec(rd.to_reg())
-}
-
-fn enc_fpurrrr(top17: u32, rd: Writable<Reg>, rn: Reg, rm: Reg, ra: Reg) -> u32 {
-    (top17 << 15)
-        | (machreg_to_vec(rm) << 16)
-        | (machreg_to_vec(ra) << 10)
-        | (machreg_to_vec(rn) << 5)
-        | machreg_to_vec(rd.to_reg())
-}
-
-fn enc_fcmp(size: ScalarSize, rn: Reg, rm: Reg) -> u32 {
-    0b000_11110_00_1_00000_00_1000_00000_00000
-        | (size.ftype() << 22)
-        | (machreg_to_vec(rm) << 16)
-        | (machreg_to_vec(rn) << 5)
-}
-
-fn enc_fputoint(top16: u32, rd: Writable<Reg>, rn: Reg) -> u32 {
-    (top16 << 16) | (machreg_to_vec(rn) << 5) | machreg_to_gpr(rd.to_reg())
-}
-
-fn enc_inttofpu(top16: u32, rd: Writable<Reg>, rn: Reg) -> u32 {
-    (top16 << 16) | (machreg_to_gpr(rn) << 5) | machreg_to_vec(rd.to_reg())
-}
-
-fn enc_fround(top22: u32, rd: Writable<Reg>, rn: Reg) -> u32 {
-    (top22 << 10) | (machreg_to_vec(rn) << 5) | machreg_to_vec(rd.to_reg())
-}
-
-fn enc_vec_rr_misc(qu: u32, size: u32, bits_12_16: u32, rd: Writable<Reg>, rn: Reg) -> u32 {
-    debug_assert_eq!(qu & 0b11, qu);
-    debug_assert_eq!(size & 0b11, size);
-    debug_assert_eq!(bits_12_16 & 0b11111, bits_12_16);
-    let bits = 0b0_00_01110_00_10000_00000_10_00000_00000;
-    bits | qu << 29
-        | size << 22
-        | bits_12_16 << 12
-        | machreg_to_vec(rn) << 5
-        | machreg_to_vec(rd.to_reg())
-}
-
-fn enc_vec_rr_pair(bits_12_16: u32, rd: Writable<Reg>, rn: Reg) -> u32 {
-    debug_assert_eq!(bits_12_16 & 0b11111, bits_12_16);
-
-    0b010_11110_11_11000_11011_10_00000_00000
-        | bits_12_16 << 12
-        | machreg_to_vec(rn) << 5
-        | machreg_to_vec(rd.to_reg())
-}
-
-fn enc_vec_rr_pair_long(u: u32, enc_size: u32, rd: Writable<Reg>, rn: Reg) -> u32 {
-    debug_assert_eq!(u & 0b1, u);
-    debug_assert_eq!(enc_size & 0b1, enc_size);
-
-    0b0_1_0_01110_00_10000_00_0_10_10_00000_00000
-        | u << 29
-        | enc_size << 22
-        | machreg_to_vec(rn) << 5
-        | machreg_to_vec(rd.to_reg())
-}
-
-fn enc_vec_lanes(q: u32, u: u32, size: u32, opcode: u32, rd: Writable<Reg>, rn: Reg) -> u32 {
-    debug_assert_eq!(q & 0b1, q);
-    debug_assert_eq!(u & 0b1, u);
-    debug_assert_eq!(size & 0b11, size);
-    debug_assert_eq!(opcode & 0b11111, opcode);
-    0b0_0_0_01110_00_11000_0_0000_10_00000_00000
-        | q << 30
-        | u << 29
-        | size << 22
-        | opcode << 12
-        | machreg_to_vec(rn) << 5
-        | machreg_to_vec(rd.to_reg())
-}
-
-fn enc_tbl(is_extension: bool, len: u32, rd: Writable<Reg>, rn: Reg, rm: Reg) -> u32 {
-    debug_assert_eq!(len & 0b11, len);
-    0b0_1_001110_000_00000_0_00_0_00_00000_00000
-        | (machreg_to_vec(rm) << 16)
-        | len << 13
-        | (is_extension as u32) << 12
-        | (machreg_to_vec(rn) << 5)
-        | machreg_to_vec(rd.to_reg())
-}
-
-fn enc_dmb_ish() -> u32 {
-    0xD5033BBF
-}
-
-fn enc_ldal(ty: Type, op: AtomicRMWOp, rs: Reg, rt: Writable<Reg>, rn: Reg) -> u32 {
-    assert!(machreg_to_gpr(rt.to_reg()) != 31);
-    let sz = match ty {
-        I64 => 0b11,
-        I32 => 0b10,
-        I16 => 0b01,
-        I8 => 0b00,
-        _ => unreachable!(),
-    };
-    let op = match op {
-        AtomicRMWOp::Add => 0b000,
-        AtomicRMWOp::Clr => 0b001,
-        AtomicRMWOp::Eor => 0b010,
-        AtomicRMWOp::Set => 0b011,
-        AtomicRMWOp::Smax => 0b100,
-        AtomicRMWOp::Smin => 0b101,
-        AtomicRMWOp::Umax => 0b110,
-        AtomicRMWOp::Umin => 0b111,
-    };
-    0b00_111_000_111_00000_0_000_00_00000_00000
-        | (sz << 30)
-        | (machreg_to_gpr(rs) << 16)
-        | (op << 12)
-        | (machreg_to_gpr(rn) << 5)
-        | machreg_to_gpr(rt.to_reg())
-}
-
-fn enc_ldar(ty: Type, rt: Writable<Reg>, rn: Reg) -> u32 {
-    let sz = match ty {
-        I64 => 0b11,
-        I32 => 0b10,
-        I16 => 0b01,
-        I8 => 0b00,
-        _ => unreachable!(),
-    };
-    0b00_001000_1_1_0_11111_1_11111_00000_00000
-        | (sz << 30)
-        | (machreg_to_gpr(rn) << 5)
-        | machreg_to_gpr(rt.to_reg())
-}
-
-fn enc_stlr(ty: Type, rt: Reg, rn: Reg) -> u32 {
-    let sz = match ty {
-        I64 => 0b11,
-        I32 => 0b10,
-        I16 => 0b01,
-        I8 => 0b00,
-        _ => unreachable!(),
-    };
-    0b00_001000_100_11111_1_11111_00000_00000
-        | (sz << 30)
-        | (machreg_to_gpr(rn) << 5)
-        | machreg_to_gpr(rt)
-}
-
-fn enc_ldaxr(ty: Type, rt: Writable<Reg>, rn: Reg) -> u32 {
-    let sz = match ty {
-        I64 => 0b11,
-        I32 => 0b10,
-        I16 => 0b01,
-        I8 => 0b00,
-        _ => unreachable!(),
-    };
-    0b00_001000_0_1_0_11111_1_11111_00000_00000
-        | (sz << 30)
-        | (machreg_to_gpr(rn) << 5)
-        | machreg_to_gpr(rt.to_reg())
-}
-
-fn enc_stlxr(ty: Type, rs: Writable<Reg>, rt: Reg, rn: Reg) -> u32 {
-    let sz = match ty {
-        I64 => 0b11,
-        I32 => 0b10,
-        I16 => 0b01,
-        I8 => 0b00,
-        _ => unreachable!(),
-    };
-    0b00_001000_000_00000_1_11111_00000_00000
-        | (sz << 30)
-        | (machreg_to_gpr(rs.to_reg()) << 16)
-        | (machreg_to_gpr(rn) << 5)
-        | machreg_to_gpr(rt)
-}
-
-fn enc_cas(size: u32, rs: Writable<Reg>, rt: Reg, rn: Reg) -> u32 {
-    debug_assert_eq!(size & 0b11, size);
-
-    0b00_0010001_1_1_00000_1_11111_00000_00000
-        | size << 30
-        | machreg_to_gpr(rs.to_reg()) << 16
-        | machreg_to_gpr(rn) << 5
-        | machreg_to_gpr(rt)
-}
-
-fn enc_asimd_mod_imm(rd: Writable<Reg>, q_op: u32, cmode: u32, imm: u8) -> u32 {
-    let abc = (imm >> 5) as u32;
-    let defgh = (imm & 0b11111) as u32;
-
-    debug_assert_eq!(cmode & 0b1111, cmode);
-    debug_assert_eq!(q_op & 0b11, q_op);
-
-    0b0_0_0_0111100000_000_0000_01_00000_00000
-        | (q_op << 29)
-        | (abc << 16)
-        | (cmode << 12)
-        | (defgh << 5)
-        | machreg_to_vec(rd.to_reg())
-}
-
-/// State carried between emissions of a sequence of instructions.
-#[derive(Default, Clone, Debug)]
-pub struct EmitState {
-    /// Addend to convert nominal-SP offsets to real-SP offsets at the current
-    /// program point.
-    pub(crate) virtual_sp_offset: i64,
-    /// Offset of FP from nominal-SP.
-    pub(crate) nominal_sp_to_fp: i64,
-    /// Safepoint stack map for upcoming instruction, as provided to `pre_safepoint()`.
-    stack_map: Option<StackMap>,
-    /// Current source-code location corresponding to instruction to be emitted.
-    cur_srcloc: SourceLoc,
-}
-
-impl MachInstEmitState<Inst> for EmitState {
-    fn new(abi: &dyn ABICallee<I = Inst>) -> Self {
-        EmitState {
-            virtual_sp_offset: 0,
-            nominal_sp_to_fp: abi.frame_size() as i64,
-            stack_map: None,
-            cur_srcloc: SourceLoc::default(),
-        }
-    }
-
-    fn pre_safepoint(&mut self, stack_map: StackMap) {
-        self.stack_map = Some(stack_map);
-    }
-
-    fn pre_sourceloc(&mut self, srcloc: SourceLoc) {
-        self.cur_srcloc = srcloc;
-    }
-}
-
-impl EmitState {
-    fn take_stack_map(&mut self) -> Option<StackMap> {
-        self.stack_map.take()
-    }
-
-    fn clear_post_insn(&mut self) {
-        self.stack_map = None;
-    }
-
-    fn cur_srcloc(&self) -> SourceLoc {
-        self.cur_srcloc
-    }
-}
-
-/// Constant state used during function compilation.
-pub struct EmitInfo(settings::Flags);
-
-impl EmitInfo {
-    pub(crate) fn new(flags: settings::Flags) -> Self {
-        Self(flags)
-    }
-}
-
-impl MachInstEmit for Inst {
-    type State = EmitState;
-    type Info = EmitInfo;
-
-    fn emit(&self, sink: &mut MachBuffer<Inst>, emit_info: &Self::Info, state: &mut EmitState) {
-        // N.B.: we *must* not exceed the "worst-case size" used to compute
-        // where to insert islands, except when islands are explicitly triggered
-        // (with an `EmitIsland`). We check this in debug builds. This is `mut`
-        // to allow disabling the check for `JTSequence`, which is always
-        // emitted following an `EmitIsland`.
-        let mut start_off = sink.cur_offset();
-
-        match self {
-            &Inst::AluRRR {
-                alu_op,
-                size,
-                rd,
-                rn,
-                rm,
-            } => {
-                debug_assert!(match alu_op {
-                    ALUOp::SDiv | ALUOp::UDiv | ALUOp::SMulH | ALUOp::UMulH =>
-                        size == OperandSize::Size64,
-                    _ => true,
-                });
-                let top11 = match alu_op {
-                    ALUOp::Add => 0b00001011_000,
-                    ALUOp::Adc => 0b00011010_000,
-                    ALUOp::AdcS => 0b00111010_000,
-                    ALUOp::Sub => 0b01001011_000,
-                    ALUOp::Sbc => 0b01011010_000,
-                    ALUOp::SbcS => 0b01111010_000,
-                    ALUOp::Orr => 0b00101010_000,
-                    ALUOp::And => 0b00001010_000,
-                    ALUOp::AndS => 0b01101010_000,
-                    ALUOp::Eor => 0b01001010_000,
-                    ALUOp::OrrNot => 0b00101010_001,
-                    ALUOp::AndNot => 0b00001010_001,
-                    ALUOp::EorNot => 0b01001010_001,
-                    ALUOp::AddS => 0b00101011_000,
-                    ALUOp::SubS => 0b01101011_000,
-                    ALUOp::SDiv => 0b10011010_110,
-                    ALUOp::UDiv => 0b10011010_110,
-                    ALUOp::RotR | ALUOp::Lsr | ALUOp::Asr | ALUOp::Lsl => 0b00011010_110,
-                    ALUOp::SMulH => 0b10011011_010,
-                    ALUOp::UMulH => 0b10011011_110,
-                };
-                let top11 = top11 | size.sf_bit() << 10;
-                let bit15_10 = match alu_op {
-                    ALUOp::SDiv => 0b000011,
-                    ALUOp::UDiv => 0b000010,
-                    ALUOp::RotR => 0b001011,
-                    ALUOp::Lsr => 0b001001,
-                    ALUOp::Asr => 0b001010,
-                    ALUOp::Lsl => 0b001000,
-                    ALUOp::SMulH | ALUOp::UMulH => 0b011111,
-                    _ => 0b000000,
-                };
-                debug_assert_ne!(writable_stack_reg(), rd);
-                // The stack pointer is the zero register in this context, so this might be an
-                // indication that something is wrong.
-                debug_assert_ne!(stack_reg(), rn);
-                debug_assert_ne!(stack_reg(), rm);
-                sink.put4(enc_arith_rrr(top11, bit15_10, rd, rn, rm));
-            }
-            &Inst::AluRRRR {
-                alu_op,
-                rd,
-                rm,
-                rn,
-                ra,
-            } => {
-                let (top11, bit15) = match alu_op {
-                    ALUOp3::MAdd32 => (0b0_00_11011_000, 0),
-                    ALUOp3::MSub32 => (0b0_00_11011_000, 1),
-                    ALUOp3::MAdd64 => (0b1_00_11011_000, 0),
-                    ALUOp3::MSub64 => (0b1_00_11011_000, 1),
-                };
-                sink.put4(enc_arith_rrrr(top11, rm, bit15, ra, rn, rd));
-            }
-            &Inst::AluRRImm12 {
-                alu_op,
-                size,
-                rd,
-                rn,
-                ref imm12,
-            } => {
-                let top8 = match alu_op {
-                    ALUOp::Add => 0b000_10001,
-                    ALUOp::Sub => 0b010_10001,
-                    ALUOp::AddS => 0b001_10001,
-                    ALUOp::SubS => 0b011_10001,
-                    _ => unimplemented!("{:?}", alu_op),
-                };
-                let top8 = top8 | size.sf_bit() << 7;
-                sink.put4(enc_arith_rr_imm12(
-                    top8,
-                    imm12.shift_bits(),
-                    imm12.imm_bits(),
-                    rn,
-                    rd,
-                ));
-            }
-            &Inst::AluRRImmLogic {
-                alu_op,
-                size,
-                rd,
-                rn,
-                ref imml,
-            } => {
-                let (top9, inv) = match alu_op {
-                    ALUOp::Orr => (0b001_100100, false),
-                    ALUOp::And => (0b000_100100, false),
-                    ALUOp::AndS => (0b011_100100, false),
-                    ALUOp::Eor => (0b010_100100, false),
-                    ALUOp::OrrNot => (0b001_100100, true),
-                    ALUOp::AndNot => (0b000_100100, true),
-                    ALUOp::EorNot => (0b010_100100, true),
-                    _ => unimplemented!("{:?}", alu_op),
-                };
-                let top9 = top9 | size.sf_bit() << 8;
-                let imml = if inv { imml.invert() } else { imml.clone() };
-                sink.put4(enc_arith_rr_imml(top9, imml.enc_bits(), rn, rd));
-            }
-
-            &Inst::AluRRImmShift {
-                alu_op,
-                size,
-                rd,
-                rn,
-                ref immshift,
-            } => {
-                let amt = immshift.value();
-                let (top10, immr, imms) = match alu_op {
-                    ALUOp::RotR => (0b0001001110, machreg_to_gpr(rn), u32::from(amt)),
-                    ALUOp::Lsr => (0b0101001100, u32::from(amt), 0b011111),
-                    ALUOp::Asr => (0b0001001100, u32::from(amt), 0b011111),
-                    ALUOp::Lsl => {
-                        let bits = if size.is64() { 64 } else { 32 };
-                        (
-                            0b0101001100,
-                            u32::from((bits - amt) % bits),
-                            u32::from(bits - 1 - amt),
-                        )
-                    }
-                    _ => unimplemented!("{:?}", alu_op),
-                };
-                let top10 = top10 | size.sf_bit() << 9 | size.sf_bit();
-                let imms = match alu_op {
-                    ALUOp::Lsr | ALUOp::Asr => imms | size.sf_bit() << 5,
-                    _ => imms,
-                };
-                sink.put4(
-                    (top10 << 22)
-                        | (immr << 16)
-                        | (imms << 10)
-                        | (machreg_to_gpr(rn) << 5)
-                        | machreg_to_gpr(rd.to_reg()),
-                );
-            }
-
-            &Inst::AluRRRShift {
-                alu_op,
-                size,
-                rd,
-                rn,
-                rm,
-                ref shiftop,
-            } => {
-                let top11: u32 = match alu_op {
-                    ALUOp::Add => 0b000_01011000,
-                    ALUOp::AddS => 0b001_01011000,
-                    ALUOp::Sub => 0b010_01011000,
-                    ALUOp::SubS => 0b011_01011000,
-                    ALUOp::Orr => 0b001_01010000,
-                    ALUOp::And => 0b000_01010000,
-                    ALUOp::AndS => 0b011_01010000,
-                    ALUOp::Eor => 0b010_01010000,
-                    ALUOp::OrrNot => 0b001_01010001,
-                    ALUOp::EorNot => 0b010_01010001,
-                    ALUOp::AndNot => 0b000_01010001,
-                    _ => unimplemented!("{:?}", alu_op),
-                };
-                let top11 = top11 | size.sf_bit() << 10;
-                let top11 = top11 | (u32::from(shiftop.op().bits()) << 1);
-                let bits_15_10 = u32::from(shiftop.amt().value());
-                sink.put4(enc_arith_rrr(top11, bits_15_10, rd, rn, rm));
-            }
-
-            &Inst::AluRRRExtend {
-                alu_op,
-                size,
-                rd,
-                rn,
-                rm,
-                extendop,
-            } => {
-                let top11: u32 = match alu_op {
-                    ALUOp::Add => 0b00001011001,
-                    ALUOp::Sub => 0b01001011001,
-                    ALUOp::AddS => 0b00101011001,
-                    ALUOp::SubS => 0b01101011001,
-                    _ => unimplemented!("{:?}", alu_op),
-                };
-                let top11 = top11 | size.sf_bit() << 10;
-                let bits_15_10 = u32::from(extendop.bits()) << 3;
-                sink.put4(enc_arith_rrr(top11, bits_15_10, rd, rn, rm));
-            }
-
-            &Inst::BitRR {
-                op, size, rd, rn, ..
-            } => {
-                let (op1, op2) = match op {
-                    BitOp::RBit => (0b00000, 0b000000),
-                    BitOp::Clz => (0b00000, 0b000100),
-                    BitOp::Cls => (0b00000, 0b000101),
-                };
-                sink.put4(enc_bit_rr(size.sf_bit(), op1, op2, rn, rd))
-            }
-
-            &Inst::ULoad8 { rd, ref mem, flags }
-            | &Inst::SLoad8 { rd, ref mem, flags }
-            | &Inst::ULoad16 { rd, ref mem, flags }
-            | &Inst::SLoad16 { rd, ref mem, flags }
-            | &Inst::ULoad32 { rd, ref mem, flags }
-            | &Inst::SLoad32 { rd, ref mem, flags }
-            | &Inst::ULoad64 {
-                rd, ref mem, flags, ..
-            }
-            | &Inst::FpuLoad32 { rd, ref mem, flags }
-            | &Inst::FpuLoad64 { rd, ref mem, flags }
-            | &Inst::FpuLoad128 { rd, ref mem, flags } => {
-                let (mem_insts, mem) = mem_finalize(sink.cur_offset(), mem, state);
-
-                for inst in mem_insts.into_iter() {
-                    inst.emit(sink, emit_info, state);
-                }
-
-                // ldst encoding helpers take Reg, not Writable<Reg>.
-                let rd = rd.to_reg();
-
-                // This is the base opcode (top 10 bits) for the "unscaled
-                // immediate" form (Unscaled). Other addressing modes will OR in
-                // other values for bits 24/25 (bits 1/2 of this constant).
-                let (op, bits) = match self {
-                    &Inst::ULoad8 { .. } => (0b0011100001, 8),
-                    &Inst::SLoad8 { .. } => (0b0011100010, 8),
-                    &Inst::ULoad16 { .. } => (0b0111100001, 16),
-                    &Inst::SLoad16 { .. } => (0b0111100010, 16),
-                    &Inst::ULoad32 { .. } => (0b1011100001, 32),
-                    &Inst::SLoad32 { .. } => (0b1011100010, 32),
-                    &Inst::ULoad64 { .. } => (0b1111100001, 64),
-                    &Inst::FpuLoad32 { .. } => (0b1011110001, 32),
-                    &Inst::FpuLoad64 { .. } => (0b1111110001, 64),
-                    &Inst::FpuLoad128 { .. } => (0b0011110011, 128),
-                    _ => unreachable!(),
-                };
-
-                let srcloc = state.cur_srcloc();
-                if srcloc != SourceLoc::default() && !flags.notrap() {
-                    // Register the offset at which the actual load instruction starts.
-                    sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
-                }
-
-                match &mem {
-                    &AMode::Unscaled(reg, simm9) => {
-                        sink.put4(enc_ldst_simm9(op, simm9, 0b00, reg, rd));
-                    }
-                    &AMode::UnsignedOffset(reg, uimm12scaled) => {
-                        if uimm12scaled.value() != 0 {
-                            assert_eq!(bits, ty_bits(uimm12scaled.scale_ty()));
-                        }
-                        sink.put4(enc_ldst_uimm12(op, uimm12scaled, reg, rd));
-                    }
-                    &AMode::RegReg(r1, r2) => {
-                        sink.put4(enc_ldst_reg(
-                            op, r1, r2, /* scaled = */ false, /* extendop = */ None, rd,
-                        ));
-                    }
-                    &AMode::RegScaled(r1, r2, ty) | &AMode::RegScaledExtended(r1, r2, ty, _) => {
-                        assert_eq!(bits, ty_bits(ty));
-                        let extendop = match &mem {
-                            &AMode::RegScaled(..) => None,
-                            &AMode::RegScaledExtended(_, _, _, op) => Some(op),
-                            _ => unreachable!(),
-                        };
-                        sink.put4(enc_ldst_reg(
-                            op, r1, r2, /* scaled = */ true, extendop, rd,
-                        ));
-                    }
-                    &AMode::RegExtended(r1, r2, extendop) => {
-                        sink.put4(enc_ldst_reg(
-                            op,
-                            r1,
-                            r2,
-                            /* scaled = */ false,
-                            Some(extendop),
-                            rd,
-                        ));
-                    }
-                    &AMode::Label(ref label) => {
-                        let offset = match label {
-                            // cast i32 to u32 (two's-complement)
-                            &MemLabel::PCRel(off) => off as u32,
-                        } / 4;
-                        assert!(offset < (1 << 19));
-                        match self {
-                            &Inst::ULoad32 { .. } => {
-                                sink.put4(enc_ldst_imm19(0b00011000, offset, rd));
-                            }
-                            &Inst::SLoad32 { .. } => {
-                                sink.put4(enc_ldst_imm19(0b10011000, offset, rd));
-                            }
-                            &Inst::FpuLoad32 { .. } => {
-                                sink.put4(enc_ldst_imm19(0b00011100, offset, rd));
-                            }
-                            &Inst::ULoad64 { .. } => {
-                                sink.put4(enc_ldst_imm19(0b01011000, offset, rd));
-                            }
-                            &Inst::FpuLoad64 { .. } => {
-                                sink.put4(enc_ldst_imm19(0b01011100, offset, rd));
-                            }
-                            &Inst::FpuLoad128 { .. } => {
-                                sink.put4(enc_ldst_imm19(0b10011100, offset, rd));
-                            }
-                            _ => panic!("Unspported size for LDR from constant pool!"),
-                        }
-                    }
-                    &AMode::PreIndexed(reg, simm9) => {
-                        sink.put4(enc_ldst_simm9(op, simm9, 0b11, reg.to_reg(), rd));
-                    }
-                    &AMode::PostIndexed(reg, simm9) => {
-                        sink.put4(enc_ldst_simm9(op, simm9, 0b01, reg.to_reg(), rd));
-                    }
-                    // Eliminated by `mem_finalize()` above.
-                    &AMode::SPOffset(..) | &AMode::FPOffset(..) | &AMode::NominalSPOffset(..) => {
-                        panic!("Should not see stack-offset here!")
-                    }
-                    &AMode::RegOffset(..) => panic!("SHould not see generic reg-offset here!"),
-                }
-            }
-
-            &Inst::Store8 { rd, ref mem, flags }
-            | &Inst::Store16 { rd, ref mem, flags }
-            | &Inst::Store32 { rd, ref mem, flags }
-            | &Inst::Store64 { rd, ref mem, flags }
-            | &Inst::FpuStore32 { rd, ref mem, flags }
-            | &Inst::FpuStore64 { rd, ref mem, flags }
-            | &Inst::FpuStore128 { rd, ref mem, flags } => {
-                let (mem_insts, mem) = mem_finalize(sink.cur_offset(), mem, state);
-
-                for inst in mem_insts.into_iter() {
-                    inst.emit(sink, emit_info, state);
-                }
-
-                let (op, bits) = match self {
-                    &Inst::Store8 { .. } => (0b0011100000, 8),
-                    &Inst::Store16 { .. } => (0b0111100000, 16),
-                    &Inst::Store32 { .. } => (0b1011100000, 32),
-                    &Inst::Store64 { .. } => (0b1111100000, 64),
-                    &Inst::FpuStore32 { .. } => (0b1011110000, 32),
-                    &Inst::FpuStore64 { .. } => (0b1111110000, 64),
-                    &Inst::FpuStore128 { .. } => (0b0011110010, 128),
-                    _ => unreachable!(),
-                };
-
-                let srcloc = state.cur_srcloc();
-                if srcloc != SourceLoc::default() && !flags.notrap() {
-                    // Register the offset at which the actual store instruction starts.
-                    sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
-                }
-
-                match &mem {
-                    &AMode::Unscaled(reg, simm9) => {
-                        sink.put4(enc_ldst_simm9(op, simm9, 0b00, reg, rd));
-                    }
-                    &AMode::UnsignedOffset(reg, uimm12scaled) => {
-                        if uimm12scaled.value() != 0 {
-                            assert_eq!(bits, ty_bits(uimm12scaled.scale_ty()));
-                        }
-                        sink.put4(enc_ldst_uimm12(op, uimm12scaled, reg, rd));
-                    }
-                    &AMode::RegReg(r1, r2) => {
-                        sink.put4(enc_ldst_reg(
-                            op, r1, r2, /* scaled = */ false, /* extendop = */ None, rd,
-                        ));
-                    }
-                    &AMode::RegScaled(r1, r2, _ty) | &AMode::RegScaledExtended(r1, r2, _ty, _) => {
-                        let extendop = match &mem {
-                            &AMode::RegScaled(..) => None,
-                            &AMode::RegScaledExtended(_, _, _, op) => Some(op),
-                            _ => unreachable!(),
-                        };
-                        sink.put4(enc_ldst_reg(
-                            op, r1, r2, /* scaled = */ true, extendop, rd,
-                        ));
-                    }
-                    &AMode::RegExtended(r1, r2, extendop) => {
-                        sink.put4(enc_ldst_reg(
-                            op,
-                            r1,
-                            r2,
-                            /* scaled = */ false,
-                            Some(extendop),
-                            rd,
-                        ));
-                    }
-                    &AMode::Label(..) => {
-                        panic!("Store to a MemLabel not implemented!");
-                    }
-                    &AMode::PreIndexed(reg, simm9) => {
-                        sink.put4(enc_ldst_simm9(op, simm9, 0b11, reg.to_reg(), rd));
-                    }
-                    &AMode::PostIndexed(reg, simm9) => {
-                        sink.put4(enc_ldst_simm9(op, simm9, 0b01, reg.to_reg(), rd));
-                    }
-                    // Eliminated by `mem_finalize()` above.
-                    &AMode::SPOffset(..) | &AMode::FPOffset(..) | &AMode::NominalSPOffset(..) => {
-                        panic!("Should not see stack-offset here!")
-                    }
-                    &AMode::RegOffset(..) => panic!("SHould not see generic reg-offset here!"),
-                }
-            }
-
-            &Inst::StoreP64 {
-                rt,
-                rt2,
-                ref mem,
-                flags,
-            } => {
-                let srcloc = state.cur_srcloc();
-                if srcloc != SourceLoc::default() && !flags.notrap() {
-                    // Register the offset at which the actual store instruction starts.
-                    sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
-                }
-                match mem {
-                    &PairAMode::SignedOffset(reg, simm7) => {
-                        assert_eq!(simm7.scale_ty, I64);
-                        sink.put4(enc_ldst_pair(0b1010100100, simm7, reg, rt, rt2));
-                    }
-                    &PairAMode::PreIndexed(reg, simm7) => {
-                        assert_eq!(simm7.scale_ty, I64);
-                        sink.put4(enc_ldst_pair(0b1010100110, simm7, reg.to_reg(), rt, rt2));
-                    }
-                    &PairAMode::PostIndexed(reg, simm7) => {
-                        assert_eq!(simm7.scale_ty, I64);
-                        sink.put4(enc_ldst_pair(0b1010100010, simm7, reg.to_reg(), rt, rt2));
-                    }
-                }
-            }
-            &Inst::LoadP64 {
-                rt,
-                rt2,
-                ref mem,
-                flags,
-            } => {
-                let srcloc = state.cur_srcloc();
-                if srcloc != SourceLoc::default() && !flags.notrap() {
-                    // Register the offset at which the actual load instruction starts.
-                    sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
-                }
-
-                let rt = rt.to_reg();
-                let rt2 = rt2.to_reg();
-                match mem {
-                    &PairAMode::SignedOffset(reg, simm7) => {
-                        assert_eq!(simm7.scale_ty, I64);
-                        sink.put4(enc_ldst_pair(0b1010100101, simm7, reg, rt, rt2));
-                    }
-                    &PairAMode::PreIndexed(reg, simm7) => {
-                        assert_eq!(simm7.scale_ty, I64);
-                        sink.put4(enc_ldst_pair(0b1010100111, simm7, reg.to_reg(), rt, rt2));
-                    }
-                    &PairAMode::PostIndexed(reg, simm7) => {
-                        assert_eq!(simm7.scale_ty, I64);
-                        sink.put4(enc_ldst_pair(0b1010100011, simm7, reg.to_reg(), rt, rt2));
-                    }
-                }
-            }
-            &Inst::FpuLoadP64 {
-                rt,
-                rt2,
-                ref mem,
-                flags,
-            }
-            | &Inst::FpuLoadP128 {
-                rt,
-                rt2,
-                ref mem,
-                flags,
-            } => {
-                let srcloc = state.cur_srcloc();
-
-                if srcloc != SourceLoc::default() && !flags.notrap() {
-                    // Register the offset at which the actual load instruction starts.
-                    sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
-                }
-
-                let opc = match self {
-                    &Inst::FpuLoadP64 { .. } => 0b01,
-                    &Inst::FpuLoadP128 { .. } => 0b10,
-                    _ => unreachable!(),
-                };
-                let rt = rt.to_reg();
-                let rt2 = rt2.to_reg();
-
-                match mem {
-                    &PairAMode::SignedOffset(reg, simm7) => {
-                        assert!(simm7.scale_ty == F64 || simm7.scale_ty == I8X16);
-                        sink.put4(enc_ldst_vec_pair(opc, 0b10, true, simm7, reg, rt, rt2));
-                    }
-                    &PairAMode::PreIndexed(reg, simm7) => {
-                        assert!(simm7.scale_ty == F64 || simm7.scale_ty == I8X16);
-                        sink.put4(enc_ldst_vec_pair(
-                            opc,
-                            0b11,
-                            true,
-                            simm7,
-                            reg.to_reg(),
-                            rt,
-                            rt2,
-                        ));
-                    }
-                    &PairAMode::PostIndexed(reg, simm7) => {
-                        assert!(simm7.scale_ty == F64 || simm7.scale_ty == I8X16);
-                        sink.put4(enc_ldst_vec_pair(
-                            opc,
-                            0b01,
-                            true,
-                            simm7,
-                            reg.to_reg(),
-                            rt,
-                            rt2,
-                        ));
-                    }
-                }
-            }
-            &Inst::FpuStoreP64 {
-                rt,
-                rt2,
-                ref mem,
-                flags,
-            }
-            | &Inst::FpuStoreP128 {
-                rt,
-                rt2,
-                ref mem,
-                flags,
-            } => {
-                let srcloc = state.cur_srcloc();
-
-                if srcloc != SourceLoc::default() && !flags.notrap() {
-                    // Register the offset at which the actual store instruction starts.
-                    sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
-                }
-
-                let opc = match self {
-                    &Inst::FpuStoreP64 { .. } => 0b01,
-                    &Inst::FpuStoreP128 { .. } => 0b10,
-                    _ => unreachable!(),
-                };
-
-                match mem {
-                    &PairAMode::SignedOffset(reg, simm7) => {
-                        assert!(simm7.scale_ty == F64 || simm7.scale_ty == I8X16);
-                        sink.put4(enc_ldst_vec_pair(opc, 0b10, false, simm7, reg, rt, rt2));
-                    }
-                    &PairAMode::PreIndexed(reg, simm7) => {
-                        assert!(simm7.scale_ty == F64 || simm7.scale_ty == I8X16);
-                        sink.put4(enc_ldst_vec_pair(
-                            opc,
-                            0b11,
-                            false,
-                            simm7,
-                            reg.to_reg(),
-                            rt,
-                            rt2,
-                        ));
-                    }
-                    &PairAMode::PostIndexed(reg, simm7) => {
-                        assert!(simm7.scale_ty == F64 || simm7.scale_ty == I8X16);
-                        sink.put4(enc_ldst_vec_pair(
-                            opc,
-                            0b01,
-                            false,
-                            simm7,
-                            reg.to_reg(),
-                            rt,
-                            rt2,
-                        ));
-                    }
-                }
-            }
-            &Inst::Mov64 { rd, rm } => {
-                assert!(rd.to_reg().get_class() == rm.get_class());
-                assert!(rm.get_class() == RegClass::I64);
-
-                // MOV to SP is interpreted as MOV to XZR instead. And our codegen
-                // should never MOV to XZR.
-                assert!(rd.to_reg() != stack_reg());
-
-                if rm == stack_reg() {
-                    // We can't use ORR here, so use an `add rd, sp, #0` instead.
-                    let imm12 = Imm12::maybe_from_u64(0).unwrap();
-                    sink.put4(enc_arith_rr_imm12(
-                        0b100_10001,
-                        imm12.shift_bits(),
-                        imm12.imm_bits(),
-                        rm,
-                        rd,
-                    ));
-                } else {
-                    // Encoded as ORR rd, rm, zero.
-                    sink.put4(enc_arith_rrr(0b10101010_000, 0b000_000, rd, zero_reg(), rm));
-                }
-            }
-            &Inst::Mov32 { rd, rm } => {
-                // MOV to SP is interpreted as MOV to XZR instead. And our codegen
-                // should never MOV to XZR.
-                assert!(machreg_to_gpr(rd.to_reg()) != 31);
-                // Encoded as ORR rd, rm, zero.
-                sink.put4(enc_arith_rrr(0b00101010_000, 0b000_000, rd, zero_reg(), rm));
-            }
-            &Inst::MovZ { rd, imm, size } => {
-                sink.put4(enc_move_wide(MoveWideOpcode::MOVZ, rd, imm, size))
-            }
-            &Inst::MovN { rd, imm, size } => {
-                sink.put4(enc_move_wide(MoveWideOpcode::MOVN, rd, imm, size))
-            }
-            &Inst::MovK { rd, imm, size } => {
-                sink.put4(enc_move_wide(MoveWideOpcode::MOVK, rd, imm, size))
-            }
-            &Inst::CSel { rd, rn, rm, cond } => {
-                sink.put4(enc_csel(rd, rn, rm, cond));
-            }
-            &Inst::CSet { rd, cond } => {
-                sink.put4(enc_cset(rd, cond));
-            }
-            &Inst::CSetm { rd, cond } => {
-                sink.put4(enc_csetm(rd, cond));
-            }
-            &Inst::CCmpImm {
-                size,
-                rn,
-                imm,
-                nzcv,
-                cond,
-            } => {
-                sink.put4(enc_ccmp_imm(size, rn, imm, nzcv, cond));
-            }
-            &Inst::AtomicRMW { ty, op, rs, rt, rn } => {
-                sink.put4(enc_ldal(ty, op, rs, rt, rn));
-            }
-            &Inst::AtomicRMWLoop { ty, op } => {
-                /* Emit this:
-                     again:
-                      ldaxr{,b,h}  x/w27, [x25]
-                      op          x28, x27, x26 // op is add,sub,and,orr,eor
-                      stlxr{,b,h}  w24, x/w28, [x25]
-                      cbnz        x24, again
-
-                   Operand conventions:
-                      IN:  x25 (addr), x26 (2nd arg for op)
-                      OUT: x27 (old value), x24 (trashed), x28 (trashed)
-
-                   It is unfortunate that, per the ARM documentation, x28 cannot be used for
-                   both the store-data and success-flag operands of stlxr.  This causes the
-                   instruction's behaviour to be "CONSTRAINED UNPREDICTABLE", so we use x24
-                   instead for the success-flag.
-                */
-                // TODO: We should not hardcode registers here, a better idea would be to
-                // pass some scratch registers in the AtomicRMWLoop pseudo-instruction, and use those
-                let xzr = zero_reg();
-                let x24 = xreg(24);
-                let x25 = xreg(25);
-                let x26 = xreg(26);
-                let x27 = xreg(27);
-                let x28 = xreg(28);
-                let x24wr = writable_xreg(24);
-                let x27wr = writable_xreg(27);
-                let x28wr = writable_xreg(28);
-                let again_label = sink.get_label();
-
-                // again:
-                sink.bind_label(again_label);
-                let srcloc = state.cur_srcloc();
-                if srcloc != SourceLoc::default() {
-                    sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
-                }
-                sink.put4(enc_ldaxr(ty, x27wr, x25)); // ldaxr x27, [x25]
-                let size = OperandSize::from_ty(ty);
-
-                match op {
-                    AtomicRmwOp::Xchg => {} // do nothing
-                    AtomicRmwOp::Nand => {
-                        // and x28, x27, x26
-                        // mvn x28, x28
-
-                        Inst::AluRRR {
-                            alu_op: ALUOp::And,
-                            size,
-                            rd: x28wr,
-                            rn: x27,
-                            rm: x26,
-                        }
-                        .emit(sink, emit_info, state);
-
-                        Inst::AluRRR {
-                            alu_op: ALUOp::OrrNot,
-                            size,
-                            rd: x28wr,
-                            rn: xzr,
-                            rm: x28,
-                        }
-                        .emit(sink, emit_info, state);
-                    }
-                    AtomicRmwOp::Umin
-                    | AtomicRmwOp::Umax
-                    | AtomicRmwOp::Smin
-                    | AtomicRmwOp::Smax => {
-                        // cmp x27, x26
-                        // csel.op x28, x27, x26
-
-                        let cond = match op {
-                            AtomicRmwOp::Umin => Cond::Lo,
-                            AtomicRmwOp::Umax => Cond::Hi,
-                            AtomicRmwOp::Smin => Cond::Lt,
-                            AtomicRmwOp::Smax => Cond::Gt,
-                            _ => unreachable!(),
-                        };
-
-                        Inst::AluRRR {
-                            alu_op: ALUOp::SubS,
-                            size,
-                            rd: writable_zero_reg(),
-                            rn: x27,
-                            rm: x26,
-                        }
-                        .emit(sink, emit_info, state);
-
-                        Inst::CSel {
-                            cond,
-                            rd: x28wr,
-                            rn: x27,
-                            rm: x26,
-                        }
-                        .emit(sink, emit_info, state);
-                    }
-                    _ => {
-                        // add/sub/and/orr/eor x28, x27, x26
-                        let alu_op = match op {
-                            AtomicRmwOp::Add => ALUOp::Add,
-                            AtomicRmwOp::Sub => ALUOp::Sub,
-                            AtomicRmwOp::And => ALUOp::And,
-                            AtomicRmwOp::Or => ALUOp::Orr,
-                            AtomicRmwOp::Xor => ALUOp::Eor,
-                            AtomicRmwOp::Nand
-                            | AtomicRmwOp::Umin
-                            | AtomicRmwOp::Umax
-                            | AtomicRmwOp::Smin
-                            | AtomicRmwOp::Smax
-                            | AtomicRmwOp::Xchg => unreachable!(),
-                        };
-
-                        Inst::AluRRR {
-                            alu_op,
-                            size,
-                            rd: x28wr,
-                            rn: x27,
-                            rm: x26,
-                        }
-                        .emit(sink, emit_info, state);
-                    }
-                }
-
-                let srcloc = state.cur_srcloc();
-                if srcloc != SourceLoc::default() {
-                    sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
-                }
-                if op == AtomicRmwOp::Xchg {
-                    sink.put4(enc_stlxr(ty, x24wr, x26, x25)); // stlxr w24, x26, [x25]
-                } else {
-                    sink.put4(enc_stlxr(ty, x24wr, x28, x25)); // stlxr w24, x28, [x25]
-                }
-
-                // cbnz w24, again
-                // Note, we're actually testing x24, and relying on the default zero-high-half
-                // rule in the assignment that `stlxr` does.
-                let br_offset = sink.cur_offset();
-                sink.put4(enc_conditional_br(
-                    BranchTarget::Label(again_label),
-                    CondBrKind::NotZero(x24),
-                ));
-                sink.use_label_at_offset(br_offset, again_label, LabelUse::Branch19);
-            }
-            &Inst::AtomicCAS { rs, rt, rn, ty } => {
-                let size = match ty {
-                    I8 => 0b00,
-                    I16 => 0b01,
-                    I32 => 0b10,
-                    I64 => 0b11,
-                    _ => panic!("Unsupported type: {}", ty),
-                };
-
-                sink.put4(enc_cas(size, rs, rt, rn));
-            }
-            &Inst::AtomicCASLoop { ty } => {
-                /* Emit this:
-                    again:
-                     ldaxr{,b,h} x/w27, [x25]
-                     cmp         x27, x/w26 uxt{b,h}
-                     b.ne        out
-                     stlxr{,b,h} w24, x/w28, [x25]
-                     cbnz        x24, again
-                    out:
-
-                  Operand conventions:
-                     IN:  x25 (addr), x26 (expected value), x28 (replacement value)
-                     OUT: x27 (old value), x24 (trashed)
-                */
-                let x24 = xreg(24);
-                let x25 = xreg(25);
-                let x26 = xreg(26);
-                let x27 = xreg(27);
-                let x28 = xreg(28);
-                let xzrwr = writable_zero_reg();
-                let x24wr = writable_xreg(24);
-                let x27wr = writable_xreg(27);
-                let again_label = sink.get_label();
-                let out_label = sink.get_label();
-
-                // again:
-                sink.bind_label(again_label);
-                let srcloc = state.cur_srcloc();
-                if srcloc != SourceLoc::default() {
-                    sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
-                }
-                // ldaxr x27, [x25]
-                sink.put4(enc_ldaxr(ty, x27wr, x25));
-
-                // The top 32-bits are zero-extended by the ldaxr so we don't
-                // have to use UXTW, just the x-form of the register.
-                let (bit21, extend_op) = match ty {
-                    I8 => (0b1, 0b000000),
-                    I16 => (0b1, 0b001000),
-                    _ => (0b0, 0b000000),
-                };
-                let bits_31_21 = 0b111_01011_000 | bit21;
-                // cmp x27, x26 (== subs xzr, x27, x26)
-                sink.put4(enc_arith_rrr(bits_31_21, extend_op, xzrwr, x27, x26));
-
-                // b.ne out
-                let br_out_offset = sink.cur_offset();
-                sink.put4(enc_conditional_br(
-                    BranchTarget::Label(out_label),
-                    CondBrKind::Cond(Cond::Ne),
-                ));
-                sink.use_label_at_offset(br_out_offset, out_label, LabelUse::Branch19);
-
-                let srcloc = state.cur_srcloc();
-                if srcloc != SourceLoc::default() {
-                    sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
-                }
-                sink.put4(enc_stlxr(ty, x24wr, x28, x25)); // stlxr w24, x28, [x25]
-
-                // cbnz w24, again.
-                // Note, we're actually testing x24, and relying on the default zero-high-half
-                // rule in the assignment that `stlxr` does.
-                let br_again_offset = sink.cur_offset();
-                sink.put4(enc_conditional_br(
-                    BranchTarget::Label(again_label),
-                    CondBrKind::NotZero(x24),
-                ));
-                sink.use_label_at_offset(br_again_offset, again_label, LabelUse::Branch19);
-
-                // out:
-                sink.bind_label(out_label);
-            }
-            &Inst::LoadAcquire { access_ty, rt, rn } => {
-                sink.put4(enc_ldar(access_ty, rt, rn));
-            }
-            &Inst::StoreRelease { access_ty, rt, rn } => {
-                sink.put4(enc_stlr(access_ty, rt, rn));
-            }
-            &Inst::Fence {} => {
-                sink.put4(enc_dmb_ish()); // dmb ish
-            }
-            &Inst::FpuMove64 { rd, rn } => {
-                sink.put4(enc_fpurr(0b000_11110_01_1_000000_10000, rd, rn));
-            }
-            &Inst::FpuMove128 { rd, rn } => {
-                sink.put4(enc_vecmov(/* 16b = */ true, rd, rn));
-            }
-            &Inst::FpuMoveFromVec { rd, rn, idx, size } => {
-                let (imm5, shift, mask) = match size.lane_size() {
-                    ScalarSize::Size32 => (0b00100, 3, 0b011),
-                    ScalarSize::Size64 => (0b01000, 4, 0b001),
-                    _ => unimplemented!(),
-                };
-                debug_assert_eq!(idx & mask, idx);
-                let imm5 = imm5 | ((idx as u32) << shift);
-                sink.put4(
-                    0b010_11110000_00000_000001_00000_00000
-                        | (imm5 << 16)
-                        | (machreg_to_vec(rn) << 5)
-                        | machreg_to_vec(rd.to_reg()),
-                );
-            }
-            &Inst::FpuExtend { rd, rn, size } => {
-                sink.put4(enc_fpurr(
-                    0b000_11110_00_1_000000_10000 | (size.ftype() << 13),
-                    rd,
-                    rn,
-                ));
-            }
-            &Inst::FpuRR { fpu_op, rd, rn } => {
-                let top22 = match fpu_op {
-                    FPUOp1::Abs32 => 0b000_11110_00_1_000001_10000,
-                    FPUOp1::Abs64 => 0b000_11110_01_1_000001_10000,
-                    FPUOp1::Neg32 => 0b000_11110_00_1_000010_10000,
-                    FPUOp1::Neg64 => 0b000_11110_01_1_000010_10000,
-                    FPUOp1::Sqrt32 => 0b000_11110_00_1_000011_10000,
-                    FPUOp1::Sqrt64 => 0b000_11110_01_1_000011_10000,
-                    FPUOp1::Cvt32To64 => 0b000_11110_00_1_000101_10000,
-                    FPUOp1::Cvt64To32 => 0b000_11110_01_1_000100_10000,
-                };
-                sink.put4(enc_fpurr(top22, rd, rn));
-            }
-            &Inst::FpuRRR { fpu_op, rd, rn, rm } => {
-                let top22 = match fpu_op {
-                    FPUOp2::Add32 => 0b000_11110_00_1_00000_001010,
-                    FPUOp2::Add64 => 0b000_11110_01_1_00000_001010,
-                    FPUOp2::Sub32 => 0b000_11110_00_1_00000_001110,
-                    FPUOp2::Sub64 => 0b000_11110_01_1_00000_001110,
-                    FPUOp2::Mul32 => 0b000_11110_00_1_00000_000010,
-                    FPUOp2::Mul64 => 0b000_11110_01_1_00000_000010,
-                    FPUOp2::Div32 => 0b000_11110_00_1_00000_000110,
-                    FPUOp2::Div64 => 0b000_11110_01_1_00000_000110,
-                    FPUOp2::Max32 => 0b000_11110_00_1_00000_010010,
-                    FPUOp2::Max64 => 0b000_11110_01_1_00000_010010,
-                    FPUOp2::Min32 => 0b000_11110_00_1_00000_010110,
-                    FPUOp2::Min64 => 0b000_11110_01_1_00000_010110,
-                    FPUOp2::Sqadd64 => 0b010_11110_11_1_00000_000011,
-                    FPUOp2::Uqadd64 => 0b011_11110_11_1_00000_000011,
-                    FPUOp2::Sqsub64 => 0b010_11110_11_1_00000_001011,
-                    FPUOp2::Uqsub64 => 0b011_11110_11_1_00000_001011,
-                };
-                sink.put4(enc_fpurrr(top22, rd, rn, rm));
-            }
-            &Inst::FpuRRI { fpu_op, rd, rn } => match fpu_op {
-                FPUOpRI::UShr32(imm) => {
-                    debug_assert_eq!(32, imm.lane_size_in_bits);
-                    sink.put4(
-                        0b0_0_1_011110_0000000_00_0_0_0_1_00000_00000
-                            | imm.enc() << 16
-                            | machreg_to_vec(rn) << 5
-                            | machreg_to_vec(rd.to_reg()),
-                    )
-                }
-                FPUOpRI::UShr64(imm) => {
-                    debug_assert_eq!(64, imm.lane_size_in_bits);
-                    sink.put4(
-                        0b01_1_111110_0000000_00_0_0_0_1_00000_00000
-                            | imm.enc() << 16
-                            | machreg_to_vec(rn) << 5
-                            | machreg_to_vec(rd.to_reg()),
-                    )
-                }
-                FPUOpRI::Sli64(imm) => {
-                    debug_assert_eq!(64, imm.lane_size_in_bits);
-                    sink.put4(
-                        0b01_1_111110_0000000_010101_00000_00000
-                            | imm.enc() << 16
-                            | machreg_to_vec(rn) << 5
-                            | machreg_to_vec(rd.to_reg()),
-                    )
-                }
-                FPUOpRI::Sli32(imm) => {
-                    debug_assert_eq!(32, imm.lane_size_in_bits);
-                    sink.put4(
-                        0b0_0_1_011110_0000000_010101_00000_00000
-                            | imm.enc() << 16
-                            | machreg_to_vec(rn) << 5
-                            | machreg_to_vec(rd.to_reg()),
-                    )
-                }
-            },
-            &Inst::FpuRRRR {
-                fpu_op,
-                rd,
-                rn,
-                rm,
-                ra,
-            } => {
-                let top17 = match fpu_op {
-                    FPUOp3::MAdd32 => 0b000_11111_00_0_00000_0,
-                    FPUOp3::MAdd64 => 0b000_11111_01_0_00000_0,
-                };
-                sink.put4(enc_fpurrrr(top17, rd, rn, rm, ra));
-            }
-            &Inst::VecMisc { op, rd, rn, size } => {
-                let (q, enc_size) = size.enc_size();
-                let (u, bits_12_16, size) = match op {
-                    VecMisc2::Not => (0b1, 0b00101, 0b00),
-                    VecMisc2::Neg => (0b1, 0b01011, enc_size),
-                    VecMisc2::Abs => (0b0, 0b01011, enc_size),
-                    VecMisc2::Fabs => {
-                        debug_assert!(
-                            size == VectorSize::Size32x2
-                                || size == VectorSize::Size32x4
-                                || size == VectorSize::Size64x2
-                        );
-                        (0b0, 0b01111, enc_size)
-                    }
-                    VecMisc2::Fneg => {
-                        debug_assert!(
-                            size == VectorSize::Size32x2
-                                || size == VectorSize::Size32x4
-                                || size == VectorSize::Size64x2
-                        );
-                        (0b1, 0b01111, enc_size)
-                    }
-                    VecMisc2::Fsqrt => {
-                        debug_assert!(
-                            size == VectorSize::Size32x2
-                                || size == VectorSize::Size32x4
-                                || size == VectorSize::Size64x2
-                        );
-                        (0b1, 0b11111, enc_size)
-                    }
-                    VecMisc2::Rev64 => {
-                        debug_assert_ne!(VectorSize::Size64x2, size);
-                        (0b0, 0b00000, enc_size)
-                    }
-                    VecMisc2::Fcvtzs => {
-                        debug_assert!(
-                            size == VectorSize::Size32x2
-                                || size == VectorSize::Size32x4
-                                || size == VectorSize::Size64x2
-                        );
-                        (0b0, 0b11011, enc_size)
-                    }
-                    VecMisc2::Fcvtzu => {
-                        debug_assert!(
-                            size == VectorSize::Size32x2
-                                || size == VectorSize::Size32x4
-                                || size == VectorSize::Size64x2
-                        );
-                        (0b1, 0b11011, enc_size)
-                    }
-                    VecMisc2::Scvtf => {
-                        debug_assert!(size == VectorSize::Size32x4 || size == VectorSize::Size64x2);
-                        (0b0, 0b11101, enc_size & 0b1)
-                    }
-                    VecMisc2::Ucvtf => {
-                        debug_assert!(size == VectorSize::Size32x4 || size == VectorSize::Size64x2);
-                        (0b1, 0b11101, enc_size & 0b1)
-                    }
-                    VecMisc2::Frintn => {
-                        debug_assert!(
-                            size == VectorSize::Size32x2
-                                || size == VectorSize::Size32x4
-                                || size == VectorSize::Size64x2
-                        );
-                        (0b0, 0b11000, enc_size & 0b01)
-                    }
-                    VecMisc2::Frintz => {
-                        debug_assert!(
-                            size == VectorSize::Size32x2
-                                || size == VectorSize::Size32x4
-                                || size == VectorSize::Size64x2
-                        );
-                        (0b0, 0b11001, enc_size)
-                    }
-                    VecMisc2::Frintm => {
-                        debug_assert!(
-                            size == VectorSize::Size32x2
-                                || size == VectorSize::Size32x4
-                                || size == VectorSize::Size64x2
-                        );
-                        (0b0, 0b11001, enc_size & 0b01)
-                    }
-                    VecMisc2::Frintp => {
-                        debug_assert!(
-                            size == VectorSize::Size32x2
-                                || size == VectorSize::Size32x4
-                                || size == VectorSize::Size64x2
-                        );
-                        (0b0, 0b11000, enc_size)
-                    }
-                    VecMisc2::Cnt => {
-                        debug_assert!(size == VectorSize::Size8x8 || size == VectorSize::Size8x16);
-                        (0b0, 0b00101, enc_size)
-                    }
-                    VecMisc2::Cmeq0 => (0b0, 0b01001, enc_size),
-                };
-                sink.put4(enc_vec_rr_misc((q << 1) | u, size, bits_12_16, rd, rn));
-            }
-            &Inst::VecLanes { op, rd, rn, size } => {
-                let (q, size) = match size {
-                    VectorSize::Size8x8 => (0b0, 0b00),
-                    VectorSize::Size8x16 => (0b1, 0b00),
-                    VectorSize::Size16x4 => (0b0, 0b01),
-                    VectorSize::Size16x8 => (0b1, 0b01),
-                    VectorSize::Size32x4 => (0b1, 0b10),
-                    _ => unreachable!(),
-                };
-                let (u, opcode) = match op {
-                    VecLanesOp::Uminv => (0b1, 0b11010),
-                    VecLanesOp::Addv => (0b0, 0b11011),
-                };
-                sink.put4(enc_vec_lanes(q, u, size, opcode, rd, rn));
-            }
-            &Inst::VecShiftImm {
-                op,
-                rd,
-                rn,
-                size,
-                imm,
-            } => {
-                let (is_shr, template) = match op {
-                    VecShiftImmOp::Ushr => (true, 0b_011_011110_0000_000_000001_00000_00000_u32),
-                    VecShiftImmOp::Sshr => (true, 0b_010_011110_0000_000_000001_00000_00000_u32),
-                    VecShiftImmOp::Shl => (false, 0b_010_011110_0000_000_010101_00000_00000_u32),
-                };
-                let imm = imm as u32;
-                // Deal with the somewhat strange encoding scheme for, and limits on,
-                // the shift amount.
-                let immh_immb = match (size, is_shr) {
-                    (VectorSize::Size64x2, true) if imm >= 1 && imm <= 64 => {
-                        0b_1000_000_u32 | (64 - imm)
-                    }
-                    (VectorSize::Size32x4, true) if imm >= 1 && imm <= 32 => {
-                        0b_0100_000_u32 | (32 - imm)
-                    }
-                    (VectorSize::Size16x8, true) if imm >= 1 && imm <= 16 => {
-                        0b_0010_000_u32 | (16 - imm)
-                    }
-                    (VectorSize::Size8x16, true) if imm >= 1 && imm <= 8 => {
-                        0b_0001_000_u32 | (8 - imm)
-                    }
-                    (VectorSize::Size64x2, false) if imm <= 63 => 0b_1000_000_u32 | imm,
-                    (VectorSize::Size32x4, false) if imm <= 31 => 0b_0100_000_u32 | imm,
-                    (VectorSize::Size16x8, false) if imm <= 15 => 0b_0010_000_u32 | imm,
-                    (VectorSize::Size8x16, false) if imm <= 7 => 0b_0001_000_u32 | imm,
-                    _ => panic!(
-                        "aarch64: Inst::VecShiftImm: emit: invalid op/size/imm {:?}, {:?}, {:?}",
-                        op, size, imm
-                    ),
-                };
-                let rn_enc = machreg_to_vec(rn);
-                let rd_enc = machreg_to_vec(rd.to_reg());
-                sink.put4(template | (immh_immb << 16) | (rn_enc << 5) | rd_enc);
-            }
-            &Inst::VecExtract { rd, rn, rm, imm4 } => {
-                if imm4 < 16 {
-                    let template = 0b_01_101110_000_00000_0_0000_0_00000_00000_u32;
-                    let rm_enc = machreg_to_vec(rm);
-                    let rn_enc = machreg_to_vec(rn);
-                    let rd_enc = machreg_to_vec(rd.to_reg());
-                    sink.put4(
-                        template | (rm_enc << 16) | ((imm4 as u32) << 11) | (rn_enc << 5) | rd_enc,
-                    );
-                } else {
-                    panic!(
-                        "aarch64: Inst::VecExtract: emit: invalid extract index {}",
-                        imm4
-                    );
-                }
-            }
-            &Inst::VecTbl {
-                rd,
-                rn,
-                rm,
-                is_extension,
-            } => {
-                sink.put4(enc_tbl(is_extension, 0b00, rd, rn, rm));
-            }
-            &Inst::VecTbl2 {
-                rd,
-                rn,
-                rn2,
-                rm,
-                is_extension,
-            } => {
-                assert_eq!(machreg_to_vec(rn2), (machreg_to_vec(rn) + 1) % 32);
-                sink.put4(enc_tbl(is_extension, 0b01, rd, rn, rm));
-            }
-            &Inst::FpuCmp32 { rn, rm } => {
-                sink.put4(enc_fcmp(ScalarSize::Size32, rn, rm));
-            }
-            &Inst::FpuCmp64 { rn, rm } => {
-                sink.put4(enc_fcmp(ScalarSize::Size64, rn, rm));
-            }
-            &Inst::FpuToInt { op, rd, rn } => {
-                let top16 = match op {
-                    // FCVTZS (32/32-bit)
-                    FpuToIntOp::F32ToI32 => 0b000_11110_00_1_11_000,
-                    // FCVTZU (32/32-bit)
-                    FpuToIntOp::F32ToU32 => 0b000_11110_00_1_11_001,
-                    // FCVTZS (32/64-bit)
-                    FpuToIntOp::F32ToI64 => 0b100_11110_00_1_11_000,
-                    // FCVTZU (32/64-bit)
-                    FpuToIntOp::F32ToU64 => 0b100_11110_00_1_11_001,
-                    // FCVTZS (64/32-bit)
-                    FpuToIntOp::F64ToI32 => 0b000_11110_01_1_11_000,
-                    // FCVTZU (64/32-bit)
-                    FpuToIntOp::F64ToU32 => 0b000_11110_01_1_11_001,
-                    // FCVTZS (64/64-bit)
-                    FpuToIntOp::F64ToI64 => 0b100_11110_01_1_11_000,
-                    // FCVTZU (64/64-bit)
-                    FpuToIntOp::F64ToU64 => 0b100_11110_01_1_11_001,
-                };
-                sink.put4(enc_fputoint(top16, rd, rn));
-            }
-            &Inst::IntToFpu { op, rd, rn } => {
-                let top16 = match op {
-                    // SCVTF (32/32-bit)
-                    IntToFpuOp::I32ToF32 => 0b000_11110_00_1_00_010,
-                    // UCVTF (32/32-bit)
-                    IntToFpuOp::U32ToF32 => 0b000_11110_00_1_00_011,
-                    // SCVTF (64/32-bit)
-                    IntToFpuOp::I64ToF32 => 0b100_11110_00_1_00_010,
-                    // UCVTF (64/32-bit)
-                    IntToFpuOp::U64ToF32 => 0b100_11110_00_1_00_011,
-                    // SCVTF (32/64-bit)
-                    IntToFpuOp::I32ToF64 => 0b000_11110_01_1_00_010,
-                    // UCVTF (32/64-bit)
-                    IntToFpuOp::U32ToF64 => 0b000_11110_01_1_00_011,
-                    // SCVTF (64/64-bit)
-                    IntToFpuOp::I64ToF64 => 0b100_11110_01_1_00_010,
-                    // UCVTF (64/64-bit)
-                    IntToFpuOp::U64ToF64 => 0b100_11110_01_1_00_011,
-                };
-                sink.put4(enc_inttofpu(top16, rd, rn));
-            }
-            &Inst::LoadFpuConst64 { rd, const_data } => {
-                let inst = Inst::FpuLoad64 {
-                    rd,
-                    mem: AMode::Label(MemLabel::PCRel(8)),
-                    flags: MemFlags::trusted(),
-                };
-                inst.emit(sink, emit_info, state);
-                let inst = Inst::Jump {
-                    dest: BranchTarget::ResolvedOffset(12),
-                };
-                inst.emit(sink, emit_info, state);
-                sink.put8(const_data);
-            }
-            &Inst::LoadFpuConst128 { rd, const_data } => {
-                let inst = Inst::FpuLoad128 {
-                    rd,
-                    mem: AMode::Label(MemLabel::PCRel(8)),
-                    flags: MemFlags::trusted(),
-                };
-                inst.emit(sink, emit_info, state);
-                let inst = Inst::Jump {
-                    dest: BranchTarget::ResolvedOffset(20),
-                };
-                inst.emit(sink, emit_info, state);
-
-                for i in const_data.to_le_bytes().iter() {
-                    sink.put1(*i);
-                }
-            }
-            &Inst::FpuCSel32 { rd, rn, rm, cond } => {
-                sink.put4(enc_fcsel(rd, rn, rm, cond, ScalarSize::Size32));
-            }
-            &Inst::FpuCSel64 { rd, rn, rm, cond } => {
-                sink.put4(enc_fcsel(rd, rn, rm, cond, ScalarSize::Size64));
-            }
-            &Inst::FpuRound { op, rd, rn } => {
-                let top22 = match op {
-                    FpuRoundMode::Minus32 => 0b000_11110_00_1_001_010_10000,
-                    FpuRoundMode::Minus64 => 0b000_11110_01_1_001_010_10000,
-                    FpuRoundMode::Plus32 => 0b000_11110_00_1_001_001_10000,
-                    FpuRoundMode::Plus64 => 0b000_11110_01_1_001_001_10000,
-                    FpuRoundMode::Zero32 => 0b000_11110_00_1_001_011_10000,
-                    FpuRoundMode::Zero64 => 0b000_11110_01_1_001_011_10000,
-                    FpuRoundMode::Nearest32 => 0b000_11110_00_1_001_000_10000,
-                    FpuRoundMode::Nearest64 => 0b000_11110_01_1_001_000_10000,
-                };
-                sink.put4(enc_fround(top22, rd, rn));
-            }
-            &Inst::MovToFpu { rd, rn, size } => {
-                let template = match size {
-                    ScalarSize::Size32 => 0b000_11110_00_1_00_111_000000_00000_00000,
-                    ScalarSize::Size64 => 0b100_11110_01_1_00_111_000000_00000_00000,
-                    _ => unreachable!(),
-                };
-                sink.put4(template | (machreg_to_gpr(rn) << 5) | machreg_to_vec(rd.to_reg()));
-            }
-            &Inst::FpuMoveFPImm { rd, imm, size } => {
-                let size_code = match size {
-                    ScalarSize::Size32 => 0b00,
-                    ScalarSize::Size64 => 0b01,
-                    _ => unimplemented!(),
-                };
-                sink.put4(
-                    0b000_11110_00_1_00_000_000100_00000_00000
-                        | size_code << 22
-                        | ((imm.enc_bits() as u32) << 13)
-                        | machreg_to_vec(rd.to_reg()),
-                );
-            }
-            &Inst::MovToVec { rd, rn, idx, size } => {
-                let (imm5, shift) = match size.lane_size() {
-                    ScalarSize::Size8 => (0b00001, 1),
-                    ScalarSize::Size16 => (0b00010, 2),
-                    ScalarSize::Size32 => (0b00100, 3),
-                    ScalarSize::Size64 => (0b01000, 4),
-                    _ => unreachable!(),
-                };
-                debug_assert_eq!(idx & (0b11111 >> shift), idx);
-                let imm5 = imm5 | ((idx as u32) << shift);
-                sink.put4(
-                    0b010_01110000_00000_0_0011_1_00000_00000
-                        | (imm5 << 16)
-                        | (machreg_to_gpr(rn) << 5)
-                        | machreg_to_vec(rd.to_reg()),
-                );
-            }
-            &Inst::MovFromVec { rd, rn, idx, size } => {
-                let (q, imm5, shift, mask) = match size {
-                    VectorSize::Size8x16 => (0b0, 0b00001, 1, 0b1111),
-                    VectorSize::Size16x8 => (0b0, 0b00010, 2, 0b0111),
-                    VectorSize::Size32x4 => (0b0, 0b00100, 3, 0b0011),
-                    VectorSize::Size64x2 => (0b1, 0b01000, 4, 0b0001),
-                    _ => unreachable!(),
-                };
-                debug_assert_eq!(idx & mask, idx);
-                let imm5 = imm5 | ((idx as u32) << shift);
-                sink.put4(
-                    0b000_01110000_00000_0_0111_1_00000_00000
-                        | (q << 30)
-                        | (imm5 << 16)
-                        | (machreg_to_vec(rn) << 5)
-                        | machreg_to_gpr(rd.to_reg()),
-                );
-            }
-            &Inst::MovFromVecSigned {
-                rd,
-                rn,
-                idx,
-                size,
-                scalar_size,
-            } => {
-                let (imm5, shift, half) = match size {
-                    VectorSize::Size8x8 => (0b00001, 1, true),
-                    VectorSize::Size8x16 => (0b00001, 1, false),
-                    VectorSize::Size16x4 => (0b00010, 2, true),
-                    VectorSize::Size16x8 => (0b00010, 2, false),
-                    VectorSize::Size32x2 => {
-                        debug_assert_ne!(scalar_size, OperandSize::Size32);
-                        (0b00100, 3, true)
-                    }
-                    VectorSize::Size32x4 => {
-                        debug_assert_ne!(scalar_size, OperandSize::Size32);
-                        (0b00100, 3, false)
-                    }
-                    _ => panic!("Unexpected vector operand size"),
-                };
-                debug_assert_eq!(idx & (0b11111 >> (half as u32 + shift)), idx);
-                let imm5 = imm5 | ((idx as u32) << shift);
-                sink.put4(
-                    0b000_01110000_00000_0_0101_1_00000_00000
-                        | (scalar_size.is64() as u32) << 30
-                        | (imm5 << 16)
-                        | (machreg_to_vec(rn) << 5)
-                        | machreg_to_gpr(rd.to_reg()),
-                );
-            }
-            &Inst::VecDup { rd, rn, size } => {
-                let imm5 = match size {
-                    VectorSize::Size8x16 => 0b00001,
-                    VectorSize::Size16x8 => 0b00010,
-                    VectorSize::Size32x4 => 0b00100,
-                    VectorSize::Size64x2 => 0b01000,
-                    _ => unimplemented!(),
-                };
-                sink.put4(
-                    0b010_01110000_00000_000011_00000_00000
-                        | (imm5 << 16)
-                        | (machreg_to_gpr(rn) << 5)
-                        | machreg_to_vec(rd.to_reg()),
-                );
-            }
-            &Inst::VecDupFromFpu { rd, rn, size } => {
-                let imm5 = match size {
-                    VectorSize::Size32x4 => 0b00100,
-                    VectorSize::Size64x2 => 0b01000,
-                    _ => unimplemented!(),
-                };
-                sink.put4(
-                    0b010_01110000_00000_000001_00000_00000
-                        | (imm5 << 16)
-                        | (machreg_to_vec(rn) << 5)
-                        | machreg_to_vec(rd.to_reg()),
-                );
-            }
-            &Inst::VecDupFPImm { rd, imm, size } => {
-                let imm = imm.enc_bits();
-                let op = match size.lane_size() {
-                    ScalarSize::Size32 => 0,
-                    ScalarSize::Size64 => 1,
-                    _ => unimplemented!(),
-                };
-                let q_op = op | ((size.is_128bits() as u32) << 1);
-
-                sink.put4(enc_asimd_mod_imm(rd, q_op, 0b1111, imm));
-            }
-            &Inst::VecDupImm {
-                rd,
-                imm,
-                invert,
-                size,
-            } => {
-                let (imm, shift, shift_ones) = imm.value();
-                let (op, cmode) = match size.lane_size() {
-                    ScalarSize::Size8 => {
-                        assert!(!invert);
-                        assert_eq!(shift, 0);
-
-                        (0, 0b1110)
-                    }
-                    ScalarSize::Size16 => {
-                        let s = shift & 8;
-
-                        assert!(!shift_ones);
-                        assert_eq!(s, shift);
-
-                        (invert as u32, 0b1000 | (s >> 2))
-                    }
-                    ScalarSize::Size32 => {
-                        if shift_ones {
-                            assert!(shift == 8 || shift == 16);
-
-                            (invert as u32, 0b1100 | (shift >> 4))
-                        } else {
-                            let s = shift & 24;
-
-                            assert_eq!(s, shift);
-
-                            (invert as u32, 0b0000 | (s >> 2))
-                        }
-                    }
-                    ScalarSize::Size64 => {
-                        assert!(!invert);
-                        assert_eq!(shift, 0);
-
-                        (1, 0b1110)
-                    }
-                    _ => unreachable!(),
-                };
-                let q_op = op | ((size.is_128bits() as u32) << 1);
-
-                sink.put4(enc_asimd_mod_imm(rd, q_op, cmode, imm));
-            }
-            &Inst::VecExtend {
-                t,
-                rd,
-                rn,
-                high_half,
-            } => {
-                let (u, immh) = match t {
-                    VecExtendOp::Sxtl8 => (0b0, 0b001),
-                    VecExtendOp::Sxtl16 => (0b0, 0b010),
-                    VecExtendOp::Sxtl32 => (0b0, 0b100),
-                    VecExtendOp::Uxtl8 => (0b1, 0b001),
-                    VecExtendOp::Uxtl16 => (0b1, 0b010),
-                    VecExtendOp::Uxtl32 => (0b1, 0b100),
-                };
-                sink.put4(
-                    0b000_011110_0000_000_101001_00000_00000
-                        | ((high_half as u32) << 30)
-                        | (u << 29)
-                        | (immh << 19)
-                        | (machreg_to_vec(rn) << 5)
-                        | machreg_to_vec(rd.to_reg()),
-                );
-            }
-            &Inst::VecRRLong {
-                op,
-                rd,
-                rn,
-                high_half,
-            } => {
-                let (u, size, bits_12_16) = match op {
-                    VecRRLongOp::Fcvtl16 => (0b0, 0b00, 0b10111),
-                    VecRRLongOp::Fcvtl32 => (0b0, 0b01, 0b10111),
-                    VecRRLongOp::Shll8 => (0b1, 0b00, 0b10011),
-                    VecRRLongOp::Shll16 => (0b1, 0b01, 0b10011),
-                    VecRRLongOp::Shll32 => (0b1, 0b10, 0b10011),
-                };
-
-                sink.put4(enc_vec_rr_misc(
-                    ((high_half as u32) << 1) | u,
-                    size,
-                    bits_12_16,
-                    rd,
-                    rn,
-                ));
-            }
-            &Inst::VecRRNarrow {
-                op,
-                rd,
-                rn,
-                high_half,
-            } => {
-                let (u, size, bits_12_16) = match op {
-                    VecRRNarrowOp::Xtn16 => (0b0, 0b00, 0b10010),
-                    VecRRNarrowOp::Xtn32 => (0b0, 0b01, 0b10010),
-                    VecRRNarrowOp::Xtn64 => (0b0, 0b10, 0b10010),
-                    VecRRNarrowOp::Sqxtn16 => (0b0, 0b00, 0b10100),
-                    VecRRNarrowOp::Sqxtn32 => (0b0, 0b01, 0b10100),
-                    VecRRNarrowOp::Sqxtn64 => (0b0, 0b10, 0b10100),
-                    VecRRNarrowOp::Sqxtun16 => (0b1, 0b00, 0b10010),
-                    VecRRNarrowOp::Sqxtun32 => (0b1, 0b01, 0b10010),
-                    VecRRNarrowOp::Sqxtun64 => (0b1, 0b10, 0b10010),
-                    VecRRNarrowOp::Uqxtn16 => (0b1, 0b00, 0b10100),
-                    VecRRNarrowOp::Uqxtn32 => (0b1, 0b01, 0b10100),
-                    VecRRNarrowOp::Uqxtn64 => (0b1, 0b10, 0b10100),
-                    VecRRNarrowOp::Fcvtn32 => (0b0, 0b00, 0b10110),
-                    VecRRNarrowOp::Fcvtn64 => (0b0, 0b01, 0b10110),
-                };
-
-                sink.put4(enc_vec_rr_misc(
-                    ((high_half as u32) << 1) | u,
-                    size,
-                    bits_12_16,
-                    rd,
-                    rn,
-                ));
-            }
-            &Inst::VecMovElement {
-                rd,
-                rn,
-                dest_idx,
-                src_idx,
-                size,
-            } => {
-                let (imm5, shift) = match size.lane_size() {
-                    ScalarSize::Size8 => (0b00001, 1),
-                    ScalarSize::Size16 => (0b00010, 2),
-                    ScalarSize::Size32 => (0b00100, 3),
-                    ScalarSize::Size64 => (0b01000, 4),
-                    _ => unreachable!(),
-                };
-                let mask = 0b11111 >> shift;
-                debug_assert_eq!(dest_idx & mask, dest_idx);
-                debug_assert_eq!(src_idx & mask, src_idx);
-                let imm4 = (src_idx as u32) << (shift - 1);
-                let imm5 = imm5 | ((dest_idx as u32) << shift);
-                sink.put4(
-                    0b011_01110000_00000_0_0000_1_00000_00000
-                        | (imm5 << 16)
-                        | (imm4 << 11)
-                        | (machreg_to_vec(rn) << 5)
-                        | machreg_to_vec(rd.to_reg()),
-                );
-            }
-            &Inst::VecRRPair { op, rd, rn } => {
-                let bits_12_16 = match op {
-                    VecPairOp::Addp => 0b11011,
-                };
-
-                sink.put4(enc_vec_rr_pair(bits_12_16, rd, rn));
-            }
-            &Inst::VecRRRLong {
-                rd,
-                rn,
-                rm,
-                alu_op,
-                high_half,
-            } => {
-                let (u, size, bit14) = match alu_op {
-                    VecRRRLongOp::Smull8 => (0b0, 0b00, 0b1),
-                    VecRRRLongOp::Smull16 => (0b0, 0b01, 0b1),
-                    VecRRRLongOp::Smull32 => (0b0, 0b10, 0b1),
-                    VecRRRLongOp::Umull8 => (0b1, 0b00, 0b1),
-                    VecRRRLongOp::Umull16 => (0b1, 0b01, 0b1),
-                    VecRRRLongOp::Umull32 => (0b1, 0b10, 0b1),
-                    VecRRRLongOp::Umlal8 => (0b1, 0b00, 0b0),
-                    VecRRRLongOp::Umlal16 => (0b1, 0b01, 0b0),
-                    VecRRRLongOp::Umlal32 => (0b1, 0b10, 0b0),
-                };
-                sink.put4(enc_vec_rrr_long(
-                    high_half as u32,
-                    u,
-                    size,
-                    bit14,
-                    rm,
-                    rn,
-                    rd,
-                ));
-            }
-            &Inst::VecRRPairLong { op, rd, rn } => {
-                let (u, size) = match op {
-                    VecRRPairLongOp::Saddlp8 => (0b0, 0b0),
-                    VecRRPairLongOp::Uaddlp8 => (0b1, 0b0),
-                    VecRRPairLongOp::Saddlp16 => (0b0, 0b1),
-                    VecRRPairLongOp::Uaddlp16 => (0b1, 0b1),
-                };
-
-                sink.put4(enc_vec_rr_pair_long(u, size, rd, rn));
-            }
-            &Inst::VecRRR {
-                rd,
-                rn,
-                rm,
-                alu_op,
-                size,
-            } => {
-                let (q, enc_size) = size.enc_size();
-                let is_float = match alu_op {
-                    VecALUOp::Fcmeq
-                    | VecALUOp::Fcmgt
-                    | VecALUOp::Fcmge
-                    | VecALUOp::Fadd
-                    | VecALUOp::Fsub
-                    | VecALUOp::Fdiv
-                    | VecALUOp::Fmax
-                    | VecALUOp::Fmin
-                    | VecALUOp::Fmul => true,
-                    _ => false,
-                };
-                let enc_float_size = match (is_float, size) {
-                    (true, VectorSize::Size32x2) => 0b0,
-                    (true, VectorSize::Size32x4) => 0b0,
-                    (true, VectorSize::Size64x2) => 0b1,
-                    (true, _) => unimplemented!(),
-                    _ => 0,
-                };
-
-                let (top11, bit15_10) = match alu_op {
-                    VecALUOp::Sqadd => (0b000_01110_00_1 | enc_size << 1, 0b000011),
-                    VecALUOp::Sqsub => (0b000_01110_00_1 | enc_size << 1, 0b001011),
-                    VecALUOp::Uqadd => (0b001_01110_00_1 | enc_size << 1, 0b000011),
-                    VecALUOp::Uqsub => (0b001_01110_00_1 | enc_size << 1, 0b001011),
-                    VecALUOp::Cmeq => (0b001_01110_00_1 | enc_size << 1, 0b100011),
-                    VecALUOp::Cmge => (0b000_01110_00_1 | enc_size << 1, 0b001111),
-                    VecALUOp::Cmgt => (0b000_01110_00_1 | enc_size << 1, 0b001101),
-                    VecALUOp::Cmhi => (0b001_01110_00_1 | enc_size << 1, 0b001101),
-                    VecALUOp::Cmhs => (0b001_01110_00_1 | enc_size << 1, 0b001111),
-                    VecALUOp::Fcmeq => (0b000_01110_00_1, 0b111001),
-                    VecALUOp::Fcmgt => (0b001_01110_10_1, 0b111001),
-                    VecALUOp::Fcmge => (0b001_01110_00_1, 0b111001),
-                    // The following logical instructions operate on bytes, so are not encoded differently
-                    // for the different vector types.
-                    VecALUOp::And => (0b000_01110_00_1, 0b000111),
-                    VecALUOp::Bic => (0b000_01110_01_1, 0b000111),
-                    VecALUOp::Orr => (0b000_01110_10_1, 0b000111),
-                    VecALUOp::Eor => (0b001_01110_00_1, 0b000111),
-                    VecALUOp::Bsl => (0b001_01110_01_1, 0b000111),
-                    VecALUOp::Umaxp => {
-                        debug_assert_ne!(size, VectorSize::Size64x2);
-
-                        (0b001_01110_00_1 | enc_size << 1, 0b101001)
-                    }
-                    VecALUOp::Add => (0b000_01110_00_1 | enc_size << 1, 0b100001),
-                    VecALUOp::Sub => (0b001_01110_00_1 | enc_size << 1, 0b100001),
-                    VecALUOp::Mul => {
-                        debug_assert_ne!(size, VectorSize::Size64x2);
-                        (0b000_01110_00_1 | enc_size << 1, 0b100111)
-                    }
-                    VecALUOp::Sshl => (0b000_01110_00_1 | enc_size << 1, 0b010001),
-                    VecALUOp::Ushl => (0b001_01110_00_1 | enc_size << 1, 0b010001),
-                    VecALUOp::Umin => {
-                        debug_assert_ne!(size, VectorSize::Size64x2);
-
-                        (0b001_01110_00_1 | enc_size << 1, 0b011011)
-                    }
-                    VecALUOp::Smin => {
-                        debug_assert_ne!(size, VectorSize::Size64x2);
-
-                        (0b000_01110_00_1 | enc_size << 1, 0b011011)
-                    }
-                    VecALUOp::Umax => {
-                        debug_assert_ne!(size, VectorSize::Size64x2);
-
-                        (0b001_01110_00_1 | enc_size << 1, 0b011001)
-                    }
-                    VecALUOp::Smax => {
-                        debug_assert_ne!(size, VectorSize::Size64x2);
-
-                        (0b000_01110_00_1 | enc_size << 1, 0b011001)
-                    }
-                    VecALUOp::Urhadd => {
-                        debug_assert_ne!(size, VectorSize::Size64x2);
-
-                        (0b001_01110_00_1 | enc_size << 1, 0b000101)
-                    }
-                    VecALUOp::Fadd => (0b000_01110_00_1, 0b110101),
-                    VecALUOp::Fsub => (0b000_01110_10_1, 0b110101),
-                    VecALUOp::Fdiv => (0b001_01110_00_1, 0b111111),
-                    VecALUOp::Fmax => (0b000_01110_00_1, 0b111101),
-                    VecALUOp::Fmin => (0b000_01110_10_1, 0b111101),
-                    VecALUOp::Fmul => (0b001_01110_00_1, 0b110111),
-                    VecALUOp::Addp => (0b000_01110_00_1 | enc_size << 1, 0b101111),
-                    VecALUOp::Zip1 => (0b01001110_00_0 | enc_size << 1, 0b001110),
-                    VecALUOp::Sqrdmulh => {
-                        debug_assert!(
-                            size.lane_size() == ScalarSize::Size16
-                                || size.lane_size() == ScalarSize::Size32
-                        );
-
-                        (0b001_01110_00_1 | enc_size << 1, 0b101101)
-                    }
-                };
-                let top11 = if is_float {
-                    top11 | enc_float_size << 1
-                } else {
-                    top11
-                };
-                sink.put4(enc_vec_rrr(top11 | q << 9, rm, bit15_10, rn, rd));
-            }
-            &Inst::VecLoadReplicate { rd, rn, size } => {
-                let (q, size) = size.enc_size();
-
-                let srcloc = state.cur_srcloc();
-                if srcloc != SourceLoc::default() {
-                    // Register the offset at which the actual load instruction starts.
-                    sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
-                }
-
-                sink.put4(enc_ldst_vec(q, size, rn, rd));
-            }
-            &Inst::VecCSel { rd, rn, rm, cond } => {
-                /* Emit this:
-                      b.cond  else
-                      mov     rd, rm
-                      b       out
-                     else:
-                      mov     rd, rn
-                     out:
-
-                   Note, we could do better in the cases where rd == rn or rd == rm.
-                */
-                let else_label = sink.get_label();
-                let out_label = sink.get_label();
-
-                // b.cond else
-                let br_else_offset = sink.cur_offset();
-                sink.put4(enc_conditional_br(
-                    BranchTarget::Label(else_label),
-                    CondBrKind::Cond(cond),
-                ));
-                sink.use_label_at_offset(br_else_offset, else_label, LabelUse::Branch19);
-
-                // mov rd, rm
-                sink.put4(enc_vecmov(/* 16b = */ true, rd, rm));
-
-                // b out
-                let b_out_offset = sink.cur_offset();
-                sink.use_label_at_offset(b_out_offset, out_label, LabelUse::Branch26);
-                sink.add_uncond_branch(b_out_offset, b_out_offset + 4, out_label);
-                sink.put4(enc_jump26(0b000101, 0 /* will be fixed up later */));
-
-                // else:
-                sink.bind_label(else_label);
-
-                // mov rd, rn
-                sink.put4(enc_vecmov(/* 16b = */ true, rd, rn));
-
-                // out:
-                sink.bind_label(out_label);
-            }
-            &Inst::MovToNZCV { rn } => {
-                sink.put4(0xd51b4200 | machreg_to_gpr(rn));
-            }
-            &Inst::MovFromNZCV { rd } => {
-                sink.put4(0xd53b4200 | machreg_to_gpr(rd.to_reg()));
-            }
-            &Inst::Extend {
-                rd,
-                rn,
-                signed: false,
-                from_bits: 1,
-                to_bits,
-            } => {
-                assert!(to_bits <= 64);
-                // Reduce zero-extend-from-1-bit to:
-                // - and rd, rn, #1
-                // Note: This is special cased as UBFX may take more cycles
-                // than AND on smaller cores.
-                let imml = ImmLogic::maybe_from_u64(1, I32).unwrap();
-                Inst::AluRRImmLogic {
-                    alu_op: ALUOp::And,
-                    size: OperandSize::Size32,
-                    rd,
-                    rn,
-                    imml,
-                }
-                .emit(sink, emit_info, state);
-            }
-            &Inst::Extend {
-                rd,
-                rn,
-                signed: false,
-                from_bits: 32,
-                to_bits: 64,
-            } => {
-                let mov = Inst::Mov32 { rd, rm: rn };
-                mov.emit(sink, emit_info, state);
-            }
-            &Inst::Extend {
-                rd,
-                rn,
-                signed,
-                from_bits,
-                to_bits,
-            } => {
-                let (opc, size) = if signed {
-                    (0b00, OperandSize::from_bits(to_bits))
-                } else {
-                    (0b10, OperandSize::Size32)
-                };
-                sink.put4(enc_bfm(opc, size, rd, rn, 0, from_bits - 1));
-            }
-            &Inst::Jump { ref dest } => {
-                let off = sink.cur_offset();
-                // Indicate that the jump uses a label, if so, so that a fixup can occur later.
-                if let Some(l) = dest.as_label() {
-                    sink.use_label_at_offset(off, l, LabelUse::Branch26);
-                    sink.add_uncond_branch(off, off + 4, l);
-                }
-                // Emit the jump itself.
-                sink.put4(enc_jump26(0b000101, dest.as_offset26_or_zero()));
-            }
-            &Inst::Ret => {
-                sink.put4(0xd65f03c0);
-            }
-            &Inst::EpiloguePlaceholder => {
-                // Noop; this is just a placeholder for epilogues.
-            }
-            &Inst::Call { ref info } => {
-                if let Some(s) = state.take_stack_map() {
-                    sink.add_stack_map(StackMapExtent::UpcomingBytes(4), s);
-                }
-                let loc = state.cur_srcloc();
-                sink.add_reloc(loc, Reloc::Arm64Call, &info.dest, 0);
-                sink.put4(enc_jump26(0b100101, 0));
-                if info.opcode.is_call() {
-                    sink.add_call_site(loc, info.opcode);
-                }
-            }
-            &Inst::CallInd { ref info } => {
-                if let Some(s) = state.take_stack_map() {
-                    sink.add_stack_map(StackMapExtent::UpcomingBytes(4), s);
-                }
-                sink.put4(0b1101011_0001_11111_000000_00000_00000 | (machreg_to_gpr(info.rn) << 5));
-                let loc = state.cur_srcloc();
-                if info.opcode.is_call() {
-                    sink.add_call_site(loc, info.opcode);
-                }
-            }
-            &Inst::CondBr {
-                taken,
-                not_taken,
-                kind,
-            } => {
-                // Conditional part first.
-                let cond_off = sink.cur_offset();
-                if let Some(l) = taken.as_label() {
-                    sink.use_label_at_offset(cond_off, l, LabelUse::Branch19);
-                    let inverted = enc_conditional_br(taken, kind.invert()).to_le_bytes();
-                    sink.add_cond_branch(cond_off, cond_off + 4, l, &inverted[..]);
-                }
-                sink.put4(enc_conditional_br(taken, kind));
-
-                // Unconditional part next.
-                let uncond_off = sink.cur_offset();
-                if let Some(l) = not_taken.as_label() {
-                    sink.use_label_at_offset(uncond_off, l, LabelUse::Branch26);
-                    sink.add_uncond_branch(uncond_off, uncond_off + 4, l);
-                }
-                sink.put4(enc_jump26(0b000101, not_taken.as_offset26_or_zero()));
-            }
-            &Inst::TrapIf { kind, trap_code } => {
-                // condbr KIND, LABEL
-                let off = sink.cur_offset();
-                let label = sink.get_label();
-                sink.put4(enc_conditional_br(
-                    BranchTarget::Label(label),
-                    kind.invert(),
-                ));
-                sink.use_label_at_offset(off, label, LabelUse::Branch19);
-                // udf
-                let trap = Inst::Udf { trap_code };
-                trap.emit(sink, emit_info, state);
-                // LABEL:
-                sink.bind_label(label);
-            }
-            &Inst::IndirectBr { rn, .. } => {
-                sink.put4(enc_br(rn));
-            }
-            &Inst::Nop0 => {}
-            &Inst::Nop4 => {
-                sink.put4(0xd503201f);
-            }
-            &Inst::Brk => {
-                sink.put4(0xd4200000);
-            }
-            &Inst::Udf { trap_code } => {
-                let srcloc = state.cur_srcloc();
-                sink.add_trap(srcloc, trap_code);
-                if let Some(s) = state.take_stack_map() {
-                    sink.add_stack_map(StackMapExtent::UpcomingBytes(4), s);
-                }
-                sink.put4(0xd4a00000);
-            }
-            &Inst::Adr { rd, off } => {
-                assert!(off > -(1 << 20));
-                assert!(off < (1 << 20));
-                sink.put4(enc_adr(off, rd));
-            }
-            &Inst::Word4 { data } => {
-                sink.put4(data);
-            }
-            &Inst::Word8 { data } => {
-                sink.put8(data);
-            }
-            &Inst::JTSequence {
-                ridx,
-                rtmp1,
-                rtmp2,
-                ref info,
-                ..
-            } => {
-                // This sequence is *one* instruction in the vcode, and is expanded only here at
-                // emission time, because we cannot allow the regalloc to insert spills/reloads in
-                // the middle; we depend on hardcoded PC-rel addressing below.
-
-                // Branch to default when condition code from prior comparison indicates.
-                let br = enc_conditional_br(info.default_target, CondBrKind::Cond(Cond::Hs));
-                // No need to inform the sink's branch folding logic about this branch, because it
-                // will not be merged with any other branch, flipped, or elided (it is not preceded
-                // or succeeded by any other branch). Just emit it with the label use.
-                let default_br_offset = sink.cur_offset();
-                if let BranchTarget::Label(l) = info.default_target {
-                    sink.use_label_at_offset(default_br_offset, l, LabelUse::Branch19);
-                }
-                sink.put4(br);
-
-                // Save index in a tmp (the live range of ridx only goes to start of this
-                // sequence; rtmp1 or rtmp2 may overwrite it).
-                let inst = Inst::gen_move(rtmp2, ridx, I64);
-                inst.emit(sink, emit_info, state);
-                // Load address of jump table
-                let inst = Inst::Adr { rd: rtmp1, off: 16 };
-                inst.emit(sink, emit_info, state);
-                // Load value out of jump table
-                let inst = Inst::SLoad32 {
-                    rd: rtmp2,
-                    mem: AMode::reg_plus_reg_scaled_extended(
-                        rtmp1.to_reg(),
-                        rtmp2.to_reg(),
-                        I32,
-                        ExtendOp::UXTW,
-                    ),
-                    flags: MemFlags::trusted(),
-                };
-                inst.emit(sink, emit_info, state);
-                // Add base of jump table to jump-table-sourced block offset
-                let inst = Inst::AluRRR {
-                    alu_op: ALUOp::Add,
-                    size: OperandSize::Size64,
-                    rd: rtmp1,
-                    rn: rtmp1.to_reg(),
-                    rm: rtmp2.to_reg(),
-                };
-                inst.emit(sink, emit_info, state);
-                // Branch to computed address. (`targets` here is only used for successor queries
-                // and is not needed for emission.)
-                let inst = Inst::IndirectBr {
-                    rn: rtmp1.to_reg(),
-                    targets: vec![],
-                };
-                inst.emit(sink, emit_info, state);
-                // Emit jump table (table of 32-bit offsets).
-                let jt_off = sink.cur_offset();
-                for &target in info.targets.iter() {
-                    let word_off = sink.cur_offset();
-                    // off_into_table is an addend here embedded in the label to be later patched
-                    // at the end of codegen. The offset is initially relative to this jump table
-                    // entry; with the extra addend, it'll be relative to the jump table's start,
-                    // after patching.
-                    let off_into_table = word_off - jt_off;
-                    sink.use_label_at_offset(
-                        word_off,
-                        target.as_label().unwrap(),
-                        LabelUse::PCRel32,
-                    );
-                    sink.put4(off_into_table);
-                }
-
-                // Lowering produces an EmitIsland before using a JTSequence, so we can safely
-                // disable the worst-case-size check in this case.
-                start_off = sink.cur_offset();
-            }
-            &Inst::LoadExtName {
-                rd,
-                ref name,
-                offset,
-            } => {
-                let inst = Inst::ULoad64 {
-                    rd,
-                    mem: AMode::Label(MemLabel::PCRel(8)),
-                    flags: MemFlags::trusted(),
-                };
-                inst.emit(sink, emit_info, state);
-                let inst = Inst::Jump {
-                    dest: BranchTarget::ResolvedOffset(12),
-                };
-                inst.emit(sink, emit_info, state);
-                let srcloc = state.cur_srcloc();
-                sink.add_reloc(srcloc, Reloc::Abs8, name, offset);
-                if emit_info.0.emit_all_ones_funcaddrs() {
-                    sink.put8(u64::max_value());
-                } else {
-                    sink.put8(0);
-                }
-            }
-            &Inst::LoadAddr { rd, ref mem } => {
-                let (mem_insts, mem) = mem_finalize(sink.cur_offset(), mem, state);
-                for inst in mem_insts.into_iter() {
-                    inst.emit(sink, emit_info, state);
-                }
-
-                let (reg, index_reg, offset) = match mem {
-                    AMode::RegExtended(r, idx, extendop) => (r, Some((idx, extendop)), 0),
-                    AMode::Unscaled(r, simm9) => (r, None, simm9.value()),
-                    AMode::UnsignedOffset(r, uimm12scaled) => {
-                        (r, None, uimm12scaled.value() as i32)
-                    }
-                    _ => panic!("Unsupported case for LoadAddr: {:?}", mem),
-                };
-                let abs_offset = if offset < 0 {
-                    -offset as u64
-                } else {
-                    offset as u64
-                };
-                let alu_op = if offset < 0 { ALUOp::Sub } else { ALUOp::Add };
-
-                if let Some((idx, extendop)) = index_reg {
-                    let add = Inst::AluRRRExtend {
-                        alu_op: ALUOp::Add,
-                        size: OperandSize::Size64,
-                        rd,
-                        rn: reg,
-                        rm: idx,
-                        extendop,
-                    };
-
-                    add.emit(sink, emit_info, state);
-                } else if offset == 0 {
-                    if reg != rd.to_reg() {
-                        let mov = Inst::Mov64 { rd, rm: reg };
-
-                        mov.emit(sink, emit_info, state);
-                    }
-                } else if let Some(imm12) = Imm12::maybe_from_u64(abs_offset) {
-                    let add = Inst::AluRRImm12 {
-                        alu_op,
-                        size: OperandSize::Size64,
-                        rd,
-                        rn: reg,
-                        imm12,
-                    };
-                    add.emit(sink, emit_info, state);
-                } else {
-                    // Use `tmp2` here: `reg` may be `spilltmp` if the `AMode` on this instruction
-                    // was initially an `SPOffset`. Assert that `tmp2` is truly free to use. Note
-                    // that no other instructions will be inserted here (we're emitting directly),
-                    // and a live range of `tmp2` should not span this instruction, so this use
-                    // should otherwise be correct.
-                    debug_assert!(rd.to_reg() != tmp2_reg());
-                    debug_assert!(reg != tmp2_reg());
-                    let tmp = writable_tmp2_reg();
-                    for insn in Inst::load_constant(tmp, abs_offset).into_iter() {
-                        insn.emit(sink, emit_info, state);
-                    }
-                    let add = Inst::AluRRR {
-                        alu_op,
-                        size: OperandSize::Size64,
-                        rd,
-                        rn: reg,
-                        rm: tmp.to_reg(),
-                    };
-                    add.emit(sink, emit_info, state);
-                }
-            }
-            &Inst::VirtualSPOffsetAdj { offset } => {
-                log::trace!(
-                    "virtual sp offset adjusted by {} -> {}",
-                    offset,
-                    state.virtual_sp_offset + offset,
-                );
-                state.virtual_sp_offset += offset;
-            }
-            &Inst::EmitIsland { needed_space } => {
-                if sink.island_needed(needed_space + 4) {
-                    let jump_around_label = sink.get_label();
-                    let jmp = Inst::Jump {
-                        dest: BranchTarget::Label(jump_around_label),
-                    };
-                    jmp.emit(sink, emit_info, state);
-                    sink.emit_island(needed_space + 4);
-                    sink.bind_label(jump_around_label);
-                }
-            }
-
-            &Inst::ElfTlsGetAddr { ref symbol } => {
-                // This is the instruction sequence that GCC emits for ELF GD TLS Relocations in aarch64
-                // See: https://gcc.godbolt.org/z/KhMh5Gvra
-
-                // adrp x0, <label>
-                sink.add_reloc(state.cur_srcloc(), Reloc::Aarch64TlsGdAdrPage21, symbol, 0);
-                sink.put4(0x90000000);
-
-                // add x0, x0, <label>
-                sink.add_reloc(state.cur_srcloc(), Reloc::Aarch64TlsGdAddLo12Nc, symbol, 0);
-                sink.put4(0x91000000);
-
-                // bl __tls_get_addr
-                sink.add_reloc(
-                    state.cur_srcloc(),
-                    Reloc::Arm64Call,
-                    &ExternalName::LibCall(LibCall::ElfTlsGetAddr),
-                    0,
-                );
-                sink.put4(0x94000000);
-
-                // nop
-                sink.put4(0xd503201f);
-            }
-
-            &Inst::ValueLabelMarker { .. } => {
-                // Nothing; this is only used to compute debug info.
-            }
-
-            &Inst::Unwind { ref inst } => {
-                sink.add_unwind(inst.clone());
-            }
-        }
-
-        let end_off = sink.cur_offset();
-        debug_assert!((end_off - start_off) <= Inst::worst_case_size());
-
-        state.clear_post_insn();
-    }
-
-    fn pretty_print(&self, mb_rru: Option<&RealRegUniverse>, state: &mut EmitState) -> String {
-        self.print_with_state(mb_rru, state)
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/inst/emit_tests.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/inst/emit_tests.rs
deleted file mode 100644
index 6e7c67e26..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/inst/emit_tests.rs
+++ /dev/null
@@ -1,6742 +0,0 @@
-use crate::ir::types::*;
-use crate::ir::TrapCode;
-use crate::isa::aarch64::inst::*;
-use crate::isa::CallConv;
-use crate::settings;
-
-use alloc::boxed::Box;
-use alloc::vec::Vec;
-
-#[test]
-fn test_aarch64_binemit() {
-    let mut insns = Vec::<(Inst, &str, &str)>::new();
-
-    // N.B.: the architecture is little-endian, so when transcribing the 32-bit
-    // hex instructions from e.g. objdump disassembly, one must swap the bytes
-    // seen below. (E.g., a `ret` is normally written as the u32 `D65F03C0`,
-    // but we write it here as C0035FD6.)
-
-    // Useful helper script to produce the encodings from the text:
-    //
-    //      #!/bin/sh
-    //      tmp=`mktemp /tmp/XXXXXXXX.o`
-    //      aarch64-linux-gnu-as /dev/stdin -o $tmp
-    //      aarch64-linux-gnu-objdump -d $tmp
-    //      rm -f $tmp
-    //
-    // Then:
-    //
-    //      $ echo "mov x1, x2" | aarch64inst.sh
-    insns.push((Inst::Ret, "C0035FD6", "ret"));
-    insns.push((Inst::Nop0, "", "nop-zero-len"));
-    insns.push((Inst::Nop4, "1F2003D5", "nop"));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::Add,
-            size: OperandSize::Size32,
-            rd: writable_xreg(1),
-            rn: xreg(2),
-            rm: xreg(3),
-        },
-        "4100030B",
-        "add w1, w2, w3",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::Add,
-            size: OperandSize::Size64,
-            rd: writable_xreg(4),
-            rn: xreg(5),
-            rm: xreg(6),
-        },
-        "A400068B",
-        "add x4, x5, x6",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::Adc,
-            size: OperandSize::Size32,
-            rd: writable_xreg(1),
-            rn: xreg(2),
-            rm: xreg(3),
-        },
-        "4100031A",
-        "adc w1, w2, w3",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::Adc,
-            size: OperandSize::Size64,
-            rd: writable_xreg(4),
-            rn: xreg(5),
-            rm: xreg(6),
-        },
-        "A400069A",
-        "adc x4, x5, x6",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::AdcS,
-            size: OperandSize::Size32,
-            rd: writable_xreg(1),
-            rn: xreg(2),
-            rm: xreg(3),
-        },
-        "4100033A",
-        "adcs w1, w2, w3",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::AdcS,
-            size: OperandSize::Size64,
-            rd: writable_xreg(4),
-            rn: xreg(5),
-            rm: xreg(6),
-        },
-        "A40006BA",
-        "adcs x4, x5, x6",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::Sub,
-            size: OperandSize::Size32,
-            rd: writable_xreg(1),
-            rn: xreg(2),
-            rm: xreg(3),
-        },
-        "4100034B",
-        "sub w1, w2, w3",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::Sub,
-            size: OperandSize::Size64,
-            rd: writable_xreg(4),
-            rn: xreg(5),
-            rm: xreg(6),
-        },
-        "A40006CB",
-        "sub x4, x5, x6",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::Sbc,
-            size: OperandSize::Size32,
-            rd: writable_xreg(1),
-            rn: xreg(2),
-            rm: xreg(3),
-        },
-        "4100035A",
-        "sbc w1, w2, w3",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::Sbc,
-            size: OperandSize::Size64,
-            rd: writable_xreg(4),
-            rn: xreg(5),
-            rm: xreg(6),
-        },
-        "A40006DA",
-        "sbc x4, x5, x6",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::SbcS,
-            size: OperandSize::Size32,
-            rd: writable_xreg(1),
-            rn: xreg(2),
-            rm: xreg(3),
-        },
-        "4100037A",
-        "sbcs w1, w2, w3",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::SbcS,
-            size: OperandSize::Size64,
-            rd: writable_xreg(4),
-            rn: xreg(5),
-            rm: xreg(6),
-        },
-        "A40006FA",
-        "sbcs x4, x5, x6",
-    ));
-
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::Orr,
-            size: OperandSize::Size32,
-            rd: writable_xreg(1),
-            rn: xreg(2),
-            rm: xreg(3),
-        },
-        "4100032A",
-        "orr w1, w2, w3",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::Orr,
-            size: OperandSize::Size64,
-            rd: writable_xreg(4),
-            rn: xreg(5),
-            rm: xreg(6),
-        },
-        "A40006AA",
-        "orr x4, x5, x6",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::And,
-            size: OperandSize::Size32,
-            rd: writable_xreg(1),
-            rn: xreg(2),
-            rm: xreg(3),
-        },
-        "4100030A",
-        "and w1, w2, w3",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::And,
-            size: OperandSize::Size64,
-            rd: writable_xreg(4),
-            rn: xreg(5),
-            rm: xreg(6),
-        },
-        "A400068A",
-        "and x4, x5, x6",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::AndS,
-            size: OperandSize::Size32,
-            rd: writable_xreg(1),
-            rn: xreg(2),
-            rm: xreg(3),
-        },
-        "4100036A",
-        "ands w1, w2, w3",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::AndS,
-            size: OperandSize::Size64,
-            rd: writable_xreg(4),
-            rn: xreg(5),
-            rm: xreg(6),
-        },
-        "A40006EA",
-        "ands x4, x5, x6",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::SubS,
-            size: OperandSize::Size32,
-            rd: writable_zero_reg(),
-            rn: xreg(2),
-            rm: xreg(3),
-        },
-        "5F00036B",
-        // TODO: Display as cmp
-        "subs wzr, w2, w3",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::SubS,
-            size: OperandSize::Size32,
-            rd: writable_xreg(1),
-            rn: xreg(2),
-            rm: xreg(3),
-        },
-        "4100036B",
-        "subs w1, w2, w3",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::SubS,
-            size: OperandSize::Size64,
-            rd: writable_xreg(4),
-            rn: xreg(5),
-            rm: xreg(6),
-        },
-        "A40006EB",
-        "subs x4, x5, x6",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::AddS,
-            size: OperandSize::Size32,
-            rd: writable_xreg(1),
-            rn: xreg(2),
-            rm: xreg(3),
-        },
-        "4100032B",
-        "adds w1, w2, w3",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::AddS,
-            size: OperandSize::Size64,
-            rd: writable_xreg(4),
-            rn: xreg(5),
-            rm: xreg(6),
-        },
-        "A40006AB",
-        "adds x4, x5, x6",
-    ));
-    insns.push((
-        Inst::AluRRImm12 {
-            alu_op: ALUOp::AddS,
-            size: OperandSize::Size64,
-            rd: writable_zero_reg(),
-            rn: xreg(5),
-            imm12: Imm12::maybe_from_u64(1).unwrap(),
-        },
-        "BF0400B1",
-        // TODO: Display as cmn.
-        "adds xzr, x5, #1",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::SDiv,
-            size: OperandSize::Size64,
-            rd: writable_xreg(4),
-            rn: xreg(5),
-            rm: xreg(6),
-        },
-        "A40CC69A",
-        "sdiv x4, x5, x6",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::UDiv,
-            size: OperandSize::Size64,
-            rd: writable_xreg(4),
-            rn: xreg(5),
-            rm: xreg(6),
-        },
-        "A408C69A",
-        "udiv x4, x5, x6",
-    ));
-
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::Eor,
-            size: OperandSize::Size32,
-            rd: writable_xreg(4),
-            rn: xreg(5),
-            rm: xreg(6),
-        },
-        "A400064A",
-        "eor w4, w5, w6",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::Eor,
-            size: OperandSize::Size64,
-            rd: writable_xreg(4),
-            rn: xreg(5),
-            rm: xreg(6),
-        },
-        "A40006CA",
-        "eor x4, x5, x6",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::AndNot,
-            size: OperandSize::Size32,
-            rd: writable_xreg(4),
-            rn: xreg(5),
-            rm: xreg(6),
-        },
-        "A400260A",
-        "bic w4, w5, w6",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::AndNot,
-            size: OperandSize::Size64,
-            rd: writable_xreg(4),
-            rn: xreg(5),
-            rm: xreg(6),
-        },
-        "A400268A",
-        "bic x4, x5, x6",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::OrrNot,
-            size: OperandSize::Size32,
-            rd: writable_xreg(4),
-            rn: xreg(5),
-            rm: xreg(6),
-        },
-        "A400262A",
-        "orn w4, w5, w6",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::OrrNot,
-            size: OperandSize::Size64,
-            rd: writable_xreg(4),
-            rn: xreg(5),
-            rm: xreg(6),
-        },
-        "A40026AA",
-        "orn x4, x5, x6",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::EorNot,
-            size: OperandSize::Size32,
-            rd: writable_xreg(4),
-            rn: xreg(5),
-            rm: xreg(6),
-        },
-        "A400264A",
-        "eon w4, w5, w6",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::EorNot,
-            size: OperandSize::Size64,
-            rd: writable_xreg(4),
-            rn: xreg(5),
-            rm: xreg(6),
-        },
-        "A40026CA",
-        "eon x4, x5, x6",
-    ));
-
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::RotR,
-            size: OperandSize::Size32,
-            rd: writable_xreg(4),
-            rn: xreg(5),
-            rm: xreg(6),
-        },
-        "A42CC61A",
-        "ror w4, w5, w6",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::RotR,
-            size: OperandSize::Size64,
-            rd: writable_xreg(4),
-            rn: xreg(5),
-            rm: xreg(6),
-        },
-        "A42CC69A",
-        "ror x4, x5, x6",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::Lsr,
-            size: OperandSize::Size32,
-            rd: writable_xreg(4),
-            rn: xreg(5),
-            rm: xreg(6),
-        },
-        "A424C61A",
-        "lsr w4, w5, w6",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::Lsr,
-            size: OperandSize::Size64,
-            rd: writable_xreg(4),
-            rn: xreg(5),
-            rm: xreg(6),
-        },
-        "A424C69A",
-        "lsr x4, x5, x6",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::Asr,
-            size: OperandSize::Size32,
-            rd: writable_xreg(4),
-            rn: xreg(5),
-            rm: xreg(6),
-        },
-        "A428C61A",
-        "asr w4, w5, w6",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::Asr,
-            size: OperandSize::Size64,
-            rd: writable_xreg(4),
-            rn: xreg(5),
-            rm: xreg(6),
-        },
-        "A428C69A",
-        "asr x4, x5, x6",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::Lsl,
-            size: OperandSize::Size32,
-            rd: writable_xreg(4),
-            rn: xreg(5),
-            rm: xreg(6),
-        },
-        "A420C61A",
-        "lsl w4, w5, w6",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::Lsl,
-            size: OperandSize::Size64,
-            rd: writable_xreg(4),
-            rn: xreg(5),
-            rm: xreg(6),
-        },
-        "A420C69A",
-        "lsl x4, x5, x6",
-    ));
-
-    insns.push((
-        Inst::AluRRImm12 {
-            alu_op: ALUOp::Add,
-            size: OperandSize::Size32,
-            rd: writable_xreg(7),
-            rn: xreg(8),
-            imm12: Imm12 {
-                bits: 0x123,
-                shift12: false,
-            },
-        },
-        "078D0411",
-        "add w7, w8, #291",
-    ));
-    insns.push((
-        Inst::AluRRImm12 {
-            alu_op: ALUOp::Add,
-            size: OperandSize::Size32,
-            rd: writable_xreg(7),
-            rn: xreg(8),
-            imm12: Imm12 {
-                bits: 0x123,
-                shift12: true,
-            },
-        },
-        "078D4411",
-        "add w7, w8, #1191936",
-    ));
-    insns.push((
-        Inst::AluRRImm12 {
-            alu_op: ALUOp::Add,
-            size: OperandSize::Size64,
-            rd: writable_xreg(7),
-            rn: xreg(8),
-            imm12: Imm12 {
-                bits: 0x123,
-                shift12: false,
-            },
-        },
-        "078D0491",
-        "add x7, x8, #291",
-    ));
-    insns.push((
-        Inst::AluRRImm12 {
-            alu_op: ALUOp::Sub,
-            size: OperandSize::Size32,
-            rd: writable_xreg(7),
-            rn: xreg(8),
-            imm12: Imm12 {
-                bits: 0x123,
-                shift12: false,
-            },
-        },
-        "078D0451",
-        "sub w7, w8, #291",
-    ));
-    insns.push((
-        Inst::AluRRImm12 {
-            alu_op: ALUOp::Sub,
-            size: OperandSize::Size64,
-            rd: writable_xreg(7),
-            rn: xreg(8),
-            imm12: Imm12 {
-                bits: 0x123,
-                shift12: false,
-            },
-        },
-        "078D04D1",
-        "sub x7, x8, #291",
-    ));
-    insns.push((
-        Inst::AluRRImm12 {
-            alu_op: ALUOp::SubS,
-            size: OperandSize::Size32,
-            rd: writable_xreg(7),
-            rn: xreg(8),
-            imm12: Imm12 {
-                bits: 0x123,
-                shift12: false,
-            },
-        },
-        "078D0471",
-        "subs w7, w8, #291",
-    ));
-    insns.push((
-        Inst::AluRRImm12 {
-            alu_op: ALUOp::SubS,
-            size: OperandSize::Size64,
-            rd: writable_xreg(7),
-            rn: xreg(8),
-            imm12: Imm12 {
-                bits: 0x123,
-                shift12: false,
-            },
-        },
-        "078D04F1",
-        "subs x7, x8, #291",
-    ));
-
-    insns.push((
-        Inst::AluRRRExtend {
-            alu_op: ALUOp::Add,
-            size: OperandSize::Size32,
-            rd: writable_xreg(7),
-            rn: xreg(8),
-            rm: xreg(9),
-            extendop: ExtendOp::SXTB,
-        },
-        "0781290B",
-        "add w7, w8, w9, SXTB",
-    ));
-
-    insns.push((
-        Inst::AluRRRExtend {
-            alu_op: ALUOp::Add,
-            size: OperandSize::Size64,
-            rd: writable_xreg(15),
-            rn: xreg(16),
-            rm: xreg(17),
-            extendop: ExtendOp::UXTB,
-        },
-        "0F02318B",
-        "add x15, x16, x17, UXTB",
-    ));
-
-    insns.push((
-        Inst::AluRRRExtend {
-            alu_op: ALUOp::Sub,
-            size: OperandSize::Size32,
-            rd: writable_xreg(1),
-            rn: xreg(2),
-            rm: xreg(3),
-            extendop: ExtendOp::SXTH,
-        },
-        "41A0234B",
-        "sub w1, w2, w3, SXTH",
-    ));
-
-    insns.push((
-        Inst::AluRRRExtend {
-            alu_op: ALUOp::Sub,
-            size: OperandSize::Size64,
-            rd: writable_xreg(20),
-            rn: xreg(21),
-            rm: xreg(22),
-            extendop: ExtendOp::UXTW,
-        },
-        "B44236CB",
-        "sub x20, x21, x22, UXTW",
-    ));
-
-    insns.push((
-        Inst::AluRRRShift {
-            alu_op: ALUOp::Add,
-            size: OperandSize::Size32,
-            rd: writable_xreg(10),
-            rn: xreg(11),
-            rm: xreg(12),
-            shiftop: ShiftOpAndAmt::new(
-                ShiftOp::LSL,
-                ShiftOpShiftImm::maybe_from_shift(20).unwrap(),
-            ),
-        },
-        "6A510C0B",
-        "add w10, w11, w12, LSL 20",
-    ));
-    insns.push((
-        Inst::AluRRRShift {
-            alu_op: ALUOp::Add,
-            size: OperandSize::Size64,
-            rd: writable_xreg(10),
-            rn: xreg(11),
-            rm: xreg(12),
-            shiftop: ShiftOpAndAmt::new(
-                ShiftOp::ASR,
-                ShiftOpShiftImm::maybe_from_shift(42).unwrap(),
-            ),
-        },
-        "6AA98C8B",
-        "add x10, x11, x12, ASR 42",
-    ));
-    insns.push((
-        Inst::AluRRRShift {
-            alu_op: ALUOp::Sub,
-            size: OperandSize::Size32,
-            rd: writable_xreg(10),
-            rn: xreg(11),
-            rm: xreg(12),
-            shiftop: ShiftOpAndAmt::new(
-                ShiftOp::LSL,
-                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
-            ),
-        },
-        "6A5D0C4B",
-        "sub w10, w11, w12, LSL 23",
-    ));
-    insns.push((
-        Inst::AluRRRShift {
-            alu_op: ALUOp::Sub,
-            size: OperandSize::Size64,
-            rd: writable_xreg(10),
-            rn: xreg(11),
-            rm: xreg(12),
-            shiftop: ShiftOpAndAmt::new(
-                ShiftOp::LSL,
-                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
-            ),
-        },
-        "6A5D0CCB",
-        "sub x10, x11, x12, LSL 23",
-    ));
-    insns.push((
-        Inst::AluRRRShift {
-            alu_op: ALUOp::Orr,
-            size: OperandSize::Size32,
-            rd: writable_xreg(10),
-            rn: xreg(11),
-            rm: xreg(12),
-            shiftop: ShiftOpAndAmt::new(
-                ShiftOp::LSL,
-                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
-            ),
-        },
-        "6A5D0C2A",
-        "orr w10, w11, w12, LSL 23",
-    ));
-    insns.push((
-        Inst::AluRRRShift {
-            alu_op: ALUOp::Orr,
-            size: OperandSize::Size64,
-            rd: writable_xreg(10),
-            rn: xreg(11),
-            rm: xreg(12),
-            shiftop: ShiftOpAndAmt::new(
-                ShiftOp::LSL,
-                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
-            ),
-        },
-        "6A5D0CAA",
-        "orr x10, x11, x12, LSL 23",
-    ));
-    insns.push((
-        Inst::AluRRRShift {
-            alu_op: ALUOp::And,
-            size: OperandSize::Size32,
-            rd: writable_xreg(10),
-            rn: xreg(11),
-            rm: xreg(12),
-            shiftop: ShiftOpAndAmt::new(
-                ShiftOp::LSL,
-                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
-            ),
-        },
-        "6A5D0C0A",
-        "and w10, w11, w12, LSL 23",
-    ));
-    insns.push((
-        Inst::AluRRRShift {
-            alu_op: ALUOp::And,
-            size: OperandSize::Size64,
-            rd: writable_xreg(10),
-            rn: xreg(11),
-            rm: xreg(12),
-            shiftop: ShiftOpAndAmt::new(
-                ShiftOp::LSL,
-                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
-            ),
-        },
-        "6A5D0C8A",
-        "and x10, x11, x12, LSL 23",
-    ));
-    insns.push((
-        Inst::AluRRRShift {
-            alu_op: ALUOp::AndS,
-            size: OperandSize::Size32,
-            rd: writable_xreg(10),
-            rn: xreg(11),
-            rm: xreg(12),
-            shiftop: ShiftOpAndAmt::new(
-                ShiftOp::LSL,
-                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
-            ),
-        },
-        "6A5D0C6A",
-        "ands w10, w11, w12, LSL 23",
-    ));
-    insns.push((
-        Inst::AluRRRShift {
-            alu_op: ALUOp::AndS,
-            size: OperandSize::Size64,
-            rd: writable_xreg(10),
-            rn: xreg(11),
-            rm: xreg(12),
-            shiftop: ShiftOpAndAmt::new(
-                ShiftOp::LSL,
-                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
-            ),
-        },
-        "6A5D0CEA",
-        "ands x10, x11, x12, LSL 23",
-    ));
-    insns.push((
-        Inst::AluRRRShift {
-            alu_op: ALUOp::Eor,
-            size: OperandSize::Size32,
-            rd: writable_xreg(10),
-            rn: xreg(11),
-            rm: xreg(12),
-            shiftop: ShiftOpAndAmt::new(
-                ShiftOp::LSL,
-                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
-            ),
-        },
-        "6A5D0C4A",
-        "eor w10, w11, w12, LSL 23",
-    ));
-    insns.push((
-        Inst::AluRRRShift {
-            alu_op: ALUOp::Eor,
-            size: OperandSize::Size64,
-            rd: writable_xreg(10),
-            rn: xreg(11),
-            rm: xreg(12),
-            shiftop: ShiftOpAndAmt::new(
-                ShiftOp::LSL,
-                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
-            ),
-        },
-        "6A5D0CCA",
-        "eor x10, x11, x12, LSL 23",
-    ));
-    insns.push((
-        Inst::AluRRRShift {
-            alu_op: ALUOp::OrrNot,
-            size: OperandSize::Size32,
-            rd: writable_xreg(10),
-            rn: xreg(11),
-            rm: xreg(12),
-            shiftop: ShiftOpAndAmt::new(
-                ShiftOp::LSL,
-                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
-            ),
-        },
-        "6A5D2C2A",
-        "orn w10, w11, w12, LSL 23",
-    ));
-    insns.push((
-        Inst::AluRRRShift {
-            alu_op: ALUOp::OrrNot,
-            size: OperandSize::Size64,
-            rd: writable_xreg(10),
-            rn: xreg(11),
-            rm: xreg(12),
-            shiftop: ShiftOpAndAmt::new(
-                ShiftOp::LSL,
-                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
-            ),
-        },
-        "6A5D2CAA",
-        "orn x10, x11, x12, LSL 23",
-    ));
-    insns.push((
-        Inst::AluRRRShift {
-            alu_op: ALUOp::AndNot,
-            size: OperandSize::Size32,
-            rd: writable_xreg(10),
-            rn: xreg(11),
-            rm: xreg(12),
-            shiftop: ShiftOpAndAmt::new(
-                ShiftOp::LSL,
-                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
-            ),
-        },
-        "6A5D2C0A",
-        "bic w10, w11, w12, LSL 23",
-    ));
-    insns.push((
-        Inst::AluRRRShift {
-            alu_op: ALUOp::AndNot,
-            size: OperandSize::Size64,
-            rd: writable_xreg(10),
-            rn: xreg(11),
-            rm: xreg(12),
-            shiftop: ShiftOpAndAmt::new(
-                ShiftOp::LSL,
-                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
-            ),
-        },
-        "6A5D2C8A",
-        "bic x10, x11, x12, LSL 23",
-    ));
-    insns.push((
-        Inst::AluRRRShift {
-            alu_op: ALUOp::EorNot,
-            size: OperandSize::Size32,
-            rd: writable_xreg(10),
-            rn: xreg(11),
-            rm: xreg(12),
-            shiftop: ShiftOpAndAmt::new(
-                ShiftOp::LSL,
-                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
-            ),
-        },
-        "6A5D2C4A",
-        "eon w10, w11, w12, LSL 23",
-    ));
-    insns.push((
-        Inst::AluRRRShift {
-            alu_op: ALUOp::EorNot,
-            size: OperandSize::Size64,
-            rd: writable_xreg(10),
-            rn: xreg(11),
-            rm: xreg(12),
-            shiftop: ShiftOpAndAmt::new(
-                ShiftOp::LSL,
-                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
-            ),
-        },
-        "6A5D2CCA",
-        "eon x10, x11, x12, LSL 23",
-    ));
-    insns.push((
-        Inst::AluRRRShift {
-            alu_op: ALUOp::AddS,
-            size: OperandSize::Size32,
-            rd: writable_xreg(10),
-            rn: xreg(11),
-            rm: xreg(12),
-            shiftop: ShiftOpAndAmt::new(
-                ShiftOp::LSL,
-                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
-            ),
-        },
-        "6A5D0C2B",
-        "adds w10, w11, w12, LSL 23",
-    ));
-    insns.push((
-        Inst::AluRRRShift {
-            alu_op: ALUOp::AddS,
-            size: OperandSize::Size64,
-            rd: writable_xreg(10),
-            rn: xreg(11),
-            rm: xreg(12),
-            shiftop: ShiftOpAndAmt::new(
-                ShiftOp::LSL,
-                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
-            ),
-        },
-        "6A5D0CAB",
-        "adds x10, x11, x12, LSL 23",
-    ));
-    insns.push((
-        Inst::AluRRRShift {
-            alu_op: ALUOp::SubS,
-            size: OperandSize::Size32,
-            rd: writable_xreg(10),
-            rn: xreg(11),
-            rm: xreg(12),
-            shiftop: ShiftOpAndAmt::new(
-                ShiftOp::LSL,
-                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
-            ),
-        },
-        "6A5D0C6B",
-        "subs w10, w11, w12, LSL 23",
-    ));
-    insns.push((
-        Inst::AluRRRShift {
-            alu_op: ALUOp::SubS,
-            size: OperandSize::Size64,
-            rd: writable_xreg(10),
-            rn: xreg(11),
-            rm: xreg(12),
-            shiftop: ShiftOpAndAmt::new(
-                ShiftOp::LSL,
-                ShiftOpShiftImm::maybe_from_shift(23).unwrap(),
-            ),
-        },
-        "6A5D0CEB",
-        "subs x10, x11, x12, LSL 23",
-    ));
-
-    insns.push((
-        Inst::AluRRRExtend {
-            alu_op: ALUOp::SubS,
-            size: OperandSize::Size64,
-            rd: writable_zero_reg(),
-            rn: stack_reg(),
-            rm: xreg(12),
-            extendop: ExtendOp::UXTX,
-        },
-        "FF632CEB",
-        "subs xzr, sp, x12, UXTX",
-    ));
-
-    insns.push((
-        Inst::AluRRRR {
-            alu_op: ALUOp3::MAdd32,
-            rd: writable_xreg(1),
-            rn: xreg(2),
-            rm: xreg(3),
-            ra: xreg(4),
-        },
-        "4110031B",
-        "madd w1, w2, w3, w4",
-    ));
-    insns.push((
-        Inst::AluRRRR {
-            alu_op: ALUOp3::MAdd64,
-            rd: writable_xreg(1),
-            rn: xreg(2),
-            rm: xreg(3),
-            ra: xreg(4),
-        },
-        "4110039B",
-        "madd x1, x2, x3, x4",
-    ));
-    insns.push((
-        Inst::AluRRRR {
-            alu_op: ALUOp3::MSub32,
-            rd: writable_xreg(1),
-            rn: xreg(2),
-            rm: xreg(3),
-            ra: xreg(4),
-        },
-        "4190031B",
-        "msub w1, w2, w3, w4",
-    ));
-    insns.push((
-        Inst::AluRRRR {
-            alu_op: ALUOp3::MSub64,
-            rd: writable_xreg(1),
-            rn: xreg(2),
-            rm: xreg(3),
-            ra: xreg(4),
-        },
-        "4190039B",
-        "msub x1, x2, x3, x4",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::SMulH,
-            size: OperandSize::Size64,
-            rd: writable_xreg(1),
-            rn: xreg(2),
-            rm: xreg(3),
-        },
-        "417C439B",
-        "smulh x1, x2, x3",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::UMulH,
-            size: OperandSize::Size64,
-            rd: writable_xreg(1),
-            rn: xreg(2),
-            rm: xreg(3),
-        },
-        "417CC39B",
-        "umulh x1, x2, x3",
-    ));
-
-    insns.push((
-        Inst::AluRRImmShift {
-            alu_op: ALUOp::RotR,
-            size: OperandSize::Size32,
-            rd: writable_xreg(20),
-            rn: xreg(21),
-            immshift: ImmShift::maybe_from_u64(19).unwrap(),
-        },
-        "B44E9513",
-        "ror w20, w21, #19",
-    ));
-    insns.push((
-        Inst::AluRRImmShift {
-            alu_op: ALUOp::RotR,
-            size: OperandSize::Size64,
-            rd: writable_xreg(20),
-            rn: xreg(21),
-            immshift: ImmShift::maybe_from_u64(42).unwrap(),
-        },
-        "B4AAD593",
-        "ror x20, x21, #42",
-    ));
-    insns.push((
-        Inst::AluRRImmShift {
-            alu_op: ALUOp::Lsr,
-            size: OperandSize::Size32,
-            rd: writable_xreg(10),
-            rn: xreg(11),
-            immshift: ImmShift::maybe_from_u64(13).unwrap(),
-        },
-        "6A7D0D53",
-        "lsr w10, w11, #13",
-    ));
-    insns.push((
-        Inst::AluRRImmShift {
-            alu_op: ALUOp::Lsr,
-            size: OperandSize::Size64,
-            rd: writable_xreg(10),
-            rn: xreg(11),
-            immshift: ImmShift::maybe_from_u64(57).unwrap(),
-        },
-        "6AFD79D3",
-        "lsr x10, x11, #57",
-    ));
-    insns.push((
-        Inst::AluRRImmShift {
-            alu_op: ALUOp::Asr,
-            size: OperandSize::Size32,
-            rd: writable_xreg(4),
-            rn: xreg(5),
-            immshift: ImmShift::maybe_from_u64(7).unwrap(),
-        },
-        "A47C0713",
-        "asr w4, w5, #7",
-    ));
-    insns.push((
-        Inst::AluRRImmShift {
-            alu_op: ALUOp::Asr,
-            size: OperandSize::Size64,
-            rd: writable_xreg(4),
-            rn: xreg(5),
-            immshift: ImmShift::maybe_from_u64(35).unwrap(),
-        },
-        "A4FC6393",
-        "asr x4, x5, #35",
-    ));
-    insns.push((
-        Inst::AluRRImmShift {
-            alu_op: ALUOp::Lsl,
-            size: OperandSize::Size32,
-            rd: writable_xreg(8),
-            rn: xreg(9),
-            immshift: ImmShift::maybe_from_u64(24).unwrap(),
-        },
-        "281D0853",
-        "lsl w8, w9, #24",
-    ));
-    insns.push((
-        Inst::AluRRImmShift {
-            alu_op: ALUOp::Lsl,
-            size: OperandSize::Size64,
-            rd: writable_xreg(8),
-            rn: xreg(9),
-            immshift: ImmShift::maybe_from_u64(63).unwrap(),
-        },
-        "280141D3",
-        "lsl x8, x9, #63",
-    ));
-    insns.push((
-        Inst::AluRRImmShift {
-            alu_op: ALUOp::Lsl,
-            size: OperandSize::Size32,
-            rd: writable_xreg(10),
-            rn: xreg(11),
-            immshift: ImmShift::maybe_from_u64(0).unwrap(),
-        },
-        "6A7D0053",
-        "lsl w10, w11, #0",
-    ));
-    insns.push((
-        Inst::AluRRImmShift {
-            alu_op: ALUOp::Lsl,
-            size: OperandSize::Size64,
-            rd: writable_xreg(10),
-            rn: xreg(11),
-            immshift: ImmShift::maybe_from_u64(0).unwrap(),
-        },
-        "6AFD40D3",
-        "lsl x10, x11, #0",
-    ));
-
-    insns.push((
-        Inst::AluRRImmLogic {
-            alu_op: ALUOp::And,
-            size: OperandSize::Size32,
-            rd: writable_xreg(21),
-            rn: xreg(27),
-            imml: ImmLogic::maybe_from_u64(0x80003fff, I32).unwrap(),
-        },
-        "753B0112",
-        "and w21, w27, #2147500031",
-    ));
-    insns.push((
-        Inst::AluRRImmLogic {
-            alu_op: ALUOp::And,
-            size: OperandSize::Size64,
-            rd: writable_xreg(7),
-            rn: xreg(6),
-            imml: ImmLogic::maybe_from_u64(0x3fff80003fff800, I64).unwrap(),
-        },
-        "C7381592",
-        "and x7, x6, #288221580125796352",
-    ));
-    insns.push((
-        Inst::AluRRImmLogic {
-            alu_op: ALUOp::AndS,
-            size: OperandSize::Size32,
-            rd: writable_xreg(21),
-            rn: xreg(27),
-            imml: ImmLogic::maybe_from_u64(0x80003fff, I32).unwrap(),
-        },
-        "753B0172",
-        "ands w21, w27, #2147500031",
-    ));
-    insns.push((
-        Inst::AluRRImmLogic {
-            alu_op: ALUOp::AndS,
-            size: OperandSize::Size64,
-            rd: writable_xreg(7),
-            rn: xreg(6),
-            imml: ImmLogic::maybe_from_u64(0x3fff80003fff800, I64).unwrap(),
-        },
-        "C73815F2",
-        "ands x7, x6, #288221580125796352",
-    ));
-    insns.push((
-        Inst::AluRRImmLogic {
-            alu_op: ALUOp::Orr,
-            size: OperandSize::Size32,
-            rd: writable_xreg(1),
-            rn: xreg(5),
-            imml: ImmLogic::maybe_from_u64(0x100000, I32).unwrap(),
-        },
-        "A1000C32",
-        "orr w1, w5, #1048576",
-    ));
-    insns.push((
-        Inst::AluRRImmLogic {
-            alu_op: ALUOp::Orr,
-            size: OperandSize::Size64,
-            rd: writable_xreg(4),
-            rn: xreg(5),
-            imml: ImmLogic::maybe_from_u64(0x8181818181818181, I64).unwrap(),
-        },
-        "A4C401B2",
-        "orr x4, x5, #9331882296111890817",
-    ));
-    insns.push((
-        Inst::AluRRImmLogic {
-            alu_op: ALUOp::Eor,
-            size: OperandSize::Size32,
-            rd: writable_xreg(1),
-            rn: xreg(5),
-            imml: ImmLogic::maybe_from_u64(0x00007fff, I32).unwrap(),
-        },
-        "A1380052",
-        "eor w1, w5, #32767",
-    ));
-    insns.push((
-        Inst::AluRRImmLogic {
-            alu_op: ALUOp::Eor,
-            size: OperandSize::Size64,
-            rd: writable_xreg(10),
-            rn: xreg(8),
-            imml: ImmLogic::maybe_from_u64(0x8181818181818181, I64).unwrap(),
-        },
-        "0AC501D2",
-        "eor x10, x8, #9331882296111890817",
-    ));
-
-    insns.push((
-        Inst::BitRR {
-            op: BitOp::RBit,
-            size: OperandSize::Size32,
-            rd: writable_xreg(1),
-            rn: xreg(10),
-        },
-        "4101C05A",
-        "rbit w1, w10",
-    ));
-
-    insns.push((
-        Inst::BitRR {
-            op: BitOp::RBit,
-            size: OperandSize::Size64,
-            rd: writable_xreg(1),
-            rn: xreg(10),
-        },
-        "4101C0DA",
-        "rbit x1, x10",
-    ));
-
-    insns.push((
-        Inst::BitRR {
-            op: BitOp::Clz,
-            size: OperandSize::Size32,
-            rd: writable_xreg(15),
-            rn: xreg(3),
-        },
-        "6F10C05A",
-        "clz w15, w3",
-    ));
-
-    insns.push((
-        Inst::BitRR {
-            op: BitOp::Clz,
-            size: OperandSize::Size64,
-            rd: writable_xreg(15),
-            rn: xreg(3),
-        },
-        "6F10C0DA",
-        "clz x15, x3",
-    ));
-
-    insns.push((
-        Inst::BitRR {
-            op: BitOp::Cls,
-            size: OperandSize::Size32,
-            rd: writable_xreg(21),
-            rn: xreg(16),
-        },
-        "1516C05A",
-        "cls w21, w16",
-    ));
-
-    insns.push((
-        Inst::BitRR {
-            op: BitOp::Cls,
-            size: OperandSize::Size64,
-            rd: writable_xreg(21),
-            rn: xreg(16),
-        },
-        "1516C0DA",
-        "cls x21, x16",
-    ));
-
-    insns.push((
-        Inst::ULoad8 {
-            rd: writable_xreg(1),
-            mem: AMode::Unscaled(xreg(2), SImm9::zero()),
-            flags: MemFlags::trusted(),
-        },
-        "41004038",
-        "ldurb w1, [x2]",
-    ));
-    insns.push((
-        Inst::ULoad8 {
-            rd: writable_xreg(1),
-            mem: AMode::UnsignedOffset(xreg(2), UImm12Scaled::zero(I8)),
-            flags: MemFlags::trusted(),
-        },
-        "41004039",
-        "ldrb w1, [x2]",
-    ));
-    insns.push((
-        Inst::ULoad8 {
-            rd: writable_xreg(1),
-            mem: AMode::RegReg(xreg(2), xreg(5)),
-            flags: MemFlags::trusted(),
-        },
-        "41686538",
-        "ldrb w1, [x2, x5]",
-    ));
-    insns.push((
-        Inst::SLoad8 {
-            rd: writable_xreg(1),
-            mem: AMode::Unscaled(xreg(2), SImm9::zero()),
-            flags: MemFlags::trusted(),
-        },
-        "41008038",
-        "ldursb x1, [x2]",
-    ));
-    insns.push((
-        Inst::SLoad8 {
-            rd: writable_xreg(1),
-            mem: AMode::UnsignedOffset(xreg(2), UImm12Scaled::maybe_from_i64(63, I8).unwrap()),
-            flags: MemFlags::trusted(),
-        },
-        "41FC8039",
-        "ldrsb x1, [x2, #63]",
-    ));
-    insns.push((
-        Inst::SLoad8 {
-            rd: writable_xreg(1),
-            mem: AMode::RegReg(xreg(2), xreg(5)),
-            flags: MemFlags::trusted(),
-        },
-        "4168A538",
-        "ldrsb x1, [x2, x5]",
-    ));
-    insns.push((
-        Inst::ULoad16 {
-            rd: writable_xreg(1),
-            mem: AMode::Unscaled(xreg(2), SImm9::maybe_from_i64(5).unwrap()),
-            flags: MemFlags::trusted(),
-        },
-        "41504078",
-        "ldurh w1, [x2, #5]",
-    ));
-    insns.push((
-        Inst::ULoad16 {
-            rd: writable_xreg(1),
-            mem: AMode::UnsignedOffset(xreg(2), UImm12Scaled::maybe_from_i64(8, I16).unwrap()),
-            flags: MemFlags::trusted(),
-        },
-        "41104079",
-        "ldrh w1, [x2, #8]",
-    ));
-    insns.push((
-        Inst::ULoad16 {
-            rd: writable_xreg(1),
-            mem: AMode::RegScaled(xreg(2), xreg(3), I16),
-            flags: MemFlags::trusted(),
-        },
-        "41786378",
-        "ldrh w1, [x2, x3, LSL #1]",
-    ));
-    insns.push((
-        Inst::SLoad16 {
-            rd: writable_xreg(1),
-            mem: AMode::Unscaled(xreg(2), SImm9::zero()),
-            flags: MemFlags::trusted(),
-        },
-        "41008078",
-        "ldursh x1, [x2]",
-    ));
-    insns.push((
-        Inst::SLoad16 {
-            rd: writable_xreg(28),
-            mem: AMode::UnsignedOffset(xreg(20), UImm12Scaled::maybe_from_i64(24, I16).unwrap()),
-            flags: MemFlags::trusted(),
-        },
-        "9C328079",
-        "ldrsh x28, [x20, #24]",
-    ));
-    insns.push((
-        Inst::SLoad16 {
-            rd: writable_xreg(28),
-            mem: AMode::RegScaled(xreg(20), xreg(20), I16),
-            flags: MemFlags::trusted(),
-        },
-        "9C7AB478",
-        "ldrsh x28, [x20, x20, LSL #1]",
-    ));
-    insns.push((
-        Inst::ULoad32 {
-            rd: writable_xreg(1),
-            mem: AMode::Unscaled(xreg(2), SImm9::zero()),
-            flags: MemFlags::trusted(),
-        },
-        "410040B8",
-        "ldur w1, [x2]",
-    ));
-    insns.push((
-        Inst::ULoad32 {
-            rd: writable_xreg(12),
-            mem: AMode::UnsignedOffset(xreg(0), UImm12Scaled::maybe_from_i64(204, I32).unwrap()),
-            flags: MemFlags::trusted(),
-        },
-        "0CCC40B9",
-        "ldr w12, [x0, #204]",
-    ));
-    insns.push((
-        Inst::ULoad32 {
-            rd: writable_xreg(1),
-            mem: AMode::RegScaled(xreg(2), xreg(12), I32),
-            flags: MemFlags::trusted(),
-        },
-        "41786CB8",
-        "ldr w1, [x2, x12, LSL #2]",
-    ));
-    insns.push((
-        Inst::SLoad32 {
-            rd: writable_xreg(1),
-            mem: AMode::Unscaled(xreg(2), SImm9::zero()),
-            flags: MemFlags::trusted(),
-        },
-        "410080B8",
-        "ldursw x1, [x2]",
-    ));
-    insns.push((
-        Inst::SLoad32 {
-            rd: writable_xreg(12),
-            mem: AMode::UnsignedOffset(xreg(1), UImm12Scaled::maybe_from_i64(16380, I32).unwrap()),
-            flags: MemFlags::trusted(),
-        },
-        "2CFCBFB9",
-        "ldrsw x12, [x1, #16380]",
-    ));
-    insns.push((
-        Inst::SLoad32 {
-            rd: writable_xreg(1),
-            mem: AMode::RegScaled(xreg(5), xreg(1), I32),
-            flags: MemFlags::trusted(),
-        },
-        "A178A1B8",
-        "ldrsw x1, [x5, x1, LSL #2]",
-    ));
-    insns.push((
-        Inst::ULoad64 {
-            rd: writable_xreg(1),
-            mem: AMode::Unscaled(xreg(2), SImm9::zero()),
-            flags: MemFlags::trusted(),
-        },
-        "410040F8",
-        "ldur x1, [x2]",
-    ));
-    insns.push((
-        Inst::ULoad64 {
-            rd: writable_xreg(1),
-            mem: AMode::Unscaled(xreg(2), SImm9::maybe_from_i64(-256).unwrap()),
-            flags: MemFlags::trusted(),
-        },
-        "410050F8",
-        "ldur x1, [x2, #-256]",
-    ));
-    insns.push((
-        Inst::ULoad64 {
-            rd: writable_xreg(1),
-            mem: AMode::Unscaled(xreg(2), SImm9::maybe_from_i64(255).unwrap()),
-            flags: MemFlags::trusted(),
-        },
-        "41F04FF8",
-        "ldur x1, [x2, #255]",
-    ));
-    insns.push((
-        Inst::ULoad64 {
-            rd: writable_xreg(1),
-            mem: AMode::UnsignedOffset(xreg(2), UImm12Scaled::maybe_from_i64(32760, I64).unwrap()),
-            flags: MemFlags::trusted(),
-        },
-        "41FC7FF9",
-        "ldr x1, [x2, #32760]",
-    ));
-    insns.push((
-        Inst::ULoad64 {
-            rd: writable_xreg(1),
-            mem: AMode::RegReg(xreg(2), xreg(3)),
-            flags: MemFlags::trusted(),
-        },
-        "416863F8",
-        "ldr x1, [x2, x3]",
-    ));
-    insns.push((
-        Inst::ULoad64 {
-            rd: writable_xreg(1),
-            mem: AMode::RegScaled(xreg(2), xreg(3), I64),
-            flags: MemFlags::trusted(),
-        },
-        "417863F8",
-        "ldr x1, [x2, x3, LSL #3]",
-    ));
-    insns.push((
-        Inst::ULoad64 {
-            rd: writable_xreg(1),
-            mem: AMode::RegScaledExtended(xreg(2), xreg(3), I64, ExtendOp::SXTW),
-            flags: MemFlags::trusted(),
-        },
-        "41D863F8",
-        "ldr x1, [x2, w3, SXTW #3]",
-    ));
-    insns.push((
-        Inst::ULoad64 {
-            rd: writable_xreg(1),
-            mem: AMode::RegExtended(xreg(2), xreg(3), ExtendOp::SXTW),
-            flags: MemFlags::trusted(),
-        },
-        "41C863F8",
-        "ldr x1, [x2, w3, SXTW]",
-    ));
-    insns.push((
-        Inst::ULoad64 {
-            rd: writable_xreg(1),
-            mem: AMode::Label(MemLabel::PCRel(64)),
-            flags: MemFlags::trusted(),
-        },
-        "01020058",
-        "ldr x1, pc+64",
-    ));
-    insns.push((
-        Inst::ULoad64 {
-            rd: writable_xreg(1),
-            mem: AMode::PreIndexed(writable_xreg(2), SImm9::maybe_from_i64(16).unwrap()),
-            flags: MemFlags::trusted(),
-        },
-        "410C41F8",
-        "ldr x1, [x2, #16]!",
-    ));
-    insns.push((
-        Inst::ULoad64 {
-            rd: writable_xreg(1),
-            mem: AMode::PostIndexed(writable_xreg(2), SImm9::maybe_from_i64(16).unwrap()),
-            flags: MemFlags::trusted(),
-        },
-        "410441F8",
-        "ldr x1, [x2], #16",
-    ));
-    insns.push((
-        Inst::ULoad64 {
-            rd: writable_xreg(1),
-            mem: AMode::FPOffset(32768, I8),
-            flags: MemFlags::trusted(),
-        },
-        "100090D2B063308B010240F9",
-        "movz x16, #32768 ; add x16, fp, x16, UXTX ; ldr x1, [x16]",
-    ));
-    insns.push((
-        Inst::ULoad64 {
-            rd: writable_xreg(1),
-            mem: AMode::FPOffset(-32768, I8),
-            flags: MemFlags::trusted(),
-        },
-        "F0FF8F92B063308B010240F9",
-        "movn x16, #32767 ; add x16, fp, x16, UXTX ; ldr x1, [x16]",
-    ));
-    insns.push((
-        Inst::ULoad64 {
-            rd: writable_xreg(1),
-            mem: AMode::FPOffset(1048576, I8), // 2^20
-            flags: MemFlags::trusted(),
-        },
-        "1002A0D2B063308B010240F9",
-        "movz x16, #16, LSL #16 ; add x16, fp, x16, UXTX ; ldr x1, [x16]",
-    ));
-    insns.push((
-        Inst::ULoad64 {
-            rd: writable_xreg(1),
-            mem: AMode::FPOffset(1048576 + 1, I8), // 2^20 + 1
-            flags: MemFlags::trusted(),
-        },
-        "300080521002A072B063308B010240F9",
-        "movz w16, #1 ; movk w16, #16, LSL #16 ; add x16, fp, x16, UXTX ; ldr x1, [x16]",
-    ));
-
-    insns.push((
-        Inst::ULoad64 {
-            rd: writable_xreg(1),
-            mem: AMode::RegOffset(xreg(7), 8, I64),
-            flags: MemFlags::trusted(),
-        },
-        "E18040F8",
-        "ldur x1, [x7, #8]",
-    ));
-
-    insns.push((
-        Inst::ULoad64 {
-            rd: writable_xreg(1),
-            mem: AMode::RegOffset(xreg(7), 1024, I64),
-            flags: MemFlags::trusted(),
-        },
-        "E10042F9",
-        "ldr x1, [x7, #1024]",
-    ));
-
-    insns.push((
-        Inst::ULoad64 {
-            rd: writable_xreg(1),
-            mem: AMode::RegOffset(xreg(7), 1048576, I64),
-            flags: MemFlags::trusted(),
-        },
-        "1002A0D2F060308B010240F9",
-        "movz x16, #16, LSL #16 ; add x16, x7, x16, UXTX ; ldr x1, [x16]",
-    ));
-
-    insns.push((
-        Inst::Store8 {
-            rd: xreg(1),
-            mem: AMode::Unscaled(xreg(2), SImm9::zero()),
-            flags: MemFlags::trusted(),
-        },
-        "41000038",
-        "sturb w1, [x2]",
-    ));
-    insns.push((
-        Inst::Store8 {
-            rd: xreg(1),
-            mem: AMode::UnsignedOffset(xreg(2), UImm12Scaled::maybe_from_i64(4095, I8).unwrap()),
-            flags: MemFlags::trusted(),
-        },
-        "41FC3F39",
-        "strb w1, [x2, #4095]",
-    ));
-    insns.push((
-        Inst::Store16 {
-            rd: xreg(1),
-            mem: AMode::Unscaled(xreg(2), SImm9::zero()),
-            flags: MemFlags::trusted(),
-        },
-        "41000078",
-        "sturh w1, [x2]",
-    ));
-    insns.push((
-        Inst::Store16 {
-            rd: xreg(1),
-            mem: AMode::UnsignedOffset(xreg(2), UImm12Scaled::maybe_from_i64(8190, I16).unwrap()),
-            flags: MemFlags::trusted(),
-        },
-        "41FC3F79",
-        "strh w1, [x2, #8190]",
-    ));
-    insns.push((
-        Inst::Store32 {
-            rd: xreg(1),
-            mem: AMode::Unscaled(xreg(2), SImm9::zero()),
-            flags: MemFlags::trusted(),
-        },
-        "410000B8",
-        "stur w1, [x2]",
-    ));
-    insns.push((
-        Inst::Store32 {
-            rd: xreg(1),
-            mem: AMode::UnsignedOffset(xreg(2), UImm12Scaled::maybe_from_i64(16380, I32).unwrap()),
-            flags: MemFlags::trusted(),
-        },
-        "41FC3FB9",
-        "str w1, [x2, #16380]",
-    ));
-    insns.push((
-        Inst::Store64 {
-            rd: xreg(1),
-            mem: AMode::Unscaled(xreg(2), SImm9::zero()),
-            flags: MemFlags::trusted(),
-        },
-        "410000F8",
-        "stur x1, [x2]",
-    ));
-    insns.push((
-        Inst::Store64 {
-            rd: xreg(1),
-            mem: AMode::UnsignedOffset(xreg(2), UImm12Scaled::maybe_from_i64(32760, I64).unwrap()),
-            flags: MemFlags::trusted(),
-        },
-        "41FC3FF9",
-        "str x1, [x2, #32760]",
-    ));
-    insns.push((
-        Inst::Store64 {
-            rd: xreg(1),
-            mem: AMode::RegReg(xreg(2), xreg(3)),
-            flags: MemFlags::trusted(),
-        },
-        "416823F8",
-        "str x1, [x2, x3]",
-    ));
-    insns.push((
-        Inst::Store64 {
-            rd: xreg(1),
-            mem: AMode::RegScaled(xreg(2), xreg(3), I64),
-            flags: MemFlags::trusted(),
-        },
-        "417823F8",
-        "str x1, [x2, x3, LSL #3]",
-    ));
-    insns.push((
-        Inst::Store64 {
-            rd: xreg(1),
-            mem: AMode::RegScaledExtended(xreg(2), xreg(3), I64, ExtendOp::UXTW),
-            flags: MemFlags::trusted(),
-        },
-        "415823F8",
-        "str x1, [x2, w3, UXTW #3]",
-    ));
-    insns.push((
-        Inst::Store64 {
-            rd: xreg(1),
-            mem: AMode::RegExtended(xreg(2), xreg(3), ExtendOp::UXTW),
-            flags: MemFlags::trusted(),
-        },
-        "414823F8",
-        "str x1, [x2, w3, UXTW]",
-    ));
-    insns.push((
-        Inst::Store64 {
-            rd: xreg(1),
-            mem: AMode::PreIndexed(writable_xreg(2), SImm9::maybe_from_i64(16).unwrap()),
-            flags: MemFlags::trusted(),
-        },
-        "410C01F8",
-        "str x1, [x2, #16]!",
-    ));
-    insns.push((
-        Inst::Store64 {
-            rd: xreg(1),
-            mem: AMode::PostIndexed(writable_xreg(2), SImm9::maybe_from_i64(16).unwrap()),
-            flags: MemFlags::trusted(),
-        },
-        "410401F8",
-        "str x1, [x2], #16",
-    ));
-
-    insns.push((
-        Inst::StoreP64 {
-            rt: xreg(8),
-            rt2: xreg(9),
-            mem: PairAMode::SignedOffset(xreg(10), SImm7Scaled::zero(I64)),
-            flags: MemFlags::trusted(),
-        },
-        "482500A9",
-        "stp x8, x9, [x10]",
-    ));
-    insns.push((
-        Inst::StoreP64 {
-            rt: xreg(8),
-            rt2: xreg(9),
-            mem: PairAMode::SignedOffset(xreg(10), SImm7Scaled::maybe_from_i64(504, I64).unwrap()),
-            flags: MemFlags::trusted(),
-        },
-        "48A51FA9",
-        "stp x8, x9, [x10, #504]",
-    ));
-    insns.push((
-        Inst::StoreP64 {
-            rt: xreg(8),
-            rt2: xreg(9),
-            mem: PairAMode::SignedOffset(xreg(10), SImm7Scaled::maybe_from_i64(-64, I64).unwrap()),
-            flags: MemFlags::trusted(),
-        },
-        "48253CA9",
-        "stp x8, x9, [x10, #-64]",
-    ));
-    insns.push((
-        Inst::StoreP64 {
-            rt: xreg(21),
-            rt2: xreg(28),
-            mem: PairAMode::SignedOffset(xreg(1), SImm7Scaled::maybe_from_i64(-512, I64).unwrap()),
-            flags: MemFlags::trusted(),
-        },
-        "357020A9",
-        "stp x21, x28, [x1, #-512]",
-    ));
-    insns.push((
-        Inst::StoreP64 {
-            rt: xreg(8),
-            rt2: xreg(9),
-            mem: PairAMode::PreIndexed(
-                writable_xreg(10),
-                SImm7Scaled::maybe_from_i64(-64, I64).unwrap(),
-            ),
-            flags: MemFlags::trusted(),
-        },
-        "4825BCA9",
-        "stp x8, x9, [x10, #-64]!",
-    ));
-    insns.push((
-        Inst::StoreP64 {
-            rt: xreg(15),
-            rt2: xreg(16),
-            mem: PairAMode::PostIndexed(
-                writable_xreg(20),
-                SImm7Scaled::maybe_from_i64(504, I64).unwrap(),
-            ),
-            flags: MemFlags::trusted(),
-        },
-        "8FC29FA8",
-        "stp x15, x16, [x20], #504",
-    ));
-
-    insns.push((
-        Inst::LoadP64 {
-            rt: writable_xreg(8),
-            rt2: writable_xreg(9),
-            mem: PairAMode::SignedOffset(xreg(10), SImm7Scaled::zero(I64)),
-            flags: MemFlags::trusted(),
-        },
-        "482540A9",
-        "ldp x8, x9, [x10]",
-    ));
-    insns.push((
-        Inst::LoadP64 {
-            rt: writable_xreg(8),
-            rt2: writable_xreg(9),
-            mem: PairAMode::SignedOffset(xreg(10), SImm7Scaled::maybe_from_i64(504, I64).unwrap()),
-            flags: MemFlags::trusted(),
-        },
-        "48A55FA9",
-        "ldp x8, x9, [x10, #504]",
-    ));
-    insns.push((
-        Inst::LoadP64 {
-            rt: writable_xreg(8),
-            rt2: writable_xreg(9),
-            mem: PairAMode::SignedOffset(xreg(10), SImm7Scaled::maybe_from_i64(-64, I64).unwrap()),
-            flags: MemFlags::trusted(),
-        },
-        "48257CA9",
-        "ldp x8, x9, [x10, #-64]",
-    ));
-    insns.push((
-        Inst::LoadP64 {
-            rt: writable_xreg(8),
-            rt2: writable_xreg(9),
-            mem: PairAMode::SignedOffset(xreg(10), SImm7Scaled::maybe_from_i64(-512, I64).unwrap()),
-            flags: MemFlags::trusted(),
-        },
-        "482560A9",
-        "ldp x8, x9, [x10, #-512]",
-    ));
-    insns.push((
-        Inst::LoadP64 {
-            rt: writable_xreg(8),
-            rt2: writable_xreg(9),
-            mem: PairAMode::PreIndexed(
-                writable_xreg(10),
-                SImm7Scaled::maybe_from_i64(-64, I64).unwrap(),
-            ),
-            flags: MemFlags::trusted(),
-        },
-        "4825FCA9",
-        "ldp x8, x9, [x10, #-64]!",
-    ));
-    insns.push((
-        Inst::LoadP64 {
-            rt: writable_xreg(8),
-            rt2: writable_xreg(25),
-            mem: PairAMode::PostIndexed(
-                writable_xreg(12),
-                SImm7Scaled::maybe_from_i64(504, I64).unwrap(),
-            ),
-            flags: MemFlags::trusted(),
-        },
-        "88E5DFA8",
-        "ldp x8, x25, [x12], #504",
-    ));
-
-    insns.push((
-        Inst::Mov64 {
-            rd: writable_xreg(8),
-            rm: xreg(9),
-        },
-        "E80309AA",
-        "mov x8, x9",
-    ));
-    insns.push((
-        Inst::Mov32 {
-            rd: writable_xreg(8),
-            rm: xreg(9),
-        },
-        "E803092A",
-        "mov w8, w9",
-    ));
-
-    insns.push((
-        Inst::MovZ {
-            rd: writable_xreg(8),
-            imm: MoveWideConst::maybe_from_u64(0x0000_0000_0000_ffff).unwrap(),
-            size: OperandSize::Size64,
-        },
-        "E8FF9FD2",
-        "movz x8, #65535",
-    ));
-    insns.push((
-        Inst::MovZ {
-            rd: writable_xreg(8),
-            imm: MoveWideConst::maybe_from_u64(0x0000_0000_ffff_0000).unwrap(),
-            size: OperandSize::Size64,
-        },
-        "E8FFBFD2",
-        "movz x8, #65535, LSL #16",
-    ));
-    insns.push((
-        Inst::MovZ {
-            rd: writable_xreg(8),
-            imm: MoveWideConst::maybe_from_u64(0x0000_ffff_0000_0000).unwrap(),
-            size: OperandSize::Size64,
-        },
-        "E8FFDFD2",
-        "movz x8, #65535, LSL #32",
-    ));
-    insns.push((
-        Inst::MovZ {
-            rd: writable_xreg(8),
-            imm: MoveWideConst::maybe_from_u64(0xffff_0000_0000_0000).unwrap(),
-            size: OperandSize::Size64,
-        },
-        "E8FFFFD2",
-        "movz x8, #65535, LSL #48",
-    ));
-    insns.push((
-        Inst::MovZ {
-            rd: writable_xreg(8),
-            imm: MoveWideConst::maybe_from_u64(0x0000_0000_ffff_0000).unwrap(),
-            size: OperandSize::Size32,
-        },
-        "E8FFBF52",
-        "movz w8, #65535, LSL #16",
-    ));
-
-    insns.push((
-        Inst::MovN {
-            rd: writable_xreg(8),
-            imm: MoveWideConst::maybe_from_u64(0x0000_0000_0000_ffff).unwrap(),
-            size: OperandSize::Size64,
-        },
-        "E8FF9F92",
-        "movn x8, #65535",
-    ));
-    insns.push((
-        Inst::MovN {
-            rd: writable_xreg(8),
-            imm: MoveWideConst::maybe_from_u64(0x0000_0000_ffff_0000).unwrap(),
-            size: OperandSize::Size64,
-        },
-        "E8FFBF92",
-        "movn x8, #65535, LSL #16",
-    ));
-    insns.push((
-        Inst::MovN {
-            rd: writable_xreg(8),
-            imm: MoveWideConst::maybe_from_u64(0x0000_ffff_0000_0000).unwrap(),
-            size: OperandSize::Size64,
-        },
-        "E8FFDF92",
-        "movn x8, #65535, LSL #32",
-    ));
-    insns.push((
-        Inst::MovN {
-            rd: writable_xreg(8),
-            imm: MoveWideConst::maybe_from_u64(0xffff_0000_0000_0000).unwrap(),
-            size: OperandSize::Size64,
-        },
-        "E8FFFF92",
-        "movn x8, #65535, LSL #48",
-    ));
-    insns.push((
-        Inst::MovN {
-            rd: writable_xreg(8),
-            imm: MoveWideConst::maybe_from_u64(0x0000_0000_0000_ffff).unwrap(),
-            size: OperandSize::Size32,
-        },
-        "E8FF9F12",
-        "movn w8, #65535",
-    ));
-
-    insns.push((
-        Inst::MovK {
-            rd: writable_xreg(12),
-            imm: MoveWideConst::maybe_from_u64(0x0000_0000_0000_0000).unwrap(),
-            size: OperandSize::Size64,
-        },
-        "0C0080F2",
-        "movk x12, #0",
-    ));
-    insns.push((
-        Inst::MovK {
-            rd: writable_xreg(19),
-            imm: MoveWideConst::maybe_with_shift(0x0000, 16).unwrap(),
-            size: OperandSize::Size64,
-        },
-        "1300A0F2",
-        "movk x19, #0, LSL #16",
-    ));
-    insns.push((
-        Inst::MovK {
-            rd: writable_xreg(3),
-            imm: MoveWideConst::maybe_from_u64(0x0000_0000_0000_ffff).unwrap(),
-            size: OperandSize::Size64,
-        },
-        "E3FF9FF2",
-        "movk x3, #65535",
-    ));
-    insns.push((
-        Inst::MovK {
-            rd: writable_xreg(8),
-            imm: MoveWideConst::maybe_from_u64(0x0000_0000_ffff_0000).unwrap(),
-            size: OperandSize::Size64,
-        },
-        "E8FFBFF2",
-        "movk x8, #65535, LSL #16",
-    ));
-    insns.push((
-        Inst::MovK {
-            rd: writable_xreg(8),
-            imm: MoveWideConst::maybe_from_u64(0x0000_ffff_0000_0000).unwrap(),
-            size: OperandSize::Size64,
-        },
-        "E8FFDFF2",
-        "movk x8, #65535, LSL #32",
-    ));
-    insns.push((
-        Inst::MovK {
-            rd: writable_xreg(8),
-            imm: MoveWideConst::maybe_from_u64(0xffff_0000_0000_0000).unwrap(),
-            size: OperandSize::Size64,
-        },
-        "E8FFFFF2",
-        "movk x8, #65535, LSL #48",
-    ));
-
-    insns.push((
-        Inst::CSel {
-            rd: writable_xreg(10),
-            rn: xreg(12),
-            rm: xreg(14),
-            cond: Cond::Hs,
-        },
-        "8A218E9A",
-        "csel x10, x12, x14, hs",
-    ));
-    insns.push((
-        Inst::CSet {
-            rd: writable_xreg(15),
-            cond: Cond::Ge,
-        },
-        "EFB79F9A",
-        "cset x15, ge",
-    ));
-    insns.push((
-        Inst::CSetm {
-            rd: writable_xreg(0),
-            cond: Cond::Eq,
-        },
-        "E0139FDA",
-        "csetm x0, eq",
-    ));
-    insns.push((
-        Inst::CSetm {
-            rd: writable_xreg(16),
-            cond: Cond::Vs,
-        },
-        "F0739FDA",
-        "csetm x16, vs",
-    ));
-    insns.push((
-        Inst::CCmpImm {
-            size: OperandSize::Size64,
-            rn: xreg(22),
-            imm: UImm5::maybe_from_u8(5).unwrap(),
-            nzcv: NZCV::new(false, false, true, true),
-            cond: Cond::Eq,
-        },
-        "C30A45FA",
-        "ccmp x22, #5, #nzCV, eq",
-    ));
-    insns.push((
-        Inst::CCmpImm {
-            size: OperandSize::Size32,
-            rn: xreg(3),
-            imm: UImm5::maybe_from_u8(30).unwrap(),
-            nzcv: NZCV::new(true, true, true, true),
-            cond: Cond::Gt,
-        },
-        "6FC85E7A",
-        "ccmp w3, #30, #NZCV, gt",
-    ));
-    insns.push((
-        Inst::MovToFpu {
-            rd: writable_vreg(31),
-            rn: xreg(0),
-            size: ScalarSize::Size64,
-        },
-        "1F00679E",
-        "fmov d31, x0",
-    ));
-    insns.push((
-        Inst::MovToFpu {
-            rd: writable_vreg(1),
-            rn: xreg(28),
-            size: ScalarSize::Size32,
-        },
-        "8103271E",
-        "fmov s1, w28",
-    ));
-    insns.push((
-        Inst::FpuMoveFPImm {
-            rd: writable_vreg(31),
-            imm: ASIMDFPModImm::maybe_from_u64(f64::to_bits(1.0), ScalarSize::Size64).unwrap(),
-            size: ScalarSize::Size64,
-        },
-        "1F106E1E",
-        "fmov d31, #1",
-    ));
-    insns.push((
-        Inst::FpuMoveFPImm {
-            rd: writable_vreg(1),
-            imm: ASIMDFPModImm::maybe_from_u64(f32::to_bits(31.0).into(), ScalarSize::Size32)
-                .unwrap(),
-            size: ScalarSize::Size32,
-        },
-        "01F0271E",
-        "fmov s1, #31",
-    ));
-    insns.push((
-        Inst::MovToVec {
-            rd: writable_vreg(0),
-            rn: xreg(0),
-            idx: 7,
-            size: VectorSize::Size8x8,
-        },
-        "001C0F4E",
-        "mov v0.b[7], w0",
-    ));
-    insns.push((
-        Inst::MovToVec {
-            rd: writable_vreg(20),
-            rn: xreg(21),
-            idx: 0,
-            size: VectorSize::Size64x2,
-        },
-        "B41E084E",
-        "mov v20.d[0], x21",
-    ));
-    insns.push((
-        Inst::MovFromVec {
-            rd: writable_xreg(3),
-            rn: vreg(27),
-            idx: 14,
-            size: VectorSize::Size8x16,
-        },
-        "633F1D0E",
-        "umov w3, v27.b[14]",
-    ));
-    insns.push((
-        Inst::MovFromVec {
-            rd: writable_xreg(24),
-            rn: vreg(5),
-            idx: 3,
-            size: VectorSize::Size16x8,
-        },
-        "B83C0E0E",
-        "umov w24, v5.h[3]",
-    ));
-    insns.push((
-        Inst::MovFromVec {
-            rd: writable_xreg(12),
-            rn: vreg(17),
-            idx: 1,
-            size: VectorSize::Size32x4,
-        },
-        "2C3E0C0E",
-        "mov w12, v17.s[1]",
-    ));
-    insns.push((
-        Inst::MovFromVec {
-            rd: writable_xreg(21),
-            rn: vreg(20),
-            idx: 0,
-            size: VectorSize::Size64x2,
-        },
-        "953E084E",
-        "mov x21, v20.d[0]",
-    ));
-    insns.push((
-        Inst::MovFromVecSigned {
-            rd: writable_xreg(0),
-            rn: vreg(0),
-            idx: 15,
-            size: VectorSize::Size8x16,
-            scalar_size: OperandSize::Size32,
-        },
-        "002C1F0E",
-        "smov w0, v0.b[15]",
-    ));
-    insns.push((
-        Inst::MovFromVecSigned {
-            rd: writable_xreg(12),
-            rn: vreg(13),
-            idx: 7,
-            size: VectorSize::Size8x8,
-            scalar_size: OperandSize::Size64,
-        },
-        "AC2D0F4E",
-        "smov x12, v13.b[7]",
-    ));
-    insns.push((
-        Inst::MovFromVecSigned {
-            rd: writable_xreg(23),
-            rn: vreg(31),
-            idx: 7,
-            size: VectorSize::Size16x8,
-            scalar_size: OperandSize::Size32,
-        },
-        "F72F1E0E",
-        "smov w23, v31.h[7]",
-    ));
-    insns.push((
-        Inst::MovFromVecSigned {
-            rd: writable_xreg(24),
-            rn: vreg(5),
-            idx: 1,
-            size: VectorSize::Size32x2,
-            scalar_size: OperandSize::Size64,
-        },
-        "B82C0C4E",
-        "smov x24, v5.s[1]",
-    ));
-    insns.push((
-        Inst::MovToNZCV { rn: xreg(13) },
-        "0D421BD5",
-        "msr nzcv, x13",
-    ));
-    insns.push((
-        Inst::MovFromNZCV {
-            rd: writable_xreg(27),
-        },
-        "1B423BD5",
-        "mrs x27, nzcv",
-    ));
-    insns.push((
-        Inst::VecDup {
-            rd: writable_vreg(25),
-            rn: xreg(7),
-            size: VectorSize::Size8x16,
-        },
-        "F90C014E",
-        "dup v25.16b, w7",
-    ));
-    insns.push((
-        Inst::VecDup {
-            rd: writable_vreg(2),
-            rn: xreg(23),
-            size: VectorSize::Size16x8,
-        },
-        "E20E024E",
-        "dup v2.8h, w23",
-    ));
-    insns.push((
-        Inst::VecDup {
-            rd: writable_vreg(0),
-            rn: xreg(28),
-            size: VectorSize::Size32x4,
-        },
-        "800F044E",
-        "dup v0.4s, w28",
-    ));
-    insns.push((
-        Inst::VecDup {
-            rd: writable_vreg(31),
-            rn: xreg(5),
-            size: VectorSize::Size64x2,
-        },
-        "BF0C084E",
-        "dup v31.2d, x5",
-    ));
-    insns.push((
-        Inst::VecDupFromFpu {
-            rd: writable_vreg(14),
-            rn: vreg(19),
-            size: VectorSize::Size32x4,
-        },
-        "6E06044E",
-        "dup v14.4s, v19.s[0]",
-    ));
-    insns.push((
-        Inst::VecDupFromFpu {
-            rd: writable_vreg(18),
-            rn: vreg(10),
-            size: VectorSize::Size64x2,
-        },
-        "5205084E",
-        "dup v18.2d, v10.d[0]",
-    ));
-    insns.push((
-        Inst::VecDupFPImm {
-            rd: writable_vreg(31),
-            imm: ASIMDFPModImm::maybe_from_u64(1_f32.to_bits() as u64, ScalarSize::Size32).unwrap(),
-            size: VectorSize::Size32x2,
-        },
-        "1FF6030F",
-        "fmov v31.2s, #1",
-    ));
-    insns.push((
-        Inst::VecDupFPImm {
-            rd: writable_vreg(0),
-            imm: ASIMDFPModImm::maybe_from_u64(2_f64.to_bits(), ScalarSize::Size64).unwrap(),
-            size: VectorSize::Size64x2,
-        },
-        "00F4006F",
-        "fmov v0.2d, #2",
-    ));
-    insns.push((
-        Inst::VecDupImm {
-            rd: writable_vreg(31),
-            imm: ASIMDMovModImm::maybe_from_u64(255, ScalarSize::Size8).unwrap(),
-            invert: false,
-            size: VectorSize::Size8x16,
-        },
-        "FFE7074F",
-        "movi v31.16b, #255",
-    ));
-    insns.push((
-        Inst::VecDupImm {
-            rd: writable_vreg(30),
-            imm: ASIMDMovModImm::maybe_from_u64(0, ScalarSize::Size16).unwrap(),
-            invert: false,
-            size: VectorSize::Size16x8,
-        },
-        "1E84004F",
-        "movi v30.8h, #0",
-    ));
-    insns.push((
-        Inst::VecDupImm {
-            rd: writable_vreg(0),
-            imm: ASIMDMovModImm::zero(ScalarSize::Size16),
-            invert: true,
-            size: VectorSize::Size16x4,
-        },
-        "0084002F",
-        "mvni v0.4h, #0",
-    ));
-    insns.push((
-        Inst::VecDupImm {
-            rd: writable_vreg(0),
-            imm: ASIMDMovModImm::maybe_from_u64(256, ScalarSize::Size16).unwrap(),
-            invert: false,
-            size: VectorSize::Size16x8,
-        },
-        "20A4004F",
-        "movi v0.8h, #1, LSL #8",
-    ));
-    insns.push((
-        Inst::VecDupImm {
-            rd: writable_vreg(8),
-            imm: ASIMDMovModImm::maybe_from_u64(2228223, ScalarSize::Size32).unwrap(),
-            invert: false,
-            size: VectorSize::Size32x4,
-        },
-        "28D4014F",
-        "movi v8.4s, #33, MSL #16",
-    ));
-    insns.push((
-        Inst::VecDupImm {
-            rd: writable_vreg(16),
-            imm: ASIMDMovModImm::maybe_from_u64(35071, ScalarSize::Size32).unwrap(),
-            invert: true,
-            size: VectorSize::Size32x2,
-        },
-        "10C5042F",
-        "mvni v16.2s, #136, MSL #8",
-    ));
-    insns.push((
-        Inst::VecDupImm {
-            rd: writable_vreg(1),
-            imm: ASIMDMovModImm::maybe_from_u64(0, ScalarSize::Size32).unwrap(),
-            invert: false,
-            size: VectorSize::Size32x2,
-        },
-        "0104000F",
-        "movi v1.2s, #0",
-    ));
-    insns.push((
-        Inst::VecDupImm {
-            rd: writable_vreg(24),
-            imm: ASIMDMovModImm::maybe_from_u64(1107296256, ScalarSize::Size32).unwrap(),
-            invert: false,
-            size: VectorSize::Size32x4,
-        },
-        "5864024F",
-        "movi v24.4s, #66, LSL #24",
-    ));
-    insns.push((
-        Inst::VecDupImm {
-            rd: writable_vreg(8),
-            imm: ASIMDMovModImm::zero(ScalarSize::Size64),
-            invert: false,
-            size: VectorSize::Size64x2,
-        },
-        "08E4006F",
-        "movi v8.2d, #0",
-    ));
-    insns.push((
-        Inst::VecDupImm {
-            rd: writable_vreg(7),
-            imm: ASIMDMovModImm::maybe_from_u64(18374687574904995840, ScalarSize::Size64).unwrap(),
-            invert: false,
-            size: VectorSize::Size64x2,
-        },
-        "87E6046F",
-        "movi v7.2d, #18374687574904995840",
-    ));
-    insns.push((
-        Inst::VecExtend {
-            t: VecExtendOp::Sxtl8,
-            rd: writable_vreg(4),
-            rn: vreg(27),
-            high_half: false,
-        },
-        "64A7080F",
-        "sxtl v4.8h, v27.8b",
-    ));
-    insns.push((
-        Inst::VecExtend {
-            t: VecExtendOp::Sxtl16,
-            rd: writable_vreg(17),
-            rn: vreg(19),
-            high_half: true,
-        },
-        "71A6104F",
-        "sxtl2 v17.4s, v19.8h",
-    ));
-    insns.push((
-        Inst::VecExtend {
-            t: VecExtendOp::Sxtl32,
-            rd: writable_vreg(30),
-            rn: vreg(6),
-            high_half: false,
-        },
-        "DEA4200F",
-        "sxtl v30.2d, v6.2s",
-    ));
-    insns.push((
-        Inst::VecExtend {
-            t: VecExtendOp::Uxtl8,
-            rd: writable_vreg(3),
-            rn: vreg(29),
-            high_half: true,
-        },
-        "A3A7086F",
-        "uxtl2 v3.8h, v29.16b",
-    ));
-    insns.push((
-        Inst::VecExtend {
-            t: VecExtendOp::Uxtl16,
-            rd: writable_vreg(15),
-            rn: vreg(12),
-            high_half: false,
-        },
-        "8FA5102F",
-        "uxtl v15.4s, v12.4h",
-    ));
-    insns.push((
-        Inst::VecExtend {
-            t: VecExtendOp::Uxtl32,
-            rd: writable_vreg(28),
-            rn: vreg(2),
-            high_half: true,
-        },
-        "5CA4206F",
-        "uxtl2 v28.2d, v2.4s",
-    ));
-
-    insns.push((
-        Inst::VecMovElement {
-            rd: writable_vreg(0),
-            rn: vreg(31),
-            dest_idx: 7,
-            src_idx: 7,
-            size: VectorSize::Size16x8,
-        },
-        "E0771E6E",
-        "mov v0.h[7], v31.h[7]",
-    ));
-
-    insns.push((
-        Inst::VecMovElement {
-            rd: writable_vreg(31),
-            rn: vreg(16),
-            dest_idx: 1,
-            src_idx: 0,
-            size: VectorSize::Size32x2,
-        },
-        "1F060C6E",
-        "mov v31.s[1], v16.s[0]",
-    ));
-
-    insns.push((
-        Inst::VecRRLong {
-            op: VecRRLongOp::Fcvtl16,
-            rd: writable_vreg(0),
-            rn: vreg(30),
-            high_half: false,
-        },
-        "C07B210E",
-        "fcvtl v0.4s, v30.4h",
-    ));
-
-    insns.push((
-        Inst::VecRRLong {
-            op: VecRRLongOp::Fcvtl32,
-            rd: writable_vreg(16),
-            rn: vreg(1),
-            high_half: true,
-        },
-        "3078614E",
-        "fcvtl2 v16.2d, v1.4s",
-    ));
-
-    insns.push((
-        Inst::VecRRLong {
-            op: VecRRLongOp::Shll8,
-            rd: writable_vreg(12),
-            rn: vreg(5),
-            high_half: false,
-        },
-        "AC38212E",
-        "shll v12.8h, v5.8b, #8",
-    ));
-
-    insns.push((
-        Inst::VecRRLong {
-            op: VecRRLongOp::Shll16,
-            rd: writable_vreg(9),
-            rn: vreg(1),
-            high_half: true,
-        },
-        "2938616E",
-        "shll2 v9.4s, v1.8h, #16",
-    ));
-
-    insns.push((
-        Inst::VecRRLong {
-            op: VecRRLongOp::Shll32,
-            rd: writable_vreg(1),
-            rn: vreg(10),
-            high_half: false,
-        },
-        "4139A12E",
-        "shll v1.2d, v10.2s, #32",
-    ));
-
-    insns.push((
-        Inst::VecRRNarrow {
-            op: VecRRNarrowOp::Xtn16,
-            rd: writable_vreg(25),
-            rn: vreg(17),
-            high_half: false,
-        },
-        "392A210E",
-        "xtn v25.8b, v17.8h",
-    ));
-
-    insns.push((
-        Inst::VecRRNarrow {
-            op: VecRRNarrowOp::Xtn32,
-            rd: writable_vreg(3),
-            rn: vreg(10),
-            high_half: true,
-        },
-        "4329614E",
-        "xtn2 v3.8h, v10.4s",
-    ));
-
-    insns.push((
-        Inst::VecRRNarrow {
-            op: VecRRNarrowOp::Xtn64,
-            rd: writable_vreg(22),
-            rn: vreg(8),
-            high_half: false,
-        },
-        "1629A10E",
-        "xtn v22.2s, v8.2d",
-    ));
-
-    insns.push((
-        Inst::VecRRNarrow {
-            op: VecRRNarrowOp::Sqxtn16,
-            rd: writable_vreg(7),
-            rn: vreg(22),
-            high_half: true,
-        },
-        "C74A214E",
-        "sqxtn2 v7.16b, v22.8h",
-    ));
-
-    insns.push((
-        Inst::VecRRNarrow {
-            op: VecRRNarrowOp::Sqxtn32,
-            rd: writable_vreg(31),
-            rn: vreg(0),
-            high_half: true,
-        },
-        "1F48614E",
-        "sqxtn2 v31.8h, v0.4s",
-    ));
-
-    insns.push((
-        Inst::VecRRNarrow {
-            op: VecRRNarrowOp::Sqxtn64,
-            rd: writable_vreg(14),
-            rn: vreg(20),
-            high_half: false,
-        },
-        "8E4AA10E",
-        "sqxtn v14.2s, v20.2d",
-    ));
-
-    insns.push((
-        Inst::VecRRNarrow {
-            op: VecRRNarrowOp::Sqxtun16,
-            rd: writable_vreg(16),
-            rn: vreg(23),
-            high_half: false,
-        },
-        "F02A212E",
-        "sqxtun v16.8b, v23.8h",
-    ));
-
-    insns.push((
-        Inst::VecRRNarrow {
-            op: VecRRNarrowOp::Sqxtun32,
-            rd: writable_vreg(28),
-            rn: vreg(9),
-            high_half: true,
-        },
-        "3C29616E",
-        "sqxtun2 v28.8h, v9.4s",
-    ));
-
-    insns.push((
-        Inst::VecRRNarrow {
-            op: VecRRNarrowOp::Sqxtun64,
-            rd: writable_vreg(15),
-            rn: vreg(15),
-            high_half: false,
-        },
-        "EF29A12E",
-        "sqxtun v15.2s, v15.2d",
-    ));
-
-    insns.push((
-        Inst::VecRRNarrow {
-            op: VecRRNarrowOp::Uqxtn16,
-            rd: writable_vreg(21),
-            rn: vreg(4),
-            high_half: true,
-        },
-        "9548216E",
-        "uqxtn2 v21.16b, v4.8h",
-    ));
-
-    insns.push((
-        Inst::VecRRNarrow {
-            op: VecRRNarrowOp::Uqxtn32,
-            rd: writable_vreg(31),
-            rn: vreg(31),
-            high_half: false,
-        },
-        "FF4B612E",
-        "uqxtn v31.4h, v31.4s",
-    ));
-
-    insns.push((
-        Inst::VecRRNarrow {
-            op: VecRRNarrowOp::Uqxtn64,
-            rd: writable_vreg(11),
-            rn: vreg(12),
-            high_half: true,
-        },
-        "8B49A16E",
-        "uqxtn2 v11.4s, v12.2d",
-    ));
-
-    insns.push((
-        Inst::VecRRNarrow {
-            op: VecRRNarrowOp::Fcvtn32,
-            rd: writable_vreg(0),
-            rn: vreg(0),
-            high_half: false,
-        },
-        "0068210E",
-        "fcvtn v0.4h, v0.4s",
-    ));
-
-    insns.push((
-        Inst::VecRRNarrow {
-            op: VecRRNarrowOp::Fcvtn64,
-            rd: writable_vreg(31),
-            rn: vreg(30),
-            high_half: true,
-        },
-        "DF6B614E",
-        "fcvtn2 v31.4s, v30.2d",
-    ));
-
-    insns.push((
-        Inst::VecRRPair {
-            op: VecPairOp::Addp,
-            rd: writable_vreg(0),
-            rn: vreg(30),
-        },
-        "C0BBF15E",
-        "addp d0, v30.2d",
-    ));
-
-    insns.push((
-        Inst::VecRRPairLong {
-            op: VecRRPairLongOp::Uaddlp8,
-            rd: writable_vreg(0),
-            rn: vreg(1),
-        },
-        "2028206E",
-        "uaddlp v0.8h, v1.16b",
-    ));
-
-    insns.push((
-        Inst::VecRRPairLong {
-            op: VecRRPairLongOp::Saddlp8,
-            rd: writable_vreg(3),
-            rn: vreg(11),
-        },
-        "6329204E",
-        "saddlp v3.8h, v11.16b",
-    ));
-
-    insns.push((
-        Inst::VecRRPairLong {
-            op: VecRRPairLongOp::Uaddlp16,
-            rd: writable_vreg(14),
-            rn: vreg(23),
-        },
-        "EE2A606E",
-        "uaddlp v14.4s, v23.8h",
-    ));
-
-    insns.push((
-        Inst::VecRRPairLong {
-            op: VecRRPairLongOp::Saddlp16,
-            rd: writable_vreg(29),
-            rn: vreg(0),
-        },
-        "1D28604E",
-        "saddlp v29.4s, v0.8h",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Sqadd,
-            rd: writable_vreg(1),
-            rn: vreg(2),
-            rm: vreg(8),
-            size: VectorSize::Size8x16,
-        },
-        "410C284E",
-        "sqadd v1.16b, v2.16b, v8.16b",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Sqadd,
-            rd: writable_vreg(1),
-            rn: vreg(12),
-            rm: vreg(28),
-            size: VectorSize::Size16x8,
-        },
-        "810D7C4E",
-        "sqadd v1.8h, v12.8h, v28.8h",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Sqadd,
-            rd: writable_vreg(12),
-            rn: vreg(2),
-            rm: vreg(6),
-            size: VectorSize::Size32x4,
-        },
-        "4C0CA64E",
-        "sqadd v12.4s, v2.4s, v6.4s",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Sqadd,
-            rd: writable_vreg(20),
-            rn: vreg(7),
-            rm: vreg(13),
-            size: VectorSize::Size64x2,
-        },
-        "F40CED4E",
-        "sqadd v20.2d, v7.2d, v13.2d",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Sqsub,
-            rd: writable_vreg(1),
-            rn: vreg(2),
-            rm: vreg(8),
-            size: VectorSize::Size8x16,
-        },
-        "412C284E",
-        "sqsub v1.16b, v2.16b, v8.16b",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Sqsub,
-            rd: writable_vreg(1),
-            rn: vreg(12),
-            rm: vreg(28),
-            size: VectorSize::Size16x8,
-        },
-        "812D7C4E",
-        "sqsub v1.8h, v12.8h, v28.8h",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Sqsub,
-            rd: writable_vreg(12),
-            rn: vreg(2),
-            rm: vreg(6),
-            size: VectorSize::Size32x4,
-        },
-        "4C2CA64E",
-        "sqsub v12.4s, v2.4s, v6.4s",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Sqsub,
-            rd: writable_vreg(20),
-            rn: vreg(7),
-            rm: vreg(13),
-            size: VectorSize::Size64x2,
-        },
-        "F42CED4E",
-        "sqsub v20.2d, v7.2d, v13.2d",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Uqadd,
-            rd: writable_vreg(1),
-            rn: vreg(2),
-            rm: vreg(8),
-            size: VectorSize::Size8x16,
-        },
-        "410C286E",
-        "uqadd v1.16b, v2.16b, v8.16b",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Uqadd,
-            rd: writable_vreg(1),
-            rn: vreg(12),
-            rm: vreg(28),
-            size: VectorSize::Size16x8,
-        },
-        "810D7C6E",
-        "uqadd v1.8h, v12.8h, v28.8h",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Uqadd,
-            rd: writable_vreg(12),
-            rn: vreg(2),
-            rm: vreg(6),
-            size: VectorSize::Size32x4,
-        },
-        "4C0CA66E",
-        "uqadd v12.4s, v2.4s, v6.4s",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Uqadd,
-            rd: writable_vreg(20),
-            rn: vreg(7),
-            rm: vreg(13),
-            size: VectorSize::Size64x2,
-        },
-        "F40CED6E",
-        "uqadd v20.2d, v7.2d, v13.2d",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Uqsub,
-            rd: writable_vreg(1),
-            rn: vreg(2),
-            rm: vreg(8),
-            size: VectorSize::Size8x16,
-        },
-        "412C286E",
-        "uqsub v1.16b, v2.16b, v8.16b",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Uqsub,
-            rd: writable_vreg(1),
-            rn: vreg(12),
-            rm: vreg(28),
-            size: VectorSize::Size16x8,
-        },
-        "812D7C6E",
-        "uqsub v1.8h, v12.8h, v28.8h",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Uqsub,
-            rd: writable_vreg(12),
-            rn: vreg(2),
-            rm: vreg(6),
-            size: VectorSize::Size32x4,
-        },
-        "4C2CA66E",
-        "uqsub v12.4s, v2.4s, v6.4s",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Uqsub,
-            rd: writable_vreg(20),
-            rn: vreg(7),
-            rm: vreg(13),
-            size: VectorSize::Size64x2,
-        },
-        "F42CED6E",
-        "uqsub v20.2d, v7.2d, v13.2d",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Cmeq,
-            rd: writable_vreg(3),
-            rn: vreg(23),
-            rm: vreg(24),
-            size: VectorSize::Size8x16,
-        },
-        "E38E386E",
-        "cmeq v3.16b, v23.16b, v24.16b",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Cmgt,
-            rd: writable_vreg(3),
-            rn: vreg(23),
-            rm: vreg(24),
-            size: VectorSize::Size8x16,
-        },
-        "E336384E",
-        "cmgt v3.16b, v23.16b, v24.16b",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Cmge,
-            rd: writable_vreg(23),
-            rn: vreg(9),
-            rm: vreg(12),
-            size: VectorSize::Size8x16,
-        },
-        "373D2C4E",
-        "cmge v23.16b, v9.16b, v12.16b",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Cmhi,
-            rd: writable_vreg(5),
-            rn: vreg(1),
-            rm: vreg(1),
-            size: VectorSize::Size8x16,
-        },
-        "2534216E",
-        "cmhi v5.16b, v1.16b, v1.16b",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Cmhs,
-            rd: writable_vreg(8),
-            rn: vreg(2),
-            rm: vreg(15),
-            size: VectorSize::Size8x16,
-        },
-        "483C2F6E",
-        "cmhs v8.16b, v2.16b, v15.16b",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Cmeq,
-            rd: writable_vreg(3),
-            rn: vreg(23),
-            rm: vreg(24),
-            size: VectorSize::Size16x8,
-        },
-        "E38E786E",
-        "cmeq v3.8h, v23.8h, v24.8h",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Cmgt,
-            rd: writable_vreg(3),
-            rn: vreg(23),
-            rm: vreg(24),
-            size: VectorSize::Size16x8,
-        },
-        "E336784E",
-        "cmgt v3.8h, v23.8h, v24.8h",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Cmge,
-            rd: writable_vreg(23),
-            rn: vreg(9),
-            rm: vreg(12),
-            size: VectorSize::Size16x8,
-        },
-        "373D6C4E",
-        "cmge v23.8h, v9.8h, v12.8h",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Cmhi,
-            rd: writable_vreg(5),
-            rn: vreg(1),
-            rm: vreg(1),
-            size: VectorSize::Size16x8,
-        },
-        "2534616E",
-        "cmhi v5.8h, v1.8h, v1.8h",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Cmhs,
-            rd: writable_vreg(8),
-            rn: vreg(2),
-            rm: vreg(15),
-            size: VectorSize::Size16x8,
-        },
-        "483C6F6E",
-        "cmhs v8.8h, v2.8h, v15.8h",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Cmeq,
-            rd: writable_vreg(3),
-            rn: vreg(23),
-            rm: vreg(24),
-            size: VectorSize::Size32x4,
-        },
-        "E38EB86E",
-        "cmeq v3.4s, v23.4s, v24.4s",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Cmgt,
-            rd: writable_vreg(3),
-            rn: vreg(23),
-            rm: vreg(24),
-            size: VectorSize::Size32x4,
-        },
-        "E336B84E",
-        "cmgt v3.4s, v23.4s, v24.4s",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Cmge,
-            rd: writable_vreg(23),
-            rn: vreg(9),
-            rm: vreg(12),
-            size: VectorSize::Size32x4,
-        },
-        "373DAC4E",
-        "cmge v23.4s, v9.4s, v12.4s",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Cmhi,
-            rd: writable_vreg(5),
-            rn: vreg(1),
-            rm: vreg(1),
-            size: VectorSize::Size32x4,
-        },
-        "2534A16E",
-        "cmhi v5.4s, v1.4s, v1.4s",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Cmhs,
-            rd: writable_vreg(8),
-            rn: vreg(2),
-            rm: vreg(15),
-            size: VectorSize::Size32x4,
-        },
-        "483CAF6E",
-        "cmhs v8.4s, v2.4s, v15.4s",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Fcmeq,
-            rd: writable_vreg(28),
-            rn: vreg(12),
-            rm: vreg(4),
-            size: VectorSize::Size32x2,
-        },
-        "9CE5240E",
-        "fcmeq v28.2s, v12.2s, v4.2s",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Fcmgt,
-            rd: writable_vreg(3),
-            rn: vreg(16),
-            rm: vreg(31),
-            size: VectorSize::Size64x2,
-        },
-        "03E6FF6E",
-        "fcmgt v3.2d, v16.2d, v31.2d",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Fcmge,
-            rd: writable_vreg(18),
-            rn: vreg(23),
-            rm: vreg(0),
-            size: VectorSize::Size64x2,
-        },
-        "F2E6606E",
-        "fcmge v18.2d, v23.2d, v0.2d",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::And,
-            rd: writable_vreg(20),
-            rn: vreg(19),
-            rm: vreg(18),
-            size: VectorSize::Size32x4,
-        },
-        "741E324E",
-        "and v20.16b, v19.16b, v18.16b",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Bic,
-            rd: writable_vreg(8),
-            rn: vreg(11),
-            rm: vreg(1),
-            size: VectorSize::Size8x16,
-        },
-        "681D614E",
-        "bic v8.16b, v11.16b, v1.16b",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Orr,
-            rd: writable_vreg(15),
-            rn: vreg(2),
-            rm: vreg(12),
-            size: VectorSize::Size16x8,
-        },
-        "4F1CAC4E",
-        "orr v15.16b, v2.16b, v12.16b",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Eor,
-            rd: writable_vreg(18),
-            rn: vreg(3),
-            rm: vreg(22),
-            size: VectorSize::Size8x16,
-        },
-        "721C366E",
-        "eor v18.16b, v3.16b, v22.16b",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Bsl,
-            rd: writable_vreg(8),
-            rn: vreg(9),
-            rm: vreg(1),
-            size: VectorSize::Size8x16,
-        },
-        "281D616E",
-        "bsl v8.16b, v9.16b, v1.16b",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Umaxp,
-            rd: writable_vreg(8),
-            rn: vreg(12),
-            rm: vreg(1),
-            size: VectorSize::Size8x16,
-        },
-        "88A5216E",
-        "umaxp v8.16b, v12.16b, v1.16b",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Umaxp,
-            rd: writable_vreg(1),
-            rn: vreg(6),
-            rm: vreg(1),
-            size: VectorSize::Size16x8,
-        },
-        "C1A4616E",
-        "umaxp v1.8h, v6.8h, v1.8h",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Umaxp,
-            rd: writable_vreg(1),
-            rn: vreg(20),
-            rm: vreg(16),
-            size: VectorSize::Size32x4,
-        },
-        "81A6B06E",
-        "umaxp v1.4s, v20.4s, v16.4s",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Add,
-            rd: writable_vreg(5),
-            rn: vreg(1),
-            rm: vreg(1),
-            size: VectorSize::Size8x16,
-        },
-        "2584214E",
-        "add v5.16b, v1.16b, v1.16b",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Add,
-            rd: writable_vreg(7),
-            rn: vreg(13),
-            rm: vreg(2),
-            size: VectorSize::Size16x8,
-        },
-        "A785624E",
-        "add v7.8h, v13.8h, v2.8h",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Add,
-            rd: writable_vreg(18),
-            rn: vreg(9),
-            rm: vreg(6),
-            size: VectorSize::Size32x4,
-        },
-        "3285A64E",
-        "add v18.4s, v9.4s, v6.4s",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Add,
-            rd: writable_vreg(1),
-            rn: vreg(3),
-            rm: vreg(2),
-            size: VectorSize::Size64x2,
-        },
-        "6184E24E",
-        "add v1.2d, v3.2d, v2.2d",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Sub,
-            rd: writable_vreg(5),
-            rn: vreg(1),
-            rm: vreg(1),
-            size: VectorSize::Size8x16,
-        },
-        "2584216E",
-        "sub v5.16b, v1.16b, v1.16b",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Sub,
-            rd: writable_vreg(7),
-            rn: vreg(13),
-            rm: vreg(2),
-            size: VectorSize::Size16x8,
-        },
-        "A785626E",
-        "sub v7.8h, v13.8h, v2.8h",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Sub,
-            rd: writable_vreg(18),
-            rn: vreg(9),
-            rm: vreg(6),
-            size: VectorSize::Size32x4,
-        },
-        "3285A66E",
-        "sub v18.4s, v9.4s, v6.4s",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Sub,
-            rd: writable_vreg(18),
-            rn: vreg(0),
-            rm: vreg(8),
-            size: VectorSize::Size64x2,
-        },
-        "1284E86E",
-        "sub v18.2d, v0.2d, v8.2d",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Mul,
-            rd: writable_vreg(25),
-            rn: vreg(9),
-            rm: vreg(8),
-            size: VectorSize::Size8x16,
-        },
-        "399D284E",
-        "mul v25.16b, v9.16b, v8.16b",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Mul,
-            rd: writable_vreg(30),
-            rn: vreg(30),
-            rm: vreg(12),
-            size: VectorSize::Size16x8,
-        },
-        "DE9F6C4E",
-        "mul v30.8h, v30.8h, v12.8h",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Mul,
-            rd: writable_vreg(18),
-            rn: vreg(18),
-            rm: vreg(18),
-            size: VectorSize::Size32x4,
-        },
-        "529EB24E",
-        "mul v18.4s, v18.4s, v18.4s",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Ushl,
-            rd: writable_vreg(18),
-            rn: vreg(18),
-            rm: vreg(18),
-            size: VectorSize::Size8x16,
-        },
-        "5246326E",
-        "ushl v18.16b, v18.16b, v18.16b",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Ushl,
-            rd: writable_vreg(18),
-            rn: vreg(18),
-            rm: vreg(18),
-            size: VectorSize::Size16x8,
-        },
-        "5246726E",
-        "ushl v18.8h, v18.8h, v18.8h",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Ushl,
-            rd: writable_vreg(18),
-            rn: vreg(1),
-            rm: vreg(21),
-            size: VectorSize::Size32x4,
-        },
-        "3244B56E",
-        "ushl v18.4s, v1.4s, v21.4s",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Ushl,
-            rd: writable_vreg(5),
-            rn: vreg(7),
-            rm: vreg(19),
-            size: VectorSize::Size64x2,
-        },
-        "E544F36E",
-        "ushl v5.2d, v7.2d, v19.2d",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Sshl,
-            rd: writable_vreg(18),
-            rn: vreg(18),
-            rm: vreg(18),
-            size: VectorSize::Size8x16,
-        },
-        "5246324E",
-        "sshl v18.16b, v18.16b, v18.16b",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Sshl,
-            rd: writable_vreg(30),
-            rn: vreg(1),
-            rm: vreg(29),
-            size: VectorSize::Size16x8,
-        },
-        "3E447D4E",
-        "sshl v30.8h, v1.8h, v29.8h",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Sshl,
-            rd: writable_vreg(8),
-            rn: vreg(22),
-            rm: vreg(21),
-            size: VectorSize::Size32x4,
-        },
-        "C846B54E",
-        "sshl v8.4s, v22.4s, v21.4s",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Sshl,
-            rd: writable_vreg(8),
-            rn: vreg(22),
-            rm: vreg(2),
-            size: VectorSize::Size64x2,
-        },
-        "C846E24E",
-        "sshl v8.2d, v22.2d, v2.2d",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Umin,
-            rd: writable_vreg(1),
-            rn: vreg(12),
-            rm: vreg(3),
-            size: VectorSize::Size8x16,
-        },
-        "816D236E",
-        "umin v1.16b, v12.16b, v3.16b",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Umin,
-            rd: writable_vreg(30),
-            rn: vreg(20),
-            rm: vreg(10),
-            size: VectorSize::Size16x8,
-        },
-        "9E6E6A6E",
-        "umin v30.8h, v20.8h, v10.8h",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Umin,
-            rd: writable_vreg(8),
-            rn: vreg(22),
-            rm: vreg(21),
-            size: VectorSize::Size32x4,
-        },
-        "C86EB56E",
-        "umin v8.4s, v22.4s, v21.4s",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Smin,
-            rd: writable_vreg(1),
-            rn: vreg(12),
-            rm: vreg(3),
-            size: VectorSize::Size8x16,
-        },
-        "816D234E",
-        "smin v1.16b, v12.16b, v3.16b",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Smin,
-            rd: writable_vreg(30),
-            rn: vreg(20),
-            rm: vreg(10),
-            size: VectorSize::Size16x8,
-        },
-        "9E6E6A4E",
-        "smin v30.8h, v20.8h, v10.8h",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Smin,
-            rd: writable_vreg(8),
-            rn: vreg(22),
-            rm: vreg(21),
-            size: VectorSize::Size32x4,
-        },
-        "C86EB54E",
-        "smin v8.4s, v22.4s, v21.4s",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Umax,
-            rd: writable_vreg(6),
-            rn: vreg(9),
-            rm: vreg(8),
-            size: VectorSize::Size8x8,
-        },
-        "2665282E",
-        "umax v6.8b, v9.8b, v8.8b",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Umax,
-            rd: writable_vreg(11),
-            rn: vreg(13),
-            rm: vreg(2),
-            size: VectorSize::Size16x8,
-        },
-        "AB65626E",
-        "umax v11.8h, v13.8h, v2.8h",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Umax,
-            rd: writable_vreg(8),
-            rn: vreg(12),
-            rm: vreg(14),
-            size: VectorSize::Size32x4,
-        },
-        "8865AE6E",
-        "umax v8.4s, v12.4s, v14.4s",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Smax,
-            rd: writable_vreg(6),
-            rn: vreg(9),
-            rm: vreg(8),
-            size: VectorSize::Size8x16,
-        },
-        "2665284E",
-        "smax v6.16b, v9.16b, v8.16b",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Smax,
-            rd: writable_vreg(11),
-            rn: vreg(13),
-            rm: vreg(2),
-            size: VectorSize::Size16x8,
-        },
-        "AB65624E",
-        "smax v11.8h, v13.8h, v2.8h",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Smax,
-            rd: writable_vreg(8),
-            rn: vreg(12),
-            rm: vreg(14),
-            size: VectorSize::Size32x4,
-        },
-        "8865AE4E",
-        "smax v8.4s, v12.4s, v14.4s",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Urhadd,
-            rd: writable_vreg(8),
-            rn: vreg(1),
-            rm: vreg(3),
-            size: VectorSize::Size8x16,
-        },
-        "2814236E",
-        "urhadd v8.16b, v1.16b, v3.16b",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Urhadd,
-            rd: writable_vreg(2),
-            rn: vreg(13),
-            rm: vreg(6),
-            size: VectorSize::Size16x8,
-        },
-        "A215666E",
-        "urhadd v2.8h, v13.8h, v6.8h",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Urhadd,
-            rd: writable_vreg(8),
-            rn: vreg(12),
-            rm: vreg(14),
-            size: VectorSize::Size32x4,
-        },
-        "8815AE6E",
-        "urhadd v8.4s, v12.4s, v14.4s",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Fadd,
-            rd: writable_vreg(31),
-            rn: vreg(0),
-            rm: vreg(16),
-            size: VectorSize::Size32x4,
-        },
-        "1FD4304E",
-        "fadd v31.4s, v0.4s, v16.4s",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Fsub,
-            rd: writable_vreg(8),
-            rn: vreg(7),
-            rm: vreg(15),
-            size: VectorSize::Size64x2,
-        },
-        "E8D4EF4E",
-        "fsub v8.2d, v7.2d, v15.2d",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Fdiv,
-            rd: writable_vreg(1),
-            rn: vreg(3),
-            rm: vreg(4),
-            size: VectorSize::Size32x4,
-        },
-        "61FC246E",
-        "fdiv v1.4s, v3.4s, v4.4s",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Fmax,
-            rd: writable_vreg(31),
-            rn: vreg(16),
-            rm: vreg(0),
-            size: VectorSize::Size64x2,
-        },
-        "1FF6604E",
-        "fmax v31.2d, v16.2d, v0.2d",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Fmin,
-            rd: writable_vreg(5),
-            rn: vreg(19),
-            rm: vreg(26),
-            size: VectorSize::Size32x4,
-        },
-        "65F6BA4E",
-        "fmin v5.4s, v19.4s, v26.4s",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Fmul,
-            rd: writable_vreg(2),
-            rn: vreg(0),
-            rm: vreg(5),
-            size: VectorSize::Size64x2,
-        },
-        "02DC656E",
-        "fmul v2.2d, v0.2d, v5.2d",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Addp,
-            rd: writable_vreg(16),
-            rn: vreg(12),
-            rm: vreg(1),
-            size: VectorSize::Size8x16,
-        },
-        "90BD214E",
-        "addp v16.16b, v12.16b, v1.16b",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Addp,
-            rd: writable_vreg(8),
-            rn: vreg(12),
-            rm: vreg(14),
-            size: VectorSize::Size32x4,
-        },
-        "88BDAE4E",
-        "addp v8.4s, v12.4s, v14.4s",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Zip1,
-            rd: writable_vreg(16),
-            rn: vreg(12),
-            rm: vreg(1),
-            size: VectorSize::Size8x16,
-        },
-        "9039014E",
-        "zip1 v16.16b, v12.16b, v1.16b",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Zip1,
-            rd: writable_vreg(2),
-            rn: vreg(13),
-            rm: vreg(6),
-            size: VectorSize::Size16x8,
-        },
-        "A239464E",
-        "zip1 v2.8h, v13.8h, v6.8h",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Zip1,
-            rd: writable_vreg(8),
-            rn: vreg(12),
-            rm: vreg(14),
-            size: VectorSize::Size32x4,
-        },
-        "88398E4E",
-        "zip1 v8.4s, v12.4s, v14.4s",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Zip1,
-            rd: writable_vreg(9),
-            rn: vreg(20),
-            rm: vreg(17),
-            size: VectorSize::Size64x2,
-        },
-        "893AD14E",
-        "zip1 v9.2d, v20.2d, v17.2d",
-    ));
-
-    insns.push((
-        Inst::VecRRRLong {
-            alu_op: VecRRRLongOp::Smull8,
-            rd: writable_vreg(16),
-            rn: vreg(12),
-            rm: vreg(1),
-            high_half: false,
-        },
-        "90C1210E",
-        "smull v16.8h, v12.8b, v1.8b",
-    ));
-
-    insns.push((
-        Inst::VecRRRLong {
-            alu_op: VecRRRLongOp::Umull8,
-            rd: writable_vreg(15),
-            rn: vreg(11),
-            rm: vreg(2),
-            high_half: false,
-        },
-        "6FC1222E",
-        "umull v15.8h, v11.8b, v2.8b",
-    ));
-
-    insns.push((
-        Inst::VecRRRLong {
-            alu_op: VecRRRLongOp::Umlal8,
-            rd: writable_vreg(4),
-            rn: vreg(8),
-            rm: vreg(16),
-            high_half: false,
-        },
-        "0481302E",
-        "umlal v4.8h, v8.8b, v16.8b",
-    ));
-
-    insns.push((
-        Inst::VecRRRLong {
-            alu_op: VecRRRLongOp::Smull16,
-            rd: writable_vreg(2),
-            rn: vreg(13),
-            rm: vreg(6),
-            high_half: false,
-        },
-        "A2C1660E",
-        "smull v2.4s, v13.4h, v6.4h",
-    ));
-
-    insns.push((
-        Inst::VecRRRLong {
-            alu_op: VecRRRLongOp::Umull16,
-            rd: writable_vreg(3),
-            rn: vreg(14),
-            rm: vreg(7),
-            high_half: false,
-        },
-        "C3C1672E",
-        "umull v3.4s, v14.4h, v7.4h",
-    ));
-
-    insns.push((
-        Inst::VecRRRLong {
-            alu_op: VecRRRLongOp::Umlal16,
-            rd: writable_vreg(7),
-            rn: vreg(14),
-            rm: vreg(21),
-            high_half: false,
-        },
-        "C781752E",
-        "umlal v7.4s, v14.4h, v21.4h",
-    ));
-
-    insns.push((
-        Inst::VecRRRLong {
-            alu_op: VecRRRLongOp::Smull32,
-            rd: writable_vreg(8),
-            rn: vreg(12),
-            rm: vreg(14),
-            high_half: false,
-        },
-        "88C1AE0E",
-        "smull v8.2d, v12.2s, v14.2s",
-    ));
-
-    insns.push((
-        Inst::VecRRRLong {
-            alu_op: VecRRRLongOp::Umull32,
-            rd: writable_vreg(9),
-            rn: vreg(5),
-            rm: vreg(6),
-            high_half: false,
-        },
-        "A9C0A62E",
-        "umull v9.2d, v5.2s, v6.2s",
-    ));
-
-    insns.push((
-        Inst::VecRRRLong {
-            alu_op: VecRRRLongOp::Umlal32,
-            rd: writable_vreg(9),
-            rn: vreg(20),
-            rm: vreg(17),
-            high_half: false,
-        },
-        "8982B12E",
-        "umlal v9.2d, v20.2s, v17.2s",
-    ));
-
-    insns.push((
-        Inst::VecRRRLong {
-            alu_op: VecRRRLongOp::Smull8,
-            rd: writable_vreg(16),
-            rn: vreg(12),
-            rm: vreg(1),
-            high_half: true,
-        },
-        "90C1214E",
-        "smull2 v16.8h, v12.16b, v1.16b",
-    ));
-
-    insns.push((
-        Inst::VecRRRLong {
-            alu_op: VecRRRLongOp::Umull8,
-            rd: writable_vreg(29),
-            rn: vreg(22),
-            rm: vreg(10),
-            high_half: true,
-        },
-        "DDC22A6E",
-        "umull2 v29.8h, v22.16b, v10.16b",
-    ));
-
-    insns.push((
-        Inst::VecRRRLong {
-            alu_op: VecRRRLongOp::Umlal8,
-            rd: writable_vreg(1),
-            rn: vreg(5),
-            rm: vreg(15),
-            high_half: true,
-        },
-        "A1802F6E",
-        "umlal2 v1.8h, v5.16b, v15.16b",
-    ));
-
-    insns.push((
-        Inst::VecRRRLong {
-            alu_op: VecRRRLongOp::Smull16,
-            rd: writable_vreg(2),
-            rn: vreg(13),
-            rm: vreg(6),
-            high_half: true,
-        },
-        "A2C1664E",
-        "smull2 v2.4s, v13.8h, v6.8h",
-    ));
-
-    insns.push((
-        Inst::VecRRRLong {
-            alu_op: VecRRRLongOp::Umull16,
-            rd: writable_vreg(19),
-            rn: vreg(18),
-            rm: vreg(17),
-            high_half: true,
-        },
-        "53C2716E",
-        "umull2 v19.4s, v18.8h, v17.8h",
-    ));
-
-    insns.push((
-        Inst::VecRRRLong {
-            alu_op: VecRRRLongOp::Umlal16,
-            rd: writable_vreg(11),
-            rn: vreg(10),
-            rm: vreg(12),
-            high_half: true,
-        },
-        "4B816C6E",
-        "umlal2 v11.4s, v10.8h, v12.8h",
-    ));
-
-    insns.push((
-        Inst::VecRRRLong {
-            alu_op: VecRRRLongOp::Smull32,
-            rd: writable_vreg(8),
-            rn: vreg(12),
-            rm: vreg(14),
-            high_half: true,
-        },
-        "88C1AE4E",
-        "smull2 v8.2d, v12.4s, v14.4s",
-    ));
-
-    insns.push((
-        Inst::VecRRRLong {
-            alu_op: VecRRRLongOp::Umull32,
-            rd: writable_vreg(4),
-            rn: vreg(12),
-            rm: vreg(16),
-            high_half: true,
-        },
-        "84C1B06E",
-        "umull2 v4.2d, v12.4s, v16.4s",
-    ));
-
-    insns.push((
-        Inst::VecRRRLong {
-            alu_op: VecRRRLongOp::Umlal32,
-            rd: writable_vreg(10),
-            rn: vreg(29),
-            rm: vreg(2),
-            high_half: true,
-        },
-        "AA83A26E",
-        "umlal2 v10.2d, v29.4s, v2.4s",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Sqrdmulh,
-            rd: writable_vreg(31),
-            rn: vreg(0),
-            rm: vreg(31),
-            size: VectorSize::Size16x8,
-        },
-        "1FB47F6E",
-        "sqrdmulh v31.8h, v0.8h, v31.8h",
-    ));
-
-    insns.push((
-        Inst::VecRRR {
-            alu_op: VecALUOp::Sqrdmulh,
-            rd: writable_vreg(7),
-            rn: vreg(7),
-            rm: vreg(23),
-            size: VectorSize::Size32x2,
-        },
-        "E7B4B72E",
-        "sqrdmulh v7.2s, v7.2s, v23.2s",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Not,
-            rd: writable_vreg(20),
-            rn: vreg(17),
-            size: VectorSize::Size8x8,
-        },
-        "345A202E",
-        "mvn v20.8b, v17.8b",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Not,
-            rd: writable_vreg(2),
-            rn: vreg(1),
-            size: VectorSize::Size32x4,
-        },
-        "2258206E",
-        "mvn v2.16b, v1.16b",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Neg,
-            rd: writable_vreg(3),
-            rn: vreg(7),
-            size: VectorSize::Size8x8,
-        },
-        "E3B8202E",
-        "neg v3.8b, v7.8b",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Neg,
-            rd: writable_vreg(8),
-            rn: vreg(12),
-            size: VectorSize::Size8x16,
-        },
-        "88B9206E",
-        "neg v8.16b, v12.16b",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Neg,
-            rd: writable_vreg(0),
-            rn: vreg(31),
-            size: VectorSize::Size16x8,
-        },
-        "E0BB606E",
-        "neg v0.8h, v31.8h",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Neg,
-            rd: writable_vreg(2),
-            rn: vreg(3),
-            size: VectorSize::Size32x4,
-        },
-        "62B8A06E",
-        "neg v2.4s, v3.4s",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Neg,
-            rd: writable_vreg(10),
-            rn: vreg(8),
-            size: VectorSize::Size64x2,
-        },
-        "0AB9E06E",
-        "neg v10.2d, v8.2d",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Abs,
-            rd: writable_vreg(3),
-            rn: vreg(1),
-            size: VectorSize::Size8x8,
-        },
-        "23B8200E",
-        "abs v3.8b, v1.8b",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Abs,
-            rd: writable_vreg(1),
-            rn: vreg(1),
-            size: VectorSize::Size8x16,
-        },
-        "21B8204E",
-        "abs v1.16b, v1.16b",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Abs,
-            rd: writable_vreg(29),
-            rn: vreg(28),
-            size: VectorSize::Size16x8,
-        },
-        "9DBB604E",
-        "abs v29.8h, v28.8h",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Abs,
-            rd: writable_vreg(7),
-            rn: vreg(8),
-            size: VectorSize::Size32x4,
-        },
-        "07B9A04E",
-        "abs v7.4s, v8.4s",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Abs,
-            rd: writable_vreg(1),
-            rn: vreg(10),
-            size: VectorSize::Size64x2,
-        },
-        "41B9E04E",
-        "abs v1.2d, v10.2d",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Fabs,
-            rd: writable_vreg(15),
-            rn: vreg(16),
-            size: VectorSize::Size32x4,
-        },
-        "0FFAA04E",
-        "fabs v15.4s, v16.4s",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Fabs,
-            rd: writable_vreg(3),
-            rn: vreg(22),
-            size: VectorSize::Size64x2,
-        },
-        "C3FAE04E",
-        "fabs v3.2d, v22.2d",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Fneg,
-            rd: writable_vreg(31),
-            rn: vreg(0),
-            size: VectorSize::Size32x4,
-        },
-        "1FF8A06E",
-        "fneg v31.4s, v0.4s",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Fneg,
-            rd: writable_vreg(11),
-            rn: vreg(6),
-            size: VectorSize::Size64x2,
-        },
-        "CBF8E06E",
-        "fneg v11.2d, v6.2d",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Fsqrt,
-            rd: writable_vreg(18),
-            rn: vreg(25),
-            size: VectorSize::Size32x2,
-        },
-        "32FBA12E",
-        "fsqrt v18.2s, v25.2s",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Fsqrt,
-            rd: writable_vreg(7),
-            rn: vreg(18),
-            size: VectorSize::Size64x2,
-        },
-        "47FAE16E",
-        "fsqrt v7.2d, v18.2d",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Rev64,
-            rd: writable_vreg(1),
-            rn: vreg(10),
-            size: VectorSize::Size32x4,
-        },
-        "4109A04E",
-        "rev64 v1.4s, v10.4s",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Fcvtzs,
-            rd: writable_vreg(4),
-            rn: vreg(22),
-            size: VectorSize::Size32x4,
-        },
-        "C4BAA14E",
-        "fcvtzs v4.4s, v22.4s",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Fcvtzs,
-            rd: writable_vreg(0),
-            rn: vreg(31),
-            size: VectorSize::Size64x2,
-        },
-        "E0BBE14E",
-        "fcvtzs v0.2d, v31.2d",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Fcvtzu,
-            rd: writable_vreg(4),
-            rn: vreg(26),
-            size: VectorSize::Size32x2,
-        },
-        "44BBA12E",
-        "fcvtzu v4.2s, v26.2s",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Fcvtzu,
-            rd: writable_vreg(29),
-            rn: vreg(15),
-            size: VectorSize::Size64x2,
-        },
-        "FDB9E16E",
-        "fcvtzu v29.2d, v15.2d",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Scvtf,
-            rd: writable_vreg(20),
-            rn: vreg(8),
-            size: VectorSize::Size32x4,
-        },
-        "14D9214E",
-        "scvtf v20.4s, v8.4s",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Ucvtf,
-            rd: writable_vreg(10),
-            rn: vreg(19),
-            size: VectorSize::Size64x2,
-        },
-        "6ADA616E",
-        "ucvtf v10.2d, v19.2d",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Frintn,
-            rd: writable_vreg(20),
-            rn: vreg(7),
-            size: VectorSize::Size32x2,
-        },
-        "F488210E",
-        "frintn v20.2s, v7.2s",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Frintn,
-            rd: writable_vreg(11),
-            rn: vreg(18),
-            size: VectorSize::Size32x4,
-        },
-        "4B8A214E",
-        "frintn v11.4s, v18.4s",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Frintn,
-            rd: writable_vreg(12),
-            rn: vreg(17),
-            size: VectorSize::Size64x2,
-        },
-        "2C8A614E",
-        "frintn v12.2d, v17.2d",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Frintz,
-            rd: writable_vreg(1),
-            rn: vreg(30),
-            size: VectorSize::Size32x2,
-        },
-        "C19BA10E",
-        "frintz v1.2s, v30.2s",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Frintz,
-            rd: writable_vreg(11),
-            rn: vreg(18),
-            size: VectorSize::Size32x4,
-        },
-        "4B9AA14E",
-        "frintz v11.4s, v18.4s",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Frintz,
-            rd: writable_vreg(12),
-            rn: vreg(17),
-            size: VectorSize::Size64x2,
-        },
-        "2C9AE14E",
-        "frintz v12.2d, v17.2d",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Frintm,
-            rd: writable_vreg(15),
-            rn: vreg(7),
-            size: VectorSize::Size32x2,
-        },
-        "EF98210E",
-        "frintm v15.2s, v7.2s",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Frintm,
-            rd: writable_vreg(11),
-            rn: vreg(18),
-            size: VectorSize::Size32x4,
-        },
-        "4B9A214E",
-        "frintm v11.4s, v18.4s",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Frintm,
-            rd: writable_vreg(12),
-            rn: vreg(17),
-            size: VectorSize::Size64x2,
-        },
-        "2C9A614E",
-        "frintm v12.2d, v17.2d",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Frintp,
-            rd: writable_vreg(3),
-            rn: vreg(4),
-            size: VectorSize::Size32x2,
-        },
-        "8388A10E",
-        "frintp v3.2s, v4.2s",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Frintp,
-            rd: writable_vreg(11),
-            rn: vreg(18),
-            size: VectorSize::Size32x4,
-        },
-        "4B8AA14E",
-        "frintp v11.4s, v18.4s",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Frintp,
-            rd: writable_vreg(12),
-            rn: vreg(17),
-            size: VectorSize::Size64x2,
-        },
-        "2C8AE14E",
-        "frintp v12.2d, v17.2d",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Cnt,
-            rd: writable_vreg(23),
-            rn: vreg(5),
-            size: VectorSize::Size8x8,
-        },
-        "B758200E",
-        "cnt v23.8b, v5.8b",
-    ));
-
-    insns.push((
-        Inst::VecMisc {
-            op: VecMisc2::Cmeq0,
-            rd: writable_vreg(12),
-            rn: vreg(27),
-            size: VectorSize::Size16x8,
-        },
-        "6C9B604E",
-        "cmeq v12.8h, v27.8h, #0",
-    ));
-
-    insns.push((
-        Inst::VecLanes {
-            op: VecLanesOp::Uminv,
-            rd: writable_vreg(0),
-            rn: vreg(31),
-            size: VectorSize::Size8x8,
-        },
-        "E0AB312E",
-        "uminv b0, v31.8b",
-    ));
-
-    insns.push((
-        Inst::VecLanes {
-            op: VecLanesOp::Uminv,
-            rd: writable_vreg(2),
-            rn: vreg(1),
-            size: VectorSize::Size8x16,
-        },
-        "22A8316E",
-        "uminv b2, v1.16b",
-    ));
-
-    insns.push((
-        Inst::VecLanes {
-            op: VecLanesOp::Uminv,
-            rd: writable_vreg(3),
-            rn: vreg(11),
-            size: VectorSize::Size16x8,
-        },
-        "63A9716E",
-        "uminv h3, v11.8h",
-    ));
-
-    insns.push((
-        Inst::VecLanes {
-            op: VecLanesOp::Uminv,
-            rd: writable_vreg(18),
-            rn: vreg(4),
-            size: VectorSize::Size32x4,
-        },
-        "92A8B16E",
-        "uminv s18, v4.4s",
-    ));
-
-    insns.push((
-        Inst::VecLanes {
-            op: VecLanesOp::Addv,
-            rd: writable_vreg(2),
-            rn: vreg(29),
-            size: VectorSize::Size8x16,
-        },
-        "A2BB314E",
-        "addv b2, v29.16b",
-    ));
-
-    insns.push((
-        Inst::VecLanes {
-            op: VecLanesOp::Addv,
-            rd: writable_vreg(15),
-            rn: vreg(7),
-            size: VectorSize::Size16x4,
-        },
-        "EFB8710E",
-        "addv h15, v7.4h",
-    ));
-
-    insns.push((
-        Inst::VecLanes {
-            op: VecLanesOp::Addv,
-            rd: writable_vreg(3),
-            rn: vreg(21),
-            size: VectorSize::Size16x8,
-        },
-        "A3BA714E",
-        "addv h3, v21.8h",
-    ));
-
-    insns.push((
-        Inst::VecLanes {
-            op: VecLanesOp::Addv,
-            rd: writable_vreg(18),
-            rn: vreg(5),
-            size: VectorSize::Size32x4,
-        },
-        "B2B8B14E",
-        "addv s18, v5.4s",
-    ));
-
-    insns.push((
-        Inst::VecShiftImm {
-            op: VecShiftImmOp::Shl,
-            rd: writable_vreg(27),
-            rn: vreg(5),
-            imm: 7,
-            size: VectorSize::Size8x16,
-        },
-        "BB540F4F",
-        "shl v27.16b, v5.16b, #7",
-    ));
-
-    insns.push((
-        Inst::VecShiftImm {
-            op: VecShiftImmOp::Shl,
-            rd: writable_vreg(1),
-            rn: vreg(30),
-            imm: 0,
-            size: VectorSize::Size8x16,
-        },
-        "C157084F",
-        "shl v1.16b, v30.16b, #0",
-    ));
-
-    insns.push((
-        Inst::VecShiftImm {
-            op: VecShiftImmOp::Sshr,
-            rd: writable_vreg(26),
-            rn: vreg(6),
-            imm: 16,
-            size: VectorSize::Size16x8,
-        },
-        "DA04104F",
-        "sshr v26.8h, v6.8h, #16",
-    ));
-
-    insns.push((
-        Inst::VecShiftImm {
-            op: VecShiftImmOp::Sshr,
-            rd: writable_vreg(3),
-            rn: vreg(19),
-            imm: 1,
-            size: VectorSize::Size16x8,
-        },
-        "63061F4F",
-        "sshr v3.8h, v19.8h, #1",
-    ));
-
-    insns.push((
-        Inst::VecShiftImm {
-            op: VecShiftImmOp::Ushr,
-            rd: writable_vreg(25),
-            rn: vreg(6),
-            imm: 32,
-            size: VectorSize::Size32x4,
-        },
-        "D904206F",
-        "ushr v25.4s, v6.4s, #32",
-    ));
-
-    insns.push((
-        Inst::VecShiftImm {
-            op: VecShiftImmOp::Ushr,
-            rd: writable_vreg(5),
-            rn: vreg(21),
-            imm: 1,
-            size: VectorSize::Size32x4,
-        },
-        "A5063F6F",
-        "ushr v5.4s, v21.4s, #1",
-    ));
-
-    insns.push((
-        Inst::VecShiftImm {
-            op: VecShiftImmOp::Shl,
-            rd: writable_vreg(22),
-            rn: vreg(13),
-            imm: 63,
-            size: VectorSize::Size64x2,
-        },
-        "B6557F4F",
-        "shl v22.2d, v13.2d, #63",
-    ));
-
-    insns.push((
-        Inst::VecShiftImm {
-            op: VecShiftImmOp::Shl,
-            rd: writable_vreg(23),
-            rn: vreg(9),
-            imm: 0,
-            size: VectorSize::Size64x2,
-        },
-        "3755404F",
-        "shl v23.2d, v9.2d, #0",
-    ));
-
-    insns.push((
-        Inst::VecExtract {
-            rd: writable_vreg(1),
-            rn: vreg(30),
-            rm: vreg(17),
-            imm4: 0,
-        },
-        "C103116E",
-        "ext v1.16b, v30.16b, v17.16b, #0",
-    ));
-
-    insns.push((
-        Inst::VecExtract {
-            rd: writable_vreg(1),
-            rn: vreg(30),
-            rm: vreg(17),
-            imm4: 8,
-        },
-        "C143116E",
-        "ext v1.16b, v30.16b, v17.16b, #8",
-    ));
-
-    insns.push((
-        Inst::VecExtract {
-            rd: writable_vreg(1),
-            rn: vreg(30),
-            rm: vreg(17),
-            imm4: 15,
-        },
-        "C17B116E",
-        "ext v1.16b, v30.16b, v17.16b, #15",
-    ));
-
-    insns.push((
-        Inst::VecTbl {
-            rd: writable_vreg(0),
-            rn: vreg(31),
-            rm: vreg(16),
-            is_extension: false,
-        },
-        "E003104E",
-        "tbl v0.16b, { v31.16b }, v16.16b",
-    ));
-
-    insns.push((
-        Inst::VecTbl {
-            rd: writable_vreg(4),
-            rn: vreg(12),
-            rm: vreg(23),
-            is_extension: true,
-        },
-        "8411174E",
-        "tbx v4.16b, { v12.16b }, v23.16b",
-    ));
-
-    insns.push((
-        Inst::VecTbl2 {
-            rd: writable_vreg(16),
-            rn: vreg(31),
-            rn2: vreg(0),
-            rm: vreg(26),
-            is_extension: false,
-        },
-        "F0231A4E",
-        "tbl v16.16b, { v31.16b, v0.16b }, v26.16b",
-    ));
-
-    insns.push((
-        Inst::VecTbl2 {
-            rd: writable_vreg(3),
-            rn: vreg(11),
-            rn2: vreg(12),
-            rm: vreg(19),
-            is_extension: true,
-        },
-        "6331134E",
-        "tbx v3.16b, { v11.16b, v12.16b }, v19.16b",
-    ));
-
-    insns.push((
-        Inst::VecLoadReplicate {
-            rd: writable_vreg(31),
-            rn: xreg(0),
-
-            size: VectorSize::Size64x2,
-        },
-        "1FCC404D",
-        "ld1r { v31.2d }, [x0]",
-    ));
-
-    insns.push((
-        Inst::VecLoadReplicate {
-            rd: writable_vreg(0),
-            rn: xreg(25),
-
-            size: VectorSize::Size8x8,
-        },
-        "20C3400D",
-        "ld1r { v0.8b }, [x25]",
-    ));
-
-    insns.push((
-        Inst::VecCSel {
-            rd: writable_vreg(5),
-            rn: vreg(10),
-            rm: vreg(19),
-            cond: Cond::Gt,
-        },
-        "6C000054651EB34E02000014451DAA4E",
-        "vcsel v5.16b, v10.16b, v19.16b, gt (if-then-else diamond)",
-    ));
-
-    insns.push((
-        Inst::Extend {
-            rd: writable_xreg(3),
-            rn: xreg(5),
-            signed: false,
-            from_bits: 1,
-            to_bits: 32,
-        },
-        "A3000012",
-        "and w3, w5, #1",
-    ));
-    insns.push((
-        Inst::Extend {
-            rd: writable_xreg(3),
-            rn: xreg(5),
-            signed: false,
-            from_bits: 1,
-            to_bits: 64,
-        },
-        "A3000012",
-        "and w3, w5, #1",
-    ));
-    insns.push((
-        Inst::Extend {
-            rd: writable_xreg(10),
-            rn: xreg(21),
-            signed: true,
-            from_bits: 1,
-            to_bits: 32,
-        },
-        "AA020013",
-        "sbfx w10, w21, #0, #1",
-    ));
-    insns.push((
-        Inst::Extend {
-            rd: writable_xreg(1),
-            rn: xreg(2),
-            signed: true,
-            from_bits: 1,
-            to_bits: 64,
-        },
-        "41004093",
-        "sbfx x1, x2, #0, #1",
-    ));
-    insns.push((
-        Inst::Extend {
-            rd: writable_xreg(1),
-            rn: xreg(2),
-            signed: false,
-            from_bits: 8,
-            to_bits: 32,
-        },
-        "411C0053",
-        "uxtb w1, w2",
-    ));
-    insns.push((
-        Inst::Extend {
-            rd: writable_xreg(1),
-            rn: xreg(2),
-            signed: true,
-            from_bits: 8,
-            to_bits: 32,
-        },
-        "411C0013",
-        "sxtb w1, w2",
-    ));
-    insns.push((
-        Inst::Extend {
-            rd: writable_xreg(1),
-            rn: xreg(2),
-            signed: false,
-            from_bits: 16,
-            to_bits: 32,
-        },
-        "413C0053",
-        "uxth w1, w2",
-    ));
-    insns.push((
-        Inst::Extend {
-            rd: writable_xreg(1),
-            rn: xreg(2),
-            signed: true,
-            from_bits: 16,
-            to_bits: 32,
-        },
-        "413C0013",
-        "sxth w1, w2",
-    ));
-    insns.push((
-        Inst::Extend {
-            rd: writable_xreg(1),
-            rn: xreg(2),
-            signed: false,
-            from_bits: 8,
-            to_bits: 64,
-        },
-        "411C0053",
-        "uxtb w1, w2",
-    ));
-    insns.push((
-        Inst::Extend {
-            rd: writable_xreg(1),
-            rn: xreg(2),
-            signed: true,
-            from_bits: 8,
-            to_bits: 64,
-        },
-        "411C4093",
-        "sxtb x1, w2",
-    ));
-    insns.push((
-        Inst::Extend {
-            rd: writable_xreg(1),
-            rn: xreg(2),
-            signed: false,
-            from_bits: 16,
-            to_bits: 64,
-        },
-        "413C0053",
-        "uxth w1, w2",
-    ));
-    insns.push((
-        Inst::Extend {
-            rd: writable_xreg(1),
-            rn: xreg(2),
-            signed: true,
-            from_bits: 16,
-            to_bits: 64,
-        },
-        "413C4093",
-        "sxth x1, w2",
-    ));
-    insns.push((
-        Inst::Extend {
-            rd: writable_xreg(1),
-            rn: xreg(2),
-            signed: false,
-            from_bits: 32,
-            to_bits: 64,
-        },
-        "E103022A",
-        "mov w1, w2",
-    ));
-    insns.push((
-        Inst::Extend {
-            rd: writable_xreg(1),
-            rn: xreg(2),
-            signed: true,
-            from_bits: 32,
-            to_bits: 64,
-        },
-        "417C4093",
-        "sxtw x1, w2",
-    ));
-
-    insns.push((
-        Inst::Jump {
-            dest: BranchTarget::ResolvedOffset(64),
-        },
-        "10000014",
-        "b 64",
-    ));
-
-    insns.push((
-        Inst::TrapIf {
-            trap_code: TrapCode::Interrupt,
-            kind: CondBrKind::NotZero(xreg(8)),
-        },
-        "480000B40000A0D4",
-        "cbz x8, 8 ; udf",
-    ));
-    insns.push((
-        Inst::TrapIf {
-            trap_code: TrapCode::Interrupt,
-            kind: CondBrKind::Zero(xreg(8)),
-        },
-        "480000B50000A0D4",
-        "cbnz x8, 8 ; udf",
-    ));
-    insns.push((
-        Inst::TrapIf {
-            trap_code: TrapCode::Interrupt,
-            kind: CondBrKind::Cond(Cond::Ne),
-        },
-        "400000540000A0D4",
-        "b.eq 8 ; udf",
-    ));
-    insns.push((
-        Inst::TrapIf {
-            trap_code: TrapCode::Interrupt,
-            kind: CondBrKind::Cond(Cond::Eq),
-        },
-        "410000540000A0D4",
-        "b.ne 8 ; udf",
-    ));
-    insns.push((
-        Inst::TrapIf {
-            trap_code: TrapCode::Interrupt,
-            kind: CondBrKind::Cond(Cond::Lo),
-        },
-        "420000540000A0D4",
-        "b.hs 8 ; udf",
-    ));
-    insns.push((
-        Inst::TrapIf {
-            trap_code: TrapCode::Interrupt,
-            kind: CondBrKind::Cond(Cond::Hs),
-        },
-        "430000540000A0D4",
-        "b.lo 8 ; udf",
-    ));
-    insns.push((
-        Inst::TrapIf {
-            trap_code: TrapCode::Interrupt,
-            kind: CondBrKind::Cond(Cond::Pl),
-        },
-        "440000540000A0D4",
-        "b.mi 8 ; udf",
-    ));
-    insns.push((
-        Inst::TrapIf {
-            trap_code: TrapCode::Interrupt,
-            kind: CondBrKind::Cond(Cond::Mi),
-        },
-        "450000540000A0D4",
-        "b.pl 8 ; udf",
-    ));
-    insns.push((
-        Inst::TrapIf {
-            trap_code: TrapCode::Interrupt,
-            kind: CondBrKind::Cond(Cond::Vc),
-        },
-        "460000540000A0D4",
-        "b.vs 8 ; udf",
-    ));
-    insns.push((
-        Inst::TrapIf {
-            trap_code: TrapCode::Interrupt,
-            kind: CondBrKind::Cond(Cond::Vs),
-        },
-        "470000540000A0D4",
-        "b.vc 8 ; udf",
-    ));
-    insns.push((
-        Inst::TrapIf {
-            trap_code: TrapCode::Interrupt,
-            kind: CondBrKind::Cond(Cond::Ls),
-        },
-        "480000540000A0D4",
-        "b.hi 8 ; udf",
-    ));
-    insns.push((
-        Inst::TrapIf {
-            trap_code: TrapCode::Interrupt,
-            kind: CondBrKind::Cond(Cond::Hi),
-        },
-        "490000540000A0D4",
-        "b.ls 8 ; udf",
-    ));
-    insns.push((
-        Inst::TrapIf {
-            trap_code: TrapCode::Interrupt,
-            kind: CondBrKind::Cond(Cond::Lt),
-        },
-        "4A0000540000A0D4",
-        "b.ge 8 ; udf",
-    ));
-    insns.push((
-        Inst::TrapIf {
-            trap_code: TrapCode::Interrupt,
-            kind: CondBrKind::Cond(Cond::Ge),
-        },
-        "4B0000540000A0D4",
-        "b.lt 8 ; udf",
-    ));
-    insns.push((
-        Inst::TrapIf {
-            trap_code: TrapCode::Interrupt,
-            kind: CondBrKind::Cond(Cond::Le),
-        },
-        "4C0000540000A0D4",
-        "b.gt 8 ; udf",
-    ));
-    insns.push((
-        Inst::TrapIf {
-            trap_code: TrapCode::Interrupt,
-            kind: CondBrKind::Cond(Cond::Gt),
-        },
-        "4D0000540000A0D4",
-        "b.le 8 ; udf",
-    ));
-    insns.push((
-        Inst::TrapIf {
-            trap_code: TrapCode::Interrupt,
-            kind: CondBrKind::Cond(Cond::Nv),
-        },
-        "4E0000540000A0D4",
-        "b.al 8 ; udf",
-    ));
-    insns.push((
-        Inst::TrapIf {
-            trap_code: TrapCode::Interrupt,
-            kind: CondBrKind::Cond(Cond::Al),
-        },
-        "4F0000540000A0D4",
-        "b.nv 8 ; udf",
-    ));
-
-    insns.push((
-        Inst::CondBr {
-            taken: BranchTarget::ResolvedOffset(64),
-            not_taken: BranchTarget::ResolvedOffset(128),
-            kind: CondBrKind::Cond(Cond::Le),
-        },
-        "0D02005420000014",
-        "b.le 64 ; b 128",
-    ));
-
-    insns.push((
-        Inst::Call {
-            info: Box::new(CallInfo {
-                dest: ExternalName::testcase("test0"),
-                uses: Vec::new(),
-                defs: Vec::new(),
-                opcode: Opcode::Call,
-                caller_callconv: CallConv::SystemV,
-                callee_callconv: CallConv::SystemV,
-            }),
-        },
-        "00000094",
-        "bl 0",
-    ));
-
-    insns.push((
-        Inst::CallInd {
-            info: Box::new(CallIndInfo {
-                rn: xreg(10),
-                uses: Vec::new(),
-                defs: Vec::new(),
-                opcode: Opcode::CallIndirect,
-                caller_callconv: CallConv::SystemV,
-                callee_callconv: CallConv::SystemV,
-            }),
-        },
-        "40013FD6",
-        "blr x10",
-    ));
-
-    insns.push((
-        Inst::IndirectBr {
-            rn: xreg(3),
-            targets: vec![],
-        },
-        "60001FD6",
-        "br x3",
-    ));
-
-    insns.push((Inst::Brk, "000020D4", "brk #0"));
-
-    insns.push((
-        Inst::Adr {
-            rd: writable_xreg(15),
-            off: (1 << 20) - 4,
-        },
-        "EFFF7F10",
-        "adr x15, pc+1048572",
-    ));
-
-    insns.push((
-        Inst::FpuMove64 {
-            rd: writable_vreg(8),
-            rn: vreg(4),
-        },
-        "8840601E",
-        "fmov d8, d4",
-    ));
-
-    insns.push((
-        Inst::FpuMove128 {
-            rd: writable_vreg(17),
-            rn: vreg(26),
-        },
-        "511FBA4E",
-        "mov v17.16b, v26.16b",
-    ));
-
-    insns.push((
-        Inst::FpuMoveFromVec {
-            rd: writable_vreg(1),
-            rn: vreg(30),
-            idx: 2,
-            size: VectorSize::Size32x4,
-        },
-        "C107145E",
-        "mov s1, v30.s[2]",
-    ));
-
-    insns.push((
-        Inst::FpuMoveFromVec {
-            rd: writable_vreg(23),
-            rn: vreg(11),
-            idx: 0,
-            size: VectorSize::Size64x2,
-        },
-        "7705085E",
-        "mov d23, v11.d[0]",
-    ));
-
-    insns.push((
-        Inst::FpuExtend {
-            rd: writable_vreg(31),
-            rn: vreg(0),
-            size: ScalarSize::Size32,
-        },
-        "1F40201E",
-        "fmov s31, s0",
-    ));
-
-    insns.push((
-        Inst::FpuRR {
-            fpu_op: FPUOp1::Abs32,
-            rd: writable_vreg(15),
-            rn: vreg(30),
-        },
-        "CFC3201E",
-        "fabs s15, s30",
-    ));
-
-    insns.push((
-        Inst::FpuRR {
-            fpu_op: FPUOp1::Abs64,
-            rd: writable_vreg(15),
-            rn: vreg(30),
-        },
-        "CFC3601E",
-        "fabs d15, d30",
-    ));
-
-    insns.push((
-        Inst::FpuRR {
-            fpu_op: FPUOp1::Neg32,
-            rd: writable_vreg(15),
-            rn: vreg(30),
-        },
-        "CF43211E",
-        "fneg s15, s30",
-    ));
-
-    insns.push((
-        Inst::FpuRR {
-            fpu_op: FPUOp1::Neg64,
-            rd: writable_vreg(15),
-            rn: vreg(30),
-        },
-        "CF43611E",
-        "fneg d15, d30",
-    ));
-
-    insns.push((
-        Inst::FpuRR {
-            fpu_op: FPUOp1::Sqrt32,
-            rd: writable_vreg(15),
-            rn: vreg(30),
-        },
-        "CFC3211E",
-        "fsqrt s15, s30",
-    ));
-
-    insns.push((
-        Inst::FpuRR {
-            fpu_op: FPUOp1::Sqrt64,
-            rd: writable_vreg(15),
-            rn: vreg(30),
-        },
-        "CFC3611E",
-        "fsqrt d15, d30",
-    ));
-
-    insns.push((
-        Inst::FpuRR {
-            fpu_op: FPUOp1::Cvt32To64,
-            rd: writable_vreg(15),
-            rn: vreg(30),
-        },
-        "CFC3221E",
-        "fcvt d15, s30",
-    ));
-
-    insns.push((
-        Inst::FpuRR {
-            fpu_op: FPUOp1::Cvt64To32,
-            rd: writable_vreg(15),
-            rn: vreg(30),
-        },
-        "CF43621E",
-        "fcvt s15, d30",
-    ));
-
-    insns.push((
-        Inst::FpuRRR {
-            fpu_op: FPUOp2::Add32,
-            rd: writable_vreg(15),
-            rn: vreg(30),
-            rm: vreg(31),
-        },
-        "CF2B3F1E",
-        "fadd s15, s30, s31",
-    ));
-
-    insns.push((
-        Inst::FpuRRR {
-            fpu_op: FPUOp2::Add64,
-            rd: writable_vreg(15),
-            rn: vreg(30),
-            rm: vreg(31),
-        },
-        "CF2B7F1E",
-        "fadd d15, d30, d31",
-    ));
-
-    insns.push((
-        Inst::FpuRRR {
-            fpu_op: FPUOp2::Sub32,
-            rd: writable_vreg(15),
-            rn: vreg(30),
-            rm: vreg(31),
-        },
-        "CF3B3F1E",
-        "fsub s15, s30, s31",
-    ));
-
-    insns.push((
-        Inst::FpuRRR {
-            fpu_op: FPUOp2::Sub64,
-            rd: writable_vreg(15),
-            rn: vreg(30),
-            rm: vreg(31),
-        },
-        "CF3B7F1E",
-        "fsub d15, d30, d31",
-    ));
-
-    insns.push((
-        Inst::FpuRRR {
-            fpu_op: FPUOp2::Mul32,
-            rd: writable_vreg(15),
-            rn: vreg(30),
-            rm: vreg(31),
-        },
-        "CF0B3F1E",
-        "fmul s15, s30, s31",
-    ));
-
-    insns.push((
-        Inst::FpuRRR {
-            fpu_op: FPUOp2::Mul64,
-            rd: writable_vreg(15),
-            rn: vreg(30),
-            rm: vreg(31),
-        },
-        "CF0B7F1E",
-        "fmul d15, d30, d31",
-    ));
-
-    insns.push((
-        Inst::FpuRRR {
-            fpu_op: FPUOp2::Div32,
-            rd: writable_vreg(15),
-            rn: vreg(30),
-            rm: vreg(31),
-        },
-        "CF1B3F1E",
-        "fdiv s15, s30, s31",
-    ));
-
-    insns.push((
-        Inst::FpuRRR {
-            fpu_op: FPUOp2::Div64,
-            rd: writable_vreg(15),
-            rn: vreg(30),
-            rm: vreg(31),
-        },
-        "CF1B7F1E",
-        "fdiv d15, d30, d31",
-    ));
-
-    insns.push((
-        Inst::FpuRRR {
-            fpu_op: FPUOp2::Max32,
-            rd: writable_vreg(15),
-            rn: vreg(30),
-            rm: vreg(31),
-        },
-        "CF4B3F1E",
-        "fmax s15, s30, s31",
-    ));
-
-    insns.push((
-        Inst::FpuRRR {
-            fpu_op: FPUOp2::Max64,
-            rd: writable_vreg(15),
-            rn: vreg(30),
-            rm: vreg(31),
-        },
-        "CF4B7F1E",
-        "fmax d15, d30, d31",
-    ));
-
-    insns.push((
-        Inst::FpuRRR {
-            fpu_op: FPUOp2::Min32,
-            rd: writable_vreg(15),
-            rn: vreg(30),
-            rm: vreg(31),
-        },
-        "CF5B3F1E",
-        "fmin s15, s30, s31",
-    ));
-
-    insns.push((
-        Inst::FpuRRR {
-            fpu_op: FPUOp2::Min64,
-            rd: writable_vreg(15),
-            rn: vreg(30),
-            rm: vreg(31),
-        },
-        "CF5B7F1E",
-        "fmin d15, d30, d31",
-    ));
-
-    insns.push((
-        Inst::FpuRRR {
-            fpu_op: FPUOp2::Uqadd64,
-            rd: writable_vreg(21),
-            rn: vreg(22),
-            rm: vreg(23),
-        },
-        "D50EF77E",
-        "uqadd d21, d22, d23",
-    ));
-
-    insns.push((
-        Inst::FpuRRR {
-            fpu_op: FPUOp2::Sqadd64,
-            rd: writable_vreg(21),
-            rn: vreg(22),
-            rm: vreg(23),
-        },
-        "D50EF75E",
-        "sqadd d21, d22, d23",
-    ));
-
-    insns.push((
-        Inst::FpuRRR {
-            fpu_op: FPUOp2::Uqsub64,
-            rd: writable_vreg(21),
-            rn: vreg(22),
-            rm: vreg(23),
-        },
-        "D52EF77E",
-        "uqsub d21, d22, d23",
-    ));
-
-    insns.push((
-        Inst::FpuRRR {
-            fpu_op: FPUOp2::Sqsub64,
-            rd: writable_vreg(21),
-            rn: vreg(22),
-            rm: vreg(23),
-        },
-        "D52EF75E",
-        "sqsub d21, d22, d23",
-    ));
-
-    insns.push((
-        Inst::FpuRRRR {
-            fpu_op: FPUOp3::MAdd32,
-            rd: writable_vreg(15),
-            rn: vreg(30),
-            rm: vreg(31),
-            ra: vreg(1),
-        },
-        "CF071F1F",
-        "fmadd s15, s30, s31, s1",
-    ));
-
-    insns.push((
-        Inst::FpuRRRR {
-            fpu_op: FPUOp3::MAdd64,
-            rd: writable_vreg(15),
-            rn: vreg(30),
-            rm: vreg(31),
-            ra: vreg(1),
-        },
-        "CF075F1F",
-        "fmadd d15, d30, d31, d1",
-    ));
-
-    insns.push((
-        Inst::FpuRRI {
-            fpu_op: FPUOpRI::UShr32(FPURightShiftImm::maybe_from_u8(32, 32).unwrap()),
-            rd: writable_vreg(2),
-            rn: vreg(5),
-        },
-        "A204202F",
-        "ushr v2.2s, v5.2s, #32",
-    ));
-
-    insns.push((
-        Inst::FpuRRI {
-            fpu_op: FPUOpRI::UShr64(FPURightShiftImm::maybe_from_u8(63, 64).unwrap()),
-            rd: writable_vreg(2),
-            rn: vreg(5),
-        },
-        "A204417F",
-        "ushr d2, d5, #63",
-    ));
-
-    insns.push((
-        Inst::FpuRRI {
-            fpu_op: FPUOpRI::Sli32(FPULeftShiftImm::maybe_from_u8(31, 32).unwrap()),
-            rd: writable_vreg(4),
-            rn: vreg(10),
-        },
-        "44553F2F",
-        "sli v4.2s, v10.2s, #31",
-    ));
-
-    insns.push((
-        Inst::FpuRRI {
-            fpu_op: FPUOpRI::Sli64(FPULeftShiftImm::maybe_from_u8(63, 64).unwrap()),
-            rd: writable_vreg(4),
-            rn: vreg(10),
-        },
-        "44557F7F",
-        "sli d4, d10, #63",
-    ));
-
-    insns.push((
-        Inst::FpuToInt {
-            op: FpuToIntOp::F32ToU32,
-            rd: writable_xreg(1),
-            rn: vreg(4),
-        },
-        "8100391E",
-        "fcvtzu w1, s4",
-    ));
-
-    insns.push((
-        Inst::FpuToInt {
-            op: FpuToIntOp::F32ToU64,
-            rd: writable_xreg(1),
-            rn: vreg(4),
-        },
-        "8100399E",
-        "fcvtzu x1, s4",
-    ));
-
-    insns.push((
-        Inst::FpuToInt {
-            op: FpuToIntOp::F32ToI32,
-            rd: writable_xreg(1),
-            rn: vreg(4),
-        },
-        "8100381E",
-        "fcvtzs w1, s4",
-    ));
-
-    insns.push((
-        Inst::FpuToInt {
-            op: FpuToIntOp::F32ToI64,
-            rd: writable_xreg(1),
-            rn: vreg(4),
-        },
-        "8100389E",
-        "fcvtzs x1, s4",
-    ));
-
-    insns.push((
-        Inst::FpuToInt {
-            op: FpuToIntOp::F64ToU32,
-            rd: writable_xreg(1),
-            rn: vreg(4),
-        },
-        "8100791E",
-        "fcvtzu w1, d4",
-    ));
-
-    insns.push((
-        Inst::FpuToInt {
-            op: FpuToIntOp::F64ToU64,
-            rd: writable_xreg(1),
-            rn: vreg(4),
-        },
-        "8100799E",
-        "fcvtzu x1, d4",
-    ));
-
-    insns.push((
-        Inst::FpuToInt {
-            op: FpuToIntOp::F64ToI32,
-            rd: writable_xreg(1),
-            rn: vreg(4),
-        },
-        "8100781E",
-        "fcvtzs w1, d4",
-    ));
-
-    insns.push((
-        Inst::FpuToInt {
-            op: FpuToIntOp::F64ToI64,
-            rd: writable_xreg(1),
-            rn: vreg(4),
-        },
-        "8100789E",
-        "fcvtzs x1, d4",
-    ));
-
-    insns.push((
-        Inst::IntToFpu {
-            op: IntToFpuOp::U32ToF32,
-            rd: writable_vreg(1),
-            rn: xreg(4),
-        },
-        "8100231E",
-        "ucvtf s1, w4",
-    ));
-
-    insns.push((
-        Inst::IntToFpu {
-            op: IntToFpuOp::I32ToF32,
-            rd: writable_vreg(1),
-            rn: xreg(4),
-        },
-        "8100221E",
-        "scvtf s1, w4",
-    ));
-
-    insns.push((
-        Inst::IntToFpu {
-            op: IntToFpuOp::U32ToF64,
-            rd: writable_vreg(1),
-            rn: xreg(4),
-        },
-        "8100631E",
-        "ucvtf d1, w4",
-    ));
-
-    insns.push((
-        Inst::IntToFpu {
-            op: IntToFpuOp::I32ToF64,
-            rd: writable_vreg(1),
-            rn: xreg(4),
-        },
-        "8100621E",
-        "scvtf d1, w4",
-    ));
-
-    insns.push((
-        Inst::IntToFpu {
-            op: IntToFpuOp::U64ToF32,
-            rd: writable_vreg(1),
-            rn: xreg(4),
-        },
-        "8100239E",
-        "ucvtf s1, x4",
-    ));
-
-    insns.push((
-        Inst::IntToFpu {
-            op: IntToFpuOp::I64ToF32,
-            rd: writable_vreg(1),
-            rn: xreg(4),
-        },
-        "8100229E",
-        "scvtf s1, x4",
-    ));
-
-    insns.push((
-        Inst::IntToFpu {
-            op: IntToFpuOp::U64ToF64,
-            rd: writable_vreg(1),
-            rn: xreg(4),
-        },
-        "8100639E",
-        "ucvtf d1, x4",
-    ));
-
-    insns.push((
-        Inst::IntToFpu {
-            op: IntToFpuOp::I64ToF64,
-            rd: writable_vreg(1),
-            rn: xreg(4),
-        },
-        "8100629E",
-        "scvtf d1, x4",
-    ));
-
-    insns.push((
-        Inst::FpuCmp32 {
-            rn: vreg(23),
-            rm: vreg(24),
-        },
-        "E022381E",
-        "fcmp s23, s24",
-    ));
-
-    insns.push((
-        Inst::FpuCmp64 {
-            rn: vreg(23),
-            rm: vreg(24),
-        },
-        "E022781E",
-        "fcmp d23, d24",
-    ));
-
-    insns.push((
-        Inst::FpuLoad32 {
-            rd: writable_vreg(16),
-            mem: AMode::RegScaled(xreg(8), xreg(9), F32),
-            flags: MemFlags::trusted(),
-        },
-        "107969BC",
-        "ldr s16, [x8, x9, LSL #2]",
-    ));
-
-    insns.push((
-        Inst::FpuLoad64 {
-            rd: writable_vreg(16),
-            mem: AMode::RegScaled(xreg(8), xreg(9), F64),
-            flags: MemFlags::trusted(),
-        },
-        "107969FC",
-        "ldr d16, [x8, x9, LSL #3]",
-    ));
-
-    insns.push((
-        Inst::FpuLoad128 {
-            rd: writable_vreg(16),
-            mem: AMode::RegScaled(xreg(8), xreg(9), I128),
-            flags: MemFlags::trusted(),
-        },
-        "1079E93C",
-        "ldr q16, [x8, x9, LSL #4]",
-    ));
-
-    insns.push((
-        Inst::FpuLoad32 {
-            rd: writable_vreg(16),
-            mem: AMode::Label(MemLabel::PCRel(8)),
-            flags: MemFlags::trusted(),
-        },
-        "5000001C",
-        "ldr s16, pc+8",
-    ));
-
-    insns.push((
-        Inst::FpuLoad64 {
-            rd: writable_vreg(16),
-            mem: AMode::Label(MemLabel::PCRel(8)),
-            flags: MemFlags::trusted(),
-        },
-        "5000005C",
-        "ldr d16, pc+8",
-    ));
-
-    insns.push((
-        Inst::FpuLoad128 {
-            rd: writable_vreg(16),
-            mem: AMode::Label(MemLabel::PCRel(8)),
-            flags: MemFlags::trusted(),
-        },
-        "5000009C",
-        "ldr q16, pc+8",
-    ));
-
-    insns.push((
-        Inst::FpuStore32 {
-            rd: vreg(16),
-            mem: AMode::RegScaled(xreg(8), xreg(9), F32),
-            flags: MemFlags::trusted(),
-        },
-        "107929BC",
-        "str s16, [x8, x9, LSL #2]",
-    ));
-
-    insns.push((
-        Inst::FpuStore64 {
-            rd: vreg(16),
-            mem: AMode::RegScaled(xreg(8), xreg(9), F64),
-            flags: MemFlags::trusted(),
-        },
-        "107929FC",
-        "str d16, [x8, x9, LSL #3]",
-    ));
-
-    insns.push((
-        Inst::FpuStore128 {
-            rd: vreg(16),
-            mem: AMode::RegScaled(xreg(8), xreg(9), I128),
-            flags: MemFlags::trusted(),
-        },
-        "1079A93C",
-        "str q16, [x8, x9, LSL #4]",
-    ));
-
-    insns.push((
-        Inst::FpuLoadP64 {
-            rt: writable_vreg(0),
-            rt2: writable_vreg(31),
-            mem: PairAMode::SignedOffset(xreg(0), SImm7Scaled::zero(F64)),
-            flags: MemFlags::trusted(),
-        },
-        "007C406D",
-        "ldp d0, d31, [x0]",
-    ));
-
-    insns.push((
-        Inst::FpuLoadP64 {
-            rt: writable_vreg(19),
-            rt2: writable_vreg(11),
-            mem: PairAMode::PreIndexed(
-                writable_xreg(25),
-                SImm7Scaled::maybe_from_i64(-512, F64).unwrap(),
-            ),
-            flags: MemFlags::trusted(),
-        },
-        "332FE06D",
-        "ldp d19, d11, [x25, #-512]!",
-    ));
-
-    insns.push((
-        Inst::FpuLoadP64 {
-            rt: writable_vreg(7),
-            rt2: writable_vreg(20),
-            mem: PairAMode::PostIndexed(
-                writable_stack_reg(),
-                SImm7Scaled::maybe_from_i64(64, F64).unwrap(),
-            ),
-            flags: MemFlags::trusted(),
-        },
-        "E753C46C",
-        "ldp d7, d20, [sp], #64",
-    ));
-
-    insns.push((
-        Inst::FpuStoreP64 {
-            rt: vreg(4),
-            rt2: vreg(26),
-            mem: PairAMode::SignedOffset(
-                stack_reg(),
-                SImm7Scaled::maybe_from_i64(504, F64).unwrap(),
-            ),
-            flags: MemFlags::trusted(),
-        },
-        "E4EB1F6D",
-        "stp d4, d26, [sp, #504]",
-    ));
-
-    insns.push((
-        Inst::FpuStoreP64 {
-            rt: vreg(16),
-            rt2: vreg(8),
-            mem: PairAMode::PreIndexed(
-                writable_xreg(15),
-                SImm7Scaled::maybe_from_i64(48, F64).unwrap(),
-            ),
-            flags: MemFlags::trusted(),
-        },
-        "F021836D",
-        "stp d16, d8, [x15, #48]!",
-    ));
-
-    insns.push((
-        Inst::FpuStoreP64 {
-            rt: vreg(5),
-            rt2: vreg(6),
-            mem: PairAMode::PostIndexed(
-                writable_xreg(28),
-                SImm7Scaled::maybe_from_i64(-32, F64).unwrap(),
-            ),
-            flags: MemFlags::trusted(),
-        },
-        "851BBE6C",
-        "stp d5, d6, [x28], #-32",
-    ));
-
-    insns.push((
-        Inst::FpuLoadP128 {
-            rt: writable_vreg(0),
-            rt2: writable_vreg(17),
-            mem: PairAMode::SignedOffset(xreg(3), SImm7Scaled::zero(I8X16)),
-            flags: MemFlags::trusted(),
-        },
-        "604440AD",
-        "ldp q0, q17, [x3]",
-    ));
-
-    insns.push((
-        Inst::FpuLoadP128 {
-            rt: writable_vreg(29),
-            rt2: writable_vreg(9),
-            mem: PairAMode::PreIndexed(
-                writable_xreg(16),
-                SImm7Scaled::maybe_from_i64(-1024, I8X16).unwrap(),
-            ),
-            flags: MemFlags::trusted(),
-        },
-        "1D26E0AD",
-        "ldp q29, q9, [x16, #-1024]!",
-    ));
-
-    insns.push((
-        Inst::FpuLoadP128 {
-            rt: writable_vreg(10),
-            rt2: writable_vreg(20),
-            mem: PairAMode::PostIndexed(
-                writable_xreg(26),
-                SImm7Scaled::maybe_from_i64(256, I8X16).unwrap(),
-            ),
-            flags: MemFlags::trusted(),
-        },
-        "4A53C8AC",
-        "ldp q10, q20, [x26], #256",
-    ));
-
-    insns.push((
-        Inst::FpuStoreP128 {
-            rt: vreg(9),
-            rt2: vreg(31),
-            mem: PairAMode::SignedOffset(
-                stack_reg(),
-                SImm7Scaled::maybe_from_i64(1008, I8X16).unwrap(),
-            ),
-            flags: MemFlags::trusted(),
-        },
-        "E9FF1FAD",
-        "stp q9, q31, [sp, #1008]",
-    ));
-
-    insns.push((
-        Inst::FpuStoreP128 {
-            rt: vreg(27),
-            rt2: vreg(13),
-            mem: PairAMode::PreIndexed(
-                writable_stack_reg(),
-                SImm7Scaled::maybe_from_i64(-192, I8X16).unwrap(),
-            ),
-            flags: MemFlags::trusted(),
-        },
-        "FB37BAAD",
-        "stp q27, q13, [sp, #-192]!",
-    ));
-
-    insns.push((
-        Inst::FpuStoreP128 {
-            rt: vreg(18),
-            rt2: vreg(22),
-            mem: PairAMode::PostIndexed(
-                writable_xreg(13),
-                SImm7Scaled::maybe_from_i64(304, I8X16).unwrap(),
-            ),
-            flags: MemFlags::trusted(),
-        },
-        "B2D989AC",
-        "stp q18, q22, [x13], #304",
-    ));
-
-    insns.push((
-        Inst::LoadFpuConst64 {
-            rd: writable_vreg(16),
-            const_data: 1.0_f64.to_bits(),
-        },
-        "5000005C03000014000000000000F03F",
-        "ldr d16, pc+8 ; b 12 ; data.f64 1",
-    ));
-
-    insns.push((
-        Inst::LoadFpuConst128 {
-            rd: writable_vreg(5),
-            const_data: 0x0f0e0d0c0b0a09080706050403020100,
-        },
-        "4500009C05000014000102030405060708090A0B0C0D0E0F",
-        "ldr q5, pc+8 ; b 20 ; data.f128 0x0f0e0d0c0b0a09080706050403020100",
-    ));
-
-    insns.push((
-        Inst::FpuCSel32 {
-            rd: writable_vreg(1),
-            rn: vreg(2),
-            rm: vreg(3),
-            cond: Cond::Hi,
-        },
-        "418C231E",
-        "fcsel s1, s2, s3, hi",
-    ));
-
-    insns.push((
-        Inst::FpuCSel64 {
-            rd: writable_vreg(1),
-            rn: vreg(2),
-            rm: vreg(3),
-            cond: Cond::Eq,
-        },
-        "410C631E",
-        "fcsel d1, d2, d3, eq",
-    ));
-
-    insns.push((
-        Inst::FpuRound {
-            rd: writable_vreg(23),
-            rn: vreg(24),
-            op: FpuRoundMode::Minus32,
-        },
-        "1743251E",
-        "frintm s23, s24",
-    ));
-    insns.push((
-        Inst::FpuRound {
-            rd: writable_vreg(23),
-            rn: vreg(24),
-            op: FpuRoundMode::Minus64,
-        },
-        "1743651E",
-        "frintm d23, d24",
-    ));
-    insns.push((
-        Inst::FpuRound {
-            rd: writable_vreg(23),
-            rn: vreg(24),
-            op: FpuRoundMode::Plus32,
-        },
-        "17C3241E",
-        "frintp s23, s24",
-    ));
-    insns.push((
-        Inst::FpuRound {
-            rd: writable_vreg(23),
-            rn: vreg(24),
-            op: FpuRoundMode::Plus64,
-        },
-        "17C3641E",
-        "frintp d23, d24",
-    ));
-    insns.push((
-        Inst::FpuRound {
-            rd: writable_vreg(23),
-            rn: vreg(24),
-            op: FpuRoundMode::Zero32,
-        },
-        "17C3251E",
-        "frintz s23, s24",
-    ));
-    insns.push((
-        Inst::FpuRound {
-            rd: writable_vreg(23),
-            rn: vreg(24),
-            op: FpuRoundMode::Zero64,
-        },
-        "17C3651E",
-        "frintz d23, d24",
-    ));
-    insns.push((
-        Inst::FpuRound {
-            rd: writable_vreg(23),
-            rn: vreg(24),
-            op: FpuRoundMode::Nearest32,
-        },
-        "1743241E",
-        "frintn s23, s24",
-    ));
-    insns.push((
-        Inst::FpuRound {
-            rd: writable_vreg(23),
-            rn: vreg(24),
-            op: FpuRoundMode::Nearest64,
-        },
-        "1743641E",
-        "frintn d23, d24",
-    ));
-
-    insns.push((
-        Inst::AtomicRMWLoop {
-            ty: I16,
-            op: inst_common::AtomicRmwOp::Xor,
-        },
-        "3BFF5F487C031A4A3CFF1848B8FFFFB5",
-        "1: ldaxrh w27, [x25]; eor w28, w27, w26; stlxrh w24, w28, [x25]; cbnz w24, 1b",
-    ));
-    insns.push((
-        Inst::AtomicRMWLoop {
-            ty: I8,
-            op: inst_common::AtomicRmwOp::Add,
-        },
-        "3BFF5F087C031A0B3CFF1808B8FFFFB5",
-        "1: ldaxrb w27, [x25]; add w28, w27, w26; stlxrb w24, w28, [x25]; cbnz w24, 1b",
-    ));
-    insns.push((
-        Inst::AtomicRMWLoop {
-            ty: I32,
-            op: inst_common::AtomicRmwOp::Or,
-        },
-        "3BFF5F887C031A2A3CFF1888B8FFFFB5",
-        "1: ldaxr w27, [x25]; orr w28, w27, w26; stlxr w24, w28, [x25]; cbnz w24, 1b",
-    ));
-    insns.push((
-        Inst::AtomicRMWLoop {
-            ty: I64,
-            op: inst_common::AtomicRmwOp::And,
-        },
-        "3BFF5FC87C031A8A3CFF18C8B8FFFFB5",
-        "1: ldaxr x27, [x25]; and x28, x27, x26; stlxr w24, x28, [x25]; cbnz w24, 1b",
-    ));
-    insns.push((
-        Inst::AtomicRMWLoop {
-            ty: I8,
-            op: inst_common::AtomicRmwOp::Xchg,
-        },
-        "3BFF5F083AFF1808D8FFFFB5",
-        "1: ldaxrb w27, [x25]; stlxrb w24, w26, [x25]; cbnz w24, 1b",
-    ));
-    insns.push((
-        Inst::AtomicRMWLoop {
-            ty: I16,
-            op: inst_common::AtomicRmwOp::Nand,
-        },
-        "3BFF5F487C031A0AFC033C2A3CFF184898FFFFB5",
-        "1: ldaxrh w27, [x25]; and w28, w27, w26; mvn w28, w28; stlxrh w24, w28, [x25]; cbnz w24, 1b",
-    ));
-    insns.push((
-        Inst::AtomicRMWLoop {
-            ty: I32,
-            op: inst_common::AtomicRmwOp::Smin,
-        },
-        "3BFF5F887F031A6B7CB39A9A3CFF188898FFFFB5",
-        "1: ldaxr w27, [x25]; cmp w27, w26; csel w28, w27, w26, lt; stlxr w24, w28, [x25]; cbnz w24, 1b",
-    ));
-    insns.push((
-        Inst::AtomicRMWLoop {
-            ty: I64,
-            op: inst_common::AtomicRmwOp::Smax,
-        },
-        "3BFF5FC87F031AEB7CC39A9A3CFF18C898FFFFB5",
-        "1: ldaxr x27, [x25]; cmp x27, x26; csel x28, x27, x26, gt; stlxr w24, x28, [x25]; cbnz w24, 1b",
-    ));
-    insns.push((
-        Inst::AtomicRMWLoop {
-            ty: I8,
-            op: inst_common::AtomicRmwOp::Umin,
-        },
-        "3BFF5F087F031A6B7C339A9A3CFF180898FFFFB5",
-        "1: ldaxrb w27, [x25]; cmp w27, w26; csel w28, w27, w26, lo; stlxrb w24, w28, [x25]; cbnz w24, 1b",
-    ));
-    insns.push((
-        Inst::AtomicRMWLoop {
-            ty: I16,
-            op: inst_common::AtomicRmwOp::Umax,
-        },
-        "3BFF5F487F031A6B7C839A9A3CFF184898FFFFB5",
-        "1: ldaxrh w27, [x25]; cmp w27, w26; csel w28, w27, w26, hi; stlxrh w24, w28, [x25]; cbnz w24, 1b",
-    ));
-
-    insns.push((
-        Inst::AtomicRMW {
-            ty: I8,
-            op: AtomicRMWOp::Add,
-            rs: xreg(1),
-            rt: writable_xreg(2),
-            rn: xreg(3),
-        },
-        "6200E138",
-        "ldaddalb w1, w2, [x3]",
-    ));
-    insns.push((
-        Inst::AtomicRMW {
-            ty: I16,
-            op: AtomicRMWOp::Add,
-            rs: xreg(4),
-            rt: writable_xreg(5),
-            rn: xreg(6),
-        },
-        "C500E478",
-        "ldaddalh w4, w5, [x6]",
-    ));
-    insns.push((
-        Inst::AtomicRMW {
-            ty: I32,
-            op: AtomicRMWOp::Add,
-            rs: xreg(7),
-            rt: writable_xreg(8),
-            rn: xreg(9),
-        },
-        "2801E7B8",
-        "ldaddal w7, w8, [x9]",
-    ));
-    insns.push((
-        Inst::AtomicRMW {
-            ty: I64,
-            op: AtomicRMWOp::Add,
-            rs: xreg(10),
-            rt: writable_xreg(11),
-            rn: xreg(12),
-        },
-        "8B01EAF8",
-        "ldaddal x10, x11, [x12]",
-    ));
-    insns.push((
-        Inst::AtomicRMW {
-            ty: I8,
-            op: AtomicRMWOp::Clr,
-            rs: xreg(13),
-            rt: writable_xreg(14),
-            rn: xreg(15),
-        },
-        "EE11ED38",
-        "ldclralb w13, w14, [x15]",
-    ));
-    insns.push((
-        Inst::AtomicRMW {
-            ty: I16,
-            op: AtomicRMWOp::Clr,
-            rs: xreg(16),
-            rt: writable_xreg(17),
-            rn: xreg(18),
-        },
-        "5112F078",
-        "ldclralh w16, w17, [x18]",
-    ));
-    insns.push((
-        Inst::AtomicRMW {
-            ty: I32,
-            op: AtomicRMWOp::Clr,
-            rs: xreg(19),
-            rt: writable_xreg(20),
-            rn: xreg(21),
-        },
-        "B412F3B8",
-        "ldclral w19, w20, [x21]",
-    ));
-    insns.push((
-        Inst::AtomicRMW {
-            ty: I64,
-            op: AtomicRMWOp::Clr,
-            rs: xreg(22),
-            rt: writable_xreg(23),
-            rn: xreg(24),
-        },
-        "1713F6F8",
-        "ldclral x22, x23, [x24]",
-    ));
-    insns.push((
-        Inst::AtomicRMW {
-            ty: I8,
-            op: AtomicRMWOp::Eor,
-            rs: xreg(25),
-            rt: writable_xreg(26),
-            rn: xreg(27),
-        },
-        "7A23F938",
-        "ldeoralb w25, w26, [x27]",
-    ));
-    insns.push((
-        Inst::AtomicRMW {
-            ty: I16,
-            op: AtomicRMWOp::Eor,
-            rs: xreg(28),
-            rt: writable_xreg(29),
-            rn: xreg(30),
-        },
-        "DD23FC78",
-        "ldeoralh w28, fp, [lr]",
-    ));
-    insns.push((
-        Inst::AtomicRMW {
-            ty: I32,
-            op: AtomicRMWOp::Eor,
-            rs: xreg(29),
-            rt: writable_xreg(28),
-            rn: xreg(27),
-        },
-        "7C23FDB8",
-        "ldeoral fp, w28, [x27]",
-    ));
-    insns.push((
-        Inst::AtomicRMW {
-            ty: I64,
-            op: AtomicRMWOp::Eor,
-            rs: xreg(26),
-            rt: writable_xreg(25),
-            rn: xreg(24),
-        },
-        "1923FAF8",
-        "ldeoral x26, x25, [x24]",
-    ));
-    insns.push((
-        Inst::AtomicRMW {
-            ty: I8,
-            op: AtomicRMWOp::Set,
-            rs: xreg(23),
-            rt: writable_xreg(22),
-            rn: xreg(21),
-        },
-        "B632F738",
-        "ldsetalb w23, w22, [x21]",
-    ));
-    insns.push((
-        Inst::AtomicRMW {
-            ty: I16,
-            op: AtomicRMWOp::Set,
-            rs: xreg(20),
-            rt: writable_xreg(19),
-            rn: xreg(18),
-        },
-        "5332F478",
-        "ldsetalh w20, w19, [x18]",
-    ));
-    insns.push((
-        Inst::AtomicRMW {
-            ty: I32,
-            op: AtomicRMWOp::Set,
-            rs: xreg(17),
-            rt: writable_xreg(16),
-            rn: xreg(15),
-        },
-        "F031F1B8",
-        "ldsetal w17, w16, [x15]",
-    ));
-    insns.push((
-        Inst::AtomicRMW {
-            ty: I64,
-            op: AtomicRMWOp::Set,
-            rs: xreg(14),
-            rt: writable_xreg(13),
-            rn: xreg(12),
-        },
-        "8D31EEF8",
-        "ldsetal x14, x13, [x12]",
-    ));
-    insns.push((
-        Inst::AtomicRMW {
-            ty: I8,
-            op: AtomicRMWOp::Smax,
-            rs: xreg(11),
-            rt: writable_xreg(10),
-            rn: xreg(9),
-        },
-        "2A41EB38",
-        "ldsmaxalb w11, w10, [x9]",
-    ));
-    insns.push((
-        Inst::AtomicRMW {
-            ty: I16,
-            op: AtomicRMWOp::Smax,
-            rs: xreg(8),
-            rt: writable_xreg(7),
-            rn: xreg(6),
-        },
-        "C740E878",
-        "ldsmaxalh w8, w7, [x6]",
-    ));
-    insns.push((
-        Inst::AtomicRMW {
-            ty: I32,
-            op: AtomicRMWOp::Smax,
-            rs: xreg(5),
-            rt: writable_xreg(4),
-            rn: xreg(3),
-        },
-        "6440E5B8",
-        "ldsmaxal w5, w4, [x3]",
-    ));
-    insns.push((
-        Inst::AtomicRMW {
-            ty: I64,
-            op: AtomicRMWOp::Smax,
-            rs: xreg(2),
-            rt: writable_xreg(1),
-            rn: xreg(0),
-        },
-        "0140E2F8",
-        "ldsmaxal x2, x1, [x0]",
-    ));
-    insns.push((
-        Inst::AtomicRMW {
-            ty: I8,
-            op: AtomicRMWOp::Smin,
-            rs: xreg(1),
-            rt: writable_xreg(2),
-            rn: xreg(3),
-        },
-        "6250E138",
-        "ldsminalb w1, w2, [x3]",
-    ));
-    insns.push((
-        Inst::AtomicRMW {
-            ty: I16,
-            op: AtomicRMWOp::Smin,
-            rs: xreg(4),
-            rt: writable_xreg(5),
-            rn: xreg(6),
-        },
-        "C550E478",
-        "ldsminalh w4, w5, [x6]",
-    ));
-    insns.push((
-        Inst::AtomicRMW {
-            ty: I32,
-            op: AtomicRMWOp::Smin,
-            rs: xreg(7),
-            rt: writable_xreg(8),
-            rn: xreg(9),
-        },
-        "2851E7B8",
-        "ldsminal w7, w8, [x9]",
-    ));
-    insns.push((
-        Inst::AtomicRMW {
-            ty: I64,
-            op: AtomicRMWOp::Smin,
-            rs: xreg(10),
-            rt: writable_xreg(11),
-            rn: xreg(12),
-        },
-        "8B51EAF8",
-        "ldsminal x10, x11, [x12]",
-    ));
-    insns.push((
-        Inst::AtomicRMW {
-            ty: I8,
-            op: AtomicRMWOp::Umax,
-            rs: xreg(13),
-            rt: writable_xreg(14),
-            rn: xreg(15),
-        },
-        "EE61ED38",
-        "ldumaxalb w13, w14, [x15]",
-    ));
-    insns.push((
-        Inst::AtomicRMW {
-            ty: I16,
-            op: AtomicRMWOp::Umax,
-            rs: xreg(16),
-            rt: writable_xreg(17),
-            rn: xreg(18),
-        },
-        "5162F078",
-        "ldumaxalh w16, w17, [x18]",
-    ));
-    insns.push((
-        Inst::AtomicRMW {
-            ty: I32,
-            op: AtomicRMWOp::Umax,
-            rs: xreg(19),
-            rt: writable_xreg(20),
-            rn: xreg(21),
-        },
-        "B462F3B8",
-        "ldumaxal w19, w20, [x21]",
-    ));
-    insns.push((
-        Inst::AtomicRMW {
-            ty: I64,
-            op: AtomicRMWOp::Umax,
-            rs: xreg(22),
-            rt: writable_xreg(23),
-            rn: xreg(24),
-        },
-        "1763F6F8",
-        "ldumaxal x22, x23, [x24]",
-    ));
-    insns.push((
-        Inst::AtomicRMW {
-            ty: I8,
-            op: AtomicRMWOp::Umin,
-            rs: xreg(16),
-            rt: writable_xreg(17),
-            rn: xreg(18),
-        },
-        "5172F038",
-        "lduminalb w16, w17, [x18]",
-    ));
-    insns.push((
-        Inst::AtomicRMW {
-            ty: I16,
-            op: AtomicRMWOp::Umin,
-            rs: xreg(19),
-            rt: writable_xreg(20),
-            rn: xreg(21),
-        },
-        "B472F378",
-        "lduminalh w19, w20, [x21]",
-    ));
-    insns.push((
-        Inst::AtomicRMW {
-            ty: I32,
-            op: AtomicRMWOp::Umin,
-            rs: xreg(22),
-            rt: writable_xreg(23),
-            rn: xreg(24),
-        },
-        "1773F6B8",
-        "lduminal w22, w23, [x24]",
-    ));
-    insns.push((
-        Inst::AtomicRMW {
-            ty: I64,
-            op: AtomicRMWOp::Umin,
-            rs: xreg(25),
-            rt: writable_xreg(26),
-            rn: xreg(27),
-        },
-        "7A73F9F8",
-        "lduminal x25, x26, [x27]",
-    ));
-
-    insns.push((
-        Inst::AtomicCAS {
-            rs: writable_xreg(28),
-            rt: xreg(20),
-            rn: xreg(10),
-            ty: I8,
-        },
-        "54FDFC08",
-        "casalb w28, w20, [x10]",
-    ));
-    insns.push((
-        Inst::AtomicCAS {
-            rs: writable_xreg(2),
-            rt: xreg(19),
-            rn: xreg(23),
-            ty: I16,
-        },
-        "F3FEE248",
-        "casalh w2, w19, [x23]",
-    ));
-    insns.push((
-        Inst::AtomicCAS {
-            rs: writable_xreg(0),
-            rt: zero_reg(),
-            rn: stack_reg(),
-            ty: I32,
-        },
-        "FFFFE088",
-        "casal w0, wzr, [sp]",
-    ));
-    insns.push((
-        Inst::AtomicCAS {
-            rs: writable_xreg(7),
-            rt: xreg(15),
-            rn: xreg(27),
-            ty: I64,
-        },
-        "6FFFE7C8",
-        "casal x7, x15, [x27]",
-    ));
-    insns.push((
-        Inst::AtomicCASLoop {
-            ty: I8,
-        },
-        "3BFF5F087F033AEB610000543CFF180898FFFFB5",
-        "atomically { compare-and-swap(8_bits_at_[x25], x26 -> x28), x27 = old_value_at_[x25]; x24 = trash }"
-    ));
-
-    insns.push((
-        Inst::AtomicCASLoop {
-            ty: I16,
-        },
-        "3BFF5F487F233AEB610000543CFF184898FFFFB5",
-        "atomically { compare-and-swap(16_bits_at_[x25], x26 -> x28), x27 = old_value_at_[x25]; x24 = trash }"
-    ));
-
-    insns.push((
-        Inst::AtomicCASLoop {
-            ty: I32,
-        },
-        "3BFF5F887F031AEB610000543CFF188898FFFFB5",
-        "atomically { compare-and-swap(32_bits_at_[x25], x26 -> x28), x27 = old_value_at_[x25]; x24 = trash }"
-    ));
-
-    insns.push((
-        Inst::AtomicCASLoop {
-            ty: I64,
-        },
-        "3BFF5FC87F031AEB610000543CFF18C898FFFFB5",
-        "atomically { compare-and-swap(64_bits_at_[x25], x26 -> x28), x27 = old_value_at_[x25]; x24 = trash }"
-    ));
-
-    insns.push((
-        Inst::LoadAcquire {
-            access_ty: I8,
-            rt: writable_xreg(7),
-            rn: xreg(28),
-        },
-        "87FFDF08",
-        "ldarb w7, [x28]",
-    ));
-
-    insns.push((
-        Inst::LoadAcquire {
-            access_ty: I16,
-            rt: writable_xreg(2),
-            rn: xreg(3),
-        },
-        "62FCDF48",
-        "ldarh w2, [x3]",
-    ));
-
-    insns.push((
-        Inst::LoadAcquire {
-            access_ty: I32,
-            rt: writable_xreg(15),
-            rn: xreg(0),
-        },
-        "0FFCDF88",
-        "ldar w15, [x0]",
-    ));
-
-    insns.push((
-        Inst::LoadAcquire {
-            access_ty: I64,
-            rt: writable_xreg(28),
-            rn: xreg(7),
-        },
-        "FCFCDFC8",
-        "ldar x28, [x7]",
-    ));
-
-    insns.push((
-        Inst::StoreRelease {
-            access_ty: I8,
-            rt: xreg(7),
-            rn: xreg(28),
-        },
-        "87FF9F08",
-        "stlrb w7, [x28]",
-    ));
-
-    insns.push((
-        Inst::StoreRelease {
-            access_ty: I16,
-            rt: xreg(2),
-            rn: xreg(3),
-        },
-        "62FC9F48",
-        "stlrh w2, [x3]",
-    ));
-
-    insns.push((
-        Inst::StoreRelease {
-            access_ty: I32,
-            rt: xreg(15),
-            rn: xreg(0),
-        },
-        "0FFC9F88",
-        "stlr w15, [x0]",
-    ));
-
-    insns.push((
-        Inst::StoreRelease {
-            access_ty: I64,
-            rt: xreg(28),
-            rn: xreg(7),
-        },
-        "FCFC9FC8",
-        "stlr x28, [x7]",
-    ));
-
-    insns.push((Inst::Fence {}, "BF3B03D5", "dmb ish"));
-
-    let flags = settings::Flags::new(settings::builder());
-    let rru = create_reg_universe(&flags);
-    let emit_info = EmitInfo::new(flags);
-    for (insn, expected_encoding, expected_printing) in insns {
-        println!(
-            "AArch64: {:?}, {}, {}",
-            insn, expected_encoding, expected_printing
-        );
-
-        // Check the printed text is as expected.
-        let actual_printing = insn.show_rru(Some(&rru));
-        assert_eq!(expected_printing, actual_printing);
-
-        let mut buffer = MachBuffer::new();
-        insn.emit(&mut buffer, &emit_info, &mut Default::default());
-        let buffer = buffer.finish();
-        let actual_encoding = &buffer.stringify_code_bytes();
-        assert_eq!(expected_encoding, actual_encoding);
-    }
-}
-
-#[test]
-fn test_cond_invert() {
-    for cond in vec![
-        Cond::Eq,
-        Cond::Ne,
-        Cond::Hs,
-        Cond::Lo,
-        Cond::Mi,
-        Cond::Pl,
-        Cond::Vs,
-        Cond::Vc,
-        Cond::Hi,
-        Cond::Ls,
-        Cond::Ge,
-        Cond::Lt,
-        Cond::Gt,
-        Cond::Le,
-        Cond::Al,
-        Cond::Nv,
-    ]
-    .into_iter()
-    {
-        assert_eq!(cond.invert().invert(), cond);
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/inst/imms.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/inst/imms.rs
deleted file mode 100644
index beed2f40d..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/inst/imms.rs
+++ /dev/null
@@ -1,1257 +0,0 @@
-//! AArch64 ISA definitions: immediate constants.
-
-// Some variants are never constructed, but we still want them as options in the future.
-#[allow(dead_code)]
-use crate::ir::types::*;
-use crate::ir::Type;
-use crate::isa::aarch64::inst::{OperandSize, ScalarSize};
-
-use regalloc::{PrettyPrint, RealRegUniverse};
-
-use core::convert::TryFrom;
-use std::string::String;
-
-/// An immediate that represents the NZCV flags.
-#[derive(Clone, Copy, Debug)]
-pub struct NZCV {
-    /// The negative condition flag.
-    n: bool,
-    /// The zero condition flag.
-    z: bool,
-    /// The carry condition flag.
-    c: bool,
-    /// The overflow condition flag.
-    v: bool,
-}
-
-impl NZCV {
-    pub fn new(n: bool, z: bool, c: bool, v: bool) -> NZCV {
-        NZCV { n, z, c, v }
-    }
-
-    /// Bits for encoding.
-    pub fn bits(&self) -> u32 {
-        (u32::from(self.n) << 3)
-            | (u32::from(self.z) << 2)
-            | (u32::from(self.c) << 1)
-            | u32::from(self.v)
-    }
-}
-
-/// An unsigned 5-bit immediate.
-#[derive(Clone, Copy, Debug)]
-pub struct UImm5 {
-    /// The value.
-    value: u8,
-}
-
-impl UImm5 {
-    pub fn maybe_from_u8(value: u8) -> Option<UImm5> {
-        if value < 32 {
-            Some(UImm5 { value })
-        } else {
-            None
-        }
-    }
-
-    /// Bits for encoding.
-    pub fn bits(&self) -> u32 {
-        u32::from(self.value)
-    }
-}
-
-/// A signed, scaled 7-bit offset.
-#[derive(Clone, Copy, Debug)]
-pub struct SImm7Scaled {
-    /// The value.
-    pub value: i16,
-    /// multiplied by the size of this type
-    pub scale_ty: Type,
-}
-
-impl SImm7Scaled {
-    /// Create a SImm7Scaled from a raw offset and the known scale type, if
-    /// possible.
-    pub fn maybe_from_i64(value: i64, scale_ty: Type) -> Option<SImm7Scaled> {
-        assert!(scale_ty == I64 || scale_ty == I32 || scale_ty == F64 || scale_ty == I8X16);
-        let scale = scale_ty.bytes();
-        assert!(scale.is_power_of_two());
-        let scale = i64::from(scale);
-        let upper_limit = 63 * scale;
-        let lower_limit = -(64 * scale);
-        if value >= lower_limit && value <= upper_limit && (value & (scale - 1)) == 0 {
-            Some(SImm7Scaled {
-                value: i16::try_from(value).unwrap(),
-                scale_ty,
-            })
-        } else {
-            None
-        }
-    }
-
-    /// Create a zero immediate of this format.
-    pub fn zero(scale_ty: Type) -> SImm7Scaled {
-        SImm7Scaled { value: 0, scale_ty }
-    }
-
-    /// Bits for encoding.
-    pub fn bits(&self) -> u32 {
-        let ty_bytes: i16 = self.scale_ty.bytes() as i16;
-        let scaled: i16 = self.value / ty_bytes;
-        assert!(scaled <= 63 && scaled >= -64);
-        let scaled: i8 = scaled as i8;
-        let encoded: u32 = scaled as u32;
-        encoded & 0x7f
-    }
-}
-
-#[derive(Clone, Copy, Debug)]
-pub struct FPULeftShiftImm {
-    pub amount: u8,
-    pub lane_size_in_bits: u8,
-}
-
-impl FPULeftShiftImm {
-    pub fn maybe_from_u8(amount: u8, lane_size_in_bits: u8) -> Option<Self> {
-        debug_assert!(lane_size_in_bits == 32 || lane_size_in_bits == 64);
-        if amount < lane_size_in_bits {
-            Some(Self {
-                amount,
-                lane_size_in_bits,
-            })
-        } else {
-            None
-        }
-    }
-
-    pub fn enc(&self) -> u32 {
-        debug_assert!(self.lane_size_in_bits.is_power_of_two());
-        debug_assert!(self.lane_size_in_bits > self.amount);
-        // The encoding of the immediate follows the table below,
-        // where xs encode the shift amount.
-        //
-        // | lane_size_in_bits | encoding |
-        // +------------------------------+
-        // | 8                 | 0001xxx  |
-        // | 16                | 001xxxx  |
-        // | 32                | 01xxxxx  |
-        // | 64                | 1xxxxxx  |
-        //
-        // The highest one bit is represented by `lane_size_in_bits`. Since
-        // `lane_size_in_bits` is a power of 2 and `amount` is less
-        // than `lane_size_in_bits`, they can be ORed
-        // together to produced the encoded value.
-        u32::from(self.lane_size_in_bits | self.amount)
-    }
-}
-
-#[derive(Clone, Copy, Debug)]
-pub struct FPURightShiftImm {
-    pub amount: u8,
-    pub lane_size_in_bits: u8,
-}
-
-impl FPURightShiftImm {
-    pub fn maybe_from_u8(amount: u8, lane_size_in_bits: u8) -> Option<Self> {
-        debug_assert!(lane_size_in_bits == 32 || lane_size_in_bits == 64);
-        if amount > 0 && amount <= lane_size_in_bits {
-            Some(Self {
-                amount,
-                lane_size_in_bits,
-            })
-        } else {
-            None
-        }
-    }
-
-    pub fn enc(&self) -> u32 {
-        debug_assert_ne!(0, self.amount);
-        // The encoding of the immediate follows the table below,
-        // where xs encodes the negated shift amount.
-        //
-        // | lane_size_in_bits | encoding |
-        // +------------------------------+
-        // | 8                 | 0001xxx  |
-        // | 16                | 001xxxx  |
-        // | 32                | 01xxxxx  |
-        // | 64                | 1xxxxxx  |
-        //
-        // The shift amount is negated such that a shift ammount
-        // of 1 (in 64-bit) is encoded as 0b111111 and a shift
-        // amount of 64 is encoded as 0b000000,
-        // in the bottom 6 bits.
-        u32::from((self.lane_size_in_bits * 2) - self.amount)
-    }
-}
-
-/// a 9-bit signed offset.
-#[derive(Clone, Copy, Debug)]
-pub struct SImm9 {
-    /// The value.
-    pub value: i16,
-}
-
-impl SImm9 {
-    /// Create a signed 9-bit offset from a full-range value, if possible.
-    pub fn maybe_from_i64(value: i64) -> Option<SImm9> {
-        if value >= -256 && value <= 255 {
-            Some(SImm9 {
-                value: value as i16,
-            })
-        } else {
-            None
-        }
-    }
-
-    /// Create a zero immediate of this format.
-    pub fn zero() -> SImm9 {
-        SImm9 { value: 0 }
-    }
-
-    /// Bits for encoding.
-    pub fn bits(&self) -> u32 {
-        (self.value as u32) & 0x1ff
-    }
-
-    /// Signed value of immediate.
-    pub fn value(&self) -> i32 {
-        self.value as i32
-    }
-}
-
-/// An unsigned, scaled 12-bit offset.
-#[derive(Clone, Copy, Debug)]
-pub struct UImm12Scaled {
-    /// The value.
-    pub value: u16,
-    /// multiplied by the size of this type
-    pub scale_ty: Type,
-}
-
-impl UImm12Scaled {
-    /// Create a UImm12Scaled from a raw offset and the known scale type, if
-    /// possible.
-    pub fn maybe_from_i64(value: i64, scale_ty: Type) -> Option<UImm12Scaled> {
-        // Ensure the type is at least one byte.
-        let scale_ty = if scale_ty == B1 { B8 } else { scale_ty };
-
-        let scale = scale_ty.bytes();
-        assert!(scale.is_power_of_two());
-        let scale = scale as i64;
-        let limit = 4095 * scale;
-        if value >= 0 && value <= limit && (value & (scale - 1)) == 0 {
-            Some(UImm12Scaled {
-                value: value as u16,
-                scale_ty,
-            })
-        } else {
-            None
-        }
-    }
-
-    /// Create a zero immediate of this format.
-    pub fn zero(scale_ty: Type) -> UImm12Scaled {
-        UImm12Scaled { value: 0, scale_ty }
-    }
-
-    /// Encoded bits.
-    pub fn bits(&self) -> u32 {
-        (self.value as u32 / self.scale_ty.bytes()) & 0xfff
-    }
-
-    /// Value after scaling.
-    pub fn value(&self) -> u32 {
-        self.value as u32
-    }
-
-    /// The value type which is the scaling base.
-    pub fn scale_ty(&self) -> Type {
-        self.scale_ty
-    }
-}
-
-/// A shifted immediate value in 'imm12' format: supports 12 bits, shifted
-/// left by 0 or 12 places.
-#[derive(Copy, Clone, Debug)]
-pub struct Imm12 {
-    /// The immediate bits.
-    pub bits: u16,
-    /// Whether the immediate bits are shifted left by 12 or not.
-    pub shift12: bool,
-}
-
-impl Imm12 {
-    /// Compute a Imm12 from raw bits, if possible.
-    pub fn maybe_from_u64(val: u64) -> Option<Imm12> {
-        if val == 0 {
-            Some(Imm12 {
-                bits: 0,
-                shift12: false,
-            })
-        } else if val < 0xfff {
-            Some(Imm12 {
-                bits: val as u16,
-                shift12: false,
-            })
-        } else if val < 0xfff_000 && (val & 0xfff == 0) {
-            Some(Imm12 {
-                bits: (val >> 12) as u16,
-                shift12: true,
-            })
-        } else {
-            None
-        }
-    }
-
-    /// Create a zero immediate of this format.
-    pub fn zero() -> Self {
-        Imm12 {
-            bits: 0,
-            shift12: false,
-        }
-    }
-
-    /// Bits for 2-bit "shift" field in e.g. AddI.
-    pub fn shift_bits(&self) -> u32 {
-        if self.shift12 {
-            0b01
-        } else {
-            0b00
-        }
-    }
-
-    /// Bits for 12-bit "imm" field in e.g. AddI.
-    pub fn imm_bits(&self) -> u32 {
-        self.bits as u32
-    }
-}
-
-/// An immediate for logical instructions.
-#[derive(Copy, Clone, Debug, PartialEq)]
-pub struct ImmLogic {
-    /// The actual value.
-    value: u64,
-    /// `N` flag.
-    pub n: bool,
-    /// `S` field: element size and element bits.
-    pub r: u8,
-    /// `R` field: rotate amount.
-    pub s: u8,
-    /// Was this constructed for a 32-bit or 64-bit instruction?
-    pub size: OperandSize,
-}
-
-impl ImmLogic {
-    /// Compute an ImmLogic from raw bits, if possible.
-    pub fn maybe_from_u64(value: u64, ty: Type) -> Option<ImmLogic> {
-        // Note: This function is a port of VIXL's Assembler::IsImmLogical.
-
-        if ty != I64 && ty != I32 {
-            return None;
-        }
-        let operand_size = OperandSize::from_ty(ty);
-
-        let original_value = value;
-
-        let value = if ty == I32 {
-            // To handle 32-bit logical immediates, the very easiest thing is to repeat
-            // the input value twice to make a 64-bit word. The correct encoding of that
-            // as a logical immediate will also be the correct encoding of the 32-bit
-            // value.
-
-            // Avoid making the assumption that the most-significant 32 bits are zero by
-            // shifting the value left and duplicating it.
-            let value = value << 32;
-            value | value >> 32
-        } else {
-            value
-        };
-
-        // Logical immediates are encoded using parameters n, imm_s and imm_r using
-        // the following table:
-        //
-        //    N   imms    immr    size        S             R
-        //    1  ssssss  rrrrrr    64    UInt(ssssss)  UInt(rrrrrr)
-        //    0  0sssss  xrrrrr    32    UInt(sssss)   UInt(rrrrr)
-        //    0  10ssss  xxrrrr    16    UInt(ssss)    UInt(rrrr)
-        //    0  110sss  xxxrrr     8    UInt(sss)     UInt(rrr)
-        //    0  1110ss  xxxxrr     4    UInt(ss)      UInt(rr)
-        //    0  11110s  xxxxxr     2    UInt(s)       UInt(r)
-        // (s bits must not be all set)
-        //
-        // A pattern is constructed of size bits, where the least significant S+1 bits
-        // are set. The pattern is rotated right by R, and repeated across a 32 or
-        // 64-bit value, depending on destination register width.
-        //
-        // Put another way: the basic format of a logical immediate is a single
-        // contiguous stretch of 1 bits, repeated across the whole word at intervals
-        // given by a power of 2. To identify them quickly, we first locate the
-        // lowest stretch of 1 bits, then the next 1 bit above that; that combination
-        // is different for every logical immediate, so it gives us all the
-        // information we need to identify the only logical immediate that our input
-        // could be, and then we simply check if that's the value we actually have.
-        //
-        // (The rotation parameter does give the possibility of the stretch of 1 bits
-        // going 'round the end' of the word. To deal with that, we observe that in
-        // any situation where that happens the bitwise NOT of the value is also a
-        // valid logical immediate. So we simply invert the input whenever its low bit
-        // is set, and then we know that the rotated case can't arise.)
-        let (value, inverted) = if value & 1 == 1 {
-            (!value, true)
-        } else {
-            (value, false)
-        };
-
-        if value == 0 {
-            return None;
-        }
-
-        // The basic analysis idea: imagine our input word looks like this.
-        //
-        //    0011111000111110001111100011111000111110001111100011111000111110
-        //                                                          c  b    a
-        //                                                          |<--d-->|
-        //
-        // We find the lowest set bit (as an actual power-of-2 value, not its index)
-        // and call it a. Then we add a to our original number, which wipes out the
-        // bottommost stretch of set bits and replaces it with a 1 carried into the
-        // next zero bit. Then we look for the new lowest set bit, which is in
-        // position b, and subtract it, so now our number is just like the original
-        // but with the lowest stretch of set bits completely gone. Now we find the
-        // lowest set bit again, which is position c in the diagram above. Then we'll
-        // measure the distance d between bit positions a and c (using CLZ), and that
-        // tells us that the only valid logical immediate that could possibly be equal
-        // to this number is the one in which a stretch of bits running from a to just
-        // below b is replicated every d bits.
-        fn lowest_set_bit(value: u64) -> u64 {
-            let bit = value.trailing_zeros();
-            1u64.checked_shl(bit).unwrap_or(0)
-        }
-        let a = lowest_set_bit(value);
-        assert_ne!(0, a);
-        let value_plus_a = value.wrapping_add(a);
-        let b = lowest_set_bit(value_plus_a);
-        let value_plus_a_minus_b = value_plus_a - b;
-        let c = lowest_set_bit(value_plus_a_minus_b);
-
-        let (d, clz_a, out_n, mask) = if c != 0 {
-            // The general case, in which there is more than one stretch of set bits.
-            // Compute the repeat distance d, and set up a bitmask covering the basic
-            // unit of repetition (i.e. a word with the bottom d bits set). Also, in all
-            // of these cases the N bit of the output will be zero.
-            let clz_a = a.leading_zeros();
-            let clz_c = c.leading_zeros();
-            let d = clz_a - clz_c;
-            let mask = (1 << d) - 1;
-            (d, clz_a, 0, mask)
-        } else {
-            (64, a.leading_zeros(), 1, u64::max_value())
-        };
-
-        // If the repeat period d is not a power of two, it can't be encoded.
-        if !d.is_power_of_two() {
-            return None;
-        }
-
-        if ((b.wrapping_sub(a)) & !mask) != 0 {
-            // If the bit stretch (b - a) does not fit within the mask derived from the
-            // repeat period, then fail.
-            return None;
-        }
-
-        // The only possible option is b - a repeated every d bits. Now we're going to
-        // actually construct the valid logical immediate derived from that
-        // specification, and see if it equals our original input.
-        //
-        // To repeat a value every d bits, we multiply it by a number of the form
-        // (1 + 2^d + 2^(2d) + ...), i.e. 0x0001000100010001 or similar. These can
-        // be derived using a table lookup on CLZ(d).
-        const MULTIPLIERS: [u64; 6] = [
-            0x0000000000000001,
-            0x0000000100000001,
-            0x0001000100010001,
-            0x0101010101010101,
-            0x1111111111111111,
-            0x5555555555555555,
-        ];
-        let multiplier = MULTIPLIERS[(u64::from(d).leading_zeros() - 57) as usize];
-        let candidate = b.wrapping_sub(a) * multiplier;
-
-        if value != candidate {
-            // The candidate pattern doesn't match our input value, so fail.
-            return None;
-        }
-
-        // We have a match! This is a valid logical immediate, so now we have to
-        // construct the bits and pieces of the instruction encoding that generates
-        // it.
-
-        // Count the set bits in our basic stretch. The special case of clz(0) == -1
-        // makes the answer come out right for stretches that reach the very top of
-        // the word (e.g. numbers like 0xffffc00000000000).
-        let clz_b = if b == 0 {
-            u32::max_value() // -1
-        } else {
-            b.leading_zeros()
-        };
-        let s = clz_a.wrapping_sub(clz_b);
-
-        // Decide how many bits to rotate right by, to put the low bit of that basic
-        // stretch in position a.
-        let (s, r) = if inverted {
-            // If we inverted the input right at the start of this function, here's
-            // where we compensate: the number of set bits becomes the number of clear
-            // bits, and the rotation count is based on position b rather than position
-            // a (since b is the location of the 'lowest' 1 bit after inversion).
-            // Need wrapping for when clz_b is max_value() (for when b == 0).
-            (d - s, clz_b.wrapping_add(1) & (d - 1))
-        } else {
-            (s, (clz_a + 1) & (d - 1))
-        };
-
-        // Now we're done, except for having to encode the S output in such a way that
-        // it gives both the number of set bits and the length of the repeated
-        // segment. The s field is encoded like this:
-        //
-        //     imms    size        S
-        //    ssssss    64    UInt(ssssss)
-        //    0sssss    32    UInt(sssss)
-        //    10ssss    16    UInt(ssss)
-        //    110sss     8    UInt(sss)
-        //    1110ss     4    UInt(ss)
-        //    11110s     2    UInt(s)
-        //
-        // So we 'or' (2 * -d) with our computed s to form imms.
-        let s = ((d * 2).wrapping_neg() | (s - 1)) & 0x3f;
-        debug_assert!(u8::try_from(r).is_ok());
-        debug_assert!(u8::try_from(s).is_ok());
-        Some(ImmLogic {
-            value: original_value,
-            n: out_n != 0,
-            r: r as u8,
-            s: s as u8,
-            size: operand_size,
-        })
-    }
-
-    /// Returns bits ready for encoding: (N:1, R:6, S:6)
-    pub fn enc_bits(&self) -> u32 {
-        ((self.n as u32) << 12) | ((self.r as u32) << 6) | (self.s as u32)
-    }
-
-    /// Returns the value that this immediate represents.
-    pub fn value(&self) -> u64 {
-        self.value
-    }
-
-    /// Return an immediate for the bitwise-inverted value.
-    pub fn invert(&self) -> ImmLogic {
-        // For every ImmLogical immediate, the inverse can also be encoded.
-        Self::maybe_from_u64(!self.value, self.size.to_ty()).unwrap()
-    }
-
-    /// This provides a safe(ish) way to avoid the costs of `maybe_from_u64` when we want to
-    /// encode a constant that we know at compiler-build time.  It constructs an `ImmLogic` from
-    /// the fields `n`, `r`, `s` and `size`, but in a debug build, checks that `value_to_check`
-    /// corresponds to those four fields.  The intention is that, in a non-debug build, this
-    /// reduces to something small enough that it will be a candidate for inlining.
-    pub fn from_n_r_s(value_to_check: u64, n: bool, r: u8, s: u8, size: OperandSize) -> Self {
-        // Construct it from the components we got given.
-        let imml = Self {
-            value: value_to_check,
-            n,
-            r,
-            s,
-            size,
-        };
-
-        // In debug mode, check that `n`/`r`/`s` are correct, given `value` and `size`.
-        debug_assert!(match ImmLogic::maybe_from_u64(
-            value_to_check,
-            if size == OperandSize::Size64 {
-                I64
-            } else {
-                I32
-            }
-        ) {
-            None => false, // fail: `value` is unrepresentable
-            Some(imml_check) => imml_check == imml,
-        });
-
-        imml
-    }
-}
-
-/// An immediate for shift instructions.
-#[derive(Copy, Clone, Debug)]
-pub struct ImmShift {
-    /// 6-bit shift amount.
-    pub imm: u8,
-}
-
-impl ImmShift {
-    /// Create an ImmShift from raw bits, if possible.
-    pub fn maybe_from_u64(val: u64) -> Option<ImmShift> {
-        if val < 64 {
-            Some(ImmShift { imm: val as u8 })
-        } else {
-            None
-        }
-    }
-
-    /// Get the immediate value.
-    pub fn value(&self) -> u8 {
-        self.imm
-    }
-}
-
-/// A 16-bit immediate for a MOVZ instruction, with a {0,16,32,48}-bit shift.
-#[derive(Clone, Copy, Debug)]
-pub struct MoveWideConst {
-    /// The value.
-    pub bits: u16,
-    /// Result is `bits` shifted 16*shift bits to the left.
-    pub shift: u8,
-}
-
-impl MoveWideConst {
-    /// Construct a MoveWideConst from an arbitrary 64-bit constant if possible.
-    pub fn maybe_from_u64(value: u64) -> Option<MoveWideConst> {
-        let mask0 = 0x0000_0000_0000_ffffu64;
-        let mask1 = 0x0000_0000_ffff_0000u64;
-        let mask2 = 0x0000_ffff_0000_0000u64;
-        let mask3 = 0xffff_0000_0000_0000u64;
-
-        if value == (value & mask0) {
-            return Some(MoveWideConst {
-                bits: (value & mask0) as u16,
-                shift: 0,
-            });
-        }
-        if value == (value & mask1) {
-            return Some(MoveWideConst {
-                bits: ((value >> 16) & mask0) as u16,
-                shift: 1,
-            });
-        }
-        if value == (value & mask2) {
-            return Some(MoveWideConst {
-                bits: ((value >> 32) & mask0) as u16,
-                shift: 2,
-            });
-        }
-        if value == (value & mask3) {
-            return Some(MoveWideConst {
-                bits: ((value >> 48) & mask0) as u16,
-                shift: 3,
-            });
-        }
-        None
-    }
-
-    pub fn maybe_with_shift(imm: u16, shift: u8) -> Option<MoveWideConst> {
-        let shift_enc = shift / 16;
-        if shift_enc > 3 {
-            None
-        } else {
-            Some(MoveWideConst {
-                bits: imm,
-                shift: shift_enc,
-            })
-        }
-    }
-
-    /// Returns the value that this constant represents.
-    pub fn value(&self) -> u64 {
-        (self.bits as u64) << (16 * self.shift)
-    }
-}
-
-/// Advanced SIMD modified immediate as used by MOVI/MVNI.
-#[derive(Clone, Copy, Debug, PartialEq)]
-pub struct ASIMDMovModImm {
-    imm: u8,
-    shift: u8,
-    is_64bit: bool,
-    shift_ones: bool,
-}
-
-impl ASIMDMovModImm {
-    /// Construct an ASIMDMovModImm from an arbitrary 64-bit constant, if possible.
-    /// Note that the bits in `value` outside of the range specified by `size` are
-    /// ignored; for example, in the case of `ScalarSize::Size8` all bits above the
-    /// lowest 8 are ignored.
-    pub fn maybe_from_u64(value: u64, size: ScalarSize) -> Option<ASIMDMovModImm> {
-        match size {
-            ScalarSize::Size8 => Some(ASIMDMovModImm {
-                imm: value as u8,
-                shift: 0,
-                is_64bit: false,
-                shift_ones: false,
-            }),
-            ScalarSize::Size16 => {
-                let value = value as u16;
-
-                if value >> 8 == 0 {
-                    Some(ASIMDMovModImm {
-                        imm: value as u8,
-                        shift: 0,
-                        is_64bit: false,
-                        shift_ones: false,
-                    })
-                } else if value as u8 == 0 {
-                    Some(ASIMDMovModImm {
-                        imm: (value >> 8) as u8,
-                        shift: 8,
-                        is_64bit: false,
-                        shift_ones: false,
-                    })
-                } else {
-                    None
-                }
-            }
-            ScalarSize::Size32 => {
-                let value = value as u32;
-
-                // Value is of the form 0x00MMFFFF.
-                if value & 0xFF00FFFF == 0x0000FFFF {
-                    let imm = (value >> 16) as u8;
-
-                    Some(ASIMDMovModImm {
-                        imm,
-                        shift: 16,
-                        is_64bit: false,
-                        shift_ones: true,
-                    })
-                // Value is of the form 0x0000MMFF.
-                } else if value & 0xFFFF00FF == 0x000000FF {
-                    let imm = (value >> 8) as u8;
-
-                    Some(ASIMDMovModImm {
-                        imm,
-                        shift: 8,
-                        is_64bit: false,
-                        shift_ones: true,
-                    })
-                } else {
-                    // Of the 4 bytes, at most one is non-zero.
-                    for shift in (0..32).step_by(8) {
-                        if value & (0xFF << shift) == value {
-                            return Some(ASIMDMovModImm {
-                                imm: (value >> shift) as u8,
-                                shift,
-                                is_64bit: false,
-                                shift_ones: false,
-                            });
-                        }
-                    }
-
-                    None
-                }
-            }
-            ScalarSize::Size64 => {
-                let mut imm = 0u8;
-
-                // Check if all bytes are either 0 or 0xFF.
-                for i in 0..8 {
-                    let b = (value >> (i * 8)) as u8;
-
-                    if b == 0 || b == 0xFF {
-                        imm |= (b & 1) << i;
-                    } else {
-                        return None;
-                    }
-                }
-
-                Some(ASIMDMovModImm {
-                    imm,
-                    shift: 0,
-                    is_64bit: true,
-                    shift_ones: false,
-                })
-            }
-            _ => None,
-        }
-    }
-
-    /// Create a zero immediate of this format.
-    pub fn zero(size: ScalarSize) -> Self {
-        ASIMDMovModImm {
-            imm: 0,
-            shift: 0,
-            is_64bit: size == ScalarSize::Size64,
-            shift_ones: false,
-        }
-    }
-
-    /// Returns the value that this immediate represents.
-    pub fn value(&self) -> (u8, u32, bool) {
-        (self.imm, self.shift as u32, self.shift_ones)
-    }
-}
-
-/// Advanced SIMD modified immediate as used by the vector variant of FMOV.
-#[derive(Clone, Copy, Debug, PartialEq)]
-pub struct ASIMDFPModImm {
-    imm: u8,
-    is_64bit: bool,
-}
-
-impl ASIMDFPModImm {
-    /// Construct an ASIMDFPModImm from an arbitrary 64-bit constant, if possible.
-    pub fn maybe_from_u64(value: u64, size: ScalarSize) -> Option<ASIMDFPModImm> {
-        // In all cases immediates are encoded as an 8-bit number 0b_abcdefgh;
-        // let `D` be the inverse of the digit `d`.
-        match size {
-            ScalarSize::Size32 => {
-                // In this case the representable immediates are 32-bit numbers of the form
-                // 0b_aBbb_bbbc_defg_h000 shifted to the left by 16.
-                let value = value as u32;
-                let b0_5 = (value >> 19) & 0b111111;
-                let b6 = (value >> 19) & (1 << 6);
-                let b7 = (value >> 24) & (1 << 7);
-                let imm = (b0_5 | b6 | b7) as u8;
-
-                if value == Self::value32(imm) {
-                    Some(ASIMDFPModImm {
-                        imm,
-                        is_64bit: false,
-                    })
-                } else {
-                    None
-                }
-            }
-            ScalarSize::Size64 => {
-                // In this case the representable immediates are 64-bit numbers of the form
-                // 0b_aBbb_bbbb_bbcd_efgh shifted to the left by 48.
-                let b0_5 = (value >> 48) & 0b111111;
-                let b6 = (value >> 48) & (1 << 6);
-                let b7 = (value >> 56) & (1 << 7);
-                let imm = (b0_5 | b6 | b7) as u8;
-
-                if value == Self::value64(imm) {
-                    Some(ASIMDFPModImm {
-                        imm,
-                        is_64bit: true,
-                    })
-                } else {
-                    None
-                }
-            }
-            _ => None,
-        }
-    }
-
-    /// Returns bits ready for encoding.
-    pub fn enc_bits(&self) -> u8 {
-        self.imm
-    }
-
-    /// Returns the 32-bit value that corresponds to an 8-bit encoding.
-    fn value32(imm: u8) -> u32 {
-        let imm = imm as u32;
-        let b0_5 = imm & 0b111111;
-        let b6 = (imm >> 6) & 1;
-        let b6_inv = b6 ^ 1;
-        let b7 = (imm >> 7) & 1;
-
-        b0_5 << 19 | (b6 * 0b11111) << 25 | b6_inv << 30 | b7 << 31
-    }
-
-    /// Returns the 64-bit value that corresponds to an 8-bit encoding.
-    fn value64(imm: u8) -> u64 {
-        let imm = imm as u64;
-        let b0_5 = imm & 0b111111;
-        let b6 = (imm >> 6) & 1;
-        let b6_inv = b6 ^ 1;
-        let b7 = (imm >> 7) & 1;
-
-        b0_5 << 48 | (b6 * 0b11111111) << 54 | b6_inv << 62 | b7 << 63
-    }
-}
-
-impl PrettyPrint for NZCV {
-    fn show_rru(&self, _mb_rru: Option<&RealRegUniverse>) -> String {
-        let fmt = |c: char, v| if v { c.to_ascii_uppercase() } else { c };
-        format!(
-            "#{}{}{}{}",
-            fmt('n', self.n),
-            fmt('z', self.z),
-            fmt('c', self.c),
-            fmt('v', self.v)
-        )
-    }
-}
-
-impl PrettyPrint for UImm5 {
-    fn show_rru(&self, _mb_rru: Option<&RealRegUniverse>) -> String {
-        format!("#{}", self.value)
-    }
-}
-
-impl PrettyPrint for Imm12 {
-    fn show_rru(&self, _mb_rru: Option<&RealRegUniverse>) -> String {
-        let shift = if self.shift12 { 12 } else { 0 };
-        let value = u32::from(self.bits) << shift;
-        format!("#{}", value)
-    }
-}
-
-impl PrettyPrint for SImm7Scaled {
-    fn show_rru(&self, _mb_rru: Option<&RealRegUniverse>) -> String {
-        format!("#{}", self.value)
-    }
-}
-
-impl PrettyPrint for FPULeftShiftImm {
-    fn show_rru(&self, _mb_rru: Option<&RealRegUniverse>) -> String {
-        format!("#{}", self.amount)
-    }
-}
-
-impl PrettyPrint for FPURightShiftImm {
-    fn show_rru(&self, _mb_rru: Option<&RealRegUniverse>) -> String {
-        format!("#{}", self.amount)
-    }
-}
-
-impl PrettyPrint for SImm9 {
-    fn show_rru(&self, _mb_rru: Option<&RealRegUniverse>) -> String {
-        format!("#{}", self.value)
-    }
-}
-
-impl PrettyPrint for UImm12Scaled {
-    fn show_rru(&self, _mb_rru: Option<&RealRegUniverse>) -> String {
-        format!("#{}", self.value)
-    }
-}
-
-impl PrettyPrint for ImmLogic {
-    fn show_rru(&self, _mb_rru: Option<&RealRegUniverse>) -> String {
-        format!("#{}", self.value())
-    }
-}
-
-impl PrettyPrint for ImmShift {
-    fn show_rru(&self, _mb_rru: Option<&RealRegUniverse>) -> String {
-        format!("#{}", self.imm)
-    }
-}
-
-impl PrettyPrint for MoveWideConst {
-    fn show_rru(&self, _mb_rru: Option<&RealRegUniverse>) -> String {
-        if self.shift == 0 {
-            format!("#{}", self.bits)
-        } else {
-            format!("#{}, LSL #{}", self.bits, self.shift * 16)
-        }
-    }
-}
-
-impl PrettyPrint for ASIMDMovModImm {
-    fn show_rru(&self, _mb_rru: Option<&RealRegUniverse>) -> String {
-        if self.is_64bit {
-            debug_assert_eq!(self.shift, 0);
-
-            let enc_imm = self.imm as i8;
-            let mut imm = 0u64;
-
-            for i in 0..8 {
-                let b = (enc_imm >> i) & 1;
-
-                imm |= (-b as u8 as u64) << (i * 8);
-            }
-
-            format!("#{}", imm)
-        } else if self.shift == 0 {
-            format!("#{}", self.imm)
-        } else {
-            let shift_type = if self.shift_ones { "MSL" } else { "LSL" };
-            format!("#{}, {} #{}", self.imm, shift_type, self.shift)
-        }
-    }
-}
-
-impl PrettyPrint for ASIMDFPModImm {
-    fn show_rru(&self, _mb_rru: Option<&RealRegUniverse>) -> String {
-        if self.is_64bit {
-            format!("#{}", f64::from_bits(Self::value64(self.imm)))
-        } else {
-            format!("#{}", f32::from_bits(Self::value32(self.imm)))
-        }
-    }
-}
-
-#[cfg(test)]
-mod test {
-    use super::*;
-
-    #[test]
-    fn imm_logical_test() {
-        assert_eq!(None, ImmLogic::maybe_from_u64(0, I64));
-        assert_eq!(None, ImmLogic::maybe_from_u64(u64::max_value(), I64));
-
-        assert_eq!(
-            Some(ImmLogic {
-                value: 1,
-                n: true,
-                r: 0,
-                s: 0,
-                size: OperandSize::Size64,
-            }),
-            ImmLogic::maybe_from_u64(1, I64)
-        );
-
-        assert_eq!(
-            Some(ImmLogic {
-                value: 2,
-                n: true,
-                r: 63,
-                s: 0,
-                size: OperandSize::Size64,
-            }),
-            ImmLogic::maybe_from_u64(2, I64)
-        );
-
-        assert_eq!(None, ImmLogic::maybe_from_u64(5, I64));
-
-        assert_eq!(None, ImmLogic::maybe_from_u64(11, I64));
-
-        assert_eq!(
-            Some(ImmLogic {
-                value: 248,
-                n: true,
-                r: 61,
-                s: 4,
-                size: OperandSize::Size64,
-            }),
-            ImmLogic::maybe_from_u64(248, I64)
-        );
-
-        assert_eq!(None, ImmLogic::maybe_from_u64(249, I64));
-
-        assert_eq!(
-            Some(ImmLogic {
-                value: 1920,
-                n: true,
-                r: 57,
-                s: 3,
-                size: OperandSize::Size64,
-            }),
-            ImmLogic::maybe_from_u64(1920, I64)
-        );
-
-        assert_eq!(
-            Some(ImmLogic {
-                value: 0x7ffe,
-                n: true,
-                r: 63,
-                s: 13,
-                size: OperandSize::Size64,
-            }),
-            ImmLogic::maybe_from_u64(0x7ffe, I64)
-        );
-
-        assert_eq!(
-            Some(ImmLogic {
-                value: 0x30000,
-                n: true,
-                r: 48,
-                s: 1,
-                size: OperandSize::Size64,
-            }),
-            ImmLogic::maybe_from_u64(0x30000, I64)
-        );
-
-        assert_eq!(
-            Some(ImmLogic {
-                value: 0x100000,
-                n: true,
-                r: 44,
-                s: 0,
-                size: OperandSize::Size64,
-            }),
-            ImmLogic::maybe_from_u64(0x100000, I64)
-        );
-
-        assert_eq!(
-            Some(ImmLogic {
-                value: u64::max_value() - 1,
-                n: true,
-                r: 63,
-                s: 62,
-                size: OperandSize::Size64,
-            }),
-            ImmLogic::maybe_from_u64(u64::max_value() - 1, I64)
-        );
-
-        assert_eq!(
-            Some(ImmLogic {
-                value: 0xaaaaaaaaaaaaaaaa,
-                n: false,
-                r: 1,
-                s: 60,
-                size: OperandSize::Size64,
-            }),
-            ImmLogic::maybe_from_u64(0xaaaaaaaaaaaaaaaa, I64)
-        );
-
-        assert_eq!(
-            Some(ImmLogic {
-                value: 0x8181818181818181,
-                n: false,
-                r: 1,
-                s: 49,
-                size: OperandSize::Size64,
-            }),
-            ImmLogic::maybe_from_u64(0x8181818181818181, I64)
-        );
-
-        assert_eq!(
-            Some(ImmLogic {
-                value: 0xffc3ffc3ffc3ffc3,
-                n: false,
-                r: 10,
-                s: 43,
-                size: OperandSize::Size64,
-            }),
-            ImmLogic::maybe_from_u64(0xffc3ffc3ffc3ffc3, I64)
-        );
-
-        assert_eq!(
-            Some(ImmLogic {
-                value: 0x100000001,
-                n: false,
-                r: 0,
-                s: 0,
-                size: OperandSize::Size64,
-            }),
-            ImmLogic::maybe_from_u64(0x100000001, I64)
-        );
-
-        assert_eq!(
-            Some(ImmLogic {
-                value: 0x1111111111111111,
-                n: false,
-                r: 0,
-                s: 56,
-                size: OperandSize::Size64,
-            }),
-            ImmLogic::maybe_from_u64(0x1111111111111111, I64)
-        );
-
-        for n in 0..2 {
-            let types = if n == 0 { vec![I64, I32] } else { vec![I64] };
-            for s in 0..64 {
-                for r in 0..64 {
-                    let imm = get_logical_imm(n, s, r);
-                    for &ty in &types {
-                        match ImmLogic::maybe_from_u64(imm, ty) {
-                            Some(ImmLogic { value, .. }) => {
-                                assert_eq!(imm, value);
-                                ImmLogic::maybe_from_u64(!value, ty).unwrap();
-                            }
-                            None => assert_eq!(0, imm),
-                        };
-                    }
-                }
-            }
-        }
-    }
-
-    // Repeat a value that has `width` bits, across a 64-bit value.
-    fn repeat(value: u64, width: u64) -> u64 {
-        let mut result = value & ((1 << width) - 1);
-        let mut i = width;
-        while i < 64 {
-            result |= result << i;
-            i *= 2;
-        }
-        result
-    }
-
-    // Get the logical immediate, from the encoding N/R/S bits.
-    fn get_logical_imm(n: u32, s: u32, r: u32) -> u64 {
-        // An integer is constructed from the n, imm_s and imm_r bits according to
-        // the following table:
-        //
-        //  N   imms    immr    size        S             R
-        //  1  ssssss  rrrrrr    64    UInt(ssssss)  UInt(rrrrrr)
-        //  0  0sssss  xrrrrr    32    UInt(sssss)   UInt(rrrrr)
-        //  0  10ssss  xxrrrr    16    UInt(ssss)    UInt(rrrr)
-        //  0  110sss  xxxrrr     8    UInt(sss)     UInt(rrr)
-        //  0  1110ss  xxxxrr     4    UInt(ss)      UInt(rr)
-        //  0  11110s  xxxxxr     2    UInt(s)       UInt(r)
-        // (s bits must not be all set)
-        //
-        // A pattern is constructed of size bits, where the least significant S+1
-        // bits are set. The pattern is rotated right by R, and repeated across a
-        // 64-bit value.
-
-        if n == 1 {
-            if s == 0x3f {
-                return 0;
-            }
-            let bits = (1u64 << (s + 1)) - 1;
-            bits.rotate_right(r)
-        } else {
-            if (s >> 1) == 0x1f {
-                return 0;
-            }
-            let mut width = 0x20;
-            while width >= 0x2 {
-                if (s & width) == 0 {
-                    let mask = width - 1;
-                    if (s & mask) == mask {
-                        return 0;
-                    }
-                    let bits = (1u64 << ((s & mask) + 1)) - 1;
-                    return repeat(bits.rotate_right(r & mask), width.into());
-                }
-                width >>= 1;
-            }
-            unreachable!();
-        }
-    }
-
-    #[test]
-    fn asimd_fp_mod_imm_test() {
-        assert_eq!(None, ASIMDFPModImm::maybe_from_u64(0, ScalarSize::Size32));
-        assert_eq!(
-            None,
-            ASIMDFPModImm::maybe_from_u64(0.013671875_f32.to_bits() as u64, ScalarSize::Size32)
-        );
-        assert_eq!(None, ASIMDFPModImm::maybe_from_u64(0, ScalarSize::Size64));
-        assert_eq!(
-            None,
-            ASIMDFPModImm::maybe_from_u64(10000_f64.to_bits(), ScalarSize::Size64)
-        );
-    }
-
-    #[test]
-    fn asimd_mov_mod_imm_test() {
-        assert_eq!(
-            None,
-            ASIMDMovModImm::maybe_from_u64(513, ScalarSize::Size16)
-        );
-        assert_eq!(
-            None,
-            ASIMDMovModImm::maybe_from_u64(4278190335, ScalarSize::Size32)
-        );
-        assert_eq!(
-            None,
-            ASIMDMovModImm::maybe_from_u64(8388608, ScalarSize::Size64)
-        );
-
-        assert_eq!(
-            Some(ASIMDMovModImm {
-                imm: 66,
-                shift: 16,
-                is_64bit: false,
-                shift_ones: true,
-            }),
-            ASIMDMovModImm::maybe_from_u64(4390911, ScalarSize::Size32)
-        );
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/inst/mod.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/inst/mod.rs
deleted file mode 100644
index 4e161ea45..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/inst/mod.rs
+++ /dev/null
@@ -1,3676 +0,0 @@
-//! This module defines aarch64-specific machine instruction types.
-
-// Some variants are not constructed, but we still want them as options in the future.
-#![allow(dead_code)]
-
-use crate::binemit::{Addend, CodeOffset, Reloc};
-use crate::ir::types::{
-    B1, B128, B16, B32, B64, B8, F32, F64, FFLAGS, I128, I16, I32, I64, I8, I8X16, IFLAGS, R32, R64,
-};
-use crate::ir::{ExternalName, MemFlags, Opcode, SourceLoc, Type, ValueLabel};
-use crate::isa::CallConv;
-use crate::machinst::*;
-use crate::{settings, CodegenError, CodegenResult};
-
-use regalloc::RegUsageCollector;
-use regalloc::{PrettyPrint, RealRegUniverse, Reg, RegClass, SpillSlot, VirtualReg, Writable};
-
-use alloc::vec::Vec;
-use core::convert::TryFrom;
-use smallvec::{smallvec, SmallVec};
-use std::string::{String, ToString};
-
-pub mod regs;
-pub use self::regs::*;
-pub mod imms;
-pub use self::imms::*;
-pub mod args;
-pub use self::args::*;
-pub mod emit;
-pub use self::emit::*;
-use crate::isa::aarch64::abi::AArch64MachineDeps;
-
-pub mod unwind;
-
-#[cfg(test)]
-mod emit_tests;
-
-//=============================================================================
-// Instructions (top level): definition
-
-pub use crate::isa::aarch64::lower::isle::generated_code::{
-    ALUOp, ALUOp3, AtomicRMWOp, BitOp, FPUOp1, FPUOp2, FPUOp3, FpuRoundMode, FpuToIntOp,
-    IntToFpuOp, MInst as Inst, VecALUOp, VecExtendOp, VecLanesOp, VecMisc2, VecPairOp, VecRRLongOp,
-    VecRRNarrowOp, VecRRPairLongOp, VecRRRLongOp, VecShiftImmOp,
-};
-
-/// A floating-point unit (FPU) operation with two args, a register and an immediate.
-#[derive(Copy, Clone, Debug)]
-pub enum FPUOpRI {
-    /// Unsigned right shift. Rd = Rn << #imm
-    UShr32(FPURightShiftImm),
-    /// Unsigned right shift. Rd = Rn << #imm
-    UShr64(FPURightShiftImm),
-    /// Shift left and insert. Rd |= Rn << #imm
-    Sli32(FPULeftShiftImm),
-    /// Shift left and insert. Rd |= Rn << #imm
-    Sli64(FPULeftShiftImm),
-}
-
-impl BitOp {
-    /// Get the assembly mnemonic for this opcode.
-    pub fn op_str(&self) -> &'static str {
-        match self {
-            BitOp::RBit => "rbit",
-            BitOp::Clz => "clz",
-            BitOp::Cls => "cls",
-        }
-    }
-}
-
-/// Additional information for (direct) Call instructions, left out of line to lower the size of
-/// the Inst enum.
-#[derive(Clone, Debug)]
-pub struct CallInfo {
-    pub dest: ExternalName,
-    pub uses: Vec<Reg>,
-    pub defs: Vec<Writable<Reg>>,
-    pub opcode: Opcode,
-    pub caller_callconv: CallConv,
-    pub callee_callconv: CallConv,
-}
-
-/// Additional information for CallInd instructions, left out of line to lower the size of the Inst
-/// enum.
-#[derive(Clone, Debug)]
-pub struct CallIndInfo {
-    pub rn: Reg,
-    pub uses: Vec<Reg>,
-    pub defs: Vec<Writable<Reg>>,
-    pub opcode: Opcode,
-    pub caller_callconv: CallConv,
-    pub callee_callconv: CallConv,
-}
-
-/// Additional information for JTSequence instructions, left out of line to lower the size of the Inst
-/// enum.
-#[derive(Clone, Debug)]
-pub struct JTSequenceInfo {
-    pub targets: Vec<BranchTarget>,
-    pub default_target: BranchTarget,
-    pub targets_for_term: Vec<MachLabel>, // needed for MachTerminator.
-}
-
-fn count_zero_half_words(mut value: u64, num_half_words: u8) -> usize {
-    let mut count = 0;
-    for _ in 0..num_half_words {
-        if value & 0xffff == 0 {
-            count += 1;
-        }
-        value >>= 16;
-    }
-
-    count
-}
-
-#[test]
-fn inst_size_test() {
-    // This test will help with unintentionally growing the size
-    // of the Inst enum.
-    assert_eq!(32, std::mem::size_of::<Inst>());
-}
-
-impl Inst {
-    /// Create an instruction that loads a constant, using one of serveral options (MOVZ, MOVN,
-    /// logical immediate, or constant pool).
-    pub fn load_constant(rd: Writable<Reg>, value: u64) -> SmallVec<[Inst; 4]> {
-        // NB: this is duplicated in `lower/isle.rs` and `inst.isle` right now,
-        // if modifications are made here before this is deleted after moving to
-        // ISLE then those locations should be updated as well.
-
-        if let Some(imm) = MoveWideConst::maybe_from_u64(value) {
-            // 16-bit immediate (shifted by 0, 16, 32 or 48 bits) in MOVZ
-            smallvec![Inst::MovZ {
-                rd,
-                imm,
-                size: OperandSize::Size64
-            }]
-        } else if let Some(imm) = MoveWideConst::maybe_from_u64(!value) {
-            // 16-bit immediate (shifted by 0, 16, 32 or 48 bits) in MOVN
-            smallvec![Inst::MovN {
-                rd,
-                imm,
-                size: OperandSize::Size64
-            }]
-        } else if let Some(imml) = ImmLogic::maybe_from_u64(value, I64) {
-            // Weird logical-instruction immediate in ORI using zero register
-            smallvec![Inst::AluRRImmLogic {
-                alu_op: ALUOp::Orr,
-                size: OperandSize::Size64,
-                rd,
-                rn: zero_reg(),
-                imml,
-            }]
-        } else {
-            let mut insts = smallvec![];
-
-            // If the top 32 bits are zero, use 32-bit `mov` operations.
-            let (num_half_words, size, negated) = if value >> 32 == 0 {
-                (2, OperandSize::Size32, (!value << 32) >> 32)
-            } else {
-                (4, OperandSize::Size64, !value)
-            };
-            // If the number of 0xffff half words is greater than the number of 0x0000 half words
-            // it is more efficient to use `movn` for the first instruction.
-            let first_is_inverted = count_zero_half_words(negated, num_half_words)
-                > count_zero_half_words(value, num_half_words);
-            // Either 0xffff or 0x0000 half words can be skipped, depending on the first
-            // instruction used.
-            let ignored_halfword = if first_is_inverted { 0xffff } else { 0 };
-            let mut first_mov_emitted = false;
-
-            for i in 0..num_half_words {
-                let imm16 = (value >> (16 * i)) & 0xffff;
-                if imm16 != ignored_halfword {
-                    if !first_mov_emitted {
-                        first_mov_emitted = true;
-                        if first_is_inverted {
-                            let imm =
-                                MoveWideConst::maybe_with_shift(((!imm16) & 0xffff) as u16, i * 16)
-                                    .unwrap();
-                            insts.push(Inst::MovN { rd, imm, size });
-                        } else {
-                            let imm =
-                                MoveWideConst::maybe_with_shift(imm16 as u16, i * 16).unwrap();
-                            insts.push(Inst::MovZ { rd, imm, size });
-                        }
-                    } else {
-                        let imm = MoveWideConst::maybe_with_shift(imm16 as u16, i * 16).unwrap();
-                        insts.push(Inst::MovK { rd, imm, size });
-                    }
-                }
-            }
-
-            assert!(first_mov_emitted);
-
-            insts
-        }
-    }
-
-    /// Create instructions that load a 128-bit constant.
-    pub fn load_constant128(to_regs: ValueRegs<Writable<Reg>>, value: u128) -> SmallVec<[Inst; 4]> {
-        assert_eq!(to_regs.len(), 2, "Expected to load i128 into two registers");
-
-        let lower = value as u64;
-        let upper = (value >> 64) as u64;
-
-        let lower_reg = to_regs.regs()[0];
-        let upper_reg = to_regs.regs()[1];
-
-        let mut load_ins = Inst::load_constant(lower_reg, lower);
-        let load_upper = Inst::load_constant(upper_reg, upper);
-
-        load_ins.extend(load_upper.into_iter());
-        load_ins
-    }
-
-    /// Create instructions that load a 32-bit floating-point constant.
-    pub fn load_fp_constant32<F: FnMut(Type) -> Writable<Reg>>(
-        rd: Writable<Reg>,
-        const_data: u32,
-        mut alloc_tmp: F,
-    ) -> SmallVec<[Inst; 4]> {
-        // Note that we must make sure that all bits outside the lowest 32 are set to 0
-        // because this function is also used to load wider constants (that have zeros
-        // in their most significant bits).
-        if const_data == 0 {
-            smallvec![Inst::VecDupImm {
-                rd,
-                imm: ASIMDMovModImm::zero(ScalarSize::Size32),
-                invert: false,
-                size: VectorSize::Size32x2,
-            }]
-        } else if let Some(imm) =
-            ASIMDFPModImm::maybe_from_u64(const_data.into(), ScalarSize::Size32)
-        {
-            smallvec![Inst::FpuMoveFPImm {
-                rd,
-                imm,
-                size: ScalarSize::Size32,
-            }]
-        } else {
-            let tmp = alloc_tmp(I32);
-            let mut insts = Inst::load_constant(tmp, const_data as u64);
-
-            insts.push(Inst::MovToFpu {
-                rd,
-                rn: tmp.to_reg(),
-                size: ScalarSize::Size32,
-            });
-
-            insts
-        }
-    }
-
-    /// Create instructions that load a 64-bit floating-point constant.
-    pub fn load_fp_constant64<F: FnMut(Type) -> Writable<Reg>>(
-        rd: Writable<Reg>,
-        const_data: u64,
-        mut alloc_tmp: F,
-    ) -> SmallVec<[Inst; 4]> {
-        // Note that we must make sure that all bits outside the lowest 64 are set to 0
-        // because this function is also used to load wider constants (that have zeros
-        // in their most significant bits).
-        // TODO: Treat as half of a 128 bit vector and consider replicated patterns.
-        // Scalar MOVI might also be an option.
-        if const_data == 0 {
-            smallvec![Inst::VecDupImm {
-                rd,
-                imm: ASIMDMovModImm::zero(ScalarSize::Size32),
-                invert: false,
-                size: VectorSize::Size32x2,
-            }]
-        } else if let Some(imm) = ASIMDFPModImm::maybe_from_u64(const_data, ScalarSize::Size64) {
-            smallvec![Inst::FpuMoveFPImm {
-                rd,
-                imm,
-                size: ScalarSize::Size64,
-            }]
-        } else if let Ok(const_data) = u32::try_from(const_data) {
-            Inst::load_fp_constant32(rd, const_data, alloc_tmp)
-        } else if const_data & (u32::MAX as u64) == 0 {
-            let tmp = alloc_tmp(I64);
-            let mut insts = Inst::load_constant(tmp, const_data);
-
-            insts.push(Inst::MovToFpu {
-                rd,
-                rn: tmp.to_reg(),
-                size: ScalarSize::Size64,
-            });
-
-            insts
-        } else {
-            smallvec![Inst::LoadFpuConst64 { rd, const_data }]
-        }
-    }
-
-    /// Create instructions that load a 128-bit vector constant.
-    pub fn load_fp_constant128<F: FnMut(Type) -> Writable<Reg>>(
-        rd: Writable<Reg>,
-        const_data: u128,
-        alloc_tmp: F,
-    ) -> SmallVec<[Inst; 5]> {
-        if let Ok(const_data) = u64::try_from(const_data) {
-            SmallVec::from(&Inst::load_fp_constant64(rd, const_data, alloc_tmp)[..])
-        } else if let Some((pattern, size)) =
-            Inst::get_replicated_vector_pattern(const_data, ScalarSize::Size64)
-        {
-            Inst::load_replicated_vector_pattern(
-                rd,
-                pattern,
-                VectorSize::from_lane_size(size, true),
-                alloc_tmp,
-            )
-        } else {
-            smallvec![Inst::LoadFpuConst128 { rd, const_data }]
-        }
-    }
-
-    /// Determine whether a 128-bit constant represents a vector consisting of elements with
-    /// the same value.
-    pub fn get_replicated_vector_pattern(
-        value: u128,
-        size: ScalarSize,
-    ) -> Option<(u64, ScalarSize)> {
-        let (mask, shift, next_size) = match size {
-            ScalarSize::Size8 => (u8::MAX as u128, 8, ScalarSize::Size128),
-            ScalarSize::Size16 => (u16::MAX as u128, 16, ScalarSize::Size8),
-            ScalarSize::Size32 => (u32::MAX as u128, 32, ScalarSize::Size16),
-            ScalarSize::Size64 => (u64::MAX as u128, 64, ScalarSize::Size32),
-            _ => return None,
-        };
-        let mut r = None;
-        let v = value & mask;
-
-        if (value >> shift) & mask == v {
-            r = Inst::get_replicated_vector_pattern(v, next_size);
-
-            if r.is_none() {
-                r = Some((v as u64, size));
-            }
-        }
-
-        r
-    }
-
-    /// Create instructions that load a vector constant consisting of elements with
-    /// the same value.
-    pub fn load_replicated_vector_pattern<F: FnMut(Type) -> Writable<Reg>>(
-        rd: Writable<Reg>,
-        pattern: u64,
-        size: VectorSize,
-        mut alloc_tmp: F,
-    ) -> SmallVec<[Inst; 5]> {
-        let lane_size = size.lane_size();
-        let widen_32_bit_pattern = |pattern, lane_size| {
-            if lane_size == ScalarSize::Size32 {
-                let pattern = pattern as u32 as u64;
-
-                ASIMDMovModImm::maybe_from_u64(pattern | (pattern << 32), ScalarSize::Size64)
-            } else {
-                None
-            }
-        };
-
-        if let Some(imm) = ASIMDMovModImm::maybe_from_u64(pattern, lane_size) {
-            smallvec![Inst::VecDupImm {
-                rd,
-                imm,
-                invert: false,
-                size
-            }]
-        } else if let Some(imm) = ASIMDMovModImm::maybe_from_u64(!pattern, lane_size) {
-            debug_assert_ne!(lane_size, ScalarSize::Size8);
-            debug_assert_ne!(lane_size, ScalarSize::Size64);
-
-            smallvec![Inst::VecDupImm {
-                rd,
-                imm,
-                invert: true,
-                size
-            }]
-        } else if let Some(imm) = widen_32_bit_pattern(pattern, lane_size) {
-            let mut insts = smallvec![Inst::VecDupImm {
-                rd,
-                imm,
-                invert: false,
-                size: VectorSize::Size64x2,
-            }];
-
-            // TODO: Implement support for 64-bit scalar MOVI; we zero-extend the
-            // lower 64 bits instead.
-            if !size.is_128bits() {
-                insts.push(Inst::FpuExtend {
-                    rd,
-                    rn: rd.to_reg(),
-                    size: ScalarSize::Size64,
-                });
-            }
-
-            insts
-        } else if let Some(imm) = ASIMDFPModImm::maybe_from_u64(pattern, lane_size) {
-            smallvec![Inst::VecDupFPImm { rd, imm, size }]
-        } else {
-            let tmp = alloc_tmp(I64);
-            let mut insts = SmallVec::from(&Inst::load_constant(tmp, pattern)[..]);
-
-            insts.push(Inst::VecDup {
-                rd,
-                rn: tmp.to_reg(),
-                size,
-            });
-
-            insts
-        }
-    }
-
-    /// Generic constructor for a load (zero-extending where appropriate).
-    pub fn gen_load(into_reg: Writable<Reg>, mem: AMode, ty: Type, flags: MemFlags) -> Inst {
-        match ty {
-            B1 | B8 | I8 => Inst::ULoad8 {
-                rd: into_reg,
-                mem,
-                flags,
-            },
-            B16 | I16 => Inst::ULoad16 {
-                rd: into_reg,
-                mem,
-                flags,
-            },
-            B32 | I32 | R32 => Inst::ULoad32 {
-                rd: into_reg,
-                mem,
-                flags,
-            },
-            B64 | I64 | R64 => Inst::ULoad64 {
-                rd: into_reg,
-                mem,
-                flags,
-            },
-            F32 => Inst::FpuLoad32 {
-                rd: into_reg,
-                mem,
-                flags,
-            },
-            F64 => Inst::FpuLoad64 {
-                rd: into_reg,
-                mem,
-                flags,
-            },
-            _ => {
-                if ty.is_vector() {
-                    let bits = ty_bits(ty);
-                    let rd = into_reg;
-
-                    if bits == 128 {
-                        Inst::FpuLoad128 { rd, mem, flags }
-                    } else {
-                        assert_eq!(bits, 64);
-                        Inst::FpuLoad64 { rd, mem, flags }
-                    }
-                } else {
-                    unimplemented!("gen_load({})", ty);
-                }
-            }
-        }
-    }
-
-    /// Generic constructor for a store.
-    pub fn gen_store(mem: AMode, from_reg: Reg, ty: Type, flags: MemFlags) -> Inst {
-        match ty {
-            B1 | B8 | I8 => Inst::Store8 {
-                rd: from_reg,
-                mem,
-                flags,
-            },
-            B16 | I16 => Inst::Store16 {
-                rd: from_reg,
-                mem,
-                flags,
-            },
-            B32 | I32 | R32 => Inst::Store32 {
-                rd: from_reg,
-                mem,
-                flags,
-            },
-            B64 | I64 | R64 => Inst::Store64 {
-                rd: from_reg,
-                mem,
-                flags,
-            },
-            F32 => Inst::FpuStore32 {
-                rd: from_reg,
-                mem,
-                flags,
-            },
-            F64 => Inst::FpuStore64 {
-                rd: from_reg,
-                mem,
-                flags,
-            },
-            _ => {
-                if ty.is_vector() {
-                    let bits = ty_bits(ty);
-                    let rd = from_reg;
-
-                    if bits == 128 {
-                        Inst::FpuStore128 { rd, mem, flags }
-                    } else {
-                        assert_eq!(bits, 64);
-                        Inst::FpuStore64 { rd, mem, flags }
-                    }
-                } else {
-                    unimplemented!("gen_store({})", ty);
-                }
-            }
-        }
-    }
-
-    /// Generate a LoadAddr instruction (load address of an amode into
-    /// register). Elides when possible (when amode is just a register). Returns
-    /// destination register: either `rd` or a register directly from the amode.
-    pub fn gen_load_addr(rd: Writable<Reg>, mem: AMode) -> (Reg, Option<Inst>) {
-        if let Some(r) = mem.is_reg() {
-            (r, None)
-        } else {
-            (rd.to_reg(), Some(Inst::LoadAddr { rd, mem }))
-        }
-    }
-}
-
-//=============================================================================
-// Instructions: get_regs
-
-fn memarg_regs(memarg: &AMode, collector: &mut RegUsageCollector) {
-    match memarg {
-        &AMode::Unscaled(reg, ..) | &AMode::UnsignedOffset(reg, ..) => {
-            collector.add_use(reg);
-        }
-        &AMode::RegReg(r1, r2, ..)
-        | &AMode::RegScaled(r1, r2, ..)
-        | &AMode::RegScaledExtended(r1, r2, ..)
-        | &AMode::RegExtended(r1, r2, ..) => {
-            collector.add_use(r1);
-            collector.add_use(r2);
-        }
-        &AMode::Label(..) => {}
-        &AMode::PreIndexed(reg, ..) | &AMode::PostIndexed(reg, ..) => {
-            collector.add_mod(reg);
-        }
-        &AMode::FPOffset(..) => {
-            collector.add_use(fp_reg());
-        }
-        &AMode::SPOffset(..) | &AMode::NominalSPOffset(..) => {
-            collector.add_use(stack_reg());
-        }
-        &AMode::RegOffset(r, ..) => {
-            collector.add_use(r);
-        }
-    }
-}
-
-fn pairmemarg_regs(pairmemarg: &PairAMode, collector: &mut RegUsageCollector) {
-    match pairmemarg {
-        &PairAMode::SignedOffset(reg, ..) => {
-            collector.add_use(reg);
-        }
-        &PairAMode::PreIndexed(reg, ..) | &PairAMode::PostIndexed(reg, ..) => {
-            collector.add_mod(reg);
-        }
-    }
-}
-
-fn aarch64_get_regs(inst: &Inst, collector: &mut RegUsageCollector) {
-    match inst {
-        &Inst::AluRRR { rd, rn, rm, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-            collector.add_use(rm);
-        }
-        &Inst::AluRRRR { rd, rn, rm, ra, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-            collector.add_use(rm);
-            collector.add_use(ra);
-        }
-        &Inst::AluRRImm12 { rd, rn, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-        }
-        &Inst::AluRRImmLogic { rd, rn, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-        }
-        &Inst::AluRRImmShift { rd, rn, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-        }
-        &Inst::AluRRRShift { rd, rn, rm, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-            collector.add_use(rm);
-        }
-        &Inst::AluRRRExtend { rd, rn, rm, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-            collector.add_use(rm);
-        }
-        &Inst::BitRR { rd, rn, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-        }
-        &Inst::ULoad8 { rd, ref mem, .. }
-        | &Inst::SLoad8 { rd, ref mem, .. }
-        | &Inst::ULoad16 { rd, ref mem, .. }
-        | &Inst::SLoad16 { rd, ref mem, .. }
-        | &Inst::ULoad32 { rd, ref mem, .. }
-        | &Inst::SLoad32 { rd, ref mem, .. }
-        | &Inst::ULoad64 { rd, ref mem, .. } => {
-            collector.add_def(rd);
-            memarg_regs(mem, collector);
-        }
-        &Inst::Store8 { rd, ref mem, .. }
-        | &Inst::Store16 { rd, ref mem, .. }
-        | &Inst::Store32 { rd, ref mem, .. }
-        | &Inst::Store64 { rd, ref mem, .. } => {
-            collector.add_use(rd);
-            memarg_regs(mem, collector);
-        }
-        &Inst::StoreP64 {
-            rt, rt2, ref mem, ..
-        } => {
-            collector.add_use(rt);
-            collector.add_use(rt2);
-            pairmemarg_regs(mem, collector);
-        }
-        &Inst::LoadP64 {
-            rt, rt2, ref mem, ..
-        } => {
-            collector.add_def(rt);
-            collector.add_def(rt2);
-            pairmemarg_regs(mem, collector);
-        }
-        &Inst::Mov64 { rd, rm } => {
-            collector.add_def(rd);
-            collector.add_use(rm);
-        }
-        &Inst::Mov32 { rd, rm } => {
-            collector.add_def(rd);
-            collector.add_use(rm);
-        }
-        &Inst::MovZ { rd, .. } | &Inst::MovN { rd, .. } => {
-            collector.add_def(rd);
-        }
-        &Inst::MovK { rd, .. } => {
-            collector.add_mod(rd);
-        }
-        &Inst::CSel { rd, rn, rm, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-            collector.add_use(rm);
-        }
-        &Inst::CSet { rd, .. } | &Inst::CSetm { rd, .. } => {
-            collector.add_def(rd);
-        }
-        &Inst::CCmpImm { rn, .. } => {
-            collector.add_use(rn);
-        }
-        &Inst::AtomicRMWLoop { op, .. } => {
-            collector.add_use(xreg(25));
-            collector.add_use(xreg(26));
-            collector.add_def(writable_xreg(24));
-            collector.add_def(writable_xreg(27));
-            if op != AtomicRmwOp::Xchg {
-                collector.add_def(writable_xreg(28));
-            }
-        }
-        &Inst::AtomicRMW { rs, rt, rn, .. } => {
-            collector.add_use(rs);
-            collector.add_def(rt);
-            collector.add_use(rn);
-        }
-        &Inst::AtomicCAS { rs, rt, rn, .. } => {
-            collector.add_mod(rs);
-            collector.add_use(rt);
-            collector.add_use(rn);
-        }
-        &Inst::AtomicCASLoop { .. } => {
-            collector.add_use(xreg(25));
-            collector.add_use(xreg(26));
-            collector.add_use(xreg(28));
-            collector.add_def(writable_xreg(24));
-            collector.add_def(writable_xreg(27));
-        }
-        &Inst::LoadAcquire { rt, rn, .. } => {
-            collector.add_use(rn);
-            collector.add_def(rt);
-        }
-        &Inst::StoreRelease { rt, rn, .. } => {
-            collector.add_use(rn);
-            collector.add_use(rt);
-        }
-        &Inst::Fence {} => {}
-        &Inst::FpuMove64 { rd, rn } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-        }
-        &Inst::FpuMove128 { rd, rn } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-        }
-        &Inst::FpuMoveFromVec { rd, rn, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-        }
-        &Inst::FpuExtend { rd, rn, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-        }
-        &Inst::FpuRR { rd, rn, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-        }
-        &Inst::FpuRRR { rd, rn, rm, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-            collector.add_use(rm);
-        }
-        &Inst::FpuRRI { fpu_op, rd, rn, .. } => {
-            match fpu_op {
-                FPUOpRI::UShr32(..) | FPUOpRI::UShr64(..) => collector.add_def(rd),
-                FPUOpRI::Sli32(..) | FPUOpRI::Sli64(..) => collector.add_mod(rd),
-            }
-            collector.add_use(rn);
-        }
-        &Inst::FpuRRRR { rd, rn, rm, ra, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-            collector.add_use(rm);
-            collector.add_use(ra);
-        }
-        &Inst::VecMisc { rd, rn, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-        }
-
-        &Inst::VecLanes { rd, rn, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-        }
-        &Inst::VecShiftImm { rd, rn, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-        }
-        &Inst::VecExtract { rd, rn, rm, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-            collector.add_use(rm);
-        }
-        &Inst::VecTbl {
-            rd,
-            rn,
-            rm,
-            is_extension,
-        } => {
-            collector.add_use(rn);
-            collector.add_use(rm);
-
-            if is_extension {
-                collector.add_mod(rd);
-            } else {
-                collector.add_def(rd);
-            }
-        }
-        &Inst::VecTbl2 {
-            rd,
-            rn,
-            rn2,
-            rm,
-            is_extension,
-        } => {
-            collector.add_use(rn);
-            collector.add_use(rn2);
-            collector.add_use(rm);
-
-            if is_extension {
-                collector.add_mod(rd);
-            } else {
-                collector.add_def(rd);
-            }
-        }
-        &Inst::VecLoadReplicate { rd, rn, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-        }
-        &Inst::VecCSel { rd, rn, rm, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-            collector.add_use(rm);
-        }
-        &Inst::FpuCmp32 { rn, rm } | &Inst::FpuCmp64 { rn, rm } => {
-            collector.add_use(rn);
-            collector.add_use(rm);
-        }
-        &Inst::FpuLoad32 { rd, ref mem, .. } => {
-            collector.add_def(rd);
-            memarg_regs(mem, collector);
-        }
-        &Inst::FpuLoad64 { rd, ref mem, .. } => {
-            collector.add_def(rd);
-            memarg_regs(mem, collector);
-        }
-        &Inst::FpuLoad128 { rd, ref mem, .. } => {
-            collector.add_def(rd);
-            memarg_regs(mem, collector);
-        }
-        &Inst::FpuStore32 { rd, ref mem, .. } => {
-            collector.add_use(rd);
-            memarg_regs(mem, collector);
-        }
-        &Inst::FpuStore64 { rd, ref mem, .. } => {
-            collector.add_use(rd);
-            memarg_regs(mem, collector);
-        }
-        &Inst::FpuStore128 { rd, ref mem, .. } => {
-            collector.add_use(rd);
-            memarg_regs(mem, collector);
-        }
-        &Inst::FpuLoadP64 {
-            rt, rt2, ref mem, ..
-        } => {
-            collector.add_def(rt);
-            collector.add_def(rt2);
-            pairmemarg_regs(mem, collector);
-        }
-        &Inst::FpuStoreP64 {
-            rt, rt2, ref mem, ..
-        } => {
-            collector.add_use(rt);
-            collector.add_use(rt2);
-            pairmemarg_regs(mem, collector);
-        }
-        &Inst::FpuLoadP128 {
-            rt, rt2, ref mem, ..
-        } => {
-            collector.add_def(rt);
-            collector.add_def(rt2);
-            pairmemarg_regs(mem, collector);
-        }
-        &Inst::FpuStoreP128 {
-            rt, rt2, ref mem, ..
-        } => {
-            collector.add_use(rt);
-            collector.add_use(rt2);
-            pairmemarg_regs(mem, collector);
-        }
-        &Inst::LoadFpuConst64 { rd, .. } | &Inst::LoadFpuConst128 { rd, .. } => {
-            collector.add_def(rd);
-        }
-        &Inst::FpuToInt { rd, rn, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-        }
-        &Inst::IntToFpu { rd, rn, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-        }
-        &Inst::FpuCSel32 { rd, rn, rm, .. } | &Inst::FpuCSel64 { rd, rn, rm, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-            collector.add_use(rm);
-        }
-        &Inst::FpuRound { rd, rn, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-        }
-        &Inst::MovToFpu { rd, rn, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-        }
-        &Inst::FpuMoveFPImm { rd, .. } => {
-            collector.add_def(rd);
-        }
-        &Inst::MovToVec { rd, rn, .. } => {
-            collector.add_mod(rd);
-            collector.add_use(rn);
-        }
-        &Inst::MovFromVec { rd, rn, .. } | &Inst::MovFromVecSigned { rd, rn, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-        }
-        &Inst::VecDup { rd, rn, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-        }
-        &Inst::VecDupFromFpu { rd, rn, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-        }
-        &Inst::VecDupFPImm { rd, .. } => {
-            collector.add_def(rd);
-        }
-        &Inst::VecDupImm { rd, .. } => {
-            collector.add_def(rd);
-        }
-        &Inst::VecExtend { rd, rn, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-        }
-        &Inst::VecMovElement { rd, rn, .. } => {
-            collector.add_mod(rd);
-            collector.add_use(rn);
-        }
-        &Inst::VecRRLong { rd, rn, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-        }
-        &Inst::VecRRNarrow {
-            rd, rn, high_half, ..
-        } => {
-            collector.add_use(rn);
-
-            if high_half {
-                collector.add_mod(rd);
-            } else {
-                collector.add_def(rd);
-            }
-        }
-        &Inst::VecRRPair { rd, rn, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-        }
-        &Inst::VecRRRLong {
-            alu_op, rd, rn, rm, ..
-        } => {
-            match alu_op {
-                VecRRRLongOp::Umlal8 | VecRRRLongOp::Umlal16 | VecRRRLongOp::Umlal32 => {
-                    collector.add_mod(rd)
-                }
-                _ => collector.add_def(rd),
-            };
-            collector.add_use(rn);
-            collector.add_use(rm);
-        }
-        &Inst::VecRRPairLong { rd, rn, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-        }
-        &Inst::VecRRR {
-            alu_op, rd, rn, rm, ..
-        } => {
-            if alu_op == VecALUOp::Bsl {
-                collector.add_mod(rd);
-            } else {
-                collector.add_def(rd);
-            }
-            collector.add_use(rn);
-            collector.add_use(rm);
-        }
-        &Inst::MovToNZCV { rn } => {
-            collector.add_use(rn);
-        }
-        &Inst::MovFromNZCV { rd } => {
-            collector.add_def(rd);
-        }
-        &Inst::Extend { rd, rn, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-        }
-        &Inst::Jump { .. } | &Inst::Ret | &Inst::EpiloguePlaceholder => {}
-        &Inst::Call { ref info, .. } => {
-            collector.add_uses(&*info.uses);
-            collector.add_defs(&*info.defs);
-        }
-        &Inst::CallInd { ref info, .. } => {
-            collector.add_uses(&*info.uses);
-            collector.add_defs(&*info.defs);
-            collector.add_use(info.rn);
-        }
-        &Inst::CondBr { ref kind, .. } => match kind {
-            CondBrKind::Zero(rt) | CondBrKind::NotZero(rt) => {
-                collector.add_use(*rt);
-            }
-            CondBrKind::Cond(_) => {}
-        },
-        &Inst::IndirectBr { rn, .. } => {
-            collector.add_use(rn);
-        }
-        &Inst::Nop0 | Inst::Nop4 => {}
-        &Inst::Brk => {}
-        &Inst::Udf { .. } => {}
-        &Inst::TrapIf { ref kind, .. } => match kind {
-            CondBrKind::Zero(rt) | CondBrKind::NotZero(rt) => {
-                collector.add_use(*rt);
-            }
-            CondBrKind::Cond(_) => {}
-        },
-        &Inst::Adr { rd, .. } => {
-            collector.add_def(rd);
-        }
-        &Inst::Word4 { .. } | &Inst::Word8 { .. } => {}
-        &Inst::JTSequence {
-            ridx, rtmp1, rtmp2, ..
-        } => {
-            collector.add_use(ridx);
-            collector.add_def(rtmp1);
-            collector.add_def(rtmp2);
-        }
-        &Inst::LoadExtName { rd, .. } => {
-            collector.add_def(rd);
-        }
-        &Inst::LoadAddr { rd, ref mem } => {
-            collector.add_def(rd);
-            memarg_regs(mem, collector);
-        }
-        &Inst::VirtualSPOffsetAdj { .. } => {}
-        &Inst::ValueLabelMarker { reg, .. } => {
-            collector.add_use(reg);
-        }
-
-        &Inst::ElfTlsGetAddr { .. } => {
-            for reg in AArch64MachineDeps::get_regs_clobbered_by_call(CallConv::SystemV) {
-                collector.add_def(reg);
-            }
-        }
-        &Inst::Unwind { .. } => {}
-        &Inst::EmitIsland { .. } => {}
-    }
-}
-
-//=============================================================================
-// Instructions: map_regs
-
-pub fn aarch64_map_regs<RM: RegMapper>(inst: &mut Inst, mapper: &RM) {
-    fn map_mem<RM: RegMapper>(m: &RM, mem: &mut AMode) {
-        // N.B.: we take only the pre-map here, but this is OK because the
-        // only addressing modes that update registers (pre/post-increment on
-        // AArch64) both read and write registers, so they are "mods" rather
-        // than "defs", so must be the same in both the pre- and post-map.
-        match mem {
-            &mut AMode::Unscaled(ref mut reg, ..) => m.map_use(reg),
-            &mut AMode::UnsignedOffset(ref mut reg, ..) => m.map_use(reg),
-            &mut AMode::RegReg(ref mut r1, ref mut r2)
-            | &mut AMode::RegScaled(ref mut r1, ref mut r2, ..)
-            | &mut AMode::RegScaledExtended(ref mut r1, ref mut r2, ..)
-            | &mut AMode::RegExtended(ref mut r1, ref mut r2, ..) => {
-                m.map_use(r1);
-                m.map_use(r2);
-            }
-            &mut AMode::Label(..) => {}
-            &mut AMode::PreIndexed(ref mut r, ..) => m.map_mod(r),
-            &mut AMode::PostIndexed(ref mut r, ..) => m.map_mod(r),
-            &mut AMode::FPOffset(..)
-            | &mut AMode::SPOffset(..)
-            | &mut AMode::NominalSPOffset(..) => {}
-            &mut AMode::RegOffset(ref mut r, ..) => m.map_use(r),
-        };
-    }
-
-    fn map_pairmem<RM: RegMapper>(m: &RM, mem: &mut PairAMode) {
-        match mem {
-            &mut PairAMode::SignedOffset(ref mut reg, ..) => m.map_use(reg),
-            &mut PairAMode::PreIndexed(ref mut reg, ..) => m.map_def(reg),
-            &mut PairAMode::PostIndexed(ref mut reg, ..) => m.map_def(reg),
-        }
-    }
-
-    fn map_br<RM: RegMapper>(m: &RM, br: &mut CondBrKind) {
-        match br {
-            &mut CondBrKind::Zero(ref mut reg) => m.map_use(reg),
-            &mut CondBrKind::NotZero(ref mut reg) => m.map_use(reg),
-            &mut CondBrKind::Cond(..) => {}
-        };
-    }
-
-    match inst {
-        &mut Inst::AluRRR {
-            ref mut rd,
-            ref mut rn,
-            ref mut rm,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-            mapper.map_use(rm);
-        }
-        &mut Inst::AluRRRR {
-            ref mut rd,
-            ref mut rn,
-            ref mut rm,
-            ref mut ra,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-            mapper.map_use(rm);
-            mapper.map_use(ra);
-        }
-        &mut Inst::AluRRImm12 {
-            ref mut rd,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::AluRRImmLogic {
-            ref mut rd,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::AluRRImmShift {
-            ref mut rd,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::AluRRRShift {
-            ref mut rd,
-            ref mut rn,
-            ref mut rm,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-            mapper.map_use(rm);
-        }
-        &mut Inst::AluRRRExtend {
-            ref mut rd,
-            ref mut rn,
-            ref mut rm,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-            mapper.map_use(rm);
-        }
-        &mut Inst::BitRR {
-            ref mut rd,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::ULoad8 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_def(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::SLoad8 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_def(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::ULoad16 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_def(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::SLoad16 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_def(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::ULoad32 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_def(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::SLoad32 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_def(rd);
-            map_mem(mapper, mem);
-        }
-
-        &mut Inst::ULoad64 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_def(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::Store8 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_use(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::Store16 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_use(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::Store32 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_use(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::Store64 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_use(rd);
-            map_mem(mapper, mem);
-        }
-
-        &mut Inst::StoreP64 {
-            ref mut rt,
-            ref mut rt2,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_use(rt);
-            mapper.map_use(rt2);
-            map_pairmem(mapper, mem);
-        }
-        &mut Inst::LoadP64 {
-            ref mut rt,
-            ref mut rt2,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_def(rt);
-            mapper.map_def(rt2);
-            map_pairmem(mapper, mem);
-        }
-        &mut Inst::Mov64 {
-            ref mut rd,
-            ref mut rm,
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rm);
-        }
-        &mut Inst::Mov32 {
-            ref mut rd,
-            ref mut rm,
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rm);
-        }
-        &mut Inst::MovZ { ref mut rd, .. } => {
-            mapper.map_def(rd);
-        }
-        &mut Inst::MovN { ref mut rd, .. } => {
-            mapper.map_def(rd);
-        }
-        &mut Inst::MovK { ref mut rd, .. } => {
-            mapper.map_def(rd);
-        }
-        &mut Inst::CSel {
-            ref mut rd,
-            ref mut rn,
-            ref mut rm,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-            mapper.map_use(rm);
-        }
-        &mut Inst::CSet { ref mut rd, .. } | &mut Inst::CSetm { ref mut rd, .. } => {
-            mapper.map_def(rd);
-        }
-        &mut Inst::CCmpImm { ref mut rn, .. } => {
-            mapper.map_use(rn);
-        }
-        &mut Inst::AtomicRMWLoop { .. } => {
-            // There are no vregs to map in this insn.
-        }
-        &mut Inst::AtomicRMW {
-            ref mut rs,
-            ref mut rt,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_use(rs);
-            mapper.map_def(rt);
-            mapper.map_use(rn);
-        }
-        &mut Inst::AtomicCAS {
-            ref mut rs,
-            ref mut rt,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_mod(rs);
-            mapper.map_use(rt);
-            mapper.map_use(rn);
-        }
-        &mut Inst::AtomicCASLoop { .. } => {
-            // There are no vregs to map in this insn.
-        }
-        &mut Inst::LoadAcquire {
-            ref mut rt,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_def(rt);
-            mapper.map_use(rn);
-        }
-        &mut Inst::StoreRelease {
-            ref mut rt,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_use(rt);
-            mapper.map_use(rn);
-        }
-        &mut Inst::Fence {} => {}
-        &mut Inst::FpuMove64 {
-            ref mut rd,
-            ref mut rn,
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::FpuMove128 {
-            ref mut rd,
-            ref mut rn,
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::FpuMoveFromVec {
-            ref mut rd,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::FpuExtend {
-            ref mut rd,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::FpuRR {
-            ref mut rd,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::FpuRRR {
-            ref mut rd,
-            ref mut rn,
-            ref mut rm,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-            mapper.map_use(rm);
-        }
-        &mut Inst::FpuRRI {
-            fpu_op,
-            ref mut rd,
-            ref mut rn,
-            ..
-        } => {
-            match fpu_op {
-                FPUOpRI::UShr32(..) | FPUOpRI::UShr64(..) => mapper.map_def(rd),
-                FPUOpRI::Sli32(..) | FPUOpRI::Sli64(..) => mapper.map_mod(rd),
-            }
-            mapper.map_use(rn);
-        }
-        &mut Inst::FpuRRRR {
-            ref mut rd,
-            ref mut rn,
-            ref mut rm,
-            ref mut ra,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-            mapper.map_use(rm);
-            mapper.map_use(ra);
-        }
-        &mut Inst::VecMisc {
-            ref mut rd,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::VecLanes {
-            ref mut rd,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::VecShiftImm {
-            ref mut rd,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::VecExtract {
-            ref mut rd,
-            ref mut rn,
-            ref mut rm,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-            mapper.map_use(rm);
-        }
-        &mut Inst::VecTbl {
-            ref mut rd,
-            ref mut rn,
-            ref mut rm,
-            is_extension,
-        } => {
-            mapper.map_use(rn);
-            mapper.map_use(rm);
-
-            if is_extension {
-                mapper.map_mod(rd);
-            } else {
-                mapper.map_def(rd);
-            }
-        }
-        &mut Inst::VecTbl2 {
-            ref mut rd,
-            ref mut rn,
-            ref mut rn2,
-            ref mut rm,
-            is_extension,
-        } => {
-            mapper.map_use(rn);
-            mapper.map_use(rn2);
-            mapper.map_use(rm);
-
-            if is_extension {
-                mapper.map_mod(rd);
-            } else {
-                mapper.map_def(rd);
-            }
-        }
-        &mut Inst::VecLoadReplicate {
-            ref mut rd,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::VecCSel {
-            ref mut rd,
-            ref mut rn,
-            ref mut rm,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-            mapper.map_use(rm);
-        }
-        &mut Inst::FpuCmp32 {
-            ref mut rn,
-            ref mut rm,
-        } => {
-            mapper.map_use(rn);
-            mapper.map_use(rm);
-        }
-        &mut Inst::FpuCmp64 {
-            ref mut rn,
-            ref mut rm,
-        } => {
-            mapper.map_use(rn);
-            mapper.map_use(rm);
-        }
-        &mut Inst::FpuLoad32 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_def(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::FpuLoad64 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_def(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::FpuLoad128 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_def(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::FpuStore32 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_use(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::FpuStore64 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_use(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::FpuStore128 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_use(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::FpuLoadP64 {
-            ref mut rt,
-            ref mut rt2,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_def(rt);
-            mapper.map_def(rt2);
-            map_pairmem(mapper, mem);
-        }
-        &mut Inst::FpuStoreP64 {
-            ref mut rt,
-            ref mut rt2,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_use(rt);
-            mapper.map_use(rt2);
-            map_pairmem(mapper, mem);
-        }
-        &mut Inst::FpuLoadP128 {
-            ref mut rt,
-            ref mut rt2,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_def(rt);
-            mapper.map_def(rt2);
-            map_pairmem(mapper, mem);
-        }
-        &mut Inst::FpuStoreP128 {
-            ref mut rt,
-            ref mut rt2,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_use(rt);
-            mapper.map_use(rt2);
-            map_pairmem(mapper, mem);
-        }
-        &mut Inst::LoadFpuConst64 { ref mut rd, .. } => {
-            mapper.map_def(rd);
-        }
-        &mut Inst::LoadFpuConst128 { ref mut rd, .. } => {
-            mapper.map_def(rd);
-        }
-        &mut Inst::FpuToInt {
-            ref mut rd,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::IntToFpu {
-            ref mut rd,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::FpuCSel32 {
-            ref mut rd,
-            ref mut rn,
-            ref mut rm,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-            mapper.map_use(rm);
-        }
-        &mut Inst::FpuCSel64 {
-            ref mut rd,
-            ref mut rn,
-            ref mut rm,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-            mapper.map_use(rm);
-        }
-        &mut Inst::FpuRound {
-            ref mut rd,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::MovToFpu {
-            ref mut rd,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::FpuMoveFPImm { ref mut rd, .. } => {
-            mapper.map_def(rd);
-        }
-        &mut Inst::MovToVec {
-            ref mut rd,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_mod(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::MovFromVec {
-            ref mut rd,
-            ref mut rn,
-            ..
-        }
-        | &mut Inst::MovFromVecSigned {
-            ref mut rd,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::VecDup {
-            ref mut rd,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::VecDupFromFpu {
-            ref mut rd,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::VecDupFPImm { ref mut rd, .. } => {
-            mapper.map_def(rd);
-        }
-        &mut Inst::VecDupImm { ref mut rd, .. } => {
-            mapper.map_def(rd);
-        }
-        &mut Inst::VecExtend {
-            ref mut rd,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::VecMovElement {
-            ref mut rd,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_mod(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::VecRRLong {
-            ref mut rd,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::VecRRNarrow {
-            ref mut rd,
-            ref mut rn,
-            high_half,
-            ..
-        } => {
-            mapper.map_use(rn);
-
-            if high_half {
-                mapper.map_mod(rd);
-            } else {
-                mapper.map_def(rd);
-            }
-        }
-        &mut Inst::VecRRPair {
-            ref mut rd,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::VecRRRLong {
-            alu_op,
-            ref mut rd,
-            ref mut rn,
-            ref mut rm,
-            ..
-        } => {
-            match alu_op {
-                VecRRRLongOp::Umlal8 | VecRRRLongOp::Umlal16 | VecRRRLongOp::Umlal32 => {
-                    mapper.map_mod(rd)
-                }
-                _ => mapper.map_def(rd),
-            };
-            mapper.map_use(rn);
-            mapper.map_use(rm);
-        }
-        &mut Inst::VecRRPairLong {
-            ref mut rd,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::VecRRR {
-            alu_op,
-            ref mut rd,
-            ref mut rn,
-            ref mut rm,
-            ..
-        } => {
-            if alu_op == VecALUOp::Bsl {
-                mapper.map_mod(rd);
-            } else {
-                mapper.map_def(rd);
-            }
-            mapper.map_use(rn);
-            mapper.map_use(rm);
-        }
-        &mut Inst::MovToNZCV { ref mut rn } => {
-            mapper.map_use(rn);
-        }
-        &mut Inst::MovFromNZCV { ref mut rd } => {
-            mapper.map_def(rd);
-        }
-        &mut Inst::Extend {
-            ref mut rd,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::Jump { .. } => {}
-        &mut Inst::Call { ref mut info } => {
-            for r in info.uses.iter_mut() {
-                mapper.map_use(r);
-            }
-            for r in info.defs.iter_mut() {
-                mapper.map_def(r);
-            }
-        }
-        &mut Inst::Ret | &mut Inst::EpiloguePlaceholder => {}
-        &mut Inst::CallInd { ref mut info, .. } => {
-            for r in info.uses.iter_mut() {
-                mapper.map_use(r);
-            }
-            for r in info.defs.iter_mut() {
-                mapper.map_def(r);
-            }
-            mapper.map_use(&mut info.rn);
-        }
-        &mut Inst::CondBr { ref mut kind, .. } => {
-            map_br(mapper, kind);
-        }
-        &mut Inst::IndirectBr { ref mut rn, .. } => {
-            mapper.map_use(rn);
-        }
-        &mut Inst::Nop0 | &mut Inst::Nop4 | &mut Inst::Brk | &mut Inst::Udf { .. } => {}
-        &mut Inst::TrapIf { ref mut kind, .. } => {
-            map_br(mapper, kind);
-        }
-        &mut Inst::Adr { ref mut rd, .. } => {
-            mapper.map_def(rd);
-        }
-        &mut Inst::Word4 { .. } | &mut Inst::Word8 { .. } => {}
-        &mut Inst::JTSequence {
-            ref mut ridx,
-            ref mut rtmp1,
-            ref mut rtmp2,
-            ..
-        } => {
-            mapper.map_use(ridx);
-            mapper.map_def(rtmp1);
-            mapper.map_def(rtmp2);
-        }
-        &mut Inst::LoadExtName { ref mut rd, .. } => {
-            mapper.map_def(rd);
-        }
-        &mut Inst::LoadAddr {
-            ref mut rd,
-            ref mut mem,
-        } => {
-            mapper.map_def(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::VirtualSPOffsetAdj { .. } => {}
-        &mut Inst::EmitIsland { .. } => {}
-        &mut Inst::ElfTlsGetAddr { .. } => {}
-        &mut Inst::ValueLabelMarker { ref mut reg, .. } => {
-            mapper.map_use(reg);
-        }
-        &mut Inst::Unwind { .. } => {}
-    }
-}
-
-//=============================================================================
-// Instructions: misc functions and external interface
-
-impl MachInst for Inst {
-    type LabelUse = LabelUse;
-
-    fn get_regs(&self, collector: &mut RegUsageCollector) {
-        aarch64_get_regs(self, collector)
-    }
-
-    fn map_regs<RM: RegMapper>(&mut self, mapper: &RM) {
-        aarch64_map_regs(self, mapper);
-    }
-
-    fn is_move(&self) -> Option<(Writable<Reg>, Reg)> {
-        match self {
-            &Inst::Mov64 { rd, rm } => Some((rd, rm)),
-            &Inst::FpuMove64 { rd, rn } => Some((rd, rn)),
-            &Inst::FpuMove128 { rd, rn } => Some((rd, rn)),
-            _ => None,
-        }
-    }
-
-    fn is_epilogue_placeholder(&self) -> bool {
-        if let Inst::EpiloguePlaceholder = self {
-            true
-        } else {
-            false
-        }
-    }
-
-    fn is_included_in_clobbers(&self) -> bool {
-        // We exclude call instructions from the clobber-set when they are calls
-        // from caller to callee with the same ABI. Such calls cannot possibly
-        // force any new registers to be saved in the prologue, because anything
-        // that the callee clobbers, the caller is also allowed to clobber. This
-        // both saves work and enables us to more precisely follow the
-        // half-caller-save, half-callee-save SysV ABI for some vector
-        // registers.
-        //
-        // See the note in [crate::isa::aarch64::abi::is_caller_save_reg] for
-        // more information on this ABI-implementation hack.
-        match self {
-            &Inst::Call { ref info } => info.caller_callconv != info.callee_callconv,
-            &Inst::CallInd { ref info } => info.caller_callconv != info.callee_callconv,
-            _ => true,
-        }
-    }
-
-    fn is_term<'a>(&'a self) -> MachTerminator<'a> {
-        match self {
-            &Inst::Ret | &Inst::EpiloguePlaceholder => MachTerminator::Ret,
-            &Inst::Jump { dest } => MachTerminator::Uncond(dest.as_label().unwrap()),
-            &Inst::CondBr {
-                taken, not_taken, ..
-            } => MachTerminator::Cond(taken.as_label().unwrap(), not_taken.as_label().unwrap()),
-            &Inst::IndirectBr { ref targets, .. } => MachTerminator::Indirect(&targets[..]),
-            &Inst::JTSequence { ref info, .. } => {
-                MachTerminator::Indirect(&info.targets_for_term[..])
-            }
-            _ => MachTerminator::None,
-        }
-    }
-
-    fn gen_move(to_reg: Writable<Reg>, from_reg: Reg, ty: Type) -> Inst {
-        let bits = ty.bits();
-
-        assert!(bits <= 128);
-        assert!(to_reg.to_reg().get_class() == from_reg.get_class());
-
-        if from_reg.get_class() == RegClass::I64 {
-            Inst::Mov64 {
-                rd: to_reg,
-                rm: from_reg,
-            }
-        } else if from_reg.get_class() == RegClass::V128 {
-            if bits > 64 {
-                Inst::FpuMove128 {
-                    rd: to_reg,
-                    rn: from_reg,
-                }
-            } else {
-                Inst::FpuMove64 {
-                    rd: to_reg,
-                    rn: from_reg,
-                }
-            }
-        } else {
-            panic!("Unexpected register class: {:?}", from_reg.get_class());
-        }
-    }
-
-    fn gen_constant<F: FnMut(Type) -> Writable<Reg>>(
-        to_regs: ValueRegs<Writable<Reg>>,
-        value: u128,
-        ty: Type,
-        alloc_tmp: F,
-    ) -> SmallVec<[Inst; 4]> {
-        let to_reg = to_regs.only_reg();
-        match ty {
-            F64 => Inst::load_fp_constant64(to_reg.unwrap(), value as u64, alloc_tmp),
-            F32 => Inst::load_fp_constant32(to_reg.unwrap(), value as u32, alloc_tmp),
-            B1 | B8 | B16 | B32 | B64 | I8 | I16 | I32 | I64 | R32 | R64 => {
-                Inst::load_constant(to_reg.unwrap(), value as u64)
-            }
-            I128 => Inst::load_constant128(to_regs, value),
-            _ => panic!("Cannot generate constant for type: {}", ty),
-        }
-    }
-
-    fn gen_nop(preferred_size: usize) -> Inst {
-        if preferred_size == 0 {
-            return Inst::Nop0;
-        }
-        // We can't give a NOP (or any insn) < 4 bytes.
-        assert!(preferred_size >= 4);
-        Inst::Nop4
-    }
-
-    fn maybe_direct_reload(&self, _reg: VirtualReg, _slot: SpillSlot) -> Option<Inst> {
-        None
-    }
-
-    fn rc_for_type(ty: Type) -> CodegenResult<(&'static [RegClass], &'static [Type])> {
-        match ty {
-            I8 => Ok((&[RegClass::I64], &[I8])),
-            I16 => Ok((&[RegClass::I64], &[I16])),
-            I32 => Ok((&[RegClass::I64], &[I32])),
-            I64 => Ok((&[RegClass::I64], &[I64])),
-            B1 => Ok((&[RegClass::I64], &[B1])),
-            B8 => Ok((&[RegClass::I64], &[B8])),
-            B16 => Ok((&[RegClass::I64], &[B16])),
-            B32 => Ok((&[RegClass::I64], &[B32])),
-            B64 => Ok((&[RegClass::I64], &[B64])),
-            R32 => panic!("32-bit reftype pointer should never be seen on AArch64"),
-            R64 => Ok((&[RegClass::I64], &[R64])),
-            F32 => Ok((&[RegClass::V128], &[F32])),
-            F64 => Ok((&[RegClass::V128], &[F64])),
-            I128 => Ok((&[RegClass::I64, RegClass::I64], &[I64, I64])),
-            B128 => Ok((&[RegClass::I64, RegClass::I64], &[B64, B64])),
-            _ if ty.is_vector() => {
-                assert!(ty.bits() <= 128);
-                Ok((&[RegClass::V128], &[I8X16]))
-            }
-            IFLAGS | FFLAGS => Ok((&[RegClass::I64], &[I64])),
-            _ => Err(CodegenError::Unsupported(format!(
-                "Unexpected SSA-value type: {}",
-                ty
-            ))),
-        }
-    }
-
-    fn gen_jump(target: MachLabel) -> Inst {
-        Inst::Jump {
-            dest: BranchTarget::Label(target),
-        }
-    }
-
-    fn worst_case_size() -> CodeOffset {
-        // The maximum size, in bytes, of any `Inst`'s emitted code. We have at least one case of
-        // an 8-instruction sequence (saturating int-to-float conversions) with three embedded
-        // 64-bit f64 constants.
-        //
-        // Note that inline jump-tables handle island/pool insertion separately, so we do not need
-        // to account for them here (otherwise the worst case would be 2^31 * 4, clearly not
-        // feasible for other reasons).
-        44
-    }
-
-    fn ref_type_regclass(_: &settings::Flags) -> RegClass {
-        RegClass::I64
-    }
-
-    fn gen_value_label_marker(label: ValueLabel, reg: Reg) -> Self {
-        Inst::ValueLabelMarker { label, reg }
-    }
-
-    fn defines_value_label(&self) -> Option<(ValueLabel, Reg)> {
-        match self {
-            Inst::ValueLabelMarker { label, reg } => Some((*label, *reg)),
-            _ => None,
-        }
-    }
-}
-
-//=============================================================================
-// Pretty-printing of instructions.
-
-fn mem_finalize_for_show(
-    mem: &AMode,
-    mb_rru: Option<&RealRegUniverse>,
-    state: &EmitState,
-) -> (String, AMode) {
-    let (mem_insts, mem) = mem_finalize(0, mem, state);
-    let mut mem_str = mem_insts
-        .into_iter()
-        .map(|inst| inst.show_rru(mb_rru))
-        .collect::<Vec<_>>()
-        .join(" ; ");
-    if !mem_str.is_empty() {
-        mem_str += " ; ";
-    }
-
-    (mem_str, mem)
-}
-
-impl PrettyPrint for Inst {
-    fn show_rru(&self, mb_rru: Option<&RealRegUniverse>) -> String {
-        self.pretty_print(mb_rru, &mut EmitState::default())
-    }
-}
-
-impl Inst {
-    fn print_with_state(&self, mb_rru: Option<&RealRegUniverse>, state: &mut EmitState) -> String {
-        fn op_name(alu_op: ALUOp) -> &'static str {
-            match alu_op {
-                ALUOp::Add => "add",
-                ALUOp::Sub => "sub",
-                ALUOp::Orr => "orr",
-                ALUOp::And => "and",
-                ALUOp::AndS => "ands",
-                ALUOp::Eor => "eor",
-                ALUOp::AddS => "adds",
-                ALUOp::SubS => "subs",
-                ALUOp::SMulH => "smulh",
-                ALUOp::UMulH => "umulh",
-                ALUOp::SDiv => "sdiv",
-                ALUOp::UDiv => "udiv",
-                ALUOp::AndNot => "bic",
-                ALUOp::OrrNot => "orn",
-                ALUOp::EorNot => "eon",
-                ALUOp::RotR => "ror",
-                ALUOp::Lsr => "lsr",
-                ALUOp::Asr => "asr",
-                ALUOp::Lsl => "lsl",
-                ALUOp::Adc => "adc",
-                ALUOp::AdcS => "adcs",
-                ALUOp::Sbc => "sbc",
-                ALUOp::SbcS => "sbcs",
-            }
-        }
-
-        match self {
-            &Inst::Nop0 => "nop-zero-len".to_string(),
-            &Inst::Nop4 => "nop".to_string(),
-            &Inst::AluRRR {
-                alu_op,
-                size,
-                rd,
-                rn,
-                rm,
-            } => {
-                let op = op_name(alu_op);
-                let rd = show_ireg_sized(rd.to_reg(), mb_rru, size);
-                let rn = show_ireg_sized(rn, mb_rru, size);
-                let rm = show_ireg_sized(rm, mb_rru, size);
-                format!("{} {}, {}, {}", op, rd, rn, rm)
-            }
-            &Inst::AluRRRR {
-                alu_op,
-                rd,
-                rn,
-                rm,
-                ra,
-            } => {
-                let (op, size) = match alu_op {
-                    ALUOp3::MAdd32 => ("madd", OperandSize::Size32),
-                    ALUOp3::MAdd64 => ("madd", OperandSize::Size64),
-                    ALUOp3::MSub32 => ("msub", OperandSize::Size32),
-                    ALUOp3::MSub64 => ("msub", OperandSize::Size64),
-                };
-                let rd = show_ireg_sized(rd.to_reg(), mb_rru, size);
-                let rn = show_ireg_sized(rn, mb_rru, size);
-                let rm = show_ireg_sized(rm, mb_rru, size);
-                let ra = show_ireg_sized(ra, mb_rru, size);
-
-                format!("{} {}, {}, {}, {}", op, rd, rn, rm, ra)
-            }
-            &Inst::AluRRImm12 {
-                alu_op,
-                size,
-                rd,
-                rn,
-                ref imm12,
-            } => {
-                let op = op_name(alu_op);
-                let rd = show_ireg_sized(rd.to_reg(), mb_rru, size);
-                let rn = show_ireg_sized(rn, mb_rru, size);
-
-                if imm12.bits == 0 && alu_op == ALUOp::Add && size.is64() {
-                    // special-case MOV (used for moving into SP).
-                    format!("mov {}, {}", rd, rn)
-                } else {
-                    let imm12 = imm12.show_rru(mb_rru);
-                    format!("{} {}, {}, {}", op, rd, rn, imm12)
-                }
-            }
-            &Inst::AluRRImmLogic {
-                alu_op,
-                size,
-                rd,
-                rn,
-                ref imml,
-            } => {
-                let op = op_name(alu_op);
-                let rd = show_ireg_sized(rd.to_reg(), mb_rru, size);
-                let rn = show_ireg_sized(rn, mb_rru, size);
-                let imml = imml.show_rru(mb_rru);
-                format!("{} {}, {}, {}", op, rd, rn, imml)
-            }
-            &Inst::AluRRImmShift {
-                alu_op,
-                size,
-                rd,
-                rn,
-                ref immshift,
-            } => {
-                let op = op_name(alu_op);
-                let rd = show_ireg_sized(rd.to_reg(), mb_rru, size);
-                let rn = show_ireg_sized(rn, mb_rru, size);
-                let immshift = immshift.show_rru(mb_rru);
-                format!("{} {}, {}, {}", op, rd, rn, immshift)
-            }
-            &Inst::AluRRRShift {
-                alu_op,
-                size,
-                rd,
-                rn,
-                rm,
-                ref shiftop,
-            } => {
-                let op = op_name(alu_op);
-                let rd = show_ireg_sized(rd.to_reg(), mb_rru, size);
-                let rn = show_ireg_sized(rn, mb_rru, size);
-                let rm = show_ireg_sized(rm, mb_rru, size);
-                let shiftop = shiftop.show_rru(mb_rru);
-                format!("{} {}, {}, {}, {}", op, rd, rn, rm, shiftop)
-            }
-            &Inst::AluRRRExtend {
-                alu_op,
-                size,
-                rd,
-                rn,
-                rm,
-                ref extendop,
-            } => {
-                let op = op_name(alu_op);
-                let rd = show_ireg_sized(rd.to_reg(), mb_rru, size);
-                let rn = show_ireg_sized(rn, mb_rru, size);
-                let rm = show_ireg_sized(rm, mb_rru, size);
-                let extendop = extendop.show_rru(mb_rru);
-                format!("{} {}, {}, {}, {}", op, rd, rn, rm, extendop)
-            }
-            &Inst::BitRR { op, size, rd, rn } => {
-                let op = op.op_str();
-                let rd = show_ireg_sized(rd.to_reg(), mb_rru, size);
-                let rn = show_ireg_sized(rn, mb_rru, size);
-                format!("{} {}, {}", op, rd, rn)
-            }
-            &Inst::ULoad8 { rd, ref mem, .. }
-            | &Inst::SLoad8 { rd, ref mem, .. }
-            | &Inst::ULoad16 { rd, ref mem, .. }
-            | &Inst::SLoad16 { rd, ref mem, .. }
-            | &Inst::ULoad32 { rd, ref mem, .. }
-            | &Inst::SLoad32 { rd, ref mem, .. }
-            | &Inst::ULoad64 { rd, ref mem, .. } => {
-                let (mem_str, mem) = mem_finalize_for_show(mem, mb_rru, state);
-
-                let is_unscaled = match &mem {
-                    &AMode::Unscaled(..) => true,
-                    _ => false,
-                };
-                let (op, size) = match (self, is_unscaled) {
-                    (&Inst::ULoad8 { .. }, false) => ("ldrb", OperandSize::Size32),
-                    (&Inst::ULoad8 { .. }, true) => ("ldurb", OperandSize::Size32),
-                    (&Inst::SLoad8 { .. }, false) => ("ldrsb", OperandSize::Size64),
-                    (&Inst::SLoad8 { .. }, true) => ("ldursb", OperandSize::Size64),
-                    (&Inst::ULoad16 { .. }, false) => ("ldrh", OperandSize::Size32),
-                    (&Inst::ULoad16 { .. }, true) => ("ldurh", OperandSize::Size32),
-                    (&Inst::SLoad16 { .. }, false) => ("ldrsh", OperandSize::Size64),
-                    (&Inst::SLoad16 { .. }, true) => ("ldursh", OperandSize::Size64),
-                    (&Inst::ULoad32 { .. }, false) => ("ldr", OperandSize::Size32),
-                    (&Inst::ULoad32 { .. }, true) => ("ldur", OperandSize::Size32),
-                    (&Inst::SLoad32 { .. }, false) => ("ldrsw", OperandSize::Size64),
-                    (&Inst::SLoad32 { .. }, true) => ("ldursw", OperandSize::Size64),
-                    (&Inst::ULoad64 { .. }, false) => ("ldr", OperandSize::Size64),
-                    (&Inst::ULoad64 { .. }, true) => ("ldur", OperandSize::Size64),
-                    _ => unreachable!(),
-                };
-                let rd = show_ireg_sized(rd.to_reg(), mb_rru, size);
-                let mem = mem.show_rru(mb_rru);
-                format!("{}{} {}, {}", mem_str, op, rd, mem)
-            }
-            &Inst::Store8 { rd, ref mem, .. }
-            | &Inst::Store16 { rd, ref mem, .. }
-            | &Inst::Store32 { rd, ref mem, .. }
-            | &Inst::Store64 { rd, ref mem, .. } => {
-                let (mem_str, mem) = mem_finalize_for_show(mem, mb_rru, state);
-
-                let is_unscaled = match &mem {
-                    &AMode::Unscaled(..) => true,
-                    _ => false,
-                };
-                let (op, size) = match (self, is_unscaled) {
-                    (&Inst::Store8 { .. }, false) => ("strb", OperandSize::Size32),
-                    (&Inst::Store8 { .. }, true) => ("sturb", OperandSize::Size32),
-                    (&Inst::Store16 { .. }, false) => ("strh", OperandSize::Size32),
-                    (&Inst::Store16 { .. }, true) => ("sturh", OperandSize::Size32),
-                    (&Inst::Store32 { .. }, false) => ("str", OperandSize::Size32),
-                    (&Inst::Store32 { .. }, true) => ("stur", OperandSize::Size32),
-                    (&Inst::Store64 { .. }, false) => ("str", OperandSize::Size64),
-                    (&Inst::Store64 { .. }, true) => ("stur", OperandSize::Size64),
-                    _ => unreachable!(),
-                };
-                let rd = show_ireg_sized(rd, mb_rru, size);
-                let mem = mem.show_rru(mb_rru);
-                format!("{}{} {}, {}", mem_str, op, rd, mem)
-            }
-            &Inst::StoreP64 {
-                rt, rt2, ref mem, ..
-            } => {
-                let rt = rt.show_rru(mb_rru);
-                let rt2 = rt2.show_rru(mb_rru);
-                let mem = mem.show_rru(mb_rru);
-                format!("stp {}, {}, {}", rt, rt2, mem)
-            }
-            &Inst::LoadP64 {
-                rt, rt2, ref mem, ..
-            } => {
-                let rt = rt.to_reg().show_rru(mb_rru);
-                let rt2 = rt2.to_reg().show_rru(mb_rru);
-                let mem = mem.show_rru(mb_rru);
-                format!("ldp {}, {}, {}", rt, rt2, mem)
-            }
-            &Inst::Mov64 { rd, rm } => {
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let rm = rm.show_rru(mb_rru);
-                format!("mov {}, {}", rd, rm)
-            }
-            &Inst::Mov32 { rd, rm } => {
-                let rd = show_ireg_sized(rd.to_reg(), mb_rru, OperandSize::Size32);
-                let rm = show_ireg_sized(rm, mb_rru, OperandSize::Size32);
-                format!("mov {}, {}", rd, rm)
-            }
-            &Inst::MovZ { rd, ref imm, size } => {
-                let rd = show_ireg_sized(rd.to_reg(), mb_rru, size);
-                let imm = imm.show_rru(mb_rru);
-                format!("movz {}, {}", rd, imm)
-            }
-            &Inst::MovN { rd, ref imm, size } => {
-                let rd = show_ireg_sized(rd.to_reg(), mb_rru, size);
-                let imm = imm.show_rru(mb_rru);
-                format!("movn {}, {}", rd, imm)
-            }
-            &Inst::MovK { rd, ref imm, size } => {
-                let rd = show_ireg_sized(rd.to_reg(), mb_rru, size);
-                let imm = imm.show_rru(mb_rru);
-                format!("movk {}, {}", rd, imm)
-            }
-            &Inst::CSel { rd, rn, rm, cond } => {
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let rn = rn.show_rru(mb_rru);
-                let rm = rm.show_rru(mb_rru);
-                let cond = cond.show_rru(mb_rru);
-                format!("csel {}, {}, {}, {}", rd, rn, rm, cond)
-            }
-            &Inst::CSet { rd, cond } => {
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let cond = cond.show_rru(mb_rru);
-                format!("cset {}, {}", rd, cond)
-            }
-            &Inst::CSetm { rd, cond } => {
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let cond = cond.show_rru(mb_rru);
-                format!("csetm {}, {}", rd, cond)
-            }
-            &Inst::CCmpImm {
-                size,
-                rn,
-                imm,
-                nzcv,
-                cond,
-            } => {
-                let rn = show_ireg_sized(rn, mb_rru, size);
-                let imm = imm.show_rru(mb_rru);
-                let nzcv = nzcv.show_rru(mb_rru);
-                let cond = cond.show_rru(mb_rru);
-                format!("ccmp {}, {}, {}, {}", rn, imm, nzcv, cond)
-            }
-            &Inst::AtomicRMW { rs, rt, rn, ty, op } => {
-                let op = match op {
-                    AtomicRMWOp::Add => "ldaddal",
-                    AtomicRMWOp::Clr => "ldclral",
-                    AtomicRMWOp::Eor => "ldeoral",
-                    AtomicRMWOp::Set => "ldsetal",
-                    AtomicRMWOp::Smax => "ldsmaxal",
-                    AtomicRMWOp::Umax => "ldumaxal",
-                    AtomicRMWOp::Smin => "ldsminal",
-                    AtomicRMWOp::Umin => "lduminal",
-                };
-
-                let size = OperandSize::from_ty(ty);
-                let rs = show_ireg_sized(rs, mb_rru, size);
-                let rt = show_ireg_sized(rt.to_reg(), mb_rru, size);
-                let rn = rn.show_rru(mb_rru);
-
-                let ty_suffix = match ty {
-                    I8 => "b",
-                    I16 => "h",
-                    _ => "",
-                };
-                format!("{}{} {}, {}, [{}]", op, ty_suffix, rs, rt, rn)
-            }
-            &Inst::AtomicRMWLoop { ty, op, .. } => {
-                let ty_suffix = match ty {
-                    I8 => "b",
-                    I16 => "h",
-                    _ => "",
-                };
-                let size = OperandSize::from_ty(ty);
-                let r_status = show_ireg_sized(xreg(24), mb_rru, OperandSize::Size32);
-                let r_arg2 = show_ireg_sized(xreg(26), mb_rru, size);
-                let r_tmp = show_ireg_sized(xreg(27), mb_rru, size);
-                let mut r_dst = show_ireg_sized(xreg(28), mb_rru, size);
-
-                let mut loop_str: String = "1: ".to_string();
-                loop_str.push_str(&format!("ldaxr{} {}, [x25]; ", ty_suffix, r_tmp));
-
-                let op_str = match op {
-                    inst_common::AtomicRmwOp::Add => "add",
-                    inst_common::AtomicRmwOp::Sub => "sub",
-                    inst_common::AtomicRmwOp::Xor => "eor",
-                    inst_common::AtomicRmwOp::Or => "orr",
-                    inst_common::AtomicRmwOp::And => "and",
-                    _ => "",
-                };
-
-                if op_str.is_empty() {
-                    match op {
-                        inst_common::AtomicRmwOp::Xchg => r_dst = r_arg2,
-                        inst_common::AtomicRmwOp::Nand => {
-                            loop_str.push_str(&format!("and {}, {}, {}; ", r_dst, r_tmp, r_arg2));
-                            loop_str.push_str(&format!("mvn {}, {}; ", r_dst, r_dst));
-                        }
-                        _ => {
-                            loop_str.push_str(&format!("cmp {}, {}; ", r_tmp, r_arg2));
-                            let cond = match op {
-                                inst_common::AtomicRmwOp::Smin => "lt",
-                                inst_common::AtomicRmwOp::Smax => "gt",
-                                inst_common::AtomicRmwOp::Umin => "lo",
-                                inst_common::AtomicRmwOp::Umax => "hi",
-                                _ => unreachable!(),
-                            };
-                            loop_str.push_str(&format!(
-                                "csel {}, {}, {}, {}; ",
-                                r_dst, r_tmp, r_arg2, cond
-                            ));
-                        }
-                    };
-                } else {
-                    loop_str.push_str(&format!("{} {}, {}, {}; ", op_str, r_dst, r_tmp, r_arg2));
-                }
-                loop_str.push_str(&format!(
-                    "stlxr{} {}, {}, [x25]; ",
-                    ty_suffix, r_status, r_dst
-                ));
-                loop_str.push_str(&format!("cbnz {}, 1b", r_status));
-                loop_str
-            }
-            &Inst::AtomicCAS { rs, rt, rn, ty } => {
-                let op = match ty {
-                    I8 => "casalb",
-                    I16 => "casalh",
-                    I32 | I64 => "casal",
-                    _ => panic!("Unsupported type: {}", ty),
-                };
-                let size = OperandSize::from_ty(ty);
-                let rs = show_ireg_sized(rs.to_reg(), mb_rru, size);
-                let rt = show_ireg_sized(rt, mb_rru, size);
-                let rn = rn.show_rru(mb_rru);
-
-                format!("{} {}, {}, [{}]", op, rs, rt, rn)
-            }
-            &Inst::AtomicCASLoop { ty } => {
-                format!(
-                    "atomically {{ compare-and-swap({}_bits_at_[x25], x26 -> x28), x27 = old_value_at_[x25]; x24 = trash }}",
-                    ty.bits())
-            }
-            &Inst::LoadAcquire {
-                access_ty, rt, rn, ..
-            } => {
-                let (op, ty) = match access_ty {
-                    I8 => ("ldarb", I32),
-                    I16 => ("ldarh", I32),
-                    I32 => ("ldar", I32),
-                    I64 => ("ldar", I64),
-                    _ => panic!("Unsupported type: {}", access_ty),
-                };
-                let size = OperandSize::from_ty(ty);
-                let rt = show_ireg_sized(rt.to_reg(), mb_rru, size);
-                let rn = rn.show_rru(mb_rru);
-                format!("{} {}, [{}]", op, rt, rn)
-            }
-            &Inst::StoreRelease {
-                access_ty, rt, rn, ..
-            } => {
-                let (op, ty) = match access_ty {
-                    I8 => ("stlrb", I32),
-                    I16 => ("stlrh", I32),
-                    I32 => ("stlr", I32),
-                    I64 => ("stlr", I64),
-                    _ => panic!("Unsupported type: {}", access_ty),
-                };
-                let size = OperandSize::from_ty(ty);
-                let rt = show_ireg_sized(rt, mb_rru, size);
-                let rn = rn.show_rru(mb_rru);
-                format!("{} {}, [{}]", op, rt, rn)
-            }
-            &Inst::Fence {} => {
-                format!("dmb ish")
-            }
-            &Inst::FpuMove64 { rd, rn } => {
-                let rd = show_vreg_scalar(rd.to_reg(), mb_rru, ScalarSize::Size64);
-                let rn = show_vreg_scalar(rn, mb_rru, ScalarSize::Size64);
-                format!("fmov {}, {}", rd, rn)
-            }
-            &Inst::FpuMove128 { rd, rn } => {
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let rn = rn.show_rru(mb_rru);
-                format!("mov {}.16b, {}.16b", rd, rn)
-            }
-            &Inst::FpuMoveFromVec { rd, rn, idx, size } => {
-                let rd = show_vreg_scalar(rd.to_reg(), mb_rru, size.lane_size());
-                let rn = show_vreg_element(rn, mb_rru, idx, size);
-                format!("mov {}, {}", rd, rn)
-            }
-            &Inst::FpuExtend { rd, rn, size } => {
-                let rd = show_vreg_scalar(rd.to_reg(), mb_rru, size);
-                let rn = show_vreg_scalar(rn, mb_rru, size);
-
-                format!("fmov {}, {}", rd, rn)
-            }
-            &Inst::FpuRR { fpu_op, rd, rn } => {
-                let (op, sizesrc, sizedest) = match fpu_op {
-                    FPUOp1::Abs32 => ("fabs", ScalarSize::Size32, ScalarSize::Size32),
-                    FPUOp1::Abs64 => ("fabs", ScalarSize::Size64, ScalarSize::Size64),
-                    FPUOp1::Neg32 => ("fneg", ScalarSize::Size32, ScalarSize::Size32),
-                    FPUOp1::Neg64 => ("fneg", ScalarSize::Size64, ScalarSize::Size64),
-                    FPUOp1::Sqrt32 => ("fsqrt", ScalarSize::Size32, ScalarSize::Size32),
-                    FPUOp1::Sqrt64 => ("fsqrt", ScalarSize::Size64, ScalarSize::Size64),
-                    FPUOp1::Cvt32To64 => ("fcvt", ScalarSize::Size32, ScalarSize::Size64),
-                    FPUOp1::Cvt64To32 => ("fcvt", ScalarSize::Size64, ScalarSize::Size32),
-                };
-                let rd = show_vreg_scalar(rd.to_reg(), mb_rru, sizedest);
-                let rn = show_vreg_scalar(rn, mb_rru, sizesrc);
-                format!("{} {}, {}", op, rd, rn)
-            }
-            &Inst::FpuRRR { fpu_op, rd, rn, rm } => {
-                let (op, size) = match fpu_op {
-                    FPUOp2::Add32 => ("fadd", ScalarSize::Size32),
-                    FPUOp2::Add64 => ("fadd", ScalarSize::Size64),
-                    FPUOp2::Sub32 => ("fsub", ScalarSize::Size32),
-                    FPUOp2::Sub64 => ("fsub", ScalarSize::Size64),
-                    FPUOp2::Mul32 => ("fmul", ScalarSize::Size32),
-                    FPUOp2::Mul64 => ("fmul", ScalarSize::Size64),
-                    FPUOp2::Div32 => ("fdiv", ScalarSize::Size32),
-                    FPUOp2::Div64 => ("fdiv", ScalarSize::Size64),
-                    FPUOp2::Max32 => ("fmax", ScalarSize::Size32),
-                    FPUOp2::Max64 => ("fmax", ScalarSize::Size64),
-                    FPUOp2::Min32 => ("fmin", ScalarSize::Size32),
-                    FPUOp2::Min64 => ("fmin", ScalarSize::Size64),
-                    FPUOp2::Sqadd64 => ("sqadd", ScalarSize::Size64),
-                    FPUOp2::Uqadd64 => ("uqadd", ScalarSize::Size64),
-                    FPUOp2::Sqsub64 => ("sqsub", ScalarSize::Size64),
-                    FPUOp2::Uqsub64 => ("uqsub", ScalarSize::Size64),
-                };
-                let rd = show_vreg_scalar(rd.to_reg(), mb_rru, size);
-                let rn = show_vreg_scalar(rn, mb_rru, size);
-                let rm = show_vreg_scalar(rm, mb_rru, size);
-                format!("{} {}, {}, {}", op, rd, rn, rm)
-            }
-            &Inst::FpuRRI { fpu_op, rd, rn } => {
-                let (op, imm, vector) = match fpu_op {
-                    FPUOpRI::UShr32(imm) => ("ushr", imm.show_rru(mb_rru), true),
-                    FPUOpRI::UShr64(imm) => ("ushr", imm.show_rru(mb_rru), false),
-                    FPUOpRI::Sli32(imm) => ("sli", imm.show_rru(mb_rru), true),
-                    FPUOpRI::Sli64(imm) => ("sli", imm.show_rru(mb_rru), false),
-                };
-
-                let show_vreg_fn: fn(Reg, Option<&RealRegUniverse>) -> String = if vector {
-                    |reg, mb_rru| show_vreg_vector(reg, mb_rru, VectorSize::Size32x2)
-                } else {
-                    |reg, mb_rru| show_vreg_scalar(reg, mb_rru, ScalarSize::Size64)
-                };
-                let rd = show_vreg_fn(rd.to_reg(), mb_rru);
-                let rn = show_vreg_fn(rn, mb_rru);
-                format!("{} {}, {}, {}", op, rd, rn, imm)
-            }
-            &Inst::FpuRRRR {
-                fpu_op,
-                rd,
-                rn,
-                rm,
-                ra,
-            } => {
-                let (op, size) = match fpu_op {
-                    FPUOp3::MAdd32 => ("fmadd", ScalarSize::Size32),
-                    FPUOp3::MAdd64 => ("fmadd", ScalarSize::Size64),
-                };
-                let rd = show_vreg_scalar(rd.to_reg(), mb_rru, size);
-                let rn = show_vreg_scalar(rn, mb_rru, size);
-                let rm = show_vreg_scalar(rm, mb_rru, size);
-                let ra = show_vreg_scalar(ra, mb_rru, size);
-                format!("{} {}, {}, {}, {}", op, rd, rn, rm, ra)
-            }
-            &Inst::FpuCmp32 { rn, rm } => {
-                let rn = show_vreg_scalar(rn, mb_rru, ScalarSize::Size32);
-                let rm = show_vreg_scalar(rm, mb_rru, ScalarSize::Size32);
-                format!("fcmp {}, {}", rn, rm)
-            }
-            &Inst::FpuCmp64 { rn, rm } => {
-                let rn = show_vreg_scalar(rn, mb_rru, ScalarSize::Size64);
-                let rm = show_vreg_scalar(rm, mb_rru, ScalarSize::Size64);
-                format!("fcmp {}, {}", rn, rm)
-            }
-            &Inst::FpuLoad32 { rd, ref mem, .. } => {
-                let rd = show_vreg_scalar(rd.to_reg(), mb_rru, ScalarSize::Size32);
-                let (mem_str, mem) = mem_finalize_for_show(mem, mb_rru, state);
-                let mem = mem.show_rru(mb_rru);
-                format!("{}ldr {}, {}", mem_str, rd, mem)
-            }
-            &Inst::FpuLoad64 { rd, ref mem, .. } => {
-                let rd = show_vreg_scalar(rd.to_reg(), mb_rru, ScalarSize::Size64);
-                let (mem_str, mem) = mem_finalize_for_show(mem, mb_rru, state);
-                let mem = mem.show_rru(mb_rru);
-                format!("{}ldr {}, {}", mem_str, rd, mem)
-            }
-            &Inst::FpuLoad128 { rd, ref mem, .. } => {
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let rd = "q".to_string() + &rd[1..];
-                let (mem_str, mem) = mem_finalize_for_show(mem, mb_rru, state);
-                let mem = mem.show_rru(mb_rru);
-                format!("{}ldr {}, {}", mem_str, rd, mem)
-            }
-            &Inst::FpuStore32 { rd, ref mem, .. } => {
-                let rd = show_vreg_scalar(rd, mb_rru, ScalarSize::Size32);
-                let (mem_str, mem) = mem_finalize_for_show(mem, mb_rru, state);
-                let mem = mem.show_rru(mb_rru);
-                format!("{}str {}, {}", mem_str, rd, mem)
-            }
-            &Inst::FpuStore64 { rd, ref mem, .. } => {
-                let rd = show_vreg_scalar(rd, mb_rru, ScalarSize::Size64);
-                let (mem_str, mem) = mem_finalize_for_show(mem, mb_rru, state);
-                let mem = mem.show_rru(mb_rru);
-                format!("{}str {}, {}", mem_str, rd, mem)
-            }
-            &Inst::FpuStore128 { rd, ref mem, .. } => {
-                let rd = rd.show_rru(mb_rru);
-                let rd = "q".to_string() + &rd[1..];
-                let (mem_str, mem) = mem_finalize_for_show(mem, mb_rru, state);
-                let mem = mem.show_rru(mb_rru);
-                format!("{}str {}, {}", mem_str, rd, mem)
-            }
-            &Inst::FpuLoadP64 {
-                rt, rt2, ref mem, ..
-            } => {
-                let rt = show_vreg_scalar(rt.to_reg(), mb_rru, ScalarSize::Size64);
-                let rt2 = show_vreg_scalar(rt2.to_reg(), mb_rru, ScalarSize::Size64);
-                let mem = mem.show_rru(mb_rru);
-
-                format!("ldp {}, {}, {}", rt, rt2, mem)
-            }
-            &Inst::FpuStoreP64 {
-                rt, rt2, ref mem, ..
-            } => {
-                let rt = show_vreg_scalar(rt, mb_rru, ScalarSize::Size64);
-                let rt2 = show_vreg_scalar(rt2, mb_rru, ScalarSize::Size64);
-                let mem = mem.show_rru(mb_rru);
-
-                format!("stp {}, {}, {}", rt, rt2, mem)
-            }
-            &Inst::FpuLoadP128 {
-                rt, rt2, ref mem, ..
-            } => {
-                let rt = show_vreg_scalar(rt.to_reg(), mb_rru, ScalarSize::Size128);
-                let rt2 = show_vreg_scalar(rt2.to_reg(), mb_rru, ScalarSize::Size128);
-                let mem = mem.show_rru(mb_rru);
-
-                format!("ldp {}, {}, {}", rt, rt2, mem)
-            }
-            &Inst::FpuStoreP128 {
-                rt, rt2, ref mem, ..
-            } => {
-                let rt = show_vreg_scalar(rt, mb_rru, ScalarSize::Size128);
-                let rt2 = show_vreg_scalar(rt2, mb_rru, ScalarSize::Size128);
-                let mem = mem.show_rru(mb_rru);
-
-                format!("stp {}, {}, {}", rt, rt2, mem)
-            }
-            &Inst::LoadFpuConst64 { rd, const_data } => {
-                let rd = show_vreg_scalar(rd.to_reg(), mb_rru, ScalarSize::Size64);
-                format!(
-                    "ldr {}, pc+8 ; b 12 ; data.f64 {}",
-                    rd,
-                    f64::from_bits(const_data)
-                )
-            }
-            &Inst::LoadFpuConst128 { rd, const_data } => {
-                let rd = show_vreg_scalar(rd.to_reg(), mb_rru, ScalarSize::Size128);
-                format!("ldr {}, pc+8 ; b 20 ; data.f128 0x{:032x}", rd, const_data)
-            }
-            &Inst::FpuToInt { op, rd, rn } => {
-                let (op, sizesrc, sizedest) = match op {
-                    FpuToIntOp::F32ToI32 => ("fcvtzs", ScalarSize::Size32, OperandSize::Size32),
-                    FpuToIntOp::F32ToU32 => ("fcvtzu", ScalarSize::Size32, OperandSize::Size32),
-                    FpuToIntOp::F32ToI64 => ("fcvtzs", ScalarSize::Size32, OperandSize::Size64),
-                    FpuToIntOp::F32ToU64 => ("fcvtzu", ScalarSize::Size32, OperandSize::Size64),
-                    FpuToIntOp::F64ToI32 => ("fcvtzs", ScalarSize::Size64, OperandSize::Size32),
-                    FpuToIntOp::F64ToU32 => ("fcvtzu", ScalarSize::Size64, OperandSize::Size32),
-                    FpuToIntOp::F64ToI64 => ("fcvtzs", ScalarSize::Size64, OperandSize::Size64),
-                    FpuToIntOp::F64ToU64 => ("fcvtzu", ScalarSize::Size64, OperandSize::Size64),
-                };
-                let rd = show_ireg_sized(rd.to_reg(), mb_rru, sizedest);
-                let rn = show_vreg_scalar(rn, mb_rru, sizesrc);
-                format!("{} {}, {}", op, rd, rn)
-            }
-            &Inst::IntToFpu { op, rd, rn } => {
-                let (op, sizesrc, sizedest) = match op {
-                    IntToFpuOp::I32ToF32 => ("scvtf", OperandSize::Size32, ScalarSize::Size32),
-                    IntToFpuOp::U32ToF32 => ("ucvtf", OperandSize::Size32, ScalarSize::Size32),
-                    IntToFpuOp::I64ToF32 => ("scvtf", OperandSize::Size64, ScalarSize::Size32),
-                    IntToFpuOp::U64ToF32 => ("ucvtf", OperandSize::Size64, ScalarSize::Size32),
-                    IntToFpuOp::I32ToF64 => ("scvtf", OperandSize::Size32, ScalarSize::Size64),
-                    IntToFpuOp::U32ToF64 => ("ucvtf", OperandSize::Size32, ScalarSize::Size64),
-                    IntToFpuOp::I64ToF64 => ("scvtf", OperandSize::Size64, ScalarSize::Size64),
-                    IntToFpuOp::U64ToF64 => ("ucvtf", OperandSize::Size64, ScalarSize::Size64),
-                };
-                let rd = show_vreg_scalar(rd.to_reg(), mb_rru, sizedest);
-                let rn = show_ireg_sized(rn, mb_rru, sizesrc);
-                format!("{} {}, {}", op, rd, rn)
-            }
-            &Inst::FpuCSel32 { rd, rn, rm, cond } => {
-                let rd = show_vreg_scalar(rd.to_reg(), mb_rru, ScalarSize::Size32);
-                let rn = show_vreg_scalar(rn, mb_rru, ScalarSize::Size32);
-                let rm = show_vreg_scalar(rm, mb_rru, ScalarSize::Size32);
-                let cond = cond.show_rru(mb_rru);
-                format!("fcsel {}, {}, {}, {}", rd, rn, rm, cond)
-            }
-            &Inst::FpuCSel64 { rd, rn, rm, cond } => {
-                let rd = show_vreg_scalar(rd.to_reg(), mb_rru, ScalarSize::Size64);
-                let rn = show_vreg_scalar(rn, mb_rru, ScalarSize::Size64);
-                let rm = show_vreg_scalar(rm, mb_rru, ScalarSize::Size64);
-                let cond = cond.show_rru(mb_rru);
-                format!("fcsel {}, {}, {}, {}", rd, rn, rm, cond)
-            }
-            &Inst::FpuRound { op, rd, rn } => {
-                let (inst, size) = match op {
-                    FpuRoundMode::Minus32 => ("frintm", ScalarSize::Size32),
-                    FpuRoundMode::Minus64 => ("frintm", ScalarSize::Size64),
-                    FpuRoundMode::Plus32 => ("frintp", ScalarSize::Size32),
-                    FpuRoundMode::Plus64 => ("frintp", ScalarSize::Size64),
-                    FpuRoundMode::Zero32 => ("frintz", ScalarSize::Size32),
-                    FpuRoundMode::Zero64 => ("frintz", ScalarSize::Size64),
-                    FpuRoundMode::Nearest32 => ("frintn", ScalarSize::Size32),
-                    FpuRoundMode::Nearest64 => ("frintn", ScalarSize::Size64),
-                };
-                let rd = show_vreg_scalar(rd.to_reg(), mb_rru, size);
-                let rn = show_vreg_scalar(rn, mb_rru, size);
-                format!("{} {}, {}", inst, rd, rn)
-            }
-            &Inst::MovToFpu { rd, rn, size } => {
-                let operand_size = size.operand_size();
-                let rd = show_vreg_scalar(rd.to_reg(), mb_rru, size);
-                let rn = show_ireg_sized(rn, mb_rru, operand_size);
-                format!("fmov {}, {}", rd, rn)
-            }
-            &Inst::FpuMoveFPImm { rd, imm, size } => {
-                let imm = imm.show_rru(mb_rru);
-                let rd = show_vreg_scalar(rd.to_reg(), mb_rru, size);
-
-                format!("fmov {}, {}", rd, imm)
-            }
-            &Inst::MovToVec { rd, rn, idx, size } => {
-                let rd = show_vreg_element(rd.to_reg(), mb_rru, idx, size);
-                let rn = show_ireg_sized(rn, mb_rru, size.operand_size());
-                format!("mov {}, {}", rd, rn)
-            }
-            &Inst::MovFromVec { rd, rn, idx, size } => {
-                let op = match size {
-                    VectorSize::Size8x16 => "umov",
-                    VectorSize::Size16x8 => "umov",
-                    VectorSize::Size32x4 => "mov",
-                    VectorSize::Size64x2 => "mov",
-                    _ => unimplemented!(),
-                };
-                let rd = show_ireg_sized(rd.to_reg(), mb_rru, size.operand_size());
-                let rn = show_vreg_element(rn, mb_rru, idx, size);
-                format!("{} {}, {}", op, rd, rn)
-            }
-            &Inst::MovFromVecSigned {
-                rd,
-                rn,
-                idx,
-                size,
-                scalar_size,
-            } => {
-                let rd = show_ireg_sized(rd.to_reg(), mb_rru, scalar_size);
-                let rn = show_vreg_element(rn, mb_rru, idx, size);
-                format!("smov {}, {}", rd, rn)
-            }
-            &Inst::VecDup { rd, rn, size } => {
-                let rd = show_vreg_vector(rd.to_reg(), mb_rru, size);
-                let rn = show_ireg_sized(rn, mb_rru, size.operand_size());
-                format!("dup {}, {}", rd, rn)
-            }
-            &Inst::VecDupFromFpu { rd, rn, size } => {
-                let rd = show_vreg_vector(rd.to_reg(), mb_rru, size);
-                let rn = show_vreg_element(rn, mb_rru, 0, size);
-                format!("dup {}, {}", rd, rn)
-            }
-            &Inst::VecDupFPImm { rd, imm, size } => {
-                let imm = imm.show_rru(mb_rru);
-                let rd = show_vreg_vector(rd.to_reg(), mb_rru, size);
-
-                format!("fmov {}, {}", rd, imm)
-            }
-            &Inst::VecDupImm {
-                rd,
-                imm,
-                invert,
-                size,
-            } => {
-                let imm = imm.show_rru(mb_rru);
-                let op = if invert { "mvni" } else { "movi" };
-                let rd = show_vreg_vector(rd.to_reg(), mb_rru, size);
-
-                format!("{} {}, {}", op, rd, imm)
-            }
-            &Inst::VecExtend {
-                t,
-                rd,
-                rn,
-                high_half,
-            } => {
-                let (op, dest, src) = match (t, high_half) {
-                    (VecExtendOp::Sxtl8, false) => {
-                        ("sxtl", VectorSize::Size16x8, VectorSize::Size8x8)
-                    }
-                    (VecExtendOp::Sxtl8, true) => {
-                        ("sxtl2", VectorSize::Size16x8, VectorSize::Size8x16)
-                    }
-                    (VecExtendOp::Sxtl16, false) => {
-                        ("sxtl", VectorSize::Size32x4, VectorSize::Size16x4)
-                    }
-                    (VecExtendOp::Sxtl16, true) => {
-                        ("sxtl2", VectorSize::Size32x4, VectorSize::Size16x8)
-                    }
-                    (VecExtendOp::Sxtl32, false) => {
-                        ("sxtl", VectorSize::Size64x2, VectorSize::Size32x2)
-                    }
-                    (VecExtendOp::Sxtl32, true) => {
-                        ("sxtl2", VectorSize::Size64x2, VectorSize::Size32x4)
-                    }
-                    (VecExtendOp::Uxtl8, false) => {
-                        ("uxtl", VectorSize::Size16x8, VectorSize::Size8x8)
-                    }
-                    (VecExtendOp::Uxtl8, true) => {
-                        ("uxtl2", VectorSize::Size16x8, VectorSize::Size8x16)
-                    }
-                    (VecExtendOp::Uxtl16, false) => {
-                        ("uxtl", VectorSize::Size32x4, VectorSize::Size16x4)
-                    }
-                    (VecExtendOp::Uxtl16, true) => {
-                        ("uxtl2", VectorSize::Size32x4, VectorSize::Size16x8)
-                    }
-                    (VecExtendOp::Uxtl32, false) => {
-                        ("uxtl", VectorSize::Size64x2, VectorSize::Size32x2)
-                    }
-                    (VecExtendOp::Uxtl32, true) => {
-                        ("uxtl2", VectorSize::Size64x2, VectorSize::Size32x4)
-                    }
-                };
-                let rd = show_vreg_vector(rd.to_reg(), mb_rru, dest);
-                let rn = show_vreg_vector(rn, mb_rru, src);
-                format!("{} {}, {}", op, rd, rn)
-            }
-            &Inst::VecMovElement {
-                rd,
-                rn,
-                dest_idx,
-                src_idx,
-                size,
-            } => {
-                let rd = show_vreg_element(rd.to_reg(), mb_rru, dest_idx, size);
-                let rn = show_vreg_element(rn, mb_rru, src_idx, size);
-                format!("mov {}, {}", rd, rn)
-            }
-            &Inst::VecRRLong {
-                op,
-                rd,
-                rn,
-                high_half,
-            } => {
-                let (op, rd_size, size, suffix) = match (op, high_half) {
-                    (VecRRLongOp::Fcvtl16, false) => {
-                        ("fcvtl", VectorSize::Size32x4, VectorSize::Size16x4, "")
-                    }
-                    (VecRRLongOp::Fcvtl16, true) => {
-                        ("fcvtl2", VectorSize::Size32x4, VectorSize::Size16x8, "")
-                    }
-                    (VecRRLongOp::Fcvtl32, false) => {
-                        ("fcvtl", VectorSize::Size64x2, VectorSize::Size32x2, "")
-                    }
-                    (VecRRLongOp::Fcvtl32, true) => {
-                        ("fcvtl2", VectorSize::Size64x2, VectorSize::Size32x4, "")
-                    }
-                    (VecRRLongOp::Shll8, false) => {
-                        ("shll", VectorSize::Size16x8, VectorSize::Size8x8, ", #8")
-                    }
-                    (VecRRLongOp::Shll8, true) => {
-                        ("shll2", VectorSize::Size16x8, VectorSize::Size8x16, ", #8")
-                    }
-                    (VecRRLongOp::Shll16, false) => {
-                        ("shll", VectorSize::Size32x4, VectorSize::Size16x4, ", #16")
-                    }
-                    (VecRRLongOp::Shll16, true) => {
-                        ("shll2", VectorSize::Size32x4, VectorSize::Size16x8, ", #16")
-                    }
-                    (VecRRLongOp::Shll32, false) => {
-                        ("shll", VectorSize::Size64x2, VectorSize::Size32x2, ", #32")
-                    }
-                    (VecRRLongOp::Shll32, true) => {
-                        ("shll2", VectorSize::Size64x2, VectorSize::Size32x4, ", #32")
-                    }
-                };
-                let rd = show_vreg_vector(rd.to_reg(), mb_rru, rd_size);
-                let rn = show_vreg_vector(rn, mb_rru, size);
-
-                format!("{} {}, {}{}", op, rd, rn, suffix)
-            }
-            &Inst::VecRRNarrow {
-                op,
-                rd,
-                rn,
-                high_half,
-            } => {
-                let (op, rd_size, size) = match (op, high_half) {
-                    (VecRRNarrowOp::Xtn16, false) => {
-                        ("xtn", VectorSize::Size8x8, VectorSize::Size16x8)
-                    }
-                    (VecRRNarrowOp::Xtn16, true) => {
-                        ("xtn2", VectorSize::Size8x16, VectorSize::Size16x8)
-                    }
-                    (VecRRNarrowOp::Xtn32, false) => {
-                        ("xtn", VectorSize::Size16x4, VectorSize::Size32x4)
-                    }
-                    (VecRRNarrowOp::Xtn32, true) => {
-                        ("xtn2", VectorSize::Size16x8, VectorSize::Size32x4)
-                    }
-                    (VecRRNarrowOp::Xtn64, false) => {
-                        ("xtn", VectorSize::Size32x2, VectorSize::Size64x2)
-                    }
-                    (VecRRNarrowOp::Xtn64, true) => {
-                        ("xtn2", VectorSize::Size32x4, VectorSize::Size64x2)
-                    }
-                    (VecRRNarrowOp::Sqxtn16, false) => {
-                        ("sqxtn", VectorSize::Size8x8, VectorSize::Size16x8)
-                    }
-                    (VecRRNarrowOp::Sqxtn16, true) => {
-                        ("sqxtn2", VectorSize::Size8x16, VectorSize::Size16x8)
-                    }
-                    (VecRRNarrowOp::Sqxtn32, false) => {
-                        ("sqxtn", VectorSize::Size16x4, VectorSize::Size32x4)
-                    }
-                    (VecRRNarrowOp::Sqxtn32, true) => {
-                        ("sqxtn2", VectorSize::Size16x8, VectorSize::Size32x4)
-                    }
-                    (VecRRNarrowOp::Sqxtn64, false) => {
-                        ("sqxtn", VectorSize::Size32x2, VectorSize::Size64x2)
-                    }
-                    (VecRRNarrowOp::Sqxtn64, true) => {
-                        ("sqxtn2", VectorSize::Size32x4, VectorSize::Size64x2)
-                    }
-                    (VecRRNarrowOp::Sqxtun16, false) => {
-                        ("sqxtun", VectorSize::Size8x8, VectorSize::Size16x8)
-                    }
-                    (VecRRNarrowOp::Sqxtun16, true) => {
-                        ("sqxtun2", VectorSize::Size8x16, VectorSize::Size16x8)
-                    }
-                    (VecRRNarrowOp::Sqxtun32, false) => {
-                        ("sqxtun", VectorSize::Size16x4, VectorSize::Size32x4)
-                    }
-                    (VecRRNarrowOp::Sqxtun32, true) => {
-                        ("sqxtun2", VectorSize::Size16x8, VectorSize::Size32x4)
-                    }
-                    (VecRRNarrowOp::Sqxtun64, false) => {
-                        ("sqxtun", VectorSize::Size32x2, VectorSize::Size64x2)
-                    }
-                    (VecRRNarrowOp::Sqxtun64, true) => {
-                        ("sqxtun2", VectorSize::Size32x4, VectorSize::Size64x2)
-                    }
-                    (VecRRNarrowOp::Uqxtn16, false) => {
-                        ("uqxtn", VectorSize::Size8x8, VectorSize::Size16x8)
-                    }
-                    (VecRRNarrowOp::Uqxtn16, true) => {
-                        ("uqxtn2", VectorSize::Size8x16, VectorSize::Size16x8)
-                    }
-                    (VecRRNarrowOp::Uqxtn32, false) => {
-                        ("uqxtn", VectorSize::Size16x4, VectorSize::Size32x4)
-                    }
-                    (VecRRNarrowOp::Uqxtn32, true) => {
-                        ("uqxtn2", VectorSize::Size16x8, VectorSize::Size32x4)
-                    }
-                    (VecRRNarrowOp::Uqxtn64, false) => {
-                        ("uqxtn", VectorSize::Size32x2, VectorSize::Size64x2)
-                    }
-                    (VecRRNarrowOp::Uqxtn64, true) => {
-                        ("uqxtn2", VectorSize::Size32x4, VectorSize::Size64x2)
-                    }
-                    (VecRRNarrowOp::Fcvtn32, false) => {
-                        ("fcvtn", VectorSize::Size16x4, VectorSize::Size32x4)
-                    }
-                    (VecRRNarrowOp::Fcvtn32, true) => {
-                        ("fcvtn2", VectorSize::Size16x8, VectorSize::Size32x4)
-                    }
-                    (VecRRNarrowOp::Fcvtn64, false) => {
-                        ("fcvtn", VectorSize::Size32x2, VectorSize::Size64x2)
-                    }
-                    (VecRRNarrowOp::Fcvtn64, true) => {
-                        ("fcvtn2", VectorSize::Size32x4, VectorSize::Size64x2)
-                    }
-                };
-                let rd = show_vreg_vector(rd.to_reg(), mb_rru, rd_size);
-                let rn = show_vreg_vector(rn, mb_rru, size);
-
-                format!("{} {}, {}", op, rd, rn)
-            }
-            &Inst::VecRRPair { op, rd, rn } => {
-                let op = match op {
-                    VecPairOp::Addp => "addp",
-                };
-                let rd = show_vreg_scalar(rd.to_reg(), mb_rru, ScalarSize::Size64);
-                let rn = show_vreg_vector(rn, mb_rru, VectorSize::Size64x2);
-
-                format!("{} {}, {}", op, rd, rn)
-            }
-            &Inst::VecRRPairLong { op, rd, rn } => {
-                let (op, dest, src) = match op {
-                    VecRRPairLongOp::Saddlp8 => {
-                        ("saddlp", VectorSize::Size16x8, VectorSize::Size8x16)
-                    }
-                    VecRRPairLongOp::Saddlp16 => {
-                        ("saddlp", VectorSize::Size32x4, VectorSize::Size16x8)
-                    }
-                    VecRRPairLongOp::Uaddlp8 => {
-                        ("uaddlp", VectorSize::Size16x8, VectorSize::Size8x16)
-                    }
-                    VecRRPairLongOp::Uaddlp16 => {
-                        ("uaddlp", VectorSize::Size32x4, VectorSize::Size16x8)
-                    }
-                };
-                let rd = show_vreg_vector(rd.to_reg(), mb_rru, dest);
-                let rn = show_vreg_vector(rn, mb_rru, src);
-
-                format!("{} {}, {}", op, rd, rn)
-            }
-            &Inst::VecRRR {
-                rd,
-                rn,
-                rm,
-                alu_op,
-                size,
-            } => {
-                let (op, size) = match alu_op {
-                    VecALUOp::Sqadd => ("sqadd", size),
-                    VecALUOp::Uqadd => ("uqadd", size),
-                    VecALUOp::Sqsub => ("sqsub", size),
-                    VecALUOp::Uqsub => ("uqsub", size),
-                    VecALUOp::Cmeq => ("cmeq", size),
-                    VecALUOp::Cmge => ("cmge", size),
-                    VecALUOp::Cmgt => ("cmgt", size),
-                    VecALUOp::Cmhs => ("cmhs", size),
-                    VecALUOp::Cmhi => ("cmhi", size),
-                    VecALUOp::Fcmeq => ("fcmeq", size),
-                    VecALUOp::Fcmgt => ("fcmgt", size),
-                    VecALUOp::Fcmge => ("fcmge", size),
-                    VecALUOp::And => ("and", VectorSize::Size8x16),
-                    VecALUOp::Bic => ("bic", VectorSize::Size8x16),
-                    VecALUOp::Orr => ("orr", VectorSize::Size8x16),
-                    VecALUOp::Eor => ("eor", VectorSize::Size8x16),
-                    VecALUOp::Bsl => ("bsl", VectorSize::Size8x16),
-                    VecALUOp::Umaxp => ("umaxp", size),
-                    VecALUOp::Add => ("add", size),
-                    VecALUOp::Sub => ("sub", size),
-                    VecALUOp::Mul => ("mul", size),
-                    VecALUOp::Sshl => ("sshl", size),
-                    VecALUOp::Ushl => ("ushl", size),
-                    VecALUOp::Umin => ("umin", size),
-                    VecALUOp::Smin => ("smin", size),
-                    VecALUOp::Umax => ("umax", size),
-                    VecALUOp::Smax => ("smax", size),
-                    VecALUOp::Urhadd => ("urhadd", size),
-                    VecALUOp::Fadd => ("fadd", size),
-                    VecALUOp::Fsub => ("fsub", size),
-                    VecALUOp::Fdiv => ("fdiv", size),
-                    VecALUOp::Fmax => ("fmax", size),
-                    VecALUOp::Fmin => ("fmin", size),
-                    VecALUOp::Fmul => ("fmul", size),
-                    VecALUOp::Addp => ("addp", size),
-                    VecALUOp::Zip1 => ("zip1", size),
-                    VecALUOp::Sqrdmulh => ("sqrdmulh", size),
-                };
-                let rd = show_vreg_vector(rd.to_reg(), mb_rru, size);
-                let rn = show_vreg_vector(rn, mb_rru, size);
-                let rm = show_vreg_vector(rm, mb_rru, size);
-                format!("{} {}, {}, {}", op, rd, rn, rm)
-            }
-            &Inst::VecRRRLong {
-                rd,
-                rn,
-                rm,
-                alu_op,
-                high_half,
-            } => {
-                let (op, dest_size, src_size) = match (alu_op, high_half) {
-                    (VecRRRLongOp::Smull8, false) => {
-                        ("smull", VectorSize::Size16x8, VectorSize::Size8x8)
-                    }
-                    (VecRRRLongOp::Smull8, true) => {
-                        ("smull2", VectorSize::Size16x8, VectorSize::Size8x16)
-                    }
-                    (VecRRRLongOp::Smull16, false) => {
-                        ("smull", VectorSize::Size32x4, VectorSize::Size16x4)
-                    }
-                    (VecRRRLongOp::Smull16, true) => {
-                        ("smull2", VectorSize::Size32x4, VectorSize::Size16x8)
-                    }
-                    (VecRRRLongOp::Smull32, false) => {
-                        ("smull", VectorSize::Size64x2, VectorSize::Size32x2)
-                    }
-                    (VecRRRLongOp::Smull32, true) => {
-                        ("smull2", VectorSize::Size64x2, VectorSize::Size32x4)
-                    }
-                    (VecRRRLongOp::Umull8, false) => {
-                        ("umull", VectorSize::Size16x8, VectorSize::Size8x8)
-                    }
-                    (VecRRRLongOp::Umull8, true) => {
-                        ("umull2", VectorSize::Size16x8, VectorSize::Size8x16)
-                    }
-                    (VecRRRLongOp::Umull16, false) => {
-                        ("umull", VectorSize::Size32x4, VectorSize::Size16x4)
-                    }
-                    (VecRRRLongOp::Umull16, true) => {
-                        ("umull2", VectorSize::Size32x4, VectorSize::Size16x8)
-                    }
-                    (VecRRRLongOp::Umull32, false) => {
-                        ("umull", VectorSize::Size64x2, VectorSize::Size32x2)
-                    }
-                    (VecRRRLongOp::Umull32, true) => {
-                        ("umull2", VectorSize::Size64x2, VectorSize::Size32x4)
-                    }
-                    (VecRRRLongOp::Umlal8, false) => {
-                        ("umlal", VectorSize::Size16x8, VectorSize::Size8x8)
-                    }
-                    (VecRRRLongOp::Umlal8, true) => {
-                        ("umlal2", VectorSize::Size16x8, VectorSize::Size8x16)
-                    }
-                    (VecRRRLongOp::Umlal16, false) => {
-                        ("umlal", VectorSize::Size32x4, VectorSize::Size16x4)
-                    }
-                    (VecRRRLongOp::Umlal16, true) => {
-                        ("umlal2", VectorSize::Size32x4, VectorSize::Size16x8)
-                    }
-                    (VecRRRLongOp::Umlal32, false) => {
-                        ("umlal", VectorSize::Size64x2, VectorSize::Size32x2)
-                    }
-                    (VecRRRLongOp::Umlal32, true) => {
-                        ("umlal2", VectorSize::Size64x2, VectorSize::Size32x4)
-                    }
-                };
-                let rd = show_vreg_vector(rd.to_reg(), mb_rru, dest_size);
-                let rn = show_vreg_vector(rn, mb_rru, src_size);
-                let rm = show_vreg_vector(rm, mb_rru, src_size);
-                format!("{} {}, {}, {}", op, rd, rn, rm)
-            }
-            &Inst::VecMisc { op, rd, rn, size } => {
-                let (op, size, suffix) = match op {
-                    VecMisc2::Not => (
-                        "mvn",
-                        if size.is_128bits() {
-                            VectorSize::Size8x16
-                        } else {
-                            VectorSize::Size8x8
-                        },
-                        "",
-                    ),
-                    VecMisc2::Neg => ("neg", size, ""),
-                    VecMisc2::Abs => ("abs", size, ""),
-                    VecMisc2::Fabs => ("fabs", size, ""),
-                    VecMisc2::Fneg => ("fneg", size, ""),
-                    VecMisc2::Fsqrt => ("fsqrt", size, ""),
-                    VecMisc2::Rev64 => ("rev64", size, ""),
-                    VecMisc2::Fcvtzs => ("fcvtzs", size, ""),
-                    VecMisc2::Fcvtzu => ("fcvtzu", size, ""),
-                    VecMisc2::Scvtf => ("scvtf", size, ""),
-                    VecMisc2::Ucvtf => ("ucvtf", size, ""),
-                    VecMisc2::Frintn => ("frintn", size, ""),
-                    VecMisc2::Frintz => ("frintz", size, ""),
-                    VecMisc2::Frintm => ("frintm", size, ""),
-                    VecMisc2::Frintp => ("frintp", size, ""),
-                    VecMisc2::Cnt => ("cnt", size, ""),
-                    VecMisc2::Cmeq0 => ("cmeq", size, ", #0"),
-                };
-                let rd = show_vreg_vector(rd.to_reg(), mb_rru, size);
-                let rn = show_vreg_vector(rn, mb_rru, size);
-                format!("{} {}, {}{}", op, rd, rn, suffix)
-            }
-            &Inst::VecLanes { op, rd, rn, size } => {
-                let op = match op {
-                    VecLanesOp::Uminv => "uminv",
-                    VecLanesOp::Addv => "addv",
-                };
-                let rd = show_vreg_scalar(rd.to_reg(), mb_rru, size.lane_size());
-                let rn = show_vreg_vector(rn, mb_rru, size);
-                format!("{} {}, {}", op, rd, rn)
-            }
-            &Inst::VecShiftImm {
-                op,
-                rd,
-                rn,
-                size,
-                imm,
-            } => {
-                let op = match op {
-                    VecShiftImmOp::Shl => "shl",
-                    VecShiftImmOp::Ushr => "ushr",
-                    VecShiftImmOp::Sshr => "sshr",
-                };
-                let rd = show_vreg_vector(rd.to_reg(), mb_rru, size);
-                let rn = show_vreg_vector(rn, mb_rru, size);
-                format!("{} {}, {}, #{}", op, rd, rn, imm)
-            }
-            &Inst::VecExtract { rd, rn, rm, imm4 } => {
-                let rd = show_vreg_vector(rd.to_reg(), mb_rru, VectorSize::Size8x16);
-                let rn = show_vreg_vector(rn, mb_rru, VectorSize::Size8x16);
-                let rm = show_vreg_vector(rm, mb_rru, VectorSize::Size8x16);
-                format!("ext {}, {}, {}, #{}", rd, rn, rm, imm4)
-            }
-            &Inst::VecTbl {
-                rd,
-                rn,
-                rm,
-                is_extension,
-            } => {
-                let op = if is_extension { "tbx" } else { "tbl" };
-                let rd = show_vreg_vector(rd.to_reg(), mb_rru, VectorSize::Size8x16);
-                let rn = show_vreg_vector(rn, mb_rru, VectorSize::Size8x16);
-                let rm = show_vreg_vector(rm, mb_rru, VectorSize::Size8x16);
-                format!("{} {}, {{ {} }}, {}", op, rd, rn, rm)
-            }
-            &Inst::VecTbl2 {
-                rd,
-                rn,
-                rn2,
-                rm,
-                is_extension,
-            } => {
-                let op = if is_extension { "tbx" } else { "tbl" };
-                let rd = show_vreg_vector(rd.to_reg(), mb_rru, VectorSize::Size8x16);
-                let rn = show_vreg_vector(rn, mb_rru, VectorSize::Size8x16);
-                let rn2 = show_vreg_vector(rn2, mb_rru, VectorSize::Size8x16);
-                let rm = show_vreg_vector(rm, mb_rru, VectorSize::Size8x16);
-                format!("{} {}, {{ {}, {} }}, {}", op, rd, rn, rn2, rm)
-            }
-            &Inst::VecLoadReplicate { rd, rn, size, .. } => {
-                let rd = show_vreg_vector(rd.to_reg(), mb_rru, size);
-                let rn = rn.show_rru(mb_rru);
-
-                format!("ld1r {{ {} }}, [{}]", rd, rn)
-            }
-            &Inst::VecCSel { rd, rn, rm, cond } => {
-                let rd = show_vreg_vector(rd.to_reg(), mb_rru, VectorSize::Size8x16);
-                let rn = show_vreg_vector(rn, mb_rru, VectorSize::Size8x16);
-                let rm = show_vreg_vector(rm, mb_rru, VectorSize::Size8x16);
-                let cond = cond.show_rru(mb_rru);
-                format!(
-                    "vcsel {}, {}, {}, {} (if-then-else diamond)",
-                    rd, rn, rm, cond
-                )
-            }
-            &Inst::MovToNZCV { rn } => {
-                let rn = rn.show_rru(mb_rru);
-                format!("msr nzcv, {}", rn)
-            }
-            &Inst::MovFromNZCV { rd } => {
-                let rd = rd.to_reg().show_rru(mb_rru);
-                format!("mrs {}, nzcv", rd)
-            }
-            &Inst::Extend {
-                rd,
-                rn,
-                signed: false,
-                from_bits: 1,
-                ..
-            } => {
-                let rd = show_ireg_sized(rd.to_reg(), mb_rru, OperandSize::Size32);
-                let rn = show_ireg_sized(rn, mb_rru, OperandSize::Size32);
-                format!("and {}, {}, #1", rd, rn)
-            }
-            &Inst::Extend {
-                rd,
-                rn,
-                signed: false,
-                from_bits: 32,
-                to_bits: 64,
-            } => {
-                // The case of a zero extension from 32 to 64 bits, is implemented
-                // with a "mov" to a 32-bit (W-reg) dest, because this zeroes
-                // the top 32 bits.
-                let rd = show_ireg_sized(rd.to_reg(), mb_rru, OperandSize::Size32);
-                let rn = show_ireg_sized(rn, mb_rru, OperandSize::Size32);
-                format!("mov {}, {}", rd, rn)
-            }
-            &Inst::Extend {
-                rd,
-                rn,
-                signed,
-                from_bits,
-                to_bits,
-            } => {
-                assert!(from_bits <= to_bits);
-                let op = match (signed, from_bits) {
-                    (false, 8) => "uxtb",
-                    (true, 8) => "sxtb",
-                    (false, 16) => "uxth",
-                    (true, 16) => "sxth",
-                    (true, 32) => "sxtw",
-                    (true, _) => "sbfx",
-                    (false, _) => "ubfx",
-                };
-                if op == "sbfx" || op == "ubfx" {
-                    let dest_size = OperandSize::from_bits(to_bits);
-                    let rd = show_ireg_sized(rd.to_reg(), mb_rru, dest_size);
-                    let rn = show_ireg_sized(rn, mb_rru, dest_size);
-                    format!("{} {}, {}, #0, #{}", op, rd, rn, from_bits)
-                } else {
-                    let dest_size = if signed {
-                        OperandSize::from_bits(to_bits)
-                    } else {
-                        OperandSize::Size32
-                    };
-                    let rd = show_ireg_sized(rd.to_reg(), mb_rru, dest_size);
-                    let rn = show_ireg_sized(rn, mb_rru, OperandSize::from_bits(from_bits));
-                    format!("{} {}, {}", op, rd, rn)
-                }
-            }
-            &Inst::Call { .. } => format!("bl 0"),
-            &Inst::CallInd { ref info, .. } => {
-                let rn = info.rn.show_rru(mb_rru);
-                format!("blr {}", rn)
-            }
-            &Inst::Ret => "ret".to_string(),
-            &Inst::EpiloguePlaceholder => "epilogue placeholder".to_string(),
-            &Inst::Jump { ref dest } => {
-                let dest = dest.show_rru(mb_rru);
-                format!("b {}", dest)
-            }
-            &Inst::CondBr {
-                ref taken,
-                ref not_taken,
-                ref kind,
-            } => {
-                let taken = taken.show_rru(mb_rru);
-                let not_taken = not_taken.show_rru(mb_rru);
-                match kind {
-                    &CondBrKind::Zero(reg) => {
-                        let reg = reg.show_rru(mb_rru);
-                        format!("cbz {}, {} ; b {}", reg, taken, not_taken)
-                    }
-                    &CondBrKind::NotZero(reg) => {
-                        let reg = reg.show_rru(mb_rru);
-                        format!("cbnz {}, {} ; b {}", reg, taken, not_taken)
-                    }
-                    &CondBrKind::Cond(c) => {
-                        let c = c.show_rru(mb_rru);
-                        format!("b.{} {} ; b {}", c, taken, not_taken)
-                    }
-                }
-            }
-            &Inst::IndirectBr { rn, .. } => {
-                let rn = rn.show_rru(mb_rru);
-                format!("br {}", rn)
-            }
-            &Inst::Brk => "brk #0".to_string(),
-            &Inst::Udf { .. } => "udf".to_string(),
-            &Inst::TrapIf { ref kind, .. } => match kind {
-                &CondBrKind::Zero(reg) => {
-                    let reg = reg.show_rru(mb_rru);
-                    format!("cbnz {}, 8 ; udf", reg)
-                }
-                &CondBrKind::NotZero(reg) => {
-                    let reg = reg.show_rru(mb_rru);
-                    format!("cbz {}, 8 ; udf", reg)
-                }
-                &CondBrKind::Cond(c) => {
-                    let c = c.invert().show_rru(mb_rru);
-                    format!("b.{} 8 ; udf", c)
-                }
-            },
-            &Inst::Adr { rd, off } => {
-                let rd = rd.show_rru(mb_rru);
-                format!("adr {}, pc+{}", rd, off)
-            }
-            &Inst::Word4 { data } => format!("data.i32 {}", data),
-            &Inst::Word8 { data } => format!("data.i64 {}", data),
-            &Inst::JTSequence {
-                ref info,
-                ridx,
-                rtmp1,
-                rtmp2,
-                ..
-            } => {
-                let ridx = ridx.show_rru(mb_rru);
-                let rtmp1 = rtmp1.show_rru(mb_rru);
-                let rtmp2 = rtmp2.show_rru(mb_rru);
-                let default_target = info.default_target.show_rru(mb_rru);
-                format!(
-                    concat!(
-                        "b.hs {} ; ",
-                        "adr {}, pc+16 ; ",
-                        "ldrsw {}, [{}, {}, LSL 2] ; ",
-                        "add {}, {}, {} ; ",
-                        "br {} ; ",
-                        "jt_entries {:?}"
-                    ),
-                    default_target,
-                    rtmp1,
-                    rtmp2,
-                    rtmp1,
-                    ridx,
-                    rtmp1,
-                    rtmp1,
-                    rtmp2,
-                    rtmp1,
-                    info.targets
-                )
-            }
-            &Inst::LoadExtName {
-                rd,
-                ref name,
-                offset,
-            } => {
-                let rd = rd.show_rru(mb_rru);
-                format!("ldr {}, 8 ; b 12 ; data {:?} + {}", rd, name, offset)
-            }
-            &Inst::LoadAddr { rd, ref mem } => {
-                // TODO: we really should find a better way to avoid duplication of
-                // this logic between `emit()` and `show_rru()` -- a separate 1-to-N
-                // expansion stage (i.e., legalization, but without the slow edit-in-place
-                // of the existing legalization framework).
-                let (mem_insts, mem) = mem_finalize(0, mem, state);
-                let mut ret = String::new();
-                for inst in mem_insts.into_iter() {
-                    ret.push_str(&inst.show_rru(mb_rru));
-                }
-                let (reg, index_reg, offset) = match mem {
-                    AMode::RegExtended(r, idx, extendop) => (r, Some((idx, extendop)), 0),
-                    AMode::Unscaled(r, simm9) => (r, None, simm9.value()),
-                    AMode::UnsignedOffset(r, uimm12scaled) => {
-                        (r, None, uimm12scaled.value() as i32)
-                    }
-                    _ => panic!("Unsupported case for LoadAddr: {:?}", mem),
-                };
-                let abs_offset = if offset < 0 {
-                    -offset as u64
-                } else {
-                    offset as u64
-                };
-                let alu_op = if offset < 0 { ALUOp::Sub } else { ALUOp::Add };
-
-                if let Some((idx, extendop)) = index_reg {
-                    let add = Inst::AluRRRExtend {
-                        alu_op: ALUOp::Add,
-                        size: OperandSize::Size64,
-                        rd,
-                        rn: reg,
-                        rm: idx,
-                        extendop,
-                    };
-
-                    ret.push_str(&add.show_rru(mb_rru));
-                } else if offset == 0 {
-                    let mov = Inst::gen_move(rd, reg, I64);
-                    ret.push_str(&mov.show_rru(mb_rru));
-                } else if let Some(imm12) = Imm12::maybe_from_u64(abs_offset) {
-                    let add = Inst::AluRRImm12 {
-                        alu_op,
-                        size: OperandSize::Size64,
-                        rd,
-                        rn: reg,
-                        imm12,
-                    };
-                    ret.push_str(&add.show_rru(mb_rru));
-                } else {
-                    let tmp = writable_spilltmp_reg();
-                    for inst in Inst::load_constant(tmp, abs_offset).into_iter() {
-                        ret.push_str(&inst.show_rru(mb_rru));
-                    }
-                    let add = Inst::AluRRR {
-                        alu_op,
-                        size: OperandSize::Size64,
-                        rd,
-                        rn: reg,
-                        rm: tmp.to_reg(),
-                    };
-                    ret.push_str(&add.show_rru(mb_rru));
-                }
-                ret
-            }
-            &Inst::VirtualSPOffsetAdj { offset } => {
-                state.virtual_sp_offset += offset;
-                format!("virtual_sp_offset_adjust {}", offset)
-            }
-            &Inst::EmitIsland { needed_space } => format!("emit_island {}", needed_space),
-
-            &Inst::ElfTlsGetAddr { ref symbol } => {
-                format!("elf_tls_get_addr {}", symbol)
-            }
-
-            &Inst::ValueLabelMarker { label, reg } => {
-                format!("value_label {:?}, {}", label, reg.show_rru(mb_rru))
-            }
-
-            &Inst::Unwind { ref inst } => {
-                format!("unwind {:?}", inst)
-            }
-        }
-    }
-}
-
-//=============================================================================
-// Label fixups and jump veneers.
-
-/// Different forms of label references for different instruction formats.
-#[derive(Clone, Copy, Debug, PartialEq, Eq)]
-pub enum LabelUse {
-    /// 19-bit branch offset (conditional branches). PC-rel, offset is imm << 2. Immediate is 19
-    /// signed bits, in bits 23:5. Used by cbz, cbnz, b.cond.
-    Branch19,
-    /// 26-bit branch offset (unconditional branches). PC-rel, offset is imm << 2. Immediate is 26
-    /// signed bits, in bits 25:0. Used by b, bl.
-    Branch26,
-    /// 19-bit offset for LDR (load literal). PC-rel, offset is imm << 2. Immediate is 19 signed bits,
-    /// in bits 23:5.
-    Ldr19,
-    /// 21-bit offset for ADR (get address of label). PC-rel, offset is not shifted. Immediate is
-    /// 21 signed bits, with high 19 bits in bits 23:5 and low 2 bits in bits 30:29.
-    Adr21,
-    /// 32-bit PC relative constant offset (from address of constant itself),
-    /// signed. Used in jump tables.
-    PCRel32,
-}
-
-impl MachInstLabelUse for LabelUse {
-    /// Alignment for veneer code. Every AArch64 instruction must be 4-byte-aligned.
-    const ALIGN: CodeOffset = 4;
-
-    /// Maximum PC-relative range (positive), inclusive.
-    fn max_pos_range(self) -> CodeOffset {
-        match self {
-            // 19-bit immediate, left-shifted by 2, for 21 bits of total range. Signed, so +2^20
-            // from zero. Likewise for two other shifted cases below.
-            LabelUse::Branch19 => (1 << 20) - 1,
-            LabelUse::Branch26 => (1 << 27) - 1,
-            LabelUse::Ldr19 => (1 << 20) - 1,
-            // Adr does not shift its immediate, so the 21-bit immediate gives 21 bits of total
-            // range.
-            LabelUse::Adr21 => (1 << 20) - 1,
-            LabelUse::PCRel32 => 0x7fffffff,
-        }
-    }
-
-    /// Maximum PC-relative range (negative).
-    fn max_neg_range(self) -> CodeOffset {
-        // All forms are twos-complement signed offsets, so negative limit is one more than
-        // positive limit.
-        self.max_pos_range() + 1
-    }
-
-    /// Size of window into code needed to do the patch.
-    fn patch_size(self) -> CodeOffset {
-        // Patch is on one instruction only for all of these label reference types.
-        4
-    }
-
-    /// Perform the patch.
-    fn patch(self, buffer: &mut [u8], use_offset: CodeOffset, label_offset: CodeOffset) {
-        let pc_rel = (label_offset as i64) - (use_offset as i64);
-        debug_assert!(pc_rel <= self.max_pos_range() as i64);
-        debug_assert!(pc_rel >= -(self.max_neg_range() as i64));
-        let pc_rel = pc_rel as u32;
-        let insn_word = u32::from_le_bytes([buffer[0], buffer[1], buffer[2], buffer[3]]);
-        let mask = match self {
-            LabelUse::Branch19 => 0x00ffffe0, // bits 23..5 inclusive
-            LabelUse::Branch26 => 0x03ffffff, // bits 25..0 inclusive
-            LabelUse::Ldr19 => 0x00ffffe0,    // bits 23..5 inclusive
-            LabelUse::Adr21 => 0x60ffffe0,    // bits 30..29, 25..5 inclusive
-            LabelUse::PCRel32 => 0xffffffff,
-        };
-        let pc_rel_shifted = match self {
-            LabelUse::Adr21 | LabelUse::PCRel32 => pc_rel,
-            _ => {
-                debug_assert!(pc_rel & 3 == 0);
-                pc_rel >> 2
-            }
-        };
-        let pc_rel_inserted = match self {
-            LabelUse::Branch19 | LabelUse::Ldr19 => (pc_rel_shifted & 0x7ffff) << 5,
-            LabelUse::Branch26 => pc_rel_shifted & 0x3ffffff,
-            LabelUse::Adr21 => (pc_rel_shifted & 0x7ffff) << 5 | (pc_rel_shifted & 0x180000) << 10,
-            LabelUse::PCRel32 => pc_rel_shifted,
-        };
-        let is_add = match self {
-            LabelUse::PCRel32 => true,
-            _ => false,
-        };
-        let insn_word = if is_add {
-            insn_word.wrapping_add(pc_rel_inserted)
-        } else {
-            (insn_word & !mask) | pc_rel_inserted
-        };
-        buffer[0..4].clone_from_slice(&u32::to_le_bytes(insn_word));
-    }
-
-    /// Is a veneer supported for this label reference type?
-    fn supports_veneer(self) -> bool {
-        match self {
-            LabelUse::Branch19 => true, // veneer is a Branch26
-            LabelUse::Branch26 => true, // veneer is a PCRel32
-            _ => false,
-        }
-    }
-
-    /// How large is the veneer, if supported?
-    fn veneer_size(self) -> CodeOffset {
-        match self {
-            LabelUse::Branch19 => 4,
-            LabelUse::Branch26 => 20,
-            _ => unreachable!(),
-        }
-    }
-
-    /// Generate a veneer into the buffer, given that this veneer is at `veneer_offset`, and return
-    /// an offset and label-use for the veneer's use of the original label.
-    fn generate_veneer(
-        self,
-        buffer: &mut [u8],
-        veneer_offset: CodeOffset,
-    ) -> (CodeOffset, LabelUse) {
-        match self {
-            LabelUse::Branch19 => {
-                // veneer is a Branch26 (unconditional branch). Just encode directly here -- don't
-                // bother with constructing an Inst.
-                let insn_word = 0b000101 << 26;
-                buffer[0..4].clone_from_slice(&u32::to_le_bytes(insn_word));
-                (veneer_offset, LabelUse::Branch26)
-            }
-
-            // This is promoting a 26-bit call/jump to a 32-bit call/jump to
-            // get a further range. This jump translates to a jump to a
-            // relative location based on the address of the constant loaded
-            // from here.
-            //
-            // If this path is taken from a call instruction then caller-saved
-            // registers are available (minus arguments), so x16/x17 are
-            // available. Otherwise for intra-function jumps we also reserve
-            // x16/x17 as spill-style registers. In both cases these are
-            // available for us to use.
-            LabelUse::Branch26 => {
-                let tmp1 = regs::spilltmp_reg();
-                let tmp1_w = regs::writable_spilltmp_reg();
-                let tmp2 = regs::tmp2_reg();
-                let tmp2_w = regs::writable_tmp2_reg();
-                // ldrsw x16, 16
-                let ldr = emit::enc_ldst_imm19(0b1001_1000, 16 / 4, tmp1);
-                // adr x17, 12
-                let adr = emit::enc_adr(12, tmp2_w);
-                // add x16, x16, x17
-                let add = emit::enc_arith_rrr(0b10001011_000, 0, tmp1_w, tmp1, tmp2);
-                // br x16
-                let br = emit::enc_br(tmp1);
-                buffer[0..4].clone_from_slice(&u32::to_le_bytes(ldr));
-                buffer[4..8].clone_from_slice(&u32::to_le_bytes(adr));
-                buffer[8..12].clone_from_slice(&u32::to_le_bytes(add));
-                buffer[12..16].clone_from_slice(&u32::to_le_bytes(br));
-                // the 4-byte signed immediate we'll load is after these
-                // instructions, 16-bytes in.
-                (veneer_offset + 16, LabelUse::PCRel32)
-            }
-
-            _ => panic!("Unsupported label-reference type for veneer generation!"),
-        }
-    }
-
-    fn from_reloc(reloc: Reloc, addend: Addend) -> Option<LabelUse> {
-        match (reloc, addend) {
-            (Reloc::Arm64Call, 0) => Some(LabelUse::Branch26),
-            _ => None,
-        }
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/inst/regs.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/inst/regs.rs
deleted file mode 100644
index 0b4babe04..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/inst/regs.rs
+++ /dev/null
@@ -1,351 +0,0 @@
-//! AArch64 ISA definitions: registers.
-
-use crate::isa::aarch64::inst::OperandSize;
-use crate::isa::aarch64::inst::ScalarSize;
-use crate::isa::aarch64::inst::VectorSize;
-use crate::settings;
-
-use regalloc::{
-    PrettyPrint, RealRegUniverse, Reg, RegClass, RegClassInfo, Writable, NUM_REG_CLASSES,
-};
-
-use std::string::{String, ToString};
-
-//=============================================================================
-// Registers, the Universe thereof, and printing
-
-/// The pinned register on this architecture.
-/// It must be the same as Spidermonkey's HeapReg, as found in this file.
-/// https://searchfox.org/mozilla-central/source/js/src/jit/arm64/Assembler-arm64.h#103
-pub const PINNED_REG: u8 = 21;
-
-#[rustfmt::skip]
-const XREG_INDICES: [u8; 31] = [
-    // X0 - X7
-    32, 33, 34, 35, 36, 37, 38, 39,
-    // X8 - X15
-    40, 41, 42, 43, 44, 45, 46, 47,
-    // X16, X17
-    58, 59,
-    // X18
-    60,
-    // X19, X20
-    48, 49,
-    // X21, put aside because it's the pinned register.
-    57,
-    // X22 - X28
-    50, 51, 52, 53, 54, 55, 56,
-    // X29 (FP)
-    61,
-    // X30 (LR)
-    62,
-];
-
-const ZERO_REG_INDEX: u8 = 63;
-
-const SP_REG_INDEX: u8 = 64;
-
-/// Get a reference to an X-register (integer register).
-pub fn xreg(num: u8) -> Reg {
-    assert!(num < 31);
-    Reg::new_real(
-        RegClass::I64,
-        /* enc = */ num,
-        /* index = */ XREG_INDICES[num as usize],
-    )
-}
-
-/// Get a writable reference to an X-register.
-pub fn writable_xreg(num: u8) -> Writable<Reg> {
-    Writable::from_reg(xreg(num))
-}
-
-/// Get a reference to a V-register (vector/FP register).
-pub fn vreg(num: u8) -> Reg {
-    assert!(num < 32);
-    Reg::new_real(RegClass::V128, /* enc = */ num, /* index = */ num)
-}
-
-/// Get a writable reference to a V-register.
-pub fn writable_vreg(num: u8) -> Writable<Reg> {
-    Writable::from_reg(vreg(num))
-}
-
-/// Get a reference to the zero-register.
-pub fn zero_reg() -> Reg {
-    // This should be the same as what xreg(31) returns, except that
-    // we use the special index into the register index space.
-    Reg::new_real(
-        RegClass::I64,
-        /* enc = */ 31,
-        /* index = */ ZERO_REG_INDEX,
-    )
-}
-
-/// Get a writable reference to the zero-register (this discards a result).
-pub fn writable_zero_reg() -> Writable<Reg> {
-    Writable::from_reg(zero_reg())
-}
-
-/// Get a reference to the stack-pointer register.
-pub fn stack_reg() -> Reg {
-    // XSP (stack) and XZR (zero) are logically different registers which have
-    // the same hardware encoding, and whose meaning, in real aarch64
-    // instructions, is context-dependent.  For convenience of
-    // universe-construction and for correct printing, we make them be two
-    // different real registers.
-    Reg::new_real(
-        RegClass::I64,
-        /* enc = */ 31,
-        /* index = */ SP_REG_INDEX,
-    )
-}
-
-/// Get a writable reference to the stack-pointer register.
-pub fn writable_stack_reg() -> Writable<Reg> {
-    Writable::from_reg(stack_reg())
-}
-
-/// Get a reference to the link register (x30).
-pub fn link_reg() -> Reg {
-    xreg(30)
-}
-
-/// Get a writable reference to the link register.
-pub fn writable_link_reg() -> Writable<Reg> {
-    Writable::from_reg(link_reg())
-}
-
-/// Get a reference to the frame pointer (x29).
-pub fn fp_reg() -> Reg {
-    xreg(29)
-}
-
-/// Get a writable reference to the frame pointer.
-pub fn writable_fp_reg() -> Writable<Reg> {
-    Writable::from_reg(fp_reg())
-}
-
-/// Get a reference to the first temporary, sometimes "spill temporary", register. This register is
-/// used to compute the address of a spill slot when a direct offset addressing mode from FP is not
-/// sufficient (+/- 2^11 words). We exclude this register from regalloc and reserve it for this
-/// purpose for simplicity; otherwise we need a multi-stage analysis where we first determine how
-/// many spill slots we have, then perhaps remove the reg from the pool and recompute regalloc.
-///
-/// We use x16 for this (aka IP0 in the AArch64 ABI) because it's a scratch register but is
-/// slightly special (used for linker veneers). We're free to use it as long as we don't expect it
-/// to live through call instructions.
-pub fn spilltmp_reg() -> Reg {
-    xreg(16)
-}
-
-/// Get a writable reference to the spilltmp reg.
-pub fn writable_spilltmp_reg() -> Writable<Reg> {
-    Writable::from_reg(spilltmp_reg())
-}
-
-/// Get a reference to the second temp register. We need this in some edge cases
-/// where we need both the spilltmp and another temporary.
-///
-/// We use x17 (aka IP1), the other "interprocedural"/linker-veneer scratch reg that is
-/// free to use otherwise.
-pub fn tmp2_reg() -> Reg {
-    xreg(17)
-}
-
-/// Get a writable reference to the tmp2 reg.
-pub fn writable_tmp2_reg() -> Writable<Reg> {
-    Writable::from_reg(tmp2_reg())
-}
-
-/// Create the register universe for AArch64.
-pub fn create_reg_universe(flags: &settings::Flags) -> RealRegUniverse {
-    let mut regs = vec![];
-    let mut allocable_by_class = [None; NUM_REG_CLASSES];
-
-    // Numbering Scheme: we put V-regs first, then X-regs. The X-regs exclude several registers:
-    // x18 (globally reserved for platform-specific purposes), x29 (frame pointer), x30 (link
-    // register), x31 (stack pointer or zero register, depending on context).
-
-    let v_reg_base = 0u8; // in contiguous real-register index space
-    let v_reg_count = 32;
-    for i in 0u8..v_reg_count {
-        let reg = Reg::new_real(
-            RegClass::V128,
-            /* enc = */ i,
-            /* index = */ v_reg_base + i,
-        )
-        .to_real_reg();
-        let name = format!("v{}", i);
-        regs.push((reg, name));
-    }
-    let v_reg_last = v_reg_base + v_reg_count - 1;
-
-    // Add the X registers. N.B.: the order here must match the order implied
-    // by XREG_INDICES, ZERO_REG_INDEX, and SP_REG_INDEX above.
-
-    let x_reg_base = 32u8; // in contiguous real-register index space
-    let mut x_reg_count = 0;
-
-    let uses_pinned_reg = flags.enable_pinned_reg();
-
-    for i in 0u8..32u8 {
-        // See above for excluded registers.
-        if i == 16 || i == 17 || i == 18 || i == 29 || i == 30 || i == 31 || i == PINNED_REG {
-            continue;
-        }
-        let reg = Reg::new_real(
-            RegClass::I64,
-            /* enc = */ i,
-            /* index = */ x_reg_base + x_reg_count,
-        )
-        .to_real_reg();
-        let name = format!("x{}", i);
-        regs.push((reg, name));
-        x_reg_count += 1;
-    }
-    let x_reg_last = x_reg_base + x_reg_count - 1;
-
-    allocable_by_class[RegClass::I64.rc_to_usize()] = Some(RegClassInfo {
-        first: x_reg_base as usize,
-        last: x_reg_last as usize,
-        suggested_scratch: Some(XREG_INDICES[19] as usize),
-    });
-    allocable_by_class[RegClass::V128.rc_to_usize()] = Some(RegClassInfo {
-        first: v_reg_base as usize,
-        last: v_reg_last as usize,
-        suggested_scratch: Some(/* V31: */ 31),
-    });
-
-    // Other regs, not available to the allocator.
-    let allocable = if uses_pinned_reg {
-        // The pinned register is not allocatable in this case, so record the length before adding
-        // it.
-        let len = regs.len();
-        regs.push((xreg(PINNED_REG).to_real_reg(), "x21/pinned_reg".to_string()));
-        len
-    } else {
-        regs.push((xreg(PINNED_REG).to_real_reg(), "x21".to_string()));
-        regs.len()
-    };
-
-    regs.push((xreg(16).to_real_reg(), "x16".to_string()));
-    regs.push((xreg(17).to_real_reg(), "x17".to_string()));
-    regs.push((xreg(18).to_real_reg(), "x18".to_string()));
-    regs.push((fp_reg().to_real_reg(), "fp".to_string()));
-    regs.push((link_reg().to_real_reg(), "lr".to_string()));
-    regs.push((zero_reg().to_real_reg(), "xzr".to_string()));
-    regs.push((stack_reg().to_real_reg(), "sp".to_string()));
-
-    // FIXME JRS 2020Feb06: unfortunately this pushes the number of real regs
-    // to 65, which is potentially inconvenient from a compiler performance
-    // standpoint.  We could possibly drop back to 64 by "losing" a vector
-    // register in future.
-
-    // Assert sanity: the indices in the register structs must match their
-    // actual indices in the array.
-    for (i, reg) in regs.iter().enumerate() {
-        assert_eq!(i, reg.0.get_index());
-    }
-
-    RealRegUniverse {
-        regs,
-        allocable,
-        allocable_by_class,
-    }
-}
-
-/// If `ireg` denotes an I64-classed reg, make a best-effort attempt to show
-/// its name at the 32-bit size.
-pub fn show_ireg_sized(reg: Reg, mb_rru: Option<&RealRegUniverse>, size: OperandSize) -> String {
-    let mut s = reg.show_rru(mb_rru);
-    if reg.get_class() != RegClass::I64 || !size.is32() {
-        // We can't do any better.
-        return s;
-    }
-
-    if reg.is_real() {
-        // Change (eg) "x42" into "w42" as appropriate
-        if reg.get_class() == RegClass::I64 && size.is32() && s.starts_with("x") {
-            s = "w".to_string() + &s[1..];
-        }
-    } else {
-        // Add a "w" suffix to RegClass::I64 vregs used in a 32-bit role
-        if reg.get_class() == RegClass::I64 && size.is32() {
-            s.push('w');
-        }
-    }
-    s
-}
-
-/// Show a vector register used in a scalar context.
-pub fn show_vreg_scalar(reg: Reg, mb_rru: Option<&RealRegUniverse>, size: ScalarSize) -> String {
-    let mut s = reg.show_rru(mb_rru);
-    if reg.get_class() != RegClass::V128 {
-        // We can't do any better.
-        return s;
-    }
-
-    if reg.is_real() {
-        // Change (eg) "v0" into "d0".
-        if s.starts_with("v") {
-            let replacement = match size {
-                ScalarSize::Size8 => "b",
-                ScalarSize::Size16 => "h",
-                ScalarSize::Size32 => "s",
-                ScalarSize::Size64 => "d",
-                ScalarSize::Size128 => "q",
-            };
-            s.replace_range(0..1, replacement);
-        }
-    } else {
-        // Add a "d" suffix to RegClass::V128 vregs.
-        if reg.get_class() == RegClass::V128 {
-            s.push('d');
-        }
-    }
-    s
-}
-
-/// Show a vector register.
-pub fn show_vreg_vector(reg: Reg, mb_rru: Option<&RealRegUniverse>, size: VectorSize) -> String {
-    assert_eq!(RegClass::V128, reg.get_class());
-    let mut s = reg.show_rru(mb_rru);
-
-    let suffix = match size {
-        VectorSize::Size8x8 => ".8b",
-        VectorSize::Size8x16 => ".16b",
-        VectorSize::Size16x4 => ".4h",
-        VectorSize::Size16x8 => ".8h",
-        VectorSize::Size32x2 => ".2s",
-        VectorSize::Size32x4 => ".4s",
-        VectorSize::Size64x2 => ".2d",
-    };
-
-    s.push_str(suffix);
-    s
-}
-
-/// Show an indexed vector element.
-pub fn show_vreg_element(
-    reg: Reg,
-    mb_rru: Option<&RealRegUniverse>,
-    idx: u8,
-    size: VectorSize,
-) -> String {
-    assert_eq!(RegClass::V128, reg.get_class());
-    let mut s = reg.show_rru(mb_rru);
-
-    let suffix = match size {
-        VectorSize::Size8x8 => "b",
-        VectorSize::Size8x16 => "b",
-        VectorSize::Size16x4 => "h",
-        VectorSize::Size16x8 => "h",
-        VectorSize::Size32x2 => "s",
-        VectorSize::Size32x4 => "s",
-        VectorSize::Size64x2 => "d",
-    };
-
-    s.push_str(&format!(".{}[{}]", suffix, idx));
-    s
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/inst/unwind.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/inst/unwind.rs
deleted file mode 100644
index 1e2bb904d..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/inst/unwind.rs
+++ /dev/null
@@ -1,2 +0,0 @@
-#[cfg(feature = "unwind")]
-pub(crate) mod systemv;
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/inst/unwind/systemv.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/inst/unwind/systemv.rs
deleted file mode 100644
index 12651427b..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/inst/unwind/systemv.rs
+++ /dev/null
@@ -1,177 +0,0 @@
-//! Unwind information for System V ABI (Aarch64).
-
-use crate::isa::aarch64::inst::regs;
-use crate::isa::unwind::systemv::RegisterMappingError;
-use gimli::{write::CommonInformationEntry, Encoding, Format, Register};
-use regalloc::{Reg, RegClass};
-
-/// Creates a new aarch64 common information entry (CIE).
-pub fn create_cie() -> CommonInformationEntry {
-    use gimli::write::CallFrameInstruction;
-
-    let mut entry = CommonInformationEntry::new(
-        Encoding {
-            address_size: 8,
-            format: Format::Dwarf32,
-            version: 1,
-        },
-        4,  // Code alignment factor
-        -8, // Data alignment factor
-        Register(regs::link_reg().get_hw_encoding().into()),
-    );
-
-    // Every frame will start with the call frame address (CFA) at SP
-    let sp = Register(regs::stack_reg().get_hw_encoding().into());
-    entry.add_instruction(CallFrameInstruction::Cfa(sp, 0));
-
-    entry
-}
-
-/// Map Cranelift registers to their corresponding Gimli registers.
-pub fn map_reg(reg: Reg) -> Result<Register, RegisterMappingError> {
-    // For AArch64 DWARF register mappings, see:
-    //
-    // https://developer.arm.com/documentation/ihi0057/e/?lang=en#dwarf-register-names
-    //
-    // X0--X31 is 0--31; V0--V31 is 64--95.
-    match reg.get_class() {
-        RegClass::I64 => {
-            let reg = reg.get_hw_encoding() as u16;
-            Ok(Register(reg))
-        }
-        RegClass::V128 => {
-            let reg = reg.get_hw_encoding() as u16;
-            Ok(Register(64 + reg))
-        }
-        _ => Err(RegisterMappingError::UnsupportedRegisterBank("class?")),
-    }
-}
-
-pub(crate) struct RegisterMapper;
-
-impl crate::isa::unwind::systemv::RegisterMapper<Reg> for RegisterMapper {
-    fn map(&self, reg: Reg) -> Result<u16, RegisterMappingError> {
-        Ok(map_reg(reg)?.0)
-    }
-    fn sp(&self) -> u16 {
-        regs::stack_reg().get_hw_encoding().into()
-    }
-    fn fp(&self) -> Option<u16> {
-        Some(regs::fp_reg().get_hw_encoding().into())
-    }
-    fn lr(&self) -> Option<u16> {
-        Some(regs::link_reg().get_hw_encoding().into())
-    }
-    fn lr_offset(&self) -> Option<u32> {
-        Some(8)
-    }
-}
-
-#[cfg(test)]
-mod tests {
-    use crate::cursor::{Cursor, FuncCursor};
-    use crate::ir::{
-        types, AbiParam, ExternalName, Function, InstBuilder, Signature, StackSlotData,
-        StackSlotKind,
-    };
-    use crate::isa::{lookup, CallConv};
-    use crate::settings::{builder, Flags};
-    use crate::Context;
-    use gimli::write::Address;
-    use std::str::FromStr;
-    use target_lexicon::triple;
-
-    #[test]
-    fn test_simple_func() {
-        let isa = lookup(triple!("aarch64"))
-            .expect("expect aarch64 ISA")
-            .finish(Flags::new(builder()))
-            .expect("Creating compiler backend");
-
-        let mut context = Context::for_function(create_function(
-            CallConv::SystemV,
-            Some(StackSlotData::new(StackSlotKind::ExplicitSlot, 64)),
-        ));
-
-        context.compile(&*isa).expect("expected compilation");
-
-        let fde = match context
-            .create_unwind_info(isa.as_ref())
-            .expect("can create unwind info")
-        {
-            Some(crate::isa::unwind::UnwindInfo::SystemV(info)) => {
-                info.to_fde(Address::Constant(1234))
-            }
-            _ => panic!("expected unwind information"),
-        };
-
-        assert_eq!(format!("{:?}", fde), "FrameDescriptionEntry { address: Constant(1234), length: 24, lsda: None, instructions: [(0, ValExpression(Register(34), Expression { operations: [Simple(DwOp(48))] })), (4, CfaOffset(16)), (4, Offset(Register(29), -16)), (4, Offset(Register(30), -8)), (8, CfaRegister(Register(29)))] }");
-    }
-
-    fn create_function(call_conv: CallConv, stack_slot: Option<StackSlotData>) -> Function {
-        let mut func =
-            Function::with_name_signature(ExternalName::user(0, 0), Signature::new(call_conv));
-
-        let block0 = func.dfg.make_block();
-        let mut pos = FuncCursor::new(&mut func);
-        pos.insert_block(block0);
-        pos.ins().return_(&[]);
-
-        if let Some(stack_slot) = stack_slot {
-            func.stack_slots.push(stack_slot);
-        }
-
-        func
-    }
-
-    #[test]
-    fn test_multi_return_func() {
-        let isa = lookup(triple!("aarch64"))
-            .expect("expect aarch64 ISA")
-            .finish(Flags::new(builder()))
-            .expect("Creating compiler backend");
-
-        let mut context = Context::for_function(create_multi_return_function(CallConv::SystemV));
-
-        context.compile(&*isa).expect("expected compilation");
-
-        let fde = match context
-            .create_unwind_info(isa.as_ref())
-            .expect("can create unwind info")
-        {
-            Some(crate::isa::unwind::UnwindInfo::SystemV(info)) => {
-                info.to_fde(Address::Constant(4321))
-            }
-            _ => panic!("expected unwind information"),
-        };
-
-        assert_eq!(
-            format!("{:?}", fde),
-            "FrameDescriptionEntry { address: Constant(4321), length: 16, lsda: None, instructions: [(0, ValExpression(Register(34), Expression { operations: [Simple(DwOp(48))] }))] }"
-        );
-    }
-
-    fn create_multi_return_function(call_conv: CallConv) -> Function {
-        let mut sig = Signature::new(call_conv);
-        sig.params.push(AbiParam::new(types::I32));
-        let mut func = Function::with_name_signature(ExternalName::user(0, 0), sig);
-
-        let block0 = func.dfg.make_block();
-        let v0 = func.dfg.append_block_param(block0, types::I32);
-        let block1 = func.dfg.make_block();
-        let block2 = func.dfg.make_block();
-
-        let mut pos = FuncCursor::new(&mut func);
-        pos.insert_block(block0);
-        pos.ins().brnz(v0, block2, &[]);
-        pos.ins().jump(block1, &[]);
-
-        pos.insert_block(block1);
-        pos.ins().return_(&[]);
-
-        pos.insert_block(block2);
-        pos.ins().return_(&[]);
-
-        func
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/lower.isle b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/lower.isle
deleted file mode 100644
index 50a97d920..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/lower.isle
+++ /dev/null
@@ -1,1126 +0,0 @@
-;; aarch64 instruction selection and CLIF-to-MachInst lowering.
-
-;; The main lowering constructor term: takes a clif `Inst` and returns the
-;; register(s) within which the lowered instruction's result values live.
-(decl lower (Inst) InstOutput)
-
-;;;; Rules for `iconst` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type ty (iconst (u64_from_imm64 n))))
-      (imm ty n))
-
-;;;; Rules for `bconst` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type ty (bconst $false)))
-      (imm ty 0))
-
-(rule (lower (has_type ty (bconst $true)))
-      (imm ty 1))
-
-;;;; Rules for `null` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type ty (null)))
-      (imm ty 0))
-
-;;;; Rules for `iadd` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; `i64` and smaller
-
-;; Base case, simply adding things in registers.
-(rule (lower (has_type (fits_in_64 ty) (iadd x y)))
-      (add ty  x y))
-
-;; Special cases for when one operand is an immediate that fits in 12 bits.
-(rule (lower (has_type (fits_in_64 ty) (iadd x (imm12_from_value y))))
-      (add_imm ty x y))
-
-(rule (lower (has_type (fits_in_64 ty) (iadd (imm12_from_value x) y)))
-      (add_imm ty y x))
-
-;; Same as the previous special cases, except we can switch the addition to a
-;; subtraction if the negated immediate fits in 12 bits.
-(rule (lower (has_type (fits_in_64 ty) (iadd x (imm12_from_negated_value y))))
-      (sub_imm ty x y))
-
-(rule (lower (has_type (fits_in_64 ty) (iadd (imm12_from_negated_value x) y)))
-      (sub_imm ty y x))
-
-;; Special cases for when we're adding an extended register where the extending
-;; operation can get folded into the add itself.
-(rule (lower (has_type (fits_in_64 ty) (iadd x (extended_value_from_value y))))
-      (add_extend ty x y))
-
-(rule (lower (has_type (fits_in_64 ty) (iadd (extended_value_from_value x) y)))
-      (add_extend ty y x))
-
-;; Special cases for when we're adding the shift of a different
-;; register by a constant amount and the shift can get folded into the add.
-(rule (lower (has_type (fits_in_64 ty)
-                       (iadd x (ishl y (iconst (lshl_from_imm64 <ty amt))))))
-      (add_shift ty x y amt))
-
-(rule (lower (has_type (fits_in_64 ty)
-                       (iadd (ishl x (iconst (lshl_from_imm64 <ty amt))) y)))
-      (add_shift ty y x amt))
-
-;; Fold an `iadd` and `imul` combination into a `madd` instruction.
-(rule (lower (has_type (fits_in_64 ty) (iadd x (imul y z))))
-      (madd ty y z x))
-
-(rule (lower (has_type (fits_in_64 ty) (iadd (imul x y) z)))
-      (madd ty x y z))
-
-;; vectors
-
-(rule (lower (has_type ty @ (multi_lane _ _) (iadd x y)))
-      (add_vec x y (vector_size ty)))
-
-;; `i128`
-(rule (lower (has_type $I128 (iadd x y)))
-      (let
-          ;; Get the high/low registers for `x`.
-          ((x_regs ValueRegs x)
-           (x_lo Reg (value_regs_get x_regs 0))
-           (x_hi Reg (value_regs_get x_regs 1))
-
-           ;; Get the high/low registers for `y`.
-           (y_regs ValueRegs y)
-           (y_lo Reg (value_regs_get y_regs 0))
-           (y_hi Reg (value_regs_get y_regs 1)))
-        ;; the actual addition is `adds` followed by `adc` which comprises the
-        ;; low/high bits of the result
-        (with_flags
-          (add_with_flags_paired $I64 x_lo y_lo)
-          (adc_paired $I64 x_hi y_hi))))
-
-;;;; Rules for `isub` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; `i64` and smaller
-
-;; Base case, simply subtracting things in registers.
-(rule (lower (has_type (fits_in_64 ty) (isub x y)))
-      (sub ty x y))
-
-;; Special case for when one operand is an immediate that fits in 12 bits.
-(rule (lower (has_type (fits_in_64 ty) (isub x (imm12_from_value y))))
-      (sub_imm ty x y))
-
-;; Same as the previous special case, except we can switch the subtraction to an
-;; addition if the negated immediate fits in 12 bits.
-(rule (lower (has_type (fits_in_64 ty) (isub x (imm12_from_negated_value y))))
-      (add_imm ty x y))
-
-;; Special cases for when we're subtracting an extended register where the
-;; extending operation can get folded into the sub itself.
-(rule (lower (has_type (fits_in_64 ty) (isub x (extended_value_from_value y))))
-      (sub_extend ty x y))
-
-;; Finally a special case for when we're subtracting the shift of a different
-;; register by a constant amount and the shift can get folded into the sub.
-(rule (lower (has_type (fits_in_64 ty)
-                       (isub x (ishl y (iconst (lshl_from_imm64 <ty amt))))))
-      (sub_shift ty x y amt))
-
-;; vectors
-(rule (lower (has_type ty @ (multi_lane _ _) (isub x y)))
-      (sub_vec x y (vector_size ty)))
-
-;; `i128`
-(rule (lower (has_type $I128 (isub x y)))
-      (let
-          ;; Get the high/low registers for `x`.
-          ((x_regs ValueRegs x)
-           (x_lo Reg (value_regs_get x_regs 0))
-           (x_hi Reg (value_regs_get x_regs 1))
-
-           ;; Get the high/low registers for `y`.
-           (y_regs ValueRegs y)
-           (y_lo Reg (value_regs_get y_regs 0))
-           (y_hi Reg (value_regs_get y_regs 1)))
-        ;; the actual subtraction is `subs` followed by `sbc` which comprises
-        ;; the low/high bits of the result
-        (with_flags
-          (sub_with_flags_paired $I64 x_lo y_lo)
-          (sbc_paired $I64 x_hi y_hi))))
-
-;;;; Rules for `uadd_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type (vec128 ty) (uadd_sat x y)))
-      (uqadd x y (vector_size ty)))
-
-;;;; Rules for `sadd_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type (vec128 ty) (sadd_sat x y)))
-      (sqadd x y (vector_size ty)))
-
-;;;; Rules for `usub_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type (vec128 ty) (usub_sat x y)))
-      (uqsub x y (vector_size ty)))
-
-;;;; Rules for `ssub_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type (vec128 ty) (ssub_sat x y)))
-      (sqsub x y (vector_size ty)))
-
-;;;; Rules for `ineg` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; `i64` and smaller.
-(rule (lower (has_type (fits_in_64 ty) (ineg x)))
-      (sub ty (zero_reg) x))
-
-;; vectors.
-(rule (lower (has_type (vec128 ty) (ineg x)))
-      (neg x (vector_size ty)))
-
-;;;; Rules for `imul` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; `i64` and smaller.
-(rule (lower (has_type (fits_in_64 ty) (imul x y)))
-      (madd ty x y (zero_reg)))
-
-;; `i128`.
-(rule (lower (has_type $I128 (imul x y)))
-      (let
-          ;; Get the high/low registers for `x`.
-          ((x_regs ValueRegs x)
-           (x_lo Reg (value_regs_get x_regs 0))
-           (x_hi Reg (value_regs_get x_regs 1))
-
-           ;; Get the high/low registers for `y`.
-           (y_regs ValueRegs y)
-           (y_lo Reg (value_regs_get y_regs 0))
-           (y_hi Reg (value_regs_get y_regs 1))
-
-           ;; 128bit mul formula:
-           ;;   dst_lo = x_lo * y_lo
-           ;;   dst_hi = umulhi(x_lo, y_lo) + (x_lo * y_hi) + (x_hi * y_lo)
-           ;;
-           ;; We can convert the above formula into the following
-           ;; umulh   dst_hi, x_lo, y_lo
-           ;; madd    dst_hi, x_lo, y_hi, dst_hi
-           ;; madd    dst_hi, x_hi, y_lo, dst_hi
-           ;; madd    dst_lo, x_lo, y_lo, zero
-           (dst_hi1 Reg (umulh $I64 x_lo y_lo))
-           (dst_hi2 Reg (madd64 x_lo y_hi dst_hi1))
-           (dst_hi Reg (madd64 x_hi y_lo dst_hi2))
-           (dst_lo Reg (madd64 x_lo y_lo (zero_reg))))
-        (value_regs dst_lo dst_hi)))
-
-;; Case for i8x16, i16x8, and i32x4.
-(rule (lower (has_type (vec128 ty @ (not_i64x2)) (imul x y)))
-      (mul x y (vector_size ty)))
-
-;; Special lowering for i64x2.
-;;
-;; This I64X2 multiplication is performed with several 32-bit
-;; operations.
-;;
-;; 64-bit numbers x and y, can be represented as:
-;;   x = a + 2^32(b)
-;;   y = c + 2^32(d)
-;;
-;; A 64-bit multiplication is:
-;;   x * y = ac + 2^32(ad + bc) + 2^64(bd)
-;; note: `2^64(bd)` can be ignored, the value is too large to fit in
-;; 64 bits.
-;;
-;; This sequence implements a I64X2 multiply, where the registers
-;; `rn` and `rm` are split up into 32-bit components:
-;;   rn = |d|c|b|a|
-;;   rm = |h|g|f|e|
-;;
-;;   rn * rm = |cg + 2^32(ch + dg)|ae + 2^32(af + be)|
-;;
-;;  The sequence is:
-;;  rev64 rd.4s, rm.4s
-;;  mul rd.4s, rd.4s, rn.4s
-;;  xtn tmp1.2s, rn.2d
-;;  addp rd.4s, rd.4s, rd.4s
-;;  xtn tmp2.2s, rm.2d
-;;  shll rd.2d, rd.2s, #32
-;;  umlal rd.2d, tmp2.2s, tmp1.2s
-(rule (lower (has_type $I64X2 (imul x y)))
-      (let ((rn Reg x)
-            (rm Reg y)
-            ;; Reverse the 32-bit elements in the 64-bit words.
-            ;;   rd = |g|h|e|f|
-            (rev Reg (rev64 rm (VectorSize.Size32x4)))
-
-            ;; Calculate the high half components.
-            ;;   rd = |dg|ch|be|af|
-            ;;
-            ;; Note that this 32-bit multiply of the high half
-            ;; discards the bits that would overflow, same as
-            ;; if 64-bit operations were used. Also the Shll
-            ;; below would shift out the overflow bits anyway.
-            (mul Reg (mul rev rn (VectorSize.Size32x4)))
-
-            ;; Extract the low half components of rn.
-            ;;   tmp1 = |c|a|
-            (tmp1 Reg (xtn64 rn $false))
-
-            ;; Sum the respective high half components.
-            ;;   rd = |dg+ch|be+af||dg+ch|be+af|
-            (sum Reg (addp mul mul (VectorSize.Size32x4)))
-
-            ;; Extract the low half components of rm.
-            ;;   tmp2 = |g|e|
-            (tmp2 Reg (xtn64 rm $false))
-
-            ;; Shift the high half components, into the high half.
-            ;;   rd = |dg+ch << 32|be+af << 32|
-            (shift Reg (shll32 sum $false))
-
-            ;; Multiply the low components together, and accumulate with the high
-            ;; half.
-            ;;   rd = |rd[1] + cg|rd[0] + ae|
-            (result Reg (umlal32 shift tmp2 tmp1 $false)))
-        result))
-
-;; Special case for `i16x8.extmul_low_i8x16_s`.
-(rule (lower (has_type $I16X8
-                       (imul (swiden_low x @ (value_type $I8X16))
-                             (swiden_low y @ (value_type $I8X16)))))
-      (smull8 x y $false))
-
-;; Special case for `i16x8.extmul_high_i8x16_s`.
-(rule (lower (has_type $I16X8
-                       (imul (swiden_high x @ (value_type $I8X16))
-                             (swiden_high y @ (value_type $I8X16)))))
-      (smull8 x y $true))
-
-;; Special case for `i16x8.extmul_low_i8x16_u`.
-(rule (lower (has_type $I16X8
-                       (imul (uwiden_low x @ (value_type $I8X16))
-                             (uwiden_low y @ (value_type $I8X16)))))
-      (umull8 x y $false))
-
-;; Special case for `i16x8.extmul_high_i8x16_u`.
-(rule (lower (has_type $I16X8
-                       (imul (uwiden_high x @ (value_type $I8X16))
-                             (uwiden_high y @ (value_type $I8X16)))))
-      (umull8 x y $true))
-
-;; Special case for `i32x4.extmul_low_i16x8_s`.
-(rule (lower (has_type $I32X4
-                       (imul (swiden_low x @ (value_type $I16X8))
-                             (swiden_low y @ (value_type $I16X8)))))
-      (smull16 x y $false))
-
-;; Special case for `i32x4.extmul_high_i16x8_s`.
-(rule (lower (has_type $I32X4
-                       (imul (swiden_high x @ (value_type $I16X8))
-                             (swiden_high y @ (value_type $I16X8)))))
-      (smull16 x y $true))
-
-;; Special case for `i32x4.extmul_low_i16x8_u`.
-(rule (lower (has_type $I32X4
-                       (imul (uwiden_low x @ (value_type $I16X8))
-                             (uwiden_low y @ (value_type $I16X8)))))
-      (umull16 x y $false))
-
-;; Special case for `i32x4.extmul_high_i16x8_u`.
-(rule (lower (has_type $I32X4
-                       (imul (uwiden_high x @ (value_type $I16X8))
-                             (uwiden_high y @ (value_type $I16X8)))))
-      (umull16 x y $true))
-
-;; Special case for `i64x2.extmul_low_i32x4_s`.
-(rule (lower (has_type $I64X2
-                       (imul (swiden_low x @ (value_type $I32X4))
-                             (swiden_low y @ (value_type $I32X4)))))
-      (smull32 x y $false))
-
-;; Special case for `i64x2.extmul_high_i32x4_s`.
-(rule (lower (has_type $I64X2
-                       (imul (swiden_high x @ (value_type $I32X4))
-                             (swiden_high y @ (value_type $I32X4)))))
-      (smull32 x y $true))
-
-;; Special case for `i64x2.extmul_low_i32x4_u`.
-(rule (lower (has_type $I64X2
-                       (imul (uwiden_low x @ (value_type $I32X4))
-                             (uwiden_low y @ (value_type $I32X4)))))
-      (umull32 x y $false))
-
-;; Special case for `i64x2.extmul_high_i32x4_u`.
-(rule (lower (has_type $I64X2
-                       (imul (uwiden_high x @ (value_type $I32X4))
-                             (uwiden_high y @ (value_type $I32X4)))))
-      (umull32 x y $true))
-
-;;;; Rules for `smulhi` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type $I64 (smulhi x y)))
-      (smulh $I64 x y))
-
-(rule (lower (has_type (fits_in_32 ty) (smulhi x y)))
-      (let ((x64 Reg (put_in_reg_sext64 x))
-            (y64 Reg (put_in_reg_sext64 y))
-            (mul Reg (madd64 x64 y64 (zero_reg)))
-            (result Reg (asr_imm $I64 mul (imm_shift_from_u8 (ty_bits ty)))))
-        result))
-
-;;;; Rules for `umulhi` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type $I64 (umulhi x y)))
-      (umulh $I64 x y))
-
-(rule (lower (has_type (fits_in_32 ty) (umulhi x y)))
-      (let ((x64 Reg (put_in_reg_zext64 x))
-            (y64 Reg (put_in_reg_zext64 y))
-            (mul Reg (madd64 x64 y64 (zero_reg)))
-            (result Reg (lsr_imm $I64 mul (imm_shift_from_u8 (ty_bits ty)))))
-        result))
-
-;;;; Rules for `udiv` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; TODO: Add UDiv32 to implement 32-bit directly, rather
-;; than extending the input.
-;;
-;; Note that aarch64's `udiv` doesn't trap so to respect the semantics of
-;; CLIF's `udiv` the check for zero needs to be manually performed.
-(rule (lower (has_type (fits_in_64 ty) (udiv x y)))
-      (a64_udiv $I64 (put_in_reg_zext64 x) (put_nonzero_in_reg_zext64 y)))
-
-;; Helper for placing a `Value` into a `Reg` and validating that it's nonzero.
-(decl put_nonzero_in_reg_zext64 (Value) Reg)
-(rule (put_nonzero_in_reg_zext64 val)
-      (trap_if_zero_divisor (put_in_reg_zext64 val)))
-
-;; Special case where if a `Value` is known to be nonzero we can trivially
-;; move it into a register.
-(rule (put_nonzero_in_reg_zext64 (and (value_type ty)
-                                      (iconst (nonzero_u64_from_imm64 n))))
-      (imm ty n))
-
-;;;; Rules for `sdiv` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; TODO: Add SDiv32 to implement 32-bit directly, rather
-;; than extending the input.
-;;
-;; The sequence of checks here should look like:
-;;
-;;   cbnz rm, #8
-;;   udf ; divide by zero
-;;   cmn rm, 1
-;;   ccmp rn, 1, #nzcv, eq
-;;   b.vc #8
-;;   udf ; signed overflow
-;;
-;; Note The div instruction does not trap on divide by zero or overflow, so
-;; checks need to be manually inserted.
-;;
-;; TODO: if `y` is -1 then a check that `x` is not INT_MIN is all that's
-;; necessary, but right now `y` is checked to not be -1 as well.
-(rule (lower (has_type (fits_in_64 ty) (sdiv x y)))
-      (let ((x64 Reg (put_in_reg_sext64 x))
-            (y64 Reg (put_nonzero_in_reg_sext64 y))
-            (valid_x64 Reg (trap_if_div_overflow ty x64 y64))
-            (result Reg (a64_sdiv $I64 valid_x64 y64)))
-        result))
-
-;; Helper for extracting an immediate that's not 0 and not -1 from an imm64.
-(decl safe_divisor_from_imm64 (u64) Imm64)
-(extern extractor safe_divisor_from_imm64 safe_divisor_from_imm64)
-
-;; Special case for `sdiv` where no checks are needed due to division by a
-;; constant meaning the checks are always passed.
-(rule (lower (has_type (fits_in_64 ty) (sdiv x (iconst (safe_divisor_from_imm64 y)))))
-      (a64_sdiv $I64 (put_in_reg_sext64 x) (imm ty y)))
-
-;; Helper for placing a `Value` into a `Reg` and validating that it's nonzero.
-(decl put_nonzero_in_reg_sext64 (Value) Reg)
-(rule (put_nonzero_in_reg_sext64 val)
-      (trap_if_zero_divisor (put_in_reg_sext64 val)))
-
-;; Note that this has a special case where if the `Value` is a constant that's
-;; not zero we can skip the zero check.
-(rule (put_nonzero_in_reg_sext64 (and (value_type ty)
-                                      (iconst (nonzero_u64_from_imm64 n))))
-      (imm ty n))
-
-;;;; Rules for `urem` and `srem` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Remainder (x % y) is implemented as:
-;;
-;;   tmp = x / y
-;;   result = x - (tmp*y)
-;;
-;; use 'result' for tmp and you have:
-;;
-;;   cbnz y, #8         ; branch over trap
-;;   udf                ; divide by zero
-;;   div rd, x, y       ; rd = x / y
-;;   msub rd, rd, y, x  ; rd = x - rd * y
-
-(rule (lower (has_type (fits_in_64 ty) (urem x y)))
-      (let ((x64 Reg (put_in_reg_zext64 x))
-            (y64 Reg (put_nonzero_in_reg_zext64 y))
-            (div Reg (a64_udiv $I64 x64 y64))
-            (result Reg (msub64 div y64 x64)))
-        result))
-
-(rule (lower (has_type (fits_in_64 ty) (srem x y)))
-      (let ((x64 Reg (put_in_reg_sext64 x))
-            (y64 Reg (put_nonzero_in_reg_sext64 y))
-            (div Reg (a64_sdiv $I64 x64 y64))
-            (result Reg (msub64 div y64 x64)))
-        result))
-
-;;;; Rules for `uextend` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; General rule for extending input to an output which fits in a single
-;; register.
-(rule (lower (has_type (fits_in_64 out) (uextend x @ (value_type in))))
-      (extend x $false (ty_bits in) (ty_bits out)))
-
-;; Extraction of a vector lane automatically extends as necessary, so we can
-;; skip an explicit extending instruction.
-(rule (lower (has_type (fits_in_64 out)
-                       (uextend (extractlane vec @ (value_type in)
-                                             (u8_from_uimm8 lane)))))
-      (mov_from_vec (put_in_reg vec) lane (vector_size in)))
-
-;; Atomic loads will also automatically zero their upper bits so the `uextend`
-;; instruction can effectively get skipped here.
-(rule (lower (has_type (fits_in_64 out)
-                       (uextend (and (value_type in) (sinkable_atomic_load addr)))))
-      (load_acquire in (sink_atomic_load addr)))
-
-;; Conversion to 128-bit needs a zero-extension of the lower bits and the upper
-;; bits are all zero.
-(rule (lower (has_type $I128 (uextend x)))
-      (value_regs (put_in_reg_zext64 x) (imm $I64 0)))
-
-;; Like above where vector extraction automatically zero-extends extending to
-;; i128 only requires generating a 0 constant for the upper bits.
-(rule (lower (has_type $I128
-                       (uextend (extractlane vec @ (value_type in)
-                                             (u8_from_uimm8 lane)))))
-      (value_regs (mov_from_vec (put_in_reg vec) lane (vector_size in)) (imm $I64 0)))
-
-;;;; Rules for `sextend` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; General rule for extending input to an output which fits in a single
-;; register.
-(rule (lower (has_type (fits_in_64 out) (sextend x @ (value_type in))))
-      (extend x $true (ty_bits in) (ty_bits out)))
-
-;; Extraction of a vector lane automatically extends as necessary, so we can
-;; skip an explicit extending instruction.
-(rule (lower (has_type (fits_in_64 out)
-                       (sextend (extractlane vec @ (value_type in)
-                                             (u8_from_uimm8 lane)))))
-      (mov_from_vec_signed (put_in_reg vec)
-                           lane
-                           (vector_size in)
-                           (size_from_ty out)))
-
-;; 64-bit to 128-bit only needs to sign-extend the input to the upper bits.
-(rule (lower (has_type $I128 (sextend x)))
-      (let ((lo Reg (put_in_reg_sext64 x))
-            (hi Reg (asr_imm $I64 lo (imm_shift_from_u8 63))))
-        (value_regs lo hi)))
-
-;; Like above where vector extraction automatically zero-extends extending to
-;; i128 only requires generating a 0 constant for the upper bits.
-;;
-;; Note that `mov_from_vec_signed` doesn't exist for i64x2, so that's
-;; specifically excluded here.
-(rule (lower (has_type $I128
-                       (sextend (extractlane vec @ (value_type in @ (not_i64x2))
-                                             (u8_from_uimm8 lane)))))
-      (let ((lo Reg (mov_from_vec_signed (put_in_reg vec)
-                                         lane
-                                         (vector_size in)
-                                         (size_from_ty $I64)))
-            (hi Reg (asr_imm $I64 lo (imm_shift_from_u8 63))))
-        (value_regs lo hi)))
-
-;; Extension from an extraction of i64x2 into i128.
-(rule (lower (has_type $I128
-                       (sextend (extractlane vec @ (value_type $I64X2)
-                                             (u8_from_uimm8 lane)))))
-      (let ((lo Reg (mov_from_vec (put_in_reg vec)
-                                  lane
-                                  (VectorSize.Size64x2)))
-            (hi Reg (asr_imm $I64 lo (imm_shift_from_u8 63))))
-        (value_regs lo hi)))
-
-;;;; Rules for `bnot` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Base case using `orn` between two registers.
-;;
-;; Note that bitwise negation is implemented here as
-;;
-;;      NOT rd, rm ==> ORR_NOT rd, zero, rm
-(rule (lower (has_type (fits_in_64 ty) (bnot x)))
-      (orr_not ty (zero_reg) x))
-
-;; Special case to use `orr_not_shift` if it's a `bnot` of a const-left-shifted
-;; value.
-(rule (lower (has_type (fits_in_64 ty)
-                       (bnot (ishl x (iconst (lshl_from_imm64 <ty amt))))))
-      (orr_not_shift ty (zero_reg) x amt))
-
-;; Implementation of `bnot` for `i128`.
-(rule (lower (has_type $I128 (bnot x)))
-      (let ((x_regs ValueRegs x)
-            (x_lo Reg (value_regs_get x_regs 0))
-            (x_hi Reg (value_regs_get x_regs 1))
-            (new_lo Reg (orr_not $I64 (zero_reg) x_lo))
-            (new_hi Reg (orr_not $I64 (zero_reg) x_hi)))
-        (value_regs new_lo new_hi)))
-
-;; Implementation of `bnot` for vector types.
-(rule (lower (has_type (vec128 ty) (bnot x)))
-      (not x (vector_size ty)))
-
-;;;; Rules for `band` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type (fits_in_32 ty) (band x y)))
-      (alu_rs_imm_logic_commutative (ALUOp.And) ty x y))
-
-(rule (lower (has_type $I64 (band x y)))
-      (alu_rs_imm_logic_commutative (ALUOp.And) $I64 x y))
-
-(rule (lower (has_type $I128 (band x y))) (i128_alu_bitop (ALUOp.And) $I64 x y))
-
-(rule (lower (has_type (vec128 ty) (band x y)))
-      (and_vec x y (vector_size ty)))
-
-;;;; Rules for `bor` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type (fits_in_32 ty) (bor x y)))
-      (alu_rs_imm_logic_commutative (ALUOp.Orr) ty x y))
-
-(rule (lower (has_type $I64 (bor x y)))
-      (alu_rs_imm_logic_commutative (ALUOp.Orr) $I64 x y))
-
-(rule (lower (has_type $I128 (bor x y))) (i128_alu_bitop (ALUOp.Orr) $I64 x y))
-
-(rule (lower (has_type (vec128 ty) (bor x y)))
-      (orr_vec x y (vector_size ty)))
-
-;;;; Rules for `bxor` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type (fits_in_32 ty) (bxor x y)))
-      (alu_rs_imm_logic_commutative (ALUOp.Eor) ty x y))
-
-(rule (lower (has_type $I64 (bxor x y)))
-      (alu_rs_imm_logic_commutative (ALUOp.Eor) $I64 x y))
-
-(rule (lower (has_type $I128 (bxor x y))) (i128_alu_bitop (ALUOp.Eor) $I64 x y))
-
-(rule (lower (has_type (vec128 ty) (bxor x y)))
-      (eor_vec x y (vector_size ty)))
-
-;;;; Rules for `band_not` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type (fits_in_32 ty) (band_not x y)))
-      (alu_rs_imm_logic (ALUOp.AndNot) ty x y))
-
-(rule (lower (has_type $I64 (band_not x y)))
-      (alu_rs_imm_logic (ALUOp.AndNot) $I64 x y))
-
-(rule (lower (has_type $I128 (band_not x y))) (i128_alu_bitop (ALUOp.AndNot) $I64 x y))
-
-(rule (lower (has_type (vec128 ty) (band_not x y)))
-      (bic_vec x y (vector_size ty)))
-
-;;;; Rules for `bor_not` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type (fits_in_32 ty) (bor_not x y)))
-      (alu_rs_imm_logic (ALUOp.OrrNot) ty x y))
-
-(rule (lower (has_type $I64 (bor_not x y)))
-      (alu_rs_imm_logic (ALUOp.OrrNot) $I64 x y))
-
-(rule (lower (has_type $I128 (bor_not x y))) (i128_alu_bitop (ALUOp.OrrNot) $I64 x y))
-
-;;;; Rules for `bxor_not` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type (fits_in_32 ty) (bxor_not x y)))
-      (alu_rs_imm_logic (ALUOp.EorNot) $I32 x y))
-
-(rule (lower (has_type $I64 (bxor_not x y)))
-      (alu_rs_imm_logic (ALUOp.EorNot) $I64 x y))
-
-(rule (lower (has_type $I128 (bxor_not x y))) (i128_alu_bitop (ALUOp.EorNot) $I64 x y))
-
-;;;; Rules for `ishl` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Shift for i8/i16/i32.
-(rule (lower (has_type (fits_in_32 ty) (ishl x y)))
-      (do_shift (ALUOp.Lsl) ty x y))
-
-;; Shift for i64.
-(rule (lower (has_type $I64 (ishl x y)))
-      (do_shift (ALUOp.Lsl) $I64 x y))
-
-;; Shift for i128.
-(rule (lower (has_type $I128 (ishl x y)))
-      (lower_shl128 x (value_regs_get y 0)))
-
-;;     lsl     lo_lshift, src_lo, amt
-;;     lsl     hi_lshift, src_hi, amt
-;;     mvn     inv_amt, amt
-;;     lsr     lo_rshift, src_lo, #1
-;;     lsr     lo_rshift, lo_rshift, inv_amt
-;;     orr     maybe_hi, hi_lshift, lo_rshift
-;;     tst     amt, #0x40
-;;     csel    dst_hi, lo_lshift, maybe_hi, ne
-;;     csel    dst_lo, xzr, lo_lshift, ne
-(decl lower_shl128 (ValueRegs Reg) ValueRegs)
-(rule (lower_shl128 src amt)
-      (let ((src_lo Reg (value_regs_get src 0))
-            (src_hi Reg (value_regs_get src 1))
-            (lo_lshift Reg (lsl $I64 src_lo amt))
-            (hi_lshift Reg (lsl $I64 src_hi amt))
-            (inv_amt Reg (orr_not $I32 (zero_reg) amt))
-            (lo_rshift Reg (lsr $I64 (lsr_imm $I64 src_lo (imm_shift_from_u8 1))
-                                inv_amt))
-          (maybe_hi Reg (orr $I64 hi_lshift lo_rshift))
-        )
-        (with_flags
-         (tst_imm $I64 amt (u64_into_imm_logic $I64 64))
-         (consumes_flags_concat
-          (csel (Cond.Ne) (zero_reg) lo_lshift)
-          (csel (Cond.Ne) lo_lshift maybe_hi)))))
-
-;; Shift for vector types.
-(rule (lower (has_type (vec128 ty) (ishl x y)))
-      (let ((size VectorSize (vector_size ty))
-            (shift Reg (vec_dup y size)))
-        (sshl x shift size)))
-
-;; Helper function to emit a shift operation with the opcode specified and
-;; the output type specified. The `Reg` provided is shifted by the `Value`
-;; given.
-;;
-;; Note that this automatically handles the clif semantics of masking the
-;; shift amount where necessary.
-(decl do_shift (ALUOp Type Reg Value) Reg)
-
-;; 8/16-bit shift base case.
-;;
-;; When shifting for amounts larger than the size of the type, the CLIF shift
-;; instructions implement a "wrapping" behaviour, such that an i8 << 8 is
-;; equivalent to i8 << 0
-;;
-;; On i32 and i64 types this matches what the aarch64 spec does, but on smaller
-;; types (i16, i8) we need to do this manually, so we wrap the shift amount
-;; with an AND instruction
-(rule (do_shift op (fits_in_16 ty) x y)
-      (let ((shift_amt Reg (value_regs_get y 0))
-            (masked_shift_amt Reg (and_imm $I32 shift_amt (shift_mask ty))))
-        (alu_rrr op $I32 x masked_shift_amt)))
-
-(decl shift_mask (Type) ImmLogic)
-(extern constructor shift_mask shift_mask)
-
-;; 32/64-bit shift base cases.
-(rule (do_shift op $I32 x y) (alu_rrr op $I32 x (value_regs_get y 0)))
-(rule (do_shift op $I64 x y) (alu_rrr op $I64 x (value_regs_get y 0)))
-
-;; Special case for shifting by a constant value where the value can fit into an
-;; `ImmShift`.
-;;
-;; Note that this rule explicitly has a higher priority than the others
-;; to ensure it's attempted first, otherwise the type-based filters on the
-;; previous rules seem to take priority over this rule.
-(rule 1 (do_shift op ty x (iconst (imm_shift_from_imm64 <ty shift)))
-      (alu_rr_imm_shift op ty x shift))
-
-;;;; Rules for `ushr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Shift for i8/i16/i32.
-(rule (lower (has_type (fits_in_32 ty) (ushr x y)))
-      (do_shift (ALUOp.Lsr) ty (put_in_reg_zext32 x) y))
-
-;; Shift for i64.
-(rule (lower (has_type $I64 (ushr x y)))
-      (do_shift (ALUOp.Lsr) $I64 (put_in_reg_zext64 x) y))
-
-;; Shift for i128.
-(rule (lower (has_type $I128 (ushr x y)))
-      (lower_ushr128 x (value_regs_get y 0)))
-
-;; Vector shifts.
-(rule (lower (has_type (vec128 ty) (ushr x y)))
-      (let ((size VectorSize (vector_size ty))
-            (shift Reg (vec_dup (sub $I32 (zero_reg) y) size)))
-        (ushl x shift size)))
-
-;;     lsr       lo_rshift, src_lo, amt
-;;     lsr       hi_rshift, src_hi, amt
-;;     mvn       inv_amt, amt
-;;     lsl       hi_lshift, src_hi, #1
-;;     lsl       hi_lshift, hi_lshift, inv_amt
-;;     tst       amt, #0x40
-;;     orr       maybe_lo, lo_rshift, hi_lshift
-;;     csel      dst_hi, xzr, hi_rshift, ne
-;;     csel      dst_lo, hi_rshift, maybe_lo, ne
-(decl lower_ushr128 (ValueRegs Reg) ValueRegs)
-(rule (lower_ushr128 src amt)
-      (let ((src_lo Reg (value_regs_get src 0))
-            (src_hi Reg (value_regs_get src 1))
-            (lo_rshift Reg (lsr $I64 src_lo amt))
-            (hi_rshift Reg (lsr $I64 src_hi amt))
-            
-            (inv_amt Reg (orr_not $I32 (zero_reg) amt))
-            (hi_lshift Reg (lsl $I64 (lsl_imm $I64 src_hi (imm_shift_from_u8 1))
-                                inv_amt))
-          (maybe_lo Reg (orr $I64 lo_rshift hi_lshift))
-        )
-        (with_flags
-         (tst_imm $I64 amt (u64_into_imm_logic $I64 64))
-         (consumes_flags_concat
-          (csel (Cond.Ne) hi_rshift maybe_lo)
-          (csel (Cond.Ne) (zero_reg) hi_rshift)))))
-
-;;;; Rules for `sshr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Shift for i8/i16/i32.
-(rule (lower (has_type (fits_in_32 ty) (sshr x y)))
-      (do_shift (ALUOp.Asr) ty (put_in_reg_sext32 x) y))
-
-;; Shift for i64.
-(rule (lower (has_type $I64 (sshr x y)))
-      (do_shift (ALUOp.Asr) $I64 (put_in_reg_sext64 x) y))
-
-;; Shift for i128.
-(rule (lower (has_type $I128 (sshr x y)))
-      (lower_sshr128 x (value_regs_get y 0)))
-
-;; Vector shifts.
-;;
-;; Note that right shifts are implemented with a negative left shift.
-(rule (lower (has_type (vec128 ty) (sshr x y)))
-      (let ((size VectorSize (vector_size ty))
-            (shift Reg (vec_dup (sub $I32 (zero_reg) y) size)))
-        (sshl x shift size)))
-
-;;     lsr       lo_rshift, src_lo, amt
-;;     asr       hi_rshift, src_hi, amt
-;;     mvn       inv_amt, amt
-;;     lsl       hi_lshift, src_hi, #1
-;;     lsl       hi_lshift, hi_lshift, inv_amt
-;;     asr       hi_sign, src_hi, #63
-;;     orr       maybe_lo, lo_rshift, hi_lshift
-;;     tst       amt, #0x40
-;;     csel      dst_hi, hi_sign, hi_rshift, ne
-;;     csel      dst_lo, hi_rshift, maybe_lo, ne
-(decl lower_sshr128 (ValueRegs Reg) ValueRegs)
-(rule (lower_sshr128 src amt)
-      (let ((src_lo Reg (value_regs_get src 0))
-            (src_hi Reg (value_regs_get src 1))
-            (lo_rshift Reg (lsr $I64 src_lo amt))
-            (hi_rshift Reg (asr $I64 src_hi amt))
-
-            (inv_amt Reg (orr_not $I32 (zero_reg) amt))
-            (hi_lshift Reg (lsl $I64 (lsl_imm $I64 src_hi (imm_shift_from_u8 1))
-                                inv_amt))
-          (hi_sign Reg (asr_imm $I64 src_hi (imm_shift_from_u8 63)))
-          (maybe_lo Reg (orr $I64 lo_rshift hi_lshift))
-        )
-        (with_flags
-         (tst_imm $I64 amt (u64_into_imm_logic $I64 64))
-         (consumes_flags_concat
-          (csel (Cond.Ne) hi_rshift maybe_lo)
-          (csel (Cond.Ne) hi_sign hi_rshift)))))
-
-;;;; Rules for `rotl` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; General 8/16-bit case.
-(rule (lower (has_type (fits_in_16 ty) (rotl x y)))
-      (let ((neg_shift Reg (sub $I32 (zero_reg) y)))
-        (small_rotr ty (put_in_reg_zext32 x) neg_shift)))
-
-;; Specialization for the 8/16-bit case when the rotation amount is an immediate.
-(rule (lower (has_type (fits_in_16 ty) (rotl x (iconst (imm_shift_from_imm64 <ty n)))))
-      (small_rotr_imm ty (put_in_reg_zext32 x) (negate_imm_shift ty n)))
-
-;; aarch64 doesn't have a left-rotate instruction, but a left rotation of K
-;; places is effectively a right rotation of N - K places, if N is the integer's
-;; bit size. We implement left rotations with this trick.
-;;
-;; Note that when negating the shift amount here the upper bits are ignored
-;; by the rotr instruction, meaning that we'll still left-shift by the desired
-;; amount.
-
-;; General 32-bit case.
-(rule (lower (has_type $I32 (rotl x y)))
-      (let ((neg_shift Reg (sub $I32 (zero_reg) y)))
-        (a64_rotr $I32 x neg_shift)))
-
-;; General 64-bit case.
-(rule (lower (has_type $I64 (rotl x y)))
-      (let ((neg_shift Reg (sub $I64 (zero_reg) y)))
-        (a64_rotr $I64 x neg_shift)))
-
-;; Specialization for the 32-bit case when the rotation amount is an immediate.
-(rule (lower (has_type $I32 (rotl x (iconst (imm_shift_from_imm64 <$I32 n)))))
-      (a64_rotr_imm $I32 x (negate_imm_shift $I32 n)))
-
-;; Specialization for the 64-bit case when the rotation amount is an immediate.
-(rule (lower (has_type $I64 (rotl x (iconst (imm_shift_from_imm64 <$I64 n)))))
-      (a64_rotr_imm $I64 x (negate_imm_shift $I64 n)))
-
-(decl negate_imm_shift (Type ImmShift) ImmShift)
-(extern constructor negate_imm_shift negate_imm_shift)
-
-;; General 128-bit case.
-;;
-;; TODO: much better codegen is possible with a constant amount.
-(rule (lower (has_type $I128 (rotl x y)))
-      (let ((val ValueRegs x)
-            (amt Reg (value_regs_get y 0))
-            (neg_amt Reg (sub $I64 (imm $I64 128) amt))
-            (lshift ValueRegs (lower_shl128 val amt))
-            (rshift ValueRegs (lower_ushr128 val neg_amt)))
-        (value_regs
-          (orr $I64 (value_regs_get lshift 0) (value_regs_get rshift 0))
-          (orr $I64 (value_regs_get lshift 1) (value_regs_get rshift 1)))))
-
-;;;; Rules for `rotr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; General 8/16-bit case.
-(rule (lower (has_type (fits_in_16 ty) (rotr x y)))
-      (small_rotr ty (put_in_reg_zext32 x) y))
-
-;; General 32-bit case.
-(rule (lower (has_type $I32 (rotr x y)))
-      (a64_rotr $I32 x y))
-
-;; General 64-bit case.
-(rule (lower (has_type $I64 (rotr x y)))
-      (a64_rotr $I64 x y))
-
-;; Specialization for the 8/16-bit case when the rotation amount is an immediate.
-(rule (lower (has_type (fits_in_16 ty) (rotr x (iconst (imm_shift_from_imm64 <ty n)))))
-      (small_rotr_imm ty (put_in_reg_zext32 x) n))
-
-;; Specialization for the 32-bit case when the rotation amount is an immediate.
-(rule (lower (has_type $I32 (rotr x (iconst (imm_shift_from_imm64 <$I32 n)))))
-      (a64_rotr_imm $I32 x n))
-
-;; Specialization for the 64-bit case when the rotation amount is an immediate.
-(rule (lower (has_type $I64 (rotr x (iconst (imm_shift_from_imm64 <$I64 n)))))
-      (a64_rotr_imm $I64 x n))
-
-;; For a < 32-bit rotate-right, we synthesize this as:
-;;
-;;    rotr rd, val, amt
-;;
-;;       =>
-;;
-;;    and masked_amt, amt, <bitwidth - 1>
-;;    sub tmp_sub, masked_amt, <bitwidth>
-;;    sub neg_amt, zero, tmp_sub  ; neg
-;;    lsr val_rshift, val, masked_amt
-;;    lsl val_lshift, val, neg_amt
-;;    orr rd, val_lshift val_rshift
-(decl small_rotr (Type Reg Reg) Reg)
-(rule (small_rotr ty val amt)
-      (let ((masked_amt Reg (and_imm $I32 amt (rotr_mask ty)))
-            (tmp_sub Reg (sub_imm $I32 masked_amt (u8_into_imm12 (ty_bits ty))))
-            (neg_amt Reg (sub $I32 (zero_reg) tmp_sub))
-            (val_rshift Reg (lsr $I32 val masked_amt))
-            (val_lshift Reg (lsl $I32 val neg_amt)))
-        (orr $I32 val_lshift val_rshift)))
-
-(decl rotr_mask (Type) ImmLogic)
-(extern constructor rotr_mask rotr_mask)
-
-;; For a constant amount, we can instead do:
-;;
-;;    rotr rd, val, #amt
-;;
-;;       =>
-;;
-;;    lsr val_rshift, val, #<amt>
-;;    lsl val_lshift, val, <bitwidth - amt>
-;;    orr rd, val_lshift, val_rshift
-(decl small_rotr_imm (Type Reg ImmShift) Reg)
-(rule (small_rotr_imm ty val amt)
-      (let ((val_rshift Reg (lsr_imm $I32 val amt))
-            (val_lshift Reg (lsl_imm $I32 val (rotr_opposite_amount ty amt))))
-        (orr $I32 val_lshift val_rshift)))
-
-(decl rotr_opposite_amount (Type ImmShift) ImmShift)
-(extern constructor rotr_opposite_amount rotr_opposite_amount)
-
-;; General 128-bit case.
-;;
-;; TODO: much better codegen is possible with a constant amount.
-(rule (lower (has_type $I128 (rotr x y)))
-      (let ((val ValueRegs x)
-            (amt Reg (value_regs_get y 0))
-            (neg_amt Reg (sub $I64 (imm $I64 128) amt))
-            (rshift ValueRegs (lower_ushr128 val amt))
-            (lshift ValueRegs (lower_shl128 val neg_amt))
-            (hi Reg (orr $I64 (value_regs_get rshift 1) (value_regs_get lshift 1)))
-            (lo Reg (orr $I64 (value_regs_get rshift 0) (value_regs_get lshift 0))))
-        (value_regs lo hi)))
-
-;;;; Rules for `bitrev` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Reversing an 8-bit value with a 32-bit bitrev instruction will place
-;; the reversed result in the highest 8 bits, so we need to shift them down into
-;; place.
-(rule (lower (has_type $I8 (bitrev x)))
-      (lsr_imm $I32 (rbit $I32 x) (imm_shift_from_u8 24)))
-
-;; Reversing an 16-bit value with a 32-bit bitrev instruction will place
-;; the reversed result in the highest 16 bits, so we need to shift them down into
-;; place.
-(rule (lower (has_type $I16 (bitrev x)))
-      (lsr_imm $I32 (rbit $I32 x) (imm_shift_from_u8 16)))
-
-(rule (lower (has_type $I128 (bitrev x)))
-      (let ((val ValueRegs x)
-            (lo_rev Reg (rbit $I64 (value_regs_get val 0)))
-            (hi_rev Reg (rbit $I64 (value_regs_get val 1))))
-        (value_regs hi_rev lo_rev)))
-
-(rule (lower (has_type ty (bitrev x)))
-      (rbit ty x))
-
-
-;;;; Rules for `clz` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type $I8 (clz x)))
-      (sub_imm $I32 (a64_clz $I32 (put_in_reg_zext32 x)) (u8_into_imm12 24)))
-
-(rule (lower (has_type $I16 (clz x)))
-      (sub_imm $I32 (a64_clz $I32 (put_in_reg_zext32 x)) (u8_into_imm12 16)))
-
-(rule (lower (has_type $I128 (clz x)))
-      (lower_clz128 x))
-
-(rule (lower (has_type ty (clz x)))
-      (a64_clz ty x))
-
-;; clz hi_clz, hi
-;; clz lo_clz, lo
-;; lsr tmp, hi_clz, #6
-;; madd dst_lo, lo_clz, tmp, hi_clz
-;; mov  dst_hi, 0
-(decl lower_clz128 (ValueRegs) ValueRegs)
-(rule (lower_clz128 val)
-      (let ((hi_clz Reg (a64_clz $I64 (value_regs_get val 1)))
-            (lo_clz Reg (a64_clz $I64 (value_regs_get val 0)))
-            (tmp Reg (lsr_imm $I64 hi_clz (imm_shift_from_u8 6))))
-        (value_regs (madd64 lo_clz tmp hi_clz) (imm $I64 0))))
-
-;;;; Rules for `ctz` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Note that all `ctz` instructions are implemented by reversing the bits and
-;; then using a `clz` instruction since the tail zeros are the same as the
-;; leading zeros of the reversed value.
-
-(rule (lower (has_type $I8 (ctz x)))
-      (a64_clz $I32 (orr_imm $I32 (rbit $I32 x) (u64_into_imm_logic $I32 0x800000))))
-
-(rule (lower (has_type $I16 (ctz x)))
-      (a64_clz $I32 (orr_imm $I32 (rbit $I32 x) (u64_into_imm_logic $I32 0x8000))))
-
-(rule (lower (has_type $I128 (ctz x)))
-      (let ((val ValueRegs x)
-            (lo Reg (rbit $I64 (value_regs_get val 0)))
-            (hi Reg (rbit $I64 (value_regs_get val 1))))
-        (lower_clz128 (value_regs hi lo))))
-
-(rule (lower (has_type ty (ctz x)))
-      (a64_clz ty (rbit ty x)))
-
-;;;; Rules for `cls` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type $I8 (cls x)))
-      (sub_imm $I32 (a64_cls $I32 (put_in_reg_zext32 x)) (u8_into_imm12 24)))
-
-(rule (lower (has_type $I16 (cls x)))
-      (sub_imm $I32 (a64_cls $I32 (put_in_reg_zext32 x)) (u8_into_imm12 16)))
-
-;; cls lo_cls, lo
-;; cls hi_cls, hi
-;; eon sign_eq_eor, hi, lo
-;; lsr sign_eq, sign_eq_eor, #63
-;; madd lo_sign_bits, out_lo, sign_eq, sign_eq
-;; cmp hi_cls, #63
-;; csel maybe_lo, lo_sign_bits, xzr, eq
-;; add  out_lo, maybe_lo, hi_cls
-;; mov  out_hi, 0
-(rule (lower (has_type $I128 (cls x)))
-      (let ((val ValueRegs x)
-            (lo Reg (value_regs_get val 0))
-            (hi Reg (value_regs_get val 1))
-            (lo_cls Reg (a64_cls $I64 lo))
-            (hi_cls Reg (a64_cls $I64 hi))
-            (sign_eq_eon Reg (eon $I64 hi lo))
-            (sign_eq Reg (lsr_imm $I64 sign_eq_eon (imm_shift_from_u8 63)))
-            (lo_sign_bits Reg (madd64 lo_cls sign_eq sign_eq))
-            (maybe_lo Reg (with_flags_reg
-                           (cmp64_imm hi_cls (u8_into_imm12 63))
-                           (csel (Cond.Eq) lo_sign_bits (zero_reg)))))
-        (value_regs (add $I64 maybe_lo hi_cls) (imm $I64 0))))
-
-(rule (lower (has_type ty (cls x)))
-      (a64_cls ty x))
-
-;;;; Rules for `popcnt` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; The implementation of `popcnt` for scalar types is done by moving the value
-;; into a vector register, using the `cnt` instruction, and then collating the
-;; result back into a normal register.
-;;
-;; The general sequence emitted here is
-;;
-;;     fmov tmp, in_lo
-;;     if ty == i128:
-;;         mov tmp.d[1], in_hi
-;;
-;;     cnt tmp.16b, tmp.16b / cnt tmp.8b, tmp.8b
-;;     addv tmp, tmp.16b / addv tmp, tmp.8b / addp tmp.8b, tmp.8b, tmp.8b / (no instruction for 8-bit inputs)
-;;
-;;     umov out_lo, tmp.b[0]
-;;     if ty == i128:
-;;         mov out_hi, 0
-
-(rule (lower (has_type $I8 (popcnt x)))
-      (let ((tmp Reg (mov_to_fpu x (ScalarSize.Size32)))
-            (nbits Reg (vec_cnt tmp (VectorSize.Size8x8))))
-        (mov_from_vec nbits 0 (VectorSize.Size8x16))))
-
-;; Note that this uses `addp` instead of `addv` as it's usually cheaper.
-(rule (lower (has_type $I16 (popcnt x)))
-      (let ((tmp Reg (mov_to_fpu x (ScalarSize.Size32)))
-            (nbits Reg (vec_cnt tmp (VectorSize.Size8x8)))
-            (added Reg (addp nbits nbits (VectorSize.Size8x8))))
-        (mov_from_vec added 0 (VectorSize.Size8x16))))
-
-(rule (lower (has_type $I32 (popcnt x)))
-      (let ((tmp Reg (mov_to_fpu x (ScalarSize.Size32)))
-            (nbits Reg (vec_cnt tmp (VectorSize.Size8x8)))
-            (added Reg (addv nbits (VectorSize.Size8x8))))
-        (mov_from_vec added 0 (VectorSize.Size8x16))))
-
-(rule (lower (has_type $I64 (popcnt x)))
-      (let ((tmp Reg (mov_to_fpu x (ScalarSize.Size64)))
-            (nbits Reg (vec_cnt tmp (VectorSize.Size8x8)))
-            (added Reg (addv nbits (VectorSize.Size8x8))))
-        (mov_from_vec added 0 (VectorSize.Size8x16))))
-
-(rule (lower (has_type $I128 (popcnt x)))
-      (let ((val ValueRegs x)
-            (tmp_half Reg (mov_to_fpu (value_regs_get val 0) (ScalarSize.Size64)))
-            (tmp Reg (mov_to_vec tmp_half (value_regs_get val 1) 1 (VectorSize.Size64x2)))
-            (nbits Reg (vec_cnt tmp (VectorSize.Size8x16)))
-            (added Reg (addv nbits (VectorSize.Size8x16))))
-        (value_regs (mov_from_vec added 0 (VectorSize.Size8x16)) (imm $I64 0))))
-
-(rule (lower (has_type $I8X16 (popcnt x)))
-      (vec_cnt x (VectorSize.Size8x16)))
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/lower.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/lower.rs
deleted file mode 100644
index bb4c8ee02..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/lower.rs
+++ /dev/null
@@ -1,1581 +0,0 @@
-//! Lowering rules for AArch64.
-//!
-//! TODO: opportunities for better code generation:
-//!
-//! - Smarter use of addressing modes. Recognize a+SCALE*b patterns. Recognize
-//!   pre/post-index opportunities.
-//!
-//! - Floating-point immediates (FIMM instruction).
-
-use crate::ir::condcodes::{FloatCC, IntCC};
-use crate::ir::types::*;
-use crate::ir::Inst as IRInst;
-use crate::ir::{Opcode, Type, Value};
-use crate::machinst::lower::*;
-use crate::machinst::*;
-use crate::{CodegenError, CodegenResult};
-
-use crate::isa::aarch64::inst::*;
-use crate::isa::aarch64::AArch64Backend;
-
-use super::lower_inst;
-
-use crate::data_value::DataValue;
-use regalloc::{Reg, Writable};
-use smallvec::SmallVec;
-use std::cmp;
-
-pub mod isle;
-
-//============================================================================
-// Result enum types.
-//
-// Lowering of a given value results in one of these enums, depending on the
-// modes in which we can accept the value.
-
-/// A lowering result: register, register-shift.  An SSA value can always be
-/// lowered into one of these options; the register form is the fallback.
-#[derive(Clone, Debug)]
-enum ResultRS {
-    Reg(Reg),
-    RegShift(Reg, ShiftOpAndAmt),
-}
-
-/// A lowering result: register, register-shift, register-extend.  An SSA value can always be
-/// lowered into one of these options; the register form is the fallback.
-#[derive(Clone, Debug)]
-enum ResultRSE {
-    Reg(Reg),
-    RegShift(Reg, ShiftOpAndAmt),
-    RegExtend(Reg, ExtendOp),
-}
-
-impl ResultRSE {
-    fn from_rs(rs: ResultRS) -> ResultRSE {
-        match rs {
-            ResultRS::Reg(r) => ResultRSE::Reg(r),
-            ResultRS::RegShift(r, s) => ResultRSE::RegShift(r, s),
-        }
-    }
-}
-
-/// A lowering result: register, register-shift, register-extend, or 12-bit immediate form.
-/// An SSA value can always be lowered into one of these options; the register form is the
-/// fallback.
-#[derive(Clone, Debug)]
-pub(crate) enum ResultRSEImm12 {
-    Reg(Reg),
-    RegShift(Reg, ShiftOpAndAmt),
-    RegExtend(Reg, ExtendOp),
-    Imm12(Imm12),
-}
-
-impl ResultRSEImm12 {
-    fn from_rse(rse: ResultRSE) -> ResultRSEImm12 {
-        match rse {
-            ResultRSE::Reg(r) => ResultRSEImm12::Reg(r),
-            ResultRSE::RegShift(r, s) => ResultRSEImm12::RegShift(r, s),
-            ResultRSE::RegExtend(r, e) => ResultRSEImm12::RegExtend(r, e),
-        }
-    }
-}
-
-//============================================================================
-// Lowering: convert instruction inputs to forms that we can use.
-
-/// Lower an instruction input to a 64-bit constant, if possible.
-pub(crate) fn input_to_const<C: LowerCtx<I = Inst>>(ctx: &mut C, input: InsnInput) -> Option<u64> {
-    let input = ctx.get_input_as_source_or_const(input.insn, input.input);
-    input.constant
-}
-
-/// Lower an instruction input to a constant register-shift amount, if possible.
-pub(crate) fn input_to_shiftimm<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    input: InsnInput,
-) -> Option<ShiftOpShiftImm> {
-    input_to_const(ctx, input).and_then(ShiftOpShiftImm::maybe_from_shift)
-}
-
-pub(crate) fn const_param_to_u128<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    inst: IRInst,
-) -> Option<u128> {
-    match ctx.get_immediate(inst) {
-        Some(DataValue::V128(bytes)) => Some(u128::from_le_bytes(bytes)),
-        _ => None,
-    }
-}
-
-/// How to handle narrow values loaded into registers; see note on `narrow_mode`
-/// parameter to `put_input_in_*` below.
-#[derive(Clone, Copy, Debug, PartialEq, Eq)]
-pub(crate) enum NarrowValueMode {
-    None,
-    /// Zero-extend to 32 bits if original is < 32 bits.
-    ZeroExtend32,
-    /// Sign-extend to 32 bits if original is < 32 bits.
-    SignExtend32,
-    /// Zero-extend to 64 bits if original is < 64 bits.
-    ZeroExtend64,
-    /// Sign-extend to 64 bits if original is < 64 bits.
-    SignExtend64,
-}
-
-impl NarrowValueMode {
-    fn is_32bit(&self) -> bool {
-        match self {
-            NarrowValueMode::None => false,
-            NarrowValueMode::ZeroExtend32 | NarrowValueMode::SignExtend32 => true,
-            NarrowValueMode::ZeroExtend64 | NarrowValueMode::SignExtend64 => false,
-        }
-    }
-
-    fn is_signed(&self) -> bool {
-        match self {
-            NarrowValueMode::SignExtend32 | NarrowValueMode::SignExtend64 => true,
-            NarrowValueMode::ZeroExtend32 | NarrowValueMode::ZeroExtend64 => false,
-            NarrowValueMode::None => false,
-        }
-    }
-}
-
-/// Emits instruction(s) to generate the given constant value into newly-allocated
-/// temporary registers, returning these registers.
-fn generate_constant<C: LowerCtx<I = Inst>>(ctx: &mut C, ty: Type, c: u128) -> ValueRegs<Reg> {
-    let from_bits = ty_bits(ty);
-    let masked = if from_bits < 128 {
-        c & ((1u128 << from_bits) - 1)
-    } else {
-        c
-    };
-
-    let cst_copy = ctx.alloc_tmp(ty);
-    for inst in Inst::gen_constant(cst_copy, masked, ty, |ty| {
-        ctx.alloc_tmp(ty).only_reg().unwrap()
-    })
-    .into_iter()
-    {
-        ctx.emit(inst);
-    }
-    non_writable_value_regs(cst_copy)
-}
-
-/// Extends a register according to `narrow_mode`.
-/// If extended, the value is always extended to 64 bits, for simplicity.
-fn extend_reg<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    ty: Type,
-    in_reg: Reg,
-    is_const: bool,
-    narrow_mode: NarrowValueMode,
-) -> Reg {
-    let from_bits = ty_bits(ty) as u8;
-    match (narrow_mode, from_bits) {
-        (NarrowValueMode::None, _) => in_reg,
-        (NarrowValueMode::ZeroExtend32, n) if n < 32 => {
-            let tmp = ctx.alloc_tmp(I32).only_reg().unwrap();
-            ctx.emit(Inst::Extend {
-                rd: tmp,
-                rn: in_reg,
-                signed: false,
-                from_bits,
-                to_bits: 32,
-            });
-            tmp.to_reg()
-        }
-        (NarrowValueMode::SignExtend32, n) if n < 32 => {
-            let tmp = ctx.alloc_tmp(I32).only_reg().unwrap();
-            ctx.emit(Inst::Extend {
-                rd: tmp,
-                rn: in_reg,
-                signed: true,
-                from_bits,
-                to_bits: 32,
-            });
-            tmp.to_reg()
-        }
-        (NarrowValueMode::ZeroExtend32, 32) | (NarrowValueMode::SignExtend32, 32) => in_reg,
-
-        (NarrowValueMode::ZeroExtend64, n) if n < 64 => {
-            if is_const {
-                // Constants are zero-extended to full 64-bit width on load already.
-                in_reg
-            } else {
-                let tmp = ctx.alloc_tmp(I32).only_reg().unwrap();
-                ctx.emit(Inst::Extend {
-                    rd: tmp,
-                    rn: in_reg,
-                    signed: false,
-                    from_bits,
-                    to_bits: 64,
-                });
-                tmp.to_reg()
-            }
-        }
-        (NarrowValueMode::SignExtend64, n) if n < 64 => {
-            let tmp = ctx.alloc_tmp(I32).only_reg().unwrap();
-            ctx.emit(Inst::Extend {
-                rd: tmp,
-                rn: in_reg,
-                signed: true,
-                from_bits,
-                to_bits: 64,
-            });
-            tmp.to_reg()
-        }
-        (_, 64) => in_reg,
-        (_, 128) => in_reg,
-
-        _ => panic!(
-            "Unsupported input width: input ty {} bits {} mode {:?}",
-            ty, from_bits, narrow_mode
-        ),
-    }
-}
-
-/// Lowers an instruction input to multiple regs
-fn lower_value_to_regs<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    value: Value,
-) -> (ValueRegs<Reg>, Type, bool) {
-    log::trace!("lower_value_to_regs: value {:?}", value);
-    let ty = ctx.value_ty(value);
-    let inputs = ctx.get_value_as_source_or_const(value);
-    let is_const = inputs.constant.is_some();
-
-    let in_regs = if let Some(c) = inputs.constant {
-        // Generate constants fresh at each use to minimize long-range register pressure.
-        generate_constant(ctx, ty, c as u128)
-    } else {
-        ctx.put_value_in_regs(value)
-    };
-
-    (in_regs, ty, is_const)
-}
-
-/// Lower an instruction input to a register
-///
-/// The given register will be extended appropriately, according to
-/// `narrow_mode` and the input's type. If extended, the value is
-/// always extended to 64 bits, for simplicity.
-pub(crate) fn put_input_in_reg<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    input: InsnInput,
-    narrow_mode: NarrowValueMode,
-) -> Reg {
-    let value = ctx.input_as_value(input.insn, input.input);
-    put_value_in_reg(ctx, value, narrow_mode)
-}
-
-/// Like above, only for values
-fn put_value_in_reg<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    value: Value,
-    narrow_mode: NarrowValueMode,
-) -> Reg {
-    let (in_regs, ty, is_const) = lower_value_to_regs(ctx, value);
-    let reg = in_regs
-        .only_reg()
-        .expect("Multi-register value not expected");
-
-    extend_reg(ctx, ty, reg, is_const, narrow_mode)
-}
-
-/// Lower an instruction input to multiple regs
-pub(crate) fn put_input_in_regs<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    input: InsnInput,
-) -> ValueRegs<Reg> {
-    let value = ctx.input_as_value(input.insn, input.input);
-    let (in_regs, _, _) = lower_value_to_regs(ctx, value);
-    in_regs
-}
-
-/// Lower an instruction input to a reg or reg/shift, or reg/extend operand.
-///
-/// The `narrow_mode` flag indicates whether the consumer of this value needs
-/// the high bits clear. For many operations, such as an add/sub/mul or any
-/// bitwise logical operation, the low-bit results depend only on the low-bit
-/// inputs, so e.g. we can do an 8 bit add on 32 bit registers where the 8-bit
-/// value is stored in the low 8 bits of the register and the high 24 bits are
-/// undefined. If the op truly needs the high N bits clear (such as for a
-/// divide or a right-shift or a compare-to-zero), `narrow_mode` should be
-/// set to `ZeroExtend` or `SignExtend` as appropriate, and the resulting
-/// register will be provided the extended value.
-fn put_input_in_rs<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    input: InsnInput,
-    narrow_mode: NarrowValueMode,
-) -> ResultRS {
-    let inputs = ctx.get_input_as_source_or_const(input.insn, input.input);
-    if let Some((insn, 0)) = inputs.inst {
-        let op = ctx.data(insn).opcode();
-
-        if op == Opcode::Ishl {
-            let shiftee = InsnInput { insn, input: 0 };
-            let shift_amt = InsnInput { insn, input: 1 };
-
-            // Can we get the shift amount as an immediate?
-            if let Some(shiftimm) = input_to_shiftimm(ctx, shift_amt) {
-                let shiftee_bits = ty_bits(ctx.input_ty(insn, 0));
-                if shiftee_bits <= std::u8::MAX as usize {
-                    let shiftimm = shiftimm.mask(shiftee_bits as u8);
-                    let reg = put_input_in_reg(ctx, shiftee, narrow_mode);
-                    return ResultRS::RegShift(reg, ShiftOpAndAmt::new(ShiftOp::LSL, shiftimm));
-                }
-            }
-        }
-    }
-
-    ResultRS::Reg(put_input_in_reg(ctx, input, narrow_mode))
-}
-
-/// Lower an instruction input to a reg or reg/shift, or reg/extend operand.
-/// This does not actually codegen the source instruction; it just uses the
-/// vreg into which the source instruction will generate its value.
-///
-/// See note on `put_input_in_rs` for a description of `narrow_mode`.
-fn put_input_in_rse<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    input: InsnInput,
-    narrow_mode: NarrowValueMode,
-) -> ResultRSE {
-    let value = ctx.input_as_value(input.insn, input.input);
-    if let Some((val, extendop)) = get_as_extended_value(ctx, value, narrow_mode) {
-        let reg = put_value_in_reg(ctx, val, NarrowValueMode::None);
-        return ResultRSE::RegExtend(reg, extendop);
-    }
-
-    ResultRSE::from_rs(put_input_in_rs(ctx, input, narrow_mode))
-}
-
-fn get_as_extended_value<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    val: Value,
-    narrow_mode: NarrowValueMode,
-) -> Option<(Value, ExtendOp)> {
-    let inputs = ctx.get_value_as_source_or_const(val);
-    let (insn, n) = inputs.inst?;
-    if n != 0 {
-        return None;
-    }
-    let op = ctx.data(insn).opcode();
-    let out_ty = ctx.output_ty(insn, 0);
-    let out_bits = ty_bits(out_ty);
-
-    // Is this a zero-extend or sign-extend and can we handle that with a register-mode operator?
-    if op == Opcode::Uextend || op == Opcode::Sextend {
-        let sign_extend = op == Opcode::Sextend;
-        let inner_ty = ctx.input_ty(insn, 0);
-        let inner_bits = ty_bits(inner_ty);
-        assert!(inner_bits < out_bits);
-        if match (sign_extend, narrow_mode) {
-            // A single zero-extend or sign-extend is equal to itself.
-            (_, NarrowValueMode::None) => true,
-            // Two zero-extends or sign-extends in a row is equal to a single zero-extend or sign-extend.
-            (false, NarrowValueMode::ZeroExtend32) | (false, NarrowValueMode::ZeroExtend64) => true,
-            (true, NarrowValueMode::SignExtend32) | (true, NarrowValueMode::SignExtend64) => true,
-            // A zero-extend and a sign-extend in a row is not equal to a single zero-extend or sign-extend
-            (false, NarrowValueMode::SignExtend32) | (false, NarrowValueMode::SignExtend64) => {
-                false
-            }
-            (true, NarrowValueMode::ZeroExtend32) | (true, NarrowValueMode::ZeroExtend64) => false,
-        } {
-            let extendop = match (sign_extend, inner_bits) {
-                (true, 8) => ExtendOp::SXTB,
-                (false, 8) => ExtendOp::UXTB,
-                (true, 16) => ExtendOp::SXTH,
-                (false, 16) => ExtendOp::UXTH,
-                (true, 32) => ExtendOp::SXTW,
-                (false, 32) => ExtendOp::UXTW,
-                _ => unreachable!(),
-            };
-            return Some((ctx.input_as_value(insn, 0), extendop));
-        }
-    }
-
-    // If `out_ty` is smaller than 32 bits and we need to zero- or sign-extend,
-    // then get the result into a register and return an Extend-mode operand on
-    // that register.
-    if narrow_mode != NarrowValueMode::None
-        && ((narrow_mode.is_32bit() && out_bits < 32) || (!narrow_mode.is_32bit() && out_bits < 64))
-    {
-        let extendop = match (narrow_mode, out_bits) {
-            (NarrowValueMode::SignExtend32, 1) | (NarrowValueMode::SignExtend64, 1) => {
-                ExtendOp::SXTB
-            }
-            (NarrowValueMode::ZeroExtend32, 1) | (NarrowValueMode::ZeroExtend64, 1) => {
-                ExtendOp::UXTB
-            }
-            (NarrowValueMode::SignExtend32, 8) | (NarrowValueMode::SignExtend64, 8) => {
-                ExtendOp::SXTB
-            }
-            (NarrowValueMode::ZeroExtend32, 8) | (NarrowValueMode::ZeroExtend64, 8) => {
-                ExtendOp::UXTB
-            }
-            (NarrowValueMode::SignExtend32, 16) | (NarrowValueMode::SignExtend64, 16) => {
-                ExtendOp::SXTH
-            }
-            (NarrowValueMode::ZeroExtend32, 16) | (NarrowValueMode::ZeroExtend64, 16) => {
-                ExtendOp::UXTH
-            }
-            (NarrowValueMode::SignExtend64, 32) => ExtendOp::SXTW,
-            (NarrowValueMode::ZeroExtend64, 32) => ExtendOp::UXTW,
-            _ => unreachable!(),
-        };
-        return Some((val, extendop));
-    }
-    None
-}
-
-pub(crate) fn put_input_in_rse_imm12<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    input: InsnInput,
-    narrow_mode: NarrowValueMode,
-) -> ResultRSEImm12 {
-    if let Some(imm_value) = input_to_const(ctx, input) {
-        if let Some(i) = Imm12::maybe_from_u64(imm_value) {
-            let out_ty_bits = ty_bits(ctx.input_ty(input.insn, input.input));
-            let is_negative = (i.bits as u64) & (1 << (cmp::max(out_ty_bits, 1) - 1)) != 0;
-
-            // This condition can happen if we matched a value that overflows the output type of
-            // its `iconst` when viewed as a signed value (i.e. iconst.i8 200).
-            // When that happens we need to lower as a negative value, which we cannot do here.
-            if !(narrow_mode.is_signed() && is_negative) {
-                return ResultRSEImm12::Imm12(i);
-            }
-        }
-    }
-
-    ResultRSEImm12::from_rse(put_input_in_rse(ctx, input, narrow_mode))
-}
-
-//============================================================================
-// ALU instruction constructors.
-
-pub(crate) fn alu_inst_imm12(
-    op: ALUOp,
-    ty: Type,
-    rd: Writable<Reg>,
-    rn: Reg,
-    rm: ResultRSEImm12,
-) -> Inst {
-    let size = OperandSize::from_ty(ty);
-    match rm {
-        ResultRSEImm12::Imm12(imm12) => Inst::AluRRImm12 {
-            alu_op: op,
-            size,
-            rd,
-            rn,
-            imm12,
-        },
-        ResultRSEImm12::Reg(rm) => Inst::AluRRR {
-            alu_op: op,
-            size,
-            rd,
-            rn,
-            rm,
-        },
-        ResultRSEImm12::RegShift(rm, shiftop) => Inst::AluRRRShift {
-            alu_op: op,
-            size,
-            rd,
-            rn,
-            rm,
-            shiftop,
-        },
-        ResultRSEImm12::RegExtend(rm, extendop) => Inst::AluRRRExtend {
-            alu_op: op,
-            size,
-            rd,
-            rn,
-            rm,
-            extendop,
-        },
-    }
-}
-
-//============================================================================
-// Lowering: addressing mode support. Takes instruction directly, rather
-// than an `InsnInput`, to do more introspection.
-
-/// 32-bit addends that make up an address: an input, and an extension mode on that
-/// input.
-type AddressAddend32List = SmallVec<[(Reg, ExtendOp); 4]>;
-/// 64-bit addends that make up an address: just an input.
-type AddressAddend64List = SmallVec<[Reg; 4]>;
-
-/// Collect all addends that feed into an address computation, with extend-modes
-/// on each.  Note that a load/store may have multiple address components (and
-/// the CLIF semantics are that these components are added to form the final
-/// address), but sometimes the CLIF that we receive still has arguments that
-/// refer to `iadd` instructions. We also want to handle uextend/sextend below
-/// the add(s).
-///
-/// We match any 64-bit add (and descend into its inputs), and we match any
-/// 32-to-64-bit sign or zero extension. The returned addend-list will use
-/// NarrowValueMode values to indicate how to extend each input:
-///
-/// - NarrowValueMode::None: the associated input is 64 bits wide; no extend.
-/// - NarrowValueMode::SignExtend64: the associated input is 32 bits wide;
-///                                  do a sign-extension.
-/// - NarrowValueMode::ZeroExtend64: the associated input is 32 bits wide;
-///                                  do a zero-extension.
-///
-/// We do not descend further into the inputs of extensions (unless it is a constant),
-/// because supporting (e.g.) a 32-bit add that is later extended would require
-/// additional masking of high-order bits, which is too complex. So, in essence, we
-/// descend any number of adds from the roots, collecting all 64-bit address addends;
-/// then possibly support extensions at these leaves.
-fn collect_address_addends<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    roots: &[InsnInput],
-) -> (AddressAddend64List, AddressAddend32List, i64) {
-    let mut result32: AddressAddend32List = SmallVec::new();
-    let mut result64: AddressAddend64List = SmallVec::new();
-    let mut offset: i64 = 0;
-
-    let mut workqueue: SmallVec<[InsnInput; 4]> = roots.iter().cloned().collect();
-
-    while let Some(input) = workqueue.pop() {
-        debug_assert!(ty_bits(ctx.input_ty(input.insn, input.input)) == 64);
-        if let Some((op, insn)) = maybe_input_insn_multi(
-            ctx,
-            input,
-            &[
-                Opcode::Uextend,
-                Opcode::Sextend,
-                Opcode::Iadd,
-                Opcode::Iconst,
-            ],
-        ) {
-            match op {
-                Opcode::Uextend | Opcode::Sextend if ty_bits(ctx.input_ty(insn, 0)) == 32 => {
-                    let extendop = if op == Opcode::Uextend {
-                        ExtendOp::UXTW
-                    } else {
-                        ExtendOp::SXTW
-                    };
-                    let extendee_input = InsnInput { insn, input: 0 };
-                    // If the input is a zero-extension of a constant, add the value to the known
-                    // offset.
-                    // Only do this for zero-extension, as generating a sign-extended
-                    // constant may be more instructions than using the 'SXTW' addressing mode.
-                    if let (Some(insn), ExtendOp::UXTW) = (
-                        maybe_input_insn(ctx, extendee_input, Opcode::Iconst),
-                        extendop,
-                    ) {
-                        let value = (ctx.get_constant(insn).unwrap() & 0xFFFF_FFFF_u64) as i64;
-                        offset += value;
-                    } else {
-                        let reg = put_input_in_reg(ctx, extendee_input, NarrowValueMode::None);
-                        result32.push((reg, extendop));
-                    }
-                }
-                Opcode::Uextend | Opcode::Sextend => {
-                    let reg = put_input_in_reg(ctx, input, NarrowValueMode::None);
-                    result64.push(reg);
-                }
-                Opcode::Iadd => {
-                    for input in 0..ctx.num_inputs(insn) {
-                        let addend = InsnInput { insn, input };
-                        workqueue.push(addend);
-                    }
-                }
-                Opcode::Iconst => {
-                    let value: i64 = ctx.get_constant(insn).unwrap() as i64;
-                    offset += value;
-                }
-                _ => panic!("Unexpected opcode from maybe_input_insn_multi"),
-            }
-        } else {
-            let reg = put_input_in_reg(ctx, input, NarrowValueMode::ZeroExtend64);
-            result64.push(reg);
-        }
-    }
-
-    (result64, result32, offset)
-}
-
-/// Lower the address of a pair load or store.
-pub(crate) fn lower_pair_address<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    roots: &[InsnInput],
-    offset: i32,
-) -> PairAMode {
-    // Collect addends through an arbitrary tree of 32-to-64-bit sign/zero
-    // extends and addition ops. We update these as we consume address
-    // components, so they represent the remaining addends not yet handled.
-    let (mut addends64, mut addends32, args_offset) = collect_address_addends(ctx, roots);
-    let offset = args_offset + (offset as i64);
-
-    log::trace!(
-        "lower_pair_address: addends64 {:?}, addends32 {:?}, offset {}",
-        addends64,
-        addends32,
-        offset
-    );
-
-    // Pairs basically only have reg + imm formats so we only have to worry about those
-
-    let base_reg = if let Some(reg64) = addends64.pop() {
-        reg64
-    } else if let Some((reg32, extendop)) = addends32.pop() {
-        let tmp = ctx.alloc_tmp(I64).only_reg().unwrap();
-        let signed = match extendop {
-            ExtendOp::SXTW => true,
-            ExtendOp::UXTW => false,
-            _ => unreachable!(),
-        };
-        ctx.emit(Inst::Extend {
-            rd: tmp,
-            rn: reg32,
-            signed,
-            from_bits: 32,
-            to_bits: 64,
-        });
-        tmp.to_reg()
-    } else {
-        zero_reg()
-    };
-
-    let addr = ctx.alloc_tmp(I64).only_reg().unwrap();
-    ctx.emit(Inst::gen_move(addr, base_reg, I64));
-
-    // We have the base register, if we have any others, we need to add them
-    lower_add_addends(ctx, addr, addends64, addends32);
-
-    // Figure out what offset we should emit
-    let imm7 = SImm7Scaled::maybe_from_i64(offset, I64).unwrap_or_else(|| {
-        lower_add_immediate(ctx, addr, addr.to_reg(), offset);
-        SImm7Scaled::maybe_from_i64(0, I64).unwrap()
-    });
-
-    PairAMode::SignedOffset(addr.to_reg(), imm7)
-}
-
-/// Lower the address of a load or store.
-pub(crate) fn lower_address<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    elem_ty: Type,
-    roots: &[InsnInput],
-    offset: i32,
-) -> AMode {
-    // TODO: support base_reg + scale * index_reg. For this, we would need to pattern-match shl or
-    // mul instructions (Load/StoreComplex don't include scale factors).
-
-    // Collect addends through an arbitrary tree of 32-to-64-bit sign/zero
-    // extends and addition ops. We update these as we consume address
-    // components, so they represent the remaining addends not yet handled.
-    let (mut addends64, mut addends32, args_offset) = collect_address_addends(ctx, roots);
-    let mut offset = args_offset + (offset as i64);
-
-    log::trace!(
-        "lower_address: addends64 {:?}, addends32 {:?}, offset {}",
-        addends64,
-        addends32,
-        offset
-    );
-
-    // First, decide what the `AMode` will be. Take one extendee and one 64-bit
-    // reg, or two 64-bit regs, or a 64-bit reg and a 32-bit reg with extension,
-    // or some other combination as appropriate.
-    let memarg = if addends64.len() > 0 {
-        if addends32.len() > 0 {
-            let (reg32, extendop) = addends32.pop().unwrap();
-            let reg64 = addends64.pop().unwrap();
-            AMode::RegExtended(reg64, reg32, extendop)
-        } else if offset > 0 && offset < 0x1000 {
-            let reg64 = addends64.pop().unwrap();
-            let off = offset;
-            offset = 0;
-            AMode::RegOffset(reg64, off, elem_ty)
-        } else if addends64.len() >= 2 {
-            let reg1 = addends64.pop().unwrap();
-            let reg2 = addends64.pop().unwrap();
-            AMode::RegReg(reg1, reg2)
-        } else {
-            let reg1 = addends64.pop().unwrap();
-            AMode::reg(reg1)
-        }
-    } else
-    /* addends64.len() == 0 */
-    {
-        if addends32.len() > 0 {
-            let tmp = ctx.alloc_tmp(I64).only_reg().unwrap();
-            let (reg1, extendop) = addends32.pop().unwrap();
-            let signed = match extendop {
-                ExtendOp::SXTW => true,
-                ExtendOp::UXTW => false,
-                _ => unreachable!(),
-            };
-            ctx.emit(Inst::Extend {
-                rd: tmp,
-                rn: reg1,
-                signed,
-                from_bits: 32,
-                to_bits: 64,
-            });
-            if let Some((reg2, extendop)) = addends32.pop() {
-                AMode::RegExtended(tmp.to_reg(), reg2, extendop)
-            } else {
-                AMode::reg(tmp.to_reg())
-            }
-        } else
-        /* addends32.len() == 0 */
-        {
-            let off_reg = ctx.alloc_tmp(I64).only_reg().unwrap();
-            lower_constant_u64(ctx, off_reg, offset as u64);
-            offset = 0;
-            AMode::reg(off_reg.to_reg())
-        }
-    };
-
-    // At this point, if we have any remaining components, we need to allocate a
-    // temp, replace one of the registers in the AMode with the temp, and emit
-    // instructions to add together the remaining components. Return immediately
-    // if this is *not* the case.
-    if offset == 0 && addends32.len() == 0 && addends64.len() == 0 {
-        return memarg;
-    }
-
-    // Allocate the temp and shoehorn it into the AMode.
-    let addr = ctx.alloc_tmp(I64).only_reg().unwrap();
-    let (reg, memarg) = match memarg {
-        AMode::RegExtended(r1, r2, extendop) => {
-            (r1, AMode::RegExtended(addr.to_reg(), r2, extendop))
-        }
-        AMode::RegOffset(r, off, ty) => (r, AMode::RegOffset(addr.to_reg(), off, ty)),
-        AMode::RegReg(r1, r2) => (r2, AMode::RegReg(addr.to_reg(), r1)),
-        AMode::UnsignedOffset(r, imm) => (r, AMode::UnsignedOffset(addr.to_reg(), imm)),
-        _ => unreachable!(),
-    };
-
-    // If there is any offset, load that first into `addr`, and add the `reg`
-    // that we kicked out of the `AMode`; otherwise, start with that reg.
-    if offset != 0 {
-        lower_add_immediate(ctx, addr, reg, offset)
-    } else {
-        ctx.emit(Inst::gen_move(addr, reg, I64));
-    }
-
-    // Now handle reg64 and reg32-extended components.
-    lower_add_addends(ctx, addr, addends64, addends32);
-
-    memarg
-}
-
-fn lower_add_addends<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    rd: Writable<Reg>,
-    addends64: AddressAddend64List,
-    addends32: AddressAddend32List,
-) {
-    for reg in addends64 {
-        // If the register is the stack reg, we must move it to another reg
-        // before adding it.
-        let reg = if reg == stack_reg() {
-            let tmp = ctx.alloc_tmp(I64).only_reg().unwrap();
-            ctx.emit(Inst::gen_move(tmp, stack_reg(), I64));
-            tmp.to_reg()
-        } else {
-            reg
-        };
-        ctx.emit(Inst::AluRRR {
-            alu_op: ALUOp::Add,
-            size: OperandSize::Size64,
-            rd,
-            rn: rd.to_reg(),
-            rm: reg,
-        });
-    }
-    for (reg, extendop) in addends32 {
-        assert!(reg != stack_reg());
-        ctx.emit(Inst::AluRRRExtend {
-            alu_op: ALUOp::Add,
-            size: OperandSize::Size64,
-            rd,
-            rn: rd.to_reg(),
-            rm: reg,
-            extendop,
-        });
-    }
-}
-
-/// Adds into `rd` a signed imm pattern matching the best instruction for it.
-// TODO: This function is duplicated in ctx.gen_add_imm
-fn lower_add_immediate<C: LowerCtx<I = Inst>>(ctx: &mut C, dst: Writable<Reg>, src: Reg, imm: i64) {
-    // If we can fit offset or -offset in an imm12, use an add-imm
-    // Otherwise, lower the constant first then add.
-    if let Some(imm12) = Imm12::maybe_from_u64(imm as u64) {
-        ctx.emit(Inst::AluRRImm12 {
-            alu_op: ALUOp::Add,
-            size: OperandSize::Size64,
-            rd: dst,
-            rn: src,
-            imm12,
-        });
-    } else if let Some(imm12) = Imm12::maybe_from_u64(imm.wrapping_neg() as u64) {
-        ctx.emit(Inst::AluRRImm12 {
-            alu_op: ALUOp::Sub,
-            size: OperandSize::Size64,
-            rd: dst,
-            rn: src,
-            imm12,
-        });
-    } else {
-        lower_constant_u64(ctx, dst, imm as u64);
-        ctx.emit(Inst::AluRRR {
-            alu_op: ALUOp::Add,
-            size: OperandSize::Size64,
-            rd: dst,
-            rn: dst.to_reg(),
-            rm: src,
-        });
-    }
-}
-
-pub(crate) fn lower_constant_u64<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    rd: Writable<Reg>,
-    value: u64,
-) {
-    for inst in Inst::load_constant(rd, value) {
-        ctx.emit(inst);
-    }
-}
-
-pub(crate) fn lower_constant_f32<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    rd: Writable<Reg>,
-    value: f32,
-) {
-    let alloc_tmp = |ty| ctx.alloc_tmp(ty).only_reg().unwrap();
-
-    for inst in Inst::load_fp_constant32(rd, value.to_bits(), alloc_tmp) {
-        ctx.emit(inst);
-    }
-}
-
-pub(crate) fn lower_constant_f64<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    rd: Writable<Reg>,
-    value: f64,
-) {
-    let alloc_tmp = |ty| ctx.alloc_tmp(ty).only_reg().unwrap();
-
-    for inst in Inst::load_fp_constant64(rd, value.to_bits(), alloc_tmp) {
-        ctx.emit(inst);
-    }
-}
-
-pub(crate) fn lower_constant_f128<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    rd: Writable<Reg>,
-    value: u128,
-) {
-    if value == 0 {
-        // Fast-track a common case.  The general case, viz, calling `Inst::load_fp_constant128`,
-        // is potentially expensive.
-        ctx.emit(Inst::VecDupImm {
-            rd,
-            imm: ASIMDMovModImm::zero(ScalarSize::Size8),
-            invert: false,
-            size: VectorSize::Size8x16,
-        });
-    } else {
-        let alloc_tmp = |ty| ctx.alloc_tmp(ty).only_reg().unwrap();
-        for inst in Inst::load_fp_constant128(rd, value, alloc_tmp) {
-            ctx.emit(inst);
-        }
-    }
-}
-
-pub(crate) fn lower_splat_const<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    rd: Writable<Reg>,
-    value: u64,
-    size: VectorSize,
-) {
-    let (value, narrow_size) = match size.lane_size() {
-        ScalarSize::Size8 => (value as u8 as u64, ScalarSize::Size128),
-        ScalarSize::Size16 => (value as u16 as u64, ScalarSize::Size8),
-        ScalarSize::Size32 => (value as u32 as u64, ScalarSize::Size16),
-        ScalarSize::Size64 => (value, ScalarSize::Size32),
-        _ => unreachable!(),
-    };
-    let (value, size) = match Inst::get_replicated_vector_pattern(value as u128, narrow_size) {
-        Some((value, lane_size)) => (
-            value,
-            VectorSize::from_lane_size(lane_size, size.is_128bits()),
-        ),
-        None => (value, size),
-    };
-    let alloc_tmp = |ty| ctx.alloc_tmp(ty).only_reg().unwrap();
-
-    for inst in Inst::load_replicated_vector_pattern(rd, value, size, alloc_tmp) {
-        ctx.emit(inst);
-    }
-}
-
-pub(crate) fn lower_condcode(cc: IntCC) -> Cond {
-    match cc {
-        IntCC::Equal => Cond::Eq,
-        IntCC::NotEqual => Cond::Ne,
-        IntCC::SignedGreaterThanOrEqual => Cond::Ge,
-        IntCC::SignedGreaterThan => Cond::Gt,
-        IntCC::SignedLessThanOrEqual => Cond::Le,
-        IntCC::SignedLessThan => Cond::Lt,
-        IntCC::UnsignedGreaterThanOrEqual => Cond::Hs,
-        IntCC::UnsignedGreaterThan => Cond::Hi,
-        IntCC::UnsignedLessThanOrEqual => Cond::Ls,
-        IntCC::UnsignedLessThan => Cond::Lo,
-        IntCC::Overflow => Cond::Vs,
-        IntCC::NotOverflow => Cond::Vc,
-    }
-}
-
-pub(crate) fn lower_fp_condcode(cc: FloatCC) -> Cond {
-    // Refer to `codegen/shared/src/condcodes.rs` and to the `FCMP` AArch64 docs.
-    // The FCMP instruction sets:
-    //               NZCV
-    // - PCSR.NZCV = 0011 on UN (unordered),
-    //               0110 on EQ,
-    //               1000 on LT,
-    //               0010 on GT.
-    match cc {
-        // EQ | LT | GT. Vc => V clear.
-        FloatCC::Ordered => Cond::Vc,
-        // UN. Vs => V set.
-        FloatCC::Unordered => Cond::Vs,
-        // EQ. Eq => Z set.
-        FloatCC::Equal => Cond::Eq,
-        // UN | LT | GT. Ne => Z clear.
-        FloatCC::NotEqual => Cond::Ne,
-        // LT | GT.
-        FloatCC::OrderedNotEqual => unimplemented!(),
-        //  UN | EQ
-        FloatCC::UnorderedOrEqual => unimplemented!(),
-        // LT. Mi => N set.
-        FloatCC::LessThan => Cond::Mi,
-        // LT | EQ. Ls => C clear or Z set.
-        FloatCC::LessThanOrEqual => Cond::Ls,
-        // GT. Gt => Z clear, N = V.
-        FloatCC::GreaterThan => Cond::Gt,
-        // GT | EQ. Ge => N = V.
-        FloatCC::GreaterThanOrEqual => Cond::Ge,
-        // UN | LT
-        FloatCC::UnorderedOrLessThan => unimplemented!(),
-        // UN | LT | EQ
-        FloatCC::UnorderedOrLessThanOrEqual => unimplemented!(),
-        // UN | GT
-        FloatCC::UnorderedOrGreaterThan => unimplemented!(),
-        // UN | GT | EQ
-        FloatCC::UnorderedOrGreaterThanOrEqual => unimplemented!(),
-    }
-}
-
-pub(crate) fn lower_vector_compare<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    rd: Writable<Reg>,
-    mut rn: Reg,
-    mut rm: Reg,
-    ty: Type,
-    cond: Cond,
-) -> CodegenResult<()> {
-    let is_float = ty.lane_type().is_float();
-    let size = VectorSize::from_ty(ty);
-
-    if is_float && (cond == Cond::Vc || cond == Cond::Vs) {
-        let tmp = ctx.alloc_tmp(ty).only_reg().unwrap();
-
-        ctx.emit(Inst::VecRRR {
-            alu_op: VecALUOp::Fcmeq,
-            rd,
-            rn,
-            rm: rn,
-            size,
-        });
-        ctx.emit(Inst::VecRRR {
-            alu_op: VecALUOp::Fcmeq,
-            rd: tmp,
-            rn: rm,
-            rm,
-            size,
-        });
-        ctx.emit(Inst::VecRRR {
-            alu_op: VecALUOp::And,
-            rd,
-            rn: rd.to_reg(),
-            rm: tmp.to_reg(),
-            size,
-        });
-
-        if cond == Cond::Vs {
-            ctx.emit(Inst::VecMisc {
-                op: VecMisc2::Not,
-                rd,
-                rn: rd.to_reg(),
-                size,
-            });
-        }
-    } else {
-        // 'Less than' operations are implemented by swapping
-        // the order of operands and using the 'greater than'
-        // instructions.
-        // 'Not equal' is implemented with 'equal' and inverting
-        // the result.
-        let (alu_op, swap) = match (is_float, cond) {
-            (false, Cond::Eq) => (VecALUOp::Cmeq, false),
-            (false, Cond::Ne) => (VecALUOp::Cmeq, false),
-            (false, Cond::Ge) => (VecALUOp::Cmge, false),
-            (false, Cond::Gt) => (VecALUOp::Cmgt, false),
-            (false, Cond::Le) => (VecALUOp::Cmge, true),
-            (false, Cond::Lt) => (VecALUOp::Cmgt, true),
-            (false, Cond::Hs) => (VecALUOp::Cmhs, false),
-            (false, Cond::Hi) => (VecALUOp::Cmhi, false),
-            (false, Cond::Ls) => (VecALUOp::Cmhs, true),
-            (false, Cond::Lo) => (VecALUOp::Cmhi, true),
-            (true, Cond::Eq) => (VecALUOp::Fcmeq, false),
-            (true, Cond::Ne) => (VecALUOp::Fcmeq, false),
-            (true, Cond::Mi) => (VecALUOp::Fcmgt, true),
-            (true, Cond::Ls) => (VecALUOp::Fcmge, true),
-            (true, Cond::Ge) => (VecALUOp::Fcmge, false),
-            (true, Cond::Gt) => (VecALUOp::Fcmgt, false),
-            _ => {
-                return Err(CodegenError::Unsupported(format!(
-                    "Unsupported {} SIMD vector comparison: {:?}",
-                    if is_float {
-                        "floating-point"
-                    } else {
-                        "integer"
-                    },
-                    cond
-                )))
-            }
-        };
-
-        if swap {
-            std::mem::swap(&mut rn, &mut rm);
-        }
-
-        ctx.emit(Inst::VecRRR {
-            alu_op,
-            rd,
-            rn,
-            rm,
-            size,
-        });
-
-        if cond == Cond::Ne {
-            ctx.emit(Inst::VecMisc {
-                op: VecMisc2::Not,
-                rd,
-                rn: rd.to_reg(),
-                size,
-            });
-        }
-    }
-
-    Ok(())
-}
-
-/// Determines whether this condcode interprets inputs as signed or unsigned.  See the
-/// documentation for the `icmp` instruction in cranelift-codegen/meta/src/shared/instructions.rs
-/// for further insights into this.
-pub(crate) fn condcode_is_signed(cc: IntCC) -> bool {
-    match cc {
-        IntCC::Equal
-        | IntCC::UnsignedGreaterThanOrEqual
-        | IntCC::UnsignedGreaterThan
-        | IntCC::UnsignedLessThanOrEqual
-        | IntCC::UnsignedLessThan
-        | IntCC::NotEqual => false,
-        IntCC::SignedGreaterThanOrEqual
-        | IntCC::SignedGreaterThan
-        | IntCC::SignedLessThanOrEqual
-        | IntCC::SignedLessThan
-        | IntCC::Overflow
-        | IntCC::NotOverflow => true,
-    }
-}
-
-//=============================================================================
-// Helpers for instruction lowering.
-
-pub(crate) fn choose_32_64<T: Copy>(ty: Type, op32: T, op64: T) -> T {
-    let bits = ty_bits(ty);
-    if bits <= 32 {
-        op32
-    } else if bits == 64 {
-        op64
-    } else {
-        panic!("choose_32_64 on > 64 bits!")
-    }
-}
-
-/// Checks for an instance of `op` feeding the given input.
-pub(crate) fn maybe_input_insn<C: LowerCtx<I = Inst>>(
-    c: &mut C,
-    input: InsnInput,
-    op: Opcode,
-) -> Option<IRInst> {
-    let inputs = c.get_input_as_source_or_const(input.insn, input.input);
-    log::trace!(
-        "maybe_input_insn: input {:?} has options {:?}; looking for op {:?}",
-        input,
-        inputs,
-        op
-    );
-    if let Some((src_inst, _)) = inputs.inst {
-        let data = c.data(src_inst);
-        log::trace!(" -> input inst {:?}", data);
-        if data.opcode() == op {
-            return Some(src_inst);
-        }
-    }
-    None
-}
-
-/// Checks for an instance of any one of `ops` feeding the given input.
-pub(crate) fn maybe_input_insn_multi<C: LowerCtx<I = Inst>>(
-    c: &mut C,
-    input: InsnInput,
-    ops: &[Opcode],
-) -> Option<(Opcode, IRInst)> {
-    for &op in ops {
-        if let Some(inst) = maybe_input_insn(c, input, op) {
-            return Some((op, inst));
-        }
-    }
-    None
-}
-
-/// Checks for an instance of `op` feeding the given input, possibly via a conversion `conv` (e.g.,
-/// Bint or a bitcast).
-///
-/// FIXME cfallin 2020-03-30: this is really ugly. Factor out tree-matching stuff and make it
-/// a bit more generic.
-pub(crate) fn maybe_input_insn_via_conv<C: LowerCtx<I = Inst>>(
-    c: &mut C,
-    input: InsnInput,
-    op: Opcode,
-    conv: Opcode,
-) -> Option<IRInst> {
-    let inputs = c.get_input_as_source_or_const(input.insn, input.input);
-    if let Some((src_inst, _)) = inputs.inst {
-        let data = c.data(src_inst);
-        if data.opcode() == op {
-            return Some(src_inst);
-        }
-        if data.opcode() == conv {
-            let inputs = c.get_input_as_source_or_const(src_inst, 0);
-            if let Some((src_inst, _)) = inputs.inst {
-                let data = c.data(src_inst);
-                if data.opcode() == op {
-                    return Some(src_inst);
-                }
-            }
-        }
-    }
-    None
-}
-
-/// Specifies what [lower_icmp] should do when lowering
-#[derive(Debug, Clone, PartialEq)]
-pub(crate) enum IcmpOutput {
-    /// Lowers the comparison into a cond code, discarding the results. The cond code emitted can
-    /// be checked in the resulting [IcmpResult].
-    CondCode,
-    /// Materializes the results into a register. This may overwrite any flags previously set.
-    Register(Writable<Reg>),
-}
-
-impl IcmpOutput {
-    pub fn reg(&self) -> Option<Writable<Reg>> {
-        match self {
-            IcmpOutput::CondCode => None,
-            IcmpOutput::Register(reg) => Some(*reg),
-        }
-    }
-}
-
-/// The output of an Icmp lowering.
-#[derive(Debug, Clone, PartialEq)]
-pub(crate) enum IcmpResult {
-    /// The result was output into the given [Cond]. Callers may perform operations using this [Cond]
-    /// and its inverse, other [Cond]'s are not guaranteed to be correct.
-    CondCode(Cond),
-    /// The result was materialized into the output register.
-    Register,
-}
-
-impl IcmpResult {
-    pub fn unwrap_cond(&self) -> Cond {
-        match self {
-            IcmpResult::CondCode(c) => *c,
-            _ => panic!("Unwrapped cond, but IcmpResult was {:?}", self),
-        }
-    }
-}
-
-/// Lower an icmp comparision
-///
-/// We can lower into the status flags, or materialize the result into a register
-/// This is controlled by the `output` parameter.
-pub(crate) fn lower_icmp<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    insn: IRInst,
-    condcode: IntCC,
-    output: IcmpOutput,
-) -> CodegenResult<IcmpResult> {
-    log::trace!(
-        "lower_icmp: insn {}, condcode: {}, output: {:?}",
-        insn,
-        condcode,
-        output
-    );
-
-    let rd = output.reg().unwrap_or(writable_zero_reg());
-    let inputs = insn_inputs(ctx, insn);
-    let cond = lower_condcode(condcode);
-    let is_signed = condcode_is_signed(condcode);
-    let ty = ctx.input_ty(insn, 0);
-    let bits = ty_bits(ty);
-    let narrow_mode = match (bits <= 32, is_signed) {
-        (true, true) => NarrowValueMode::SignExtend32,
-        (true, false) => NarrowValueMode::ZeroExtend32,
-        (false, true) => NarrowValueMode::SignExtend64,
-        (false, false) => NarrowValueMode::ZeroExtend64,
-    };
-    let mut should_materialize = output.reg().is_some();
-
-    let out_condcode = if ty == I128 {
-        let lhs = put_input_in_regs(ctx, inputs[0]);
-        let rhs = put_input_in_regs(ctx, inputs[1]);
-
-        let tmp1 = ctx.alloc_tmp(I64).only_reg().unwrap();
-        let tmp2 = ctx.alloc_tmp(I64).only_reg().unwrap();
-
-        match condcode {
-            IntCC::Equal | IntCC::NotEqual => {
-                // eor     tmp1, lhs_lo, rhs_lo
-                // eor     tmp2, lhs_hi, rhs_hi
-                // adds    xzr, tmp1, tmp2
-                // cset    dst, {eq, ne}
-
-                ctx.emit(Inst::AluRRR {
-                    alu_op: ALUOp::Eor,
-                    size: OperandSize::Size64,
-                    rd: tmp1,
-                    rn: lhs.regs()[0],
-                    rm: rhs.regs()[0],
-                });
-                ctx.emit(Inst::AluRRR {
-                    alu_op: ALUOp::Eor,
-                    size: OperandSize::Size64,
-                    rd: tmp2,
-                    rn: lhs.regs()[1],
-                    rm: rhs.regs()[1],
-                });
-                ctx.emit(Inst::AluRRR {
-                    alu_op: ALUOp::AddS,
-                    size: OperandSize::Size64,
-                    rd: writable_zero_reg(),
-                    rn: tmp1.to_reg(),
-                    rm: tmp2.to_reg(),
-                });
-            }
-            IntCC::Overflow | IntCC::NotOverflow => {
-                // We can do an 128bit add while throwing away the results
-                // and check the overflow flags at the end.
-                //
-                // adds    xzr, lhs_lo, rhs_lo
-                // adcs    xzr, lhs_hi, rhs_hi
-                // cset    dst, {vs, vc}
-
-                ctx.emit(Inst::AluRRR {
-                    alu_op: ALUOp::AddS,
-                    size: OperandSize::Size64,
-                    rd: writable_zero_reg(),
-                    rn: lhs.regs()[0],
-                    rm: rhs.regs()[0],
-                });
-                ctx.emit(Inst::AluRRR {
-                    alu_op: ALUOp::AdcS,
-                    size: OperandSize::Size64,
-                    rd: writable_zero_reg(),
-                    rn: lhs.regs()[1],
-                    rm: rhs.regs()[1],
-                });
-            }
-            _ => {
-                // cmp     lhs_lo, rhs_lo
-                // cset    tmp1, unsigned_cond
-                // cmp     lhs_hi, rhs_hi
-                // cset    tmp2, cond
-                // csel    dst, tmp1, tmp2, eq
-
-                let rd = output.reg().unwrap_or(tmp1);
-                let unsigned_cond = lower_condcode(condcode.unsigned());
-
-                ctx.emit(Inst::AluRRR {
-                    alu_op: ALUOp::SubS,
-                    size: OperandSize::Size64,
-                    rd: writable_zero_reg(),
-                    rn: lhs.regs()[0],
-                    rm: rhs.regs()[0],
-                });
-                materialize_bool_result(ctx, insn, tmp1, unsigned_cond);
-                ctx.emit(Inst::AluRRR {
-                    alu_op: ALUOp::SubS,
-                    size: OperandSize::Size64,
-                    rd: writable_zero_reg(),
-                    rn: lhs.regs()[1],
-                    rm: rhs.regs()[1],
-                });
-                materialize_bool_result(ctx, insn, tmp2, cond);
-                ctx.emit(Inst::CSel {
-                    cond: Cond::Eq,
-                    rd,
-                    rn: tmp1.to_reg(),
-                    rm: tmp2.to_reg(),
-                });
-
-                if output == IcmpOutput::CondCode {
-                    // We only need to guarantee that the flags for `cond` are correct, so we can
-                    // compare rd with 0 or 1
-
-                    // If we are doing compare or equal, we want to compare with 1 instead of zero
-                    if condcode.without_equal() != condcode {
-                        lower_constant_u64(ctx, tmp2, 1);
-                    }
-
-                    let xzr = zero_reg();
-                    let rd = rd.to_reg();
-                    let tmp2 = tmp2.to_reg();
-                    let (rn, rm) = match condcode {
-                        IntCC::SignedGreaterThanOrEqual => (rd, tmp2),
-                        IntCC::UnsignedGreaterThanOrEqual => (rd, tmp2),
-                        IntCC::SignedLessThanOrEqual => (tmp2, rd),
-                        IntCC::UnsignedLessThanOrEqual => (tmp2, rd),
-                        IntCC::SignedGreaterThan => (rd, xzr),
-                        IntCC::UnsignedGreaterThan => (rd, xzr),
-                        IntCC::SignedLessThan => (xzr, rd),
-                        IntCC::UnsignedLessThan => (xzr, rd),
-                        _ => unreachable!(),
-                    };
-
-                    ctx.emit(Inst::AluRRR {
-                        alu_op: ALUOp::SubS,
-                        size: OperandSize::Size64,
-                        rd: writable_zero_reg(),
-                        rn,
-                        rm,
-                    });
-                }
-
-                // Prevent a second materialize_bool_result to be emitted at the end of the function
-                should_materialize = false;
-            }
-        }
-        cond
-    } else if ty.is_vector() {
-        assert_ne!(output, IcmpOutput::CondCode);
-        should_materialize = false;
-
-        let rn = put_input_in_reg(ctx, inputs[0], narrow_mode);
-        let rm = put_input_in_reg(ctx, inputs[1], narrow_mode);
-        lower_vector_compare(ctx, rd, rn, rm, ty, cond)?;
-        cond
-    } else {
-        let rn = put_input_in_reg(ctx, inputs[0], narrow_mode);
-        let rm = put_input_in_rse_imm12(ctx, inputs[1], narrow_mode);
-
-        let is_overflow = condcode == IntCC::Overflow || condcode == IntCC::NotOverflow;
-        let is_small_type = ty == I8 || ty == I16;
-        let (cond, rn, rm) = if is_overflow && is_small_type {
-            // Overflow checks for non native types require additional instructions, other than
-            // just the extend op.
-            //
-            // TODO: Codegen improvements: Merge the second sxt{h,b} into the following sub instruction.
-            //
-            // sxt{h,b}  w0, w0
-            // sxt{h,b}  w1, w1
-            // sub       w0, w0, w1
-            // cmp       w0, w0, sxt{h,b}
-            //
-            // The result of this comparison is either the EQ or NE condition code, so we need to
-            // signal that to the caller
-
-            let extend_op = if ty == I8 {
-                ExtendOp::SXTB
-            } else {
-                ExtendOp::SXTH
-            };
-            let tmp1 = ctx.alloc_tmp(I32).only_reg().unwrap();
-            ctx.emit(alu_inst_imm12(ALUOp::Sub, I32, tmp1, rn, rm));
-
-            let out_cond = match condcode {
-                IntCC::Overflow => Cond::Ne,
-                IntCC::NotOverflow => Cond::Eq,
-                _ => unreachable!(),
-            };
-            (
-                out_cond,
-                tmp1.to_reg(),
-                ResultRSEImm12::RegExtend(tmp1.to_reg(), extend_op),
-            )
-        } else {
-            (cond, rn, rm)
-        };
-
-        ctx.emit(alu_inst_imm12(ALUOp::SubS, ty, writable_zero_reg(), rn, rm));
-        cond
-    };
-
-    // Most of the comparisons above produce flags by default, if the caller requested the result
-    // in a register we materialize those flags into a register. Some branches do end up producing
-    // the result as a register by default, so we ignore those.
-    if should_materialize {
-        materialize_bool_result(ctx, insn, rd, cond);
-    }
-
-    Ok(match output {
-        // We currently never emit a different register than what was asked for
-        IcmpOutput::Register(_) => IcmpResult::Register,
-        IcmpOutput::CondCode => IcmpResult::CondCode(out_condcode),
-    })
-}
-
-pub(crate) fn lower_fcmp_or_ffcmp_to_flags<C: LowerCtx<I = Inst>>(ctx: &mut C, insn: IRInst) {
-    let ty = ctx.input_ty(insn, 0);
-    let bits = ty_bits(ty);
-    let inputs = [InsnInput { insn, input: 0 }, InsnInput { insn, input: 1 }];
-    let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-    let rm = put_input_in_reg(ctx, inputs[1], NarrowValueMode::None);
-    match bits {
-        32 => {
-            ctx.emit(Inst::FpuCmp32 { rn, rm });
-        }
-        64 => {
-            ctx.emit(Inst::FpuCmp64 { rn, rm });
-        }
-        _ => panic!("Unknown float size"),
-    }
-}
-
-/// Materialize a boolean value into a register from the flags
-/// (e.g set by a comparison).
-/// A 0 / -1 (all-ones) result as expected for bool operations.
-pub(crate) fn materialize_bool_result<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    insn: IRInst,
-    rd: Writable<Reg>,
-    cond: Cond,
-) {
-    // A boolean is 0 / -1; if output width is > 1 use `csetm`,
-    // otherwise use `cset`.
-    if ty_bits(ctx.output_ty(insn, 0)) > 1 {
-        ctx.emit(Inst::CSetm { rd, cond });
-    } else {
-        ctx.emit(Inst::CSet { rd, cond });
-    }
-}
-
-/// This is target-word-size dependent.  And it excludes booleans and reftypes.
-pub(crate) fn is_valid_atomic_transaction_ty(ty: Type) -> bool {
-    match ty {
-        I8 | I16 | I32 | I64 => true,
-        _ => false,
-    }
-}
-
-pub(crate) fn emit_atomic_load<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    rt: Writable<Reg>,
-    insn: IRInst,
-) -> Inst {
-    assert!(ctx.data(insn).opcode() == Opcode::AtomicLoad);
-    let inputs = insn_inputs(ctx, insn);
-    let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-    let access_ty = ctx.output_ty(insn, 0);
-    assert!(is_valid_atomic_transaction_ty(access_ty));
-    // We're ignoring the result type of the load because the LoadAcquire will
-    // explicitly zero extend to the nearest word, and also zero the high half
-    // of an X register.
-    Inst::LoadAcquire { access_ty, rt, rn }
-}
-
-fn load_op_to_ty(op: Opcode) -> Option<Type> {
-    match op {
-        Opcode::Sload8 | Opcode::Uload8 | Opcode::Sload8Complex | Opcode::Uload8Complex => Some(I8),
-        Opcode::Sload16 | Opcode::Uload16 | Opcode::Sload16Complex | Opcode::Uload16Complex => {
-            Some(I16)
-        }
-        Opcode::Sload32 | Opcode::Uload32 | Opcode::Sload32Complex | Opcode::Uload32Complex => {
-            Some(I32)
-        }
-        Opcode::Load | Opcode::LoadComplex => None,
-        Opcode::Sload8x8 | Opcode::Uload8x8 | Opcode::Sload8x8Complex | Opcode::Uload8x8Complex => {
-            Some(I8X8)
-        }
-        Opcode::Sload16x4
-        | Opcode::Uload16x4
-        | Opcode::Sload16x4Complex
-        | Opcode::Uload16x4Complex => Some(I16X4),
-        Opcode::Sload32x2
-        | Opcode::Uload32x2
-        | Opcode::Sload32x2Complex
-        | Opcode::Uload32x2Complex => Some(I32X2),
-        _ => None,
-    }
-}
-
-/// Helper to lower a load instruction; this is used in several places, because
-/// a load can sometimes be merged into another operation.
-pub(crate) fn lower_load<
-    C: LowerCtx<I = Inst>,
-    F: FnMut(&mut C, ValueRegs<Writable<Reg>>, Type, AMode) -> CodegenResult<()>,
->(
-    ctx: &mut C,
-    ir_inst: IRInst,
-    inputs: &[InsnInput],
-    output: InsnOutput,
-    mut f: F,
-) -> CodegenResult<()> {
-    let op = ctx.data(ir_inst).opcode();
-
-    let elem_ty = load_op_to_ty(op).unwrap_or_else(|| ctx.output_ty(ir_inst, 0));
-
-    let off = ctx.data(ir_inst).load_store_offset().unwrap();
-    let mem = lower_address(ctx, elem_ty, &inputs[..], off);
-    let rd = get_output_reg(ctx, output);
-
-    f(ctx, rd, elem_ty, mem)
-}
-
-//=============================================================================
-// Lowering-backend trait implementation.
-
-impl LowerBackend for AArch64Backend {
-    type MInst = Inst;
-
-    fn lower<C: LowerCtx<I = Inst>>(&self, ctx: &mut C, ir_inst: IRInst) -> CodegenResult<()> {
-        lower_inst::lower_insn_to_regs(ctx, ir_inst, &self.flags, &self.isa_flags)
-    }
-
-    fn lower_branch_group<C: LowerCtx<I = Inst>>(
-        &self,
-        ctx: &mut C,
-        branches: &[IRInst],
-        targets: &[MachLabel],
-    ) -> CodegenResult<()> {
-        lower_inst::lower_branch(ctx, branches, targets)
-    }
-
-    fn maybe_pinned_reg(&self) -> Option<Reg> {
-        Some(xreg(PINNED_REG))
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/lower/isle.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/lower/isle.rs
deleted file mode 100644
index 56d86ccfa..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/lower/isle.rs
+++ /dev/null
@@ -1,289 +0,0 @@
-//! ISLE integration glue code for aarch64 lowering.
-
-// Pull in the ISLE generated code.
-pub mod generated_code;
-
-// Types that the generated ISLE code uses via `use super::*`.
-use super::{
-    writable_zero_reg, zero_reg, AMode, ASIMDFPModImm, ASIMDMovModImm, AtomicRmwOp, BranchTarget,
-    CallIndInfo, CallInfo, Cond, CondBrKind, ExtendOp, FPUOpRI, Imm12, ImmLogic, ImmShift,
-    Inst as MInst, JTSequenceInfo, MachLabel, MoveWideConst, NarrowValueMode, Opcode, OperandSize,
-    PairAMode, Reg, ScalarSize, ShiftOpAndAmt, UImm5, VectorSize, NZCV,
-};
-use crate::isa::aarch64::settings::Flags as IsaFlags;
-use crate::machinst::isle::*;
-use crate::settings::Flags;
-use crate::{
-    binemit::CodeOffset,
-    ir::{
-        immediates::*, types::*, ExternalName, Inst, InstructionData, MemFlags, TrapCode, Value,
-        ValueLabel, ValueList,
-    },
-    isa::aarch64::inst::aarch64_map_regs,
-    isa::aarch64::inst::args::{ShiftOp, ShiftOpShiftImm},
-    isa::unwind::UnwindInst,
-    machinst::{ty_bits, InsnOutput, LowerCtx},
-};
-use std::boxed::Box;
-use std::convert::TryFrom;
-use std::vec::Vec;
-
-type BoxCallInfo = Box<CallInfo>;
-type BoxCallIndInfo = Box<CallIndInfo>;
-type VecMachLabel = Vec<MachLabel>;
-type BoxJTSequenceInfo = Box<JTSequenceInfo>;
-type BoxExternalName = Box<ExternalName>;
-
-/// The main entry point for lowering with ISLE.
-pub(crate) fn lower<C>(
-    lower_ctx: &mut C,
-    flags: &Flags,
-    isa_flags: &IsaFlags,
-    outputs: &[InsnOutput],
-    inst: Inst,
-) -> Result<(), ()>
-where
-    C: LowerCtx<I = MInst>,
-{
-    lower_common(
-        lower_ctx,
-        flags,
-        isa_flags,
-        outputs,
-        inst,
-        |cx, insn| generated_code::constructor_lower(cx, insn),
-        aarch64_map_regs,
-    )
-}
-
-pub struct ExtendedValue {
-    val: Value,
-    extend: ExtendOp,
-}
-
-pub struct SinkableAtomicLoad {
-    atomic_load: Inst,
-    atomic_addr: Value,
-}
-
-impl<C> generated_code::Context for IsleContext<'_, C, Flags, IsaFlags, 6>
-where
-    C: LowerCtx<I = MInst>,
-{
-    isle_prelude_methods!();
-
-    fn move_wide_const_from_u64(&mut self, n: u64) -> Option<MoveWideConst> {
-        MoveWideConst::maybe_from_u64(n)
-    }
-
-    fn move_wide_const_from_negated_u64(&mut self, n: u64) -> Option<MoveWideConst> {
-        MoveWideConst::maybe_from_u64(!n)
-    }
-
-    fn imm_logic_from_u64(&mut self, n: u64, ty: Type) -> Option<ImmLogic> {
-        let ty = if ty.bits() < 32 { I32 } else { ty };
-        ImmLogic::maybe_from_u64(n, ty)
-    }
-
-    fn imm_logic_from_imm64(&mut self, n: Imm64, ty: Type) -> Option<ImmLogic> {
-        self.imm_logic_from_u64(n.bits() as u64, ty)
-    }
-
-    fn imm12_from_u64(&mut self, n: u64) -> Option<Imm12> {
-        Imm12::maybe_from_u64(n)
-    }
-
-    fn imm12_from_negated_u64(&mut self, n: u64) -> Option<Imm12> {
-        Imm12::maybe_from_u64((n as i64).wrapping_neg() as u64)
-    }
-
-    fn imm_shift_from_u8(&mut self, n: u8) -> ImmShift {
-        ImmShift::maybe_from_u64(n.into()).unwrap()
-    }
-
-    fn lshl_from_imm64(&mut self, n: Imm64, ty: Type) -> Option<ShiftOpAndAmt> {
-        let shiftimm = ShiftOpShiftImm::maybe_from_shift(n.bits() as u64)?;
-        let shiftee_bits = ty_bits(ty);
-        if shiftee_bits <= std::u8::MAX as usize {
-            let shiftimm = shiftimm.mask(shiftee_bits as u8);
-            Some(ShiftOpAndAmt::new(ShiftOp::LSL, shiftimm))
-        } else {
-            None
-        }
-    }
-
-    fn integral_ty(&mut self, ty: Type) -> Option<Type> {
-        match ty {
-            I8 | I16 | I32 | I64 | R64 => Some(ty),
-            ty if ty.is_bool() => Some(ty),
-            _ => None,
-        }
-    }
-
-    /// This is the fallback case for loading a 64-bit integral constant into a
-    /// register.
-    ///
-    /// The logic here is nontrivial enough that it's not really worth porting
-    /// this over to ISLE.
-    fn load_constant64_full(&mut self, value: u64) -> Reg {
-        // If the top 32 bits are zero, use 32-bit `mov` operations.
-        let (num_half_words, size, negated) = if value >> 32 == 0 {
-            (2, OperandSize::Size32, (!value << 32) >> 32)
-        } else {
-            (4, OperandSize::Size64, !value)
-        };
-        // If the number of 0xffff half words is greater than the number of 0x0000 half words
-        // it is more efficient to use `movn` for the first instruction.
-        let first_is_inverted = count_zero_half_words(negated, num_half_words)
-            > count_zero_half_words(value, num_half_words);
-        // Either 0xffff or 0x0000 half words can be skipped, depending on the first
-        // instruction used.
-        let ignored_halfword = if first_is_inverted { 0xffff } else { 0 };
-        let mut first_mov_emitted = false;
-
-        let rd = self.temp_writable_reg(I64);
-
-        for i in 0..num_half_words {
-            let imm16 = (value >> (16 * i)) & 0xffff;
-            if imm16 != ignored_halfword {
-                if !first_mov_emitted {
-                    first_mov_emitted = true;
-                    if first_is_inverted {
-                        let imm =
-                            MoveWideConst::maybe_with_shift(((!imm16) & 0xffff) as u16, i * 16)
-                                .unwrap();
-                        self.emit(&MInst::MovN { rd, imm, size });
-                    } else {
-                        let imm = MoveWideConst::maybe_with_shift(imm16 as u16, i * 16).unwrap();
-                        self.emit(&MInst::MovZ { rd, imm, size });
-                    }
-                } else {
-                    let imm = MoveWideConst::maybe_with_shift(imm16 as u16, i * 16).unwrap();
-                    self.emit(&MInst::MovK { rd, imm, size });
-                }
-            }
-        }
-
-        assert!(first_mov_emitted);
-
-        return self.writable_reg_to_reg(rd);
-
-        fn count_zero_half_words(mut value: u64, num_half_words: u8) -> usize {
-            let mut count = 0;
-            for _ in 0..num_half_words {
-                if value & 0xffff == 0 {
-                    count += 1;
-                }
-                value >>= 16;
-            }
-
-            count
-        }
-    }
-
-    fn zero_reg(&mut self) -> Reg {
-        zero_reg()
-    }
-
-    fn extended_value_from_value(&mut self, val: Value) -> Option<ExtendedValue> {
-        let (val, extend) =
-            super::get_as_extended_value(self.lower_ctx, val, NarrowValueMode::None)?;
-        Some(ExtendedValue { val, extend })
-    }
-
-    fn put_extended_in_reg(&mut self, reg: &ExtendedValue) -> Reg {
-        self.put_in_reg(reg.val)
-    }
-
-    fn get_extended_op(&mut self, reg: &ExtendedValue) -> ExtendOp {
-        reg.extend
-    }
-
-    fn emit(&mut self, inst: &MInst) -> Unit {
-        self.emitted_insts.push((inst.clone(), false));
-    }
-
-    fn emit_safepoint(&mut self, inst: &MInst) -> Unit {
-        self.emitted_insts.push((inst.clone(), true));
-    }
-
-    fn cond_br_zero(&mut self, reg: Reg) -> CondBrKind {
-        CondBrKind::Zero(reg)
-    }
-
-    fn cond_br_cond(&mut self, cond: &Cond) -> CondBrKind {
-        CondBrKind::Cond(*cond)
-    }
-
-    fn nzcv(&mut self, n: bool, z: bool, c: bool, v: bool) -> NZCV {
-        NZCV::new(n, z, c, v)
-    }
-
-    fn u8_into_uimm5(&mut self, x: u8) -> UImm5 {
-        UImm5::maybe_from_u8(x).unwrap()
-    }
-
-    fn u8_into_imm12(&mut self, x: u8) -> Imm12 {
-        Imm12::maybe_from_u64(x.into()).unwrap()
-    }
-
-    fn writable_zero_reg(&mut self) -> WritableReg {
-        writable_zero_reg()
-    }
-
-    fn safe_divisor_from_imm64(&mut self, val: Imm64) -> Option<u64> {
-        match val.bits() {
-            0 | -1 => None,
-            n => Some(n as u64),
-        }
-    }
-
-    fn sinkable_atomic_load(&mut self, val: Value) -> Option<SinkableAtomicLoad> {
-        let input = self.lower_ctx.get_value_as_source_or_const(val);
-        if let Some((atomic_load, 0)) = input.inst {
-            if self.lower_ctx.data(atomic_load).opcode() == Opcode::AtomicLoad {
-                let atomic_addr = self.lower_ctx.input_as_value(atomic_load, 0);
-                return Some(SinkableAtomicLoad {
-                    atomic_load,
-                    atomic_addr,
-                });
-            }
-        }
-        None
-    }
-
-    fn sink_atomic_load(&mut self, load: &SinkableAtomicLoad) -> Reg {
-        self.lower_ctx.sink_inst(load.atomic_load);
-        self.put_in_reg(load.atomic_addr)
-    }
-
-    fn shift_mask(&mut self, ty: Type) -> ImmLogic {
-        let mask = (ty.bits() - 1) as u64;
-        ImmLogic::maybe_from_u64(mask, I32).unwrap()
-    }
-
-    fn imm_shift_from_imm64(&mut self, val: Imm64, ty: Type) -> Option<ImmShift> {
-        let imm_value = (val.bits() as u64) & ((ty.bits() - 1) as u64);
-        ImmShift::maybe_from_u64(imm_value)
-    }
-
-    fn u64_into_imm_logic(&mut self, ty: Type, val: u64) -> ImmLogic {
-        ImmLogic::maybe_from_u64(val, ty).unwrap()
-    }
-
-    fn negate_imm_shift(&mut self, ty: Type, mut imm: ImmShift) -> ImmShift {
-        let size = u8::try_from(ty.bits()).unwrap();
-        imm.imm = size.wrapping_sub(imm.value());
-        imm.imm &= size - 1;
-        imm
-    }
-
-    fn rotr_mask(&mut self, ty: Type) -> ImmLogic {
-        ImmLogic::maybe_from_u64((ty.bits() - 1) as u64, I32).unwrap()
-    }
-
-    fn rotr_opposite_amount(&mut self, ty: Type, val: ImmShift) -> ImmShift {
-        let amount = val.value() & u8::try_from(ty.bits() - 1).unwrap();
-        ImmShift::maybe_from_u64(u64::from(ty.bits()) - u64::from(amount)).unwrap()
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/lower/isle/generated_code.manifest b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/lower/isle/generated_code.manifest
deleted file mode 100644
index a9fae6d4d..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/lower/isle/generated_code.manifest
+++ /dev/null
@@ -1,4 +0,0 @@
-src/clif.isle 9ea75a6f790b5c03
-src/prelude.isle b2bc986bcbbbb77
-src/isa/aarch64/inst.isle 3678d0a37bdb4cff
-src/isa/aarch64/lower.isle 90accbfcadaea46d
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/lower/isle/generated_code.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/lower/isle/generated_code.rs
deleted file mode 100644
index 817d95a04..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/lower/isle/generated_code.rs
+++ /dev/null
@@ -1,6490 +0,0 @@
-// GENERATED BY ISLE. DO NOT EDIT!
-//
-// Generated automatically from the instruction-selection DSL code in:
-// - src/clif.isle
-// - src/prelude.isle
-// - src/isa/aarch64/inst.isle
-// - src/isa/aarch64/lower.isle
-
-#![allow(dead_code, unreachable_code, unreachable_patterns)]
-#![allow(unused_imports, unused_variables, non_snake_case)]
-#![allow(irrefutable_let_patterns)]
-
-use super::*; // Pulls in all external types.
-
-/// Context during lowering: an implementation of this trait
-/// must be provided with all external constructors and extractors.
-/// A mutable borrow is passed along through all lowering logic.
-pub trait Context {
-    fn unpack_value_array_2(&mut self, arg0: &ValueArray2) -> (Value, Value);
-    fn pack_value_array_2(&mut self, arg0: Value, arg1: Value) -> ValueArray2;
-    fn unpack_value_array_3(&mut self, arg0: &ValueArray3) -> (Value, Value, Value);
-    fn pack_value_array_3(&mut self, arg0: Value, arg1: Value, arg2: Value) -> ValueArray3;
-    fn u32_add(&mut self, arg0: u32, arg1: u32) -> u32;
-    fn u8_and(&mut self, arg0: u8, arg1: u8) -> u8;
-    fn value_reg(&mut self, arg0: Reg) -> ValueRegs;
-    fn value_regs(&mut self, arg0: Reg, arg1: Reg) -> ValueRegs;
-    fn value_regs_invalid(&mut self) -> ValueRegs;
-    fn output_none(&mut self) -> InstOutput;
-    fn output(&mut self, arg0: ValueRegs) -> InstOutput;
-    fn output_pair(&mut self, arg0: ValueRegs, arg1: ValueRegs) -> InstOutput;
-    fn output_builder_new(&mut self) -> InstOutputBuilder;
-    fn output_builder_push(&mut self, arg0: &InstOutputBuilder, arg1: ValueRegs) -> Unit;
-    fn output_builder_finish(&mut self, arg0: &InstOutputBuilder) -> InstOutput;
-    fn temp_writable_reg(&mut self, arg0: Type) -> WritableReg;
-    fn invalid_reg(&mut self) -> Reg;
-    fn put_in_reg(&mut self, arg0: Value) -> Reg;
-    fn put_in_regs(&mut self, arg0: Value) -> ValueRegs;
-    fn value_regs_get(&mut self, arg0: ValueRegs, arg1: usize) -> Reg;
-    fn u8_as_u64(&mut self, arg0: u8) -> u64;
-    fn u16_as_u64(&mut self, arg0: u16) -> u64;
-    fn u32_as_u64(&mut self, arg0: u32) -> u64;
-    fn i64_as_u64(&mut self, arg0: i64) -> u64;
-    fn u64_add(&mut self, arg0: u64, arg1: u64) -> u64;
-    fn u64_sub(&mut self, arg0: u64, arg1: u64) -> u64;
-    fn u64_and(&mut self, arg0: u64, arg1: u64) -> u64;
-    fn ty_bits(&mut self, arg0: Type) -> u8;
-    fn ty_bits_u16(&mut self, arg0: Type) -> u16;
-    fn ty_bits_u64(&mut self, arg0: Type) -> u64;
-    fn ty_mask(&mut self, arg0: Type) -> u64;
-    fn ty_bytes(&mut self, arg0: Type) -> u16;
-    fn lane_type(&mut self, arg0: Type) -> Type;
-    fn fits_in_16(&mut self, arg0: Type) -> Option<Type>;
-    fn fits_in_32(&mut self, arg0: Type) -> Option<Type>;
-    fn fits_in_64(&mut self, arg0: Type) -> Option<Type>;
-    fn ty_32_or_64(&mut self, arg0: Type) -> Option<Type>;
-    fn ty_8_or_16(&mut self, arg0: Type) -> Option<Type>;
-    fn ty_int_bool_64(&mut self, arg0: Type) -> Option<Type>;
-    fn ty_int_bool_128(&mut self, arg0: Type) -> Option<Type>;
-    fn vec128(&mut self, arg0: Type) -> Option<Type>;
-    fn not_i64x2(&mut self, arg0: Type) -> Option<()>;
-    fn value_list_slice(&mut self, arg0: ValueList) -> ValueSlice;
-    fn value_slice_empty(&mut self, arg0: ValueSlice) -> Option<()>;
-    fn value_slice_unwrap(&mut self, arg0: ValueSlice) -> Option<(Value, ValueSlice)>;
-    fn value_slice_len(&mut self, arg0: ValueSlice) -> usize;
-    fn value_slice_get(&mut self, arg0: ValueSlice, arg1: usize) -> Value;
-    fn writable_reg_to_reg(&mut self, arg0: WritableReg) -> Reg;
-    fn u8_from_uimm8(&mut self, arg0: Uimm8) -> u8;
-    fn u64_from_imm64(&mut self, arg0: Imm64) -> u64;
-    fn nonzero_u64_from_imm64(&mut self, arg0: Imm64) -> Option<u64>;
-    fn u64_from_ieee32(&mut self, arg0: Ieee32) -> u64;
-    fn u64_from_ieee64(&mut self, arg0: Ieee64) -> u64;
-    fn inst_results(&mut self, arg0: Inst) -> ValueSlice;
-    fn first_result(&mut self, arg0: Inst) -> Option<Value>;
-    fn inst_data(&mut self, arg0: Inst) -> InstructionData;
-    fn value_type(&mut self, arg0: Value) -> Type;
-    fn multi_lane(&mut self, arg0: Type) -> Option<(u8, u16)>;
-    fn def_inst(&mut self, arg0: Value) -> Option<Inst>;
-    fn emit(&mut self, arg0: &MInst) -> Unit;
-    fn emit_safepoint(&mut self, arg0: &MInst) -> Unit;
-    fn trap_code_division_by_zero(&mut self) -> TrapCode;
-    fn trap_code_integer_overflow(&mut self) -> TrapCode;
-    fn trap_code_bad_conversion_to_integer(&mut self) -> TrapCode;
-    fn avoid_div_traps(&mut self, arg0: Type) -> Option<()>;
-    fn func_ref_data(&mut self, arg0: FuncRef) -> (SigRef, ExternalName, RelocDistance);
-    fn symbol_value_data(
-        &mut self,
-        arg0: GlobalValue,
-    ) -> Option<(ExternalName, RelocDistance, i64)>;
-    fn reloc_distance_near(&mut self, arg0: RelocDistance) -> Option<()>;
-    fn move_wide_const_from_u64(&mut self, arg0: u64) -> Option<MoveWideConst>;
-    fn move_wide_const_from_negated_u64(&mut self, arg0: u64) -> Option<MoveWideConst>;
-    fn imm_logic_from_u64(&mut self, arg0: u64, arg1: Type) -> Option<ImmLogic>;
-    fn imm_logic_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ImmLogic>;
-    fn imm_shift_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ImmShift>;
-    fn imm_shift_from_u8(&mut self, arg0: u8) -> ImmShift;
-    fn imm12_from_u64(&mut self, arg0: u64) -> Option<Imm12>;
-    fn u8_into_uimm5(&mut self, arg0: u8) -> UImm5;
-    fn u8_into_imm12(&mut self, arg0: u8) -> Imm12;
-    fn u64_into_imm_logic(&mut self, arg0: Type, arg1: u64) -> ImmLogic;
-    fn imm12_from_negated_u64(&mut self, arg0: u64) -> Option<Imm12>;
-    fn lshl_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ShiftOpAndAmt>;
-    fn integral_ty(&mut self, arg0: Type) -> Option<Type>;
-    fn extended_value_from_value(&mut self, arg0: Value) -> Option<ExtendedValue>;
-    fn put_extended_in_reg(&mut self, arg0: &ExtendedValue) -> Reg;
-    fn get_extended_op(&mut self, arg0: &ExtendedValue) -> ExtendOp;
-    fn nzcv(&mut self, arg0: bool, arg1: bool, arg2: bool, arg3: bool) -> NZCV;
-    fn cond_br_zero(&mut self, arg0: Reg) -> CondBrKind;
-    fn cond_br_cond(&mut self, arg0: &Cond) -> CondBrKind;
-    fn zero_reg(&mut self) -> Reg;
-    fn writable_zero_reg(&mut self) -> WritableReg;
-    fn load_constant64_full(&mut self, arg0: u64) -> Reg;
-    fn sinkable_atomic_load(&mut self, arg0: Value) -> Option<SinkableAtomicLoad>;
-    fn sink_atomic_load(&mut self, arg0: &SinkableAtomicLoad) -> Reg;
-    fn safe_divisor_from_imm64(&mut self, arg0: Imm64) -> Option<u64>;
-    fn shift_mask(&mut self, arg0: Type) -> ImmLogic;
-    fn negate_imm_shift(&mut self, arg0: Type, arg1: ImmShift) -> ImmShift;
-    fn rotr_mask(&mut self, arg0: Type) -> ImmLogic;
-    fn rotr_opposite_amount(&mut self, arg0: Type, arg1: ImmShift) -> ImmShift;
-}
-
-/// Internal type SideEffectNoResult: defined at src/prelude.isle line 393.
-#[derive(Clone, Debug)]
-pub enum SideEffectNoResult {
-    Inst { inst: MInst },
-}
-
-/// Internal type ProducesFlags: defined at src/prelude.isle line 415.
-#[derive(Clone, Debug)]
-pub enum ProducesFlags {
-    ProducesFlagsSideEffect { inst: MInst },
-    ProducesFlagsReturnsReg { inst: MInst, result: Reg },
-    ProducesFlagsReturnsResultWithConsumer { inst: MInst, result: Reg },
-}
-
-/// Internal type ConsumesFlags: defined at src/prelude.isle line 426.
-#[derive(Clone, Debug)]
-pub enum ConsumesFlags {
-    ConsumesFlagsReturnsResultWithProducer {
-        inst: MInst,
-        result: Reg,
-    },
-    ConsumesFlagsReturnsReg {
-        inst: MInst,
-        result: Reg,
-    },
-    ConsumesFlagsTwiceReturnsValueRegs {
-        inst1: MInst,
-        inst2: MInst,
-        result: ValueRegs,
-    },
-    ConsumesFlagsFourTimesReturnsValueRegs {
-        inst1: MInst,
-        inst2: MInst,
-        inst3: MInst,
-        inst4: MInst,
-        result: ValueRegs,
-    },
-}
-
-/// Internal type MInst: defined at src/isa/aarch64/inst.isle line 2.
-#[derive(Clone, Debug)]
-pub enum MInst {
-    Nop0,
-    Nop4,
-    AluRRR {
-        alu_op: ALUOp,
-        size: OperandSize,
-        rd: WritableReg,
-        rn: Reg,
-        rm: Reg,
-    },
-    AluRRRR {
-        alu_op: ALUOp3,
-        rd: WritableReg,
-        rn: Reg,
-        rm: Reg,
-        ra: Reg,
-    },
-    AluRRImm12 {
-        alu_op: ALUOp,
-        size: OperandSize,
-        rd: WritableReg,
-        rn: Reg,
-        imm12: Imm12,
-    },
-    AluRRImmLogic {
-        alu_op: ALUOp,
-        size: OperandSize,
-        rd: WritableReg,
-        rn: Reg,
-        imml: ImmLogic,
-    },
-    AluRRImmShift {
-        alu_op: ALUOp,
-        size: OperandSize,
-        rd: WritableReg,
-        rn: Reg,
-        immshift: ImmShift,
-    },
-    AluRRRShift {
-        alu_op: ALUOp,
-        size: OperandSize,
-        rd: WritableReg,
-        rn: Reg,
-        rm: Reg,
-        shiftop: ShiftOpAndAmt,
-    },
-    AluRRRExtend {
-        alu_op: ALUOp,
-        size: OperandSize,
-        rd: WritableReg,
-        rn: Reg,
-        rm: Reg,
-        extendop: ExtendOp,
-    },
-    BitRR {
-        op: BitOp,
-        size: OperandSize,
-        rd: WritableReg,
-        rn: Reg,
-    },
-    ULoad8 {
-        rd: WritableReg,
-        mem: AMode,
-        flags: MemFlags,
-    },
-    SLoad8 {
-        rd: WritableReg,
-        mem: AMode,
-        flags: MemFlags,
-    },
-    ULoad16 {
-        rd: WritableReg,
-        mem: AMode,
-        flags: MemFlags,
-    },
-    SLoad16 {
-        rd: WritableReg,
-        mem: AMode,
-        flags: MemFlags,
-    },
-    ULoad32 {
-        rd: WritableReg,
-        mem: AMode,
-        flags: MemFlags,
-    },
-    SLoad32 {
-        rd: WritableReg,
-        mem: AMode,
-        flags: MemFlags,
-    },
-    ULoad64 {
-        rd: WritableReg,
-        mem: AMode,
-        flags: MemFlags,
-    },
-    Store8 {
-        rd: Reg,
-        mem: AMode,
-        flags: MemFlags,
-    },
-    Store16 {
-        rd: Reg,
-        mem: AMode,
-        flags: MemFlags,
-    },
-    Store32 {
-        rd: Reg,
-        mem: AMode,
-        flags: MemFlags,
-    },
-    Store64 {
-        rd: Reg,
-        mem: AMode,
-        flags: MemFlags,
-    },
-    StoreP64 {
-        rt: Reg,
-        rt2: Reg,
-        mem: PairAMode,
-        flags: MemFlags,
-    },
-    LoadP64 {
-        rt: WritableReg,
-        rt2: WritableReg,
-        mem: PairAMode,
-        flags: MemFlags,
-    },
-    Mov64 {
-        rd: WritableReg,
-        rm: Reg,
-    },
-    Mov32 {
-        rd: WritableReg,
-        rm: Reg,
-    },
-    MovZ {
-        rd: WritableReg,
-        imm: MoveWideConst,
-        size: OperandSize,
-    },
-    MovN {
-        rd: WritableReg,
-        imm: MoveWideConst,
-        size: OperandSize,
-    },
-    MovK {
-        rd: WritableReg,
-        imm: MoveWideConst,
-        size: OperandSize,
-    },
-    Extend {
-        rd: WritableReg,
-        rn: Reg,
-        signed: bool,
-        from_bits: u8,
-        to_bits: u8,
-    },
-    CSel {
-        rd: WritableReg,
-        cond: Cond,
-        rn: Reg,
-        rm: Reg,
-    },
-    CSet {
-        rd: WritableReg,
-        cond: Cond,
-    },
-    CSetm {
-        rd: WritableReg,
-        cond: Cond,
-    },
-    CCmpImm {
-        size: OperandSize,
-        rn: Reg,
-        imm: UImm5,
-        nzcv: NZCV,
-        cond: Cond,
-    },
-    AtomicRMWLoop {
-        ty: Type,
-        op: AtomicRmwOp,
-    },
-    AtomicRMW {
-        op: AtomicRMWOp,
-        rs: Reg,
-        rt: WritableReg,
-        rn: Reg,
-        ty: Type,
-    },
-    AtomicCAS {
-        rs: WritableReg,
-        rt: Reg,
-        rn: Reg,
-        ty: Type,
-    },
-    AtomicCASLoop {
-        ty: Type,
-    },
-    LoadAcquire {
-        access_ty: Type,
-        rt: WritableReg,
-        rn: Reg,
-    },
-    StoreRelease {
-        access_ty: Type,
-        rt: Reg,
-        rn: Reg,
-    },
-    Fence,
-    FpuMove64 {
-        rd: WritableReg,
-        rn: Reg,
-    },
-    FpuMove128 {
-        rd: WritableReg,
-        rn: Reg,
-    },
-    FpuMoveFromVec {
-        rd: WritableReg,
-        rn: Reg,
-        idx: u8,
-        size: VectorSize,
-    },
-    FpuExtend {
-        rd: WritableReg,
-        rn: Reg,
-        size: ScalarSize,
-    },
-    FpuRR {
-        fpu_op: FPUOp1,
-        rd: WritableReg,
-        rn: Reg,
-    },
-    FpuRRR {
-        fpu_op: FPUOp2,
-        rd: WritableReg,
-        rn: Reg,
-        rm: Reg,
-    },
-    FpuRRI {
-        fpu_op: FPUOpRI,
-        rd: WritableReg,
-        rn: Reg,
-    },
-    FpuRRRR {
-        fpu_op: FPUOp3,
-        rd: WritableReg,
-        rn: Reg,
-        rm: Reg,
-        ra: Reg,
-    },
-    FpuCmp32 {
-        rn: Reg,
-        rm: Reg,
-    },
-    FpuCmp64 {
-        rn: Reg,
-        rm: Reg,
-    },
-    FpuLoad32 {
-        rd: WritableReg,
-        mem: AMode,
-        flags: MemFlags,
-    },
-    FpuStore32 {
-        rd: Reg,
-        mem: AMode,
-        flags: MemFlags,
-    },
-    FpuLoad64 {
-        rd: WritableReg,
-        mem: AMode,
-        flags: MemFlags,
-    },
-    FpuStore64 {
-        rd: Reg,
-        mem: AMode,
-        flags: MemFlags,
-    },
-    FpuLoad128 {
-        rd: WritableReg,
-        mem: AMode,
-        flags: MemFlags,
-    },
-    FpuStore128 {
-        rd: Reg,
-        mem: AMode,
-        flags: MemFlags,
-    },
-    FpuLoadP64 {
-        rt: WritableReg,
-        rt2: WritableReg,
-        mem: PairAMode,
-        flags: MemFlags,
-    },
-    FpuStoreP64 {
-        rt: Reg,
-        rt2: Reg,
-        mem: PairAMode,
-        flags: MemFlags,
-    },
-    FpuLoadP128 {
-        rt: WritableReg,
-        rt2: WritableReg,
-        mem: PairAMode,
-        flags: MemFlags,
-    },
-    FpuStoreP128 {
-        rt: Reg,
-        rt2: Reg,
-        mem: PairAMode,
-        flags: MemFlags,
-    },
-    LoadFpuConst64 {
-        rd: WritableReg,
-        const_data: u64,
-    },
-    LoadFpuConst128 {
-        rd: WritableReg,
-        const_data: u128,
-    },
-    FpuToInt {
-        op: FpuToIntOp,
-        rd: WritableReg,
-        rn: Reg,
-    },
-    IntToFpu {
-        op: IntToFpuOp,
-        rd: WritableReg,
-        rn: Reg,
-    },
-    FpuCSel32 {
-        rd: WritableReg,
-        rn: Reg,
-        rm: Reg,
-        cond: Cond,
-    },
-    FpuCSel64 {
-        rd: WritableReg,
-        rn: Reg,
-        rm: Reg,
-        cond: Cond,
-    },
-    FpuRound {
-        op: FpuRoundMode,
-        rd: WritableReg,
-        rn: Reg,
-    },
-    MovToFpu {
-        rd: WritableReg,
-        rn: Reg,
-        size: ScalarSize,
-    },
-    FpuMoveFPImm {
-        rd: WritableReg,
-        imm: ASIMDFPModImm,
-        size: ScalarSize,
-    },
-    MovToVec {
-        rd: WritableReg,
-        rn: Reg,
-        idx: u8,
-        size: VectorSize,
-    },
-    MovFromVec {
-        rd: WritableReg,
-        rn: Reg,
-        idx: u8,
-        size: VectorSize,
-    },
-    MovFromVecSigned {
-        rd: WritableReg,
-        rn: Reg,
-        idx: u8,
-        size: VectorSize,
-        scalar_size: OperandSize,
-    },
-    VecDup {
-        rd: WritableReg,
-        rn: Reg,
-        size: VectorSize,
-    },
-    VecDupFromFpu {
-        rd: WritableReg,
-        rn: Reg,
-        size: VectorSize,
-    },
-    VecDupFPImm {
-        rd: WritableReg,
-        imm: ASIMDFPModImm,
-        size: VectorSize,
-    },
-    VecDupImm {
-        rd: WritableReg,
-        imm: ASIMDMovModImm,
-        invert: bool,
-        size: VectorSize,
-    },
-    VecExtend {
-        t: VecExtendOp,
-        rd: WritableReg,
-        rn: Reg,
-        high_half: bool,
-    },
-    VecMovElement {
-        rd: WritableReg,
-        rn: Reg,
-        dest_idx: u8,
-        src_idx: u8,
-        size: VectorSize,
-    },
-    VecRRLong {
-        op: VecRRLongOp,
-        rd: WritableReg,
-        rn: Reg,
-        high_half: bool,
-    },
-    VecRRNarrow {
-        op: VecRRNarrowOp,
-        rd: WritableReg,
-        rn: Reg,
-        high_half: bool,
-    },
-    VecRRPair {
-        op: VecPairOp,
-        rd: WritableReg,
-        rn: Reg,
-    },
-    VecRRRLong {
-        alu_op: VecRRRLongOp,
-        rd: WritableReg,
-        rn: Reg,
-        rm: Reg,
-        high_half: bool,
-    },
-    VecRRPairLong {
-        op: VecRRPairLongOp,
-        rd: WritableReg,
-        rn: Reg,
-    },
-    VecRRR {
-        alu_op: VecALUOp,
-        rd: WritableReg,
-        rn: Reg,
-        rm: Reg,
-        size: VectorSize,
-    },
-    VecMisc {
-        op: VecMisc2,
-        rd: WritableReg,
-        rn: Reg,
-        size: VectorSize,
-    },
-    VecLanes {
-        op: VecLanesOp,
-        rd: WritableReg,
-        rn: Reg,
-        size: VectorSize,
-    },
-    VecShiftImm {
-        op: VecShiftImmOp,
-        rd: WritableReg,
-        rn: Reg,
-        size: VectorSize,
-        imm: u8,
-    },
-    VecExtract {
-        rd: WritableReg,
-        rn: Reg,
-        rm: Reg,
-        imm4: u8,
-    },
-    VecTbl {
-        rd: WritableReg,
-        rn: Reg,
-        rm: Reg,
-        is_extension: bool,
-    },
-    VecTbl2 {
-        rd: WritableReg,
-        rn: Reg,
-        rn2: Reg,
-        rm: Reg,
-        is_extension: bool,
-    },
-    VecLoadReplicate {
-        rd: WritableReg,
-        rn: Reg,
-        size: VectorSize,
-    },
-    VecCSel {
-        rd: WritableReg,
-        rn: Reg,
-        rm: Reg,
-        cond: Cond,
-    },
-    MovToNZCV {
-        rn: Reg,
-    },
-    MovFromNZCV {
-        rd: WritableReg,
-    },
-    Call {
-        info: BoxCallInfo,
-    },
-    CallInd {
-        info: BoxCallIndInfo,
-    },
-    Ret,
-    EpiloguePlaceholder,
-    Jump {
-        dest: BranchTarget,
-    },
-    CondBr {
-        taken: BranchTarget,
-        not_taken: BranchTarget,
-        kind: CondBrKind,
-    },
-    TrapIf {
-        kind: CondBrKind,
-        trap_code: TrapCode,
-    },
-    IndirectBr {
-        rn: Reg,
-        targets: VecMachLabel,
-    },
-    Brk,
-    Udf {
-        trap_code: TrapCode,
-    },
-    Adr {
-        rd: WritableReg,
-        off: i32,
-    },
-    Word4 {
-        data: u32,
-    },
-    Word8 {
-        data: u64,
-    },
-    JTSequence {
-        info: BoxJTSequenceInfo,
-        ridx: Reg,
-        rtmp1: WritableReg,
-        rtmp2: WritableReg,
-    },
-    LoadExtName {
-        rd: WritableReg,
-        name: BoxExternalName,
-        offset: i64,
-    },
-    LoadAddr {
-        rd: WritableReg,
-        mem: AMode,
-    },
-    VirtualSPOffsetAdj {
-        offset: i64,
-    },
-    EmitIsland {
-        needed_space: CodeOffset,
-    },
-    ElfTlsGetAddr {
-        symbol: ExternalName,
-    },
-    ValueLabelMarker {
-        reg: Reg,
-        label: ValueLabel,
-    },
-    Unwind {
-        inst: UnwindInst,
-    },
-}
-
-/// Internal type ALUOp: defined at src/isa/aarch64/inst.isle line 796.
-#[derive(Copy, Clone, PartialEq, Eq, Debug)]
-pub enum ALUOp {
-    Add,
-    Sub,
-    Orr,
-    OrrNot,
-    And,
-    AndS,
-    AndNot,
-    Eor,
-    EorNot,
-    AddS,
-    SubS,
-    SMulH,
-    UMulH,
-    SDiv,
-    UDiv,
-    RotR,
-    Lsr,
-    Asr,
-    Lsl,
-    Adc,
-    AdcS,
-    Sbc,
-    SbcS,
-}
-
-/// Internal type ALUOp3: defined at src/isa/aarch64/inst.isle line 834.
-#[derive(Copy, Clone, PartialEq, Eq, Debug)]
-pub enum ALUOp3 {
-    MAdd32,
-    MAdd64,
-    MSub32,
-    MSub64,
-}
-
-/// Internal type BitOp: defined at src/isa/aarch64/inst.isle line 877.
-#[derive(Copy, Clone, PartialEq, Eq, Debug)]
-pub enum BitOp {
-    RBit,
-    Clz,
-    Cls,
-}
-
-/// Internal type FPUOp1: defined at src/isa/aarch64/inst.isle line 944.
-#[derive(Copy, Clone, PartialEq, Eq, Debug)]
-pub enum FPUOp1 {
-    Abs32,
-    Abs64,
-    Neg32,
-    Neg64,
-    Sqrt32,
-    Sqrt64,
-    Cvt32To64,
-    Cvt64To32,
-}
-
-/// Internal type FPUOp2: defined at src/isa/aarch64/inst.isle line 957.
-#[derive(Copy, Clone, PartialEq, Eq, Debug)]
-pub enum FPUOp2 {
-    Add32,
-    Add64,
-    Sub32,
-    Sub64,
-    Mul32,
-    Mul64,
-    Div32,
-    Div64,
-    Max32,
-    Max64,
-    Min32,
-    Min64,
-    Sqadd64,
-    Uqadd64,
-    Sqsub64,
-    Uqsub64,
-}
-
-/// Internal type FPUOp3: defined at src/isa/aarch64/inst.isle line 982.
-#[derive(Copy, Clone, PartialEq, Eq, Debug)]
-pub enum FPUOp3 {
-    MAdd32,
-    MAdd64,
-}
-
-/// Internal type FpuToIntOp: defined at src/isa/aarch64/inst.isle line 989.
-#[derive(Copy, Clone, PartialEq, Eq, Debug)]
-pub enum FpuToIntOp {
-    F32ToU32,
-    F32ToI32,
-    F32ToU64,
-    F32ToI64,
-    F64ToU32,
-    F64ToI32,
-    F64ToU64,
-    F64ToI64,
-}
-
-/// Internal type IntToFpuOp: defined at src/isa/aarch64/inst.isle line 1002.
-#[derive(Copy, Clone, PartialEq, Eq, Debug)]
-pub enum IntToFpuOp {
-    U32ToF32,
-    I32ToF32,
-    U32ToF64,
-    I32ToF64,
-    U64ToF32,
-    I64ToF32,
-    U64ToF64,
-    I64ToF64,
-}
-
-/// Internal type FpuRoundMode: defined at src/isa/aarch64/inst.isle line 1016.
-#[derive(Copy, Clone, PartialEq, Eq, Debug)]
-pub enum FpuRoundMode {
-    Minus32,
-    Minus64,
-    Plus32,
-    Plus64,
-    Zero32,
-    Zero64,
-    Nearest32,
-    Nearest64,
-}
-
-/// Internal type VecExtendOp: defined at src/isa/aarch64/inst.isle line 1029.
-#[derive(Copy, Clone, PartialEq, Eq, Debug)]
-pub enum VecExtendOp {
-    Sxtl8,
-    Sxtl16,
-    Sxtl32,
-    Uxtl8,
-    Uxtl16,
-    Uxtl32,
-}
-
-/// Internal type VecALUOp: defined at src/isa/aarch64/inst.isle line 1046.
-#[derive(Copy, Clone, PartialEq, Eq, Debug)]
-pub enum VecALUOp {
-    Sqadd,
-    Uqadd,
-    Sqsub,
-    Uqsub,
-    Cmeq,
-    Cmge,
-    Cmgt,
-    Cmhs,
-    Cmhi,
-    Fcmeq,
-    Fcmgt,
-    Fcmge,
-    And,
-    Bic,
-    Orr,
-    Eor,
-    Bsl,
-    Umaxp,
-    Add,
-    Sub,
-    Mul,
-    Sshl,
-    Ushl,
-    Umin,
-    Smin,
-    Umax,
-    Smax,
-    Urhadd,
-    Fadd,
-    Fsub,
-    Fdiv,
-    Fmax,
-    Fmin,
-    Fmul,
-    Addp,
-    Zip1,
-    Sqrdmulh,
-}
-
-/// Internal type VecMisc2: defined at src/isa/aarch64/inst.isle line 1125.
-#[derive(Copy, Clone, PartialEq, Eq, Debug)]
-pub enum VecMisc2 {
-    Not,
-    Neg,
-    Abs,
-    Fabs,
-    Fneg,
-    Fsqrt,
-    Rev64,
-    Fcvtzs,
-    Fcvtzu,
-    Scvtf,
-    Ucvtf,
-    Frintn,
-    Frintz,
-    Frintm,
-    Frintp,
-    Cnt,
-    Cmeq0,
-}
-
-/// Internal type VecRRLongOp: defined at src/isa/aarch64/inst.isle line 1164.
-#[derive(Copy, Clone, PartialEq, Eq, Debug)]
-pub enum VecRRLongOp {
-    Fcvtl16,
-    Fcvtl32,
-    Shll8,
-    Shll16,
-    Shll32,
-}
-
-/// Internal type VecRRNarrowOp: defined at src/isa/aarch64/inst.isle line 1179.
-#[derive(Copy, Clone, PartialEq, Eq, Debug)]
-pub enum VecRRNarrowOp {
-    Xtn16,
-    Xtn32,
-    Xtn64,
-    Sqxtn16,
-    Sqxtn32,
-    Sqxtn64,
-    Sqxtun16,
-    Sqxtun32,
-    Sqxtun64,
-    Uqxtn16,
-    Uqxtn32,
-    Uqxtn64,
-    Fcvtn32,
-    Fcvtn64,
-}
-
-/// Internal type VecRRRLongOp: defined at src/isa/aarch64/inst.isle line 1211.
-#[derive(Copy, Clone, PartialEq, Eq, Debug)]
-pub enum VecRRRLongOp {
-    Smull8,
-    Smull16,
-    Smull32,
-    Umull8,
-    Umull16,
-    Umull32,
-    Umlal8,
-    Umlal16,
-    Umlal32,
-}
-
-/// Internal type VecPairOp: defined at src/isa/aarch64/inst.isle line 1228.
-#[derive(Copy, Clone, PartialEq, Eq, Debug)]
-pub enum VecPairOp {
-    Addp,
-}
-
-/// Internal type VecRRPairLongOp: defined at src/isa/aarch64/inst.isle line 1236.
-#[derive(Copy, Clone, PartialEq, Eq, Debug)]
-pub enum VecRRPairLongOp {
-    Saddlp8,
-    Saddlp16,
-    Uaddlp8,
-    Uaddlp16,
-}
-
-/// Internal type VecLanesOp: defined at src/isa/aarch64/inst.isle line 1247.
-#[derive(Copy, Clone, PartialEq, Eq, Debug)]
-pub enum VecLanesOp {
-    Addv,
-    Uminv,
-}
-
-/// Internal type VecShiftImmOp: defined at src/isa/aarch64/inst.isle line 1256.
-#[derive(Copy, Clone, PartialEq, Eq, Debug)]
-pub enum VecShiftImmOp {
-    Shl,
-    Ushr,
-    Sshr,
-}
-
-/// Internal type AtomicRMWOp: defined at src/isa/aarch64/inst.isle line 1267.
-#[derive(Copy, Clone, PartialEq, Eq, Debug)]
-pub enum AtomicRMWOp {
-    Add,
-    Clr,
-    Eor,
-    Set,
-    Smax,
-    Smin,
-    Umax,
-    Umin,
-}
-
-// Generated as internal constructor for term output_reg.
-pub fn constructor_output_reg<C: Context>(ctx: &mut C, arg0: Reg) -> Option<InstOutput> {
-    let pattern0_0 = arg0;
-    // Rule at src/prelude.isle line 86.
-    let expr0_0 = C::value_reg(ctx, pattern0_0);
-    let expr1_0 = C::output(ctx, expr0_0);
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term output_value.
-pub fn constructor_output_value<C: Context>(ctx: &mut C, arg0: Value) -> Option<InstOutput> {
-    let pattern0_0 = arg0;
-    // Rule at src/prelude.isle line 90.
-    let expr0_0 = C::put_in_regs(ctx, pattern0_0);
-    let expr1_0 = C::output(ctx, expr0_0);
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term temp_reg.
-pub fn constructor_temp_reg<C: Context>(ctx: &mut C, arg0: Type) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    // Rule at src/prelude.isle line 110.
-    let expr0_0 = C::temp_writable_reg(ctx, pattern0_0);
-    let expr1_0 = C::writable_reg_to_reg(ctx, expr0_0);
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term lo_reg.
-pub fn constructor_lo_reg<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    // Rule at src/prelude.isle line 145.
-    let expr0_0 = C::put_in_regs(ctx, pattern0_0);
-    let expr1_0: usize = 0;
-    let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term side_effect.
-pub fn constructor_side_effect<C: Context>(
-    ctx: &mut C,
-    arg0: &SideEffectNoResult,
-) -> Option<InstOutput> {
-    let pattern0_0 = arg0;
-    if let &SideEffectNoResult::Inst {
-        inst: ref pattern1_0,
-    } = pattern0_0
-    {
-        // Rule at src/prelude.isle line 398.
-        let expr0_0 = C::emit(ctx, pattern1_0);
-        let expr1_0 = C::output_none(ctx);
-        return Some(expr1_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term safepoint.
-pub fn constructor_safepoint<C: Context>(
-    ctx: &mut C,
-    arg0: &SideEffectNoResult,
-) -> Option<InstOutput> {
-    let pattern0_0 = arg0;
-    if let &SideEffectNoResult::Inst {
-        inst: ref pattern1_0,
-    } = pattern0_0
-    {
-        // Rule at src/prelude.isle line 404.
-        let expr0_0 = C::emit_safepoint(ctx, pattern1_0);
-        let expr1_0 = C::output_none(ctx);
-        return Some(expr1_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term produces_flags_get_reg.
-pub fn constructor_produces_flags_get_reg<C: Context>(
-    ctx: &mut C,
-    arg0: &ProducesFlags,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    if let &ProducesFlags::ProducesFlagsReturnsReg {
-        inst: ref pattern1_0,
-        result: pattern1_1,
-    } = pattern0_0
-    {
-        // Rule at src/prelude.isle line 442.
-        return Some(pattern1_1);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term produces_flags_ignore.
-pub fn constructor_produces_flags_ignore<C: Context>(
-    ctx: &mut C,
-    arg0: &ProducesFlags,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    match pattern0_0 {
-        &ProducesFlags::ProducesFlagsReturnsReg {
-            inst: ref pattern1_0,
-            result: pattern1_1,
-        } => {
-            // Rule at src/prelude.isle line 447.
-            let expr0_0 = ProducesFlags::ProducesFlagsSideEffect {
-                inst: pattern1_0.clone(),
-            };
-            return Some(expr0_0);
-        }
-        &ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
-            inst: ref pattern1_0,
-            result: pattern1_1,
-        } => {
-            // Rule at src/prelude.isle line 449.
-            let expr0_0 = ProducesFlags::ProducesFlagsSideEffect {
-                inst: pattern1_0.clone(),
-            };
-            return Some(expr0_0);
-        }
-        _ => {}
-    }
-    return None;
-}
-
-// Generated as internal constructor for term consumes_flags_concat.
-pub fn constructor_consumes_flags_concat<C: Context>(
-    ctx: &mut C,
-    arg0: &ConsumesFlags,
-    arg1: &ConsumesFlags,
-) -> Option<ConsumesFlags> {
-    let pattern0_0 = arg0;
-    if let &ConsumesFlags::ConsumesFlagsReturnsReg {
-        inst: ref pattern1_0,
-        result: pattern1_1,
-    } = pattern0_0
-    {
-        let pattern2_0 = arg1;
-        if let &ConsumesFlags::ConsumesFlagsReturnsReg {
-            inst: ref pattern3_0,
-            result: pattern3_1,
-        } = pattern2_0
-        {
-            // Rule at src/prelude.isle line 456.
-            let expr0_0 = C::value_regs(ctx, pattern1_1, pattern3_1);
-            let expr1_0 = ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs {
-                inst1: pattern1_0.clone(),
-                inst2: pattern3_0.clone(),
-                result: expr0_0,
-            };
-            return Some(expr1_0);
-        }
-    }
-    return None;
-}
-
-// Generated as internal constructor for term with_flags.
-pub fn constructor_with_flags<C: Context>(
-    ctx: &mut C,
-    arg0: &ProducesFlags,
-    arg1: &ConsumesFlags,
-) -> Option<ValueRegs> {
-    let pattern0_0 = arg0;
-    match pattern0_0 {
-        &ProducesFlags::ProducesFlagsSideEffect {
-            inst: ref pattern1_0,
-        } => {
-            let pattern2_0 = arg1;
-            match pattern2_0 {
-                &ConsumesFlags::ConsumesFlagsReturnsReg {
-                    inst: ref pattern3_0,
-                    result: pattern3_1,
-                } => {
-                    // Rule at src/prelude.isle line 481.
-                    let expr0_0 = C::emit(ctx, pattern1_0);
-                    let expr1_0 = C::emit(ctx, pattern3_0);
-                    let expr2_0 = C::value_reg(ctx, pattern3_1);
-                    return Some(expr2_0);
-                }
-                &ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs {
-                    inst1: ref pattern3_0,
-                    inst2: ref pattern3_1,
-                    result: pattern3_2,
-                } => {
-                    // Rule at src/prelude.isle line 487.
-                    let expr0_0 = C::emit(ctx, pattern1_0);
-                    let expr1_0 = C::emit(ctx, pattern3_0);
-                    let expr2_0 = C::emit(ctx, pattern3_1);
-                    return Some(pattern3_2);
-                }
-                &ConsumesFlags::ConsumesFlagsFourTimesReturnsValueRegs {
-                    inst1: ref pattern3_0,
-                    inst2: ref pattern3_1,
-                    inst3: ref pattern3_2,
-                    inst4: ref pattern3_3,
-                    result: pattern3_4,
-                } => {
-                    // Rule at src/prelude.isle line 499.
-                    let expr0_0 = C::emit(ctx, pattern1_0);
-                    let expr1_0 = C::emit(ctx, pattern3_0);
-                    let expr2_0 = C::emit(ctx, pattern3_1);
-                    let expr3_0 = C::emit(ctx, pattern3_2);
-                    let expr4_0 = C::emit(ctx, pattern3_3);
-                    return Some(pattern3_4);
-                }
-                _ => {}
-            }
-        }
-        &ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
-            inst: ref pattern1_0,
-            result: pattern1_1,
-        } => {
-            let pattern2_0 = arg1;
-            if let &ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
-                inst: ref pattern3_0,
-                result: pattern3_1,
-            } = pattern2_0
-            {
-                // Rule at src/prelude.isle line 475.
-                let expr0_0 = C::emit(ctx, pattern1_0);
-                let expr1_0 = C::emit(ctx, pattern3_0);
-                let expr2_0 = C::value_regs(ctx, pattern1_1, pattern3_1);
-                return Some(expr2_0);
-            }
-        }
-        _ => {}
-    }
-    return None;
-}
-
-// Generated as internal constructor for term with_flags_reg.
-pub fn constructor_with_flags_reg<C: Context>(
-    ctx: &mut C,
-    arg0: &ProducesFlags,
-    arg1: &ConsumesFlags,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/prelude.isle line 516.
-    let expr0_0 = constructor_with_flags(ctx, pattern0_0, pattern1_0)?;
-    let expr1_0: usize = 0;
-    let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term operand_size.
-pub fn constructor_operand_size<C: Context>(ctx: &mut C, arg0: Type) -> Option<OperandSize> {
-    let pattern0_0 = arg0;
-    if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
-        // Rule at src/isa/aarch64/inst.isle line 895.
-        let expr0_0 = OperandSize::Size32;
-        return Some(expr0_0);
-    }
-    if let Some(pattern1_0) = C::fits_in_64(ctx, pattern0_0) {
-        // Rule at src/isa/aarch64/inst.isle line 896.
-        let expr0_0 = OperandSize::Size64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term vector_size.
-pub fn constructor_vector_size<C: Context>(ctx: &mut C, arg0: Type) -> Option<VectorSize> {
-    let pattern0_0 = arg0;
-    if let Some((pattern1_0, pattern1_1)) = C::multi_lane(ctx, pattern0_0) {
-        if pattern1_0 == 8 {
-            if pattern1_1 == 16 {
-                // Rule at src/isa/aarch64/inst.isle line 938.
-                let expr0_0 = VectorSize::Size8x16;
-                return Some(expr0_0);
-            }
-        }
-        if pattern1_0 == 16 {
-            if pattern1_1 == 8 {
-                // Rule at src/isa/aarch64/inst.isle line 939.
-                let expr0_0 = VectorSize::Size16x8;
-                return Some(expr0_0);
-            }
-        }
-        if pattern1_0 == 32 {
-            if pattern1_1 == 4 {
-                // Rule at src/isa/aarch64/inst.isle line 940.
-                let expr0_0 = VectorSize::Size32x4;
-                return Some(expr0_0);
-            }
-        }
-        if pattern1_0 == 64 {
-            if pattern1_1 == 2 {
-                // Rule at src/isa/aarch64/inst.isle line 941.
-                let expr0_0 = VectorSize::Size64x2;
-                return Some(expr0_0);
-            }
-        }
-    }
-    return None;
-}
-
-// Generated as internal constructor for term movz.
-pub fn constructor_movz<C: Context>(
-    ctx: &mut C,
-    arg0: MoveWideConst,
-    arg1: &OperandSize,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/aarch64/inst.isle line 1363.
-    let expr0_0: Type = I64;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = MInst::MovZ {
-        rd: expr1_0,
-        imm: pattern0_0,
-        size: pattern1_0.clone(),
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term movn.
-pub fn constructor_movn<C: Context>(
-    ctx: &mut C,
-    arg0: MoveWideConst,
-    arg1: &OperandSize,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/aarch64/inst.isle line 1370.
-    let expr0_0: Type = I64;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = MInst::MovN {
-        rd: expr1_0,
-        imm: pattern0_0,
-        size: pattern1_0.clone(),
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term alu_rr_imm_logic.
-pub fn constructor_alu_rr_imm_logic<C: Context>(
-    ctx: &mut C,
-    arg0: &ALUOp,
-    arg1: Type,
-    arg2: Reg,
-    arg3: ImmLogic,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/aarch64/inst.isle line 1377.
-    let expr0_0: Type = I64;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
-    let expr3_0 = MInst::AluRRImmLogic {
-        alu_op: pattern0_0.clone(),
-        size: expr2_0,
-        rd: expr1_0,
-        rn: pattern2_0,
-        imml: pattern3_0,
-    };
-    let expr4_0 = C::emit(ctx, &expr3_0);
-    let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr5_0);
-}
-
-// Generated as internal constructor for term alu_rr_imm_shift.
-pub fn constructor_alu_rr_imm_shift<C: Context>(
-    ctx: &mut C,
-    arg0: &ALUOp,
-    arg1: Type,
-    arg2: Reg,
-    arg3: ImmShift,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/aarch64/inst.isle line 1384.
-    let expr0_0: Type = I64;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
-    let expr3_0 = MInst::AluRRImmShift {
-        alu_op: pattern0_0.clone(),
-        size: expr2_0,
-        rd: expr1_0,
-        rn: pattern2_0,
-        immshift: pattern3_0,
-    };
-    let expr4_0 = C::emit(ctx, &expr3_0);
-    let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr5_0);
-}
-
-// Generated as internal constructor for term alu_rrr.
-pub fn constructor_alu_rrr<C: Context>(
-    ctx: &mut C,
-    arg0: &ALUOp,
-    arg1: Type,
-    arg2: Reg,
-    arg3: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/aarch64/inst.isle line 1391.
-    let expr0_0: Type = I64;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
-    let expr3_0 = MInst::AluRRR {
-        alu_op: pattern0_0.clone(),
-        size: expr2_0,
-        rd: expr1_0,
-        rn: pattern2_0,
-        rm: pattern3_0,
-    };
-    let expr4_0 = C::emit(ctx, &expr3_0);
-    let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr5_0);
-}
-
-// Generated as internal constructor for term vec_rrr.
-pub fn constructor_vec_rrr<C: Context>(
-    ctx: &mut C,
-    arg0: &VecALUOp,
-    arg1: Reg,
-    arg2: Reg,
-    arg3: &VectorSize,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/aarch64/inst.isle line 1398.
-    let expr0_0: Type = I8X16;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = MInst::VecRRR {
-        alu_op: pattern0_0.clone(),
-        rd: expr1_0,
-        rn: pattern1_0,
-        rm: pattern2_0,
-        size: pattern3_0.clone(),
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term vec_lanes.
-pub fn constructor_vec_lanes<C: Context>(
-    ctx: &mut C,
-    arg0: &VecLanesOp,
-    arg1: Reg,
-    arg2: &VectorSize,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1405.
-    let expr0_0: Type = I8X16;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = MInst::VecLanes {
-        op: pattern0_0.clone(),
-        rd: expr1_0,
-        rn: pattern1_0,
-        size: pattern2_0.clone(),
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term vec_dup.
-pub fn constructor_vec_dup<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/aarch64/inst.isle line 1412.
-    let expr0_0: Type = I8X16;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = MInst::VecDup {
-        rd: expr1_0,
-        rn: pattern0_0,
-        size: pattern1_0.clone(),
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term alu_rr_imm12.
-pub fn constructor_alu_rr_imm12<C: Context>(
-    ctx: &mut C,
-    arg0: &ALUOp,
-    arg1: Type,
-    arg2: Reg,
-    arg3: Imm12,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/aarch64/inst.isle line 1419.
-    let expr0_0: Type = I64;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
-    let expr3_0 = MInst::AluRRImm12 {
-        alu_op: pattern0_0.clone(),
-        size: expr2_0,
-        rd: expr1_0,
-        rn: pattern2_0,
-        imm12: pattern3_0,
-    };
-    let expr4_0 = C::emit(ctx, &expr3_0);
-    let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr5_0);
-}
-
-// Generated as internal constructor for term alu_rrr_shift.
-pub fn constructor_alu_rrr_shift<C: Context>(
-    ctx: &mut C,
-    arg0: &ALUOp,
-    arg1: Type,
-    arg2: Reg,
-    arg3: Reg,
-    arg4: ShiftOpAndAmt,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    let pattern4_0 = arg4;
-    // Rule at src/isa/aarch64/inst.isle line 1426.
-    let expr0_0: Type = I64;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
-    let expr3_0 = MInst::AluRRRShift {
-        alu_op: pattern0_0.clone(),
-        size: expr2_0,
-        rd: expr1_0,
-        rn: pattern2_0,
-        rm: pattern3_0,
-        shiftop: pattern4_0,
-    };
-    let expr4_0 = C::emit(ctx, &expr3_0);
-    let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr5_0);
-}
-
-// Generated as internal constructor for term alu_rrr_extend.
-pub fn constructor_alu_rrr_extend<C: Context>(
-    ctx: &mut C,
-    arg0: &ALUOp,
-    arg1: Type,
-    arg2: Reg,
-    arg3: Reg,
-    arg4: &ExtendOp,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    let pattern4_0 = arg4;
-    // Rule at src/isa/aarch64/inst.isle line 1433.
-    let expr0_0: Type = I64;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
-    let expr3_0 = MInst::AluRRRExtend {
-        alu_op: pattern0_0.clone(),
-        size: expr2_0,
-        rd: expr1_0,
-        rn: pattern2_0,
-        rm: pattern3_0,
-        extendop: pattern4_0.clone(),
-    };
-    let expr4_0 = C::emit(ctx, &expr3_0);
-    let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr5_0);
-}
-
-// Generated as internal constructor for term alu_rr_extend_reg.
-pub fn constructor_alu_rr_extend_reg<C: Context>(
-    ctx: &mut C,
-    arg0: &ALUOp,
-    arg1: Type,
-    arg2: Reg,
-    arg3: &ExtendedValue,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/aarch64/inst.isle line 1441.
-    let expr0_0 = C::put_extended_in_reg(ctx, pattern3_0);
-    let expr1_0 = C::get_extended_op(ctx, pattern3_0);
-    let expr2_0 =
-        constructor_alu_rrr_extend(ctx, pattern0_0, pattern1_0, pattern2_0, expr0_0, &expr1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term alu_rrrr.
-pub fn constructor_alu_rrrr<C: Context>(
-    ctx: &mut C,
-    arg0: &ALUOp3,
-    arg1: Reg,
-    arg2: Reg,
-    arg3: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/aarch64/inst.isle line 1448.
-    let expr0_0: Type = I64;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = MInst::AluRRRR {
-        alu_op: pattern0_0.clone(),
-        rd: expr1_0,
-        rn: pattern1_0,
-        rm: pattern2_0,
-        ra: pattern3_0,
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term bit_rr.
-pub fn constructor_bit_rr<C: Context>(
-    ctx: &mut C,
-    arg0: &BitOp,
-    arg1: Type,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1455.
-    let expr0_0: Type = I64;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
-    let expr3_0 = MInst::BitRR {
-        op: pattern0_0.clone(),
-        size: expr2_0,
-        rd: expr1_0,
-        rn: pattern2_0,
-    };
-    let expr4_0 = C::emit(ctx, &expr3_0);
-    let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr5_0);
-}
-
-// Generated as internal constructor for term add_with_flags_paired.
-pub fn constructor_add_with_flags_paired<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1462.
-    let expr0_0: Type = I64;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = ALUOp::AddS;
-    let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
-    let expr4_0 = MInst::AluRRR {
-        alu_op: expr2_0,
-        size: expr3_0,
-        rd: expr1_0,
-        rn: pattern1_0,
-        rm: pattern2_0,
-    };
-    let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    let expr6_0 = ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
-        inst: expr4_0,
-        result: expr5_0,
-    };
-    return Some(expr6_0);
-}
-
-// Generated as internal constructor for term adc_paired.
-pub fn constructor_adc_paired<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<ConsumesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1470.
-    let expr0_0: Type = I64;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = ALUOp::Adc;
-    let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
-    let expr4_0 = MInst::AluRRR {
-        alu_op: expr2_0,
-        size: expr3_0,
-        rd: expr1_0,
-        rn: pattern1_0,
-        rm: pattern2_0,
-    };
-    let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    let expr6_0 = ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
-        inst: expr4_0,
-        result: expr5_0,
-    };
-    return Some(expr6_0);
-}
-
-// Generated as internal constructor for term sub_with_flags_paired.
-pub fn constructor_sub_with_flags_paired<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1478.
-    let expr0_0: Type = I64;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = ALUOp::SubS;
-    let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
-    let expr4_0 = MInst::AluRRR {
-        alu_op: expr2_0,
-        size: expr3_0,
-        rd: expr1_0,
-        rn: pattern1_0,
-        rm: pattern2_0,
-    };
-    let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    let expr6_0 = ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
-        inst: expr4_0,
-        result: expr5_0,
-    };
-    return Some(expr6_0);
-}
-
-// Generated as internal constructor for term cmp64_imm.
-pub fn constructor_cmp64_imm<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: Imm12,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/aarch64/inst.isle line 1485.
-    let expr0_0 = ALUOp::SubS;
-    let expr1_0 = OperandSize::Size64;
-    let expr2_0 = C::writable_zero_reg(ctx);
-    let expr3_0 = MInst::AluRRImm12 {
-        alu_op: expr0_0,
-        size: expr1_0,
-        rd: expr2_0,
-        rn: pattern0_0,
-        imm12: pattern1_0,
-    };
-    let expr4_0 = ProducesFlags::ProducesFlagsSideEffect { inst: expr3_0 };
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term sbc_paired.
-pub fn constructor_sbc_paired<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<ConsumesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1492.
-    let expr0_0: Type = I64;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = ALUOp::Sbc;
-    let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
-    let expr4_0 = MInst::AluRRR {
-        alu_op: expr2_0,
-        size: expr3_0,
-        rd: expr1_0,
-        rn: pattern1_0,
-        rm: pattern2_0,
-    };
-    let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    let expr6_0 = ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
-        inst: expr4_0,
-        result: expr5_0,
-    };
-    return Some(expr6_0);
-}
-
-// Generated as internal constructor for term vec_misc.
-pub fn constructor_vec_misc<C: Context>(
-    ctx: &mut C,
-    arg0: &VecMisc2,
-    arg1: Reg,
-    arg2: &VectorSize,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1500.
-    let expr0_0: Type = I8X16;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = MInst::VecMisc {
-        op: pattern0_0.clone(),
-        rd: expr1_0,
-        rn: pattern1_0,
-        size: pattern2_0.clone(),
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term vec_rrr_long.
-pub fn constructor_vec_rrr_long<C: Context>(
-    ctx: &mut C,
-    arg0: &VecRRRLongOp,
-    arg1: Reg,
-    arg2: Reg,
-    arg3: bool,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/aarch64/inst.isle line 1507.
-    let expr0_0: Type = I8X16;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = MInst::VecRRRLong {
-        alu_op: pattern0_0.clone(),
-        rd: expr1_0,
-        rn: pattern1_0,
-        rm: pattern2_0,
-        high_half: pattern3_0,
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term vec_rrrr_long.
-pub fn constructor_vec_rrrr_long<C: Context>(
-    ctx: &mut C,
-    arg0: &VecRRRLongOp,
-    arg1: Reg,
-    arg2: Reg,
-    arg3: Reg,
-    arg4: bool,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    let pattern4_0 = arg4;
-    // Rule at src/isa/aarch64/inst.isle line 1517.
-    let expr0_0: Type = I8X16;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = MInst::FpuMove128 {
-        rd: expr1_0,
-        rn: pattern1_0,
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = MInst::VecRRRLong {
-        alu_op: pattern0_0.clone(),
-        rd: expr1_0,
-        rn: pattern2_0,
-        rm: pattern3_0,
-        high_half: pattern4_0,
-    };
-    let expr5_0 = C::emit(ctx, &expr4_0);
-    let expr6_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr6_0);
-}
-
-// Generated as internal constructor for term vec_rr_narrow.
-pub fn constructor_vec_rr_narrow<C: Context>(
-    ctx: &mut C,
-    arg0: &VecRRNarrowOp,
-    arg1: Reg,
-    arg2: bool,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1525.
-    let expr0_0: Type = I8X16;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = MInst::VecRRNarrow {
-        op: pattern0_0.clone(),
-        rd: expr1_0,
-        rn: pattern1_0,
-        high_half: pattern2_0,
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term vec_rr_long.
-pub fn constructor_vec_rr_long<C: Context>(
-    ctx: &mut C,
-    arg0: &VecRRLongOp,
-    arg1: Reg,
-    arg2: bool,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1532.
-    let expr0_0: Type = I8X16;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = MInst::VecRRLong {
-        op: pattern0_0.clone(),
-        rd: expr1_0,
-        rn: pattern1_0,
-        high_half: pattern2_0,
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term mov_to_fpu.
-pub fn constructor_mov_to_fpu<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: &ScalarSize,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/aarch64/inst.isle line 1539.
-    let expr0_0: Type = I8X16;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = MInst::MovToFpu {
-        rd: expr1_0,
-        rn: pattern0_0,
-        size: pattern1_0.clone(),
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term mov_to_vec.
-pub fn constructor_mov_to_vec<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: Reg,
-    arg2: u8,
-    arg3: &VectorSize,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/aarch64/inst.isle line 1546.
-    let expr0_0: Type = I8X16;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = MInst::FpuMove128 {
-        rd: expr1_0,
-        rn: pattern0_0,
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = MInst::MovToVec {
-        rd: expr1_0,
-        rn: pattern1_0,
-        idx: pattern2_0,
-        size: pattern3_0.clone(),
-    };
-    let expr5_0 = C::emit(ctx, &expr4_0);
-    let expr6_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr6_0);
-}
-
-// Generated as internal constructor for term mov_from_vec.
-pub fn constructor_mov_from_vec<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: u8,
-    arg2: &VectorSize,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1554.
-    let expr0_0: Type = I64;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = MInst::MovFromVec {
-        rd: expr1_0,
-        rn: pattern0_0,
-        idx: pattern1_0,
-        size: pattern2_0.clone(),
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term mov_from_vec_signed.
-pub fn constructor_mov_from_vec_signed<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: u8,
-    arg2: &VectorSize,
-    arg3: &OperandSize,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/aarch64/inst.isle line 1561.
-    let expr0_0: Type = I64;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = MInst::MovFromVecSigned {
-        rd: expr1_0,
-        rn: pattern0_0,
-        idx: pattern1_0,
-        size: pattern2_0.clone(),
-        scalar_size: pattern3_0.clone(),
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term extend.
-pub fn constructor_extend<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: bool,
-    arg2: u8,
-    arg3: u8,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/aarch64/inst.isle line 1568.
-    let expr0_0: Type = I64;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = MInst::Extend {
-        rd: expr1_0,
-        rn: pattern0_0,
-        signed: pattern1_0,
-        from_bits: pattern2_0,
-        to_bits: pattern3_0,
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term load_acquire.
-pub fn constructor_load_acquire<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/aarch64/inst.isle line 1575.
-    let expr0_0: Type = I64;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = MInst::LoadAcquire {
-        access_ty: pattern0_0,
-        rt: expr1_0,
-        rn: pattern1_0,
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term tst_imm.
-pub fn constructor_tst_imm<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: ImmLogic,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1585.
-    let expr0_0 = ALUOp::AndS;
-    let expr1_0 = constructor_operand_size(ctx, pattern0_0)?;
-    let expr2_0 = C::writable_zero_reg(ctx);
-    let expr3_0 = MInst::AluRRImmLogic {
-        alu_op: expr0_0,
-        size: expr1_0,
-        rd: expr2_0,
-        rn: pattern1_0,
-        imml: pattern2_0,
-    };
-    let expr4_0 = ProducesFlags::ProducesFlagsSideEffect { inst: expr3_0 };
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term csel.
-pub fn constructor_csel<C: Context>(
-    ctx: &mut C,
-    arg0: &Cond,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<ConsumesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1599.
-    let expr0_0: Type = I64;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = MInst::CSel {
-        rd: expr1_0,
-        cond: pattern0_0.clone(),
-        rn: pattern1_0,
-        rm: pattern2_0,
-    };
-    let expr3_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    let expr4_0 = ConsumesFlags::ConsumesFlagsReturnsReg {
-        inst: expr2_0,
-        result: expr3_0,
-    };
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term add.
-pub fn constructor_add<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1608.
-    let expr0_0 = ALUOp::Add;
-    let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term add_imm.
-pub fn constructor_add_imm<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Imm12,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1611.
-    let expr0_0 = ALUOp::Add;
-    let expr1_0 = constructor_alu_rr_imm12(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term add_extend.
-pub fn constructor_add_extend<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: &ExtendedValue,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1614.
-    let expr0_0 = ALUOp::Add;
-    let expr1_0 = constructor_alu_rr_extend_reg(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term add_shift.
-pub fn constructor_add_shift<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-    arg3: ShiftOpAndAmt,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/aarch64/inst.isle line 1617.
-    let expr0_0 = ALUOp::Add;
-    let expr1_0 = constructor_alu_rrr_shift(
-        ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
-    )?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term add_vec.
-pub fn constructor_add_vec<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: Reg,
-    arg2: &VectorSize,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1620.
-    let expr0_0 = VecALUOp::Add;
-    let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term sub.
-pub fn constructor_sub<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1625.
-    let expr0_0 = ALUOp::Sub;
-    let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term sub_imm.
-pub fn constructor_sub_imm<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Imm12,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1628.
-    let expr0_0 = ALUOp::Sub;
-    let expr1_0 = constructor_alu_rr_imm12(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term sub_extend.
-pub fn constructor_sub_extend<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: &ExtendedValue,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1631.
-    let expr0_0 = ALUOp::Sub;
-    let expr1_0 = constructor_alu_rr_extend_reg(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term sub_shift.
-pub fn constructor_sub_shift<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-    arg3: ShiftOpAndAmt,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/aarch64/inst.isle line 1634.
-    let expr0_0 = ALUOp::Sub;
-    let expr1_0 = constructor_alu_rrr_shift(
-        ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
-    )?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term sub_vec.
-pub fn constructor_sub_vec<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: Reg,
-    arg2: &VectorSize,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1637.
-    let expr0_0 = VecALUOp::Sub;
-    let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term madd.
-pub fn constructor_madd<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-    arg3: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I64 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/aarch64/inst.isle line 1643.
-        let expr0_0 = constructor_madd64(ctx, pattern2_0, pattern3_0, pattern4_0)?;
-        return Some(expr0_0);
-    }
-    if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/aarch64/inst.isle line 1642.
-        let expr0_0 = constructor_madd32(ctx, pattern2_0, pattern3_0, pattern4_0)?;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term madd32.
-pub fn constructor_madd32<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg, arg2: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1646.
-    let expr0_0 = ALUOp3::MAdd32;
-    let expr1_0 = constructor_alu_rrrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term madd64.
-pub fn constructor_madd64<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg, arg2: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1649.
-    let expr0_0 = ALUOp3::MAdd64;
-    let expr1_0 = constructor_alu_rrrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term msub64.
-pub fn constructor_msub64<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg, arg2: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1654.
-    let expr0_0 = ALUOp3::MSub64;
-    let expr1_0 = constructor_alu_rrrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term uqadd.
-pub fn constructor_uqadd<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: Reg,
-    arg2: &VectorSize,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1658.
-    let expr0_0 = VecALUOp::Uqadd;
-    let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term sqadd.
-pub fn constructor_sqadd<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: Reg,
-    arg2: &VectorSize,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1662.
-    let expr0_0 = VecALUOp::Sqadd;
-    let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term uqsub.
-pub fn constructor_uqsub<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: Reg,
-    arg2: &VectorSize,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1666.
-    let expr0_0 = VecALUOp::Uqsub;
-    let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term sqsub.
-pub fn constructor_sqsub<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: Reg,
-    arg2: &VectorSize,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1670.
-    let expr0_0 = VecALUOp::Sqsub;
-    let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term umulh.
-pub fn constructor_umulh<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1674.
-    let expr0_0 = ALUOp::UMulH;
-    let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term smulh.
-pub fn constructor_smulh<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1678.
-    let expr0_0 = ALUOp::SMulH;
-    let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term mul.
-pub fn constructor_mul<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: Reg,
-    arg2: &VectorSize,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1682.
-    let expr0_0 = VecALUOp::Mul;
-    let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term neg.
-pub fn constructor_neg<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/aarch64/inst.isle line 1686.
-    let expr0_0 = VecMisc2::Neg;
-    let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term rev64.
-pub fn constructor_rev64<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/aarch64/inst.isle line 1690.
-    let expr0_0 = VecMisc2::Rev64;
-    let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term xtn64.
-pub fn constructor_xtn64<C: Context>(ctx: &mut C, arg0: Reg, arg1: bool) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/aarch64/inst.isle line 1694.
-    let expr0_0 = VecRRNarrowOp::Xtn64;
-    let expr1_0 = constructor_vec_rr_narrow(ctx, &expr0_0, pattern0_0, pattern1_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term addp.
-pub fn constructor_addp<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: Reg,
-    arg2: &VectorSize,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1698.
-    let expr0_0 = VecALUOp::Addp;
-    let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term addv.
-pub fn constructor_addv<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/aarch64/inst.isle line 1702.
-    let expr0_0 = VecLanesOp::Addv;
-    let expr1_0 = constructor_vec_lanes(ctx, &expr0_0, pattern0_0, pattern1_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term shll32.
-pub fn constructor_shll32<C: Context>(ctx: &mut C, arg0: Reg, arg1: bool) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/aarch64/inst.isle line 1706.
-    let expr0_0 = VecRRLongOp::Shll32;
-    let expr1_0 = constructor_vec_rr_long(ctx, &expr0_0, pattern0_0, pattern1_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term umlal32.
-pub fn constructor_umlal32<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: Reg,
-    arg2: Reg,
-    arg3: bool,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/aarch64/inst.isle line 1710.
-    let expr0_0 = VecRRRLongOp::Umlal32;
-    let expr1_0 = constructor_vec_rrrr_long(
-        ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
-    )?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term smull8.
-pub fn constructor_smull8<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: Reg,
-    arg2: bool,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1714.
-    let expr0_0 = VecRRRLongOp::Smull8;
-    let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term umull8.
-pub fn constructor_umull8<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: Reg,
-    arg2: bool,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1718.
-    let expr0_0 = VecRRRLongOp::Umull8;
-    let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term smull16.
-pub fn constructor_smull16<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: Reg,
-    arg2: bool,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1722.
-    let expr0_0 = VecRRRLongOp::Smull16;
-    let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term umull16.
-pub fn constructor_umull16<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: Reg,
-    arg2: bool,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1726.
-    let expr0_0 = VecRRRLongOp::Umull16;
-    let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term smull32.
-pub fn constructor_smull32<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: Reg,
-    arg2: bool,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1730.
-    let expr0_0 = VecRRRLongOp::Smull32;
-    let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term umull32.
-pub fn constructor_umull32<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: Reg,
-    arg2: bool,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1734.
-    let expr0_0 = VecRRRLongOp::Umull32;
-    let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term asr.
-pub fn constructor_asr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1738.
-    let expr0_0 = ALUOp::Asr;
-    let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term asr_imm.
-pub fn constructor_asr_imm<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: ImmShift,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1741.
-    let expr0_0 = ALUOp::Asr;
-    let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term lsr.
-pub fn constructor_lsr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1745.
-    let expr0_0 = ALUOp::Lsr;
-    let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term lsr_imm.
-pub fn constructor_lsr_imm<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: ImmShift,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1748.
-    let expr0_0 = ALUOp::Lsr;
-    let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term lsl.
-pub fn constructor_lsl<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1752.
-    let expr0_0 = ALUOp::Lsl;
-    let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term lsl_imm.
-pub fn constructor_lsl_imm<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: ImmShift,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1755.
-    let expr0_0 = ALUOp::Lsl;
-    let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term a64_udiv.
-pub fn constructor_a64_udiv<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1759.
-    let expr0_0 = ALUOp::UDiv;
-    let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term a64_sdiv.
-pub fn constructor_a64_sdiv<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1763.
-    let expr0_0 = ALUOp::SDiv;
-    let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term not.
-pub fn constructor_not<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/aarch64/inst.isle line 1767.
-    let expr0_0 = VecMisc2::Not;
-    let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term orr_not.
-pub fn constructor_orr_not<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1772.
-    let expr0_0 = ALUOp::OrrNot;
-    let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term orr_not_shift.
-pub fn constructor_orr_not_shift<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-    arg3: ShiftOpAndAmt,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/aarch64/inst.isle line 1775.
-    let expr0_0 = ALUOp::OrrNot;
-    let expr1_0 = constructor_alu_rrr_shift(
-        ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
-    )?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term orr.
-pub fn constructor_orr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1780.
-    let expr0_0 = ALUOp::Orr;
-    let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term orr_imm.
-pub fn constructor_orr_imm<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: ImmLogic,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1783.
-    let expr0_0 = ALUOp::Orr;
-    let expr1_0 = constructor_alu_rr_imm_logic(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term orr_vec.
-pub fn constructor_orr_vec<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: Reg,
-    arg2: &VectorSize,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1786.
-    let expr0_0 = VecALUOp::Orr;
-    let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term and_imm.
-pub fn constructor_and_imm<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: ImmLogic,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1791.
-    let expr0_0 = ALUOp::And;
-    let expr1_0 = constructor_alu_rr_imm_logic(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term and_vec.
-pub fn constructor_and_vec<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: Reg,
-    arg2: &VectorSize,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1794.
-    let expr0_0 = VecALUOp::And;
-    let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term eor_vec.
-pub fn constructor_eor_vec<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: Reg,
-    arg2: &VectorSize,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1798.
-    let expr0_0 = VecALUOp::Eor;
-    let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term bic_vec.
-pub fn constructor_bic_vec<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: Reg,
-    arg2: &VectorSize,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1802.
-    let expr0_0 = VecALUOp::Bic;
-    let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term sshl.
-pub fn constructor_sshl<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: Reg,
-    arg2: &VectorSize,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1806.
-    let expr0_0 = VecALUOp::Sshl;
-    let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term ushl.
-pub fn constructor_ushl<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: Reg,
-    arg2: &VectorSize,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1810.
-    let expr0_0 = VecALUOp::Ushl;
-    let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term a64_rotr.
-pub fn constructor_a64_rotr<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1815.
-    let expr0_0 = ALUOp::RotR;
-    let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term a64_rotr_imm.
-pub fn constructor_a64_rotr_imm<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: ImmShift,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1818.
-    let expr0_0 = ALUOp::RotR;
-    let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term rbit.
-pub fn constructor_rbit<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/aarch64/inst.isle line 1823.
-    let expr0_0 = BitOp::RBit;
-    let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term a64_clz.
-pub fn constructor_a64_clz<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/aarch64/inst.isle line 1828.
-    let expr0_0 = BitOp::Clz;
-    let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term a64_cls.
-pub fn constructor_a64_cls<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/aarch64/inst.isle line 1833.
-    let expr0_0 = BitOp::Cls;
-    let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term eon.
-pub fn constructor_eon<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1838.
-    let expr0_0 = ALUOp::EorNot;
-    let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term vec_cnt.
-pub fn constructor_vec_cnt<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/aarch64/inst.isle line 1843.
-    let expr0_0 = VecMisc2::Cnt;
-    let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term imm.
-pub fn constructor_imm<C: Context>(ctx: &mut C, arg0: Type, arg1: u64) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    if let Some(pattern1_0) = C::integral_ty(ctx, pattern0_0) {
-        let pattern2_0 = arg1;
-        let closure3 = || {
-            let expr0_0: Type = I64;
-            return Some(expr0_0);
-        };
-        if let Some(pattern3_0) = closure3() {
-            if let Some(pattern4_0) = C::imm_logic_from_u64(ctx, pattern2_0, pattern3_0) {
-                // Rule at src/isa/aarch64/inst.isle line 1858.
-                let expr0_0: Type = I64;
-                let expr1_0 = C::zero_reg(ctx);
-                let expr2_0 = constructor_orr_imm(ctx, expr0_0, expr1_0, pattern4_0)?;
-                return Some(expr2_0);
-            }
-        }
-        if let Some(pattern3_0) = C::move_wide_const_from_u64(ctx, pattern2_0) {
-            // Rule at src/isa/aarch64/inst.isle line 1850.
-            let expr0_0 = OperandSize::Size64;
-            let expr1_0 = constructor_movz(ctx, pattern3_0, &expr0_0)?;
-            return Some(expr1_0);
-        }
-        if let Some(pattern3_0) = C::move_wide_const_from_negated_u64(ctx, pattern2_0) {
-            // Rule at src/isa/aarch64/inst.isle line 1854.
-            let expr0_0 = OperandSize::Size64;
-            let expr1_0 = constructor_movn(ctx, pattern3_0, &expr0_0)?;
-            return Some(expr1_0);
-        }
-        // Rule at src/isa/aarch64/inst.isle line 1865.
-        let expr0_0 = C::load_constant64_full(ctx, pattern2_0);
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term put_in_reg_sext32.
-pub fn constructor_put_in_reg_sext32<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = C::value_type(ctx, pattern0_0);
-    if pattern1_0 == I32 {
-        // Rule at src/isa/aarch64/inst.isle line 1876.
-        let expr0_0 = C::put_in_reg(ctx, pattern0_0);
-        return Some(expr0_0);
-    }
-    if pattern1_0 == I64 {
-        // Rule at src/isa/aarch64/inst.isle line 1877.
-        let expr0_0 = C::put_in_reg(ctx, pattern0_0);
-        return Some(expr0_0);
-    }
-    if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
-        // Rule at src/isa/aarch64/inst.isle line 1872.
-        let expr0_0 = C::put_in_reg(ctx, pattern0_0);
-        let expr1_0: bool = true;
-        let expr2_0 = C::ty_bits(ctx, pattern2_0);
-        let expr3_0: u8 = 32;
-        let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
-        return Some(expr4_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term put_in_reg_zext32.
-pub fn constructor_put_in_reg_zext32<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = C::value_type(ctx, pattern0_0);
-    if pattern1_0 == I32 {
-        // Rule at src/isa/aarch64/inst.isle line 1885.
-        let expr0_0 = C::put_in_reg(ctx, pattern0_0);
-        return Some(expr0_0);
-    }
-    if pattern1_0 == I64 {
-        // Rule at src/isa/aarch64/inst.isle line 1886.
-        let expr0_0 = C::put_in_reg(ctx, pattern0_0);
-        return Some(expr0_0);
-    }
-    if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
-        // Rule at src/isa/aarch64/inst.isle line 1881.
-        let expr0_0 = C::put_in_reg(ctx, pattern0_0);
-        let expr1_0: bool = false;
-        let expr2_0 = C::ty_bits(ctx, pattern2_0);
-        let expr3_0: u8 = 32;
-        let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
-        return Some(expr4_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term put_in_reg_sext64.
-pub fn constructor_put_in_reg_sext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = C::value_type(ctx, pattern0_0);
-    if pattern1_0 == I64 {
-        // Rule at src/isa/aarch64/inst.isle line 1894.
-        let expr0_0 = C::put_in_reg(ctx, pattern0_0);
-        return Some(expr0_0);
-    }
-    if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
-        // Rule at src/isa/aarch64/inst.isle line 1890.
-        let expr0_0 = C::put_in_reg(ctx, pattern0_0);
-        let expr1_0: bool = true;
-        let expr2_0 = C::ty_bits(ctx, pattern2_0);
-        let expr3_0: u8 = 64;
-        let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
-        return Some(expr4_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term put_in_reg_zext64.
-pub fn constructor_put_in_reg_zext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = C::value_type(ctx, pattern0_0);
-    if pattern1_0 == I64 {
-        // Rule at src/isa/aarch64/inst.isle line 1902.
-        let expr0_0 = C::put_in_reg(ctx, pattern0_0);
-        return Some(expr0_0);
-    }
-    if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
-        // Rule at src/isa/aarch64/inst.isle line 1898.
-        let expr0_0 = C::put_in_reg(ctx, pattern0_0);
-        let expr1_0: bool = false;
-        let expr2_0 = C::ty_bits(ctx, pattern2_0);
-        let expr3_0: u8 = 64;
-        let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
-        return Some(expr4_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term trap_if_zero_divisor.
-pub fn constructor_trap_if_zero_divisor<C: Context>(ctx: &mut C, arg0: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/aarch64/inst.isle line 1907.
-    let expr0_0 = C::cond_br_zero(ctx, pattern0_0);
-    let expr1_0 = C::trap_code_division_by_zero(ctx);
-    let expr2_0 = MInst::TrapIf {
-        kind: expr0_0,
-        trap_code: expr1_0,
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    return Some(pattern0_0);
-}
-
-// Generated as internal constructor for term size_from_ty.
-pub fn constructor_size_from_ty<C: Context>(ctx: &mut C, arg0: Type) -> Option<OperandSize> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I64 {
-        // Rule at src/isa/aarch64/inst.isle line 1913.
-        let expr0_0 = OperandSize::Size64;
-        return Some(expr0_0);
-    }
-    if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
-        // Rule at src/isa/aarch64/inst.isle line 1912.
-        let expr0_0 = OperandSize::Size32;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term trap_if_div_overflow.
-pub fn constructor_trap_if_div_overflow<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/inst.isle line 1919.
-    let expr0_0 = ALUOp::AddS;
-    let expr1_0 = constructor_operand_size(ctx, pattern0_0)?;
-    let expr2_0 = C::writable_zero_reg(ctx);
-    let expr3_0: u8 = 1;
-    let expr4_0 = C::u8_into_imm12(ctx, expr3_0);
-    let expr5_0 = MInst::AluRRImm12 {
-        alu_op: expr0_0,
-        size: expr1_0,
-        rd: expr2_0,
-        rn: pattern2_0,
-        imm12: expr4_0,
-    };
-    let expr6_0 = C::emit(ctx, &expr5_0);
-    let expr7_0 = constructor_size_from_ty(ctx, pattern0_0)?;
-    let expr8_0: u8 = 1;
-    let expr9_0 = C::u8_into_uimm5(ctx, expr8_0);
-    let expr10_0: bool = false;
-    let expr11_0: bool = false;
-    let expr12_0: bool = false;
-    let expr13_0: bool = false;
-    let expr14_0 = C::nzcv(ctx, expr10_0, expr11_0, expr12_0, expr13_0);
-    let expr15_0 = Cond::Eq;
-    let expr16_0 = MInst::CCmpImm {
-        size: expr7_0,
-        rn: pattern1_0,
-        imm: expr9_0,
-        nzcv: expr14_0,
-        cond: expr15_0,
-    };
-    let expr17_0 = C::emit(ctx, &expr16_0);
-    let expr18_0 = Cond::Vs;
-    let expr19_0 = C::cond_br_cond(ctx, &expr18_0);
-    let expr20_0 = C::trap_code_integer_overflow(ctx);
-    let expr21_0 = MInst::TrapIf {
-        kind: expr19_0,
-        trap_code: expr20_0,
-    };
-    let expr22_0 = C::emit(ctx, &expr21_0);
-    return Some(pattern1_0);
-}
-
-// Generated as internal constructor for term alu_rs_imm_logic_commutative.
-pub fn constructor_alu_rs_imm_logic_commutative<C: Context>(
-    ctx: &mut C,
-    arg0: &ALUOp,
-    arg1: Type,
-    arg2: Value,
-    arg3: Value,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    if let Some(pattern3_0) = C::def_inst(ctx, pattern2_0) {
-        let pattern4_0 = C::inst_data(ctx, pattern3_0);
-        match &pattern4_0 {
-            &InstructionData::UnaryImm {
-                opcode: ref pattern5_0,
-                imm: pattern5_1,
-            } => {
-                if let &Opcode::Iconst = pattern5_0 {
-                    let closure7 = || {
-                        return Some(pattern1_0);
-                    };
-                    if let Some(pattern7_0) = closure7() {
-                        if let Some(pattern8_0) =
-                            C::imm_logic_from_imm64(ctx, pattern5_1, pattern7_0)
-                        {
-                            let pattern9_0 = arg3;
-                            // Rule at src/isa/aarch64/inst.isle line 1964.
-                            let expr0_0 = C::put_in_reg(ctx, pattern9_0);
-                            let expr1_0 = constructor_alu_rr_imm_logic(
-                                ctx, pattern0_0, pattern1_0, expr0_0, pattern8_0,
-                            )?;
-                            return Some(expr1_0);
-                        }
-                    }
-                }
-            }
-            &InstructionData::Binary {
-                opcode: ref pattern5_0,
-                args: ref pattern5_1,
-            } => {
-                if let &Opcode::Ishl = pattern5_0 {
-                    let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                    if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
-                        let pattern9_0 = C::inst_data(ctx, pattern8_0);
-                        if let &InstructionData::UnaryImm {
-                            opcode: ref pattern10_0,
-                            imm: pattern10_1,
-                        } = &pattern9_0
-                        {
-                            if let &Opcode::Iconst = pattern10_0 {
-                                let closure12 = || {
-                                    return Some(pattern1_0);
-                                };
-                                if let Some(pattern12_0) = closure12() {
-                                    if let Some(pattern13_0) =
-                                        C::lshl_from_imm64(ctx, pattern10_1, pattern12_0)
-                                    {
-                                        let pattern14_0 = arg3;
-                                        // Rule at src/isa/aarch64/inst.isle line 1970.
-                                        let expr0_0 = C::put_in_reg(ctx, pattern14_0);
-                                        let expr1_0 = C::put_in_reg(ctx, pattern7_0);
-                                        let expr2_0 = constructor_alu_rrr_shift(
-                                            ctx,
-                                            pattern0_0,
-                                            pattern1_0,
-                                            expr0_0,
-                                            expr1_0,
-                                            pattern13_0,
-                                        )?;
-                                        return Some(expr2_0);
-                                    }
-                                }
-                            }
-                        }
-                    }
-                }
-            }
-            _ => {}
-        }
-    }
-    let pattern3_0 = arg3;
-    if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
-        let pattern5_0 = C::inst_data(ctx, pattern4_0);
-        match &pattern5_0 {
-            &InstructionData::UnaryImm {
-                opcode: ref pattern6_0,
-                imm: pattern6_1,
-            } => {
-                if let &Opcode::Iconst = pattern6_0 {
-                    let closure8 = || {
-                        return Some(pattern1_0);
-                    };
-                    if let Some(pattern8_0) = closure8() {
-                        if let Some(pattern9_0) =
-                            C::imm_logic_from_imm64(ctx, pattern6_1, pattern8_0)
-                        {
-                            // Rule at src/isa/aarch64/inst.isle line 1962.
-                            let expr0_0 = C::put_in_reg(ctx, pattern2_0);
-                            let expr1_0 = constructor_alu_rr_imm_logic(
-                                ctx, pattern0_0, pattern1_0, expr0_0, pattern9_0,
-                            )?;
-                            return Some(expr1_0);
-                        }
-                    }
-                }
-            }
-            &InstructionData::Binary {
-                opcode: ref pattern6_0,
-                args: ref pattern6_1,
-            } => {
-                if let &Opcode::Ishl = pattern6_0 {
-                    let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
-                    if let Some(pattern9_0) = C::def_inst(ctx, pattern8_1) {
-                        let pattern10_0 = C::inst_data(ctx, pattern9_0);
-                        if let &InstructionData::UnaryImm {
-                            opcode: ref pattern11_0,
-                            imm: pattern11_1,
-                        } = &pattern10_0
-                        {
-                            if let &Opcode::Iconst = pattern11_0 {
-                                let closure13 = || {
-                                    return Some(pattern1_0);
-                                };
-                                if let Some(pattern13_0) = closure13() {
-                                    if let Some(pattern14_0) =
-                                        C::lshl_from_imm64(ctx, pattern11_1, pattern13_0)
-                                    {
-                                        // Rule at src/isa/aarch64/inst.isle line 1968.
-                                        let expr0_0 = C::put_in_reg(ctx, pattern2_0);
-                                        let expr1_0 = C::put_in_reg(ctx, pattern8_0);
-                                        let expr2_0 = constructor_alu_rrr_shift(
-                                            ctx,
-                                            pattern0_0,
-                                            pattern1_0,
-                                            expr0_0,
-                                            expr1_0,
-                                            pattern14_0,
-                                        )?;
-                                        return Some(expr2_0);
-                                    }
-                                }
-                            }
-                        }
-                    }
-                }
-            }
-            _ => {}
-        }
-    }
-    // Rule at src/isa/aarch64/inst.isle line 1958.
-    let expr0_0 = C::put_in_reg(ctx, pattern2_0);
-    let expr1_0 = C::put_in_reg(ctx, pattern3_0);
-    let expr2_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr0_0, expr1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term alu_rs_imm_logic.
-pub fn constructor_alu_rs_imm_logic<C: Context>(
-    ctx: &mut C,
-    arg0: &ALUOp,
-    arg1: Type,
-    arg2: Value,
-    arg3: Value,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
-        let pattern5_0 = C::inst_data(ctx, pattern4_0);
-        match &pattern5_0 {
-            &InstructionData::UnaryImm {
-                opcode: ref pattern6_0,
-                imm: pattern6_1,
-            } => {
-                if let &Opcode::Iconst = pattern6_0 {
-                    let closure8 = || {
-                        return Some(pattern1_0);
-                    };
-                    if let Some(pattern8_0) = closure8() {
-                        if let Some(pattern9_0) =
-                            C::imm_logic_from_imm64(ctx, pattern6_1, pattern8_0)
-                        {
-                            // Rule at src/isa/aarch64/inst.isle line 1978.
-                            let expr0_0 = C::put_in_reg(ctx, pattern2_0);
-                            let expr1_0 = constructor_alu_rr_imm_logic(
-                                ctx, pattern0_0, pattern1_0, expr0_0, pattern9_0,
-                            )?;
-                            return Some(expr1_0);
-                        }
-                    }
-                }
-            }
-            &InstructionData::Binary {
-                opcode: ref pattern6_0,
-                args: ref pattern6_1,
-            } => {
-                if let &Opcode::Ishl = pattern6_0 {
-                    let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
-                    if let Some(pattern9_0) = C::def_inst(ctx, pattern8_1) {
-                        let pattern10_0 = C::inst_data(ctx, pattern9_0);
-                        if let &InstructionData::UnaryImm {
-                            opcode: ref pattern11_0,
-                            imm: pattern11_1,
-                        } = &pattern10_0
-                        {
-                            if let &Opcode::Iconst = pattern11_0 {
-                                let closure13 = || {
-                                    return Some(pattern1_0);
-                                };
-                                if let Some(pattern13_0) = closure13() {
-                                    if let Some(pattern14_0) =
-                                        C::lshl_from_imm64(ctx, pattern11_1, pattern13_0)
-                                    {
-                                        // Rule at src/isa/aarch64/inst.isle line 1980.
-                                        let expr0_0 = C::put_in_reg(ctx, pattern2_0);
-                                        let expr1_0 = C::put_in_reg(ctx, pattern8_0);
-                                        let expr2_0 = constructor_alu_rrr_shift(
-                                            ctx,
-                                            pattern0_0,
-                                            pattern1_0,
-                                            expr0_0,
-                                            expr1_0,
-                                            pattern14_0,
-                                        )?;
-                                        return Some(expr2_0);
-                                    }
-                                }
-                            }
-                        }
-                    }
-                }
-            }
-            _ => {}
-        }
-    }
-    // Rule at src/isa/aarch64/inst.isle line 1976.
-    let expr0_0 = C::put_in_reg(ctx, pattern2_0);
-    let expr1_0 = C::put_in_reg(ctx, pattern3_0);
-    let expr2_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr0_0, expr1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term i128_alu_bitop.
-pub fn constructor_i128_alu_bitop<C: Context>(
-    ctx: &mut C,
-    arg0: &ALUOp,
-    arg1: Type,
-    arg2: Value,
-    arg3: Value,
-) -> Option<ValueRegs> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/aarch64/inst.isle line 1988.
-    let expr0_0 = C::put_in_regs(ctx, pattern2_0);
-    let expr1_0: usize = 0;
-    let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
-    let expr3_0: usize = 1;
-    let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
-    let expr5_0 = C::put_in_regs(ctx, pattern3_0);
-    let expr6_0: usize = 0;
-    let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
-    let expr8_0: usize = 1;
-    let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
-    let expr10_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr2_0, expr7_0)?;
-    let expr11_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr4_0, expr9_0)?;
-    let expr12_0 = C::value_regs(ctx, expr10_0, expr11_0);
-    return Some(expr12_0);
-}
-
-// Generated as internal constructor for term lower.
-pub fn constructor_lower<C: Context>(ctx: &mut C, arg0: Inst) -> Option<InstOutput> {
-    let pattern0_0 = arg0;
-    if let Some(pattern1_0) = C::first_result(ctx, pattern0_0) {
-        let pattern2_0 = C::value_type(ctx, pattern1_0);
-        if pattern2_0 == I8 {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            if let &InstructionData::Unary {
-                opcode: ref pattern5_0,
-                arg: pattern5_1,
-            } = &pattern4_0
-            {
-                match pattern5_0 {
-                    &Opcode::Bitrev => {
-                        // Rule at src/isa/aarch64/lower.isle line 974.
-                        let expr0_0: Type = I32;
-                        let expr1_0: Type = I32;
-                        let expr2_0 = C::put_in_reg(ctx, pattern5_1);
-                        let expr3_0 = constructor_rbit(ctx, expr1_0, expr2_0)?;
-                        let expr4_0: u8 = 24;
-                        let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
-                        let expr6_0 = constructor_lsr_imm(ctx, expr0_0, expr3_0, expr5_0)?;
-                        let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
-                        return Some(expr7_0);
-                    }
-                    &Opcode::Clz => {
-                        // Rule at src/isa/aarch64/lower.isle line 995.
-                        let expr0_0: Type = I32;
-                        let expr1_0: Type = I32;
-                        let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
-                        let expr3_0 = constructor_a64_clz(ctx, expr1_0, expr2_0)?;
-                        let expr4_0: u8 = 24;
-                        let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
-                        let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
-                        let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
-                        return Some(expr7_0);
-                    }
-                    &Opcode::Cls => {
-                        // Rule at src/isa/aarch64/lower.isle line 1042.
-                        let expr0_0: Type = I32;
-                        let expr1_0: Type = I32;
-                        let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
-                        let expr3_0 = constructor_a64_cls(ctx, expr1_0, expr2_0)?;
-                        let expr4_0: u8 = 24;
-                        let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
-                        let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
-                        let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
-                        return Some(expr7_0);
-                    }
-                    &Opcode::Ctz => {
-                        // Rule at src/isa/aarch64/lower.isle line 1025.
-                        let expr0_0: Type = I32;
-                        let expr1_0: Type = I32;
-                        let expr2_0: Type = I32;
-                        let expr3_0 = C::put_in_reg(ctx, pattern5_1);
-                        let expr4_0 = constructor_rbit(ctx, expr2_0, expr3_0)?;
-                        let expr5_0: Type = I32;
-                        let expr6_0: u64 = 8388608;
-                        let expr7_0 = C::u64_into_imm_logic(ctx, expr5_0, expr6_0);
-                        let expr8_0 = constructor_orr_imm(ctx, expr1_0, expr4_0, expr7_0)?;
-                        let expr9_0 = constructor_a64_clz(ctx, expr0_0, expr8_0)?;
-                        let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
-                        return Some(expr10_0);
-                    }
-                    &Opcode::Popcnt => {
-                        // Rule at src/isa/aarch64/lower.isle line 1093.
-                        let expr0_0 = C::put_in_reg(ctx, pattern5_1);
-                        let expr1_0 = ScalarSize::Size32;
-                        let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
-                        let expr3_0 = VectorSize::Size8x8;
-                        let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
-                        let expr5_0: u8 = 0;
-                        let expr6_0 = VectorSize::Size8x16;
-                        let expr7_0 = constructor_mov_from_vec(ctx, expr4_0, expr5_0, &expr6_0)?;
-                        let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
-                        return Some(expr8_0);
-                    }
-                    _ => {}
-                }
-            }
-        }
-        if pattern2_0 == I16 {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            if let &InstructionData::Unary {
-                opcode: ref pattern5_0,
-                arg: pattern5_1,
-            } = &pattern4_0
-            {
-                match pattern5_0 {
-                    &Opcode::Bitrev => {
-                        // Rule at src/isa/aarch64/lower.isle line 980.
-                        let expr0_0: Type = I32;
-                        let expr1_0: Type = I32;
-                        let expr2_0 = C::put_in_reg(ctx, pattern5_1);
-                        let expr3_0 = constructor_rbit(ctx, expr1_0, expr2_0)?;
-                        let expr4_0: u8 = 16;
-                        let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
-                        let expr6_0 = constructor_lsr_imm(ctx, expr0_0, expr3_0, expr5_0)?;
-                        let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
-                        return Some(expr7_0);
-                    }
-                    &Opcode::Clz => {
-                        // Rule at src/isa/aarch64/lower.isle line 998.
-                        let expr0_0: Type = I32;
-                        let expr1_0: Type = I32;
-                        let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
-                        let expr3_0 = constructor_a64_clz(ctx, expr1_0, expr2_0)?;
-                        let expr4_0: u8 = 16;
-                        let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
-                        let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
-                        let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
-                        return Some(expr7_0);
-                    }
-                    &Opcode::Cls => {
-                        // Rule at src/isa/aarch64/lower.isle line 1045.
-                        let expr0_0: Type = I32;
-                        let expr1_0: Type = I32;
-                        let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
-                        let expr3_0 = constructor_a64_cls(ctx, expr1_0, expr2_0)?;
-                        let expr4_0: u8 = 16;
-                        let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
-                        let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
-                        let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
-                        return Some(expr7_0);
-                    }
-                    &Opcode::Ctz => {
-                        // Rule at src/isa/aarch64/lower.isle line 1028.
-                        let expr0_0: Type = I32;
-                        let expr1_0: Type = I32;
-                        let expr2_0: Type = I32;
-                        let expr3_0 = C::put_in_reg(ctx, pattern5_1);
-                        let expr4_0 = constructor_rbit(ctx, expr2_0, expr3_0)?;
-                        let expr5_0: Type = I32;
-                        let expr6_0: u64 = 32768;
-                        let expr7_0 = C::u64_into_imm_logic(ctx, expr5_0, expr6_0);
-                        let expr8_0 = constructor_orr_imm(ctx, expr1_0, expr4_0, expr7_0)?;
-                        let expr9_0 = constructor_a64_clz(ctx, expr0_0, expr8_0)?;
-                        let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
-                        return Some(expr10_0);
-                    }
-                    &Opcode::Popcnt => {
-                        // Rule at src/isa/aarch64/lower.isle line 1099.
-                        let expr0_0 = C::put_in_reg(ctx, pattern5_1);
-                        let expr1_0 = ScalarSize::Size32;
-                        let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
-                        let expr3_0 = VectorSize::Size8x8;
-                        let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
-                        let expr5_0 = VectorSize::Size8x8;
-                        let expr6_0 = constructor_addp(ctx, expr4_0, expr4_0, &expr5_0)?;
-                        let expr7_0: u8 = 0;
-                        let expr8_0 = VectorSize::Size8x16;
-                        let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
-                        let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
-                        return Some(expr10_0);
-                    }
-                    _ => {}
-                }
-            }
-        }
-        if pattern2_0 == I32 {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            match &pattern4_0 {
-                &InstructionData::Binary {
-                    opcode: ref pattern5_0,
-                    args: ref pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Rotl => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
-                                let pattern9_0 = C::inst_data(ctx, pattern8_0);
-                                if let &InstructionData::UnaryImm {
-                                    opcode: ref pattern10_0,
-                                    imm: pattern10_1,
-                                } = &pattern9_0
-                                {
-                                    if let &Opcode::Iconst = pattern10_0 {
-                                        let closure12 = || {
-                                            let expr0_0: Type = I32;
-                                            return Some(expr0_0);
-                                        };
-                                        if let Some(pattern12_0) = closure12() {
-                                            if let Some(pattern13_0) = C::imm_shift_from_imm64(
-                                                ctx,
-                                                pattern10_1,
-                                                pattern12_0,
-                                            ) {
-                                                // Rule at src/isa/aarch64/lower.isle line 865.
-                                                let expr0_0: Type = I32;
-                                                let expr1_0 = C::put_in_reg(ctx, pattern7_0);
-                                                let expr2_0: Type = I32;
-                                                let expr3_0 =
-                                                    C::negate_imm_shift(ctx, expr2_0, pattern13_0);
-                                                let expr4_0 = constructor_a64_rotr_imm(
-                                                    ctx, expr0_0, expr1_0, expr3_0,
-                                                )?;
-                                                let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
-                                                return Some(expr5_0);
-                                            }
-                                        }
-                                    }
-                                }
-                            }
-                            // Rule at src/isa/aarch64/lower.isle line 855.
-                            let expr0_0: Type = I32;
-                            let expr1_0 = C::zero_reg(ctx);
-                            let expr2_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?;
-                            let expr4_0: Type = I32;
-                            let expr5_0 = C::put_in_reg(ctx, pattern7_0);
-                            let expr6_0 = constructor_a64_rotr(ctx, expr4_0, expr5_0, expr3_0)?;
-                            let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
-                            return Some(expr7_0);
-                        }
-                        &Opcode::Rotr => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
-                                let pattern9_0 = C::inst_data(ctx, pattern8_0);
-                                if let &InstructionData::UnaryImm {
-                                    opcode: ref pattern10_0,
-                                    imm: pattern10_1,
-                                } = &pattern9_0
-                                {
-                                    if let &Opcode::Iconst = pattern10_0 {
-                                        let closure12 = || {
-                                            let expr0_0: Type = I32;
-                                            return Some(expr0_0);
-                                        };
-                                        if let Some(pattern12_0) = closure12() {
-                                            if let Some(pattern13_0) = C::imm_shift_from_imm64(
-                                                ctx,
-                                                pattern10_1,
-                                                pattern12_0,
-                                            ) {
-                                                // Rule at src/isa/aarch64/lower.isle line 907.
-                                                let expr0_0: Type = I32;
-                                                let expr1_0 = C::put_in_reg(ctx, pattern7_0);
-                                                let expr2_0 = constructor_a64_rotr_imm(
-                                                    ctx,
-                                                    expr0_0,
-                                                    expr1_0,
-                                                    pattern13_0,
-                                                )?;
-                                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                                return Some(expr3_0);
-                                            }
-                                        }
-                                    }
-                                }
-                            }
-                            // Rule at src/isa/aarch64/lower.isle line 895.
-                            let expr0_0: Type = I32;
-                            let expr1_0 = C::put_in_reg(ctx, pattern7_0);
-                            let expr2_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr3_0 = constructor_a64_rotr(ctx, expr0_0, expr1_0, expr2_0)?;
-                            let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                            return Some(expr4_0);
-                        }
-                        _ => {}
-                    }
-                }
-                &InstructionData::Unary {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                } => {
-                    if let &Opcode::Popcnt = pattern5_0 {
-                        // Rule at src/isa/aarch64/lower.isle line 1105.
-                        let expr0_0 = C::put_in_reg(ctx, pattern5_1);
-                        let expr1_0 = ScalarSize::Size32;
-                        let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
-                        let expr3_0 = VectorSize::Size8x8;
-                        let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
-                        let expr5_0 = VectorSize::Size8x8;
-                        let expr6_0 = constructor_addv(ctx, expr4_0, &expr5_0)?;
-                        let expr7_0: u8 = 0;
-                        let expr8_0 = VectorSize::Size8x16;
-                        let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
-                        let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
-                        return Some(expr10_0);
-                    }
-                }
-                _ => {}
-            }
-        }
-        if pattern2_0 == I64 {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            match &pattern4_0 {
-                &InstructionData::Binary {
-                    opcode: ref pattern5_0,
-                    args: ref pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Umulhi => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 367.
-                            let expr0_0: Type = I64;
-                            let expr1_0 = C::put_in_reg(ctx, pattern7_0);
-                            let expr2_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr3_0 = constructor_umulh(ctx, expr0_0, expr1_0, expr2_0)?;
-                            let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                            return Some(expr4_0);
-                        }
-                        &Opcode::Smulhi => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 355.
-                            let expr0_0: Type = I64;
-                            let expr1_0 = C::put_in_reg(ctx, pattern7_0);
-                            let expr2_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr3_0 = constructor_smulh(ctx, expr0_0, expr1_0, expr2_0)?;
-                            let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                            return Some(expr4_0);
-                        }
-                        &Opcode::Band => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 586.
-                            let expr0_0 = ALUOp::And;
-                            let expr1_0: Type = I64;
-                            let expr2_0 = constructor_alu_rs_imm_logic_commutative(
-                                ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
-                            )?;
-                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Bor => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 599.
-                            let expr0_0 = ALUOp::Orr;
-                            let expr1_0: Type = I64;
-                            let expr2_0 = constructor_alu_rs_imm_logic_commutative(
-                                ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
-                            )?;
-                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Bxor => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 612.
-                            let expr0_0 = ALUOp::Eor;
-                            let expr1_0: Type = I64;
-                            let expr2_0 = constructor_alu_rs_imm_logic_commutative(
-                                ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
-                            )?;
-                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::BandNot => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 625.
-                            let expr0_0 = ALUOp::AndNot;
-                            let expr1_0: Type = I64;
-                            let expr2_0 = constructor_alu_rs_imm_logic(
-                                ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
-                            )?;
-                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::BorNot => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 638.
-                            let expr0_0 = ALUOp::OrrNot;
-                            let expr1_0: Type = I64;
-                            let expr2_0 = constructor_alu_rs_imm_logic(
-                                ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
-                            )?;
-                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::BxorNot => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 648.
-                            let expr0_0 = ALUOp::EorNot;
-                            let expr1_0: Type = I64;
-                            let expr2_0 = constructor_alu_rs_imm_logic(
-                                ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
-                            )?;
-                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Rotl => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
-                                let pattern9_0 = C::inst_data(ctx, pattern8_0);
-                                if let &InstructionData::UnaryImm {
-                                    opcode: ref pattern10_0,
-                                    imm: pattern10_1,
-                                } = &pattern9_0
-                                {
-                                    if let &Opcode::Iconst = pattern10_0 {
-                                        let closure12 = || {
-                                            let expr0_0: Type = I64;
-                                            return Some(expr0_0);
-                                        };
-                                        if let Some(pattern12_0) = closure12() {
-                                            if let Some(pattern13_0) = C::imm_shift_from_imm64(
-                                                ctx,
-                                                pattern10_1,
-                                                pattern12_0,
-                                            ) {
-                                                // Rule at src/isa/aarch64/lower.isle line 869.
-                                                let expr0_0: Type = I64;
-                                                let expr1_0 = C::put_in_reg(ctx, pattern7_0);
-                                                let expr2_0: Type = I64;
-                                                let expr3_0 =
-                                                    C::negate_imm_shift(ctx, expr2_0, pattern13_0);
-                                                let expr4_0 = constructor_a64_rotr_imm(
-                                                    ctx, expr0_0, expr1_0, expr3_0,
-                                                )?;
-                                                let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
-                                                return Some(expr5_0);
-                                            }
-                                        }
-                                    }
-                                }
-                            }
-                            // Rule at src/isa/aarch64/lower.isle line 860.
-                            let expr0_0: Type = I64;
-                            let expr1_0 = C::zero_reg(ctx);
-                            let expr2_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?;
-                            let expr4_0: Type = I64;
-                            let expr5_0 = C::put_in_reg(ctx, pattern7_0);
-                            let expr6_0 = constructor_a64_rotr(ctx, expr4_0, expr5_0, expr3_0)?;
-                            let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
-                            return Some(expr7_0);
-                        }
-                        &Opcode::Rotr => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
-                                let pattern9_0 = C::inst_data(ctx, pattern8_0);
-                                if let &InstructionData::UnaryImm {
-                                    opcode: ref pattern10_0,
-                                    imm: pattern10_1,
-                                } = &pattern9_0
-                                {
-                                    if let &Opcode::Iconst = pattern10_0 {
-                                        let closure12 = || {
-                                            let expr0_0: Type = I64;
-                                            return Some(expr0_0);
-                                        };
-                                        if let Some(pattern12_0) = closure12() {
-                                            if let Some(pattern13_0) = C::imm_shift_from_imm64(
-                                                ctx,
-                                                pattern10_1,
-                                                pattern12_0,
-                                            ) {
-                                                // Rule at src/isa/aarch64/lower.isle line 911.
-                                                let expr0_0: Type = I64;
-                                                let expr1_0 = C::put_in_reg(ctx, pattern7_0);
-                                                let expr2_0 = constructor_a64_rotr_imm(
-                                                    ctx,
-                                                    expr0_0,
-                                                    expr1_0,
-                                                    pattern13_0,
-                                                )?;
-                                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                                return Some(expr3_0);
-                                            }
-                                        }
-                                    }
-                                }
-                            }
-                            // Rule at src/isa/aarch64/lower.isle line 899.
-                            let expr0_0: Type = I64;
-                            let expr1_0 = C::put_in_reg(ctx, pattern7_0);
-                            let expr2_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr3_0 = constructor_a64_rotr(ctx, expr0_0, expr1_0, expr2_0)?;
-                            let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                            return Some(expr4_0);
-                        }
-                        &Opcode::Ishl => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 660.
-                            let expr0_0 = ALUOp::Lsl;
-                            let expr1_0: Type = I64;
-                            let expr2_0 = C::put_in_reg(ctx, pattern7_0);
-                            let expr3_0 =
-                                constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
-                            let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                            return Some(expr4_0);
-                        }
-                        &Opcode::Ushr => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 744.
-                            let expr0_0 = ALUOp::Lsr;
-                            let expr1_0: Type = I64;
-                            let expr2_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
-                            let expr3_0 =
-                                constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
-                            let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                            return Some(expr4_0);
-                        }
-                        &Opcode::Sshr => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 791.
-                            let expr0_0 = ALUOp::Asr;
-                            let expr1_0: Type = I64;
-                            let expr2_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
-                            let expr3_0 =
-                                constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
-                            let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                            return Some(expr4_0);
-                        }
-                        _ => {}
-                    }
-                }
-                &InstructionData::Unary {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                } => {
-                    if let &Opcode::Popcnt = pattern5_0 {
-                        // Rule at src/isa/aarch64/lower.isle line 1111.
-                        let expr0_0 = C::put_in_reg(ctx, pattern5_1);
-                        let expr1_0 = ScalarSize::Size64;
-                        let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
-                        let expr3_0 = VectorSize::Size8x8;
-                        let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
-                        let expr5_0 = VectorSize::Size8x8;
-                        let expr6_0 = constructor_addv(ctx, expr4_0, &expr5_0)?;
-                        let expr7_0: u8 = 0;
-                        let expr8_0 = VectorSize::Size8x16;
-                        let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
-                        let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
-                        return Some(expr10_0);
-                    }
-                }
-                _ => {}
-            }
-        }
-        if pattern2_0 == I128 {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            match &pattern4_0 {
-                &InstructionData::Binary {
-                    opcode: ref pattern5_0,
-                    args: ref pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Iadd => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 79.
-                            let expr0_0 = C::put_in_regs(ctx, pattern7_0);
-                            let expr1_0: usize = 0;
-                            let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
-                            let expr3_0: usize = 1;
-                            let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
-                            let expr5_0 = C::put_in_regs(ctx, pattern7_1);
-                            let expr6_0: usize = 0;
-                            let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
-                            let expr8_0: usize = 1;
-                            let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
-                            let expr10_0: Type = I64;
-                            let expr11_0 =
-                                constructor_add_with_flags_paired(ctx, expr10_0, expr2_0, expr7_0)?;
-                            let expr12_0: Type = I64;
-                            let expr13_0 = constructor_adc_paired(ctx, expr12_0, expr4_0, expr9_0)?;
-                            let expr14_0 = constructor_with_flags(ctx, &expr11_0, &expr13_0)?;
-                            let expr15_0 = C::output(ctx, expr14_0);
-                            return Some(expr15_0);
-                        }
-                        &Opcode::Isub => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 129.
-                            let expr0_0 = C::put_in_regs(ctx, pattern7_0);
-                            let expr1_0: usize = 0;
-                            let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
-                            let expr3_0: usize = 1;
-                            let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
-                            let expr5_0 = C::put_in_regs(ctx, pattern7_1);
-                            let expr6_0: usize = 0;
-                            let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
-                            let expr8_0: usize = 1;
-                            let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
-                            let expr10_0: Type = I64;
-                            let expr11_0 =
-                                constructor_sub_with_flags_paired(ctx, expr10_0, expr2_0, expr7_0)?;
-                            let expr12_0: Type = I64;
-                            let expr13_0 = constructor_sbc_paired(ctx, expr12_0, expr4_0, expr9_0)?;
-                            let expr14_0 = constructor_with_flags(ctx, &expr11_0, &expr13_0)?;
-                            let expr15_0 = C::output(ctx, expr14_0);
-                            return Some(expr15_0);
-                        }
-                        &Opcode::Imul => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 183.
-                            let expr0_0 = C::put_in_regs(ctx, pattern7_0);
-                            let expr1_0: usize = 0;
-                            let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
-                            let expr3_0: usize = 1;
-                            let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
-                            let expr5_0 = C::put_in_regs(ctx, pattern7_1);
-                            let expr6_0: usize = 0;
-                            let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
-                            let expr8_0: usize = 1;
-                            let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
-                            let expr10_0: Type = I64;
-                            let expr11_0 = constructor_umulh(ctx, expr10_0, expr2_0, expr7_0)?;
-                            let expr12_0 = constructor_madd64(ctx, expr2_0, expr9_0, expr11_0)?;
-                            let expr13_0 = constructor_madd64(ctx, expr4_0, expr7_0, expr12_0)?;
-                            let expr14_0 = C::zero_reg(ctx);
-                            let expr15_0 = constructor_madd64(ctx, expr2_0, expr7_0, expr14_0)?;
-                            let expr16_0 = C::value_regs(ctx, expr15_0, expr13_0);
-                            let expr17_0 = C::output(ctx, expr16_0);
-                            return Some(expr17_0);
-                        }
-                        &Opcode::Band => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 589.
-                            let expr0_0 = ALUOp::And;
-                            let expr1_0: Type = I64;
-                            let expr2_0 = constructor_i128_alu_bitop(
-                                ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
-                            )?;
-                            let expr3_0 = C::output(ctx, expr2_0);
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Bor => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 602.
-                            let expr0_0 = ALUOp::Orr;
-                            let expr1_0: Type = I64;
-                            let expr2_0 = constructor_i128_alu_bitop(
-                                ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
-                            )?;
-                            let expr3_0 = C::output(ctx, expr2_0);
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Bxor => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 615.
-                            let expr0_0 = ALUOp::Eor;
-                            let expr1_0: Type = I64;
-                            let expr2_0 = constructor_i128_alu_bitop(
-                                ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
-                            )?;
-                            let expr3_0 = C::output(ctx, expr2_0);
-                            return Some(expr3_0);
-                        }
-                        &Opcode::BandNot => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 628.
-                            let expr0_0 = ALUOp::AndNot;
-                            let expr1_0: Type = I64;
-                            let expr2_0 = constructor_i128_alu_bitop(
-                                ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
-                            )?;
-                            let expr3_0 = C::output(ctx, expr2_0);
-                            return Some(expr3_0);
-                        }
-                        &Opcode::BorNot => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 641.
-                            let expr0_0 = ALUOp::OrrNot;
-                            let expr1_0: Type = I64;
-                            let expr2_0 = constructor_i128_alu_bitop(
-                                ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
-                            )?;
-                            let expr3_0 = C::output(ctx, expr2_0);
-                            return Some(expr3_0);
-                        }
-                        &Opcode::BxorNot => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 651.
-                            let expr0_0 = ALUOp::EorNot;
-                            let expr1_0: Type = I64;
-                            let expr2_0 = constructor_i128_alu_bitop(
-                                ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
-                            )?;
-                            let expr3_0 = C::output(ctx, expr2_0);
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Rotl => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 878.
-                            let expr0_0 = C::put_in_regs(ctx, pattern7_0);
-                            let expr1_0 = C::put_in_regs(ctx, pattern7_1);
-                            let expr2_0: usize = 0;
-                            let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
-                            let expr4_0: Type = I64;
-                            let expr5_0: Type = I64;
-                            let expr6_0: u64 = 128;
-                            let expr7_0 = constructor_imm(ctx, expr5_0, expr6_0)?;
-                            let expr8_0 = constructor_sub(ctx, expr4_0, expr7_0, expr3_0)?;
-                            let expr9_0 = constructor_lower_shl128(ctx, expr0_0, expr3_0)?;
-                            let expr10_0 = constructor_lower_ushr128(ctx, expr0_0, expr8_0)?;
-                            let expr11_0: Type = I64;
-                            let expr12_0: usize = 0;
-                            let expr13_0 = C::value_regs_get(ctx, expr9_0, expr12_0);
-                            let expr14_0: usize = 0;
-                            let expr15_0 = C::value_regs_get(ctx, expr10_0, expr14_0);
-                            let expr16_0 = constructor_orr(ctx, expr11_0, expr13_0, expr15_0)?;
-                            let expr17_0: Type = I64;
-                            let expr18_0: usize = 1;
-                            let expr19_0 = C::value_regs_get(ctx, expr9_0, expr18_0);
-                            let expr20_0: usize = 1;
-                            let expr21_0 = C::value_regs_get(ctx, expr10_0, expr20_0);
-                            let expr22_0 = constructor_orr(ctx, expr17_0, expr19_0, expr21_0)?;
-                            let expr23_0 = C::value_regs(ctx, expr16_0, expr22_0);
-                            let expr24_0 = C::output(ctx, expr23_0);
-                            return Some(expr24_0);
-                        }
-                        &Opcode::Rotr => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 959.
-                            let expr0_0 = C::put_in_regs(ctx, pattern7_0);
-                            let expr1_0 = C::put_in_regs(ctx, pattern7_1);
-                            let expr2_0: usize = 0;
-                            let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
-                            let expr4_0: Type = I64;
-                            let expr5_0: Type = I64;
-                            let expr6_0: u64 = 128;
-                            let expr7_0 = constructor_imm(ctx, expr5_0, expr6_0)?;
-                            let expr8_0 = constructor_sub(ctx, expr4_0, expr7_0, expr3_0)?;
-                            let expr9_0 = constructor_lower_ushr128(ctx, expr0_0, expr3_0)?;
-                            let expr10_0 = constructor_lower_shl128(ctx, expr0_0, expr8_0)?;
-                            let expr11_0: Type = I64;
-                            let expr12_0: usize = 1;
-                            let expr13_0 = C::value_regs_get(ctx, expr9_0, expr12_0);
-                            let expr14_0: usize = 1;
-                            let expr15_0 = C::value_regs_get(ctx, expr10_0, expr14_0);
-                            let expr16_0 = constructor_orr(ctx, expr11_0, expr13_0, expr15_0)?;
-                            let expr17_0: Type = I64;
-                            let expr18_0: usize = 0;
-                            let expr19_0 = C::value_regs_get(ctx, expr9_0, expr18_0);
-                            let expr20_0: usize = 0;
-                            let expr21_0 = C::value_regs_get(ctx, expr10_0, expr20_0);
-                            let expr22_0 = constructor_orr(ctx, expr17_0, expr19_0, expr21_0)?;
-                            let expr23_0 = C::value_regs(ctx, expr22_0, expr16_0);
-                            let expr24_0 = C::output(ctx, expr23_0);
-                            return Some(expr24_0);
-                        }
-                        &Opcode::Ishl => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 664.
-                            let expr0_0 = C::put_in_regs(ctx, pattern7_0);
-                            let expr1_0 = C::put_in_regs(ctx, pattern7_1);
-                            let expr2_0: usize = 0;
-                            let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
-                            let expr4_0 = constructor_lower_shl128(ctx, expr0_0, expr3_0)?;
-                            let expr5_0 = C::output(ctx, expr4_0);
-                            return Some(expr5_0);
-                        }
-                        &Opcode::Ushr => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 748.
-                            let expr0_0 = C::put_in_regs(ctx, pattern7_0);
-                            let expr1_0 = C::put_in_regs(ctx, pattern7_1);
-                            let expr2_0: usize = 0;
-                            let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
-                            let expr4_0 = constructor_lower_ushr128(ctx, expr0_0, expr3_0)?;
-                            let expr5_0 = C::output(ctx, expr4_0);
-                            return Some(expr5_0);
-                        }
-                        &Opcode::Sshr => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 795.
-                            let expr0_0 = C::put_in_regs(ctx, pattern7_0);
-                            let expr1_0 = C::put_in_regs(ctx, pattern7_1);
-                            let expr2_0: usize = 0;
-                            let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
-                            let expr4_0 = constructor_lower_sshr128(ctx, expr0_0, expr3_0)?;
-                            let expr5_0 = C::output(ctx, expr4_0);
-                            return Some(expr5_0);
-                        }
-                        _ => {}
-                    }
-                }
-                &InstructionData::Unary {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Bnot => {
-                            // Rule at src/isa/aarch64/lower.isle line 569.
-                            let expr0_0 = C::put_in_regs(ctx, pattern5_1);
-                            let expr1_0: usize = 0;
-                            let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
-                            let expr3_0: usize = 1;
-                            let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
-                            let expr5_0: Type = I64;
-                            let expr6_0 = C::zero_reg(ctx);
-                            let expr7_0 = constructor_orr_not(ctx, expr5_0, expr6_0, expr2_0)?;
-                            let expr8_0: Type = I64;
-                            let expr9_0 = C::zero_reg(ctx);
-                            let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, expr4_0)?;
-                            let expr11_0 = C::value_regs(ctx, expr7_0, expr10_0);
-                            let expr12_0 = C::output(ctx, expr11_0);
-                            return Some(expr12_0);
-                        }
-                        &Opcode::Bitrev => {
-                            // Rule at src/isa/aarch64/lower.isle line 983.
-                            let expr0_0 = C::put_in_regs(ctx, pattern5_1);
-                            let expr1_0: Type = I64;
-                            let expr2_0: usize = 0;
-                            let expr3_0 = C::value_regs_get(ctx, expr0_0, expr2_0);
-                            let expr4_0 = constructor_rbit(ctx, expr1_0, expr3_0)?;
-                            let expr5_0: Type = I64;
-                            let expr6_0: usize = 1;
-                            let expr7_0 = C::value_regs_get(ctx, expr0_0, expr6_0);
-                            let expr8_0 = constructor_rbit(ctx, expr5_0, expr7_0)?;
-                            let expr9_0 = C::value_regs(ctx, expr8_0, expr4_0);
-                            let expr10_0 = C::output(ctx, expr9_0);
-                            return Some(expr10_0);
-                        }
-                        &Opcode::Clz => {
-                            // Rule at src/isa/aarch64/lower.isle line 1001.
-                            let expr0_0 = C::put_in_regs(ctx, pattern5_1);
-                            let expr1_0 = constructor_lower_clz128(ctx, expr0_0)?;
-                            let expr2_0 = C::output(ctx, expr1_0);
-                            return Some(expr2_0);
-                        }
-                        &Opcode::Cls => {
-                            // Rule at src/isa/aarch64/lower.isle line 1057.
-                            let expr0_0 = C::put_in_regs(ctx, pattern5_1);
-                            let expr1_0: usize = 0;
-                            let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
-                            let expr3_0: usize = 1;
-                            let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
-                            let expr5_0: Type = I64;
-                            let expr6_0 = constructor_a64_cls(ctx, expr5_0, expr2_0)?;
-                            let expr7_0: Type = I64;
-                            let expr8_0 = constructor_a64_cls(ctx, expr7_0, expr4_0)?;
-                            let expr9_0: Type = I64;
-                            let expr10_0 = constructor_eon(ctx, expr9_0, expr4_0, expr2_0)?;
-                            let expr11_0: Type = I64;
-                            let expr12_0: u8 = 63;
-                            let expr13_0 = C::imm_shift_from_u8(ctx, expr12_0);
-                            let expr14_0 = constructor_lsr_imm(ctx, expr11_0, expr10_0, expr13_0)?;
-                            let expr15_0 = constructor_madd64(ctx, expr6_0, expr14_0, expr14_0)?;
-                            let expr16_0: u8 = 63;
-                            let expr17_0 = C::u8_into_imm12(ctx, expr16_0);
-                            let expr18_0 = constructor_cmp64_imm(ctx, expr8_0, expr17_0)?;
-                            let expr19_0 = Cond::Eq;
-                            let expr20_0 = C::zero_reg(ctx);
-                            let expr21_0 = constructor_csel(ctx, &expr19_0, expr15_0, expr20_0)?;
-                            let expr22_0 = constructor_with_flags_reg(ctx, &expr18_0, &expr21_0)?;
-                            let expr23_0: Type = I64;
-                            let expr24_0 = constructor_add(ctx, expr23_0, expr22_0, expr8_0)?;
-                            let expr25_0: Type = I64;
-                            let expr26_0: u64 = 0;
-                            let expr27_0 = constructor_imm(ctx, expr25_0, expr26_0)?;
-                            let expr28_0 = C::value_regs(ctx, expr24_0, expr27_0);
-                            let expr29_0 = C::output(ctx, expr28_0);
-                            return Some(expr29_0);
-                        }
-                        &Opcode::Ctz => {
-                            // Rule at src/isa/aarch64/lower.isle line 1031.
-                            let expr0_0 = C::put_in_regs(ctx, pattern5_1);
-                            let expr1_0: Type = I64;
-                            let expr2_0: usize = 0;
-                            let expr3_0 = C::value_regs_get(ctx, expr0_0, expr2_0);
-                            let expr4_0 = constructor_rbit(ctx, expr1_0, expr3_0)?;
-                            let expr5_0: Type = I64;
-                            let expr6_0: usize = 1;
-                            let expr7_0 = C::value_regs_get(ctx, expr0_0, expr6_0);
-                            let expr8_0 = constructor_rbit(ctx, expr5_0, expr7_0)?;
-                            let expr9_0 = C::value_regs(ctx, expr8_0, expr4_0);
-                            let expr10_0 = constructor_lower_clz128(ctx, expr9_0)?;
-                            let expr11_0 = C::output(ctx, expr10_0);
-                            return Some(expr11_0);
-                        }
-                        &Opcode::Popcnt => {
-                            // Rule at src/isa/aarch64/lower.isle line 1117.
-                            let expr0_0 = C::put_in_regs(ctx, pattern5_1);
-                            let expr1_0: usize = 0;
-                            let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
-                            let expr3_0 = ScalarSize::Size64;
-                            let expr4_0 = constructor_mov_to_fpu(ctx, expr2_0, &expr3_0)?;
-                            let expr5_0: usize = 1;
-                            let expr6_0 = C::value_regs_get(ctx, expr0_0, expr5_0);
-                            let expr7_0: u8 = 1;
-                            let expr8_0 = VectorSize::Size64x2;
-                            let expr9_0 =
-                                constructor_mov_to_vec(ctx, expr4_0, expr6_0, expr7_0, &expr8_0)?;
-                            let expr10_0 = VectorSize::Size8x16;
-                            let expr11_0 = constructor_vec_cnt(ctx, expr9_0, &expr10_0)?;
-                            let expr12_0 = VectorSize::Size8x16;
-                            let expr13_0 = constructor_addv(ctx, expr11_0, &expr12_0)?;
-                            let expr14_0: u8 = 0;
-                            let expr15_0 = VectorSize::Size8x16;
-                            let expr16_0 =
-                                constructor_mov_from_vec(ctx, expr13_0, expr14_0, &expr15_0)?;
-                            let expr17_0: Type = I64;
-                            let expr18_0: u64 = 0;
-                            let expr19_0 = constructor_imm(ctx, expr17_0, expr18_0)?;
-                            let expr20_0 = C::value_regs(ctx, expr16_0, expr19_0);
-                            let expr21_0 = C::output(ctx, expr20_0);
-                            return Some(expr21_0);
-                        }
-                        &Opcode::Uextend => {
-                            if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
-                                let pattern8_0 = C::inst_data(ctx, pattern7_0);
-                                if let &InstructionData::BinaryImm8 {
-                                    opcode: ref pattern9_0,
-                                    arg: pattern9_1,
-                                    imm: pattern9_2,
-                                } = &pattern8_0
-                                {
-                                    if let &Opcode::Extractlane = pattern9_0 {
-                                        let pattern11_0 = C::value_type(ctx, pattern9_1);
-                                        let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
-                                        // Rule at src/isa/aarch64/lower.isle line 499.
-                                        let expr0_0 = C::put_in_reg(ctx, pattern9_1);
-                                        let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
-                                        let expr2_0 = constructor_mov_from_vec(
-                                            ctx,
-                                            expr0_0,
-                                            pattern12_0,
-                                            &expr1_0,
-                                        )?;
-                                        let expr3_0: Type = I64;
-                                        let expr4_0: u64 = 0;
-                                        let expr5_0 = constructor_imm(ctx, expr3_0, expr4_0)?;
-                                        let expr6_0 = C::value_regs(ctx, expr2_0, expr5_0);
-                                        let expr7_0 = C::output(ctx, expr6_0);
-                                        return Some(expr7_0);
-                                    }
-                                }
-                            }
-                            // Rule at src/isa/aarch64/lower.isle line 494.
-                            let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern5_1)?;
-                            let expr1_0: Type = I64;
-                            let expr2_0: u64 = 0;
-                            let expr3_0 = constructor_imm(ctx, expr1_0, expr2_0)?;
-                            let expr4_0 = C::value_regs(ctx, expr0_0, expr3_0);
-                            let expr5_0 = C::output(ctx, expr4_0);
-                            return Some(expr5_0);
-                        }
-                        &Opcode::Sextend => {
-                            if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
-                                let pattern8_0 = C::inst_data(ctx, pattern7_0);
-                                if let &InstructionData::BinaryImm8 {
-                                    opcode: ref pattern9_0,
-                                    arg: pattern9_1,
-                                    imm: pattern9_2,
-                                } = &pattern8_0
-                                {
-                                    if let &Opcode::Extractlane = pattern9_0 {
-                                        let pattern11_0 = C::value_type(ctx, pattern9_1);
-                                        if pattern11_0 == I64X2 {
-                                            let pattern13_0 = C::u8_from_uimm8(ctx, pattern9_2);
-                                            // Rule at src/isa/aarch64/lower.isle line 543.
-                                            let expr0_0 = C::put_in_reg(ctx, pattern9_1);
-                                            let expr1_0 = VectorSize::Size64x2;
-                                            let expr2_0 = constructor_mov_from_vec(
-                                                ctx,
-                                                expr0_0,
-                                                pattern13_0,
-                                                &expr1_0,
-                                            )?;
-                                            let expr3_0: Type = I64;
-                                            let expr4_0: u8 = 63;
-                                            let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
-                                            let expr6_0 = constructor_asr_imm(
-                                                ctx, expr3_0, expr2_0, expr5_0,
-                                            )?;
-                                            let expr7_0 = C::value_regs(ctx, expr2_0, expr6_0);
-                                            let expr8_0 = C::output(ctx, expr7_0);
-                                            return Some(expr8_0);
-                                        }
-                                        if let Some(()) = C::not_i64x2(ctx, pattern11_0) {
-                                            let pattern13_0 = C::u8_from_uimm8(ctx, pattern9_2);
-                                            // Rule at src/isa/aarch64/lower.isle line 532.
-                                            let expr0_0 = C::put_in_reg(ctx, pattern9_1);
-                                            let expr1_0 =
-                                                constructor_vector_size(ctx, pattern11_0)?;
-                                            let expr2_0: Type = I64;
-                                            let expr3_0 = constructor_size_from_ty(ctx, expr2_0)?;
-                                            let expr4_0 = constructor_mov_from_vec_signed(
-                                                ctx,
-                                                expr0_0,
-                                                pattern13_0,
-                                                &expr1_0,
-                                                &expr3_0,
-                                            )?;
-                                            let expr5_0: Type = I64;
-                                            let expr6_0: u8 = 63;
-                                            let expr7_0 = C::imm_shift_from_u8(ctx, expr6_0);
-                                            let expr8_0 = constructor_asr_imm(
-                                                ctx, expr5_0, expr4_0, expr7_0,
-                                            )?;
-                                            let expr9_0 = C::value_regs(ctx, expr4_0, expr8_0);
-                                            let expr10_0 = C::output(ctx, expr9_0);
-                                            return Some(expr10_0);
-                                        }
-                                    }
-                                }
-                            }
-                            // Rule at src/isa/aarch64/lower.isle line 522.
-                            let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern5_1)?;
-                            let expr1_0: Type = I64;
-                            let expr2_0: u8 = 63;
-                            let expr3_0 = C::imm_shift_from_u8(ctx, expr2_0);
-                            let expr4_0 = constructor_asr_imm(ctx, expr1_0, expr0_0, expr3_0)?;
-                            let expr5_0 = C::value_regs(ctx, expr0_0, expr4_0);
-                            let expr6_0 = C::output(ctx, expr5_0);
-                            return Some(expr6_0);
-                        }
-                        _ => {}
-                    }
-                }
-                _ => {}
-            }
-        }
-        if pattern2_0 == I8X16 {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            if let &InstructionData::Unary {
-                opcode: ref pattern5_0,
-                arg: pattern5_1,
-            } = &pattern4_0
-            {
-                if let &Opcode::Popcnt = pattern5_0 {
-                    // Rule at src/isa/aarch64/lower.isle line 1125.
-                    let expr0_0 = C::put_in_reg(ctx, pattern5_1);
-                    let expr1_0 = VectorSize::Size8x16;
-                    let expr2_0 = constructor_vec_cnt(ctx, expr0_0, &expr1_0)?;
-                    let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                    return Some(expr3_0);
-                }
-            }
-        }
-        if pattern2_0 == I16X8 {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            if let &InstructionData::Binary {
-                opcode: ref pattern5_0,
-                args: ref pattern5_1,
-            } = &pattern4_0
-            {
-                if let &Opcode::Imul = pattern5_0 {
-                    let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                    if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
-                        let pattern9_0 = C::inst_data(ctx, pattern8_0);
-                        if let &InstructionData::Unary {
-                            opcode: ref pattern10_0,
-                            arg: pattern10_1,
-                        } = &pattern9_0
-                        {
-                            match pattern10_0 {
-                                &Opcode::SwidenLow => {
-                                    let pattern12_0 = C::value_type(ctx, pattern10_1);
-                                    if pattern12_0 == I8X16 {
-                                        if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
-                                            let pattern15_0 = C::inst_data(ctx, pattern14_0);
-                                            if let &InstructionData::Unary {
-                                                opcode: ref pattern16_0,
-                                                arg: pattern16_1,
-                                            } = &pattern15_0
-                                            {
-                                                if let &Opcode::SwidenLow = pattern16_0 {
-                                                    let pattern18_0 =
-                                                        C::value_type(ctx, pattern16_1);
-                                                    if pattern18_0 == I8X16 {
-                                                        // Rule at src/isa/aarch64/lower.isle line 282.
-                                                        let expr0_0 =
-                                                            C::put_in_reg(ctx, pattern10_1);
-                                                        let expr1_0 =
-                                                            C::put_in_reg(ctx, pattern16_1);
-                                                        let expr2_0: bool = false;
-                                                        let expr3_0 = constructor_smull8(
-                                                            ctx, expr0_0, expr1_0, expr2_0,
-                                                        )?;
-                                                        let expr4_0 =
-                                                            constructor_output_reg(ctx, expr3_0)?;
-                                                        return Some(expr4_0);
-                                                    }
-                                                }
-                                            }
-                                        }
-                                    }
-                                }
-                                &Opcode::SwidenHigh => {
-                                    let pattern12_0 = C::value_type(ctx, pattern10_1);
-                                    if pattern12_0 == I8X16 {
-                                        if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
-                                            let pattern15_0 = C::inst_data(ctx, pattern14_0);
-                                            if let &InstructionData::Unary {
-                                                opcode: ref pattern16_0,
-                                                arg: pattern16_1,
-                                            } = &pattern15_0
-                                            {
-                                                if let &Opcode::SwidenHigh = pattern16_0 {
-                                                    let pattern18_0 =
-                                                        C::value_type(ctx, pattern16_1);
-                                                    if pattern18_0 == I8X16 {
-                                                        // Rule at src/isa/aarch64/lower.isle line 288.
-                                                        let expr0_0 =
-                                                            C::put_in_reg(ctx, pattern10_1);
-                                                        let expr1_0 =
-                                                            C::put_in_reg(ctx, pattern16_1);
-                                                        let expr2_0: bool = true;
-                                                        let expr3_0 = constructor_smull8(
-                                                            ctx, expr0_0, expr1_0, expr2_0,
-                                                        )?;
-                                                        let expr4_0 =
-                                                            constructor_output_reg(ctx, expr3_0)?;
-                                                        return Some(expr4_0);
-                                                    }
-                                                }
-                                            }
-                                        }
-                                    }
-                                }
-                                &Opcode::UwidenLow => {
-                                    let pattern12_0 = C::value_type(ctx, pattern10_1);
-                                    if pattern12_0 == I8X16 {
-                                        if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
-                                            let pattern15_0 = C::inst_data(ctx, pattern14_0);
-                                            if let &InstructionData::Unary {
-                                                opcode: ref pattern16_0,
-                                                arg: pattern16_1,
-                                            } = &pattern15_0
-                                            {
-                                                if let &Opcode::UwidenLow = pattern16_0 {
-                                                    let pattern18_0 =
-                                                        C::value_type(ctx, pattern16_1);
-                                                    if pattern18_0 == I8X16 {
-                                                        // Rule at src/isa/aarch64/lower.isle line 294.
-                                                        let expr0_0 =
-                                                            C::put_in_reg(ctx, pattern10_1);
-                                                        let expr1_0 =
-                                                            C::put_in_reg(ctx, pattern16_1);
-                                                        let expr2_0: bool = false;
-                                                        let expr3_0 = constructor_umull8(
-                                                            ctx, expr0_0, expr1_0, expr2_0,
-                                                        )?;
-                                                        let expr4_0 =
-                                                            constructor_output_reg(ctx, expr3_0)?;
-                                                        return Some(expr4_0);
-                                                    }
-                                                }
-                                            }
-                                        }
-                                    }
-                                }
-                                &Opcode::UwidenHigh => {
-                                    let pattern12_0 = C::value_type(ctx, pattern10_1);
-                                    if pattern12_0 == I8X16 {
-                                        if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
-                                            let pattern15_0 = C::inst_data(ctx, pattern14_0);
-                                            if let &InstructionData::Unary {
-                                                opcode: ref pattern16_0,
-                                                arg: pattern16_1,
-                                            } = &pattern15_0
-                                            {
-                                                if let &Opcode::UwidenHigh = pattern16_0 {
-                                                    let pattern18_0 =
-                                                        C::value_type(ctx, pattern16_1);
-                                                    if pattern18_0 == I8X16 {
-                                                        // Rule at src/isa/aarch64/lower.isle line 300.
-                                                        let expr0_0 =
-                                                            C::put_in_reg(ctx, pattern10_1);
-                                                        let expr1_0 =
-                                                            C::put_in_reg(ctx, pattern16_1);
-                                                        let expr2_0: bool = true;
-                                                        let expr3_0 = constructor_umull8(
-                                                            ctx, expr0_0, expr1_0, expr2_0,
-                                                        )?;
-                                                        let expr4_0 =
-                                                            constructor_output_reg(ctx, expr3_0)?;
-                                                        return Some(expr4_0);
-                                                    }
-                                                }
-                                            }
-                                        }
-                                    }
-                                }
-                                _ => {}
-                            }
-                        }
-                    }
-                }
-            }
-        }
-        if pattern2_0 == I32X4 {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            if let &InstructionData::Binary {
-                opcode: ref pattern5_0,
-                args: ref pattern5_1,
-            } = &pattern4_0
-            {
-                if let &Opcode::Imul = pattern5_0 {
-                    let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                    if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
-                        let pattern9_0 = C::inst_data(ctx, pattern8_0);
-                        if let &InstructionData::Unary {
-                            opcode: ref pattern10_0,
-                            arg: pattern10_1,
-                        } = &pattern9_0
-                        {
-                            match pattern10_0 {
-                                &Opcode::SwidenLow => {
-                                    let pattern12_0 = C::value_type(ctx, pattern10_1);
-                                    if pattern12_0 == I16X8 {
-                                        if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
-                                            let pattern15_0 = C::inst_data(ctx, pattern14_0);
-                                            if let &InstructionData::Unary {
-                                                opcode: ref pattern16_0,
-                                                arg: pattern16_1,
-                                            } = &pattern15_0
-                                            {
-                                                if let &Opcode::SwidenLow = pattern16_0 {
-                                                    let pattern18_0 =
-                                                        C::value_type(ctx, pattern16_1);
-                                                    if pattern18_0 == I16X8 {
-                                                        // Rule at src/isa/aarch64/lower.isle line 306.
-                                                        let expr0_0 =
-                                                            C::put_in_reg(ctx, pattern10_1);
-                                                        let expr1_0 =
-                                                            C::put_in_reg(ctx, pattern16_1);
-                                                        let expr2_0: bool = false;
-                                                        let expr3_0 = constructor_smull16(
-                                                            ctx, expr0_0, expr1_0, expr2_0,
-                                                        )?;
-                                                        let expr4_0 =
-                                                            constructor_output_reg(ctx, expr3_0)?;
-                                                        return Some(expr4_0);
-                                                    }
-                                                }
-                                            }
-                                        }
-                                    }
-                                }
-                                &Opcode::SwidenHigh => {
-                                    let pattern12_0 = C::value_type(ctx, pattern10_1);
-                                    if pattern12_0 == I16X8 {
-                                        if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
-                                            let pattern15_0 = C::inst_data(ctx, pattern14_0);
-                                            if let &InstructionData::Unary {
-                                                opcode: ref pattern16_0,
-                                                arg: pattern16_1,
-                                            } = &pattern15_0
-                                            {
-                                                if let &Opcode::SwidenHigh = pattern16_0 {
-                                                    let pattern18_0 =
-                                                        C::value_type(ctx, pattern16_1);
-                                                    if pattern18_0 == I16X8 {
-                                                        // Rule at src/isa/aarch64/lower.isle line 312.
-                                                        let expr0_0 =
-                                                            C::put_in_reg(ctx, pattern10_1);
-                                                        let expr1_0 =
-                                                            C::put_in_reg(ctx, pattern16_1);
-                                                        let expr2_0: bool = true;
-                                                        let expr3_0 = constructor_smull16(
-                                                            ctx, expr0_0, expr1_0, expr2_0,
-                                                        )?;
-                                                        let expr4_0 =
-                                                            constructor_output_reg(ctx, expr3_0)?;
-                                                        return Some(expr4_0);
-                                                    }
-                                                }
-                                            }
-                                        }
-                                    }
-                                }
-                                &Opcode::UwidenLow => {
-                                    let pattern12_0 = C::value_type(ctx, pattern10_1);
-                                    if pattern12_0 == I16X8 {
-                                        if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
-                                            let pattern15_0 = C::inst_data(ctx, pattern14_0);
-                                            if let &InstructionData::Unary {
-                                                opcode: ref pattern16_0,
-                                                arg: pattern16_1,
-                                            } = &pattern15_0
-                                            {
-                                                if let &Opcode::UwidenLow = pattern16_0 {
-                                                    let pattern18_0 =
-                                                        C::value_type(ctx, pattern16_1);
-                                                    if pattern18_0 == I16X8 {
-                                                        // Rule at src/isa/aarch64/lower.isle line 318.
-                                                        let expr0_0 =
-                                                            C::put_in_reg(ctx, pattern10_1);
-                                                        let expr1_0 =
-                                                            C::put_in_reg(ctx, pattern16_1);
-                                                        let expr2_0: bool = false;
-                                                        let expr3_0 = constructor_umull16(
-                                                            ctx, expr0_0, expr1_0, expr2_0,
-                                                        )?;
-                                                        let expr4_0 =
-                                                            constructor_output_reg(ctx, expr3_0)?;
-                                                        return Some(expr4_0);
-                                                    }
-                                                }
-                                            }
-                                        }
-                                    }
-                                }
-                                &Opcode::UwidenHigh => {
-                                    let pattern12_0 = C::value_type(ctx, pattern10_1);
-                                    if pattern12_0 == I16X8 {
-                                        if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
-                                            let pattern15_0 = C::inst_data(ctx, pattern14_0);
-                                            if let &InstructionData::Unary {
-                                                opcode: ref pattern16_0,
-                                                arg: pattern16_1,
-                                            } = &pattern15_0
-                                            {
-                                                if let &Opcode::UwidenHigh = pattern16_0 {
-                                                    let pattern18_0 =
-                                                        C::value_type(ctx, pattern16_1);
-                                                    if pattern18_0 == I16X8 {
-                                                        // Rule at src/isa/aarch64/lower.isle line 324.
-                                                        let expr0_0 =
-                                                            C::put_in_reg(ctx, pattern10_1);
-                                                        let expr1_0 =
-                                                            C::put_in_reg(ctx, pattern16_1);
-                                                        let expr2_0: bool = true;
-                                                        let expr3_0 = constructor_umull16(
-                                                            ctx, expr0_0, expr1_0, expr2_0,
-                                                        )?;
-                                                        let expr4_0 =
-                                                            constructor_output_reg(ctx, expr3_0)?;
-                                                        return Some(expr4_0);
-                                                    }
-                                                }
-                                            }
-                                        }
-                                    }
-                                }
-                                _ => {}
-                            }
-                        }
-                    }
-                }
-            }
-        }
-        if pattern2_0 == I64X2 {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            if let &InstructionData::Binary {
-                opcode: ref pattern5_0,
-                args: ref pattern5_1,
-            } = &pattern4_0
-            {
-                if let &Opcode::Imul = pattern5_0 {
-                    let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                    if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
-                        let pattern9_0 = C::inst_data(ctx, pattern8_0);
-                        if let &InstructionData::Unary {
-                            opcode: ref pattern10_0,
-                            arg: pattern10_1,
-                        } = &pattern9_0
-                        {
-                            match pattern10_0 {
-                                &Opcode::SwidenLow => {
-                                    let pattern12_0 = C::value_type(ctx, pattern10_1);
-                                    if pattern12_0 == I32X4 {
-                                        if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
-                                            let pattern15_0 = C::inst_data(ctx, pattern14_0);
-                                            if let &InstructionData::Unary {
-                                                opcode: ref pattern16_0,
-                                                arg: pattern16_1,
-                                            } = &pattern15_0
-                                            {
-                                                if let &Opcode::SwidenLow = pattern16_0 {
-                                                    let pattern18_0 =
-                                                        C::value_type(ctx, pattern16_1);
-                                                    if pattern18_0 == I32X4 {
-                                                        // Rule at src/isa/aarch64/lower.isle line 330.
-                                                        let expr0_0 =
-                                                            C::put_in_reg(ctx, pattern10_1);
-                                                        let expr1_0 =
-                                                            C::put_in_reg(ctx, pattern16_1);
-                                                        let expr2_0: bool = false;
-                                                        let expr3_0 = constructor_smull32(
-                                                            ctx, expr0_0, expr1_0, expr2_0,
-                                                        )?;
-                                                        let expr4_0 =
-                                                            constructor_output_reg(ctx, expr3_0)?;
-                                                        return Some(expr4_0);
-                                                    }
-                                                }
-                                            }
-                                        }
-                                    }
-                                }
-                                &Opcode::SwidenHigh => {
-                                    let pattern12_0 = C::value_type(ctx, pattern10_1);
-                                    if pattern12_0 == I32X4 {
-                                        if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
-                                            let pattern15_0 = C::inst_data(ctx, pattern14_0);
-                                            if let &InstructionData::Unary {
-                                                opcode: ref pattern16_0,
-                                                arg: pattern16_1,
-                                            } = &pattern15_0
-                                            {
-                                                if let &Opcode::SwidenHigh = pattern16_0 {
-                                                    let pattern18_0 =
-                                                        C::value_type(ctx, pattern16_1);
-                                                    if pattern18_0 == I32X4 {
-                                                        // Rule at src/isa/aarch64/lower.isle line 336.
-                                                        let expr0_0 =
-                                                            C::put_in_reg(ctx, pattern10_1);
-                                                        let expr1_0 =
-                                                            C::put_in_reg(ctx, pattern16_1);
-                                                        let expr2_0: bool = true;
-                                                        let expr3_0 = constructor_smull32(
-                                                            ctx, expr0_0, expr1_0, expr2_0,
-                                                        )?;
-                                                        let expr4_0 =
-                                                            constructor_output_reg(ctx, expr3_0)?;
-                                                        return Some(expr4_0);
-                                                    }
-                                                }
-                                            }
-                                        }
-                                    }
-                                }
-                                &Opcode::UwidenLow => {
-                                    let pattern12_0 = C::value_type(ctx, pattern10_1);
-                                    if pattern12_0 == I32X4 {
-                                        if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
-                                            let pattern15_0 = C::inst_data(ctx, pattern14_0);
-                                            if let &InstructionData::Unary {
-                                                opcode: ref pattern16_0,
-                                                arg: pattern16_1,
-                                            } = &pattern15_0
-                                            {
-                                                if let &Opcode::UwidenLow = pattern16_0 {
-                                                    let pattern18_0 =
-                                                        C::value_type(ctx, pattern16_1);
-                                                    if pattern18_0 == I32X4 {
-                                                        // Rule at src/isa/aarch64/lower.isle line 342.
-                                                        let expr0_0 =
-                                                            C::put_in_reg(ctx, pattern10_1);
-                                                        let expr1_0 =
-                                                            C::put_in_reg(ctx, pattern16_1);
-                                                        let expr2_0: bool = false;
-                                                        let expr3_0 = constructor_umull32(
-                                                            ctx, expr0_0, expr1_0, expr2_0,
-                                                        )?;
-                                                        let expr4_0 =
-                                                            constructor_output_reg(ctx, expr3_0)?;
-                                                        return Some(expr4_0);
-                                                    }
-                                                }
-                                            }
-                                        }
-                                    }
-                                }
-                                &Opcode::UwidenHigh => {
-                                    let pattern12_0 = C::value_type(ctx, pattern10_1);
-                                    if pattern12_0 == I32X4 {
-                                        if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
-                                            let pattern15_0 = C::inst_data(ctx, pattern14_0);
-                                            if let &InstructionData::Unary {
-                                                opcode: ref pattern16_0,
-                                                arg: pattern16_1,
-                                            } = &pattern15_0
-                                            {
-                                                if let &Opcode::UwidenHigh = pattern16_0 {
-                                                    let pattern18_0 =
-                                                        C::value_type(ctx, pattern16_1);
-                                                    if pattern18_0 == I32X4 {
-                                                        // Rule at src/isa/aarch64/lower.isle line 348.
-                                                        let expr0_0 =
-                                                            C::put_in_reg(ctx, pattern10_1);
-                                                        let expr1_0 =
-                                                            C::put_in_reg(ctx, pattern16_1);
-                                                        let expr2_0: bool = true;
-                                                        let expr3_0 = constructor_umull32(
-                                                            ctx, expr0_0, expr1_0, expr2_0,
-                                                        )?;
-                                                        let expr4_0 =
-                                                            constructor_output_reg(ctx, expr3_0)?;
-                                                        return Some(expr4_0);
-                                                    }
-                                                }
-                                            }
-                                        }
-                                    }
-                                }
-                                _ => {}
-                            }
-                        }
-                    }
-                    // Rule at src/isa/aarch64/lower.isle line 243.
-                    let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                    let expr1_0 = C::put_in_reg(ctx, pattern7_1);
-                    let expr2_0 = VectorSize::Size32x4;
-                    let expr3_0 = constructor_rev64(ctx, expr1_0, &expr2_0)?;
-                    let expr4_0 = VectorSize::Size32x4;
-                    let expr5_0 = constructor_mul(ctx, expr3_0, expr0_0, &expr4_0)?;
-                    let expr6_0: bool = false;
-                    let expr7_0 = constructor_xtn64(ctx, expr0_0, expr6_0)?;
-                    let expr8_0 = VectorSize::Size32x4;
-                    let expr9_0 = constructor_addp(ctx, expr5_0, expr5_0, &expr8_0)?;
-                    let expr10_0: bool = false;
-                    let expr11_0 = constructor_xtn64(ctx, expr1_0, expr10_0)?;
-                    let expr12_0: bool = false;
-                    let expr13_0 = constructor_shll32(ctx, expr9_0, expr12_0)?;
-                    let expr14_0: bool = false;
-                    let expr15_0 = constructor_umlal32(ctx, expr13_0, expr11_0, expr7_0, expr14_0)?;
-                    let expr16_0 = constructor_output_reg(ctx, expr15_0)?;
-                    return Some(expr16_0);
-                }
-            }
-        }
-        let pattern3_0 = C::inst_data(ctx, pattern0_0);
-        match &pattern3_0 {
-            &InstructionData::NullAry {
-                opcode: ref pattern4_0,
-            } => {
-                if let &Opcode::Null = pattern4_0 {
-                    // Rule at src/isa/aarch64/lower.isle line 22.
-                    let expr0_0: u64 = 0;
-                    let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
-                    let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                    return Some(expr2_0);
-                }
-            }
-            &InstructionData::UnaryImm {
-                opcode: ref pattern4_0,
-                imm: pattern4_1,
-            } => {
-                if let &Opcode::Iconst = pattern4_0 {
-                    let pattern6_0 = C::u64_from_imm64(ctx, pattern4_1);
-                    // Rule at src/isa/aarch64/lower.isle line 9.
-                    let expr0_0 = constructor_imm(ctx, pattern2_0, pattern6_0)?;
-                    let expr1_0 = constructor_output_reg(ctx, expr0_0)?;
-                    return Some(expr1_0);
-                }
-            }
-            &InstructionData::UnaryBool {
-                opcode: ref pattern4_0,
-                imm: pattern4_1,
-            } => {
-                if let &Opcode::Bconst = pattern4_0 {
-                    if pattern4_1 == true {
-                        // Rule at src/isa/aarch64/lower.isle line 17.
-                        let expr0_0: u64 = 1;
-                        let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
-                        let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                        return Some(expr2_0);
-                    }
-                    if pattern4_1 == false {
-                        // Rule at src/isa/aarch64/lower.isle line 14.
-                        let expr0_0: u64 = 0;
-                        let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
-                        let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                        return Some(expr2_0);
-                    }
-                }
-            }
-            &InstructionData::Unary {
-                opcode: ref pattern4_0,
-                arg: pattern4_1,
-            } => {
-                match pattern4_0 {
-                    &Opcode::Bitrev => {
-                        // Rule at src/isa/aarch64/lower.isle line 989.
-                        let expr0_0 = C::put_in_reg(ctx, pattern4_1);
-                        let expr1_0 = constructor_rbit(ctx, pattern2_0, expr0_0)?;
-                        let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                        return Some(expr2_0);
-                    }
-                    &Opcode::Clz => {
-                        // Rule at src/isa/aarch64/lower.isle line 1004.
-                        let expr0_0 = C::put_in_reg(ctx, pattern4_1);
-                        let expr1_0 = constructor_a64_clz(ctx, pattern2_0, expr0_0)?;
-                        let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                        return Some(expr2_0);
-                    }
-                    &Opcode::Cls => {
-                        // Rule at src/isa/aarch64/lower.isle line 1071.
-                        let expr0_0 = C::put_in_reg(ctx, pattern4_1);
-                        let expr1_0 = constructor_a64_cls(ctx, pattern2_0, expr0_0)?;
-                        let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                        return Some(expr2_0);
-                    }
-                    &Opcode::Ctz => {
-                        // Rule at src/isa/aarch64/lower.isle line 1037.
-                        let expr0_0 = C::put_in_reg(ctx, pattern4_1);
-                        let expr1_0 = constructor_rbit(ctx, pattern2_0, expr0_0)?;
-                        let expr2_0 = constructor_a64_clz(ctx, pattern2_0, expr1_0)?;
-                        let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                        return Some(expr3_0);
-                    }
-                    _ => {}
-                }
-            }
-            _ => {}
-        }
-        if let Some((pattern3_0, pattern3_1)) = C::multi_lane(ctx, pattern2_0) {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            if let &InstructionData::Binary {
-                opcode: ref pattern5_0,
-                args: ref pattern5_1,
-            } = &pattern4_0
-            {
-                match pattern5_0 {
-                    &Opcode::Iadd => {
-                        let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                        // Rule at src/isa/aarch64/lower.isle line 75.
-                        let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                        let expr1_0 = C::put_in_reg(ctx, pattern7_1);
-                        let expr2_0 = constructor_vector_size(ctx, pattern2_0)?;
-                        let expr3_0 = constructor_add_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
-                        let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                        return Some(expr4_0);
-                    }
-                    &Opcode::Isub => {
-                        let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                        // Rule at src/isa/aarch64/lower.isle line 125.
-                        let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                        let expr1_0 = C::put_in_reg(ctx, pattern7_1);
-                        let expr2_0 = constructor_vector_size(ctx, pattern2_0)?;
-                        let expr3_0 = constructor_sub_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
-                        let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                        return Some(expr4_0);
-                    }
-                    _ => {}
-                }
-            }
-        }
-        if let Some(pattern3_0) = C::fits_in_16(ctx, pattern2_0) {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            if let &InstructionData::Binary {
-                opcode: ref pattern5_0,
-                args: ref pattern5_1,
-            } = &pattern4_0
-            {
-                match pattern5_0 {
-                    &Opcode::Rotl => {
-                        let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                        if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
-                            let pattern9_0 = C::inst_data(ctx, pattern8_0);
-                            if let &InstructionData::UnaryImm {
-                                opcode: ref pattern10_0,
-                                imm: pattern10_1,
-                            } = &pattern9_0
-                            {
-                                if let &Opcode::Iconst = pattern10_0 {
-                                    let closure12 = || {
-                                        return Some(pattern3_0);
-                                    };
-                                    if let Some(pattern12_0) = closure12() {
-                                        if let Some(pattern13_0) =
-                                            C::imm_shift_from_imm64(ctx, pattern10_1, pattern12_0)
-                                        {
-                                            // Rule at src/isa/aarch64/lower.isle line 843.
-                                            let expr0_0 =
-                                                constructor_put_in_reg_zext32(ctx, pattern7_0)?;
-                                            let expr1_0 =
-                                                C::negate_imm_shift(ctx, pattern3_0, pattern13_0);
-                                            let expr2_0 = constructor_small_rotr_imm(
-                                                ctx, pattern3_0, expr0_0, expr1_0,
-                                            )?;
-                                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                            return Some(expr3_0);
-                                        }
-                                    }
-                                }
-                            }
-                        }
-                        // Rule at src/isa/aarch64/lower.isle line 838.
-                        let expr0_0: Type = I32;
-                        let expr1_0 = C::zero_reg(ctx);
-                        let expr2_0 = C::put_in_reg(ctx, pattern7_1);
-                        let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?;
-                        let expr4_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
-                        let expr5_0 = constructor_small_rotr(ctx, pattern3_0, expr4_0, expr3_0)?;
-                        let expr6_0 = constructor_output_reg(ctx, expr5_0)?;
-                        return Some(expr6_0);
-                    }
-                    &Opcode::Rotr => {
-                        let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                        if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
-                            let pattern9_0 = C::inst_data(ctx, pattern8_0);
-                            if let &InstructionData::UnaryImm {
-                                opcode: ref pattern10_0,
-                                imm: pattern10_1,
-                            } = &pattern9_0
-                            {
-                                if let &Opcode::Iconst = pattern10_0 {
-                                    let closure12 = || {
-                                        return Some(pattern3_0);
-                                    };
-                                    if let Some(pattern12_0) = closure12() {
-                                        if let Some(pattern13_0) =
-                                            C::imm_shift_from_imm64(ctx, pattern10_1, pattern12_0)
-                                        {
-                                            // Rule at src/isa/aarch64/lower.isle line 903.
-                                            let expr0_0 =
-                                                constructor_put_in_reg_zext32(ctx, pattern7_0)?;
-                                            let expr1_0 = constructor_small_rotr_imm(
-                                                ctx,
-                                                pattern3_0,
-                                                expr0_0,
-                                                pattern13_0,
-                                            )?;
-                                            let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                                            return Some(expr2_0);
-                                        }
-                                    }
-                                }
-                            }
-                        }
-                        // Rule at src/isa/aarch64/lower.isle line 891.
-                        let expr0_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
-                        let expr1_0 = C::put_in_reg(ctx, pattern7_1);
-                        let expr2_0 = constructor_small_rotr(ctx, pattern3_0, expr0_0, expr1_0)?;
-                        let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                        return Some(expr3_0);
-                    }
-                    _ => {}
-                }
-            }
-        }
-        if let Some(pattern3_0) = C::fits_in_32(ctx, pattern2_0) {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            if let &InstructionData::Binary {
-                opcode: ref pattern5_0,
-                args: ref pattern5_1,
-            } = &pattern4_0
-            {
-                match pattern5_0 {
-                    &Opcode::Umulhi => {
-                        let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                        // Rule at src/isa/aarch64/lower.isle line 370.
-                        let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
-                        let expr1_0 = constructor_put_in_reg_zext64(ctx, pattern7_1)?;
-                        let expr2_0 = C::zero_reg(ctx);
-                        let expr3_0 = constructor_madd64(ctx, expr0_0, expr1_0, expr2_0)?;
-                        let expr4_0: Type = I64;
-                        let expr5_0 = C::ty_bits(ctx, pattern3_0);
-                        let expr6_0 = C::imm_shift_from_u8(ctx, expr5_0);
-                        let expr7_0 = constructor_lsr_imm(ctx, expr4_0, expr3_0, expr6_0)?;
-                        let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
-                        return Some(expr8_0);
-                    }
-                    &Opcode::Smulhi => {
-                        let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                        // Rule at src/isa/aarch64/lower.isle line 358.
-                        let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
-                        let expr1_0 = constructor_put_in_reg_sext64(ctx, pattern7_1)?;
-                        let expr2_0 = C::zero_reg(ctx);
-                        let expr3_0 = constructor_madd64(ctx, expr0_0, expr1_0, expr2_0)?;
-                        let expr4_0: Type = I64;
-                        let expr5_0 = C::ty_bits(ctx, pattern3_0);
-                        let expr6_0 = C::imm_shift_from_u8(ctx, expr5_0);
-                        let expr7_0 = constructor_asr_imm(ctx, expr4_0, expr3_0, expr6_0)?;
-                        let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
-                        return Some(expr8_0);
-                    }
-                    &Opcode::Band => {
-                        let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                        // Rule at src/isa/aarch64/lower.isle line 583.
-                        let expr0_0 = ALUOp::And;
-                        let expr1_0 = constructor_alu_rs_imm_logic_commutative(
-                            ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
-                        )?;
-                        let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                        return Some(expr2_0);
-                    }
-                    &Opcode::Bor => {
-                        let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                        // Rule at src/isa/aarch64/lower.isle line 596.
-                        let expr0_0 = ALUOp::Orr;
-                        let expr1_0 = constructor_alu_rs_imm_logic_commutative(
-                            ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
-                        )?;
-                        let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                        return Some(expr2_0);
-                    }
-                    &Opcode::Bxor => {
-                        let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                        // Rule at src/isa/aarch64/lower.isle line 609.
-                        let expr0_0 = ALUOp::Eor;
-                        let expr1_0 = constructor_alu_rs_imm_logic_commutative(
-                            ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
-                        )?;
-                        let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                        return Some(expr2_0);
-                    }
-                    &Opcode::BandNot => {
-                        let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                        // Rule at src/isa/aarch64/lower.isle line 622.
-                        let expr0_0 = ALUOp::AndNot;
-                        let expr1_0 = constructor_alu_rs_imm_logic(
-                            ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
-                        )?;
-                        let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                        return Some(expr2_0);
-                    }
-                    &Opcode::BorNot => {
-                        let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                        // Rule at src/isa/aarch64/lower.isle line 635.
-                        let expr0_0 = ALUOp::OrrNot;
-                        let expr1_0 = constructor_alu_rs_imm_logic(
-                            ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
-                        )?;
-                        let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                        return Some(expr2_0);
-                    }
-                    &Opcode::BxorNot => {
-                        let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                        // Rule at src/isa/aarch64/lower.isle line 645.
-                        let expr0_0 = ALUOp::EorNot;
-                        let expr1_0: Type = I32;
-                        let expr2_0 = constructor_alu_rs_imm_logic(
-                            ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
-                        )?;
-                        let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                        return Some(expr3_0);
-                    }
-                    &Opcode::Ishl => {
-                        let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                        // Rule at src/isa/aarch64/lower.isle line 656.
-                        let expr0_0 = ALUOp::Lsl;
-                        let expr1_0 = C::put_in_reg(ctx, pattern7_0);
-                        let expr2_0 =
-                            constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
-                        let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                        return Some(expr3_0);
-                    }
-                    &Opcode::Ushr => {
-                        let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                        // Rule at src/isa/aarch64/lower.isle line 740.
-                        let expr0_0 = ALUOp::Lsr;
-                        let expr1_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
-                        let expr2_0 =
-                            constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
-                        let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                        return Some(expr3_0);
-                    }
-                    &Opcode::Sshr => {
-                        let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                        // Rule at src/isa/aarch64/lower.isle line 787.
-                        let expr0_0 = ALUOp::Asr;
-                        let expr1_0 = constructor_put_in_reg_sext32(ctx, pattern7_0)?;
-                        let expr2_0 =
-                            constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
-                        let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                        return Some(expr3_0);
-                    }
-                    _ => {}
-                }
-            }
-        }
-        if let Some(pattern3_0) = C::fits_in_64(ctx, pattern2_0) {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            match &pattern4_0 {
-                &InstructionData::Binary {
-                    opcode: ref pattern5_0,
-                    args: ref pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Iadd => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
-                                let pattern9_0 = C::inst_data(ctx, pattern8_0);
-                                match &pattern9_0 {
-                                    &InstructionData::UnaryImm {
-                                        opcode: ref pattern10_0,
-                                        imm: pattern10_1,
-                                    } => {
-                                        if let &Opcode::Iconst = pattern10_0 {
-                                            let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
-                                            if let Some(pattern13_0) =
-                                                C::imm12_from_u64(ctx, pattern12_0)
-                                            {
-                                                // Rule at src/isa/aarch64/lower.isle line 37.
-                                                let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                                let expr1_0 = constructor_add_imm(
-                                                    ctx,
-                                                    pattern3_0,
-                                                    expr0_0,
-                                                    pattern13_0,
-                                                )?;
-                                                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                                                return Some(expr2_0);
-                                            }
-                                            if let Some(pattern13_0) =
-                                                C::imm12_from_negated_u64(ctx, pattern12_0)
-                                            {
-                                                // Rule at src/isa/aarch64/lower.isle line 45.
-                                                let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                                let expr1_0 = constructor_sub_imm(
-                                                    ctx,
-                                                    pattern3_0,
-                                                    expr0_0,
-                                                    pattern13_0,
-                                                )?;
-                                                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                                                return Some(expr2_0);
-                                            }
-                                        }
-                                    }
-                                    &InstructionData::Binary {
-                                        opcode: ref pattern10_0,
-                                        args: ref pattern10_1,
-                                    } => {
-                                        match pattern10_0 {
-                                            &Opcode::Imul => {
-                                                let (pattern12_0, pattern12_1) =
-                                                    C::unpack_value_array_2(ctx, pattern10_1);
-                                                // Rule at src/isa/aarch64/lower.isle line 70.
-                                                let expr0_0 = C::put_in_reg(ctx, pattern12_0);
-                                                let expr1_0 = C::put_in_reg(ctx, pattern12_1);
-                                                let expr2_0 = C::put_in_reg(ctx, pattern7_1);
-                                                let expr3_0 = constructor_madd(
-                                                    ctx, pattern3_0, expr0_0, expr1_0, expr2_0,
-                                                )?;
-                                                let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                                                return Some(expr4_0);
-                                            }
-                                            &Opcode::Ishl => {
-                                                let (pattern12_0, pattern12_1) =
-                                                    C::unpack_value_array_2(ctx, pattern10_1);
-                                                if let Some(pattern13_0) =
-                                                    C::def_inst(ctx, pattern12_1)
-                                                {
-                                                    let pattern14_0 =
-                                                        C::inst_data(ctx, pattern13_0);
-                                                    if let &InstructionData::UnaryImm {
-                                                        opcode: ref pattern15_0,
-                                                        imm: pattern15_1,
-                                                    } = &pattern14_0
-                                                    {
-                                                        if let &Opcode::Iconst = pattern15_0 {
-                                                            let closure17 = || {
-                                                                return Some(pattern3_0);
-                                                            };
-                                                            if let Some(pattern17_0) = closure17() {
-                                                                if let Some(pattern18_0) =
-                                                                    C::lshl_from_imm64(
-                                                                        ctx,
-                                                                        pattern15_1,
-                                                                        pattern17_0,
-                                                                    )
-                                                                {
-                                                                    // Rule at src/isa/aarch64/lower.isle line 62.
-                                                                    let expr0_0 = C::put_in_reg(
-                                                                        ctx, pattern7_1,
-                                                                    );
-                                                                    let expr1_0 = C::put_in_reg(
-                                                                        ctx,
-                                                                        pattern12_0,
-                                                                    );
-                                                                    let expr2_0 =
-                                                                        constructor_add_shift(
-                                                                            ctx,
-                                                                            pattern3_0,
-                                                                            expr0_0,
-                                                                            expr1_0,
-                                                                            pattern18_0,
-                                                                        )?;
-                                                                    let expr3_0 =
-                                                                        constructor_output_reg(
-                                                                            ctx, expr2_0,
-                                                                        )?;
-                                                                    return Some(expr3_0);
-                                                                }
-                                                            }
-                                                        }
-                                                    }
-                                                }
-                                            }
-                                            _ => {}
-                                        }
-                                    }
-                                    _ => {}
-                                }
-                            }
-                            if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_0)
-                            {
-                                // Rule at src/isa/aarch64/lower.isle line 53.
-                                let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                let expr1_0 =
-                                    constructor_add_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
-                                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
-                                let pattern9_0 = C::inst_data(ctx, pattern8_0);
-                                match &pattern9_0 {
-                                    &InstructionData::UnaryImm {
-                                        opcode: ref pattern10_0,
-                                        imm: pattern10_1,
-                                    } => {
-                                        if let &Opcode::Iconst = pattern10_0 {
-                                            let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
-                                            if let Some(pattern13_0) =
-                                                C::imm12_from_u64(ctx, pattern12_0)
-                                            {
-                                                // Rule at src/isa/aarch64/lower.isle line 34.
-                                                let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                                let expr1_0 = constructor_add_imm(
-                                                    ctx,
-                                                    pattern3_0,
-                                                    expr0_0,
-                                                    pattern13_0,
-                                                )?;
-                                                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                                                return Some(expr2_0);
-                                            }
-                                            if let Some(pattern13_0) =
-                                                C::imm12_from_negated_u64(ctx, pattern12_0)
-                                            {
-                                                // Rule at src/isa/aarch64/lower.isle line 42.
-                                                let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                                let expr1_0 = constructor_sub_imm(
-                                                    ctx,
-                                                    pattern3_0,
-                                                    expr0_0,
-                                                    pattern13_0,
-                                                )?;
-                                                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                                                return Some(expr2_0);
-                                            }
-                                        }
-                                    }
-                                    &InstructionData::Binary {
-                                        opcode: ref pattern10_0,
-                                        args: ref pattern10_1,
-                                    } => {
-                                        match pattern10_0 {
-                                            &Opcode::Imul => {
-                                                let (pattern12_0, pattern12_1) =
-                                                    C::unpack_value_array_2(ctx, pattern10_1);
-                                                // Rule at src/isa/aarch64/lower.isle line 67.
-                                                let expr0_0 = C::put_in_reg(ctx, pattern12_0);
-                                                let expr1_0 = C::put_in_reg(ctx, pattern12_1);
-                                                let expr2_0 = C::put_in_reg(ctx, pattern7_0);
-                                                let expr3_0 = constructor_madd(
-                                                    ctx, pattern3_0, expr0_0, expr1_0, expr2_0,
-                                                )?;
-                                                let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                                                return Some(expr4_0);
-                                            }
-                                            &Opcode::Ishl => {
-                                                let (pattern12_0, pattern12_1) =
-                                                    C::unpack_value_array_2(ctx, pattern10_1);
-                                                if let Some(pattern13_0) =
-                                                    C::def_inst(ctx, pattern12_1)
-                                                {
-                                                    let pattern14_0 =
-                                                        C::inst_data(ctx, pattern13_0);
-                                                    if let &InstructionData::UnaryImm {
-                                                        opcode: ref pattern15_0,
-                                                        imm: pattern15_1,
-                                                    } = &pattern14_0
-                                                    {
-                                                        if let &Opcode::Iconst = pattern15_0 {
-                                                            let closure17 = || {
-                                                                return Some(pattern3_0);
-                                                            };
-                                                            if let Some(pattern17_0) = closure17() {
-                                                                if let Some(pattern18_0) =
-                                                                    C::lshl_from_imm64(
-                                                                        ctx,
-                                                                        pattern15_1,
-                                                                        pattern17_0,
-                                                                    )
-                                                                {
-                                                                    // Rule at src/isa/aarch64/lower.isle line 58.
-                                                                    let expr0_0 = C::put_in_reg(
-                                                                        ctx, pattern7_0,
-                                                                    );
-                                                                    let expr1_0 = C::put_in_reg(
-                                                                        ctx,
-                                                                        pattern12_0,
-                                                                    );
-                                                                    let expr2_0 =
-                                                                        constructor_add_shift(
-                                                                            ctx,
-                                                                            pattern3_0,
-                                                                            expr0_0,
-                                                                            expr1_0,
-                                                                            pattern18_0,
-                                                                        )?;
-                                                                    let expr3_0 =
-                                                                        constructor_output_reg(
-                                                                            ctx, expr2_0,
-                                                                        )?;
-                                                                    return Some(expr3_0);
-                                                                }
-                                                            }
-                                                        }
-                                                    }
-                                                }
-                                            }
-                                            _ => {}
-                                        }
-                                    }
-                                    _ => {}
-                                }
-                            }
-                            if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_1)
-                            {
-                                // Rule at src/isa/aarch64/lower.isle line 50.
-                                let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                let expr1_0 =
-                                    constructor_add_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
-                                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            // Rule at src/isa/aarch64/lower.isle line 30.
-                            let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                            let expr1_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr2_0 = constructor_add(ctx, pattern3_0, expr0_0, expr1_0)?;
-                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Isub => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
-                                let pattern9_0 = C::inst_data(ctx, pattern8_0);
-                                match &pattern9_0 {
-                                    &InstructionData::UnaryImm {
-                                        opcode: ref pattern10_0,
-                                        imm: pattern10_1,
-                                    } => {
-                                        if let &Opcode::Iconst = pattern10_0 {
-                                            let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
-                                            if let Some(pattern13_0) =
-                                                C::imm12_from_u64(ctx, pattern12_0)
-                                            {
-                                                // Rule at src/isa/aarch64/lower.isle line 105.
-                                                let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                                let expr1_0 = constructor_sub_imm(
-                                                    ctx,
-                                                    pattern3_0,
-                                                    expr0_0,
-                                                    pattern13_0,
-                                                )?;
-                                                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                                                return Some(expr2_0);
-                                            }
-                                            if let Some(pattern13_0) =
-                                                C::imm12_from_negated_u64(ctx, pattern12_0)
-                                            {
-                                                // Rule at src/isa/aarch64/lower.isle line 110.
-                                                let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                                let expr1_0 = constructor_add_imm(
-                                                    ctx,
-                                                    pattern3_0,
-                                                    expr0_0,
-                                                    pattern13_0,
-                                                )?;
-                                                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                                                return Some(expr2_0);
-                                            }
-                                        }
-                                    }
-                                    &InstructionData::Binary {
-                                        opcode: ref pattern10_0,
-                                        args: ref pattern10_1,
-                                    } => {
-                                        if let &Opcode::Ishl = pattern10_0 {
-                                            let (pattern12_0, pattern12_1) =
-                                                C::unpack_value_array_2(ctx, pattern10_1);
-                                            if let Some(pattern13_0) = C::def_inst(ctx, pattern12_1)
-                                            {
-                                                let pattern14_0 = C::inst_data(ctx, pattern13_0);
-                                                if let &InstructionData::UnaryImm {
-                                                    opcode: ref pattern15_0,
-                                                    imm: pattern15_1,
-                                                } = &pattern14_0
-                                                {
-                                                    if let &Opcode::Iconst = pattern15_0 {
-                                                        let closure17 = || {
-                                                            return Some(pattern3_0);
-                                                        };
-                                                        if let Some(pattern17_0) = closure17() {
-                                                            if let Some(pattern18_0) =
-                                                                C::lshl_from_imm64(
-                                                                    ctx,
-                                                                    pattern15_1,
-                                                                    pattern17_0,
-                                                                )
-                                                            {
-                                                                // Rule at src/isa/aarch64/lower.isle line 120.
-                                                                let expr0_0 =
-                                                                    C::put_in_reg(ctx, pattern7_0);
-                                                                let expr1_0 =
-                                                                    C::put_in_reg(ctx, pattern12_0);
-                                                                let expr2_0 =
-                                                                    constructor_sub_shift(
-                                                                        ctx,
-                                                                        pattern3_0,
-                                                                        expr0_0,
-                                                                        expr1_0,
-                                                                        pattern18_0,
-                                                                    )?;
-                                                                let expr3_0 =
-                                                                    constructor_output_reg(
-                                                                        ctx, expr2_0,
-                                                                    )?;
-                                                                return Some(expr3_0);
-                                                            }
-                                                        }
-                                                    }
-                                                }
-                                            }
-                                        }
-                                    }
-                                    _ => {}
-                                }
-                            }
-                            if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_1)
-                            {
-                                // Rule at src/isa/aarch64/lower.isle line 115.
-                                let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                let expr1_0 =
-                                    constructor_sub_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
-                                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            // Rule at src/isa/aarch64/lower.isle line 101.
-                            let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                            let expr1_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr2_0 = constructor_sub(ctx, pattern3_0, expr0_0, expr1_0)?;
-                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Imul => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 179.
-                            let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                            let expr1_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr2_0 = C::zero_reg(ctx);
-                            let expr3_0 =
-                                constructor_madd(ctx, pattern3_0, expr0_0, expr1_0, expr2_0)?;
-                            let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                            return Some(expr4_0);
-                        }
-                        &Opcode::Udiv => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 384.
-                            let expr0_0: Type = I64;
-                            let expr1_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
-                            let expr2_0 = constructor_put_nonzero_in_reg_zext64(ctx, pattern7_1)?;
-                            let expr3_0 = constructor_a64_udiv(ctx, expr0_0, expr1_0, expr2_0)?;
-                            let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                            return Some(expr4_0);
-                        }
-                        &Opcode::Sdiv => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
-                                let pattern9_0 = C::inst_data(ctx, pattern8_0);
-                                if let &InstructionData::UnaryImm {
-                                    opcode: ref pattern10_0,
-                                    imm: pattern10_1,
-                                } = &pattern9_0
-                                {
-                                    if let &Opcode::Iconst = pattern10_0 {
-                                        if let Some(pattern12_0) =
-                                            C::safe_divisor_from_imm64(ctx, pattern10_1)
-                                        {
-                                            // Rule at src/isa/aarch64/lower.isle line 430.
-                                            let expr0_0: Type = I64;
-                                            let expr1_0 =
-                                                constructor_put_in_reg_sext64(ctx, pattern7_0)?;
-                                            let expr2_0 =
-                                                constructor_imm(ctx, pattern3_0, pattern12_0)?;
-                                            let expr3_0 = constructor_a64_sdiv(
-                                                ctx, expr0_0, expr1_0, expr2_0,
-                                            )?;
-                                            let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                                            return Some(expr4_0);
-                                        }
-                                    }
-                                }
-                            }
-                            // Rule at src/isa/aarch64/lower.isle line 417.
-                            let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_nonzero_in_reg_sext64(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_trap_if_div_overflow(
-                                ctx, pattern3_0, expr0_0, expr1_0,
-                            )?;
-                            let expr3_0: Type = I64;
-                            let expr4_0 = constructor_a64_sdiv(ctx, expr3_0, expr2_0, expr1_0)?;
-                            let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
-                            return Some(expr5_0);
-                        }
-                        &Opcode::Urem => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 458.
-                            let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_nonzero_in_reg_zext64(ctx, pattern7_1)?;
-                            let expr2_0: Type = I64;
-                            let expr3_0 = constructor_a64_udiv(ctx, expr2_0, expr0_0, expr1_0)?;
-                            let expr4_0 = constructor_msub64(ctx, expr3_0, expr1_0, expr0_0)?;
-                            let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
-                            return Some(expr5_0);
-                        }
-                        &Opcode::Srem => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 465.
-                            let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_nonzero_in_reg_sext64(ctx, pattern7_1)?;
-                            let expr2_0: Type = I64;
-                            let expr3_0 = constructor_a64_sdiv(ctx, expr2_0, expr0_0, expr1_0)?;
-                            let expr4_0 = constructor_msub64(ctx, expr3_0, expr1_0, expr0_0)?;
-                            let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
-                            return Some(expr5_0);
-                        }
-                        _ => {}
-                    }
-                }
-                &InstructionData::Unary {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Ineg => {
-                            // Rule at src/isa/aarch64/lower.isle line 169.
-                            let expr0_0 = C::zero_reg(ctx);
-                            let expr1_0 = C::put_in_reg(ctx, pattern5_1);
-                            let expr2_0 = constructor_sub(ctx, pattern3_0, expr0_0, expr1_0)?;
-                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Bnot => {
-                            if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
-                                let pattern8_0 = C::inst_data(ctx, pattern7_0);
-                                if let &InstructionData::Binary {
-                                    opcode: ref pattern9_0,
-                                    args: ref pattern9_1,
-                                } = &pattern8_0
-                                {
-                                    if let &Opcode::Ishl = pattern9_0 {
-                                        let (pattern11_0, pattern11_1) =
-                                            C::unpack_value_array_2(ctx, pattern9_1);
-                                        if let Some(pattern12_0) = C::def_inst(ctx, pattern11_1) {
-                                            let pattern13_0 = C::inst_data(ctx, pattern12_0);
-                                            if let &InstructionData::UnaryImm {
-                                                opcode: ref pattern14_0,
-                                                imm: pattern14_1,
-                                            } = &pattern13_0
-                                            {
-                                                if let &Opcode::Iconst = pattern14_0 {
-                                                    let closure16 = || {
-                                                        return Some(pattern3_0);
-                                                    };
-                                                    if let Some(pattern16_0) = closure16() {
-                                                        if let Some(pattern17_0) =
-                                                            C::lshl_from_imm64(
-                                                                ctx,
-                                                                pattern14_1,
-                                                                pattern16_0,
-                                                            )
-                                                        {
-                                                            // Rule at src/isa/aarch64/lower.isle line 564.
-                                                            let expr0_0 = C::zero_reg(ctx);
-                                                            let expr1_0 =
-                                                                C::put_in_reg(ctx, pattern11_0);
-                                                            let expr2_0 =
-                                                                constructor_orr_not_shift(
-                                                                    ctx,
-                                                                    pattern3_0,
-                                                                    expr0_0,
-                                                                    expr1_0,
-                                                                    pattern17_0,
-                                                                )?;
-                                                            let expr3_0 = constructor_output_reg(
-                                                                ctx, expr2_0,
-                                                            )?;
-                                                            return Some(expr3_0);
-                                                        }
-                                                    }
-                                                }
-                                            }
-                                        }
-                                    }
-                                }
-                            }
-                            // Rule at src/isa/aarch64/lower.isle line 559.
-                            let expr0_0 = C::zero_reg(ctx);
-                            let expr1_0 = C::put_in_reg(ctx, pattern5_1);
-                            let expr2_0 = constructor_orr_not(ctx, pattern3_0, expr0_0, expr1_0)?;
-                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Uextend => {
-                            if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
-                                let pattern8_0 = C::inst_data(ctx, pattern7_0);
-                                if let &InstructionData::BinaryImm8 {
-                                    opcode: ref pattern9_0,
-                                    arg: pattern9_1,
-                                    imm: pattern9_2,
-                                } = &pattern8_0
-                                {
-                                    if let &Opcode::Extractlane = pattern9_0 {
-                                        let pattern11_0 = C::value_type(ctx, pattern9_1);
-                                        let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
-                                        // Rule at src/isa/aarch64/lower.isle line 481.
-                                        let expr0_0 = C::put_in_reg(ctx, pattern9_1);
-                                        let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
-                                        let expr2_0 = constructor_mov_from_vec(
-                                            ctx,
-                                            expr0_0,
-                                            pattern12_0,
-                                            &expr1_0,
-                                        )?;
-                                        let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                        return Some(expr3_0);
-                                    }
-                                }
-                            }
-                            let pattern7_0 = C::value_type(ctx, pattern5_1);
-                            if let Some(pattern8_0) = C::sinkable_atomic_load(ctx, pattern5_1) {
-                                // Rule at src/isa/aarch64/lower.isle line 488.
-                                let expr0_0 = C::sink_atomic_load(ctx, &pattern8_0);
-                                let expr1_0 = constructor_load_acquire(ctx, pattern7_0, expr0_0)?;
-                                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            // Rule at src/isa/aarch64/lower.isle line 476.
-                            let expr0_0 = C::put_in_reg(ctx, pattern5_1);
-                            let expr1_0: bool = false;
-                            let expr2_0 = C::ty_bits(ctx, pattern7_0);
-                            let expr3_0 = C::ty_bits(ctx, pattern3_0);
-                            let expr4_0 =
-                                constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
-                            let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
-                            return Some(expr5_0);
-                        }
-                        &Opcode::Sextend => {
-                            if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
-                                let pattern8_0 = C::inst_data(ctx, pattern7_0);
-                                if let &InstructionData::BinaryImm8 {
-                                    opcode: ref pattern9_0,
-                                    arg: pattern9_1,
-                                    imm: pattern9_2,
-                                } = &pattern8_0
-                                {
-                                    if let &Opcode::Extractlane = pattern9_0 {
-                                        let pattern11_0 = C::value_type(ctx, pattern9_1);
-                                        let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
-                                        // Rule at src/isa/aarch64/lower.isle line 513.
-                                        let expr0_0 = C::put_in_reg(ctx, pattern9_1);
-                                        let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
-                                        let expr2_0 = constructor_size_from_ty(ctx, pattern3_0)?;
-                                        let expr3_0 = constructor_mov_from_vec_signed(
-                                            ctx,
-                                            expr0_0,
-                                            pattern12_0,
-                                            &expr1_0,
-                                            &expr2_0,
-                                        )?;
-                                        let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                                        return Some(expr4_0);
-                                    }
-                                }
-                            }
-                            let pattern7_0 = C::value_type(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 508.
-                            let expr0_0 = C::put_in_reg(ctx, pattern5_1);
-                            let expr1_0: bool = true;
-                            let expr2_0 = C::ty_bits(ctx, pattern7_0);
-                            let expr3_0 = C::ty_bits(ctx, pattern3_0);
-                            let expr4_0 =
-                                constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
-                            let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
-                            return Some(expr5_0);
-                        }
-                        _ => {}
-                    }
-                }
-                _ => {}
-            }
-        }
-        if let Some(pattern3_0) = C::vec128(ctx, pattern2_0) {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            match &pattern4_0 {
-                &InstructionData::Binary {
-                    opcode: ref pattern5_0,
-                    args: ref pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::UaddSat => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 148.
-                            let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                            let expr1_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
-                            let expr3_0 = constructor_uqadd(ctx, expr0_0, expr1_0, &expr2_0)?;
-                            let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                            return Some(expr4_0);
-                        }
-                        &Opcode::SaddSat => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 153.
-                            let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                            let expr1_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
-                            let expr3_0 = constructor_sqadd(ctx, expr0_0, expr1_0, &expr2_0)?;
-                            let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                            return Some(expr4_0);
-                        }
-                        &Opcode::UsubSat => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 158.
-                            let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                            let expr1_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
-                            let expr3_0 = constructor_uqsub(ctx, expr0_0, expr1_0, &expr2_0)?;
-                            let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                            return Some(expr4_0);
-                        }
-                        &Opcode::SsubSat => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 163.
-                            let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                            let expr1_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
-                            let expr3_0 = constructor_sqsub(ctx, expr0_0, expr1_0, &expr2_0)?;
-                            let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                            return Some(expr4_0);
-                        }
-                        &Opcode::Band => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 591.
-                            let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                            let expr1_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
-                            let expr3_0 = constructor_and_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
-                            let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                            return Some(expr4_0);
-                        }
-                        &Opcode::Bor => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 604.
-                            let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                            let expr1_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
-                            let expr3_0 = constructor_orr_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
-                            let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                            return Some(expr4_0);
-                        }
-                        &Opcode::Bxor => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 617.
-                            let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                            let expr1_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
-                            let expr3_0 = constructor_eor_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
-                            let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                            return Some(expr4_0);
-                        }
-                        &Opcode::BandNot => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 630.
-                            let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                            let expr1_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
-                            let expr3_0 = constructor_bic_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
-                            let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                            return Some(expr4_0);
-                        }
-                        &Opcode::Ishl => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 694.
-                            let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
-                            let expr1_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr2_0 = constructor_vec_dup(ctx, expr1_0, &expr0_0)?;
-                            let expr3_0 = C::put_in_reg(ctx, pattern7_0);
-                            let expr4_0 = constructor_sshl(ctx, expr3_0, expr2_0, &expr0_0)?;
-                            let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
-                            return Some(expr5_0);
-                        }
-                        &Opcode::Ushr => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 752.
-                            let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
-                            let expr1_0: Type = I32;
-                            let expr2_0 = C::zero_reg(ctx);
-                            let expr3_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr4_0 = constructor_sub(ctx, expr1_0, expr2_0, expr3_0)?;
-                            let expr5_0 = constructor_vec_dup(ctx, expr4_0, &expr0_0)?;
-                            let expr6_0 = C::put_in_reg(ctx, pattern7_0);
-                            let expr7_0 = constructor_ushl(ctx, expr6_0, expr5_0, &expr0_0)?;
-                            let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
-                            return Some(expr8_0);
-                        }
-                        &Opcode::Sshr => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/aarch64/lower.isle line 801.
-                            let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
-                            let expr1_0: Type = I32;
-                            let expr2_0 = C::zero_reg(ctx);
-                            let expr3_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr4_0 = constructor_sub(ctx, expr1_0, expr2_0, expr3_0)?;
-                            let expr5_0 = constructor_vec_dup(ctx, expr4_0, &expr0_0)?;
-                            let expr6_0 = C::put_in_reg(ctx, pattern7_0);
-                            let expr7_0 = constructor_sshl(ctx, expr6_0, expr5_0, &expr0_0)?;
-                            let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
-                            return Some(expr8_0);
-                        }
-                        _ => {}
-                    }
-                }
-                &InstructionData::Unary {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Ineg => {
-                            // Rule at src/isa/aarch64/lower.isle line 173.
-                            let expr0_0 = C::put_in_reg(ctx, pattern5_1);
-                            let expr1_0 = constructor_vector_size(ctx, pattern3_0)?;
-                            let expr2_0 = constructor_neg(ctx, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Bnot => {
-                            // Rule at src/isa/aarch64/lower.isle line 578.
-                            let expr0_0 = C::put_in_reg(ctx, pattern5_1);
-                            let expr1_0 = constructor_vector_size(ctx, pattern3_0)?;
-                            let expr2_0 = constructor_not(ctx, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        _ => {}
-                    }
-                }
-                _ => {}
-            }
-            if let Some(()) = C::not_i64x2(ctx, pattern3_0) {
-                let pattern5_0 = C::inst_data(ctx, pattern0_0);
-                if let &InstructionData::Binary {
-                    opcode: ref pattern6_0,
-                    args: ref pattern6_1,
-                } = &pattern5_0
-                {
-                    if let &Opcode::Imul = pattern6_0 {
-                        let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
-                        // Rule at src/isa/aarch64/lower.isle line 211.
-                        let expr0_0 = C::put_in_reg(ctx, pattern8_0);
-                        let expr1_0 = C::put_in_reg(ctx, pattern8_1);
-                        let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
-                        let expr3_0 = constructor_mul(ctx, expr0_0, expr1_0, &expr2_0)?;
-                        let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                        return Some(expr4_0);
-                    }
-                }
-            }
-        }
-    }
-    return None;
-}
-
-// Generated as internal constructor for term put_nonzero_in_reg_zext64.
-pub fn constructor_put_nonzero_in_reg_zext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = C::value_type(ctx, pattern0_0);
-    if let Some(pattern2_0) = C::def_inst(ctx, pattern0_0) {
-        let pattern3_0 = C::inst_data(ctx, pattern2_0);
-        if let &InstructionData::UnaryImm {
-            opcode: ref pattern4_0,
-            imm: pattern4_1,
-        } = &pattern3_0
-        {
-            if let &Opcode::Iconst = pattern4_0 {
-                if let Some(pattern6_0) = C::nonzero_u64_from_imm64(ctx, pattern4_1) {
-                    // Rule at src/isa/aarch64/lower.isle line 394.
-                    let expr0_0 = constructor_imm(ctx, pattern1_0, pattern6_0)?;
-                    return Some(expr0_0);
-                }
-            }
-        }
-    }
-    // Rule at src/isa/aarch64/lower.isle line 389.
-    let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern0_0)?;
-    let expr1_0 = constructor_trap_if_zero_divisor(ctx, expr0_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term put_nonzero_in_reg_sext64.
-pub fn constructor_put_nonzero_in_reg_sext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = C::value_type(ctx, pattern0_0);
-    if let Some(pattern2_0) = C::def_inst(ctx, pattern0_0) {
-        let pattern3_0 = C::inst_data(ctx, pattern2_0);
-        if let &InstructionData::UnaryImm {
-            opcode: ref pattern4_0,
-            imm: pattern4_1,
-        } = &pattern3_0
-        {
-            if let &Opcode::Iconst = pattern4_0 {
-                if let Some(pattern6_0) = C::nonzero_u64_from_imm64(ctx, pattern4_1) {
-                    // Rule at src/isa/aarch64/lower.isle line 440.
-                    let expr0_0 = constructor_imm(ctx, pattern1_0, pattern6_0)?;
-                    return Some(expr0_0);
-                }
-            }
-        }
-    }
-    // Rule at src/isa/aarch64/lower.isle line 435.
-    let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern0_0)?;
-    let expr1_0 = constructor_trap_if_zero_divisor(ctx, expr0_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term lower_shl128.
-pub fn constructor_lower_shl128<C: Context>(
-    ctx: &mut C,
-    arg0: ValueRegs,
-    arg1: Reg,
-) -> Option<ValueRegs> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/aarch64/lower.isle line 677.
-    let expr0_0: usize = 0;
-    let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
-    let expr2_0: usize = 1;
-    let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
-    let expr4_0: Type = I64;
-    let expr5_0 = constructor_lsl(ctx, expr4_0, expr1_0, pattern1_0)?;
-    let expr6_0: Type = I64;
-    let expr7_0 = constructor_lsl(ctx, expr6_0, expr3_0, pattern1_0)?;
-    let expr8_0: Type = I32;
-    let expr9_0 = C::zero_reg(ctx);
-    let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?;
-    let expr11_0: Type = I64;
-    let expr12_0: Type = I64;
-    let expr13_0: u8 = 1;
-    let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0);
-    let expr15_0 = constructor_lsr_imm(ctx, expr12_0, expr1_0, expr14_0)?;
-    let expr16_0 = constructor_lsr(ctx, expr11_0, expr15_0, expr10_0)?;
-    let expr17_0: Type = I64;
-    let expr18_0 = constructor_orr(ctx, expr17_0, expr7_0, expr16_0)?;
-    let expr19_0: Type = I64;
-    let expr20_0: Type = I64;
-    let expr21_0: u64 = 64;
-    let expr22_0 = C::u64_into_imm_logic(ctx, expr20_0, expr21_0);
-    let expr23_0 = constructor_tst_imm(ctx, expr19_0, pattern1_0, expr22_0)?;
-    let expr24_0 = Cond::Ne;
-    let expr25_0 = C::zero_reg(ctx);
-    let expr26_0 = constructor_csel(ctx, &expr24_0, expr25_0, expr5_0)?;
-    let expr27_0 = Cond::Ne;
-    let expr28_0 = constructor_csel(ctx, &expr27_0, expr5_0, expr18_0)?;
-    let expr29_0 = constructor_consumes_flags_concat(ctx, &expr26_0, &expr28_0)?;
-    let expr30_0 = constructor_with_flags(ctx, &expr23_0, &expr29_0)?;
-    return Some(expr30_0);
-}
-
-// Generated as internal constructor for term do_shift.
-pub fn constructor_do_shift<C: Context>(
-    ctx: &mut C,
-    arg0: &ALUOp,
-    arg1: Type,
-    arg2: Reg,
-    arg3: Value,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
-        let pattern5_0 = C::inst_data(ctx, pattern4_0);
-        if let &InstructionData::UnaryImm {
-            opcode: ref pattern6_0,
-            imm: pattern6_1,
-        } = &pattern5_0
-        {
-            if let &Opcode::Iconst = pattern6_0 {
-                let closure8 = || {
-                    return Some(pattern1_0);
-                };
-                if let Some(pattern8_0) = closure8() {
-                    if let Some(pattern9_0) = C::imm_shift_from_imm64(ctx, pattern6_1, pattern8_0) {
-                        // Rule at src/isa/aarch64/lower.isle line 734.
-                        let expr0_0 = constructor_alu_rr_imm_shift(
-                            ctx, pattern0_0, pattern1_0, pattern2_0, pattern9_0,
-                        )?;
-                        return Some(expr0_0);
-                    }
-                }
-            }
-        }
-    }
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    if pattern1_0 == I32 {
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/aarch64/lower.isle line 725.
-        let expr0_0: Type = I32;
-        let expr1_0 = C::put_in_regs(ctx, pattern4_0);
-        let expr2_0: usize = 0;
-        let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
-        let expr4_0 = constructor_alu_rrr(ctx, pattern0_0, expr0_0, pattern3_0, expr3_0)?;
-        return Some(expr4_0);
-    }
-    if pattern1_0 == I64 {
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/aarch64/lower.isle line 726.
-        let expr0_0: Type = I64;
-        let expr1_0 = C::put_in_regs(ctx, pattern4_0);
-        let expr2_0: usize = 0;
-        let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
-        let expr4_0 = constructor_alu_rrr(ctx, pattern0_0, expr0_0, pattern3_0, expr3_0)?;
-        return Some(expr4_0);
-    }
-    if let Some(pattern2_0) = C::fits_in_16(ctx, pattern1_0) {
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/aarch64/lower.isle line 716.
-        let expr0_0 = C::put_in_regs(ctx, pattern4_0);
-        let expr1_0: usize = 0;
-        let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
-        let expr3_0: Type = I32;
-        let expr4_0 = C::shift_mask(ctx, pattern2_0);
-        let expr5_0 = constructor_and_imm(ctx, expr3_0, expr2_0, expr4_0)?;
-        let expr6_0: Type = I32;
-        let expr7_0 = constructor_alu_rrr(ctx, pattern0_0, expr6_0, pattern3_0, expr5_0)?;
-        return Some(expr7_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term lower_ushr128.
-pub fn constructor_lower_ushr128<C: Context>(
-    ctx: &mut C,
-    arg0: ValueRegs,
-    arg1: Reg,
-) -> Option<ValueRegs> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/aarch64/lower.isle line 767.
-    let expr0_0: usize = 0;
-    let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
-    let expr2_0: usize = 1;
-    let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
-    let expr4_0: Type = I64;
-    let expr5_0 = constructor_lsr(ctx, expr4_0, expr1_0, pattern1_0)?;
-    let expr6_0: Type = I64;
-    let expr7_0 = constructor_lsr(ctx, expr6_0, expr3_0, pattern1_0)?;
-    let expr8_0: Type = I32;
-    let expr9_0 = C::zero_reg(ctx);
-    let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?;
-    let expr11_0: Type = I64;
-    let expr12_0: Type = I64;
-    let expr13_0: u8 = 1;
-    let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0);
-    let expr15_0 = constructor_lsl_imm(ctx, expr12_0, expr3_0, expr14_0)?;
-    let expr16_0 = constructor_lsl(ctx, expr11_0, expr15_0, expr10_0)?;
-    let expr17_0: Type = I64;
-    let expr18_0 = constructor_orr(ctx, expr17_0, expr5_0, expr16_0)?;
-    let expr19_0: Type = I64;
-    let expr20_0: Type = I64;
-    let expr21_0: u64 = 64;
-    let expr22_0 = C::u64_into_imm_logic(ctx, expr20_0, expr21_0);
-    let expr23_0 = constructor_tst_imm(ctx, expr19_0, pattern1_0, expr22_0)?;
-    let expr24_0 = Cond::Ne;
-    let expr25_0 = constructor_csel(ctx, &expr24_0, expr7_0, expr18_0)?;
-    let expr26_0 = Cond::Ne;
-    let expr27_0 = C::zero_reg(ctx);
-    let expr28_0 = constructor_csel(ctx, &expr26_0, expr27_0, expr7_0)?;
-    let expr29_0 = constructor_consumes_flags_concat(ctx, &expr25_0, &expr28_0)?;
-    let expr30_0 = constructor_with_flags(ctx, &expr23_0, &expr29_0)?;
-    return Some(expr30_0);
-}
-
-// Generated as internal constructor for term lower_sshr128.
-pub fn constructor_lower_sshr128<C: Context>(
-    ctx: &mut C,
-    arg0: ValueRegs,
-    arg1: Reg,
-) -> Option<ValueRegs> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/aarch64/lower.isle line 817.
-    let expr0_0: usize = 0;
-    let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
-    let expr2_0: usize = 1;
-    let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
-    let expr4_0: Type = I64;
-    let expr5_0 = constructor_lsr(ctx, expr4_0, expr1_0, pattern1_0)?;
-    let expr6_0: Type = I64;
-    let expr7_0 = constructor_asr(ctx, expr6_0, expr3_0, pattern1_0)?;
-    let expr8_0: Type = I32;
-    let expr9_0 = C::zero_reg(ctx);
-    let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?;
-    let expr11_0: Type = I64;
-    let expr12_0: Type = I64;
-    let expr13_0: u8 = 1;
-    let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0);
-    let expr15_0 = constructor_lsl_imm(ctx, expr12_0, expr3_0, expr14_0)?;
-    let expr16_0 = constructor_lsl(ctx, expr11_0, expr15_0, expr10_0)?;
-    let expr17_0: Type = I64;
-    let expr18_0: u8 = 63;
-    let expr19_0 = C::imm_shift_from_u8(ctx, expr18_0);
-    let expr20_0 = constructor_asr_imm(ctx, expr17_0, expr3_0, expr19_0)?;
-    let expr21_0: Type = I64;
-    let expr22_0 = constructor_orr(ctx, expr21_0, expr5_0, expr16_0)?;
-    let expr23_0: Type = I64;
-    let expr24_0: Type = I64;
-    let expr25_0: u64 = 64;
-    let expr26_0 = C::u64_into_imm_logic(ctx, expr24_0, expr25_0);
-    let expr27_0 = constructor_tst_imm(ctx, expr23_0, pattern1_0, expr26_0)?;
-    let expr28_0 = Cond::Ne;
-    let expr29_0 = constructor_csel(ctx, &expr28_0, expr7_0, expr22_0)?;
-    let expr30_0 = Cond::Ne;
-    let expr31_0 = constructor_csel(ctx, &expr30_0, expr20_0, expr7_0)?;
-    let expr32_0 = constructor_consumes_flags_concat(ctx, &expr29_0, &expr31_0)?;
-    let expr33_0 = constructor_with_flags(ctx, &expr27_0, &expr32_0)?;
-    return Some(expr33_0);
-}
-
-// Generated as internal constructor for term small_rotr.
-pub fn constructor_small_rotr<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/lower.isle line 927.
-    let expr0_0: Type = I32;
-    let expr1_0 = C::rotr_mask(ctx, pattern0_0);
-    let expr2_0 = constructor_and_imm(ctx, expr0_0, pattern2_0, expr1_0)?;
-    let expr3_0: Type = I32;
-    let expr4_0 = C::ty_bits(ctx, pattern0_0);
-    let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
-    let expr6_0 = constructor_sub_imm(ctx, expr3_0, expr2_0, expr5_0)?;
-    let expr7_0: Type = I32;
-    let expr8_0 = C::zero_reg(ctx);
-    let expr9_0 = constructor_sub(ctx, expr7_0, expr8_0, expr6_0)?;
-    let expr10_0: Type = I32;
-    let expr11_0 = constructor_lsr(ctx, expr10_0, pattern1_0, expr2_0)?;
-    let expr12_0: Type = I32;
-    let expr13_0 = constructor_lsl(ctx, expr12_0, pattern1_0, expr9_0)?;
-    let expr14_0: Type = I32;
-    let expr15_0 = constructor_orr(ctx, expr14_0, expr13_0, expr11_0)?;
-    return Some(expr15_0);
-}
-
-// Generated as internal constructor for term small_rotr_imm.
-pub fn constructor_small_rotr_imm<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: ImmShift,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/aarch64/lower.isle line 948.
-    let expr0_0: Type = I32;
-    let expr1_0 = constructor_lsr_imm(ctx, expr0_0, pattern1_0, pattern2_0)?;
-    let expr2_0: Type = I32;
-    let expr3_0 = C::rotr_opposite_amount(ctx, pattern0_0, pattern2_0);
-    let expr4_0 = constructor_lsl_imm(ctx, expr2_0, pattern1_0, expr3_0)?;
-    let expr5_0: Type = I32;
-    let expr6_0 = constructor_orr(ctx, expr5_0, expr4_0, expr1_0)?;
-    return Some(expr6_0);
-}
-
-// Generated as internal constructor for term lower_clz128.
-pub fn constructor_lower_clz128<C: Context>(ctx: &mut C, arg0: ValueRegs) -> Option<ValueRegs> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/aarch64/lower.isle line 1013.
-    let expr0_0: Type = I64;
-    let expr1_0: usize = 1;
-    let expr2_0 = C::value_regs_get(ctx, pattern0_0, expr1_0);
-    let expr3_0 = constructor_a64_clz(ctx, expr0_0, expr2_0)?;
-    let expr4_0: Type = I64;
-    let expr5_0: usize = 0;
-    let expr6_0 = C::value_regs_get(ctx, pattern0_0, expr5_0);
-    let expr7_0 = constructor_a64_clz(ctx, expr4_0, expr6_0)?;
-    let expr8_0: Type = I64;
-    let expr9_0: u8 = 6;
-    let expr10_0 = C::imm_shift_from_u8(ctx, expr9_0);
-    let expr11_0 = constructor_lsr_imm(ctx, expr8_0, expr3_0, expr10_0)?;
-    let expr12_0 = constructor_madd64(ctx, expr7_0, expr11_0, expr3_0)?;
-    let expr13_0: Type = I64;
-    let expr14_0: u64 = 0;
-    let expr15_0 = constructor_imm(ctx, expr13_0, expr14_0)?;
-    let expr16_0 = C::value_regs(ctx, expr12_0, expr15_0);
-    return Some(expr16_0);
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/lower_inst.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/lower_inst.rs
deleted file mode 100644
index 4f03159b8..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/lower_inst.rs
+++ /dev/null
@@ -1,2787 +0,0 @@
-//! Lower a single Cranelift instruction into vcode.
-
-use crate::binemit::CodeOffset;
-use crate::ir::condcodes::FloatCC;
-use crate::ir::types::*;
-use crate::ir::Inst as IRInst;
-use crate::ir::{InstructionData, Opcode, TrapCode};
-use crate::isa::aarch64::settings as aarch64_settings;
-use crate::machinst::lower::*;
-use crate::machinst::*;
-use crate::settings::{Flags, TlsModel};
-use crate::{CodegenError, CodegenResult};
-
-use crate::isa::aarch64::abi::*;
-use crate::isa::aarch64::inst::*;
-
-use regalloc::Writable;
-
-use alloc::boxed::Box;
-use alloc::vec::Vec;
-use core::convert::TryFrom;
-
-use super::lower::*;
-
-/// Actually codegen an instruction's results into registers.
-pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    insn: IRInst,
-    flags: &Flags,
-    isa_flags: &aarch64_settings::Flags,
-) -> CodegenResult<()> {
-    let op = ctx.data(insn).opcode();
-    let inputs = insn_inputs(ctx, insn);
-    let outputs = insn_outputs(ctx, insn);
-    let ty = if outputs.len() > 0 {
-        Some(ctx.output_ty(insn, 0))
-    } else {
-        None
-    };
-
-    if let Ok(()) = super::lower::isle::lower(ctx, flags, isa_flags, &outputs, insn) {
-        return Ok(());
-    }
-
-    let implemented_in_isle = |ctx: &mut C| -> ! {
-        unreachable!(
-            "implemented in ISLE: inst = `{}`, type = `{:?}`",
-            ctx.dfg().display_inst(insn),
-            ty
-        );
-    };
-
-    match op {
-        Opcode::Iconst | Opcode::Bconst | Opcode::Null => implemented_in_isle(ctx),
-
-        Opcode::F32const | Opcode::F64const => unreachable!(
-            "Should never see constant ops at top level lowering entry
-            point, as constants are rematerialized at use-sites"
-        ),
-
-        Opcode::Iadd => implemented_in_isle(ctx),
-        Opcode::Isub => implemented_in_isle(ctx),
-        Opcode::UaddSat | Opcode::SaddSat | Opcode::UsubSat | Opcode::SsubSat => {
-            implemented_in_isle(ctx)
-        }
-
-        Opcode::Ineg => implemented_in_isle(ctx),
-
-        Opcode::Imul => implemented_in_isle(ctx),
-
-        Opcode::Umulhi | Opcode::Smulhi => implemented_in_isle(ctx),
-
-        Opcode::Udiv | Opcode::Sdiv | Opcode::Urem | Opcode::Srem => implemented_in_isle(ctx),
-
-        Opcode::Uextend | Opcode::Sextend => implemented_in_isle(ctx),
-
-        Opcode::Bnot => implemented_in_isle(ctx),
-
-        Opcode::Band
-        | Opcode::Bor
-        | Opcode::Bxor
-        | Opcode::BandNot
-        | Opcode::BorNot
-        | Opcode::BxorNot => implemented_in_isle(ctx),
-
-        Opcode::Ishl | Opcode::Ushr | Opcode::Sshr => implemented_in_isle(ctx),
-
-        Opcode::Rotr | Opcode::Rotl => implemented_in_isle(ctx),
-
-        Opcode::Bitrev | Opcode::Clz | Opcode::Cls | Opcode::Ctz => implemented_in_isle(ctx),
-
-        Opcode::Popcnt => implemented_in_isle(ctx),
-
-        Opcode::Load
-        | Opcode::Uload8
-        | Opcode::Sload8
-        | Opcode::Uload16
-        | Opcode::Sload16
-        | Opcode::Uload32
-        | Opcode::Sload32
-        | Opcode::LoadComplex
-        | Opcode::Uload8Complex
-        | Opcode::Sload8Complex
-        | Opcode::Uload16Complex
-        | Opcode::Sload16Complex
-        | Opcode::Uload32Complex
-        | Opcode::Sload32Complex
-        | Opcode::Sload8x8
-        | Opcode::Uload8x8
-        | Opcode::Sload16x4
-        | Opcode::Uload16x4
-        | Opcode::Sload32x2
-        | Opcode::Uload32x2
-        | Opcode::Uload8x8Complex
-        | Opcode::Sload8x8Complex
-        | Opcode::Uload16x4Complex
-        | Opcode::Sload16x4Complex
-        | Opcode::Uload32x2Complex
-        | Opcode::Sload32x2Complex => {
-            let sign_extend = match op {
-                Opcode::Sload8
-                | Opcode::Sload8Complex
-                | Opcode::Sload16
-                | Opcode::Sload16Complex
-                | Opcode::Sload32
-                | Opcode::Sload32Complex => true,
-                _ => false,
-            };
-            let flags = ctx
-                .memflags(insn)
-                .expect("Load instruction should have memflags");
-
-            let out_ty = ctx.output_ty(insn, 0);
-            if out_ty == I128 {
-                let off = ctx.data(insn).load_store_offset().unwrap();
-                let mem = lower_pair_address(ctx, &inputs[..], off);
-                let dst = get_output_reg(ctx, outputs[0]);
-                ctx.emit(Inst::LoadP64 {
-                    rt: dst.regs()[0],
-                    rt2: dst.regs()[1],
-                    mem,
-                    flags,
-                });
-            } else {
-                lower_load(
-                    ctx,
-                    insn,
-                    &inputs[..],
-                    outputs[0],
-                    |ctx, dst, elem_ty, mem| {
-                        let rd = dst.only_reg().unwrap();
-                        let is_float = ty_has_float_or_vec_representation(elem_ty);
-                        ctx.emit(match (ty_bits(elem_ty), sign_extend, is_float) {
-                            (1, _, _) => Inst::ULoad8 { rd, mem, flags },
-                            (8, false, _) => Inst::ULoad8 { rd, mem, flags },
-                            (8, true, _) => Inst::SLoad8 { rd, mem, flags },
-                            (16, false, _) => Inst::ULoad16 { rd, mem, flags },
-                            (16, true, _) => Inst::SLoad16 { rd, mem, flags },
-                            (32, false, false) => Inst::ULoad32 { rd, mem, flags },
-                            (32, true, false) => Inst::SLoad32 { rd, mem, flags },
-                            (32, _, true) => Inst::FpuLoad32 { rd, mem, flags },
-                            (64, _, false) => Inst::ULoad64 { rd, mem, flags },
-                            // Note that we treat some of the vector loads as scalar floating-point loads,
-                            // which is correct in a little endian environment.
-                            (64, _, true) => Inst::FpuLoad64 { rd, mem, flags },
-                            (128, _, true) => Inst::FpuLoad128 { rd, mem, flags },
-                            _ => {
-                                return Err(CodegenError::Unsupported(format!(
-                                    "Unsupported type in load: {:?}",
-                                    elem_ty
-                                )))
-                            }
-                        });
-
-                        let vec_extend = match op {
-                            Opcode::Sload8x8 => Some(VecExtendOp::Sxtl8),
-                            Opcode::Sload8x8Complex => Some(VecExtendOp::Sxtl8),
-                            Opcode::Uload8x8 => Some(VecExtendOp::Uxtl8),
-                            Opcode::Uload8x8Complex => Some(VecExtendOp::Uxtl8),
-                            Opcode::Sload16x4 => Some(VecExtendOp::Sxtl16),
-                            Opcode::Sload16x4Complex => Some(VecExtendOp::Sxtl16),
-                            Opcode::Uload16x4 => Some(VecExtendOp::Uxtl16),
-                            Opcode::Uload16x4Complex => Some(VecExtendOp::Uxtl16),
-                            Opcode::Sload32x2 => Some(VecExtendOp::Sxtl32),
-                            Opcode::Sload32x2Complex => Some(VecExtendOp::Sxtl32),
-                            Opcode::Uload32x2 => Some(VecExtendOp::Uxtl32),
-                            Opcode::Uload32x2Complex => Some(VecExtendOp::Uxtl32),
-                            _ => None,
-                        };
-
-                        if let Some(t) = vec_extend {
-                            let rd = dst.only_reg().unwrap();
-                            ctx.emit(Inst::VecExtend {
-                                t,
-                                rd,
-                                rn: rd.to_reg(),
-                                high_half: false,
-                            });
-                        }
-
-                        Ok(())
-                    },
-                )?;
-            }
-        }
-
-        Opcode::Store
-        | Opcode::Istore8
-        | Opcode::Istore16
-        | Opcode::Istore32
-        | Opcode::StoreComplex
-        | Opcode::Istore8Complex
-        | Opcode::Istore16Complex
-        | Opcode::Istore32Complex => {
-            let off = ctx.data(insn).load_store_offset().unwrap();
-            let elem_ty = match op {
-                Opcode::Istore8 | Opcode::Istore8Complex => I8,
-                Opcode::Istore16 | Opcode::Istore16Complex => I16,
-                Opcode::Istore32 | Opcode::Istore32Complex => I32,
-                Opcode::Store | Opcode::StoreComplex => ctx.input_ty(insn, 0),
-                _ => unreachable!(),
-            };
-            let is_float = ty_has_float_or_vec_representation(elem_ty);
-            let flags = ctx
-                .memflags(insn)
-                .expect("Store instruction should have memflags");
-
-            let dst = put_input_in_regs(ctx, inputs[0]);
-
-            if elem_ty == I128 {
-                let mem = lower_pair_address(ctx, &inputs[1..], off);
-                ctx.emit(Inst::StoreP64 {
-                    rt: dst.regs()[0],
-                    rt2: dst.regs()[1],
-                    mem,
-                    flags,
-                });
-            } else {
-                let rd = dst.only_reg().unwrap();
-                let mem = lower_address(ctx, elem_ty, &inputs[1..], off);
-                ctx.emit(match (ty_bits(elem_ty), is_float) {
-                    (1, _) | (8, _) => Inst::Store8 { rd, mem, flags },
-                    (16, _) => Inst::Store16 { rd, mem, flags },
-                    (32, false) => Inst::Store32 { rd, mem, flags },
-                    (32, true) => Inst::FpuStore32 { rd, mem, flags },
-                    (64, false) => Inst::Store64 { rd, mem, flags },
-                    (64, true) => Inst::FpuStore64 { rd, mem, flags },
-                    (128, _) => Inst::FpuStore128 { rd, mem, flags },
-                    _ => {
-                        return Err(CodegenError::Unsupported(format!(
-                            "Unsupported type in store: {:?}",
-                            elem_ty
-                        )))
-                    }
-                });
-            }
-        }
-
-        Opcode::StackAddr => {
-            let (stack_slot, offset) = match *ctx.data(insn) {
-                InstructionData::StackLoad {
-                    opcode: Opcode::StackAddr,
-                    stack_slot,
-                    offset,
-                } => (stack_slot, offset),
-                _ => unreachable!(),
-            };
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let offset: i32 = offset.into();
-            let inst = ctx
-                .abi()
-                .stackslot_addr(stack_slot, u32::try_from(offset).unwrap(), rd);
-            ctx.emit(inst);
-        }
-
-        Opcode::AtomicRmw => {
-            let r_dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let mut r_addr = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-            let mut r_arg2 = put_input_in_reg(ctx, inputs[1], NarrowValueMode::None);
-            let ty_access = ty.unwrap();
-            assert!(is_valid_atomic_transaction_ty(ty_access));
-
-            let op = inst_common::AtomicRmwOp::from(ctx.data(insn).atomic_rmw_op().unwrap());
-            let lse_op = match op {
-                AtomicRmwOp::Add => Some(AtomicRMWOp::Add),
-                AtomicRmwOp::And => Some(AtomicRMWOp::Clr),
-                AtomicRmwOp::Xor => Some(AtomicRMWOp::Eor),
-                AtomicRmwOp::Or => Some(AtomicRMWOp::Set),
-                AtomicRmwOp::Smax => Some(AtomicRMWOp::Smax),
-                AtomicRmwOp::Umax => Some(AtomicRMWOp::Umax),
-                AtomicRmwOp::Smin => Some(AtomicRMWOp::Smin),
-                AtomicRmwOp::Umin => Some(AtomicRMWOp::Umin),
-                _ => None,
-            };
-            if isa_flags.use_lse() && lse_op.is_some() {
-                ctx.emit(Inst::AtomicRMW {
-                    op: lse_op.unwrap(),
-                    rs: r_arg2,
-                    rt: r_dst,
-                    rn: r_addr,
-                    ty: ty_access,
-                });
-            } else {
-                // Make sure that both args are in virtual regs, since in effect
-                // we have to do a parallel copy to get them safely to the AtomicRMW input
-                // regs, and that's not guaranteed safe if either is in a real reg.
-                r_addr = ctx.ensure_in_vreg(r_addr, I64);
-                r_arg2 = ctx.ensure_in_vreg(r_arg2, I64);
-                // Move the args to the preordained AtomicRMW input regs
-                ctx.emit(Inst::gen_move(Writable::from_reg(xreg(25)), r_addr, I64));
-                ctx.emit(Inst::gen_move(Writable::from_reg(xreg(26)), r_arg2, I64));
-                ctx.emit(Inst::AtomicRMWLoop { ty: ty_access, op });
-                // And finally, copy the preordained AtomicRMW output reg to its destination.
-                ctx.emit(Inst::gen_move(r_dst, xreg(27), I64));
-                // Also, x24 and x28 are trashed.  `fn aarch64_get_regs` must mention that.
-            }
-        }
-
-        Opcode::AtomicCas => {
-            let r_dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let mut r_addr = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-            let mut r_expected = put_input_in_reg(ctx, inputs[1], NarrowValueMode::None);
-            let mut r_replacement = put_input_in_reg(ctx, inputs[2], NarrowValueMode::None);
-            let ty_access = ty.unwrap();
-            assert!(is_valid_atomic_transaction_ty(ty_access));
-
-            if isa_flags.use_lse() {
-                ctx.emit(Inst::gen_move(r_dst, r_expected, ty_access));
-                ctx.emit(Inst::AtomicCAS {
-                    rs: r_dst,
-                    rt: r_replacement,
-                    rn: r_addr,
-                    ty: ty_access,
-                });
-            } else {
-                // This is very similar to, but not identical to, the AtomicRmw case.  Note
-                // that the AtomicCASLoop sequence does its own masking, so we don't need to worry
-                // about zero-extending narrow (I8/I16/I32) values here.
-                // Make sure that all three args are in virtual regs.  See corresponding comment
-                // for `Opcode::AtomicRmw` above.
-                r_addr = ctx.ensure_in_vreg(r_addr, I64);
-                r_expected = ctx.ensure_in_vreg(r_expected, I64);
-                r_replacement = ctx.ensure_in_vreg(r_replacement, I64);
-                // Move the args to the preordained AtomicCASLoop input regs
-                ctx.emit(Inst::gen_move(Writable::from_reg(xreg(25)), r_addr, I64));
-                ctx.emit(Inst::gen_move(
-                    Writable::from_reg(xreg(26)),
-                    r_expected,
-                    I64,
-                ));
-                ctx.emit(Inst::gen_move(
-                    Writable::from_reg(xreg(28)),
-                    r_replacement,
-                    I64,
-                ));
-                // Now the AtomicCASLoop itself, implemented in the normal way, with an LL-SC loop
-                ctx.emit(Inst::AtomicCASLoop { ty: ty_access });
-                // And finally, copy the preordained AtomicCASLoop output reg to its destination.
-                ctx.emit(Inst::gen_move(r_dst, xreg(27), I64));
-                // Also, x24 and x28 are trashed.  `fn aarch64_get_regs` must mention that.
-            }
-        }
-
-        Opcode::AtomicLoad => {
-            let rt = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let inst = emit_atomic_load(ctx, rt, insn);
-            ctx.emit(inst);
-        }
-
-        Opcode::AtomicStore => {
-            let rt = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-            let rn = put_input_in_reg(ctx, inputs[1], NarrowValueMode::None);
-            let access_ty = ctx.input_ty(insn, 0);
-            assert!(is_valid_atomic_transaction_ty(access_ty));
-            ctx.emit(Inst::StoreRelease { access_ty, rt, rn });
-        }
-
-        Opcode::Fence => {
-            ctx.emit(Inst::Fence {});
-        }
-
-        Opcode::StackLoad | Opcode::StackStore => {
-            panic!("Direct stack memory access not supported; should not be used by Wasm");
-        }
-
-        Opcode::HeapAddr => {
-            panic!("heap_addr should have been removed by legalization!");
-        }
-
-        Opcode::TableAddr => {
-            panic!("table_addr should have been removed by legalization!");
-        }
-
-        Opcode::Nop => {
-            // Nothing.
-        }
-
-        Opcode::Select => {
-            let flag_input = inputs[0];
-            let cond = if let Some(icmp_insn) =
-                maybe_input_insn_via_conv(ctx, flag_input, Opcode::Icmp, Opcode::Bint)
-            {
-                let condcode = ctx.data(icmp_insn).cond_code().unwrap();
-                lower_icmp(ctx, icmp_insn, condcode, IcmpOutput::CondCode)?.unwrap_cond()
-            } else if let Some(fcmp_insn) =
-                maybe_input_insn_via_conv(ctx, flag_input, Opcode::Fcmp, Opcode::Bint)
-            {
-                let condcode = ctx.data(fcmp_insn).fp_cond_code().unwrap();
-                let cond = lower_fp_condcode(condcode);
-                lower_fcmp_or_ffcmp_to_flags(ctx, fcmp_insn);
-                cond
-            } else {
-                let (size, narrow_mode) = if ty_bits(ctx.input_ty(insn, 0)) > 32 {
-                    (OperandSize::Size64, NarrowValueMode::ZeroExtend64)
-                } else {
-                    (OperandSize::Size32, NarrowValueMode::ZeroExtend32)
-                };
-
-                let rcond = put_input_in_reg(ctx, inputs[0], narrow_mode);
-                // cmp rcond, #0
-                ctx.emit(Inst::AluRRR {
-                    alu_op: ALUOp::SubS,
-                    size,
-                    rd: writable_zero_reg(),
-                    rn: rcond,
-                    rm: zero_reg(),
-                });
-                Cond::Ne
-            };
-
-            // csel.cond rd, rn, rm
-            let ty = ctx.output_ty(insn, 0);
-            let bits = ty_bits(ty);
-            let is_float = ty_has_float_or_vec_representation(ty);
-
-            let dst = get_output_reg(ctx, outputs[0]);
-            let lhs = put_input_in_regs(ctx, inputs[1]);
-            let rhs = put_input_in_regs(ctx, inputs[2]);
-
-            let rd = dst.regs()[0];
-            let rn = lhs.regs()[0];
-            let rm = rhs.regs()[0];
-
-            match (is_float, bits) {
-                (true, 32) => ctx.emit(Inst::FpuCSel32 { cond, rd, rn, rm }),
-                (true, 64) => ctx.emit(Inst::FpuCSel64 { cond, rd, rn, rm }),
-                (true, 128) => ctx.emit(Inst::VecCSel { cond, rd, rn, rm }),
-                (false, 128) => {
-                    ctx.emit(Inst::CSel {
-                        cond,
-                        rd: dst.regs()[0],
-                        rn: lhs.regs()[0],
-                        rm: rhs.regs()[0],
-                    });
-                    ctx.emit(Inst::CSel {
-                        cond,
-                        rd: dst.regs()[1],
-                        rn: lhs.regs()[1],
-                        rm: rhs.regs()[1],
-                    });
-                }
-                (false, bits) if bits <= 64 => ctx.emit(Inst::CSel { cond, rd, rn, rm }),
-                _ => {
-                    return Err(CodegenError::Unsupported(format!(
-                        "Select: Unsupported type: {:?}",
-                        ty
-                    )));
-                }
-            }
-        }
-
-        Opcode::Selectif | Opcode::SelectifSpectreGuard => {
-            let condcode = ctx.data(insn).cond_code().unwrap();
-            // Verification ensures that the input is always a
-            // single-def ifcmp.
-            let ifcmp_insn = maybe_input_insn(ctx, inputs[0], Opcode::Ifcmp).unwrap();
-            let cond = lower_icmp(ctx, ifcmp_insn, condcode, IcmpOutput::CondCode)?.unwrap_cond();
-
-            // csel.COND rd, rn, rm
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let rn = put_input_in_reg(ctx, inputs[1], NarrowValueMode::None);
-            let rm = put_input_in_reg(ctx, inputs[2], NarrowValueMode::None);
-            let ty = ctx.output_ty(insn, 0);
-            let bits = ty_bits(ty);
-            let is_float = ty_has_float_or_vec_representation(ty);
-            if is_float && bits == 32 {
-                ctx.emit(Inst::FpuCSel32 { cond, rd, rn, rm });
-            } else if is_float && bits == 64 {
-                ctx.emit(Inst::FpuCSel64 { cond, rd, rn, rm });
-            } else if !is_float && bits <= 64 {
-                ctx.emit(Inst::CSel { cond, rd, rn, rm });
-            } else {
-                return Err(CodegenError::Unsupported(format!(
-                    "{}: Unsupported type: {:?}",
-                    op, ty
-                )));
-            }
-        }
-
-        Opcode::Bitselect | Opcode::Vselect => {
-            let ty = ty.unwrap();
-            if !ty.is_vector() {
-                debug_assert_ne!(Opcode::Vselect, op);
-                let tmp = ctx.alloc_tmp(I64).only_reg().unwrap();
-                let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-                let rcond = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-                let rn = put_input_in_reg(ctx, inputs[1], NarrowValueMode::None);
-                let rm = put_input_in_reg(ctx, inputs[2], NarrowValueMode::None);
-                // AND rTmp, rn, rcond
-                ctx.emit(Inst::AluRRR {
-                    alu_op: ALUOp::And,
-                    size: OperandSize::Size64,
-                    rd: tmp,
-                    rn,
-                    rm: rcond,
-                });
-                // BIC rd, rm, rcond
-                ctx.emit(Inst::AluRRR {
-                    alu_op: ALUOp::AndNot,
-                    size: OperandSize::Size64,
-                    rd,
-                    rn: rm,
-                    rm: rcond,
-                });
-                // ORR rd, rd, rTmp
-                ctx.emit(Inst::AluRRR {
-                    alu_op: ALUOp::Orr,
-                    size: OperandSize::Size64,
-                    rd,
-                    rn: rd.to_reg(),
-                    rm: tmp.to_reg(),
-                });
-            } else {
-                let rcond = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-                let rn = put_input_in_reg(ctx, inputs[1], NarrowValueMode::None);
-                let rm = put_input_in_reg(ctx, inputs[2], NarrowValueMode::None);
-                let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-                ctx.emit(Inst::gen_move(rd, rcond, ty));
-
-                ctx.emit(Inst::VecRRR {
-                    alu_op: VecALUOp::Bsl,
-                    rd,
-                    rn,
-                    rm,
-                    size: VectorSize::from_ty(ty),
-                });
-            }
-        }
-
-        Opcode::Trueif => {
-            let condcode = ctx.data(insn).cond_code().unwrap();
-            // Verification ensures that the input is always a
-            // single-def ifcmp.
-            let ifcmp_insn = maybe_input_insn(ctx, inputs[0], Opcode::Ifcmp).unwrap();
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            lower_icmp(ctx, ifcmp_insn, condcode, IcmpOutput::Register(rd))?;
-        }
-
-        Opcode::Trueff => {
-            let condcode = ctx.data(insn).fp_cond_code().unwrap();
-            let cond = lower_fp_condcode(condcode);
-            let ffcmp_insn = maybe_input_insn(ctx, inputs[0], Opcode::Ffcmp).unwrap();
-            lower_fcmp_or_ffcmp_to_flags(ctx, ffcmp_insn);
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            materialize_bool_result(ctx, insn, rd, cond);
-        }
-
-        Opcode::IsNull | Opcode::IsInvalid => {
-            // Null references are represented by the constant value 0; invalid references are
-            // represented by the constant value -1. See `define_reftypes()` in
-            // `meta/src/isa/x86/encodings.rs` to confirm.
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-            let ty = ctx.input_ty(insn, 0);
-            let (alu_op, const_value) = match op {
-                Opcode::IsNull => {
-                    // cmp rn, #0
-                    (ALUOp::SubS, 0)
-                }
-                Opcode::IsInvalid => {
-                    // cmn rn, #1
-                    (ALUOp::AddS, 1)
-                }
-                _ => unreachable!(),
-            };
-            let const_value = ResultRSEImm12::Imm12(Imm12::maybe_from_u64(const_value).unwrap());
-            ctx.emit(alu_inst_imm12(
-                alu_op,
-                ty,
-                writable_zero_reg(),
-                rn,
-                const_value,
-            ));
-            materialize_bool_result(ctx, insn, rd, Cond::Eq);
-        }
-
-        Opcode::Copy => {
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-            let ty = ctx.input_ty(insn, 0);
-            ctx.emit(Inst::gen_move(rd, rn, ty));
-        }
-
-        Opcode::Breduce | Opcode::Ireduce => {
-            // Smaller integers/booleans are stored with high-order bits
-            // undefined, so we can simply do a copy.
-            let rn = put_input_in_regs(ctx, inputs[0]).regs()[0];
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let ty = ctx.input_ty(insn, 0);
-            ctx.emit(Inst::gen_move(rd, rn, ty));
-        }
-
-        Opcode::Bextend | Opcode::Bmask => {
-            // Bextend and Bmask both simply sign-extend. This works for:
-            // - Bextend, because booleans are stored as 0 / -1, so we
-            //   sign-extend the -1 to a -1 in the wider width.
-            // - Bmask, because the resulting integer mask value must be
-            //   all-ones (-1) if the argument is true.
-
-            let from_ty = ctx.input_ty(insn, 0);
-            let to_ty = ctx.output_ty(insn, 0);
-            let from_bits = ty_bits(from_ty);
-            let to_bits = ty_bits(to_ty);
-
-            if from_ty.is_vector() || from_bits > 64 || to_bits > 64 {
-                return Err(CodegenError::Unsupported(format!(
-                    "{}: Unsupported type: {:?}",
-                    op, from_ty
-                )));
-            }
-
-            assert!(from_bits <= to_bits);
-
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-
-            if from_bits == to_bits {
-                ctx.emit(Inst::gen_move(rd, rn, to_ty));
-            } else {
-                let to_bits = if to_bits > 32 { 64 } else { 32 };
-                let from_bits = from_bits as u8;
-                ctx.emit(Inst::Extend {
-                    rd,
-                    rn,
-                    signed: true,
-                    from_bits,
-                    to_bits,
-                });
-            }
-        }
-
-        Opcode::Bint => {
-            let ty = ty.unwrap();
-
-            if ty.is_vector() {
-                return Err(CodegenError::Unsupported(format!(
-                    "Bint: Unsupported type: {:?}",
-                    ty
-                )));
-            }
-
-            // Booleans are stored as all-zeroes (0) or all-ones (-1). We AND
-            // out the LSB to give a 0 / 1-valued integer result.
-            let input = put_input_in_regs(ctx, inputs[0]);
-            let output = get_output_reg(ctx, outputs[0]);
-
-            ctx.emit(Inst::AluRRImmLogic {
-                alu_op: ALUOp::And,
-                size: OperandSize::Size32,
-                rd: output.regs()[0],
-                rn: input.regs()[0],
-                imml: ImmLogic::maybe_from_u64(1, I32).unwrap(),
-            });
-
-            if ty_bits(ty) > 64 {
-                lower_constant_u64(ctx, output.regs()[1], 0);
-            }
-        }
-
-        Opcode::Bitcast => {
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let ity = ctx.input_ty(insn, 0);
-            let oty = ctx.output_ty(insn, 0);
-            let ity_bits = ty_bits(ity);
-            let ity_vec_reg = ty_has_float_or_vec_representation(ity);
-            let oty_bits = ty_bits(oty);
-            let oty_vec_reg = ty_has_float_or_vec_representation(oty);
-
-            debug_assert_eq!(ity_bits, oty_bits);
-
-            match (ity_vec_reg, oty_vec_reg) {
-                (true, true) => {
-                    let narrow_mode = if ity_bits <= 32 {
-                        NarrowValueMode::ZeroExtend32
-                    } else {
-                        NarrowValueMode::ZeroExtend64
-                    };
-                    let rm = put_input_in_reg(ctx, inputs[0], narrow_mode);
-                    ctx.emit(Inst::gen_move(rd, rm, oty));
-                }
-                (false, false) => {
-                    let rm = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-                    ctx.emit(Inst::gen_move(rd, rm, oty));
-                }
-                (false, true) => {
-                    let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::ZeroExtend64);
-                    ctx.emit(Inst::MovToFpu {
-                        rd,
-                        rn,
-                        size: ScalarSize::Size64,
-                    });
-                }
-                (true, false) => {
-                    let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-                    let size = VectorSize::from_lane_size(ScalarSize::from_bits(oty_bits), true);
-
-                    ctx.emit(Inst::MovFromVec {
-                        rd,
-                        rn,
-                        idx: 0,
-                        size,
-                    });
-                }
-            }
-        }
-
-        Opcode::FallthroughReturn | Opcode::Return => {
-            for (i, input) in inputs.iter().enumerate() {
-                // N.B.: according to the AArch64 ABI, the top bits of a register
-                // (above the bits for the value's type) are undefined, so we
-                // need not extend the return values.
-                let src_regs = put_input_in_regs(ctx, *input);
-                let retval_regs = ctx.retval(i);
-
-                assert_eq!(src_regs.len(), retval_regs.len());
-                let ty = ctx.input_ty(insn, i);
-                let (_, tys) = Inst::rc_for_type(ty)?;
-
-                src_regs
-                    .regs()
-                    .iter()
-                    .zip(retval_regs.regs().iter())
-                    .zip(tys.iter())
-                    .for_each(|((&src, &dst), &ty)| {
-                        ctx.emit(Inst::gen_move(dst, src, ty));
-                    });
-            }
-            // N.B.: the Ret itself is generated by the ABI.
-        }
-
-        Opcode::Ifcmp | Opcode::Ffcmp => {
-            // An Ifcmp/Ffcmp must always be seen as a use of a brif/brff or trueif/trueff
-            // instruction. This will always be the case as long as the IR uses an Ifcmp/Ffcmp from
-            // the same block, or a dominating block. In other words, it cannot pass through a BB
-            // param (phi). The flags pass of the verifier will ensure this.
-            panic!("Should never reach ifcmp as isel root!");
-        }
-
-        Opcode::Icmp => {
-            let condcode = ctx.data(insn).cond_code().unwrap();
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            lower_icmp(ctx, insn, condcode, IcmpOutput::Register(rd))?;
-        }
-
-        Opcode::Fcmp => {
-            let condcode = ctx.data(insn).fp_cond_code().unwrap();
-            let cond = lower_fp_condcode(condcode);
-            let ty = ctx.input_ty(insn, 0);
-            let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-            let rm = put_input_in_reg(ctx, inputs[1], NarrowValueMode::None);
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-
-            if !ty.is_vector() {
-                match ty_bits(ty) {
-                    32 => {
-                        ctx.emit(Inst::FpuCmp32 { rn, rm });
-                    }
-                    64 => {
-                        ctx.emit(Inst::FpuCmp64 { rn, rm });
-                    }
-                    _ => {
-                        return Err(CodegenError::Unsupported(format!(
-                            "Fcmp: Unsupported type: {:?}",
-                            ty
-                        )))
-                    }
-                }
-                materialize_bool_result(ctx, insn, rd, cond);
-            } else {
-                lower_vector_compare(ctx, rd, rn, rm, ty, cond)?;
-            }
-        }
-
-        Opcode::Debugtrap => {
-            ctx.emit(Inst::Brk);
-        }
-
-        Opcode::Trap | Opcode::ResumableTrap => {
-            let trap_code = ctx.data(insn).trap_code().unwrap();
-            ctx.emit_safepoint(Inst::Udf { trap_code });
-        }
-
-        Opcode::Trapif | Opcode::Trapff => {
-            let trap_code = ctx.data(insn).trap_code().unwrap();
-
-            let cond = if maybe_input_insn(ctx, inputs[0], Opcode::IaddIfcout).is_some() {
-                let condcode = ctx.data(insn).cond_code().unwrap();
-                let cond = lower_condcode(condcode);
-                // The flags must not have been clobbered by any other
-                // instruction between the iadd_ifcout and this instruction, as
-                // verified by the CLIF validator; so we can simply use the
-                // flags here.
-                cond
-            } else if op == Opcode::Trapif {
-                let condcode = ctx.data(insn).cond_code().unwrap();
-
-                // Verification ensures that the input is always a single-def ifcmp.
-                let ifcmp_insn = maybe_input_insn(ctx, inputs[0], Opcode::Ifcmp).unwrap();
-                lower_icmp(ctx, ifcmp_insn, condcode, IcmpOutput::CondCode)?.unwrap_cond()
-            } else {
-                let condcode = ctx.data(insn).fp_cond_code().unwrap();
-                let cond = lower_fp_condcode(condcode);
-
-                // Verification ensures that the input is always a
-                // single-def ffcmp.
-                let ffcmp_insn = maybe_input_insn(ctx, inputs[0], Opcode::Ffcmp).unwrap();
-                lower_fcmp_or_ffcmp_to_flags(ctx, ffcmp_insn);
-                cond
-            };
-
-            ctx.emit_safepoint(Inst::TrapIf {
-                trap_code,
-                kind: CondBrKind::Cond(cond),
-            });
-        }
-
-        Opcode::Trapz | Opcode::Trapnz | Opcode::ResumableTrapnz => {
-            panic!("trapz / trapnz / resumable_trapnz should have been removed by legalization!");
-        }
-
-        Opcode::FuncAddr => {
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let (extname, _) = ctx.call_target(insn).unwrap();
-            let extname = extname.clone();
-            ctx.emit(Inst::LoadExtName {
-                rd,
-                name: Box::new(extname),
-                offset: 0,
-            });
-        }
-
-        Opcode::GlobalValue => {
-            panic!("global_value should have been removed by legalization!");
-        }
-
-        Opcode::SymbolValue => {
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let (extname, _, offset) = ctx.symbol_value(insn).unwrap();
-            let extname = extname.clone();
-            ctx.emit(Inst::LoadExtName {
-                rd,
-                name: Box::new(extname),
-                offset,
-            });
-        }
-
-        Opcode::Call | Opcode::CallIndirect => {
-            let caller_conv = ctx.abi().call_conv();
-            let (mut abi, inputs) = match op {
-                Opcode::Call => {
-                    let (extname, dist) = ctx.call_target(insn).unwrap();
-                    let extname = extname.clone();
-                    let sig = ctx.call_sig(insn).unwrap();
-                    assert!(inputs.len() == sig.params.len());
-                    assert!(outputs.len() == sig.returns.len());
-                    (
-                        AArch64ABICaller::from_func(sig, &extname, dist, caller_conv, flags)?,
-                        &inputs[..],
-                    )
-                }
-                Opcode::CallIndirect => {
-                    let ptr = put_input_in_reg(ctx, inputs[0], NarrowValueMode::ZeroExtend64);
-                    let sig = ctx.call_sig(insn).unwrap();
-                    assert!(inputs.len() - 1 == sig.params.len());
-                    assert!(outputs.len() == sig.returns.len());
-                    (
-                        AArch64ABICaller::from_ptr(sig, ptr, op, caller_conv, flags)?,
-                        &inputs[1..],
-                    )
-                }
-                _ => unreachable!(),
-            };
-
-            abi.emit_stack_pre_adjust(ctx);
-            assert!(inputs.len() == abi.num_args());
-            for i in abi.get_copy_to_arg_order() {
-                let input = inputs[i];
-                let arg_regs = put_input_in_regs(ctx, input);
-                abi.emit_copy_regs_to_arg(ctx, i, arg_regs);
-            }
-            abi.emit_call(ctx);
-            for (i, output) in outputs.iter().enumerate() {
-                let retval_regs = get_output_reg(ctx, *output);
-                abi.emit_copy_retval_to_regs(ctx, i, retval_regs);
-            }
-            abi.emit_stack_post_adjust(ctx);
-        }
-
-        Opcode::GetPinnedReg => {
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            ctx.emit(Inst::gen_move(rd, xreg(PINNED_REG), I64));
-        }
-
-        Opcode::SetPinnedReg => {
-            let rm = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-            ctx.emit(Inst::gen_move(writable_xreg(PINNED_REG), rm, I64));
-        }
-
-        Opcode::Jump
-        | Opcode::Brz
-        | Opcode::Brnz
-        | Opcode::BrIcmp
-        | Opcode::Brif
-        | Opcode::Brff
-        | Opcode::BrTable => {
-            panic!("Branch opcode reached non-branch lowering logic!");
-        }
-
-        Opcode::Vconst => {
-            let value = const_param_to_u128(ctx, insn).expect("Invalid immediate bytes");
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            lower_constant_f128(ctx, rd, value);
-        }
-
-        Opcode::RawBitcast => {
-            let rm = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let ty = ctx.input_ty(insn, 0);
-            ctx.emit(Inst::gen_move(rd, rm, ty));
-        }
-
-        Opcode::Extractlane => {
-            if let InstructionData::BinaryImm8 { imm, .. } = ctx.data(insn) {
-                let idx = *imm;
-                let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-                let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-                let size = VectorSize::from_ty(ctx.input_ty(insn, 0));
-                let ty = ty.unwrap();
-
-                if ty_has_int_representation(ty) {
-                    ctx.emit(Inst::MovFromVec { rd, rn, idx, size });
-                // Plain moves are faster on some processors.
-                } else if idx == 0 {
-                    ctx.emit(Inst::gen_move(rd, rn, ty));
-                } else {
-                    ctx.emit(Inst::FpuMoveFromVec { rd, rn, idx, size });
-                }
-            } else {
-                unreachable!();
-            }
-        }
-
-        Opcode::Insertlane => {
-            let idx = if let InstructionData::TernaryImm8 { imm, .. } = ctx.data(insn) {
-                *imm
-            } else {
-                unreachable!();
-            };
-            let input_ty = ctx.input_ty(insn, 1);
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let rm = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-            let rn = put_input_in_reg(ctx, inputs[1], NarrowValueMode::None);
-            let ty = ty.unwrap();
-            let size = VectorSize::from_ty(ty);
-
-            ctx.emit(Inst::gen_move(rd, rm, ty));
-
-            if ty_has_int_representation(input_ty) {
-                ctx.emit(Inst::MovToVec { rd, rn, idx, size });
-            } else {
-                ctx.emit(Inst::VecMovElement {
-                    rd,
-                    rn,
-                    dest_idx: idx,
-                    src_idx: 0,
-                    size,
-                });
-            }
-        }
-
-        Opcode::Splat => {
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let size = VectorSize::from_ty(ty.unwrap());
-
-            if let Some((_, insn)) = maybe_input_insn_multi(
-                ctx,
-                inputs[0],
-                &[
-                    Opcode::Bconst,
-                    Opcode::F32const,
-                    Opcode::F64const,
-                    Opcode::Iconst,
-                ],
-            ) {
-                lower_splat_const(ctx, rd, ctx.get_constant(insn).unwrap(), size);
-            } else if let Some(insn) =
-                maybe_input_insn_via_conv(ctx, inputs[0], Opcode::Iconst, Opcode::Ireduce)
-            {
-                lower_splat_const(ctx, rd, ctx.get_constant(insn).unwrap(), size);
-            } else if let Some(insn) =
-                maybe_input_insn_via_conv(ctx, inputs[0], Opcode::Bconst, Opcode::Breduce)
-            {
-                lower_splat_const(ctx, rd, ctx.get_constant(insn).unwrap(), size);
-            } else if let Some((_, insn)) = maybe_input_insn_multi(
-                ctx,
-                inputs[0],
-                &[
-                    Opcode::Uload8,
-                    Opcode::Sload8,
-                    Opcode::Uload16,
-                    Opcode::Sload16,
-                    Opcode::Uload32,
-                    Opcode::Sload32,
-                    Opcode::Load,
-                ],
-            ) {
-                ctx.sink_inst(insn);
-                let load_inputs = insn_inputs(ctx, insn);
-                let load_outputs = insn_outputs(ctx, insn);
-                lower_load(
-                    ctx,
-                    insn,
-                    &load_inputs[..],
-                    load_outputs[0],
-                    |ctx, _rd, _elem_ty, mem| {
-                        let tmp = ctx.alloc_tmp(I64).only_reg().unwrap();
-                        let (addr, addr_inst) = Inst::gen_load_addr(tmp, mem);
-                        if let Some(addr_inst) = addr_inst {
-                            ctx.emit(addr_inst);
-                        }
-                        ctx.emit(Inst::VecLoadReplicate { rd, rn: addr, size });
-
-                        Ok(())
-                    },
-                )?;
-            } else {
-                let input_ty = ctx.input_ty(insn, 0);
-                let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-                let inst = if ty_has_int_representation(input_ty) {
-                    Inst::VecDup { rd, rn, size }
-                } else {
-                    Inst::VecDupFromFpu { rd, rn, size }
-                };
-
-                ctx.emit(inst);
-            }
-        }
-
-        Opcode::ScalarToVector => {
-            let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let input_ty = ctx.input_ty(insn, 0);
-            if (input_ty == I32 && ty.unwrap() == I32X4)
-                || (input_ty == I64 && ty.unwrap() == I64X2)
-            {
-                ctx.emit(Inst::MovToFpu {
-                    rd,
-                    rn,
-                    size: ScalarSize::from_ty(input_ty),
-                });
-            } else {
-                return Err(CodegenError::Unsupported(format!(
-                    "ScalarToVector: unsupported types {:?} -> {:?}",
-                    input_ty, ty
-                )));
-            }
-        }
-
-        Opcode::VallTrue if ctx.input_ty(insn, 0).lane_bits() == 64 => {
-            let input_ty = ctx.input_ty(insn, 0);
-
-            if input_ty.lane_count() != 2 {
-                return Err(CodegenError::Unsupported(format!(
-                    "VallTrue: unsupported type {:?}",
-                    input_ty
-                )));
-            }
-
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let rm = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-            let tmp = ctx.alloc_tmp(I64X2).only_reg().unwrap();
-
-            // cmeq vtmp.2d, vm.2d, #0
-            // addp dtmp, vtmp.2d
-            // fcmp dtmp, dtmp
-            // cset xd, eq
-            //
-            // Note that after the ADDP the value of the temporary register will
-            // be either 0 when all input elements are true, i.e. non-zero, or a
-            // NaN otherwise (either -1 or -2 when represented as an integer);
-            // NaNs are the only floating-point numbers that compare unequal to
-            // themselves.
-
-            ctx.emit(Inst::VecMisc {
-                op: VecMisc2::Cmeq0,
-                rd: tmp,
-                rn: rm,
-                size: VectorSize::Size64x2,
-            });
-            ctx.emit(Inst::VecRRPair {
-                op: VecPairOp::Addp,
-                rd: tmp,
-                rn: tmp.to_reg(),
-            });
-            ctx.emit(Inst::FpuCmp64 {
-                rn: tmp.to_reg(),
-                rm: tmp.to_reg(),
-            });
-            materialize_bool_result(ctx, insn, rd, Cond::Eq);
-        }
-
-        Opcode::VanyTrue | Opcode::VallTrue => {
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let rm = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-            let src_ty = ctx.input_ty(insn, 0);
-            let tmp = ctx.alloc_tmp(src_ty).only_reg().unwrap();
-
-            // This operation is implemented by using umaxp or uminv to
-            // create a scalar value, which is then compared against zero.
-            //
-            // umaxp vn.16b, vm.16, vm.16 / uminv bn, vm.16b
-            // mov xm, vn.d[0]
-            // cmp xm, #0
-            // cset xm, ne
-
-            let s = VectorSize::from_ty(src_ty);
-            let size = if s == VectorSize::Size64x2 {
-                // `vall_true` with 64-bit elements is handled elsewhere.
-                debug_assert_ne!(op, Opcode::VallTrue);
-
-                VectorSize::Size32x4
-            } else {
-                s
-            };
-
-            if op == Opcode::VanyTrue {
-                ctx.emit(Inst::VecRRR {
-                    alu_op: VecALUOp::Umaxp,
-                    rd: tmp,
-                    rn: rm,
-                    rm,
-                    size,
-                });
-            } else {
-                if size == VectorSize::Size32x2 {
-                    return Err(CodegenError::Unsupported(format!(
-                        "VallTrue: Unsupported type: {:?}",
-                        src_ty
-                    )));
-                }
-
-                ctx.emit(Inst::VecLanes {
-                    op: VecLanesOp::Uminv,
-                    rd: tmp,
-                    rn: rm,
-                    size,
-                });
-            };
-
-            ctx.emit(Inst::MovFromVec {
-                rd,
-                rn: tmp.to_reg(),
-                idx: 0,
-                size: VectorSize::Size64x2,
-            });
-
-            ctx.emit(Inst::AluRRImm12 {
-                alu_op: ALUOp::SubS,
-                size: OperandSize::Size64,
-                rd: writable_zero_reg(),
-                rn: rd.to_reg(),
-                imm12: Imm12::zero(),
-            });
-
-            materialize_bool_result(ctx, insn, rd, Cond::Ne);
-        }
-
-        Opcode::VhighBits => {
-            let dst_r = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let src_v = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-            let ty = ctx.input_ty(insn, 0);
-            // All three sequences use one integer temporary and two vector temporaries.  The
-            // shift is done early so as to give the register allocator the possibility of using
-            // the same reg for `tmp_v1` and `src_v` in the case that this is the last use of
-            // `src_v`.  See https://github.com/WebAssembly/simd/pull/201 for the background and
-            // derivation of these sequences.  Alternative sequences are discussed in
-            // https://github.com/bytecodealliance/wasmtime/issues/2296, although they are not
-            // used here.
-            let tmp_r0 = ctx.alloc_tmp(I64).only_reg().unwrap();
-            let tmp_v0 = ctx.alloc_tmp(I8X16).only_reg().unwrap();
-            let tmp_v1 = ctx.alloc_tmp(I8X16).only_reg().unwrap();
-            match ty {
-                I8X16 => {
-                    // sshr  tmp_v1.16b, src_v.16b, #7
-                    // mov   tmp_r0, #0x0201
-                    // movk  tmp_r0, #0x0804, lsl 16
-                    // movk  tmp_r0, #0x2010, lsl 32
-                    // movk  tmp_r0, #0x8040, lsl 48
-                    // dup   tmp_v0.2d, tmp_r0
-                    // and   tmp_v1.16b, tmp_v1.16b, tmp_v0.16b
-                    // ext   tmp_v0.16b, tmp_v1.16b, tmp_v1.16b, #8
-                    // zip1  tmp_v0.16b, tmp_v1.16b, tmp_v0.16b
-                    // addv  tmp_v0h, tmp_v0.8h
-                    // mov   dst_r, tmp_v0.h[0]
-                    ctx.emit(Inst::VecShiftImm {
-                        op: VecShiftImmOp::Sshr,
-                        rd: tmp_v1,
-                        rn: src_v,
-                        size: VectorSize::Size8x16,
-                        imm: 7,
-                    });
-                    lower_splat_const(ctx, tmp_v0, 0x8040201008040201u64, VectorSize::Size64x2);
-                    ctx.emit(Inst::VecRRR {
-                        alu_op: VecALUOp::And,
-                        rd: tmp_v1,
-                        rn: tmp_v1.to_reg(),
-                        rm: tmp_v0.to_reg(),
-                        size: VectorSize::Size8x16,
-                    });
-                    ctx.emit(Inst::VecExtract {
-                        rd: tmp_v0,
-                        rn: tmp_v1.to_reg(),
-                        rm: tmp_v1.to_reg(),
-                        imm4: 8,
-                    });
-                    ctx.emit(Inst::VecRRR {
-                        alu_op: VecALUOp::Zip1,
-                        rd: tmp_v0,
-                        rn: tmp_v1.to_reg(),
-                        rm: tmp_v0.to_reg(),
-                        size: VectorSize::Size8x16,
-                    });
-                    ctx.emit(Inst::VecLanes {
-                        op: VecLanesOp::Addv,
-                        rd: tmp_v0,
-                        rn: tmp_v0.to_reg(),
-                        size: VectorSize::Size16x8,
-                    });
-                    ctx.emit(Inst::MovFromVec {
-                        rd: dst_r,
-                        rn: tmp_v0.to_reg(),
-                        idx: 0,
-                        size: VectorSize::Size16x8,
-                    });
-                }
-                I16X8 => {
-                    // sshr  tmp_v1.8h, src_v.8h, #15
-                    // mov   tmp_r0, #0x1
-                    // movk  tmp_r0, #0x2, lsl 16
-                    // movk  tmp_r0, #0x4, lsl 32
-                    // movk  tmp_r0, #0x8, lsl 48
-                    // dup   tmp_v0.2d, tmp_r0
-                    // shl   tmp_r0, tmp_r0, #4
-                    // mov   tmp_v0.d[1], tmp_r0
-                    // and   tmp_v0.16b, tmp_v1.16b, tmp_v0.16b
-                    // addv  tmp_v0h, tmp_v0.8h
-                    // mov   dst_r, tmp_v0.h[0]
-                    ctx.emit(Inst::VecShiftImm {
-                        op: VecShiftImmOp::Sshr,
-                        rd: tmp_v1,
-                        rn: src_v,
-                        size: VectorSize::Size16x8,
-                        imm: 15,
-                    });
-                    lower_constant_u64(ctx, tmp_r0, 0x0008000400020001u64);
-                    ctx.emit(Inst::VecDup {
-                        rd: tmp_v0,
-                        rn: tmp_r0.to_reg(),
-                        size: VectorSize::Size64x2,
-                    });
-                    ctx.emit(Inst::AluRRImmShift {
-                        alu_op: ALUOp::Lsl,
-                        size: OperandSize::Size64,
-                        rd: tmp_r0,
-                        rn: tmp_r0.to_reg(),
-                        immshift: ImmShift { imm: 4 },
-                    });
-                    ctx.emit(Inst::MovToVec {
-                        rd: tmp_v0,
-                        rn: tmp_r0.to_reg(),
-                        idx: 1,
-                        size: VectorSize::Size64x2,
-                    });
-                    ctx.emit(Inst::VecRRR {
-                        alu_op: VecALUOp::And,
-                        rd: tmp_v0,
-                        rn: tmp_v1.to_reg(),
-                        rm: tmp_v0.to_reg(),
-                        size: VectorSize::Size8x16,
-                    });
-                    ctx.emit(Inst::VecLanes {
-                        op: VecLanesOp::Addv,
-                        rd: tmp_v0,
-                        rn: tmp_v0.to_reg(),
-                        size: VectorSize::Size16x8,
-                    });
-                    ctx.emit(Inst::MovFromVec {
-                        rd: dst_r,
-                        rn: tmp_v0.to_reg(),
-                        idx: 0,
-                        size: VectorSize::Size16x8,
-                    });
-                }
-                I32X4 => {
-                    // sshr  tmp_v1.4s, src_v.4s, #31
-                    // mov   tmp_r0, #0x1
-                    // movk  tmp_r0, #0x2, lsl 32
-                    // dup   tmp_v0.2d, tmp_r0
-                    // shl   tmp_r0, tmp_r0, #2
-                    // mov   tmp_v0.d[1], tmp_r0
-                    // and   tmp_v0.16b, tmp_v1.16b, tmp_v0.16b
-                    // addv  tmp_v0s, tmp_v0.4s
-                    // mov   dst_r, tmp_v0.s[0]
-                    ctx.emit(Inst::VecShiftImm {
-                        op: VecShiftImmOp::Sshr,
-                        rd: tmp_v1,
-                        rn: src_v,
-                        size: VectorSize::Size32x4,
-                        imm: 31,
-                    });
-                    lower_constant_u64(ctx, tmp_r0, 0x0000000200000001u64);
-                    ctx.emit(Inst::VecDup {
-                        rd: tmp_v0,
-                        rn: tmp_r0.to_reg(),
-                        size: VectorSize::Size64x2,
-                    });
-                    ctx.emit(Inst::AluRRImmShift {
-                        alu_op: ALUOp::Lsl,
-                        size: OperandSize::Size64,
-                        rd: tmp_r0,
-                        rn: tmp_r0.to_reg(),
-                        immshift: ImmShift { imm: 2 },
-                    });
-                    ctx.emit(Inst::MovToVec {
-                        rd: tmp_v0,
-                        rn: tmp_r0.to_reg(),
-                        idx: 1,
-                        size: VectorSize::Size64x2,
-                    });
-                    ctx.emit(Inst::VecRRR {
-                        alu_op: VecALUOp::And,
-                        rd: tmp_v0,
-                        rn: tmp_v1.to_reg(),
-                        rm: tmp_v0.to_reg(),
-                        size: VectorSize::Size8x16,
-                    });
-                    ctx.emit(Inst::VecLanes {
-                        op: VecLanesOp::Addv,
-                        rd: tmp_v0,
-                        rn: tmp_v0.to_reg(),
-                        size: VectorSize::Size32x4,
-                    });
-                    ctx.emit(Inst::MovFromVec {
-                        rd: dst_r,
-                        rn: tmp_v0.to_reg(),
-                        idx: 0,
-                        size: VectorSize::Size32x4,
-                    });
-                }
-                I64X2 => {
-                    // mov dst_r, src_v.d[0]
-                    // mov tmp_r0, src_v.d[1]
-                    // lsr dst_r, dst_r, #63
-                    // lsr tmp_r0, tmp_r0, #63
-                    // add dst_r, dst_r, tmp_r0, lsl #1
-                    ctx.emit(Inst::MovFromVec {
-                        rd: dst_r,
-                        rn: src_v,
-                        idx: 0,
-                        size: VectorSize::Size64x2,
-                    });
-                    ctx.emit(Inst::MovFromVec {
-                        rd: tmp_r0,
-                        rn: src_v,
-                        idx: 1,
-                        size: VectorSize::Size64x2,
-                    });
-                    ctx.emit(Inst::AluRRImmShift {
-                        alu_op: ALUOp::Lsr,
-                        size: OperandSize::Size64,
-                        rd: dst_r,
-                        rn: dst_r.to_reg(),
-                        immshift: ImmShift::maybe_from_u64(63).unwrap(),
-                    });
-                    ctx.emit(Inst::AluRRImmShift {
-                        alu_op: ALUOp::Lsr,
-                        size: OperandSize::Size64,
-                        rd: tmp_r0,
-                        rn: tmp_r0.to_reg(),
-                        immshift: ImmShift::maybe_from_u64(63).unwrap(),
-                    });
-                    ctx.emit(Inst::AluRRRShift {
-                        alu_op: ALUOp::Add,
-                        size: OperandSize::Size32,
-                        rd: dst_r,
-                        rn: dst_r.to_reg(),
-                        rm: tmp_r0.to_reg(),
-                        shiftop: ShiftOpAndAmt::new(
-                            ShiftOp::LSL,
-                            ShiftOpShiftImm::maybe_from_shift(1).unwrap(),
-                        ),
-                    });
-                }
-                _ => {
-                    return Err(CodegenError::Unsupported(format!(
-                        "VhighBits: Unsupported type: {:?}",
-                        ty
-                    )))
-                }
-            }
-        }
-
-        Opcode::Shuffle => {
-            let mask = const_param_to_u128(ctx, insn).expect("Invalid immediate mask bytes");
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-            let rn2 = put_input_in_reg(ctx, inputs[1], NarrowValueMode::None);
-            // 2 register table vector lookups require consecutive table registers;
-            // we satisfy this constraint by hardcoding the usage of v29 and v30.
-            let temp = writable_vreg(29);
-            let temp2 = writable_vreg(30);
-            let input_ty = ctx.input_ty(insn, 0);
-            assert_eq!(input_ty, ctx.input_ty(insn, 1));
-            // Make sure that both inputs are in virtual registers, since it is
-            // not guaranteed that we can get them safely to the temporaries if
-            // either is in a real register.
-            let rn = ctx.ensure_in_vreg(rn, input_ty);
-            let rn2 = ctx.ensure_in_vreg(rn2, input_ty);
-
-            lower_constant_f128(ctx, rd, mask);
-            ctx.emit(Inst::gen_move(temp, rn, input_ty));
-            ctx.emit(Inst::gen_move(temp2, rn2, input_ty));
-            ctx.emit(Inst::VecTbl2 {
-                rd,
-                rn: temp.to_reg(),
-                rn2: temp2.to_reg(),
-                rm: rd.to_reg(),
-                is_extension: false,
-            });
-        }
-
-        Opcode::Swizzle => {
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let rm = put_input_in_reg(ctx, inputs[1], NarrowValueMode::None);
-            let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-
-            ctx.emit(Inst::VecTbl {
-                rd,
-                rn,
-                rm,
-                is_extension: false,
-            });
-        }
-
-        Opcode::Isplit => {
-            let input_ty = ctx.input_ty(insn, 0);
-
-            if input_ty != I128 {
-                return Err(CodegenError::Unsupported(format!(
-                    "Isplit: Unsupported type: {:?}",
-                    input_ty
-                )));
-            }
-
-            assert_eq!(ctx.output_ty(insn, 0), I64);
-            assert_eq!(ctx.output_ty(insn, 1), I64);
-
-            let src_regs = put_input_in_regs(ctx, inputs[0]);
-            let dst_lo = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let dst_hi = get_output_reg(ctx, outputs[1]).only_reg().unwrap();
-
-            ctx.emit(Inst::gen_move(dst_lo, src_regs.regs()[0], I64));
-            ctx.emit(Inst::gen_move(dst_hi, src_regs.regs()[1], I64));
-        }
-
-        Opcode::Iconcat => {
-            let ty = ty.unwrap();
-
-            if ty != I128 {
-                return Err(CodegenError::Unsupported(format!(
-                    "Iconcat: Unsupported type: {:?}",
-                    ty
-                )));
-            }
-
-            assert_eq!(ctx.input_ty(insn, 0), I64);
-            assert_eq!(ctx.input_ty(insn, 1), I64);
-
-            let src_lo = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-            let src_hi = put_input_in_reg(ctx, inputs[1], NarrowValueMode::None);
-            let dst = get_output_reg(ctx, outputs[0]);
-
-            ctx.emit(Inst::gen_move(dst.regs()[0], src_lo, I64));
-            ctx.emit(Inst::gen_move(dst.regs()[1], src_hi, I64));
-        }
-
-        Opcode::Imax | Opcode::Umax | Opcode::Umin | Opcode::Imin => {
-            let ty = ty.unwrap();
-
-            if !ty.is_vector() || ty.lane_bits() == 64 {
-                return Err(CodegenError::Unsupported(format!(
-                    "{}: Unsupported type: {:?}",
-                    op, ty
-                )));
-            }
-
-            let alu_op = match op {
-                Opcode::Umin => VecALUOp::Umin,
-                Opcode::Imin => VecALUOp::Smin,
-                Opcode::Umax => VecALUOp::Umax,
-                Opcode::Imax => VecALUOp::Smax,
-                _ => unreachable!(),
-            };
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-            let rm = put_input_in_reg(ctx, inputs[1], NarrowValueMode::None);
-            ctx.emit(Inst::VecRRR {
-                alu_op,
-                rd,
-                rn,
-                rm,
-                size: VectorSize::from_ty(ty),
-            });
-        }
-
-        Opcode::IaddPairwise => {
-            let ty = ty.unwrap();
-            let lane_type = ty.lane_type();
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-
-            let mut match_long_pair =
-                |ext_low_op, ext_high_op| -> Option<(VecRRPairLongOp, regalloc::Reg)> {
-                    if let Some(lhs) = maybe_input_insn(ctx, inputs[0], ext_low_op) {
-                        if let Some(rhs) = maybe_input_insn(ctx, inputs[1], ext_high_op) {
-                            let lhs_inputs = insn_inputs(ctx, lhs);
-                            let rhs_inputs = insn_inputs(ctx, rhs);
-                            let low = put_input_in_reg(ctx, lhs_inputs[0], NarrowValueMode::None);
-                            let high = put_input_in_reg(ctx, rhs_inputs[0], NarrowValueMode::None);
-                            if low == high {
-                                match (lane_type, ext_low_op) {
-                                    (I16, Opcode::SwidenLow) => {
-                                        return Some((VecRRPairLongOp::Saddlp8, low))
-                                    }
-                                    (I32, Opcode::SwidenLow) => {
-                                        return Some((VecRRPairLongOp::Saddlp16, low))
-                                    }
-                                    (I16, Opcode::UwidenLow) => {
-                                        return Some((VecRRPairLongOp::Uaddlp8, low))
-                                    }
-                                    (I32, Opcode::UwidenLow) => {
-                                        return Some((VecRRPairLongOp::Uaddlp16, low))
-                                    }
-                                    _ => (),
-                                };
-                            }
-                        }
-                    }
-                    None
-                };
-
-            if let Some((op, rn)) = match_long_pair(Opcode::SwidenLow, Opcode::SwidenHigh) {
-                ctx.emit(Inst::VecRRPairLong { op, rd, rn });
-            } else if let Some((op, rn)) = match_long_pair(Opcode::UwidenLow, Opcode::UwidenHigh) {
-                ctx.emit(Inst::VecRRPairLong { op, rd, rn });
-            } else {
-                let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-                let rm = put_input_in_reg(ctx, inputs[1], NarrowValueMode::None);
-                ctx.emit(Inst::VecRRR {
-                    alu_op: VecALUOp::Addp,
-                    rd,
-                    rn,
-                    rm,
-                    size: VectorSize::from_ty(ty),
-                });
-            }
-        }
-
-        Opcode::WideningPairwiseDotProductS => {
-            let r_y = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let r_a = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-            let r_b = put_input_in_reg(ctx, inputs[1], NarrowValueMode::None);
-            let ty = ty.unwrap();
-            if ty == I32X4 {
-                let tmp = ctx.alloc_tmp(I8X16).only_reg().unwrap();
-                // The args have type I16X8.
-                // "y = i32x4.dot_i16x8_s(a, b)"
-                // => smull  tmp, a, b
-                //    smull2 y,   a, b
-                //    addp   y,   tmp, y
-                ctx.emit(Inst::VecRRRLong {
-                    alu_op: VecRRRLongOp::Smull16,
-                    rd: tmp,
-                    rn: r_a,
-                    rm: r_b,
-                    high_half: false,
-                });
-                ctx.emit(Inst::VecRRRLong {
-                    alu_op: VecRRRLongOp::Smull16,
-                    rd: r_y,
-                    rn: r_a,
-                    rm: r_b,
-                    high_half: true,
-                });
-                ctx.emit(Inst::VecRRR {
-                    alu_op: VecALUOp::Addp,
-                    rd: r_y,
-                    rn: tmp.to_reg(),
-                    rm: r_y.to_reg(),
-                    size: VectorSize::Size32x4,
-                });
-            } else {
-                return Err(CodegenError::Unsupported(format!(
-                    "Opcode::WideningPairwiseDotProductS: unsupported laneage: {:?}",
-                    ty
-                )));
-            }
-        }
-
-        Opcode::Fadd | Opcode::Fsub | Opcode::Fmul | Opcode::Fdiv | Opcode::Fmin | Opcode::Fmax => {
-            let ty = ty.unwrap();
-            let bits = ty_bits(ty);
-            let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-            let rm = put_input_in_reg(ctx, inputs[1], NarrowValueMode::None);
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            if !ty.is_vector() {
-                let fpu_op = match (op, bits) {
-                    (Opcode::Fadd, 32) => FPUOp2::Add32,
-                    (Opcode::Fadd, 64) => FPUOp2::Add64,
-                    (Opcode::Fsub, 32) => FPUOp2::Sub32,
-                    (Opcode::Fsub, 64) => FPUOp2::Sub64,
-                    (Opcode::Fmul, 32) => FPUOp2::Mul32,
-                    (Opcode::Fmul, 64) => FPUOp2::Mul64,
-                    (Opcode::Fdiv, 32) => FPUOp2::Div32,
-                    (Opcode::Fdiv, 64) => FPUOp2::Div64,
-                    (Opcode::Fmin, 32) => FPUOp2::Min32,
-                    (Opcode::Fmin, 64) => FPUOp2::Min64,
-                    (Opcode::Fmax, 32) => FPUOp2::Max32,
-                    (Opcode::Fmax, 64) => FPUOp2::Max64,
-                    _ => {
-                        return Err(CodegenError::Unsupported(format!(
-                            "{}: Unsupported type: {:?}",
-                            op, ty
-                        )))
-                    }
-                };
-                ctx.emit(Inst::FpuRRR { fpu_op, rd, rn, rm });
-            } else {
-                let alu_op = match op {
-                    Opcode::Fadd => VecALUOp::Fadd,
-                    Opcode::Fsub => VecALUOp::Fsub,
-                    Opcode::Fdiv => VecALUOp::Fdiv,
-                    Opcode::Fmax => VecALUOp::Fmax,
-                    Opcode::Fmin => VecALUOp::Fmin,
-                    Opcode::Fmul => VecALUOp::Fmul,
-                    _ => unreachable!(),
-                };
-
-                ctx.emit(Inst::VecRRR {
-                    rd,
-                    rn,
-                    rm,
-                    alu_op,
-                    size: VectorSize::from_ty(ty),
-                });
-            }
-        }
-
-        Opcode::FminPseudo | Opcode::FmaxPseudo => {
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let rm = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-            let rn = put_input_in_reg(ctx, inputs[1], NarrowValueMode::None);
-            let (ra, rb) = if op == Opcode::FminPseudo {
-                (rm, rn)
-            } else {
-                (rn, rm)
-            };
-            let ty = ty.unwrap();
-            let lane_type = ty.lane_type();
-
-            debug_assert!(lane_type == F32 || lane_type == F64);
-
-            if ty.is_vector() {
-                let size = VectorSize::from_ty(ty);
-
-                // pmin(a,b) => bitsel(b, a, cmpgt(a, b))
-                // pmax(a,b) => bitsel(b, a, cmpgt(b, a))
-                // Since we're going to write the output register `rd` anyway, we might as well
-                // first use it to hold the comparison result.  This has the slightly unusual
-                // effect that we modify the output register in the first instruction (`fcmgt`)
-                // but read both the inputs again in the second instruction (`bsl`), which means
-                // that the output register can't be either of the input registers.  Regalloc
-                // should handle this correctly, nevertheless.
-                ctx.emit(Inst::VecRRR {
-                    alu_op: VecALUOp::Fcmgt,
-                    rd,
-                    rn: ra,
-                    rm: rb,
-                    size,
-                });
-                ctx.emit(Inst::VecRRR {
-                    alu_op: VecALUOp::Bsl,
-                    rd,
-                    rn,
-                    rm,
-                    size,
-                });
-            } else {
-                if lane_type == F32 {
-                    ctx.emit(Inst::FpuCmp32 { rn: ra, rm: rb });
-                    ctx.emit(Inst::FpuCSel32 {
-                        rd,
-                        rn,
-                        rm,
-                        cond: Cond::Gt,
-                    });
-                } else {
-                    ctx.emit(Inst::FpuCmp64 { rn: ra, rm: rb });
-                    ctx.emit(Inst::FpuCSel64 {
-                        rd,
-                        rn,
-                        rm,
-                        cond: Cond::Gt,
-                    });
-                }
-            }
-        }
-
-        Opcode::Sqrt | Opcode::Fneg | Opcode::Fabs | Opcode::Fpromote | Opcode::Fdemote => {
-            let ty = ty.unwrap();
-            let bits = ty_bits(ty);
-            let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            if !ty.is_vector() {
-                let fpu_op = match (op, bits) {
-                    (Opcode::Sqrt, 32) => FPUOp1::Sqrt32,
-                    (Opcode::Sqrt, 64) => FPUOp1::Sqrt64,
-                    (Opcode::Fneg, 32) => FPUOp1::Neg32,
-                    (Opcode::Fneg, 64) => FPUOp1::Neg64,
-                    (Opcode::Fabs, 32) => FPUOp1::Abs32,
-                    (Opcode::Fabs, 64) => FPUOp1::Abs64,
-                    (Opcode::Fpromote, 64) => FPUOp1::Cvt32To64,
-                    (Opcode::Fdemote, 32) => FPUOp1::Cvt64To32,
-                    _ => {
-                        return Err(CodegenError::Unsupported(format!(
-                            "{}: Unsupported type: {:?}",
-                            op, ty
-                        )))
-                    }
-                };
-                ctx.emit(Inst::FpuRR { fpu_op, rd, rn });
-            } else {
-                let op = match op {
-                    Opcode::Fabs => VecMisc2::Fabs,
-                    Opcode::Fneg => VecMisc2::Fneg,
-                    Opcode::Sqrt => VecMisc2::Fsqrt,
-                    _ => {
-                        return Err(CodegenError::Unsupported(format!(
-                            "{}: Unsupported type: {:?}",
-                            op, ty
-                        )))
-                    }
-                };
-
-                ctx.emit(Inst::VecMisc {
-                    op,
-                    rd,
-                    rn,
-                    size: VectorSize::from_ty(ty),
-                });
-            }
-        }
-
-        Opcode::Ceil | Opcode::Floor | Opcode::Trunc | Opcode::Nearest => {
-            let ty = ctx.output_ty(insn, 0);
-            if !ty.is_vector() {
-                let bits = ty_bits(ty);
-                let op = match (op, bits) {
-                    (Opcode::Ceil, 32) => FpuRoundMode::Plus32,
-                    (Opcode::Ceil, 64) => FpuRoundMode::Plus64,
-                    (Opcode::Floor, 32) => FpuRoundMode::Minus32,
-                    (Opcode::Floor, 64) => FpuRoundMode::Minus64,
-                    (Opcode::Trunc, 32) => FpuRoundMode::Zero32,
-                    (Opcode::Trunc, 64) => FpuRoundMode::Zero64,
-                    (Opcode::Nearest, 32) => FpuRoundMode::Nearest32,
-                    (Opcode::Nearest, 64) => FpuRoundMode::Nearest64,
-                    _ => {
-                        return Err(CodegenError::Unsupported(format!(
-                            "{}: Unsupported type: {:?}",
-                            op, ty
-                        )))
-                    }
-                };
-                let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-                let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-                ctx.emit(Inst::FpuRound { op, rd, rn });
-            } else {
-                let (op, size) = match (op, ty) {
-                    (Opcode::Ceil, F32X4) => (VecMisc2::Frintp, VectorSize::Size32x4),
-                    (Opcode::Ceil, F64X2) => (VecMisc2::Frintp, VectorSize::Size64x2),
-                    (Opcode::Floor, F32X4) => (VecMisc2::Frintm, VectorSize::Size32x4),
-                    (Opcode::Floor, F64X2) => (VecMisc2::Frintm, VectorSize::Size64x2),
-                    (Opcode::Trunc, F32X4) => (VecMisc2::Frintz, VectorSize::Size32x4),
-                    (Opcode::Trunc, F64X2) => (VecMisc2::Frintz, VectorSize::Size64x2),
-                    (Opcode::Nearest, F32X4) => (VecMisc2::Frintn, VectorSize::Size32x4),
-                    (Opcode::Nearest, F64X2) => (VecMisc2::Frintn, VectorSize::Size64x2),
-                    _ => {
-                        return Err(CodegenError::Unsupported(format!(
-                            "{}: Unsupported type: {:?}",
-                            op, ty
-                        )))
-                    }
-                };
-                let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-                let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-                ctx.emit(Inst::VecMisc { op, rd, rn, size });
-            }
-        }
-
-        Opcode::Fma => {
-            let ty = ty.unwrap();
-            let bits = ty_bits(ty);
-            let fpu_op = match bits {
-                32 => FPUOp3::MAdd32,
-                64 => FPUOp3::MAdd64,
-                _ => {
-                    return Err(CodegenError::Unsupported(format!(
-                        "Fma: Unsupported type: {:?}",
-                        ty
-                    )))
-                }
-            };
-            let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-            let rm = put_input_in_reg(ctx, inputs[1], NarrowValueMode::None);
-            let ra = put_input_in_reg(ctx, inputs[2], NarrowValueMode::None);
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            ctx.emit(Inst::FpuRRRR {
-                fpu_op,
-                rn,
-                rm,
-                ra,
-                rd,
-            });
-        }
-
-        Opcode::Fcopysign => {
-            // Copy the sign bit from inputs[1] to inputs[0]. We use the following sequence:
-            //
-            // This is a scalar Fcopysign.
-            // This uses scalar NEON operations for 64-bit and vector operations (2S) for 32-bit.
-            // In the latter case it still sets all bits except the lowest 32 to 0.
-            //
-            //  mov vd, vn
-            //  ushr vtmp, vm, #63 / #31
-            //  sli vd, vtmp, #63 / #31
-
-            let ty = ctx.output_ty(insn, 0);
-
-            if ty != F32 && ty != F64 {
-                return Err(CodegenError::Unsupported(format!(
-                    "Fcopysign: Unsupported type: {:?}",
-                    ty
-                )));
-            }
-
-            let bits = ty_bits(ty) as u8;
-            let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-            let rm = put_input_in_reg(ctx, inputs[1], NarrowValueMode::None);
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let tmp = ctx.alloc_tmp(F64).only_reg().unwrap();
-
-            // Copy LHS to rd.
-            ctx.emit(Inst::gen_move(rd, rn, ty));
-
-            // Copy the sign bit to the lowest bit in tmp.
-            let imm = FPURightShiftImm::maybe_from_u8(bits - 1, bits).unwrap();
-            ctx.emit(Inst::FpuRRI {
-                fpu_op: choose_32_64(ty, FPUOpRI::UShr32(imm), FPUOpRI::UShr64(imm)),
-                rd: tmp,
-                rn: rm,
-            });
-
-            // Insert the bit from tmp into the sign bit of rd.
-            let imm = FPULeftShiftImm::maybe_from_u8(bits - 1, bits).unwrap();
-            ctx.emit(Inst::FpuRRI {
-                fpu_op: choose_32_64(ty, FPUOpRI::Sli32(imm), FPUOpRI::Sli64(imm)),
-                rd,
-                rn: tmp.to_reg(),
-            });
-        }
-
-        Opcode::FcvtToUint | Opcode::FcvtToSint => {
-            let input_ty = ctx.input_ty(insn, 0);
-            let in_bits = ty_bits(input_ty);
-            let output_ty = ty.unwrap();
-            let out_bits = ty_bits(output_ty);
-            let signed = op == Opcode::FcvtToSint;
-            let op = match (signed, in_bits, out_bits) {
-                (false, 32, 8) | (false, 32, 16) | (false, 32, 32) => FpuToIntOp::F32ToU32,
-                (true, 32, 8) | (true, 32, 16) | (true, 32, 32) => FpuToIntOp::F32ToI32,
-                (false, 32, 64) => FpuToIntOp::F32ToU64,
-                (true, 32, 64) => FpuToIntOp::F32ToI64,
-                (false, 64, 8) | (false, 64, 16) | (false, 64, 32) => FpuToIntOp::F64ToU32,
-                (true, 64, 8) | (true, 64, 16) | (true, 64, 32) => FpuToIntOp::F64ToI32,
-                (false, 64, 64) => FpuToIntOp::F64ToU64,
-                (true, 64, 64) => FpuToIntOp::F64ToI64,
-                _ => {
-                    return Err(CodegenError::Unsupported(format!(
-                        "{}: Unsupported types: {:?} -> {:?}",
-                        op, input_ty, output_ty
-                    )))
-                }
-            };
-
-            let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-
-            // First, check the output: it's important to carry the NaN conversion before the
-            // in-bounds conversion, per wasm semantics.
-
-            // Check that the input is not a NaN.
-            if in_bits == 32 {
-                ctx.emit(Inst::FpuCmp32 { rn, rm: rn });
-            } else {
-                ctx.emit(Inst::FpuCmp64 { rn, rm: rn });
-            }
-            let trap_code = TrapCode::BadConversionToInteger;
-            ctx.emit(Inst::TrapIf {
-                trap_code,
-                kind: CondBrKind::Cond(lower_fp_condcode(FloatCC::Unordered)),
-            });
-
-            let tmp = ctx.alloc_tmp(I8X16).only_reg().unwrap();
-
-            // Check that the input is in range, with "truncate towards zero" semantics. This means
-            // we allow values that are slightly out of range:
-            // - for signed conversions, we allow values strictly greater than INT_MIN-1 (when this
-            // can be represented), and strictly less than INT_MAX+1 (when this can be
-            // represented).
-            // - for unsigned conversions, we allow values strictly greater than -1, and strictly
-            // less than UINT_MAX+1 (when this can be represented).
-
-            if in_bits == 32 {
-                // From float32.
-                let (low_bound, low_cond, high_bound) = match (signed, out_bits) {
-                    (true, 8) => (
-                        i8::min_value() as f32 - 1.,
-                        FloatCC::GreaterThan,
-                        i8::max_value() as f32 + 1.,
-                    ),
-                    (true, 16) => (
-                        i16::min_value() as f32 - 1.,
-                        FloatCC::GreaterThan,
-                        i16::max_value() as f32 + 1.,
-                    ),
-                    (true, 32) => (
-                        i32::min_value() as f32, // I32_MIN - 1 isn't precisely representable as a f32.
-                        FloatCC::GreaterThanOrEqual,
-                        i32::max_value() as f32 + 1.,
-                    ),
-                    (true, 64) => (
-                        i64::min_value() as f32, // I64_MIN - 1 isn't precisely representable as a f32.
-                        FloatCC::GreaterThanOrEqual,
-                        i64::max_value() as f32 + 1.,
-                    ),
-                    (false, 8) => (-1., FloatCC::GreaterThan, u8::max_value() as f32 + 1.),
-                    (false, 16) => (-1., FloatCC::GreaterThan, u16::max_value() as f32 + 1.),
-                    (false, 32) => (-1., FloatCC::GreaterThan, u32::max_value() as f32 + 1.),
-                    (false, 64) => (-1., FloatCC::GreaterThan, u64::max_value() as f32 + 1.),
-                    _ => unreachable!(),
-                };
-
-                // >= low_bound
-                lower_constant_f32(ctx, tmp, low_bound);
-                ctx.emit(Inst::FpuCmp32 {
-                    rn,
-                    rm: tmp.to_reg(),
-                });
-                let trap_code = TrapCode::IntegerOverflow;
-                ctx.emit(Inst::TrapIf {
-                    trap_code,
-                    kind: CondBrKind::Cond(lower_fp_condcode(low_cond).invert()),
-                });
-
-                // <= high_bound
-                lower_constant_f32(ctx, tmp, high_bound);
-                ctx.emit(Inst::FpuCmp32 {
-                    rn,
-                    rm: tmp.to_reg(),
-                });
-                let trap_code = TrapCode::IntegerOverflow;
-                ctx.emit(Inst::TrapIf {
-                    trap_code,
-                    kind: CondBrKind::Cond(lower_fp_condcode(FloatCC::LessThan).invert()),
-                });
-            } else {
-                // From float64.
-                let (low_bound, low_cond, high_bound) = match (signed, out_bits) {
-                    (true, 8) => (
-                        i8::min_value() as f64 - 1.,
-                        FloatCC::GreaterThan,
-                        i8::max_value() as f64 + 1.,
-                    ),
-                    (true, 16) => (
-                        i16::min_value() as f64 - 1.,
-                        FloatCC::GreaterThan,
-                        i16::max_value() as f64 + 1.,
-                    ),
-                    (true, 32) => (
-                        i32::min_value() as f64 - 1.,
-                        FloatCC::GreaterThan,
-                        i32::max_value() as f64 + 1.,
-                    ),
-                    (true, 64) => (
-                        i64::min_value() as f64, // I64_MIN - 1 is not precisely representable as an i64.
-                        FloatCC::GreaterThanOrEqual,
-                        i64::max_value() as f64 + 1.,
-                    ),
-                    (false, 8) => (-1., FloatCC::GreaterThan, u8::max_value() as f64 + 1.),
-                    (false, 16) => (-1., FloatCC::GreaterThan, u16::max_value() as f64 + 1.),
-                    (false, 32) => (-1., FloatCC::GreaterThan, u32::max_value() as f64 + 1.),
-                    (false, 64) => (-1., FloatCC::GreaterThan, u64::max_value() as f64 + 1.),
-                    _ => unreachable!(),
-                };
-
-                // >= low_bound
-                lower_constant_f64(ctx, tmp, low_bound);
-                ctx.emit(Inst::FpuCmp64 {
-                    rn,
-                    rm: tmp.to_reg(),
-                });
-                let trap_code = TrapCode::IntegerOverflow;
-                ctx.emit(Inst::TrapIf {
-                    trap_code,
-                    kind: CondBrKind::Cond(lower_fp_condcode(low_cond).invert()),
-                });
-
-                // <= high_bound
-                lower_constant_f64(ctx, tmp, high_bound);
-                ctx.emit(Inst::FpuCmp64 {
-                    rn,
-                    rm: tmp.to_reg(),
-                });
-                let trap_code = TrapCode::IntegerOverflow;
-                ctx.emit(Inst::TrapIf {
-                    trap_code,
-                    kind: CondBrKind::Cond(lower_fp_condcode(FloatCC::LessThan).invert()),
-                });
-            };
-
-            // Do the conversion.
-            ctx.emit(Inst::FpuToInt { op, rd, rn });
-        }
-
-        Opcode::FcvtFromUint | Opcode::FcvtFromSint => {
-            let input_ty = ctx.input_ty(insn, 0);
-            let ty = ty.unwrap();
-            let signed = op == Opcode::FcvtFromSint;
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-
-            if ty.is_vector() {
-                if input_ty.lane_bits() != ty.lane_bits() {
-                    return Err(CodegenError::Unsupported(format!(
-                        "{}: Unsupported types: {:?} -> {:?}",
-                        op, input_ty, ty
-                    )));
-                }
-
-                let op = if signed {
-                    VecMisc2::Scvtf
-                } else {
-                    VecMisc2::Ucvtf
-                };
-                let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-
-                ctx.emit(Inst::VecMisc {
-                    op,
-                    rd,
-                    rn,
-                    size: VectorSize::from_ty(ty),
-                });
-            } else {
-                let in_bits = ty_bits(input_ty);
-                let out_bits = ty_bits(ty);
-                let op = match (signed, in_bits, out_bits) {
-                    (false, 8, 32) | (false, 16, 32) | (false, 32, 32) => IntToFpuOp::U32ToF32,
-                    (true, 8, 32) | (true, 16, 32) | (true, 32, 32) => IntToFpuOp::I32ToF32,
-                    (false, 8, 64) | (false, 16, 64) | (false, 32, 64) => IntToFpuOp::U32ToF64,
-                    (true, 8, 64) | (true, 16, 64) | (true, 32, 64) => IntToFpuOp::I32ToF64,
-                    (false, 64, 32) => IntToFpuOp::U64ToF32,
-                    (true, 64, 32) => IntToFpuOp::I64ToF32,
-                    (false, 64, 64) => IntToFpuOp::U64ToF64,
-                    (true, 64, 64) => IntToFpuOp::I64ToF64,
-                    _ => {
-                        return Err(CodegenError::Unsupported(format!(
-                            "{}: Unsupported types: {:?} -> {:?}",
-                            op, input_ty, ty
-                        )))
-                    }
-                };
-                let narrow_mode = match (signed, in_bits) {
-                    (false, 8) | (false, 16) | (false, 32) => NarrowValueMode::ZeroExtend32,
-                    (true, 8) | (true, 16) | (true, 32) => NarrowValueMode::SignExtend32,
-                    (false, 64) => NarrowValueMode::ZeroExtend64,
-                    (true, 64) => NarrowValueMode::SignExtend64,
-                    _ => unreachable!(),
-                };
-                let rn = put_input_in_reg(ctx, inputs[0], narrow_mode);
-                ctx.emit(Inst::IntToFpu { op, rd, rn });
-            }
-        }
-
-        Opcode::FcvtToUintSat | Opcode::FcvtToSintSat => {
-            let in_ty = ctx.input_ty(insn, 0);
-            let ty = ty.unwrap();
-            let out_signed = op == Opcode::FcvtToSintSat;
-            let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-
-            if ty.is_vector() {
-                if in_ty.lane_bits() != ty.lane_bits() {
-                    return Err(CodegenError::Unsupported(format!(
-                        "{}: Unsupported types: {:?} -> {:?}",
-                        op, in_ty, ty
-                    )));
-                }
-
-                let op = if out_signed {
-                    VecMisc2::Fcvtzs
-                } else {
-                    VecMisc2::Fcvtzu
-                };
-
-                ctx.emit(Inst::VecMisc {
-                    op,
-                    rd,
-                    rn,
-                    size: VectorSize::from_ty(ty),
-                });
-            } else {
-                let in_bits = ty_bits(in_ty);
-                let out_bits = ty_bits(ty);
-                // FIMM Vtmp1, u32::MAX or u64::MAX or i32::MAX or i64::MAX
-                // FMIN Vtmp2, Vin, Vtmp1
-                // FIMM Vtmp1, 0 or 0 or i32::MIN or i64::MIN
-                // FMAX Vtmp2, Vtmp2, Vtmp1
-                // (if signed) FIMM Vtmp1, 0
-                // FCMP Vin, Vin
-                // FCSEL Vtmp2, Vtmp1, Vtmp2, NE  // on NaN, select 0
-                // convert Rout, Vtmp2
-
-                assert!(in_ty.is_float() && (in_bits == 32 || in_bits == 64));
-                assert!(out_bits == 32 || out_bits == 64);
-
-                let min: f64 = match (out_bits, out_signed) {
-                    (32, true) => std::i32::MIN as f64,
-                    (32, false) => 0.0,
-                    (64, true) => std::i64::MIN as f64,
-                    (64, false) => 0.0,
-                    _ => unreachable!(),
-                };
-
-                let max = match (out_bits, out_signed) {
-                    (32, true) => std::i32::MAX as f64,
-                    (32, false) => std::u32::MAX as f64,
-                    (64, true) => std::i64::MAX as f64,
-                    (64, false) => std::u64::MAX as f64,
-                    _ => unreachable!(),
-                };
-
-                let rtmp1 = ctx.alloc_tmp(in_ty).only_reg().unwrap();
-                let rtmp2 = ctx.alloc_tmp(in_ty).only_reg().unwrap();
-
-                if in_bits == 32 {
-                    lower_constant_f32(ctx, rtmp1, max as f32);
-                } else {
-                    lower_constant_f64(ctx, rtmp1, max);
-                }
-                ctx.emit(Inst::FpuRRR {
-                    fpu_op: choose_32_64(in_ty, FPUOp2::Min32, FPUOp2::Min64),
-                    rd: rtmp2,
-                    rn,
-                    rm: rtmp1.to_reg(),
-                });
-                if in_bits == 32 {
-                    lower_constant_f32(ctx, rtmp1, min as f32);
-                } else {
-                    lower_constant_f64(ctx, rtmp1, min);
-                }
-                ctx.emit(Inst::FpuRRR {
-                    fpu_op: choose_32_64(in_ty, FPUOp2::Max32, FPUOp2::Max64),
-                    rd: rtmp2,
-                    rn: rtmp2.to_reg(),
-                    rm: rtmp1.to_reg(),
-                });
-                if out_signed {
-                    if in_bits == 32 {
-                        lower_constant_f32(ctx, rtmp1, 0.0);
-                    } else {
-                        lower_constant_f64(ctx, rtmp1, 0.0);
-                    }
-                }
-                if in_bits == 32 {
-                    ctx.emit(Inst::FpuCmp32 { rn, rm: rn });
-                    ctx.emit(Inst::FpuCSel32 {
-                        rd: rtmp2,
-                        rn: rtmp1.to_reg(),
-                        rm: rtmp2.to_reg(),
-                        cond: Cond::Ne,
-                    });
-                } else {
-                    ctx.emit(Inst::FpuCmp64 { rn, rm: rn });
-                    ctx.emit(Inst::FpuCSel64 {
-                        rd: rtmp2,
-                        rn: rtmp1.to_reg(),
-                        rm: rtmp2.to_reg(),
-                        cond: Cond::Ne,
-                    });
-                }
-
-                let cvt = match (in_bits, out_bits, out_signed) {
-                    (32, 32, false) => FpuToIntOp::F32ToU32,
-                    (32, 32, true) => FpuToIntOp::F32ToI32,
-                    (32, 64, false) => FpuToIntOp::F32ToU64,
-                    (32, 64, true) => FpuToIntOp::F32ToI64,
-                    (64, 32, false) => FpuToIntOp::F64ToU32,
-                    (64, 32, true) => FpuToIntOp::F64ToI32,
-                    (64, 64, false) => FpuToIntOp::F64ToU64,
-                    (64, 64, true) => FpuToIntOp::F64ToI64,
-                    _ => unreachable!(),
-                };
-                ctx.emit(Inst::FpuToInt {
-                    op: cvt,
-                    rd,
-                    rn: rtmp2.to_reg(),
-                });
-            }
-        }
-
-        Opcode::IaddIfcout => {
-            // This is a two-output instruction that is needed for the
-            // legalizer's explicit heap-check sequence, among possible other
-            // uses. Its second output is a flags output only ever meant to
-            // check for overflow using the
-            // `backend.unsigned_add_overflow_condition()` condition.
-            //
-            // Note that the CLIF validation will ensure that no flag-setting
-            // operation comes between this IaddIfcout and its use (e.g., a
-            // Trapif). Thus, we can rely on implicit communication through the
-            // processor flags rather than explicitly generating flags into a
-            // register. We simply use the variant of the add instruction that
-            // sets flags (`adds`) here.
-
-            // Note that the second output (the flags) need not be generated,
-            // because flags are never materialized into a register; the only
-            // instructions that can use a value of type `iflags` or `fflags`
-            // will look directly for the flags-producing instruction (which can
-            // always be found, by construction) and merge it.
-
-            // Now handle the iadd as above, except use an AddS opcode that sets
-            // flags.
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-            let rm = put_input_in_rse_imm12(ctx, inputs[1], NarrowValueMode::None);
-            let ty = ty.unwrap();
-            ctx.emit(alu_inst_imm12(ALUOp::AddS, ty, rd, rn, rm));
-        }
-
-        Opcode::IaddImm
-        | Opcode::ImulImm
-        | Opcode::UdivImm
-        | Opcode::SdivImm
-        | Opcode::UremImm
-        | Opcode::SremImm
-        | Opcode::IrsubImm
-        | Opcode::IaddCin
-        | Opcode::IaddIfcin
-        | Opcode::IaddCout
-        | Opcode::IaddCarry
-        | Opcode::IaddIfcarry
-        | Opcode::IsubBin
-        | Opcode::IsubIfbin
-        | Opcode::IsubBout
-        | Opcode::IsubIfbout
-        | Opcode::IsubBorrow
-        | Opcode::IsubIfborrow
-        | Opcode::BandImm
-        | Opcode::BorImm
-        | Opcode::BxorImm
-        | Opcode::RotlImm
-        | Opcode::RotrImm
-        | Opcode::IshlImm
-        | Opcode::UshrImm
-        | Opcode::SshrImm
-        | Opcode::IcmpImm
-        | Opcode::IfcmpImm => {
-            panic!("ALU+imm and ALU+carry ops should not appear here!");
-        }
-
-        Opcode::Iabs => {
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-            let ty = ty.unwrap();
-            ctx.emit(Inst::VecMisc {
-                op: VecMisc2::Abs,
-                rd,
-                rn,
-                size: VectorSize::from_ty(ty),
-            });
-        }
-        Opcode::AvgRound => {
-            let ty = ty.unwrap();
-
-            if ty.lane_bits() == 64 {
-                return Err(CodegenError::Unsupported(format!(
-                    "AvgRound: Unsupported type: {:?}",
-                    ty
-                )));
-            }
-
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-            let rm = put_input_in_reg(ctx, inputs[1], NarrowValueMode::None);
-            ctx.emit(Inst::VecRRR {
-                alu_op: VecALUOp::Urhadd,
-                rd,
-                rn,
-                rm,
-                size: VectorSize::from_ty(ty),
-            });
-        }
-
-        Opcode::Snarrow | Opcode::Unarrow | Opcode::Uunarrow => {
-            let nonzero_high_half = maybe_input_insn(ctx, inputs[1], Opcode::Vconst)
-                .map_or(true, |insn| {
-                    const_param_to_u128(ctx, insn).expect("Invalid immediate bytes") != 0
-                });
-            let op = match (op, ty.unwrap()) {
-                (Opcode::Snarrow, I8X16) => VecRRNarrowOp::Sqxtn16,
-                (Opcode::Snarrow, I16X8) => VecRRNarrowOp::Sqxtn32,
-                (Opcode::Snarrow, I32X4) => VecRRNarrowOp::Sqxtn64,
-                (Opcode::Unarrow, I8X16) => VecRRNarrowOp::Sqxtun16,
-                (Opcode::Unarrow, I16X8) => VecRRNarrowOp::Sqxtun32,
-                (Opcode::Unarrow, I32X4) => VecRRNarrowOp::Sqxtun64,
-                (Opcode::Uunarrow, I8X16) => VecRRNarrowOp::Uqxtn16,
-                (Opcode::Uunarrow, I16X8) => VecRRNarrowOp::Uqxtn32,
-                (Opcode::Uunarrow, I32X4) => VecRRNarrowOp::Uqxtn64,
-                (_, ty) => {
-                    return Err(CodegenError::Unsupported(format!(
-                        "{}: Unsupported type: {:?}",
-                        op, ty
-                    )))
-                }
-            };
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-
-            ctx.emit(Inst::VecRRNarrow {
-                op,
-                rd,
-                rn,
-                high_half: false,
-            });
-
-            if nonzero_high_half {
-                let rn = put_input_in_reg(ctx, inputs[1], NarrowValueMode::None);
-
-                ctx.emit(Inst::VecRRNarrow {
-                    op,
-                    rd,
-                    rn,
-                    high_half: true,
-                });
-            }
-        }
-
-        Opcode::SwidenLow | Opcode::SwidenHigh | Opcode::UwidenLow | Opcode::UwidenHigh => {
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-            let (t, high_half) = match (ty.unwrap(), op) {
-                (I16X8, Opcode::SwidenLow) => (VecExtendOp::Sxtl8, false),
-                (I16X8, Opcode::SwidenHigh) => (VecExtendOp::Sxtl8, true),
-                (I16X8, Opcode::UwidenLow) => (VecExtendOp::Uxtl8, false),
-                (I16X8, Opcode::UwidenHigh) => (VecExtendOp::Uxtl8, true),
-                (I32X4, Opcode::SwidenLow) => (VecExtendOp::Sxtl16, false),
-                (I32X4, Opcode::SwidenHigh) => (VecExtendOp::Sxtl16, true),
-                (I32X4, Opcode::UwidenLow) => (VecExtendOp::Uxtl16, false),
-                (I32X4, Opcode::UwidenHigh) => (VecExtendOp::Uxtl16, true),
-                (I64X2, Opcode::SwidenLow) => (VecExtendOp::Sxtl32, false),
-                (I64X2, Opcode::SwidenHigh) => (VecExtendOp::Sxtl32, true),
-                (I64X2, Opcode::UwidenLow) => (VecExtendOp::Uxtl32, false),
-                (I64X2, Opcode::UwidenHigh) => (VecExtendOp::Uxtl32, true),
-                (ty, _) => {
-                    return Err(CodegenError::Unsupported(format!(
-                        "{}: Unsupported type: {:?}",
-                        op, ty
-                    )));
-                }
-            };
-
-            ctx.emit(Inst::VecExtend {
-                t,
-                rd,
-                rn,
-                high_half,
-            });
-        }
-
-        Opcode::TlsValue => match flags.tls_model() {
-            TlsModel::ElfGd => {
-                let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-                let (name, _, _) = ctx.symbol_value(insn).unwrap();
-                let symbol = name.clone();
-                ctx.emit(Inst::ElfTlsGetAddr { symbol });
-
-                let x0 = xreg(0);
-                ctx.emit(Inst::gen_move(dst, x0, I64));
-            }
-            _ => {
-                return Err(CodegenError::Unsupported(format!(
-                    "Unimplemented TLS model in AArch64 backend: {:?}",
-                    flags.tls_model()
-                )));
-            }
-        },
-
-        Opcode::SqmulRoundSat => {
-            let ty = ty.unwrap();
-
-            if !ty.is_vector() || (ty.lane_type() != I16 && ty.lane_type() != I32) {
-                return Err(CodegenError::Unsupported(format!(
-                    "SqmulRoundSat: Unsupported type: {:?}",
-                    ty
-                )));
-            }
-
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-            let rm = put_input_in_reg(ctx, inputs[1], NarrowValueMode::None);
-
-            ctx.emit(Inst::VecRRR {
-                alu_op: VecALUOp::Sqrdmulh,
-                rd,
-                rn,
-                rm,
-                size: VectorSize::from_ty(ty),
-            });
-        }
-
-        Opcode::FcvtLowFromSint => {
-            let ty = ty.unwrap();
-
-            if ty != F64X2 {
-                return Err(CodegenError::Unsupported(format!(
-                    "FcvtLowFromSint: Unsupported type: {:?}",
-                    ty
-                )));
-            }
-
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-
-            ctx.emit(Inst::VecExtend {
-                t: VecExtendOp::Sxtl32,
-                rd,
-                rn,
-                high_half: false,
-            });
-            ctx.emit(Inst::VecMisc {
-                op: VecMisc2::Scvtf,
-                rd,
-                rn: rd.to_reg(),
-                size: VectorSize::Size64x2,
-            });
-        }
-
-        Opcode::FvpromoteLow => {
-            debug_assert_eq!(ty.unwrap(), F64X2);
-
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-
-            ctx.emit(Inst::VecRRLong {
-                op: VecRRLongOp::Fcvtl32,
-                rd,
-                rn,
-                high_half: false,
-            });
-        }
-
-        Opcode::Fvdemote => {
-            debug_assert_eq!(ty.unwrap(), F32X4);
-
-            let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
-
-            ctx.emit(Inst::VecRRNarrow {
-                op: VecRRNarrowOp::Fcvtn64,
-                rd,
-                rn,
-                high_half: false,
-            });
-        }
-
-        Opcode::ConstAddr | Opcode::Vconcat | Opcode::Vsplit | Opcode::IfcmpSp => {
-            return Err(CodegenError::Unsupported(format!(
-                "Unimplemented lowering: {}",
-                op
-            )));
-        }
-    }
-
-    Ok(())
-}
-
-pub(crate) fn lower_branch<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    branches: &[IRInst],
-    targets: &[MachLabel],
-) -> CodegenResult<()> {
-    // A block should end with at most two branches. The first may be a
-    // conditional branch; a conditional branch can be followed only by an
-    // unconditional branch or fallthrough. Otherwise, if only one branch,
-    // it may be an unconditional branch, a fallthrough, a return, or a
-    // trap. These conditions are verified by `is_ebb_basic()` during the
-    // verifier pass.
-    assert!(branches.len() <= 2);
-
-    if branches.len() == 2 {
-        // Must be a conditional branch followed by an unconditional branch.
-        let op0 = ctx.data(branches[0]).opcode();
-        let op1 = ctx.data(branches[1]).opcode();
-
-        assert!(op1 == Opcode::Jump);
-        let taken = BranchTarget::Label(targets[0]);
-        // not_taken target is the target of the second branch, even if it is a Fallthrough
-        // instruction: because we reorder blocks while we lower, the fallthrough in the new
-        // order is not (necessarily) the same as the fallthrough in CLIF. So we use the
-        // explicitly-provided target.
-        let not_taken = BranchTarget::Label(targets[1]);
-
-        match op0 {
-            Opcode::Brz | Opcode::Brnz => {
-                let ty = ctx.input_ty(branches[0], 0);
-                let flag_input = InsnInput {
-                    insn: branches[0],
-                    input: 0,
-                };
-                if let Some(icmp_insn) =
-                    maybe_input_insn_via_conv(ctx, flag_input, Opcode::Icmp, Opcode::Bint)
-                {
-                    let condcode = ctx.data(icmp_insn).cond_code().unwrap();
-                    let cond =
-                        lower_icmp(ctx, icmp_insn, condcode, IcmpOutput::CondCode)?.unwrap_cond();
-                    let negated = op0 == Opcode::Brz;
-                    let cond = if negated { cond.invert() } else { cond };
-
-                    ctx.emit(Inst::CondBr {
-                        taken,
-                        not_taken,
-                        kind: CondBrKind::Cond(cond),
-                    });
-                } else if let Some(fcmp_insn) =
-                    maybe_input_insn_via_conv(ctx, flag_input, Opcode::Fcmp, Opcode::Bint)
-                {
-                    let condcode = ctx.data(fcmp_insn).fp_cond_code().unwrap();
-                    let cond = lower_fp_condcode(condcode);
-                    let negated = op0 == Opcode::Brz;
-                    let cond = if negated { cond.invert() } else { cond };
-
-                    lower_fcmp_or_ffcmp_to_flags(ctx, fcmp_insn);
-                    ctx.emit(Inst::CondBr {
-                        taken,
-                        not_taken,
-                        kind: CondBrKind::Cond(cond),
-                    });
-                } else {
-                    let rt = if ty == I128 {
-                        let tmp = ctx.alloc_tmp(I64).only_reg().unwrap();
-                        let input = put_input_in_regs(ctx, flag_input);
-                        ctx.emit(Inst::AluRRR {
-                            alu_op: ALUOp::Orr,
-                            size: OperandSize::Size64,
-                            rd: tmp,
-                            rn: input.regs()[0],
-                            rm: input.regs()[1],
-                        });
-                        tmp.to_reg()
-                    } else {
-                        put_input_in_reg(ctx, flag_input, NarrowValueMode::ZeroExtend64)
-                    };
-                    let kind = match op0 {
-                        Opcode::Brz => CondBrKind::Zero(rt),
-                        Opcode::Brnz => CondBrKind::NotZero(rt),
-                        _ => unreachable!(),
-                    };
-                    ctx.emit(Inst::CondBr {
-                        taken,
-                        not_taken,
-                        kind,
-                    });
-                }
-            }
-            Opcode::BrIcmp => {
-                let condcode = ctx.data(branches[0]).cond_code().unwrap();
-                let cond =
-                    lower_icmp(ctx, branches[0], condcode, IcmpOutput::CondCode)?.unwrap_cond();
-
-                ctx.emit(Inst::CondBr {
-                    taken,
-                    not_taken,
-                    kind: CondBrKind::Cond(cond),
-                });
-            }
-
-            Opcode::Brif => {
-                let condcode = ctx.data(branches[0]).cond_code().unwrap();
-
-                let flag_input = InsnInput {
-                    insn: branches[0],
-                    input: 0,
-                };
-                if let Some(ifcmp_insn) = maybe_input_insn(ctx, flag_input, Opcode::Ifcmp) {
-                    let cond =
-                        lower_icmp(ctx, ifcmp_insn, condcode, IcmpOutput::CondCode)?.unwrap_cond();
-                    ctx.emit(Inst::CondBr {
-                        taken,
-                        not_taken,
-                        kind: CondBrKind::Cond(cond),
-                    });
-                } else {
-                    // If the ifcmp result is actually placed in a
-                    // register, we need to move it back into the flags.
-                    let rn = put_input_in_reg(ctx, flag_input, NarrowValueMode::None);
-                    ctx.emit(Inst::MovToNZCV { rn });
-                    ctx.emit(Inst::CondBr {
-                        taken,
-                        not_taken,
-                        kind: CondBrKind::Cond(lower_condcode(condcode)),
-                    });
-                }
-            }
-
-            Opcode::Brff => {
-                let condcode = ctx.data(branches[0]).fp_cond_code().unwrap();
-                let cond = lower_fp_condcode(condcode);
-                let kind = CondBrKind::Cond(cond);
-                let flag_input = InsnInput {
-                    insn: branches[0],
-                    input: 0,
-                };
-                if let Some(ffcmp_insn) = maybe_input_insn(ctx, flag_input, Opcode::Ffcmp) {
-                    lower_fcmp_or_ffcmp_to_flags(ctx, ffcmp_insn);
-                    ctx.emit(Inst::CondBr {
-                        taken,
-                        not_taken,
-                        kind,
-                    });
-                } else {
-                    // If the ffcmp result is actually placed in a
-                    // register, we need to move it back into the flags.
-                    let rn = put_input_in_reg(ctx, flag_input, NarrowValueMode::None);
-                    ctx.emit(Inst::MovToNZCV { rn });
-                    ctx.emit(Inst::CondBr {
-                        taken,
-                        not_taken,
-                        kind,
-                    });
-                }
-            }
-
-            _ => unimplemented!(),
-        }
-    } else {
-        // Must be an unconditional branch or an indirect branch.
-        let op = ctx.data(branches[0]).opcode();
-        match op {
-            Opcode::Jump => {
-                assert!(branches.len() == 1);
-                ctx.emit(Inst::Jump {
-                    dest: BranchTarget::Label(targets[0]),
-                });
-            }
-
-            Opcode::BrTable => {
-                // Expand `br_table index, default, JT` to:
-                //
-                //   emit_island  // this forces an island at this point
-                //                // if the jumptable would push us past
-                //                // the deadline
-                //   subs idx, #jt_size
-                //   b.hs default
-                //   adr vTmp1, PC+16
-                //   ldr vTmp2, [vTmp1, idx, lsl #2]
-                //   add vTmp2, vTmp2, vTmp1
-                //   br vTmp2
-                //   [jumptable offsets relative to JT base]
-                let jt_size = targets.len() - 1;
-                assert!(jt_size <= std::u32::MAX as usize);
-
-                ctx.emit(Inst::EmitIsland {
-                    needed_space: 4 * (6 + jt_size) as CodeOffset,
-                });
-
-                let ridx = put_input_in_reg(
-                    ctx,
-                    InsnInput {
-                        insn: branches[0],
-                        input: 0,
-                    },
-                    NarrowValueMode::ZeroExtend32,
-                );
-
-                let rtmp1 = ctx.alloc_tmp(I32).only_reg().unwrap();
-                let rtmp2 = ctx.alloc_tmp(I32).only_reg().unwrap();
-
-                // Bounds-check, leaving condition codes for JTSequence's
-                // branch to default target below.
-                if let Some(imm12) = Imm12::maybe_from_u64(jt_size as u64) {
-                    ctx.emit(Inst::AluRRImm12 {
-                        alu_op: ALUOp::SubS,
-                        size: OperandSize::Size32,
-                        rd: writable_zero_reg(),
-                        rn: ridx,
-                        imm12,
-                    });
-                } else {
-                    lower_constant_u64(ctx, rtmp1, jt_size as u64);
-                    ctx.emit(Inst::AluRRR {
-                        alu_op: ALUOp::SubS,
-                        size: OperandSize::Size32,
-                        rd: writable_zero_reg(),
-                        rn: ridx,
-                        rm: rtmp1.to_reg(),
-                    });
-                }
-
-                // Emit the compound instruction that does:
-                //
-                // b.hs default
-                // adr rA, jt
-                // ldrsw rB, [rA, rIndex, UXTW 2]
-                // add rA, rA, rB
-                // br rA
-                // [jt entries]
-                //
-                // This must be *one* instruction in the vcode because
-                // we cannot allow regalloc to insert any spills/fills
-                // in the middle of the sequence; otherwise, the ADR's
-                // PC-rel offset to the jumptable would be incorrect.
-                // (The alternative is to introduce a relocation pass
-                // for inlined jumptables, which is much worse, IMHO.)
-
-                let jt_targets: Vec<BranchTarget> = targets
-                    .iter()
-                    .skip(1)
-                    .map(|bix| BranchTarget::Label(*bix))
-                    .collect();
-                let default_target = BranchTarget::Label(targets[0]);
-                let targets_for_term: Vec<MachLabel> = targets.to_vec();
-                ctx.emit(Inst::JTSequence {
-                    ridx,
-                    rtmp1,
-                    rtmp2,
-                    info: Box::new(JTSequenceInfo {
-                        targets: jt_targets,
-                        default_target,
-                        targets_for_term,
-                    }),
-                });
-            }
-
-            _ => panic!("Unknown branch type!"),
-        }
-    }
-
-    Ok(())
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/mod.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/mod.rs
deleted file mode 100644
index 2a1a4a42f..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/mod.rs
+++ /dev/null
@@ -1,297 +0,0 @@
-//! ARM 64-bit Instruction Set Architecture.
-
-use crate::ir::condcodes::IntCC;
-use crate::ir::Function;
-use crate::isa::aarch64::settings as aarch64_settings;
-use crate::isa::{Builder as IsaBuilder, TargetIsa};
-use crate::machinst::{
-    compile, MachCompileResult, MachTextSectionBuilder, TextSectionBuilder, VCode,
-};
-use crate::result::CodegenResult;
-use crate::settings as shared_settings;
-use alloc::{boxed::Box, vec::Vec};
-use core::fmt;
-use regalloc::{PrettyPrint, RealRegUniverse};
-use target_lexicon::{Aarch64Architecture, Architecture, Triple};
-
-// New backend:
-mod abi;
-pub(crate) mod inst;
-mod lower;
-mod lower_inst;
-mod settings;
-
-use inst::create_reg_universe;
-
-use self::inst::EmitInfo;
-
-/// An AArch64 backend.
-pub struct AArch64Backend {
-    triple: Triple,
-    flags: shared_settings::Flags,
-    isa_flags: aarch64_settings::Flags,
-    reg_universe: RealRegUniverse,
-}
-
-impl AArch64Backend {
-    /// Create a new AArch64 backend with the given (shared) flags.
-    pub fn new_with_flags(
-        triple: Triple,
-        flags: shared_settings::Flags,
-        isa_flags: aarch64_settings::Flags,
-    ) -> AArch64Backend {
-        let reg_universe = create_reg_universe(&flags);
-        AArch64Backend {
-            triple,
-            flags,
-            isa_flags,
-            reg_universe,
-        }
-    }
-
-    /// This performs lowering to VCode, register-allocates the code, computes block layout and
-    /// finalizes branches. The result is ready for binary emission.
-    fn compile_vcode(
-        &self,
-        func: &Function,
-        flags: shared_settings::Flags,
-    ) -> CodegenResult<VCode<inst::Inst>> {
-        let emit_info = EmitInfo::new(flags.clone());
-        let abi = Box::new(abi::AArch64ABICallee::new(func, flags, self.isa_flags())?);
-        compile::compile::<AArch64Backend>(func, self, abi, &self.reg_universe, emit_info)
-    }
-}
-
-impl TargetIsa for AArch64Backend {
-    fn compile_function(
-        &self,
-        func: &Function,
-        want_disasm: bool,
-    ) -> CodegenResult<MachCompileResult> {
-        let flags = self.flags();
-        let vcode = self.compile_vcode(func, flags.clone())?;
-
-        let (buffer, bb_starts, bb_edges) = vcode.emit();
-        let frame_size = vcode.frame_size();
-        let stackslot_offsets = vcode.stackslot_offsets().clone();
-
-        let disasm = if want_disasm {
-            Some(vcode.show_rru(Some(&create_reg_universe(flags))))
-        } else {
-            None
-        };
-
-        let buffer = buffer.finish();
-
-        Ok(MachCompileResult {
-            buffer,
-            frame_size,
-            disasm,
-            value_labels_ranges: Default::default(),
-            stackslot_offsets,
-            bb_starts,
-            bb_edges,
-        })
-    }
-
-    fn name(&self) -> &'static str {
-        "aarch64"
-    }
-
-    fn triple(&self) -> &Triple {
-        &self.triple
-    }
-
-    fn flags(&self) -> &shared_settings::Flags {
-        &self.flags
-    }
-
-    fn isa_flags(&self) -> Vec<shared_settings::Value> {
-        self.isa_flags.iter().collect()
-    }
-
-    fn unsigned_add_overflow_condition(&self) -> IntCC {
-        // Unsigned `>=`; this corresponds to the carry flag set on aarch64, which happens on
-        // overflow of an add.
-        IntCC::UnsignedGreaterThanOrEqual
-    }
-
-    #[cfg(feature = "unwind")]
-    fn emit_unwind_info(
-        &self,
-        result: &MachCompileResult,
-        kind: crate::machinst::UnwindInfoKind,
-    ) -> CodegenResult<Option<crate::isa::unwind::UnwindInfo>> {
-        use crate::isa::unwind::UnwindInfo;
-        use crate::machinst::UnwindInfoKind;
-        Ok(match kind {
-            UnwindInfoKind::SystemV => {
-                let mapper = self::inst::unwind::systemv::RegisterMapper;
-                Some(UnwindInfo::SystemV(
-                    crate::isa::unwind::systemv::create_unwind_info_from_insts(
-                        &result.buffer.unwind_info[..],
-                        result.buffer.data().len(),
-                        &mapper,
-                    )?,
-                ))
-            }
-            UnwindInfoKind::Windows => {
-                // TODO: support Windows unwind info on AArch64
-                None
-            }
-            _ => None,
-        })
-    }
-
-    #[cfg(feature = "unwind")]
-    fn create_systemv_cie(&self) -> Option<gimli::write::CommonInformationEntry> {
-        Some(inst::unwind::systemv::create_cie())
-    }
-
-    fn text_section_builder(&self, num_funcs: u32) -> Box<dyn TextSectionBuilder> {
-        Box::new(MachTextSectionBuilder::<inst::Inst>::new(num_funcs))
-    }
-}
-
-impl fmt::Display for AArch64Backend {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        f.debug_struct("MachBackend")
-            .field("name", &self.name())
-            .field("triple", &self.triple())
-            .field("flags", &format!("{}", self.flags()))
-            .finish()
-    }
-}
-
-/// Create a new `isa::Builder`.
-pub fn isa_builder(triple: Triple) -> IsaBuilder {
-    assert!(triple.architecture == Architecture::Aarch64(Aarch64Architecture::Aarch64));
-    IsaBuilder {
-        triple,
-        setup: aarch64_settings::builder(),
-        constructor: |triple, shared_flags, builder| {
-            let isa_flags = aarch64_settings::Flags::new(&shared_flags, builder);
-            let backend = AArch64Backend::new_with_flags(triple, shared_flags, isa_flags);
-            Ok(Box::new(backend))
-        },
-    }
-}
-
-#[cfg(test)]
-mod test {
-    use super::*;
-    use crate::cursor::{Cursor, FuncCursor};
-    use crate::ir::types::*;
-    use crate::ir::{AbiParam, ExternalName, Function, InstBuilder, Signature};
-    use crate::isa::CallConv;
-    use crate::settings;
-    use crate::settings::Configurable;
-    use core::str::FromStr;
-    use target_lexicon::Triple;
-
-    #[test]
-    fn test_compile_function() {
-        let name = ExternalName::testcase("test0");
-        let mut sig = Signature::new(CallConv::SystemV);
-        sig.params.push(AbiParam::new(I32));
-        sig.returns.push(AbiParam::new(I32));
-        let mut func = Function::with_name_signature(name, sig);
-
-        let bb0 = func.dfg.make_block();
-        let arg0 = func.dfg.append_block_param(bb0, I32);
-
-        let mut pos = FuncCursor::new(&mut func);
-        pos.insert_block(bb0);
-        let v0 = pos.ins().iconst(I32, 0x1234);
-        let v1 = pos.ins().iadd(arg0, v0);
-        pos.ins().return_(&[v1]);
-
-        let mut shared_flags_builder = settings::builder();
-        shared_flags_builder.set("opt_level", "none").unwrap();
-        let shared_flags = settings::Flags::new(shared_flags_builder);
-        let isa_flags = aarch64_settings::Flags::new(&shared_flags, aarch64_settings::builder());
-        let backend = AArch64Backend::new_with_flags(
-            Triple::from_str("aarch64").unwrap(),
-            shared_flags,
-            isa_flags,
-        );
-        let buffer = backend.compile_function(&mut func, false).unwrap().buffer;
-        let code = buffer.data();
-
-        // mov x1, #0x1234
-        // add w0, w0, w1
-        // ret
-        let golden = vec![
-            0x81, 0x46, 0x82, 0xd2, 0x00, 0x00, 0x01, 0x0b, 0xc0, 0x03, 0x5f, 0xd6,
-        ];
-
-        assert_eq!(code, &golden[..]);
-    }
-
-    #[test]
-    fn test_branch_lowering() {
-        let name = ExternalName::testcase("test0");
-        let mut sig = Signature::new(CallConv::SystemV);
-        sig.params.push(AbiParam::new(I32));
-        sig.returns.push(AbiParam::new(I32));
-        let mut func = Function::with_name_signature(name, sig);
-
-        let bb0 = func.dfg.make_block();
-        let arg0 = func.dfg.append_block_param(bb0, I32);
-        let bb1 = func.dfg.make_block();
-        let bb2 = func.dfg.make_block();
-        let bb3 = func.dfg.make_block();
-
-        let mut pos = FuncCursor::new(&mut func);
-        pos.insert_block(bb0);
-        let v0 = pos.ins().iconst(I32, 0x1234);
-        let v1 = pos.ins().iadd(arg0, v0);
-        pos.ins().brnz(v1, bb1, &[]);
-        pos.ins().jump(bb2, &[]);
-        pos.insert_block(bb1);
-        pos.ins().brnz(v1, bb2, &[]);
-        pos.ins().jump(bb3, &[]);
-        pos.insert_block(bb2);
-        let v2 = pos.ins().iadd(v1, v0);
-        pos.ins().brnz(v2, bb2, &[]);
-        pos.ins().jump(bb1, &[]);
-        pos.insert_block(bb3);
-        let v3 = pos.ins().isub(v1, v0);
-        pos.ins().return_(&[v3]);
-
-        let mut shared_flags_builder = settings::builder();
-        shared_flags_builder.set("opt_level", "none").unwrap();
-        let shared_flags = settings::Flags::new(shared_flags_builder);
-        let isa_flags = aarch64_settings::Flags::new(&shared_flags, aarch64_settings::builder());
-        let backend = AArch64Backend::new_with_flags(
-            Triple::from_str("aarch64").unwrap(),
-            shared_flags,
-            isa_flags,
-        );
-        let result = backend
-            .compile_function(&mut func, /* want_disasm = */ false)
-            .unwrap();
-        let code = result.buffer.data();
-
-        // mov	x1, #0x1234                	// #4660
-        // add	w0, w0, w1
-        // mov	w1, w0
-        // cbnz	x1, 0x28
-        // mov	x1, #0x1234                	// #4660
-        // add	w1, w0, w1
-        // mov	w1, w1
-        // cbnz	x1, 0x18
-        // mov	w1, w0
-        // cbnz	x1, 0x18
-        // mov	x1, #0x1234                	// #4660
-        // sub	w0, w0, w1
-        // ret
-        let golden = vec![
-            129, 70, 130, 210, 0, 0, 1, 11, 225, 3, 0, 42, 161, 0, 0, 181, 129, 70, 130, 210, 1, 0,
-            1, 11, 225, 3, 1, 42, 161, 255, 255, 181, 225, 3, 0, 42, 97, 255, 255, 181, 129, 70,
-            130, 210, 0, 0, 1, 75, 192, 3, 95, 214,
-        ];
-
-        assert_eq!(code, &golden[..]);
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/settings.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/settings.rs
deleted file mode 100644
index 9d3898e7b..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/aarch64/settings.rs
+++ /dev/null
@@ -1,9 +0,0 @@
-//! AArch64 Settings.
-
-use crate::settings::{self, detail, Builder, Value};
-use core::fmt;
-
-// Include code generated by `cranelift-codegen/meta/src/gen_settings.rs:`. This file contains a
-// public `Flags` struct with an impl for all of the settings defined in
-// `cranelift-codegen/meta/src/isa/arm64/settings.rs`.
-include!(concat!(env!("OUT_DIR"), "/settings-arm64.rs"));
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/call_conv.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/call_conv.rs
deleted file mode 100644
index d9ee48f89..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/call_conv.rs
+++ /dev/null
@@ -1,148 +0,0 @@
-use crate::settings::{self, LibcallCallConv};
-use core::fmt;
-use core::str;
-use target_lexicon::{CallingConvention, Triple};
-
-#[cfg(feature = "enable-serde")]
-use serde::{Deserialize, Serialize};
-
-/// Calling convention identifiers.
-#[derive(Debug, Copy, Clone, PartialEq, Eq, Hash)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub enum CallConv {
-    /// Best performance, not ABI-stable.
-    Fast,
-    /// Smallest caller code size, not ABI-stable.
-    Cold,
-    /// System V-style convention used on many platforms.
-    SystemV,
-    /// Windows "fastcall" convention, also used for x64 and ARM.
-    WindowsFastcall,
-    /// Mac aarch64 calling convention, which is a tweaked aarch64 ABI.
-    AppleAarch64,
-    /// SpiderMonkey WebAssembly convention on systems using natively SystemV.
-    BaldrdashSystemV,
-    /// SpiderMonkey WebAssembly convention on Windows.
-    BaldrdashWindows,
-    /// SpiderMonkey WebAssembly convention for "ABI-2020", with extra TLS
-    /// register slots in the frame.
-    Baldrdash2020,
-    /// Specialized convention for the probestack function.
-    Probestack,
-    /// Wasmtime equivalent of SystemV, not ABI-stable.
-    ///
-    /// Currently only differs in how multiple return values are handled,
-    /// returning the first return value in a register and everything else
-    /// through a return-pointer.
-    WasmtimeSystemV,
-    /// Wasmtime equivalent of WindowsFastcall, not ABI-stable.
-    ///
-    /// Differs from fastcall in the same way as `WasmtimeSystemV`.
-    WasmtimeFastcall,
-    /// Wasmtime equivalent of AppleAarch64, not ABI-stable.
-    ///
-    /// Differs from apple-aarch64 in the same way as `WasmtimeSystemV`.
-    WasmtimeAppleAarch64,
-}
-
-impl CallConv {
-    /// Return the default calling convention for the given target triple.
-    pub fn triple_default(triple: &Triple) -> Self {
-        match triple.default_calling_convention() {
-            // Default to System V for unknown targets because most everything
-            // uses System V.
-            Ok(CallingConvention::SystemV) | Err(()) => Self::SystemV,
-            Ok(CallingConvention::AppleAarch64) => Self::AppleAarch64,
-            Ok(CallingConvention::WindowsFastcall) => Self::WindowsFastcall,
-            Ok(unimp) => unimplemented!("calling convention: {:?}", unimp),
-        }
-    }
-
-    /// Returns the calling convention used for libcalls according to the current flags.
-    pub fn for_libcall(flags: &settings::Flags, default_call_conv: CallConv) -> Self {
-        match flags.libcall_call_conv() {
-            LibcallCallConv::IsaDefault => default_call_conv,
-            LibcallCallConv::Fast => Self::Fast,
-            LibcallCallConv::Cold => Self::Cold,
-            LibcallCallConv::SystemV => Self::SystemV,
-            LibcallCallConv::WindowsFastcall => Self::WindowsFastcall,
-            LibcallCallConv::AppleAarch64 => Self::AppleAarch64,
-            LibcallCallConv::BaldrdashSystemV => Self::BaldrdashSystemV,
-            LibcallCallConv::BaldrdashWindows => Self::BaldrdashWindows,
-            LibcallCallConv::Baldrdash2020 => Self::Baldrdash2020,
-            LibcallCallConv::Probestack => Self::Probestack,
-        }
-    }
-
-    /// Is the calling convention extending the Windows Fastcall ABI?
-    pub fn extends_windows_fastcall(self) -> bool {
-        match self {
-            Self::WindowsFastcall | Self::BaldrdashWindows | Self::WasmtimeFastcall => true,
-            _ => false,
-        }
-    }
-
-    /// Is the calling convention extending the Apple aarch64 ABI?
-    pub fn extends_apple_aarch64(self) -> bool {
-        match self {
-            Self::AppleAarch64 | Self::WasmtimeAppleAarch64 => true,
-            _ => false,
-        }
-    }
-
-    /// Is the calling convention extending the Baldrdash ABI?
-    pub fn extends_baldrdash(self) -> bool {
-        match self {
-            Self::BaldrdashSystemV | Self::BaldrdashWindows | Self::Baldrdash2020 => true,
-            _ => false,
-        }
-    }
-
-    /// Is the calling convention extending the Wasmtime ABI?
-    pub fn extends_wasmtime(self) -> bool {
-        match self {
-            Self::WasmtimeSystemV | Self::WasmtimeFastcall | Self::WasmtimeAppleAarch64 => true,
-            _ => false,
-        }
-    }
-}
-
-impl fmt::Display for CallConv {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        f.write_str(match *self {
-            Self::Fast => "fast",
-            Self::Cold => "cold",
-            Self::SystemV => "system_v",
-            Self::WindowsFastcall => "windows_fastcall",
-            Self::AppleAarch64 => "apple_aarch64",
-            Self::BaldrdashSystemV => "baldrdash_system_v",
-            Self::BaldrdashWindows => "baldrdash_windows",
-            Self::Baldrdash2020 => "baldrdash_2020",
-            Self::Probestack => "probestack",
-            Self::WasmtimeSystemV => "wasmtime_system_v",
-            Self::WasmtimeFastcall => "wasmtime_fastcall",
-            Self::WasmtimeAppleAarch64 => "wasmtime_apple_aarch64",
-        })
-    }
-}
-
-impl str::FromStr for CallConv {
-    type Err = ();
-    fn from_str(s: &str) -> Result<Self, Self::Err> {
-        match s {
-            "fast" => Ok(Self::Fast),
-            "cold" => Ok(Self::Cold),
-            "system_v" => Ok(Self::SystemV),
-            "windows_fastcall" => Ok(Self::WindowsFastcall),
-            "apple_aarch64" => Ok(Self::AppleAarch64),
-            "baldrdash_system_v" => Ok(Self::BaldrdashSystemV),
-            "baldrdash_windows" => Ok(Self::BaldrdashWindows),
-            "baldrdash_2020" => Ok(Self::Baldrdash2020),
-            "probestack" => Ok(Self::Probestack),
-            "wasmtime_system_v" => Ok(Self::WasmtimeSystemV),
-            "wasmtime_fastcall" => Ok(Self::WasmtimeFastcall),
-            "wasmtime_apple_aarch64" => Ok(Self::WasmtimeAppleAarch64),
-            _ => Err(()),
-        }
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/mod.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/mod.rs
deleted file mode 100644
index 821b9627e..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/mod.rs
+++ /dev/null
@@ -1,359 +0,0 @@
-//! Instruction Set Architectures.
-//!
-//! The `isa` module provides a `TargetIsa` trait which provides the behavior specialization needed
-//! by the ISA-independent code generator. The sub-modules of this module provide definitions for
-//! the instruction sets that Cranelift can target. Each sub-module has it's own implementation of
-//! `TargetIsa`.
-//!
-//! # Constructing a `TargetIsa` instance
-//!
-//! The target ISA is built from the following information:
-//!
-//! - The name of the target ISA as a string. Cranelift is a cross-compiler, so the ISA to target
-//!   can be selected dynamically. Individual ISAs can be left out when Cranelift is compiled, so a
-//!   string is used to identify the proper sub-module.
-//! - Values for settings that apply to all ISAs. This is represented by a `settings::Flags`
-//!   instance.
-//! - Values for ISA-specific settings.
-//!
-//! The `isa::lookup()` function is the main entry point which returns an `isa::Builder`
-//! appropriate for the requested ISA:
-//!
-//! ```
-//! # #[macro_use] extern crate target_lexicon;
-//! use cranelift_codegen::isa;
-//! use cranelift_codegen::settings::{self, Configurable};
-//! use std::str::FromStr;
-//! use target_lexicon::Triple;
-//!
-//! let shared_builder = settings::builder();
-//! let shared_flags = settings::Flags::new(shared_builder);
-//!
-//! match isa::lookup(triple!("x86_64")) {
-//!     Err(_) => {
-//!         // The x86_64 target ISA is not available.
-//!     }
-//!     Ok(mut isa_builder) => {
-//!         isa_builder.set("use_popcnt", "on");
-//!         let isa = isa_builder.finish(shared_flags);
-//!     }
-//! }
-//! ```
-//!
-//! The configured target ISA trait object is a `Box<TargetIsa>` which can be used for multiple
-//! concurrent function compilations.
-
-pub use crate::isa::call_conv::CallConv;
-
-use crate::flowgraph;
-use crate::ir::{self, Function};
-#[cfg(feature = "unwind")]
-use crate::isa::unwind::systemv::RegisterMappingError;
-use crate::machinst::{MachCompileResult, TextSectionBuilder, UnwindInfoKind};
-use crate::settings;
-use crate::settings::SetResult;
-use crate::CodegenResult;
-use alloc::{boxed::Box, vec::Vec};
-use core::fmt;
-use core::fmt::{Debug, Formatter};
-use target_lexicon::{triple, Architecture, OperatingSystem, PointerWidth, Triple};
-
-// This module is made public here for benchmarking purposes. No guarantees are
-// made regarding API stability.
-#[cfg(feature = "x86")]
-pub mod x64;
-
-#[cfg(feature = "arm64")]
-pub(crate) mod aarch64;
-
-#[cfg(feature = "s390x")]
-mod s390x;
-
-pub mod unwind;
-
-mod call_conv;
-
-/// Returns a builder that can create a corresponding `TargetIsa`
-/// or `Err(LookupError::SupportDisabled)` if not enabled.
-macro_rules! isa_builder {
-    ($name: ident, $cfg_terms: tt, $triple: ident) => {{
-        #[cfg $cfg_terms]
-        {
-            Ok($name::isa_builder($triple))
-        }
-        #[cfg(not $cfg_terms)]
-        {
-            Err(LookupError::SupportDisabled)
-        }
-    }};
-}
-
-/// Look for an ISA for the given `triple`.
-/// Return a builder that can create a corresponding `TargetIsa`.
-pub fn lookup(triple: Triple) -> Result<Builder, LookupError> {
-    match triple.architecture {
-        Architecture::X86_64 => {
-            isa_builder!(x64, (feature = "x86"), triple)
-        }
-        Architecture::Aarch64 { .. } => isa_builder!(aarch64, (feature = "arm64"), triple),
-        Architecture::S390x { .. } => isa_builder!(s390x, (feature = "s390x"), triple),
-        _ => Err(LookupError::Unsupported),
-    }
-}
-
-/// Look for a supported ISA with the given `name`.
-/// Return a builder that can create a corresponding `TargetIsa`.
-pub fn lookup_by_name(name: &str) -> Result<Builder, LookupError> {
-    use alloc::str::FromStr;
-    lookup(triple!(name))
-}
-
-/// Describes reason for target lookup failure
-#[derive(PartialEq, Eq, Copy, Clone, Debug)]
-pub enum LookupError {
-    /// Support for this target was disabled in the current build.
-    SupportDisabled,
-
-    /// Support for this target has not yet been implemented.
-    Unsupported,
-}
-
-// This is manually implementing Error and Display instead of using thiserror to reduce the amount
-// of dependencies used by Cranelift.
-impl std::error::Error for LookupError {}
-
-impl fmt::Display for LookupError {
-    fn fmt(&self, f: &mut Formatter) -> fmt::Result {
-        match self {
-            LookupError::SupportDisabled => write!(f, "Support for this target is disabled"),
-            LookupError::Unsupported => {
-                write!(f, "Support for this target has not been implemented yet")
-            }
-        }
-    }
-}
-
-/// Builder for a `TargetIsa`.
-/// Modify the ISA-specific settings before creating the `TargetIsa` trait object with `finish`.
-#[derive(Clone)]
-pub struct Builder {
-    triple: Triple,
-    setup: settings::Builder,
-    constructor:
-        fn(Triple, settings::Flags, settings::Builder) -> CodegenResult<Box<dyn TargetIsa>>,
-}
-
-impl Builder {
-    /// Gets the triple for the builder.
-    pub fn triple(&self) -> &Triple {
-        &self.triple
-    }
-
-    /// Iterates the available settings in the builder.
-    pub fn iter(&self) -> impl Iterator<Item = settings::Setting> {
-        self.setup.iter()
-    }
-
-    /// Combine the ISA-specific settings with the provided
-    /// ISA-independent settings and allocate a fully configured
-    /// `TargetIsa` trait object. May return an error if some of the
-    /// flags are inconsistent or incompatible: for example, some
-    /// platform-independent features, like general SIMD support, may
-    /// need certain ISA extensions to be enabled.
-    pub fn finish(self, shared_flags: settings::Flags) -> CodegenResult<Box<dyn TargetIsa>> {
-        (self.constructor)(self.triple, shared_flags, self.setup)
-    }
-}
-
-impl settings::Configurable for Builder {
-    fn set(&mut self, name: &str, value: &str) -> SetResult<()> {
-        self.setup.set(name, value)
-    }
-
-    fn enable(&mut self, name: &str) -> SetResult<()> {
-        self.setup.enable(name)
-    }
-}
-
-/// After determining that an instruction doesn't have an encoding, how should we proceed to
-/// legalize it?
-///
-/// The `Encodings` iterator returns a legalization function to call.
-pub type Legalize =
-    fn(ir::Inst, &mut ir::Function, &mut flowgraph::ControlFlowGraph, &dyn TargetIsa) -> bool;
-
-/// This struct provides information that a frontend may need to know about a target to
-/// produce Cranelift IR for the target.
-#[derive(Clone, Copy, Hash)]
-pub struct TargetFrontendConfig {
-    /// The default calling convention of the target.
-    pub default_call_conv: CallConv,
-
-    /// The pointer width of the target.
-    pub pointer_width: PointerWidth,
-}
-
-impl TargetFrontendConfig {
-    /// Get the pointer type of this target.
-    pub fn pointer_type(self) -> ir::Type {
-        ir::Type::int(u16::from(self.pointer_bits())).unwrap()
-    }
-
-    /// Get the width of pointers on this target, in units of bits.
-    pub fn pointer_bits(self) -> u8 {
-        self.pointer_width.bits()
-    }
-
-    /// Get the width of pointers on this target, in units of bytes.
-    pub fn pointer_bytes(self) -> u8 {
-        self.pointer_width.bytes()
-    }
-}
-
-/// Methods that are specialized to a target ISA.
-///
-/// Implies a Display trait that shows the shared flags, as well as any ISA-specific flags.
-pub trait TargetIsa: fmt::Display + Send + Sync {
-    /// Get the name of this ISA.
-    fn name(&self) -> &'static str;
-
-    /// Get the target triple that was used to make this trait object.
-    fn triple(&self) -> &Triple;
-
-    /// Get the ISA-independent flags that were used to make this trait object.
-    fn flags(&self) -> &settings::Flags;
-
-    /// Get the ISA-dependent flag values that were used to make this trait object.
-    fn isa_flags(&self) -> Vec<settings::Value>;
-
-    /// Compile the given function.
-    fn compile_function(
-        &self,
-        func: &Function,
-        want_disasm: bool,
-    ) -> CodegenResult<MachCompileResult>;
-
-    #[cfg(feature = "unwind")]
-    /// Map a regalloc::Reg to its corresponding DWARF register.
-    fn map_regalloc_reg_to_dwarf(&self, _: ::regalloc::Reg) -> Result<u16, RegisterMappingError> {
-        Err(RegisterMappingError::UnsupportedArchitecture)
-    }
-
-    /// IntCC condition for Unsigned Addition Overflow (Carry).
-    fn unsigned_add_overflow_condition(&self) -> ir::condcodes::IntCC;
-
-    /// Creates unwind information for the function.
-    ///
-    /// Returns `None` if there is no unwind information for the function.
-    #[cfg(feature = "unwind")]
-    fn emit_unwind_info(
-        &self,
-        result: &MachCompileResult,
-        kind: UnwindInfoKind,
-    ) -> CodegenResult<Option<crate::isa::unwind::UnwindInfo>>;
-
-    /// Creates a new System V Common Information Entry for the ISA.
-    ///
-    /// Returns `None` if the ISA does not support System V unwind information.
-    #[cfg(feature = "unwind")]
-    fn create_systemv_cie(&self) -> Option<gimli::write::CommonInformationEntry> {
-        // By default, an ISA cannot create a System V CIE
-        None
-    }
-
-    /// Returns an object that can be used to build the text section of an
-    /// executable.
-    ///
-    /// This object will internally attempt to handle as many relocations as
-    /// possible using relative calls/jumps/etc between functions.
-    ///
-    /// The `num_labeled_funcs` argument here is the number of functions which
-    /// will be "labeled" or might have calls between them, typically the number
-    /// of defined functions in the object file.
-    fn text_section_builder(&self, num_labeled_funcs: u32) -> Box<dyn TextSectionBuilder>;
-}
-
-/// Methods implemented for free for target ISA!
-impl<'a> dyn TargetIsa + 'a {
-    /// Get the default calling convention of this target.
-    pub fn default_call_conv(&self) -> CallConv {
-        CallConv::triple_default(self.triple())
-    }
-
-    /// Get the endianness of this ISA.
-    pub fn endianness(&self) -> ir::Endianness {
-        match self.triple().endianness().unwrap() {
-            target_lexicon::Endianness::Little => ir::Endianness::Little,
-            target_lexicon::Endianness::Big => ir::Endianness::Big,
-        }
-    }
-
-    /// Returns the code (text) section alignment for this ISA.
-    pub fn code_section_alignment(&self) -> u64 {
-        use target_lexicon::*;
-        match (self.triple().operating_system, self.triple().architecture) {
-            (
-                OperatingSystem::MacOSX { .. }
-                | OperatingSystem::Darwin
-                | OperatingSystem::Ios
-                | OperatingSystem::Tvos,
-                Architecture::Aarch64(..),
-            ) => 0x4000,
-            // 64 KB is the maximal page size (i.e. memory translation granule size)
-            // supported by the architecture and is used on some platforms.
-            (_, Architecture::Aarch64(..)) => 0x10000,
-            _ => 0x1000,
-        }
-    }
-
-    /// Get the pointer type of this ISA.
-    pub fn pointer_type(&self) -> ir::Type {
-        ir::Type::int(u16::from(self.pointer_bits())).unwrap()
-    }
-
-    /// Get the width of pointers on this ISA.
-    pub(crate) fn pointer_width(&self) -> PointerWidth {
-        self.triple().pointer_width().unwrap()
-    }
-
-    /// Get the width of pointers on this ISA, in units of bits.
-    pub fn pointer_bits(&self) -> u8 {
-        self.pointer_width().bits()
-    }
-
-    /// Get the width of pointers on this ISA, in units of bytes.
-    pub fn pointer_bytes(&self) -> u8 {
-        self.pointer_width().bytes()
-    }
-
-    /// Get the information needed by frontends producing Cranelift IR.
-    pub fn frontend_config(&self) -> TargetFrontendConfig {
-        TargetFrontendConfig {
-            default_call_conv: self.default_call_conv(),
-            pointer_width: self.pointer_width(),
-        }
-    }
-
-    /// Returns the flavor of unwind information emitted for this target.
-    pub(crate) fn unwind_info_kind(&self) -> UnwindInfoKind {
-        match self.triple().operating_system {
-            #[cfg(feature = "unwind")]
-            OperatingSystem::Windows => UnwindInfoKind::Windows,
-            #[cfg(feature = "unwind")]
-            _ => UnwindInfoKind::SystemV,
-            #[cfg(not(feature = "unwind"))]
-            _ => UnwindInfoKind::None,
-        }
-    }
-}
-
-impl Debug for &dyn TargetIsa {
-    fn fmt(&self, f: &mut Formatter<'_>) -> fmt::Result {
-        write!(
-            f,
-            "TargetIsa {{ triple: {:?}, pointer_width: {:?}}}",
-            self.triple(),
-            self.pointer_width()
-        )
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/abi.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/abi.rs
deleted file mode 100644
index 1ab9a1f00..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/abi.rs
+++ /dev/null
@@ -1,803 +0,0 @@
-//! Implementation of a standard S390x ABI.
-//!
-//! This machine uses the "vanilla" ABI implementation from abi_impl.rs,
-//! however a few details are different from the description there:
-//!
-//! - On s390x, the caller must provide a "register save area" of 160
-//!   bytes to any function it calls.  The called function is free to use
-//!   this space for any purpose; usually to save callee-saved GPRs.
-//!   (Note that while this area is allocated by the caller, it is counted
-//!   as part of the callee's stack frame; in particular, the callee's CFA
-//!   is the top of the register save area, not the incoming SP value.)
-//!
-//! - Overflow arguments are passed on the stack starting immediately
-//!   above the register save area.  On s390x, this space is allocated
-//!   only once directly in the prologue, using a size large enough to
-//!   hold overflow arguments for every call in the function.
-//!
-//! - On s390x we do not use a frame pointer register; instead, every
-//!   element of the stack frame is addressed via (constant) offsets
-//!   from the stack pointer.  Note that due to the above (and because
-//!   there are no variable-sized stack allocations in cranelift), the
-//!   value of the stack pointer register never changes after the
-//!   initial allocation in the function prologue.
-//!
-//! Overall, the stack frame layout on s390x is as follows:
-//!
-//! ```plain
-//!   (high address)
-//!
-//!                              +---------------------------+
-//!                              |          ...              |
-//! CFA                  ----->  | stack args                |
-//!                              +---------------------------+
-//!                              |          ...              |
-//!                              | 160 bytes reg save area   |
-//! SP at function entry ----->  | (used to save GPRs)       |
-//!                              +---------------------------+
-//!                              |          ...              |
-//!                              | clobbered callee-saves    |
-//!                              | (used to save FPRs)       |
-//! unwind-frame base     ---->  | (alloc'd by prologue)     |
-//!                              +---------------------------+
-//!                              |          ...              |
-//!                              | spill slots               |
-//!                              | (accessed via nominal SP) |
-//!                              |          ...              |
-//!                              | stack slots               |
-//!                              | (accessed via nominal SP) |
-//! nominal SP --------------->  | (alloc'd by prologue)     |
-//!                              +---------------------------+
-//!                              |          ...              |
-//!                              | args for call             |
-//!                              | outgoing reg save area    |
-//! SP during function  ------>  | (alloc'd by prologue)     |
-//!                              +---------------------------+
-//!
-//!   (low address)
-//! ```
-
-use crate::ir;
-use crate::ir::condcodes::IntCC;
-use crate::ir::types;
-use crate::ir::MemFlags;
-use crate::ir::Type;
-use crate::isa;
-use crate::isa::s390x::inst::*;
-use crate::isa::unwind::UnwindInst;
-use crate::machinst::*;
-use crate::settings;
-use crate::{CodegenError, CodegenResult};
-use alloc::boxed::Box;
-use alloc::vec::Vec;
-use regalloc::{RealReg, Reg, RegClass, Set, Writable};
-use smallvec::{smallvec, SmallVec};
-use std::convert::TryFrom;
-
-// We use a generic implementation that factors out ABI commonalities.
-
-/// Support for the S390x ABI from the callee side (within a function body).
-pub type S390xABICallee = ABICalleeImpl<S390xMachineDeps>;
-
-/// Support for the S390x ABI from the caller side (at a callsite).
-pub type S390xABICaller = ABICallerImpl<S390xMachineDeps>;
-
-/// ABI Register usage
-
-fn in_int_reg(ty: Type) -> bool {
-    match ty {
-        types::I8 | types::I16 | types::I32 | types::I64 | types::R64 => true,
-        types::B1 | types::B8 | types::B16 | types::B32 | types::B64 => true,
-        _ => false,
-    }
-}
-
-fn in_flt_reg(ty: Type) -> bool {
-    match ty {
-        types::F32 | types::F64 => true,
-        _ => false,
-    }
-}
-
-fn get_intreg_for_arg(idx: usize) -> Option<Reg> {
-    match idx {
-        0 => Some(regs::gpr(2)),
-        1 => Some(regs::gpr(3)),
-        2 => Some(regs::gpr(4)),
-        3 => Some(regs::gpr(5)),
-        4 => Some(regs::gpr(6)),
-        _ => None,
-    }
-}
-
-fn get_fltreg_for_arg(idx: usize) -> Option<Reg> {
-    match idx {
-        0 => Some(regs::fpr(0)),
-        1 => Some(regs::fpr(2)),
-        2 => Some(regs::fpr(4)),
-        3 => Some(regs::fpr(6)),
-        _ => None,
-    }
-}
-
-fn get_intreg_for_ret(idx: usize) -> Option<Reg> {
-    match idx {
-        0 => Some(regs::gpr(2)),
-        // ABI extension to support multi-value returns:
-        1 => Some(regs::gpr(3)),
-        2 => Some(regs::gpr(4)),
-        3 => Some(regs::gpr(5)),
-        _ => None,
-    }
-}
-
-fn get_fltreg_for_ret(idx: usize) -> Option<Reg> {
-    match idx {
-        0 => Some(regs::fpr(0)),
-        // ABI extension to support multi-value returns:
-        1 => Some(regs::fpr(2)),
-        2 => Some(regs::fpr(4)),
-        3 => Some(regs::fpr(6)),
-        _ => None,
-    }
-}
-
-/// This is the limit for the size of argument and return-value areas on the
-/// stack. We place a reasonable limit here to avoid integer overflow issues
-/// with 32-bit arithmetic: for now, 128 MB.
-static STACK_ARG_RET_SIZE_LIMIT: u64 = 128 * 1024 * 1024;
-
-impl Into<MemArg> for StackAMode {
-    fn into(self) -> MemArg {
-        match self {
-            StackAMode::FPOffset(off, _ty) => MemArg::InitialSPOffset { off },
-            StackAMode::NominalSPOffset(off, _ty) => MemArg::NominalSPOffset { off },
-            StackAMode::SPOffset(off, _ty) => {
-                MemArg::reg_plus_off(stack_reg(), off, MemFlags::trusted())
-            }
-        }
-    }
-}
-
-/// S390x-specific ABI behavior. This struct just serves as an implementation
-/// point for the trait; it is never actually instantiated.
-pub struct S390xMachineDeps;
-
-impl ABIMachineSpec for S390xMachineDeps {
-    type I = Inst;
-
-    fn word_bits() -> u32 {
-        64
-    }
-
-    /// Return required stack alignment in bytes.
-    fn stack_align(_call_conv: isa::CallConv) -> u32 {
-        8
-    }
-
-    fn compute_arg_locs(
-        call_conv: isa::CallConv,
-        _flags: &settings::Flags,
-        params: &[ir::AbiParam],
-        args_or_rets: ArgsOrRets,
-        add_ret_area_ptr: bool,
-    ) -> CodegenResult<(Vec<ABIArg>, i64, Option<usize>)> {
-        let mut next_gpr = 0;
-        let mut next_fpr = 0;
-        let mut next_stack: u64 = 0;
-        let mut ret = vec![];
-
-        if args_or_rets == ArgsOrRets::Args {
-            next_stack = 160;
-        }
-
-        for i in 0..params.len() {
-            let param = &params[i];
-
-            // Validate "purpose".
-            match &param.purpose {
-                &ir::ArgumentPurpose::VMContext
-                | &ir::ArgumentPurpose::Normal
-                | &ir::ArgumentPurpose::StackLimit
-                | &ir::ArgumentPurpose::SignatureId => {}
-                _ => panic!(
-                    "Unsupported argument purpose {:?} in signature: {:?}",
-                    param.purpose, params
-                ),
-            }
-
-            let intreg = in_int_reg(param.value_type);
-            let fltreg = in_flt_reg(param.value_type);
-            debug_assert!(intreg || fltreg);
-            debug_assert!(!(intreg && fltreg));
-
-            let (next_reg, candidate) = if intreg {
-                let candidate = match args_or_rets {
-                    ArgsOrRets::Args => get_intreg_for_arg(next_gpr),
-                    ArgsOrRets::Rets => get_intreg_for_ret(next_gpr),
-                };
-                (&mut next_gpr, candidate)
-            } else {
-                let candidate = match args_or_rets {
-                    ArgsOrRets::Args => get_fltreg_for_arg(next_fpr),
-                    ArgsOrRets::Rets => get_fltreg_for_ret(next_fpr),
-                };
-                (&mut next_fpr, candidate)
-            };
-
-            // In the Wasmtime ABI only the first return value can be in a register.
-            let candidate =
-                if call_conv.extends_wasmtime() && args_or_rets == ArgsOrRets::Rets && i > 0 {
-                    None
-                } else {
-                    candidate
-                };
-
-            if let Some(reg) = candidate {
-                ret.push(ABIArg::reg(
-                    reg.to_real_reg(),
-                    param.value_type,
-                    param.extension,
-                    param.purpose,
-                ));
-                *next_reg += 1;
-            } else {
-                // Compute size. Every argument or return value takes a slot of
-                // at least 8 bytes, except for return values in the Wasmtime ABI.
-                let size = (ty_bits(param.value_type) / 8) as u64;
-                let slot_size = if call_conv.extends_wasmtime() && args_or_rets == ArgsOrRets::Rets
-                {
-                    size
-                } else {
-                    std::cmp::max(size, 8)
-                };
-
-                // Align the stack slot.
-                debug_assert!(slot_size.is_power_of_two());
-                next_stack = align_to(next_stack, slot_size);
-
-                // If the type is actually of smaller size (and the argument
-                // was not extended), it is passed right-aligned.
-                let offset = if size < slot_size && param.extension == ir::ArgumentExtension::None {
-                    slot_size - size
-                } else {
-                    0
-                };
-                ret.push(ABIArg::stack(
-                    (next_stack + offset) as i64,
-                    param.value_type,
-                    param.extension,
-                    param.purpose,
-                ));
-                next_stack += slot_size;
-            }
-        }
-
-        next_stack = align_to(next_stack, 8);
-
-        let extra_arg = if add_ret_area_ptr {
-            debug_assert!(args_or_rets == ArgsOrRets::Args);
-            if let Some(reg) = get_intreg_for_arg(next_gpr) {
-                ret.push(ABIArg::reg(
-                    reg.to_real_reg(),
-                    types::I64,
-                    ir::ArgumentExtension::None,
-                    ir::ArgumentPurpose::Normal,
-                ));
-            } else {
-                ret.push(ABIArg::stack(
-                    next_stack as i64,
-                    types::I64,
-                    ir::ArgumentExtension::None,
-                    ir::ArgumentPurpose::Normal,
-                ));
-                next_stack += 8;
-            }
-            Some(ret.len() - 1)
-        } else {
-            None
-        };
-
-        // To avoid overflow issues, limit the arg/return size to something
-        // reasonable -- here, 128 MB.
-        if next_stack > STACK_ARG_RET_SIZE_LIMIT {
-            return Err(CodegenError::ImplLimitExceeded);
-        }
-
-        Ok((ret, next_stack as i64, extra_arg))
-    }
-
-    fn fp_to_arg_offset(_call_conv: isa::CallConv, _flags: &settings::Flags) -> i64 {
-        0
-    }
-
-    fn gen_load_stack(mem: StackAMode, into_reg: Writable<Reg>, ty: Type) -> Inst {
-        Inst::gen_load(into_reg, mem.into(), ty)
-    }
-
-    fn gen_store_stack(mem: StackAMode, from_reg: Reg, ty: Type) -> Inst {
-        Inst::gen_store(mem.into(), from_reg, ty)
-    }
-
-    fn gen_move(to_reg: Writable<Reg>, from_reg: Reg, ty: Type) -> Inst {
-        Inst::gen_move(to_reg, from_reg, ty)
-    }
-
-    fn gen_extend(
-        to_reg: Writable<Reg>,
-        from_reg: Reg,
-        signed: bool,
-        from_bits: u8,
-        to_bits: u8,
-    ) -> Inst {
-        assert!(from_bits < to_bits);
-        Inst::Extend {
-            rd: to_reg,
-            rn: from_reg,
-            signed,
-            from_bits,
-            to_bits,
-        }
-    }
-
-    fn gen_ret() -> Inst {
-        Inst::Ret { link: gpr(14) }
-    }
-
-    fn gen_add_imm(into_reg: Writable<Reg>, from_reg: Reg, imm: u32) -> SmallInstVec<Inst> {
-        let mut insts = SmallVec::new();
-        if let Some(imm) = UImm12::maybe_from_u64(imm as u64) {
-            insts.push(Inst::LoadAddr {
-                rd: into_reg,
-                mem: MemArg::BXD12 {
-                    base: from_reg,
-                    index: zero_reg(),
-                    disp: imm,
-                    flags: MemFlags::trusted(),
-                },
-            });
-        } else if let Some(imm) = SImm20::maybe_from_i64(imm as i64) {
-            insts.push(Inst::LoadAddr {
-                rd: into_reg,
-                mem: MemArg::BXD20 {
-                    base: from_reg,
-                    index: zero_reg(),
-                    disp: imm,
-                    flags: MemFlags::trusted(),
-                },
-            });
-        } else {
-            if from_reg != into_reg.to_reg() {
-                insts.push(Inst::mov64(into_reg, from_reg));
-            }
-            insts.push(Inst::AluRUImm32 {
-                alu_op: ALUOp::AddLogical64,
-                rd: into_reg,
-                imm,
-            });
-        }
-        insts
-    }
-
-    fn gen_stack_lower_bound_trap(limit_reg: Reg) -> SmallInstVec<Inst> {
-        let mut insts = SmallVec::new();
-        insts.push(Inst::CmpTrapRR {
-            op: CmpOp::CmpL64,
-            rn: stack_reg(),
-            rm: limit_reg,
-            cond: Cond::from_intcc(IntCC::UnsignedLessThanOrEqual),
-            trap_code: ir::TrapCode::StackOverflow,
-        });
-        insts
-    }
-
-    fn gen_epilogue_placeholder() -> Inst {
-        Inst::EpiloguePlaceholder
-    }
-
-    fn gen_get_stack_addr(mem: StackAMode, into_reg: Writable<Reg>, _ty: Type) -> Inst {
-        let mem = mem.into();
-        Inst::LoadAddr { rd: into_reg, mem }
-    }
-
-    fn get_stacklimit_reg() -> Reg {
-        spilltmp_reg()
-    }
-
-    fn gen_load_base_offset(into_reg: Writable<Reg>, base: Reg, offset: i32, ty: Type) -> Inst {
-        let mem = MemArg::reg_plus_off(base, offset.into(), MemFlags::trusted());
-        Inst::gen_load(into_reg, mem, ty)
-    }
-
-    fn gen_store_base_offset(base: Reg, offset: i32, from_reg: Reg, ty: Type) -> Inst {
-        let mem = MemArg::reg_plus_off(base, offset.into(), MemFlags::trusted());
-        Inst::gen_store(mem, from_reg, ty)
-    }
-
-    fn gen_sp_reg_adjust(imm: i32) -> SmallInstVec<Inst> {
-        if imm == 0 {
-            return SmallVec::new();
-        }
-
-        let mut insts = SmallVec::new();
-        if let Ok(imm) = i16::try_from(imm) {
-            insts.push(Inst::AluRSImm16 {
-                alu_op: ALUOp::Add64,
-                rd: writable_stack_reg(),
-                imm,
-            });
-        } else {
-            insts.push(Inst::AluRSImm32 {
-                alu_op: ALUOp::Add64,
-                rd: writable_stack_reg(),
-                imm,
-            });
-        }
-        insts
-    }
-
-    fn gen_nominal_sp_adj(offset: i32) -> Inst {
-        Inst::VirtualSPOffsetAdj {
-            offset: offset.into(),
-        }
-    }
-
-    fn gen_prologue_frame_setup(_flags: &settings::Flags) -> SmallInstVec<Inst> {
-        SmallVec::new()
-    }
-
-    fn gen_epilogue_frame_restore(_flags: &settings::Flags) -> SmallInstVec<Inst> {
-        SmallVec::new()
-    }
-
-    fn gen_probestack(_: u32) -> SmallInstVec<Self::I> {
-        // TODO: implement if we ever require stack probes on an s390x host
-        // (unlikely unless Lucet is ported)
-        smallvec![]
-    }
-
-    // Returns stack bytes used as well as instructions. Does not adjust
-    // nominal SP offset; abi_impl generic code will do that.
-    fn gen_clobber_save(
-        _call_conv: isa::CallConv,
-        _setup_frame: bool,
-        flags: &settings::Flags,
-        clobbered_callee_saves: &Vec<Writable<RealReg>>,
-        fixed_frame_storage_size: u32,
-        outgoing_args_size: u32,
-    ) -> (u64, SmallVec<[Inst; 16]>) {
-        let mut insts = SmallVec::new();
-        let mut clobbered_fpr = vec![];
-        let mut clobbered_gpr = vec![];
-
-        for &reg in clobbered_callee_saves.iter() {
-            match reg.to_reg().get_class() {
-                RegClass::I64 => clobbered_gpr.push(reg),
-                RegClass::F64 => clobbered_fpr.push(reg),
-                class => panic!("Unexpected RegClass: {:?}", class),
-            }
-        }
-
-        let mut first_clobbered_gpr = 16;
-        for reg in clobbered_gpr {
-            let enc = reg.to_reg().get_hw_encoding();
-            if enc < first_clobbered_gpr {
-                first_clobbered_gpr = enc;
-            }
-        }
-        let clobber_size = clobbered_fpr.len() * 8;
-        if flags.unwind_info() {
-            insts.push(Inst::Unwind {
-                inst: UnwindInst::DefineNewFrame {
-                    offset_upward_to_caller_sp: 160,
-                    offset_downward_to_clobbers: clobber_size as u32,
-                },
-            });
-        }
-
-        // Use STMG to save clobbered GPRs into save area.
-        if first_clobbered_gpr < 16 {
-            let offset = 8 * first_clobbered_gpr as i64;
-            insts.push(Inst::StoreMultiple64 {
-                rt: gpr(first_clobbered_gpr as u8),
-                rt2: gpr(15),
-                mem: MemArg::reg_plus_off(stack_reg(), offset, MemFlags::trusted()),
-            });
-        }
-        if flags.unwind_info() {
-            for i in first_clobbered_gpr..16 {
-                insts.push(Inst::Unwind {
-                    inst: UnwindInst::SaveReg {
-                        clobber_offset: clobber_size as u32 + (i * 8) as u32,
-                        reg: gpr(i as u8).to_real_reg(),
-                    },
-                });
-            }
-        }
-
-        // Decrement stack pointer.
-        let stack_size =
-            outgoing_args_size as i32 + clobber_size as i32 + fixed_frame_storage_size as i32;
-        insts.extend(Self::gen_sp_reg_adjust(-stack_size));
-        if flags.unwind_info() {
-            insts.push(Inst::Unwind {
-                inst: UnwindInst::StackAlloc {
-                    size: stack_size as u32,
-                },
-            });
-        }
-
-        let sp_adj = outgoing_args_size as i32;
-        if sp_adj > 0 {
-            insts.push(Self::gen_nominal_sp_adj(sp_adj));
-        }
-
-        // Save FPRs.
-        for (i, reg) in clobbered_fpr.iter().enumerate() {
-            insts.push(Inst::FpuStore64 {
-                rd: reg.to_reg().to_reg(),
-                mem: MemArg::reg_plus_off(
-                    stack_reg(),
-                    (i * 8) as i64 + outgoing_args_size as i64 + fixed_frame_storage_size as i64,
-                    MemFlags::trusted(),
-                ),
-            });
-            if flags.unwind_info() {
-                insts.push(Inst::Unwind {
-                    inst: UnwindInst::SaveReg {
-                        clobber_offset: (i * 8) as u32,
-                        reg: reg.to_reg(),
-                    },
-                });
-            }
-        }
-
-        (clobber_size as u64, insts)
-    }
-
-    fn gen_clobber_restore(
-        call_conv: isa::CallConv,
-        _: &settings::Flags,
-        clobbers: &Set<Writable<RealReg>>,
-        fixed_frame_storage_size: u32,
-        outgoing_args_size: u32,
-    ) -> SmallVec<[Inst; 16]> {
-        let mut insts = SmallVec::new();
-
-        // Collect clobbered registers.
-        let (clobbered_gpr, clobbered_fpr) = get_regs_saved_in_prologue(call_conv, clobbers);
-        let mut first_clobbered_gpr = 16;
-        for reg in clobbered_gpr {
-            let enc = reg.to_reg().get_hw_encoding();
-            if enc < first_clobbered_gpr {
-                first_clobbered_gpr = enc;
-            }
-        }
-        let clobber_size = clobbered_fpr.len() * 8;
-
-        // Restore FPRs.
-        for (i, reg) in clobbered_fpr.iter().enumerate() {
-            insts.push(Inst::FpuLoad64 {
-                rd: Writable::from_reg(reg.to_reg().to_reg()),
-                mem: MemArg::reg_plus_off(
-                    stack_reg(),
-                    (i * 8) as i64 + outgoing_args_size as i64 + fixed_frame_storage_size as i64,
-                    MemFlags::trusted(),
-                ),
-            });
-        }
-
-        // Increment stack pointer unless it will be restored implicitly.
-        let stack_size =
-            outgoing_args_size as i32 + clobber_size as i32 + fixed_frame_storage_size as i32;
-        let implicit_sp_restore = first_clobbered_gpr < 16
-            && SImm20::maybe_from_i64(8 * first_clobbered_gpr as i64 + stack_size as i64).is_some();
-        if !implicit_sp_restore {
-            insts.extend(Self::gen_sp_reg_adjust(stack_size));
-        }
-
-        // Use LMG to restore clobbered GPRs from save area.
-        if first_clobbered_gpr < 16 {
-            let mut offset = 8 * first_clobbered_gpr as i64;
-            if implicit_sp_restore {
-                offset += stack_size as i64;
-            }
-            insts.push(Inst::LoadMultiple64 {
-                rt: writable_gpr(first_clobbered_gpr as u8),
-                rt2: writable_gpr(15),
-                mem: MemArg::reg_plus_off(stack_reg(), offset, MemFlags::trusted()),
-            });
-        }
-
-        insts
-    }
-
-    fn gen_call(
-        dest: &CallDest,
-        uses: Vec<Reg>,
-        defs: Vec<Writable<Reg>>,
-        opcode: ir::Opcode,
-        tmp: Writable<Reg>,
-        _callee_conv: isa::CallConv,
-        _caller_conv: isa::CallConv,
-    ) -> SmallVec<[(InstIsSafepoint, Inst); 2]> {
-        let mut insts = SmallVec::new();
-        match &dest {
-            &CallDest::ExtName(ref name, RelocDistance::Near) => insts.push((
-                InstIsSafepoint::Yes,
-                Inst::Call {
-                    link: writable_gpr(14),
-                    info: Box::new(CallInfo {
-                        dest: name.clone(),
-                        uses,
-                        defs,
-                        opcode,
-                    }),
-                },
-            )),
-            &CallDest::ExtName(ref name, RelocDistance::Far) => {
-                insts.push((
-                    InstIsSafepoint::No,
-                    Inst::LoadExtNameFar {
-                        rd: tmp,
-                        name: Box::new(name.clone()),
-                        offset: 0,
-                    },
-                ));
-                insts.push((
-                    InstIsSafepoint::Yes,
-                    Inst::CallInd {
-                        link: writable_gpr(14),
-                        info: Box::new(CallIndInfo {
-                            rn: tmp.to_reg(),
-                            uses,
-                            defs,
-                            opcode,
-                        }),
-                    },
-                ));
-            }
-            &CallDest::Reg(reg) => insts.push((
-                InstIsSafepoint::Yes,
-                Inst::CallInd {
-                    link: writable_gpr(14),
-                    info: Box::new(CallIndInfo {
-                        rn: *reg,
-                        uses,
-                        defs,
-                        opcode,
-                    }),
-                },
-            )),
-        }
-
-        insts
-    }
-
-    fn gen_memcpy(
-        _call_conv: isa::CallConv,
-        _dst: Reg,
-        _src: Reg,
-        _size: usize,
-    ) -> SmallVec<[Self::I; 8]> {
-        unimplemented!("StructArgs not implemented for S390X yet");
-    }
-
-    fn get_number_of_spillslots_for_value(rc: RegClass) -> u32 {
-        // We allocate in terms of 8-byte slots.
-        match rc {
-            RegClass::I64 => 1,
-            RegClass::F64 => 1,
-            _ => panic!("Unexpected register class!"),
-        }
-    }
-
-    /// Get the current virtual-SP offset from an instruction-emission state.
-    fn get_virtual_sp_offset_from_state(s: &EmitState) -> i64 {
-        s.virtual_sp_offset
-    }
-
-    /// Get the nominal-SP-to-FP offset from an instruction-emission state.
-    fn get_nominal_sp_to_fp(s: &EmitState) -> i64 {
-        s.initial_sp_offset
-    }
-
-    fn get_regs_clobbered_by_call(call_conv_of_callee: isa::CallConv) -> Vec<Writable<Reg>> {
-        let mut caller_saved = Vec::new();
-        for i in 0..15 {
-            let x = writable_gpr(i);
-            if is_reg_clobbered_by_call(call_conv_of_callee, x.to_reg().to_real_reg()) {
-                caller_saved.push(x);
-            }
-        }
-        for i in 0..15 {
-            let v = writable_fpr(i);
-            if is_reg_clobbered_by_call(call_conv_of_callee, v.to_reg().to_real_reg()) {
-                caller_saved.push(v);
-            }
-        }
-        caller_saved
-    }
-
-    fn get_ext_mode(
-        _call_conv: isa::CallConv,
-        specified: ir::ArgumentExtension,
-    ) -> ir::ArgumentExtension {
-        specified
-    }
-
-    fn get_clobbered_callee_saves(
-        call_conv: isa::CallConv,
-        regs: &Set<Writable<RealReg>>,
-    ) -> Vec<Writable<RealReg>> {
-        let mut regs: Vec<Writable<RealReg>> = regs
-            .iter()
-            .cloned()
-            .filter(|r| is_reg_saved_in_prologue(call_conv, r.to_reg()))
-            .collect();
-
-        // Sort registers for deterministic code output. We can do an unstable
-        // sort because the registers will be unique (there are no dups).
-        regs.sort_unstable_by_key(|r| r.to_reg().get_index());
-        regs
-    }
-
-    fn is_frame_setup_needed(
-        _is_leaf: bool,
-        _stack_args_size: u32,
-        _num_clobbered_callee_saves: usize,
-        _fixed_frame_storage_size: u32,
-    ) -> bool {
-        // The call frame set-up is handled by gen_clobber_save().
-        false
-    }
-}
-
-fn is_reg_saved_in_prologue(_call_conv: isa::CallConv, r: RealReg) -> bool {
-    match r.get_class() {
-        RegClass::I64 => {
-            // r6 - r15 inclusive are callee-saves.
-            r.get_hw_encoding() >= 6 && r.get_hw_encoding() <= 15
-        }
-        RegClass::F64 => {
-            // f8 - f15 inclusive are callee-saves.
-            r.get_hw_encoding() >= 8 && r.get_hw_encoding() <= 15
-        }
-        _ => panic!("Unexpected RegClass"),
-    }
-}
-
-fn get_regs_saved_in_prologue(
-    call_conv: isa::CallConv,
-    regs: &Set<Writable<RealReg>>,
-) -> (Vec<Writable<RealReg>>, Vec<Writable<RealReg>>) {
-    let mut int_saves = vec![];
-    let mut fpr_saves = vec![];
-    for &reg in regs.iter() {
-        if is_reg_saved_in_prologue(call_conv, reg.to_reg()) {
-            match reg.to_reg().get_class() {
-                RegClass::I64 => int_saves.push(reg),
-                RegClass::F64 => fpr_saves.push(reg),
-                _ => panic!("Unexpected RegClass"),
-            }
-        }
-    }
-    // Sort registers for deterministic code output.
-    int_saves.sort_by_key(|r| r.to_reg().get_index());
-    fpr_saves.sort_by_key(|r| r.to_reg().get_index());
-    (int_saves, fpr_saves)
-}
-
-fn is_reg_clobbered_by_call(_call_conv: isa::CallConv, r: RealReg) -> bool {
-    match r.get_class() {
-        RegClass::I64 => {
-            // r0 - r5 inclusive are caller-saves.
-            r.get_hw_encoding() <= 5
-        }
-        RegClass::F64 => {
-            // f0 - f7 inclusive are caller-saves.
-            r.get_hw_encoding() <= 7
-        }
-        _ => panic!("Unexpected RegClass"),
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/inst.isle b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/inst.isle
deleted file mode 100644
index 09a41a4fe..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/inst.isle
+++ /dev/null
@@ -1,3249 +0,0 @@
-;; Instruction formats.
-(type MInst
-  (enum
-    ;; A no-op of zero size.
-    (Nop0)
-
-    ;; A no-op of size two bytes.
-    (Nop2)
-
-    ;; An ALU operation with two register sources and a register destination.
-    (AluRRR
-      (alu_op ALUOp)
-      (rd WritableReg)
-      (rn Reg)
-      (rm Reg))
-
-    ;; An ALU operation with a register source and a signed 16-bit
-    ;; immediate source, and a separate register destination.
-    (AluRRSImm16
-      (alu_op ALUOp)
-      (rd WritableReg)
-      (rn Reg)
-      (imm i16))
-
-    ;; An ALU operation with a register in-/out operand and
-    ;; a second register source.
-    (AluRR
-      (alu_op ALUOp)
-      (rd WritableReg)
-      (rm Reg))
-
-    ;; An ALU operation with a register in-/out operand and
-    ;; a memory source.
-    (AluRX
-      (alu_op ALUOp)
-      (rd WritableReg)
-      (mem MemArg))
-
-    ;; An ALU operation with a register in-/out operand and a signed 16-bit
-    ;; immediate source.
-    (AluRSImm16
-      (alu_op ALUOp)
-      (rd WritableReg)
-      (imm i16))
-
-    ;; An ALU operation with a register in-/out operand and a signed 32-bit
-    ;; immediate source.
-    (AluRSImm32
-      (alu_op ALUOp)
-      (rd WritableReg)
-      (imm i32))
-
-    ;; An ALU operation with a register in-/out operand and an unsigned 32-bit
-    ;; immediate source.
-    (AluRUImm32
-      (alu_op ALUOp)
-      (rd WritableReg)
-      (imm u32))
-
-    ;; An ALU operation with a register in-/out operand and a shifted 16-bit
-    ;; immediate source.
-    (AluRUImm16Shifted
-      (alu_op ALUOp)
-      (rd WritableReg)
-      (imm UImm16Shifted))
-
-    ;; An ALU operation with a register in-/out operand and a shifted 32-bit
-    ;; immediate source.
-    (AluRUImm32Shifted
-      (alu_op ALUOp)
-      (rd WritableReg)
-      (imm UImm32Shifted))
-
-    ;; A multiply operation with two register sources and a register pair destination.
-    ;; FIXME: The pair is hard-coded as %r0/%r1 because regalloc cannot handle pairs.
-    (SMulWide
-      (rn Reg)
-      (rm Reg))
-
-    ;; A multiply operation with an in/out register pair, and an extra register source.
-    ;; Only the lower half of the register pair is used as input.
-    ;; FIXME: The pair is hard-coded as %r0/%r1 because regalloc cannot handle pairs.
-    (UMulWide
-      (rn Reg))
-
-    ;; A divide operation with an in/out register pair, and an extra register source.
-    ;; Only the lower half of the register pair is used as input.
-    ;; FIXME: The pair is hard-coded as %r0/%r1 because regalloc cannot handle pairs.
-    (SDivMod32
-      (rn Reg))
-    (SDivMod64
-      (rn Reg))
-
-    ;; A divide operation with an in/out register pair, and an extra register source.
-    ;; FIXME: The pair is hard-coded as %r0/%r1 because regalloc cannot handle pairs.
-    (UDivMod32
-      (rn Reg))
-    (UDivMod64
-      (rn Reg))
-
-    ;; A FLOGR operation with a register source and a register pair destination.
-    ;; FIXME The pair is hard-coded as %r0/%r1 because regalloc cannot handle pairs.
-    (Flogr
-      (rn Reg))
-
-    ;; A shift instruction with a register source, a register destination,
-    ;; and an immediate plus an optional register as shift count.
-    (ShiftRR
-      (shift_op ShiftOp)
-      (rd WritableReg)
-      (rn Reg)
-      (shift_imm u8)
-      (shift_reg Reg))
-
-    ;; A rotate-then-<op>-selected-bits instruction with a register
-    ;; in/out-operand, another register source, and three immediates.
-    (RxSBG
-        (op RxSBGOp)
-        (rd WritableReg)
-        (rn Reg)
-        (start_bit u8)
-        (end_bit u8)
-        (rotate_amt i8))
-
-    ;; The test-only version of RxSBG, which does not modify any register
-    ;; but only sets the condition code.
-    (RxSBGTest
-        (op RxSBGOp)
-        (rd Reg)
-        (rn Reg)
-        (start_bit u8)
-        (end_bit u8)
-        (rotate_amt i8))
-
-    ;; An unary operation with a register source and a register destination.
-    (UnaryRR
-      (op UnaryOp)
-      (rd WritableReg)
-      (rn Reg))
-
-    ;; A compare operation with two register sources.
-    (CmpRR
-      (op CmpOp)
-      (rn Reg)
-      (rm Reg))
-
-    ;; A compare operation with a register source and a memory source.
-    (CmpRX
-      (op CmpOp)
-      (rn Reg)
-      (mem MemArg))
-
-    ;; A compare operation with a register source and a signed 16-bit
-    ;; immediate source.
-    (CmpRSImm16
-      (op CmpOp)
-      (rn Reg)
-      (imm i16))
-
-    ;; A compare operation with a register source and a signed 32-bit
-    ;; immediate source.
-    (CmpRSImm32
-      (op CmpOp)
-      (rn Reg)
-      (imm i32))
-
-    ;; A compare operation with a register source and a unsigned 32-bit
-    ;; immediate source.
-    (CmpRUImm32
-      (op CmpOp)
-      (rn Reg)
-      (imm u32))
-
-    ;; A compare-and-trap instruction with two register sources.
-    (CmpTrapRR
-      (op CmpOp)
-      (rn Reg)
-      (rm Reg)
-      (cond Cond)
-      (trap_code TrapCode))
-
-    ;; A compare-and-trap operation with a register source and a signed 16-bit
-    ;; immediate source.
-    (CmpTrapRSImm16
-      (op CmpOp)
-      (rn Reg)
-      (imm i16)
-      (cond Cond)
-      (trap_code TrapCode))
-
-    ;; A compare-and-trap operation with a register source and an unsigned 16-bit
-    ;; immediate source.
-    (CmpTrapRUImm16
-      (op CmpOp)
-      (rn Reg)
-      (imm u16)
-      (cond Cond)
-      (trap_code TrapCode))
-
-    ;; An atomic read-modify-write operation with a memory in-/out operand,
-    ;; a register destination, and a register source.
-    ;; a memory source.
-    (AtomicRmw
-      (alu_op ALUOp)
-      (rd WritableReg)
-      (rn Reg)
-      (mem MemArg))
-
-    ;; A 32-bit atomic compare-and-swap operation.
-    (AtomicCas32
-      (rd WritableReg)
-      (rn Reg)
-      (mem MemArg))
-
-    ;; A 64-bit atomic compare-and-swap operation.
-    (AtomicCas64
-      (rd WritableReg)
-      (rn Reg)
-      (mem MemArg))
-
-    ;; A memory fence operation.
-    (Fence)
-
-    ;; A 32-bit load.
-    (Load32
-      (rd WritableReg)
-      (mem MemArg))
-
-    ;; An unsigned (zero-extending) 8-bit to 32-bit load.
-    (Load32ZExt8
-      (rd WritableReg)
-      (mem MemArg))
-
-    ;; A signed (sign-extending) 8-bit to 32-bit load.
-    (Load32SExt8
-      (rd WritableReg)
-      (mem MemArg))
-
-    ;; An unsigned (zero-extending) 16-bit to 32-bit load.
-    (Load32ZExt16
-      (rd WritableReg)
-      (mem MemArg))
-
-    ;; A signed (sign-extending) 16-bit to 32-bit load.
-    (Load32SExt16
-      (rd WritableReg)
-      (mem MemArg))
-
-    ;; A 64-bit load.
-    (Load64
-      (rd WritableReg)
-      (mem MemArg))
-
-    ;; An unsigned (zero-extending) 8-bit to 64-bit load.
-    (Load64ZExt8
-      (rd WritableReg)
-      (mem MemArg))
-
-    ;; A signed (sign-extending) 8-bit to 64-bit load.
-    (Load64SExt8
-      (rd WritableReg)
-      (mem MemArg))
-
-    ;; An unsigned (zero-extending) 16-bit to 64-bit load.
-    (Load64ZExt16
-      (rd WritableReg)
-      (mem MemArg))
-
-    ;; A signed (sign-extending) 16-bit to 64-bit load.
-    (Load64SExt16
-      (rd WritableReg)
-      (mem MemArg))
-
-    ;; An unsigned (zero-extending) 32-bit to 64-bit load.
-    (Load64ZExt32
-      (rd WritableReg)
-      (mem MemArg))
-
-    ;; A signed (sign-extending) 32-bit to 64-bit load.
-    (Load64SExt32
-      (rd WritableReg)
-      (mem MemArg))
-
-    ;; A 16-bit byte-reversed load.
-    (LoadRev16
-      (rd WritableReg)
-      (mem MemArg))
-
-    ;; A 32-bit byte-reversed load.
-    (LoadRev32
-      (rd WritableReg)
-      (mem MemArg))
-
-    ;; A 64-bit byte-reversed load.
-    (LoadRev64
-      (rd WritableReg)
-      (mem MemArg))
-
-    ;; An 8-bit store.
-    (Store8
-      (rd Reg)
-      (mem MemArg))
-
-    ;; A 16-bit store.
-    (Store16
-      (rd Reg)
-      (mem MemArg))
-
-    ;; A 32-bit store.
-    (Store32
-      (rd Reg)
-      (mem MemArg))
-
-    ;; A 64-bit store.
-    (Store64
-      (rd Reg)
-      (mem MemArg))
-
-    ;; An 8-bit store of an immediate.
-    (StoreImm8
-      (imm u8)
-      (mem MemArg))
-
-    ;; A 16-bit store of an immediate.
-    (StoreImm16
-      (imm i16)
-      (mem MemArg))
-
-    ;; A 32-bit store of a sign-extended 16-bit immediate.
-    (StoreImm32SExt16
-      (imm i16)
-      (mem MemArg))
-
-    ;; A 64-bit store of a sign-extended 16-bit immediate.
-    (StoreImm64SExt16
-      (imm i16)
-      (mem MemArg))
-
-    ;; A 16-bit byte-reversed store.
-    (StoreRev16
-      (rd Reg)
-      (mem MemArg))
-
-    ;; A 32-bit byte-reversed store.
-    (StoreRev32
-      (rd Reg)
-      (mem MemArg))
-
-    ;; A 64-bit byte-reversed store.
-    (StoreRev64
-      (rd Reg)
-      (mem MemArg))
-
-    ;; A load-multiple instruction.
-    (LoadMultiple64
-      (rt WritableReg)
-      (rt2 WritableReg)
-      (mem MemArg))
-
-    ;; A store-multiple instruction.
-    (StoreMultiple64
-      (rt Reg)
-      (rt2 Reg)
-      (mem MemArg))
-
-    ;; A 32-bit move instruction.
-    (Mov32
-      (rd WritableReg)
-      (rm Reg))
-
-    ;; A 64-bit move instruction.
-    (Mov64
-      (rd WritableReg)
-      (rm Reg))
-
-    ;; A 32-bit move instruction with a full 32-bit immediate.
-    (Mov32Imm
-      (rd WritableReg)
-      (imm u32))
-
-    ;; A 32-bit move instruction with a 16-bit signed immediate.
-    (Mov32SImm16
-      (rd WritableReg)
-      (imm i16))
-
-    ;; A 64-bit move instruction with a 16-bit signed immediate.
-    (Mov64SImm16
-      (rd WritableReg)
-      (imm i16))
-
-    ;; A 64-bit move instruction with a 32-bit signed immediate.
-    (Mov64SImm32
-      (rd WritableReg)
-      (imm i32))
-
-    ;; A 64-bit move instruction with a shifted 16-bit immediate.
-    (Mov64UImm16Shifted
-      (rd WritableReg)
-      (imm UImm16Shifted))
-
-    ;; A 64-bit move instruction with a shifted 32-bit immediate.
-    (Mov64UImm32Shifted
-      (rd WritableReg)
-      (imm UImm32Shifted))
-
-    ;; A 64-bit insert instruction with a shifted 16-bit immediate.
-    (Insert64UImm16Shifted
-      (rd WritableReg)
-      (imm UImm16Shifted))
-
-    ;; A 64-bit insert instruction with a shifted 32-bit immediate.
-    (Insert64UImm32Shifted
-      (rd WritableReg)
-      (imm UImm32Shifted))
-
-    ;; A sign- or zero-extend operation.
-    (Extend
-      (rd WritableReg)
-      (rn Reg)
-      (signed bool)
-      (from_bits u8)
-      (to_bits u8))
-
-    ;; A 32-bit conditional move instruction.
-    (CMov32
-      (rd WritableReg)
-      (cond Cond)
-      (rm Reg))
-
-    ;; A 64-bit conditional move instruction.
-    (CMov64
-      (rd WritableReg)
-      (cond Cond)
-      (rm Reg))
-
-    ;; A 32-bit conditional move instruction with a 16-bit signed immediate.
-    (CMov32SImm16
-      (rd WritableReg)
-      (cond Cond)
-      (imm i16))
-
-    ;; A 64-bit conditional move instruction with a 16-bit signed immediate.
-    (CMov64SImm16
-      (rd WritableReg)
-      (cond Cond)
-      (imm i16))
-
-    ;; A 32-bit FPU move.
-    (FpuMove32
-      (rd WritableReg)
-      (rn Reg))
-
-    ;; A 64-bit FPU move.
-    (FpuMove64
-      (rd WritableReg)
-      (rn Reg))
-
-    ;; A 32-bit conditional move FPU instruction.
-    (FpuCMov32
-      (rd WritableReg)
-      (cond Cond)
-      (rm Reg))
-
-    ;; A 64-bit conditional move FPU instruction.
-    (FpuCMov64
-      (rd WritableReg)
-      (cond Cond)
-      (rm Reg))
-
-    ;; A 64-bit move instruction from GPR to FPR.
-    (MovToFpr
-      (rd WritableReg)
-      (rn Reg))
-
-    ;; A 64-bit move instruction from FPR to GPR.
-    (MovFromFpr
-      (rd WritableReg)
-      (rn Reg))
-
-    ;; 1-op FPU instruction.
-    (FpuRR
-      (fpu_op FPUOp1)
-      (rd WritableReg)
-      (rn Reg))
-
-    ;; 2-op FPU instruction.
-    (FpuRRR
-      (fpu_op FPUOp2)
-      (rd WritableReg)
-      (rm Reg))
-
-    ;; 3-op FPU instruction.
-    (FpuRRRR
-      (fpu_op FPUOp3)
-      (rd WritableReg)
-      (rn Reg)
-      (rm Reg))
-
-    ;; FPU copy sign instruction.
-    (FpuCopysign
-      (rd WritableReg)
-      (rn Reg)
-      (rm Reg))
-
-    ;; FPU comparison, single-precision (32 bit).
-    (FpuCmp32
-      (rn Reg)
-      (rm Reg))
-
-    ;; FPU comparison, double-precision (64 bit).
-    (FpuCmp64
-      (rn Reg)
-      (rm Reg))
-
-    ;; Floating-point load, single-precision (32 bit).
-    (FpuLoad32
-      (rd WritableReg)
-      (mem MemArg))
-
-    ;; Floating-point store, single-precision (32 bit).
-    (FpuStore32
-      (rd Reg)
-      (mem MemArg))
-
-    ;; Floating-point load, double-precision (64 bit).
-    (FpuLoad64
-      (rd WritableReg)
-      (mem MemArg))
-
-    ;; Floating-point store, double-precision (64 bit).
-    (FpuStore64
-      (rd Reg)
-      (mem MemArg))
-
-    ;; Floating-point byte-reversed load, single-precision (32 bit).
-    (FpuLoadRev32
-      (rd WritableReg)
-      (mem MemArg))
-
-    ;; Floating-point byte-reversed store, single-precision (32 bit).
-    (FpuStoreRev32
-      (rd Reg)
-      (mem MemArg))
-
-    ;; Floating-point byte-reversed load, double-precision (64 bit).
-    (FpuLoadRev64
-      (rd WritableReg)
-      (mem MemArg))
-
-    ;; Floating-point byte-reversed store, double-precision (64 bit).
-    (FpuStoreRev64
-      (rd Reg)
-      (mem MemArg))
-
-    ;; Load floating-point constant, single-precision (32 bit).
-    (LoadFpuConst32
-      (rd WritableReg)
-      (const_data u32))
-
-    ;; Load floating-point constant, double-precision (64 bit).
-    (LoadFpuConst64
-      (rd WritableReg)
-      (const_data u64))
-
-    ;; Conversion FP -> integer.
-    (FpuToInt
-      (op FpuToIntOp)
-      (rd WritableReg)
-      (rn Reg))
-
-    ;; Conversion integer -> FP.
-    (IntToFpu
-      (op IntToFpuOp)
-      (rd WritableReg)
-      (rn Reg))
-
-    ;; Round to integer.
-    (FpuRound
-      (op FpuRoundMode)
-      (rd WritableReg)
-      (rn Reg))
-
-    ;; 2-op FPU instruction implemented as vector instruction with the W bit.
-    (FpuVecRRR
-      (fpu_op FPUOp2)
-      (rd WritableReg)
-      (rn Reg)
-      (rm Reg))
-
-    ;; A machine call instruction.
-    (Call
-      (link WritableReg)
-      (info BoxCallInfo))
-
-    ;; A machine indirect-call instruction.
-    (CallInd
-      (link WritableReg)
-      (info BoxCallIndInfo))
-
-    ;; ---- branches (exactly one must appear at end of BB) ----
-
-    ;; A machine return instruction.
-    (Ret
-      (link Reg))
-
-    ;; A placeholder instruction, generating no code, meaning that a function epilogue must be
-    ;; inserted there.
-    (EpiloguePlaceholder)
-
-    ;; An unconditional branch.
-    (Jump
-      (dest MachLabel))
-
-    ;; A conditional branch. Contains two targets; at emission time, both are emitted, but
-    ;; the MachBuffer knows to truncate the trailing branch if fallthrough. We optimize the
-    ;; choice of taken/not_taken (inverting the branch polarity as needed) based on the
-    ;; fallthrough at the time of lowering.
-    (CondBr
-      (taken MachLabel)
-      (not_taken MachLabel)
-      (cond Cond))
-
-    ;; A conditional trap execute a `Trap` if the condition is true. This is
-    ;; one VCode instruction because it uses embedded control flow; it is
-    ;; logically a single-in, single-out region, but needs to appear as one
-    ;; unit to the register allocator.
-    ;;
-    ;; The `Cond` gives the conditional-branch condition that will
-    ;; *execute* the embedded `Trap`. (In the emitted code, we use the inverse
-    ;; of this condition in a branch that skips the trap instruction.)
-    (TrapIf
-      (cond Cond)
-      (trap_code TrapCode))
-
-    ;; A one-way conditional branch, invisible to the CFG processing; used *only* as part of
-    ;; straight-line sequences in code to be emitted.
-    ;;
-    ;; In more detail:
-    ;; - This branch is lowered to a branch at the machine-code level, but does not end a basic
-    ;;   block, and does not create edges in the CFG seen by regalloc.
-    ;; - Thus, it is *only* valid to use as part of a single-in, single-out sequence that is
-    ;;   lowered from a single CLIF instruction. For example, certain arithmetic operations may
-    ;;   use these branches to handle certain conditions, such as overflows, traps, etc.
-    ;;
-    ;; See, e.g., the lowering of `trapif` (conditional trap) for an example.
-    (OneWayCondBr
-      (target MachLabel)
-      (cond Cond))
-
-    ;; An indirect branch through a register, augmented with set of all
-    ;; possible successors.
-    (IndirectBr
-      (rn Reg)
-      (targets VecMachLabel))
-
-    ;; A "debugtrap" instruction, used for e.g. traps and debug breakpoints.
-    (Debugtrap)
-
-    ;; An instruction guaranteed to always be undefined and to trigger an illegal instruction at
-    ;; runtime.
-    (Trap
-      (trap_code TrapCode))
-
-    ;; Jump-table sequence, as one compound instruction (see note in lower.rs
-    ;; for rationale).
-    (JTSequence
-      (ridx Reg)
-      (targets VecMachLabel))
-
-    ;; Load an inline symbol reference with RelocDistance::Far.
-    (LoadExtNameFar
-      (rd WritableReg)
-      (name BoxExternalName)
-      (offset i64))
-
-    ;; Load address referenced by `mem` into `rd`.
-    (LoadAddr
-      (rd WritableReg)
-      (mem MemArg))
-
-    ;; Meta-instruction to emit a loop around a sequence of instructions.
-    ;; This control flow is not visible to the compiler core, in particular
-    ;; the register allocator.  Therefore, instructions in the loop may not
-    ;; write to any virtual register, so any writes must use reserved hard
-    ;; registers (e.g. %r0, %r1).  *Reading* virtual registers is OK.
-    (Loop
-      (body VecMInst)
-      (cond Cond))
-
-    ;; Conditional branch breaking out of a loop emitted via Loop.
-    (CondBreak
-      (cond Cond))
-
-    ;; Marker, no-op in generated code SP "virtual offset" is adjusted. This
-    ;; controls how MemArg::NominalSPOffset args are lowered.
-    (VirtualSPOffsetAdj
-      (offset i64))
-
-    ;; A definition of a value label.
-    (ValueLabelMarker
-      (reg Reg)
-      (label ValueLabel))
-
-    ;; An unwind pseudoinstruction describing the state of the
-    ;; machine at this program point.
-    (Unwind
-      (inst UnwindInst))
-))
-
-;; Primitive types used in instruction formats.
-
-(type BoxCallInfo (primitive BoxCallInfo))
-(type BoxCallIndInfo (primitive BoxCallIndInfo))
-(type BoxJTSequenceInfo (primitive BoxJTSequenceInfo))
-
-;; An ALU operation.
-(type ALUOp
-  (enum
-    (Add32)
-    (Add32Ext16)
-    (Add64)
-    (Add64Ext16)
-    (Add64Ext32)
-    (AddLogical32)
-    (AddLogical64)
-    (AddLogical64Ext32)
-    (Sub32)
-    (Sub32Ext16)
-    (Sub64)
-    (Sub64Ext16)
-    (Sub64Ext32)
-    (SubLogical32)
-    (SubLogical64)
-    (SubLogical64Ext32)
-    (Mul32)
-    (Mul32Ext16)
-    (Mul64)
-    (Mul64Ext16)
-    (Mul64Ext32)
-    (And32)
-    (And64)
-    (Orr32)
-    (Orr64)
-    (Xor32)
-    (Xor64)
-    ;; NAND
-    (AndNot32)
-    (AndNot64)
-    ;; NOR
-    (OrrNot32)
-    (OrrNot64)
-    ;; XNOR
-    (XorNot32)
-    (XorNot64)
-))
-
-;; A unary operation.
-(type UnaryOp
-  (enum
-    (Abs32)
-    (Abs64)
-    (Abs64Ext32)
-    (Neg32)
-    (Neg64)
-    (Neg64Ext32)
-    (PopcntByte)
-    (PopcntReg)
-    (BSwap32)
-    (BSwap64)
-))
-
-;; A shift operation.
-(type ShiftOp
-  (enum
-    (RotL32)
-    (RotL64)
-    (LShL32)
-    (LShL64)
-    (LShR32)
-    (LShR64)
-    (AShR32)
-    (AShR64)
-))
-
-;; A rotate-then-<op>-selected-bits operation.
-(type RxSBGOp
-  (enum
-    (Insert)
-    (And)
-    (Or)
-    (Xor)
-))
-
-;; An integer comparison operation.
-(type CmpOp
-  (enum
-    (CmpS32)
-    (CmpS32Ext16)
-    (CmpS64)
-    (CmpS64Ext16)
-    (CmpS64Ext32)
-    (CmpL32)
-    (CmpL32Ext16)
-    (CmpL64)
-    (CmpL64Ext16)
-    (CmpL64Ext32)
-))
-
-;; A floating-point unit (FPU) operation with one arg.
-(type FPUOp1
-  (enum
-    (Abs32)
-    (Abs64)
-    (Neg32)
-    (Neg64)
-    (NegAbs32)
-    (NegAbs64)
-    (Sqrt32)
-    (Sqrt64)
-    (Cvt32To64)
-    (Cvt64To32)
-))
-
-;; A floating-point unit (FPU) operation with two args.
-(type FPUOp2
-  (enum
-    (Add32)
-    (Add64)
-    (Sub32)
-    (Sub64)
-    (Mul32)
-    (Mul64)
-    (Div32)
-    (Div64)
-    (Max32)
-    (Max64)
-    (Min32)
-    (Min64)
-))
-
-;; A floating-point unit (FPU) operation with three args.
-(type FPUOp3
-  (enum
-    (MAdd32)
-    (MAdd64)
-    (MSub32)
-    (MSub64)
-))
-
-;; A conversion from an FP to an integer value.
-(type FpuToIntOp
-  (enum
-    (F32ToU32)
-    (F32ToI32)
-    (F32ToU64)
-    (F32ToI64)
-    (F64ToU32)
-    (F64ToI32)
-    (F64ToU64)
-    (F64ToI64)
-))
-
-;; A conversion from an integer to an FP value.
-(type IntToFpuOp
-  (enum
-    (U32ToF32)
-    (I32ToF32)
-    (U32ToF64)
-    (I32ToF64)
-    (U64ToF32)
-    (I64ToF32)
-    (U64ToF64)
-    (I64ToF64)
-))
-
-;; Modes for FP rounding ops: round down (floor) or up (ceil), or toward zero
-;; (trunc), or to nearest, and for 32- or 64-bit FP values.
-(type FpuRoundMode
-  (enum
-    (Minus32)
-    (Minus64)
-    (Plus32)
-    (Plus64)
-    (Zero32)
-    (Zero64)
-    (Nearest32)
-    (Nearest64)
-))
-
-
-;; Helpers for querying enabled ISA extensions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl mie2_enabled () Type)
-(extern extractor mie2_enabled mie2_enabled)
-(decl mie2_disabled () Type)
-(extern extractor mie2_disabled mie2_disabled)
-
-(decl vxrs_ext2_enabled () Type)
-(extern extractor vxrs_ext2_enabled vxrs_ext2_enabled)
-(decl vxrs_ext2_disabled () Type)
-(extern extractor vxrs_ext2_disabled vxrs_ext2_disabled)
-
-(decl allow_div_traps () Type)
-(extern extractor allow_div_traps allow_div_traps)
-
-
-;; Helpers for register numbers and types ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Hard-coded registers.
-(decl writable_gpr (u8) WritableReg)
-(extern constructor writable_gpr writable_gpr)
-
-;; The zero register.
-(decl zero_reg () Reg)
-(extern constructor zero_reg zero_reg)
-
-;; Types that can be operated on using 32-bit GPR instructions
-(decl gpr32_ty (Type) Type)
-(extern extractor gpr32_ty gpr32_ty)
-
-;; Types that can be operated on using 64-bit GPR instructions
-(decl gpr64_ty (Type) Type)
-(extern extractor gpr64_ty gpr64_ty)
-
-
-;; Helpers for various immmediate constants ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Special integer types and their constructors
-
-(type UImm32Shifted (primitive UImm32Shifted))
-(decl uimm32shifted (u32 u8) UImm32Shifted)
-(extern constructor uimm32shifted uimm32shifted)
-
-(type UImm16Shifted (primitive UImm16Shifted))
-(decl uimm16shifted (u16 u8) UImm16Shifted)
-(extern constructor uimm16shifted uimm16shifted)
-
-;; Detect specific integer values
-
-(decl i64_nonequal (i64 i64) i64)
-(extern extractor i64_nonequal i64_nonequal (out in))
-
-(decl i64_nonzero (i64) i64)
-(extractor (i64_nonzero val) (i64_nonequal val <0))
-
-(decl i64_not_neg1 (i64) i64)
-(extractor (i64_not_neg1 val) (i64_nonequal val <-1))
-
-;; Integer type casts (with the rust `as` semantics).
-
-(decl u8_as_u16 (u8) u16)
-(extern constructor u8_as_u16 u8_as_u16)
-
-(decl u64_as_u32 (u64) u32)
-(extern constructor u64_as_u32 u64_as_u32)
-
-(decl u64_as_i16 (u64) i16)
-(extern constructor u64_as_i16 u64_as_i16)
-
-;; Split an u64 into high and low parts.
-
-(decl u64_nonzero_hipart (u64) u64)
-(extern extractor u64_nonzero_hipart u64_nonzero_hipart)
-
-(decl u64_nonzero_lopart (u64) u64)
-(extern extractor u64_nonzero_lopart u64_nonzero_lopart)
-
-;; Extract smaller integer type from u64 if it matches.
-
-(decl i32_from_u64 (i32) u64)
-(extern extractor i32_from_u64 i32_from_u64)
-
-(decl i16_from_u64 (i16) u64)
-(extern extractor i16_from_u64 i16_from_u64)
-
-(decl uimm32shifted_from_u64 (UImm32Shifted) u64)
-(extern extractor uimm32shifted_from_u64 uimm32shifted_from_u64)
-
-(decl uimm16shifted_from_u64 (UImm16Shifted) u64)
-(extern extractor uimm16shifted_from_u64 uimm16shifted_from_u64)
-
-;; Extract integer of certain type from value if it matches.
-
-(decl u64_from_value (u64) Value)
-(extern extractor u64_from_value u64_from_value)
-
-(decl u32_from_value (u32) Value)
-(extern extractor u32_from_value u32_from_value)
-
-(decl u8_from_value (u8) Value)
-(extern extractor u8_from_value u8_from_value)
-
-(decl u64_from_signed_value (u64) Value)
-(extern extractor u64_from_signed_value u64_from_signed_value)
-
-(decl i64_from_value (i64) Value)
-(extern extractor i64_from_value i64_from_value)
-
-(decl i32_from_value (i32) Value)
-(extern extractor i32_from_value i32_from_value)
-
-(decl i16_from_value (i16) Value)
-(extern extractor i16_from_value i16_from_value)
-
-(decl i16_from_swapped_value (i16) Value)
-(extern extractor i16_from_swapped_value i16_from_swapped_value)
-
-(decl i64_from_negated_value (i64) Value)
-(extern extractor i64_from_negated_value i64_from_negated_value)
-
-(decl i32_from_negated_value (i32) Value)
-(extern extractor i32_from_negated_value i32_from_negated_value)
-
-(decl i16_from_negated_value (i16) Value)
-(extern extractor i16_from_negated_value i16_from_negated_value)
-
-(decl uimm16shifted_from_value (UImm16Shifted) Value)
-(extern extractor uimm16shifted_from_value uimm16shifted_from_value)
-
-(decl uimm32shifted_from_value (UImm32Shifted) Value)
-(extern extractor uimm32shifted_from_value uimm32shifted_from_value)
-
-(decl uimm16shifted_from_inverted_value (UImm16Shifted) Value)
-(extern extractor uimm16shifted_from_inverted_value uimm16shifted_from_inverted_value)
-
-(decl uimm32shifted_from_inverted_value (UImm32Shifted) Value)
-(extern extractor uimm32shifted_from_inverted_value uimm32shifted_from_inverted_value)
-
-
-;; Helpers for masking shift amounts ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Mask (immediate) shift amount to the type size.
-(decl mask_amt_imm (Type i64) u8)
-(extern constructor mask_amt_imm mask_amt_imm)
-
-;; Mask (immediate) shift amount to the type size.
-;; Note that the hardware instructions always masks to six bits, so
-;; in the case of a 64-bit type we do not need any explicit masking.
-(decl mask_amt_reg (Type Reg) Reg)
-(rule (mask_amt_reg (gpr32_ty ty) reg)
-      (let ((mask u8 (mask_amt_imm ty -1)))
-        (and_uimm16shifted ty reg (uimm16shifted (u8_as_u16 mask) 0))))
-(rule (mask_amt_reg (gpr64_ty ty) reg) reg)
-
-
-;; Helpers for condition codes ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(type Cond extern (enum))
-
-(decl mask_as_cond (u8) Cond)
-(extern constructor mask_as_cond mask_as_cond)
-
-(decl intcc_as_cond (IntCC) Cond)
-(extern constructor intcc_as_cond intcc_as_cond)
-
-(decl floatcc_as_cond (FloatCC) Cond)
-(extern constructor floatcc_as_cond floatcc_as_cond)
-
-(decl invert_cond (Cond) Cond)
-(extern constructor invert_cond invert_cond)
-
-(decl signed () IntCC)
-(extern extractor signed signed)
-
-(decl unsigned () IntCC)
-(extern extractor unsigned unsigned)
-
-
-;; Helpers for machine label vectors ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl vec_length_minus1 (VecMachLabel) u32)
-(extern constructor vec_length_minus1 vec_length_minus1)
-
-(decl vec_element (VecMachLabel u8) MachLabel)
-(extern constructor vec_element vec_element)
-
-
-;; Helpers for memory arguments ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Accessors for `Offset32`.
-
-(decl zero_offset () Offset32)
-(extern constructor zero_offset zero_offset)
-
-(decl i64_from_offset (i64) Offset32)
-(extern extractor infallible i64_from_offset i64_from_offset)
-
-;; Accessors for `ExternalName`.
-
-(decl box_external_name (ExternalName) BoxExternalName)
-(extern constructor box_external_name box_external_name)
-
-;; Accessors for `MemFlags`.
-
-(decl littleendian () MemFlags)
-(extern extractor littleendian littleendian)
-
-(decl bigendian () MemFlags)
-(extern extractor bigendian bigendian)
-
-(decl memflags_trusted () MemFlags)
-(extern constructor memflags_trusted memflags_trusted)
-
-;; Accessors for `MemArg`.
-
-(type MemArg extern (enum))
-
-(decl memarg_reg_plus_reg (Reg Reg MemFlags) MemArg)
-(extern constructor memarg_reg_plus_reg memarg_reg_plus_reg)
-
-(decl memarg_reg_plus_off (Reg i64 MemFlags) MemArg)
-(extern constructor memarg_reg_plus_off memarg_reg_plus_off)
-
-(decl memarg_symbol (ExternalName i32 MemFlags) MemArg)
-(extern constructor memarg_symbol memarg_symbol)
-
-;; Form the sum of two offset values, and check that the result is
-;; a valid `MemArg::Symbol` offset (i.e. is even and fits into i32).
-(decl memarg_symbol_offset_sum (i64 i32) i64)
-(extern extractor memarg_symbol_offset_sum memarg_symbol_offset_sum (in out))
-
-;; Likewise, but just check a single offset value.
-(decl memarg_symbol_offset (i32) i64)
-(extractor (memarg_symbol_offset offset) (memarg_symbol_offset_sum <0 offset))
-
-;; Lower an address into a `MemArg`.
-
-(decl lower_address (MemFlags Value Offset32) MemArg)
-
-(rule (lower_address flags addr (i64_from_offset offset))
-      (memarg_reg_plus_off addr offset flags))
-
-(rule (lower_address flags (def_inst (iadd x y)) (i64_from_offset 0))
-      (memarg_reg_plus_reg x y flags))
-
-(rule (lower_address flags
-        (def_inst (symbol_value (symbol_value_data name (reloc_distance_near) offset)))
-        (i64_from_offset (memarg_symbol_offset_sum <offset final_offset)))
-      (memarg_symbol name final_offset flags))
-
-
-;; Test whether a `load` address will be lowered to a `MemArg::Symbol`.
-
-(decl load_sym (Inst) Inst)
-(extractor (load_sym inst)
-  (and inst
-       (load _ (def_inst (symbol_value (symbol_value_data _ (reloc_distance_near) offset)))
-               (i64_from_offset (memarg_symbol_offset_sum <offset _)))))
-
-(decl uload16_sym (Inst) Inst)
-(extractor (uload16_sym inst)
-  (and inst
-       (uload16 _ (def_inst (symbol_value (symbol_value_data _ (reloc_distance_near) offset)))
-                  (i64_from_offset (memarg_symbol_offset_sum <offset _)))))
-
-
-;; Helpers for stack-slot addresses ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl abi_stackslot_addr (WritableReg StackSlot Offset32) MInst)
-(extern constructor abi_stackslot_addr abi_stackslot_addr)
-
-(decl stack_addr_impl (Type StackSlot Offset32) Reg)
-(rule (stack_addr_impl ty stack_slot offset)
-      (let ((dst WritableReg (temp_writable_reg ty))
-            (_ Unit (emit (abi_stackslot_addr dst stack_slot offset))))
-        dst))
-
-
-;; Helpers for extracting extensions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; A value that is the result of a sign-extend from a 32-bit value.
-(decl sext32_value (Value) Value)
-(extractor (sext32_value x) (def_inst (sextend (and x (value_type $I32)))))
-
-;; A value that is the result of a zero-extend from a 32-bit value.
-(decl zext32_value (Value) Value)
-(extractor (zext32_value x) (def_inst (uextend (and x (value_type $I32)))))
-
-
-;; Helpers for sinkable loads ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Extract a sinkable instruction from a value operand.
-(decl sinkable_inst (Inst) Value)
-(extern extractor sinkable_inst sinkable_inst)
-
-;; Sink a sinkable instruction.
-;;
-;; This is a side-effectful operation that notifies the context that the
-;; sinkable instruction been sunk into another instruction, and no longer
-;; needs to be lowered.
-(decl sink_inst (Inst) Unit)
-(extern constructor sink_inst sink_inst)
-
-
-;; Sinkable big-endian load instruction.
-(decl sinkable_load (Inst) Value)
-(extractor (sinkable_load inst)
-           (sinkable_inst (and inst (load (bigendian) _addr _offset))))
-
-;; Sinkable big-endian load instruction (32/64-bit types only).
-(decl sinkable_load_32_64 (Inst) Value)
-(extractor (sinkable_load_32_64 inst)
-           (and (value_type (ty_32_or_64 _)) (sinkable_load inst)))
-
-;; Sinkable big-endian load instruction (16-bit types only).
-(decl sinkable_load_16 (Inst) Value)
-(extractor (sinkable_load_16 inst)
-           (and (value_type $I16) (sinkable_load inst)))
-
-;; Sinkable big-endian sload16 instruction.
-(decl sinkable_sload16 (Inst) Value)
-(extractor (sinkable_sload16 inst)
-           (sinkable_inst (and inst (sload16 (bigendian) _addr _offset))))
-
-;; Sinkable big-endian sload32 instruction.
-(decl sinkable_sload32 (Inst) Value)
-(extractor (sinkable_sload32 inst)
-           (sinkable_inst (and inst (sload32 (bigendian) _addr _offset))))
-
-;; Sinkable big-endian uload16 instruction.
-(decl sinkable_uload16 (Inst) Value)
-(extractor (sinkable_uload16 inst)
-           (sinkable_inst (and inst (uload16 (bigendian) _addr _offset))))
-
-;; Sinkable big-endian uload32 instruction.
-(decl sinkable_uload32 (Inst) Value)
-(extractor (sinkable_uload32 inst)
-           (sinkable_inst (and inst (uload32 (bigendian) _addr _offset))))
-
-;; Sink a load instruction, returning its address as `MemArg`.
-;; This is a side-effectful operation, see `sink_inst`.
-(decl sink_load (Inst) MemArg)
-(rule (sink_load inst @ (load flags addr offset))
-      (let ((_ Unit (sink_inst inst)))
-        (lower_address flags addr offset)))
-
-;; Sink a sload16 instruction, returning its address as `MemArg`.
-;; This is a side-effectful operation, see `sink_inst`.
-(decl sink_sload16 (Inst) MemArg)
-(rule (sink_sload16 inst @ (sload16 flags addr offset))
-      (let ((_ Unit (sink_inst inst)))
-        (lower_address flags addr offset)))
-
-;; Sink a sload32 instruction, returning its address as `MemArg`.
-;; This is a side-effectful operation, see `sink_inst`.
-(decl sink_sload32 (Inst) MemArg)
-(rule (sink_sload32 inst @ (sload32 flags addr offset))
-      (let ((_ Unit (sink_inst inst)))
-        (lower_address flags addr offset)))
-
-;; Sink a uload16 instruction, returning its address as `MemArg`.
-;; This is a side-effectful operation, see `sink_inst`.
-(decl sink_uload16 (Inst) MemArg)
-(rule (sink_uload16 inst @ (uload16 flags addr offset))
-      (let ((_ Unit (sink_inst inst)))
-        (lower_address flags addr offset)))
-
-;; Sink a uload32 instruction, returning its address as `MemArg`.
-;; This is a side-effectful operation, see `sink_inst`.
-(decl sink_uload32 (Inst) MemArg)
-(rule (sink_uload32 inst @ (uload32 flags addr offset))
-      (let ((_ Unit (sink_inst inst)))
-        (lower_address flags addr offset)))
-
-
-;; Helpers for register pairs ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; A writable register pair.
-(type WritableRegPair (enum (WritableRegPair (hi WritableReg) (lo WritableReg))))
-
-;; Allocate a writable register pair.
-;; FIXME: The pair is hard-coded as %r0/%r1 because regalloc cannot handle pairs.
-(decl temp_writable_regpair () WritableRegPair)
-(rule (temp_writable_regpair)
-      (WritableRegPair.WritableRegPair (writable_gpr 0) (writable_gpr 1)))
-
-;; Allocate a writable register pair and initialize it as a copy of the input.
-;; FIXME: Because there is only a single hard-coded regpair, the copy is a no-op.
-(decl copy_writable_regpair (RegPair) WritableRegPair)
-(rule (copy_writable_regpair _src) (temp_writable_regpair))
-
-;; Retrieve the high word of the writable register pair.
-(decl writable_regpair_hi (WritableRegPair) WritableReg)
-(rule (writable_regpair_hi (WritableRegPair.WritableRegPair hi _)) hi)
-
-;; Retrieve the low word of the writable register pair.
-(decl writable_regpair_lo (WritableRegPair) WritableReg)
-(rule (writable_regpair_lo (WritableRegPair.WritableRegPair _ lo)) lo)
-
-;; A (read-only) register pair.
-(type RegPair (enum (RegPair (hi Reg) (lo Reg))))
-
-;; Construct a register pair from a writable register pair.
-(decl writable_regpair_to_regpair (WritableRegPair) RegPair)
-(rule (writable_regpair_to_regpair (WritableRegPair.WritableRegPair hi lo))
-      (RegPair.RegPair hi lo))
-
-;; Uninitalized register pair that can be used for piecewise initialization.
-(decl uninitialized_regpair () RegPair)
-(rule (uninitialized_regpair)
-      (temp_writable_regpair))
-
-;; Retrieve the high word of the register pair.
-(decl regpair_hi (RegPair) Reg)
-(rule (regpair_hi (RegPair.RegPair hi _)) hi)
-
-;; Retrieve the low word of the register pair.
-(decl regpair_lo (RegPair) Reg)
-(rule (regpair_lo (RegPair.RegPair _ lo)) lo)
-
-
-;; Instruction creation helpers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Helper for emitting `MInst.AluRRR` instructions.
-(decl alu_rrr (Type ALUOp Reg Reg) Reg)
-(rule (alu_rrr ty op src1 src2)
-      (let ((dst WritableReg (temp_writable_reg ty))
-            (_ Unit (emit (MInst.AluRRR op dst src1 src2))))
-        dst))
-
-;; Helper for emitting `MInst.AluRRSImm16` instructions.
-(decl alu_rrsimm16 (Type ALUOp Reg i16) Reg)
-(rule (alu_rrsimm16 ty op src imm)
-      (let ((dst WritableReg (temp_writable_reg ty))
-            (_ Unit (emit (MInst.AluRRSImm16 op dst src imm))))
-        dst))
-
-;; Helper for emitting `MInst.AluRR` instructions.
-(decl alu_rr (Type ALUOp Reg Reg) Reg)
-(rule (alu_rr ty op src1 src2)
-      (let ((dst WritableReg (copy_writable_reg ty src1))
-            (_ Unit (emit (MInst.AluRR op dst src2))))
-        dst))
-
-;; Helper for emitting `MInst.AluRX` instructions.
-(decl alu_rx (Type ALUOp Reg MemArg) Reg)
-(rule (alu_rx ty op src mem)
-      (let ((dst WritableReg (copy_writable_reg ty src))
-            (_ Unit (emit (MInst.AluRX op dst mem))))
-        dst))
-
-;; Helper for emitting `MInst.AluRSImm16` instructions.
-(decl alu_rsimm16 (Type ALUOp Reg i16) Reg)
-(rule (alu_rsimm16 ty op src imm)
-      (let ((dst WritableReg (copy_writable_reg ty src))
-            (_ Unit (emit (MInst.AluRSImm16 op dst imm))))
-        dst))
-
-;; Helper for emitting `MInst.AluRSImm32` instructions.
-(decl alu_rsimm32 (Type ALUOp Reg i32) Reg)
-(rule (alu_rsimm32 ty op src imm)
-      (let ((dst WritableReg (copy_writable_reg ty src))
-            (_ Unit (emit (MInst.AluRSImm32 op dst imm))))
-        dst))
-
-;; Helper for emitting `MInst.AluRUImm32` instructions.
-(decl alu_ruimm32 (Type ALUOp Reg u32) Reg)
-(rule (alu_ruimm32 ty op src imm)
-      (let ((dst WritableReg (copy_writable_reg ty src))
-            (_ Unit (emit (MInst.AluRUImm32 op dst imm))))
-        dst))
-
-;; Helper for emitting `MInst.AluRUImm16Shifted` instructions.
-(decl alu_ruimm16shifted (Type ALUOp Reg UImm16Shifted) Reg)
-(rule (alu_ruimm16shifted ty op src imm)
-      (let ((dst WritableReg (copy_writable_reg ty src))
-            (_ Unit (emit (MInst.AluRUImm16Shifted op dst imm))))
-        dst))
-
-;; Helper for emitting `MInst.AluRUImm32Shifted` instructions.
-(decl alu_ruimm32shifted (Type ALUOp Reg UImm32Shifted) Reg)
-(rule (alu_ruimm32shifted ty op src imm)
-      (let ((dst WritableReg (copy_writable_reg ty src))
-            (_ Unit (emit (MInst.AluRUImm32Shifted op dst imm))))
-        dst))
-
-;; Helper for emitting `MInst.SMulWide` instructions.
-(decl smul_wide (Reg Reg) RegPair)
-(rule (smul_wide src1 src2)
-      (let ((dst WritableRegPair (temp_writable_regpair))
-            (_ Unit (emit (MInst.SMulWide src1 src2))))
-        dst))
-
-;; Helper for emitting `MInst.UMulWide` instructions.
-(decl umul_wide (Reg Reg) RegPair)
-(rule (umul_wide src1 src2)
-      (let ((dst WritableRegPair (temp_writable_regpair))
-            (_1 Unit (emit (MInst.Mov64 (writable_regpair_lo dst) src2)))
-            (_2 Unit (emit (MInst.UMulWide src1))))
-        dst))
-
-;; Helper for emitting `MInst.SDivMod32` instructions.
-(decl sdivmod32 (RegPair Reg) RegPair)
-(rule (sdivmod32 src1 src2)
-      (let ((dst WritableRegPair (copy_writable_regpair src1))
-            (_ Unit (emit (MInst.SDivMod32 src2))))
-        dst))
-
-;; Helper for emitting `MInst.SDivMod64` instructions.
-(decl sdivmod64 (RegPair Reg) RegPair)
-(rule (sdivmod64 src1 src2)
-      (let ((dst WritableRegPair (copy_writable_regpair src1))
-            (_ Unit (emit (MInst.SDivMod64 src2))))
-        dst))
-
-;; Helper for emitting `MInst.UDivMod32` instructions.
-(decl udivmod32 (RegPair Reg) RegPair)
-(rule (udivmod32 src1 src2)
-      (let ((dst WritableRegPair (copy_writable_regpair src1))
-            (_ Unit (emit (MInst.UDivMod32 src2))))
-        dst))
-
-;; Helper for emitting `MInst.UDivMod64` instructions.
-(decl udivmod64 (RegPair Reg) RegPair)
-(rule (udivmod64 src1 src2)
-      (let ((dst WritableRegPair (copy_writable_regpair src1))
-            (_ Unit (emit (MInst.UDivMod64 src2))))
-        dst))
-
-;; Helper for emitting `MInst.ShiftRR` instructions.
-(decl shift_rr (Type ShiftOp Reg u8 Reg) Reg)
-(rule (shift_rr ty op src shift_imm shift_reg)
-      (let ((dst WritableReg (temp_writable_reg ty))
-            (_ Unit (emit (MInst.ShiftRR op dst src shift_imm shift_reg))))
-        dst))
-
-;; Helper for emitting `MInst.RxSBGTest` instructions.
-(decl rxsbg_test (RxSBGOp Reg Reg u8 u8 i8) ProducesFlags)
-(rule (rxsbg_test op src1 src2 start_bit end_bit rotate_amt)
-      (ProducesFlags.ProducesFlagsSideEffect
-            (MInst.RxSBGTest op src1 src2 start_bit end_bit rotate_amt)))
-
-;; Helper for emitting `MInst.UnaryRR` instructions.
-(decl unary_rr (Type UnaryOp Reg) Reg)
-(rule (unary_rr ty op src)
-      (let ((dst WritableReg (temp_writable_reg ty))
-            (_ Unit (emit (MInst.UnaryRR op dst src))))
-        dst))
-
-;; Helper for emitting `MInst.CmpRR` instructions.
-(decl cmp_rr (CmpOp Reg Reg) ProducesFlags)
-(rule (cmp_rr op src1 src2)
-      (ProducesFlags.ProducesFlagsSideEffect (MInst.CmpRR op src1 src2)))
-
-;; Helper for emitting `MInst.CmpRX` instructions.
-(decl cmp_rx (CmpOp Reg MemArg) ProducesFlags)
-(rule (cmp_rx op src mem)
-      (ProducesFlags.ProducesFlagsSideEffect (MInst.CmpRX op src mem)))
-
-;; Helper for emitting `MInst.CmpRSImm16` instructions.
-(decl cmp_rsimm16 (CmpOp Reg i16) ProducesFlags)
-(rule (cmp_rsimm16 op src imm)
-      (ProducesFlags.ProducesFlagsSideEffect (MInst.CmpRSImm16 op src imm)))
-
-;; Helper for emitting `MInst.CmpRSImm32` instructions.
-(decl cmp_rsimm32 (CmpOp Reg i32) ProducesFlags)
-(rule (cmp_rsimm32 op src imm)
-      (ProducesFlags.ProducesFlagsSideEffect (MInst.CmpRSImm32 op src imm)))
-
-;; Helper for emitting `MInst.CmpRUImm32` instructions.
-(decl cmp_ruimm32 (CmpOp Reg u32) ProducesFlags)
-(rule (cmp_ruimm32 op src imm)
-      (ProducesFlags.ProducesFlagsSideEffect (MInst.CmpRUImm32 op src imm)))
-
-;; Helper for emitting `MInst.AtomicRmw` instructions.
-(decl atomic_rmw_impl (Type ALUOp Reg MemArg) Reg)
-(rule (atomic_rmw_impl ty op src mem)
-      (let ((dst WritableReg (temp_writable_reg ty))
-            (_ Unit (emit (MInst.AtomicRmw op dst src mem))))
-        dst))
-
-;; Helper for emitting `MInst.AtomicCas32` instructions.
-(decl atomic_cas32 (Reg Reg MemArg) Reg)
-(rule (atomic_cas32 src1 src2 mem)
-      (let ((dst WritableReg (copy_writable_reg $I32 src1))
-            (_ Unit (emit (MInst.AtomicCas32 dst src2 mem))))
-        dst))
-
-;; Helper for emitting `MInst.AtomicCas64` instructions.
-(decl atomic_cas64 (Reg Reg MemArg) Reg)
-(rule (atomic_cas64 src1 src2 mem)
-      (let ((dst WritableReg (copy_writable_reg $I64 src1))
-            (_ Unit (emit (MInst.AtomicCas64 dst src2 mem))))
-        dst))
-
-;; Helper for emitting `MInst.Fence` instructions.
-(decl fence_impl () SideEffectNoResult)
-(rule (fence_impl)
-      (SideEffectNoResult.Inst (MInst.Fence)))
-
-;; Helper for emitting `MInst.Load32` instructions.
-(decl load32 (MemArg) Reg)
-(rule (load32 addr)
-      (let ((dst WritableReg (temp_writable_reg $I32))
-            (_ Unit (emit (MInst.Load32 dst addr))))
-        dst))
-
-;; Helper for emitting `MInst.Load64` instructions.
-(decl load64 (MemArg) Reg)
-(rule (load64 addr)
-      (let ((dst WritableReg (temp_writable_reg $I64))
-            (_ Unit (emit (MInst.Load64 dst addr))))
-        dst))
-
-;; Helper for emitting `MInst.LoadRev16` instructions.
-(decl loadrev16 (MemArg) Reg)
-(rule (loadrev16 addr)
-      (let ((dst WritableReg (temp_writable_reg $I32))
-            (_ Unit (emit (MInst.LoadRev16 dst addr))))
-        dst))
-
-;; Helper for emitting `MInst.LoadRev32` instructions.
-(decl loadrev32 (MemArg) Reg)
-(rule (loadrev32 addr)
-      (let ((dst WritableReg (temp_writable_reg $I32))
-            (_ Unit (emit (MInst.LoadRev32 dst addr))))
-        dst))
-
-;; Helper for emitting `MInst.LoadRev64` instructions.
-(decl loadrev64 (MemArg) Reg)
-(rule (loadrev64 addr)
-      (let ((dst WritableReg (temp_writable_reg $I64))
-            (_ Unit (emit (MInst.LoadRev64 dst addr))))
-        dst))
-
-;; Helper for emitting `MInst.Store8` instructions.
-(decl store8 (Reg MemArg) SideEffectNoResult)
-(rule (store8 src addr)
-      (SideEffectNoResult.Inst (MInst.Store8 src addr)))
-
-;; Helper for emitting `MInst.Store16` instructions.
-(decl store16 (Reg MemArg) SideEffectNoResult)
-(rule (store16 src addr)
-      (SideEffectNoResult.Inst (MInst.Store16 src addr)))
-
-;; Helper for emitting `MInst.Store32` instructions.
-(decl store32 (Reg MemArg) SideEffectNoResult)
-(rule (store32 src addr)
-      (SideEffectNoResult.Inst (MInst.Store32 src addr)))
-
-;; Helper for emitting `MInst.Store64` instructions.
-(decl store64 (Reg MemArg) SideEffectNoResult)
-(rule (store64 src addr)
-      (SideEffectNoResult.Inst (MInst.Store64 src addr)))
-
-;; Helper for emitting `MInst.StoreImm8` instructions.
-(decl store8_imm (u8 MemArg) SideEffectNoResult)
-(rule (store8_imm imm addr)
-      (SideEffectNoResult.Inst (MInst.StoreImm8 imm addr)))
-
-;; Helper for emitting `MInst.StoreImm16` instructions.
-(decl store16_imm (i16 MemArg) SideEffectNoResult)
-(rule (store16_imm imm addr)
-      (SideEffectNoResult.Inst (MInst.StoreImm16 imm addr)))
-
-;; Helper for emitting `MInst.StoreImm32SExt16` instructions.
-(decl store32_simm16 (i16 MemArg) SideEffectNoResult)
-(rule (store32_simm16 imm addr)
-      (SideEffectNoResult.Inst (MInst.StoreImm32SExt16 imm addr)))
-
-;; Helper for emitting `MInst.StoreImm64SExt16` instructions.
-(decl store64_simm16 (i16 MemArg) SideEffectNoResult)
-(rule (store64_simm16 imm addr)
-      (SideEffectNoResult.Inst (MInst.StoreImm64SExt16 imm addr)))
-
-;; Helper for emitting `MInst.StoreRev16` instructions.
-(decl storerev16 (Reg MemArg) SideEffectNoResult)
-(rule (storerev16 src addr)
-      (SideEffectNoResult.Inst (MInst.StoreRev16 src addr)))
-
-;; Helper for emitting `MInst.StoreRev32` instructions.
-(decl storerev32 (Reg MemArg) SideEffectNoResult)
-(rule (storerev32 src addr)
-      (SideEffectNoResult.Inst (MInst.StoreRev32 src addr)))
-
-;; Helper for emitting `MInst.StoreRev64` instructions.
-(decl storerev64 (Reg MemArg) SideEffectNoResult)
-(rule (storerev64 src addr)
-      (SideEffectNoResult.Inst (MInst.StoreRev64 src addr)))
-
-;; Helper for emitting `MInst.FpuRR` instructions.
-(decl fpu_rr (Type FPUOp1 Reg) Reg)
-(rule (fpu_rr ty op src)
-      (let ((dst WritableReg (temp_writable_reg ty))
-            (_ Unit (emit (MInst.FpuRR op dst src))))
-        dst))
-
-;; Helper for emitting `MInst.FpuRRR` instructions.
-(decl fpu_rrr (Type FPUOp2 Reg Reg) Reg)
-(rule (fpu_rrr ty op src1 src2)
-      (let ((dst WritableReg (copy_writable_reg ty src1))
-            (_ Unit (emit (MInst.FpuRRR op dst src2))))
-        dst))
-
-;; Helper for emitting `MInst.FpuRRRR` instructions.
-(decl fpu_rrrr (Type FPUOp3 Reg Reg Reg) Reg)
-(rule (fpu_rrrr ty op src1 src2 src3)
-      (let ((dst WritableReg (copy_writable_reg ty src1))
-            (_ Unit (emit (MInst.FpuRRRR op dst src2 src3))))
-        dst))
-
-;; Helper for emitting `MInst.FpuCopysign` instructions.
-(decl fpu_copysign (Type Reg Reg) Reg)
-(rule (fpu_copysign ty src1 src2)
-      (let ((dst WritableReg (temp_writable_reg ty))
-            (_ Unit (emit (MInst.FpuCopysign dst src1 src2))))
-        dst))
-
-;; Helper for emitting `MInst.FpuCmp32` instructions.
-(decl fpu_cmp32 (Reg Reg) ProducesFlags)
-(rule (fpu_cmp32 src1 src2)
-      (ProducesFlags.ProducesFlagsSideEffect (MInst.FpuCmp32 src1 src2)))
-
-;; Helper for emitting `MInst.FpuCmp64` instructions.
-(decl fpu_cmp64 (Reg Reg) ProducesFlags)
-(rule (fpu_cmp64 src1 src2)
-      (ProducesFlags.ProducesFlagsSideEffect (MInst.FpuCmp64 src1 src2)))
-
-;; Helper for emitting `MInst.FpuToInt` instructions.
-(decl fpu_to_int (Type FpuToIntOp Reg) ProducesFlags)
-(rule (fpu_to_int ty op src)
-      (let ((dst WritableReg (temp_writable_reg ty)))
-        (ProducesFlags.ProducesFlagsReturnsReg (MInst.FpuToInt op dst src)
-                                               dst)))
-
-;; Helper for emitting `MInst.IntToFpu` instructions.
-(decl int_to_fpu (Type IntToFpuOp Reg) Reg)
-(rule (int_to_fpu ty op src)
-      (let ((dst WritableReg (temp_writable_reg ty))
-            (_ Unit (emit (MInst.IntToFpu op dst src))))
-        dst))
-
-;; Helper for emitting `MInst.FpuRound` instructions.
-(decl fpu_round (Type FpuRoundMode Reg) Reg)
-(rule (fpu_round ty mode src)
-      (let ((dst WritableReg (temp_writable_reg ty))
-            (_ Unit (emit (MInst.FpuRound mode dst src))))
-        dst))
-
-;; Helper for emitting `MInst.FpuVecRRR` instructions.
-(decl fpuvec_rrr (Type FPUOp2 Reg Reg) Reg)
-(rule (fpuvec_rrr ty op src1 src2)
-      (let ((dst WritableReg (temp_writable_reg ty))
-            (_ Unit (emit (MInst.FpuVecRRR op dst src1 src2))))
-        dst))
-
-;; Helper for emitting `MInst.MovToFpr` instructions.
-(decl mov_to_fpr (Reg) Reg)
-(rule (mov_to_fpr src)
-      (let ((dst WritableReg (temp_writable_reg $F64))
-            (_ Unit (emit (MInst.MovToFpr dst src))))
-        dst))
-
-;; Helper for emitting `MInst.MovFromFpr` instructions.
-(decl mov_from_fpr (Reg) Reg)
-(rule (mov_from_fpr src)
-      (let ((dst WritableReg (temp_writable_reg $I64))
-            (_ Unit (emit (MInst.MovFromFpr dst src))))
-        dst))
-
-;; Helper for emitting `MInst.FpuLoad32` instructions.
-(decl fpu_load32 (MemArg) Reg)
-(rule (fpu_load32 addr)
-      (let ((dst WritableReg (temp_writable_reg $F32))
-            (_ Unit (emit (MInst.FpuLoad32 dst addr))))
-        dst))
-
-;; Helper for emitting `MInst.FpuLoad64` instructions.
-(decl fpu_load64 (MemArg) Reg)
-(rule (fpu_load64 addr)
-      (let ((dst WritableReg (temp_writable_reg $F64))
-            (_ Unit (emit (MInst.FpuLoad64 dst addr))))
-        dst))
-
-;; Helper for emitting `MInst.FpuLoadRev32` instructions.
-(decl fpu_loadrev32 (MemArg) Reg)
-(rule (fpu_loadrev32 addr)
-      (let ((dst WritableReg (temp_writable_reg $F32))
-            (_ Unit (emit (MInst.FpuLoadRev32 dst addr))))
-        dst))
-
-;; Helper for emitting `MInst.FpuLoadRev64` instructions.
-(decl fpu_loadrev64 (MemArg) Reg)
-(rule (fpu_loadrev64 addr)
-      (let ((dst WritableReg (temp_writable_reg $F64))
-            (_ Unit (emit (MInst.FpuLoadRev64 dst addr))))
-        dst))
-
-;; Helper for emitting `MInst.FpuStore32` instructions.
-(decl fpu_store32 (Reg MemArg) SideEffectNoResult)
-(rule (fpu_store32 src addr)
-      (SideEffectNoResult.Inst (MInst.FpuStore32 src addr)))
-
-;; Helper for emitting `MInst.FpuStore64` instructions.
-(decl fpu_store64 (Reg MemArg) SideEffectNoResult)
-(rule (fpu_store64 src addr)
-      (SideEffectNoResult.Inst (MInst.FpuStore64 src addr)))
-
-;; Helper for emitting `MInst.FpuStoreRev32` instructions.
-(decl fpu_storerev32 (Reg MemArg) SideEffectNoResult)
-(rule (fpu_storerev32 src addr)
-      (SideEffectNoResult.Inst (MInst.FpuStoreRev32 src addr)))
-
-;; Helper for emitting `MInst.FpuStoreRev64` instructions.
-(decl fpu_storerev64 (Reg MemArg) SideEffectNoResult)
-(rule (fpu_storerev64 src addr)
-      (SideEffectNoResult.Inst (MInst.FpuStoreRev64 src addr)))
-
-;; Helper for emitting `MInst.LoadExtNameFar` instructions.
-(decl load_ext_name_far (ExternalName i64) Reg)
-(rule (load_ext_name_far name offset)
-      (let ((dst WritableReg (temp_writable_reg $I64))
-            (boxed_name BoxExternalName (box_external_name name))
-            (_ Unit (emit (MInst.LoadExtNameFar dst boxed_name offset))))
-        dst))
-
-;; Helper for emitting `MInst.LoadAddr` instructions.
-(decl load_addr (MemArg) Reg)
-(rule (load_addr mem)
-      (let ((dst WritableReg (temp_writable_reg $I64))
-            (_ Unit (emit (MInst.LoadAddr dst mem))))
-        dst))
-
-;; Helper for emitting `MInst.Jump` instructions.
-(decl jump_impl (MachLabel) SideEffectNoResult)
-(rule (jump_impl target)
-      (SideEffectNoResult.Inst (MInst.Jump target)))
-
-;; Helper for emitting `MInst.CondBr` instructions.
-(decl cond_br (MachLabel MachLabel Cond) SideEffectNoResult)
-(rule (cond_br taken not_taken cond)
-      (SideEffectNoResult.Inst (MInst.CondBr taken not_taken cond)))
-
-;; Helper for emitting `MInst.OneWayCondBr` instructions.
-(decl oneway_cond_br (MachLabel Cond) SideEffectNoResult)
-(rule (oneway_cond_br dest cond)
-      (SideEffectNoResult.Inst (MInst.OneWayCondBr dest cond)))
-
-;; Helper for emitting `MInst.JTSequence` instructions.
-(decl jt_sequence (Reg VecMachLabel) SideEffectNoResult)
-(rule (jt_sequence ridx targets)
-      (SideEffectNoResult.Inst (MInst.JTSequence ridx targets)))
-
-;; Emit a `ProducesFlags` instruction when the flags are not actually needed.
-(decl drop_flags (ProducesFlags) Reg)
-(rule (drop_flags (ProducesFlags.ProducesFlagsReturnsReg inst result))
-      (let ((_ Unit (emit inst)))
-        result))
-
-
-;; Helpers for instruction sequences ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Completed instruction sequence for use in MInst.Loop.
-(type VecMInst (primitive VecMInst))
-
-;; Partial (mutable) instruction sequence in the process of being created.
-(type VecMInstBuilder extern (enum))
-
-;; Create a new empty instruction sequence builder.
-(decl inst_builder_new () VecMInstBuilder)
-(extern constructor inst_builder_new inst_builder_new)
-
-;; Push an instruction to a sequence under construction.
-(decl inst_builder_push (VecMInstBuilder MInst) Unit)
-(extern constructor inst_builder_push inst_builder_push)
-
-;; Complete the sequence under construction.
-(decl inst_builder_finish (VecMInstBuilder) VecMInst)
-(extern constructor inst_builder_finish inst_builder_finish)
-
-;; It is not safe to write to virtual registers in the loop, so all destination
-;; registers must be real.  This must be handled by the user of these helpers,
-;; so we simply verify this constraint here.
-(decl real_reg (WritableReg) WritableReg)
-(extern extractor real_reg real_reg)
-
-;; Similarly, because we cannot allocate temp registers, if an instruction
-;; requires matching source and destination registers, this needs to be handled
-;; by the user.  Another helper to verify that constraint.
-(decl same_reg (WritableReg) Reg)
-(extern extractor same_reg same_reg (in))
-
-;; Push a `MInst.AluRRR` instruction to a sequence.
-(decl push_alu_reg (VecMInstBuilder ALUOp WritableReg Reg Reg) Reg)
-(rule (push_alu_reg ib op (real_reg dst) src1 src2)
-      (let ((_ Unit (inst_builder_push ib (MInst.AluRRR op dst src1 src2))))
-        dst))
-
-;; Push a `MInst.AluRUImm32Shifted` instruction to a sequence.
-(decl push_alu_uimm32shifted (VecMInstBuilder ALUOp WritableReg Reg UImm32Shifted) Reg)
-(rule (push_alu_uimm32shifted ib op (real_reg dst) (same_reg <dst) imm)
-      (let ((_ Unit (inst_builder_push ib (MInst.AluRUImm32Shifted op dst imm))))
-        dst))
-
-;; Push a `MInst.ShiftRR` instruction to a sequence.
-(decl push_shift (VecMInstBuilder ShiftOp WritableReg Reg u8 Reg) Reg)
-(rule (push_shift ib op (real_reg dst) src shift_imm shift_reg)
-      (let ((_ Unit (inst_builder_push ib
-                      (MInst.ShiftRR op dst src shift_imm shift_reg))))
-        dst))
-
-;; Push a `MInst.RxSBG` instruction to a sequence.
-(decl push_rxsbg (VecMInstBuilder RxSBGOp WritableReg Reg Reg u8 u8 i8) Reg)
-(rule (push_rxsbg ib op (real_reg dst) (same_reg <dst) src start_bit end_bit rotate_amt)
-      (let ((_ Unit (inst_builder_push ib
-                      (MInst.RxSBG op dst src start_bit end_bit rotate_amt))))
-        dst))
-
-;; Push a `MInst.UnaryRR` instruction to a sequence.
-(decl push_unary (VecMInstBuilder UnaryOp WritableReg Reg) Reg)
-(rule (push_unary ib op (real_reg dst) src)
-      (let ((_ Unit (inst_builder_push ib (MInst.UnaryRR op dst src))))
-        dst))
-
-;; Push a `MInst.AtomicCas32` instruction to a sequence.
-(decl push_atomic_cas32 (VecMInstBuilder WritableReg Reg MemArg) Reg)
-(rule (push_atomic_cas32 ib (real_reg dst_src1) src2 mem)
-      (let ((_ Unit (inst_builder_push ib (MInst.AtomicCas32 dst_src1 src2 mem))))
-        dst_src1))
-
-;; Push a `MInst.AtomicCas64` instruction to a sequence.
-(decl push_atomic_cas64 (VecMInstBuilder WritableReg Reg MemArg) Reg)
-(rule (push_atomic_cas64 ib (real_reg dst_src1) src2 mem)
-      (let ((_ Unit (inst_builder_push ib (MInst.AtomicCas64 dst_src1 src2 mem))))
-        dst_src1))
-
-;; Push instructions to break out of the loop if condition is met.
-(decl push_break_if (VecMInstBuilder ProducesFlags Cond) Reg)
-(rule (push_break_if ib (ProducesFlags.ProducesFlagsSideEffect inst) cond)
-      (let ((_1 Unit (inst_builder_push ib inst))
-            (_2 Unit (inst_builder_push ib (MInst.CondBreak cond))))
-        (invalid_reg)))
-
-;; Emit a `MInst.Loop` instruction holding a loop body instruction sequence.
-(decl emit_loop (VecMInstBuilder Cond) Unit)
-(rule (emit_loop ib cond)
-      (emit (MInst.Loop (inst_builder_finish ib) cond)))
-
-
-;; Helpers for generating register moves ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Move source register into destination.  (Non-SSA form.)
-(decl emit_mov (Type WritableReg Reg) Unit)
-
-(rule (emit_mov (gpr32_ty _ty) dst src)
-      (emit (MInst.Mov32 dst src)))
-
-(rule (emit_mov (gpr64_ty _ty) dst src)
-      (emit (MInst.Mov64 dst src)))
-
-(rule (emit_mov $F32 dst src)
-      (emit (MInst.FpuMove32 dst src)))
-
-(rule (emit_mov $F64 dst src)
-      (emit (MInst.FpuMove64 dst src)))
-
-;; Allocate a temporary (writable) register, initialized as a copy of the input.
-(decl copy_writable_reg (Type Reg) WritableReg)
-(rule (copy_writable_reg ty src)
-      (let ((dst WritableReg (temp_writable_reg ty))
-            (_ Unit (emit_mov ty dst src)))
-        dst))
-
-;; Likewise, but returning a Reg instead of a WritableReg.
-(decl copy_reg (Type Reg) Reg)
-(rule (copy_reg ty reg) (copy_writable_reg ty reg))
-
-;; Move from memory location into destination.
-(decl emit_load (Type WritableReg MemArg) Unit)
-(rule (emit_load $I32 dst addr)
-      (emit (MInst.Load32 dst addr)))
-(rule (emit_load $I64 dst addr)
-      (emit (MInst.Load64 dst addr)))
-
-
-;; Helpers for generating immediate values ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Move immediate value into destination register.  (Non-SSA form.)
-(decl emit_imm (Type WritableReg u64) Unit)
-
-;; 16-bit (or smaller) result type, any value
-(rule (emit_imm (fits_in_16 _ty) dst n)
-      (emit (MInst.Mov32SImm16 dst (u64_as_i16 n))))
-
-;; 32-bit result type, value fits in i16
-(rule (emit_imm (gpr32_ty _ty) dst (i16_from_u64 n))
-      (emit (MInst.Mov32SImm16 dst n)))
-
-;; 32-bit result type, any value
-(rule (emit_imm (gpr32_ty _ty) dst n)
-      (emit (MInst.Mov32Imm dst (u64_as_u32 n))))
-
-;; 64-bit result type, value fits in i16
-(rule (emit_imm (gpr64_ty _ty) dst (i16_from_u64 n))
-      (emit (MInst.Mov64SImm16 dst n)))
-
-;; 64-bit result type, value fits in i32
-(rule (emit_imm (gpr64_ty _ty) dst (i32_from_u64 n))
-      (emit (MInst.Mov64SImm32 dst n)))
-
-;; 64-bit result type, value fits in UImm16Shifted
-(rule (emit_imm (gpr64_ty _ty) dst (uimm16shifted_from_u64 n))
-      (emit (MInst.Mov64UImm16Shifted dst n)))
-
-;; 64-bit result type, value fits in UImm32Shifted
-(rule (emit_imm (gpr64_ty _ty) dst (uimm32shifted_from_u64 n))
-      (emit (MInst.Mov64UImm32Shifted dst n)))
-
-;; 64-bit result type, value with non-zero low-/high-parts.
-(rule (emit_imm (gpr64_ty ty) dst (and (u64_nonzero_hipart hi)
-                                       (u64_nonzero_lopart lo)))
-      (let ((_ Unit (emit_imm ty dst hi)))
-        (emit_insert_imm dst lo)))
-
-;; Insert immediate value into destination register.  (Non-SSA form.)
-(decl emit_insert_imm (WritableReg u64) Unit)
-
-;; Insertion, value fits in UImm16Shifted
-(rule (emit_insert_imm dst (uimm16shifted_from_u64 n))
-      (emit (MInst.Insert64UImm16Shifted dst n)))
-
-;; Insertion, value fits in UImm32Shifted
-(rule (emit_insert_imm dst (uimm32shifted_from_u64 n))
-      (emit (MInst.Insert64UImm32Shifted dst n)))
-
-;; 32-bit floating-point type, any value.  Loaded from literal pool.
-;; TODO: use LZER to load 0.0
-(rule (emit_imm $F32 dst n)
-      (emit (MInst.LoadFpuConst32 dst (u64_as_u32 n))))
-
-;; 64-bit floating-point type, any value.  Loaded from literal pool.
-;; TODO: use LZDR to load 0.0
-(rule (emit_imm $F64 dst n)
-      (emit (MInst.LoadFpuConst64 dst n)))
-
-;; Allocate a temporary register, initialized with an immediate.
-(decl imm (Type u64) Reg)
-(rule (imm ty n)
-      (let ((dst WritableReg (temp_writable_reg ty))
-            (_ Unit (emit_imm ty dst n)))
-        dst))
-
-;; Place an immediate into the low half of a register pair.
-;; The high half is taken from the input.
-(decl imm_regpair_lo (Type u64 RegPair) RegPair)
-(rule (imm_regpair_lo ty n regpair)
-      (let ((dst WritableRegPair (copy_writable_regpair regpair))
-            (_ Unit (emit_imm ty (writable_regpair_lo dst) n)))
-        dst))
-
-;; Place an immediate into the high half of a register pair.
-;; The low half is taken from the input.
-(decl imm_regpair_hi (Type u64 RegPair) RegPair)
-(rule (imm_regpair_hi ty n regpair)
-      (let ((dst WritableRegPair (copy_writable_regpair regpair))
-            (_ Unit (emit_imm ty (writable_regpair_hi dst) n)))
-        dst))
-
-
-;; Helpers for generating extensions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Result type of extending integer `Type` to 32 bits if smaller.
-(decl ty_ext32 (Type) Type)
-(rule (ty_ext32 $I8) $I32)
-(rule (ty_ext32 $I16) $I32)
-(rule (ty_ext32 $I32) $I32)
-(rule (ty_ext32 $I64) $I64)
-
-;; Result type of extending integer `Type` to 64 bits if smaller.
-(decl ty_ext64 (Type) Type)
-(rule (ty_ext64 $I8) $I64)
-(rule (ty_ext64 $I16) $I64)
-(rule (ty_ext64 $I32) $I64)
-(rule (ty_ext64 $I64) $I64)
-
-;; Zero-extend a register from a smaller `Type` into a 32-bit destination.  (Non-SSA form.)
-;; This handles both integer and boolean input types.
-(decl emit_zext32_reg (WritableReg Type Reg) Unit)
-(rule (emit_zext32_reg dst ty src)
-      (emit (MInst.Extend dst src $false (ty_bits ty) 32)))
-
-;; Sign-extend a register from a smaller `Type` into a 32-bit destination.  (Non-SSA form.)
-;; This handles both integer and boolean input types.
-(decl emit_sext32_reg (WritableReg Type Reg) Unit)
-(rule (emit_sext32_reg dst ty src)
-      (emit (MInst.Extend dst src $true (ty_bits ty) 32)))
-
-;; Zero-extend a register from a smaller `Type` into a 64-bit destination.  (Non-SSA form.)
-;; This handles both integer and boolean input types.
-(decl emit_zext64_reg (WritableReg Type Reg) Unit)
-(rule (emit_zext64_reg dst ty src)
-      (emit (MInst.Extend dst src $false (ty_bits ty) 64)))
-
-;; Sign-extend a register from a smaller `Type` into a 64-bit destination.  (Non-SSA form.)
-;; This handles both integer and boolean input types.
-(decl emit_sext64_reg (WritableReg Type Reg) Unit)
-(rule (emit_sext64_reg dst ty src)
-      (emit (MInst.Extend dst src $true (ty_bits ty) 64)))
-
-;; Zero-extend a register from a smaller `Type` into a 32-bit register.
-;; This handles both integer and boolean input types.
-(decl zext32_reg (Type Reg) Reg)
-(rule (zext32_reg ty src)
-      (let ((dst WritableReg (temp_writable_reg $I32))
-            (_ Unit (emit_zext32_reg dst ty src)))
-        dst))
-
-;; Sign-extend a register from a smaller `Type` into a 32-bit register.
-;; This handles both integer and boolean input types (except $B1).
-(decl sext32_reg (Type Reg) Reg)
-(rule (sext32_reg ty src)
-      (let ((dst WritableReg (temp_writable_reg $I32))
-            (_ Unit (emit_sext32_reg dst ty src)))
-        dst))
-
-;; Zero-extend a register from a smaller `Type` into a 64-bit register.
-;; This handles both integer and boolean input types (except $B1).
-(decl zext64_reg (Type Reg) Reg)
-(rule (zext64_reg ty src)
-      (let ((dst WritableReg (temp_writable_reg $I64))
-            (_ Unit (emit_zext64_reg dst ty src)))
-        dst))
-
-;; Sign-extend a register from a smaller `Type` into a 64-bit register.
-;; This handles both integer and boolean input types (except $B1).
-(decl sext64_reg (Type Reg) Reg)
-(rule (sext64_reg ty src)
-      (let ((dst WritableReg (temp_writable_reg $I64))
-            (_ Unit (emit_sext64_reg dst ty src)))
-        dst))
-
-
-;; Zero-extend memory from a smaller `Type` into a 32-bit destination.  (Non-SSA form.)
-(decl emit_zext32_mem (WritableReg Type MemArg) Unit)
-(rule (emit_zext32_mem dst $I8 mem) (emit (MInst.Load32ZExt8 dst mem)))
-(rule (emit_zext32_mem dst $I16 mem) (emit (MInst.Load32ZExt16 dst mem)))
-
-;; Sign-extend memory from a smaller `Type` into a 32-bit destination.  (Non-SSA form.)
-(decl emit_sext32_mem (WritableReg Type MemArg) Unit)
-(rule (emit_sext32_mem dst $I8 mem) (emit (MInst.Load32SExt8 dst mem)))
-(rule (emit_sext32_mem dst $I16 mem) (emit (MInst.Load32SExt16 dst mem)))
-
-;; Zero-extend memory from a smaller `Type` into a 64-bit destination.  (Non-SSA form.)
-(decl emit_zext64_mem (WritableReg Type MemArg) Unit)
-(rule (emit_zext64_mem dst $I8 mem) (emit (MInst.Load64ZExt8 dst mem)))
-(rule (emit_zext64_mem dst $I16 mem) (emit (MInst.Load64ZExt16 dst mem)))
-(rule (emit_zext64_mem dst $I32 mem) (emit (MInst.Load64ZExt32 dst mem)))
-
-;; Sign-extend memory from a smaller `Type` into a 64-bit destination.  (Non-SSA form.)
-(decl emit_sext64_mem (WritableReg Type MemArg) Unit)
-(rule (emit_sext64_mem dst $I8 mem) (emit (MInst.Load64SExt8 dst mem)))
-(rule (emit_sext64_mem dst $I16 mem) (emit (MInst.Load64SExt16 dst mem)))
-(rule (emit_sext64_mem dst $I32 mem) (emit (MInst.Load64SExt32 dst mem)))
-
-;; Zero-extend memory from a smaller `Type` into a 32-bit register.
-(decl zext32_mem (Type MemArg) Reg)
-(rule (zext32_mem ty mem)
-      (let ((dst WritableReg (temp_writable_reg $I32))
-            (_ Unit (emit_zext32_mem dst ty mem)))
-        dst))
-
-;; Sign-extend memory from a smaller `Type` into a 32-bit register.
-(decl sext32_mem (Type MemArg) Reg)
-(rule (sext32_mem ty mem)
-      (let ((dst WritableReg (temp_writable_reg $I32))
-            (_ Unit (emit_sext32_mem dst ty mem)))
-        dst))
-
-;; Zero-extend memory from a smaller `Type` into a 64-bit register.
-(decl zext64_mem (Type MemArg) Reg)
-(rule (zext64_mem ty mem)
-      (let ((dst WritableReg (temp_writable_reg $I64))
-            (_ Unit (emit_zext64_mem dst ty mem)))
-        dst))
-
-;; Sign-extend memory from a smaller `Type` into a 64-bit register.
-(decl sext64_mem (Type MemArg) Reg)
-(rule (sext64_mem ty mem)
-      (let ((dst WritableReg (temp_writable_reg $I64))
-            (_ Unit (emit_sext64_mem dst ty mem)))
-        dst))
-
-
-;; Place `Value` into destination, zero-extending to 32 bits if smaller.  (Non-SSA form.)
-(decl emit_put_in_reg_zext32 (WritableReg Value) Unit)
-(rule (emit_put_in_reg_zext32 dst (and (value_type ty) (u64_from_value val)))
-      (emit_imm (ty_ext32 ty) dst val))
-(rule (emit_put_in_reg_zext32 dst (and (value_type (fits_in_16 ty)) (sinkable_load load)))
-      (emit_zext32_mem dst ty (sink_load load)))
-(rule (emit_put_in_reg_zext32 dst val @ (value_type (fits_in_16 ty)))
-      (emit_zext32_reg dst ty (put_in_reg val)))
-(rule (emit_put_in_reg_zext32 dst val @ (value_type (ty_32_or_64 ty)))
-      (emit_mov ty dst (put_in_reg val)))
-
-;; Place `Value` into destination, sign-extending to 32 bits if smaller.  (Non-SSA form.)
-(decl emit_put_in_reg_sext32 (WritableReg Value) Unit)
-(rule (emit_put_in_reg_sext32 dst (and (value_type ty) (u64_from_signed_value val)))
-      (emit_imm (ty_ext32 ty) dst val))
-(rule (emit_put_in_reg_sext32 dst (and (value_type (fits_in_16 ty)) (sinkable_load load)))
-      (emit_sext32_mem dst ty (sink_load load)))
-(rule (emit_put_in_reg_sext32 dst val @ (value_type (fits_in_16 ty)))
-      (emit_sext32_reg dst ty (put_in_reg val)))
-(rule (emit_put_in_reg_sext32 dst val @ (value_type (ty_32_or_64 ty)))
-      (emit_mov ty dst (put_in_reg val)))
-
-;; Place `Value` into destination, zero-extending to 64 bits if smaller.  (Non-SSA form.)
-(decl emit_put_in_reg_zext64 (WritableReg Value) Unit)
-(rule (emit_put_in_reg_zext64 dst (and (value_type ty) (u64_from_value val)))
-      (emit_imm (ty_ext64 ty) dst val))
-(rule (emit_put_in_reg_zext64 dst (and (value_type (gpr32_ty ty)) (sinkable_load load)))
-      (emit_zext64_mem dst ty (sink_load load)))
-(rule (emit_put_in_reg_zext64 dst val @ (value_type (gpr32_ty ty)))
-      (emit_zext64_reg dst ty (put_in_reg val)))
-(rule (emit_put_in_reg_zext64 dst val @ (value_type (gpr64_ty ty)))
-      (emit_mov ty dst (put_in_reg val)))
-
-;; Place `Value` into destination, sign-extending to 64 bits if smaller.  (Non-SSA form.)
-(decl emit_put_in_reg_sext64 (WritableReg Value) Unit)
-(rule (emit_put_in_reg_sext64 dst (and (value_type ty) (u64_from_signed_value val)))
-      (emit_imm (ty_ext64 ty) dst val))
-(rule (emit_put_in_reg_sext64 dst (and (value_type (gpr32_ty ty)) (sinkable_load load)))
-      (emit_sext64_mem dst ty (sink_load load)))
-(rule (emit_put_in_reg_sext64 dst val @ (value_type (gpr32_ty ty)))
-      (emit_sext64_reg dst ty (put_in_reg val)))
-(rule (emit_put_in_reg_sext64 dst val @ (value_type (gpr64_ty ty)))
-      (emit_mov ty dst (put_in_reg val)))
-
-;; Place `Value` into a register, zero-extending to 32 bits if smaller.
-(decl put_in_reg_zext32 (Value) Reg)
-(rule (put_in_reg_zext32 (and (value_type ty) (u64_from_value val)))
-      (imm (ty_ext32 ty) val))
-(rule (put_in_reg_zext32 (and (value_type (fits_in_16 ty)) (sinkable_load load)))
-      (zext32_mem ty (sink_load load)))
-(rule (put_in_reg_zext32 val @ (value_type (fits_in_16 ty)))
-      (zext32_reg ty (put_in_reg val)))
-(rule (put_in_reg_zext32 val @ (value_type (ty_32_or_64 _ty)))
-      (put_in_reg val))
-
-;; Place `Value` into a register, sign-extending to 32 bits if smaller.
-(decl put_in_reg_sext32 (Value) Reg)
-(rule (put_in_reg_sext32 (and (value_type ty) (u64_from_signed_value val)))
-      (imm (ty_ext32 ty) val))
-(rule (put_in_reg_sext32 (and (value_type (fits_in_16 ty)) (sinkable_load load)))
-      (sext32_mem ty (sink_load load)))
-(rule (put_in_reg_sext32 val @ (value_type (fits_in_16 ty)))
-      (sext32_reg ty (put_in_reg val)))
-(rule (put_in_reg_sext32 val @ (value_type (ty_32_or_64 _ty)))
-      (put_in_reg val))
-
-;; Place `Value` into a register, zero-extending to 64 bits if smaller.
-(decl put_in_reg_zext64 (Value) Reg)
-(rule (put_in_reg_zext64 (and (value_type ty) (u64_from_value val)))
-      (imm (ty_ext64 ty) val))
-(rule (put_in_reg_zext64 (and (value_type (gpr32_ty ty)) (sinkable_load load)))
-      (zext64_mem ty (sink_load load)))
-(rule (put_in_reg_zext64 val @ (value_type (gpr32_ty ty)))
-      (zext64_reg ty (put_in_reg val)))
-(rule (put_in_reg_zext64 val @ (value_type (gpr64_ty ty)))
-      (put_in_reg val))
-
-;; Place `Value` into a register, sign-extending to 64 bits if smaller.
-(decl put_in_reg_sext64 (Value) Reg)
-(rule (put_in_reg_sext64 (and (value_type ty) (u64_from_signed_value val)))
-      (imm (ty_ext64 ty) val))
-(rule (put_in_reg_sext64 (and (value_type (gpr32_ty ty)) (sinkable_load load)))
-      (sext64_mem ty (sink_load load)))
-(rule (put_in_reg_sext64 val @ (value_type (gpr32_ty ty)))
-      (sext64_reg ty (put_in_reg val)))
-(rule (put_in_reg_sext64 val @ (value_type (gpr64_ty ty)))
-      (put_in_reg val))
-
-;; Place `Value` into the low half of a register pair, zero-extending
-;; to 32 bits if smaller.  The high half is taken from the input.
-(decl put_in_regpair_lo_zext32 (Value RegPair) RegPair)
-(rule (put_in_regpair_lo_zext32 val regpair)
-      (let ((dst WritableRegPair (copy_writable_regpair regpair))
-            (_ Unit (emit_put_in_reg_zext32 (writable_regpair_lo dst) val)))
-        dst))
-
-;; Place `Value` into the low half of a register pair, sign-extending
-;; to 32 bits if smaller.  The high half is taken from the input.
-(decl put_in_regpair_lo_sext32 (Value RegPair) RegPair)
-(rule (put_in_regpair_lo_sext32 val regpair)
-      (let ((dst WritableRegPair (copy_writable_regpair regpair))
-            (_ Unit (emit_put_in_reg_sext32 (writable_regpair_lo dst) val)))
-        dst))
-
-;; Place `Value` into the low half of a register pair, zero-extending
-;; to 64 bits if smaller.  The high half is taken from the input.
-(decl put_in_regpair_lo_zext64 (Value RegPair) RegPair)
-(rule (put_in_regpair_lo_zext64 val regpair)
-      (let ((dst WritableRegPair (copy_writable_regpair regpair))
-            (_ Unit (emit_put_in_reg_zext64 (writable_regpair_lo dst) val)))
-        dst))
-
-;; Place `Value` into the low half of a register pair, sign-extending
-;; to 64 bits if smaller.  The high half is taken from the input.
-(decl put_in_regpair_lo_sext64 (Value RegPair) RegPair)
-(rule (put_in_regpair_lo_sext64 val regpair)
-      (let ((dst WritableRegPair (copy_writable_regpair regpair))
-            (_ Unit (emit_put_in_reg_sext64 (writable_regpair_lo dst) val)))
-        dst))
-
-
-;; Helpers for generating conditional moves ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Conditionally move immediate value into destination register.  (Non-SSA form.)
-(decl emit_cmov_imm (Type WritableReg Cond i16) ConsumesFlags)
-(rule (emit_cmov_imm (gpr32_ty _ty) dst cond imm)
-      (ConsumesFlags.ConsumesFlagsReturnsReg (MInst.CMov32SImm16 dst cond imm)
-                                             dst))
-(rule (emit_cmov_imm (gpr64_ty _ty) dst cond imm)
-      (ConsumesFlags.ConsumesFlagsReturnsReg (MInst.CMov64SImm16 dst cond imm)
-                                             dst))
-
-;; Conditionally select between immediate and source register.
-(decl cmov_imm (Type Cond i16 Reg) ConsumesFlags)
-(rule (cmov_imm ty cond imm src)
-      (let ((dst WritableReg (copy_writable_reg ty src)))
-        (emit_cmov_imm ty dst cond imm)))
-
-;; Conditionally modify the low word of a register pair.
-;; This cannot be ConsumesFlags since the return value is not a register.
-(decl cmov_imm_regpair_lo (Type ProducesFlags Cond i16 RegPair) RegPair)
-(rule (cmov_imm_regpair_lo ty producer cond imm src)
-      (let ((dst WritableRegPair (copy_writable_regpair src))
-            (consumer ConsumesFlags (emit_cmov_imm ty (writable_regpair_lo dst) cond imm))
-            (_ Reg (with_flags_reg producer consumer)))
-        dst))
-
-;; Conditionally modify the high word of a register pair.
-;; This cannot be ConsumesFlags since the return value is not a register.
-(decl cmov_imm_regpair_hi (Type ProducesFlags Cond i16 RegPair) RegPair)
-(rule (cmov_imm_regpair_hi ty producer cond imm src)
-      (let ((dst WritableRegPair (copy_writable_regpair src))
-            (consumer ConsumesFlags (emit_cmov_imm ty (writable_regpair_hi dst) cond imm))
-            (_ Reg (with_flags_reg producer consumer)))
-        dst))
-
-;; Conditionally select between two source registers.  (Non-SSA form.)
-(decl emit_cmov_reg (Type WritableReg Cond Reg) ConsumesFlags)
-(rule (emit_cmov_reg (gpr32_ty _ty) dst cond src)
-      (ConsumesFlags.ConsumesFlagsReturnsReg (MInst.CMov32 dst cond src)
-                                             dst))
-(rule (emit_cmov_reg (gpr64_ty _ty) dst cond src)
-      (ConsumesFlags.ConsumesFlagsReturnsReg (MInst.CMov64 dst cond src)
-                                             dst))
-(rule (emit_cmov_reg $F32 dst cond src)
-      (ConsumesFlags.ConsumesFlagsReturnsReg (MInst.FpuCMov32 dst cond src)
-                                             dst))
-(rule (emit_cmov_reg $F64 dst cond src)
-      (ConsumesFlags.ConsumesFlagsReturnsReg (MInst.FpuCMov64 dst cond src)
-                                             dst))
-
-;; Conditionally select between two source registers.
-(decl cmov_reg (Type Cond Reg Reg) ConsumesFlags)
-(rule (cmov_reg ty cond src1 src2)
-      (let ((dst WritableReg (copy_writable_reg ty src2)))
-        (emit_cmov_reg ty dst cond src1)))
-
-
-;; Helpers for generating conditional traps ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl trap_if (ProducesFlags Cond TrapCode) Reg)
-(rule (trap_if (ProducesFlags.ProducesFlagsReturnsReg inst result) cond trap_code)
-      (let ((_1 Unit (emit inst))
-            (_2 Unit (emit (MInst.TrapIf cond trap_code))))
-        result))
-(rule (trap_if (ProducesFlags.ProducesFlagsSideEffect inst) cond trap_code)
-      (let ((_1 Unit (emit inst))
-            (_2 Unit (emit (MInst.TrapIf cond trap_code))))
-        (invalid_reg)))
-
-(decl icmps_reg_and_trap (Type Reg Reg Cond TrapCode) Reg)
-(rule (icmps_reg_and_trap ty src1 src2 cond trap_code)
-      (let ((_ Unit (emit (MInst.CmpTrapRR (cmpop_cmps ty)
-                                           src1 src2 cond trap_code))))
-        (invalid_reg)))
-
-(decl icmps_simm16_and_trap (Type Reg i16 Cond TrapCode) Reg)
-(rule (icmps_simm16_and_trap ty src imm cond trap_code)
-      (let ((_ Unit (emit (MInst.CmpTrapRSImm16 (cmpop_cmps ty)
-                                                src imm cond trap_code))))
-        (invalid_reg)))
-
-(decl icmpu_reg_and_trap (Type Reg Reg Cond TrapCode) Reg)
-(rule (icmpu_reg_and_trap ty src1 src2 cond trap_code)
-      (let ((_ Unit (emit (MInst.CmpTrapRR (cmpop_cmpu ty)
-                                           src1 src2 cond trap_code))))
-        (invalid_reg)))
-
-(decl icmpu_uimm16_and_trap (Type Reg u16 Cond TrapCode) Reg)
-(rule (icmpu_uimm16_and_trap ty src imm cond trap_code)
-      (let ((_ Unit (emit (MInst.CmpTrapRUImm16 (cmpop_cmpu ty)
-                                                src imm cond trap_code))))
-        (invalid_reg)))
-
-(decl trap_impl (TrapCode) SideEffectNoResult)
-(rule (trap_impl trap_code)
-      (SideEffectNoResult.Inst (MInst.Trap trap_code)))
-
-(decl trap_if_impl (Cond TrapCode) SideEffectNoResult)
-(rule (trap_if_impl cond trap_code)
-      (SideEffectNoResult.Inst (MInst.TrapIf cond trap_code)))
-
-(decl debugtrap_impl () SideEffectNoResult)
-(rule (debugtrap_impl)
-      (SideEffectNoResult.Inst (MInst.Debugtrap)))
-
-
-;; Helpers for handling boolean conditions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Capture a flags-producing instruction together with a condition code mask
-;; that tells how to interpret the resulting condition code.  The result can
-;; be used to represent a boolean condition.
-(type ProducesBool (enum (ProducesBool (producer ProducesFlags) (cond Cond))))
-(decl bool (ProducesFlags Cond) ProducesBool)
-(rule (bool producer cond) (ProducesBool.ProducesBool producer cond))
-
-;; Invert boolean condition.
-(decl invert_bool (ProducesBool) ProducesBool)
-(rule (invert_bool (ProducesBool.ProducesBool producer cond))
-      (bool producer (invert_cond cond)))
-
-;; Helpers to emit a `ProducesFlags` or `ConsumesFlags` instruction directly.
-;; We use this in `select_bool_reg` and `select_bool_imm` below instead of
-;; using the `with_flags` mechanism so that we can insert another unrelated
-;; instruction in between the producer and consumer.  (This use is only valid
-;; if that unrelated instruction does not modify the condition code.)
-(decl emit_producer (ProducesFlags) Unit)
-(rule (emit_producer (ProducesFlags.ProducesFlagsSideEffect insn)) (emit insn))
-(decl emit_consumer (ConsumesFlags) Unit)
-(rule (emit_consumer (ConsumesFlags.ConsumesFlagsReturnsReg insn _)) (emit insn))
-
-;; Use a boolean condition to select between two registers.
-(decl select_bool_reg (Type ProducesBool Reg Reg) Reg)
-(rule (select_bool_reg ty (ProducesBool.ProducesBool producer cond) reg_true reg_false)
-      (let ((dst WritableReg (temp_writable_reg ty))
-            (_1 Unit (emit_producer producer))
-            (_2 Unit (emit_mov ty dst reg_false))
-            (_3 Unit (emit_consumer (emit_cmov_reg ty dst cond reg_true))))
-        dst))
-
-;; Use a boolean condition to select between two immediate values.
-(decl select_bool_imm (Type ProducesBool i16 u64) Reg)
-(rule (select_bool_imm ty (ProducesBool.ProducesBool producer cond) imm_true imm_false)
-      (let ((dst WritableReg (temp_writable_reg ty))
-            (_1 Unit (emit_producer producer))
-            (_2 Unit (emit_imm ty dst imm_false))
-            (_3 Unit (emit_consumer (emit_cmov_imm ty dst cond imm_true))))
-        dst))
-
-;; Lower a boolean condition to a boolean type.  The value used to represent
-;; "true" is -1 for all result types except for $B1, which uses 1.
-(decl lower_bool (Type ProducesBool) Reg)
-(rule (lower_bool $B1 cond) (select_bool_imm $B1 cond 1 0))
-(rule (lower_bool $B8 cond) (select_bool_imm $B8 cond -1 0))
-(rule (lower_bool $B16 cond) (select_bool_imm $B16 cond -1 0))
-(rule (lower_bool $B32 cond) (select_bool_imm $B32 cond -1 0))
-(rule (lower_bool $B64 cond) (select_bool_imm $B64 cond -1 0))
-
-;; Emit a conditional branch based on a boolean condition.
-(decl cond_br_bool (ProducesBool MachLabel MachLabel) SideEffectNoResult)
-(rule (cond_br_bool (ProducesBool.ProducesBool producer cond) taken not_taken)
-      (let ((_ Unit (emit_producer producer)))
-        (cond_br taken not_taken cond)))
-
-;; Emit a one-way conditional branch based on a boolean condition.
-(decl oneway_cond_br_bool (ProducesBool MachLabel) SideEffectNoResult)
-(rule (oneway_cond_br_bool (ProducesBool.ProducesBool producer cond) dest)
-      (let ((_ Unit (emit_producer producer)))
-        (oneway_cond_br dest cond)))
-
-;; Emit a conditional trap based on a boolean condition.
-(decl trap_if_bool (ProducesBool TrapCode) SideEffectNoResult)
-(rule (trap_if_bool (ProducesBool.ProducesBool producer cond) trap_code)
-      (let ((_ Unit (emit_producer producer)))
-        (trap_if_impl cond trap_code)))
-
-
-;;;; Helpers for compare-and-swap loops ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; We use the emit_loop functionality to create compare-and-swap loops.
-;; As noted there, code inside a loop emitted via emit_loop cannot write
-;; to any virtual register, only hard registers.  We use the two reserved
-;; registers %r0 and %r1 in compare-and-swap loops.
-
-;; %r0 always holds the value currently loaded from the memory location.
-(decl casloop_val_reg () WritableReg)
-(rule (casloop_val_reg) (writable_gpr 0))
-
-;; %r1 is available to compute the new value to be written.
-(decl casloop_tmp_reg () WritableReg)
-(rule (casloop_tmp_reg) (writable_gpr 1))
-
-;; This takes a loop body for a compare-and-swap loop, completes it by
-;; adding the actual compare-and-swap instruction, and emits the initial
-;; memory load followed by the loop itself.  "val" is the new value to
-;; be written if the memory location still holds the old value in %r0.
-;; The result should be passed to "casloop_result" or (in the case of
-;; subword loops) to "casloop_rotate_result".
-(decl casloop_emit (VecMInstBuilder Type MemFlags Reg Reg) Reg)
-(rule (casloop_emit ib ty flags aligned_addr val)
-      (let (;; Construct a memory argument for the aligned word.
-            (aligned_mem MemArg (memarg_reg_plus_off aligned_addr 0 flags))
-            ;; Add the compare-and-swap instruction to the builder.
-            (result Reg (push_atomic_cas ib (ty_ext32 ty)
-                          (casloop_val_reg) val aligned_mem))
-            ;; Emit initial load followed by compare-and-swap loop.
-            (_1 Unit (emit_load (ty_ext32 ty) (casloop_val_reg) aligned_mem))
-            (_2 Unit (emit_loop ib (intcc_as_cond (IntCC.NotEqual)))))
-        result))
-
-;; Compute the previous memory value after a (fullword) compare-and-swap loop.
-;; In the big-endian case, the value is already correct, but may need to be
-;; copied out of the hard register.  In the little-endian case, we need to
-;; byte-swap since the compare-and-swap instruction is always big-endian.
-(decl casloop_result (Type MemFlags Reg) Reg)
-(rule (casloop_result (ty_32_or_64 ty) (bigendian) result)
-      (copy_reg ty result))
-(rule (casloop_result (ty_32_or_64 ty) (littleendian) result)
-      (bswap_reg ty result))
-
-;; Emit a fullword compare-and-swap loop, returning the previous memory value.
-(decl casloop (VecMInstBuilder Type MemFlags Reg Reg) Reg)
-(rule (casloop ib ty flags aligned_addr val)
-      (casloop_result ty flags (casloop_emit ib ty flags aligned_addr val)))
-
-;; For types smaller than $I32, we have no native compare-and-swap
-;; instruction, so we need to perform the compare-and-swap loop on the
-;; surrounding aligned word.  To actually operate on the target $I8 or
-;; $I16 data, that aligned word then needs to be rotated by an amount
-;; determined by the low address bits.
-
-;; Determine the rotate amount to bring the target data into a position
-;; in the high bytes of the enclosing $I32.  Since the compare-and-swap
-;; instruction performs a big-endian memory access, this can be done by
-;; rotating (left) by "(addr & 3) * 8" bits, or "(addr << 3) & 31" bits.
-;; We can omit the "& 31" since this is implicit with a 32-bit rotate.
-(decl casloop_bitshift (Reg) Reg)
-(rule (casloop_bitshift addr)
-      (lshl_imm $I32 addr 3))
-
-;; The address of the surrounding 32-bit word, by masking off low bits.
-(decl casloop_aligned_addr (Reg) Reg)
-(rule (casloop_aligned_addr addr)
-      (and_uimm16shifted $I64 addr (uimm16shifted 0xfffc 0)))
-
-;; Push an instruction sequence to rotate a value loaded from memory
-;; to the well-defined location: the high bytes in case of a big-endian
-;; memory operation, and the low bytes in the little-endian case.
-;; (This is somewhat arbitary but chosen to allow the most efficient
-;; sequences to compute the various atomic operations.)
-;; Note that $I8 accesses always use the big-endian case.
-(decl casloop_rotate_in (VecMInstBuilder Type MemFlags Reg Reg) Reg)
-(rule (casloop_rotate_in ib $I8 _ bitshift val)
-      (push_rot_imm_reg ib $I32 (casloop_tmp_reg) val 0 bitshift))
-(rule (casloop_rotate_in ib $I16 (bigendian) bitshift val)
-      (push_rot_imm_reg ib $I32 (casloop_tmp_reg) val 0 bitshift))
-(rule (casloop_rotate_in ib $I16 (littleendian) bitshift val)
-      (push_rot_imm_reg ib $I32 (casloop_tmp_reg) val 16 bitshift))
-
-;; The inverse operation: rotate values back to the original memory order.
-;; This can be done by simply using the negated shift count.  As an extra
-;; optimization, we note that in the $I16 case the shift count can only
-;; take the values 0 or 16, both of which negate to themselves (mod 32),
-;; so the explicit negation operation can be omitted here.
-(decl casloop_rotate_out (VecMInstBuilder Type MemFlags Reg Reg) Reg)
-(rule (casloop_rotate_out ib $I8 _ bitshift val)
-      (push_rot_imm_reg ib $I32 (casloop_tmp_reg) val 0 (neg_reg $I32 bitshift)))
-(rule (casloop_rotate_out ib $I16 (bigendian) bitshift val)
-      (push_rot_imm_reg ib $I32 (casloop_tmp_reg) val 0 bitshift))
-(rule (casloop_rotate_out ib $I16 (littleendian) bitshift val)
-      (push_rot_imm_reg ib $I32 (casloop_tmp_reg) val 16 bitshift))
-
-;; Compute the previous memory value after a subword compare-and-swap loop.
-;; This is similar to casloop_rotate_in, but brings the value to the *low*
-;; bytes.  This can be achieved simply by adding the type size to the rotate
-;; amount, which can be done within the same instruction.  In the little-
-;; endian case, we also need to byte-swap the result.  Since we only have
-;; a 32-bit byte-swap instruction, we load the value to the high bytes in
-;; this case before performing the 32-bit byte-swap.
-(decl casloop_rotate_result (Type MemFlags Reg Reg) Reg)
-(rule (casloop_rotate_result $I8 _ bitshift result)
-      (rot_imm_reg $I32 result 8 bitshift))
-(rule (casloop_rotate_result $I16 (bigendian) bitshift result)
-      (rot_imm_reg $I32 result 16 bitshift))
-(rule (casloop_rotate_result $I16 (littleendian) bitshift result)
-      (bswap_reg $I32 (rot_reg $I32 result bitshift)))
-
-;; Emit a subword compare-and-swap loop, returning the previous memory value.
-(decl casloop_subword (VecMInstBuilder Type MemFlags Reg Reg Reg) Reg)
-(rule (casloop_subword ib ty flags aligned_addr bitshift val)
-      (casloop_rotate_result ty flags bitshift
-        (casloop_emit ib ty flags aligned_addr val)))
-
-
-;; Helpers for generating `clz` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Count leading zeroes.  For a zero input, return the specified value.
-(decl clz_reg (i16 Reg) RegPair)
-
-;; The flogr instruction returns 64 for zero input by default.
-(rule (clz_reg 64 x)
-      (let ((dst WritableRegPair (temp_writable_regpair))
-            (_ Unit (emit (MInst.Flogr x))))
-        dst))
-
-;; If another zero return value was requested, we need to override the flogr
-;; result.  This cannot use any of the normal flags mechanisms because we need
-;; to use both result and condition code output of flogr as input to the
-;; conditional move, and because flogr returns a register pair.
-(rule (clz_reg zeroval x)
-      (let ((dst WritableRegPair (temp_writable_regpair))
-            (_1 Unit (emit (MInst.Flogr x)))
-            (_2 Unit (emit (MInst.CMov64SImm16 (writable_regpair_hi dst)
-                              (intcc_as_cond (IntCC.Equal)) zeroval))))
-        dst))
-
-
-;; Helpers for generating `add` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl aluop_add (Type) ALUOp)
-(rule (aluop_add $I8) (ALUOp.Add32))
-(rule (aluop_add $I16) (ALUOp.Add32))
-(rule (aluop_add $I32) (ALUOp.Add32))
-(rule (aluop_add $I64) (ALUOp.Add64))
-
-(decl aluop_add_sext16 (Type) ALUOp)
-(rule (aluop_add_sext16 $I16) (ALUOp.Add32Ext16))
-(rule (aluop_add_sext16 $I32) (ALUOp.Add32Ext16))
-(rule (aluop_add_sext16 $I64) (ALUOp.Add64Ext16))
-
-(decl aluop_add_sext32 (Type) ALUOp)
-(rule (aluop_add_sext32 $I64) (ALUOp.Add64Ext32))
-
-(decl add_reg (Type Reg Reg) Reg)
-(rule (add_reg ty x y) (alu_rrr ty (aluop_add ty) x y))
-
-(decl add_reg_sext32 (Type Reg Reg) Reg)
-(rule (add_reg_sext32 ty x y) (alu_rr ty (aluop_add_sext32 ty) x y))
-
-(decl add_simm16 (Type Reg i16) Reg)
-(rule (add_simm16 ty x y) (alu_rrsimm16 ty (aluop_add ty) x y))
-
-(decl add_simm32 (Type Reg i32) Reg)
-(rule (add_simm32 ty x y) (alu_rsimm32 ty (aluop_add ty) x y))
-
-(decl add_mem (Type Reg MemArg) Reg)
-(rule (add_mem ty x y) (alu_rx ty (aluop_add ty) x y))
-
-(decl add_mem_sext16 (Type Reg MemArg) Reg)
-(rule (add_mem_sext16 ty x y) (alu_rx ty (aluop_add_sext16 ty) x y))
-
-(decl add_mem_sext32 (Type Reg MemArg) Reg)
-(rule (add_mem_sext32 ty x y) (alu_rx ty (aluop_add_sext32 ty) x y))
-
-
-;; Helpers for generating `add_logical` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl aluop_add_logical (Type) ALUOp)
-(rule (aluop_add_logical $I32) (ALUOp.AddLogical32))
-(rule (aluop_add_logical $I64) (ALUOp.AddLogical64))
-
-(decl aluop_add_logical_zext32 (Type) ALUOp)
-(rule (aluop_add_logical_zext32 $I64) (ALUOp.AddLogical64Ext32))
-
-(decl add_logical_reg (Type Reg Reg) Reg)
-(rule (add_logical_reg ty x y) (alu_rrr ty (aluop_add_logical ty) x y))
-
-(decl add_logical_reg_zext32 (Type Reg Reg) Reg)
-(rule (add_logical_reg_zext32 ty x y) (alu_rr ty (aluop_add_logical_zext32 ty) x y))
-
-(decl add_logical_zimm32 (Type Reg u32) Reg)
-(rule (add_logical_zimm32 ty x y) (alu_ruimm32 ty (aluop_add_logical ty) x y))
-
-(decl add_logical_mem (Type Reg MemArg) Reg)
-(rule (add_logical_mem ty x y) (alu_rx ty (aluop_add_logical ty) x y))
-
-(decl add_logical_mem_zext32 (Type Reg MemArg) Reg)
-(rule (add_logical_mem_zext32 ty x y) (alu_rx ty (aluop_add_logical_zext32 ty) x y))
-
-
-;; Helpers for generating `sub` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl aluop_sub (Type) ALUOp)
-(rule (aluop_sub $I8) (ALUOp.Sub32))
-(rule (aluop_sub $I16) (ALUOp.Sub32))
-(rule (aluop_sub $I32) (ALUOp.Sub32))
-(rule (aluop_sub $I64) (ALUOp.Sub64))
-
-(decl aluop_sub_sext16 (Type) ALUOp)
-(rule (aluop_sub_sext16 $I16) (ALUOp.Sub32Ext16))
-(rule (aluop_sub_sext16 $I32) (ALUOp.Sub32Ext16))
-(rule (aluop_sub_sext16 $I64) (ALUOp.Sub64Ext16))
-
-(decl aluop_sub_sext32 (Type) ALUOp)
-(rule (aluop_sub_sext32 $I64) (ALUOp.Sub64Ext32))
-
-(decl sub_reg (Type Reg Reg) Reg)
-(rule (sub_reg ty x y) (alu_rrr ty (aluop_sub ty) x y))
-
-(decl sub_reg_sext32 (Type Reg Reg) Reg)
-(rule (sub_reg_sext32 ty x y) (alu_rr ty (aluop_sub_sext32 ty) x y))
-
-(decl sub_mem (Type Reg MemArg) Reg)
-(rule (sub_mem ty x y) (alu_rx ty (aluop_sub ty) x y))
-
-(decl sub_mem_sext16 (Type Reg MemArg) Reg)
-(rule (sub_mem_sext16 ty x y) (alu_rx ty (aluop_sub_sext16 ty) x y))
-
-(decl sub_mem_sext32 (Type Reg MemArg) Reg)
-(rule (sub_mem_sext32 ty x y) (alu_rx ty (aluop_sub_sext32 ty) x y))
-
-
-;; Helpers for generating `sub_logical` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl aluop_sub_logical (Type) ALUOp)
-(rule (aluop_sub_logical $I32) (ALUOp.SubLogical32))
-(rule (aluop_sub_logical $I64) (ALUOp.SubLogical64))
-
-(decl aluop_sub_logical_zext32 (Type) ALUOp)
-(rule (aluop_sub_logical_zext32 $I64) (ALUOp.SubLogical64Ext32))
-
-(decl sub_logical_reg (Type Reg Reg) Reg)
-(rule (sub_logical_reg ty x y) (alu_rrr ty (aluop_sub_logical ty) x y))
-
-(decl sub_logical_reg_zext32 (Type Reg Reg) Reg)
-(rule (sub_logical_reg_zext32 ty x y) (alu_rr ty (aluop_sub_logical_zext32 ty) x y))
-
-(decl sub_logical_zimm32 (Type Reg u32) Reg)
-(rule (sub_logical_zimm32 ty x y) (alu_ruimm32 ty (aluop_sub_logical ty) x y))
-
-(decl sub_logical_mem (Type Reg MemArg) Reg)
-(rule (sub_logical_mem ty x y) (alu_rx ty (aluop_sub_logical ty) x y))
-
-(decl sub_logical_mem_zext32 (Type Reg MemArg) Reg)
-(rule (sub_logical_mem_zext32 ty x y) (alu_rx ty (aluop_sub_logical ty) x y))
-
-
-;; Helpers for generating `mul` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl aluop_mul (Type) ALUOp)
-(rule (aluop_mul $I8) (ALUOp.Mul32))
-(rule (aluop_mul $I16) (ALUOp.Mul32))
-(rule (aluop_mul $I32) (ALUOp.Mul32))
-(rule (aluop_mul $I64) (ALUOp.Mul64))
-
-(decl aluop_mul_sext16 (Type) ALUOp)
-(rule (aluop_mul_sext16 $I16) (ALUOp.Mul32Ext16))
-(rule (aluop_mul_sext16 $I32) (ALUOp.Mul32Ext16))
-(rule (aluop_mul_sext16 $I64) (ALUOp.Mul64Ext16))
-
-(decl aluop_mul_sext32 (Type) ALUOp)
-(rule (aluop_mul_sext32 $I64) (ALUOp.Mul64Ext32))
-
-(decl mul_reg (Type Reg Reg) Reg)
-(rule (mul_reg ty x y) (alu_rrr ty (aluop_mul ty) x y))
-
-(decl mul_reg_sext32 (Type Reg Reg) Reg)
-(rule (mul_reg_sext32 ty x y) (alu_rr ty (aluop_mul_sext32 ty) x y))
-
-(decl mul_simm16 (Type Reg i16) Reg)
-(rule (mul_simm16 ty x y) (alu_rsimm16 ty (aluop_mul ty) x y))
-
-(decl mul_simm32 (Type Reg i32) Reg)
-(rule (mul_simm32 ty x y) (alu_rsimm32 ty (aluop_mul ty) x y))
-
-(decl mul_mem (Type Reg MemArg) Reg)
-(rule (mul_mem ty x y) (alu_rx ty (aluop_mul ty) x y))
-
-(decl mul_mem_sext16 (Type Reg MemArg) Reg)
-(rule (mul_mem_sext16 ty x y) (alu_rx ty (aluop_mul_sext16 ty) x y))
-
-(decl mul_mem_sext32 (Type Reg MemArg) Reg)
-(rule (mul_mem_sext32 ty x y) (alu_rx ty (aluop_mul_sext32 ty) x y))
-
-
-;; Helpers for generating `udivmod` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl udivmod (Type RegPair Reg) RegPair)
-(rule (udivmod $I32 x y) (udivmod32 x y))
-(rule (udivmod $I64 x y) (udivmod64 x y))
-
-
-;; Helpers for generating `sdivmod` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl sdivmod (Type RegPair Reg) RegPair)
-(rule (sdivmod $I32 x y) (sdivmod32 x y))
-(rule (sdivmod $I64 x y) (sdivmod64 x y))
-
-
-;; Helpers for generating `and` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl aluop_and (Type) ALUOp)
-(rule (aluop_and (gpr32_ty _ty)) (ALUOp.And32))
-(rule (aluop_and (gpr64_ty _ty)) (ALUOp.And64))
-
-(decl and_reg (Type Reg Reg) Reg)
-(rule (and_reg ty x y) (alu_rrr ty (aluop_and ty) x y))
-
-(decl and_uimm16shifted (Type Reg UImm16Shifted) Reg)
-(rule (and_uimm16shifted ty x y) (alu_ruimm16shifted ty (aluop_and ty) x y))
-
-(decl and_uimm32shifted (Type Reg UImm32Shifted) Reg)
-(rule (and_uimm32shifted ty x y) (alu_ruimm32shifted ty (aluop_and ty) x y))
-
-(decl and_mem (Type Reg MemArg) Reg)
-(rule (and_mem ty x y) (alu_rx ty (aluop_and ty) x y))
-
-
-;; Helpers for generating `or` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl aluop_or (Type) ALUOp)
-(rule (aluop_or (gpr32_ty _ty)) (ALUOp.Orr32))
-(rule (aluop_or (gpr64_ty _ty)) (ALUOp.Orr64))
-
-(decl or_reg (Type Reg Reg) Reg)
-(rule (or_reg ty x y) (alu_rrr ty (aluop_or ty) x y))
-
-(decl or_uimm16shifted (Type Reg UImm16Shifted) Reg)
-(rule (or_uimm16shifted ty x y) (alu_ruimm16shifted ty (aluop_or ty) x y))
-
-(decl or_uimm32shifted (Type Reg UImm32Shifted) Reg)
-(rule (or_uimm32shifted ty x y) (alu_ruimm32shifted ty (aluop_or ty) x y))
-
-(decl or_mem (Type Reg MemArg) Reg)
-(rule (or_mem ty x y) (alu_rx ty (aluop_or ty) x y))
-
-
-;; Helpers for generating `xor` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl aluop_xor (Type) ALUOp)
-(rule (aluop_xor (gpr32_ty _ty)) (ALUOp.Xor32))
-(rule (aluop_xor (gpr64_ty _ty)) (ALUOp.Xor64))
-
-(decl xor_reg (Type Reg Reg) Reg)
-(rule (xor_reg ty x y) (alu_rrr ty (aluop_xor ty) x y))
-
-(decl xor_uimm32shifted (Type Reg UImm32Shifted) Reg)
-(rule (xor_uimm32shifted ty x y) (alu_ruimm32shifted ty (aluop_xor ty) x y))
-
-(decl xor_mem (Type Reg MemArg) Reg)
-(rule (xor_mem ty x y) (alu_rx ty (aluop_xor ty) x y))
-
-(decl push_xor_uimm32shifted (VecMInstBuilder Type WritableReg Reg UImm32Shifted) Reg)
-(rule (push_xor_uimm32shifted ib ty dst src imm)
-      (push_alu_uimm32shifted ib (aluop_xor ty) dst src imm))
-
-;; Helpers for generating `not` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl not_reg (Type Reg) Reg)
-(rule (not_reg (gpr32_ty ty) x)
-      (xor_uimm32shifted ty x (uimm32shifted 0xffffffff 0)))
-(rule (not_reg (gpr64_ty ty) x)
-      (xor_uimm32shifted ty
-        (xor_uimm32shifted ty x (uimm32shifted 0xffffffff 0))
-        (uimm32shifted 0xffffffff 32)))
-
-(decl push_not_reg (VecMInstBuilder Type WritableReg Reg) Reg)
-(rule (push_not_reg ib (gpr32_ty ty) dst src)
-      (push_xor_uimm32shifted ib ty dst src (uimm32shifted 0xffffffff 0)))
-(rule (push_not_reg ib (gpr64_ty ty) dst src)
-      (let ((val Reg (push_xor_uimm32shifted ib ty dst src (uimm32shifted 0xffffffff 0))))
-        (push_xor_uimm32shifted ib ty dst val (uimm32shifted 0xffffffff 32))))
-
-
-;; Helpers for generating `and_not` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl aluop_and_not (Type) ALUOp)
-(rule (aluop_and_not (gpr32_ty _ty)) (ALUOp.AndNot32))
-(rule (aluop_and_not (gpr64_ty _ty)) (ALUOp.AndNot64))
-
-(decl and_not_reg (Type Reg Reg) Reg)
-(rule (and_not_reg ty x y) (alu_rrr ty (aluop_and_not ty) x y))
-
-
-;; Helpers for generating `or_not` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl aluop_or_not (Type) ALUOp)
-(rule (aluop_or_not (gpr32_ty _ty)) (ALUOp.OrrNot32))
-(rule (aluop_or_not (gpr64_ty _ty)) (ALUOp.OrrNot64))
-
-(decl or_not_reg (Type Reg Reg) Reg)
-(rule (or_not_reg ty x y) (alu_rrr ty (aluop_or_not ty) x y))
-
-
-;; Helpers for generating `xor_not` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl aluop_xor_not (Type) ALUOp)
-(rule (aluop_xor_not (gpr32_ty _ty)) (ALUOp.XorNot32))
-(rule (aluop_xor_not (gpr64_ty _ty)) (ALUOp.XorNot64))
-
-(decl xor_not_reg (Type Reg Reg) Reg)
-(rule (xor_not_reg ty x y) (alu_rrr ty (aluop_xor_not ty) x y))
-
-
-;; Helpers for generating `abs` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl unaryop_abs (Type) UnaryOp)
-(rule (unaryop_abs $I32) (UnaryOp.Abs32))
-(rule (unaryop_abs $I64) (UnaryOp.Abs64))
-
-(decl unaryop_abs_sext32 (Type) UnaryOp)
-(rule (unaryop_abs_sext32 $I64) (UnaryOp.Abs64Ext32))
-
-(decl abs_reg (Type Reg) Reg)
-(rule (abs_reg ty x) (unary_rr ty (unaryop_abs ty) x))
-
-(decl abs_reg_sext32 (Type Reg) Reg)
-(rule (abs_reg_sext32 ty x) (unary_rr ty (unaryop_abs_sext32 ty) x))
-
-
-;; Helpers for generating `neg` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl unaryop_neg (Type) UnaryOp)
-(rule (unaryop_neg $I8) (UnaryOp.Neg32))
-(rule (unaryop_neg $I16) (UnaryOp.Neg32))
-(rule (unaryop_neg $I32) (UnaryOp.Neg32))
-(rule (unaryop_neg $I64) (UnaryOp.Neg64))
-
-(decl unaryop_neg_sext32 (Type) UnaryOp)
-(rule (unaryop_neg_sext32 $I64) (UnaryOp.Neg64Ext32))
-
-(decl neg_reg (Type Reg) Reg)
-(rule (neg_reg ty x) (unary_rr ty (unaryop_neg ty) x))
-
-(decl neg_reg_sext32 (Type Reg) Reg)
-(rule (neg_reg_sext32 ty x) (unary_rr ty (unaryop_neg_sext32 ty) x))
-
-
-;; Helpers for generating `bswap` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl unaryop_bswap (Type) UnaryOp)
-(rule (unaryop_bswap $I32) (UnaryOp.BSwap32))
-(rule (unaryop_bswap $I64) (UnaryOp.BSwap64))
-
-(decl bswap_reg (Type Reg) Reg)
-(rule (bswap_reg ty x) (unary_rr ty (unaryop_bswap ty) x))
-
-(decl push_bswap_reg (VecMInstBuilder Type WritableReg Reg) Reg)
-(rule (push_bswap_reg ib ty dst src) (push_unary ib (unaryop_bswap ty) dst src))
-
-
-;; Helpers for generating `rot` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl shiftop_rot (Type) ShiftOp)
-(rule (shiftop_rot $I32) (ShiftOp.RotL32))
-(rule (shiftop_rot $I64) (ShiftOp.RotL64))
-
-(decl rot_reg (Type Reg Reg) Reg)
-(rule (rot_reg ty x shift_reg)
-      (shift_rr ty (shiftop_rot ty) x 0 shift_reg))
-
-(decl rot_imm (Type Reg u8) Reg)
-(rule (rot_imm ty x shift_imm)
-      (shift_rr ty (shiftop_rot ty) x shift_imm (zero_reg)))
-
-(decl rot_imm_reg (Type Reg u8 Reg) Reg)
-(rule (rot_imm_reg ty x shift_imm shift_reg)
-      (shift_rr ty (shiftop_rot ty) x shift_imm shift_reg))
-
-(decl push_rot_imm_reg (VecMInstBuilder Type WritableReg Reg u8 Reg) Reg)
-(rule (push_rot_imm_reg ib ty dst src shift_imm shift_reg)
-      (push_shift ib (shiftop_rot ty) dst src shift_imm shift_reg))
-
-
-;; Helpers for generating `lshl` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl shiftop_lshl (Type) ShiftOp)
-(rule (shiftop_lshl $I8) (ShiftOp.LShL32))
-(rule (shiftop_lshl $I16) (ShiftOp.LShL32))
-(rule (shiftop_lshl $I32) (ShiftOp.LShL32))
-(rule (shiftop_lshl $I64) (ShiftOp.LShL64))
-
-(decl lshl_reg (Type Reg Reg) Reg)
-(rule (lshl_reg ty x shift_reg)
-      (shift_rr ty (shiftop_lshl ty) x 0 shift_reg))
-
-(decl lshl_imm (Type Reg u8) Reg)
-(rule (lshl_imm ty x shift_imm)
-      (shift_rr ty (shiftop_lshl ty) x shift_imm (zero_reg)))
-
-
-;; Helpers for generating `lshr` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl shiftop_lshr (Type) ShiftOp)
-(rule (shiftop_lshr $I32) (ShiftOp.LShR32))
-(rule (shiftop_lshr $I64) (ShiftOp.LShR64))
-
-(decl lshr_reg (Type Reg Reg) Reg)
-(rule (lshr_reg ty x shift_reg)
-      (shift_rr ty (shiftop_lshr ty) x 0 shift_reg))
-
-(decl lshr_imm (Type Reg u8) Reg)
-(rule (lshr_imm ty x shift_imm)
-      (shift_rr ty (shiftop_lshr ty) x shift_imm (zero_reg)))
-
-
-;; Helpers for generating `ashr` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl shiftop_ashr (Type) ShiftOp)
-(rule (shiftop_ashr $I32) (ShiftOp.AShR32))
-(rule (shiftop_ashr $I64) (ShiftOp.AShR64))
-
-(decl ashr_reg (Type Reg Reg) Reg)
-(rule (ashr_reg ty x shift_reg)
-      (shift_rr ty (shiftop_ashr ty) x 0 shift_reg))
-
-(decl ashr_imm (Type Reg u8) Reg)
-(rule (ashr_imm ty x shift_imm)
-      (shift_rr ty (shiftop_ashr ty) x shift_imm (zero_reg)))
-
-
-;; Helpers for generating `popcnt` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl popcnt_byte (Reg) Reg)
-(rule (popcnt_byte x) (unary_rr $I64 (UnaryOp.PopcntByte) x))
-
-(decl popcnt_reg (Reg) Reg)
-(rule (popcnt_reg x) (unary_rr $I64 (UnaryOp.PopcntReg) x))
-
-
-;; Helpers for generating `atomic_rmw` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl atomic_rmw_and (Type Reg MemArg) Reg)
-(rule (atomic_rmw_and $I32 src mem) (atomic_rmw_impl $I32 (ALUOp.And32) src mem))
-(rule (atomic_rmw_and $I64 src mem) (atomic_rmw_impl $I64 (ALUOp.And64) src mem))
-
-(decl atomic_rmw_or (Type Reg MemArg) Reg)
-(rule (atomic_rmw_or $I32 src mem) (atomic_rmw_impl $I32 (ALUOp.Orr32) src mem))
-(rule (atomic_rmw_or $I64 src mem) (atomic_rmw_impl $I64 (ALUOp.Orr64) src mem))
-
-(decl atomic_rmw_xor (Type Reg MemArg) Reg)
-(rule (atomic_rmw_xor $I32 src mem) (atomic_rmw_impl $I32 (ALUOp.Xor32) src mem))
-(rule (atomic_rmw_xor $I64 src mem) (atomic_rmw_impl $I64 (ALUOp.Xor64) src mem))
-
-(decl atomic_rmw_add (Type Reg MemArg) Reg)
-(rule (atomic_rmw_add $I32 src mem) (atomic_rmw_impl $I32 (ALUOp.Add32) src mem))
-(rule (atomic_rmw_add $I64 src mem) (atomic_rmw_impl $I64 (ALUOp.Add64) src mem))
-
-
-;; Helpers for generating `atomic_cas` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl atomic_cas_impl (Type Reg Reg MemArg) Reg)
-(rule (atomic_cas_impl $I32 src1 src2 mem) (atomic_cas32 src1 src2 mem))
-(rule (atomic_cas_impl $I64 src1 src2 mem) (atomic_cas64 src1 src2 mem))
-
-(decl push_atomic_cas (VecMInstBuilder Type WritableReg Reg MemArg) Reg)
-(rule (push_atomic_cas ib $I32 src1 src2 mem) (push_atomic_cas32 ib src1 src2 mem))
-(rule (push_atomic_cas ib $I64 src1 src2 mem) (push_atomic_cas64 ib src1 src2 mem))
-
-
-;; Helpers for generating `fadd` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl fpuop2_add (Type) FPUOp2)
-(rule (fpuop2_add $F32) (FPUOp2.Add32))
-(rule (fpuop2_add $F64) (FPUOp2.Add64))
-
-(decl fadd_reg (Type Reg Reg) Reg)
-(rule (fadd_reg ty x y) (fpu_rrr ty (fpuop2_add ty) x y))
-
-
-;; Helpers for generating `fsub` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl fpuop2_sub (Type) FPUOp2)
-(rule (fpuop2_sub $F32) (FPUOp2.Sub32))
-(rule (fpuop2_sub $F64) (FPUOp2.Sub64))
-
-(decl fsub_reg (Type Reg Reg) Reg)
-(rule (fsub_reg ty x y) (fpu_rrr ty (fpuop2_sub ty) x y))
-
-
-;; Helpers for generating `fmul` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl fpuop2_mul (Type) FPUOp2)
-(rule (fpuop2_mul $F32) (FPUOp2.Mul32))
-(rule (fpuop2_mul $F64) (FPUOp2.Mul64))
-
-(decl fmul_reg (Type Reg Reg) Reg)
-(rule (fmul_reg ty x y) (fpu_rrr ty (fpuop2_mul ty) x y))
-
-
-;; Helpers for generating `fdiv` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl fpuop2_div (Type) FPUOp2)
-(rule (fpuop2_div $F32) (FPUOp2.Div32))
-(rule (fpuop2_div $F64) (FPUOp2.Div64))
-
-(decl fdiv_reg (Type Reg Reg) Reg)
-(rule (fdiv_reg ty x y) (fpu_rrr ty (fpuop2_div ty) x y))
-
-
-;; Helpers for generating `fmin` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl fpuop2_min (Type) FPUOp2)
-(rule (fpuop2_min $F32) (FPUOp2.Min32))
-(rule (fpuop2_min $F64) (FPUOp2.Min64))
-
-(decl fmin_reg (Type Reg Reg) Reg)
-(rule (fmin_reg ty x y) (fpuvec_rrr ty (fpuop2_min ty) x y))
-
-
-;; Helpers for generating `fmax` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl fpuop2_max (Type) FPUOp2)
-(rule (fpuop2_max $F32) (FPUOp2.Max32))
-(rule (fpuop2_max $F64) (FPUOp2.Max64))
-
-(decl fmax_reg (Type Reg Reg) Reg)
-(rule (fmax_reg ty x y) (fpuvec_rrr ty (fpuop2_max ty) x y))
-
-
-;; Helpers for generating `fma` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl fpuop3_fma (Type) FPUOp3)
-(rule (fpuop3_fma $F32) (FPUOp3.MAdd32))
-(rule (fpuop3_fma $F64) (FPUOp3.MAdd64))
-
-(decl fma_reg (Type Reg Reg Reg) Reg)
-(rule (fma_reg ty x y acc) (fpu_rrrr ty (fpuop3_fma ty) acc x y))
-
-
-;; Helpers for generating `sqrt` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl fpuop1_sqrt (Type) FPUOp1)
-(rule (fpuop1_sqrt $F32) (FPUOp1.Sqrt32))
-(rule (fpuop1_sqrt $F64) (FPUOp1.Sqrt64))
-
-(decl sqrt_reg (Type Reg) Reg)
-(rule (sqrt_reg ty x) (fpu_rr ty (fpuop1_sqrt ty) x))
-
-
-;; Helpers for generating `fneg` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl fpuop1_neg (Type) FPUOp1)
-(rule (fpuop1_neg $F32) (FPUOp1.Neg32))
-(rule (fpuop1_neg $F64) (FPUOp1.Neg64))
-
-(decl fneg_reg (Type Reg) Reg)
-(rule (fneg_reg ty x) (fpu_rr ty (fpuop1_neg ty) x))
-
-
-;; Helpers for generating `fabs` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl fpuop1_abs (Type) FPUOp1)
-(rule (fpuop1_abs $F32) (FPUOp1.Abs32))
-(rule (fpuop1_abs $F64) (FPUOp1.Abs64))
-
-(decl fabs_reg (Type Reg) Reg)
-(rule (fabs_reg ty x) (fpu_rr ty (fpuop1_abs ty) x))
-
-
-;; Helpers for generating `ceil` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl fpuroundmode_ceil (Type) FpuRoundMode)
-(rule (fpuroundmode_ceil $F32) (FpuRoundMode.Plus32))
-(rule (fpuroundmode_ceil $F64) (FpuRoundMode.Plus64))
-
-(decl ceil_reg (Type Reg) Reg)
-(rule (ceil_reg ty x) (fpu_round ty (fpuroundmode_ceil ty) x))
-
-
-;; Helpers for generating `floor` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl fpuroundmode_floor (Type) FpuRoundMode)
-(rule (fpuroundmode_floor $F32) (FpuRoundMode.Minus32))
-(rule (fpuroundmode_floor $F64) (FpuRoundMode.Minus64))
-
-(decl floor_reg (Type Reg) Reg)
-(rule (floor_reg ty x) (fpu_round ty (fpuroundmode_floor ty) x))
-
-
-;; Helpers for generating `trunc` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl fpuroundmode_trunc (Type) FpuRoundMode)
-(rule (fpuroundmode_trunc $F32) (FpuRoundMode.Zero32))
-(rule (fpuroundmode_trunc $F64) (FpuRoundMode.Zero64))
-
-(decl trunc_reg (Type Reg) Reg)
-(rule (trunc_reg ty x) (fpu_round ty (fpuroundmode_trunc ty) x))
-
-
-;; Helpers for generating `nearest` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl fpuroundmode_nearest (Type) FpuRoundMode)
-(rule (fpuroundmode_nearest $F32) (FpuRoundMode.Nearest32))
-(rule (fpuroundmode_nearest $F64) (FpuRoundMode.Nearest64))
-
-(decl nearest_reg (Type Reg) Reg)
-(rule (nearest_reg ty x) (fpu_round ty (fpuroundmode_nearest ty) x))
-
-
-;; Helpers for generating `fpromote` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl fpuop1_promote (Type Type) FPUOp1)
-(rule (fpuop1_promote $F64 $F32) (FPUOp1.Cvt32To64))
-
-(decl fpromote_reg (Type Type Reg) Reg)
-(rule (fpromote_reg dst_ty src_ty x)
-      (fpu_rr dst_ty (fpuop1_promote dst_ty src_ty) x))
-
-
-;; Helpers for generating `fdemote` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl fpuop1_demote (Type Type) FPUOp1)
-(rule (fpuop1_demote $F32 $F64) (FPUOp1.Cvt64To32))
-
-(decl fdemote_reg (Type Type Reg) Reg)
-(rule (fdemote_reg dst_ty src_ty x)
-      (fpu_rr dst_ty (fpuop1_demote dst_ty src_ty) x))
-
-
-;; Helpers for generating `fcvt_from_uint` instructions ;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl uint_to_fpu_op (Type Type) IntToFpuOp)
-(rule (uint_to_fpu_op $F32 $I32) (IntToFpuOp.U32ToF32))
-(rule (uint_to_fpu_op $F64 $I32) (IntToFpuOp.U32ToF64))
-(rule (uint_to_fpu_op $F32 $I64) (IntToFpuOp.U64ToF32))
-(rule (uint_to_fpu_op $F64 $I64) (IntToFpuOp.U64ToF64))
-
-(decl fcvt_from_uint_reg (Type Type Reg) Reg)
-(rule (fcvt_from_uint_reg dst_ty src_ty x)
-      (int_to_fpu dst_ty (uint_to_fpu_op dst_ty src_ty) x))
-
-
-;; Helpers for generating `fcvt_from_sint` instructions ;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl sint_to_fpu_op (Type Type) IntToFpuOp)
-(rule (sint_to_fpu_op $F32 $I32) (IntToFpuOp.I32ToF32))
-(rule (sint_to_fpu_op $F64 $I32) (IntToFpuOp.I32ToF64))
-(rule (sint_to_fpu_op $F32 $I64) (IntToFpuOp.I64ToF32))
-(rule (sint_to_fpu_op $F64 $I64) (IntToFpuOp.I64ToF64))
-
-(decl fcvt_from_sint_reg (Type Type Reg) Reg)
-(rule (fcvt_from_sint_reg dst_ty src_ty x)
-      (int_to_fpu dst_ty (sint_to_fpu_op dst_ty src_ty) x))
-
-
-;; Helpers for generating `fcvt_to_uint` instructions ;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl fpu_to_uint_op (Type Type) FpuToIntOp)
-(rule (fpu_to_uint_op $I32 $F32) (FpuToIntOp.F32ToU32))
-(rule (fpu_to_uint_op $I32 $F64) (FpuToIntOp.F64ToU32))
-(rule (fpu_to_uint_op $I64 $F32) (FpuToIntOp.F32ToU64))
-(rule (fpu_to_uint_op $I64 $F64) (FpuToIntOp.F64ToU64))
-
-(decl fcvt_to_uint_reg_with_flags (Type Type Reg) ProducesFlags)
-(rule (fcvt_to_uint_reg_with_flags dst_ty src_ty x)
-      (fpu_to_int dst_ty (fpu_to_uint_op dst_ty src_ty) x))
-
-(decl fcvt_to_uint_reg (Type Type Reg) Reg)
-(rule (fcvt_to_uint_reg dst_ty src_ty x)
-      (drop_flags (fcvt_to_uint_reg_with_flags dst_ty src_ty x)))
-
-
-;; Helpers for generating `fcvt_to_sint` instructions ;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl fpu_to_sint_op (Type Type) FpuToIntOp)
-(rule (fpu_to_sint_op $I32 $F32) (FpuToIntOp.F32ToI32))
-(rule (fpu_to_sint_op $I32 $F64) (FpuToIntOp.F64ToI32))
-(rule (fpu_to_sint_op $I64 $F32) (FpuToIntOp.F32ToI64))
-(rule (fpu_to_sint_op $I64 $F64) (FpuToIntOp.F64ToI64))
-
-(decl fcvt_to_sint_reg_with_flags (Type Type Reg) ProducesFlags)
-(rule (fcvt_to_sint_reg_with_flags dst_ty src_ty x)
-      (fpu_to_int dst_ty (fpu_to_sint_op dst_ty src_ty) x))
-
-(decl fcvt_to_sint_reg (Type Type Reg) Reg)
-(rule (fcvt_to_sint_reg dst_ty src_ty x)
-      (drop_flags (fcvt_to_sint_reg_with_flags dst_ty src_ty x)))
-
-
-;; Helpers for generating signed `icmp` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl cmpop_cmps (Type) CmpOp)
-(rule (cmpop_cmps $I32) (CmpOp.CmpS32))
-(rule (cmpop_cmps $I64) (CmpOp.CmpS64))
-
-(decl cmpop_cmps_sext16 (Type) CmpOp)
-(rule (cmpop_cmps_sext16 $I32) (CmpOp.CmpS32Ext16))
-(rule (cmpop_cmps_sext16 $I64) (CmpOp.CmpS64Ext16))
-
-(decl cmpop_cmps_sext32 (Type) CmpOp)
-(rule (cmpop_cmps_sext32 $I64) (CmpOp.CmpS64Ext32))
-
-(decl icmps_reg (Type Reg Reg) ProducesFlags)
-(rule (icmps_reg ty src1 src2) (cmp_rr (cmpop_cmps ty) src1 src2))
-
-(decl icmps_reg_sext32 (Type Reg Reg) ProducesFlags)
-(rule (icmps_reg_sext32 ty src1 src2) (cmp_rr (cmpop_cmps_sext32 ty) src1 src2))
-
-(decl icmps_simm16 (Type Reg i16) ProducesFlags)
-(rule (icmps_simm16 ty src imm) (cmp_rsimm16 (cmpop_cmps ty) src imm))
-
-(decl icmps_simm32 (Type Reg i32) ProducesFlags)
-(rule (icmps_simm32 ty src imm) (cmp_rsimm32 (cmpop_cmps ty) src imm))
-
-(decl icmps_mem (Type Reg MemArg) ProducesFlags)
-(rule (icmps_mem ty src mem) (cmp_rx (cmpop_cmps ty) src mem))
-
-(decl icmps_mem_sext16 (Type Reg MemArg) ProducesFlags)
-(rule (icmps_mem_sext16 ty src mem) (cmp_rx (cmpop_cmps_sext16 ty) src mem))
-
-(decl icmps_mem_sext32 (Type Reg MemArg) ProducesFlags)
-(rule (icmps_mem_sext32 ty src mem) (cmp_rx (cmpop_cmps_sext32 ty) src mem))
-
-
-;; Helpers for generating unsigned `icmp` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl cmpop_cmpu (Type) CmpOp)
-(rule (cmpop_cmpu $I32) (CmpOp.CmpL32))
-(rule (cmpop_cmpu $I64) (CmpOp.CmpL64))
-
-(decl cmpop_cmpu_zext16 (Type) CmpOp)
-(rule (cmpop_cmpu_zext16 $I32) (CmpOp.CmpL32Ext16))
-(rule (cmpop_cmpu_zext16 $I64) (CmpOp.CmpL64Ext16))
-
-(decl cmpop_cmpu_zext32 (Type) CmpOp)
-(rule (cmpop_cmpu_zext32 $I64) (CmpOp.CmpL64Ext32))
-
-(decl icmpu_reg (Type Reg Reg) ProducesFlags)
-(rule (icmpu_reg ty src1 src2) (cmp_rr (cmpop_cmpu ty) src1 src2))
-
-(decl icmpu_reg_zext32 (Type Reg Reg) ProducesFlags)
-(rule (icmpu_reg_zext32 ty src1 src2) (cmp_rr (cmpop_cmpu_zext32 ty) src1 src2))
-
-(decl icmpu_uimm32 (Type Reg u32) ProducesFlags)
-(rule (icmpu_uimm32 ty src imm) (cmp_ruimm32 (cmpop_cmpu ty) src imm))
-
-(decl icmpu_mem (Type Reg MemArg) ProducesFlags)
-(rule (icmpu_mem ty src mem) (cmp_rx (cmpop_cmpu ty) src mem))
-
-(decl icmpu_mem_zext16 (Type Reg MemArg) ProducesFlags)
-(rule (icmpu_mem_zext16 ty src mem) (cmp_rx (cmpop_cmpu_zext16 ty) src mem))
-
-(decl icmpu_mem_zext32 (Type Reg MemArg) ProducesFlags)
-(rule (icmpu_mem_zext32 ty src mem) (cmp_rx (cmpop_cmpu_zext32 ty) src mem))
-
-
-;; Helpers for generating `fcmp` instructions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl fcmp_reg (Type Reg Reg) ProducesFlags)
-(rule (fcmp_reg $F32 src1 src2) (fpu_cmp32 src1 src2))
-(rule (fcmp_reg $F64 src1 src2) (fpu_cmp64 src1 src2))
-
-;; Implicit conversions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(convert WritableRegPair RegPair writable_regpair_to_regpair)
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/inst/args.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/inst/args.rs
deleted file mode 100644
index 73f96c61a..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/inst/args.rs
+++ /dev/null
@@ -1,267 +0,0 @@
-//! S390x ISA definitions: instruction arguments.
-
-// Some variants are never constructed, but we still want them as options in the future.
-#![allow(dead_code)]
-
-use crate::ir::condcodes::{FloatCC, IntCC};
-use crate::ir::MemFlags;
-use crate::isa::s390x::inst::*;
-use crate::machinst::MachLabel;
-
-use regalloc::{PrettyPrint, RealRegUniverse, Reg};
-
-use std::string::String;
-
-//=============================================================================
-// Instruction sub-components (memory addresses): definitions
-
-/// A memory argument to load/store, encapsulating the possible addressing modes.
-#[derive(Clone, Debug)]
-pub enum MemArg {
-    //
-    // Real IBM Z addressing modes:
-    //
-    /// Base register, index register, and 12-bit unsigned displacement.
-    BXD12 {
-        base: Reg,
-        index: Reg,
-        disp: UImm12,
-        flags: MemFlags,
-    },
-
-    /// Base register, index register, and 20-bit signed displacement.
-    BXD20 {
-        base: Reg,
-        index: Reg,
-        disp: SImm20,
-        flags: MemFlags,
-    },
-
-    /// PC-relative Reference to a label.
-    Label { target: MachLabel },
-
-    /// PC-relative Reference to a near symbol.
-    Symbol {
-        name: Box<ExternalName>,
-        offset: i32,
-        flags: MemFlags,
-    },
-
-    //
-    // Virtual addressing modes that are lowered at emission time:
-    //
-    /// Arbitrary offset from a register. Converted to generation of large
-    /// offsets with multiple instructions as necessary during code emission.
-    RegOffset { reg: Reg, off: i64, flags: MemFlags },
-
-    /// Offset from the stack pointer at function entry.
-    InitialSPOffset { off: i64 },
-
-    /// Offset from the "nominal stack pointer", which is where the real SP is
-    /// just after stack and spill slots are allocated in the function prologue.
-    /// At emission time, this is converted to `SPOffset` with a fixup added to
-    /// the offset constant. The fixup is a running value that is tracked as
-    /// emission iterates through instructions in linear order, and can be
-    /// adjusted up and down with [Inst::VirtualSPOffsetAdj].
-    ///
-    /// The standard ABI is in charge of handling this (by emitting the
-    /// adjustment meta-instructions). It maintains the invariant that "nominal
-    /// SP" is where the actual SP is after the function prologue and before
-    /// clobber pushes. See the diagram in the documentation for
-    /// [crate::isa::s390x::abi](the ABI module) for more details.
-    NominalSPOffset { off: i64 },
-}
-
-impl MemArg {
-    /// Memory reference using an address in a register.
-    pub fn reg(reg: Reg, flags: MemFlags) -> MemArg {
-        MemArg::BXD12 {
-            base: reg,
-            index: zero_reg(),
-            disp: UImm12::zero(),
-            flags,
-        }
-    }
-
-    /// Memory reference using the sum of two registers as an address.
-    pub fn reg_plus_reg(reg1: Reg, reg2: Reg, flags: MemFlags) -> MemArg {
-        MemArg::BXD12 {
-            base: reg1,
-            index: reg2,
-            disp: UImm12::zero(),
-            flags,
-        }
-    }
-
-    /// Memory reference using the sum of a register an an offset as address.
-    pub fn reg_plus_off(reg: Reg, off: i64, flags: MemFlags) -> MemArg {
-        MemArg::RegOffset { reg, off, flags }
-    }
-
-    pub(crate) fn get_flags(&self) -> MemFlags {
-        match self {
-            MemArg::BXD12 { flags, .. } => *flags,
-            MemArg::BXD20 { flags, .. } => *flags,
-            MemArg::RegOffset { flags, .. } => *flags,
-            MemArg::Label { .. } => MemFlags::trusted(),
-            MemArg::Symbol { flags, .. } => *flags,
-            MemArg::InitialSPOffset { .. } => MemFlags::trusted(),
-            MemArg::NominalSPOffset { .. } => MemFlags::trusted(),
-        }
-    }
-
-    pub(crate) fn can_trap(&self) -> bool {
-        !self.get_flags().notrap()
-    }
-}
-
-//=============================================================================
-// Instruction sub-components (conditions, branches and branch targets):
-// definitions
-
-/// Condition for conditional branches.
-#[derive(Clone, Copy, Debug, PartialEq, Eq)]
-pub struct Cond {
-    mask: u8,
-}
-
-impl Cond {
-    pub fn from_mask(mask: u8) -> Cond {
-        assert!(mask >= 1 && mask <= 14);
-        Cond { mask }
-    }
-
-    pub fn from_intcc(cc: IntCC) -> Cond {
-        let mask = match cc {
-            IntCC::Equal => 8,
-            IntCC::NotEqual => 4 | 2,
-            IntCC::SignedGreaterThanOrEqual => 8 | 2,
-            IntCC::SignedGreaterThan => 2,
-            IntCC::SignedLessThanOrEqual => 8 | 4,
-            IntCC::SignedLessThan => 4,
-            IntCC::UnsignedGreaterThanOrEqual => 8 | 2,
-            IntCC::UnsignedGreaterThan => 2,
-            IntCC::UnsignedLessThanOrEqual => 8 | 4,
-            IntCC::UnsignedLessThan => 4,
-            IntCC::Overflow => 1,
-            IntCC::NotOverflow => 8 | 4 | 2,
-        };
-        Cond { mask }
-    }
-
-    pub fn from_floatcc(cc: FloatCC) -> Cond {
-        let mask = match cc {
-            FloatCC::Ordered => 8 | 4 | 2,
-            FloatCC::Unordered => 1,
-            FloatCC::Equal => 8,
-            FloatCC::NotEqual => 4 | 2 | 1,
-            FloatCC::OrderedNotEqual => 4 | 2,
-            FloatCC::UnorderedOrEqual => 8 | 1,
-            FloatCC::LessThan => 4,
-            FloatCC::LessThanOrEqual => 8 | 4,
-            FloatCC::GreaterThan => 2,
-            FloatCC::GreaterThanOrEqual => 8 | 2,
-            FloatCC::UnorderedOrLessThan => 4 | 1,
-            FloatCC::UnorderedOrLessThanOrEqual => 8 | 4 | 1,
-            FloatCC::UnorderedOrGreaterThan => 2 | 1,
-            FloatCC::UnorderedOrGreaterThanOrEqual => 8 | 2 | 1,
-        };
-        Cond { mask }
-    }
-
-    /// Return the inverted condition.
-    pub fn invert(self) -> Cond {
-        Cond {
-            mask: !self.mask & 15,
-        }
-    }
-
-    /// Return the machine encoding of this condition.
-    pub fn bits(self) -> u8 {
-        self.mask
-    }
-}
-
-impl PrettyPrint for MemArg {
-    fn show_rru(&self, mb_rru: Option<&RealRegUniverse>) -> String {
-        match self {
-            &MemArg::BXD12 {
-                base, index, disp, ..
-            } => {
-                if base != zero_reg() {
-                    if index != zero_reg() {
-                        format!(
-                            "{}({},{})",
-                            disp.show_rru(mb_rru),
-                            index.show_rru(mb_rru),
-                            base.show_rru(mb_rru)
-                        )
-                    } else {
-                        format!("{}({})", disp.show_rru(mb_rru), base.show_rru(mb_rru))
-                    }
-                } else {
-                    if index != zero_reg() {
-                        format!("{}({},)", disp.show_rru(mb_rru), index.show_rru(mb_rru))
-                    } else {
-                        format!("{}", disp.show_rru(mb_rru))
-                    }
-                }
-            }
-            &MemArg::BXD20 {
-                base, index, disp, ..
-            } => {
-                if base != zero_reg() {
-                    if index != zero_reg() {
-                        format!(
-                            "{}({},{})",
-                            disp.show_rru(mb_rru),
-                            index.show_rru(mb_rru),
-                            base.show_rru(mb_rru)
-                        )
-                    } else {
-                        format!("{}({})", disp.show_rru(mb_rru), base.show_rru(mb_rru))
-                    }
-                } else {
-                    if index != zero_reg() {
-                        format!("{}({},)", disp.show_rru(mb_rru), index.show_rru(mb_rru))
-                    } else {
-                        format!("{}", disp.show_rru(mb_rru))
-                    }
-                }
-            }
-            &MemArg::Label { target } => target.to_string(),
-            &MemArg::Symbol {
-                ref name, offset, ..
-            } => format!("{} + {}", name, offset),
-            // Eliminated by `mem_finalize()`.
-            &MemArg::InitialSPOffset { .. }
-            | &MemArg::NominalSPOffset { .. }
-            | &MemArg::RegOffset { .. } => {
-                panic!("Unexpected pseudo mem-arg mode (stack-offset or generic reg-offset)!")
-            }
-        }
-    }
-}
-
-impl PrettyPrint for Cond {
-    fn show_rru(&self, _mb_rru: Option<&RealRegUniverse>) -> String {
-        let s = match self.mask {
-            1 => "o",
-            2 => "h",
-            3 => "nle",
-            4 => "l",
-            5 => "nhe",
-            6 => "lh",
-            7 => "ne",
-            8 => "e",
-            9 => "nlh",
-            10 => "he",
-            11 => "nl",
-            12 => "le",
-            13 => "nh",
-            14 => "no",
-            _ => unreachable!(),
-        };
-        s.to_string()
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/inst/emit.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/inst/emit.rs
deleted file mode 100644
index 46067ed4b..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/inst/emit.rs
+++ /dev/null
@@ -1,2159 +0,0 @@
-//! S390x ISA: binary code emission.
-
-use crate::binemit::{Reloc, StackMap};
-use crate::ir::MemFlags;
-use crate::ir::{SourceLoc, TrapCode};
-use crate::isa::s390x::inst::*;
-use crate::isa::s390x::settings as s390x_settings;
-use core::convert::TryFrom;
-use regalloc::{Reg, RegClass};
-
-/// Memory addressing mode finalization: convert "special" modes (e.g.,
-/// generic arbitrary stack offset) into real addressing modes, possibly by
-/// emitting some helper instructions that come immediately before the use
-/// of this amode.
-pub fn mem_finalize(
-    mem: &MemArg,
-    state: &EmitState,
-    have_d12: bool,
-    have_d20: bool,
-    have_pcrel: bool,
-    have_index: bool,
-) -> (SmallVec<[Inst; 4]>, MemArg) {
-    let mut insts = SmallVec::new();
-
-    // Resolve virtual addressing modes.
-    let mem = match mem {
-        &MemArg::RegOffset { off, .. }
-        | &MemArg::InitialSPOffset { off }
-        | &MemArg::NominalSPOffset { off } => {
-            let base = match mem {
-                &MemArg::RegOffset { reg, .. } => reg,
-                &MemArg::InitialSPOffset { .. } | &MemArg::NominalSPOffset { .. } => stack_reg(),
-                _ => unreachable!(),
-            };
-            let adj = match mem {
-                &MemArg::InitialSPOffset { .. } => {
-                    state.initial_sp_offset + state.virtual_sp_offset
-                }
-                &MemArg::NominalSPOffset { .. } => state.virtual_sp_offset,
-                _ => 0,
-            };
-            let off = off + adj;
-
-            if let Some(disp) = UImm12::maybe_from_u64(off as u64) {
-                MemArg::BXD12 {
-                    base,
-                    index: zero_reg(),
-                    disp,
-                    flags: mem.get_flags(),
-                }
-            } else if let Some(disp) = SImm20::maybe_from_i64(off) {
-                MemArg::BXD20 {
-                    base,
-                    index: zero_reg(),
-                    disp,
-                    flags: mem.get_flags(),
-                }
-            } else {
-                let tmp = writable_spilltmp_reg();
-                assert!(base != tmp.to_reg());
-                insts.extend(Inst::load_constant64(tmp, off as u64));
-                MemArg::reg_plus_reg(base, tmp.to_reg(), mem.get_flags())
-            }
-        }
-        _ => mem.clone(),
-    };
-
-    // If this addressing mode cannot be handled by the instruction, use load-address.
-    let need_load_address = match &mem {
-        &MemArg::Label { .. } | &MemArg::Symbol { .. } if !have_pcrel => true,
-        &MemArg::BXD20 { .. } if !have_d20 => true,
-        &MemArg::BXD12 { index, .. } | &MemArg::BXD20 { index, .. } if !have_index => {
-            index != zero_reg()
-        }
-        _ => false,
-    };
-    let mem = if need_load_address {
-        let flags = mem.get_flags();
-        let tmp = writable_spilltmp_reg();
-        insts.push(Inst::LoadAddr { rd: tmp, mem });
-        MemArg::reg(tmp.to_reg(), flags)
-    } else {
-        mem
-    };
-
-    // Convert 12-bit displacement to 20-bit if required.
-    let mem = match &mem {
-        &MemArg::BXD12 {
-            base,
-            index,
-            disp,
-            flags,
-        } if !have_d12 => {
-            assert!(have_d20);
-            MemArg::BXD20 {
-                base,
-                index,
-                disp: SImm20::from_uimm12(disp),
-                flags,
-            }
-        }
-        _ => mem,
-    };
-
-    (insts, mem)
-}
-
-pub fn mem_emit(
-    rd: Reg,
-    mem: &MemArg,
-    opcode_rx: Option<u16>,
-    opcode_rxy: Option<u16>,
-    opcode_ril: Option<u16>,
-    add_trap: bool,
-    sink: &mut MachBuffer<Inst>,
-    emit_info: &EmitInfo,
-    state: &mut EmitState,
-) {
-    let (mem_insts, mem) = mem_finalize(
-        mem,
-        state,
-        opcode_rx.is_some(),
-        opcode_rxy.is_some(),
-        opcode_ril.is_some(),
-        true,
-    );
-    for inst in mem_insts.into_iter() {
-        inst.emit(sink, emit_info, state);
-    }
-
-    if add_trap && mem.can_trap() {
-        let srcloc = state.cur_srcloc();
-        if srcloc != SourceLoc::default() {
-            sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
-        }
-    }
-
-    match &mem {
-        &MemArg::BXD12 {
-            base, index, disp, ..
-        } => {
-            put(
-                sink,
-                &enc_rx(opcode_rx.unwrap(), rd, base, index, disp.bits()),
-            );
-        }
-        &MemArg::BXD20 {
-            base, index, disp, ..
-        } => {
-            put(
-                sink,
-                &enc_rxy(opcode_rxy.unwrap(), rd, base, index, disp.bits()),
-            );
-        }
-        &MemArg::Label { target } => {
-            sink.use_label_at_offset(sink.cur_offset(), target, LabelUse::BranchRIL);
-            put(sink, &enc_ril_b(opcode_ril.unwrap(), rd, 0));
-        }
-        &MemArg::Symbol {
-            ref name, offset, ..
-        } => {
-            let reloc = Reloc::S390xPCRel32Dbl;
-            let srcloc = state.cur_srcloc();
-            put_with_reloc(
-                sink,
-                &enc_ril_b(opcode_ril.unwrap(), rd, 0),
-                2,
-                srcloc,
-                reloc,
-                name,
-                offset.into(),
-            );
-        }
-        _ => unreachable!(),
-    }
-}
-
-pub fn mem_rs_emit(
-    rd: Reg,
-    rn: Reg,
-    mem: &MemArg,
-    opcode_rs: Option<u16>,
-    opcode_rsy: Option<u16>,
-    add_trap: bool,
-    sink: &mut MachBuffer<Inst>,
-    emit_info: &EmitInfo,
-    state: &mut EmitState,
-) {
-    let (mem_insts, mem) = mem_finalize(
-        mem,
-        state,
-        opcode_rs.is_some(),
-        opcode_rsy.is_some(),
-        false,
-        false,
-    );
-    for inst in mem_insts.into_iter() {
-        inst.emit(sink, emit_info, state);
-    }
-
-    if add_trap && mem.can_trap() {
-        let srcloc = state.cur_srcloc();
-        if srcloc != SourceLoc::default() {
-            sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
-        }
-    }
-
-    match &mem {
-        &MemArg::BXD12 {
-            base, index, disp, ..
-        } => {
-            assert!(index == zero_reg());
-            put(sink, &enc_rs(opcode_rs.unwrap(), rd, rn, base, disp.bits()));
-        }
-        &MemArg::BXD20 {
-            base, index, disp, ..
-        } => {
-            assert!(index == zero_reg());
-            put(
-                sink,
-                &enc_rsy(opcode_rsy.unwrap(), rd, rn, base, disp.bits()),
-            );
-        }
-        _ => unreachable!(),
-    }
-}
-
-pub fn mem_imm8_emit(
-    imm: u8,
-    mem: &MemArg,
-    opcode_si: u16,
-    opcode_siy: u16,
-    add_trap: bool,
-    sink: &mut MachBuffer<Inst>,
-    emit_info: &EmitInfo,
-    state: &mut EmitState,
-) {
-    let (mem_insts, mem) = mem_finalize(mem, state, true, true, false, false);
-    for inst in mem_insts.into_iter() {
-        inst.emit(sink, emit_info, state);
-    }
-
-    if add_trap && mem.can_trap() {
-        let srcloc = state.cur_srcloc();
-        if srcloc != SourceLoc::default() {
-            sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
-        }
-    }
-
-    match &mem {
-        &MemArg::BXD12 {
-            base, index, disp, ..
-        } => {
-            assert!(index == zero_reg());
-            put(sink, &enc_si(opcode_si, base, disp.bits(), imm));
-        }
-        &MemArg::BXD20 {
-            base, index, disp, ..
-        } => {
-            assert!(index == zero_reg());
-            put(sink, &enc_siy(opcode_siy, base, disp.bits(), imm));
-        }
-        _ => unreachable!(),
-    }
-}
-
-pub fn mem_imm16_emit(
-    imm: i16,
-    mem: &MemArg,
-    opcode_sil: u16,
-    add_trap: bool,
-    sink: &mut MachBuffer<Inst>,
-    emit_info: &EmitInfo,
-    state: &mut EmitState,
-) {
-    let (mem_insts, mem) = mem_finalize(mem, state, true, false, false, false);
-    for inst in mem_insts.into_iter() {
-        inst.emit(sink, emit_info, state);
-    }
-
-    if add_trap && mem.can_trap() {
-        let srcloc = state.cur_srcloc();
-        if srcloc != SourceLoc::default() {
-            sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
-        }
-    }
-
-    match &mem {
-        &MemArg::BXD12 {
-            base, index, disp, ..
-        } => {
-            assert!(index == zero_reg());
-            put(sink, &enc_sil(opcode_sil, base, disp.bits(), imm));
-        }
-        _ => unreachable!(),
-    }
-}
-
-//=============================================================================
-// Instructions and subcomponents: emission
-
-fn machreg_to_gpr(m: Reg) -> u8 {
-    assert_eq!(m.get_class(), RegClass::I64);
-    u8::try_from(m.to_real_reg().get_hw_encoding()).unwrap()
-}
-
-fn machreg_to_fpr(m: Reg) -> u8 {
-    assert_eq!(m.get_class(), RegClass::F64);
-    u8::try_from(m.to_real_reg().get_hw_encoding()).unwrap()
-}
-
-fn machreg_to_gpr_or_fpr(m: Reg) -> u8 {
-    u8::try_from(m.to_real_reg().get_hw_encoding()).unwrap()
-}
-
-/// E-type instructions.
-///
-///   15
-///   opcode
-///        0
-///
-fn enc_e(opcode: u16) -> [u8; 2] {
-    let mut enc: [u8; 2] = [0; 2];
-    let opcode1 = ((opcode >> 8) & 0xff) as u8;
-    let opcode2 = (opcode & 0xff) as u8;
-
-    enc[0] = opcode1;
-    enc[1] = opcode2;
-    enc
-}
-
-/// RIa-type instructions.
-///
-///   31      23 19      15
-///   opcode1 r1 opcode2 i2
-///        24 20      16  0
-///
-fn enc_ri_a(opcode: u16, r1: Reg, i2: u16) -> [u8; 4] {
-    let mut enc: [u8; 4] = [0; 4];
-    let opcode1 = ((opcode >> 4) & 0xff) as u8;
-    let opcode2 = (opcode & 0xf) as u8;
-    let r1 = machreg_to_gpr(r1) & 0x0f;
-
-    enc[0] = opcode1;
-    enc[1] = r1 << 4 | opcode2;
-    enc[2..].copy_from_slice(&i2.to_be_bytes());
-    enc
-}
-
-/// RIb-type instructions.
-///
-///   31      23 19      15
-///   opcode1 r1 opcode2 ri2
-///        24 20      16   0
-///
-fn enc_ri_b(opcode: u16, r1: Reg, ri2: i32) -> [u8; 4] {
-    let mut enc: [u8; 4] = [0; 4];
-    let opcode1 = ((opcode >> 4) & 0xff) as u8;
-    let opcode2 = (opcode & 0xf) as u8;
-    let r1 = machreg_to_gpr(r1) & 0x0f;
-    let ri2 = ((ri2 >> 1) & 0xffff) as u16;
-
-    enc[0] = opcode1;
-    enc[1] = r1 << 4 | opcode2;
-    enc[2..].copy_from_slice(&ri2.to_be_bytes());
-    enc
-}
-
-/// RIc-type instructions.
-///
-///   31      23 19      15
-///   opcode1 m1 opcode2 ri2
-///        24 20      16   0
-///
-fn enc_ri_c(opcode: u16, m1: u8, ri2: i32) -> [u8; 4] {
-    let mut enc: [u8; 4] = [0; 4];
-    let opcode1 = ((opcode >> 4) & 0xff) as u8;
-    let opcode2 = (opcode & 0xf) as u8;
-    let m1 = m1 & 0x0f;
-    let ri2 = ((ri2 >> 1) & 0xffff) as u16;
-
-    enc[0] = opcode1;
-    enc[1] = m1 << 4 | opcode2;
-    enc[2..].copy_from_slice(&ri2.to_be_bytes());
-    enc
-}
-
-/// RIEa-type instructions.
-///
-///   47      39 35 31 15 11 7
-///   opcode1 r1 -- i2 m3 -- opcode2
-///        40 36 32 16 12 8       0
-///
-fn enc_rie_a(opcode: u16, r1: Reg, i2: u16, m3: u8) -> [u8; 6] {
-    let mut enc: [u8; 6] = [0; 6];
-    let opcode1 = ((opcode >> 8) & 0xff) as u8;
-    let opcode2 = (opcode & 0xff) as u8;
-    let r1 = machreg_to_gpr(r1) & 0x0f;
-    let m3 = m3 & 0x0f;
-
-    enc[0] = opcode1;
-    enc[1] = r1 << 4;
-    enc[2..4].copy_from_slice(&i2.to_be_bytes());
-    enc[4] = m3 << 4;
-    enc[5] = opcode2;
-    enc
-}
-
-/// RIEd-type instructions.
-///
-///   47      39 35 31 15 7
-///   opcode1 r1 r3 i2 -- opcode2
-///        40 36 32 16  8       0
-///
-fn enc_rie_d(opcode: u16, r1: Reg, r3: Reg, i2: u16) -> [u8; 6] {
-    let mut enc: [u8; 6] = [0; 6];
-    let opcode1 = ((opcode >> 8) & 0xff) as u8;
-    let opcode2 = (opcode & 0xff) as u8;
-    let r1 = machreg_to_gpr(r1) & 0x0f;
-    let r3 = machreg_to_gpr(r3) & 0x0f;
-
-    enc[0] = opcode1;
-    enc[1] = r1 << 4 | r3;
-    enc[2..4].copy_from_slice(&i2.to_be_bytes());
-    enc[5] = opcode2;
-    enc
-}
-
-/// RIEf-type instructions.
-///
-///   47      39 35 31 23 15 7
-///   opcode1 r1 r2 i3 i4 i5 opcode2
-///        40 36 32 24 16  8       0
-///
-fn enc_rie_f(opcode: u16, r1: Reg, r2: Reg, i3: u8, i4: u8, i5: u8) -> [u8; 6] {
-    let mut enc: [u8; 6] = [0; 6];
-    let opcode1 = ((opcode >> 8) & 0xff) as u8;
-    let opcode2 = (opcode & 0xff) as u8;
-    let r1 = machreg_to_gpr(r1) & 0x0f;
-    let r2 = machreg_to_gpr(r2) & 0x0f;
-
-    enc[0] = opcode1;
-    enc[1] = r1 << 4 | r2;
-    enc[2] = i3;
-    enc[3] = i4;
-    enc[4] = i5;
-    enc[5] = opcode2;
-    enc
-}
-
-/// RIEg-type instructions.
-///
-///   47      39 35 31 15 7
-///   opcode1 r1 m3 i2 -- opcode2
-///        40 36 32 16  8       0
-///
-fn enc_rie_g(opcode: u16, r1: Reg, i2: u16, m3: u8) -> [u8; 6] {
-    let mut enc: [u8; 6] = [0; 6];
-    let opcode1 = ((opcode >> 8) & 0xff) as u8;
-    let opcode2 = (opcode & 0xff) as u8;
-    let r1 = machreg_to_gpr(r1) & 0x0f;
-    let m3 = m3 & 0x0f;
-
-    enc[0] = opcode1;
-    enc[1] = r1 << 4 | m3;
-    enc[2..4].copy_from_slice(&i2.to_be_bytes());
-    enc[5] = opcode2;
-    enc
-}
-
-/// RILa-type instructions.
-///
-///   47      39 35      31
-///   opcode1 r1 opcode2 i2
-///        40 36      32  0
-///
-fn enc_ril_a(opcode: u16, r1: Reg, i2: u32) -> [u8; 6] {
-    let mut enc: [u8; 6] = [0; 6];
-    let opcode1 = ((opcode >> 4) & 0xff) as u8;
-    let opcode2 = (opcode & 0xf) as u8;
-    let r1 = machreg_to_gpr(r1) & 0x0f;
-
-    enc[0] = opcode1;
-    enc[1] = r1 << 4 | opcode2;
-    enc[2..].copy_from_slice(&i2.to_be_bytes());
-    enc
-}
-
-/// RILb-type instructions.
-///
-///   47      39 35      31
-///   opcode1 r1 opcode2 ri2
-///        40 36      32   0
-///
-fn enc_ril_b(opcode: u16, r1: Reg, ri2: u32) -> [u8; 6] {
-    let mut enc: [u8; 6] = [0; 6];
-    let opcode1 = ((opcode >> 4) & 0xff) as u8;
-    let opcode2 = (opcode & 0xf) as u8;
-    let r1 = machreg_to_gpr(r1) & 0x0f;
-
-    enc[0] = opcode1;
-    enc[1] = r1 << 4 | opcode2;
-    enc[2..].copy_from_slice(&ri2.to_be_bytes());
-    enc
-}
-
-/// RILc-type instructions.
-///
-///   47      39 35      31
-///   opcode1 m1 opcode2 i2
-///        40 36      32  0
-///
-fn enc_ril_c(opcode: u16, m1: u8, ri2: u32) -> [u8; 6] {
-    let mut enc: [u8; 6] = [0; 6];
-    let opcode1 = ((opcode >> 4) & 0xff) as u8;
-    let opcode2 = (opcode & 0xf) as u8;
-    let m1 = m1 & 0x0f;
-
-    enc[0] = opcode1;
-    enc[1] = m1 << 4 | opcode2;
-    enc[2..].copy_from_slice(&ri2.to_be_bytes());
-    enc
-}
-
-/// RR-type instructions.
-///
-///   15     7  3
-///   opcode r1 r2
-///        8  4  0
-///
-fn enc_rr(opcode: u16, r1: Reg, r2: Reg) -> [u8; 2] {
-    let mut enc: [u8; 2] = [0; 2];
-    let opcode = (opcode & 0xff) as u8;
-    let r1 = machreg_to_gpr_or_fpr(r1) & 0x0f;
-    let r2 = machreg_to_gpr_or_fpr(r2) & 0x0f;
-
-    enc[0] = opcode;
-    enc[1] = r1 << 4 | r2;
-    enc
-}
-
-/// RRD-type instructions.
-///
-///   31     15 11 7  3
-///   opcode r1 -- r3 r2
-///       16 12  8 4  0
-///
-fn enc_rrd(opcode: u16, r1: Reg, r2: Reg, r3: Reg) -> [u8; 4] {
-    let mut enc: [u8; 4] = [0; 4];
-    let opcode1 = ((opcode >> 8) & 0xff) as u8;
-    let opcode2 = (opcode & 0xff) as u8;
-    let r1 = machreg_to_fpr(r1) & 0x0f;
-    let r2 = machreg_to_fpr(r2) & 0x0f;
-    let r3 = machreg_to_fpr(r3) & 0x0f;
-
-    enc[0] = opcode1;
-    enc[1] = opcode2;
-    enc[2] = r1 << 4;
-    enc[3] = r3 << 4 | r2;
-    enc
-}
-
-/// RRE-type instructions.
-///
-///   31     15 7  3
-///   opcode -- r1 r2
-///       16  8  4  0
-///
-fn enc_rre(opcode: u16, r1: Reg, r2: Reg) -> [u8; 4] {
-    let mut enc: [u8; 4] = [0; 4];
-    let opcode1 = ((opcode >> 8) & 0xff) as u8;
-    let opcode2 = (opcode & 0xff) as u8;
-    let r1 = machreg_to_gpr_or_fpr(r1) & 0x0f;
-    let r2 = machreg_to_gpr_or_fpr(r2) & 0x0f;
-
-    enc[0] = opcode1;
-    enc[1] = opcode2;
-    enc[3] = r1 << 4 | r2;
-    enc
-}
-
-/// RRFa/b-type instructions.
-///
-///   31     15 11 7  3
-///   opcode r3 m4 r1 r2
-///       16 12  8  4  0
-///
-fn enc_rrf_ab(opcode: u16, r1: Reg, r2: Reg, r3: Reg, m4: u8) -> [u8; 4] {
-    let mut enc: [u8; 4] = [0; 4];
-    let opcode1 = ((opcode >> 8) & 0xff) as u8;
-    let opcode2 = (opcode & 0xff) as u8;
-    let r1 = machreg_to_gpr_or_fpr(r1) & 0x0f;
-    let r2 = machreg_to_gpr_or_fpr(r2) & 0x0f;
-    let r3 = machreg_to_gpr_or_fpr(r3) & 0x0f;
-    let m4 = m4 & 0x0f;
-
-    enc[0] = opcode1;
-    enc[1] = opcode2;
-    enc[2] = r3 << 4 | m4;
-    enc[3] = r1 << 4 | r2;
-    enc
-}
-
-/// RRFc/d/e-type instructions.
-///
-///   31     15 11 7  3
-///   opcode m3 m4 r1 r2
-///       16 12  8  4  0
-///
-fn enc_rrf_cde(opcode: u16, r1: Reg, r2: Reg, m3: u8, m4: u8) -> [u8; 4] {
-    let mut enc: [u8; 4] = [0; 4];
-    let opcode1 = ((opcode >> 8) & 0xff) as u8;
-    let opcode2 = (opcode & 0xff) as u8;
-    let r1 = machreg_to_gpr_or_fpr(r1) & 0x0f;
-    let r2 = machreg_to_gpr_or_fpr(r2) & 0x0f;
-    let m3 = m3 & 0x0f;
-    let m4 = m4 & 0x0f;
-
-    enc[0] = opcode1;
-    enc[1] = opcode2;
-    enc[2] = m3 << 4 | m4;
-    enc[3] = r1 << 4 | r2;
-    enc
-}
-
-/// RS-type instructions.
-///
-///   31     23 19 15 11
-///   opcode r1 r3 b2 d2
-///       24 20 16 12  0
-///
-fn enc_rs(opcode: u16, r1: Reg, r3: Reg, b2: Reg, d2: u32) -> [u8; 4] {
-    let opcode = (opcode & 0xff) as u8;
-    let r1 = machreg_to_gpr_or_fpr(r1) & 0x0f;
-    let r3 = machreg_to_gpr_or_fpr(r3) & 0x0f;
-    let b2 = machreg_to_gpr(b2) & 0x0f;
-    let d2_lo = (d2 & 0xff) as u8;
-    let d2_hi = ((d2 >> 8) & 0x0f) as u8;
-
-    let mut enc: [u8; 4] = [0; 4];
-    enc[0] = opcode;
-    enc[1] = r1 << 4 | r3;
-    enc[2] = b2 << 4 | d2_hi;
-    enc[3] = d2_lo;
-    enc
-}
-
-/// RSY-type instructions.
-///
-///   47      39 35 31 27  15  7
-///   opcode1 r1 r3 b2 dl2 dh2 opcode2
-///        40 36 32 28  16   8       0
-///
-fn enc_rsy(opcode: u16, r1: Reg, r3: Reg, b2: Reg, d2: u32) -> [u8; 6] {
-    let opcode1 = ((opcode >> 8) & 0xff) as u8;
-    let opcode2 = (opcode & 0xff) as u8;
-    let r1 = machreg_to_gpr_or_fpr(r1) & 0x0f;
-    let r3 = machreg_to_gpr_or_fpr(r3) & 0x0f;
-    let b2 = machreg_to_gpr(b2) & 0x0f;
-    let dl2_lo = (d2 & 0xff) as u8;
-    let dl2_hi = ((d2 >> 8) & 0x0f) as u8;
-    let dh2 = ((d2 >> 12) & 0xff) as u8;
-
-    let mut enc: [u8; 6] = [0; 6];
-    enc[0] = opcode1;
-    enc[1] = r1 << 4 | r3;
-    enc[2] = b2 << 4 | dl2_hi;
-    enc[3] = dl2_lo;
-    enc[4] = dh2;
-    enc[5] = opcode2;
-    enc
-}
-
-/// RX-type instructions.
-///
-///   31     23 19 15 11
-///   opcode r1 x2 b2 d2
-///       24 20 16 12  0
-///
-fn enc_rx(opcode: u16, r1: Reg, b2: Reg, x2: Reg, d2: u32) -> [u8; 4] {
-    let opcode = (opcode & 0xff) as u8;
-    let r1 = machreg_to_gpr_or_fpr(r1) & 0x0f;
-    let b2 = machreg_to_gpr(b2) & 0x0f;
-    let x2 = machreg_to_gpr(x2) & 0x0f;
-    let d2_lo = (d2 & 0xff) as u8;
-    let d2_hi = ((d2 >> 8) & 0x0f) as u8;
-
-    let mut enc: [u8; 4] = [0; 4];
-    enc[0] = opcode;
-    enc[1] = r1 << 4 | x2;
-    enc[2] = b2 << 4 | d2_hi;
-    enc[3] = d2_lo;
-    enc
-}
-
-/// RXY-type instructions.
-///
-///   47      39 35 31 27  15  7
-///   opcode1 r1 x2 b2 dl2 dh2 opcode2
-///        40 36 32 28  16   8       0
-///
-fn enc_rxy(opcode: u16, r1: Reg, b2: Reg, x2: Reg, d2: u32) -> [u8; 6] {
-    let opcode1 = ((opcode >> 8) & 0xff) as u8;
-    let opcode2 = (opcode & 0xff) as u8;
-    let r1 = machreg_to_gpr_or_fpr(r1) & 0x0f;
-    let b2 = machreg_to_gpr(b2) & 0x0f;
-    let x2 = machreg_to_gpr(x2) & 0x0f;
-    let dl2_lo = (d2 & 0xff) as u8;
-    let dl2_hi = ((d2 >> 8) & 0x0f) as u8;
-    let dh2 = ((d2 >> 12) & 0xff) as u8;
-
-    let mut enc: [u8; 6] = [0; 6];
-    enc[0] = opcode1;
-    enc[1] = r1 << 4 | x2;
-    enc[2] = b2 << 4 | dl2_hi;
-    enc[3] = dl2_lo;
-    enc[4] = dh2;
-    enc[5] = opcode2;
-    enc
-}
-
-/// SI-type instructions.
-///
-///   31     23 15 11
-///   opcode i2 b1 d1
-///       24 16 12  0
-///
-fn enc_si(opcode: u16, b1: Reg, d1: u32, i2: u8) -> [u8; 4] {
-    let opcode = (opcode & 0xff) as u8;
-    let b1 = machreg_to_gpr(b1) & 0x0f;
-    let d1_lo = (d1 & 0xff) as u8;
-    let d1_hi = ((d1 >> 8) & 0x0f) as u8;
-
-    let mut enc: [u8; 4] = [0; 4];
-    enc[0] = opcode;
-    enc[1] = i2;
-    enc[2] = b1 << 4 | d1_hi;
-    enc[3] = d1_lo;
-    enc
-}
-
-/// SIL-type instructions.
-///
-///   47     31 27 15
-///   opcode b1 d1 i2
-///       32 28 16  0
-///
-fn enc_sil(opcode: u16, b1: Reg, d1: u32, i2: i16) -> [u8; 6] {
-    let opcode1 = ((opcode >> 8) & 0xff) as u8;
-    let opcode2 = (opcode & 0xff) as u8;
-    let b1 = machreg_to_gpr(b1) & 0x0f;
-    let d1_lo = (d1 & 0xff) as u8;
-    let d1_hi = ((d1 >> 8) & 0x0f) as u8;
-
-    let mut enc: [u8; 6] = [0; 6];
-    enc[0] = opcode1;
-    enc[1] = opcode2;
-    enc[2] = b1 << 4 | d1_hi;
-    enc[3] = d1_lo;
-    enc[4..].copy_from_slice(&i2.to_be_bytes());
-    enc
-}
-
-/// SIY-type instructions.
-///
-///   47      39 31 27  15  7
-///   opcode1 i2 b1 dl1 dh1 opcode2
-///        40 32 28  16   8       0
-///
-fn enc_siy(opcode: u16, b1: Reg, d1: u32, i2: u8) -> [u8; 6] {
-    let opcode1 = ((opcode >> 8) & 0xff) as u8;
-    let opcode2 = (opcode & 0xff) as u8;
-    let b1 = machreg_to_gpr(b1) & 0x0f;
-    let dl1_lo = (d1 & 0xff) as u8;
-    let dl1_hi = ((d1 >> 8) & 0x0f) as u8;
-    let dh1 = ((d1 >> 12) & 0xff) as u8;
-
-    let mut enc: [u8; 6] = [0; 6];
-    enc[0] = opcode1;
-    enc[1] = i2;
-    enc[2] = b1 << 4 | dl1_hi;
-    enc[3] = dl1_lo;
-    enc[4] = dh1;
-    enc[5] = opcode2;
-    enc
-}
-
-/// VRR-type instructions.
-///
-///   47      39 35 31 27 23 19 15 11  7
-///   opcode1 v1 v2 v3 -  m6 m5 m4 rxb opcode2
-///        40 36 32 28 24 20 16 12   8       0
-///
-fn enc_vrr(opcode: u16, v1: Reg, v2: Reg, v3: Reg, m4: u8, m5: u8, m6: u8) -> [u8; 6] {
-    let opcode1 = ((opcode >> 8) & 0xff) as u8;
-    let opcode2 = (opcode & 0xff) as u8;
-    let rxb = 0; // FIXME
-    let v1 = machreg_to_fpr(v1) & 0x0f; // FIXME
-    let v2 = machreg_to_fpr(v2) & 0x0f; // FIXME
-    let v3 = machreg_to_fpr(v3) & 0x0f; // FIXME
-    let m4 = m4 & 0x0f;
-    let m5 = m5 & 0x0f;
-    let m6 = m6 & 0x0f;
-
-    let mut enc: [u8; 6] = [0; 6];
-    enc[0] = opcode1;
-    enc[1] = v1 << 4 | v2;
-    enc[2] = v3 << 4;
-    enc[3] = m6 << 4 | m5;
-    enc[4] = m4 << 4 | rxb;
-    enc[5] = opcode2;
-    enc
-}
-
-/// VRX-type instructions.
-///
-///   47      39 35 31 27 15 11  7
-///   opcode1 v1 x2 b2 d2 m3 rxb opcode2
-///        40 36 32 28 16 12   8       0
-///
-fn enc_vrx(opcode: u16, v1: Reg, b2: Reg, x2: Reg, d2: u32, m3: u8) -> [u8; 6] {
-    let opcode1 = ((opcode >> 8) & 0xff) as u8;
-    let opcode2 = (opcode & 0xff) as u8;
-    let rxb = 0; // FIXME
-    let v1 = machreg_to_fpr(v1) & 0x0f; // FIXME
-    let b2 = machreg_to_gpr(b2) & 0x0f;
-    let x2 = machreg_to_gpr(x2) & 0x0f;
-    let d2_lo = (d2 & 0xff) as u8;
-    let d2_hi = ((d2 >> 8) & 0x0f) as u8;
-    let m3 = m3 & 0x0f;
-
-    let mut enc: [u8; 6] = [0; 6];
-    enc[0] = opcode1;
-    enc[1] = v1 << 4 | x2;
-    enc[2] = b2 << 4 | d2_hi;
-    enc[3] = d2_lo;
-    enc[4] = m3 << 4 | rxb;
-    enc[5] = opcode2;
-    enc
-}
-
-/// Emit encoding to sink.
-fn put(sink: &mut MachBuffer<Inst>, enc: &[u8]) {
-    for byte in enc {
-        sink.put1(*byte);
-    }
-}
-
-/// Emit encoding to sink, adding a trap on the last byte.
-fn put_with_trap(sink: &mut MachBuffer<Inst>, enc: &[u8], srcloc: SourceLoc, trap_code: TrapCode) {
-    let len = enc.len();
-    for i in 0..len - 1 {
-        sink.put1(enc[i]);
-    }
-    sink.add_trap(srcloc, trap_code);
-    sink.put1(enc[len - 1]);
-}
-
-/// Emit encoding to sink, adding a relocation at byte offset.
-fn put_with_reloc(
-    sink: &mut MachBuffer<Inst>,
-    enc: &[u8],
-    offset: usize,
-    ri2_srcloc: SourceLoc,
-    ri2_reloc: Reloc,
-    ri2_name: &ExternalName,
-    ri2_offset: i64,
-) {
-    let len = enc.len();
-    for i in 0..offset {
-        sink.put1(enc[i]);
-    }
-    sink.add_reloc(ri2_srcloc, ri2_reloc, ri2_name, ri2_offset + offset as i64);
-    for i in offset..len {
-        sink.put1(enc[i]);
-    }
-}
-
-/// State carried between emissions of a sequence of instructions.
-#[derive(Default, Clone, Debug)]
-pub struct EmitState {
-    pub(crate) initial_sp_offset: i64,
-    pub(crate) virtual_sp_offset: i64,
-    /// Safepoint stack map for upcoming instruction, as provided to `pre_safepoint()`.
-    stack_map: Option<StackMap>,
-    /// Current source-code location corresponding to instruction to be emitted.
-    cur_srcloc: SourceLoc,
-}
-
-impl MachInstEmitState<Inst> for EmitState {
-    fn new(abi: &dyn ABICallee<I = Inst>) -> Self {
-        EmitState {
-            virtual_sp_offset: 0,
-            initial_sp_offset: abi.frame_size() as i64,
-            stack_map: None,
-            cur_srcloc: SourceLoc::default(),
-        }
-    }
-
-    fn pre_safepoint(&mut self, stack_map: StackMap) {
-        self.stack_map = Some(stack_map);
-    }
-
-    fn pre_sourceloc(&mut self, srcloc: SourceLoc) {
-        self.cur_srcloc = srcloc;
-    }
-}
-
-impl EmitState {
-    fn take_stack_map(&mut self) -> Option<StackMap> {
-        self.stack_map.take()
-    }
-
-    fn clear_post_insn(&mut self) {
-        self.stack_map = None;
-    }
-
-    fn cur_srcloc(&self) -> SourceLoc {
-        self.cur_srcloc
-    }
-}
-
-/// Constant state used during function compilation.
-pub struct EmitInfo {
-    flags: settings::Flags,
-    isa_flags: s390x_settings::Flags,
-}
-
-impl EmitInfo {
-    pub(crate) fn new(flags: settings::Flags, isa_flags: s390x_settings::Flags) -> Self {
-        Self { flags, isa_flags }
-    }
-}
-
-impl MachInstEmit for Inst {
-    type State = EmitState;
-    type Info = EmitInfo;
-
-    fn emit(&self, sink: &mut MachBuffer<Inst>, emit_info: &Self::Info, state: &mut EmitState) {
-        // Verify that we can emit this Inst in the current ISA
-        let matches_isa_flags = |iset_requirement: &InstructionSet| -> bool {
-            match iset_requirement {
-                // Baseline ISA is z14
-                InstructionSet::Base => true,
-                // Miscellaneous-Instruction-Extensions Facility 2 (z15)
-                InstructionSet::MIE2 => emit_info.isa_flags.has_mie2(),
-                // Vector-Enhancements Facility 2 (z15)
-                InstructionSet::VXRS_EXT2 => emit_info.isa_flags.has_vxrs_ext2(),
-            }
-        };
-        let isa_requirements = self.available_in_isa();
-        if !matches_isa_flags(&isa_requirements) {
-            panic!(
-                "Cannot emit inst '{:?}' for target; failed to match ISA requirements: {:?}",
-                self, isa_requirements
-            )
-        }
-
-        // N.B.: we *must* not exceed the "worst-case size" used to compute
-        // where to insert islands, except when islands are explicitly triggered
-        // (with an `EmitIsland`). We check this in debug builds. This is `mut`
-        // to allow disabling the check for `JTSequence`, which is always
-        // emitted following an `EmitIsland`.
-        let mut start_off = sink.cur_offset();
-
-        match self {
-            &Inst::AluRRR { alu_op, rd, rn, rm } => {
-                let (opcode, have_rr) = match alu_op {
-                    ALUOp::Add32 => (0xb9f8, true),        // ARK
-                    ALUOp::Add64 => (0xb9e8, true),        // AGRK
-                    ALUOp::AddLogical32 => (0xb9fa, true), // ALRK
-                    ALUOp::AddLogical64 => (0xb9ea, true), // ALGRK
-                    ALUOp::Sub32 => (0xb9f9, true),        // SRK
-                    ALUOp::Sub64 => (0xb9e9, true),        // SGRK
-                    ALUOp::SubLogical32 => (0xb9fb, true), // SLRK
-                    ALUOp::SubLogical64 => (0xb9eb, true), // SLGRK
-                    ALUOp::Mul32 => (0xb9fd, true),        // MSRKC
-                    ALUOp::Mul64 => (0xb9ed, true),        // MSGRKC
-                    ALUOp::And32 => (0xb9f4, true),        // NRK
-                    ALUOp::And64 => (0xb9e4, true),        // NGRK
-                    ALUOp::Orr32 => (0xb9f6, true),        // ORK
-                    ALUOp::Orr64 => (0xb9e6, true),        // OGRK
-                    ALUOp::Xor32 => (0xb9f7, true),        // XRK
-                    ALUOp::Xor64 => (0xb9e7, true),        // XGRK
-                    ALUOp::AndNot32 => (0xb974, false),    // NNRK
-                    ALUOp::AndNot64 => (0xb964, false),    // NNGRK
-                    ALUOp::OrrNot32 => (0xb976, false),    // NORK
-                    ALUOp::OrrNot64 => (0xb966, false),    // NOGRK
-                    ALUOp::XorNot32 => (0xb977, false),    // NXRK
-                    ALUOp::XorNot64 => (0xb967, false),    // NXGRK
-                    _ => unreachable!(),
-                };
-                if have_rr && rd.to_reg() == rn {
-                    let inst = Inst::AluRR { alu_op, rd, rm };
-                    inst.emit(sink, emit_info, state);
-                } else {
-                    put(sink, &enc_rrf_ab(opcode, rd.to_reg(), rn, rm, 0));
-                }
-            }
-            &Inst::AluRRSImm16 {
-                alu_op,
-                rd,
-                rn,
-                imm,
-            } => {
-                if rd.to_reg() == rn {
-                    let inst = Inst::AluRSImm16 { alu_op, rd, imm };
-                    inst.emit(sink, emit_info, state);
-                } else {
-                    let opcode = match alu_op {
-                        ALUOp::Add32 => 0xecd8, // AHIK
-                        ALUOp::Add64 => 0xecd9, // AGHIK
-                        _ => unreachable!(),
-                    };
-                    put(sink, &enc_rie_d(opcode, rd.to_reg(), rn, imm as u16));
-                }
-            }
-            &Inst::AluRR { alu_op, rd, rm } => {
-                let (opcode, is_rre) = match alu_op {
-                    ALUOp::Add32 => (0x1a, false),              // AR
-                    ALUOp::Add64 => (0xb908, true),             // AGR
-                    ALUOp::Add64Ext32 => (0xb918, true),        // AGFR
-                    ALUOp::AddLogical32 => (0x1e, false),       // ALR
-                    ALUOp::AddLogical64 => (0xb90a, true),      // ALGR
-                    ALUOp::AddLogical64Ext32 => (0xb91a, true), // ALGFR
-                    ALUOp::Sub32 => (0x1b, false),              // SR
-                    ALUOp::Sub64 => (0xb909, true),             // SGR
-                    ALUOp::Sub64Ext32 => (0xb919, true),        // SGFR
-                    ALUOp::SubLogical32 => (0x1f, false),       // SLR
-                    ALUOp::SubLogical64 => (0xb90b, true),      // SLGR
-                    ALUOp::SubLogical64Ext32 => (0xb91b, true), // SLGFR
-                    ALUOp::Mul32 => (0xb252, true),             // MSR
-                    ALUOp::Mul64 => (0xb90c, true),             // MSGR
-                    ALUOp::Mul64Ext32 => (0xb91c, true),        // MSGFR
-                    ALUOp::And32 => (0x14, false),              // NR
-                    ALUOp::And64 => (0xb980, true),             // NGR
-                    ALUOp::Orr32 => (0x16, false),              // OR
-                    ALUOp::Orr64 => (0xb981, true),             // OGR
-                    ALUOp::Xor32 => (0x17, false),              // XR
-                    ALUOp::Xor64 => (0xb982, true),             // XGR
-                    _ => unreachable!(),
-                };
-                if is_rre {
-                    put(sink, &enc_rre(opcode, rd.to_reg(), rm));
-                } else {
-                    put(sink, &enc_rr(opcode, rd.to_reg(), rm));
-                }
-            }
-            &Inst::AluRX {
-                alu_op,
-                rd,
-                ref mem,
-            } => {
-                let (opcode_rx, opcode_rxy) = match alu_op {
-                    ALUOp::Add32 => (Some(0x5a), Some(0xe35a)),        // A(Y)
-                    ALUOp::Add32Ext16 => (Some(0x4a), Some(0xe34a)),   // AH(Y)
-                    ALUOp::Add64 => (None, Some(0xe308)),              // AG
-                    ALUOp::Add64Ext16 => (None, Some(0xe338)),         // AGH
-                    ALUOp::Add64Ext32 => (None, Some(0xe318)),         // AGF
-                    ALUOp::AddLogical32 => (Some(0x5e), Some(0xe35e)), // AL(Y)
-                    ALUOp::AddLogical64 => (None, Some(0xe30a)),       // ALG
-                    ALUOp::AddLogical64Ext32 => (None, Some(0xe31a)),  // ALGF
-                    ALUOp::Sub32 => (Some(0x5b), Some(0xe35b)),        // S(Y)
-                    ALUOp::Sub32Ext16 => (Some(0x4b), Some(0xe37b)),   // SH(Y)
-                    ALUOp::Sub64 => (None, Some(0xe309)),              // SG
-                    ALUOp::Sub64Ext16 => (None, Some(0xe339)),         // SGH
-                    ALUOp::Sub64Ext32 => (None, Some(0xe319)),         // SGF
-                    ALUOp::SubLogical32 => (Some(0x5f), Some(0xe35f)), // SL(Y)
-                    ALUOp::SubLogical64 => (None, Some(0xe30b)),       // SLG
-                    ALUOp::SubLogical64Ext32 => (None, Some(0xe31b)),  // SLGF
-                    ALUOp::Mul32 => (Some(0x71), Some(0xe351)),        // MS(Y)
-                    ALUOp::Mul32Ext16 => (Some(0x4c), Some(0xe37c)),   // MH(Y)
-                    ALUOp::Mul64 => (None, Some(0xe30c)),              // MSG
-                    ALUOp::Mul64Ext16 => (None, Some(0xe33c)),         // MSH
-                    ALUOp::Mul64Ext32 => (None, Some(0xe31c)),         // MSGF
-                    ALUOp::And32 => (Some(0x54), Some(0xe354)),        // N(Y)
-                    ALUOp::And64 => (None, Some(0xe380)),              // NG
-                    ALUOp::Orr32 => (Some(0x56), Some(0xe356)),        // O(Y)
-                    ALUOp::Orr64 => (None, Some(0xe381)),              // OG
-                    ALUOp::Xor32 => (Some(0x57), Some(0xe357)),        // X(Y)
-                    ALUOp::Xor64 => (None, Some(0xe382)),              // XG
-                    _ => unreachable!(),
-                };
-                let rd = rd.to_reg();
-                mem_emit(
-                    rd, mem, opcode_rx, opcode_rxy, None, true, sink, emit_info, state,
-                );
-            }
-            &Inst::AluRSImm16 { alu_op, rd, imm } => {
-                let opcode = match alu_op {
-                    ALUOp::Add32 => 0xa7a, // AHI
-                    ALUOp::Add64 => 0xa7b, // AGHI
-                    ALUOp::Mul32 => 0xa7c, // MHI
-                    ALUOp::Mul64 => 0xa7d, // MGHI
-                    _ => unreachable!(),
-                };
-                put(sink, &enc_ri_a(opcode, rd.to_reg(), imm as u16));
-            }
-            &Inst::AluRSImm32 { alu_op, rd, imm } => {
-                let opcode = match alu_op {
-                    ALUOp::Add32 => 0xc29, // AFI
-                    ALUOp::Add64 => 0xc28, // AGFI
-                    ALUOp::Mul32 => 0xc21, // MSFI
-                    ALUOp::Mul64 => 0xc20, // MSGFI
-                    _ => unreachable!(),
-                };
-                put(sink, &enc_ril_a(opcode, rd.to_reg(), imm as u32));
-            }
-            &Inst::AluRUImm32 { alu_op, rd, imm } => {
-                let opcode = match alu_op {
-                    ALUOp::AddLogical32 => 0xc2b, // ALFI
-                    ALUOp::AddLogical64 => 0xc2a, // ALGFI
-                    ALUOp::SubLogical32 => 0xc25, // SLFI
-                    ALUOp::SubLogical64 => 0xc24, // SLGFI
-                    _ => unreachable!(),
-                };
-                put(sink, &enc_ril_a(opcode, rd.to_reg(), imm));
-            }
-            &Inst::AluRUImm16Shifted { alu_op, rd, imm } => {
-                let opcode = match (alu_op, imm.shift) {
-                    (ALUOp::And32, 0) => 0xa57, // NILL
-                    (ALUOp::And32, 1) => 0xa56, // NILH
-                    (ALUOp::And64, 0) => 0xa57, // NILL
-                    (ALUOp::And64, 1) => 0xa56, // NILH
-                    (ALUOp::And64, 2) => 0xa55, // NIHL
-                    (ALUOp::And64, 3) => 0xa54, // NIHL
-                    (ALUOp::Orr32, 0) => 0xa5b, // OILL
-                    (ALUOp::Orr32, 1) => 0xa5a, // OILH
-                    (ALUOp::Orr64, 0) => 0xa5b, // OILL
-                    (ALUOp::Orr64, 1) => 0xa5a, // OILH
-                    (ALUOp::Orr64, 2) => 0xa59, // OIHL
-                    (ALUOp::Orr64, 3) => 0xa58, // OIHH
-                    _ => unreachable!(),
-                };
-                put(sink, &enc_ri_a(opcode, rd.to_reg(), imm.bits));
-            }
-            &Inst::AluRUImm32Shifted { alu_op, rd, imm } => {
-                let opcode = match (alu_op, imm.shift) {
-                    (ALUOp::And32, 0) => 0xc0b, // NILF
-                    (ALUOp::And64, 0) => 0xc0b, // NILF
-                    (ALUOp::And64, 1) => 0xc0a, // NIHF
-                    (ALUOp::Orr32, 0) => 0xc0d, // OILF
-                    (ALUOp::Orr64, 0) => 0xc0d, // OILF
-                    (ALUOp::Orr64, 1) => 0xc0c, // OILF
-                    (ALUOp::Xor32, 0) => 0xc07, // XILF
-                    (ALUOp::Xor64, 0) => 0xc07, // XILF
-                    (ALUOp::Xor64, 1) => 0xc06, // XILH
-                    _ => unreachable!(),
-                };
-                put(sink, &enc_ril_a(opcode, rd.to_reg(), imm.bits));
-            }
-
-            &Inst::SMulWide { rn, rm } => {
-                let opcode = 0xb9ec; // MGRK
-                put(sink, &enc_rrf_ab(opcode, gpr(0), rn, rm, 0));
-            }
-            &Inst::UMulWide { rn } => {
-                let opcode = 0xb986; // MLGR
-                put(sink, &enc_rre(opcode, gpr(0), rn));
-            }
-            &Inst::SDivMod32 { rn } => {
-                let opcode = 0xb91d; // DSGFR
-                let srcloc = state.cur_srcloc();
-                let trap_code = TrapCode::IntegerDivisionByZero;
-                put_with_trap(sink, &enc_rre(opcode, gpr(0), rn), srcloc, trap_code);
-            }
-            &Inst::SDivMod64 { rn } => {
-                let opcode = 0xb90d; // DSGR
-                let srcloc = state.cur_srcloc();
-                let trap_code = TrapCode::IntegerDivisionByZero;
-                put_with_trap(sink, &enc_rre(opcode, gpr(0), rn), srcloc, trap_code);
-            }
-            &Inst::UDivMod32 { rn } => {
-                let opcode = 0xb997; // DLR
-                let srcloc = state.cur_srcloc();
-                let trap_code = TrapCode::IntegerDivisionByZero;
-                put_with_trap(sink, &enc_rre(opcode, gpr(0), rn), srcloc, trap_code);
-            }
-            &Inst::UDivMod64 { rn } => {
-                let opcode = 0xb987; // DLGR
-                let srcloc = state.cur_srcloc();
-                let trap_code = TrapCode::IntegerDivisionByZero;
-                put_with_trap(sink, &enc_rre(opcode, gpr(0), rn), srcloc, trap_code);
-            }
-            &Inst::Flogr { rn } => {
-                let opcode = 0xb983; // FLOGR
-                put(sink, &enc_rre(opcode, gpr(0), rn));
-            }
-
-            &Inst::ShiftRR {
-                shift_op,
-                rd,
-                rn,
-                shift_imm,
-                shift_reg,
-            } => {
-                let opcode = match shift_op {
-                    ShiftOp::RotL32 => 0xeb1d, // RLL
-                    ShiftOp::RotL64 => 0xeb1c, // RLLG
-                    ShiftOp::LShL32 => 0xebdf, // SLLK  (SLL ?)
-                    ShiftOp::LShL64 => 0xeb0d, // SLLG
-                    ShiftOp::LShR32 => 0xebde, // SRLK  (SRL ?)
-                    ShiftOp::LShR64 => 0xeb0c, // SRLG
-                    ShiftOp::AShR32 => 0xebdc, // SRAK  (SRA ?)
-                    ShiftOp::AShR64 => 0xeb0a, // SRAG
-                };
-                put(
-                    sink,
-                    &enc_rsy(opcode, rd.to_reg(), rn, shift_reg, shift_imm.into()),
-                );
-            }
-
-            &Inst::RxSBG {
-                op,
-                rd,
-                rn,
-                start_bit,
-                end_bit,
-                rotate_amt,
-            } => {
-                let opcode = match op {
-                    RxSBGOp::Insert => 0xec59, // RISBGN
-                    RxSBGOp::And => 0xec54,    // RNSBG
-                    RxSBGOp::Or => 0xec56,     // ROSBG
-                    RxSBGOp::Xor => 0xec57,    // RXSBG
-                };
-                put(
-                    sink,
-                    &enc_rie_f(
-                        opcode,
-                        rd.to_reg(),
-                        rn,
-                        start_bit,
-                        end_bit,
-                        (rotate_amt as u8) & 63,
-                    ),
-                );
-            }
-
-            &Inst::RxSBGTest {
-                op,
-                rd,
-                rn,
-                start_bit,
-                end_bit,
-                rotate_amt,
-            } => {
-                let opcode = match op {
-                    RxSBGOp::And => 0xec54, // RNSBG
-                    RxSBGOp::Or => 0xec56,  // ROSBG
-                    RxSBGOp::Xor => 0xec57, // RXSBG
-                    _ => unreachable!(),
-                };
-                put(
-                    sink,
-                    &enc_rie_f(
-                        opcode,
-                        rd,
-                        rn,
-                        start_bit | 0x80,
-                        end_bit,
-                        (rotate_amt as u8) & 63,
-                    ),
-                );
-            }
-
-            &Inst::UnaryRR { op, rd, rn } => {
-                match op {
-                    UnaryOp::Abs32 => {
-                        let opcode = 0x10; // LPR
-                        put(sink, &enc_rr(opcode, rd.to_reg(), rn));
-                    }
-                    UnaryOp::Abs64 => {
-                        let opcode = 0xb900; // LPGR
-                        put(sink, &enc_rre(opcode, rd.to_reg(), rn));
-                    }
-                    UnaryOp::Abs64Ext32 => {
-                        let opcode = 0xb910; // LPGFR
-                        put(sink, &enc_rre(opcode, rd.to_reg(), rn));
-                    }
-                    UnaryOp::Neg32 => {
-                        let opcode = 0x13; // LCR
-                        put(sink, &enc_rr(opcode, rd.to_reg(), rn));
-                    }
-                    UnaryOp::Neg64 => {
-                        let opcode = 0xb903; // LCGR
-                        put(sink, &enc_rre(opcode, rd.to_reg(), rn));
-                    }
-                    UnaryOp::Neg64Ext32 => {
-                        let opcode = 0xb913; // LCGFR
-                        put(sink, &enc_rre(opcode, rd.to_reg(), rn));
-                    }
-                    UnaryOp::PopcntByte => {
-                        let opcode = 0xb9e1; // POPCNT
-                        put(sink, &enc_rrf_cde(opcode, rd.to_reg(), rn, 0, 0));
-                    }
-                    UnaryOp::PopcntReg => {
-                        let opcode = 0xb9e1; // POPCNT
-                        put(sink, &enc_rrf_cde(opcode, rd.to_reg(), rn, 8, 0));
-                    }
-                    UnaryOp::BSwap32 => {
-                        let opcode = 0xb91f; // LRVR
-                        put(sink, &enc_rre(opcode, rd.to_reg(), rn));
-                    }
-                    UnaryOp::BSwap64 => {
-                        let opcode = 0xb90f; // LRVRG
-                        put(sink, &enc_rre(opcode, rd.to_reg(), rn));
-                    }
-                }
-            }
-
-            &Inst::Extend {
-                rd,
-                rn,
-                signed,
-                from_bits,
-                to_bits,
-            } => {
-                let opcode = match (signed, from_bits, to_bits) {
-                    (_, 1, 32) => 0xb926,      // LBR
-                    (_, 1, 64) => 0xb906,      // LGBR
-                    (false, 8, 32) => 0xb994,  // LLCR
-                    (false, 8, 64) => 0xb984,  // LLGCR
-                    (true, 8, 32) => 0xb926,   // LBR
-                    (true, 8, 64) => 0xb906,   // LGBR
-                    (false, 16, 32) => 0xb995, // LLHR
-                    (false, 16, 64) => 0xb985, // LLGHR
-                    (true, 16, 32) => 0xb927,  // LHR
-                    (true, 16, 64) => 0xb907,  // LGHR
-                    (false, 32, 64) => 0xb916, // LLGFR
-                    (true, 32, 64) => 0xb914,  // LGFR
-                    _ => panic!(
-                        "Unsupported extend combination: signed = {}, from_bits = {}, to_bits = {}",
-                        signed, from_bits, to_bits
-                    ),
-                };
-                put(sink, &enc_rre(opcode, rd.to_reg(), rn));
-            }
-
-            &Inst::CmpRR { op, rn, rm } => {
-                let (opcode, is_rre) = match op {
-                    CmpOp::CmpS32 => (0x19, false),       // CR
-                    CmpOp::CmpS64 => (0xb920, true),      // CGR
-                    CmpOp::CmpS64Ext32 => (0xb930, true), // CGFR
-                    CmpOp::CmpL32 => (0x15, false),       // CLR
-                    CmpOp::CmpL64 => (0xb921, true),      // CLGR
-                    CmpOp::CmpL64Ext32 => (0xb931, true), // CLGFR
-                    _ => unreachable!(),
-                };
-                if is_rre {
-                    put(sink, &enc_rre(opcode, rn, rm));
-                } else {
-                    put(sink, &enc_rr(opcode, rn, rm));
-                }
-            }
-            &Inst::CmpRX { op, rn, ref mem } => {
-                let (opcode_rx, opcode_rxy, opcode_ril) = match op {
-                    CmpOp::CmpS32 => (Some(0x59), Some(0xe359), Some(0xc6d)), // C(Y), CRL
-                    CmpOp::CmpS32Ext16 => (Some(0x49), Some(0xe379), Some(0xc65)), // CH(Y), CHRL
-                    CmpOp::CmpS64 => (None, Some(0xe320), Some(0xc68)),       // CG, CGRL
-                    CmpOp::CmpS64Ext16 => (None, Some(0xe334), Some(0xc64)),  // CGH, CGHRL
-                    CmpOp::CmpS64Ext32 => (None, Some(0xe330), Some(0xc6c)),  // CGF, CGFRL
-                    CmpOp::CmpL32 => (Some(0x55), Some(0xe355), Some(0xc6f)), // CL(Y), CLRL
-                    CmpOp::CmpL32Ext16 => (None, None, Some(0xc67)),          // CLHRL
-                    CmpOp::CmpL64 => (None, Some(0xe321), Some(0xc6a)),       // CLG, CLGRL
-                    CmpOp::CmpL64Ext16 => (None, None, Some(0xc66)),          // CLGHRL
-                    CmpOp::CmpL64Ext32 => (None, Some(0xe331), Some(0xc6e)),  // CLGF, CLGFRL
-                };
-                mem_emit(
-                    rn, mem, opcode_rx, opcode_rxy, opcode_ril, true, sink, emit_info, state,
-                );
-            }
-            &Inst::CmpRSImm16 { op, rn, imm } => {
-                let opcode = match op {
-                    CmpOp::CmpS32 => 0xa7e, // CHI
-                    CmpOp::CmpS64 => 0xa7f, // CGHI
-                    _ => unreachable!(),
-                };
-                put(sink, &enc_ri_a(opcode, rn, imm as u16));
-            }
-            &Inst::CmpRSImm32 { op, rn, imm } => {
-                let opcode = match op {
-                    CmpOp::CmpS32 => 0xc2d, // CFI
-                    CmpOp::CmpS64 => 0xc2c, // CGFI
-                    _ => unreachable!(),
-                };
-                put(sink, &enc_ril_a(opcode, rn, imm as u32));
-            }
-            &Inst::CmpRUImm32 { op, rn, imm } => {
-                let opcode = match op {
-                    CmpOp::CmpL32 => 0xc2f, // CLFI
-                    CmpOp::CmpL64 => 0xc2e, // CLGFI
-                    _ => unreachable!(),
-                };
-                put(sink, &enc_ril_a(opcode, rn, imm));
-            }
-            &Inst::CmpTrapRR {
-                op,
-                rn,
-                rm,
-                cond,
-                trap_code,
-            } => {
-                let opcode = match op {
-                    CmpOp::CmpS32 => 0xb972, // CRT
-                    CmpOp::CmpS64 => 0xb960, // CGRT
-                    CmpOp::CmpL32 => 0xb973, // CLRT
-                    CmpOp::CmpL64 => 0xb961, // CLGRT
-                    _ => unreachable!(),
-                };
-                let srcloc = state.cur_srcloc();
-                put_with_trap(
-                    sink,
-                    &enc_rrf_cde(opcode, rn, rm, cond.bits(), 0),
-                    srcloc,
-                    trap_code,
-                );
-            }
-            &Inst::CmpTrapRSImm16 {
-                op,
-                rn,
-                imm,
-                cond,
-                trap_code,
-            } => {
-                let opcode = match op {
-                    CmpOp::CmpS32 => 0xec72, // CIT
-                    CmpOp::CmpS64 => 0xec70, // CGIT
-                    _ => unreachable!(),
-                };
-                let srcloc = state.cur_srcloc();
-                put_with_trap(
-                    sink,
-                    &enc_rie_a(opcode, rn, imm as u16, cond.bits()),
-                    srcloc,
-                    trap_code,
-                );
-            }
-            &Inst::CmpTrapRUImm16 {
-                op,
-                rn,
-                imm,
-                cond,
-                trap_code,
-            } => {
-                let opcode = match op {
-                    CmpOp::CmpL32 => 0xec73, // CLFIT
-                    CmpOp::CmpL64 => 0xec71, // CLGIT
-                    _ => unreachable!(),
-                };
-                let srcloc = state.cur_srcloc();
-                put_with_trap(
-                    sink,
-                    &enc_rie_a(opcode, rn, imm, cond.bits()),
-                    srcloc,
-                    trap_code,
-                );
-            }
-
-            &Inst::AtomicRmw {
-                alu_op,
-                rd,
-                rn,
-                ref mem,
-            } => {
-                let opcode = match alu_op {
-                    ALUOp::Add32 => 0xebf8,        // LAA
-                    ALUOp::Add64 => 0xebe8,        // LAAG
-                    ALUOp::AddLogical32 => 0xebfa, // LAAL
-                    ALUOp::AddLogical64 => 0xebea, // LAALG
-                    ALUOp::And32 => 0xebf4,        // LAN
-                    ALUOp::And64 => 0xebe4,        // LANG
-                    ALUOp::Orr32 => 0xebf6,        // LAO
-                    ALUOp::Orr64 => 0xebe6,        // LAOG
-                    ALUOp::Xor32 => 0xebf7,        // LAX
-                    ALUOp::Xor64 => 0xebe7,        // LAXG
-                    _ => unreachable!(),
-                };
-
-                let rd = rd.to_reg();
-                mem_rs_emit(
-                    rd,
-                    rn,
-                    mem,
-                    None,
-                    Some(opcode),
-                    true,
-                    sink,
-                    emit_info,
-                    state,
-                );
-            }
-            &Inst::Loop { ref body, cond } => {
-                // This sequence is *one* instruction in the vcode, and is expanded only here at
-                // emission time, because it requires branching to internal labels.
-                let loop_label = sink.get_label();
-                let done_label = sink.get_label();
-
-                // Emit label at the start of the loop.
-                sink.bind_label(loop_label);
-
-                for inst in (&body).into_iter() {
-                    match &inst {
-                        // Replace a CondBreak with a branch to done_label.
-                        &Inst::CondBreak { cond } => {
-                            let inst = Inst::OneWayCondBr {
-                                target: done_label,
-                                cond: *cond,
-                            };
-                            inst.emit(sink, emit_info, state);
-                        }
-                        _ => inst.emit(sink, emit_info, state),
-                    };
-                }
-
-                let inst = Inst::OneWayCondBr {
-                    target: loop_label,
-                    cond,
-                };
-                inst.emit(sink, emit_info, state);
-
-                // Emit label at the end of the loop.
-                sink.bind_label(done_label);
-            }
-            &Inst::CondBreak { .. } => unreachable!(), // Only valid inside a Loop.
-            &Inst::AtomicCas32 { rd, rn, ref mem } | &Inst::AtomicCas64 { rd, rn, ref mem } => {
-                let (opcode_rs, opcode_rsy) = match self {
-                    &Inst::AtomicCas32 { .. } => (Some(0xba), Some(0xeb14)), // CS(Y)
-                    &Inst::AtomicCas64 { .. } => (None, Some(0xeb30)),       // CSG
-                    _ => unreachable!(),
-                };
-
-                let rd = rd.to_reg();
-                mem_rs_emit(
-                    rd, rn, mem, opcode_rs, opcode_rsy, true, sink, emit_info, state,
-                );
-            }
-            &Inst::Fence => {
-                put(sink, &enc_e(0x07e0));
-            }
-
-            &Inst::Load32 { rd, ref mem }
-            | &Inst::Load32ZExt8 { rd, ref mem }
-            | &Inst::Load32SExt8 { rd, ref mem }
-            | &Inst::Load32ZExt16 { rd, ref mem }
-            | &Inst::Load32SExt16 { rd, ref mem }
-            | &Inst::Load64 { rd, ref mem }
-            | &Inst::Load64ZExt8 { rd, ref mem }
-            | &Inst::Load64SExt8 { rd, ref mem }
-            | &Inst::Load64ZExt16 { rd, ref mem }
-            | &Inst::Load64SExt16 { rd, ref mem }
-            | &Inst::Load64ZExt32 { rd, ref mem }
-            | &Inst::Load64SExt32 { rd, ref mem }
-            | &Inst::LoadRev16 { rd, ref mem }
-            | &Inst::LoadRev32 { rd, ref mem }
-            | &Inst::LoadRev64 { rd, ref mem }
-            | &Inst::FpuLoad32 { rd, ref mem }
-            | &Inst::FpuLoad64 { rd, ref mem } => {
-                let (opcode_rx, opcode_rxy, opcode_ril) = match self {
-                    &Inst::Load32 { .. } => (Some(0x58), Some(0xe358), Some(0xc4d)), // L(Y), LRL
-                    &Inst::Load32ZExt8 { .. } => (None, Some(0xe394), None),         // LLC
-                    &Inst::Load32SExt8 { .. } => (None, Some(0xe376), None),         // LB
-                    &Inst::Load32ZExt16 { .. } => (None, Some(0xe395), Some(0xc42)), // LLH, LLHRL
-                    &Inst::Load32SExt16 { .. } => (Some(0x48), Some(0xe378), Some(0xc45)), // LH(Y), LHRL
-                    &Inst::Load64 { .. } => (None, Some(0xe304), Some(0xc48)), // LG, LGRL
-                    &Inst::Load64ZExt8 { .. } => (None, Some(0xe390), None),   // LLGC
-                    &Inst::Load64SExt8 { .. } => (None, Some(0xe377), None),   // LGB
-                    &Inst::Load64ZExt16 { .. } => (None, Some(0xe391), Some(0xc46)), // LLGH, LLGHRL
-                    &Inst::Load64SExt16 { .. } => (None, Some(0xe315), Some(0xc44)), // LGH, LGHRL
-                    &Inst::Load64ZExt32 { .. } => (None, Some(0xe316), Some(0xc4e)), // LLGF, LLGFRL
-                    &Inst::Load64SExt32 { .. } => (None, Some(0xe314), Some(0xc4c)), // LGF, LGFRL
-                    &Inst::LoadRev16 { .. } => (None, Some(0xe31f), None),     // LRVH
-                    &Inst::LoadRev32 { .. } => (None, Some(0xe31e), None),     // LRV
-                    &Inst::LoadRev64 { .. } => (None, Some(0xe30f), None),     // LRVG
-                    &Inst::FpuLoad32 { .. } => (Some(0x78), Some(0xed64), None), // LE(Y)
-                    &Inst::FpuLoad64 { .. } => (Some(0x68), Some(0xed65), None), // LD(Y)
-                    _ => unreachable!(),
-                };
-                let rd = rd.to_reg();
-                mem_emit(
-                    rd, mem, opcode_rx, opcode_rxy, opcode_ril, true, sink, emit_info, state,
-                );
-            }
-            &Inst::FpuLoadRev32 { rd, ref mem } | &Inst::FpuLoadRev64 { rd, ref mem } => {
-                let opcode = match self {
-                    &Inst::FpuLoadRev32 { .. } => 0xe603, // VLEBRF
-                    &Inst::FpuLoadRev64 { .. } => 0xe602, // VLEBRG
-                    _ => unreachable!(),
-                };
-
-                let (mem_insts, mem) = mem_finalize(mem, state, true, false, false, true);
-                for inst in mem_insts.into_iter() {
-                    inst.emit(sink, emit_info, state);
-                }
-
-                let srcloc = state.cur_srcloc();
-                if srcloc != SourceLoc::default() && mem.can_trap() {
-                    sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
-                }
-
-                match &mem {
-                    &MemArg::BXD12 {
-                        base, index, disp, ..
-                    } => {
-                        put(
-                            sink,
-                            &enc_vrx(opcode, rd.to_reg(), base, index, disp.bits(), 0),
-                        );
-                    }
-                    _ => unreachable!(),
-                }
-            }
-
-            &Inst::Store8 { rd, ref mem }
-            | &Inst::Store16 { rd, ref mem }
-            | &Inst::Store32 { rd, ref mem }
-            | &Inst::Store64 { rd, ref mem }
-            | &Inst::StoreRev16 { rd, ref mem }
-            | &Inst::StoreRev32 { rd, ref mem }
-            | &Inst::StoreRev64 { rd, ref mem }
-            | &Inst::FpuStore32 { rd, ref mem }
-            | &Inst::FpuStore64 { rd, ref mem } => {
-                let (opcode_rx, opcode_rxy, opcode_ril) = match self {
-                    &Inst::Store8 { .. } => (Some(0x42), Some(0xe372), None), // STC(Y)
-                    &Inst::Store16 { .. } => (Some(0x40), Some(0xe370), Some(0xc47)), // STH(Y), STHRL
-                    &Inst::Store32 { .. } => (Some(0x50), Some(0xe350), Some(0xc4f)), // ST(Y), STRL
-                    &Inst::Store64 { .. } => (None, Some(0xe324), Some(0xc4b)),       // STG, STGRL
-                    &Inst::StoreRev16 { .. } => (None, Some(0xe33f), None),           // STRVH
-                    &Inst::StoreRev32 { .. } => (None, Some(0xe33e), None),           // STRV
-                    &Inst::StoreRev64 { .. } => (None, Some(0xe32f), None),           // STRVG
-                    &Inst::FpuStore32 { .. } => (Some(0x70), Some(0xed66), None),     // STE(Y)
-                    &Inst::FpuStore64 { .. } => (Some(0x60), Some(0xed67), None),     // STD(Y)
-                    _ => unreachable!(),
-                };
-                mem_emit(
-                    rd, mem, opcode_rx, opcode_rxy, opcode_ril, true, sink, emit_info, state,
-                );
-            }
-            &Inst::StoreImm8 { imm, ref mem } => {
-                let opcode_si = 0x92; // MVI
-                let opcode_siy = 0xeb52; // MVIY
-                mem_imm8_emit(
-                    imm, mem, opcode_si, opcode_siy, true, sink, emit_info, state,
-                );
-            }
-            &Inst::StoreImm16 { imm, ref mem }
-            | &Inst::StoreImm32SExt16 { imm, ref mem }
-            | &Inst::StoreImm64SExt16 { imm, ref mem } => {
-                let opcode = match self {
-                    &Inst::StoreImm16 { .. } => 0xe544,       // MVHHI
-                    &Inst::StoreImm32SExt16 { .. } => 0xe54c, // MVHI
-                    &Inst::StoreImm64SExt16 { .. } => 0xe548, // MVGHI
-                    _ => unreachable!(),
-                };
-                mem_imm16_emit(imm, mem, opcode, true, sink, emit_info, state);
-            }
-            &Inst::FpuStoreRev32 { rd, ref mem } | &Inst::FpuStoreRev64 { rd, ref mem } => {
-                let opcode = match self {
-                    &Inst::FpuStoreRev32 { .. } => 0xe60b, // VSTEBRF
-                    &Inst::FpuStoreRev64 { .. } => 0xe60a, // VSTEBRG
-                    _ => unreachable!(),
-                };
-
-                let (mem_insts, mem) = mem_finalize(mem, state, true, false, false, true);
-                for inst in mem_insts.into_iter() {
-                    inst.emit(sink, emit_info, state);
-                }
-
-                let srcloc = state.cur_srcloc();
-                if srcloc != SourceLoc::default() && mem.can_trap() {
-                    sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
-                }
-
-                match &mem {
-                    &MemArg::BXD12 {
-                        base, index, disp, ..
-                    } => {
-                        put(sink, &enc_vrx(opcode, rd, base, index, disp.bits(), 0));
-                    }
-                    _ => unreachable!(),
-                }
-            }
-
-            &Inst::LoadMultiple64 { rt, rt2, ref mem } => {
-                let opcode = 0xeb04; // LMG
-                let rt = rt.to_reg();
-                let rt2 = rt2.to_reg();
-                mem_rs_emit(
-                    rt,
-                    rt2,
-                    &mem,
-                    None,
-                    Some(opcode),
-                    true,
-                    sink,
-                    emit_info,
-                    state,
-                );
-            }
-            &Inst::StoreMultiple64 { rt, rt2, ref mem } => {
-                let opcode = 0xeb24; // STMG
-                mem_rs_emit(
-                    rt,
-                    rt2,
-                    &mem,
-                    None,
-                    Some(opcode),
-                    true,
-                    sink,
-                    emit_info,
-                    state,
-                );
-            }
-
-            &Inst::LoadAddr { rd, ref mem } => {
-                let opcode_rx = Some(0x41); // LA
-                let opcode_rxy = Some(0xe371); // LAY
-                let opcode_ril = Some(0xc00); // LARL
-                let rd = rd.to_reg();
-                mem_emit(
-                    rd, mem, opcode_rx, opcode_rxy, opcode_ril, false, sink, emit_info, state,
-                );
-            }
-
-            &Inst::Mov64 { rd, rm } => {
-                let opcode = 0xb904; // LGR
-                put(sink, &enc_rre(opcode, rd.to_reg(), rm));
-            }
-            &Inst::Mov32 { rd, rm } => {
-                let opcode = 0x18; // LR
-                put(sink, &enc_rr(opcode, rd.to_reg(), rm));
-            }
-            &Inst::Mov32Imm { rd, imm } => {
-                let opcode = 0xc09; // IILF
-                put(sink, &enc_ril_a(opcode, rd.to_reg(), imm));
-            }
-            &Inst::Mov32SImm16 { rd, imm } => {
-                let opcode = 0xa78; // LHI
-                put(sink, &enc_ri_a(opcode, rd.to_reg(), imm as u16));
-            }
-            &Inst::Mov64SImm16 { rd, imm } => {
-                let opcode = 0xa79; // LGHI
-                put(sink, &enc_ri_a(opcode, rd.to_reg(), imm as u16));
-            }
-            &Inst::Mov64SImm32 { rd, imm } => {
-                let opcode = 0xc01; // LGFI
-                put(sink, &enc_ril_a(opcode, rd.to_reg(), imm as u32));
-            }
-            &Inst::CMov32 { rd, cond, rm } => {
-                let opcode = 0xb9f2; // LOCR
-                put(sink, &enc_rrf_cde(opcode, rd.to_reg(), rm, cond.bits(), 0));
-            }
-            &Inst::CMov64 { rd, cond, rm } => {
-                let opcode = 0xb9e2; // LOCGR
-                put(sink, &enc_rrf_cde(opcode, rd.to_reg(), rm, cond.bits(), 0));
-            }
-            &Inst::CMov32SImm16 { rd, cond, imm } => {
-                let opcode = 0xec42; // LOCHI
-                put(
-                    sink,
-                    &enc_rie_g(opcode, rd.to_reg(), imm as u16, cond.bits()),
-                );
-            }
-            &Inst::CMov64SImm16 { rd, cond, imm } => {
-                let opcode = 0xec46; // LOCGHI
-                put(
-                    sink,
-                    &enc_rie_g(opcode, rd.to_reg(), imm as u16, cond.bits()),
-                );
-            }
-            &Inst::Mov64UImm16Shifted { rd, imm } => {
-                let opcode = match imm.shift {
-                    0 => 0xa5f, // LLILL
-                    1 => 0xa5e, // LLILH
-                    2 => 0xa5d, // LLIHL
-                    3 => 0xa5c, // LLIHH
-                    _ => unreachable!(),
-                };
-                put(sink, &enc_ri_a(opcode, rd.to_reg(), imm.bits));
-            }
-            &Inst::Mov64UImm32Shifted { rd, imm } => {
-                let opcode = match imm.shift {
-                    0 => 0xc0f, // LLILF
-                    1 => 0xc0e, // LLIHF
-                    _ => unreachable!(),
-                };
-                put(sink, &enc_ril_a(opcode, rd.to_reg(), imm.bits));
-            }
-            &Inst::Insert64UImm16Shifted { rd, imm } => {
-                let opcode = match imm.shift {
-                    0 => 0xa53, // IILL
-                    1 => 0xa52, // IILH
-                    2 => 0xa51, // IIHL
-                    3 => 0xa50, // IIHH
-                    _ => unreachable!(),
-                };
-                put(sink, &enc_ri_a(opcode, rd.to_reg(), imm.bits));
-            }
-            &Inst::Insert64UImm32Shifted { rd, imm } => {
-                let opcode = match imm.shift {
-                    0 => 0xc09, // IILF
-                    1 => 0xc08, // IIHF
-                    _ => unreachable!(),
-                };
-                put(sink, &enc_ril_a(opcode, rd.to_reg(), imm.bits));
-            }
-            &Inst::LoadExtNameFar {
-                rd,
-                ref name,
-                offset,
-            } => {
-                let opcode = 0xa75; // BRAS
-                let srcloc = state.cur_srcloc();
-                let reg = writable_spilltmp_reg().to_reg();
-                put(sink, &enc_ri_b(opcode, reg, 12));
-                sink.add_reloc(srcloc, Reloc::Abs8, name, offset);
-                if emit_info.flags.emit_all_ones_funcaddrs() {
-                    sink.put8(u64::max_value());
-                } else {
-                    sink.put8(0);
-                }
-                let inst = Inst::Load64 {
-                    rd,
-                    mem: MemArg::reg(reg, MemFlags::trusted()),
-                };
-                inst.emit(sink, emit_info, state);
-            }
-
-            &Inst::FpuMove32 { rd, rn } => {
-                let opcode = 0x38; // LER
-                put(sink, &enc_rr(opcode, rd.to_reg(), rn));
-            }
-            &Inst::FpuMove64 { rd, rn } => {
-                let opcode = 0x28; // LDR
-                put(sink, &enc_rr(opcode, rd.to_reg(), rn));
-            }
-            &Inst::FpuCMov32 { rd, cond, rm } => {
-                let opcode = 0xa74; // BCR
-                put(sink, &enc_ri_c(opcode, cond.invert().bits(), 4 + 2));
-                let opcode = 0x38; // LER
-                put(sink, &enc_rr(opcode, rd.to_reg(), rm));
-            }
-            &Inst::FpuCMov64 { rd, cond, rm } => {
-                let opcode = 0xa74; // BCR
-                put(sink, &enc_ri_c(opcode, cond.invert().bits(), 4 + 2));
-                let opcode = 0x28; // LDR
-                put(sink, &enc_rr(opcode, rd.to_reg(), rm));
-            }
-            &Inst::MovToFpr { rd, rn } => {
-                let opcode = 0xb3c1; // LDGR
-                put(sink, &enc_rre(opcode, rd.to_reg(), rn));
-            }
-            &Inst::MovFromFpr { rd, rn } => {
-                let opcode = 0xb3cd; // LGDR
-                put(sink, &enc_rre(opcode, rd.to_reg(), rn));
-            }
-            &Inst::LoadFpuConst32 { rd, const_data } => {
-                let opcode = 0xa75; // BRAS
-                let reg = writable_spilltmp_reg().to_reg();
-                put(sink, &enc_ri_b(opcode, reg, 8));
-                sink.put4(const_data.swap_bytes());
-                let inst = Inst::FpuLoad32 {
-                    rd,
-                    mem: MemArg::reg(reg, MemFlags::trusted()),
-                };
-                inst.emit(sink, emit_info, state);
-            }
-            &Inst::LoadFpuConst64 { rd, const_data } => {
-                let opcode = 0xa75; // BRAS
-                let reg = writable_spilltmp_reg().to_reg();
-                put(sink, &enc_ri_b(opcode, reg, 12));
-                sink.put8(const_data.swap_bytes());
-                let inst = Inst::FpuLoad64 {
-                    rd,
-                    mem: MemArg::reg(reg, MemFlags::trusted()),
-                };
-                inst.emit(sink, emit_info, state);
-            }
-
-            &Inst::FpuCopysign { rd, rn, rm } => {
-                let opcode = 0xb372; // CPSDR
-                put(sink, &enc_rrf_ab(opcode, rd.to_reg(), rn, rm, 0));
-            }
-            &Inst::FpuRR { fpu_op, rd, rn } => {
-                let opcode = match fpu_op {
-                    FPUOp1::Abs32 => 0xb300,     // LPEBR
-                    FPUOp1::Abs64 => 0xb310,     // LPDBR
-                    FPUOp1::Neg32 => 0xb303,     // LCEBR
-                    FPUOp1::Neg64 => 0xb313,     // LCDBR
-                    FPUOp1::NegAbs32 => 0xb301,  // LNEBR
-                    FPUOp1::NegAbs64 => 0xb311,  // LNDBR
-                    FPUOp1::Sqrt32 => 0xb314,    // SQEBR
-                    FPUOp1::Sqrt64 => 0xb315,    // SQDBR
-                    FPUOp1::Cvt32To64 => 0xb304, // LDEBR
-                    FPUOp1::Cvt64To32 => 0xb344, // LEDBR
-                };
-                put(sink, &enc_rre(opcode, rd.to_reg(), rn));
-            }
-            &Inst::FpuRRR { fpu_op, rd, rm } => {
-                let opcode = match fpu_op {
-                    FPUOp2::Add32 => 0xb30a, // AEBR
-                    FPUOp2::Add64 => 0xb31a, // ADBR
-                    FPUOp2::Sub32 => 0xb30b, // SEBR
-                    FPUOp2::Sub64 => 0xb31b, // SDBR
-                    FPUOp2::Mul32 => 0xb317, // MEEBR
-                    FPUOp2::Mul64 => 0xb31c, // MDBR
-                    FPUOp2::Div32 => 0xb30d, // DEBR
-                    FPUOp2::Div64 => 0xb31d, // DDBR
-                    _ => unimplemented!(),
-                };
-                put(sink, &enc_rre(opcode, rd.to_reg(), rm));
-            }
-            &Inst::FpuRRRR { fpu_op, rd, rn, rm } => {
-                let opcode = match fpu_op {
-                    FPUOp3::MAdd32 => 0xb30e, // MAEBR
-                    FPUOp3::MAdd64 => 0xb31e, // MADBR
-                    FPUOp3::MSub32 => 0xb30f, // MSEBR
-                    FPUOp3::MSub64 => 0xb31f, // MSDBR
-                };
-                put(sink, &enc_rrd(opcode, rd.to_reg(), rm, rn));
-            }
-            &Inst::FpuToInt { op, rd, rn } => {
-                let opcode = match op {
-                    FpuToIntOp::F32ToI32 => 0xb398, // CFEBRA
-                    FpuToIntOp::F32ToU32 => 0xb39c, // CLFEBR
-                    FpuToIntOp::F32ToI64 => 0xb3a8, // CGEBRA
-                    FpuToIntOp::F32ToU64 => 0xb3ac, // CLGEBR
-                    FpuToIntOp::F64ToI32 => 0xb399, // CFDBRA
-                    FpuToIntOp::F64ToU32 => 0xb39d, // CLFDBR
-                    FpuToIntOp::F64ToI64 => 0xb3a9, // CGDBRA
-                    FpuToIntOp::F64ToU64 => 0xb3ad, // CLGDBR
-                };
-                put(sink, &enc_rrf_cde(opcode, rd.to_reg(), rn, 5, 0));
-            }
-            &Inst::IntToFpu { op, rd, rn } => {
-                let opcode = match op {
-                    IntToFpuOp::I32ToF32 => 0xb394, // CEFBRA
-                    IntToFpuOp::U32ToF32 => 0xb390, // CELFBR
-                    IntToFpuOp::I64ToF32 => 0xb3a4, // CEGBRA
-                    IntToFpuOp::U64ToF32 => 0xb3a0, // CELGBR
-                    IntToFpuOp::I32ToF64 => 0xb395, // CDFBRA
-                    IntToFpuOp::U32ToF64 => 0xb391, // CDLFBR
-                    IntToFpuOp::I64ToF64 => 0xb3a5, // CDGBRA
-                    IntToFpuOp::U64ToF64 => 0xb3a1, // CDLGBR
-                };
-                put(sink, &enc_rrf_cde(opcode, rd.to_reg(), rn, 0, 0));
-            }
-            &Inst::FpuRound { op, rd, rn } => {
-                let (opcode, m3) = match op {
-                    FpuRoundMode::Minus32 => (0xb357, 7),   // FIEBR
-                    FpuRoundMode::Minus64 => (0xb35f, 7),   // FIDBR
-                    FpuRoundMode::Plus32 => (0xb357, 6),    // FIEBR
-                    FpuRoundMode::Plus64 => (0xb35f, 6),    // FIDBR
-                    FpuRoundMode::Zero32 => (0xb357, 5),    // FIEBR
-                    FpuRoundMode::Zero64 => (0xb35f, 5),    // FIDBR
-                    FpuRoundMode::Nearest32 => (0xb357, 4), // FIEBR
-                    FpuRoundMode::Nearest64 => (0xb35f, 4), // FIDBR
-                };
-                put(sink, &enc_rrf_cde(opcode, rd.to_reg(), rn, m3, 0));
-            }
-            &Inst::FpuVecRRR { fpu_op, rd, rn, rm } => {
-                let (opcode, m4) = match fpu_op {
-                    FPUOp2::Max32 => (0xe7ef, 2), // VFMAX
-                    FPUOp2::Max64 => (0xe7ef, 3), // VFMAX
-                    FPUOp2::Min32 => (0xe7ee, 2), // VFMIN
-                    FPUOp2::Min64 => (0xe7ee, 3), // VFMIN
-                    _ => unimplemented!(),
-                };
-                put(sink, &enc_vrr(opcode, rd.to_reg(), rn, rm, m4, 8, 1));
-            }
-            &Inst::FpuCmp32 { rn, rm } => {
-                let opcode = 0xb309; // CEBR
-                put(sink, &enc_rre(opcode, rn, rm));
-            }
-            &Inst::FpuCmp64 { rn, rm } => {
-                let opcode = 0xb319; // CDBR
-                put(sink, &enc_rre(opcode, rn, rm));
-            }
-
-            &Inst::Call { link, ref info } => {
-                let opcode = 0xc05; // BRASL
-                let reloc = Reloc::S390xPCRel32Dbl;
-                let srcloc = state.cur_srcloc();
-                if let Some(s) = state.take_stack_map() {
-                    sink.add_stack_map(StackMapExtent::UpcomingBytes(6), s);
-                }
-                put_with_reloc(
-                    sink,
-                    &enc_ril_b(opcode, link.to_reg(), 0),
-                    2,
-                    srcloc,
-                    reloc,
-                    &info.dest,
-                    0,
-                );
-                if info.opcode.is_call() {
-                    sink.add_call_site(srcloc, info.opcode);
-                }
-            }
-            &Inst::CallInd { link, ref info } => {
-                let opcode = 0x0d; // BASR
-                let srcloc = state.cur_srcloc();
-                if let Some(s) = state.take_stack_map() {
-                    sink.add_stack_map(StackMapExtent::UpcomingBytes(2), s);
-                }
-                put(sink, &enc_rr(opcode, link.to_reg(), info.rn));
-                if info.opcode.is_call() {
-                    sink.add_call_site(srcloc, info.opcode);
-                }
-            }
-            &Inst::Ret { link } => {
-                let opcode = 0x07; // BCR
-                put(sink, &enc_rr(opcode, gpr(15), link));
-            }
-            &Inst::EpiloguePlaceholder => {
-                // Noop; this is just a placeholder for epilogues.
-            }
-            &Inst::Jump { dest } => {
-                let off = sink.cur_offset();
-                // Indicate that the jump uses a label, if so, so that a fixup can occur later.
-                sink.use_label_at_offset(off, dest, LabelUse::BranchRIL);
-                sink.add_uncond_branch(off, off + 6, dest);
-                // Emit the jump itself.
-                let opcode = 0xc04; // BCRL
-                put(sink, &enc_ril_c(opcode, 15, 0));
-            }
-            &Inst::IndirectBr { rn, .. } => {
-                let opcode = 0x07; // BCR
-                put(sink, &enc_rr(opcode, gpr(15), rn));
-            }
-            &Inst::CondBr {
-                taken,
-                not_taken,
-                cond,
-            } => {
-                let opcode = 0xc04; // BCRL
-
-                // Conditional part first.
-                let cond_off = sink.cur_offset();
-                sink.use_label_at_offset(cond_off, taken, LabelUse::BranchRIL);
-                let inverted = &enc_ril_c(opcode, cond.invert().bits(), 0);
-                sink.add_cond_branch(cond_off, cond_off + 6, taken, inverted);
-                put(sink, &enc_ril_c(opcode, cond.bits(), 0));
-
-                // Unconditional part next.
-                let uncond_off = sink.cur_offset();
-                sink.use_label_at_offset(uncond_off, not_taken, LabelUse::BranchRIL);
-                sink.add_uncond_branch(uncond_off, uncond_off + 6, not_taken);
-                put(sink, &enc_ril_c(opcode, 15, 0));
-            }
-            &Inst::OneWayCondBr { target, cond } => {
-                let opcode = 0xc04; // BCRL
-                sink.use_label_at_offset(sink.cur_offset(), target, LabelUse::BranchRIL);
-                put(sink, &enc_ril_c(opcode, cond.bits(), 0));
-            }
-            &Inst::Nop0 => {}
-            &Inst::Nop2 => {
-                put(sink, &enc_e(0x0707));
-            }
-            &Inst::Debugtrap => {
-                put(sink, &enc_e(0x0001));
-            }
-            &Inst::Trap { trap_code } => {
-                if let Some(s) = state.take_stack_map() {
-                    sink.add_stack_map(StackMapExtent::UpcomingBytes(2), s);
-                }
-                let srcloc = state.cur_srcloc();
-                put_with_trap(sink, &enc_e(0x0000), srcloc, trap_code);
-            }
-            &Inst::TrapIf { cond, trap_code } => {
-                // Branch over trap if condition is false.
-                let opcode = 0xa74; // BCR
-                put(sink, &enc_ri_c(opcode, cond.invert().bits(), 4 + 2));
-                // Now emit the actual trap.
-                if let Some(s) = state.take_stack_map() {
-                    sink.add_stack_map(StackMapExtent::UpcomingBytes(2), s);
-                }
-                let srcloc = state.cur_srcloc();
-                put_with_trap(sink, &enc_e(0x0000), srcloc, trap_code);
-            }
-            &Inst::JTSequence { ridx, ref targets } => {
-                let table_label = sink.get_label();
-
-                // This sequence is *one* instruction in the vcode, and is expanded only here at
-                // emission time, because we cannot allow the regalloc to insert spills/reloads in
-                // the middle; we depend on hardcoded PC-rel addressing below.
-
-                // Set temp register to address of jump table.
-                let rtmp = writable_spilltmp_reg();
-                let inst = Inst::LoadAddr {
-                    rd: rtmp,
-                    mem: MemArg::Label {
-                        target: table_label,
-                    },
-                };
-                inst.emit(sink, emit_info, state);
-
-                // Set temp to target address by adding the value of the jump table entry.
-                let inst = Inst::AluRX {
-                    alu_op: ALUOp::Add64Ext32,
-                    rd: rtmp,
-                    mem: MemArg::reg_plus_reg(rtmp.to_reg(), ridx, MemFlags::trusted()),
-                };
-                inst.emit(sink, emit_info, state);
-
-                // Branch to computed address. (`targets` here is only used for successor queries
-                // and is not needed for emission.)
-                let inst = Inst::IndirectBr {
-                    rn: rtmp.to_reg(),
-                    targets: vec![],
-                };
-                inst.emit(sink, emit_info, state);
-
-                // Emit jump table (table of 32-bit offsets).
-                // The first entry is the default target, which is not emitted
-                // into the jump table, so we skip it here.  It is only in the
-                // list so MachTerminator will see the potential target.
-                sink.bind_label(table_label);
-                let jt_off = sink.cur_offset();
-                for &target in targets.iter().skip(1) {
-                    let word_off = sink.cur_offset();
-                    let off_into_table = word_off - jt_off;
-                    sink.use_label_at_offset(word_off, target, LabelUse::PCRel32);
-                    sink.put4(off_into_table.swap_bytes());
-                }
-
-                // Lowering produces an EmitIsland before using a JTSequence, so we can safely
-                // disable the worst-case-size check in this case.
-                start_off = sink.cur_offset();
-            }
-
-            &Inst::VirtualSPOffsetAdj { offset } => {
-                log::trace!(
-                    "virtual sp offset adjusted by {} -> {}",
-                    offset,
-                    state.virtual_sp_offset + offset
-                );
-                state.virtual_sp_offset += offset;
-            }
-
-            &Inst::ValueLabelMarker { .. } => {
-                // Nothing; this is only used to compute debug info.
-            }
-
-            &Inst::Unwind { ref inst } => {
-                sink.add_unwind(inst.clone());
-            }
-        }
-
-        let end_off = sink.cur_offset();
-        debug_assert!((end_off - start_off) <= Inst::worst_case_size());
-
-        state.clear_post_insn();
-    }
-
-    fn pretty_print(&self, mb_rru: Option<&RealRegUniverse>, state: &mut EmitState) -> String {
-        self.print_with_state(mb_rru, state)
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/inst/emit_tests.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/inst/emit_tests.rs
deleted file mode 100644
index ed2310e28..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/inst/emit_tests.rs
+++ /dev/null
@@ -1,8278 +0,0 @@
-use crate::ir::{MemFlags, TrapCode};
-use crate::isa::s390x::inst::*;
-use crate::isa::s390x::settings as s390x_settings;
-use crate::settings;
-use alloc::vec::Vec;
-
-#[test]
-fn test_s390x_binemit() {
-    let mut insns = Vec::<(Inst, &str, &str)>::new();
-
-    insns.push((Inst::Nop0, "", "nop-zero-len"));
-    insns.push((Inst::Nop2, "0707", "nop"));
-
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::Add32,
-            rd: writable_gpr(1),
-            rn: gpr(2),
-            rm: gpr(3),
-        },
-        "B9F83012",
-        "ark %r1, %r2, %r3",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::Add64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            rm: gpr(6),
-        },
-        "B9E86045",
-        "agrk %r4, %r5, %r6",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::AddLogical32,
-            rd: writable_gpr(1),
-            rn: gpr(2),
-            rm: gpr(3),
-        },
-        "B9FA3012",
-        "alrk %r1, %r2, %r3",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::AddLogical64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            rm: gpr(6),
-        },
-        "B9EA6045",
-        "algrk %r4, %r5, %r6",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::Sub32,
-            rd: writable_gpr(1),
-            rn: gpr(2),
-            rm: gpr(3),
-        },
-        "B9F93012",
-        "srk %r1, %r2, %r3",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::Sub64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            rm: gpr(6),
-        },
-        "B9E96045",
-        "sgrk %r4, %r5, %r6",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::SubLogical32,
-            rd: writable_gpr(1),
-            rn: gpr(2),
-            rm: gpr(3),
-        },
-        "B9FB3012",
-        "slrk %r1, %r2, %r3",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::SubLogical64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            rm: gpr(6),
-        },
-        "B9EB6045",
-        "slgrk %r4, %r5, %r6",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::Mul32,
-            rd: writable_gpr(1),
-            rn: gpr(2),
-            rm: gpr(3),
-        },
-        "B9FD3012",
-        "msrkc %r1, %r2, %r3",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::Mul64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            rm: gpr(6),
-        },
-        "B9ED6045",
-        "msgrkc %r4, %r5, %r6",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::And32,
-            rd: writable_gpr(1),
-            rn: gpr(2),
-            rm: gpr(3),
-        },
-        "B9F43012",
-        "nrk %r1, %r2, %r3",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::And64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            rm: gpr(6),
-        },
-        "B9E46045",
-        "ngrk %r4, %r5, %r6",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::Orr32,
-            rd: writable_gpr(1),
-            rn: gpr(2),
-            rm: gpr(3),
-        },
-        "B9F63012",
-        "ork %r1, %r2, %r3",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::Orr64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            rm: gpr(6),
-        },
-        "B9E66045",
-        "ogrk %r4, %r5, %r6",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::Xor32,
-            rd: writable_gpr(1),
-            rn: gpr(2),
-            rm: gpr(3),
-        },
-        "B9F73012",
-        "xrk %r1, %r2, %r3",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::Xor64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            rm: gpr(6),
-        },
-        "B9E76045",
-        "xgrk %r4, %r5, %r6",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::AndNot32,
-            rd: writable_gpr(1),
-            rn: gpr(2),
-            rm: gpr(3),
-        },
-        "B9743012",
-        "nnrk %r1, %r2, %r3",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::AndNot64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            rm: gpr(6),
-        },
-        "B9646045",
-        "nngrk %r4, %r5, %r6",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::OrrNot32,
-            rd: writable_gpr(1),
-            rn: gpr(2),
-            rm: gpr(3),
-        },
-        "B9763012",
-        "nork %r1, %r2, %r3",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::OrrNot64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            rm: gpr(6),
-        },
-        "B9666045",
-        "nogrk %r4, %r5, %r6",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::XorNot32,
-            rd: writable_gpr(1),
-            rn: gpr(2),
-            rm: gpr(3),
-        },
-        "B9773012",
-        "nxrk %r1, %r2, %r3",
-    ));
-    insns.push((
-        Inst::AluRRR {
-            alu_op: ALUOp::XorNot64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            rm: gpr(6),
-        },
-        "B9676045",
-        "nxgrk %r4, %r5, %r6",
-    ));
-
-    insns.push((
-        Inst::AluRRSImm16 {
-            alu_op: ALUOp::Add32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            imm: -32768,
-        },
-        "EC45800000D8",
-        "ahik %r4, %r5, -32768",
-    ));
-    insns.push((
-        Inst::AluRRSImm16 {
-            alu_op: ALUOp::Add32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            imm: 32767,
-        },
-        "EC457FFF00D8",
-        "ahik %r4, %r5, 32767",
-    ));
-    insns.push((
-        Inst::AluRRSImm16 {
-            alu_op: ALUOp::Add64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            imm: -32768,
-        },
-        "EC45800000D9",
-        "aghik %r4, %r5, -32768",
-    ));
-    insns.push((
-        Inst::AluRRSImm16 {
-            alu_op: ALUOp::Add64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            imm: 32767,
-        },
-        "EC457FFF00D9",
-        "aghik %r4, %r5, 32767",
-    ));
-
-    insns.push((
-        Inst::AluRR {
-            alu_op: ALUOp::Add32,
-            rd: writable_gpr(1),
-            rm: gpr(2),
-        },
-        "1A12",
-        "ar %r1, %r2",
-    ));
-    insns.push((
-        Inst::AluRR {
-            alu_op: ALUOp::Add64,
-            rd: writable_gpr(4),
-            rm: gpr(5),
-        },
-        "B9080045",
-        "agr %r4, %r5",
-    ));
-    insns.push((
-        Inst::AluRR {
-            alu_op: ALUOp::Add64Ext32,
-            rd: writable_gpr(4),
-            rm: gpr(5),
-        },
-        "B9180045",
-        "agfr %r4, %r5",
-    ));
-    insns.push((
-        Inst::AluRR {
-            alu_op: ALUOp::AddLogical32,
-            rd: writable_gpr(1),
-            rm: gpr(2),
-        },
-        "1E12",
-        "alr %r1, %r2",
-    ));
-    insns.push((
-        Inst::AluRR {
-            alu_op: ALUOp::AddLogical64,
-            rd: writable_gpr(4),
-            rm: gpr(5),
-        },
-        "B90A0045",
-        "algr %r4, %r5",
-    ));
-    insns.push((
-        Inst::AluRR {
-            alu_op: ALUOp::AddLogical64Ext32,
-            rd: writable_gpr(4),
-            rm: gpr(5),
-        },
-        "B91A0045",
-        "algfr %r4, %r5",
-    ));
-    insns.push((
-        Inst::AluRR {
-            alu_op: ALUOp::Sub32,
-            rd: writable_gpr(1),
-            rm: gpr(2),
-        },
-        "1B12",
-        "sr %r1, %r2",
-    ));
-    insns.push((
-        Inst::AluRR {
-            alu_op: ALUOp::Sub64,
-            rd: writable_gpr(4),
-            rm: gpr(5),
-        },
-        "B9090045",
-        "sgr %r4, %r5",
-    ));
-    insns.push((
-        Inst::AluRR {
-            alu_op: ALUOp::Sub64Ext32,
-            rd: writable_gpr(4),
-            rm: gpr(5),
-        },
-        "B9190045",
-        "sgfr %r4, %r5",
-    ));
-    insns.push((
-        Inst::AluRR {
-            alu_op: ALUOp::SubLogical32,
-            rd: writable_gpr(1),
-            rm: gpr(2),
-        },
-        "1F12",
-        "slr %r1, %r2",
-    ));
-    insns.push((
-        Inst::AluRR {
-            alu_op: ALUOp::SubLogical64,
-            rd: writable_gpr(4),
-            rm: gpr(5),
-        },
-        "B90B0045",
-        "slgr %r4, %r5",
-    ));
-    insns.push((
-        Inst::AluRR {
-            alu_op: ALUOp::SubLogical64Ext32,
-            rd: writable_gpr(4),
-            rm: gpr(5),
-        },
-        "B91B0045",
-        "slgfr %r4, %r5",
-    ));
-    insns.push((
-        Inst::AluRR {
-            alu_op: ALUOp::Mul32,
-            rd: writable_gpr(1),
-            rm: gpr(2),
-        },
-        "B2520012",
-        "msr %r1, %r2",
-    ));
-    insns.push((
-        Inst::AluRR {
-            alu_op: ALUOp::Mul64,
-            rd: writable_gpr(4),
-            rm: gpr(5),
-        },
-        "B90C0045",
-        "msgr %r4, %r5",
-    ));
-    insns.push((
-        Inst::AluRR {
-            alu_op: ALUOp::Mul64Ext32,
-            rd: writable_gpr(4),
-            rm: gpr(5),
-        },
-        "B91C0045",
-        "msgfr %r4, %r5",
-    ));
-    insns.push((
-        Inst::AluRR {
-            alu_op: ALUOp::And32,
-            rd: writable_gpr(1),
-            rm: gpr(2),
-        },
-        "1412",
-        "nr %r1, %r2",
-    ));
-    insns.push((
-        Inst::AluRR {
-            alu_op: ALUOp::And64,
-            rd: writable_gpr(4),
-            rm: gpr(5),
-        },
-        "B9800045",
-        "ngr %r4, %r5",
-    ));
-    insns.push((
-        Inst::AluRR {
-            alu_op: ALUOp::Orr32,
-            rd: writable_gpr(1),
-            rm: gpr(2),
-        },
-        "1612",
-        "or %r1, %r2",
-    ));
-    insns.push((
-        Inst::AluRR {
-            alu_op: ALUOp::Orr64,
-            rd: writable_gpr(4),
-            rm: gpr(5),
-        },
-        "B9810045",
-        "ogr %r4, %r5",
-    ));
-    insns.push((
-        Inst::AluRR {
-            alu_op: ALUOp::Xor32,
-            rd: writable_gpr(1),
-            rm: gpr(2),
-        },
-        "1712",
-        "xr %r1, %r2",
-    ));
-    insns.push((
-        Inst::AluRR {
-            alu_op: ALUOp::Xor64,
-            rd: writable_gpr(4),
-            rm: gpr(5),
-        },
-        "B9820045",
-        "xgr %r4, %r5",
-    ));
-
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::Add32,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "5A102000",
-        "a %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::Add32Ext16,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "4A102000",
-        "ah %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::Add32,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102000005A",
-        "ay %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::Add32Ext16,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102000004A",
-        "ahy %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::Add64,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020000008",
-        "ag %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::Add64Ext16,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020000038",
-        "agh %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::Add64Ext32,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020000018",
-        "agf %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::AddLogical32,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "5E102000",
-        "al %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::AddLogical32,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102000005E",
-        "aly %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::AddLogical64,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102000000A",
-        "alg %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::AddLogical64Ext32,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102000001A",
-        "algf %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::Sub32,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "5B102000",
-        "s %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::Sub32Ext16,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "4B102000",
-        "sh %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::Sub32,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102000005B",
-        "sy %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::Sub32Ext16,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102000007B",
-        "shy %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::Sub64,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020000009",
-        "sg %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::Sub64Ext16,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020000039",
-        "sgh %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::Sub64Ext32,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020000019",
-        "sgf %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::SubLogical32,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "5F102000",
-        "sl %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::SubLogical32,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102000005F",
-        "sly %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::SubLogical64,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102000000B",
-        "slg %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::SubLogical64Ext32,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102000001B",
-        "slgf %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::Mul32,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "71102000",
-        "ms %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::Mul32Ext16,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "4C102000",
-        "mh %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::Mul32,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020000051",
-        "msy %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::Mul32Ext16,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102000007C",
-        "mhy %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::Mul64,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102000000C",
-        "msg %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::Mul64Ext16,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102000003C",
-        "mgh %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::Mul64Ext32,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102000001C",
-        "msgf %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::And32,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "54102000",
-        "n %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::And32,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020000054",
-        "ny %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::And64,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020000080",
-        "ng %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::Orr32,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "56102000",
-        "o %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::Orr32,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020000056",
-        "oy %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::Orr64,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020000081",
-        "og %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::Xor32,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "57102000",
-        "x %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::Xor32,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020000057",
-        "xy %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::AluRX {
-            alu_op: ALUOp::Xor64,
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020000082",
-        "xg %r1, 0(%r2)",
-    ));
-
-    insns.push((
-        Inst::AluRSImm16 {
-            alu_op: ALUOp::Add32,
-            rd: writable_gpr(7),
-            imm: -32768,
-        },
-        "A77A8000",
-        "ahi %r7, -32768",
-    ));
-    insns.push((
-        Inst::AluRSImm16 {
-            alu_op: ALUOp::Add32,
-            rd: writable_gpr(7),
-            imm: 32767,
-        },
-        "A77A7FFF",
-        "ahi %r7, 32767",
-    ));
-    insns.push((
-        Inst::AluRSImm16 {
-            alu_op: ALUOp::Add64,
-            rd: writable_gpr(7),
-            imm: -32768,
-        },
-        "A77B8000",
-        "aghi %r7, -32768",
-    ));
-    insns.push((
-        Inst::AluRSImm16 {
-            alu_op: ALUOp::Add64,
-            rd: writable_gpr(7),
-            imm: 32767,
-        },
-        "A77B7FFF",
-        "aghi %r7, 32767",
-    ));
-    insns.push((
-        Inst::AluRSImm16 {
-            alu_op: ALUOp::Mul32,
-            rd: writable_gpr(7),
-            imm: -32768,
-        },
-        "A77C8000",
-        "mhi %r7, -32768",
-    ));
-    insns.push((
-        Inst::AluRSImm16 {
-            alu_op: ALUOp::Mul32,
-            rd: writable_gpr(7),
-            imm: 32767,
-        },
-        "A77C7FFF",
-        "mhi %r7, 32767",
-    ));
-    insns.push((
-        Inst::AluRSImm16 {
-            alu_op: ALUOp::Mul64,
-            rd: writable_gpr(7),
-            imm: -32768,
-        },
-        "A77D8000",
-        "mghi %r7, -32768",
-    ));
-    insns.push((
-        Inst::AluRSImm16 {
-            alu_op: ALUOp::Mul64,
-            rd: writable_gpr(7),
-            imm: 32767,
-        },
-        "A77D7FFF",
-        "mghi %r7, 32767",
-    ));
-
-    insns.push((
-        Inst::AluRSImm32 {
-            alu_op: ALUOp::Add32,
-            rd: writable_gpr(7),
-            imm: -2147483648,
-        },
-        "C27980000000",
-        "afi %r7, -2147483648",
-    ));
-    insns.push((
-        Inst::AluRSImm32 {
-            alu_op: ALUOp::Add32,
-            rd: writable_gpr(7),
-            imm: 2147483647,
-        },
-        "C2797FFFFFFF",
-        "afi %r7, 2147483647",
-    ));
-    insns.push((
-        Inst::AluRSImm32 {
-            alu_op: ALUOp::Mul32,
-            rd: writable_gpr(7),
-            imm: -2147483648,
-        },
-        "C27180000000",
-        "msfi %r7, -2147483648",
-    ));
-    insns.push((
-        Inst::AluRSImm32 {
-            alu_op: ALUOp::Mul32,
-            rd: writable_gpr(7),
-            imm: 2147483647,
-        },
-        "C2717FFFFFFF",
-        "msfi %r7, 2147483647",
-    ));
-    insns.push((
-        Inst::AluRSImm32 {
-            alu_op: ALUOp::Add64,
-            rd: writable_gpr(7),
-            imm: -2147483648,
-        },
-        "C27880000000",
-        "agfi %r7, -2147483648",
-    ));
-    insns.push((
-        Inst::AluRSImm32 {
-            alu_op: ALUOp::Add64,
-            rd: writable_gpr(7),
-            imm: 2147483647,
-        },
-        "C2787FFFFFFF",
-        "agfi %r7, 2147483647",
-    ));
-    insns.push((
-        Inst::AluRSImm32 {
-            alu_op: ALUOp::Mul64,
-            rd: writable_gpr(7),
-            imm: -2147483648,
-        },
-        "C27080000000",
-        "msgfi %r7, -2147483648",
-    ));
-    insns.push((
-        Inst::AluRSImm32 {
-            alu_op: ALUOp::Mul64,
-            rd: writable_gpr(7),
-            imm: 2147483647,
-        },
-        "C2707FFFFFFF",
-        "msgfi %r7, 2147483647",
-    ));
-
-    insns.push((
-        Inst::AluRUImm32 {
-            alu_op: ALUOp::AddLogical32,
-            rd: writable_gpr(7),
-            imm: 0,
-        },
-        "C27B00000000",
-        "alfi %r7, 0",
-    ));
-    insns.push((
-        Inst::AluRUImm32 {
-            alu_op: ALUOp::AddLogical32,
-            rd: writable_gpr(7),
-            imm: 4294967295,
-        },
-        "C27BFFFFFFFF",
-        "alfi %r7, 4294967295",
-    ));
-    insns.push((
-        Inst::AluRUImm32 {
-            alu_op: ALUOp::SubLogical32,
-            rd: writable_gpr(7),
-            imm: 0,
-        },
-        "C27500000000",
-        "slfi %r7, 0",
-    ));
-    insns.push((
-        Inst::AluRUImm32 {
-            alu_op: ALUOp::SubLogical32,
-            rd: writable_gpr(7),
-            imm: 4294967295,
-        },
-        "C275FFFFFFFF",
-        "slfi %r7, 4294967295",
-    ));
-    insns.push((
-        Inst::AluRUImm32 {
-            alu_op: ALUOp::AddLogical64,
-            rd: writable_gpr(7),
-            imm: 0,
-        },
-        "C27A00000000",
-        "algfi %r7, 0",
-    ));
-    insns.push((
-        Inst::AluRUImm32 {
-            alu_op: ALUOp::AddLogical64,
-            rd: writable_gpr(7),
-            imm: 4294967295,
-        },
-        "C27AFFFFFFFF",
-        "algfi %r7, 4294967295",
-    ));
-    insns.push((
-        Inst::AluRUImm32 {
-            alu_op: ALUOp::SubLogical64,
-            rd: writable_gpr(7),
-            imm: 0,
-        },
-        "C27400000000",
-        "slgfi %r7, 0",
-    ));
-    insns.push((
-        Inst::AluRUImm32 {
-            alu_op: ALUOp::SubLogical64,
-            rd: writable_gpr(7),
-            imm: 4294967295,
-        },
-        "C274FFFFFFFF",
-        "slgfi %r7, 4294967295",
-    ));
-
-    insns.push((
-        Inst::AluRUImm16Shifted {
-            alu_op: ALUOp::And32,
-            rd: writable_gpr(8),
-            imm: UImm16Shifted::maybe_from_u64(0x0000_ffff).unwrap(),
-        },
-        "A587FFFF",
-        "nill %r8, 65535",
-    ));
-    insns.push((
-        Inst::AluRUImm16Shifted {
-            alu_op: ALUOp::And32,
-            rd: writable_gpr(8),
-            imm: UImm16Shifted::maybe_from_u64(0xffff_0000).unwrap(),
-        },
-        "A586FFFF",
-        "nilh %r8, 65535",
-    ));
-    insns.push((
-        Inst::AluRUImm16Shifted {
-            alu_op: ALUOp::And64,
-            rd: writable_gpr(8),
-            imm: UImm16Shifted::maybe_from_u64(0x0000_0000_0000_ffff).unwrap(),
-        },
-        "A587FFFF",
-        "nill %r8, 65535",
-    ));
-    insns.push((
-        Inst::AluRUImm16Shifted {
-            alu_op: ALUOp::And64,
-            rd: writable_gpr(8),
-            imm: UImm16Shifted::maybe_from_u64(0x0000_0000_ffff_0000).unwrap(),
-        },
-        "A586FFFF",
-        "nilh %r8, 65535",
-    ));
-    insns.push((
-        Inst::AluRUImm16Shifted {
-            alu_op: ALUOp::And64,
-            rd: writable_gpr(8),
-            imm: UImm16Shifted::maybe_from_u64(0x0000_ffff_0000_0000).unwrap(),
-        },
-        "A585FFFF",
-        "nihl %r8, 65535",
-    ));
-    insns.push((
-        Inst::AluRUImm16Shifted {
-            alu_op: ALUOp::And64,
-            rd: writable_gpr(8),
-            imm: UImm16Shifted::maybe_from_u64(0xffff_0000_0000_0000).unwrap(),
-        },
-        "A584FFFF",
-        "nihh %r8, 65535",
-    ));
-    insns.push((
-        Inst::AluRUImm16Shifted {
-            alu_op: ALUOp::Orr32,
-            rd: writable_gpr(8),
-            imm: UImm16Shifted::maybe_from_u64(0x0000_ffff).unwrap(),
-        },
-        "A58BFFFF",
-        "oill %r8, 65535",
-    ));
-    insns.push((
-        Inst::AluRUImm16Shifted {
-            alu_op: ALUOp::Orr32,
-            rd: writable_gpr(8),
-            imm: UImm16Shifted::maybe_from_u64(0xffff_0000).unwrap(),
-        },
-        "A58AFFFF",
-        "oilh %r8, 65535",
-    ));
-    insns.push((
-        Inst::AluRUImm16Shifted {
-            alu_op: ALUOp::Orr64,
-            rd: writable_gpr(8),
-            imm: UImm16Shifted::maybe_from_u64(0x0000_0000_0000_ffff).unwrap(),
-        },
-        "A58BFFFF",
-        "oill %r8, 65535",
-    ));
-    insns.push((
-        Inst::AluRUImm16Shifted {
-            alu_op: ALUOp::Orr64,
-            rd: writable_gpr(8),
-            imm: UImm16Shifted::maybe_from_u64(0x0000_0000_ffff_0000).unwrap(),
-        },
-        "A58AFFFF",
-        "oilh %r8, 65535",
-    ));
-    insns.push((
-        Inst::AluRUImm16Shifted {
-            alu_op: ALUOp::Orr64,
-            rd: writable_gpr(8),
-            imm: UImm16Shifted::maybe_from_u64(0x0000_ffff_0000_0000).unwrap(),
-        },
-        "A589FFFF",
-        "oihl %r8, 65535",
-    ));
-    insns.push((
-        Inst::AluRUImm16Shifted {
-            alu_op: ALUOp::Orr64,
-            rd: writable_gpr(8),
-            imm: UImm16Shifted::maybe_from_u64(0xffff_0000_0000_0000).unwrap(),
-        },
-        "A588FFFF",
-        "oihh %r8, 65535",
-    ));
-
-    insns.push((
-        Inst::AluRUImm32Shifted {
-            alu_op: ALUOp::And32,
-            rd: writable_gpr(8),
-            imm: UImm32Shifted::maybe_from_u64(0xffff_ffff).unwrap(),
-        },
-        "C08BFFFFFFFF",
-        "nilf %r8, 4294967295",
-    ));
-    insns.push((
-        Inst::AluRUImm32Shifted {
-            alu_op: ALUOp::And64,
-            rd: writable_gpr(8),
-            imm: UImm32Shifted::maybe_from_u64(0x0000_0000_ffff_ffff).unwrap(),
-        },
-        "C08BFFFFFFFF",
-        "nilf %r8, 4294967295",
-    ));
-    insns.push((
-        Inst::AluRUImm32Shifted {
-            alu_op: ALUOp::And64,
-            rd: writable_gpr(8),
-            imm: UImm32Shifted::maybe_from_u64(0xffff_ffff_0000_0000).unwrap(),
-        },
-        "C08AFFFFFFFF",
-        "nihf %r8, 4294967295",
-    ));
-    insns.push((
-        Inst::AluRUImm32Shifted {
-            alu_op: ALUOp::Orr32,
-            rd: writable_gpr(8),
-            imm: UImm32Shifted::maybe_from_u64(0xffff_ffff).unwrap(),
-        },
-        "C08DFFFFFFFF",
-        "oilf %r8, 4294967295",
-    ));
-    insns.push((
-        Inst::AluRUImm32Shifted {
-            alu_op: ALUOp::Orr64,
-            rd: writable_gpr(8),
-            imm: UImm32Shifted::maybe_from_u64(0x0000_0000_ffff_ffff).unwrap(),
-        },
-        "C08DFFFFFFFF",
-        "oilf %r8, 4294967295",
-    ));
-    insns.push((
-        Inst::AluRUImm32Shifted {
-            alu_op: ALUOp::Orr64,
-            rd: writable_gpr(8),
-            imm: UImm32Shifted::maybe_from_u64(0xffff_ffff_0000_0000).unwrap(),
-        },
-        "C08CFFFFFFFF",
-        "oihf %r8, 4294967295",
-    ));
-    insns.push((
-        Inst::AluRUImm32Shifted {
-            alu_op: ALUOp::Xor32,
-            rd: writable_gpr(8),
-            imm: UImm32Shifted::maybe_from_u64(0xffff_ffff).unwrap(),
-        },
-        "C087FFFFFFFF",
-        "xilf %r8, 4294967295",
-    ));
-    insns.push((
-        Inst::AluRUImm32Shifted {
-            alu_op: ALUOp::Xor64,
-            rd: writable_gpr(8),
-            imm: UImm32Shifted::maybe_from_u64(0x0000_0000_ffff_ffff).unwrap(),
-        },
-        "C087FFFFFFFF",
-        "xilf %r8, 4294967295",
-    ));
-    insns.push((
-        Inst::AluRUImm32Shifted {
-            alu_op: ALUOp::Xor64,
-            rd: writable_gpr(8),
-            imm: UImm32Shifted::maybe_from_u64(0xffff_ffff_0000_0000).unwrap(),
-        },
-        "C086FFFFFFFF",
-        "xihf %r8, 4294967295",
-    ));
-
-    insns.push((
-        Inst::UnaryRR {
-            op: UnaryOp::Abs32,
-            rd: writable_gpr(1),
-            rn: gpr(10),
-        },
-        "101A",
-        "lpr %r1, %r10",
-    ));
-    insns.push((
-        Inst::UnaryRR {
-            op: UnaryOp::Abs64,
-            rd: writable_gpr(1),
-            rn: gpr(10),
-        },
-        "B900001A",
-        "lpgr %r1, %r10",
-    ));
-    insns.push((
-        Inst::UnaryRR {
-            op: UnaryOp::Abs64Ext32,
-            rd: writable_gpr(1),
-            rn: gpr(10),
-        },
-        "B910001A",
-        "lpgfr %r1, %r10",
-    ));
-    insns.push((
-        Inst::UnaryRR {
-            op: UnaryOp::Neg32,
-            rd: writable_gpr(1),
-            rn: gpr(10),
-        },
-        "131A",
-        "lcr %r1, %r10",
-    ));
-    insns.push((
-        Inst::UnaryRR {
-            op: UnaryOp::Neg64,
-            rd: writable_gpr(1),
-            rn: gpr(10),
-        },
-        "B903001A",
-        "lcgr %r1, %r10",
-    ));
-    insns.push((
-        Inst::UnaryRR {
-            op: UnaryOp::Neg64Ext32,
-            rd: writable_gpr(1),
-            rn: gpr(10),
-        },
-        "B913001A",
-        "lcgfr %r1, %r10",
-    ));
-    insns.push((
-        Inst::UnaryRR {
-            op: UnaryOp::PopcntByte,
-            rd: writable_gpr(1),
-            rn: gpr(10),
-        },
-        "B9E1001A",
-        "popcnt %r1, %r10",
-    ));
-    insns.push((
-        Inst::UnaryRR {
-            op: UnaryOp::PopcntReg,
-            rd: writable_gpr(1),
-            rn: gpr(10),
-        },
-        "B9E1801A",
-        "popcnt %r1, %r10, 8",
-    ));
-    insns.push((
-        Inst::UnaryRR {
-            op: UnaryOp::BSwap32,
-            rd: writable_gpr(1),
-            rn: gpr(10),
-        },
-        "B91F001A",
-        "lrvr %r1, %r10",
-    ));
-    insns.push((
-        Inst::UnaryRR {
-            op: UnaryOp::BSwap64,
-            rd: writable_gpr(1),
-            rn: gpr(10),
-        },
-        "B90F001A",
-        "lrvgr %r1, %r10",
-    ));
-
-    insns.push((
-        Inst::CmpRR {
-            op: CmpOp::CmpS32,
-            rn: gpr(5),
-            rm: gpr(6),
-        },
-        "1956",
-        "cr %r5, %r6",
-    ));
-    insns.push((
-        Inst::CmpRR {
-            op: CmpOp::CmpS64,
-            rn: gpr(5),
-            rm: gpr(6),
-        },
-        "B9200056",
-        "cgr %r5, %r6",
-    ));
-    insns.push((
-        Inst::CmpRR {
-            op: CmpOp::CmpS64Ext32,
-            rn: gpr(5),
-            rm: gpr(6),
-        },
-        "B9300056",
-        "cgfr %r5, %r6",
-    ));
-    insns.push((
-        Inst::CmpRR {
-            op: CmpOp::CmpL32,
-            rn: gpr(5),
-            rm: gpr(6),
-        },
-        "1556",
-        "clr %r5, %r6",
-    ));
-    insns.push((
-        Inst::CmpRR {
-            op: CmpOp::CmpL64,
-            rn: gpr(5),
-            rm: gpr(6),
-        },
-        "B9210056",
-        "clgr %r5, %r6",
-    ));
-    insns.push((
-        Inst::CmpRR {
-            op: CmpOp::CmpL64Ext32,
-            rn: gpr(5),
-            rm: gpr(6),
-        },
-        "B9310056",
-        "clgfr %r5, %r6",
-    ));
-
-    insns.push((
-        Inst::CmpRX {
-            op: CmpOp::CmpS32,
-            rn: gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "59102000",
-        "c %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::CmpRX {
-            op: CmpOp::CmpS32,
-            rn: gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020000059",
-        "cy %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::CmpRX {
-            op: CmpOp::CmpS32,
-            rn: gpr(1),
-            mem: MemArg::Label {
-                target: MachLabel::from_block(1),
-            },
-        },
-        "C61D00000003",
-        "crl %r1, label1",
-    ));
-    insns.push((
-        Inst::CmpRX {
-            op: CmpOp::CmpS32Ext16,
-            rn: gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "49102000",
-        "ch %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::CmpRX {
-            op: CmpOp::CmpS32Ext16,
-            rn: gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020000079",
-        "chy %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::CmpRX {
-            op: CmpOp::CmpS32Ext16,
-            rn: gpr(1),
-            mem: MemArg::Label {
-                target: MachLabel::from_block(1),
-            },
-        },
-        "C61500000003",
-        "chrl %r1, label1",
-    ));
-    insns.push((
-        Inst::CmpRX {
-            op: CmpOp::CmpS64,
-            rn: gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020000020",
-        "cg %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::CmpRX {
-            op: CmpOp::CmpS64,
-            rn: gpr(1),
-            mem: MemArg::Label {
-                target: MachLabel::from_block(1),
-            },
-        },
-        "C61800000003",
-        "cgrl %r1, label1",
-    ));
-    insns.push((
-        Inst::CmpRX {
-            op: CmpOp::CmpS64Ext16,
-            rn: gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020000034",
-        "cgh %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::CmpRX {
-            op: CmpOp::CmpS64Ext16,
-            rn: gpr(1),
-            mem: MemArg::Label {
-                target: MachLabel::from_block(1),
-            },
-        },
-        "C61400000003",
-        "cghrl %r1, label1",
-    ));
-    insns.push((
-        Inst::CmpRX {
-            op: CmpOp::CmpS64Ext32,
-            rn: gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020000030",
-        "cgf %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::CmpRX {
-            op: CmpOp::CmpS64Ext32,
-            rn: gpr(1),
-            mem: MemArg::Label {
-                target: MachLabel::from_block(1),
-            },
-        },
-        "C61C00000003",
-        "cgfrl %r1, label1",
-    ));
-    insns.push((
-        Inst::CmpRX {
-            op: CmpOp::CmpL32,
-            rn: gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "55102000",
-        "cl %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::CmpRX {
-            op: CmpOp::CmpL32,
-            rn: gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020000055",
-        "cly %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::CmpRX {
-            op: CmpOp::CmpL32,
-            rn: gpr(1),
-            mem: MemArg::Label {
-                target: MachLabel::from_block(1),
-            },
-        },
-        "C61F00000003",
-        "clrl %r1, label1",
-    ));
-    insns.push((
-        Inst::CmpRX {
-            op: CmpOp::CmpL32Ext16,
-            rn: gpr(1),
-            mem: MemArg::Label {
-                target: MachLabel::from_block(1),
-            },
-        },
-        "C61700000003",
-        "clhrl %r1, label1",
-    ));
-    insns.push((
-        Inst::CmpRX {
-            op: CmpOp::CmpL64,
-            rn: gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020000021",
-        "clg %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::CmpRX {
-            op: CmpOp::CmpL64,
-            rn: gpr(1),
-            mem: MemArg::Label {
-                target: MachLabel::from_block(1),
-            },
-        },
-        "C61A00000003",
-        "clgrl %r1, label1",
-    ));
-    insns.push((
-        Inst::CmpRX {
-            op: CmpOp::CmpL64Ext16,
-            rn: gpr(1),
-            mem: MemArg::Label {
-                target: MachLabel::from_block(1),
-            },
-        },
-        "C61600000003",
-        "clghrl %r1, label1",
-    ));
-    insns.push((
-        Inst::CmpRX {
-            op: CmpOp::CmpL64Ext32,
-            rn: gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020000031",
-        "clgf %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::CmpRX {
-            op: CmpOp::CmpL64Ext32,
-            rn: gpr(1),
-            mem: MemArg::Label {
-                target: MachLabel::from_block(1),
-            },
-        },
-        "C61E00000003",
-        "clgfrl %r1, label1",
-    ));
-
-    insns.push((
-        Inst::CmpRSImm16 {
-            op: CmpOp::CmpS32,
-            rn: gpr(7),
-            imm: -32768,
-        },
-        "A77E8000",
-        "chi %r7, -32768",
-    ));
-    insns.push((
-        Inst::CmpRSImm16 {
-            op: CmpOp::CmpS32,
-            rn: gpr(7),
-            imm: 32767,
-        },
-        "A77E7FFF",
-        "chi %r7, 32767",
-    ));
-    insns.push((
-        Inst::CmpRSImm16 {
-            op: CmpOp::CmpS64,
-            rn: gpr(7),
-            imm: -32768,
-        },
-        "A77F8000",
-        "cghi %r7, -32768",
-    ));
-    insns.push((
-        Inst::CmpRSImm16 {
-            op: CmpOp::CmpS64,
-            rn: gpr(7),
-            imm: 32767,
-        },
-        "A77F7FFF",
-        "cghi %r7, 32767",
-    ));
-    insns.push((
-        Inst::CmpRSImm32 {
-            op: CmpOp::CmpS32,
-            rn: gpr(7),
-            imm: -2147483648,
-        },
-        "C27D80000000",
-        "cfi %r7, -2147483648",
-    ));
-    insns.push((
-        Inst::CmpRSImm32 {
-            op: CmpOp::CmpS32,
-            rn: gpr(7),
-            imm: 2147483647,
-        },
-        "C27D7FFFFFFF",
-        "cfi %r7, 2147483647",
-    ));
-    insns.push((
-        Inst::CmpRSImm32 {
-            op: CmpOp::CmpS64,
-            rn: gpr(7),
-            imm: -2147483648,
-        },
-        "C27C80000000",
-        "cgfi %r7, -2147483648",
-    ));
-    insns.push((
-        Inst::CmpRSImm32 {
-            op: CmpOp::CmpS64,
-            rn: gpr(7),
-            imm: 2147483647,
-        },
-        "C27C7FFFFFFF",
-        "cgfi %r7, 2147483647",
-    ));
-    insns.push((
-        Inst::CmpRUImm32 {
-            op: CmpOp::CmpL32,
-            rn: gpr(7),
-            imm: 0,
-        },
-        "C27F00000000",
-        "clfi %r7, 0",
-    ));
-    insns.push((
-        Inst::CmpRUImm32 {
-            op: CmpOp::CmpL32,
-            rn: gpr(7),
-            imm: 4294967295,
-        },
-        "C27FFFFFFFFF",
-        "clfi %r7, 4294967295",
-    ));
-    insns.push((
-        Inst::CmpRUImm32 {
-            op: CmpOp::CmpL64,
-            rn: gpr(7),
-            imm: 0,
-        },
-        "C27E00000000",
-        "clgfi %r7, 0",
-    ));
-    insns.push((
-        Inst::CmpRUImm32 {
-            op: CmpOp::CmpL64,
-            rn: gpr(7),
-            imm: 4294967295,
-        },
-        "C27EFFFFFFFF",
-        "clgfi %r7, 4294967295",
-    ));
-
-    insns.push((
-        Inst::CmpTrapRR {
-            op: CmpOp::CmpS32,
-            rn: gpr(5),
-            rm: gpr(6),
-            cond: Cond::from_mask(8),
-            trap_code: TrapCode::StackOverflow,
-        },
-        "B9728056",
-        "crte %r5, %r6",
-    ));
-    insns.push((
-        Inst::CmpTrapRR {
-            op: CmpOp::CmpS64,
-            rn: gpr(5),
-            rm: gpr(6),
-            cond: Cond::from_mask(8),
-            trap_code: TrapCode::StackOverflow,
-        },
-        "B9608056",
-        "cgrte %r5, %r6",
-    ));
-    insns.push((
-        Inst::CmpTrapRR {
-            op: CmpOp::CmpL32,
-            rn: gpr(5),
-            rm: gpr(6),
-            cond: Cond::from_mask(8),
-            trap_code: TrapCode::StackOverflow,
-        },
-        "B9738056",
-        "clrte %r5, %r6",
-    ));
-    insns.push((
-        Inst::CmpTrapRR {
-            op: CmpOp::CmpL64,
-            rn: gpr(5),
-            rm: gpr(6),
-            cond: Cond::from_mask(8),
-            trap_code: TrapCode::StackOverflow,
-        },
-        "B9618056",
-        "clgrte %r5, %r6",
-    ));
-    insns.push((
-        Inst::CmpTrapRSImm16 {
-            op: CmpOp::CmpS32,
-            rn: gpr(7),
-            imm: -32768,
-            cond: Cond::from_mask(8),
-            trap_code: TrapCode::StackOverflow,
-        },
-        "EC7080008072",
-        "cite %r7, -32768",
-    ));
-    insns.push((
-        Inst::CmpTrapRSImm16 {
-            op: CmpOp::CmpS32,
-            rn: gpr(7),
-            imm: 32767,
-            cond: Cond::from_mask(8),
-            trap_code: TrapCode::StackOverflow,
-        },
-        "EC707FFF8072",
-        "cite %r7, 32767",
-    ));
-    insns.push((
-        Inst::CmpTrapRSImm16 {
-            op: CmpOp::CmpS64,
-            rn: gpr(7),
-            imm: -32768,
-            cond: Cond::from_mask(8),
-            trap_code: TrapCode::StackOverflow,
-        },
-        "EC7080008070",
-        "cgite %r7, -32768",
-    ));
-    insns.push((
-        Inst::CmpTrapRSImm16 {
-            op: CmpOp::CmpS64,
-            rn: gpr(7),
-            imm: 32767,
-            cond: Cond::from_mask(8),
-            trap_code: TrapCode::StackOverflow,
-        },
-        "EC707FFF8070",
-        "cgite %r7, 32767",
-    ));
-    insns.push((
-        Inst::CmpTrapRUImm16 {
-            op: CmpOp::CmpL32,
-            rn: gpr(7),
-            imm: 0,
-            cond: Cond::from_mask(8),
-            trap_code: TrapCode::StackOverflow,
-        },
-        "EC7000008073",
-        "clfite %r7, 0",
-    ));
-    insns.push((
-        Inst::CmpTrapRUImm16 {
-            op: CmpOp::CmpL32,
-            rn: gpr(7),
-            imm: 65535,
-            cond: Cond::from_mask(8),
-            trap_code: TrapCode::StackOverflow,
-        },
-        "EC70FFFF8073",
-        "clfite %r7, 65535",
-    ));
-    insns.push((
-        Inst::CmpTrapRUImm16 {
-            op: CmpOp::CmpL64,
-            rn: gpr(7),
-            imm: 0,
-            cond: Cond::from_mask(8),
-            trap_code: TrapCode::StackOverflow,
-        },
-        "EC7000008071",
-        "clgite %r7, 0",
-    ));
-    insns.push((
-        Inst::CmpTrapRUImm16 {
-            op: CmpOp::CmpL64,
-            rn: gpr(7),
-            imm: 65535,
-            cond: Cond::from_mask(8),
-            trap_code: TrapCode::StackOverflow,
-        },
-        "EC70FFFF8071",
-        "clgite %r7, 65535",
-    ));
-
-    insns.push((
-        Inst::SMulWide {
-            rn: gpr(5),
-            rm: gpr(6),
-        },
-        "B9EC6005",
-        "mgrk %r0, %r5, %r6",
-    ));
-    insns.push((Inst::UMulWide { rn: gpr(5) }, "B9860005", "mlgr %r0, %r5"));
-    insns.push((Inst::SDivMod32 { rn: gpr(5) }, "B91D0005", "dsgfr %r0, %r5"));
-    insns.push((Inst::SDivMod64 { rn: gpr(5) }, "B90D0005", "dsgr %r0, %r5"));
-    insns.push((Inst::UDivMod32 { rn: gpr(5) }, "B9970005", "dlr %r0, %r5"));
-    insns.push((Inst::UDivMod64 { rn: gpr(5) }, "B9870005", "dlgr %r0, %r5"));
-
-    insns.push((Inst::Flogr { rn: gpr(5) }, "B9830005", "flogr %r0, %r5"));
-
-    insns.push((
-        Inst::ShiftRR {
-            shift_op: ShiftOp::RotL32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            shift_imm: 0,
-            shift_reg: zero_reg(),
-        },
-        "EB450000001D",
-        "rll %r4, %r5, 0",
-    ));
-    insns.push((
-        Inst::ShiftRR {
-            shift_op: ShiftOp::RotL32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            shift_imm: 63,
-            shift_reg: zero_reg(),
-        },
-        "EB45003F001D",
-        "rll %r4, %r5, 63",
-    ));
-    insns.push((
-        Inst::ShiftRR {
-            shift_op: ShiftOp::RotL32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            shift_imm: 0,
-            shift_reg: gpr(6),
-        },
-        "EB456000001D",
-        "rll %r4, %r5, 0(%r6)",
-    ));
-    insns.push((
-        Inst::ShiftRR {
-            shift_op: ShiftOp::RotL32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            shift_imm: 63,
-            shift_reg: gpr(6),
-        },
-        "EB45603F001D",
-        "rll %r4, %r5, 63(%r6)",
-    ));
-    insns.push((
-        Inst::ShiftRR {
-            shift_op: ShiftOp::RotL64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            shift_imm: 0,
-            shift_reg: zero_reg(),
-        },
-        "EB450000001C",
-        "rllg %r4, %r5, 0",
-    ));
-    insns.push((
-        Inst::ShiftRR {
-            shift_op: ShiftOp::RotL64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            shift_imm: 63,
-            shift_reg: zero_reg(),
-        },
-        "EB45003F001C",
-        "rllg %r4, %r5, 63",
-    ));
-    insns.push((
-        Inst::ShiftRR {
-            shift_op: ShiftOp::RotL64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            shift_imm: 0,
-            shift_reg: gpr(6),
-        },
-        "EB456000001C",
-        "rllg %r4, %r5, 0(%r6)",
-    ));
-    insns.push((
-        Inst::ShiftRR {
-            shift_op: ShiftOp::RotL64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            shift_imm: 63,
-            shift_reg: gpr(6),
-        },
-        "EB45603F001C",
-        "rllg %r4, %r5, 63(%r6)",
-    ));
-    insns.push((
-        Inst::ShiftRR {
-            shift_op: ShiftOp::LShL32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            shift_imm: 0,
-            shift_reg: zero_reg(),
-        },
-        "EB45000000DF",
-        "sllk %r4, %r5, 0",
-    ));
-    insns.push((
-        Inst::ShiftRR {
-            shift_op: ShiftOp::LShL32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            shift_imm: 63,
-            shift_reg: zero_reg(),
-        },
-        "EB45003F00DF",
-        "sllk %r4, %r5, 63",
-    ));
-    insns.push((
-        Inst::ShiftRR {
-            shift_op: ShiftOp::LShL32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            shift_imm: 0,
-            shift_reg: gpr(6),
-        },
-        "EB45600000DF",
-        "sllk %r4, %r5, 0(%r6)",
-    ));
-    insns.push((
-        Inst::ShiftRR {
-            shift_op: ShiftOp::LShL32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            shift_imm: 63,
-            shift_reg: gpr(6),
-        },
-        "EB45603F00DF",
-        "sllk %r4, %r5, 63(%r6)",
-    ));
-    insns.push((
-        Inst::ShiftRR {
-            shift_op: ShiftOp::LShL64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            shift_imm: 0,
-            shift_reg: zero_reg(),
-        },
-        "EB450000000D",
-        "sllg %r4, %r5, 0",
-    ));
-    insns.push((
-        Inst::ShiftRR {
-            shift_op: ShiftOp::LShL64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            shift_imm: 63,
-            shift_reg: zero_reg(),
-        },
-        "EB45003F000D",
-        "sllg %r4, %r5, 63",
-    ));
-    insns.push((
-        Inst::ShiftRR {
-            shift_op: ShiftOp::LShL64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            shift_imm: 0,
-            shift_reg: gpr(6),
-        },
-        "EB456000000D",
-        "sllg %r4, %r5, 0(%r6)",
-    ));
-    insns.push((
-        Inst::ShiftRR {
-            shift_op: ShiftOp::LShL64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            shift_imm: 63,
-            shift_reg: gpr(6),
-        },
-        "EB45603F000D",
-        "sllg %r4, %r5, 63(%r6)",
-    ));
-    insns.push((
-        Inst::ShiftRR {
-            shift_op: ShiftOp::LShR32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            shift_imm: 0,
-            shift_reg: zero_reg(),
-        },
-        "EB45000000DE",
-        "srlk %r4, %r5, 0",
-    ));
-    insns.push((
-        Inst::ShiftRR {
-            shift_op: ShiftOp::LShR32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            shift_imm: 63,
-            shift_reg: zero_reg(),
-        },
-        "EB45003F00DE",
-        "srlk %r4, %r5, 63",
-    ));
-    insns.push((
-        Inst::ShiftRR {
-            shift_op: ShiftOp::LShR32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            shift_imm: 0,
-            shift_reg: gpr(6),
-        },
-        "EB45600000DE",
-        "srlk %r4, %r5, 0(%r6)",
-    ));
-    insns.push((
-        Inst::ShiftRR {
-            shift_op: ShiftOp::LShR32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            shift_imm: 63,
-            shift_reg: gpr(6),
-        },
-        "EB45603F00DE",
-        "srlk %r4, %r5, 63(%r6)",
-    ));
-    insns.push((
-        Inst::ShiftRR {
-            shift_op: ShiftOp::LShR64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            shift_imm: 0,
-            shift_reg: zero_reg(),
-        },
-        "EB450000000C",
-        "srlg %r4, %r5, 0",
-    ));
-    insns.push((
-        Inst::ShiftRR {
-            shift_op: ShiftOp::LShR64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            shift_imm: 63,
-            shift_reg: zero_reg(),
-        },
-        "EB45003F000C",
-        "srlg %r4, %r5, 63",
-    ));
-    insns.push((
-        Inst::ShiftRR {
-            shift_op: ShiftOp::LShR64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            shift_imm: 0,
-            shift_reg: gpr(6),
-        },
-        "EB456000000C",
-        "srlg %r4, %r5, 0(%r6)",
-    ));
-    insns.push((
-        Inst::ShiftRR {
-            shift_op: ShiftOp::LShR64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            shift_imm: 63,
-            shift_reg: gpr(6),
-        },
-        "EB45603F000C",
-        "srlg %r4, %r5, 63(%r6)",
-    ));
-    insns.push((
-        Inst::ShiftRR {
-            shift_op: ShiftOp::AShR32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            shift_imm: 0,
-            shift_reg: zero_reg(),
-        },
-        "EB45000000DC",
-        "srak %r4, %r5, 0",
-    ));
-    insns.push((
-        Inst::ShiftRR {
-            shift_op: ShiftOp::AShR32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            shift_imm: 63,
-            shift_reg: zero_reg(),
-        },
-        "EB45003F00DC",
-        "srak %r4, %r5, 63",
-    ));
-    insns.push((
-        Inst::ShiftRR {
-            shift_op: ShiftOp::AShR32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            shift_imm: 0,
-            shift_reg: gpr(6),
-        },
-        "EB45600000DC",
-        "srak %r4, %r5, 0(%r6)",
-    ));
-    insns.push((
-        Inst::ShiftRR {
-            shift_op: ShiftOp::AShR32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            shift_imm: 63,
-            shift_reg: gpr(6),
-        },
-        "EB45603F00DC",
-        "srak %r4, %r5, 63(%r6)",
-    ));
-    insns.push((
-        Inst::ShiftRR {
-            shift_op: ShiftOp::AShR64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            shift_imm: 0,
-            shift_reg: zero_reg(),
-        },
-        "EB450000000A",
-        "srag %r4, %r5, 0",
-    ));
-    insns.push((
-        Inst::ShiftRR {
-            shift_op: ShiftOp::AShR64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            shift_imm: 63,
-            shift_reg: zero_reg(),
-        },
-        "EB45003F000A",
-        "srag %r4, %r5, 63",
-    ));
-    insns.push((
-        Inst::ShiftRR {
-            shift_op: ShiftOp::AShR64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            shift_imm: 0,
-            shift_reg: gpr(6),
-        },
-        "EB456000000A",
-        "srag %r4, %r5, 0(%r6)",
-    ));
-    insns.push((
-        Inst::ShiftRR {
-            shift_op: ShiftOp::AShR64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            shift_imm: 63,
-            shift_reg: gpr(6),
-        },
-        "EB45603F000A",
-        "srag %r4, %r5, 63(%r6)",
-    ));
-
-    insns.push((
-        Inst::RxSBG {
-            op: RxSBGOp::Insert,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            start_bit: 8,
-            end_bit: 32,
-            rotate_amt: -16,
-        },
-        "EC4508203059",
-        "risbgn %r4, %r5, 8, 32, 48",
-    ));
-    insns.push((
-        Inst::RxSBG {
-            op: RxSBGOp::And,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            start_bit: 8,
-            end_bit: 32,
-            rotate_amt: 63,
-        },
-        "EC4508203F54",
-        "rnsbg %r4, %r5, 8, 32, 63",
-    ));
-    insns.push((
-        Inst::RxSBG {
-            op: RxSBGOp::Or,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            start_bit: 8,
-            end_bit: 32,
-            rotate_amt: 63,
-        },
-        "EC4508203F56",
-        "rosbg %r4, %r5, 8, 32, 63",
-    ));
-    insns.push((
-        Inst::RxSBG {
-            op: RxSBGOp::Xor,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            start_bit: 8,
-            end_bit: 32,
-            rotate_amt: 63,
-        },
-        "EC4508203F57",
-        "rxsbg %r4, %r5, 8, 32, 63",
-    ));
-    insns.push((
-        Inst::RxSBGTest {
-            op: RxSBGOp::And,
-            rd: gpr(4),
-            rn: gpr(5),
-            start_bit: 8,
-            end_bit: 32,
-            rotate_amt: 63,
-        },
-        "EC4588203F54",
-        "rnsbg %r4, %r5, 136, 32, 63",
-    ));
-    insns.push((
-        Inst::RxSBGTest {
-            op: RxSBGOp::Or,
-            rd: gpr(4),
-            rn: gpr(5),
-            start_bit: 8,
-            end_bit: 32,
-            rotate_amt: 63,
-        },
-        "EC4588203F56",
-        "rosbg %r4, %r5, 136, 32, 63",
-    ));
-    insns.push((
-        Inst::RxSBGTest {
-            op: RxSBGOp::Xor,
-            rd: gpr(4),
-            rn: gpr(5),
-            start_bit: 8,
-            end_bit: 32,
-            rotate_amt: 63,
-        },
-        "EC4588203F57",
-        "rxsbg %r4, %r5, 136, 32, 63",
-    ));
-
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::Add32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: zero_reg(),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB45000080F8",
-        "laa %r4, %r5, -524288",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::Add32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: zero_reg(),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB450FFF7FF8",
-        "laa %r4, %r5, 524287",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::Add32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: gpr(6),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB45600080F8",
-        "laa %r4, %r5, -524288(%r6)",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::Add32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: gpr(6),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB456FFF7FF8",
-        "laa %r4, %r5, 524287(%r6)",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::Add64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: zero_reg(),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB45000080E8",
-        "laag %r4, %r5, -524288",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::Add64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: zero_reg(),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB450FFF7FE8",
-        "laag %r4, %r5, 524287",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::Add64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: gpr(6),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB45600080E8",
-        "laag %r4, %r5, -524288(%r6)",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::Add64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: gpr(6),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB456FFF7FE8",
-        "laag %r4, %r5, 524287(%r6)",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::AddLogical32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: zero_reg(),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB45000080FA",
-        "laal %r4, %r5, -524288",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::AddLogical32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: zero_reg(),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB450FFF7FFA",
-        "laal %r4, %r5, 524287",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::AddLogical32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: gpr(6),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB45600080FA",
-        "laal %r4, %r5, -524288(%r6)",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::AddLogical32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: gpr(6),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB456FFF7FFA",
-        "laal %r4, %r5, 524287(%r6)",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::AddLogical64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: zero_reg(),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB45000080EA",
-        "laalg %r4, %r5, -524288",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::AddLogical64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: zero_reg(),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB450FFF7FEA",
-        "laalg %r4, %r5, 524287",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::AddLogical64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: gpr(6),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB45600080EA",
-        "laalg %r4, %r5, -524288(%r6)",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::AddLogical64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: gpr(6),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB456FFF7FEA",
-        "laalg %r4, %r5, 524287(%r6)",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::And32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: zero_reg(),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB45000080F4",
-        "lan %r4, %r5, -524288",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::And32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: zero_reg(),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB450FFF7FF4",
-        "lan %r4, %r5, 524287",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::And32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: gpr(6),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB45600080F4",
-        "lan %r4, %r5, -524288(%r6)",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::And32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: gpr(6),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB456FFF7FF4",
-        "lan %r4, %r5, 524287(%r6)",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::And64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: zero_reg(),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB45000080E4",
-        "lang %r4, %r5, -524288",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::And64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: zero_reg(),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB450FFF7FE4",
-        "lang %r4, %r5, 524287",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::And64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: gpr(6),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB45600080E4",
-        "lang %r4, %r5, -524288(%r6)",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::And64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: gpr(6),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB456FFF7FE4",
-        "lang %r4, %r5, 524287(%r6)",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::Orr32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: zero_reg(),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB45000080F6",
-        "lao %r4, %r5, -524288",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::Orr32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: zero_reg(),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB450FFF7FF6",
-        "lao %r4, %r5, 524287",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::Orr32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: gpr(6),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB45600080F6",
-        "lao %r4, %r5, -524288(%r6)",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::Orr32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: gpr(6),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB456FFF7FF6",
-        "lao %r4, %r5, 524287(%r6)",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::Orr64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: zero_reg(),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB45000080E6",
-        "laog %r4, %r5, -524288",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::Orr64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: zero_reg(),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB450FFF7FE6",
-        "laog %r4, %r5, 524287",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::Orr64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: gpr(6),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB45600080E6",
-        "laog %r4, %r5, -524288(%r6)",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::Orr64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: gpr(6),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB456FFF7FE6",
-        "laog %r4, %r5, 524287(%r6)",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::Xor32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: zero_reg(),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB45000080F7",
-        "lax %r4, %r5, -524288",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::Xor32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: zero_reg(),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB450FFF7FF7",
-        "lax %r4, %r5, 524287",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::Xor32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: gpr(6),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB45600080F7",
-        "lax %r4, %r5, -524288(%r6)",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::Xor32,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: gpr(6),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB456FFF7FF7",
-        "lax %r4, %r5, 524287(%r6)",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::Xor64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: zero_reg(),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB45000080E7",
-        "laxg %r4, %r5, -524288",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::Xor64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: zero_reg(),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB450FFF7FE7",
-        "laxg %r4, %r5, 524287",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::Xor64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: gpr(6),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB45600080E7",
-        "laxg %r4, %r5, -524288(%r6)",
-    ));
-    insns.push((
-        Inst::AtomicRmw {
-            alu_op: ALUOp::Xor64,
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: gpr(6),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB456FFF7FE7",
-        "laxg %r4, %r5, 524287(%r6)",
-    ));
-    insns.push((
-        Inst::AtomicCas32 {
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD12 {
-                base: zero_reg(),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(0).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "BA450000",
-        "cs %r4, %r5, 0",
-    ));
-    insns.push((
-        Inst::AtomicCas32 {
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD12 {
-                base: zero_reg(),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "BA450FFF",
-        "cs %r4, %r5, 4095",
-    ));
-    insns.push((
-        Inst::AtomicCas32 {
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: zero_reg(),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB4500008014",
-        "csy %r4, %r5, -524288",
-    ));
-    insns.push((
-        Inst::AtomicCas32 {
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: zero_reg(),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB450FFF7F14",
-        "csy %r4, %r5, 524287",
-    ));
-    insns.push((
-        Inst::AtomicCas32 {
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD12 {
-                base: gpr(6),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(0).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "BA456000",
-        "cs %r4, %r5, 0(%r6)",
-    ));
-    insns.push((
-        Inst::AtomicCas32 {
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD12 {
-                base: gpr(6),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "BA456FFF",
-        "cs %r4, %r5, 4095(%r6)",
-    ));
-    insns.push((
-        Inst::AtomicCas32 {
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: gpr(6),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB4560008014",
-        "csy %r4, %r5, -524288(%r6)",
-    ));
-    insns.push((
-        Inst::AtomicCas32 {
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: gpr(6),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB456FFF7F14",
-        "csy %r4, %r5, 524287(%r6)",
-    ));
-    insns.push((
-        Inst::AtomicCas64 {
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: zero_reg(),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB4500008030",
-        "csg %r4, %r5, -524288",
-    ));
-    insns.push((
-        Inst::AtomicCas64 {
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: zero_reg(),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB450FFF7F30",
-        "csg %r4, %r5, 524287",
-    ));
-    insns.push((
-        Inst::AtomicCas64 {
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: gpr(6),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB4560008030",
-        "csg %r4, %r5, -524288(%r6)",
-    ));
-    insns.push((
-        Inst::AtomicCas64 {
-            rd: writable_gpr(4),
-            rn: gpr(5),
-            mem: MemArg::BXD20 {
-                base: gpr(6),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB456FFF7F30",
-        "csg %r4, %r5, 524287(%r6)",
-    ));
-    insns.push((Inst::Fence, "07E0", "bcr 14, 0"));
-
-    insns.push((
-        Inst::Load32 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "58102000",
-        "l %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::Load32 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "58102FFF",
-        "l %r1, 4095(%r2)",
-    ));
-    insns.push((
-        Inst::Load32 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020008058",
-        "ly %r1, -524288(%r2)",
-    ));
-    insns.push((
-        Inst::Load32 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF7F58",
-        "ly %r1, 524287(%r2)",
-    ));
-    insns.push((
-        Inst::Load32 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "58123000",
-        "l %r1, 0(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load32 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "58123FFF",
-        "l %r1, 4095(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load32 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31230008058",
-        "ly %r1, -524288(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load32 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF7F58",
-        "ly %r1, 524287(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load32ZExt8 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020000094",
-        "llc %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::Load32ZExt8 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF0094",
-        "llc %r1, 4095(%r2)",
-    ));
-    insns.push((
-        Inst::Load32ZExt8 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020008094",
-        "llc %r1, -524288(%r2)",
-    ));
-    insns.push((
-        Inst::Load32ZExt8 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF7F94",
-        "llc %r1, 524287(%r2)",
-    ));
-    insns.push((
-        Inst::Load32ZExt8 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31230000094",
-        "llc %r1, 0(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load32ZExt8 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF0094",
-        "llc %r1, 4095(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load32ZExt8 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31230008094",
-        "llc %r1, -524288(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load32ZExt8 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF7F94",
-        "llc %r1, 524287(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load32SExt8 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020000076",
-        "lb %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::Load32SExt8 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF0076",
-        "lb %r1, 4095(%r2)",
-    ));
-    insns.push((
-        Inst::Load32SExt8 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020008076",
-        "lb %r1, -524288(%r2)",
-    ));
-    insns.push((
-        Inst::Load32SExt8 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF7F76",
-        "lb %r1, 524287(%r2)",
-    ));
-    insns.push((
-        Inst::Load32SExt8 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31230000076",
-        "lb %r1, 0(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load32SExt8 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF0076",
-        "lb %r1, 4095(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load32SExt8 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31230008076",
-        "lb %r1, -524288(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load32SExt8 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF7F76",
-        "lb %r1, 524287(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load32ZExt16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020000095",
-        "llh %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::Load32ZExt16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF0095",
-        "llh %r1, 4095(%r2)",
-    ));
-    insns.push((
-        Inst::Load32ZExt16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020008095",
-        "llh %r1, -524288(%r2)",
-    ));
-    insns.push((
-        Inst::Load32ZExt16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF7F95",
-        "llh %r1, 524287(%r2)",
-    ));
-    insns.push((
-        Inst::Load32ZExt16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31230000095",
-        "llh %r1, 0(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load32ZExt16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF0095",
-        "llh %r1, 4095(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load32ZExt16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31230008095",
-        "llh %r1, -524288(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load32ZExt16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF7F95",
-        "llh %r1, 524287(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load32SExt16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "48102000",
-        "lh %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::Load32SExt16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "48102FFF",
-        "lh %r1, 4095(%r2)",
-    ));
-    insns.push((
-        Inst::Load32SExt16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020008078",
-        "lhy %r1, -524288(%r2)",
-    ));
-    insns.push((
-        Inst::Load32SExt16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF7F78",
-        "lhy %r1, 524287(%r2)",
-    ));
-    insns.push((
-        Inst::Load32SExt16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "48123000",
-        "lh %r1, 0(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load32SExt16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "48123FFF",
-        "lh %r1, 4095(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load32SExt16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31230008078",
-        "lhy %r1, -524288(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load32SExt16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF7F78",
-        "lhy %r1, 524287(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load64 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020000004",
-        "lg %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::Load64 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF0004",
-        "lg %r1, 4095(%r2)",
-    ));
-    insns.push((
-        Inst::Load64 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020008004",
-        "lg %r1, -524288(%r2)",
-    ));
-    insns.push((
-        Inst::Load64 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF7F04",
-        "lg %r1, 524287(%r2)",
-    ));
-    insns.push((
-        Inst::Load64 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31230000004",
-        "lg %r1, 0(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load64 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF0004",
-        "lg %r1, 4095(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load64 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31230008004",
-        "lg %r1, -524288(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load64 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF7F04",
-        "lg %r1, 524287(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load64ZExt8 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020000090",
-        "llgc %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::Load64ZExt8 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF0090",
-        "llgc %r1, 4095(%r2)",
-    ));
-    insns.push((
-        Inst::Load64ZExt8 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020008090",
-        "llgc %r1, -524288(%r2)",
-    ));
-    insns.push((
-        Inst::Load64ZExt8 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF7F90",
-        "llgc %r1, 524287(%r2)",
-    ));
-    insns.push((
-        Inst::Load64ZExt8 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31230000090",
-        "llgc %r1, 0(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load64ZExt8 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF0090",
-        "llgc %r1, 4095(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load64ZExt8 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31230008090",
-        "llgc %r1, -524288(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load64ZExt8 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF7F90",
-        "llgc %r1, 524287(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load64SExt8 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020000077",
-        "lgb %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::Load64SExt8 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF0077",
-        "lgb %r1, 4095(%r2)",
-    ));
-    insns.push((
-        Inst::Load64SExt8 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020008077",
-        "lgb %r1, -524288(%r2)",
-    ));
-    insns.push((
-        Inst::Load64SExt8 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF7F77",
-        "lgb %r1, 524287(%r2)",
-    ));
-    insns.push((
-        Inst::Load64SExt8 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31230000077",
-        "lgb %r1, 0(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load64SExt8 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF0077",
-        "lgb %r1, 4095(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load64SExt8 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31230008077",
-        "lgb %r1, -524288(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load64SExt8 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF7F77",
-        "lgb %r1, 524287(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load64ZExt16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020000091",
-        "llgh %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::Load64ZExt16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF0091",
-        "llgh %r1, 4095(%r2)",
-    ));
-    insns.push((
-        Inst::Load64ZExt16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020008091",
-        "llgh %r1, -524288(%r2)",
-    ));
-    insns.push((
-        Inst::Load64ZExt16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF7F91",
-        "llgh %r1, 524287(%r2)",
-    ));
-    insns.push((
-        Inst::Load64ZExt16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31230000091",
-        "llgh %r1, 0(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load64ZExt16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF0091",
-        "llgh %r1, 4095(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load64ZExt16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31230008091",
-        "llgh %r1, -524288(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load64ZExt16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF7F91",
-        "llgh %r1, 524287(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load64SExt16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020000015",
-        "lgh %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::Load64SExt16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF0015",
-        "lgh %r1, 4095(%r2)",
-    ));
-    insns.push((
-        Inst::Load64SExt16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020008015",
-        "lgh %r1, -524288(%r2)",
-    ));
-    insns.push((
-        Inst::Load64SExt16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF7F15",
-        "lgh %r1, 524287(%r2)",
-    ));
-    insns.push((
-        Inst::Load64SExt16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31230000015",
-        "lgh %r1, 0(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load64SExt16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF0015",
-        "lgh %r1, 4095(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load64SExt16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31230008015",
-        "lgh %r1, -524288(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load64SExt16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF7F15",
-        "lgh %r1, 524287(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load64ZExt32 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020000016",
-        "llgf %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::Load64ZExt32 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF0016",
-        "llgf %r1, 4095(%r2)",
-    ));
-    insns.push((
-        Inst::Load64ZExt32 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020008016",
-        "llgf %r1, -524288(%r2)",
-    ));
-    insns.push((
-        Inst::Load64ZExt32 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF7F16",
-        "llgf %r1, 524287(%r2)",
-    ));
-    insns.push((
-        Inst::Load64ZExt32 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31230000016",
-        "llgf %r1, 0(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load64ZExt32 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF0016",
-        "llgf %r1, 4095(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load64ZExt32 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31230008016",
-        "llgf %r1, -524288(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load64ZExt32 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF7F16",
-        "llgf %r1, 524287(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load64SExt32 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020000014",
-        "lgf %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::Load64SExt32 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF0014",
-        "lgf %r1, 4095(%r2)",
-    ));
-    insns.push((
-        Inst::Load64SExt32 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020008014",
-        "lgf %r1, -524288(%r2)",
-    ));
-    insns.push((
-        Inst::Load64SExt32 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF7F14",
-        "lgf %r1, 524287(%r2)",
-    ));
-    insns.push((
-        Inst::Load64SExt32 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31230000014",
-        "lgf %r1, 0(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load64SExt32 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF0014",
-        "lgf %r1, 4095(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load64SExt32 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31230008014",
-        "lgf %r1, -524288(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Load64SExt32 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF7F14",
-        "lgf %r1, 524287(%r2,%r3)",
-    ));
-
-    insns.push((
-        Inst::Load32 {
-            rd: writable_gpr(1),
-            mem: MemArg::Label {
-                target: MachLabel::from_block(1),
-            },
-        },
-        "C41D00000003",
-        "lrl %r1, label1",
-    ));
-    insns.push((
-        Inst::Load32SExt16 {
-            rd: writable_gpr(1),
-            mem: MemArg::Label {
-                target: MachLabel::from_block(1),
-            },
-        },
-        "C41500000003",
-        "lhrl %r1, label1",
-    ));
-    insns.push((
-        Inst::Load32ZExt16 {
-            rd: writable_gpr(1),
-            mem: MemArg::Label {
-                target: MachLabel::from_block(1),
-            },
-        },
-        "C41200000003",
-        "llhrl %r1, label1",
-    ));
-    insns.push((
-        Inst::Load64 {
-            rd: writable_gpr(1),
-            mem: MemArg::Label {
-                target: MachLabel::from_block(1),
-            },
-        },
-        "C41800000003",
-        "lgrl %r1, label1",
-    ));
-    insns.push((
-        Inst::Load64SExt16 {
-            rd: writable_gpr(1),
-            mem: MemArg::Label {
-                target: MachLabel::from_block(1),
-            },
-        },
-        "C41400000003",
-        "lghrl %r1, label1",
-    ));
-    insns.push((
-        Inst::Load64ZExt16 {
-            rd: writable_gpr(1),
-            mem: MemArg::Label {
-                target: MachLabel::from_block(1),
-            },
-        },
-        "C41600000003",
-        "llghrl %r1, label1",
-    ));
-    insns.push((
-        Inst::Load64SExt32 {
-            rd: writable_gpr(1),
-            mem: MemArg::Label {
-                target: MachLabel::from_block(1),
-            },
-        },
-        "C41C00000003",
-        "lgfrl %r1, label1",
-    ));
-    insns.push((
-        Inst::Load64ZExt32 {
-            rd: writable_gpr(1),
-            mem: MemArg::Label {
-                target: MachLabel::from_block(1),
-            },
-        },
-        "C41E00000003",
-        "llgfrl %r1, label1",
-    ));
-    insns.push((
-        Inst::LoadRev16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102000001F",
-        "lrvh %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::LoadRev16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF001F",
-        "lrvh %r1, 4095(%r2)",
-    ));
-    insns.push((
-        Inst::LoadRev16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102000801F",
-        "lrvh %r1, -524288(%r2)",
-    ));
-    insns.push((
-        Inst::LoadRev16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF7F1F",
-        "lrvh %r1, 524287(%r2)",
-    ));
-    insns.push((
-        Inst::LoadRev16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123000001F",
-        "lrvh %r1, 0(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::LoadRev16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF001F",
-        "lrvh %r1, 4095(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::LoadRev16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123000801F",
-        "lrvh %r1, -524288(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::LoadRev16 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF7F1F",
-        "lrvh %r1, 524287(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::LoadRev32 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102000001E",
-        "lrv %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::LoadRev32 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF001E",
-        "lrv %r1, 4095(%r2)",
-    ));
-    insns.push((
-        Inst::LoadRev32 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102000801E",
-        "lrv %r1, -524288(%r2)",
-    ));
-    insns.push((
-        Inst::LoadRev32 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF7F1E",
-        "lrv %r1, 524287(%r2)",
-    ));
-    insns.push((
-        Inst::LoadRev32 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123000001E",
-        "lrv %r1, 0(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::LoadRev32 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF001E",
-        "lrv %r1, 4095(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::LoadRev32 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123000801E",
-        "lrv %r1, -524288(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::LoadRev32 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF7F1E",
-        "lrv %r1, 524287(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::LoadRev64 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102000000F",
-        "lrvg %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::LoadRev64 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF000F",
-        "lrvg %r1, 4095(%r2)",
-    ));
-    insns.push((
-        Inst::LoadRev64 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102000800F",
-        "lrvg %r1, -524288(%r2)",
-    ));
-    insns.push((
-        Inst::LoadRev64 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF7F0F",
-        "lrvg %r1, 524287(%r2)",
-    ));
-    insns.push((
-        Inst::LoadRev64 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123000000F",
-        "lrvg %r1, 0(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::LoadRev64 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF000F",
-        "lrvg %r1, 4095(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::LoadRev64 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123000800F",
-        "lrvg %r1, -524288(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::LoadRev64 {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF7F0F",
-        "lrvg %r1, 524287(%r2,%r3)",
-    ));
-
-    insns.push((
-        Inst::Store8 {
-            rd: gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "42102000",
-        "stc %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::Store8 {
-            rd: gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "42102FFF",
-        "stc %r1, 4095(%r2)",
-    ));
-    insns.push((
-        Inst::Store8 {
-            rd: gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020008072",
-        "stcy %r1, -524288(%r2)",
-    ));
-    insns.push((
-        Inst::Store8 {
-            rd: gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF7F72",
-        "stcy %r1, 524287(%r2)",
-    ));
-    insns.push((
-        Inst::Store8 {
-            rd: gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "42123000",
-        "stc %r1, 0(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Store8 {
-            rd: gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "42123FFF",
-        "stc %r1, 4095(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Store8 {
-            rd: gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31230008072",
-        "stcy %r1, -524288(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Store8 {
-            rd: gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF7F72",
-        "stcy %r1, 524287(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Store16 {
-            rd: gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "40102000",
-        "sth %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::Store16 {
-            rd: gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "40102FFF",
-        "sth %r1, 4095(%r2)",
-    ));
-    insns.push((
-        Inst::Store16 {
-            rd: gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020008070",
-        "sthy %r1, -524288(%r2)",
-    ));
-    insns.push((
-        Inst::Store16 {
-            rd: gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF7F70",
-        "sthy %r1, 524287(%r2)",
-    ));
-    insns.push((
-        Inst::Store16 {
-            rd: gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "40123000",
-        "sth %r1, 0(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Store16 {
-            rd: gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "40123FFF",
-        "sth %r1, 4095(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Store16 {
-            rd: gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31230008070",
-        "sthy %r1, -524288(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Store16 {
-            rd: gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF7F70",
-        "sthy %r1, 524287(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Store32 {
-            rd: gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "50102000",
-        "st %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::Store32 {
-            rd: gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "50102FFF",
-        "st %r1, 4095(%r2)",
-    ));
-    insns.push((
-        Inst::Store32 {
-            rd: gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020008050",
-        "sty %r1, -524288(%r2)",
-    ));
-    insns.push((
-        Inst::Store32 {
-            rd: gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF7F50",
-        "sty %r1, 524287(%r2)",
-    ));
-    insns.push((
-        Inst::Store32 {
-            rd: gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "50123000",
-        "st %r1, 0(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Store32 {
-            rd: gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "50123FFF",
-        "st %r1, 4095(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Store32 {
-            rd: gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31230008050",
-        "sty %r1, -524288(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Store32 {
-            rd: gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF7F50",
-        "sty %r1, 524287(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Store64 {
-            rd: gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020000024",
-        "stg %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::Store64 {
-            rd: gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF0024",
-        "stg %r1, 4095(%r2)",
-    ));
-    insns.push((
-        Inst::Store64 {
-            rd: gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020008024",
-        "stg %r1, -524288(%r2)",
-    ));
-    insns.push((
-        Inst::Store64 {
-            rd: gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF7F24",
-        "stg %r1, 524287(%r2)",
-    ));
-    insns.push((
-        Inst::Store64 {
-            rd: gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31230000024",
-        "stg %r1, 0(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Store64 {
-            rd: gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF0024",
-        "stg %r1, 4095(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Store64 {
-            rd: gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31230008024",
-        "stg %r1, -524288(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::Store64 {
-            rd: gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF7F24",
-        "stg %r1, 524287(%r2,%r3)",
-    ));
-
-    insns.push((
-        Inst::StoreImm8 {
-            imm: 255,
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "92FF2000",
-        "mvi 0(%r2), 255",
-    ));
-    insns.push((
-        Inst::StoreImm8 {
-            imm: 0,
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "92002FFF",
-        "mvi 4095(%r2), 0",
-    ));
-    insns.push((
-        Inst::StoreImm8 {
-            imm: 255,
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EBFF20008052",
-        "mviy -524288(%r2), 255",
-    ));
-    insns.push((
-        Inst::StoreImm8 {
-            imm: 0,
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB002FFF7F52",
-        "mviy 524287(%r2), 0",
-    ));
-    insns.push((
-        Inst::StoreImm16 {
-            imm: -32768,
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E54420008000",
-        "mvhhi 0(%r2), -32768",
-    ));
-    insns.push((
-        Inst::StoreImm16 {
-            imm: 32767,
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E5442FFF7FFF",
-        "mvhhi 4095(%r2), 32767",
-    ));
-    insns.push((
-        Inst::StoreImm32SExt16 {
-            imm: -32768,
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E54C20008000",
-        "mvhi 0(%r2), -32768",
-    ));
-    insns.push((
-        Inst::StoreImm32SExt16 {
-            imm: 32767,
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E54C2FFF7FFF",
-        "mvhi 4095(%r2), 32767",
-    ));
-    insns.push((
-        Inst::StoreImm64SExt16 {
-            imm: -32768,
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E54820008000",
-        "mvghi 0(%r2), -32768",
-    ));
-    insns.push((
-        Inst::StoreImm64SExt16 {
-            imm: 32767,
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E5482FFF7FFF",
-        "mvghi 4095(%r2), 32767",
-    ));
-
-    insns.push((
-        Inst::StoreRev16 {
-            rd: gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102000003F",
-        "strvh %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::StoreRev16 {
-            rd: gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF003F",
-        "strvh %r1, 4095(%r2)",
-    ));
-    insns.push((
-        Inst::StoreRev16 {
-            rd: gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102000803F",
-        "strvh %r1, -524288(%r2)",
-    ));
-    insns.push((
-        Inst::StoreRev16 {
-            rd: gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF7F3F",
-        "strvh %r1, 524287(%r2)",
-    ));
-    insns.push((
-        Inst::StoreRev16 {
-            rd: gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123000003F",
-        "strvh %r1, 0(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::StoreRev16 {
-            rd: gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF003F",
-        "strvh %r1, 4095(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::StoreRev16 {
-            rd: gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123000803F",
-        "strvh %r1, -524288(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::StoreRev16 {
-            rd: gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF7F3F",
-        "strvh %r1, 524287(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::StoreRev32 {
-            rd: gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102000003E",
-        "strv %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::StoreRev32 {
-            rd: gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF003E",
-        "strv %r1, 4095(%r2)",
-    ));
-    insns.push((
-        Inst::StoreRev32 {
-            rd: gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102000803E",
-        "strv %r1, -524288(%r2)",
-    ));
-    insns.push((
-        Inst::StoreRev32 {
-            rd: gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF7F3E",
-        "strv %r1, 524287(%r2)",
-    ));
-    insns.push((
-        Inst::StoreRev32 {
-            rd: gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123000003E",
-        "strv %r1, 0(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::StoreRev32 {
-            rd: gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF003E",
-        "strv %r1, 4095(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::StoreRev32 {
-            rd: gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123000803E",
-        "strv %r1, -524288(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::StoreRev32 {
-            rd: gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF7F3E",
-        "strv %r1, 524287(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::StoreRev64 {
-            rd: gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102000002F",
-        "strvg %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::StoreRev64 {
-            rd: gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF002F",
-        "strvg %r1, 4095(%r2)",
-    ));
-    insns.push((
-        Inst::StoreRev64 {
-            rd: gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102000802F",
-        "strvg %r1, -524288(%r2)",
-    ));
-    insns.push((
-        Inst::StoreRev64 {
-            rd: gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF7F2F",
-        "strvg %r1, 524287(%r2)",
-    ));
-    insns.push((
-        Inst::StoreRev64 {
-            rd: gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123000002F",
-        "strvg %r1, 0(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::StoreRev64 {
-            rd: gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF002F",
-        "strvg %r1, 4095(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::StoreRev64 {
-            rd: gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123000802F",
-        "strvg %r1, -524288(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::StoreRev64 {
-            rd: gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF7F2F",
-        "strvg %r1, 524287(%r2,%r3)",
-    ));
-
-    insns.push((
-        Inst::Store16 {
-            rd: gpr(1),
-            mem: MemArg::Label {
-                target: MachLabel::from_block(1),
-            },
-        },
-        "C41700000003",
-        "sthrl %r1, label1",
-    ));
-    insns.push((
-        Inst::Store32 {
-            rd: gpr(1),
-            mem: MemArg::Label {
-                target: MachLabel::from_block(1),
-            },
-        },
-        "C41F00000003",
-        "strl %r1, label1",
-    ));
-    insns.push((
-        Inst::Store64 {
-            rd: gpr(1),
-            mem: MemArg::Label {
-                target: MachLabel::from_block(1),
-            },
-        },
-        "C41B00000003",
-        "stgrl %r1, label1",
-    ));
-
-    insns.push((
-        Inst::LoadMultiple64 {
-            rt: writable_gpr(8),
-            rt2: writable_gpr(12),
-            mem: MemArg::BXD20 {
-                base: gpr(15),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB8CF0008004",
-        "lmg %r8, %r12, -524288(%r15)",
-    ));
-    insns.push((
-        Inst::LoadMultiple64 {
-            rt: writable_gpr(8),
-            rt2: writable_gpr(12),
-            mem: MemArg::BXD20 {
-                base: gpr(15),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB8CFFFF7F04",
-        "lmg %r8, %r12, 524287(%r15)",
-    ));
-
-    insns.push((
-        Inst::StoreMultiple64 {
-            rt: gpr(8),
-            rt2: gpr(12),
-            mem: MemArg::BXD20 {
-                base: gpr(15),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB8CF0008024",
-        "stmg %r8, %r12, -524288(%r15)",
-    ));
-    insns.push((
-        Inst::StoreMultiple64 {
-            rt: gpr(8),
-            rt2: gpr(12),
-            mem: MemArg::BXD20 {
-                base: gpr(15),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "EB8CFFFF7F24",
-        "stmg %r8, %r12, 524287(%r15)",
-    ));
-
-    insns.push((
-        Inst::LoadAddr {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: zero_reg(),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "41100000",
-        "la %r1, 0",
-    ));
-    insns.push((
-        Inst::LoadAddr {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: zero_reg(),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "41100FFF",
-        "la %r1, 4095",
-    ));
-    insns.push((
-        Inst::LoadAddr {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: zero_reg(),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31000008071",
-        "lay %r1, -524288",
-    ));
-    insns.push((
-        Inst::LoadAddr {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: zero_reg(),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3100FFF7F71",
-        "lay %r1, 524287",
-    ));
-    insns.push((
-        Inst::LoadAddr {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "41102000",
-        "la %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::LoadAddr {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "41102FFF",
-        "la %r1, 4095(%r2)",
-    ));
-    insns.push((
-        Inst::LoadAddr {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020008071",
-        "lay %r1, -524288(%r2)",
-    ));
-    insns.push((
-        Inst::LoadAddr {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF7F71",
-        "lay %r1, 524287(%r2)",
-    ));
-    insns.push((
-        Inst::LoadAddr {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "41123000",
-        "la %r1, 0(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::LoadAddr {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "41123FFF",
-        "la %r1, 4095(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::LoadAddr {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31230008071",
-        "lay %r1, -524288(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::LoadAddr {
-            rd: writable_gpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF7F71",
-        "lay %r1, 524287(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::LoadAddr {
-            rd: writable_gpr(1),
-            mem: MemArg::Label {
-                target: MachLabel::from_block(1),
-            },
-        },
-        "C01000000003",
-        "larl %r1, label1",
-    ));
-    insns.push((
-        Inst::LoadAddr {
-            rd: writable_gpr(1),
-            mem: MemArg::Symbol {
-                name: Box::new(ExternalName::testcase("test0")),
-                offset: 64,
-                flags: MemFlags::trusted(),
-            },
-        },
-        "C01000000000",
-        "larl %r1, %test0 + 64",
-    ));
-
-    insns.push((
-        Inst::LoadAddr {
-            rd: writable_gpr(1),
-            mem: MemArg::RegOffset {
-                reg: gpr(2),
-                off: 0,
-                flags: MemFlags::trusted(),
-            },
-        },
-        "41102000",
-        "la %r1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::LoadAddr {
-            rd: writable_gpr(1),
-            mem: MemArg::RegOffset {
-                reg: gpr(2),
-                off: 4095,
-                flags: MemFlags::trusted(),
-            },
-        },
-        "41102FFF",
-        "la %r1, 4095(%r2)",
-    ));
-    insns.push((
-        Inst::LoadAddr {
-            rd: writable_gpr(1),
-            mem: MemArg::RegOffset {
-                reg: gpr(2),
-                off: -524288,
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020008071",
-        "lay %r1, -524288(%r2)",
-    ));
-    insns.push((
-        Inst::LoadAddr {
-            rd: writable_gpr(1),
-            mem: MemArg::RegOffset {
-                reg: gpr(2),
-                off: 524287,
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF7F71",
-        "lay %r1, 524287(%r2)",
-    ));
-    insns.push((
-        Inst::LoadAddr {
-            rd: writable_gpr(1),
-            mem: MemArg::RegOffset {
-                reg: gpr(2),
-                off: -2147483648,
-                flags: MemFlags::trusted(),
-            },
-        },
-        "C0118000000041112000",
-        "lgfi %r1, -2147483648 ; la %r1, 0(%r1,%r2)",
-    ));
-    insns.push((
-        Inst::LoadAddr {
-            rd: writable_gpr(1),
-            mem: MemArg::RegOffset {
-                reg: gpr(2),
-                off: 2147483647,
-                flags: MemFlags::trusted(),
-            },
-        },
-        "C0117FFFFFFF41112000",
-        "lgfi %r1, 2147483647 ; la %r1, 0(%r1,%r2)",
-    ));
-    insns.push((
-        Inst::LoadAddr {
-            rd: writable_gpr(1),
-            mem: MemArg::RegOffset {
-                reg: gpr(2),
-                off: -9223372036854775808,
-                flags: MemFlags::trusted(),
-            },
-        },
-        "A51C800041112000",
-        "llihh %r1, 32768 ; la %r1, 0(%r1,%r2)",
-    ));
-    insns.push((
-        Inst::LoadAddr {
-            rd: writable_gpr(1),
-            mem: MemArg::RegOffset {
-                reg: gpr(2),
-                off: 9223372036854775807,
-                flags: MemFlags::trusted(),
-            },
-        },
-        "C01E7FFFFFFFC019FFFFFFFF41112000",
-        "llihf %r1, 2147483647 ; iilf %r1, 4294967295 ; la %r1, 0(%r1,%r2)",
-    ));
-
-    insns.push((
-        Inst::Mov64 {
-            rd: writable_gpr(8),
-            rm: gpr(9),
-        },
-        "B9040089",
-        "lgr %r8, %r9",
-    ));
-    insns.push((
-        Inst::Mov32 {
-            rd: writable_gpr(8),
-            rm: gpr(9),
-        },
-        "1889",
-        "lr %r8, %r9",
-    ));
-
-    insns.push((
-        Inst::Mov32SImm16 {
-            rd: writable_gpr(8),
-            imm: -32768,
-        },
-        "A7888000",
-        "lhi %r8, -32768",
-    ));
-    insns.push((
-        Inst::Mov32SImm16 {
-            rd: writable_gpr(8),
-            imm: 32767,
-        },
-        "A7887FFF",
-        "lhi %r8, 32767",
-    ));
-    insns.push((
-        Inst::Mov32Imm {
-            rd: writable_gpr(8),
-            imm: 2147483648,
-        },
-        "C08980000000",
-        "iilf %r8, 2147483648",
-    ));
-    insns.push((
-        Inst::Mov32Imm {
-            rd: writable_gpr(8),
-            imm: 2147483647,
-        },
-        "C0897FFFFFFF",
-        "iilf %r8, 2147483647",
-    ));
-    insns.push((
-        Inst::Mov64SImm16 {
-            rd: writable_gpr(8),
-            imm: -32768,
-        },
-        "A7898000",
-        "lghi %r8, -32768",
-    ));
-    insns.push((
-        Inst::Mov64SImm16 {
-            rd: writable_gpr(8),
-            imm: 32767,
-        },
-        "A7897FFF",
-        "lghi %r8, 32767",
-    ));
-    insns.push((
-        Inst::Mov64SImm32 {
-            rd: writable_gpr(8),
-            imm: -2147483648,
-        },
-        "C08180000000",
-        "lgfi %r8, -2147483648",
-    ));
-    insns.push((
-        Inst::Mov64SImm32 {
-            rd: writable_gpr(8),
-            imm: 2147483647,
-        },
-        "C0817FFFFFFF",
-        "lgfi %r8, 2147483647",
-    ));
-    insns.push((
-        Inst::Mov64UImm16Shifted {
-            rd: writable_gpr(8),
-            imm: UImm16Shifted::maybe_from_u64(0x0000_0000_0000_ffff).unwrap(),
-        },
-        "A58FFFFF",
-        "llill %r8, 65535",
-    ));
-    insns.push((
-        Inst::Mov64UImm16Shifted {
-            rd: writable_gpr(8),
-            imm: UImm16Shifted::maybe_from_u64(0x0000_0000_ffff_0000).unwrap(),
-        },
-        "A58EFFFF",
-        "llilh %r8, 65535",
-    ));
-    insns.push((
-        Inst::Mov64UImm16Shifted {
-            rd: writable_gpr(8),
-            imm: UImm16Shifted::maybe_from_u64(0x0000_ffff_0000_0000).unwrap(),
-        },
-        "A58DFFFF",
-        "llihl %r8, 65535",
-    ));
-    insns.push((
-        Inst::Mov64UImm16Shifted {
-            rd: writable_gpr(8),
-            imm: UImm16Shifted::maybe_from_u64(0xffff_0000_0000_0000).unwrap(),
-        },
-        "A58CFFFF",
-        "llihh %r8, 65535",
-    ));
-    insns.push((
-        Inst::Mov64UImm32Shifted {
-            rd: writable_gpr(8),
-            imm: UImm32Shifted::maybe_from_u64(0x0000_0000_ffff_ffff).unwrap(),
-        },
-        "C08FFFFFFFFF",
-        "llilf %r8, 4294967295",
-    ));
-    insns.push((
-        Inst::Mov64UImm32Shifted {
-            rd: writable_gpr(8),
-            imm: UImm32Shifted::maybe_from_u64(0xffff_ffff_0000_0000).unwrap(),
-        },
-        "C08EFFFFFFFF",
-        "llihf %r8, 4294967295",
-    ));
-
-    insns.push((
-        Inst::Insert64UImm16Shifted {
-            rd: writable_gpr(8),
-            imm: UImm16Shifted::maybe_from_u64(0x0000_0000_0000_ffff).unwrap(),
-        },
-        "A583FFFF",
-        "iill %r8, 65535",
-    ));
-    insns.push((
-        Inst::Insert64UImm16Shifted {
-            rd: writable_gpr(8),
-            imm: UImm16Shifted::maybe_from_u64(0x0000_0000_ffff_0000).unwrap(),
-        },
-        "A582FFFF",
-        "iilh %r8, 65535",
-    ));
-    insns.push((
-        Inst::Insert64UImm16Shifted {
-            rd: writable_gpr(8),
-            imm: UImm16Shifted::maybe_from_u64(0x0000_ffff_0000_0000).unwrap(),
-        },
-        "A581FFFF",
-        "iihl %r8, 65535",
-    ));
-    insns.push((
-        Inst::Insert64UImm16Shifted {
-            rd: writable_gpr(8),
-            imm: UImm16Shifted::maybe_from_u64(0xffff_0000_0000_0000).unwrap(),
-        },
-        "A580FFFF",
-        "iihh %r8, 65535",
-    ));
-    insns.push((
-        Inst::Insert64UImm32Shifted {
-            rd: writable_gpr(8),
-            imm: UImm32Shifted::maybe_from_u64(0x0000_0000_ffff_ffff).unwrap(),
-        },
-        "C089FFFFFFFF",
-        "iilf %r8, 4294967295",
-    ));
-    insns.push((
-        Inst::Insert64UImm32Shifted {
-            rd: writable_gpr(8),
-            imm: UImm32Shifted::maybe_from_u64(0xffff_ffff_0000_0000).unwrap(),
-        },
-        "C088FFFFFFFF",
-        "iihf %r8, 4294967295",
-    ));
-
-    insns.push((
-        Inst::CMov32 {
-            rd: writable_gpr(8),
-            cond: Cond::from_mask(1),
-            rm: gpr(9),
-        },
-        "B9F21089",
-        "locro %r8, %r9",
-    ));
-    insns.push((
-        Inst::CMov64 {
-            rd: writable_gpr(8),
-            cond: Cond::from_mask(1),
-            rm: gpr(9),
-        },
-        "B9E21089",
-        "locgro %r8, %r9",
-    ));
-
-    insns.push((
-        Inst::CMov32SImm16 {
-            rd: writable_gpr(8),
-            cond: Cond::from_mask(1),
-            imm: -32768,
-        },
-        "EC8180000042",
-        "lochio %r8, -32768",
-    ));
-    insns.push((
-        Inst::CMov32SImm16 {
-            rd: writable_gpr(8),
-            cond: Cond::from_mask(1),
-            imm: 32767,
-        },
-        "EC817FFF0042",
-        "lochio %r8, 32767",
-    ));
-    insns.push((
-        Inst::CMov64SImm16 {
-            rd: writable_gpr(8),
-            cond: Cond::from_mask(1),
-            imm: -32768,
-        },
-        "EC8180000046",
-        "locghio %r8, -32768",
-    ));
-    insns.push((
-        Inst::CMov64SImm16 {
-            rd: writable_gpr(8),
-            cond: Cond::from_mask(1),
-            imm: 32767,
-        },
-        "EC817FFF0046",
-        "locghio %r8, 32767",
-    ));
-
-    insns.push((
-        Inst::Extend {
-            rd: writable_gpr(1),
-            rn: gpr(2),
-            signed: false,
-            from_bits: 8,
-            to_bits: 32,
-        },
-        "B9940012",
-        "llcr %r1, %r2",
-    ));
-    insns.push((
-        Inst::Extend {
-            rd: writable_gpr(1),
-            rn: gpr(2),
-            signed: true,
-            from_bits: 8,
-            to_bits: 32,
-        },
-        "B9260012",
-        "lbr %r1, %r2",
-    ));
-    insns.push((
-        Inst::Extend {
-            rd: writable_gpr(1),
-            rn: gpr(2),
-            signed: false,
-            from_bits: 16,
-            to_bits: 32,
-        },
-        "B9950012",
-        "llhr %r1, %r2",
-    ));
-    insns.push((
-        Inst::Extend {
-            rd: writable_gpr(1),
-            rn: gpr(2),
-            signed: true,
-            from_bits: 16,
-            to_bits: 32,
-        },
-        "B9270012",
-        "lhr %r1, %r2",
-    ));
-    insns.push((
-        Inst::Extend {
-            rd: writable_gpr(1),
-            rn: gpr(2),
-            signed: false,
-            from_bits: 8,
-            to_bits: 64,
-        },
-        "B9840012",
-        "llgcr %r1, %r2",
-    ));
-    insns.push((
-        Inst::Extend {
-            rd: writable_gpr(1),
-            rn: gpr(2),
-            signed: true,
-            from_bits: 8,
-            to_bits: 64,
-        },
-        "B9060012",
-        "lgbr %r1, %r2",
-    ));
-    insns.push((
-        Inst::Extend {
-            rd: writable_gpr(1),
-            rn: gpr(2),
-            signed: false,
-            from_bits: 16,
-            to_bits: 64,
-        },
-        "B9850012",
-        "llghr %r1, %r2",
-    ));
-    insns.push((
-        Inst::Extend {
-            rd: writable_gpr(1),
-            rn: gpr(2),
-            signed: true,
-            from_bits: 16,
-            to_bits: 64,
-        },
-        "B9070012",
-        "lghr %r1, %r2",
-    ));
-    insns.push((
-        Inst::Extend {
-            rd: writable_gpr(1),
-            rn: gpr(2),
-            signed: false,
-            from_bits: 32,
-            to_bits: 64,
-        },
-        "B9160012",
-        "llgfr %r1, %r2",
-    ));
-    insns.push((
-        Inst::Extend {
-            rd: writable_gpr(1),
-            rn: gpr(2),
-            signed: true,
-            from_bits: 32,
-            to_bits: 64,
-        },
-        "B9140012",
-        "lgfr %r1, %r2",
-    ));
-
-    insns.push((
-        Inst::Jump {
-            dest: MachLabel::from_block(0),
-        },
-        "C0F400000000",
-        "jg label0",
-    ));
-
-    insns.push((
-        Inst::OneWayCondBr {
-            target: MachLabel::from_block(0),
-            cond: Cond::from_mask(1),
-        },
-        "C01400000000",
-        "jgo label0",
-    ));
-    insns.push((
-        Inst::OneWayCondBr {
-            target: MachLabel::from_block(0),
-            cond: Cond::from_mask(2),
-        },
-        "C02400000000",
-        "jgh label0",
-    ));
-    insns.push((
-        Inst::OneWayCondBr {
-            target: MachLabel::from_block(0),
-            cond: Cond::from_mask(3),
-        },
-        "C03400000000",
-        "jgnle label0",
-    ));
-    insns.push((
-        Inst::OneWayCondBr {
-            target: MachLabel::from_block(0),
-            cond: Cond::from_mask(4),
-        },
-        "C04400000000",
-        "jgl label0",
-    ));
-    insns.push((
-        Inst::OneWayCondBr {
-            target: MachLabel::from_block(0),
-            cond: Cond::from_mask(5),
-        },
-        "C05400000000",
-        "jgnhe label0",
-    ));
-    insns.push((
-        Inst::OneWayCondBr {
-            target: MachLabel::from_block(0),
-            cond: Cond::from_mask(6),
-        },
-        "C06400000000",
-        "jglh label0",
-    ));
-    insns.push((
-        Inst::OneWayCondBr {
-            target: MachLabel::from_block(0),
-            cond: Cond::from_mask(7),
-        },
-        "C07400000000",
-        "jgne label0",
-    ));
-    insns.push((
-        Inst::OneWayCondBr {
-            target: MachLabel::from_block(0),
-            cond: Cond::from_mask(8),
-        },
-        "C08400000000",
-        "jge label0",
-    ));
-    insns.push((
-        Inst::OneWayCondBr {
-            target: MachLabel::from_block(0),
-            cond: Cond::from_mask(9),
-        },
-        "C09400000000",
-        "jgnlh label0",
-    ));
-    insns.push((
-        Inst::OneWayCondBr {
-            target: MachLabel::from_block(0),
-            cond: Cond::from_mask(10),
-        },
-        "C0A400000000",
-        "jghe label0",
-    ));
-    insns.push((
-        Inst::OneWayCondBr {
-            target: MachLabel::from_block(0),
-            cond: Cond::from_mask(11),
-        },
-        "C0B400000000",
-        "jgnl label0",
-    ));
-    insns.push((
-        Inst::OneWayCondBr {
-            target: MachLabel::from_block(0),
-            cond: Cond::from_mask(12),
-        },
-        "C0C400000000",
-        "jgle label0",
-    ));
-    insns.push((
-        Inst::OneWayCondBr {
-            target: MachLabel::from_block(0),
-            cond: Cond::from_mask(13),
-        },
-        "C0D400000000",
-        "jgnh label0",
-    ));
-    insns.push((
-        Inst::OneWayCondBr {
-            target: MachLabel::from_block(0),
-            cond: Cond::from_mask(14),
-        },
-        "C0E400000000",
-        "jgno label0",
-    ));
-
-    insns.push((
-        Inst::CondBr {
-            taken: MachLabel::from_block(0),
-            not_taken: MachLabel::from_block(0),
-            cond: Cond::from_mask(1),
-        },
-        "C01400000000C0F4FFFFFFFD",
-        "jgo label0 ; jg label0",
-    ));
-    insns.push((
-        Inst::CondBr {
-            taken: MachLabel::from_block(0),
-            not_taken: MachLabel::from_block(0),
-            cond: Cond::from_mask(2),
-        },
-        "C02400000000C0F4FFFFFFFD",
-        "jgh label0 ; jg label0",
-    ));
-    insns.push((
-        Inst::CondBr {
-            taken: MachLabel::from_block(0),
-            not_taken: MachLabel::from_block(0),
-            cond: Cond::from_mask(3),
-        },
-        "C03400000000C0F4FFFFFFFD",
-        "jgnle label0 ; jg label0",
-    ));
-    insns.push((
-        Inst::CondBr {
-            taken: MachLabel::from_block(0),
-            not_taken: MachLabel::from_block(0),
-            cond: Cond::from_mask(4),
-        },
-        "C04400000000C0F4FFFFFFFD",
-        "jgl label0 ; jg label0",
-    ));
-    insns.push((
-        Inst::CondBr {
-            taken: MachLabel::from_block(0),
-            not_taken: MachLabel::from_block(0),
-            cond: Cond::from_mask(5),
-        },
-        "C05400000000C0F4FFFFFFFD",
-        "jgnhe label0 ; jg label0",
-    ));
-    insns.push((
-        Inst::CondBr {
-            taken: MachLabel::from_block(0),
-            not_taken: MachLabel::from_block(0),
-            cond: Cond::from_mask(6),
-        },
-        "C06400000000C0F4FFFFFFFD",
-        "jglh label0 ; jg label0",
-    ));
-    insns.push((
-        Inst::CondBr {
-            taken: MachLabel::from_block(0),
-            not_taken: MachLabel::from_block(0),
-            cond: Cond::from_mask(7),
-        },
-        "C07400000000C0F4FFFFFFFD",
-        "jgne label0 ; jg label0",
-    ));
-    insns.push((
-        Inst::CondBr {
-            taken: MachLabel::from_block(0),
-            not_taken: MachLabel::from_block(0),
-            cond: Cond::from_mask(8),
-        },
-        "C08400000000C0F4FFFFFFFD",
-        "jge label0 ; jg label0",
-    ));
-    insns.push((
-        Inst::CondBr {
-            taken: MachLabel::from_block(0),
-            not_taken: MachLabel::from_block(0),
-            cond: Cond::from_mask(9),
-        },
-        "C09400000000C0F4FFFFFFFD",
-        "jgnlh label0 ; jg label0",
-    ));
-    insns.push((
-        Inst::CondBr {
-            taken: MachLabel::from_block(0),
-            not_taken: MachLabel::from_block(0),
-            cond: Cond::from_mask(10),
-        },
-        "C0A400000000C0F4FFFFFFFD",
-        "jghe label0 ; jg label0",
-    ));
-    insns.push((
-        Inst::CondBr {
-            taken: MachLabel::from_block(0),
-            not_taken: MachLabel::from_block(0),
-            cond: Cond::from_mask(11),
-        },
-        "C0B400000000C0F4FFFFFFFD",
-        "jgnl label0 ; jg label0",
-    ));
-    insns.push((
-        Inst::CondBr {
-            taken: MachLabel::from_block(0),
-            not_taken: MachLabel::from_block(0),
-            cond: Cond::from_mask(12),
-        },
-        "C0C400000000C0F4FFFFFFFD",
-        "jgle label0 ; jg label0",
-    ));
-    insns.push((
-        Inst::CondBr {
-            taken: MachLabel::from_block(0),
-            not_taken: MachLabel::from_block(0),
-            cond: Cond::from_mask(13),
-        },
-        "C0D400000000C0F4FFFFFFFD",
-        "jgnh label0 ; jg label0",
-    ));
-    insns.push((
-        Inst::CondBr {
-            taken: MachLabel::from_block(0),
-            not_taken: MachLabel::from_block(0),
-            cond: Cond::from_mask(14),
-        },
-        "C0E400000000C0F4FFFFFFFD",
-        "jgno label0 ; jg label0",
-    ));
-
-    insns.push((
-        Inst::IndirectBr {
-            rn: gpr(3),
-            targets: vec![],
-        },
-        "07F3",
-        "br %r3",
-    ));
-
-    insns.push((
-        Inst::Call {
-            link: writable_gpr(14),
-            info: Box::new(CallInfo {
-                dest: ExternalName::testcase("test0"),
-                uses: Vec::new(),
-                defs: Vec::new(),
-                opcode: Opcode::Call,
-            }),
-        },
-        "C0E500000000",
-        "brasl %r14, %test0",
-    ));
-
-    insns.push((
-        Inst::CallInd {
-            link: writable_gpr(14),
-            info: Box::new(CallIndInfo {
-                rn: gpr(1),
-                uses: Vec::new(),
-                defs: Vec::new(),
-                opcode: Opcode::CallIndirect,
-            }),
-        },
-        "0DE1",
-        "basr %r14, %r1",
-    ));
-
-    insns.push((Inst::Ret { link: gpr(14) }, "07FE", "br %r14"));
-
-    insns.push((Inst::Debugtrap, "0001", "debugtrap"));
-
-    insns.push((
-        Inst::Trap {
-            trap_code: TrapCode::StackOverflow,
-        },
-        "0000",
-        "trap",
-    ));
-    insns.push((
-        Inst::TrapIf {
-            cond: Cond::from_mask(1),
-            trap_code: TrapCode::StackOverflow,
-        },
-        "A7E400030000",
-        "jno 6 ; trap",
-    ));
-
-    insns.push((
-        Inst::Loop {
-            body: vec![
-                Inst::CmpRR {
-                    op: CmpOp::CmpS32,
-                    rn: gpr(2),
-                    rm: gpr(3),
-                },
-                Inst::CondBreak {
-                    cond: Cond::from_mask(13),
-                },
-                Inst::AtomicCas32 {
-                    rd: writable_gpr(4),
-                    rn: gpr(5),
-                    mem: MemArg::BXD12 {
-                        base: gpr(6),
-                        index: zero_reg(),
-                        disp: UImm12::maybe_from_u64(0).unwrap(),
-                        flags: MemFlags::trusted(),
-                    },
-                },
-            ],
-            cond: Cond::from_mask(6),
-        },
-        "1923C0D400000008BA456000C064FFFFFFFA",
-        "0: cr %r2, %r3 ; jgnh 1f ; cs %r4, %r5, 0(%r6) ; jglh 0b ; 1:",
-    ));
-
-    insns.push((
-        Inst::FpuMove32 {
-            rd: writable_fpr(8),
-            rn: fpr(4),
-        },
-        "3884",
-        "ler %f8, %f4",
-    ));
-    insns.push((
-        Inst::FpuMove64 {
-            rd: writable_fpr(8),
-            rn: fpr(4),
-        },
-        "2884",
-        "ldr %f8, %f4",
-    ));
-    insns.push((
-        Inst::FpuCMov32 {
-            rd: writable_fpr(8),
-            rm: fpr(4),
-            cond: Cond::from_mask(1),
-        },
-        "A7E400033884",
-        "jno 6 ; ler %f8, %f4",
-    ));
-    insns.push((
-        Inst::FpuCMov64 {
-            rd: writable_fpr(8),
-            rm: fpr(4),
-            cond: Cond::from_mask(1),
-        },
-        "A7E400032884",
-        "jno 6 ; ldr %f8, %f4",
-    ));
-
-    insns.push((
-        Inst::MovToFpr {
-            rd: writable_fpr(8),
-            rn: gpr(4),
-        },
-        "B3C10084",
-        "ldgr %f8, %r4",
-    ));
-    insns.push((
-        Inst::MovFromFpr {
-            rd: writable_gpr(8),
-            rn: fpr(4),
-        },
-        "B3CD0084",
-        "lgdr %r8, %f4",
-    ));
-
-    insns.push((
-        Inst::FpuRR {
-            fpu_op: FPUOp1::Abs32,
-            rd: writable_fpr(8),
-            rn: fpr(12),
-        },
-        "B300008C",
-        "lpebr %f8, %f12",
-    ));
-    insns.push((
-        Inst::FpuRR {
-            fpu_op: FPUOp1::Abs64,
-            rd: writable_fpr(8),
-            rn: fpr(12),
-        },
-        "B310008C",
-        "lpdbr %f8, %f12",
-    ));
-    insns.push((
-        Inst::FpuRR {
-            fpu_op: FPUOp1::Neg32,
-            rd: writable_fpr(8),
-            rn: fpr(12),
-        },
-        "B303008C",
-        "lcebr %f8, %f12",
-    ));
-    insns.push((
-        Inst::FpuRR {
-            fpu_op: FPUOp1::Neg64,
-            rd: writable_fpr(8),
-            rn: fpr(12),
-        },
-        "B313008C",
-        "lcdbr %f8, %f12",
-    ));
-    insns.push((
-        Inst::FpuRR {
-            fpu_op: FPUOp1::NegAbs32,
-            rd: writable_fpr(8),
-            rn: fpr(12),
-        },
-        "B301008C",
-        "lnebr %f8, %f12",
-    ));
-    insns.push((
-        Inst::FpuRR {
-            fpu_op: FPUOp1::NegAbs64,
-            rd: writable_fpr(8),
-            rn: fpr(12),
-        },
-        "B311008C",
-        "lndbr %f8, %f12",
-    ));
-    insns.push((
-        Inst::FpuRR {
-            fpu_op: FPUOp1::Sqrt32,
-            rd: writable_fpr(8),
-            rn: fpr(12),
-        },
-        "B314008C",
-        "sqebr %f8, %f12",
-    ));
-    insns.push((
-        Inst::FpuRR {
-            fpu_op: FPUOp1::Sqrt64,
-            rd: writable_fpr(8),
-            rn: fpr(12),
-        },
-        "B315008C",
-        "sqdbr %f8, %f12",
-    ));
-    insns.push((
-        Inst::FpuRR {
-            fpu_op: FPUOp1::Cvt32To64,
-            rd: writable_fpr(8),
-            rn: fpr(12),
-        },
-        "B304008C",
-        "ldebr %f8, %f12",
-    ));
-    insns.push((
-        Inst::FpuRR {
-            fpu_op: FPUOp1::Cvt64To32,
-            rd: writable_fpr(8),
-            rn: fpr(12),
-        },
-        "B344008C",
-        "ledbr %f8, %f12",
-    ));
-
-    insns.push((
-        Inst::FpuRRR {
-            fpu_op: FPUOp2::Add32,
-            rd: writable_fpr(8),
-            rm: fpr(12),
-        },
-        "B30A008C",
-        "aebr %f8, %f12",
-    ));
-    insns.push((
-        Inst::FpuRRR {
-            fpu_op: FPUOp2::Add64,
-            rd: writable_fpr(8),
-            rm: fpr(12),
-        },
-        "B31A008C",
-        "adbr %f8, %f12",
-    ));
-    insns.push((
-        Inst::FpuRRR {
-            fpu_op: FPUOp2::Sub32,
-            rd: writable_fpr(8),
-            rm: fpr(12),
-        },
-        "B30B008C",
-        "sebr %f8, %f12",
-    ));
-    insns.push((
-        Inst::FpuRRR {
-            fpu_op: FPUOp2::Sub64,
-            rd: writable_fpr(8),
-            rm: fpr(12),
-        },
-        "B31B008C",
-        "sdbr %f8, %f12",
-    ));
-    insns.push((
-        Inst::FpuRRR {
-            fpu_op: FPUOp2::Mul32,
-            rd: writable_fpr(8),
-            rm: fpr(12),
-        },
-        "B317008C",
-        "meebr %f8, %f12",
-    ));
-    insns.push((
-        Inst::FpuRRR {
-            fpu_op: FPUOp2::Mul64,
-            rd: writable_fpr(8),
-            rm: fpr(12),
-        },
-        "B31C008C",
-        "mdbr %f8, %f12",
-    ));
-    insns.push((
-        Inst::FpuRRR {
-            fpu_op: FPUOp2::Div32,
-            rd: writable_fpr(8),
-            rm: fpr(12),
-        },
-        "B30D008C",
-        "debr %f8, %f12",
-    ));
-    insns.push((
-        Inst::FpuRRR {
-            fpu_op: FPUOp2::Div64,
-            rd: writable_fpr(8),
-            rm: fpr(12),
-        },
-        "B31D008C",
-        "ddbr %f8, %f12",
-    ));
-
-    insns.push((
-        Inst::FpuRRRR {
-            fpu_op: FPUOp3::MAdd32,
-            rd: writable_fpr(8),
-            rn: fpr(12),
-            rm: fpr(13),
-        },
-        "B30E80CD",
-        "maebr %f8, %f12, %f13",
-    ));
-    insns.push((
-        Inst::FpuRRRR {
-            fpu_op: FPUOp3::MAdd64,
-            rd: writable_fpr(8),
-            rn: fpr(12),
-            rm: fpr(13),
-        },
-        "B31E80CD",
-        "madbr %f8, %f12, %f13",
-    ));
-    insns.push((
-        Inst::FpuRRRR {
-            fpu_op: FPUOp3::MSub32,
-            rd: writable_fpr(8),
-            rn: fpr(12),
-            rm: fpr(13),
-        },
-        "B30F80CD",
-        "msebr %f8, %f12, %f13",
-    ));
-    insns.push((
-        Inst::FpuRRRR {
-            fpu_op: FPUOp3::MSub64,
-            rd: writable_fpr(8),
-            rn: fpr(12),
-            rm: fpr(13),
-        },
-        "B31F80CD",
-        "msdbr %f8, %f12, %f13",
-    ));
-
-    insns.push((
-        Inst::FpuToInt {
-            op: FpuToIntOp::F32ToU32,
-            rd: writable_gpr(1),
-            rn: fpr(4),
-        },
-        "B39C5014",
-        "clfebr %r1, 5, %f4, 0",
-    ));
-
-    insns.push((
-        Inst::FpuToInt {
-            op: FpuToIntOp::F32ToU64,
-            rd: writable_gpr(1),
-            rn: fpr(4),
-        },
-        "B3AC5014",
-        "clgebr %r1, 5, %f4, 0",
-    ));
-
-    insns.push((
-        Inst::FpuToInt {
-            op: FpuToIntOp::F32ToI32,
-            rd: writable_gpr(1),
-            rn: fpr(4),
-        },
-        "B3985014",
-        "cfebra %r1, 5, %f4, 0",
-    ));
-
-    insns.push((
-        Inst::FpuToInt {
-            op: FpuToIntOp::F32ToI64,
-            rd: writable_gpr(1),
-            rn: fpr(4),
-        },
-        "B3A85014",
-        "cgebra %r1, 5, %f4, 0",
-    ));
-
-    insns.push((
-        Inst::FpuToInt {
-            op: FpuToIntOp::F64ToU32,
-            rd: writable_gpr(1),
-            rn: fpr(4),
-        },
-        "B39D5014",
-        "clfdbr %r1, 5, %f4, 0",
-    ));
-
-    insns.push((
-        Inst::FpuToInt {
-            op: FpuToIntOp::F64ToU64,
-            rd: writable_gpr(1),
-            rn: fpr(4),
-        },
-        "B3AD5014",
-        "clgdbr %r1, 5, %f4, 0",
-    ));
-
-    insns.push((
-        Inst::FpuToInt {
-            op: FpuToIntOp::F64ToI32,
-            rd: writable_gpr(1),
-            rn: fpr(4),
-        },
-        "B3995014",
-        "cfdbra %r1, 5, %f4, 0",
-    ));
-
-    insns.push((
-        Inst::FpuToInt {
-            op: FpuToIntOp::F64ToI64,
-            rd: writable_gpr(1),
-            rn: fpr(4),
-        },
-        "B3A95014",
-        "cgdbra %r1, 5, %f4, 0",
-    ));
-
-    insns.push((
-        Inst::IntToFpu {
-            op: IntToFpuOp::U32ToF32,
-            rd: writable_fpr(1),
-            rn: gpr(4),
-        },
-        "B3900014",
-        "celfbr %f1, 0, %r4, 0",
-    ));
-
-    insns.push((
-        Inst::IntToFpu {
-            op: IntToFpuOp::I32ToF32,
-            rd: writable_fpr(1),
-            rn: gpr(4),
-        },
-        "B3940014",
-        "cefbra %f1, 0, %r4, 0",
-    ));
-
-    insns.push((
-        Inst::IntToFpu {
-            op: IntToFpuOp::U32ToF64,
-            rd: writable_fpr(1),
-            rn: gpr(4),
-        },
-        "B3910014",
-        "cdlfbr %f1, 0, %r4, 0",
-    ));
-
-    insns.push((
-        Inst::IntToFpu {
-            op: IntToFpuOp::I32ToF64,
-            rd: writable_fpr(1),
-            rn: gpr(4),
-        },
-        "B3950014",
-        "cdfbra %f1, 0, %r4, 0",
-    ));
-
-    insns.push((
-        Inst::IntToFpu {
-            op: IntToFpuOp::U64ToF32,
-            rd: writable_fpr(1),
-            rn: gpr(4),
-        },
-        "B3A00014",
-        "celgbr %f1, 0, %r4, 0",
-    ));
-
-    insns.push((
-        Inst::IntToFpu {
-            op: IntToFpuOp::I64ToF32,
-            rd: writable_fpr(1),
-            rn: gpr(4),
-        },
-        "B3A40014",
-        "cegbra %f1, 0, %r4, 0",
-    ));
-
-    insns.push((
-        Inst::IntToFpu {
-            op: IntToFpuOp::U64ToF64,
-            rd: writable_fpr(1),
-            rn: gpr(4),
-        },
-        "B3A10014",
-        "cdlgbr %f1, 0, %r4, 0",
-    ));
-
-    insns.push((
-        Inst::IntToFpu {
-            op: IntToFpuOp::I64ToF64,
-            rd: writable_fpr(1),
-            rn: gpr(4),
-        },
-        "B3A50014",
-        "cdgbra %f1, 0, %r4, 0",
-    ));
-
-    insns.push((
-        Inst::FpuCopysign {
-            rd: writable_fpr(4),
-            rn: fpr(8),
-            rm: fpr(12),
-        },
-        "B372C048",
-        "cpsdr %f4, %f12, %f8",
-    ));
-
-    insns.push((
-        Inst::FpuCmp32 {
-            rn: fpr(8),
-            rm: fpr(12),
-        },
-        "B309008C",
-        "cebr %f8, %f12",
-    ));
-    insns.push((
-        Inst::FpuCmp64 {
-            rn: fpr(8),
-            rm: fpr(12),
-        },
-        "B319008C",
-        "cdbr %f8, %f12",
-    ));
-
-    insns.push((
-        Inst::FpuLoad32 {
-            rd: writable_fpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "78102000",
-        "le %f1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::FpuLoad32 {
-            rd: writable_fpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "78102FFF",
-        "le %f1, 4095(%r2)",
-    ));
-    insns.push((
-        Inst::FpuLoad32 {
-            rd: writable_fpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "ED1020008064",
-        "ley %f1, -524288(%r2)",
-    ));
-    insns.push((
-        Inst::FpuLoad32 {
-            rd: writable_fpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "ED102FFF7F64",
-        "ley %f1, 524287(%r2)",
-    ));
-    insns.push((
-        Inst::FpuLoad32 {
-            rd: writable_fpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "78123000",
-        "le %f1, 0(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::FpuLoad32 {
-            rd: writable_fpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "78123FFF",
-        "le %f1, 4095(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::FpuLoad32 {
-            rd: writable_fpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "ED1230008064",
-        "ley %f1, -524288(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::FpuLoad32 {
-            rd: writable_fpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "ED123FFF7F64",
-        "ley %f1, 524287(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::FpuLoad64 {
-            rd: writable_fpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "68102000",
-        "ld %f1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::FpuLoad64 {
-            rd: writable_fpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "68102FFF",
-        "ld %f1, 4095(%r2)",
-    ));
-    insns.push((
-        Inst::FpuLoad64 {
-            rd: writable_fpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "ED1020008065",
-        "ldy %f1, -524288(%r2)",
-    ));
-    insns.push((
-        Inst::FpuLoad64 {
-            rd: writable_fpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "ED102FFF7F65",
-        "ldy %f1, 524287(%r2)",
-    ));
-    insns.push((
-        Inst::FpuLoad64 {
-            rd: writable_fpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "68123000",
-        "ld %f1, 0(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::FpuLoad64 {
-            rd: writable_fpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "68123FFF",
-        "ld %f1, 4095(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::FpuLoad64 {
-            rd: writable_fpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "ED1230008065",
-        "ldy %f1, -524288(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::FpuLoad64 {
-            rd: writable_fpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "ED123FFF7F65",
-        "ldy %f1, 524287(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::FpuStore32 {
-            rd: fpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "70102000",
-        "ste %f1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::FpuStore32 {
-            rd: fpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "70102FFF",
-        "ste %f1, 4095(%r2)",
-    ));
-    insns.push((
-        Inst::FpuStore32 {
-            rd: fpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "ED1020008066",
-        "stey %f1, -524288(%r2)",
-    ));
-    insns.push((
-        Inst::FpuStore32 {
-            rd: fpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "ED102FFF7F66",
-        "stey %f1, 524287(%r2)",
-    ));
-    insns.push((
-        Inst::FpuStore32 {
-            rd: fpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "70123000",
-        "ste %f1, 0(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::FpuStore32 {
-            rd: fpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "70123FFF",
-        "ste %f1, 4095(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::FpuStore32 {
-            rd: fpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "ED1230008066",
-        "stey %f1, -524288(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::FpuStore32 {
-            rd: fpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "ED123FFF7F66",
-        "stey %f1, 524287(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::FpuStore64 {
-            rd: fpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "60102000",
-        "std %f1, 0(%r2)",
-    ));
-    insns.push((
-        Inst::FpuStore64 {
-            rd: fpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "60102FFF",
-        "std %f1, 4095(%r2)",
-    ));
-    insns.push((
-        Inst::FpuStore64 {
-            rd: fpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "ED1020008067",
-        "stdy %f1, -524288(%r2)",
-    ));
-    insns.push((
-        Inst::FpuStore64 {
-            rd: fpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "ED102FFF7F67",
-        "stdy %f1, 524287(%r2)",
-    ));
-    insns.push((
-        Inst::FpuStore64 {
-            rd: fpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "60123000",
-        "std %f1, 0(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::FpuStore64 {
-            rd: fpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "60123FFF",
-        "std %f1, 4095(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::FpuStore64 {
-            rd: fpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "ED1230008067",
-        "stdy %f1, -524288(%r2,%r3)",
-    ));
-    insns.push((
-        Inst::FpuStore64 {
-            rd: fpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "ED123FFF7F67",
-        "stdy %f1, 524287(%r2,%r3)",
-    ));
-
-    insns.push((
-        Inst::FpuLoadRev32 {
-            rd: writable_fpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E61020000003",
-        "vlebrf %f1, 0(%r2), 0",
-    ));
-    insns.push((
-        Inst::FpuLoadRev32 {
-            rd: writable_fpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E6102FFF0003",
-        "vlebrf %f1, 4095(%r2), 0",
-    ));
-    insns.push((
-        Inst::FpuLoadRev32 {
-            rd: writable_fpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020008071E61010000003",
-        "lay %r1, -524288(%r2) ; vlebrf %f1, 0(%r1), 0",
-    ));
-    insns.push((
-        Inst::FpuLoadRev32 {
-            rd: writable_fpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF7F71E61010000003",
-        "lay %r1, 524287(%r2) ; vlebrf %f1, 0(%r1), 0",
-    ));
-    insns.push((
-        Inst::FpuLoadRev32 {
-            rd: writable_fpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E61230000003",
-        "vlebrf %f1, 0(%r2,%r3), 0",
-    ));
-    insns.push((
-        Inst::FpuLoadRev32 {
-            rd: writable_fpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E6123FFF0003",
-        "vlebrf %f1, 4095(%r2,%r3), 0",
-    ));
-    insns.push((
-        Inst::FpuLoadRev32 {
-            rd: writable_fpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31230008071E61010000003",
-        "lay %r1, -524288(%r2,%r3) ; vlebrf %f1, 0(%r1), 0",
-    ));
-    insns.push((
-        Inst::FpuLoadRev32 {
-            rd: writable_fpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF7F71E61010000003",
-        "lay %r1, 524287(%r2,%r3) ; vlebrf %f1, 0(%r1), 0",
-    ));
-    insns.push((
-        Inst::FpuLoadRev64 {
-            rd: writable_fpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E61020000002",
-        "vlebrg %f1, 0(%r2), 0",
-    ));
-    insns.push((
-        Inst::FpuLoadRev64 {
-            rd: writable_fpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E6102FFF0002",
-        "vlebrg %f1, 4095(%r2), 0",
-    ));
-    insns.push((
-        Inst::FpuLoadRev64 {
-            rd: writable_fpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020008071E61010000002",
-        "lay %r1, -524288(%r2) ; vlebrg %f1, 0(%r1), 0",
-    ));
-    insns.push((
-        Inst::FpuLoadRev64 {
-            rd: writable_fpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF7F71E61010000002",
-        "lay %r1, 524287(%r2) ; vlebrg %f1, 0(%r1), 0",
-    ));
-    insns.push((
-        Inst::FpuLoadRev64 {
-            rd: writable_fpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E61230000002",
-        "vlebrg %f1, 0(%r2,%r3), 0",
-    ));
-    insns.push((
-        Inst::FpuLoadRev64 {
-            rd: writable_fpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E6123FFF0002",
-        "vlebrg %f1, 4095(%r2,%r3), 0",
-    ));
-    insns.push((
-        Inst::FpuLoadRev64 {
-            rd: writable_fpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31230008071E61010000002",
-        "lay %r1, -524288(%r2,%r3) ; vlebrg %f1, 0(%r1), 0",
-    ));
-    insns.push((
-        Inst::FpuLoadRev64 {
-            rd: writable_fpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF7F71E61010000002",
-        "lay %r1, 524287(%r2,%r3) ; vlebrg %f1, 0(%r1), 0",
-    ));
-    insns.push((
-        Inst::FpuStoreRev32 {
-            rd: fpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E6102000000B",
-        "vstebrf %f1, 0(%r2), 0",
-    ));
-    insns.push((
-        Inst::FpuStoreRev32 {
-            rd: fpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E6102FFF000B",
-        "vstebrf %f1, 4095(%r2), 0",
-    ));
-    insns.push((
-        Inst::FpuStoreRev32 {
-            rd: fpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020008071E6101000000B",
-        "lay %r1, -524288(%r2) ; vstebrf %f1, 0(%r1), 0",
-    ));
-    insns.push((
-        Inst::FpuStoreRev32 {
-            rd: fpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF7F71E6101000000B",
-        "lay %r1, 524287(%r2) ; vstebrf %f1, 0(%r1), 0",
-    ));
-    insns.push((
-        Inst::FpuStoreRev32 {
-            rd: fpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E6123000000B",
-        "vstebrf %f1, 0(%r2,%r3), 0",
-    ));
-    insns.push((
-        Inst::FpuStoreRev32 {
-            rd: fpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E6123FFF000B",
-        "vstebrf %f1, 4095(%r2,%r3), 0",
-    ));
-    insns.push((
-        Inst::FpuStoreRev32 {
-            rd: fpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31230008071E6101000000B",
-        "lay %r1, -524288(%r2,%r3) ; vstebrf %f1, 0(%r1), 0",
-    ));
-    insns.push((
-        Inst::FpuStoreRev32 {
-            rd: fpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF7F71E6101000000B",
-        "lay %r1, 524287(%r2,%r3) ; vstebrf %f1, 0(%r1), 0",
-    ));
-    insns.push((
-        Inst::FpuStoreRev64 {
-            rd: fpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E6102000000A",
-        "vstebrg %f1, 0(%r2), 0",
-    ));
-    insns.push((
-        Inst::FpuStoreRev64 {
-            rd: fpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E6102FFF000A",
-        "vstebrg %f1, 4095(%r2), 0",
-    ));
-    insns.push((
-        Inst::FpuStoreRev64 {
-            rd: fpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31020008071E6101000000A",
-        "lay %r1, -524288(%r2) ; vstebrg %f1, 0(%r1), 0",
-    ));
-    insns.push((
-        Inst::FpuStoreRev64 {
-            rd: fpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(2),
-                index: zero_reg(),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3102FFF7F71E6101000000A",
-        "lay %r1, 524287(%r2) ; vstebrg %f1, 0(%r1), 0",
-    ));
-    insns.push((
-        Inst::FpuStoreRev64 {
-            rd: fpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::zero(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E6123000000A",
-        "vstebrg %f1, 0(%r2,%r3), 0",
-    ));
-    insns.push((
-        Inst::FpuStoreRev64 {
-            rd: fpr(1),
-            mem: MemArg::BXD12 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: UImm12::maybe_from_u64(4095).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E6123FFF000A",
-        "vstebrg %f1, 4095(%r2,%r3), 0",
-    ));
-    insns.push((
-        Inst::FpuStoreRev64 {
-            rd: fpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(-524288).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E31230008071E6101000000A",
-        "lay %r1, -524288(%r2,%r3) ; vstebrg %f1, 0(%r1), 0",
-    ));
-    insns.push((
-        Inst::FpuStoreRev64 {
-            rd: fpr(1),
-            mem: MemArg::BXD20 {
-                base: gpr(3),
-                index: gpr(2),
-                disp: SImm20::maybe_from_i64(524287).unwrap(),
-                flags: MemFlags::trusted(),
-            },
-        },
-        "E3123FFF7F71E6101000000A",
-        "lay %r1, 524287(%r2,%r3) ; vstebrg %f1, 0(%r1), 0",
-    ));
-
-    insns.push((
-        Inst::LoadFpuConst32 {
-            rd: writable_fpr(8),
-            const_data: 1.0_f32.to_bits(),
-        },
-        "A71500043F80000078801000",
-        "bras %r1, 8 ; data.f32 1 ; le %f8, 0(%r1)",
-    ));
-    insns.push((
-        Inst::LoadFpuConst64 {
-            rd: writable_fpr(8),
-            const_data: 1.0_f64.to_bits(),
-        },
-        "A71500063FF000000000000068801000",
-        "bras %r1, 12 ; data.f64 1 ; ld %f8, 0(%r1)",
-    ));
-
-    insns.push((
-        Inst::FpuRound {
-            rd: writable_fpr(8),
-            rn: fpr(12),
-            op: FpuRoundMode::Minus32,
-        },
-        "B357708C",
-        "fiebr %f8, %f12, 7",
-    ));
-    insns.push((
-        Inst::FpuRound {
-            rd: writable_fpr(8),
-            rn: fpr(12),
-            op: FpuRoundMode::Minus64,
-        },
-        "B35F708C",
-        "fidbr %f8, %f12, 7",
-    ));
-    insns.push((
-        Inst::FpuRound {
-            rd: writable_fpr(8),
-            rn: fpr(12),
-            op: FpuRoundMode::Plus32,
-        },
-        "B357608C",
-        "fiebr %f8, %f12, 6",
-    ));
-    insns.push((
-        Inst::FpuRound {
-            rd: writable_fpr(8),
-            rn: fpr(12),
-            op: FpuRoundMode::Plus64,
-        },
-        "B35F608C",
-        "fidbr %f8, %f12, 6",
-    ));
-    insns.push((
-        Inst::FpuRound {
-            rd: writable_fpr(8),
-            rn: fpr(12),
-            op: FpuRoundMode::Zero32,
-        },
-        "B357508C",
-        "fiebr %f8, %f12, 5",
-    ));
-    insns.push((
-        Inst::FpuRound {
-            rd: writable_fpr(8),
-            rn: fpr(12),
-            op: FpuRoundMode::Zero64,
-        },
-        "B35F508C",
-        "fidbr %f8, %f12, 5",
-    ));
-    insns.push((
-        Inst::FpuRound {
-            rd: writable_fpr(8),
-            rn: fpr(12),
-            op: FpuRoundMode::Nearest32,
-        },
-        "B357408C",
-        "fiebr %f8, %f12, 4",
-    ));
-    insns.push((
-        Inst::FpuRound {
-            rd: writable_fpr(8),
-            rn: fpr(12),
-            op: FpuRoundMode::Nearest64,
-        },
-        "B35F408C",
-        "fidbr %f8, %f12, 4",
-    ));
-
-    insns.push((
-        Inst::FpuVecRRR {
-            fpu_op: FPUOp2::Max32,
-            rd: writable_fpr(4),
-            rn: fpr(6),
-            rm: fpr(8),
-        },
-        "E746801820EF",
-        "wfmaxsb %f4, %f6, %f8, 1",
-    ));
-    insns.push((
-        Inst::FpuVecRRR {
-            fpu_op: FPUOp2::Max64,
-            rd: writable_fpr(4),
-            rn: fpr(6),
-            rm: fpr(8),
-        },
-        "E746801830EF",
-        "wfmaxdb %f4, %f6, %f8, 1",
-    ));
-    insns.push((
-        Inst::FpuVecRRR {
-            fpu_op: FPUOp2::Min32,
-            rd: writable_fpr(4),
-            rn: fpr(6),
-            rm: fpr(8),
-        },
-        "E746801820EE",
-        "wfminsb %f4, %f6, %f8, 1",
-    ));
-    insns.push((
-        Inst::FpuVecRRR {
-            fpu_op: FPUOp2::Min64,
-            rd: writable_fpr(4),
-            rn: fpr(6),
-            rm: fpr(8),
-        },
-        "E746801830EE",
-        "wfmindb %f4, %f6, %f8, 1",
-    ));
-
-    let flags = settings::Flags::new(settings::builder());
-
-    use crate::settings::Configurable;
-    let mut isa_flag_builder = s390x_settings::builder();
-    isa_flag_builder.enable("arch13").unwrap();
-    let isa_flags = s390x_settings::Flags::new(&flags, isa_flag_builder);
-
-    let rru = create_reg_universe(&flags);
-    let emit_info = EmitInfo::new(flags, isa_flags);
-    for (insn, expected_encoding, expected_printing) in insns {
-        println!(
-            "S390x: {:?}, {}, {}",
-            insn, expected_encoding, expected_printing
-        );
-
-        // Check the printed text is as expected.
-        let actual_printing = insn.show_rru(Some(&rru));
-        assert_eq!(expected_printing, actual_printing);
-
-        let mut buffer = MachBuffer::new();
-
-        // Label 0 before the instruction.
-        let label0 = buffer.get_label();
-        buffer.bind_label(label0);
-
-        // Emit the instruction.
-        insn.emit(&mut buffer, &emit_info, &mut Default::default());
-
-        // Label 1 after the instruction.
-        let label1 = buffer.get_label();
-        buffer.bind_label(label1);
-
-        let buffer = buffer.finish();
-        let actual_encoding = &buffer.stringify_code_bytes();
-        assert_eq!(expected_encoding, actual_encoding);
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/inst/imms.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/inst/imms.rs
deleted file mode 100644
index b1a459ea6..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/inst/imms.rs
+++ /dev/null
@@ -1,231 +0,0 @@
-//! S390x ISA definitions: immediate constants.
-
-use regalloc::{PrettyPrint, RealRegUniverse};
-use std::string::String;
-
-/// An unsigned 12-bit immediate.
-#[derive(Clone, Copy, Debug)]
-pub struct UImm12 {
-    /// The value.
-    value: u16,
-}
-
-impl UImm12 {
-    pub fn maybe_from_u64(value: u64) -> Option<UImm12> {
-        if value < 4096 {
-            Some(UImm12 {
-                value: value as u16,
-            })
-        } else {
-            None
-        }
-    }
-
-    /// Create a zero immediate of this format.
-    pub fn zero() -> UImm12 {
-        UImm12 { value: 0 }
-    }
-
-    /// Bits for encoding.
-    pub fn bits(&self) -> u32 {
-        u32::from(self.value)
-    }
-}
-
-/// A signed 20-bit immediate.
-#[derive(Clone, Copy, Debug)]
-pub struct SImm20 {
-    /// The value.
-    value: i32,
-}
-
-impl SImm20 {
-    pub fn maybe_from_i64(value: i64) -> Option<SImm20> {
-        if value >= -524288 && value < 524288 {
-            Some(SImm20 {
-                value: value as i32,
-            })
-        } else {
-            None
-        }
-    }
-
-    pub fn from_uimm12(value: UImm12) -> SImm20 {
-        SImm20 {
-            value: value.bits() as i32,
-        }
-    }
-
-    /// Create a zero immediate of this format.
-    pub fn zero() -> SImm20 {
-        SImm20 { value: 0 }
-    }
-
-    /// Bits for encoding.
-    pub fn bits(&self) -> u32 {
-        let encoded: u32 = self.value as u32;
-        encoded & 0xfffff
-    }
-}
-
-/// A 16-bit immediate with a {0,16,32,48}-bit shift.
-#[derive(Clone, Copy, Debug)]
-pub struct UImm16Shifted {
-    /// The value.
-    pub bits: u16,
-    /// Result is `bits` shifted 16*shift bits to the left.
-    pub shift: u8,
-}
-
-impl UImm16Shifted {
-    /// Construct a UImm16Shifted from an arbitrary 64-bit constant if possible.
-    pub fn maybe_from_u64(value: u64) -> Option<UImm16Shifted> {
-        let mask0 = 0x0000_0000_0000_ffffu64;
-        let mask1 = 0x0000_0000_ffff_0000u64;
-        let mask2 = 0x0000_ffff_0000_0000u64;
-        let mask3 = 0xffff_0000_0000_0000u64;
-
-        if value == (value & mask0) {
-            return Some(UImm16Shifted {
-                bits: (value & mask0) as u16,
-                shift: 0,
-            });
-        }
-        if value == (value & mask1) {
-            return Some(UImm16Shifted {
-                bits: ((value >> 16) & mask0) as u16,
-                shift: 1,
-            });
-        }
-        if value == (value & mask2) {
-            return Some(UImm16Shifted {
-                bits: ((value >> 32) & mask0) as u16,
-                shift: 2,
-            });
-        }
-        if value == (value & mask3) {
-            return Some(UImm16Shifted {
-                bits: ((value >> 48) & mask0) as u16,
-                shift: 3,
-            });
-        }
-        None
-    }
-
-    pub fn maybe_with_shift(imm: u16, shift: u8) -> Option<UImm16Shifted> {
-        let shift_enc = shift / 16;
-        if shift_enc > 3 {
-            None
-        } else {
-            Some(UImm16Shifted {
-                bits: imm,
-                shift: shift_enc,
-            })
-        }
-    }
-
-    pub fn negate_bits(&self) -> UImm16Shifted {
-        UImm16Shifted {
-            bits: !self.bits,
-            shift: self.shift,
-        }
-    }
-
-    /// Returns the value that this constant represents.
-    pub fn value(&self) -> u64 {
-        (self.bits as u64) << (16 * self.shift)
-    }
-}
-
-/// A 32-bit immediate with a {0,32}-bit shift.
-#[derive(Clone, Copy, Debug)]
-pub struct UImm32Shifted {
-    /// The value.
-    pub bits: u32,
-    /// Result is `bits` shifted 32*shift bits to the left.
-    pub shift: u8,
-}
-
-impl UImm32Shifted {
-    /// Construct a UImm32Shifted from an arbitrary 64-bit constant if possible.
-    pub fn maybe_from_u64(value: u64) -> Option<UImm32Shifted> {
-        let mask0 = 0x0000_0000_ffff_ffffu64;
-        let mask1 = 0xffff_ffff_0000_0000u64;
-
-        if value == (value & mask0) {
-            return Some(UImm32Shifted {
-                bits: (value & mask0) as u32,
-                shift: 0,
-            });
-        }
-        if value == (value & mask1) {
-            return Some(UImm32Shifted {
-                bits: ((value >> 32) & mask0) as u32,
-                shift: 1,
-            });
-        }
-        None
-    }
-
-    pub fn maybe_with_shift(imm: u32, shift: u8) -> Option<UImm32Shifted> {
-        let shift_enc = shift / 32;
-        if shift_enc > 3 {
-            None
-        } else {
-            Some(UImm32Shifted {
-                bits: imm,
-                shift: shift_enc,
-            })
-        }
-    }
-
-    pub fn from_uimm16shifted(value: UImm16Shifted) -> UImm32Shifted {
-        if value.shift % 2 == 0 {
-            UImm32Shifted {
-                bits: value.bits as u32,
-                shift: value.shift / 2,
-            }
-        } else {
-            UImm32Shifted {
-                bits: (value.bits as u32) << 16,
-                shift: value.shift / 2,
-            }
-        }
-    }
-
-    pub fn negate_bits(&self) -> UImm32Shifted {
-        UImm32Shifted {
-            bits: !self.bits,
-            shift: self.shift,
-        }
-    }
-
-    /// Returns the value that this constant represents.
-    pub fn value(&self) -> u64 {
-        (self.bits as u64) << (32 * self.shift)
-    }
-}
-
-impl PrettyPrint for UImm12 {
-    fn show_rru(&self, _mb_rru: Option<&RealRegUniverse>) -> String {
-        format!("{}", self.value)
-    }
-}
-
-impl PrettyPrint for SImm20 {
-    fn show_rru(&self, _mb_rru: Option<&RealRegUniverse>) -> String {
-        format!("{}", self.value)
-    }
-}
-
-impl PrettyPrint for UImm16Shifted {
-    fn show_rru(&self, _mb_rru: Option<&RealRegUniverse>) -> String {
-        format!("{}", self.bits)
-    }
-}
-
-impl PrettyPrint for UImm32Shifted {
-    fn show_rru(&self, _mb_rru: Option<&RealRegUniverse>) -> String {
-        format!("{}", self.bits)
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/inst/mod.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/inst/mod.rs
deleted file mode 100644
index adff4a4d9..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/inst/mod.rs
+++ /dev/null
@@ -1,2884 +0,0 @@
-//! This module defines s390x-specific machine instruction types.
-
-// Some variants are not constructed, but we still want them as options in the future.
-#![allow(dead_code)]
-
-use crate::binemit::{Addend, CodeOffset, Reloc};
-use crate::ir::{types, ExternalName, Opcode, Type, ValueLabel};
-use crate::machinst::*;
-use crate::{settings, CodegenError, CodegenResult};
-
-use regalloc::{PrettyPrint, RegUsageCollector, RegUsageMapper};
-use regalloc::{RealRegUniverse, Reg, RegClass, SpillSlot, VirtualReg, Writable};
-
-use alloc::boxed::Box;
-use alloc::vec::Vec;
-use core::convert::TryFrom;
-use smallvec::{smallvec, SmallVec};
-use std::string::{String, ToString};
-
-pub mod regs;
-pub use self::regs::*;
-pub mod imms;
-pub use self::imms::*;
-pub mod args;
-pub use self::args::*;
-pub mod emit;
-pub use self::emit::*;
-pub mod unwind;
-
-#[cfg(test)]
-mod emit_tests;
-
-//=============================================================================
-// Instructions (top level): definition
-
-pub use crate::isa::s390x::lower::isle::generated_code::{
-    ALUOp, CmpOp, FPUOp1, FPUOp2, FPUOp3, FpuRoundMode, FpuToIntOp, IntToFpuOp, MInst as Inst,
-    RxSBGOp, ShiftOp, UnaryOp,
-};
-
-/// Additional information for (direct) Call instructions, left out of line to lower the size of
-/// the Inst enum.
-#[derive(Clone, Debug)]
-pub struct CallInfo {
-    pub dest: ExternalName,
-    pub uses: Vec<Reg>,
-    pub defs: Vec<Writable<Reg>>,
-    pub opcode: Opcode,
-}
-
-/// Additional information for CallInd instructions, left out of line to lower the size of the Inst
-/// enum.
-#[derive(Clone, Debug)]
-pub struct CallIndInfo {
-    pub rn: Reg,
-    pub uses: Vec<Reg>,
-    pub defs: Vec<Writable<Reg>>,
-    pub opcode: Opcode,
-}
-
-#[test]
-fn inst_size_test() {
-    // This test will help with unintentionally growing the size
-    // of the Inst enum.
-    assert_eq!(32, std::mem::size_of::<Inst>());
-}
-
-/// Supported instruction sets
-#[allow(non_camel_case_types)]
-#[derive(Debug)]
-pub(crate) enum InstructionSet {
-    /// Baseline ISA for cranelift is z14.
-    Base,
-    /// Miscellaneous-Instruction-Extensions Facility 2 (z15)
-    MIE2,
-    /// Vector-Enhancements Facility 2 (z15)
-    VXRS_EXT2,
-}
-
-impl Inst {
-    /// Retrieve the ISA feature set in which the instruction is available.
-    fn available_in_isa(&self) -> InstructionSet {
-        match self {
-            // These instructions are part of the baseline ISA for cranelift (z14)
-            Inst::Nop0
-            | Inst::Nop2
-            | Inst::AluRRSImm16 { .. }
-            | Inst::AluRR { .. }
-            | Inst::AluRX { .. }
-            | Inst::AluRSImm16 { .. }
-            | Inst::AluRSImm32 { .. }
-            | Inst::AluRUImm32 { .. }
-            | Inst::AluRUImm16Shifted { .. }
-            | Inst::AluRUImm32Shifted { .. }
-            | Inst::ShiftRR { .. }
-            | Inst::RxSBG { .. }
-            | Inst::RxSBGTest { .. }
-            | Inst::SMulWide { .. }
-            | Inst::UMulWide { .. }
-            | Inst::SDivMod32 { .. }
-            | Inst::SDivMod64 { .. }
-            | Inst::UDivMod32 { .. }
-            | Inst::UDivMod64 { .. }
-            | Inst::Flogr { .. }
-            | Inst::CmpRR { .. }
-            | Inst::CmpRX { .. }
-            | Inst::CmpRSImm16 { .. }
-            | Inst::CmpRSImm32 { .. }
-            | Inst::CmpRUImm32 { .. }
-            | Inst::CmpTrapRR { .. }
-            | Inst::CmpTrapRSImm16 { .. }
-            | Inst::CmpTrapRUImm16 { .. }
-            | Inst::AtomicRmw { .. }
-            | Inst::AtomicCas32 { .. }
-            | Inst::AtomicCas64 { .. }
-            | Inst::Fence
-            | Inst::Load32 { .. }
-            | Inst::Load32ZExt8 { .. }
-            | Inst::Load32SExt8 { .. }
-            | Inst::Load32ZExt16 { .. }
-            | Inst::Load32SExt16 { .. }
-            | Inst::Load64 { .. }
-            | Inst::Load64ZExt8 { .. }
-            | Inst::Load64SExt8 { .. }
-            | Inst::Load64ZExt16 { .. }
-            | Inst::Load64SExt16 { .. }
-            | Inst::Load64ZExt32 { .. }
-            | Inst::Load64SExt32 { .. }
-            | Inst::LoadRev16 { .. }
-            | Inst::LoadRev32 { .. }
-            | Inst::LoadRev64 { .. }
-            | Inst::Store8 { .. }
-            | Inst::Store16 { .. }
-            | Inst::Store32 { .. }
-            | Inst::Store64 { .. }
-            | Inst::StoreImm8 { .. }
-            | Inst::StoreImm16 { .. }
-            | Inst::StoreImm32SExt16 { .. }
-            | Inst::StoreImm64SExt16 { .. }
-            | Inst::StoreRev16 { .. }
-            | Inst::StoreRev32 { .. }
-            | Inst::StoreRev64 { .. }
-            | Inst::LoadMultiple64 { .. }
-            | Inst::StoreMultiple64 { .. }
-            | Inst::Mov32 { .. }
-            | Inst::Mov64 { .. }
-            | Inst::Mov32Imm { .. }
-            | Inst::Mov32SImm16 { .. }
-            | Inst::Mov64SImm16 { .. }
-            | Inst::Mov64SImm32 { .. }
-            | Inst::Mov64UImm16Shifted { .. }
-            | Inst::Mov64UImm32Shifted { .. }
-            | Inst::Insert64UImm16Shifted { .. }
-            | Inst::Insert64UImm32Shifted { .. }
-            | Inst::Extend { .. }
-            | Inst::CMov32 { .. }
-            | Inst::CMov64 { .. }
-            | Inst::CMov32SImm16 { .. }
-            | Inst::CMov64SImm16 { .. }
-            | Inst::FpuMove32 { .. }
-            | Inst::FpuMove64 { .. }
-            | Inst::FpuCMov32 { .. }
-            | Inst::FpuCMov64 { .. }
-            | Inst::MovToFpr { .. }
-            | Inst::MovFromFpr { .. }
-            | Inst::FpuRR { .. }
-            | Inst::FpuRRR { .. }
-            | Inst::FpuRRRR { .. }
-            | Inst::FpuCopysign { .. }
-            | Inst::FpuCmp32 { .. }
-            | Inst::FpuCmp64 { .. }
-            | Inst::FpuLoad32 { .. }
-            | Inst::FpuStore32 { .. }
-            | Inst::FpuLoad64 { .. }
-            | Inst::FpuStore64 { .. }
-            | Inst::LoadFpuConst32 { .. }
-            | Inst::LoadFpuConst64 { .. }
-            | Inst::FpuToInt { .. }
-            | Inst::IntToFpu { .. }
-            | Inst::FpuRound { .. }
-            | Inst::FpuVecRRR { .. }
-            | Inst::Call { .. }
-            | Inst::CallInd { .. }
-            | Inst::Ret { .. }
-            | Inst::EpiloguePlaceholder
-            | Inst::Jump { .. }
-            | Inst::CondBr { .. }
-            | Inst::TrapIf { .. }
-            | Inst::OneWayCondBr { .. }
-            | Inst::IndirectBr { .. }
-            | Inst::Debugtrap
-            | Inst::Trap { .. }
-            | Inst::JTSequence { .. }
-            | Inst::LoadExtNameFar { .. }
-            | Inst::LoadAddr { .. }
-            | Inst::Loop { .. }
-            | Inst::CondBreak { .. }
-            | Inst::VirtualSPOffsetAdj { .. }
-            | Inst::ValueLabelMarker { .. }
-            | Inst::Unwind { .. } => InstructionSet::Base,
-
-            // These depend on the opcode
-            Inst::AluRRR { alu_op, .. } => match alu_op {
-                ALUOp::AndNot32 | ALUOp::AndNot64 => InstructionSet::MIE2,
-                ALUOp::OrrNot32 | ALUOp::OrrNot64 => InstructionSet::MIE2,
-                ALUOp::XorNot32 | ALUOp::XorNot64 => InstructionSet::MIE2,
-                _ => InstructionSet::Base,
-            },
-            Inst::UnaryRR { op, .. } => match op {
-                UnaryOp::PopcntReg => InstructionSet::MIE2,
-                _ => InstructionSet::Base,
-            },
-
-            // These are all part of VXRS_EXT2
-            Inst::FpuLoadRev32 { .. }
-            | Inst::FpuStoreRev32 { .. }
-            | Inst::FpuLoadRev64 { .. }
-            | Inst::FpuStoreRev64 { .. } => InstructionSet::VXRS_EXT2,
-        }
-    }
-
-    /// Create a 64-bit move instruction.
-    pub fn mov64(to_reg: Writable<Reg>, from_reg: Reg) -> Inst {
-        assert!(to_reg.to_reg().get_class() == from_reg.get_class());
-        if from_reg.get_class() == RegClass::I64 {
-            Inst::Mov64 {
-                rd: to_reg,
-                rm: from_reg,
-            }
-        } else {
-            Inst::FpuMove64 {
-                rd: to_reg,
-                rn: from_reg,
-            }
-        }
-    }
-
-    /// Create a 32-bit move instruction.
-    pub fn mov32(to_reg: Writable<Reg>, from_reg: Reg) -> Inst {
-        if from_reg.get_class() == RegClass::I64 {
-            Inst::Mov32 {
-                rd: to_reg,
-                rm: from_reg,
-            }
-        } else {
-            Inst::FpuMove32 {
-                rd: to_reg,
-                rn: from_reg,
-            }
-        }
-    }
-
-    /// Create an instruction that loads a 64-bit integer constant.
-    pub fn load_constant64(rd: Writable<Reg>, value: u64) -> SmallVec<[Inst; 4]> {
-        if let Ok(imm) = i16::try_from(value as i64) {
-            // 16-bit signed immediate
-            smallvec![Inst::Mov64SImm16 { rd, imm }]
-        } else if let Ok(imm) = i32::try_from(value as i64) {
-            // 32-bit signed immediate
-            smallvec![Inst::Mov64SImm32 { rd, imm }]
-        } else if let Some(imm) = UImm16Shifted::maybe_from_u64(value) {
-            // 16-bit shifted immediate
-            smallvec![Inst::Mov64UImm16Shifted { rd, imm }]
-        } else if let Some(imm) = UImm32Shifted::maybe_from_u64(value) {
-            // 32-bit shifted immediate
-            smallvec![Inst::Mov64UImm32Shifted { rd, imm }]
-        } else {
-            let mut insts = smallvec![];
-            let hi = value & 0xffff_ffff_0000_0000u64;
-            let lo = value & 0x0000_0000_ffff_ffffu64;
-
-            if let Some(imm) = UImm16Shifted::maybe_from_u64(hi) {
-                // 16-bit shifted immediate
-                insts.push(Inst::Mov64UImm16Shifted { rd, imm });
-            } else if let Some(imm) = UImm32Shifted::maybe_from_u64(hi) {
-                // 32-bit shifted immediate
-                insts.push(Inst::Mov64UImm32Shifted { rd, imm });
-            } else {
-                unreachable!();
-            }
-
-            if let Some(imm) = UImm16Shifted::maybe_from_u64(lo) {
-                // 16-bit shifted immediate
-                insts.push(Inst::Insert64UImm16Shifted { rd, imm });
-            } else if let Some(imm) = UImm32Shifted::maybe_from_u64(lo) {
-                // 32-bit shifted immediate
-                insts.push(Inst::Insert64UImm32Shifted { rd, imm });
-            } else {
-                unreachable!();
-            }
-
-            insts
-        }
-    }
-
-    /// Create an instruction that loads a 32-bit integer constant.
-    pub fn load_constant32(rd: Writable<Reg>, value: u32) -> SmallVec<[Inst; 4]> {
-        if let Ok(imm) = i16::try_from(value as i32) {
-            // 16-bit signed immediate
-            smallvec![Inst::Mov32SImm16 { rd, imm }]
-        } else {
-            // 32-bit full immediate
-            smallvec![Inst::Mov32Imm { rd, imm: value }]
-        }
-    }
-
-    /// Create an instruction that loads a 32-bit floating-point constant.
-    pub fn load_fp_constant32(rd: Writable<Reg>, value: f32) -> Inst {
-        // TODO: use LZER to load 0.0
-        Inst::LoadFpuConst32 {
-            rd,
-            const_data: value.to_bits(),
-        }
-    }
-
-    /// Create an instruction that loads a 64-bit floating-point constant.
-    pub fn load_fp_constant64(rd: Writable<Reg>, value: f64) -> Inst {
-        // TODO: use LZDR to load 0.0
-        Inst::LoadFpuConst64 {
-            rd,
-            const_data: value.to_bits(),
-        }
-    }
-
-    /// Generic constructor for a load (zero-extending where appropriate).
-    pub fn gen_load(into_reg: Writable<Reg>, mem: MemArg, ty: Type) -> Inst {
-        match ty {
-            types::B1 | types::B8 | types::I8 => Inst::Load64ZExt8 { rd: into_reg, mem },
-            types::B16 | types::I16 => Inst::Load64ZExt16 { rd: into_reg, mem },
-            types::B32 | types::I32 => Inst::Load64ZExt32 { rd: into_reg, mem },
-            types::B64 | types::I64 | types::R64 => Inst::Load64 { rd: into_reg, mem },
-            types::F32 => Inst::FpuLoad32 { rd: into_reg, mem },
-            types::F64 => Inst::FpuLoad64 { rd: into_reg, mem },
-            _ => unimplemented!("gen_load({})", ty),
-        }
-    }
-
-    /// Generic constructor for a store.
-    pub fn gen_store(mem: MemArg, from_reg: Reg, ty: Type) -> Inst {
-        match ty {
-            types::B1 | types::B8 | types::I8 => Inst::Store8 { rd: from_reg, mem },
-            types::B16 | types::I16 => Inst::Store16 { rd: from_reg, mem },
-            types::B32 | types::I32 => Inst::Store32 { rd: from_reg, mem },
-            types::B64 | types::I64 | types::R64 => Inst::Store64 { rd: from_reg, mem },
-            types::F32 => Inst::FpuStore32 { rd: from_reg, mem },
-            types::F64 => Inst::FpuStore64 { rd: from_reg, mem },
-            _ => unimplemented!("gen_store({})", ty),
-        }
-    }
-}
-
-//=============================================================================
-// Instructions: get_regs
-
-fn memarg_regs(memarg: &MemArg, collector: &mut RegUsageCollector) {
-    match memarg {
-        &MemArg::BXD12 { base, index, .. } | &MemArg::BXD20 { base, index, .. } => {
-            if base != zero_reg() {
-                collector.add_use(base);
-            }
-            if index != zero_reg() {
-                collector.add_use(index);
-            }
-        }
-        &MemArg::Label { .. } | &MemArg::Symbol { .. } => {}
-        &MemArg::RegOffset { reg, .. } => {
-            collector.add_use(reg);
-        }
-        &MemArg::InitialSPOffset { .. } | &MemArg::NominalSPOffset { .. } => {
-            collector.add_use(stack_reg());
-        }
-    }
-}
-
-fn s390x_get_regs(inst: &Inst, collector: &mut RegUsageCollector) {
-    match inst {
-        &Inst::AluRRR { rd, rn, rm, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-            collector.add_use(rm);
-        }
-        &Inst::AluRRSImm16 { rd, rn, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-        }
-        &Inst::AluRR { rd, rm, .. } => {
-            collector.add_mod(rd);
-            collector.add_use(rm);
-        }
-        &Inst::AluRX { rd, ref mem, .. } => {
-            collector.add_mod(rd);
-            memarg_regs(mem, collector);
-        }
-        &Inst::AluRSImm16 { rd, .. } => {
-            collector.add_mod(rd);
-        }
-        &Inst::AluRSImm32 { rd, .. } => {
-            collector.add_mod(rd);
-        }
-        &Inst::AluRUImm32 { rd, .. } => {
-            collector.add_mod(rd);
-        }
-        &Inst::AluRUImm16Shifted { rd, .. } => {
-            collector.add_mod(rd);
-        }
-        &Inst::AluRUImm32Shifted { rd, .. } => {
-            collector.add_mod(rd);
-        }
-        &Inst::SMulWide { rn, rm, .. } => {
-            collector.add_def(writable_gpr(0));
-            collector.add_def(writable_gpr(1));
-            collector.add_use(rn);
-            collector.add_use(rm);
-        }
-        &Inst::UMulWide { rn, .. } => {
-            collector.add_def(writable_gpr(0));
-            collector.add_mod(writable_gpr(1));
-            collector.add_use(rn);
-        }
-        &Inst::SDivMod32 { rn, .. } | &Inst::SDivMod64 { rn, .. } => {
-            collector.add_def(writable_gpr(0));
-            collector.add_mod(writable_gpr(1));
-            collector.add_use(rn);
-        }
-        &Inst::UDivMod32 { rn, .. } | &Inst::UDivMod64 { rn, .. } => {
-            collector.add_mod(writable_gpr(0));
-            collector.add_mod(writable_gpr(1));
-            collector.add_use(rn);
-        }
-        &Inst::Flogr { rn, .. } => {
-            collector.add_def(writable_gpr(0));
-            collector.add_def(writable_gpr(1));
-            collector.add_use(rn);
-        }
-        &Inst::ShiftRR {
-            rd, rn, shift_reg, ..
-        } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-            if shift_reg != zero_reg() {
-                collector.add_use(shift_reg);
-            }
-        }
-        &Inst::RxSBG { rd, rn, .. } => {
-            collector.add_mod(rd);
-            collector.add_use(rn);
-        }
-        &Inst::RxSBGTest { rd, rn, .. } => {
-            collector.add_use(rd);
-            collector.add_use(rn);
-        }
-        &Inst::UnaryRR { rd, rn, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-        }
-        &Inst::CmpRR { rn, rm, .. } => {
-            collector.add_use(rn);
-            collector.add_use(rm);
-        }
-        &Inst::CmpRX { rn, ref mem, .. } => {
-            collector.add_use(rn);
-            memarg_regs(mem, collector);
-        }
-        &Inst::CmpRSImm16 { rn, .. } => {
-            collector.add_use(rn);
-        }
-        &Inst::CmpRSImm32 { rn, .. } => {
-            collector.add_use(rn);
-        }
-        &Inst::CmpRUImm32 { rn, .. } => {
-            collector.add_use(rn);
-        }
-        &Inst::CmpTrapRR { rn, rm, .. } => {
-            collector.add_use(rn);
-            collector.add_use(rm);
-        }
-        &Inst::CmpTrapRSImm16 { rn, .. } => {
-            collector.add_use(rn);
-        }
-        &Inst::CmpTrapRUImm16 { rn, .. } => {
-            collector.add_use(rn);
-        }
-        &Inst::AtomicRmw {
-            rd, rn, ref mem, ..
-        } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-            memarg_regs(mem, collector);
-        }
-        &Inst::AtomicCas32 {
-            rd, rn, ref mem, ..
-        }
-        | &Inst::AtomicCas64 {
-            rd, rn, ref mem, ..
-        } => {
-            collector.add_mod(rd);
-            collector.add_use(rn);
-            memarg_regs(mem, collector);
-        }
-        &Inst::Fence => {}
-        &Inst::Load32 { rd, ref mem, .. }
-        | &Inst::Load32ZExt8 { rd, ref mem, .. }
-        | &Inst::Load32SExt8 { rd, ref mem, .. }
-        | &Inst::Load32ZExt16 { rd, ref mem, .. }
-        | &Inst::Load32SExt16 { rd, ref mem, .. }
-        | &Inst::Load64 { rd, ref mem, .. }
-        | &Inst::Load64ZExt8 { rd, ref mem, .. }
-        | &Inst::Load64SExt8 { rd, ref mem, .. }
-        | &Inst::Load64ZExt16 { rd, ref mem, .. }
-        | &Inst::Load64SExt16 { rd, ref mem, .. }
-        | &Inst::Load64ZExt32 { rd, ref mem, .. }
-        | &Inst::Load64SExt32 { rd, ref mem, .. }
-        | &Inst::LoadRev16 { rd, ref mem, .. }
-        | &Inst::LoadRev32 { rd, ref mem, .. }
-        | &Inst::LoadRev64 { rd, ref mem, .. } => {
-            collector.add_def(rd);
-            memarg_regs(mem, collector);
-        }
-        &Inst::Store8 { rd, ref mem, .. }
-        | &Inst::Store16 { rd, ref mem, .. }
-        | &Inst::Store32 { rd, ref mem, .. }
-        | &Inst::Store64 { rd, ref mem, .. }
-        | &Inst::StoreRev16 { rd, ref mem, .. }
-        | &Inst::StoreRev32 { rd, ref mem, .. }
-        | &Inst::StoreRev64 { rd, ref mem, .. } => {
-            collector.add_use(rd);
-            memarg_regs(mem, collector);
-        }
-        &Inst::StoreImm8 { ref mem, .. }
-        | &Inst::StoreImm16 { ref mem, .. }
-        | &Inst::StoreImm32SExt16 { ref mem, .. }
-        | &Inst::StoreImm64SExt16 { ref mem, .. } => {
-            memarg_regs(mem, collector);
-        }
-        &Inst::LoadMultiple64 {
-            rt, rt2, ref mem, ..
-        } => {
-            let first_regnum = rt.to_reg().get_hw_encoding();
-            let last_regnum = rt2.to_reg().get_hw_encoding();
-            for regnum in first_regnum..last_regnum + 1 {
-                collector.add_def(writable_gpr(regnum));
-            }
-            memarg_regs(mem, collector);
-        }
-        &Inst::StoreMultiple64 {
-            rt, rt2, ref mem, ..
-        } => {
-            let first_regnum = rt.get_hw_encoding();
-            let last_regnum = rt2.get_hw_encoding();
-            for regnum in first_regnum..last_regnum + 1 {
-                collector.add_use(gpr(regnum));
-            }
-            memarg_regs(mem, collector);
-        }
-        &Inst::Mov64 { rd, rm } => {
-            collector.add_def(rd);
-            collector.add_use(rm);
-        }
-        &Inst::Mov32 { rd, rm } => {
-            collector.add_def(rd);
-            collector.add_use(rm);
-        }
-        &Inst::Mov32Imm { rd, .. }
-        | &Inst::Mov32SImm16 { rd, .. }
-        | &Inst::Mov64SImm16 { rd, .. }
-        | &Inst::Mov64SImm32 { rd, .. }
-        | &Inst::Mov64UImm16Shifted { rd, .. }
-        | &Inst::Mov64UImm32Shifted { rd, .. } => {
-            collector.add_def(rd);
-        }
-        &Inst::CMov32 { rd, rm, .. } | &Inst::CMov64 { rd, rm, .. } => {
-            collector.add_mod(rd);
-            collector.add_use(rm);
-        }
-        &Inst::CMov32SImm16 { rd, .. } | &Inst::CMov64SImm16 { rd, .. } => {
-            collector.add_mod(rd);
-        }
-        &Inst::Insert64UImm16Shifted { rd, .. } | &Inst::Insert64UImm32Shifted { rd, .. } => {
-            collector.add_mod(rd);
-        }
-        &Inst::FpuMove32 { rd, rn } | &Inst::FpuMove64 { rd, rn } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-        }
-        &Inst::FpuCMov32 { rd, rm, .. } | &Inst::FpuCMov64 { rd, rm, .. } => {
-            collector.add_mod(rd);
-            collector.add_use(rm);
-        }
-        &Inst::MovToFpr { rd, rn } | &Inst::MovFromFpr { rd, rn } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-        }
-        &Inst::FpuRR { rd, rn, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-        }
-        &Inst::FpuRRR { rd, rm, .. } => {
-            collector.add_mod(rd);
-            collector.add_use(rm);
-        }
-        &Inst::FpuRRRR { rd, rn, rm, .. } => {
-            collector.add_mod(rd);
-            collector.add_use(rn);
-            collector.add_use(rm);
-        }
-        &Inst::FpuCopysign { rd, rn, rm, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-            collector.add_use(rm);
-        }
-        &Inst::FpuCmp32 { rn, rm } | &Inst::FpuCmp64 { rn, rm } => {
-            collector.add_use(rn);
-            collector.add_use(rm);
-        }
-        &Inst::FpuLoad32 { rd, ref mem, .. } => {
-            collector.add_def(rd);
-            memarg_regs(mem, collector);
-        }
-        &Inst::FpuLoad64 { rd, ref mem, .. } => {
-            collector.add_def(rd);
-            memarg_regs(mem, collector);
-        }
-        &Inst::FpuStore32 { rd, ref mem, .. } => {
-            collector.add_use(rd);
-            memarg_regs(mem, collector);
-        }
-        &Inst::FpuStore64 { rd, ref mem, .. } => {
-            collector.add_use(rd);
-            memarg_regs(mem, collector);
-        }
-        &Inst::FpuLoadRev32 { rd, ref mem, .. } => {
-            collector.add_def(rd);
-            memarg_regs(mem, collector);
-        }
-        &Inst::FpuLoadRev64 { rd, ref mem, .. } => {
-            collector.add_def(rd);
-            memarg_regs(mem, collector);
-        }
-        &Inst::FpuStoreRev32 { rd, ref mem, .. } => {
-            collector.add_use(rd);
-            memarg_regs(mem, collector);
-        }
-        &Inst::FpuStoreRev64 { rd, ref mem, .. } => {
-            collector.add_use(rd);
-            memarg_regs(mem, collector);
-        }
-        &Inst::LoadFpuConst32 { rd, .. } | &Inst::LoadFpuConst64 { rd, .. } => {
-            collector.add_def(rd);
-        }
-        &Inst::FpuToInt { rd, rn, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-        }
-        &Inst::IntToFpu { rd, rn, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-        }
-        &Inst::FpuRound { rd, rn, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-        }
-        &Inst::FpuVecRRR { rd, rn, rm, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-            collector.add_use(rm);
-        }
-        &Inst::Extend { rd, rn, .. } => {
-            collector.add_def(rd);
-            collector.add_use(rn);
-        }
-        &Inst::Call { link, ref info } => {
-            collector.add_def(link);
-            collector.add_uses(&*info.uses);
-            collector.add_defs(&*info.defs);
-        }
-        &Inst::CallInd { link, ref info } => {
-            collector.add_def(link);
-            collector.add_uses(&*info.uses);
-            collector.add_defs(&*info.defs);
-            collector.add_use(info.rn);
-        }
-        &Inst::Ret { .. } => {}
-        &Inst::Jump { .. } | &Inst::EpiloguePlaceholder => {}
-        &Inst::IndirectBr { rn, .. } => {
-            collector.add_use(rn);
-        }
-        &Inst::CondBr { .. } | &Inst::OneWayCondBr { .. } => {}
-        &Inst::Nop0 | Inst::Nop2 => {}
-        &Inst::Debugtrap => {}
-        &Inst::Trap { .. } => {}
-        &Inst::TrapIf { .. } => {}
-        &Inst::JTSequence { ridx, .. } => {
-            collector.add_use(ridx);
-        }
-        &Inst::LoadExtNameFar { rd, .. } => {
-            collector.add_def(rd);
-        }
-        &Inst::LoadAddr { rd, ref mem } => {
-            collector.add_def(rd);
-            memarg_regs(mem, collector);
-        }
-        &Inst::Loop { ref body, .. } => {
-            for inst in body.iter() {
-                s390x_get_regs(inst, collector);
-            }
-        }
-        &Inst::CondBreak { .. } => {}
-        &Inst::VirtualSPOffsetAdj { .. } => {}
-        &Inst::ValueLabelMarker { reg, .. } => {
-            collector.add_use(reg);
-        }
-        &Inst::Unwind { .. } => {}
-    }
-}
-
-//=============================================================================
-// Instructions: map_regs
-
-pub fn s390x_map_regs<RM: RegMapper>(inst: &mut Inst, mapper: &RM) {
-    fn map_mem<RM: RegMapper>(m: &RM, mem: &mut MemArg) {
-        match mem {
-            &mut MemArg::BXD12 {
-                ref mut base,
-                ref mut index,
-                ..
-            }
-            | &mut MemArg::BXD20 {
-                ref mut base,
-                ref mut index,
-                ..
-            } => {
-                if *base != zero_reg() {
-                    m.map_use(base);
-                }
-                if *index != zero_reg() {
-                    m.map_use(index);
-                }
-            }
-            &mut MemArg::Label { .. } | &mut MemArg::Symbol { .. } => {}
-            &mut MemArg::RegOffset { ref mut reg, .. } => m.map_use(reg),
-            &mut MemArg::InitialSPOffset { .. } | &mut MemArg::NominalSPOffset { .. } => {}
-        };
-    }
-
-    match inst {
-        &mut Inst::AluRRR {
-            ref mut rd,
-            ref mut rn,
-            ref mut rm,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-            mapper.map_use(rm);
-        }
-        &mut Inst::AluRRSImm16 {
-            ref mut rd,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::AluRX {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_mod(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::AluRR {
-            ref mut rd,
-            ref mut rm,
-            ..
-        } => {
-            mapper.map_mod(rd);
-            mapper.map_use(rm);
-        }
-        &mut Inst::AluRSImm16 { ref mut rd, .. } => {
-            mapper.map_mod(rd);
-        }
-        &mut Inst::AluRSImm32 { ref mut rd, .. } => {
-            mapper.map_mod(rd);
-        }
-        &mut Inst::AluRUImm32 { ref mut rd, .. } => {
-            mapper.map_mod(rd);
-        }
-        &mut Inst::AluRUImm16Shifted { ref mut rd, .. } => {
-            mapper.map_mod(rd);
-        }
-        &mut Inst::AluRUImm32Shifted { ref mut rd, .. } => {
-            mapper.map_mod(rd);
-        }
-        &mut Inst::SMulWide {
-            ref mut rn,
-            ref mut rm,
-            ..
-        } => {
-            mapper.map_use(rn);
-            mapper.map_use(rm);
-        }
-        &mut Inst::UMulWide { ref mut rn, .. } => {
-            mapper.map_use(rn);
-        }
-        &mut Inst::SDivMod32 { ref mut rn, .. } => {
-            mapper.map_use(rn);
-        }
-        &mut Inst::SDivMod64 { ref mut rn, .. } => {
-            mapper.map_use(rn);
-        }
-        &mut Inst::UDivMod32 { ref mut rn, .. } => {
-            mapper.map_use(rn);
-        }
-        &mut Inst::UDivMod64 { ref mut rn, .. } => {
-            mapper.map_use(rn);
-        }
-        &mut Inst::Flogr { ref mut rn, .. } => {
-            mapper.map_use(rn);
-        }
-        &mut Inst::ShiftRR {
-            ref mut rd,
-            ref mut rn,
-            ref mut shift_reg,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-            if *shift_reg != zero_reg() {
-                mapper.map_use(shift_reg);
-            }
-        }
-        &mut Inst::RxSBG {
-            ref mut rd,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_mod(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::RxSBGTest {
-            ref mut rd,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_use(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::UnaryRR {
-            ref mut rd,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::CmpRR {
-            ref mut rn,
-            ref mut rm,
-            ..
-        } => {
-            mapper.map_use(rn);
-            mapper.map_use(rm);
-        }
-        &mut Inst::CmpRX {
-            ref mut rn,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_use(rn);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::CmpRSImm16 { ref mut rn, .. } => {
-            mapper.map_use(rn);
-        }
-        &mut Inst::CmpRSImm32 { ref mut rn, .. } => {
-            mapper.map_use(rn);
-        }
-        &mut Inst::CmpRUImm32 { ref mut rn, .. } => {
-            mapper.map_use(rn);
-        }
-        &mut Inst::CmpTrapRR {
-            ref mut rn,
-            ref mut rm,
-            ..
-        } => {
-            mapper.map_use(rn);
-            mapper.map_use(rm);
-        }
-        &mut Inst::CmpTrapRSImm16 { ref mut rn, .. } => {
-            mapper.map_use(rn);
-        }
-        &mut Inst::CmpTrapRUImm16 { ref mut rn, .. } => {
-            mapper.map_use(rn);
-        }
-
-        &mut Inst::AtomicRmw {
-            ref mut rd,
-            ref mut rn,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::AtomicCas32 {
-            ref mut rd,
-            ref mut rn,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_mod(rd);
-            mapper.map_use(rn);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::AtomicCas64 {
-            ref mut rd,
-            ref mut rn,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_mod(rd);
-            mapper.map_use(rn);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::Fence => {}
-
-        &mut Inst::Load32 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_def(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::Load32ZExt8 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_def(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::Load32SExt8 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_def(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::Load32ZExt16 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_def(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::Load32SExt16 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_def(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::Load64 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_def(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::Load64ZExt8 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_def(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::Load64SExt8 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_def(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::Load64ZExt16 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_def(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::Load64SExt16 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_def(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::Load64ZExt32 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_def(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::Load64SExt32 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_def(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::LoadRev16 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_def(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::LoadRev32 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_def(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::LoadRev64 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_def(rd);
-            map_mem(mapper, mem);
-        }
-
-        &mut Inst::Store8 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_use(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::Store16 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_use(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::Store32 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_use(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::Store64 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_use(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::StoreImm8 { ref mut mem, .. } => {
-            map_mem(mapper, mem);
-        }
-        &mut Inst::StoreImm16 { ref mut mem, .. } => {
-            map_mem(mapper, mem);
-        }
-        &mut Inst::StoreImm32SExt16 { ref mut mem, .. } => {
-            map_mem(mapper, mem);
-        }
-        &mut Inst::StoreImm64SExt16 { ref mut mem, .. } => {
-            map_mem(mapper, mem);
-        }
-        &mut Inst::StoreRev16 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_use(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::StoreRev32 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_use(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::StoreRev64 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_use(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::LoadMultiple64 { .. } => {
-            // This instruction accesses all registers between rt and rt2,
-            // so it cannot be remapped.  But this does not matter since
-            // the instruction is only ever used after register allocation.
-            unreachable!();
-        }
-        &mut Inst::StoreMultiple64 { .. } => {
-            // This instruction accesses all registers between rt and rt2,
-            // so it cannot be remapped.  But this does not matter since
-            // the instruction is only ever used after register allocation.
-            unreachable!();
-        }
-
-        &mut Inst::Mov64 {
-            ref mut rd,
-            ref mut rm,
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rm);
-        }
-        &mut Inst::Mov32 {
-            ref mut rd,
-            ref mut rm,
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rm);
-        }
-        &mut Inst::Mov32Imm { ref mut rd, .. } => {
-            mapper.map_def(rd);
-        }
-        &mut Inst::Mov32SImm16 { ref mut rd, .. } => {
-            mapper.map_def(rd);
-        }
-        &mut Inst::Mov64SImm16 { ref mut rd, .. } => {
-            mapper.map_def(rd);
-        }
-        &mut Inst::Mov64SImm32 { ref mut rd, .. } => {
-            mapper.map_def(rd);
-        }
-        &mut Inst::Mov64UImm16Shifted { ref mut rd, .. } => {
-            mapper.map_def(rd);
-        }
-        &mut Inst::Mov64UImm32Shifted { ref mut rd, .. } => {
-            mapper.map_def(rd);
-        }
-        &mut Inst::Insert64UImm16Shifted { ref mut rd, .. } => {
-            mapper.map_mod(rd);
-        }
-        &mut Inst::Insert64UImm32Shifted { ref mut rd, .. } => {
-            mapper.map_mod(rd);
-        }
-        &mut Inst::CMov64 {
-            ref mut rd,
-            ref mut rm,
-            ..
-        } => {
-            mapper.map_mod(rd);
-            mapper.map_use(rm);
-        }
-        &mut Inst::CMov32 {
-            ref mut rd,
-            ref mut rm,
-            ..
-        } => {
-            mapper.map_mod(rd);
-            mapper.map_use(rm);
-        }
-        &mut Inst::CMov32SImm16 { ref mut rd, .. } => {
-            mapper.map_mod(rd);
-        }
-        &mut Inst::CMov64SImm16 { ref mut rd, .. } => {
-            mapper.map_mod(rd);
-        }
-        &mut Inst::FpuMove32 {
-            ref mut rd,
-            ref mut rn,
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::FpuMove64 {
-            ref mut rd,
-            ref mut rn,
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::FpuCMov64 {
-            ref mut rd,
-            ref mut rm,
-            ..
-        } => {
-            mapper.map_mod(rd);
-            mapper.map_use(rm);
-        }
-        &mut Inst::FpuCMov32 {
-            ref mut rd,
-            ref mut rm,
-            ..
-        } => {
-            mapper.map_mod(rd);
-            mapper.map_use(rm);
-        }
-        &mut Inst::MovToFpr {
-            ref mut rd,
-            ref mut rn,
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::MovFromFpr {
-            ref mut rd,
-            ref mut rn,
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::FpuRR {
-            ref mut rd,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::FpuRRR {
-            ref mut rd,
-            ref mut rm,
-            ..
-        } => {
-            mapper.map_mod(rd);
-            mapper.map_use(rm);
-        }
-        &mut Inst::FpuRRRR {
-            ref mut rd,
-            ref mut rn,
-            ref mut rm,
-            ..
-        } => {
-            mapper.map_mod(rd);
-            mapper.map_use(rn);
-            mapper.map_use(rm);
-        }
-        &mut Inst::FpuCopysign {
-            ref mut rd,
-            ref mut rn,
-            ref mut rm,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-            mapper.map_use(rm);
-        }
-        &mut Inst::FpuCmp32 {
-            ref mut rn,
-            ref mut rm,
-        } => {
-            mapper.map_use(rn);
-            mapper.map_use(rm);
-        }
-        &mut Inst::FpuCmp64 {
-            ref mut rn,
-            ref mut rm,
-        } => {
-            mapper.map_use(rn);
-            mapper.map_use(rm);
-        }
-        &mut Inst::FpuLoad32 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_def(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::FpuLoad64 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_def(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::FpuStore32 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_use(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::FpuStore64 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_use(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::FpuLoadRev32 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_def(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::FpuLoadRev64 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_def(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::FpuStoreRev32 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_use(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::FpuStoreRev64 {
-            ref mut rd,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_use(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::LoadFpuConst32 { ref mut rd, .. } => {
-            mapper.map_def(rd);
-        }
-        &mut Inst::LoadFpuConst64 { ref mut rd, .. } => {
-            mapper.map_def(rd);
-        }
-        &mut Inst::FpuToInt {
-            ref mut rd,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::IntToFpu {
-            ref mut rd,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::FpuRound {
-            ref mut rd,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::FpuVecRRR {
-            ref mut rd,
-            ref mut rn,
-            ref mut rm,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-            mapper.map_use(rm);
-        }
-        &mut Inst::Extend {
-            ref mut rd,
-            ref mut rn,
-            ..
-        } => {
-            mapper.map_def(rd);
-            mapper.map_use(rn);
-        }
-        &mut Inst::Call {
-            ref mut link,
-            ref mut info,
-        } => {
-            mapper.map_def(link);
-            for r in info.uses.iter_mut() {
-                mapper.map_use(r);
-            }
-            for r in info.defs.iter_mut() {
-                mapper.map_def(r);
-            }
-        }
-        &mut Inst::CallInd {
-            ref mut link,
-            ref mut info,
-            ..
-        } => {
-            mapper.map_def(link);
-            for r in info.uses.iter_mut() {
-                mapper.map_use(r);
-            }
-            for r in info.defs.iter_mut() {
-                mapper.map_def(r);
-            }
-            mapper.map_use(&mut info.rn);
-        }
-        &mut Inst::Ret { .. } => {}
-        &mut Inst::EpiloguePlaceholder => {}
-        &mut Inst::Jump { .. } => {}
-        &mut Inst::IndirectBr { ref mut rn, .. } => {
-            mapper.map_use(rn);
-        }
-        &mut Inst::CondBr { .. } | &mut Inst::OneWayCondBr { .. } => {}
-        &mut Inst::Debugtrap | &mut Inst::Trap { .. } | &mut Inst::TrapIf { .. } => {}
-        &mut Inst::Nop0 | &mut Inst::Nop2 => {}
-        &mut Inst::JTSequence { ref mut ridx, .. } => {
-            mapper.map_use(ridx);
-        }
-        &mut Inst::LoadExtNameFar { ref mut rd, .. } => {
-            mapper.map_def(rd);
-        }
-        &mut Inst::LoadAddr {
-            ref mut rd,
-            ref mut mem,
-        } => {
-            mapper.map_def(rd);
-            map_mem(mapper, mem);
-        }
-        &mut Inst::Loop { ref mut body, .. } => {
-            for inst in body.iter_mut() {
-                s390x_map_regs(inst, mapper);
-            }
-        }
-        &mut Inst::CondBreak { .. } => {}
-        &mut Inst::VirtualSPOffsetAdj { .. } => {}
-        &mut Inst::ValueLabelMarker { ref mut reg, .. } => {
-            mapper.map_use(reg);
-        }
-        &mut Inst::Unwind { .. } => {}
-    }
-}
-
-//=============================================================================
-// Instructions: misc functions and external interface
-
-impl MachInst for Inst {
-    type LabelUse = LabelUse;
-
-    fn get_regs(&self, collector: &mut RegUsageCollector) {
-        s390x_get_regs(self, collector)
-    }
-
-    fn map_regs<RUM: RegUsageMapper>(&mut self, mapper: &RUM) {
-        s390x_map_regs(self, mapper);
-    }
-
-    fn is_move(&self) -> Option<(Writable<Reg>, Reg)> {
-        match self {
-            &Inst::Mov32 { rd, rm } => Some((rd, rm)),
-            &Inst::Mov64 { rd, rm } => Some((rd, rm)),
-            &Inst::FpuMove32 { rd, rn } => Some((rd, rn)),
-            &Inst::FpuMove64 { rd, rn } => Some((rd, rn)),
-            _ => None,
-        }
-    }
-
-    fn is_epilogue_placeholder(&self) -> bool {
-        if let Inst::EpiloguePlaceholder = self {
-            true
-        } else {
-            false
-        }
-    }
-
-    fn is_term<'a>(&'a self) -> MachTerminator<'a> {
-        match self {
-            &Inst::Ret { .. } | &Inst::EpiloguePlaceholder => MachTerminator::Ret,
-            &Inst::Jump { dest } => MachTerminator::Uncond(dest),
-            &Inst::CondBr {
-                taken, not_taken, ..
-            } => MachTerminator::Cond(taken, not_taken),
-            &Inst::OneWayCondBr { .. } => {
-                // Explicitly invisible to CFG processing.
-                MachTerminator::None
-            }
-            &Inst::IndirectBr { ref targets, .. } => MachTerminator::Indirect(&targets[..]),
-            &Inst::JTSequence { ref targets, .. } => MachTerminator::Indirect(&targets[..]),
-            _ => MachTerminator::None,
-        }
-    }
-
-    fn stack_op_info(&self) -> Option<MachInstStackOpInfo> {
-        match self {
-            &Inst::VirtualSPOffsetAdj { offset } => Some(MachInstStackOpInfo::NomSPAdj(offset)),
-            &Inst::Store64 {
-                rd,
-                mem: MemArg::NominalSPOffset { off },
-            } => Some(MachInstStackOpInfo::StoreNomSPOff(rd, off)),
-            &Inst::Load64 {
-                rd,
-                mem: MemArg::NominalSPOffset { off },
-            } => Some(MachInstStackOpInfo::LoadNomSPOff(rd.to_reg(), off)),
-            _ => None,
-        }
-    }
-
-    fn gen_move(to_reg: Writable<Reg>, from_reg: Reg, ty: Type) -> Inst {
-        assert!(ty.bits() <= 64);
-        if ty.bits() <= 32 {
-            Inst::mov32(to_reg, from_reg)
-        } else {
-            Inst::mov64(to_reg, from_reg)
-        }
-    }
-
-    fn gen_constant<F: FnMut(Type) -> Writable<Reg>>(
-        to_regs: ValueRegs<Writable<Reg>>,
-        value: u128,
-        ty: Type,
-        _alloc_tmp: F,
-    ) -> SmallVec<[Inst; 4]> {
-        let to_reg = to_regs
-            .only_reg()
-            .expect("multi-reg values not supported yet");
-        let value = value as u64;
-        match ty {
-            types::F64 => {
-                let mut ret = SmallVec::new();
-                ret.push(Inst::load_fp_constant64(to_reg, f64::from_bits(value)));
-                ret
-            }
-            types::F32 => {
-                let mut ret = SmallVec::new();
-                ret.push(Inst::load_fp_constant32(
-                    to_reg,
-                    f32::from_bits(value as u32),
-                ));
-                ret
-            }
-            types::I64 | types::B64 | types::R64 => Inst::load_constant64(to_reg, value),
-            types::B1
-            | types::I8
-            | types::B8
-            | types::I16
-            | types::B16
-            | types::I32
-            | types::B32 => Inst::load_constant32(to_reg, value as u32),
-            _ => unreachable!(),
-        }
-    }
-
-    fn gen_nop(preferred_size: usize) -> Inst {
-        if preferred_size == 0 {
-            Inst::Nop0
-        } else {
-            // We can't give a NOP (or any insn) < 2 bytes.
-            assert!(preferred_size >= 2);
-            Inst::Nop2
-        }
-    }
-
-    fn maybe_direct_reload(&self, _reg: VirtualReg, _slot: SpillSlot) -> Option<Inst> {
-        None
-    }
-
-    fn rc_for_type(ty: Type) -> CodegenResult<(&'static [RegClass], &'static [Type])> {
-        match ty {
-            types::I8 => Ok((&[RegClass::I64], &[types::I8])),
-            types::I16 => Ok((&[RegClass::I64], &[types::I16])),
-            types::I32 => Ok((&[RegClass::I64], &[types::I32])),
-            types::I64 => Ok((&[RegClass::I64], &[types::I64])),
-            types::B1 => Ok((&[RegClass::I64], &[types::B1])),
-            types::B8 => Ok((&[RegClass::I64], &[types::B8])),
-            types::B16 => Ok((&[RegClass::I64], &[types::B16])),
-            types::B32 => Ok((&[RegClass::I64], &[types::B32])),
-            types::B64 => Ok((&[RegClass::I64], &[types::B64])),
-            types::R32 => panic!("32-bit reftype pointer should never be seen on s390x"),
-            types::R64 => Ok((&[RegClass::I64], &[types::R64])),
-            types::F32 => Ok((&[RegClass::F64], &[types::F32])),
-            types::F64 => Ok((&[RegClass::F64], &[types::F64])),
-            types::I128 => Ok((&[RegClass::I64, RegClass::I64], &[types::I64, types::I64])),
-            types::B128 => Ok((&[RegClass::I64, RegClass::I64], &[types::B64, types::B64])),
-            // FIXME: We don't really have IFLAGS, but need to allow it here
-            // for now to support the SelectifSpectreGuard instruction.
-            types::IFLAGS => Ok((&[RegClass::I64], &[types::I64])),
-            _ => Err(CodegenError::Unsupported(format!(
-                "Unexpected SSA-value type: {}",
-                ty
-            ))),
-        }
-    }
-
-    fn gen_jump(target: MachLabel) -> Inst {
-        Inst::Jump { dest: target }
-    }
-
-    fn worst_case_size() -> CodeOffset {
-        // The maximum size, in bytes, of any `Inst`'s emitted code. We have at least one case of
-        // an 8-instruction sequence (saturating int-to-float conversions) with three embedded
-        // 64-bit f64 constants.
-        //
-        // Note that inline jump-tables handle island/pool insertion separately, so we do not need
-        // to account for them here (otherwise the worst case would be 2^31 * 4, clearly not
-        // feasible for other reasons).
-        44
-    }
-
-    fn ref_type_regclass(_: &settings::Flags) -> RegClass {
-        RegClass::I64
-    }
-
-    fn gen_value_label_marker(label: ValueLabel, reg: Reg) -> Self {
-        Inst::ValueLabelMarker { label, reg }
-    }
-
-    fn defines_value_label(&self) -> Option<(ValueLabel, Reg)> {
-        match self {
-            Inst::ValueLabelMarker { label, reg } => Some((*label, *reg)),
-            _ => None,
-        }
-    }
-}
-
-//=============================================================================
-// Pretty-printing of instructions.
-
-fn mem_finalize_for_show(
-    mem: &MemArg,
-    mb_rru: Option<&RealRegUniverse>,
-    state: &EmitState,
-    have_d12: bool,
-    have_d20: bool,
-    have_pcrel: bool,
-    have_index: bool,
-) -> (String, MemArg) {
-    let (mem_insts, mem) = mem_finalize(mem, state, have_d12, have_d20, have_pcrel, have_index);
-    let mut mem_str = mem_insts
-        .into_iter()
-        .map(|inst| inst.show_rru(mb_rru))
-        .collect::<Vec<_>>()
-        .join(" ; ");
-    if !mem_str.is_empty() {
-        mem_str += " ; ";
-    }
-
-    (mem_str, mem)
-}
-
-impl PrettyPrint for Inst {
-    fn show_rru(&self, mb_rru: Option<&RealRegUniverse>) -> String {
-        self.pretty_print(mb_rru, &mut EmitState::default())
-    }
-}
-
-impl Inst {
-    fn print_with_state(&self, mb_rru: Option<&RealRegUniverse>, state: &mut EmitState) -> String {
-        match self {
-            &Inst::Nop0 => "nop-zero-len".to_string(),
-            &Inst::Nop2 => "nop".to_string(),
-            &Inst::AluRRR { alu_op, rd, rn, rm } => {
-                let (op, have_rr) = match alu_op {
-                    ALUOp::Add32 => ("ark", true),
-                    ALUOp::Add64 => ("agrk", true),
-                    ALUOp::AddLogical32 => ("alrk", true),
-                    ALUOp::AddLogical64 => ("algrk", true),
-                    ALUOp::Sub32 => ("srk", true),
-                    ALUOp::Sub64 => ("sgrk", true),
-                    ALUOp::SubLogical32 => ("slrk", true),
-                    ALUOp::SubLogical64 => ("slgrk", true),
-                    ALUOp::Mul32 => ("msrkc", true),
-                    ALUOp::Mul64 => ("msgrkc", true),
-                    ALUOp::And32 => ("nrk", true),
-                    ALUOp::And64 => ("ngrk", true),
-                    ALUOp::Orr32 => ("ork", true),
-                    ALUOp::Orr64 => ("ogrk", true),
-                    ALUOp::Xor32 => ("xrk", true),
-                    ALUOp::Xor64 => ("xgrk", true),
-                    ALUOp::AndNot32 => ("nnrk", false),
-                    ALUOp::AndNot64 => ("nngrk", false),
-                    ALUOp::OrrNot32 => ("nork", false),
-                    ALUOp::OrrNot64 => ("nogrk", false),
-                    ALUOp::XorNot32 => ("nxrk", false),
-                    ALUOp::XorNot64 => ("nxgrk", false),
-                    _ => unreachable!(),
-                };
-                if have_rr && rd.to_reg() == rn {
-                    let inst = Inst::AluRR { alu_op, rd, rm };
-                    return inst.print_with_state(mb_rru, state);
-                }
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let rn = rn.show_rru(mb_rru);
-                let rm = rm.show_rru(mb_rru);
-                format!("{} {}, {}, {}", op, rd, rn, rm)
-            }
-            &Inst::AluRRSImm16 {
-                alu_op,
-                rd,
-                rn,
-                imm,
-            } => {
-                if rd.to_reg() == rn {
-                    let inst = Inst::AluRSImm16 { alu_op, rd, imm };
-                    return inst.print_with_state(mb_rru, state);
-                }
-                let op = match alu_op {
-                    ALUOp::Add32 => "ahik",
-                    ALUOp::Add64 => "aghik",
-                    _ => unreachable!(),
-                };
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let rn = rn.show_rru(mb_rru);
-                format!("{} {}, {}, {}", op, rd, rn, imm)
-            }
-            &Inst::AluRR { alu_op, rd, rm } => {
-                let op = match alu_op {
-                    ALUOp::Add32 => "ar",
-                    ALUOp::Add64 => "agr",
-                    ALUOp::Add64Ext32 => "agfr",
-                    ALUOp::AddLogical32 => "alr",
-                    ALUOp::AddLogical64 => "algr",
-                    ALUOp::AddLogical64Ext32 => "algfr",
-                    ALUOp::Sub32 => "sr",
-                    ALUOp::Sub64 => "sgr",
-                    ALUOp::Sub64Ext32 => "sgfr",
-                    ALUOp::SubLogical32 => "slr",
-                    ALUOp::SubLogical64 => "slgr",
-                    ALUOp::SubLogical64Ext32 => "slgfr",
-                    ALUOp::Mul32 => "msr",
-                    ALUOp::Mul64 => "msgr",
-                    ALUOp::Mul64Ext32 => "msgfr",
-                    ALUOp::And32 => "nr",
-                    ALUOp::And64 => "ngr",
-                    ALUOp::Orr32 => "or",
-                    ALUOp::Orr64 => "ogr",
-                    ALUOp::Xor32 => "xr",
-                    ALUOp::Xor64 => "xgr",
-                    _ => unreachable!(),
-                };
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let rm = rm.show_rru(mb_rru);
-                format!("{} {}, {}", op, rd, rm)
-            }
-            &Inst::AluRX {
-                alu_op,
-                rd,
-                ref mem,
-            } => {
-                let (opcode_rx, opcode_rxy) = match alu_op {
-                    ALUOp::Add32 => (Some("a"), Some("ay")),
-                    ALUOp::Add32Ext16 => (Some("ah"), Some("ahy")),
-                    ALUOp::Add64 => (None, Some("ag")),
-                    ALUOp::Add64Ext16 => (None, Some("agh")),
-                    ALUOp::Add64Ext32 => (None, Some("agf")),
-                    ALUOp::AddLogical32 => (Some("al"), Some("aly")),
-                    ALUOp::AddLogical64 => (None, Some("alg")),
-                    ALUOp::AddLogical64Ext32 => (None, Some("algf")),
-                    ALUOp::Sub32 => (Some("s"), Some("sy")),
-                    ALUOp::Sub32Ext16 => (Some("sh"), Some("shy")),
-                    ALUOp::Sub64 => (None, Some("sg")),
-                    ALUOp::Sub64Ext16 => (None, Some("sgh")),
-                    ALUOp::Sub64Ext32 => (None, Some("sgf")),
-                    ALUOp::SubLogical32 => (Some("sl"), Some("sly")),
-                    ALUOp::SubLogical64 => (None, Some("slg")),
-                    ALUOp::SubLogical64Ext32 => (None, Some("slgf")),
-                    ALUOp::Mul32 => (Some("ms"), Some("msy")),
-                    ALUOp::Mul32Ext16 => (Some("mh"), Some("mhy")),
-                    ALUOp::Mul64 => (None, Some("msg")),
-                    ALUOp::Mul64Ext16 => (None, Some("mgh")),
-                    ALUOp::Mul64Ext32 => (None, Some("msgf")),
-                    ALUOp::And32 => (Some("n"), Some("ny")),
-                    ALUOp::And64 => (None, Some("ng")),
-                    ALUOp::Orr32 => (Some("o"), Some("oy")),
-                    ALUOp::Orr64 => (None, Some("og")),
-                    ALUOp::Xor32 => (Some("x"), Some("xy")),
-                    ALUOp::Xor64 => (None, Some("xg")),
-                    _ => unreachable!(),
-                };
-
-                let (mem_str, mem) = mem_finalize_for_show(
-                    mem,
-                    mb_rru,
-                    state,
-                    opcode_rx.is_some(),
-                    opcode_rxy.is_some(),
-                    false,
-                    true,
-                );
-
-                let op = match &mem {
-                    &MemArg::BXD12 { .. } => opcode_rx,
-                    &MemArg::BXD20 { .. } => opcode_rxy,
-                    _ => unreachable!(),
-                };
-
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let mem = mem.show_rru(mb_rru);
-                format!("{}{} {}, {}", mem_str, op.unwrap(), rd, mem)
-            }
-            &Inst::AluRSImm16 { alu_op, rd, imm } => {
-                let op = match alu_op {
-                    ALUOp::Add32 => "ahi",
-                    ALUOp::Add64 => "aghi",
-                    ALUOp::Mul32 => "mhi",
-                    ALUOp::Mul64 => "mghi",
-                    _ => unreachable!(),
-                };
-                let rd = rd.to_reg().show_rru(mb_rru);
-                format!("{} {}, {}", op, rd, imm)
-            }
-            &Inst::AluRSImm32 { alu_op, rd, imm } => {
-                let op = match alu_op {
-                    ALUOp::Add32 => "afi",
-                    ALUOp::Add64 => "agfi",
-                    ALUOp::Mul32 => "msfi",
-                    ALUOp::Mul64 => "msgfi",
-                    _ => unreachable!(),
-                };
-                let rd = rd.to_reg().show_rru(mb_rru);
-                format!("{} {}, {}", op, rd, imm)
-            }
-            &Inst::AluRUImm32 { alu_op, rd, imm } => {
-                let op = match alu_op {
-                    ALUOp::AddLogical32 => "alfi",
-                    ALUOp::AddLogical64 => "algfi",
-                    ALUOp::SubLogical32 => "slfi",
-                    ALUOp::SubLogical64 => "slgfi",
-                    _ => unreachable!(),
-                };
-                let rd = rd.to_reg().show_rru(mb_rru);
-                format!("{} {}, {}", op, rd, imm)
-            }
-            &Inst::AluRUImm16Shifted { alu_op, rd, imm } => {
-                let op = match (alu_op, imm.shift) {
-                    (ALUOp::And32, 0) => "nill",
-                    (ALUOp::And32, 1) => "nilh",
-                    (ALUOp::And64, 0) => "nill",
-                    (ALUOp::And64, 1) => "nilh",
-                    (ALUOp::And64, 2) => "nihl",
-                    (ALUOp::And64, 3) => "nihh",
-                    (ALUOp::Orr32, 0) => "oill",
-                    (ALUOp::Orr32, 1) => "oilh",
-                    (ALUOp::Orr64, 0) => "oill",
-                    (ALUOp::Orr64, 1) => "oilh",
-                    (ALUOp::Orr64, 2) => "oihl",
-                    (ALUOp::Orr64, 3) => "oihh",
-                    _ => unreachable!(),
-                };
-                let rd = rd.to_reg().show_rru(mb_rru);
-                format!("{} {}, {}", op, rd, imm.bits)
-            }
-            &Inst::AluRUImm32Shifted { alu_op, rd, imm } => {
-                let op = match (alu_op, imm.shift) {
-                    (ALUOp::And32, 0) => "nilf",
-                    (ALUOp::And64, 0) => "nilf",
-                    (ALUOp::And64, 1) => "nihf",
-                    (ALUOp::Orr32, 0) => "oilf",
-                    (ALUOp::Orr64, 0) => "oilf",
-                    (ALUOp::Orr64, 1) => "oihf",
-                    (ALUOp::Xor32, 0) => "xilf",
-                    (ALUOp::Xor64, 0) => "xilf",
-                    (ALUOp::Xor64, 1) => "xihf",
-                    _ => unreachable!(),
-                };
-                let rd = rd.to_reg().show_rru(mb_rru);
-                format!("{} {}, {}", op, rd, imm.bits)
-            }
-            &Inst::SMulWide { rn, rm } => {
-                let op = "mgrk";
-                let rd = gpr(0).show_rru(mb_rru);
-                let rn = rn.show_rru(mb_rru);
-                let rm = rm.show_rru(mb_rru);
-                format!("{} {}, {}, {}", op, rd, rn, rm)
-            }
-            &Inst::UMulWide { rn } => {
-                let op = "mlgr";
-                let rd = gpr(0).show_rru(mb_rru);
-                let rn = rn.show_rru(mb_rru);
-                format!("{} {}, {}", op, rd, rn)
-            }
-            &Inst::SDivMod32 { rn, .. } => {
-                let op = "dsgfr";
-                let rd = gpr(0).show_rru(mb_rru);
-                let rn = rn.show_rru(mb_rru);
-                format!("{} {}, {}", op, rd, rn)
-            }
-            &Inst::SDivMod64 { rn, .. } => {
-                let op = "dsgr";
-                let rd = gpr(0).show_rru(mb_rru);
-                let rn = rn.show_rru(mb_rru);
-                format!("{} {}, {}", op, rd, rn)
-            }
-            &Inst::UDivMod32 { rn, .. } => {
-                let op = "dlr";
-                let rd = gpr(0).show_rru(mb_rru);
-                let rn = rn.show_rru(mb_rru);
-                format!("{} {}, {}", op, rd, rn)
-            }
-            &Inst::UDivMod64 { rn, .. } => {
-                let op = "dlgr";
-                let rd = gpr(0).show_rru(mb_rru);
-                let rn = rn.show_rru(mb_rru);
-                format!("{} {}, {}", op, rd, rn)
-            }
-            &Inst::Flogr { rn } => {
-                let op = "flogr";
-                let rd = gpr(0).show_rru(mb_rru);
-                let rn = rn.show_rru(mb_rru);
-                format!("{} {}, {}", op, rd, rn)
-            }
-            &Inst::ShiftRR {
-                shift_op,
-                rd,
-                rn,
-                shift_imm,
-                shift_reg,
-            } => {
-                let op = match shift_op {
-                    ShiftOp::RotL32 => "rll",
-                    ShiftOp::RotL64 => "rllg",
-                    ShiftOp::LShL32 => "sllk",
-                    ShiftOp::LShL64 => "sllg",
-                    ShiftOp::LShR32 => "srlk",
-                    ShiftOp::LShR64 => "srlg",
-                    ShiftOp::AShR32 => "srak",
-                    ShiftOp::AShR64 => "srag",
-                };
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let rn = rn.show_rru(mb_rru);
-                let shift_reg = if shift_reg != zero_reg() {
-                    format!("({})", shift_reg.show_rru(mb_rru))
-                } else {
-                    "".to_string()
-                };
-                format!("{} {}, {}, {}{}", op, rd, rn, shift_imm, shift_reg)
-            }
-            &Inst::RxSBG {
-                op,
-                rd,
-                rn,
-                start_bit,
-                end_bit,
-                rotate_amt,
-            } => {
-                let op = match op {
-                    RxSBGOp::Insert => "risbgn",
-                    RxSBGOp::And => "rnsbg",
-                    RxSBGOp::Or => "rosbg",
-                    RxSBGOp::Xor => "rxsbg",
-                };
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let rn = rn.show_rru(mb_rru);
-                format!(
-                    "{} {}, {}, {}, {}, {}",
-                    op,
-                    rd,
-                    rn,
-                    start_bit,
-                    end_bit,
-                    (rotate_amt as u8) & 63
-                )
-            }
-            &Inst::RxSBGTest {
-                op,
-                rd,
-                rn,
-                start_bit,
-                end_bit,
-                rotate_amt,
-            } => {
-                let op = match op {
-                    RxSBGOp::And => "rnsbg",
-                    RxSBGOp::Or => "rosbg",
-                    RxSBGOp::Xor => "rxsbg",
-                    _ => unreachable!(),
-                };
-                let rd = rd.show_rru(mb_rru);
-                let rn = rn.show_rru(mb_rru);
-                format!(
-                    "{} {}, {}, {}, {}, {}",
-                    op,
-                    rd,
-                    rn,
-                    start_bit | 0x80,
-                    end_bit,
-                    (rotate_amt as u8) & 63
-                )
-            }
-            &Inst::UnaryRR { op, rd, rn } => {
-                let (op, extra) = match op {
-                    UnaryOp::Abs32 => ("lpr", ""),
-                    UnaryOp::Abs64 => ("lpgr", ""),
-                    UnaryOp::Abs64Ext32 => ("lpgfr", ""),
-                    UnaryOp::Neg32 => ("lcr", ""),
-                    UnaryOp::Neg64 => ("lcgr", ""),
-                    UnaryOp::Neg64Ext32 => ("lcgfr", ""),
-                    UnaryOp::PopcntByte => ("popcnt", ""),
-                    UnaryOp::PopcntReg => ("popcnt", ", 8"),
-                    UnaryOp::BSwap32 => ("lrvr", ""),
-                    UnaryOp::BSwap64 => ("lrvgr", ""),
-                };
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let rn = rn.show_rru(mb_rru);
-                format!("{} {}, {}{}", op, rd, rn, extra)
-            }
-            &Inst::CmpRR { op, rn, rm } => {
-                let op = match op {
-                    CmpOp::CmpS32 => "cr",
-                    CmpOp::CmpS64 => "cgr",
-                    CmpOp::CmpS64Ext32 => "cgfr",
-                    CmpOp::CmpL32 => "clr",
-                    CmpOp::CmpL64 => "clgr",
-                    CmpOp::CmpL64Ext32 => "clgfr",
-                    _ => unreachable!(),
-                };
-                let rn = rn.show_rru(mb_rru);
-                let rm = rm.show_rru(mb_rru);
-                format!("{} {}, {}", op, rn, rm)
-            }
-            &Inst::CmpRX { op, rn, ref mem } => {
-                let (opcode_rx, opcode_rxy, opcode_ril) = match op {
-                    CmpOp::CmpS32 => (Some("c"), Some("cy"), Some("crl")),
-                    CmpOp::CmpS32Ext16 => (Some("ch"), Some("chy"), Some("chrl")),
-                    CmpOp::CmpS64 => (None, Some("cg"), Some("cgrl")),
-                    CmpOp::CmpS64Ext16 => (None, Some("cgh"), Some("cghrl")),
-                    CmpOp::CmpS64Ext32 => (None, Some("cgf"), Some("cgfrl")),
-                    CmpOp::CmpL32 => (Some("cl"), Some("cly"), Some("clrl")),
-                    CmpOp::CmpL32Ext16 => (None, None, Some("clhrl")),
-                    CmpOp::CmpL64 => (None, Some("clg"), Some("clgrl")),
-                    CmpOp::CmpL64Ext16 => (None, None, Some("clghrl")),
-                    CmpOp::CmpL64Ext32 => (None, Some("clgf"), Some("clgfrl")),
-                };
-
-                let (mem_str, mem) = mem_finalize_for_show(
-                    mem,
-                    mb_rru,
-                    state,
-                    opcode_rx.is_some(),
-                    opcode_rxy.is_some(),
-                    opcode_ril.is_some(),
-                    true,
-                );
-
-                let op = match &mem {
-                    &MemArg::BXD12 { .. } => opcode_rx,
-                    &MemArg::BXD20 { .. } => opcode_rxy,
-                    &MemArg::Label { .. } | &MemArg::Symbol { .. } => opcode_ril,
-                    _ => unreachable!(),
-                };
-
-                let rn = rn.show_rru(mb_rru);
-                let mem = mem.show_rru(mb_rru);
-                format!("{}{} {}, {}", mem_str, op.unwrap(), rn, mem)
-            }
-            &Inst::CmpRSImm16 { op, rn, imm } => {
-                let op = match op {
-                    CmpOp::CmpS32 => "chi",
-                    CmpOp::CmpS64 => "cghi",
-                    _ => unreachable!(),
-                };
-                let rn = rn.show_rru(mb_rru);
-                format!("{} {}, {}", op, rn, imm)
-            }
-            &Inst::CmpRSImm32 { op, rn, imm } => {
-                let op = match op {
-                    CmpOp::CmpS32 => "cfi",
-                    CmpOp::CmpS64 => "cgfi",
-                    _ => unreachable!(),
-                };
-                let rn = rn.show_rru(mb_rru);
-                format!("{} {}, {}", op, rn, imm)
-            }
-            &Inst::CmpRUImm32 { op, rn, imm } => {
-                let op = match op {
-                    CmpOp::CmpL32 => "clfi",
-                    CmpOp::CmpL64 => "clgfi",
-                    _ => unreachable!(),
-                };
-                let rn = rn.show_rru(mb_rru);
-                format!("{} {}, {}", op, rn, imm)
-            }
-            &Inst::CmpTrapRR {
-                op, rn, rm, cond, ..
-            } => {
-                let op = match op {
-                    CmpOp::CmpS32 => "crt",
-                    CmpOp::CmpS64 => "cgrt",
-                    CmpOp::CmpL32 => "clrt",
-                    CmpOp::CmpL64 => "clgrt",
-                    _ => unreachable!(),
-                };
-                let rn = rn.show_rru(mb_rru);
-                let rm = rm.show_rru(mb_rru);
-                let cond = cond.show_rru(mb_rru);
-                format!("{}{} {}, {}", op, cond, rn, rm)
-            }
-            &Inst::CmpTrapRSImm16 {
-                op, rn, imm, cond, ..
-            } => {
-                let op = match op {
-                    CmpOp::CmpS32 => "cit",
-                    CmpOp::CmpS64 => "cgit",
-                    _ => unreachable!(),
-                };
-                let rn = rn.show_rru(mb_rru);
-                let cond = cond.show_rru(mb_rru);
-                format!("{}{} {}, {}", op, cond, rn, imm)
-            }
-            &Inst::CmpTrapRUImm16 {
-                op, rn, imm, cond, ..
-            } => {
-                let op = match op {
-                    CmpOp::CmpL32 => "clfit",
-                    CmpOp::CmpL64 => "clgit",
-                    _ => unreachable!(),
-                };
-                let rn = rn.show_rru(mb_rru);
-                let cond = cond.show_rru(mb_rru);
-                format!("{}{} {}, {}", op, cond, rn, imm)
-            }
-            &Inst::AtomicRmw {
-                alu_op,
-                rd,
-                rn,
-                ref mem,
-            } => {
-                let op = match alu_op {
-                    ALUOp::Add32 => "laa",
-                    ALUOp::Add64 => "laag",
-                    ALUOp::AddLogical32 => "laal",
-                    ALUOp::AddLogical64 => "laalg",
-                    ALUOp::And32 => "lan",
-                    ALUOp::And64 => "lang",
-                    ALUOp::Orr32 => "lao",
-                    ALUOp::Orr64 => "laog",
-                    ALUOp::Xor32 => "lax",
-                    ALUOp::Xor64 => "laxg",
-                    _ => unreachable!(),
-                };
-
-                let (mem_str, mem) =
-                    mem_finalize_for_show(mem, mb_rru, state, false, true, false, false);
-
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let rn = rn.show_rru(mb_rru);
-                let mem = mem.show_rru(mb_rru);
-                format!("{}{} {}, {}, {}", mem_str, op, rd, rn, mem)
-            }
-            &Inst::AtomicCas32 { rd, rn, ref mem } | &Inst::AtomicCas64 { rd, rn, ref mem } => {
-                let (opcode_rs, opcode_rsy) = match self {
-                    &Inst::AtomicCas32 { .. } => (Some("cs"), Some("csy")),
-                    &Inst::AtomicCas64 { .. } => (None, Some("csg")),
-                    _ => unreachable!(),
-                };
-
-                let (mem_str, mem) = mem_finalize_for_show(
-                    mem,
-                    mb_rru,
-                    state,
-                    opcode_rs.is_some(),
-                    opcode_rsy.is_some(),
-                    false,
-                    false,
-                );
-
-                let op = match &mem {
-                    &MemArg::BXD12 { .. } => opcode_rs,
-                    &MemArg::BXD20 { .. } => opcode_rsy,
-                    _ => unreachable!(),
-                };
-
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let rn = rn.show_rru(mb_rru);
-                let mem = mem.show_rru(mb_rru);
-                format!("{}{} {}, {}, {}", mem_str, op.unwrap(), rd, rn, mem)
-            }
-            &Inst::Fence => "bcr 14, 0".to_string(),
-            &Inst::Load32 { rd, ref mem }
-            | &Inst::Load32ZExt8 { rd, ref mem }
-            | &Inst::Load32SExt8 { rd, ref mem }
-            | &Inst::Load32ZExt16 { rd, ref mem }
-            | &Inst::Load32SExt16 { rd, ref mem }
-            | &Inst::Load64 { rd, ref mem }
-            | &Inst::Load64ZExt8 { rd, ref mem }
-            | &Inst::Load64SExt8 { rd, ref mem }
-            | &Inst::Load64ZExt16 { rd, ref mem }
-            | &Inst::Load64SExt16 { rd, ref mem }
-            | &Inst::Load64ZExt32 { rd, ref mem }
-            | &Inst::Load64SExt32 { rd, ref mem }
-            | &Inst::LoadRev16 { rd, ref mem }
-            | &Inst::LoadRev32 { rd, ref mem }
-            | &Inst::LoadRev64 { rd, ref mem }
-            | &Inst::FpuLoad32 { rd, ref mem }
-            | &Inst::FpuLoad64 { rd, ref mem } => {
-                let (opcode_rx, opcode_rxy, opcode_ril) = match self {
-                    &Inst::Load32 { .. } => (Some("l"), Some("ly"), Some("lrl")),
-                    &Inst::Load32ZExt8 { .. } => (None, Some("llc"), None),
-                    &Inst::Load32SExt8 { .. } => (None, Some("lb"), None),
-                    &Inst::Load32ZExt16 { .. } => (None, Some("llh"), Some("llhrl")),
-                    &Inst::Load32SExt16 { .. } => (Some("lh"), Some("lhy"), Some("lhrl")),
-                    &Inst::Load64 { .. } => (None, Some("lg"), Some("lgrl")),
-                    &Inst::Load64ZExt8 { .. } => (None, Some("llgc"), None),
-                    &Inst::Load64SExt8 { .. } => (None, Some("lgb"), None),
-                    &Inst::Load64ZExt16 { .. } => (None, Some("llgh"), Some("llghrl")),
-                    &Inst::Load64SExt16 { .. } => (None, Some("lgh"), Some("lghrl")),
-                    &Inst::Load64ZExt32 { .. } => (None, Some("llgf"), Some("llgfrl")),
-                    &Inst::Load64SExt32 { .. } => (None, Some("lgf"), Some("lgfrl")),
-                    &Inst::LoadRev16 { .. } => (None, Some("lrvh"), None),
-                    &Inst::LoadRev32 { .. } => (None, Some("lrv"), None),
-                    &Inst::LoadRev64 { .. } => (None, Some("lrvg"), None),
-                    &Inst::FpuLoad32 { .. } => (Some("le"), Some("ley"), None),
-                    &Inst::FpuLoad64 { .. } => (Some("ld"), Some("ldy"), None),
-                    _ => unreachable!(),
-                };
-
-                let (mem_str, mem) = mem_finalize_for_show(
-                    mem,
-                    mb_rru,
-                    state,
-                    opcode_rx.is_some(),
-                    opcode_rxy.is_some(),
-                    opcode_ril.is_some(),
-                    true,
-                );
-
-                let op = match &mem {
-                    &MemArg::BXD12 { .. } => opcode_rx,
-                    &MemArg::BXD20 { .. } => opcode_rxy,
-                    &MemArg::Label { .. } | &MemArg::Symbol { .. } => opcode_ril,
-                    _ => unreachable!(),
-                };
-
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let mem = mem.show_rru(mb_rru);
-                format!("{}{} {}, {}", mem_str, op.unwrap(), rd, mem)
-            }
-            &Inst::FpuLoadRev32 { rd, ref mem } | &Inst::FpuLoadRev64 { rd, ref mem } => {
-                let (mem_str, mem) =
-                    mem_finalize_for_show(mem, mb_rru, state, true, false, false, true);
-
-                let op = match self {
-                    &Inst::FpuLoadRev32 { .. } => "vlebrf",
-                    &Inst::FpuLoadRev64 { .. } => "vlebrg",
-                    _ => unreachable!(),
-                };
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let mem = mem.show_rru(mb_rru);
-                format!("{}{} {}, {}, 0", mem_str, op, rd, mem)
-            }
-            &Inst::Store8 { rd, ref mem }
-            | &Inst::Store16 { rd, ref mem }
-            | &Inst::Store32 { rd, ref mem }
-            | &Inst::Store64 { rd, ref mem }
-            | &Inst::StoreRev16 { rd, ref mem }
-            | &Inst::StoreRev32 { rd, ref mem }
-            | &Inst::StoreRev64 { rd, ref mem }
-            | &Inst::FpuStore32 { rd, ref mem }
-            | &Inst::FpuStore64 { rd, ref mem } => {
-                let (opcode_rx, opcode_rxy, opcode_ril) = match self {
-                    &Inst::Store8 { .. } => (Some("stc"), Some("stcy"), None),
-                    &Inst::Store16 { .. } => (Some("sth"), Some("sthy"), Some("sthrl")),
-                    &Inst::Store32 { .. } => (Some("st"), Some("sty"), Some("strl")),
-                    &Inst::Store64 { .. } => (None, Some("stg"), Some("stgrl")),
-                    &Inst::StoreRev16 { .. } => (None, Some("strvh"), None),
-                    &Inst::StoreRev32 { .. } => (None, Some("strv"), None),
-                    &Inst::StoreRev64 { .. } => (None, Some("strvg"), None),
-                    &Inst::FpuStore32 { .. } => (Some("ste"), Some("stey"), None),
-                    &Inst::FpuStore64 { .. } => (Some("std"), Some("stdy"), None),
-                    _ => unreachable!(),
-                };
-
-                let (mem_str, mem) = mem_finalize_for_show(
-                    mem,
-                    mb_rru,
-                    state,
-                    opcode_rx.is_some(),
-                    opcode_rxy.is_some(),
-                    opcode_ril.is_some(),
-                    true,
-                );
-
-                let op = match &mem {
-                    &MemArg::BXD12 { .. } => opcode_rx,
-                    &MemArg::BXD20 { .. } => opcode_rxy,
-                    &MemArg::Label { .. } | &MemArg::Symbol { .. } => opcode_ril,
-                    _ => unreachable!(),
-                };
-
-                let rd = rd.show_rru(mb_rru);
-                let mem = mem.show_rru(mb_rru);
-                format!("{}{} {}, {}", mem_str, op.unwrap(), rd, mem)
-            }
-            &Inst::StoreImm8 { imm, ref mem } => {
-                let (mem_str, mem) =
-                    mem_finalize_for_show(mem, mb_rru, state, true, true, false, false);
-                let op = match &mem {
-                    &MemArg::BXD12 { .. } => "mvi",
-                    &MemArg::BXD20 { .. } => "mviy",
-                    _ => unreachable!(),
-                };
-
-                let mem = mem.show_rru(mb_rru);
-                format!("{}{} {}, {}", mem_str, op, mem, imm)
-            }
-            &Inst::StoreImm16 { imm, ref mem }
-            | &Inst::StoreImm32SExt16 { imm, ref mem }
-            | &Inst::StoreImm64SExt16 { imm, ref mem } => {
-                let (mem_str, mem) =
-                    mem_finalize_for_show(mem, mb_rru, state, false, true, false, false);
-                let op = match self {
-                    &Inst::StoreImm16 { .. } => "mvhhi",
-                    &Inst::StoreImm32SExt16 { .. } => "mvhi",
-                    &Inst::StoreImm64SExt16 { .. } => "mvghi",
-                    _ => unreachable!(),
-                };
-
-                let mem = mem.show_rru(mb_rru);
-                format!("{}{} {}, {}", mem_str, op, mem, imm)
-            }
-            &Inst::FpuStoreRev32 { rd, ref mem } | &Inst::FpuStoreRev64 { rd, ref mem } => {
-                let (mem_str, mem) =
-                    mem_finalize_for_show(mem, mb_rru, state, true, false, false, true);
-
-                let op = match self {
-                    &Inst::FpuStoreRev32 { .. } => "vstebrf",
-                    &Inst::FpuStoreRev64 { .. } => "vstebrg",
-                    _ => unreachable!(),
-                };
-                let rd = rd.show_rru(mb_rru);
-                let mem = mem.show_rru(mb_rru);
-                format!("{}{} {}, {}, 0", mem_str, op, rd, mem)
-            }
-            &Inst::LoadMultiple64 { rt, rt2, ref mem } => {
-                let (mem_str, mem) =
-                    mem_finalize_for_show(mem, mb_rru, state, false, true, false, false);
-                let rt = rt.show_rru(mb_rru);
-                let rt2 = rt2.show_rru(mb_rru);
-                let mem = mem.show_rru(mb_rru);
-                format!("{}lmg {}, {}, {}", mem_str, rt, rt2, mem)
-            }
-            &Inst::StoreMultiple64 { rt, rt2, ref mem } => {
-                let (mem_str, mem) =
-                    mem_finalize_for_show(mem, mb_rru, state, false, true, false, false);
-                let rt = rt.show_rru(mb_rru);
-                let rt2 = rt2.show_rru(mb_rru);
-                let mem = mem.show_rru(mb_rru);
-                format!("{}stmg {}, {}, {}", mem_str, rt, rt2, mem)
-            }
-            &Inst::Mov64 { rd, rm } => {
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let rm = rm.show_rru(mb_rru);
-                format!("lgr {}, {}", rd, rm)
-            }
-            &Inst::Mov32 { rd, rm } => {
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let rm = rm.show_rru(mb_rru);
-                format!("lr {}, {}", rd, rm)
-            }
-            &Inst::Mov32Imm { rd, ref imm } => {
-                let rd = rd.to_reg().show_rru(mb_rru);
-                format!("iilf {}, {}", rd, imm)
-            }
-            &Inst::Mov32SImm16 { rd, ref imm } => {
-                let rd = rd.to_reg().show_rru(mb_rru);
-                format!("lhi {}, {}", rd, imm)
-            }
-            &Inst::Mov64SImm16 { rd, ref imm } => {
-                let rd = rd.to_reg().show_rru(mb_rru);
-                format!("lghi {}, {}", rd, imm)
-            }
-            &Inst::Mov64SImm32 { rd, ref imm } => {
-                let rd = rd.to_reg().show_rru(mb_rru);
-                format!("lgfi {}, {}", rd, imm)
-            }
-            &Inst::Mov64UImm16Shifted { rd, ref imm } => {
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let op = match imm.shift {
-                    0 => "llill",
-                    1 => "llilh",
-                    2 => "llihl",
-                    3 => "llihh",
-                    _ => unreachable!(),
-                };
-                format!("{} {}, {}", op, rd, imm.bits)
-            }
-            &Inst::Mov64UImm32Shifted { rd, ref imm } => {
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let op = match imm.shift {
-                    0 => "llilf",
-                    1 => "llihf",
-                    _ => unreachable!(),
-                };
-                format!("{} {}, {}", op, rd, imm.bits)
-            }
-            &Inst::Insert64UImm16Shifted { rd, ref imm } => {
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let op = match imm.shift {
-                    0 => "iill",
-                    1 => "iilh",
-                    2 => "iihl",
-                    3 => "iihh",
-                    _ => unreachable!(),
-                };
-                format!("{} {}, {}", op, rd, imm.bits)
-            }
-            &Inst::Insert64UImm32Shifted { rd, ref imm } => {
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let op = match imm.shift {
-                    0 => "iilf",
-                    1 => "iihf",
-                    _ => unreachable!(),
-                };
-                format!("{} {}, {}", op, rd, imm.bits)
-            }
-            &Inst::CMov32 { rd, cond, rm } => {
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let rm = rm.show_rru(mb_rru);
-                let cond = cond.show_rru(mb_rru);
-                format!("locr{} {}, {}", cond, rd, rm)
-            }
-            &Inst::CMov64 { rd, cond, rm } => {
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let rm = rm.show_rru(mb_rru);
-                let cond = cond.show_rru(mb_rru);
-                format!("locgr{} {}, {}", cond, rd, rm)
-            }
-            &Inst::CMov32SImm16 { rd, cond, ref imm } => {
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let cond = cond.show_rru(mb_rru);
-                format!("lochi{} {}, {}", cond, rd, imm)
-            }
-            &Inst::CMov64SImm16 { rd, cond, ref imm } => {
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let cond = cond.show_rru(mb_rru);
-                format!("locghi{} {}, {}", cond, rd, imm)
-            }
-            &Inst::FpuMove32 { rd, rn } => {
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let rn = rn.show_rru(mb_rru);
-                format!("ler {}, {}", rd, rn)
-            }
-            &Inst::FpuMove64 { rd, rn } => {
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let rn = rn.show_rru(mb_rru);
-                format!("ldr {}, {}", rd, rn)
-            }
-            &Inst::FpuCMov32 { rd, cond, rm } => {
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let rm = rm.show_rru(mb_rru);
-                let cond = cond.invert().show_rru(mb_rru);
-                format!("j{} 6 ; ler {}, {}", cond, rd, rm)
-            }
-            &Inst::FpuCMov64 { rd, cond, rm } => {
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let rm = rm.show_rru(mb_rru);
-                let cond = cond.invert().show_rru(mb_rru);
-                format!("j{} 6 ; ldr {}, {}", cond, rd, rm)
-            }
-            &Inst::MovToFpr { rd, rn } => {
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let rn = rn.show_rru(mb_rru);
-                format!("ldgr {}, {}", rd, rn)
-            }
-            &Inst::MovFromFpr { rd, rn } => {
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let rn = rn.show_rru(mb_rru);
-                format!("lgdr {}, {}", rd, rn)
-            }
-            &Inst::FpuRR { fpu_op, rd, rn } => {
-                let op = match fpu_op {
-                    FPUOp1::Abs32 => "lpebr",
-                    FPUOp1::Abs64 => "lpdbr",
-                    FPUOp1::Neg32 => "lcebr",
-                    FPUOp1::Neg64 => "lcdbr",
-                    FPUOp1::NegAbs32 => "lnebr",
-                    FPUOp1::NegAbs64 => "lndbr",
-                    FPUOp1::Sqrt32 => "sqebr",
-                    FPUOp1::Sqrt64 => "sqdbr",
-                    FPUOp1::Cvt32To64 => "ldebr",
-                    FPUOp1::Cvt64To32 => "ledbr",
-                };
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let rn = rn.show_rru(mb_rru);
-                format!("{} {}, {}", op, rd, rn)
-            }
-            &Inst::FpuRRR { fpu_op, rd, rm } => {
-                let op = match fpu_op {
-                    FPUOp2::Add32 => "aebr",
-                    FPUOp2::Add64 => "adbr",
-                    FPUOp2::Sub32 => "sebr",
-                    FPUOp2::Sub64 => "sdbr",
-                    FPUOp2::Mul32 => "meebr",
-                    FPUOp2::Mul64 => "mdbr",
-                    FPUOp2::Div32 => "debr",
-                    FPUOp2::Div64 => "ddbr",
-                    _ => unimplemented!(),
-                };
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let rm = rm.show_rru(mb_rru);
-                format!("{} {}, {}", op, rd, rm)
-            }
-            &Inst::FpuRRRR { fpu_op, rd, rn, rm } => {
-                let op = match fpu_op {
-                    FPUOp3::MAdd32 => "maebr",
-                    FPUOp3::MAdd64 => "madbr",
-                    FPUOp3::MSub32 => "msebr",
-                    FPUOp3::MSub64 => "msdbr",
-                };
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let rn = rn.show_rru(mb_rru);
-                let rm = rm.show_rru(mb_rru);
-                format!("{} {}, {}, {}", op, rd, rn, rm)
-            }
-            &Inst::FpuCopysign { rd, rn, rm } => {
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let rn = rn.show_rru(mb_rru);
-                let rm = rm.show_rru(mb_rru);
-                format!("cpsdr {}, {}, {}", rd, rm, rn)
-            }
-            &Inst::FpuCmp32 { rn, rm } => {
-                let rn = rn.show_rru(mb_rru);
-                let rm = rm.show_rru(mb_rru);
-                format!("cebr {}, {}", rn, rm)
-            }
-            &Inst::FpuCmp64 { rn, rm } => {
-                let rn = rn.show_rru(mb_rru);
-                let rm = rm.show_rru(mb_rru);
-                format!("cdbr {}, {}", rn, rm)
-            }
-            &Inst::LoadFpuConst32 { rd, const_data } => {
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let tmp = writable_spilltmp_reg().to_reg().show_rru(mb_rru);
-                format!(
-                    "bras {}, 8 ; data.f32 {} ; le {}, 0({})",
-                    tmp,
-                    f32::from_bits(const_data),
-                    rd,
-                    tmp
-                )
-            }
-            &Inst::LoadFpuConst64 { rd, const_data } => {
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let tmp = writable_spilltmp_reg().to_reg().show_rru(mb_rru);
-                format!(
-                    "bras {}, 12 ; data.f64 {} ; ld {}, 0({})",
-                    tmp,
-                    f64::from_bits(const_data),
-                    rd,
-                    tmp
-                )
-            }
-            &Inst::FpuToInt { op, rd, rn } => {
-                let op = match op {
-                    FpuToIntOp::F32ToI32 => "cfebra",
-                    FpuToIntOp::F32ToU32 => "clfebr",
-                    FpuToIntOp::F32ToI64 => "cgebra",
-                    FpuToIntOp::F32ToU64 => "clgebr",
-                    FpuToIntOp::F64ToI32 => "cfdbra",
-                    FpuToIntOp::F64ToU32 => "clfdbr",
-                    FpuToIntOp::F64ToI64 => "cgdbra",
-                    FpuToIntOp::F64ToU64 => "clgdbr",
-                };
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let rn = rn.show_rru(mb_rru);
-                format!("{} {}, 5, {}, 0", op, rd, rn)
-            }
-            &Inst::IntToFpu { op, rd, rn } => {
-                let op = match op {
-                    IntToFpuOp::I32ToF32 => "cefbra",
-                    IntToFpuOp::U32ToF32 => "celfbr",
-                    IntToFpuOp::I64ToF32 => "cegbra",
-                    IntToFpuOp::U64ToF32 => "celgbr",
-                    IntToFpuOp::I32ToF64 => "cdfbra",
-                    IntToFpuOp::U32ToF64 => "cdlfbr",
-                    IntToFpuOp::I64ToF64 => "cdgbra",
-                    IntToFpuOp::U64ToF64 => "cdlgbr",
-                };
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let rn = rn.show_rru(mb_rru);
-                format!("{} {}, 0, {}, 0", op, rd, rn)
-            }
-            &Inst::FpuRound { op, rd, rn } => {
-                let (op, m3) = match op {
-                    FpuRoundMode::Minus32 => ("fiebr", 7),
-                    FpuRoundMode::Minus64 => ("fidbr", 7),
-                    FpuRoundMode::Plus32 => ("fiebr", 6),
-                    FpuRoundMode::Plus64 => ("fidbr", 6),
-                    FpuRoundMode::Zero32 => ("fiebr", 5),
-                    FpuRoundMode::Zero64 => ("fidbr", 5),
-                    FpuRoundMode::Nearest32 => ("fiebr", 4),
-                    FpuRoundMode::Nearest64 => ("fidbr", 4),
-                };
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let rn = rn.show_rru(mb_rru);
-                format!("{} {}, {}, {}", op, rd, rn, m3)
-            }
-            &Inst::FpuVecRRR { fpu_op, rd, rn, rm } => {
-                let op = match fpu_op {
-                    FPUOp2::Max32 => "wfmaxsb",
-                    FPUOp2::Max64 => "wfmaxdb",
-                    FPUOp2::Min32 => "wfminsb",
-                    FPUOp2::Min64 => "wfmindb",
-                    _ => unimplemented!(),
-                };
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let rn = rn.show_rru(mb_rru);
-                let rm = rm.show_rru(mb_rru);
-                format!("{} {}, {}, {}, 1", op, rd, rn, rm)
-            }
-            &Inst::Extend {
-                rd,
-                rn,
-                signed,
-                from_bits,
-                to_bits,
-            } => {
-                let rd = rd.to_reg().show_rru(mb_rru);
-                let rn = rn.show_rru(mb_rru);
-                let op = match (signed, from_bits, to_bits) {
-                    (_, 1, 32) => "llcr",
-                    (_, 1, 64) => "llgcr",
-                    (false, 8, 32) => "llcr",
-                    (false, 8, 64) => "llgcr",
-                    (true, 8, 32) => "lbr",
-                    (true, 8, 64) => "lgbr",
-                    (false, 16, 32) => "llhr",
-                    (false, 16, 64) => "llghr",
-                    (true, 16, 32) => "lhr",
-                    (true, 16, 64) => "lghr",
-                    (false, 32, 64) => "llgfr",
-                    (true, 32, 64) => "lgfr",
-                    _ => panic!("Unsupported Extend case: {:?}", self),
-                };
-                format!("{} {}, {}", op, rd, rn)
-            }
-            &Inst::Call { link, ref info, .. } => {
-                let link = link.show_rru(mb_rru);
-                format!("brasl {}, {}", link, info.dest)
-            }
-            &Inst::CallInd { link, ref info, .. } => {
-                let link = link.show_rru(mb_rru);
-                let rn = info.rn.show_rru(mb_rru);
-                format!("basr {}, {}", link, rn)
-            }
-            &Inst::Ret { link } => {
-                let link = link.show_rru(mb_rru);
-                format!("br {}", link)
-            }
-            &Inst::EpiloguePlaceholder => "epilogue placeholder".to_string(),
-            &Inst::Jump { dest } => {
-                let dest = dest.to_string();
-                format!("jg {}", dest)
-            }
-            &Inst::IndirectBr { rn, .. } => {
-                let rn = rn.show_rru(mb_rru);
-                format!("br {}", rn)
-            }
-            &Inst::CondBr {
-                taken,
-                not_taken,
-                cond,
-            } => {
-                let taken = taken.to_string();
-                let not_taken = not_taken.to_string();
-                let cond = cond.show_rru(mb_rru);
-                format!("jg{} {} ; jg {}", cond, taken, not_taken)
-            }
-            &Inst::OneWayCondBr { target, cond } => {
-                let target = target.to_string();
-                let cond = cond.show_rru(mb_rru);
-                format!("jg{} {}", cond, target)
-            }
-            &Inst::Debugtrap => "debugtrap".to_string(),
-            &Inst::Trap { .. } => "trap".to_string(),
-            &Inst::TrapIf { cond, .. } => {
-                let cond = cond.invert().show_rru(mb_rru);
-                format!("j{} 6 ; trap", cond)
-            }
-            &Inst::JTSequence { ridx, ref targets } => {
-                let ridx = ridx.show_rru(mb_rru);
-                let rtmp = writable_spilltmp_reg().to_reg().show_rru(mb_rru);
-                // The first entry is the default target, which is not emitted
-                // into the jump table, so we skip it here.  It is only in the
-                // list so MachTerminator will see the potential target.
-                let jt_entries: String = targets
-                    .iter()
-                    .skip(1)
-                    .map(|label| format!(" {}", label.to_string()))
-                    .collect();
-                format!(
-                    concat!(
-                        "larl {}, 14 ; ",
-                        "agf {}, 0({}, {}) ; ",
-                        "br {} ; ",
-                        "jt_entries{}"
-                    ),
-                    rtmp, rtmp, rtmp, ridx, rtmp, jt_entries,
-                )
-            }
-            &Inst::LoadExtNameFar {
-                rd,
-                ref name,
-                offset,
-            } => {
-                let rd = rd.show_rru(mb_rru);
-                let tmp = writable_spilltmp_reg().to_reg().show_rru(mb_rru);
-                format!(
-                    "bras {}, 12 ; data {} + {} ; lg {}, 0({})",
-                    tmp, name, offset, rd, tmp
-                )
-            }
-            &Inst::LoadAddr { rd, ref mem } => {
-                let (mem_str, mem) =
-                    mem_finalize_for_show(mem, mb_rru, state, true, true, true, true);
-
-                let op = match &mem {
-                    &MemArg::BXD12 { .. } => "la",
-                    &MemArg::BXD20 { .. } => "lay",
-                    &MemArg::Label { .. } | &MemArg::Symbol { .. } => "larl",
-                    _ => unreachable!(),
-                };
-                let rd = rd.show_rru(mb_rru);
-                let mem = mem.show_rru(mb_rru);
-                format!("{}{} {}, {}", mem_str, op, rd, mem)
-            }
-            &Inst::Loop { ref body, cond } => {
-                let body = body
-                    .into_iter()
-                    .map(|inst| inst.show_rru(mb_rru))
-                    .collect::<Vec<_>>()
-                    .join(" ; ");
-                let cond = cond.show_rru(mb_rru);
-                format!("0: {} ; jg{} 0b ; 1:", body, cond)
-            }
-            &Inst::CondBreak { cond } => {
-                let cond = cond.show_rru(mb_rru);
-                format!("jg{} 1f", cond)
-            }
-            &Inst::VirtualSPOffsetAdj { offset } => {
-                state.virtual_sp_offset += offset;
-                format!("virtual_sp_offset_adjust {}", offset)
-            }
-            &Inst::ValueLabelMarker { label, reg } => {
-                format!("value_label {:?}, {}", label, reg.show_rru(mb_rru))
-            }
-            &Inst::Unwind { ref inst } => {
-                format!("unwind {:?}", inst)
-            }
-        }
-    }
-}
-
-//=============================================================================
-// Label fixups and jump veneers.
-
-/// Different forms of label references for different instruction formats.
-#[derive(Clone, Copy, Debug, PartialEq, Eq)]
-pub enum LabelUse {
-    /// RI-format branch.  16-bit signed offset.  PC-relative, offset is imm << 1.
-    BranchRI,
-    /// RIL-format branch.  32-bit signed offset.  PC-relative, offset is imm << 1.
-    BranchRIL,
-    /// 32-bit PC relative constant offset (from address of constant itself),
-    /// signed. Used in jump tables.
-    PCRel32,
-    /// 32-bit PC relative constant offset (from address of call instruction),
-    /// signed. Offset is imm << 1.  Used for call relocations.
-    PCRel32Dbl,
-}
-
-impl MachInstLabelUse for LabelUse {
-    /// Alignment for veneer code.
-    const ALIGN: CodeOffset = 2;
-
-    /// Maximum PC-relative range (positive), inclusive.
-    fn max_pos_range(self) -> CodeOffset {
-        match self {
-            // 16-bit signed immediate, left-shifted by 1.
-            LabelUse::BranchRI => ((1 << 15) - 1) << 1,
-            // 32-bit signed immediate, left-shifted by 1.
-            LabelUse::BranchRIL => 0xffff_fffe,
-            // 32-bit signed immediate.
-            LabelUse::PCRel32 => 0x7fff_ffff,
-            // 32-bit signed immediate, left-shifted by 1, offset by 2.
-            LabelUse::PCRel32Dbl => 0xffff_fffc,
-        }
-    }
-
-    /// Maximum PC-relative range (negative).
-    fn max_neg_range(self) -> CodeOffset {
-        match self {
-            // 16-bit signed immediate, left-shifted by 1.
-            LabelUse::BranchRI => (1 << 15) << 1,
-            // 32-bit signed immediate, left-shifted by 1.
-            // NOTE: This should be 4GB, but CodeOffset is only u32.
-            LabelUse::BranchRIL => 0xffff_ffff,
-            // 32-bit signed immediate.
-            LabelUse::PCRel32 => 0x8000_0000,
-            // 32-bit signed immediate, left-shifted by 1, offset by 2.
-            // NOTE: This should be 4GB + 2, but CodeOffset is only u32.
-            LabelUse::PCRel32Dbl => 0xffff_ffff,
-        }
-    }
-
-    /// Size of window into code needed to do the patch.
-    fn patch_size(self) -> CodeOffset {
-        match self {
-            LabelUse::BranchRI => 4,
-            LabelUse::BranchRIL => 6,
-            LabelUse::PCRel32 => 4,
-            LabelUse::PCRel32Dbl => 4,
-        }
-    }
-
-    /// Perform the patch.
-    fn patch(self, buffer: &mut [u8], use_offset: CodeOffset, label_offset: CodeOffset) {
-        let pc_rel = (label_offset as i64) - (use_offset as i64);
-        debug_assert!(pc_rel <= self.max_pos_range() as i64);
-        debug_assert!(pc_rel >= -(self.max_neg_range() as i64));
-        debug_assert!(pc_rel & 1 == 0);
-        let pc_rel_shifted = pc_rel >> 1;
-
-        match self {
-            LabelUse::BranchRI => {
-                buffer[2..4].clone_from_slice(&u16::to_be_bytes(pc_rel_shifted as u16));
-            }
-            LabelUse::BranchRIL => {
-                buffer[2..6].clone_from_slice(&u32::to_be_bytes(pc_rel_shifted as u32));
-            }
-            LabelUse::PCRel32 => {
-                let insn_word = u32::from_be_bytes([buffer[0], buffer[1], buffer[2], buffer[3]]);
-                let insn_word = insn_word.wrapping_add(pc_rel as u32);
-                buffer[0..4].clone_from_slice(&u32::to_be_bytes(insn_word));
-            }
-            LabelUse::PCRel32Dbl => {
-                let insn_word = u32::from_be_bytes([buffer[0], buffer[1], buffer[2], buffer[3]]);
-                let insn_word = insn_word.wrapping_add((pc_rel_shifted + 1) as u32);
-                buffer[0..4].clone_from_slice(&u32::to_be_bytes(insn_word));
-            }
-        }
-    }
-
-    /// Is a veneer supported for this label reference type?
-    fn supports_veneer(self) -> bool {
-        false
-    }
-
-    /// How large is the veneer, if supported?
-    fn veneer_size(self) -> CodeOffset {
-        0
-    }
-
-    /// Generate a veneer into the buffer, given that this veneer is at `veneer_offset`, and return
-    /// an offset and label-use for the veneer's use of the original label.
-    fn generate_veneer(
-        self,
-        _buffer: &mut [u8],
-        _veneer_offset: CodeOffset,
-    ) -> (CodeOffset, LabelUse) {
-        unreachable!();
-    }
-
-    fn from_reloc(reloc: Reloc, addend: Addend) -> Option<Self> {
-        match (reloc, addend) {
-            (Reloc::S390xPCRel32Dbl, 2) => Some(LabelUse::PCRel32Dbl),
-            _ => None,
-        }
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/inst/regs.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/inst/regs.rs
deleted file mode 100644
index 3ebba43bd..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/inst/regs.rs
+++ /dev/null
@@ -1,168 +0,0 @@
-//! S390x ISA definitions: registers.
-
-use crate::settings;
-use regalloc::{RealRegUniverse, Reg, RegClass, RegClassInfo, Writable, NUM_REG_CLASSES};
-
-//=============================================================================
-// Registers, the Universe thereof, and printing
-
-#[rustfmt::skip]
-const GPR_INDICES: [u8; 16] = [
-    // r0 and r1 reserved
-    30, 31,
-    // r2 - r5 call-clobbered
-    16, 17, 18, 19,
-    // r6 - r14 call-saved (order reversed)
-    28, 27, 26, 25, 24, 23, 22, 21, 20,
-    // r15 (SP)
-    29,
-];
-
-#[rustfmt::skip]
-const FPR_INDICES: [u8; 16] = [
-    // f0 - f7 as pairs
-    0, 4, 1, 5, 2, 6, 3, 7,
-    // f8 - f15 as pairs
-    8, 12, 9, 13, 10, 14, 11, 15,
-];
-
-/// Get a reference to a GPR (integer register).
-pub fn gpr(num: u8) -> Reg {
-    assert!(num < 16);
-    Reg::new_real(
-        RegClass::I64,
-        /* enc = */ num,
-        /* index = */ GPR_INDICES[num as usize],
-    )
-}
-
-/// Get a writable reference to a GPR.
-pub fn writable_gpr(num: u8) -> Writable<Reg> {
-    Writable::from_reg(gpr(num))
-}
-
-/// Get a reference to a FPR (floating-point register).
-pub fn fpr(num: u8) -> Reg {
-    assert!(num < 16);
-    Reg::new_real(
-        RegClass::F64,
-        /* enc = */ num,
-        /* index = */ FPR_INDICES[num as usize],
-    )
-}
-
-/// Get a writable reference to a V-register.
-pub fn writable_fpr(num: u8) -> Writable<Reg> {
-    Writable::from_reg(fpr(num))
-}
-
-/// Get a reference to the stack-pointer register.
-pub fn stack_reg() -> Reg {
-    gpr(15)
-}
-
-/// Get a writable reference to the stack-pointer register.
-pub fn writable_stack_reg() -> Writable<Reg> {
-    Writable::from_reg(stack_reg())
-}
-
-/// Get a reference to the first temporary, sometimes "spill temporary", register. This register is
-/// used to compute the address of a spill slot when a direct offset addressing mode from FP is not
-/// sufficient (+/- 2^11 words). We exclude this register from regalloc and reserve it for this
-/// purpose for simplicity; otherwise we need a multi-stage analysis where we first determine how
-/// many spill slots we have, then perhaps remove the reg from the pool and recompute regalloc.
-///
-/// We use r1 for this because it's a scratch register but is slightly special (used for linker
-/// veneers). We're free to use it as long as we don't expect it to live through call instructions.
-pub fn spilltmp_reg() -> Reg {
-    gpr(1)
-}
-
-/// Get a writable reference to the spilltmp reg.
-pub fn writable_spilltmp_reg() -> Writable<Reg> {
-    Writable::from_reg(spilltmp_reg())
-}
-
-pub fn zero_reg() -> Reg {
-    gpr(0)
-}
-
-/// Create the register universe for AArch64.
-pub fn create_reg_universe(_flags: &settings::Flags) -> RealRegUniverse {
-    let mut regs = vec![];
-    let mut allocable_by_class = [None; NUM_REG_CLASSES];
-
-    // Numbering Scheme: we put FPRs first, then GPRs. The GPRs exclude several registers:
-    // r0 (we cannot use this for addressing // FIXME regalloc)
-    // r1 (spilltmp)
-    // r15 (stack pointer)
-
-    // FPRs.
-    let mut base = regs.len();
-    regs.push((fpr(0).to_real_reg(), "%f0".into()));
-    regs.push((fpr(2).to_real_reg(), "%f2".into()));
-    regs.push((fpr(4).to_real_reg(), "%f4".into()));
-    regs.push((fpr(6).to_real_reg(), "%f6".into()));
-    regs.push((fpr(1).to_real_reg(), "%f1".into()));
-    regs.push((fpr(3).to_real_reg(), "%f3".into()));
-    regs.push((fpr(5).to_real_reg(), "%f5".into()));
-    regs.push((fpr(7).to_real_reg(), "%f7".into()));
-    regs.push((fpr(8).to_real_reg(), "%f8".into()));
-    regs.push((fpr(10).to_real_reg(), "%f10".into()));
-    regs.push((fpr(12).to_real_reg(), "%f12".into()));
-    regs.push((fpr(14).to_real_reg(), "%f14".into()));
-    regs.push((fpr(9).to_real_reg(), "%f9".into()));
-    regs.push((fpr(11).to_real_reg(), "%f11".into()));
-    regs.push((fpr(13).to_real_reg(), "%f13".into()));
-    regs.push((fpr(15).to_real_reg(), "%f15".into()));
-
-    allocable_by_class[RegClass::F64.rc_to_usize()] = Some(RegClassInfo {
-        first: base,
-        last: regs.len() - 1,
-        suggested_scratch: Some(fpr(1).get_index()),
-    });
-
-    // Caller-saved GPRs in the SystemV s390x ABI.
-    base = regs.len();
-    regs.push((gpr(2).to_real_reg(), "%r2".into()));
-    regs.push((gpr(3).to_real_reg(), "%r3".into()));
-    regs.push((gpr(4).to_real_reg(), "%r4".into()));
-    regs.push((gpr(5).to_real_reg(), "%r5".into()));
-
-    // Callee-saved GPRs in the SystemV s390x ABI.
-    // We start from r14 downwards in an attempt to allow the
-    // prolog to use as short a STMG as possible.
-    regs.push((gpr(14).to_real_reg(), "%r14".into()));
-    regs.push((gpr(13).to_real_reg(), "%r13".into()));
-    regs.push((gpr(12).to_real_reg(), "%r12".into()));
-    regs.push((gpr(11).to_real_reg(), "%r11".into()));
-    regs.push((gpr(10).to_real_reg(), "%r10".into()));
-    regs.push((gpr(9).to_real_reg(), "%r9".into()));
-    regs.push((gpr(8).to_real_reg(), "%r8".into()));
-    regs.push((gpr(7).to_real_reg(), "%r7".into()));
-    regs.push((gpr(6).to_real_reg(), "%r6".into()));
-
-    allocable_by_class[RegClass::I64.rc_to_usize()] = Some(RegClassInfo {
-        first: base,
-        last: regs.len() - 1,
-        suggested_scratch: Some(gpr(13).get_index()),
-    });
-
-    // Other regs, not available to the allocator.
-    let allocable = regs.len();
-    regs.push((gpr(15).to_real_reg(), "%r15".into()));
-    regs.push((gpr(0).to_real_reg(), "%r0".into()));
-    regs.push((gpr(1).to_real_reg(), "%r1".into()));
-
-    // Assert sanity: the indices in the register structs must match their
-    // actual indices in the array.
-    for (i, reg) in regs.iter().enumerate() {
-        assert_eq!(i, reg.0.get_index());
-    }
-
-    RealRegUniverse {
-        regs,
-        allocable,
-        allocable_by_class,
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/inst/unwind.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/inst/unwind.rs
deleted file mode 100644
index 1e2bb904d..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/inst/unwind.rs
+++ /dev/null
@@ -1,2 +0,0 @@
-#[cfg(feature = "unwind")]
-pub(crate) mod systemv;
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/inst/unwind/systemv.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/inst/unwind/systemv.rs
deleted file mode 100644
index a970c59c6..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/inst/unwind/systemv.rs
+++ /dev/null
@@ -1,199 +0,0 @@
-//! Unwind information for System V ABI (s390x).
-
-use crate::isa::unwind::systemv::RegisterMappingError;
-use gimli::{write::CommonInformationEntry, Encoding, Format, Register};
-use regalloc::{Reg, RegClass};
-
-/// Creates a new s390x common information entry (CIE).
-pub fn create_cie() -> CommonInformationEntry {
-    use gimli::write::CallFrameInstruction;
-
-    let mut entry = CommonInformationEntry::new(
-        Encoding {
-            address_size: 8,
-            format: Format::Dwarf32,
-            version: 1,
-        },
-        1,            // Code alignment factor
-        -8,           // Data alignment factor
-        Register(14), // Return address column - register %r14
-    );
-
-    // Every frame will start with the call frame address (CFA) at %r15 + 160.
-    entry.add_instruction(CallFrameInstruction::Cfa(Register(15), 160));
-
-    entry
-}
-
-/// Map Cranelift registers to their corresponding Gimli registers.
-pub fn map_reg(reg: Reg) -> Result<Register, RegisterMappingError> {
-    const GPR_MAP: [gimli::Register; 16] = [
-        Register(0),
-        Register(1),
-        Register(2),
-        Register(3),
-        Register(4),
-        Register(5),
-        Register(6),
-        Register(7),
-        Register(8),
-        Register(9),
-        Register(10),
-        Register(11),
-        Register(12),
-        Register(13),
-        Register(14),
-        Register(15),
-    ];
-    const FPR_MAP: [gimli::Register; 16] = [
-        Register(16),
-        Register(20),
-        Register(17),
-        Register(21),
-        Register(18),
-        Register(22),
-        Register(19),
-        Register(23),
-        Register(24),
-        Register(28),
-        Register(25),
-        Register(29),
-        Register(26),
-        Register(30),
-        Register(27),
-        Register(31),
-    ];
-
-    match reg.get_class() {
-        RegClass::I64 => Ok(GPR_MAP[reg.get_hw_encoding() as usize]),
-        RegClass::F64 => Ok(FPR_MAP[reg.get_hw_encoding() as usize]),
-        _ => Err(RegisterMappingError::UnsupportedRegisterBank("class?")),
-    }
-}
-
-pub(crate) struct RegisterMapper;
-
-impl crate::isa::unwind::systemv::RegisterMapper<Reg> for RegisterMapper {
-    fn map(&self, reg: Reg) -> Result<u16, RegisterMappingError> {
-        Ok(map_reg(reg)?.0)
-    }
-    fn sp(&self) -> u16 {
-        Register(15).0
-    }
-}
-
-#[cfg(test)]
-mod tests {
-    use crate::cursor::{Cursor, FuncCursor};
-    use crate::ir::{
-        types, AbiParam, ExternalName, Function, InstBuilder, Signature, StackSlotData,
-        StackSlotKind,
-    };
-    use crate::isa::{lookup, CallConv};
-    use crate::settings::{builder, Flags};
-    use crate::Context;
-    use gimli::write::Address;
-    use std::str::FromStr;
-    use target_lexicon::triple;
-
-    #[test]
-    fn test_simple_func() {
-        let isa = lookup(triple!("s390x"))
-            .expect("expect s390x ISA")
-            .finish(Flags::new(builder()))
-            .expect("Creating compiler backend");
-
-        let mut context = Context::for_function(create_function(
-            CallConv::SystemV,
-            Some(StackSlotData::new(StackSlotKind::ExplicitSlot, 64)),
-        ));
-
-        context.compile(&*isa).expect("expected compilation");
-
-        let fde = match context
-            .create_unwind_info(isa.as_ref())
-            .expect("can create unwind info")
-        {
-            Some(crate::isa::unwind::UnwindInfo::SystemV(info)) => {
-                info.to_fde(Address::Constant(1234))
-            }
-            _ => panic!("expected unwind information"),
-        };
-
-        assert_eq!(format!("{:?}", fde), "FrameDescriptionEntry { address: Constant(1234), length: 10, lsda: None, instructions: [(4, CfaOffset(224))] }");
-    }
-
-    fn create_function(call_conv: CallConv, stack_slot: Option<StackSlotData>) -> Function {
-        let mut func =
-            Function::with_name_signature(ExternalName::user(0, 0), Signature::new(call_conv));
-
-        let block0 = func.dfg.make_block();
-        let mut pos = FuncCursor::new(&mut func);
-        pos.insert_block(block0);
-        pos.ins().return_(&[]);
-
-        if let Some(stack_slot) = stack_slot {
-            func.stack_slots.push(stack_slot);
-        }
-
-        func
-    }
-
-    #[test]
-    fn test_multi_return_func() {
-        let isa = lookup(triple!("s390x"))
-            .expect("expect s390x ISA")
-            .finish(Flags::new(builder()))
-            .expect("Creating compiler backend");
-
-        let mut context = Context::for_function(create_multi_return_function(
-            CallConv::SystemV,
-            Some(StackSlotData::new(StackSlotKind::ExplicitSlot, 64)),
-        ));
-
-        context.compile(&*isa).expect("expected compilation");
-
-        let fde = match context
-            .create_unwind_info(isa.as_ref())
-            .expect("can create unwind info")
-        {
-            Some(crate::isa::unwind::UnwindInfo::SystemV(info)) => {
-                info.to_fde(Address::Constant(4321))
-            }
-            _ => panic!("expected unwind information"),
-        };
-
-        assert_eq!(format!("{:?}", fde), "FrameDescriptionEntry { address: Constant(4321), length: 26, lsda: None, instructions: [(4, CfaOffset(224))] }");
-    }
-
-    fn create_multi_return_function(
-        call_conv: CallConv,
-        stack_slot: Option<StackSlotData>,
-    ) -> Function {
-        let mut sig = Signature::new(call_conv);
-        sig.params.push(AbiParam::new(types::I32));
-        let mut func = Function::with_name_signature(ExternalName::user(0, 0), sig);
-
-        let block0 = func.dfg.make_block();
-        let v0 = func.dfg.append_block_param(block0, types::I32);
-        let block1 = func.dfg.make_block();
-        let block2 = func.dfg.make_block();
-
-        let mut pos = FuncCursor::new(&mut func);
-        pos.insert_block(block0);
-        pos.ins().brnz(v0, block2, &[]);
-        pos.ins().jump(block1, &[]);
-
-        pos.insert_block(block1);
-        pos.ins().return_(&[]);
-
-        pos.insert_block(block2);
-        pos.ins().return_(&[]);
-
-        if let Some(stack_slot) = stack_slot {
-            func.stack_slots.push(stack_slot);
-        }
-
-        func
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/lower.isle b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/lower.isle
deleted file mode 100644
index d60f1e4e6..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/lower.isle
+++ /dev/null
@@ -1,2210 +0,0 @@
-;; s390x instruction selection and CLIF-to-MachInst lowering.
-
-;; The main lowering constructor term: takes a clif `Inst` and returns the
-;; register(s) within which the lowered instruction's result values live.
-(decl lower (Inst) InstOutput)
-
-;; A variant of the main lowering constructor term, used for branches.
-;; The only difference is that it gets an extra argument holding a vector
-;; of branch targets to be used.
-(decl lower_branch (Inst VecMachLabel) InstOutput)
-
-
-;;;; Rules for `iconst` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type ty (iconst (u64_from_imm64 n))))
-      (imm ty n))
-
-
-;;;; Rules for `bconst` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type ty (bconst $false)))
-      (imm ty 0))
-(rule (lower (has_type ty (bconst $true)))
-      (imm ty 1))
-
-
-;;;; Rules for `f32const` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (f32const (u64_from_ieee32 x)))
-      (imm $F32 x))
-
-
-;;;; Rules for `f64const` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (f64const (u64_from_ieee64 x)))
-      (imm $F64 x))
-
-
-;;;; Rules for `null` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type ty (null)))
-      (imm ty 0))
-
-
-;;;; Rules for `nop` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (nop))
-      (invalid_reg))
-
-
-;;;; Rules for `copy` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (copy x))
-      x)
-
-
-;;;; Rules for `iadd` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Add two registers.
-(rule (lower (has_type (fits_in_64 ty) (iadd x y)))
-      (add_reg ty x y))
-
-;; Add a register and a sign-extended register.
-(rule (lower (has_type (fits_in_64 ty) (iadd x (sext32_value y))))
-      (add_reg_sext32 ty x y))
-(rule (lower (has_type (fits_in_64 ty) (iadd (sext32_value x) y)))
-      (add_reg_sext32 ty y x))
-
-;; Add a register and an immediate.
-(rule (lower (has_type (fits_in_64 ty) (iadd x (i16_from_value y))))
-      (add_simm16 ty x y))
-(rule (lower (has_type (fits_in_64 ty) (iadd (i16_from_value x) y)))
-      (add_simm16 ty y x))
-(rule (lower (has_type (fits_in_64 ty) (iadd x (i32_from_value y))))
-      (add_simm32 ty x y))
-(rule (lower (has_type (fits_in_64 ty) (iadd (i32_from_value x) y)))
-      (add_simm32 ty y x))
-
-;; Add a register and memory (32/64-bit types).
-(rule (lower (has_type (fits_in_64 ty) (iadd x (sinkable_load_32_64 y))))
-      (add_mem ty x (sink_load y)))
-(rule (lower (has_type (fits_in_64 ty) (iadd (sinkable_load_32_64 x) y)))
-      (add_mem ty y (sink_load x)))
-
-;; Add a register and memory (16-bit types).
-(rule (lower (has_type (fits_in_64 ty) (iadd x (sinkable_load_16 y))))
-      (add_mem_sext16 ty x (sink_load y)))
-(rule (lower (has_type (fits_in_64 ty) (iadd (sinkable_load_16 x) y)))
-      (add_mem_sext16 ty y (sink_load x)))
-
-;; Add a register and sign-extended memory.
-(rule (lower (has_type (fits_in_64 ty) (iadd x (sinkable_sload16 y))))
-      (add_mem_sext16 ty x (sink_sload16 y)))
-(rule (lower (has_type (fits_in_64 ty) (iadd (sinkable_sload16 x) y)))
-      (add_mem_sext16 ty y (sink_sload16 x)))
-(rule (lower (has_type (fits_in_64 ty) (iadd x (sinkable_sload32 y))))
-      (add_mem_sext32 ty x (sink_sload32 y)))
-(rule (lower (has_type (fits_in_64 ty) (iadd (sinkable_sload32 x) y)))
-      (add_mem_sext32 ty y (sink_sload32 x)))
-
-
-;;;; Rules for `isub` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Sub two registers.
-(rule (lower (has_type (fits_in_64 ty) (isub x y)))
-      (sub_reg ty x y))
-
-;; Sub a register and a sign-extended register.
-(rule (lower (has_type (fits_in_64 ty) (isub x (sext32_value y))))
-      (sub_reg_sext32 ty x y))
-
-;; Sub a register and an immediate (using add of the negated value).
-(rule (lower (has_type (fits_in_64 ty) (isub x (i16_from_negated_value y))))
-      (add_simm16 ty x y))
-(rule (lower (has_type (fits_in_64 ty) (isub x (i32_from_negated_value y))))
-      (add_simm32 ty x y))
-
-;; Sub a register and memory (32/64-bit types).
-(rule (lower (has_type (fits_in_64 ty) (isub x (sinkable_load_32_64 y))))
-      (sub_mem ty x (sink_load y)))
-
-;; Sub a register and memory (16-bit types).
-(rule (lower (has_type (fits_in_64 ty) (isub x (sinkable_load_16 y))))
-      (sub_mem_sext16 ty x (sink_load y)))
-
-;; Sub a register and sign-extended memory.
-(rule (lower (has_type (fits_in_64 ty) (isub x (sinkable_sload16 y))))
-      (sub_mem_sext16 ty x (sink_sload16 y)))
-(rule (lower (has_type (fits_in_64 ty) (isub x (sinkable_sload32 y))))
-      (sub_mem_sext32 ty x (sink_sload32 y)))
-
-
-;;;; Rules for `iabs` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Absolute value of a register.
-;; For types smaller than 32-bit, the input value must be sign-extended.
-(rule (lower (has_type (fits_in_64 ty) (iabs x)))
-      (abs_reg (ty_ext32 ty) (put_in_reg_sext32 x)))
-
-;; Absolute value of a sign-extended register.
-(rule (lower (has_type (fits_in_64 ty) (iabs (sext32_value x))))
-      (abs_reg_sext32 ty x))
-
-
-;;;; Rules for `iadd_ifcout` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; N.B.: the second output of `iadd_ifcout` is meant to be the `iflags` value
-;; containing the carry result, but we do not support the `iflags` mechanism.
-;; However, the only actual use case is where `iadd_ifcout` feeds into `trapif`,
-;; which is implemented by explicitly matching on the flags producer.  So we can
-;; get away with just using an invalid second output, and the reg-renaming code
-;; does the right thing, for now.
-(decl output_ifcout (Reg) InstOutput)
-(rule (output_ifcout reg)
-      (output_pair reg (value_regs_invalid)))
-
-;; Add two registers.
-(rule (lower (has_type (fits_in_64 ty) (iadd_ifcout x y)))
-      (output_ifcout (add_logical_reg ty x y)))
-
-;; Add a register and a zero-extended register.
-(rule (lower (has_type (fits_in_64 ty) (iadd_ifcout x (zext32_value y))))
-      (output_ifcout (add_logical_reg_zext32 ty x y)))
-(rule (lower (has_type (fits_in_64 ty) (iadd_ifcout (zext32_value x) y)))
-      (output_ifcout (add_logical_reg_zext32 ty y x)))
-
-;; Add a register and an immediate.
-(rule (lower (has_type (fits_in_64 ty) (iadd_ifcout x (u32_from_value y))))
-      (output_ifcout (add_logical_zimm32 ty x y)))
-(rule (lower (has_type (fits_in_64 ty) (iadd_ifcout (u32_from_value x) y)))
-      (output_ifcout (add_logical_zimm32 ty y x)))
-
-;; Add a register and memory (32/64-bit types).
-(rule (lower (has_type (fits_in_64 ty) (iadd_ifcout x (sinkable_load_32_64 y))))
-      (output_ifcout (add_logical_mem ty x (sink_load y))))
-(rule (lower (has_type (fits_in_64 ty) (iadd_ifcout (sinkable_load_32_64 x) y)))
-      (output_ifcout (add_logical_mem ty y (sink_load x))))
-
-;; Add a register and zero-extended memory.
-(rule (lower (has_type (fits_in_64 ty) (iadd_ifcout x (sinkable_uload32 y))))
-      (output_ifcout (add_logical_mem_zext32 ty x (sink_uload32 y))))
-(rule (lower (has_type (fits_in_64 ty) (iadd_ifcout (sinkable_uload32 x) y)))
-      (output_ifcout (add_logical_mem_zext32 ty y (sink_uload32 x))))
-
-
-;;;; Rules for `ineg` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Negate a register.
-(rule (lower (has_type (fits_in_64 ty) (ineg x)))
-      (neg_reg ty x))
-
-;; Negate a sign-extended register.
-(rule (lower (has_type (fits_in_64 ty) (ineg (sext32_value x))))
-      (neg_reg_sext32 ty x))
-
-
-;;;; Rules for `imul` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Multiply two registers.
-(rule (lower (has_type (fits_in_64 ty) (imul x y)))
-      (mul_reg ty x y))
-
-;; Multiply a register and a sign-extended register.
-(rule (lower (has_type (fits_in_64 ty) (imul x (sext32_value y))))
-      (mul_reg_sext32 ty x y))
-(rule (lower (has_type (fits_in_64 ty) (imul (sext32_value x) y)))
-      (mul_reg_sext32 ty y x))
-
-;; Multiply a register and an immediate.
-(rule (lower (has_type (fits_in_64 ty) (imul x (i16_from_value y))))
-      (mul_simm16 ty x y))
-(rule (lower (has_type (fits_in_64 ty) (imul (i16_from_value x) y)))
-      (mul_simm16 ty y x))
-(rule (lower (has_type (fits_in_64 ty) (imul x (i32_from_value y))))
-      (mul_simm32 ty x y))
-(rule (lower (has_type (fits_in_64 ty) (imul (i32_from_value x) y)))
-      (mul_simm32 ty y x))
-
-;; Multiply a register and memory (32/64-bit types).
-(rule (lower (has_type (fits_in_64 ty) (imul x (sinkable_load_32_64 y))))
-      (mul_mem ty x (sink_load y)))
-(rule (lower (has_type (fits_in_64 ty) (imul (sinkable_load_32_64 x) y)))
-      (mul_mem ty y (sink_load x)))
-
-;; Multiply a register and memory (16-bit types).
-(rule (lower (has_type (fits_in_64 ty) (imul x (sinkable_load_16 y))))
-      (mul_mem_sext16 ty x (sink_load y)))
-(rule (lower (has_type (fits_in_64 ty) (imul (sinkable_load_16 x) y)))
-      (mul_mem_sext16 ty y (sink_load x)))
-
-;; Multiply a register and sign-extended memory.
-(rule (lower (has_type (fits_in_64 ty) (imul x (sinkable_sload16 y))))
-      (mul_mem_sext16 ty x (sink_sload16 y)))
-(rule (lower (has_type (fits_in_64 ty) (imul (sinkable_sload16 x) y)))
-      (mul_mem_sext16 ty y (sink_sload16 x)))
-(rule (lower (has_type (fits_in_64 ty) (imul x (sinkable_sload32 y))))
-      (mul_mem_sext32 ty x (sink_sload32 y)))
-(rule (lower (has_type (fits_in_64 ty) (imul (sinkable_sload32 x) y)))
-      (mul_mem_sext32 ty y (sink_sload32 x)))
-
-
-;;;; Rules for `umulhi` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Multiply high part unsigned, 8-bit or 16-bit types.  (Uses 32-bit multiply.)
-(rule (lower (has_type (ty_8_or_16 ty) (umulhi x y)))
-      (let ((ext_reg_x Reg (put_in_reg_zext32 x))
-            (ext_reg_y Reg (put_in_reg_zext32 y))
-            (ext_mul Reg (mul_reg $I32 ext_reg_x ext_reg_y)))
-        (lshr_imm $I32 ext_mul (ty_bits ty))))
-
-;; Multiply high part unsigned, 32-bit types.  (Uses 64-bit multiply.)
-(rule (lower (has_type $I32 (umulhi x y)))
-      (let ((ext_reg_x Reg (put_in_reg_zext64 x))
-            (ext_reg_y Reg (put_in_reg_zext64 y))
-            (ext_mul Reg (mul_reg $I64 ext_reg_x ext_reg_y)))
-        (lshr_imm $I64 ext_mul 32)))
-
-;; Multiply high part unsigned, 64-bit types.  (Uses umul_wide.)
-(rule (lower (has_type $I64 (umulhi x y)))
-      (let ((pair RegPair (umul_wide x y)))
-        (copy_reg $I64 (regpair_hi pair))))
-
-
-;;;; Rules for `smulhi` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Multiply high part signed, 8-bit or 16-bit types.  (Uses 32-bit multiply.)
-(rule (lower (has_type (ty_8_or_16 ty) (smulhi x y)))
-      (let ((ext_reg_x Reg (put_in_reg_sext32 x))
-            (ext_reg_y Reg (put_in_reg_sext32 y))
-            (ext_mul Reg (mul_reg $I32 ext_reg_x ext_reg_y)))
-        (ashr_imm $I32 ext_mul (ty_bits ty))))
-
-;; Multiply high part signed, 32-bit types.  (Uses 64-bit multiply.)
-(rule (lower (has_type $I32 (smulhi x y)))
-      (let ((ext_reg_x Reg (put_in_reg_sext64 x))
-            (ext_reg_y Reg (put_in_reg_sext64 y))
-            (ext_mul Reg (mul_reg $I64 ext_reg_x ext_reg_y)))
-        (ashr_imm $I64 ext_mul 32)))
-
-;; Multiply high part signed, 64-bit types.  (Uses smul_wide.)
-(rule (lower (has_type $I64 (smulhi x y)))
-      (let ((pair RegPair (smul_wide x y)))
-        (copy_reg $I64 (regpair_hi pair))))
-
-
-;;;; Rules for `udiv` and `urem` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Divide two registers.  The architecture provides combined udiv / urem
-;; instructions with the following combination of data types:
-;;
-;;  - 64-bit dividend (split across a 2x32-bit register pair),
-;;    32-bit divisor (in a single input register)
-;;    32-bit quotient & remainder (in a 2x32-bit register pair)
-;;
-;;  - 128-bit dividend (split across a 2x64-bit register pair),
-;;    64-bit divisor (in a single input register)
-;;    64-bit quotient & remainder (in a 2x64-bit register pair)
-;;
-;; We use the first variant for 32-bit and smaller input types,
-;; and the second variant for 64-bit input types.
-
-;; Implement `udiv`.
-(rule (lower (has_type (fits_in_64 ty) (udiv x y)))
-      (let (;; Look at the divisor to determine whether we need to generate
-            ;; an explicit division-by zero check.
-            (DZcheck bool (zero_divisor_check_needed y))
-            ;; Load up the dividend, by loading the input (possibly zero-
-            ;; extended) input into the low half of the register pair,
-            ;; and setting the high half to zero.
-            (ext_x RegPair (put_in_regpair_lo_zext32 x
-                             (imm_regpair_hi (ty_ext32 ty) 0 (uninitialized_regpair))))
-            ;; Load up the divisor, zero-extended if necessary.
-            (ext_y Reg (put_in_reg_zext32 y))
-            (ext_ty Type (ty_ext32 ty))
-            ;; Now actually perform the division-by zero check if necessary.
-            ;; This cannot be done earlier than here, because the check
-            ;; requires an already extended divisor value.
-            (_ Reg (maybe_trap_if_zero_divisor DZcheck ext_ty ext_y))
-            ;; Emit the actual divide instruction.
-            (pair RegPair (udivmod ext_ty ext_x ext_y)))
-        ;; The quotient can be found in the low half of the result.
-        (copy_reg ty (regpair_lo pair))))
-
-;; Implement `urem`.  Same as `udiv`, but finds the remainder in
-;; the high half of the result register pair instead.
-(rule (lower (has_type (fits_in_64 ty) (urem x y)))
-      (let ((DZcheck bool (zero_divisor_check_needed y))
-            (ext_x RegPair (put_in_regpair_lo_zext32 x
-                             (imm_regpair_hi ty 0 (uninitialized_regpair))))
-            (ext_y Reg (put_in_reg_zext32 y))
-            (ext_ty Type (ty_ext32 ty))
-            (_ Reg (maybe_trap_if_zero_divisor DZcheck ext_ty ext_y))
-            (pair RegPair (udivmod ext_ty ext_x ext_y)))
-        (copy_reg ty (regpair_hi pair))))
-
-;; Determine whether we need to perform a divide-by-zero-check.
-;;
-;; If the `avoid_div_traps` flag is false, we never need to perform
-;; that check; we can rely on the divide instruction itself to trap.
-;;
-;; If the `avoid_div_traps` flag is true, we perform the check explicitly.
-;; This still can be omittted if the divisor is a non-zero immediate.
-(decl zero_divisor_check_needed (Value) bool)
-(rule (zero_divisor_check_needed (i64_from_value (i64_nonzero _))) $false)
-(rule (zero_divisor_check_needed (value_type (allow_div_traps))) $false)
-(rule (zero_divisor_check_needed _) $true)
-
-;; Perform the divide-by-zero check if required.
-;; This is simply a compare-and-trap of the (extended) divisor against 0.
-(decl maybe_trap_if_zero_divisor (bool Type Reg) Reg)
-(rule (maybe_trap_if_zero_divisor $false _ _) (invalid_reg))
-(rule (maybe_trap_if_zero_divisor $true ext_ty reg)
-      (icmps_simm16_and_trap ext_ty reg 0
-                             (intcc_as_cond (IntCC.Equal))
-                             (trap_code_division_by_zero)))
-
-
-;;;; Rules for `sdiv` and `srem` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Divide two registers.  The architecture provides combined sdiv / srem
-;; instructions with the following combination of data types:
-;;
-;;  - 64-bit dividend (in the low half of a 2x64-bit register pair),
-;;    32-bit divisor (in a single input register)
-;;    64-bit quotient & remainder (in a 2x64-bit register pair)
-;;
-;;  - 64-bit dividend (in the low half of a 2x64-bit register pair),
-;;    64-bit divisor (in a single input register)
-;;    64-bit quotient & remainder (in a 2x64-bit register pair)
-;;
-;; We use the first variant for 32-bit and smaller input types,
-;; and the second variant for 64-bit input types.
-
-;; Implement `sdiv`.
-(rule (lower (has_type (fits_in_64 ty) (sdiv x y)))
-      (let (;; Look at the divisor to determine whether we need to generate
-            ;; explicit division-by-zero and/or integer-overflow checks.
-            (DZcheck bool (zero_divisor_check_needed y))
-            (OFcheck bool (div_overflow_check_needed y))
-            ;; Load up the dividend (sign-extended to 64-bit) into the low
-            ;; half of a register pair (the high half remains uninitialized).
-            (ext_x RegPair (put_in_regpair_lo_sext64 x (uninitialized_regpair)))
-            ;; Load up the divisor (sign-extended if necessary).
-            (ext_y Reg (put_in_reg_sext32 y))
-            (ext_ty Type (ty_ext32 ty))
-            ;; Perform division-by-zero check (same as for `udiv`).
-            (_1 Reg (maybe_trap_if_zero_divisor DZcheck ext_ty ext_y))
-            ;; Perform integer-overflow check if necessary.
-            (_2 Reg (maybe_trap_if_sdiv_overflow OFcheck ext_ty ty ext_x ext_y))
-            ;; Emit the actual divide instruction.
-            (pair RegPair (sdivmod ext_ty ext_x ext_y)))
-        ;; The quotient can be found in the low half of the result.
-        (copy_reg ty (regpair_lo pair))))
-
-;; Implement `srem`.  Same as `sdiv`, but finds the remainder in
-;; the high half of the result register pair instead.  Also, handle
-;; the integer overflow case differently, see below.
-(rule (lower (has_type (fits_in_64 ty) (srem x y)))
-      (let ((DZcheck bool (zero_divisor_check_needed y))
-            (OFcheck bool (div_overflow_check_needed y))
-            (ext_x RegPair (put_in_regpair_lo_sext64 x (uninitialized_regpair)))
-            (ext_y Reg (put_in_reg_sext32 y))
-            (ext_ty Type (ty_ext32 ty))
-            (_ Reg (maybe_trap_if_zero_divisor DZcheck ext_ty ext_y))
-            (checked_x RegPair (maybe_avoid_srem_overflow OFcheck ext_ty ext_x ext_y))
-            (pair RegPair (sdivmod ext_ty checked_x ext_y)))
-        (copy_reg ty (regpair_hi pair))))
-
-;; Determine whether we need to perform an integer-overflow check.
-;;
-;; We never rely on the divide instruction itself to trap; while that trap
-;; would indeed happen, we have no way of signalling two different trap
-;; conditions from the same instruction.  By explicity checking for the
-;; integer-overflow case ahead of time, any hardware trap in the divide
-;; instruction is guaranteed to indicate divison-by-zero.
-;;
-;; In addition, for types smaller than 64 bits we would have to perform
-;; the check explicitly anyway, since the instruction provides a 64-bit
-;; quotient and only traps if *that* overflows.
-;;
-;; However, the only case where integer overflow can occur is if the
-;; minimum (signed) integer value is divided by -1, so if the divisor
-;; is any immediate different from -1, the check can be omitted.
-(decl div_overflow_check_needed (Value) bool)
-(rule (div_overflow_check_needed (i64_from_value (i64_not_neg1 _))) $false)
-(rule (div_overflow_check_needed _) $true)
-
-;; Perform the integer-overflow check if necessary.   This implements:
-;;
-;;    if divisor == INT_MIN && dividend == -1 { trap }
-;;
-;; but to avoid introducing control flow, it is actually done as:
-;;
-;;    if ((divisor ^ INT_MAX) & dividend) == -1 { trap }
-;;
-;; instead, using a single conditional trap instruction.
-(decl maybe_trap_if_sdiv_overflow (bool Type Type RegPair Reg) Reg)
-(rule (maybe_trap_if_sdiv_overflow $false ext_ty _ _ _) (invalid_reg))
-(rule (maybe_trap_if_sdiv_overflow $true ext_ty ty x y)
-      (let ((int_max Reg (imm ext_ty (int_max ty)))
-            (reg Reg (and_reg ext_ty (xor_reg ext_ty int_max
-                                              (regpair_lo x)) y)))
-        (icmps_simm16_and_trap ext_ty reg -1
-                               (intcc_as_cond (IntCC.Equal))
-                               (trap_code_integer_overflow))))
-(decl int_max (Type) u64)
-(rule (int_max $I8) 0x7f)
-(rule (int_max $I16) 0x7fff)
-(rule (int_max $I32) 0x7fffffff)
-(rule (int_max $I64) 0x7fffffffffffffff)
-
-;; When performing `srem`, we do not want to trap in the
-;; integer-overflow scenario, because it is only the quotient
-;; that overflows, not the remainder.
-;;
-;; For types smaller than 64 bits, we can simply let the
-;; instruction execute, since (as above) it will never trap.
-;;
-;; For 64-bit inputs, we check whether the divisor is -1, and
-;; if so simply replace the dividend by zero, which will give
-;; the correct result, since any value modulo -1 is zero.
-;;
-;; (We could in fact avoid executing the divide instruction
-;; at all in this case, but that would require introducing
-;; control flow.)
-(decl maybe_avoid_srem_overflow (bool Type RegPair Reg) RegPair)
-(rule (maybe_avoid_srem_overflow $false _ x _) x)
-(rule (maybe_avoid_srem_overflow $true $I32 x _) x)
-(rule (maybe_avoid_srem_overflow $true $I64 x y)
-      (cmov_imm_regpair_lo $I64 (icmps_simm16 $I64 y -1)
-                           (intcc_as_cond (IntCC.Equal)) 0 x))
-
-
-;;;; Rules for `ishl` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Shift left, shift amount in register.
-(rule (lower (has_type (fits_in_64 ty) (ishl x y)))
-      (let ((masked_amt Reg (mask_amt_reg ty y)))
-        (lshl_reg ty x masked_amt)))
-
-;; Shift left, immediate shift amount.
-(rule (lower (has_type (fits_in_64 ty) (ishl x (i64_from_value y))))
-      (let ((masked_amt u8 (mask_amt_imm ty y)))
-        (lshl_imm ty x masked_amt)))
-
-
-;;;; Rules for `ushr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Shift right logical, shift amount in register.
-;; For types smaller than 32-bit, the input value must be zero-extended.
-(rule (lower (has_type (fits_in_64 ty) (ushr x y)))
-      (let ((ext_reg Reg (put_in_reg_zext32 x))
-            (masked_amt Reg (mask_amt_reg ty y)))
-        (lshr_reg (ty_ext32 ty) ext_reg masked_amt)))
-
-;; Shift right logical, immediate shift amount.
-;; For types smaller than 32-bit, the input value must be zero-extended.
-(rule (lower (has_type (fits_in_64 ty) (ushr x (i64_from_value y))))
-      (let ((ext_reg Reg (put_in_reg_zext32 x))
-            (masked_amt u8 (mask_amt_imm ty y)))
-        (lshr_imm (ty_ext32 ty) ext_reg masked_amt)))
-
-
-;;;; Rules for `sshr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Shift right arithmetic, shift amount in register.
-;; For types smaller than 32-bit, the input value must be sign-extended.
-(rule (lower (has_type (fits_in_64 ty) (sshr x y)))
-      (let ((ext_reg Reg (put_in_reg_sext32 x))
-            (masked_amt Reg (mask_amt_reg ty y)))
-        (ashr_reg (ty_ext32 ty) ext_reg masked_amt)))
-
-;; Shift right arithmetic, immediate shift amount.
-;; For types smaller than 32-bit, the input value must be sign-extended.
-(rule (lower (has_type (fits_in_64 ty) (sshr x (i64_from_value y))))
-      (let ((ext_reg Reg (put_in_reg_sext32 x))
-            (masked_amt u8 (mask_amt_imm ty y)))
-        (ashr_imm (ty_ext32 ty) ext_reg masked_amt)))
-
-
-;;;; Rules for `rotl` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Rotate left, shift amount in register.  32-bit or 64-bit types.
-(rule (lower (has_type (ty_32_or_64 ty) (rotl x y)))
-      (rot_reg ty x y))
-
-;; Rotate left arithmetic, immediate shift amount.  32-bit or 64-bit types.
-(rule (lower (has_type (ty_32_or_64 ty) (rotl x (i64_from_value y))))
-      (let ((masked_amt u8 (mask_amt_imm ty y)))
-        (rot_imm ty x masked_amt)))
-
-;; Rotate left, shift amount in register.  8-bit or 16-bit types.
-;; Implemented via a pair of 32-bit shifts on the zero-extended input.
-(rule (lower (has_type (ty_8_or_16 ty) (rotl x y)))
-      (let ((ext_reg Reg (put_in_reg_zext32 x))
-            (ext_ty Type (ty_ext32 ty))
-            (pos_amt Reg y)
-            (neg_amt Reg (neg_reg ty pos_amt))
-            (masked_pos_amt Reg (mask_amt_reg ty pos_amt))
-            (masked_neg_amt Reg (mask_amt_reg ty neg_amt)))
-        (or_reg ty (lshl_reg ext_ty ext_reg masked_pos_amt)
-                (lshr_reg ext_ty ext_reg masked_neg_amt))))
-
-;; Rotate left, immediate shift amount.  8-bit or 16-bit types.
-;; Implemented via a pair of 32-bit shifts on the zero-extended input.
-(rule (lower (has_type (ty_8_or_16 ty) (rotl x (and (i64_from_value pos_amt)
-                                                    (i64_from_negated_value neg_amt)))))
-      (let ((ext_reg Reg (put_in_reg_zext32 x))
-            (ext_ty Type (ty_ext32 ty))
-            (masked_pos_amt u8 (mask_amt_imm ty pos_amt))
-            (masked_neg_amt u8 (mask_amt_imm ty neg_amt)))
-        (or_reg ty (lshl_imm ext_ty ext_reg masked_pos_amt)
-                (lshr_imm ext_ty ext_reg masked_neg_amt))))
-
-
-;;;; Rules for `rotr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Rotate right, shift amount in register.  32-bit or 64-bit types.
-;; Implemented as rotate left with negated rotate amount.
-(rule (lower (has_type (ty_32_or_64 ty) (rotr x y)))
-      (let ((negated_amt Reg (neg_reg ty y)))
-        (rot_reg ty x negated_amt)))
-
-;; Rotate right arithmetic, immediate shift amount.  32-bit or 64-bit types.
-;; Implemented as rotate left with negated rotate amount.
-(rule (lower (has_type (ty_32_or_64 ty) (rotr x (i64_from_negated_value y))))
-      (let ((negated_amt u8 (mask_amt_imm ty y)))
-        (rot_imm ty x negated_amt)))
-
-;; Rotate right, shift amount in register.  8-bit or 16-bit types.
-;; Implemented as rotate left with negated rotate amount.
-(rule (lower (has_type (ty_8_or_16 ty) (rotr x y)))
-      (let ((ext_reg Reg (put_in_reg_zext32 x))
-            (ext_ty Type (ty_ext32 ty))
-            (pos_amt Reg y)
-            (neg_amt Reg (neg_reg ty pos_amt))
-            (masked_pos_amt Reg (mask_amt_reg ty pos_amt))
-            (masked_neg_amt Reg (mask_amt_reg ty neg_amt)))
-        (or_reg ty (lshl_reg ext_ty ext_reg masked_neg_amt)
-                (lshr_reg ext_ty ext_reg masked_pos_amt))))
-
-;; Rotate right, immediate shift amount.  8-bit or 16-bit types.
-;; Implemented as rotate left with negated rotate amount.
-(rule (lower (has_type (ty_8_or_16 ty) (rotr x (and (i64_from_value pos_amt)
-                                                    (i64_from_negated_value neg_amt)))))
-      (let ((ext_reg Reg (put_in_reg_zext32 x))
-            (ext_ty Type (ty_ext32 ty))
-            (masked_pos_amt u8 (mask_amt_imm ty pos_amt))
-            (masked_neg_amt u8 (mask_amt_imm ty neg_amt)))
-        (or_reg ty (lshl_imm ext_ty ext_reg masked_neg_amt)
-                (lshr_imm ext_ty ext_reg masked_pos_amt))))
-
-;;;; Rules for `ireduce` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Always a no-op.
-(rule (lower (ireduce x))
-      x)
-
-
-;;;; Rules for `uextend` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; 16- or 32-bit target types.
-(rule (lower (has_type (gpr32_ty _ty) (uextend x)))
-      (put_in_reg_zext32 x))
-
-;; 64-bit target types.
-(rule (lower (has_type (gpr64_ty _ty) (uextend x)))
-      (put_in_reg_zext64 x))
-
-
-;;;; Rules for `sextend` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; 16- or 32-bit target types.
-(rule (lower (has_type (gpr32_ty _ty) (sextend x)))
-      (put_in_reg_sext32 x))
-
-;; 64-bit target types.
-(rule (lower (has_type (gpr64_ty _ty) (sextend x)))
-      (put_in_reg_sext64 x))
-
-
-;;;; Rules for `bnot` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; z15 version using a single instruction (NOR).
-(rule (lower (has_type (and (mie2_enabled) (fits_in_64 ty)) (bnot x)))
-      (let ((rx Reg x))
-        (or_not_reg ty rx rx)))
-
-;; z14 version using XOR with -1.
-(rule (lower (has_type (and (mie2_disabled) (fits_in_64 ty)) (bnot x)))
-      (not_reg ty x))
-
-
-;;;; Rules for `band` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; And two registers.
-(rule (lower (has_type (fits_in_64 ty) (band x y)))
-      (and_reg ty x y))
-
-;; And a register and an immediate.
-(rule (lower (has_type (fits_in_64 ty) (band x (uimm16shifted_from_inverted_value y))))
-      (and_uimm16shifted ty x y))
-(rule (lower (has_type (fits_in_64 ty) (band (uimm16shifted_from_inverted_value x) y)))
-      (and_uimm16shifted ty y x))
-(rule (lower (has_type (fits_in_64 ty) (band x (uimm32shifted_from_inverted_value y))))
-      (and_uimm32shifted ty x y))
-(rule (lower (has_type (fits_in_64 ty) (band (uimm32shifted_from_inverted_value x) y)))
-      (and_uimm32shifted ty y x))
-
-;; And a register and memory (32/64-bit types).
-(rule (lower (has_type (fits_in_64 ty) (band x (sinkable_load_32_64 y))))
-      (and_mem ty x (sink_load y)))
-(rule (lower (has_type (fits_in_64 ty) (band (sinkable_load_32_64 x) y)))
-      (and_mem ty y (sink_load x)))
-
-
-;;;; Rules for `bor` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Or two registers.
-(rule (lower (has_type (fits_in_64 ty) (bor x y)))
-      (or_reg ty x y))
-
-;; Or a register and an immediate.
-(rule (lower (has_type (fits_in_64 ty) (bor x (uimm16shifted_from_value y))))
-      (or_uimm16shifted ty x y))
-(rule (lower (has_type (fits_in_64 ty) (bor (uimm16shifted_from_value x) y)))
-      (or_uimm16shifted ty y x))
-(rule (lower (has_type (fits_in_64 ty) (bor x (uimm32shifted_from_value y))))
-      (or_uimm32shifted ty x y))
-(rule (lower (has_type (fits_in_64 ty) (bor (uimm32shifted_from_value x) y)))
-      (or_uimm32shifted ty y x))
-
-;; Or a register and memory (32/64-bit types).
-(rule (lower (has_type (fits_in_64 ty) (bor x (sinkable_load_32_64 y))))
-      (or_mem ty x (sink_load y)))
-(rule (lower (has_type (fits_in_64 ty) (bor (sinkable_load_32_64 x) y)))
-      (or_mem ty y (sink_load x)))
-
-
-;;;; Rules for `bxor` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Xor two registers.
-(rule (lower (has_type (fits_in_64 ty) (bxor x y)))
-      (xor_reg ty x y))
-
-;; Xor a register and an immediate.
-(rule (lower (has_type (fits_in_64 ty) (bxor x (uimm32shifted_from_value y))))
-      (xor_uimm32shifted ty x y))
-(rule (lower (has_type (fits_in_64 ty) (bxor (uimm32shifted_from_value x) y)))
-      (xor_uimm32shifted ty y x))
-
-;; Xor a register and memory (32/64-bit types).
-(rule (lower (has_type (fits_in_64 ty) (bxor x (sinkable_load_32_64 y))))
-      (xor_mem ty x (sink_load y)))
-(rule (lower (has_type (fits_in_64 ty) (bxor (sinkable_load_32_64 x) y)))
-      (xor_mem ty y (sink_load x)))
-
-
-;;;; Rules for `band_not` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; z15 version using a single instruction.
-(rule (lower (has_type (and (mie2_enabled) (fits_in_64 ty)) (band_not x y)))
-      (and_not_reg ty x y))
-
-;; z14 version using XOR with -1.
-(rule (lower (has_type (and (mie2_disabled) (fits_in_64 ty)) (band_not x y)))
-      (not_reg ty (and_reg ty x y)))
-
-
-;;;; Rules for `bor_not` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; z15 version using a single instruction.
-(rule (lower (has_type (and (mie2_enabled) (fits_in_64 ty)) (bor_not x y)))
-      (or_not_reg ty x y))
-
-;; z14 version using XOR with -1.
-(rule (lower (has_type (and (mie2_disabled) (fits_in_64 ty)) (bor_not x y)))
-      (not_reg ty (or_reg ty x y)))
-
-
-;;;; Rules for `bxor_not` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; z15 version using a single instruction.
-(rule (lower (has_type (and (mie2_enabled) (fits_in_64 ty)) (bxor_not x y)))
-      (xor_not_reg ty x y))
-
-;; z14 version using XOR with -1.
-(rule (lower (has_type (and (mie2_disabled) (fits_in_64 ty)) (bxor_not x y)))
-      (not_reg ty (xor_reg ty x y)))
-
-
-;;;; Rules for `bitselect` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; z15 version using a NAND instruction.
-(rule (lower (has_type (and (mie2_enabled) (fits_in_64 ty)) (bitselect x y z)))
-      (let ((rx Reg x)
-            (if_true Reg (and_reg ty y rx))
-            (if_false Reg (and_not_reg ty z rx)))
-        (or_reg ty if_false if_true)))
-
-;; z14 version using XOR with -1.
-(rule (lower (has_type (and (mie2_disabled) (fits_in_64 ty)) (bitselect x y z)))
-      (let ((rx Reg x)
-            (if_true Reg (and_reg ty y rx))
-            (if_false Reg (not_reg ty (and_reg ty z rx))))
-        (or_reg ty if_false if_true)))
-
-
-;;;; Rules for `breduce` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Always a no-op.
-(rule (lower (breduce x))
-      x)
-
-
-;;;; Rules for `bextend` and `bmask` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Use a common helper to type cast bools to either bool or integer types.
-(decl cast_bool (Type Value) Reg)
-(rule (lower (has_type ty (bextend x)))
-      (cast_bool ty x))
-(rule (lower (has_type ty (bmask x)))
-      (cast_bool ty x))
-
-;; If the target has the same or a smaller size than the source, it's a no-op.
-(rule (cast_bool $B1 x @ (value_type $B1)) x)
-(rule (cast_bool $B1 x @ (value_type $B8)) x)
-(rule (cast_bool $B8 x @ (value_type $B8)) x)
-(rule (cast_bool $I8 x @ (value_type $B8)) x)
-(rule (cast_bool (fits_in_16 _ty) x @ (value_type $B16)) x)
-(rule (cast_bool (fits_in_32 _ty) x @ (value_type $B32)) x)
-(rule (cast_bool (fits_in_64 _ty) x @ (value_type $B64)) x)
-
-;; Single-bit values are sign-extended via a pair of shifts.
-(rule (cast_bool (gpr32_ty ty) x @ (value_type $B1))
-      (ashr_imm $I32 (lshl_imm $I32 x 31) 31))
-(rule (cast_bool (gpr64_ty ty) x @ (value_type $B1))
-      (ashr_imm $I64 (lshl_imm $I64 x 63) 63))
-
-;; Other values are just sign-extended normally.
-(rule (cast_bool (gpr32_ty _ty) x @ (value_type $B8))
-      (sext32_reg $I8 x))
-(rule (cast_bool (gpr32_ty _ty) x @ (value_type $B16))
-      (sext32_reg $I16 x))
-(rule (cast_bool (gpr64_ty _ty) x @ (value_type $B8))
-      (sext64_reg $I8 x))
-(rule (cast_bool (gpr64_ty _ty) x @ (value_type $B16))
-      (sext64_reg $I16 x))
-(rule (cast_bool (gpr64_ty _ty) x @ (value_type $B32))
-      (sext64_reg $I32 x))
-
-
-;;;; Rules for `bint` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Mask with 1 to get a 0/1 result (8- or 16-bit types).
-(rule (lower (has_type (fits_in_16 ty) (bint x)))
-      (and_uimm16shifted ty x (uimm16shifted 1 0)))
-
-;; Mask with 1 to get a 0/1 result (32-bit types).
-(rule (lower (has_type (fits_in_32 ty) (bint x)))
-      (and_uimm32shifted ty x (uimm32shifted 1 0)))
-
-;; Mask with 1 to get a 0/1 result (64-bit types).
-(rule (lower (has_type (fits_in_64 ty) (bint x)))
-      (and_reg ty x (imm ty 1)))
-
-
-;;;; Rules for `clz` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; The FLOGR hardware instruction always operates on the full 64-bit register.
-;; We can zero-extend smaller types, but then we have to compensate for the
-;; additional leading zero bits the instruction will actually see.
-(decl clz_offset (Type Reg) Reg)
-(rule (clz_offset $I8 x) (add_simm16 $I8 x -56))
-(rule (clz_offset $I16 x) (add_simm16 $I16 x -48))
-(rule (clz_offset $I32 x) (add_simm16 $I32 x -32))
-(rule (clz_offset $I64 x) (copy_reg $I64 x))
-
-;; Count leading zeros, via FLOGR on an input zero-extended to 64 bits,
-;; with the result compensated for the extra bits.
-(rule (lower (has_type (fits_in_64 ty) (clz x)))
-      (let ((ext_reg Reg (put_in_reg_zext64 x))
-            ;; Ask for a value of 64 in the all-zero 64-bit input case.
-            ;; After compensation this will match the expected semantics.
-            (clz RegPair (clz_reg 64 ext_reg)))
-        (clz_offset ty (regpair_hi clz))))
-
-
-;;;; Rules for `cls` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Count leading sign-bit copies.  We don't have any instruction for that,
-;; so we instead count the leading zeros after inverting the input if negative,
-;; i.e. computing
-;;        cls(x) == clz(x ^ (x >> 63))
-;; where x is the sign-extended input.
-(rule (lower (has_type (fits_in_64 ty) (cls x)))
-      (let ((ext_reg Reg (put_in_reg_sext64 x))
-            (signbit_copies Reg (ashr_imm $I64 ext_reg 63))
-            (inv_reg Reg (xor_reg $I64 ext_reg signbit_copies))
-            (clz RegPair (clz_reg 64 inv_reg)))
-        (clz_offset ty (regpair_hi clz))))
-
-
-;;;; Rules for `ctz` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; To count trailing zeros, we find the last bit set in the input via (x & -x),
-;; count the leading zeros of that value, and subtract from 63:
-;;
-;;   ctz(x) == 63 - clz(x & -x)
-;;
-;; This works for all cases except a zero input, where the above formula would
-;; return -1, but we are expected to return the type size.  The compensation
-;; for this case is handled differently for 64-bit types vs. smaller types.
-
-;; For smaller types, we simply ensure that the extended 64-bit input is
-;; never zero by setting a "guard bit" in the position corresponding to
-;; the input type size.  This way the 64-bit algorithm above will handle
-;; that case correctly automatically.
-(rule (lower (has_type (gpr32_ty ty) (ctz x)))
-      (let ((rx Reg (or_uimm16shifted $I64 x (ctz_guardbit ty)))
-            (lastbit Reg (and_reg $I64 rx (neg_reg $I64 rx)))
-            (clz RegPair (clz_reg 64 lastbit)))
-        (sub_reg ty (imm ty 63) (regpair_hi clz))))
-
-(decl ctz_guardbit (Type) UImm16Shifted)
-(rule (ctz_guardbit $I8) (uimm16shifted 256 0))
-(rule (ctz_guardbit $I16) (uimm16shifted 1 16))
-(rule (ctz_guardbit $I32) (uimm16shifted 1 32))
-
-;; For 64-bit types, the FLOGR instruction will indicate the zero input case
-;; via its condition code.  We check for that and replace the instruction
-;; result with the value -1 via a conditional move, which will then lead to
-;; the correct result after the final subtraction from 63.
-(rule (lower (has_type (gpr64_ty _ty) (ctz x)))
-      (let ((rx Reg x)
-            (lastbit Reg (and_reg $I64 rx (neg_reg $I64 rx)))
-            (clz RegPair (clz_reg -1 lastbit)))
-        (sub_reg $I64 (imm $I64 63) (regpair_hi clz))))
-
-
-;;;; Rules for `popcnt` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Population count for 8-bit types is supported by the POPCNT instruction.
-(rule (lower (has_type $I8 (popcnt x)))
-      (popcnt_byte x))
-
-;; On z15, the POPCNT instruction has a variant to compute a full 64-bit
-;; population count, which we also use for 16- and 32-bit types.
-(rule (lower (has_type (and (mie2_enabled) (fits_in_64 ty)) (popcnt x)))
-      (popcnt_reg (put_in_reg_zext64 x)))
-
-;; On z14, we use the regular POPCNT, which computes the population count
-;; of each input byte separately, so we need to accumulate those partial
-;; results via a series of log2(type size in bytes) - 1 additions.  We
-;; accumulate in the high byte, so that a final right shift will zero out
-;; any unrelated bits to give a clean result.
-
-(rule (lower (has_type (and (mie2_disabled) $I16) (popcnt x)))
-      (let ((cnt2 Reg (popcnt_byte x))
-            (cnt1 Reg (add_reg $I32 cnt2 (lshl_imm $I32 cnt2 8))))
-        (lshr_imm $I32 cnt1 8)))
-
-(rule (lower (has_type (and (mie2_disabled) $I32) (popcnt x)))
-      (let ((cnt4 Reg (popcnt_byte x))
-            (cnt2 Reg (add_reg $I32 cnt4 (lshl_imm $I32 cnt4 16)))
-            (cnt1 Reg (add_reg $I32 cnt2 (lshl_imm $I32 cnt2 8))))
-        (lshr_imm $I32 cnt1 24)))
-
-(rule (lower (has_type (and (mie2_disabled) $I64) (popcnt x)))
-      (let ((cnt8 Reg (popcnt_byte x))
-            (cnt4 Reg (add_reg $I64 cnt8 (lshl_imm $I64 cnt8 32)))
-            (cnt2 Reg (add_reg $I64 cnt4 (lshl_imm $I64 cnt4 16)))
-            (cnt1 Reg (add_reg $I64 cnt2 (lshl_imm $I64 cnt2 8))))
-        (lshr_imm $I64 cnt1 56)))
-
-
-;;;; Rules for `fadd` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Add two registers.
-(rule (lower (has_type ty (fadd x y)))
-      (fadd_reg ty x y))
-
-
-;;;; Rules for `fsub` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Subtract two registers.
-(rule (lower (has_type ty (fsub x y)))
-      (fsub_reg ty x y))
-
-
-;;;; Rules for `fmul` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Multiply two registers.
-(rule (lower (has_type ty (fmul x y)))
-      (fmul_reg ty x y))
-
-
-;;;; Rules for `fdiv` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Divide two registers.
-(rule (lower (has_type ty (fdiv x y)))
-      (fdiv_reg ty x y))
-
-
-;;;; Rules for `fmin` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Minimum of two registers.
-(rule (lower (has_type ty (fmin x y)))
-      (fmin_reg ty x y))
-
-
-;;;; Rules for `fmax` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Maximum of two registers.
-(rule (lower (has_type ty (fmax x y)))
-      (fmax_reg ty x y))
-
-
-;;;; Rules for `fcopysign` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Copysign of two registers.
-(rule (lower (has_type ty (fcopysign x y)))
-      (fpu_copysign ty x y))
-
-
-;;;; Rules for `fma` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Multiply-and-add of three registers.
-(rule (lower (has_type ty (fma x y z)))
-      (fma_reg ty x y z))
-
-
-;;;; Rules for `sqrt` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Square root of a register.
-(rule (lower (has_type ty (sqrt x)))
-      (sqrt_reg ty x))
-
-
-;;;; Rules for `fneg` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Negated value of a register.
-(rule (lower (has_type ty (fneg x)))
-      (fneg_reg ty x))
-
-
-;;;; Rules for `fabs` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Absolute value of a register.
-(rule (lower (has_type ty (fabs x)))
-      (fabs_reg ty x))
-
-
-;;;; Rules for `ceil` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Round value in a register towards positive infinity.
-(rule (lower (has_type ty (ceil x)))
-      (ceil_reg ty x))
-
-
-;;;; Rules for `floor` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Round value in a register towards negative infinity.
-(rule (lower (has_type ty (floor x)))
-      (floor_reg ty x))
-
-
-;;;; Rules for `trunc` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Round value in a register towards zero.
-(rule (lower (has_type ty (trunc x)))
-      (trunc_reg ty x))
-
-
-;;;; Rules for `nearest` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Round value in a register towards nearest.
-(rule (lower (has_type ty (nearest x)))
-      (nearest_reg ty x))
-
-
-;;;; Rules for `fpromote` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Promote a register.
-(rule (lower (has_type dst_ty (fpromote x @ (value_type src_ty))))
-      (fpromote_reg dst_ty src_ty x))
-
-
-;;;; Rules for `fdemote` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Demote a register.
-(rule (lower (has_type dst_ty (fdemote x @ (value_type src_ty))))
-      (fdemote_reg dst_ty src_ty x))
-
-
-;;;; Rules for `fcvt_from_uint` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Convert an unsigned integer value in a register to floating-point.
-(rule (lower (has_type dst_ty (fcvt_from_uint x @ (value_type src_ty))))
-      (fcvt_from_uint_reg dst_ty (ty_ext32 src_ty)
-                          (put_in_reg_zext32 x)))
-
-
-;;;; Rules for `fcvt_from_sint` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Convert a signed integer value in a register to floating-point.
-(rule (lower (has_type dst_ty (fcvt_from_sint x @ (value_type src_ty))))
-      (fcvt_from_sint_reg dst_ty (ty_ext32 src_ty)
-                          (put_in_reg_sext32 x)))
-
-
-;;;; Rules for `fcvt_to_uint` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Convert a floating-point value in a register to an unsigned integer value.
-;; Traps if the input cannot be represented in the output type.
-;; FIXME: Add support for 8-/16-bit destination types (needs overflow check).
-(rule (lower (has_type (ty_32_or_64 dst_ty) (fcvt_to_uint x @ (value_type src_ty))))
-      (let ((src Reg x)
-            ;; First, check whether the input is a NaN, and trap if so.
-            (_ Reg (trap_if (fcmp_reg src_ty src src)
-                            (floatcc_as_cond (FloatCC.Unordered))
-                            (trap_code_bad_conversion_to_integer)))
-            ;; Perform the conversion.  If this sets CC 3, we have a
-            ;; "special case".  Since we already exluded the case where
-            ;; the input was a NaN, the only other option is that the
-            ;; conversion overflowed the target type.
-            (dst Reg (trap_if (fcvt_to_uint_reg_with_flags dst_ty src_ty src)
-                              (floatcc_as_cond (FloatCC.Unordered))
-                              (trap_code_integer_overflow))))
-        dst))
-
-
-;;;; Rules for `fcvt_to_sint` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Convert a floating-point value in a register to a signed integer value.
-;; Traps if the input cannot be represented in the output type.
-;; FIXME: Add support for 8-/16-bit destination types (needs overflow check).
-(rule (lower (has_type (ty_32_or_64 dst_ty) (fcvt_to_sint x @ (value_type src_ty))))
-      (let ((src Reg x)
-            ;; First, check whether the input is a NaN, and trap if so.
-            (_ Reg (trap_if (fcmp_reg src_ty src src)
-                            (floatcc_as_cond (FloatCC.Unordered))
-                            (trap_code_bad_conversion_to_integer)))
-            ;; Perform the conversion.  If this sets CC 3, we have a
-            ;; "special case".  Since we already exluded the case where
-            ;; the input was a NaN, the only other option is that the
-            ;; conversion overflowed the target type.
-            (dst Reg (trap_if (fcvt_to_sint_reg_with_flags dst_ty src_ty src)
-                              (floatcc_as_cond (FloatCC.Unordered))
-                              (trap_code_integer_overflow))))
-        dst))
-
-
-;;;; Rules for `fcvt_to_uint_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Convert a floating-point value in a register to an unsigned integer value.
-;; FIXME: Add support for 8-/16-bit destination types (needs overflow check).
-(rule (lower (has_type (ty_32_or_64 dst_ty) (fcvt_to_uint_sat x @ (value_type src_ty))))
-      (let ((src Reg x)
-            (dst Reg (fcvt_to_uint_reg dst_ty src_ty src))
-            ;; In most special cases, the Z instruction already yields the
-            ;; result expected by Cranelift semantics.  The only exception
-            ;; it the case where the input was a NaN.  We explicitly check
-            ;; for that and force the output to 0 in that case.
-            (sat Reg (with_flags_reg (fcmp_reg src_ty src src)
-                                     (cmov_imm dst_ty
-                                               (floatcc_as_cond (FloatCC.Unordered)) 0 dst))))
-        sat))
-
-
-;;;; Rules for `fcvt_to_sint_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Convert a floating-point value in a register to a signed integer value.
-;; FIXME: Add support for 8-/16-bit destination types (needs overflow check).
-(rule (lower (has_type (ty_32_or_64 dst_ty) (fcvt_to_sint_sat x @ (value_type src_ty))))
-      (let ((src Reg x)
-            (dst Reg (fcvt_to_sint_reg dst_ty src_ty src))
-            ;; In most special cases, the Z instruction already yields the
-            ;; result expected by Cranelift semantics.  The only exception
-            ;; it the case where the input was a NaN.  We explicitly check
-            ;; for that and force the output to 0 in that case.
-            (sat Reg (with_flags_reg (fcmp_reg src_ty src src)
-                                     (cmov_imm dst_ty
-                                               (floatcc_as_cond (FloatCC.Unordered)) 0 dst))))
-        sat))
-
-
-;;;; Rules for `bitcast` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Reinterpret a 64-bit integer value as floating-point.
-(rule (lower (has_type $F64 (bitcast x @ (value_type $I64))))
-      (mov_to_fpr x))
-
-;; Reinterpret a 64-bit floating-point value as integer.
-(rule (lower (has_type $I64 (bitcast x @ (value_type $F64))))
-      (mov_from_fpr x))
-
-;; Reinterpret a 32-bit integer value as floating-point (via $I64).
-;; Note that a 32-bit float is located in the high bits of the GPR.
-(rule (lower (has_type $F32 (bitcast x @ (value_type $I32))))
-      (mov_to_fpr (lshl_imm $I64 x 32)))
-
-;; Reinterpret a 32-bit floating-point value as integer (via $I64).
-;; Note that a 32-bit float is located in the high bits of the GPR.
-(rule (lower (has_type $I32 (bitcast x @ (value_type $F32))))
-      (lshr_imm $I64 (mov_from_fpr x) 32))
-
-
-;;;; Rules for `stack_addr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Load the address of a stack slot.
-(rule (lower (has_type ty (stack_addr stack_slot offset)))
-      (stack_addr_impl ty stack_slot offset))
-
-
-;;;; Rules for `func_addr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Load the address of a function, target reachable via PC-relative instruction.
-(rule (lower (func_addr (func_ref_data _ name (reloc_distance_near))))
-      (load_addr (memarg_symbol name 0 (memflags_trusted))))
-
-;; Load the address of a function, general case.
-(rule (lower (func_addr (func_ref_data _ name _)))
-      (load_ext_name_far name 0))
-
-
-;;;; Rules for `symbol_value` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Load the address of a symbol, target reachable via PC-relative instruction.
-(rule (lower (symbol_value (symbol_value_data name (reloc_distance_near)
-                                                   (memarg_symbol_offset offset))))
-      (load_addr (memarg_symbol name offset (memflags_trusted))))
-
-;; Load the address of a symbol, general case.
-(rule (lower (symbol_value (symbol_value_data name _ offset)))
-      (load_ext_name_far name offset))
-
-
-;;;; Rules for `load` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Load 8-bit integers.
-(rule (lower (has_type $I8 (load flags addr offset)))
-      (zext32_mem $I8 (lower_address flags addr offset)))
-
-;; Load 16-bit big-endian integers.
-(rule (lower (has_type $I16 (load flags @ (bigendian) addr offset)))
-      (zext32_mem $I16 (lower_address flags addr offset)))
-
-;; Load 16-bit little-endian integers.
-(rule (lower (has_type $I16 (load flags @ (littleendian) addr offset)))
-      (loadrev16 (lower_address flags addr offset)))
-
-;; Load 32-bit big-endian integers.
-(rule (lower (has_type $I32 (load flags @ (bigendian) addr offset)))
-      (load32 (lower_address flags addr offset)))
-
-;; Load 32-bit little-endian integers.
-(rule (lower (has_type $I32 (load flags @ (littleendian) addr offset)))
-      (loadrev32 (lower_address flags addr offset)))
-
-;; Load 64-bit big-endian integers.
-(rule (lower (has_type $I64 (load flags @ (bigendian) addr offset)))
-      (load64 (lower_address flags addr offset)))
-
-;; Load 64-bit little-endian integers.
-(rule (lower (has_type $I64 (load flags @ (littleendian) addr offset)))
-      (loadrev64 (lower_address flags addr offset)))
-
-;; Load 64-bit big-endian references.
-(rule (lower (has_type $R64 (load flags @ (bigendian) addr offset)))
-      (load64 (lower_address flags addr offset)))
-
-;; Load 64-bit little-endian references.
-(rule (lower (has_type $R64 (load flags @ (littleendian) addr offset)))
-      (loadrev64 (lower_address flags addr offset)))
-
-;; Load 32-bit big-endian floating-point values.
-(rule (lower (has_type $F32 (load flags @ (bigendian) addr offset)))
-      (fpu_load32 (lower_address flags addr offset)))
-
-;; Load 32-bit little-endian floating-point values (z15 instruction).
-(rule (lower (has_type (and (vxrs_ext2_enabled) $F32)
-                       (load flags @ (littleendian) addr offset)))
-      (fpu_loadrev32 (lower_address flags addr offset)))
-
-;; Load 32-bit little-endian floating-point values (via GPR on z14).
-(rule (lower (has_type (and (vxrs_ext2_disabled) $F32)
-                       (load flags @ (littleendian) addr offset)))
-      (let ((gpr Reg (loadrev32 (lower_address flags addr offset))))
-        (mov_to_fpr (lshl_imm $I64 gpr 32))))
-
-;; Load 64-bit big-endian floating-point values.
-(rule (lower (has_type $F64 (load flags @ (bigendian) addr offset)))
-      (fpu_load64 (lower_address flags addr offset)))
-
-;; Load 64-bit little-endian floating-point values (z15 instruction).
-(rule (lower (has_type (and (vxrs_ext2_enabled) $F64)
-                            (load flags @ (littleendian) addr offset)))
-      (fpu_loadrev64 (lower_address flags addr offset)))
-
-;; Load 64-bit little-endian floating-point values (via GPR on z14).
-(rule (lower (has_type (and (vxrs_ext2_disabled) $F64)
-                            (load flags @ (littleendian) addr offset)))
-      (let ((gpr Reg (loadrev64 (lower_address flags addr offset))))
-        (mov_to_fpr gpr)))
-
-
-;;;; Rules for `uload8` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; 16- or 32-bit target types.
-(rule (lower (has_type (gpr32_ty _ty) (uload8 flags addr offset)))
-      (zext32_mem $I8 (lower_address flags addr offset)))
-
-;; 64-bit target types.
-(rule (lower (has_type (gpr64_ty _ty) (uload8 flags addr offset)))
-      (zext64_mem $I8 (lower_address flags addr offset)))
-
-
-;;;; Rules for `sload8` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; 16- or 32-bit target types.
-(rule (lower (has_type (gpr32_ty _ty) (sload8 flags addr offset)))
-      (sext32_mem $I8 (lower_address flags addr offset)))
-
-;; 64-bit target types.
-(rule (lower (has_type (gpr64_ty _ty) (sload8 flags addr offset)))
-      (sext64_mem $I8 (lower_address flags addr offset)))
-
-
-;;;; Rules for `uload16` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; 32-bit target type, big-endian source value.
-(rule (lower (has_type (gpr32_ty _ty)
-                       (uload16 flags @ (bigendian) addr offset)))
-      (zext32_mem $I16 (lower_address flags addr offset)))
-
-;; 32-bit target type, little-endian source value (via explicit extension).
-(rule (lower (has_type (gpr32_ty _ty)
-                       (uload16 flags @ (littleendian) addr offset)))
-      (let ((reg16 Reg (loadrev16 (lower_address flags addr offset))))
-        (zext32_reg $I16 reg16)))
-
-;; 64-bit target type, big-endian source value.
-(rule (lower (has_type (gpr64_ty _ty)
-                       (uload16 flags @ (bigendian) addr offset)))
-      (zext64_mem $I16 (lower_address flags addr offset)))
-
-;; 64-bit target type, little-endian source value (via explicit extension).
-(rule (lower (has_type (gpr64_ty _ty)
-                       (uload16 flags @ (littleendian) addr offset)))
-      (let ((reg16 Reg (loadrev16 (lower_address flags addr offset))))
-        (zext64_reg $I16 reg16)))
-
-
-;;;; Rules for `sload16` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; 32-bit target type, big-endian source value.
-(rule (lower (has_type (gpr32_ty _ty)
-                       (sload16 flags @ (bigendian) addr offset)))
-      (sext32_mem $I16 (lower_address flags addr offset)))
-
-;; 32-bit target type, little-endian source value (via explicit extension).
-(rule (lower (has_type (gpr32_ty _ty)
-                       (sload16 flags @ (littleendian) addr offset)))
-      (let ((reg16 Reg (loadrev16 (lower_address flags addr offset))))
-        (sext32_reg $I16 reg16)))
-
-;; 64-bit target type, big-endian source value.
-(rule (lower (has_type (gpr64_ty _ty)
-                       (sload16 flags @ (bigendian) addr offset)))
-      (sext64_mem $I16 (lower_address flags addr offset)))
-
-;; 64-bit target type, little-endian source value (via explicit extension).
-(rule (lower (has_type (gpr64_ty _ty)
-                       (sload16 flags @ (littleendian) addr offset)))
-      (let ((reg16 Reg (loadrev16 (lower_address flags addr offset))))
-        (sext64_reg $I16 reg16)))
-
-
-;;;; Rules for `uload32` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; 64-bit target type, big-endian source value.
-(rule (lower (has_type (gpr64_ty _ty)
-                       (uload32 flags @ (bigendian) addr offset)))
-      (zext64_mem $I32 (lower_address flags addr offset)))
-
-;; 64-bit target type, little-endian source value (via explicit extension).
-(rule (lower (has_type (gpr64_ty _ty)
-                       (uload32 flags @ (littleendian) addr offset)))
-      (let ((reg32 Reg (loadrev32 (lower_address flags addr offset))))
-        (zext64_reg $I32 reg32)))
-
-
-;;;; Rules for `sload32` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; 64-bit target type, big-endian source value.
-(rule (lower (has_type (gpr64_ty _ty)
-                       (sload32 flags @ (bigendian) addr offset)))
-      (sext64_mem $I32 (lower_address flags addr offset)))
-
-;; 64-bit target type, little-endian source value (via explicit extension).
-(rule (lower (has_type (gpr64_ty _ty)
-                       (sload32 flags @ (littleendian) addr offset)))
-      (let ((reg32 Reg (loadrev32 (lower_address flags addr offset))))
-        (sext64_reg $I32 reg32)))
-
-
-;;;; Rules for `store` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; The actual store logic for integer types is identical for the `store`,
-;; `istoreNN`, and `atomic_store` instructions, so we share common helpers.
-
-;; Store 8-bit integer type, main lowering entry point.
-(rule (lower (store flags val @ (value_type $I8) addr offset))
-      (side_effect (istore8_impl flags val addr offset)))
-
-;; Store 16-bit integer type, main lowering entry point.
-(rule (lower (store flags val @ (value_type $I16) addr offset))
-      (side_effect (istore16_impl flags val addr offset)))
-
-;; Store 32-bit integer type, main lowering entry point.
-(rule (lower (store flags val @ (value_type $I32) addr offset))
-      (side_effect (istore32_impl flags val addr offset)))
-
-;; Store 64-bit integer type, main lowering entry point.
-(rule (lower (store flags val @ (value_type $I64) addr offset))
-      (side_effect (istore64_impl flags val addr offset)))
-
-;; Store 64-bit reference type, main lowering entry point.
-(rule (lower (store flags val @ (value_type $R64) addr offset))
-      (side_effect (istore64_impl flags val addr offset)))
-
-;; Store 32-bit big-endian floating-point type.
-(rule (lower (store flags @ (bigendian)
-                    val @ (value_type $F32) addr offset))
-      (side_effect (fpu_store32 (put_in_reg val)
-                                (lower_address flags addr offset))))
-
-;; Store 32-bit little-endian floating-point type (z15 instruction).
-(rule (lower (store flags @ (littleendian)
-                    val @ (value_type (and $F32 (vxrs_ext2_enabled))) addr offset))
-      (side_effect (fpu_storerev32 (put_in_reg val)
-                                   (lower_address flags addr offset))))
-
-;; Store 32-bit little-endian floating-point type (via GPR on z14).
-(rule (lower (store flags @ (littleendian)
-                    val @ (value_type (and $F32 (vxrs_ext2_disabled))) addr offset))
-      (let ((gpr Reg (lshr_imm $I64 (mov_from_fpr (put_in_reg val)) 32)))
-        (side_effect (storerev32 gpr (lower_address flags addr offset)))))
-
-;; Store 64-bit big-endian floating-point type.
-(rule (lower (store flags @ (bigendian)
-                    val @ (value_type $F64) addr offset))
-      (side_effect (fpu_store64 (put_in_reg val)
-                                (lower_address flags addr offset))))
-
-;; Store 64-bit little-endian floating-point type (z15 instruction).
-(rule (lower (store flags @ (littleendian)
-                    val @ (value_type (and $F64 (vxrs_ext2_enabled))) addr offset))
-      (side_effect (fpu_storerev64 (put_in_reg val)
-                                   (lower_address flags addr offset))))
-
-;; Store 64-bit little-endian floating-point type (via GPR on z14).
-(rule (lower (store flags @ (littleendian)
-                    val @ (value_type (and $F64 (vxrs_ext2_disabled))) addr offset))
-      (let ((gpr Reg (mov_from_fpr (put_in_reg val))))
-        (side_effect (storerev64 gpr (lower_address flags addr offset)))))
-
-
-;;;; Rules for 8-bit integer stores ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Main `istore8` lowering entry point, dispatching to the helper.
-(rule (lower (istore8 flags val addr offset))
-      (side_effect (istore8_impl flags val addr offset)))
-
-;; Helper to store 8-bit integer types.
-(decl istore8_impl (MemFlags Value Value Offset32) SideEffectNoResult)
-
-;; Store 8-bit integer types, register input.
-(rule (istore8_impl flags val addr offset)
-      (store8 (put_in_reg val) (lower_address flags addr offset)))
-
-;; Store 8-bit integer types, immediate input.
-(rule (istore8_impl flags (u8_from_value imm) addr offset)
-      (store8_imm imm (lower_address flags addr offset)))
-
-
-;;;; Rules for 16-bit integer stores ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Main `istore16` lowering entry point, dispatching to the helper.
-(rule (lower (istore16 flags val addr offset))
-      (side_effect (istore16_impl flags val addr offset)))
-
-;; Helper to store 16-bit integer types.
-(decl istore16_impl (MemFlags Value Value Offset32) SideEffectNoResult)
-
-;; Store 16-bit big-endian integer types, register input.
-(rule (istore16_impl flags @ (bigendian) val addr offset)
-      (store16 (put_in_reg val) (lower_address flags addr offset)))
-
-;; Store 16-bit little-endian integer types, register input.
-(rule (istore16_impl flags @ (littleendian) val addr offset)
-      (storerev16 (put_in_reg val) (lower_address flags addr offset)))
-
-;; Store 16-bit big-endian integer types, immediate input.
-(rule (istore16_impl flags @ (bigendian) (i16_from_value imm) addr offset)
-      (store16_imm imm (lower_address flags addr offset)))
-
-;; Store 16-bit little-endian integer types, immediate input.
-(rule (istore16_impl flags @ (littleendian) (i16_from_swapped_value imm) addr offset)
-      (store16_imm imm (lower_address flags addr offset)))
-
-
-;;;; Rules for 32-bit integer stores ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Main `istore32` lowering entry point, dispatching to the helper.
-(rule (lower (istore32 flags val addr offset))
-      (side_effect (istore32_impl flags val addr offset)))
-
-;; Helper to store 32-bit integer types.
-(decl istore32_impl (MemFlags Value Value Offset32) SideEffectNoResult)
-
-;; Store 32-bit big-endian integer types, register input.
-(rule (istore32_impl flags @ (bigendian) val addr offset)
-      (store32 (put_in_reg val) (lower_address flags addr offset)))
-
-;; Store 32-bit big-endian integer types, immediate input.
-(rule (istore32_impl flags @ (bigendian) (i16_from_value imm) addr offset)
-      (store32_simm16 imm (lower_address flags addr offset)))
-
-;; Store 32-bit little-endian integer types.
-(rule (istore32_impl flags @ (littleendian) val addr offset)
-      (storerev32 (put_in_reg val) (lower_address flags addr offset)))
-
-
-;;;; Rules for 64-bit integer stores ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Helper to store 64-bit integer types.
-(decl istore64_impl (MemFlags Value Value Offset32) SideEffectNoResult)
-
-;; Store 64-bit big-endian integer types, register input.
-(rule (istore64_impl flags @ (bigendian) val addr offset)
-      (store64 (put_in_reg val) (lower_address flags addr offset)))
-
-;; Store 64-bit big-endian integer types, immediate input.
-(rule (istore64_impl flags @ (bigendian) (i16_from_value imm) addr offset)
-      (store64_simm16 imm (lower_address flags addr offset)))
-
-;; Store 64-bit little-endian integer types.
-(rule (istore64_impl flags @ (littleendian) val addr offset)
-      (storerev64 (put_in_reg val) (lower_address flags addr offset)))
-
-
-;;;; Rules for `atomic_rmw` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Atomic operations that do not require a compare-and-swap loop.
-
-;; Atomic AND for 32/64-bit big-endian types, using a single instruction.
-(rule (lower (has_type (ty_32_or_64 ty)
-                (atomic_rmw flags @ (bigendian) (AtomicRmwOp.And) addr src)))
-      (atomic_rmw_and ty (put_in_reg src)
-                      (lower_address flags addr (zero_offset))))
-
-;; Atomic AND for 32/64-bit big-endian types, using byte-swapped input/output.
-(rule (lower (has_type (ty_32_or_64 ty)
-               (atomic_rmw flags @ (littleendian) (AtomicRmwOp.And) addr src)))
-      (bswap_reg ty (atomic_rmw_and ty (bswap_reg ty (put_in_reg src))
-                                    (lower_address flags addr (zero_offset)))))
-
-;; Atomic OR for 32/64-bit big-endian types, using a single instruction.
-(rule (lower (has_type (ty_32_or_64 ty)
-               (atomic_rmw flags @ (bigendian) (AtomicRmwOp.Or) addr src)))
-      (atomic_rmw_or ty (put_in_reg src)
-                     (lower_address flags addr (zero_offset))))
-
-;; Atomic OR for 32/64-bit little-endian types, using byte-swapped input/output.
-(rule (lower (has_type (ty_32_or_64 ty)
-               (atomic_rmw flags @ (littleendian) (AtomicRmwOp.Or) addr src)))
-      (bswap_reg ty (atomic_rmw_or ty (bswap_reg ty (put_in_reg src))
-                                   (lower_address flags addr (zero_offset)))))
-
-;; Atomic XOR for 32/64-bit big-endian types, using a single instruction.
-(rule (lower (has_type (ty_32_or_64 ty)
-               (atomic_rmw flags @ (bigendian) (AtomicRmwOp.Xor) addr src)))
-      (atomic_rmw_xor ty (put_in_reg src)
-                      (lower_address flags addr (zero_offset))))
-
-;; Atomic XOR for 32/64-bit little-endian types, using byte-swapped input/output.
-(rule (lower (has_type (ty_32_or_64 ty)
-               (atomic_rmw flags @ (littleendian) (AtomicRmwOp.Xor) addr src)))
-      (bswap_reg ty (atomic_rmw_xor ty (bswap_reg ty (put_in_reg src))
-                                    (lower_address flags addr (zero_offset)))))
-
-;; Atomic ADD for 32/64-bit big-endian types, using a single instruction.
-(rule (lower (has_type (ty_32_or_64 ty)
-               (atomic_rmw flags @ (bigendian) (AtomicRmwOp.Add) addr src)))
-      (atomic_rmw_add ty (put_in_reg src)
-                      (lower_address flags addr (zero_offset))))
-
-;; Atomic SUB for 32/64-bit big-endian types, using atomic ADD with negated input.
-(rule (lower (has_type (ty_32_or_64 ty)
-               (atomic_rmw flags @ (bigendian) (AtomicRmwOp.Sub) addr src)))
-      (atomic_rmw_add ty (neg_reg ty (put_in_reg src))
-                      (lower_address flags addr (zero_offset))))
-
-
-;; Atomic operations that require a compare-and-swap loop.
-
-;; Operations for 32/64-bit types can use a fullword compare-and-swap loop.
-(rule (lower (has_type (ty_32_or_64 ty) (atomic_rmw flags op addr src)))
-      (let ((src_reg Reg (put_in_reg src))
-            (addr_reg Reg (put_in_reg addr))
-            ;; Create body of compare-and-swap loop.
-            (ib VecMInstBuilder (inst_builder_new))
-            (val0 Reg (writable_reg_to_reg (casloop_val_reg)))
-            (val1 Reg (atomic_rmw_body ib ty flags op
-                        (casloop_tmp_reg) val0 src_reg)))
-        ;; Emit compare-and-swap loop and extract final result.
-        (casloop ib ty flags addr_reg val1)))
-
-;; Operations for 8/16-bit types must operate on the surrounding aligned word.
-(rule (lower (has_type (ty_8_or_16 ty) (atomic_rmw flags op addr src)))
-      (let ((src_reg Reg (put_in_reg src))
-            (addr_reg Reg (put_in_reg addr))
-            ;; Prepare access to surrounding aligned word.
-            (bitshift Reg (casloop_bitshift addr_reg))
-            (aligned_addr Reg (casloop_aligned_addr addr_reg))
-            ;; Create body of compare-and-swap loop.
-            (ib VecMInstBuilder (inst_builder_new))
-            (val0 Reg (writable_reg_to_reg (casloop_val_reg)))
-            (val1 Reg (casloop_rotate_in ib ty flags bitshift val0))
-            (val2 Reg (atomic_rmw_body ib ty flags op
-                        (casloop_tmp_reg) val1 src_reg))
-            (val3 Reg (casloop_rotate_out ib ty flags bitshift val2)))
-        ;; Emit compare-and-swap loop and extract final result.
-        (casloop_subword ib ty flags aligned_addr bitshift val3)))
-
-;; Loop bodies for atomic read-modify-write operations.
-(decl atomic_rmw_body (VecMInstBuilder Type MemFlags AtomicRmwOp
-                       WritableReg Reg Reg) Reg)
-
-;; Loop bodies for 32-/64-bit atomic XCHG operations.
-;; Simply use the source (possibly byte-swapped) as new target value.
-(rule (atomic_rmw_body ib (ty_32_or_64 ty) (bigendian)
-                       (AtomicRmwOp.Xchg) tmp val src)
-      src)
-(rule (atomic_rmw_body ib (ty_32_or_64 ty) (littleendian)
-                       (AtomicRmwOp.Xchg) tmp val src)
-      (bswap_reg ty src))
-
-;; Loop bodies for 32-/64-bit atomic NAND operations.
-;; On z15 this can use the NN(G)RK instruction.  On z14, perform an And
-;; operation and invert the result.  In the little-endian case, we can
-;; simply byte-swap the source operand.
-(rule (atomic_rmw_body ib (and (mie2_enabled) (ty_32_or_64 ty)) (bigendian)
-                       (AtomicRmwOp.Nand) tmp val src)
-      (push_alu_reg ib (aluop_and_not ty) tmp val src))
-(rule (atomic_rmw_body ib (and (mie2_enabled) (ty_32_or_64 ty)) (littleendian)
-                       (AtomicRmwOp.Nand) tmp val src)
-      (push_alu_reg ib (aluop_and_not ty) tmp val (bswap_reg ty src)))
-(rule (atomic_rmw_body ib (and (mie2_disabled) (ty_32_or_64 ty)) (bigendian)
-                       (AtomicRmwOp.Nand) tmp val src)
-      (push_not_reg ib ty tmp
-        (push_alu_reg ib (aluop_and ty) tmp val src)))
-(rule (atomic_rmw_body ib (and (mie2_disabled) (ty_32_or_64 ty)) (littleendian)
-                       (AtomicRmwOp.Nand) tmp val src)
-      (push_not_reg ib ty tmp
-        (push_alu_reg ib (aluop_and ty) tmp val (bswap_reg ty src))))
-
-;; Loop bodies for 8-/16-bit atomic bit operations.
-;; These use the "rotate-then-<op>-selected bits" family of instructions.
-;; For the Nand operation, we again perform And and invert the result.
-(rule (atomic_rmw_body ib (ty_8_or_16 ty) flags (AtomicRmwOp.Xchg) tmp val src)
-      (atomic_rmw_body_rxsbg ib ty flags (RxSBGOp.Insert) tmp val src))
-(rule (atomic_rmw_body ib (ty_8_or_16 ty) flags (AtomicRmwOp.And) tmp val src)
-      (atomic_rmw_body_rxsbg ib ty flags (RxSBGOp.And) tmp val src))
-(rule (atomic_rmw_body ib (ty_8_or_16 ty) flags (AtomicRmwOp.Or) tmp val src)
-      (atomic_rmw_body_rxsbg ib ty flags (RxSBGOp.Or) tmp val src))
-(rule (atomic_rmw_body ib (ty_8_or_16 ty) flags (AtomicRmwOp.Xor) tmp val src)
-      (atomic_rmw_body_rxsbg ib ty flags (RxSBGOp.Xor) tmp val src))
-(rule (atomic_rmw_body ib (ty_8_or_16 ty) flags (AtomicRmwOp.Nand) tmp val src)
-      (atomic_rmw_body_invert ib ty flags tmp
-        (atomic_rmw_body_rxsbg ib ty flags (RxSBGOp.And) tmp val src)))
-
-;; RxSBG subword operation.
-(decl atomic_rmw_body_rxsbg (VecMInstBuilder Type MemFlags RxSBGOp
-                             WritableReg Reg Reg) Reg)
-;; 8-bit case: use the low byte of "src" and the high byte of "val".
-(rule (atomic_rmw_body_rxsbg ib $I8 _ op tmp val src)
-      (push_rxsbg ib op tmp val src 32 40 24))
-;; 16-bit big-endian case: use the low two bytes of "src" and the
-;; high two bytes of "val".
-(rule (atomic_rmw_body_rxsbg ib $I16 (bigendian) op tmp val src)
-      (push_rxsbg ib op tmp val src 32 48 16))
-;; 16-bit little-endian case: use the low two bytes of "src", byte-swapped
-;; so they end up in the high two bytes, and the low two bytes of "val".
-(rule (atomic_rmw_body_rxsbg ib $I16 (littleendian) op tmp val src)
-      (push_rxsbg ib op tmp val (bswap_reg $I32 src) 48 64 -16))
-
-;; Invert a subword.
-(decl atomic_rmw_body_invert (VecMInstBuilder Type MemFlags WritableReg Reg) Reg)
-;; 8-bit case: invert the high byte.
-(rule (atomic_rmw_body_invert ib $I8 _ tmp val)
-      (push_xor_uimm32shifted ib $I32 tmp val (uimm32shifted 0xff000000 0)))
-;; 16-bit big-endian case: invert the two high bytes.
-(rule (atomic_rmw_body_invert ib $I16 (bigendian) tmp val)
-      (push_xor_uimm32shifted ib $I32 tmp val (uimm32shifted 0xffff0000 0)))
-;; 16-bit little-endian case: invert the two low bytes.
-(rule (atomic_rmw_body_invert ib $I16 (littleendian) tmp val)
-      (push_xor_uimm32shifted ib $I32 tmp val (uimm32shifted 0xffff 0)))
-
-;; Loop bodies for atomic ADD/SUB operations.
-(rule (atomic_rmw_body ib ty flags (AtomicRmwOp.Add) tmp val src)
-      (atomic_rmw_body_addsub ib ty flags (aluop_add (ty_ext32 ty)) tmp val src))
-(rule (atomic_rmw_body ib ty flags (AtomicRmwOp.Sub) tmp val src)
-      (atomic_rmw_body_addsub ib ty flags (aluop_sub (ty_ext32 ty)) tmp val src))
-
-;; Addition or subtraction operation.
-(decl atomic_rmw_body_addsub (VecMInstBuilder Type MemFlags ALUOp
-                              WritableReg Reg Reg) Reg)
-;; 32/64-bit big-endian case: just a regular add/sub operation.
-(rule (atomic_rmw_body_addsub ib (ty_32_or_64 ty) (bigendian) op tmp val src)
-      (push_alu_reg ib op tmp val src))
-;; 32/64-bit little-endian case: byte-swap the value loaded from memory before
-;; and after performing the operation in native endianness.
-(rule (atomic_rmw_body_addsub ib (ty_32_or_64 ty) (littleendian) op tmp val src)
-      (let ((val_swapped Reg (push_bswap_reg ib ty tmp val))
-            (res_swapped Reg (push_alu_reg ib op tmp val_swapped src)))
-        (push_bswap_reg ib ty tmp res_swapped)))
-;; 8-bit case: perform a 32-bit addition of the source value shifted by 24 bits
-;; to the memory value, which contains the target in its high byte.
-(rule (atomic_rmw_body_addsub ib $I8 _ op tmp val src)
-      (let ((src_shifted Reg (lshl_imm $I32 src 24)))
-        (push_alu_reg ib op tmp val src_shifted)))
-;; 16-bit big-endian case: similar, just shift the source by 16 bits.
-(rule (atomic_rmw_body_addsub ib $I16 (bigendian) op tmp val src)
-      (let ((src_shifted Reg (lshl_imm $I32 src 16)))
-        (push_alu_reg ib op tmp val src_shifted)))
-;; 16-bit little-endian case: the same, but in addition we need to byte-swap
-;; the memory value before and after the operation.  Since the value was placed
-;; in the low two bytes by our standard rotation, we can use a 32-bit byte-swap
-;; and the native-endian value will end up in the high bytes where we need it
-;; to perform the operation.
-(rule (atomic_rmw_body_addsub ib $I16 (littleendian) op tmp val src)
-      (let ((src_shifted Reg (lshl_imm $I32 src 16))
-            (val_swapped Reg (push_bswap_reg ib $I32 tmp val))
-            (res_swapped Reg (push_alu_reg ib op tmp val_swapped src_shifted)))
-        (push_bswap_reg ib $I32 tmp res_swapped)))
-
-;; Loop bodies for atomic MIN/MAX operations.
-(rule (atomic_rmw_body ib ty flags (AtomicRmwOp.Smin) tmp val src)
-      (atomic_rmw_body_minmax ib ty flags (cmpop_cmps (ty_ext32 ty))
-        (intcc_as_cond (IntCC.SignedLessThan)) tmp val src))
-(rule (atomic_rmw_body ib ty flags (AtomicRmwOp.Smax) tmp val src)
-      (atomic_rmw_body_minmax ib ty flags (cmpop_cmps (ty_ext32 ty))
-        (intcc_as_cond (IntCC.SignedGreaterThan)) tmp val src))
-(rule (atomic_rmw_body ib ty flags (AtomicRmwOp.Umin) tmp val src)
-      (atomic_rmw_body_minmax ib ty flags (cmpop_cmpu (ty_ext32 ty))
-        (intcc_as_cond (IntCC.UnsignedLessThan)) tmp val src))
-(rule (atomic_rmw_body ib ty flags (AtomicRmwOp.Umax) tmp val src)
-      (atomic_rmw_body_minmax ib ty flags (cmpop_cmpu (ty_ext32 ty))
-        (intcc_as_cond (IntCC.UnsignedGreaterThan)) tmp val src))
-
-;; Minimum or maximum operation.
-(decl atomic_rmw_body_minmax (VecMInstBuilder Type MemFlags CmpOp Cond
-                              WritableReg Reg Reg) Reg)
-;; 32/64-bit big-endian case: just a comparison followed by a conditional
-;; break out of the loop if the memory value does not need to change.
-;; If it does need to change, the new value is simply the source operand.
-(rule (atomic_rmw_body_minmax ib (ty_32_or_64 ty) (bigendian)
-                              op cond tmp val src)
-      (let ((_ Reg (push_break_if ib (cmp_rr op src val) (invert_cond cond))))
-        src))
-;; 32/64-bit little-endian case: similar, but we need to byte-swap the
-;; memory value before the comparison.  If we need to store the new value,
-;; it also needs to be byte-swapped.
-(rule (atomic_rmw_body_minmax ib (ty_32_or_64 ty) (littleendian)
-                              op cond tmp val src)
-      (let ((val_swapped Reg (push_bswap_reg ib ty tmp val))
-            (_ Reg (push_break_if ib (cmp_rr op src val_swapped)
-                                     (invert_cond cond))))
-        (push_bswap_reg ib ty tmp src)))
-;; 8-bit case: compare the memory value (which contains the target in the
-;; high byte) with the source operand shifted by 24 bits.  Note that in
-;; the case where the high bytes are equal, the comparison may succeed
-;; or fail depending on the unrelated low bits of the memory value, and
-;; so we either may or may not perform the update.  But it would be an
-;; update with the same value in any case, so this does not matter.
-(rule (atomic_rmw_body_minmax ib $I8 _ op cond tmp val src)
-      (let ((src_shifted Reg (lshl_imm $I32 src 24))
-            (_ Reg (push_break_if ib (cmp_rr op src_shifted val)
-                                     (invert_cond cond))))
-        (push_rxsbg ib (RxSBGOp.Insert) tmp val src_shifted 32 40 0)))
-;; 16-bit big-endian case: similar, just shift the source by 16 bits.
-(rule (atomic_rmw_body_minmax ib $I16 (bigendian) op cond tmp val src)
-      (let ((src_shifted Reg (lshl_imm $I32 src 16))
-            (_ Reg (push_break_if ib (cmp_rr op src_shifted val)
-                                     (invert_cond cond))))
-        (push_rxsbg ib (RxSBGOp.Insert) tmp val src_shifted 32 48 0)))
-;; 16-bit little-endian case: similar, but in addition byte-swap the
-;; memory value before and after the operation, like for _addsub_.
-(rule (atomic_rmw_body_minmax ib $I16 (littleendian) op cond tmp val src)
-      (let ((src_shifted Reg (lshl_imm $I32 src 16))
-            (val_swapped Reg (push_bswap_reg ib $I32 tmp val))
-            (_ Reg (push_break_if ib (cmp_rr op src_shifted val_swapped)
-                                     (invert_cond cond)))
-            (res_swapped Reg (push_rxsbg ib (RxSBGOp.Insert)
-                                tmp val_swapped src_shifted 32 48 0)))
-        (push_bswap_reg ib $I32 tmp res_swapped)))
-
-
-;;;; Rules for `atomic_cas` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; 32/64-bit big-endian atomic compare-and-swap instruction.
-(rule (lower (has_type (ty_32_or_64 ty)
-               (atomic_cas flags @ (bigendian) addr src1 src2)))
-      (atomic_cas_impl ty (put_in_reg src1) (put_in_reg src2)
-                       (lower_address flags addr (zero_offset))))
-
-;; 32/64-bit little-endian atomic compare-and-swap instruction.
-;; Implemented by byte-swapping old/new inputs and the output.
-(rule (lower (has_type (ty_32_or_64 ty)
-               (atomic_cas flags @ (littleendian) addr src1 src2)))
-      (bswap_reg ty (atomic_cas_impl ty (bswap_reg ty (put_in_reg src1))
-                                     (bswap_reg ty (put_in_reg src2))
-                                     (lower_address flags addr (zero_offset)))))
-
-;; 8/16-bit atomic compare-and-swap implemented via loop.
-(rule (lower (has_type (ty_8_or_16 ty) (atomic_cas flags addr src1 src2)))
-      (let ((src1_reg Reg (put_in_reg src1))
-            (src2_reg Reg (put_in_reg src2))
-            (addr_reg Reg (put_in_reg addr))
-            ;; Prepare access to the surrounding aligned word.
-            (bitshift Reg (casloop_bitshift addr_reg))
-            (aligned_addr Reg (casloop_aligned_addr addr_reg))
-            ;; Create body of compare-and-swap loop.
-            (ib VecMInstBuilder (inst_builder_new))
-            (val0 Reg (writable_reg_to_reg (casloop_val_reg)))
-            (val1 Reg (casloop_rotate_in ib ty flags bitshift val0))
-            (val2 Reg (atomic_cas_body ib ty flags
-                        (casloop_tmp_reg) val1 src1_reg src2_reg))
-            (val3 Reg (casloop_rotate_out ib ty flags bitshift val2)))
-        ;; Emit compare-and-swap loop and extract final result.
-        (casloop_subword ib ty flags aligned_addr bitshift val3)))
-
-;; Emit loop body instructions to perform a subword compare-and-swap.
-(decl atomic_cas_body (VecMInstBuilder Type MemFlags
-                       WritableReg Reg Reg Reg) Reg)
-
-;; 8-bit case: "val" contains the value loaded from memory in the high byte.
-;; Compare with the comparison value in the low byte of "src1".  If unequal,
-;; break out of the loop, otherwise replace the target byte in "val" with
-;; the low byte of "src2".
-(rule (atomic_cas_body ib $I8 _ tmp val src1 src2)
-      (let ((_ Reg (push_break_if ib (rxsbg_test (RxSBGOp.Xor) val src1 32 40 24)
-                                     (intcc_as_cond (IntCC.NotEqual)))))
-        (push_rxsbg ib (RxSBGOp.Insert) tmp val src2 32 40 24)))
-
-;; 16-bit big-endian case: Same as above, except with values in the high
-;; two bytes of "val" and low two bytes of "src1" and "src2".
-(rule (atomic_cas_body ib $I16 (bigendian) tmp val src1 src2)
-      (let ((_ Reg (push_break_if ib (rxsbg_test (RxSBGOp.Xor) val src1 32 48 16)
-                                     (intcc_as_cond (IntCC.NotEqual)))))
-        (push_rxsbg ib (RxSBGOp.Insert) tmp val src2 32 48 16)))
-
-;; 16-bit little-endian case: "val" here contains a little-endian value in the
-;; *low* two bytes.  "src1" and "src2" contain native (i.e. big-endian) values
-;; in their low two bytes.  Perform the operation in little-endian mode by
-;; byte-swapping "src1" and "src" ahead of the loop.  Note that this is a
-;; 32-bit operation so the little-endian 16-bit values end up in the *high*
-;; two bytes of the swapped values.
-(rule (atomic_cas_body ib $I16 (littleendian) tmp val src1 src2)
-      (let ((src1_swapped Reg (bswap_reg $I32 src1))
-            (src2_swapped Reg (bswap_reg $I32 src2))
-            (_ Reg (push_break_if ib
-                     (rxsbg_test (RxSBGOp.Xor) val src1_swapped 48 64 -16)
-                     (intcc_as_cond (IntCC.NotEqual)))))
-        (push_rxsbg ib (RxSBGOp.Insert) tmp val src2_swapped 48 64 -16)))
-
-
-;;;; Rules for `atomic_load` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Atomic loads can be implemented via regular loads on this platform.
-
-;; 8-bit atomic load.
-(rule (lower (has_type $I8 (atomic_load flags addr)))
-      (zext32_mem $I8 (lower_address flags addr (zero_offset))))
-
-;; 16-bit big-endian atomic load.
-(rule (lower (has_type $I16 (atomic_load flags @ (bigendian) addr)))
-      (zext32_mem $I16 (lower_address flags addr (zero_offset))))
-
-;; 16-bit little-endian atomic load.
-(rule (lower (has_type $I16 (atomic_load flags @ (littleendian) addr)))
-      (loadrev16 (lower_address flags addr (zero_offset))))
-
-;; 32-bit big-endian atomic load.
-(rule (lower (has_type $I32 (atomic_load flags @ (bigendian) addr)))
-      (load32 (lower_address flags addr (zero_offset))))
-
-;; 32-bit little-endian atomic load.
-(rule (lower (has_type $I32 (atomic_load flags @ (littleendian) addr)))
-      (loadrev32 (lower_address flags addr (zero_offset))))
-
-;; 64-bit big-endian atomic load.
-(rule (lower (has_type $I64 (atomic_load flags @ (bigendian) addr)))
-      (load64 (lower_address flags addr (zero_offset))))
-
-;; 64-bit little-endian atomic load.
-(rule (lower (has_type $I64 (atomic_load flags @ (littleendian) addr)))
-      (loadrev64 (lower_address flags addr (zero_offset))))
-
-
-;;;; Rules for `atomic_store` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Atomic stores can be implemented via regular stores followed by a fence.
-(decl atomic_store_impl (SideEffectNoResult) InstOutput)
-(rule (atomic_store_impl store)
-      (let ((_ InstOutput (side_effect store)))
-         (side_effect (fence_impl))))
-
-;; 8-bit atomic store.
-(rule (lower (atomic_store flags val @ (value_type $I8) addr))
-      (atomic_store_impl (istore8_impl flags val addr (zero_offset))))
-
-;; 16-bit atomic store.
-(rule (lower (atomic_store flags val @ (value_type $I16) addr))
-      (atomic_store_impl (istore16_impl flags val addr (zero_offset))))
-
-;; 32-bit atomic store.
-(rule (lower (atomic_store flags val @ (value_type $I32) addr))
-      (atomic_store_impl (istore32_impl flags val addr (zero_offset))))
-
-;; 64-bit atomic store.
-(rule (lower (atomic_store flags val @ (value_type $I64) addr))
-      (atomic_store_impl (istore64_impl flags val addr (zero_offset))))
-
-
-;;;; Rules for `fence` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Fence to ensure sequential consistency.
-(rule (lower (fence))
-      (side_effect (fence_impl)))
-
-
-;;;; Rules for `icmp` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; We want to optimize the typical use of `icmp` (generating an integer 0/1
-;; result) followed by some user, like a `select` or a conditional branch.
-;; Instead of first generating the integer result and later testing it again,
-;; we want to sink the comparison to be performed at the site of use.
-;;
-;; To enable this, we provide generic helpers that return a `ProducesBool`
-;; encapsulating the comparison in question, which can be used by all the
-;; above scenarios.
-;;
-;; N.B. There are specific considerations when sinking a memory load into a
-;; comparison.  When emitting an `icmp` directly, this can of course be done
-;; as usual.  However, when we use the `ProducesBool` elsewhere, we need to
-;; consider *three* instructions: the load, the `icmp`, and the final user
-;; (e.g. a conditional branch).  The only way to safely sink the load would
-;; be to sink it direct into the final user, which is only possible if there
-;; is no *other* user of the `icmp` result.  This is not currently being
-;; verified by the `SinkableInst` logic, so to be safe we do not perform this
-;; optimization at all.
-;;
-;; The generic `icmp_val` helper therefore has a flag indicating whether
-;; it is being invoked in a context where it is safe to sink memory loads
-;; (e.g. when directly emitting an `icmp`), or whether it is not (e.g. when
-;; sinking the `icmp` result into a conditional branch or select).
-
-;; Main `icmp` entry point.  Generate a `ProducesBool` capturing the
-;; integer comparison and immediately lower it to a 0/1 integer result.
-;; In this case, it is safe to sink memory loads.
-(rule (lower (has_type ty (icmp int_cc x y)))
-      (lower_bool ty (icmp_val $true int_cc x y)))
-
-
-;; Return a `ProducesBool` to implement any integer comparison.
-;; The first argument is a flag to indicate whether it is safe to sink
-;; memory loads as discussed above.
-(decl icmp_val (bool IntCC Value Value) ProducesBool)
-
-;; Dispatch for signed comparisons.
-(rule (icmp_val allow_mem int_cc @ (signed) x y)
-      (bool (icmps_val allow_mem x y) (intcc_as_cond int_cc)))
-;; Dispatch for unsigned comparisons.
-(rule (icmp_val allow_mem int_cc @ (unsigned) x y)
-      (bool (icmpu_val allow_mem x y) (intcc_as_cond int_cc)))
-
-
-;; Return a `ProducesBool` to implement signed integer comparisons.
-(decl icmps_val (bool Value Value) ProducesFlags)
-
-;; Compare (signed) two registers.
-(rule (icmps_val _ x @ (value_type (fits_in_64 ty)) y)
-      (icmps_reg (ty_ext32 ty) (put_in_reg_sext32 x) (put_in_reg_sext32 y)))
-
-;; Compare (signed) a register and a sign-extended register.
-(rule (icmps_val _ x @ (value_type (fits_in_64 ty)) (sext32_value y))
-      (icmps_reg_sext32 ty x y))
-
-;; Compare (signed) a register and an immediate.
-(rule (icmps_val _ x @ (value_type (fits_in_64 ty)) (i16_from_value y))
-      (icmps_simm16 (ty_ext32 ty) (put_in_reg_sext32 x) y))
-(rule (icmps_val _ x @ (value_type (fits_in_64 ty)) (i32_from_value y))
-      (icmps_simm32 (ty_ext32 ty) (put_in_reg_sext32 x) y))
-
-;; Compare (signed) a register and memory (32/64-bit types).
-(rule (icmps_val $true x @ (value_type (fits_in_64 ty)) (sinkable_load_32_64 y))
-      (icmps_mem ty x (sink_load y)))
-
-;; Compare (signed) a register and memory (16-bit types).
-(rule (icmps_val $true x @ (value_type (fits_in_64 ty)) (sinkable_load_16 y))
-      (icmps_mem_sext16 (ty_ext32 ty) (put_in_reg_sext32 x) (sink_load y)))
-
-;; Compare (signed) a register and sign-extended memory.
-(rule (icmps_val $true x @ (value_type (fits_in_64 ty)) (sinkable_sload16 y))
-      (icmps_mem_sext16 ty x (sink_sload16 y)))
-(rule (icmps_val $true x @ (value_type (fits_in_64 ty)) (sinkable_sload32 y))
-      (icmps_mem_sext32 ty x (sink_sload32 y)))
-
-
-;; Return a `ProducesBool` to implement unsigned integer comparisons.
-(decl icmpu_val (bool Value Value) ProducesFlags)
-
-;; Compare (unsigned) two registers.
-(rule (icmpu_val _ x @ (value_type (fits_in_64 ty)) y)
-      (icmpu_reg (ty_ext32 ty) (put_in_reg_zext32 x) (put_in_reg_zext32 y)))
-
-;; Compare (unsigned) a register and a sign-extended register.
-(rule (icmpu_val _ x @ (value_type (fits_in_64 ty)) (zext32_value y))
-      (icmpu_reg_zext32 ty x y))
-
-;; Compare (unsigned) a register and an immediate.
-(rule (icmpu_val _ x @ (value_type (fits_in_64 ty)) (u32_from_value y))
-      (icmpu_uimm32 (ty_ext32 ty) (put_in_reg_zext32 x) y))
-
-;; Compare (unsigned) a register and memory (32/64-bit types).
-(rule (icmpu_val $true x @ (value_type (fits_in_64 ty)) (sinkable_load_32_64 y))
-      (icmpu_mem ty x (sink_load y)))
-
-;; Compare (unsigned) a register and memory (16-bit types).
-;; Note that the ISA only provides instructions with a PC-relative memory
-;; address here, so we need to check whether the sinkable load matches this.
-(rule (icmpu_val $true x @ (value_type (fits_in_64 ty))
-                 (sinkable_load_16 (load_sym y)))
-      (icmpu_mem_zext16 (ty_ext32 ty) (put_in_reg_zext32 x) (sink_load y)))
-
-;; Compare (unsigned) a register and zero-extended memory.
-;; Note that the ISA only provides instructions with a PC-relative memory
-;; address here, so we need to check whether the sinkable load matches this.
-(rule (icmpu_val $true x @ (value_type (fits_in_64 ty))
-                 (sinkable_uload16 (uload16_sym y)))
-      (icmpu_mem_zext16 ty x (sink_uload16 y)))
-(rule (icmpu_val $true x @ (value_type (fits_in_64 ty)) (sinkable_uload32 y))
-      (icmpu_mem_zext32 ty x (sink_uload32 y)))
-
-
-;;;; Rules for `fcmp` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Main `fcmp` entry point.  Generate a `ProducesBool` capturing the
-;; integer comparison and immediately lower it to a 0/1 integer result.
-(rule (lower (has_type ty (fcmp float_cc x y)))
-      (lower_bool ty (fcmp_val float_cc x y)))
-
-;; Return a `ProducesBool` to implement any floating-point comparison.
-(decl fcmp_val (FloatCC Value Value) ProducesBool)
-(rule (fcmp_val float_cc x @ (value_type ty) y)
-      (bool (fcmp_reg ty x y)
-            (floatcc_as_cond float_cc)))
-
-
-;;;; Rules for `is_null` and `is_invalid`  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Null references are represented by the constant value 0.
-(rule (lower (has_type $B1 (is_null x @ (value_type $R64))))
-      (lower_bool $B1 (bool (icmps_simm16 $I64 x 0)
-                            (intcc_as_cond (IntCC.Equal)))))
-
-
-;; Invalid references are represented by the constant value -1.
-(rule (lower (has_type $B1 (is_invalid x @ (value_type $R64))))
-      (lower_bool $B1 (bool (icmps_simm16 $I64 x -1)
-                            (intcc_as_cond (IntCC.Equal)))))
-
-
-;;;; Rules for `select` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Return a `ProducesBool` to capture the fact that the input value is nonzero.
-;; In the common case where that input is the result of an `icmp` or `fcmp`
-;; instruction (possibly via an intermediate `bint`), directly use that compare.
-;; Note that it is not safe to sink memory loads here, see the `icmp` comment.
-(decl value_nonzero (Value) ProducesBool)
-(rule (value_nonzero (bint val)) (value_nonzero val))
-(rule (value_nonzero (icmp int_cc x y)) (icmp_val $false int_cc x y))
-(rule (value_nonzero (fcmp float_cc x y)) (fcmp_val float_cc x y))
-(rule (value_nonzero val @ (value_type (gpr32_ty ty)))
-      (bool (icmps_simm16 $I32 (put_in_reg_sext32 val) 0)
-                          (intcc_as_cond (IntCC.NotEqual))))
-(rule (value_nonzero val @ (value_type (gpr64_ty ty)))
-      (bool (icmps_simm16 $I64 (put_in_reg val) 0)
-                          (intcc_as_cond (IntCC.NotEqual))))
-
-;; Main `select` entry point.  Lower the `value_nonzero` result.
-(rule (lower (has_type ty (select val_cond val_true val_false)))
-      (select_bool_reg ty (value_nonzero val_cond)
-                       (put_in_reg val_true) (put_in_reg val_false)))
-
-
-;;;; Rules for `selectif_spectre_guard` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; We do not support the `iflags` mechanism on our platform.  However, common
-;; code will unconditionally emit certain patterns using `iflags` which we
-;; need to handle somehow.  Note that only those specific patterns are
-;; recognized by the code below, other uses will fail to lower.
-
-(rule (lower (has_type ty (selectif_spectre_guard int_cc
-                             (ifcmp x y) val_true val_false)))
-      (select_bool_reg ty (icmp_val $false int_cc x y)
-                       (put_in_reg val_true) (put_in_reg val_false)))
-
-
-;;;; Rules for `jump` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Unconditional branch.  The target is found as first (and only) element in
-;; the list of the current block's branch targets passed as `targets`.
-(rule (lower_branch (jump _ _) targets)
-      (side_effect (jump_impl (vec_element targets 0))))
-
-
-;;;; Rules for `br_table` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Jump table.  `targets` contains the default target followed by the
-;; list of branch targets per index value.
-(rule (lower_branch (br_table val_idx _ _) targets)
-      (let ((idx Reg (put_in_reg_zext64 val_idx))
-            ;; Bounds-check the index and branch to default.
-            ;; This is an internal branch that is not a terminator insn.
-            ;; Instead, the default target is listed a potential target
-            ;; in the final JTSequence, which is the block terminator.
-            (cond ProducesBool
-              (bool (icmpu_uimm32 $I64 idx (vec_length_minus1 targets))
-                    (intcc_as_cond (IntCC.UnsignedGreaterThanOrEqual))))
-            (_ InstOutput (side_effect (oneway_cond_br_bool cond
-                                         (vec_element targets 0)))))
-        ;; Scale the index by the element size, and then emit the
-        ;; compound instruction that does:
-        ;;
-        ;; larl %r1, <jt-base>
-        ;; agf %r1, 0(%r1, %rScaledIndex)
-        ;; br %r1
-        ;; [jt entries]
-        ;;
-        ;; This must be *one* instruction in the vcode because
-        ;; we cannot allow regalloc to insert any spills/fills
-        ;; in the middle of the sequence; otherwise, the LARL's
-        ;; PC-rel offset to the jumptable would be incorrect.
-        ;; (The alternative is to introduce a relocation pass
-        ;; for inlined jumptables, which is much worse, IMHO.)
-        (side_effect (jt_sequence (lshl_imm $I64 idx 2) targets))))
-
-
-;;;; Rules for `brz` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Two-way conditional branch on zero.  `targets` contains:
-;; - element 0: target if the condition is true (i.e. value is zero)
-;; - element 1: target if the condition is false (i.e. value is nonzero)
-(rule (lower_branch (brz val_cond _ _) targets)
-      (side_effect (cond_br_bool (invert_bool (value_nonzero val_cond))
-                                 (vec_element targets 0)
-                                 (vec_element targets 1))))
-
-
-;;;; Rules for `brnz` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Two-way conditional branch on nonzero.  `targets` contains:
-;; - element 0: target if the condition is true (i.e. value is nonzero)
-;; - element 1: target if the condition is false (i.e. value is zero)
-(rule (lower_branch (brnz val_cond _ _) targets)
-      (side_effect (cond_br_bool (value_nonzero val_cond)
-                                 (vec_element targets 0)
-                                 (vec_element targets 1))))
-
-
-;;;; Rules for `brif` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Similarly to `selectif_spectre_guard`, we only recognize specific patterns
-;; generated by common code here.  Others will fail to lower.
-
-(rule (lower_branch (brif int_cc (ifcmp x y) _ _) targets)
-      (side_effect (cond_br_bool (icmp_val $false int_cc x y)
-                                 (vec_element targets 0)
-                                 (vec_element targets 1))))
-
-
-;;;; Rules for `trap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (trap trap_code))
-      (safepoint (trap_impl trap_code)))
-
-
-;;;; Rules for `resumable_trap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (resumable_trap trap_code))
-      (safepoint (trap_impl trap_code)))
-
-
-;;;; Rules for `trapz` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (trapz val trap_code))
-      (safepoint (trap_if_bool (invert_bool (value_nonzero val)) trap_code)))
-
-
-;;;; Rules for `trapnz` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (trapnz val trap_code))
-      (safepoint (trap_if_bool (value_nonzero val) trap_code)))
-
-
-;;;; Rules for `resumable_trapnz` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (resumable_trapnz val trap_code))
-      (safepoint (trap_if_bool (value_nonzero val) trap_code)))
-
-
-;;;; Rules for `debugtrap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (debugtrap))
-      (side_effect (debugtrap_impl)))
-
-
-;;;; Rules for `trapif` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Similarly to `selectif_spectre_guard`, we only recognize specific patterns
-;; generated by common code here.  Others will fail to lower.
-
-;; Recognize the case of `ifcmp` feeding into `trapif`.  Directly generate
-;; the desired comparison here; there is no separate `ifcmp` lowering.
-
-(rule (lower (trapif int_cc (ifcmp x y) trap_code))
-      (safepoint (trap_if_bool (icmp_val $false int_cc x y) trap_code)))
-
-;; Recognize the case of `iadd_ifcout` feeding into `trapif`.  Note that
-;; in the case, the `iadd_ifcout` is generated by a separate lowering
-;; (in order to properly handle the register output of that instruction.)
-;;
-;; The flags must not have been clobbered by any other instruction between the
-;; iadd_ifcout and this instruction, as verified by the CLIF validator; so we
-;; can simply rely on the condition code here.
-;;
-;; IaddIfcout is implemented via a ADD LOGICAL instruction, which sets the
-;; the condition code as follows:
-;;   0   Result zero; no carry
-;;   1   Result not zero; no carry
-;;   2   Result zero; carry
-;;   3   Result not zero; carry
-;; This means "carry" corresponds to condition code 2 or 3, i.e.
-;; a condition mask of 2 | 1.
-;;
-;; As this does not match any of the encodings used with a normal integer
-;; comparsion, this cannot be represented by any IntCC value.  We need to
-;; remap the IntCC::UnsignedGreaterThan value that we have here as result
-;; of the unsigned_add_overflow_condition call to the correct mask.
-
-(rule (lower (trapif (IntCC.UnsignedGreaterThan)
-                     (iadd_ifcout x y) trap_code))
-      (side_effect (trap_if_impl (mask_as_cond 3) trap_code)))
-
-
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/lower.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/lower.rs
deleted file mode 100644
index 2f181478f..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/lower.rs
+++ /dev/null
@@ -1,448 +0,0 @@
-//! Lowering rules for S390x.
-
-use crate::ir::condcodes::IntCC;
-use crate::ir::Inst as IRInst;
-use crate::ir::{MemFlags, Opcode};
-use crate::isa::s390x::abi::*;
-use crate::isa::s390x::inst::*;
-use crate::isa::s390x::settings as s390x_settings;
-use crate::isa::s390x::S390xBackend;
-use crate::machinst::lower::*;
-use crate::machinst::*;
-use crate::settings::Flags;
-use crate::CodegenResult;
-use regalloc::Reg;
-use smallvec::SmallVec;
-
-pub mod isle;
-
-//============================================================================
-// Lowering: force instruction input into a register
-
-/// Sign-extend the low `from_bits` bits of `value` to a full u64.
-fn sign_extend_to_u64(value: u64, from_bits: u8) -> u64 {
-    assert!(from_bits <= 64);
-    if from_bits >= 64 {
-        value
-    } else {
-        (((value << (64 - from_bits)) as i64) >> (64 - from_bits)) as u64
-    }
-}
-
-/// Lower an instruction input to a reg.
-fn put_input_in_reg<C: LowerCtx<I = Inst>>(ctx: &mut C, input: InsnInput) -> Reg {
-    ctx.put_input_in_regs(input.insn, input.input)
-        .only_reg()
-        .unwrap()
-}
-
-//=============================================================================
-// Lowering: comparisons
-
-/// Determines whether this condcode interprets inputs as signed or
-/// unsigned.  See the documentation for the `icmp` instruction in
-/// cranelift-codegen/meta/src/shared/instructions.rs for further insights
-/// into this.
-pub fn condcode_is_signed(cc: IntCC) -> bool {
-    match cc {
-        IntCC::Equal => false,
-        IntCC::NotEqual => false,
-        IntCC::SignedGreaterThanOrEqual => true,
-        IntCC::SignedGreaterThan => true,
-        IntCC::SignedLessThanOrEqual => true,
-        IntCC::SignedLessThan => true,
-        IntCC::UnsignedGreaterThanOrEqual => false,
-        IntCC::UnsignedGreaterThan => false,
-        IntCC::UnsignedLessThanOrEqual => false,
-        IntCC::UnsignedLessThan => false,
-        IntCC::Overflow => true,
-        IntCC::NotOverflow => true,
-    }
-}
-
-//============================================================================
-// Lowering: main entry point for lowering a instruction
-
-fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    insn: IRInst,
-    flags: &Flags,
-    isa_flags: &s390x_settings::Flags,
-) -> CodegenResult<()> {
-    let op = ctx.data(insn).opcode();
-    let inputs: SmallVec<[InsnInput; 4]> = (0..ctx.num_inputs(insn))
-        .map(|i| InsnInput { insn, input: i })
-        .collect();
-    let outputs: SmallVec<[InsnOutput; 2]> = (0..ctx.num_outputs(insn))
-        .map(|i| InsnOutput { insn, output: i })
-        .collect();
-    let ty = if outputs.len() > 0 {
-        Some(ctx.output_ty(insn, 0))
-    } else {
-        None
-    };
-
-    if let Ok(()) = super::lower::isle::lower(ctx, flags, isa_flags, &outputs, insn) {
-        return Ok(());
-    }
-
-    let implemented_in_isle = || {
-        unreachable!(
-            "implemented in ISLE: inst = `{}`, type = `{:?}`",
-            ctx.dfg().display_inst(insn),
-            ty
-        );
-    };
-
-    match op {
-        Opcode::Nop
-        | Opcode::Copy
-        | Opcode::Iconst
-        | Opcode::Bconst
-        | Opcode::F32const
-        | Opcode::F64const
-        | Opcode::Null
-        | Opcode::Iadd
-        | Opcode::IaddIfcout
-        | Opcode::Isub
-        | Opcode::Iabs
-        | Opcode::Ineg
-        | Opcode::Imul
-        | Opcode::Umulhi
-        | Opcode::Smulhi
-        | Opcode::Udiv
-        | Opcode::Urem
-        | Opcode::Sdiv
-        | Opcode::Srem
-        | Opcode::Ishl
-        | Opcode::Ushr
-        | Opcode::Sshr
-        | Opcode::Rotr
-        | Opcode::Rotl
-        | Opcode::Ireduce
-        | Opcode::Uextend
-        | Opcode::Sextend
-        | Opcode::Bnot
-        | Opcode::Band
-        | Opcode::Bor
-        | Opcode::Bxor
-        | Opcode::BandNot
-        | Opcode::BorNot
-        | Opcode::BxorNot
-        | Opcode::Bitselect
-        | Opcode::Breduce
-        | Opcode::Bextend
-        | Opcode::Bmask
-        | Opcode::Bint
-        | Opcode::Clz
-        | Opcode::Cls
-        | Opcode::Ctz
-        | Opcode::Popcnt
-        | Opcode::Fadd
-        | Opcode::Fsub
-        | Opcode::Fmul
-        | Opcode::Fdiv
-        | Opcode::Fmin
-        | Opcode::Fmax
-        | Opcode::Sqrt
-        | Opcode::Fneg
-        | Opcode::Fabs
-        | Opcode::Fpromote
-        | Opcode::Fdemote
-        | Opcode::Ceil
-        | Opcode::Floor
-        | Opcode::Trunc
-        | Opcode::Nearest
-        | Opcode::Fma
-        | Opcode::Fcopysign
-        | Opcode::FcvtFromUint
-        | Opcode::FcvtFromSint
-        | Opcode::FcvtToUint
-        | Opcode::FcvtToSint
-        | Opcode::FcvtToUintSat
-        | Opcode::FcvtToSintSat
-        | Opcode::Bitcast
-        | Opcode::Load
-        | Opcode::Uload8
-        | Opcode::Sload8
-        | Opcode::Uload16
-        | Opcode::Sload16
-        | Opcode::Uload32
-        | Opcode::Sload32
-        | Opcode::Store
-        | Opcode::Istore8
-        | Opcode::Istore16
-        | Opcode::Istore32
-        | Opcode::AtomicRmw
-        | Opcode::AtomicCas
-        | Opcode::AtomicLoad
-        | Opcode::AtomicStore
-        | Opcode::Fence
-        | Opcode::Icmp
-        | Opcode::Fcmp
-        | Opcode::IsNull
-        | Opcode::IsInvalid
-        | Opcode::Select
-        | Opcode::SelectifSpectreGuard
-        | Opcode::Trap
-        | Opcode::ResumableTrap
-        | Opcode::Trapz
-        | Opcode::Trapnz
-        | Opcode::ResumableTrapnz
-        | Opcode::Trapif
-        | Opcode::Debugtrap
-        | Opcode::StackAddr
-        | Opcode::FuncAddr
-        | Opcode::SymbolValue => implemented_in_isle(),
-
-        Opcode::UaddSat | Opcode::SaddSat => unimplemented!(),
-        Opcode::UsubSat | Opcode::SsubSat => unimplemented!(),
-
-        Opcode::Bitrev => unimplemented!(),
-
-        Opcode::FcvtLowFromSint => unimplemented!("FcvtLowFromSint"),
-
-        Opcode::StackLoad | Opcode::StackStore => {
-            panic!("Direct stack memory access not supported; should not be used by Wasm");
-        }
-
-        Opcode::ConstAddr => unimplemented!(),
-
-        Opcode::HeapAddr => {
-            panic!("heap_addr should have been removed by legalization!");
-        }
-
-        Opcode::TableAddr => {
-            panic!("table_addr should have been removed by legalization!");
-        }
-
-        Opcode::GlobalValue => {
-            panic!("global_value should have been removed by legalization!");
-        }
-
-        Opcode::TlsValue => {
-            unimplemented!("Thread-local storage support not implemented!");
-        }
-
-        Opcode::GetPinnedReg | Opcode::SetPinnedReg => {
-            unimplemented!("Pinned register support not implemented!");
-        }
-
-        Opcode::Call | Opcode::CallIndirect => {
-            let caller_conv = ctx.abi().call_conv();
-            let (mut abi, inputs) = match op {
-                Opcode::Call => {
-                    let (extname, dist) = ctx.call_target(insn).unwrap();
-                    let extname = extname.clone();
-                    let sig = ctx.call_sig(insn).unwrap();
-                    assert!(inputs.len() == sig.params.len());
-                    assert!(outputs.len() == sig.returns.len());
-                    (
-                        S390xABICaller::from_func(sig, &extname, dist, caller_conv, flags)?,
-                        &inputs[..],
-                    )
-                }
-                Opcode::CallIndirect => {
-                    let ptr = put_input_in_reg(ctx, inputs[0]);
-                    let sig = ctx.call_sig(insn).unwrap();
-                    assert!(inputs.len() - 1 == sig.params.len());
-                    assert!(outputs.len() == sig.returns.len());
-                    (
-                        S390xABICaller::from_ptr(sig, ptr, op, caller_conv, flags)?,
-                        &inputs[1..],
-                    )
-                }
-                _ => unreachable!(),
-            };
-
-            assert!(inputs.len() == abi.num_args());
-            for (i, input) in inputs.iter().enumerate() {
-                let arg_reg = put_input_in_reg(ctx, *input);
-                abi.emit_copy_regs_to_arg(ctx, i, ValueRegs::one(arg_reg));
-            }
-            abi.emit_call(ctx);
-            for (i, output) in outputs.iter().enumerate() {
-                let retval_reg = get_output_reg(ctx, *output).only_reg().unwrap();
-                abi.emit_copy_retval_to_regs(ctx, i, ValueRegs::one(retval_reg));
-            }
-            abi.accumulate_outgoing_args_size(ctx);
-        }
-
-        Opcode::FallthroughReturn | Opcode::Return => {
-            for (i, input) in inputs.iter().enumerate() {
-                let reg = put_input_in_reg(ctx, *input);
-                let retval_reg = ctx.retval(i).only_reg().unwrap();
-                let ty = ctx.input_ty(insn, i);
-                ctx.emit(Inst::gen_move(retval_reg, reg, ty));
-            }
-            // N.B.: the Ret itself is generated by the ABI.
-        }
-
-        Opcode::RawBitcast
-        | Opcode::Splat
-        | Opcode::Swizzle
-        | Opcode::Insertlane
-        | Opcode::Extractlane
-        | Opcode::Imin
-        | Opcode::Umin
-        | Opcode::Imax
-        | Opcode::Umax
-        | Opcode::AvgRound
-        | Opcode::FminPseudo
-        | Opcode::FmaxPseudo
-        | Opcode::Uload8x8
-        | Opcode::Uload8x8Complex
-        | Opcode::Sload8x8
-        | Opcode::Sload8x8Complex
-        | Opcode::Uload16x4
-        | Opcode::Uload16x4Complex
-        | Opcode::Sload16x4
-        | Opcode::Sload16x4Complex
-        | Opcode::Uload32x2
-        | Opcode::Uload32x2Complex
-        | Opcode::Sload32x2
-        | Opcode::Sload32x2Complex
-        | Opcode::Vconst
-        | Opcode::Shuffle
-        | Opcode::Vsplit
-        | Opcode::Vconcat
-        | Opcode::Vselect
-        | Opcode::VanyTrue
-        | Opcode::VallTrue
-        | Opcode::VhighBits
-        | Opcode::ScalarToVector
-        | Opcode::Snarrow
-        | Opcode::Unarrow
-        | Opcode::Uunarrow
-        | Opcode::SwidenLow
-        | Opcode::SwidenHigh
-        | Opcode::UwidenLow
-        | Opcode::UwidenHigh
-        | Opcode::WideningPairwiseDotProductS
-        | Opcode::SqmulRoundSat
-        | Opcode::FvpromoteLow
-        | Opcode::Fvdemote
-        | Opcode::IaddPairwise => {
-            // TODO
-            unimplemented!("Vector ops not implemented.");
-        }
-
-        Opcode::Isplit | Opcode::Iconcat => unimplemented!("Wide integer ops not implemented."),
-
-        Opcode::IfcmpSp => {
-            panic!("Unused opcode should not be encountered.");
-        }
-
-        Opcode::LoadComplex
-        | Opcode::Uload8Complex
-        | Opcode::Sload8Complex
-        | Opcode::Uload16Complex
-        | Opcode::Sload16Complex
-        | Opcode::Uload32Complex
-        | Opcode::Sload32Complex
-        | Opcode::StoreComplex
-        | Opcode::Istore8Complex
-        | Opcode::Istore16Complex
-        | Opcode::Istore32Complex => {
-            panic!("Load/store complex opcode should not be encountered.");
-        }
-
-        Opcode::Ifcmp
-        | Opcode::Ffcmp
-        | Opcode::Trapff
-        | Opcode::Trueif
-        | Opcode::Trueff
-        | Opcode::Selectif => {
-            panic!("Flags opcode should not be encountered.");
-        }
-
-        Opcode::Jump
-        | Opcode::Brz
-        | Opcode::Brnz
-        | Opcode::BrIcmp
-        | Opcode::Brif
-        | Opcode::Brff
-        | Opcode::BrTable => {
-            panic!("Branch opcode reached non-branch lowering logic!");
-        }
-
-        Opcode::IaddImm
-        | Opcode::ImulImm
-        | Opcode::UdivImm
-        | Opcode::SdivImm
-        | Opcode::UremImm
-        | Opcode::SremImm
-        | Opcode::IrsubImm
-        | Opcode::IaddCin
-        | Opcode::IaddIfcin
-        | Opcode::IaddCout
-        | Opcode::IaddCarry
-        | Opcode::IaddIfcarry
-        | Opcode::IsubBin
-        | Opcode::IsubIfbin
-        | Opcode::IsubBout
-        | Opcode::IsubIfbout
-        | Opcode::IsubBorrow
-        | Opcode::IsubIfborrow
-        | Opcode::BandImm
-        | Opcode::BorImm
-        | Opcode::BxorImm
-        | Opcode::RotlImm
-        | Opcode::RotrImm
-        | Opcode::IshlImm
-        | Opcode::UshrImm
-        | Opcode::SshrImm
-        | Opcode::IcmpImm
-        | Opcode::IfcmpImm => {
-            panic!("ALU+imm and ALU+carry ops should not appear here!");
-        }
-    }
-
-    Ok(())
-}
-
-//=============================================================================
-// Lowering-backend trait implementation.
-
-impl LowerBackend for S390xBackend {
-    type MInst = Inst;
-
-    fn lower<C: LowerCtx<I = Inst>>(&self, ctx: &mut C, ir_inst: IRInst) -> CodegenResult<()> {
-        lower_insn_to_regs(ctx, ir_inst, &self.flags, &self.isa_flags)
-    }
-
-    fn lower_branch_group<C: LowerCtx<I = Inst>>(
-        &self,
-        ctx: &mut C,
-        branches: &[IRInst],
-        targets: &[MachLabel],
-    ) -> CodegenResult<()> {
-        // A block should end with at most two branches. The first may be a
-        // conditional branch; a conditional branch can be followed only by an
-        // unconditional branch or fallthrough. Otherwise, if only one branch,
-        // it may be an unconditional branch, a fallthrough, a return, or a
-        // trap. These conditions are verified by `is_ebb_basic()` during the
-        // verifier pass.
-        assert!(branches.len() <= 2);
-        if branches.len() == 2 {
-            let op1 = ctx.data(branches[1]).opcode();
-            assert!(op1 == Opcode::Jump);
-        }
-
-        // Lower the first branch in ISLE.  This will automatically handle
-        // the second branch (if any) by emitting a two-way conditional branch.
-        if let Ok(()) = super::lower::isle::lower_branch(
-            ctx,
-            &self.flags,
-            &self.isa_flags,
-            branches[0],
-            targets,
-        ) {
-            return Ok(());
-        }
-        unreachable!(
-            "implemented in ISLE: branch = `{}`",
-            ctx.dfg().display_inst(branches[0]),
-        );
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/lower/isle.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/lower/isle.rs
deleted file mode 100644
index 0d7d1fecf..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/lower/isle.rs
+++ /dev/null
@@ -1,533 +0,0 @@
-//! ISLE integration glue code for s390x lowering.
-
-// Pull in the ISLE generated code.
-pub mod generated_code;
-
-// Types that the generated ISLE code uses via `use super::*`.
-use super::{
-    CallIndInfo, CallInfo, Cond, Inst as MInst, MachLabel, MemArg, MemFlags, Opcode, Reg,
-    UImm16Shifted, UImm32Shifted,
-};
-use crate::isa::s390x::settings::Flags as IsaFlags;
-use crate::machinst::isle::*;
-use crate::settings::Flags;
-use crate::{
-    ir::{
-        condcodes::*, immediates::*, types::*, AtomicRmwOp, Endianness, Inst, InstructionData,
-        StackSlot, TrapCode, Value, ValueLabel, ValueList,
-    },
-    isa::s390x::inst::s390x_map_regs,
-    isa::unwind::UnwindInst,
-    machinst::{InsnOutput, LowerCtx},
-};
-use std::boxed::Box;
-use std::cell::Cell;
-use std::convert::TryFrom;
-use std::vec::Vec;
-
-type BoxCallInfo = Box<CallInfo>;
-type BoxCallIndInfo = Box<CallIndInfo>;
-type VecMachLabel = Vec<MachLabel>;
-type BoxExternalName = Box<ExternalName>;
-type VecMInst = Vec<MInst>;
-type VecMInstBuilder = Cell<Vec<MInst>>;
-
-/// The main entry point for lowering with ISLE.
-pub(crate) fn lower<C>(
-    lower_ctx: &mut C,
-    flags: &Flags,
-    isa_flags: &IsaFlags,
-    outputs: &[InsnOutput],
-    inst: Inst,
-) -> Result<(), ()>
-where
-    C: LowerCtx<I = MInst>,
-{
-    lower_common(
-        lower_ctx,
-        flags,
-        isa_flags,
-        outputs,
-        inst,
-        |cx, insn| generated_code::constructor_lower(cx, insn),
-        s390x_map_regs,
-    )
-}
-
-/// The main entry point for branch lowering with ISLE.
-pub(crate) fn lower_branch<C>(
-    lower_ctx: &mut C,
-    flags: &Flags,
-    isa_flags: &IsaFlags,
-    branch: Inst,
-    targets: &[MachLabel],
-) -> Result<(), ()>
-where
-    C: LowerCtx<I = MInst>,
-{
-    lower_common(
-        lower_ctx,
-        flags,
-        isa_flags,
-        &[],
-        branch,
-        |cx, insn| generated_code::constructor_lower_branch(cx, insn, &targets.to_vec()),
-        s390x_map_regs,
-    )
-}
-
-impl<C> generated_code::Context for IsleContext<'_, C, Flags, IsaFlags, 6>
-where
-    C: LowerCtx<I = MInst>,
-{
-    isle_prelude_methods!();
-
-    #[inline]
-    fn allow_div_traps(&mut self, _: Type) -> Option<()> {
-        if !self.flags.avoid_div_traps() {
-            Some(())
-        } else {
-            None
-        }
-    }
-
-    #[inline]
-    fn mie2_enabled(&mut self, _: Type) -> Option<()> {
-        if self.isa_flags.has_mie2() {
-            Some(())
-        } else {
-            None
-        }
-    }
-
-    #[inline]
-    fn mie2_disabled(&mut self, _: Type) -> Option<()> {
-        if !self.isa_flags.has_mie2() {
-            Some(())
-        } else {
-            None
-        }
-    }
-
-    #[inline]
-    fn vxrs_ext2_enabled(&mut self, _: Type) -> Option<()> {
-        if self.isa_flags.has_vxrs_ext2() {
-            Some(())
-        } else {
-            None
-        }
-    }
-
-    #[inline]
-    fn vxrs_ext2_disabled(&mut self, _: Type) -> Option<()> {
-        if !self.isa_flags.has_vxrs_ext2() {
-            Some(())
-        } else {
-            None
-        }
-    }
-
-    #[inline]
-    fn writable_gpr(&mut self, regno: u8) -> WritableReg {
-        super::writable_gpr(regno)
-    }
-
-    #[inline]
-    fn zero_reg(&mut self) -> Reg {
-        super::zero_reg()
-    }
-
-    #[inline]
-    fn gpr32_ty(&mut self, ty: Type) -> Option<Type> {
-        match ty {
-            I8 | I16 | I32 | B1 | B8 | B16 | B32 => Some(ty),
-            _ => None,
-        }
-    }
-
-    #[inline]
-    fn gpr64_ty(&mut self, ty: Type) -> Option<Type> {
-        match ty {
-            I64 | B64 | R64 => Some(ty),
-            _ => None,
-        }
-    }
-
-    #[inline]
-    fn uimm32shifted(&mut self, n: u32, shift: u8) -> UImm32Shifted {
-        UImm32Shifted::maybe_with_shift(n, shift).unwrap()
-    }
-
-    #[inline]
-    fn uimm16shifted(&mut self, n: u16, shift: u8) -> UImm16Shifted {
-        UImm16Shifted::maybe_with_shift(n, shift).unwrap()
-    }
-
-    #[inline]
-    fn i64_nonequal(&mut self, val: i64, cmp: i64) -> Option<i64> {
-        if val != cmp {
-            Some(val)
-        } else {
-            None
-        }
-    }
-
-    #[inline]
-    fn u8_as_u16(&mut self, n: u8) -> u16 {
-        n as u16
-    }
-
-    #[inline]
-    fn u64_as_u32(&mut self, n: u64) -> u32 {
-        n as u32
-    }
-
-    #[inline]
-    fn u64_as_i16(&mut self, n: u64) -> i16 {
-        n as i16
-    }
-
-    #[inline]
-    fn u64_nonzero_hipart(&mut self, n: u64) -> Option<u64> {
-        let part = n & 0xffff_ffff_0000_0000;
-        if part != 0 {
-            Some(part)
-        } else {
-            None
-        }
-    }
-
-    #[inline]
-    fn u64_nonzero_lopart(&mut self, n: u64) -> Option<u64> {
-        let part = n & 0x0000_0000_ffff_ffff;
-        if part != 0 {
-            Some(part)
-        } else {
-            None
-        }
-    }
-
-    #[inline]
-    fn i32_from_u64(&mut self, n: u64) -> Option<i32> {
-        if let Ok(imm) = i32::try_from(n as i64) {
-            Some(imm)
-        } else {
-            None
-        }
-    }
-
-    #[inline]
-    fn i16_from_u64(&mut self, n: u64) -> Option<i16> {
-        if let Ok(imm) = i16::try_from(n as i64) {
-            Some(imm)
-        } else {
-            None
-        }
-    }
-
-    #[inline]
-    fn uimm32shifted_from_u64(&mut self, n: u64) -> Option<UImm32Shifted> {
-        UImm32Shifted::maybe_from_u64(n)
-    }
-
-    #[inline]
-    fn uimm16shifted_from_u64(&mut self, n: u64) -> Option<UImm16Shifted> {
-        UImm16Shifted::maybe_from_u64(n)
-    }
-
-    #[inline]
-    fn u64_from_value(&mut self, val: Value) -> Option<u64> {
-        let inst = self.lower_ctx.dfg().value_def(val).inst()?;
-        let constant = self.lower_ctx.get_constant(inst)?;
-        Some(constant)
-    }
-
-    #[inline]
-    fn u32_from_value(&mut self, val: Value) -> Option<u32> {
-        let constant = self.u64_from_value(val)?;
-        let imm = u32::try_from(constant).ok()?;
-        Some(imm)
-    }
-
-    #[inline]
-    fn u8_from_value(&mut self, val: Value) -> Option<u8> {
-        let constant = self.u64_from_value(val)?;
-        let imm = u8::try_from(constant).ok()?;
-        Some(imm)
-    }
-
-    #[inline]
-    fn u64_from_signed_value(&mut self, val: Value) -> Option<u64> {
-        let inst = self.lower_ctx.dfg().value_def(val).inst()?;
-        let constant = self.lower_ctx.get_constant(inst)?;
-        let ty = self.lower_ctx.output_ty(inst, 0);
-        Some(super::sign_extend_to_u64(constant, self.ty_bits(ty)))
-    }
-
-    #[inline]
-    fn i64_from_value(&mut self, val: Value) -> Option<i64> {
-        let constant = self.u64_from_signed_value(val)? as i64;
-        Some(constant)
-    }
-
-    #[inline]
-    fn i32_from_value(&mut self, val: Value) -> Option<i32> {
-        let constant = self.u64_from_signed_value(val)? as i64;
-        let imm = i32::try_from(constant).ok()?;
-        Some(imm)
-    }
-
-    #[inline]
-    fn i16_from_value(&mut self, val: Value) -> Option<i16> {
-        let constant = self.u64_from_signed_value(val)? as i64;
-        let imm = i16::try_from(constant).ok()?;
-        Some(imm)
-    }
-
-    #[inline]
-    fn i16_from_swapped_value(&mut self, val: Value) -> Option<i16> {
-        let constant = self.u64_from_signed_value(val)? as i64;
-        let imm = i16::try_from(constant).ok()?;
-        Some(imm.swap_bytes())
-    }
-
-    #[inline]
-    fn i64_from_negated_value(&mut self, val: Value) -> Option<i64> {
-        let constant = self.u64_from_signed_value(val)? as i64;
-        let imm = -constant;
-        Some(imm)
-    }
-
-    #[inline]
-    fn i32_from_negated_value(&mut self, val: Value) -> Option<i32> {
-        let constant = self.u64_from_signed_value(val)? as i64;
-        let imm = i32::try_from(-constant).ok()?;
-        Some(imm)
-    }
-
-    #[inline]
-    fn i16_from_negated_value(&mut self, val: Value) -> Option<i16> {
-        let constant = self.u64_from_signed_value(val)? as i64;
-        let imm = i16::try_from(-constant).ok()?;
-        Some(imm)
-    }
-
-    #[inline]
-    fn uimm16shifted_from_value(&mut self, val: Value) -> Option<UImm16Shifted> {
-        let constant = self.u64_from_value(val)?;
-        UImm16Shifted::maybe_from_u64(constant)
-    }
-
-    #[inline]
-    fn uimm32shifted_from_value(&mut self, val: Value) -> Option<UImm32Shifted> {
-        let constant = self.u64_from_value(val)?;
-        UImm32Shifted::maybe_from_u64(constant)
-    }
-
-    #[inline]
-    fn uimm16shifted_from_inverted_value(&mut self, val: Value) -> Option<UImm16Shifted> {
-        let constant = self.u64_from_value(val)?;
-        let imm = UImm16Shifted::maybe_from_u64(!constant)?;
-        Some(imm.negate_bits())
-    }
-
-    #[inline]
-    fn uimm32shifted_from_inverted_value(&mut self, val: Value) -> Option<UImm32Shifted> {
-        let constant = self.u64_from_value(val)?;
-        let imm = UImm32Shifted::maybe_from_u64(!constant)?;
-        Some(imm.negate_bits())
-    }
-
-    #[inline]
-    fn mask_amt_imm(&mut self, ty: Type, amt: i64) -> u8 {
-        let mask = self.ty_bits(ty) - 1;
-        (amt as u8) & mask
-    }
-
-    #[inline]
-    fn mask_as_cond(&mut self, mask: u8) -> Cond {
-        Cond::from_mask(mask)
-    }
-
-    #[inline]
-    fn intcc_as_cond(&mut self, cc: &IntCC) -> Cond {
-        Cond::from_intcc(*cc)
-    }
-
-    #[inline]
-    fn floatcc_as_cond(&mut self, cc: &FloatCC) -> Cond {
-        Cond::from_floatcc(*cc)
-    }
-
-    #[inline]
-    fn invert_cond(&mut self, cond: &Cond) -> Cond {
-        Cond::invert(*cond)
-    }
-
-    #[inline]
-    fn signed(&mut self, cc: &IntCC) -> Option<()> {
-        if super::condcode_is_signed(*cc) {
-            Some(())
-        } else {
-            None
-        }
-    }
-
-    #[inline]
-    fn unsigned(&mut self, cc: &IntCC) -> Option<()> {
-        if !super::condcode_is_signed(*cc) {
-            Some(())
-        } else {
-            None
-        }
-    }
-
-    #[inline]
-    fn vec_length_minus1(&mut self, vec: &VecMachLabel) -> u32 {
-        u32::try_from(vec.len()).unwrap() - 1
-    }
-
-    #[inline]
-    fn vec_element(&mut self, vec: &VecMachLabel, index: u8) -> MachLabel {
-        vec[usize::from(index)]
-    }
-
-    #[inline]
-    fn zero_offset(&mut self) -> Offset32 {
-        Offset32::new(0)
-    }
-
-    #[inline]
-    fn i64_from_offset(&mut self, off: Offset32) -> i64 {
-        i64::from(off)
-    }
-
-    #[inline]
-    fn littleendian(&mut self, flags: MemFlags) -> Option<()> {
-        let endianness = flags.endianness(Endianness::Big);
-        if endianness == Endianness::Little {
-            Some(())
-        } else {
-            None
-        }
-    }
-
-    #[inline]
-    fn bigendian(&mut self, flags: MemFlags) -> Option<()> {
-        let endianness = flags.endianness(Endianness::Big);
-        if endianness == Endianness::Big {
-            Some(())
-        } else {
-            None
-        }
-    }
-
-    #[inline]
-    fn box_external_name(&mut self, name: ExternalName) -> BoxExternalName {
-        Box::new(name)
-    }
-
-    #[inline]
-    fn memflags_trusted(&mut self) -> MemFlags {
-        MemFlags::trusted()
-    }
-
-    #[inline]
-    fn memarg_reg_plus_reg(&mut self, x: Reg, y: Reg, flags: MemFlags) -> MemArg {
-        MemArg::reg_plus_reg(x, y, flags)
-    }
-
-    #[inline]
-    fn memarg_reg_plus_off(&mut self, reg: Reg, off: i64, flags: MemFlags) -> MemArg {
-        MemArg::reg_plus_off(reg, off, flags)
-    }
-
-    #[inline]
-    fn memarg_symbol(&mut self, name: ExternalName, offset: i32, flags: MemFlags) -> MemArg {
-        MemArg::Symbol {
-            name: Box::new(name),
-            offset,
-            flags,
-        }
-    }
-
-    #[inline]
-    fn memarg_symbol_offset_sum(&mut self, off1: i64, off2: i64) -> Option<i32> {
-        let off = i32::try_from(off1 + off2).ok()?;
-        if off & 1 == 0 {
-            Some(off)
-        } else {
-            None
-        }
-    }
-
-    #[inline]
-    fn abi_stackslot_addr(
-        &mut self,
-        dst: WritableReg,
-        stack_slot: StackSlot,
-        offset: Offset32,
-    ) -> MInst {
-        let offset = u32::try_from(i32::from(offset)).unwrap();
-        self.lower_ctx.abi().stackslot_addr(stack_slot, offset, dst)
-    }
-
-    #[inline]
-    fn inst_builder_new(&mut self) -> VecMInstBuilder {
-        Cell::new(Vec::<MInst>::new())
-    }
-
-    #[inline]
-    fn inst_builder_push(&mut self, builder: &VecMInstBuilder, inst: &MInst) -> Unit {
-        let mut vec = builder.take();
-        vec.push(inst.clone());
-        builder.set(vec);
-    }
-
-    #[inline]
-    fn inst_builder_finish(&mut self, builder: &VecMInstBuilder) -> Vec<MInst> {
-        builder.take()
-    }
-
-    #[inline]
-    fn real_reg(&mut self, reg: WritableReg) -> Option<WritableReg> {
-        if reg.to_reg().is_real() {
-            Some(reg)
-        } else {
-            None
-        }
-    }
-
-    #[inline]
-    fn same_reg(&mut self, src: Reg, dst: WritableReg) -> Option<()> {
-        if dst.to_reg() == src {
-            Some(())
-        } else {
-            None
-        }
-    }
-
-    #[inline]
-    fn sinkable_inst(&mut self, val: Value) -> Option<Inst> {
-        let input = self.lower_ctx.get_value_as_source_or_const(val);
-        if let Some((inst, 0)) = input.inst {
-            return Some(inst);
-        }
-        None
-    }
-
-    #[inline]
-    fn sink_inst(&mut self, inst: Inst) -> Unit {
-        self.lower_ctx.sink_inst(inst);
-    }
-
-    #[inline]
-    fn emit(&mut self, inst: &MInst) -> Unit {
-        self.emitted_insts.push((inst.clone(), false));
-    }
-
-    #[inline]
-    fn emit_safepoint(&mut self, inst: &MInst) -> Unit {
-        self.emitted_insts.push((inst.clone(), true));
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/lower/isle/generated_code.manifest b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/lower/isle/generated_code.manifest
deleted file mode 100644
index f72035cd1..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/lower/isle/generated_code.manifest
+++ /dev/null
@@ -1,4 +0,0 @@
-src/clif.isle 9ea75a6f790b5c03
-src/prelude.isle b2bc986bcbbbb77
-src/isa/s390x/inst.isle d91a16074ab186a8
-src/isa/s390x/lower.isle 1cc5a12adc8c75f9
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/lower/isle/generated_code.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/lower/isle/generated_code.rs
deleted file mode 100644
index 09fbd7b4c..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/lower/isle/generated_code.rs
+++ /dev/null
@@ -1,13743 +0,0 @@
-// GENERATED BY ISLE. DO NOT EDIT!
-//
-// Generated automatically from the instruction-selection DSL code in:
-// - src/clif.isle
-// - src/prelude.isle
-// - src/isa/s390x/inst.isle
-// - src/isa/s390x/lower.isle
-
-#![allow(dead_code, unreachable_code, unreachable_patterns)]
-#![allow(unused_imports, unused_variables, non_snake_case)]
-#![allow(irrefutable_let_patterns)]
-
-use super::*; // Pulls in all external types.
-
-/// Context during lowering: an implementation of this trait
-/// must be provided with all external constructors and extractors.
-/// A mutable borrow is passed along through all lowering logic.
-pub trait Context {
-    fn unpack_value_array_2(&mut self, arg0: &ValueArray2) -> (Value, Value);
-    fn pack_value_array_2(&mut self, arg0: Value, arg1: Value) -> ValueArray2;
-    fn unpack_value_array_3(&mut self, arg0: &ValueArray3) -> (Value, Value, Value);
-    fn pack_value_array_3(&mut self, arg0: Value, arg1: Value, arg2: Value) -> ValueArray3;
-    fn u32_add(&mut self, arg0: u32, arg1: u32) -> u32;
-    fn u8_and(&mut self, arg0: u8, arg1: u8) -> u8;
-    fn value_reg(&mut self, arg0: Reg) -> ValueRegs;
-    fn value_regs(&mut self, arg0: Reg, arg1: Reg) -> ValueRegs;
-    fn value_regs_invalid(&mut self) -> ValueRegs;
-    fn output_none(&mut self) -> InstOutput;
-    fn output(&mut self, arg0: ValueRegs) -> InstOutput;
-    fn output_pair(&mut self, arg0: ValueRegs, arg1: ValueRegs) -> InstOutput;
-    fn output_builder_new(&mut self) -> InstOutputBuilder;
-    fn output_builder_push(&mut self, arg0: &InstOutputBuilder, arg1: ValueRegs) -> Unit;
-    fn output_builder_finish(&mut self, arg0: &InstOutputBuilder) -> InstOutput;
-    fn temp_writable_reg(&mut self, arg0: Type) -> WritableReg;
-    fn invalid_reg(&mut self) -> Reg;
-    fn put_in_reg(&mut self, arg0: Value) -> Reg;
-    fn put_in_regs(&mut self, arg0: Value) -> ValueRegs;
-    fn value_regs_get(&mut self, arg0: ValueRegs, arg1: usize) -> Reg;
-    fn u8_as_u64(&mut self, arg0: u8) -> u64;
-    fn u16_as_u64(&mut self, arg0: u16) -> u64;
-    fn u32_as_u64(&mut self, arg0: u32) -> u64;
-    fn i64_as_u64(&mut self, arg0: i64) -> u64;
-    fn u64_add(&mut self, arg0: u64, arg1: u64) -> u64;
-    fn u64_sub(&mut self, arg0: u64, arg1: u64) -> u64;
-    fn u64_and(&mut self, arg0: u64, arg1: u64) -> u64;
-    fn ty_bits(&mut self, arg0: Type) -> u8;
-    fn ty_bits_u16(&mut self, arg0: Type) -> u16;
-    fn ty_bits_u64(&mut self, arg0: Type) -> u64;
-    fn ty_mask(&mut self, arg0: Type) -> u64;
-    fn ty_bytes(&mut self, arg0: Type) -> u16;
-    fn lane_type(&mut self, arg0: Type) -> Type;
-    fn fits_in_16(&mut self, arg0: Type) -> Option<Type>;
-    fn fits_in_32(&mut self, arg0: Type) -> Option<Type>;
-    fn fits_in_64(&mut self, arg0: Type) -> Option<Type>;
-    fn ty_32_or_64(&mut self, arg0: Type) -> Option<Type>;
-    fn ty_8_or_16(&mut self, arg0: Type) -> Option<Type>;
-    fn ty_int_bool_64(&mut self, arg0: Type) -> Option<Type>;
-    fn ty_int_bool_128(&mut self, arg0: Type) -> Option<Type>;
-    fn vec128(&mut self, arg0: Type) -> Option<Type>;
-    fn not_i64x2(&mut self, arg0: Type) -> Option<()>;
-    fn value_list_slice(&mut self, arg0: ValueList) -> ValueSlice;
-    fn value_slice_empty(&mut self, arg0: ValueSlice) -> Option<()>;
-    fn value_slice_unwrap(&mut self, arg0: ValueSlice) -> Option<(Value, ValueSlice)>;
-    fn value_slice_len(&mut self, arg0: ValueSlice) -> usize;
-    fn value_slice_get(&mut self, arg0: ValueSlice, arg1: usize) -> Value;
-    fn writable_reg_to_reg(&mut self, arg0: WritableReg) -> Reg;
-    fn u8_from_uimm8(&mut self, arg0: Uimm8) -> u8;
-    fn u64_from_imm64(&mut self, arg0: Imm64) -> u64;
-    fn nonzero_u64_from_imm64(&mut self, arg0: Imm64) -> Option<u64>;
-    fn u64_from_ieee32(&mut self, arg0: Ieee32) -> u64;
-    fn u64_from_ieee64(&mut self, arg0: Ieee64) -> u64;
-    fn inst_results(&mut self, arg0: Inst) -> ValueSlice;
-    fn first_result(&mut self, arg0: Inst) -> Option<Value>;
-    fn inst_data(&mut self, arg0: Inst) -> InstructionData;
-    fn value_type(&mut self, arg0: Value) -> Type;
-    fn multi_lane(&mut self, arg0: Type) -> Option<(u8, u16)>;
-    fn def_inst(&mut self, arg0: Value) -> Option<Inst>;
-    fn emit(&mut self, arg0: &MInst) -> Unit;
-    fn emit_safepoint(&mut self, arg0: &MInst) -> Unit;
-    fn trap_code_division_by_zero(&mut self) -> TrapCode;
-    fn trap_code_integer_overflow(&mut self) -> TrapCode;
-    fn trap_code_bad_conversion_to_integer(&mut self) -> TrapCode;
-    fn avoid_div_traps(&mut self, arg0: Type) -> Option<()>;
-    fn func_ref_data(&mut self, arg0: FuncRef) -> (SigRef, ExternalName, RelocDistance);
-    fn symbol_value_data(
-        &mut self,
-        arg0: GlobalValue,
-    ) -> Option<(ExternalName, RelocDistance, i64)>;
-    fn reloc_distance_near(&mut self, arg0: RelocDistance) -> Option<()>;
-    fn mie2_enabled(&mut self, arg0: Type) -> Option<()>;
-    fn mie2_disabled(&mut self, arg0: Type) -> Option<()>;
-    fn vxrs_ext2_enabled(&mut self, arg0: Type) -> Option<()>;
-    fn vxrs_ext2_disabled(&mut self, arg0: Type) -> Option<()>;
-    fn allow_div_traps(&mut self, arg0: Type) -> Option<()>;
-    fn writable_gpr(&mut self, arg0: u8) -> WritableReg;
-    fn zero_reg(&mut self) -> Reg;
-    fn gpr32_ty(&mut self, arg0: Type) -> Option<Type>;
-    fn gpr64_ty(&mut self, arg0: Type) -> Option<Type>;
-    fn uimm32shifted(&mut self, arg0: u32, arg1: u8) -> UImm32Shifted;
-    fn uimm16shifted(&mut self, arg0: u16, arg1: u8) -> UImm16Shifted;
-    fn i64_nonequal(&mut self, arg0: i64, arg1: i64) -> Option<i64>;
-    fn u8_as_u16(&mut self, arg0: u8) -> u16;
-    fn u64_as_u32(&mut self, arg0: u64) -> u32;
-    fn u64_as_i16(&mut self, arg0: u64) -> i16;
-    fn u64_nonzero_hipart(&mut self, arg0: u64) -> Option<u64>;
-    fn u64_nonzero_lopart(&mut self, arg0: u64) -> Option<u64>;
-    fn i32_from_u64(&mut self, arg0: u64) -> Option<i32>;
-    fn i16_from_u64(&mut self, arg0: u64) -> Option<i16>;
-    fn uimm32shifted_from_u64(&mut self, arg0: u64) -> Option<UImm32Shifted>;
-    fn uimm16shifted_from_u64(&mut self, arg0: u64) -> Option<UImm16Shifted>;
-    fn u64_from_value(&mut self, arg0: Value) -> Option<u64>;
-    fn u32_from_value(&mut self, arg0: Value) -> Option<u32>;
-    fn u8_from_value(&mut self, arg0: Value) -> Option<u8>;
-    fn u64_from_signed_value(&mut self, arg0: Value) -> Option<u64>;
-    fn i64_from_value(&mut self, arg0: Value) -> Option<i64>;
-    fn i32_from_value(&mut self, arg0: Value) -> Option<i32>;
-    fn i16_from_value(&mut self, arg0: Value) -> Option<i16>;
-    fn i16_from_swapped_value(&mut self, arg0: Value) -> Option<i16>;
-    fn i64_from_negated_value(&mut self, arg0: Value) -> Option<i64>;
-    fn i32_from_negated_value(&mut self, arg0: Value) -> Option<i32>;
-    fn i16_from_negated_value(&mut self, arg0: Value) -> Option<i16>;
-    fn uimm16shifted_from_value(&mut self, arg0: Value) -> Option<UImm16Shifted>;
-    fn uimm32shifted_from_value(&mut self, arg0: Value) -> Option<UImm32Shifted>;
-    fn uimm16shifted_from_inverted_value(&mut self, arg0: Value) -> Option<UImm16Shifted>;
-    fn uimm32shifted_from_inverted_value(&mut self, arg0: Value) -> Option<UImm32Shifted>;
-    fn mask_amt_imm(&mut self, arg0: Type, arg1: i64) -> u8;
-    fn mask_as_cond(&mut self, arg0: u8) -> Cond;
-    fn intcc_as_cond(&mut self, arg0: &IntCC) -> Cond;
-    fn floatcc_as_cond(&mut self, arg0: &FloatCC) -> Cond;
-    fn invert_cond(&mut self, arg0: &Cond) -> Cond;
-    fn signed(&mut self, arg0: &IntCC) -> Option<()>;
-    fn unsigned(&mut self, arg0: &IntCC) -> Option<()>;
-    fn vec_length_minus1(&mut self, arg0: &VecMachLabel) -> u32;
-    fn vec_element(&mut self, arg0: &VecMachLabel, arg1: u8) -> MachLabel;
-    fn zero_offset(&mut self) -> Offset32;
-    fn i64_from_offset(&mut self, arg0: Offset32) -> i64;
-    fn box_external_name(&mut self, arg0: ExternalName) -> BoxExternalName;
-    fn littleendian(&mut self, arg0: MemFlags) -> Option<()>;
-    fn bigendian(&mut self, arg0: MemFlags) -> Option<()>;
-    fn memflags_trusted(&mut self) -> MemFlags;
-    fn memarg_reg_plus_reg(&mut self, arg0: Reg, arg1: Reg, arg2: MemFlags) -> MemArg;
-    fn memarg_reg_plus_off(&mut self, arg0: Reg, arg1: i64, arg2: MemFlags) -> MemArg;
-    fn memarg_symbol(&mut self, arg0: ExternalName, arg1: i32, arg2: MemFlags) -> MemArg;
-    fn memarg_symbol_offset_sum(&mut self, arg0: i64, arg1: i64) -> Option<i32>;
-    fn abi_stackslot_addr(&mut self, arg0: WritableReg, arg1: StackSlot, arg2: Offset32) -> MInst;
-    fn sinkable_inst(&mut self, arg0: Value) -> Option<Inst>;
-    fn sink_inst(&mut self, arg0: Inst) -> Unit;
-    fn inst_builder_new(&mut self) -> VecMInstBuilder;
-    fn inst_builder_push(&mut self, arg0: &VecMInstBuilder, arg1: &MInst) -> Unit;
-    fn inst_builder_finish(&mut self, arg0: &VecMInstBuilder) -> VecMInst;
-    fn real_reg(&mut self, arg0: WritableReg) -> Option<WritableReg>;
-    fn same_reg(&mut self, arg0: Reg, arg1: WritableReg) -> Option<()>;
-}
-
-/// Internal type SideEffectNoResult: defined at src/prelude.isle line 393.
-#[derive(Clone, Debug)]
-pub enum SideEffectNoResult {
-    Inst { inst: MInst },
-}
-
-/// Internal type ProducesFlags: defined at src/prelude.isle line 415.
-#[derive(Clone, Debug)]
-pub enum ProducesFlags {
-    ProducesFlagsSideEffect { inst: MInst },
-    ProducesFlagsReturnsReg { inst: MInst, result: Reg },
-    ProducesFlagsReturnsResultWithConsumer { inst: MInst, result: Reg },
-}
-
-/// Internal type ConsumesFlags: defined at src/prelude.isle line 426.
-#[derive(Clone, Debug)]
-pub enum ConsumesFlags {
-    ConsumesFlagsReturnsResultWithProducer {
-        inst: MInst,
-        result: Reg,
-    },
-    ConsumesFlagsReturnsReg {
-        inst: MInst,
-        result: Reg,
-    },
-    ConsumesFlagsTwiceReturnsValueRegs {
-        inst1: MInst,
-        inst2: MInst,
-        result: ValueRegs,
-    },
-    ConsumesFlagsFourTimesReturnsValueRegs {
-        inst1: MInst,
-        inst2: MInst,
-        inst3: MInst,
-        inst4: MInst,
-        result: ValueRegs,
-    },
-}
-
-/// Internal type MInst: defined at src/isa/s390x/inst.isle line 2.
-#[derive(Clone, Debug)]
-pub enum MInst {
-    Nop0,
-    Nop2,
-    AluRRR {
-        alu_op: ALUOp,
-        rd: WritableReg,
-        rn: Reg,
-        rm: Reg,
-    },
-    AluRRSImm16 {
-        alu_op: ALUOp,
-        rd: WritableReg,
-        rn: Reg,
-        imm: i16,
-    },
-    AluRR {
-        alu_op: ALUOp,
-        rd: WritableReg,
-        rm: Reg,
-    },
-    AluRX {
-        alu_op: ALUOp,
-        rd: WritableReg,
-        mem: MemArg,
-    },
-    AluRSImm16 {
-        alu_op: ALUOp,
-        rd: WritableReg,
-        imm: i16,
-    },
-    AluRSImm32 {
-        alu_op: ALUOp,
-        rd: WritableReg,
-        imm: i32,
-    },
-    AluRUImm32 {
-        alu_op: ALUOp,
-        rd: WritableReg,
-        imm: u32,
-    },
-    AluRUImm16Shifted {
-        alu_op: ALUOp,
-        rd: WritableReg,
-        imm: UImm16Shifted,
-    },
-    AluRUImm32Shifted {
-        alu_op: ALUOp,
-        rd: WritableReg,
-        imm: UImm32Shifted,
-    },
-    SMulWide {
-        rn: Reg,
-        rm: Reg,
-    },
-    UMulWide {
-        rn: Reg,
-    },
-    SDivMod32 {
-        rn: Reg,
-    },
-    SDivMod64 {
-        rn: Reg,
-    },
-    UDivMod32 {
-        rn: Reg,
-    },
-    UDivMod64 {
-        rn: Reg,
-    },
-    Flogr {
-        rn: Reg,
-    },
-    ShiftRR {
-        shift_op: ShiftOp,
-        rd: WritableReg,
-        rn: Reg,
-        shift_imm: u8,
-        shift_reg: Reg,
-    },
-    RxSBG {
-        op: RxSBGOp,
-        rd: WritableReg,
-        rn: Reg,
-        start_bit: u8,
-        end_bit: u8,
-        rotate_amt: i8,
-    },
-    RxSBGTest {
-        op: RxSBGOp,
-        rd: Reg,
-        rn: Reg,
-        start_bit: u8,
-        end_bit: u8,
-        rotate_amt: i8,
-    },
-    UnaryRR {
-        op: UnaryOp,
-        rd: WritableReg,
-        rn: Reg,
-    },
-    CmpRR {
-        op: CmpOp,
-        rn: Reg,
-        rm: Reg,
-    },
-    CmpRX {
-        op: CmpOp,
-        rn: Reg,
-        mem: MemArg,
-    },
-    CmpRSImm16 {
-        op: CmpOp,
-        rn: Reg,
-        imm: i16,
-    },
-    CmpRSImm32 {
-        op: CmpOp,
-        rn: Reg,
-        imm: i32,
-    },
-    CmpRUImm32 {
-        op: CmpOp,
-        rn: Reg,
-        imm: u32,
-    },
-    CmpTrapRR {
-        op: CmpOp,
-        rn: Reg,
-        rm: Reg,
-        cond: Cond,
-        trap_code: TrapCode,
-    },
-    CmpTrapRSImm16 {
-        op: CmpOp,
-        rn: Reg,
-        imm: i16,
-        cond: Cond,
-        trap_code: TrapCode,
-    },
-    CmpTrapRUImm16 {
-        op: CmpOp,
-        rn: Reg,
-        imm: u16,
-        cond: Cond,
-        trap_code: TrapCode,
-    },
-    AtomicRmw {
-        alu_op: ALUOp,
-        rd: WritableReg,
-        rn: Reg,
-        mem: MemArg,
-    },
-    AtomicCas32 {
-        rd: WritableReg,
-        rn: Reg,
-        mem: MemArg,
-    },
-    AtomicCas64 {
-        rd: WritableReg,
-        rn: Reg,
-        mem: MemArg,
-    },
-    Fence,
-    Load32 {
-        rd: WritableReg,
-        mem: MemArg,
-    },
-    Load32ZExt8 {
-        rd: WritableReg,
-        mem: MemArg,
-    },
-    Load32SExt8 {
-        rd: WritableReg,
-        mem: MemArg,
-    },
-    Load32ZExt16 {
-        rd: WritableReg,
-        mem: MemArg,
-    },
-    Load32SExt16 {
-        rd: WritableReg,
-        mem: MemArg,
-    },
-    Load64 {
-        rd: WritableReg,
-        mem: MemArg,
-    },
-    Load64ZExt8 {
-        rd: WritableReg,
-        mem: MemArg,
-    },
-    Load64SExt8 {
-        rd: WritableReg,
-        mem: MemArg,
-    },
-    Load64ZExt16 {
-        rd: WritableReg,
-        mem: MemArg,
-    },
-    Load64SExt16 {
-        rd: WritableReg,
-        mem: MemArg,
-    },
-    Load64ZExt32 {
-        rd: WritableReg,
-        mem: MemArg,
-    },
-    Load64SExt32 {
-        rd: WritableReg,
-        mem: MemArg,
-    },
-    LoadRev16 {
-        rd: WritableReg,
-        mem: MemArg,
-    },
-    LoadRev32 {
-        rd: WritableReg,
-        mem: MemArg,
-    },
-    LoadRev64 {
-        rd: WritableReg,
-        mem: MemArg,
-    },
-    Store8 {
-        rd: Reg,
-        mem: MemArg,
-    },
-    Store16 {
-        rd: Reg,
-        mem: MemArg,
-    },
-    Store32 {
-        rd: Reg,
-        mem: MemArg,
-    },
-    Store64 {
-        rd: Reg,
-        mem: MemArg,
-    },
-    StoreImm8 {
-        imm: u8,
-        mem: MemArg,
-    },
-    StoreImm16 {
-        imm: i16,
-        mem: MemArg,
-    },
-    StoreImm32SExt16 {
-        imm: i16,
-        mem: MemArg,
-    },
-    StoreImm64SExt16 {
-        imm: i16,
-        mem: MemArg,
-    },
-    StoreRev16 {
-        rd: Reg,
-        mem: MemArg,
-    },
-    StoreRev32 {
-        rd: Reg,
-        mem: MemArg,
-    },
-    StoreRev64 {
-        rd: Reg,
-        mem: MemArg,
-    },
-    LoadMultiple64 {
-        rt: WritableReg,
-        rt2: WritableReg,
-        mem: MemArg,
-    },
-    StoreMultiple64 {
-        rt: Reg,
-        rt2: Reg,
-        mem: MemArg,
-    },
-    Mov32 {
-        rd: WritableReg,
-        rm: Reg,
-    },
-    Mov64 {
-        rd: WritableReg,
-        rm: Reg,
-    },
-    Mov32Imm {
-        rd: WritableReg,
-        imm: u32,
-    },
-    Mov32SImm16 {
-        rd: WritableReg,
-        imm: i16,
-    },
-    Mov64SImm16 {
-        rd: WritableReg,
-        imm: i16,
-    },
-    Mov64SImm32 {
-        rd: WritableReg,
-        imm: i32,
-    },
-    Mov64UImm16Shifted {
-        rd: WritableReg,
-        imm: UImm16Shifted,
-    },
-    Mov64UImm32Shifted {
-        rd: WritableReg,
-        imm: UImm32Shifted,
-    },
-    Insert64UImm16Shifted {
-        rd: WritableReg,
-        imm: UImm16Shifted,
-    },
-    Insert64UImm32Shifted {
-        rd: WritableReg,
-        imm: UImm32Shifted,
-    },
-    Extend {
-        rd: WritableReg,
-        rn: Reg,
-        signed: bool,
-        from_bits: u8,
-        to_bits: u8,
-    },
-    CMov32 {
-        rd: WritableReg,
-        cond: Cond,
-        rm: Reg,
-    },
-    CMov64 {
-        rd: WritableReg,
-        cond: Cond,
-        rm: Reg,
-    },
-    CMov32SImm16 {
-        rd: WritableReg,
-        cond: Cond,
-        imm: i16,
-    },
-    CMov64SImm16 {
-        rd: WritableReg,
-        cond: Cond,
-        imm: i16,
-    },
-    FpuMove32 {
-        rd: WritableReg,
-        rn: Reg,
-    },
-    FpuMove64 {
-        rd: WritableReg,
-        rn: Reg,
-    },
-    FpuCMov32 {
-        rd: WritableReg,
-        cond: Cond,
-        rm: Reg,
-    },
-    FpuCMov64 {
-        rd: WritableReg,
-        cond: Cond,
-        rm: Reg,
-    },
-    MovToFpr {
-        rd: WritableReg,
-        rn: Reg,
-    },
-    MovFromFpr {
-        rd: WritableReg,
-        rn: Reg,
-    },
-    FpuRR {
-        fpu_op: FPUOp1,
-        rd: WritableReg,
-        rn: Reg,
-    },
-    FpuRRR {
-        fpu_op: FPUOp2,
-        rd: WritableReg,
-        rm: Reg,
-    },
-    FpuRRRR {
-        fpu_op: FPUOp3,
-        rd: WritableReg,
-        rn: Reg,
-        rm: Reg,
-    },
-    FpuCopysign {
-        rd: WritableReg,
-        rn: Reg,
-        rm: Reg,
-    },
-    FpuCmp32 {
-        rn: Reg,
-        rm: Reg,
-    },
-    FpuCmp64 {
-        rn: Reg,
-        rm: Reg,
-    },
-    FpuLoad32 {
-        rd: WritableReg,
-        mem: MemArg,
-    },
-    FpuStore32 {
-        rd: Reg,
-        mem: MemArg,
-    },
-    FpuLoad64 {
-        rd: WritableReg,
-        mem: MemArg,
-    },
-    FpuStore64 {
-        rd: Reg,
-        mem: MemArg,
-    },
-    FpuLoadRev32 {
-        rd: WritableReg,
-        mem: MemArg,
-    },
-    FpuStoreRev32 {
-        rd: Reg,
-        mem: MemArg,
-    },
-    FpuLoadRev64 {
-        rd: WritableReg,
-        mem: MemArg,
-    },
-    FpuStoreRev64 {
-        rd: Reg,
-        mem: MemArg,
-    },
-    LoadFpuConst32 {
-        rd: WritableReg,
-        const_data: u32,
-    },
-    LoadFpuConst64 {
-        rd: WritableReg,
-        const_data: u64,
-    },
-    FpuToInt {
-        op: FpuToIntOp,
-        rd: WritableReg,
-        rn: Reg,
-    },
-    IntToFpu {
-        op: IntToFpuOp,
-        rd: WritableReg,
-        rn: Reg,
-    },
-    FpuRound {
-        op: FpuRoundMode,
-        rd: WritableReg,
-        rn: Reg,
-    },
-    FpuVecRRR {
-        fpu_op: FPUOp2,
-        rd: WritableReg,
-        rn: Reg,
-        rm: Reg,
-    },
-    Call {
-        link: WritableReg,
-        info: BoxCallInfo,
-    },
-    CallInd {
-        link: WritableReg,
-        info: BoxCallIndInfo,
-    },
-    Ret {
-        link: Reg,
-    },
-    EpiloguePlaceholder,
-    Jump {
-        dest: MachLabel,
-    },
-    CondBr {
-        taken: MachLabel,
-        not_taken: MachLabel,
-        cond: Cond,
-    },
-    TrapIf {
-        cond: Cond,
-        trap_code: TrapCode,
-    },
-    OneWayCondBr {
-        target: MachLabel,
-        cond: Cond,
-    },
-    IndirectBr {
-        rn: Reg,
-        targets: VecMachLabel,
-    },
-    Debugtrap,
-    Trap {
-        trap_code: TrapCode,
-    },
-    JTSequence {
-        ridx: Reg,
-        targets: VecMachLabel,
-    },
-    LoadExtNameFar {
-        rd: WritableReg,
-        name: BoxExternalName,
-        offset: i64,
-    },
-    LoadAddr {
-        rd: WritableReg,
-        mem: MemArg,
-    },
-    Loop {
-        body: VecMInst,
-        cond: Cond,
-    },
-    CondBreak {
-        cond: Cond,
-    },
-    VirtualSPOffsetAdj {
-        offset: i64,
-    },
-    ValueLabelMarker {
-        reg: Reg,
-        label: ValueLabel,
-    },
-    Unwind {
-        inst: UnwindInst,
-    },
-}
-
-/// Internal type ALUOp: defined at src/isa/s390x/inst.isle line 717.
-#[derive(Copy, Clone, PartialEq, Eq, Debug)]
-pub enum ALUOp {
-    Add32,
-    Add32Ext16,
-    Add64,
-    Add64Ext16,
-    Add64Ext32,
-    AddLogical32,
-    AddLogical64,
-    AddLogical64Ext32,
-    Sub32,
-    Sub32Ext16,
-    Sub64,
-    Sub64Ext16,
-    Sub64Ext32,
-    SubLogical32,
-    SubLogical64,
-    SubLogical64Ext32,
-    Mul32,
-    Mul32Ext16,
-    Mul64,
-    Mul64Ext16,
-    Mul64Ext32,
-    And32,
-    And64,
-    Orr32,
-    Orr64,
-    Xor32,
-    Xor64,
-    AndNot32,
-    AndNot64,
-    OrrNot32,
-    OrrNot64,
-    XorNot32,
-    XorNot64,
-}
-
-/// Internal type UnaryOp: defined at src/isa/s390x/inst.isle line 758.
-#[derive(Copy, Clone, PartialEq, Eq, Debug)]
-pub enum UnaryOp {
-    Abs32,
-    Abs64,
-    Abs64Ext32,
-    Neg32,
-    Neg64,
-    Neg64Ext32,
-    PopcntByte,
-    PopcntReg,
-    BSwap32,
-    BSwap64,
-}
-
-/// Internal type ShiftOp: defined at src/isa/s390x/inst.isle line 773.
-#[derive(Copy, Clone, PartialEq, Eq, Debug)]
-pub enum ShiftOp {
-    RotL32,
-    RotL64,
-    LShL32,
-    LShL64,
-    LShR32,
-    LShR64,
-    AShR32,
-    AShR64,
-}
-
-/// Internal type RxSBGOp: defined at src/isa/s390x/inst.isle line 786.
-#[derive(Copy, Clone, PartialEq, Eq, Debug)]
-pub enum RxSBGOp {
-    Insert,
-    And,
-    Or,
-    Xor,
-}
-
-/// Internal type CmpOp: defined at src/isa/s390x/inst.isle line 795.
-#[derive(Copy, Clone, PartialEq, Eq, Debug)]
-pub enum CmpOp {
-    CmpS32,
-    CmpS32Ext16,
-    CmpS64,
-    CmpS64Ext16,
-    CmpS64Ext32,
-    CmpL32,
-    CmpL32Ext16,
-    CmpL64,
-    CmpL64Ext16,
-    CmpL64Ext32,
-}
-
-/// Internal type FPUOp1: defined at src/isa/s390x/inst.isle line 810.
-#[derive(Copy, Clone, PartialEq, Eq, Debug)]
-pub enum FPUOp1 {
-    Abs32,
-    Abs64,
-    Neg32,
-    Neg64,
-    NegAbs32,
-    NegAbs64,
-    Sqrt32,
-    Sqrt64,
-    Cvt32To64,
-    Cvt64To32,
-}
-
-/// Internal type FPUOp2: defined at src/isa/s390x/inst.isle line 825.
-#[derive(Copy, Clone, PartialEq, Eq, Debug)]
-pub enum FPUOp2 {
-    Add32,
-    Add64,
-    Sub32,
-    Sub64,
-    Mul32,
-    Mul64,
-    Div32,
-    Div64,
-    Max32,
-    Max64,
-    Min32,
-    Min64,
-}
-
-/// Internal type FPUOp3: defined at src/isa/s390x/inst.isle line 842.
-#[derive(Copy, Clone, PartialEq, Eq, Debug)]
-pub enum FPUOp3 {
-    MAdd32,
-    MAdd64,
-    MSub32,
-    MSub64,
-}
-
-/// Internal type FpuToIntOp: defined at src/isa/s390x/inst.isle line 851.
-#[derive(Copy, Clone, PartialEq, Eq, Debug)]
-pub enum FpuToIntOp {
-    F32ToU32,
-    F32ToI32,
-    F32ToU64,
-    F32ToI64,
-    F64ToU32,
-    F64ToI32,
-    F64ToU64,
-    F64ToI64,
-}
-
-/// Internal type IntToFpuOp: defined at src/isa/s390x/inst.isle line 864.
-#[derive(Copy, Clone, PartialEq, Eq, Debug)]
-pub enum IntToFpuOp {
-    U32ToF32,
-    I32ToF32,
-    U32ToF64,
-    I32ToF64,
-    U64ToF32,
-    I64ToF32,
-    U64ToF64,
-    I64ToF64,
-}
-
-/// Internal type FpuRoundMode: defined at src/isa/s390x/inst.isle line 878.
-#[derive(Copy, Clone, PartialEq, Eq, Debug)]
-pub enum FpuRoundMode {
-    Minus32,
-    Minus64,
-    Plus32,
-    Plus64,
-    Zero32,
-    Zero64,
-    Nearest32,
-    Nearest64,
-}
-
-/// Internal type WritableRegPair: defined at src/isa/s390x/inst.isle line 1269.
-#[derive(Clone, Debug)]
-pub enum WritableRegPair {
-    WritableRegPair { hi: WritableReg, lo: WritableReg },
-}
-
-/// Internal type RegPair: defined at src/isa/s390x/inst.isle line 1291.
-#[derive(Clone, Debug)]
-pub enum RegPair {
-    RegPair { hi: Reg, lo: Reg },
-}
-
-/// Internal type ProducesBool: defined at src/isa/s390x/inst.isle line 2316.
-#[derive(Clone, Debug)]
-pub enum ProducesBool {
-    ProducesBool { producer: ProducesFlags, cond: Cond },
-}
-
-// Generated as internal constructor for term output_reg.
-pub fn constructor_output_reg<C: Context>(ctx: &mut C, arg0: Reg) -> Option<InstOutput> {
-    let pattern0_0 = arg0;
-    // Rule at src/prelude.isle line 86.
-    let expr0_0 = C::value_reg(ctx, pattern0_0);
-    let expr1_0 = C::output(ctx, expr0_0);
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term output_value.
-pub fn constructor_output_value<C: Context>(ctx: &mut C, arg0: Value) -> Option<InstOutput> {
-    let pattern0_0 = arg0;
-    // Rule at src/prelude.isle line 90.
-    let expr0_0 = C::put_in_regs(ctx, pattern0_0);
-    let expr1_0 = C::output(ctx, expr0_0);
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term temp_reg.
-pub fn constructor_temp_reg<C: Context>(ctx: &mut C, arg0: Type) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    // Rule at src/prelude.isle line 110.
-    let expr0_0 = C::temp_writable_reg(ctx, pattern0_0);
-    let expr1_0 = C::writable_reg_to_reg(ctx, expr0_0);
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term lo_reg.
-pub fn constructor_lo_reg<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    // Rule at src/prelude.isle line 145.
-    let expr0_0 = C::put_in_regs(ctx, pattern0_0);
-    let expr1_0: usize = 0;
-    let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term side_effect.
-pub fn constructor_side_effect<C: Context>(
-    ctx: &mut C,
-    arg0: &SideEffectNoResult,
-) -> Option<InstOutput> {
-    let pattern0_0 = arg0;
-    if let &SideEffectNoResult::Inst {
-        inst: ref pattern1_0,
-    } = pattern0_0
-    {
-        // Rule at src/prelude.isle line 398.
-        let expr0_0 = C::emit(ctx, pattern1_0);
-        let expr1_0 = C::output_none(ctx);
-        return Some(expr1_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term safepoint.
-pub fn constructor_safepoint<C: Context>(
-    ctx: &mut C,
-    arg0: &SideEffectNoResult,
-) -> Option<InstOutput> {
-    let pattern0_0 = arg0;
-    if let &SideEffectNoResult::Inst {
-        inst: ref pattern1_0,
-    } = pattern0_0
-    {
-        // Rule at src/prelude.isle line 404.
-        let expr0_0 = C::emit_safepoint(ctx, pattern1_0);
-        let expr1_0 = C::output_none(ctx);
-        return Some(expr1_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term produces_flags_get_reg.
-pub fn constructor_produces_flags_get_reg<C: Context>(
-    ctx: &mut C,
-    arg0: &ProducesFlags,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    if let &ProducesFlags::ProducesFlagsReturnsReg {
-        inst: ref pattern1_0,
-        result: pattern1_1,
-    } = pattern0_0
-    {
-        // Rule at src/prelude.isle line 442.
-        return Some(pattern1_1);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term produces_flags_ignore.
-pub fn constructor_produces_flags_ignore<C: Context>(
-    ctx: &mut C,
-    arg0: &ProducesFlags,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    match pattern0_0 {
-        &ProducesFlags::ProducesFlagsReturnsReg {
-            inst: ref pattern1_0,
-            result: pattern1_1,
-        } => {
-            // Rule at src/prelude.isle line 447.
-            let expr0_0 = ProducesFlags::ProducesFlagsSideEffect {
-                inst: pattern1_0.clone(),
-            };
-            return Some(expr0_0);
-        }
-        &ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
-            inst: ref pattern1_0,
-            result: pattern1_1,
-        } => {
-            // Rule at src/prelude.isle line 449.
-            let expr0_0 = ProducesFlags::ProducesFlagsSideEffect {
-                inst: pattern1_0.clone(),
-            };
-            return Some(expr0_0);
-        }
-        _ => {}
-    }
-    return None;
-}
-
-// Generated as internal constructor for term consumes_flags_concat.
-pub fn constructor_consumes_flags_concat<C: Context>(
-    ctx: &mut C,
-    arg0: &ConsumesFlags,
-    arg1: &ConsumesFlags,
-) -> Option<ConsumesFlags> {
-    let pattern0_0 = arg0;
-    if let &ConsumesFlags::ConsumesFlagsReturnsReg {
-        inst: ref pattern1_0,
-        result: pattern1_1,
-    } = pattern0_0
-    {
-        let pattern2_0 = arg1;
-        if let &ConsumesFlags::ConsumesFlagsReturnsReg {
-            inst: ref pattern3_0,
-            result: pattern3_1,
-        } = pattern2_0
-        {
-            // Rule at src/prelude.isle line 456.
-            let expr0_0 = C::value_regs(ctx, pattern1_1, pattern3_1);
-            let expr1_0 = ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs {
-                inst1: pattern1_0.clone(),
-                inst2: pattern3_0.clone(),
-                result: expr0_0,
-            };
-            return Some(expr1_0);
-        }
-    }
-    return None;
-}
-
-// Generated as internal constructor for term with_flags.
-pub fn constructor_with_flags<C: Context>(
-    ctx: &mut C,
-    arg0: &ProducesFlags,
-    arg1: &ConsumesFlags,
-) -> Option<ValueRegs> {
-    let pattern0_0 = arg0;
-    match pattern0_0 {
-        &ProducesFlags::ProducesFlagsSideEffect {
-            inst: ref pattern1_0,
-        } => {
-            let pattern2_0 = arg1;
-            match pattern2_0 {
-                &ConsumesFlags::ConsumesFlagsReturnsReg {
-                    inst: ref pattern3_0,
-                    result: pattern3_1,
-                } => {
-                    // Rule at src/prelude.isle line 481.
-                    let expr0_0 = C::emit(ctx, pattern1_0);
-                    let expr1_0 = C::emit(ctx, pattern3_0);
-                    let expr2_0 = C::value_reg(ctx, pattern3_1);
-                    return Some(expr2_0);
-                }
-                &ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs {
-                    inst1: ref pattern3_0,
-                    inst2: ref pattern3_1,
-                    result: pattern3_2,
-                } => {
-                    // Rule at src/prelude.isle line 487.
-                    let expr0_0 = C::emit(ctx, pattern1_0);
-                    let expr1_0 = C::emit(ctx, pattern3_0);
-                    let expr2_0 = C::emit(ctx, pattern3_1);
-                    return Some(pattern3_2);
-                }
-                &ConsumesFlags::ConsumesFlagsFourTimesReturnsValueRegs {
-                    inst1: ref pattern3_0,
-                    inst2: ref pattern3_1,
-                    inst3: ref pattern3_2,
-                    inst4: ref pattern3_3,
-                    result: pattern3_4,
-                } => {
-                    // Rule at src/prelude.isle line 499.
-                    let expr0_0 = C::emit(ctx, pattern1_0);
-                    let expr1_0 = C::emit(ctx, pattern3_0);
-                    let expr2_0 = C::emit(ctx, pattern3_1);
-                    let expr3_0 = C::emit(ctx, pattern3_2);
-                    let expr4_0 = C::emit(ctx, pattern3_3);
-                    return Some(pattern3_4);
-                }
-                _ => {}
-            }
-        }
-        &ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
-            inst: ref pattern1_0,
-            result: pattern1_1,
-        } => {
-            let pattern2_0 = arg1;
-            if let &ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
-                inst: ref pattern3_0,
-                result: pattern3_1,
-            } = pattern2_0
-            {
-                // Rule at src/prelude.isle line 475.
-                let expr0_0 = C::emit(ctx, pattern1_0);
-                let expr1_0 = C::emit(ctx, pattern3_0);
-                let expr2_0 = C::value_regs(ctx, pattern1_1, pattern3_1);
-                return Some(expr2_0);
-            }
-        }
-        _ => {}
-    }
-    return None;
-}
-
-// Generated as internal constructor for term with_flags_reg.
-pub fn constructor_with_flags_reg<C: Context>(
-    ctx: &mut C,
-    arg0: &ProducesFlags,
-    arg1: &ConsumesFlags,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/prelude.isle line 516.
-    let expr0_0 = constructor_with_flags(ctx, pattern0_0, pattern1_0)?;
-    let expr1_0: usize = 0;
-    let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term mask_amt_reg.
-pub fn constructor_mask_amt_reg<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    if let Some(pattern1_0) = C::gpr32_ty(ctx, pattern0_0) {
-        let pattern2_0 = arg1;
-        // Rule at src/isa/s390x/inst.isle line 1040.
-        let expr0_0: i64 = -1;
-        let expr1_0 = C::mask_amt_imm(ctx, pattern1_0, expr0_0);
-        let expr2_0 = C::u8_as_u16(ctx, expr1_0);
-        let expr3_0: u8 = 0;
-        let expr4_0 = C::uimm16shifted(ctx, expr2_0, expr3_0);
-        let expr5_0 = constructor_and_uimm16shifted(ctx, pattern1_0, pattern2_0, expr4_0)?;
-        return Some(expr5_0);
-    }
-    if let Some(pattern1_0) = C::gpr64_ty(ctx, pattern0_0) {
-        let pattern2_0 = arg1;
-        // Rule at src/isa/s390x/inst.isle line 1043.
-        return Some(pattern2_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term lower_address.
-pub fn constructor_lower_address<C: Context>(
-    ctx: &mut C,
-    arg0: MemFlags,
-    arg1: Value,
-    arg2: Offset32,
-) -> Option<MemArg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    if let Some(pattern2_0) = C::def_inst(ctx, pattern1_0) {
-        let pattern3_0 = C::inst_data(ctx, pattern2_0);
-        match &pattern3_0 {
-            &InstructionData::UnaryGlobalValue {
-                opcode: ref pattern4_0,
-                global_value: pattern4_1,
-            } => {
-                if let &Opcode::SymbolValue = pattern4_0 {
-                    if let Some((pattern6_0, pattern6_1, pattern6_2)) =
-                        C::symbol_value_data(ctx, pattern4_1)
-                    {
-                        if let Some(()) = C::reloc_distance_near(ctx, pattern6_1) {
-                            let pattern8_0 = arg2;
-                            let pattern9_0 = C::i64_from_offset(ctx, pattern8_0);
-                            let closure10 = || {
-                                return Some(pattern6_2);
-                            };
-                            if let Some(pattern10_0) = closure10() {
-                                if let Some(pattern11_0) =
-                                    C::memarg_symbol_offset_sum(ctx, pattern9_0, pattern10_0)
-                                {
-                                    // Rule at src/isa/s390x/inst.isle line 1136.
-                                    let expr0_0 =
-                                        C::memarg_symbol(ctx, pattern6_0, pattern11_0, pattern0_0);
-                                    return Some(expr0_0);
-                                }
-                            }
-                        }
-                    }
-                }
-            }
-            &InstructionData::Binary {
-                opcode: ref pattern4_0,
-                args: ref pattern4_1,
-            } => {
-                if let &Opcode::Iadd = pattern4_0 {
-                    let (pattern6_0, pattern6_1) = C::unpack_value_array_2(ctx, pattern4_1);
-                    let pattern7_0 = arg2;
-                    let pattern8_0 = C::i64_from_offset(ctx, pattern7_0);
-                    if pattern8_0 == 0 {
-                        // Rule at src/isa/s390x/inst.isle line 1133.
-                        let expr0_0 = C::put_in_reg(ctx, pattern6_0);
-                        let expr1_0 = C::put_in_reg(ctx, pattern6_1);
-                        let expr2_0 = C::memarg_reg_plus_reg(ctx, expr0_0, expr1_0, pattern0_0);
-                        return Some(expr2_0);
-                    }
-                }
-            }
-            _ => {}
-        }
-    }
-    let pattern2_0 = arg2;
-    let pattern3_0 = C::i64_from_offset(ctx, pattern2_0);
-    // Rule at src/isa/s390x/inst.isle line 1130.
-    let expr0_0 = C::put_in_reg(ctx, pattern1_0);
-    let expr1_0 = C::memarg_reg_plus_off(ctx, expr0_0, pattern3_0, pattern0_0);
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term stack_addr_impl.
-pub fn constructor_stack_addr_impl<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: StackSlot,
-    arg2: Offset32,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 1163.
-    let expr0_0 = C::temp_writable_reg(ctx, pattern0_0);
-    let expr1_0 = C::abi_stackslot_addr(ctx, expr0_0, pattern1_0, pattern2_0);
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = C::writable_reg_to_reg(ctx, expr0_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term sink_load.
-pub fn constructor_sink_load<C: Context>(ctx: &mut C, arg0: Inst) -> Option<MemArg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = C::inst_data(ctx, pattern0_0);
-    if let &InstructionData::Load {
-        opcode: ref pattern2_0,
-        arg: pattern2_1,
-        flags: pattern2_2,
-        offset: pattern2_3,
-    } = &pattern1_0
-    {
-        if let &Opcode::Load = pattern2_0 {
-            // Rule at src/isa/s390x/inst.isle line 1233.
-            let expr0_0 = C::sink_inst(ctx, pattern0_0);
-            let expr1_0 = constructor_lower_address(ctx, pattern2_2, pattern2_1, pattern2_3)?;
-            return Some(expr1_0);
-        }
-    }
-    return None;
-}
-
-// Generated as internal constructor for term sink_sload16.
-pub fn constructor_sink_sload16<C: Context>(ctx: &mut C, arg0: Inst) -> Option<MemArg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = C::inst_data(ctx, pattern0_0);
-    if let &InstructionData::Load {
-        opcode: ref pattern2_0,
-        arg: pattern2_1,
-        flags: pattern2_2,
-        offset: pattern2_3,
-    } = &pattern1_0
-    {
-        if let &Opcode::Sload16 = pattern2_0 {
-            // Rule at src/isa/s390x/inst.isle line 1240.
-            let expr0_0 = C::sink_inst(ctx, pattern0_0);
-            let expr1_0 = constructor_lower_address(ctx, pattern2_2, pattern2_1, pattern2_3)?;
-            return Some(expr1_0);
-        }
-    }
-    return None;
-}
-
-// Generated as internal constructor for term sink_sload32.
-pub fn constructor_sink_sload32<C: Context>(ctx: &mut C, arg0: Inst) -> Option<MemArg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = C::inst_data(ctx, pattern0_0);
-    if let &InstructionData::Load {
-        opcode: ref pattern2_0,
-        arg: pattern2_1,
-        flags: pattern2_2,
-        offset: pattern2_3,
-    } = &pattern1_0
-    {
-        if let &Opcode::Sload32 = pattern2_0 {
-            // Rule at src/isa/s390x/inst.isle line 1247.
-            let expr0_0 = C::sink_inst(ctx, pattern0_0);
-            let expr1_0 = constructor_lower_address(ctx, pattern2_2, pattern2_1, pattern2_3)?;
-            return Some(expr1_0);
-        }
-    }
-    return None;
-}
-
-// Generated as internal constructor for term sink_uload16.
-pub fn constructor_sink_uload16<C: Context>(ctx: &mut C, arg0: Inst) -> Option<MemArg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = C::inst_data(ctx, pattern0_0);
-    if let &InstructionData::Load {
-        opcode: ref pattern2_0,
-        arg: pattern2_1,
-        flags: pattern2_2,
-        offset: pattern2_3,
-    } = &pattern1_0
-    {
-        if let &Opcode::Uload16 = pattern2_0 {
-            // Rule at src/isa/s390x/inst.isle line 1254.
-            let expr0_0 = C::sink_inst(ctx, pattern0_0);
-            let expr1_0 = constructor_lower_address(ctx, pattern2_2, pattern2_1, pattern2_3)?;
-            return Some(expr1_0);
-        }
-    }
-    return None;
-}
-
-// Generated as internal constructor for term sink_uload32.
-pub fn constructor_sink_uload32<C: Context>(ctx: &mut C, arg0: Inst) -> Option<MemArg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = C::inst_data(ctx, pattern0_0);
-    if let &InstructionData::Load {
-        opcode: ref pattern2_0,
-        arg: pattern2_1,
-        flags: pattern2_2,
-        offset: pattern2_3,
-    } = &pattern1_0
-    {
-        if let &Opcode::Uload32 = pattern2_0 {
-            // Rule at src/isa/s390x/inst.isle line 1261.
-            let expr0_0 = C::sink_inst(ctx, pattern0_0);
-            let expr1_0 = constructor_lower_address(ctx, pattern2_2, pattern2_1, pattern2_3)?;
-            return Some(expr1_0);
-        }
-    }
-    return None;
-}
-
-// Generated as internal constructor for term temp_writable_regpair.
-pub fn constructor_temp_writable_regpair<C: Context>(ctx: &mut C) -> Option<WritableRegPair> {
-    // Rule at src/isa/s390x/inst.isle line 1274.
-    let expr0_0: u8 = 0;
-    let expr1_0 = C::writable_gpr(ctx, expr0_0);
-    let expr2_0: u8 = 1;
-    let expr3_0 = C::writable_gpr(ctx, expr2_0);
-    let expr4_0 = WritableRegPair::WritableRegPair {
-        hi: expr1_0,
-        lo: expr3_0,
-    };
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term copy_writable_regpair.
-pub fn constructor_copy_writable_regpair<C: Context>(
-    ctx: &mut C,
-    arg0: &RegPair,
-) -> Option<WritableRegPair> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/s390x/inst.isle line 1280.
-    let expr0_0 = constructor_temp_writable_regpair(ctx)?;
-    return Some(expr0_0);
-}
-
-// Generated as internal constructor for term writable_regpair_hi.
-pub fn constructor_writable_regpair_hi<C: Context>(
-    ctx: &mut C,
-    arg0: &WritableRegPair,
-) -> Option<WritableReg> {
-    let pattern0_0 = arg0;
-    if let &WritableRegPair::WritableRegPair {
-        hi: pattern1_0,
-        lo: pattern1_1,
-    } = pattern0_0
-    {
-        // Rule at src/isa/s390x/inst.isle line 1284.
-        return Some(pattern1_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term writable_regpair_lo.
-pub fn constructor_writable_regpair_lo<C: Context>(
-    ctx: &mut C,
-    arg0: &WritableRegPair,
-) -> Option<WritableReg> {
-    let pattern0_0 = arg0;
-    if let &WritableRegPair::WritableRegPair {
-        hi: pattern1_0,
-        lo: pattern1_1,
-    } = pattern0_0
-    {
-        // Rule at src/isa/s390x/inst.isle line 1288.
-        return Some(pattern1_1);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term writable_regpair_to_regpair.
-pub fn constructor_writable_regpair_to_regpair<C: Context>(
-    ctx: &mut C,
-    arg0: &WritableRegPair,
-) -> Option<RegPair> {
-    let pattern0_0 = arg0;
-    if let &WritableRegPair::WritableRegPair {
-        hi: pattern1_0,
-        lo: pattern1_1,
-    } = pattern0_0
-    {
-        // Rule at src/isa/s390x/inst.isle line 1295.
-        let expr0_0 = C::writable_reg_to_reg(ctx, pattern1_0);
-        let expr1_0 = C::writable_reg_to_reg(ctx, pattern1_1);
-        let expr2_0 = RegPair::RegPair {
-            hi: expr0_0,
-            lo: expr1_0,
-        };
-        return Some(expr2_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term uninitialized_regpair.
-pub fn constructor_uninitialized_regpair<C: Context>(ctx: &mut C) -> Option<RegPair> {
-    // Rule at src/isa/s390x/inst.isle line 1300.
-    let expr0_0 = constructor_temp_writable_regpair(ctx)?;
-    let expr1_0 = constructor_writable_regpair_to_regpair(ctx, &expr0_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term regpair_hi.
-pub fn constructor_regpair_hi<C: Context>(ctx: &mut C, arg0: &RegPair) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    if let &RegPair::RegPair {
-        hi: pattern1_0,
-        lo: pattern1_1,
-    } = pattern0_0
-    {
-        // Rule at src/isa/s390x/inst.isle line 1305.
-        return Some(pattern1_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term regpair_lo.
-pub fn constructor_regpair_lo<C: Context>(ctx: &mut C, arg0: &RegPair) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    if let &RegPair::RegPair {
-        hi: pattern1_0,
-        lo: pattern1_1,
-    } = pattern0_0
-    {
-        // Rule at src/isa/s390x/inst.isle line 1309.
-        return Some(pattern1_1);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term alu_rrr.
-pub fn constructor_alu_rrr<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &ALUOp,
-    arg2: Reg,
-    arg3: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/s390x/inst.isle line 1316.
-    let expr0_0 = C::temp_writable_reg(ctx, pattern0_0);
-    let expr1_0 = MInst::AluRRR {
-        alu_op: pattern1_0.clone(),
-        rd: expr0_0,
-        rn: pattern2_0,
-        rm: pattern3_0,
-    };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = C::writable_reg_to_reg(ctx, expr0_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term alu_rrsimm16.
-pub fn constructor_alu_rrsimm16<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &ALUOp,
-    arg2: Reg,
-    arg3: i16,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/s390x/inst.isle line 1323.
-    let expr0_0 = C::temp_writable_reg(ctx, pattern0_0);
-    let expr1_0 = MInst::AluRRSImm16 {
-        alu_op: pattern1_0.clone(),
-        rd: expr0_0,
-        rn: pattern2_0,
-        imm: pattern3_0,
-    };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = C::writable_reg_to_reg(ctx, expr0_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term alu_rr.
-pub fn constructor_alu_rr<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &ALUOp,
-    arg2: Reg,
-    arg3: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/s390x/inst.isle line 1330.
-    let expr0_0 = constructor_copy_writable_reg(ctx, pattern0_0, pattern2_0)?;
-    let expr1_0 = MInst::AluRR {
-        alu_op: pattern1_0.clone(),
-        rd: expr0_0,
-        rm: pattern3_0,
-    };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = C::writable_reg_to_reg(ctx, expr0_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term alu_rx.
-pub fn constructor_alu_rx<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &ALUOp,
-    arg2: Reg,
-    arg3: &MemArg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/s390x/inst.isle line 1337.
-    let expr0_0 = constructor_copy_writable_reg(ctx, pattern0_0, pattern2_0)?;
-    let expr1_0 = MInst::AluRX {
-        alu_op: pattern1_0.clone(),
-        rd: expr0_0,
-        mem: pattern3_0.clone(),
-    };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = C::writable_reg_to_reg(ctx, expr0_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term alu_rsimm16.
-pub fn constructor_alu_rsimm16<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &ALUOp,
-    arg2: Reg,
-    arg3: i16,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/s390x/inst.isle line 1344.
-    let expr0_0 = constructor_copy_writable_reg(ctx, pattern0_0, pattern2_0)?;
-    let expr1_0 = MInst::AluRSImm16 {
-        alu_op: pattern1_0.clone(),
-        rd: expr0_0,
-        imm: pattern3_0,
-    };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = C::writable_reg_to_reg(ctx, expr0_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term alu_rsimm32.
-pub fn constructor_alu_rsimm32<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &ALUOp,
-    arg2: Reg,
-    arg3: i32,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/s390x/inst.isle line 1351.
-    let expr0_0 = constructor_copy_writable_reg(ctx, pattern0_0, pattern2_0)?;
-    let expr1_0 = MInst::AluRSImm32 {
-        alu_op: pattern1_0.clone(),
-        rd: expr0_0,
-        imm: pattern3_0,
-    };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = C::writable_reg_to_reg(ctx, expr0_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term alu_ruimm32.
-pub fn constructor_alu_ruimm32<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &ALUOp,
-    arg2: Reg,
-    arg3: u32,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/s390x/inst.isle line 1358.
-    let expr0_0 = constructor_copy_writable_reg(ctx, pattern0_0, pattern2_0)?;
-    let expr1_0 = MInst::AluRUImm32 {
-        alu_op: pattern1_0.clone(),
-        rd: expr0_0,
-        imm: pattern3_0,
-    };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = C::writable_reg_to_reg(ctx, expr0_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term alu_ruimm16shifted.
-pub fn constructor_alu_ruimm16shifted<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &ALUOp,
-    arg2: Reg,
-    arg3: UImm16Shifted,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/s390x/inst.isle line 1365.
-    let expr0_0 = constructor_copy_writable_reg(ctx, pattern0_0, pattern2_0)?;
-    let expr1_0 = MInst::AluRUImm16Shifted {
-        alu_op: pattern1_0.clone(),
-        rd: expr0_0,
-        imm: pattern3_0,
-    };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = C::writable_reg_to_reg(ctx, expr0_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term alu_ruimm32shifted.
-pub fn constructor_alu_ruimm32shifted<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &ALUOp,
-    arg2: Reg,
-    arg3: UImm32Shifted,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/s390x/inst.isle line 1372.
-    let expr0_0 = constructor_copy_writable_reg(ctx, pattern0_0, pattern2_0)?;
-    let expr1_0 = MInst::AluRUImm32Shifted {
-        alu_op: pattern1_0.clone(),
-        rd: expr0_0,
-        imm: pattern3_0,
-    };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = C::writable_reg_to_reg(ctx, expr0_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term smul_wide.
-pub fn constructor_smul_wide<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg) -> Option<RegPair> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 1379.
-    let expr0_0 = constructor_temp_writable_regpair(ctx)?;
-    let expr1_0 = MInst::SMulWide {
-        rn: pattern0_0,
-        rm: pattern1_0,
-    };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = constructor_writable_regpair_to_regpair(ctx, &expr0_0)?;
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term umul_wide.
-pub fn constructor_umul_wide<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg) -> Option<RegPair> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 1386.
-    let expr0_0 = constructor_temp_writable_regpair(ctx)?;
-    let expr1_0 = constructor_writable_regpair_lo(ctx, &expr0_0)?;
-    let expr2_0 = MInst::Mov64 {
-        rd: expr1_0,
-        rm: pattern1_0,
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = MInst::UMulWide { rn: pattern0_0 };
-    let expr5_0 = C::emit(ctx, &expr4_0);
-    let expr6_0 = constructor_writable_regpair_to_regpair(ctx, &expr0_0)?;
-    return Some(expr6_0);
-}
-
-// Generated as internal constructor for term sdivmod32.
-pub fn constructor_sdivmod32<C: Context>(
-    ctx: &mut C,
-    arg0: &RegPair,
-    arg1: Reg,
-) -> Option<RegPair> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 1394.
-    let expr0_0 = constructor_copy_writable_regpair(ctx, pattern0_0)?;
-    let expr1_0 = MInst::SDivMod32 { rn: pattern1_0 };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = constructor_writable_regpair_to_regpair(ctx, &expr0_0)?;
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term sdivmod64.
-pub fn constructor_sdivmod64<C: Context>(
-    ctx: &mut C,
-    arg0: &RegPair,
-    arg1: Reg,
-) -> Option<RegPair> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 1401.
-    let expr0_0 = constructor_copy_writable_regpair(ctx, pattern0_0)?;
-    let expr1_0 = MInst::SDivMod64 { rn: pattern1_0 };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = constructor_writable_regpair_to_regpair(ctx, &expr0_0)?;
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term udivmod32.
-pub fn constructor_udivmod32<C: Context>(
-    ctx: &mut C,
-    arg0: &RegPair,
-    arg1: Reg,
-) -> Option<RegPair> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 1408.
-    let expr0_0 = constructor_copy_writable_regpair(ctx, pattern0_0)?;
-    let expr1_0 = MInst::UDivMod32 { rn: pattern1_0 };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = constructor_writable_regpair_to_regpair(ctx, &expr0_0)?;
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term udivmod64.
-pub fn constructor_udivmod64<C: Context>(
-    ctx: &mut C,
-    arg0: &RegPair,
-    arg1: Reg,
-) -> Option<RegPair> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 1415.
-    let expr0_0 = constructor_copy_writable_regpair(ctx, pattern0_0)?;
-    let expr1_0 = MInst::UDivMod64 { rn: pattern1_0 };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = constructor_writable_regpair_to_regpair(ctx, &expr0_0)?;
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term shift_rr.
-pub fn constructor_shift_rr<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &ShiftOp,
-    arg2: Reg,
-    arg3: u8,
-    arg4: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    let pattern4_0 = arg4;
-    // Rule at src/isa/s390x/inst.isle line 1422.
-    let expr0_0 = C::temp_writable_reg(ctx, pattern0_0);
-    let expr1_0 = MInst::ShiftRR {
-        shift_op: pattern1_0.clone(),
-        rd: expr0_0,
-        rn: pattern2_0,
-        shift_imm: pattern3_0,
-        shift_reg: pattern4_0,
-    };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = C::writable_reg_to_reg(ctx, expr0_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term rxsbg_test.
-pub fn constructor_rxsbg_test<C: Context>(
-    ctx: &mut C,
-    arg0: &RxSBGOp,
-    arg1: Reg,
-    arg2: Reg,
-    arg3: u8,
-    arg4: u8,
-    arg5: i8,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    let pattern4_0 = arg4;
-    let pattern5_0 = arg5;
-    // Rule at src/isa/s390x/inst.isle line 1429.
-    let expr0_0 = MInst::RxSBGTest {
-        op: pattern0_0.clone(),
-        rd: pattern1_0,
-        rn: pattern2_0,
-        start_bit: pattern3_0,
-        end_bit: pattern4_0,
-        rotate_amt: pattern5_0,
-    };
-    let expr1_0 = ProducesFlags::ProducesFlagsSideEffect { inst: expr0_0 };
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term unary_rr.
-pub fn constructor_unary_rr<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &UnaryOp,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 1435.
-    let expr0_0 = C::temp_writable_reg(ctx, pattern0_0);
-    let expr1_0 = MInst::UnaryRR {
-        op: pattern1_0.clone(),
-        rd: expr0_0,
-        rn: pattern2_0,
-    };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = C::writable_reg_to_reg(ctx, expr0_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term cmp_rr.
-pub fn constructor_cmp_rr<C: Context>(
-    ctx: &mut C,
-    arg0: &CmpOp,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 1442.
-    let expr0_0 = MInst::CmpRR {
-        op: pattern0_0.clone(),
-        rn: pattern1_0,
-        rm: pattern2_0,
-    };
-    let expr1_0 = ProducesFlags::ProducesFlagsSideEffect { inst: expr0_0 };
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term cmp_rx.
-pub fn constructor_cmp_rx<C: Context>(
-    ctx: &mut C,
-    arg0: &CmpOp,
-    arg1: Reg,
-    arg2: &MemArg,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 1447.
-    let expr0_0 = MInst::CmpRX {
-        op: pattern0_0.clone(),
-        rn: pattern1_0,
-        mem: pattern2_0.clone(),
-    };
-    let expr1_0 = ProducesFlags::ProducesFlagsSideEffect { inst: expr0_0 };
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term cmp_rsimm16.
-pub fn constructor_cmp_rsimm16<C: Context>(
-    ctx: &mut C,
-    arg0: &CmpOp,
-    arg1: Reg,
-    arg2: i16,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 1452.
-    let expr0_0 = MInst::CmpRSImm16 {
-        op: pattern0_0.clone(),
-        rn: pattern1_0,
-        imm: pattern2_0,
-    };
-    let expr1_0 = ProducesFlags::ProducesFlagsSideEffect { inst: expr0_0 };
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term cmp_rsimm32.
-pub fn constructor_cmp_rsimm32<C: Context>(
-    ctx: &mut C,
-    arg0: &CmpOp,
-    arg1: Reg,
-    arg2: i32,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 1457.
-    let expr0_0 = MInst::CmpRSImm32 {
-        op: pattern0_0.clone(),
-        rn: pattern1_0,
-        imm: pattern2_0,
-    };
-    let expr1_0 = ProducesFlags::ProducesFlagsSideEffect { inst: expr0_0 };
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term cmp_ruimm32.
-pub fn constructor_cmp_ruimm32<C: Context>(
-    ctx: &mut C,
-    arg0: &CmpOp,
-    arg1: Reg,
-    arg2: u32,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 1462.
-    let expr0_0 = MInst::CmpRUImm32 {
-        op: pattern0_0.clone(),
-        rn: pattern1_0,
-        imm: pattern2_0,
-    };
-    let expr1_0 = ProducesFlags::ProducesFlagsSideEffect { inst: expr0_0 };
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term atomic_rmw_impl.
-pub fn constructor_atomic_rmw_impl<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &ALUOp,
-    arg2: Reg,
-    arg3: &MemArg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/s390x/inst.isle line 1467.
-    let expr0_0 = C::temp_writable_reg(ctx, pattern0_0);
-    let expr1_0 = MInst::AtomicRmw {
-        alu_op: pattern1_0.clone(),
-        rd: expr0_0,
-        rn: pattern2_0,
-        mem: pattern3_0.clone(),
-    };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = C::writable_reg_to_reg(ctx, expr0_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term atomic_cas32.
-pub fn constructor_atomic_cas32<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: Reg,
-    arg2: &MemArg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 1474.
-    let expr0_0: Type = I32;
-    let expr1_0 = constructor_copy_writable_reg(ctx, expr0_0, pattern0_0)?;
-    let expr2_0 = MInst::AtomicCas32 {
-        rd: expr1_0,
-        rn: pattern1_0,
-        mem: pattern2_0.clone(),
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term atomic_cas64.
-pub fn constructor_atomic_cas64<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: Reg,
-    arg2: &MemArg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 1481.
-    let expr0_0: Type = I64;
-    let expr1_0 = constructor_copy_writable_reg(ctx, expr0_0, pattern0_0)?;
-    let expr2_0 = MInst::AtomicCas64 {
-        rd: expr1_0,
-        rn: pattern1_0,
-        mem: pattern2_0.clone(),
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term fence_impl.
-pub fn constructor_fence_impl<C: Context>(ctx: &mut C) -> Option<SideEffectNoResult> {
-    // Rule at src/isa/s390x/inst.isle line 1488.
-    let expr0_0 = MInst::Fence;
-    let expr1_0 = SideEffectNoResult::Inst { inst: expr0_0 };
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term load32.
-pub fn constructor_load32<C: Context>(ctx: &mut C, arg0: &MemArg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/s390x/inst.isle line 1493.
-    let expr0_0: Type = I32;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = MInst::Load32 {
-        rd: expr1_0,
-        mem: pattern0_0.clone(),
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term load64.
-pub fn constructor_load64<C: Context>(ctx: &mut C, arg0: &MemArg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/s390x/inst.isle line 1500.
-    let expr0_0: Type = I64;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = MInst::Load64 {
-        rd: expr1_0,
-        mem: pattern0_0.clone(),
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term loadrev16.
-pub fn constructor_loadrev16<C: Context>(ctx: &mut C, arg0: &MemArg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/s390x/inst.isle line 1507.
-    let expr0_0: Type = I32;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = MInst::LoadRev16 {
-        rd: expr1_0,
-        mem: pattern0_0.clone(),
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term loadrev32.
-pub fn constructor_loadrev32<C: Context>(ctx: &mut C, arg0: &MemArg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/s390x/inst.isle line 1514.
-    let expr0_0: Type = I32;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = MInst::LoadRev32 {
-        rd: expr1_0,
-        mem: pattern0_0.clone(),
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term loadrev64.
-pub fn constructor_loadrev64<C: Context>(ctx: &mut C, arg0: &MemArg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/s390x/inst.isle line 1521.
-    let expr0_0: Type = I64;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = MInst::LoadRev64 {
-        rd: expr1_0,
-        mem: pattern0_0.clone(),
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term store8.
-pub fn constructor_store8<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: &MemArg,
-) -> Option<SideEffectNoResult> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 1528.
-    let expr0_0 = MInst::Store8 {
-        rd: pattern0_0,
-        mem: pattern1_0.clone(),
-    };
-    let expr1_0 = SideEffectNoResult::Inst { inst: expr0_0 };
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term store16.
-pub fn constructor_store16<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: &MemArg,
-) -> Option<SideEffectNoResult> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 1533.
-    let expr0_0 = MInst::Store16 {
-        rd: pattern0_0,
-        mem: pattern1_0.clone(),
-    };
-    let expr1_0 = SideEffectNoResult::Inst { inst: expr0_0 };
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term store32.
-pub fn constructor_store32<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: &MemArg,
-) -> Option<SideEffectNoResult> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 1538.
-    let expr0_0 = MInst::Store32 {
-        rd: pattern0_0,
-        mem: pattern1_0.clone(),
-    };
-    let expr1_0 = SideEffectNoResult::Inst { inst: expr0_0 };
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term store64.
-pub fn constructor_store64<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: &MemArg,
-) -> Option<SideEffectNoResult> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 1543.
-    let expr0_0 = MInst::Store64 {
-        rd: pattern0_0,
-        mem: pattern1_0.clone(),
-    };
-    let expr1_0 = SideEffectNoResult::Inst { inst: expr0_0 };
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term store8_imm.
-pub fn constructor_store8_imm<C: Context>(
-    ctx: &mut C,
-    arg0: u8,
-    arg1: &MemArg,
-) -> Option<SideEffectNoResult> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 1548.
-    let expr0_0 = MInst::StoreImm8 {
-        imm: pattern0_0,
-        mem: pattern1_0.clone(),
-    };
-    let expr1_0 = SideEffectNoResult::Inst { inst: expr0_0 };
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term store16_imm.
-pub fn constructor_store16_imm<C: Context>(
-    ctx: &mut C,
-    arg0: i16,
-    arg1: &MemArg,
-) -> Option<SideEffectNoResult> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 1553.
-    let expr0_0 = MInst::StoreImm16 {
-        imm: pattern0_0,
-        mem: pattern1_0.clone(),
-    };
-    let expr1_0 = SideEffectNoResult::Inst { inst: expr0_0 };
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term store32_simm16.
-pub fn constructor_store32_simm16<C: Context>(
-    ctx: &mut C,
-    arg0: i16,
-    arg1: &MemArg,
-) -> Option<SideEffectNoResult> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 1558.
-    let expr0_0 = MInst::StoreImm32SExt16 {
-        imm: pattern0_0,
-        mem: pattern1_0.clone(),
-    };
-    let expr1_0 = SideEffectNoResult::Inst { inst: expr0_0 };
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term store64_simm16.
-pub fn constructor_store64_simm16<C: Context>(
-    ctx: &mut C,
-    arg0: i16,
-    arg1: &MemArg,
-) -> Option<SideEffectNoResult> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 1563.
-    let expr0_0 = MInst::StoreImm64SExt16 {
-        imm: pattern0_0,
-        mem: pattern1_0.clone(),
-    };
-    let expr1_0 = SideEffectNoResult::Inst { inst: expr0_0 };
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term storerev16.
-pub fn constructor_storerev16<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: &MemArg,
-) -> Option<SideEffectNoResult> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 1568.
-    let expr0_0 = MInst::StoreRev16 {
-        rd: pattern0_0,
-        mem: pattern1_0.clone(),
-    };
-    let expr1_0 = SideEffectNoResult::Inst { inst: expr0_0 };
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term storerev32.
-pub fn constructor_storerev32<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: &MemArg,
-) -> Option<SideEffectNoResult> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 1573.
-    let expr0_0 = MInst::StoreRev32 {
-        rd: pattern0_0,
-        mem: pattern1_0.clone(),
-    };
-    let expr1_0 = SideEffectNoResult::Inst { inst: expr0_0 };
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term storerev64.
-pub fn constructor_storerev64<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: &MemArg,
-) -> Option<SideEffectNoResult> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 1578.
-    let expr0_0 = MInst::StoreRev64 {
-        rd: pattern0_0,
-        mem: pattern1_0.clone(),
-    };
-    let expr1_0 = SideEffectNoResult::Inst { inst: expr0_0 };
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term fpu_rr.
-pub fn constructor_fpu_rr<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &FPUOp1,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 1583.
-    let expr0_0 = C::temp_writable_reg(ctx, pattern0_0);
-    let expr1_0 = MInst::FpuRR {
-        fpu_op: pattern1_0.clone(),
-        rd: expr0_0,
-        rn: pattern2_0,
-    };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = C::writable_reg_to_reg(ctx, expr0_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term fpu_rrr.
-pub fn constructor_fpu_rrr<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &FPUOp2,
-    arg2: Reg,
-    arg3: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/s390x/inst.isle line 1590.
-    let expr0_0 = constructor_copy_writable_reg(ctx, pattern0_0, pattern2_0)?;
-    let expr1_0 = MInst::FpuRRR {
-        fpu_op: pattern1_0.clone(),
-        rd: expr0_0,
-        rm: pattern3_0,
-    };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = C::writable_reg_to_reg(ctx, expr0_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term fpu_rrrr.
-pub fn constructor_fpu_rrrr<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &FPUOp3,
-    arg2: Reg,
-    arg3: Reg,
-    arg4: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    let pattern4_0 = arg4;
-    // Rule at src/isa/s390x/inst.isle line 1597.
-    let expr0_0 = constructor_copy_writable_reg(ctx, pattern0_0, pattern2_0)?;
-    let expr1_0 = MInst::FpuRRRR {
-        fpu_op: pattern1_0.clone(),
-        rd: expr0_0,
-        rn: pattern3_0,
-        rm: pattern4_0,
-    };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = C::writable_reg_to_reg(ctx, expr0_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term fpu_copysign.
-pub fn constructor_fpu_copysign<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 1604.
-    let expr0_0 = C::temp_writable_reg(ctx, pattern0_0);
-    let expr1_0 = MInst::FpuCopysign {
-        rd: expr0_0,
-        rn: pattern1_0,
-        rm: pattern2_0,
-    };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = C::writable_reg_to_reg(ctx, expr0_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term fpu_cmp32.
-pub fn constructor_fpu_cmp32<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: Reg,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 1611.
-    let expr0_0 = MInst::FpuCmp32 {
-        rn: pattern0_0,
-        rm: pattern1_0,
-    };
-    let expr1_0 = ProducesFlags::ProducesFlagsSideEffect { inst: expr0_0 };
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term fpu_cmp64.
-pub fn constructor_fpu_cmp64<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: Reg,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 1616.
-    let expr0_0 = MInst::FpuCmp64 {
-        rn: pattern0_0,
-        rm: pattern1_0,
-    };
-    let expr1_0 = ProducesFlags::ProducesFlagsSideEffect { inst: expr0_0 };
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term fpu_to_int.
-pub fn constructor_fpu_to_int<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &FpuToIntOp,
-    arg2: Reg,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 1621.
-    let expr0_0 = C::temp_writable_reg(ctx, pattern0_0);
-    let expr1_0 = MInst::FpuToInt {
-        op: pattern1_0.clone(),
-        rd: expr0_0,
-        rn: pattern2_0,
-    };
-    let expr2_0 = C::writable_reg_to_reg(ctx, expr0_0);
-    let expr3_0 = ProducesFlags::ProducesFlagsReturnsReg {
-        inst: expr1_0,
-        result: expr2_0,
-    };
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term int_to_fpu.
-pub fn constructor_int_to_fpu<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &IntToFpuOp,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 1628.
-    let expr0_0 = C::temp_writable_reg(ctx, pattern0_0);
-    let expr1_0 = MInst::IntToFpu {
-        op: pattern1_0.clone(),
-        rd: expr0_0,
-        rn: pattern2_0,
-    };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = C::writable_reg_to_reg(ctx, expr0_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term fpu_round.
-pub fn constructor_fpu_round<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &FpuRoundMode,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 1635.
-    let expr0_0 = C::temp_writable_reg(ctx, pattern0_0);
-    let expr1_0 = MInst::FpuRound {
-        op: pattern1_0.clone(),
-        rd: expr0_0,
-        rn: pattern2_0,
-    };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = C::writable_reg_to_reg(ctx, expr0_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term fpuvec_rrr.
-pub fn constructor_fpuvec_rrr<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &FPUOp2,
-    arg2: Reg,
-    arg3: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/s390x/inst.isle line 1642.
-    let expr0_0 = C::temp_writable_reg(ctx, pattern0_0);
-    let expr1_0 = MInst::FpuVecRRR {
-        fpu_op: pattern1_0.clone(),
-        rd: expr0_0,
-        rn: pattern2_0,
-        rm: pattern3_0,
-    };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = C::writable_reg_to_reg(ctx, expr0_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term mov_to_fpr.
-pub fn constructor_mov_to_fpr<C: Context>(ctx: &mut C, arg0: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/s390x/inst.isle line 1649.
-    let expr0_0: Type = F64;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = MInst::MovToFpr {
-        rd: expr1_0,
-        rn: pattern0_0,
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term mov_from_fpr.
-pub fn constructor_mov_from_fpr<C: Context>(ctx: &mut C, arg0: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/s390x/inst.isle line 1656.
-    let expr0_0: Type = I64;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = MInst::MovFromFpr {
-        rd: expr1_0,
-        rn: pattern0_0,
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term fpu_load32.
-pub fn constructor_fpu_load32<C: Context>(ctx: &mut C, arg0: &MemArg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/s390x/inst.isle line 1663.
-    let expr0_0: Type = F32;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = MInst::FpuLoad32 {
-        rd: expr1_0,
-        mem: pattern0_0.clone(),
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term fpu_load64.
-pub fn constructor_fpu_load64<C: Context>(ctx: &mut C, arg0: &MemArg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/s390x/inst.isle line 1670.
-    let expr0_0: Type = F64;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = MInst::FpuLoad64 {
-        rd: expr1_0,
-        mem: pattern0_0.clone(),
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term fpu_loadrev32.
-pub fn constructor_fpu_loadrev32<C: Context>(ctx: &mut C, arg0: &MemArg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/s390x/inst.isle line 1677.
-    let expr0_0: Type = F32;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = MInst::FpuLoadRev32 {
-        rd: expr1_0,
-        mem: pattern0_0.clone(),
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term fpu_loadrev64.
-pub fn constructor_fpu_loadrev64<C: Context>(ctx: &mut C, arg0: &MemArg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/s390x/inst.isle line 1684.
-    let expr0_0: Type = F64;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = MInst::FpuLoadRev64 {
-        rd: expr1_0,
-        mem: pattern0_0.clone(),
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term fpu_store32.
-pub fn constructor_fpu_store32<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: &MemArg,
-) -> Option<SideEffectNoResult> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 1691.
-    let expr0_0 = MInst::FpuStore32 {
-        rd: pattern0_0,
-        mem: pattern1_0.clone(),
-    };
-    let expr1_0 = SideEffectNoResult::Inst { inst: expr0_0 };
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term fpu_store64.
-pub fn constructor_fpu_store64<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: &MemArg,
-) -> Option<SideEffectNoResult> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 1696.
-    let expr0_0 = MInst::FpuStore64 {
-        rd: pattern0_0,
-        mem: pattern1_0.clone(),
-    };
-    let expr1_0 = SideEffectNoResult::Inst { inst: expr0_0 };
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term fpu_storerev32.
-pub fn constructor_fpu_storerev32<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: &MemArg,
-) -> Option<SideEffectNoResult> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 1701.
-    let expr0_0 = MInst::FpuStoreRev32 {
-        rd: pattern0_0,
-        mem: pattern1_0.clone(),
-    };
-    let expr1_0 = SideEffectNoResult::Inst { inst: expr0_0 };
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term fpu_storerev64.
-pub fn constructor_fpu_storerev64<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: &MemArg,
-) -> Option<SideEffectNoResult> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 1706.
-    let expr0_0 = MInst::FpuStoreRev64 {
-        rd: pattern0_0,
-        mem: pattern1_0.clone(),
-    };
-    let expr1_0 = SideEffectNoResult::Inst { inst: expr0_0 };
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term load_ext_name_far.
-pub fn constructor_load_ext_name_far<C: Context>(
-    ctx: &mut C,
-    arg0: ExternalName,
-    arg1: i64,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 1711.
-    let expr0_0: Type = I64;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = C::box_external_name(ctx, pattern0_0);
-    let expr3_0 = MInst::LoadExtNameFar {
-        rd: expr1_0,
-        name: expr2_0,
-        offset: pattern1_0,
-    };
-    let expr4_0 = C::emit(ctx, &expr3_0);
-    let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr5_0);
-}
-
-// Generated as internal constructor for term load_addr.
-pub fn constructor_load_addr<C: Context>(ctx: &mut C, arg0: &MemArg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/s390x/inst.isle line 1719.
-    let expr0_0: Type = I64;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = MInst::LoadAddr {
-        rd: expr1_0,
-        mem: pattern0_0.clone(),
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term jump_impl.
-pub fn constructor_jump_impl<C: Context>(
-    ctx: &mut C,
-    arg0: MachLabel,
-) -> Option<SideEffectNoResult> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/s390x/inst.isle line 1726.
-    let expr0_0 = MInst::Jump { dest: pattern0_0 };
-    let expr1_0 = SideEffectNoResult::Inst { inst: expr0_0 };
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term cond_br.
-pub fn constructor_cond_br<C: Context>(
-    ctx: &mut C,
-    arg0: MachLabel,
-    arg1: MachLabel,
-    arg2: &Cond,
-) -> Option<SideEffectNoResult> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 1731.
-    let expr0_0 = MInst::CondBr {
-        taken: pattern0_0,
-        not_taken: pattern1_0,
-        cond: pattern2_0.clone(),
-    };
-    let expr1_0 = SideEffectNoResult::Inst { inst: expr0_0 };
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term oneway_cond_br.
-pub fn constructor_oneway_cond_br<C: Context>(
-    ctx: &mut C,
-    arg0: MachLabel,
-    arg1: &Cond,
-) -> Option<SideEffectNoResult> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 1736.
-    let expr0_0 = MInst::OneWayCondBr {
-        target: pattern0_0,
-        cond: pattern1_0.clone(),
-    };
-    let expr1_0 = SideEffectNoResult::Inst { inst: expr0_0 };
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term jt_sequence.
-pub fn constructor_jt_sequence<C: Context>(
-    ctx: &mut C,
-    arg0: Reg,
-    arg1: &VecMachLabel,
-) -> Option<SideEffectNoResult> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 1741.
-    let expr0_0 = MInst::JTSequence {
-        ridx: pattern0_0,
-        targets: pattern1_0.clone(),
-    };
-    let expr1_0 = SideEffectNoResult::Inst { inst: expr0_0 };
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term drop_flags.
-pub fn constructor_drop_flags<C: Context>(ctx: &mut C, arg0: &ProducesFlags) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    if let &ProducesFlags::ProducesFlagsReturnsReg {
-        inst: ref pattern1_0,
-        result: pattern1_1,
-    } = pattern0_0
-    {
-        // Rule at src/isa/s390x/inst.isle line 1746.
-        let expr0_0 = C::emit(ctx, pattern1_0);
-        return Some(pattern1_1);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term push_alu_reg.
-pub fn constructor_push_alu_reg<C: Context>(
-    ctx: &mut C,
-    arg0: &VecMInstBuilder,
-    arg1: &ALUOp,
-    arg2: WritableReg,
-    arg3: Reg,
-    arg4: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    if let Some(pattern3_0) = C::real_reg(ctx, pattern2_0) {
-        let pattern4_0 = arg3;
-        let pattern5_0 = arg4;
-        // Rule at src/isa/s390x/inst.isle line 1785.
-        let expr0_0 = MInst::AluRRR {
-            alu_op: pattern1_0.clone(),
-            rd: pattern3_0,
-            rn: pattern4_0,
-            rm: pattern5_0,
-        };
-        let expr1_0 = C::inst_builder_push(ctx, pattern0_0, &expr0_0);
-        let expr2_0 = C::writable_reg_to_reg(ctx, pattern3_0);
-        return Some(expr2_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term push_alu_uimm32shifted.
-pub fn constructor_push_alu_uimm32shifted<C: Context>(
-    ctx: &mut C,
-    arg0: &VecMInstBuilder,
-    arg1: &ALUOp,
-    arg2: WritableReg,
-    arg3: Reg,
-    arg4: UImm32Shifted,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    if let Some(pattern3_0) = C::real_reg(ctx, pattern2_0) {
-        let pattern4_0 = arg3;
-        let closure5 = || {
-            return Some(pattern3_0);
-        };
-        if let Some(pattern5_0) = closure5() {
-            if let Some(()) = C::same_reg(ctx, pattern4_0, pattern5_0) {
-                let pattern7_0 = arg4;
-                // Rule at src/isa/s390x/inst.isle line 1791.
-                let expr0_0 = MInst::AluRUImm32Shifted {
-                    alu_op: pattern1_0.clone(),
-                    rd: pattern3_0,
-                    imm: pattern7_0,
-                };
-                let expr1_0 = C::inst_builder_push(ctx, pattern0_0, &expr0_0);
-                let expr2_0 = C::writable_reg_to_reg(ctx, pattern3_0);
-                return Some(expr2_0);
-            }
-        }
-    }
-    return None;
-}
-
-// Generated as internal constructor for term push_shift.
-pub fn constructor_push_shift<C: Context>(
-    ctx: &mut C,
-    arg0: &VecMInstBuilder,
-    arg1: &ShiftOp,
-    arg2: WritableReg,
-    arg3: Reg,
-    arg4: u8,
-    arg5: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    if let Some(pattern3_0) = C::real_reg(ctx, pattern2_0) {
-        let pattern4_0 = arg3;
-        let pattern5_0 = arg4;
-        let pattern6_0 = arg5;
-        // Rule at src/isa/s390x/inst.isle line 1797.
-        let expr0_0 = MInst::ShiftRR {
-            shift_op: pattern1_0.clone(),
-            rd: pattern3_0,
-            rn: pattern4_0,
-            shift_imm: pattern5_0,
-            shift_reg: pattern6_0,
-        };
-        let expr1_0 = C::inst_builder_push(ctx, pattern0_0, &expr0_0);
-        let expr2_0 = C::writable_reg_to_reg(ctx, pattern3_0);
-        return Some(expr2_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term push_rxsbg.
-pub fn constructor_push_rxsbg<C: Context>(
-    ctx: &mut C,
-    arg0: &VecMInstBuilder,
-    arg1: &RxSBGOp,
-    arg2: WritableReg,
-    arg3: Reg,
-    arg4: Reg,
-    arg5: u8,
-    arg6: u8,
-    arg7: i8,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    if let Some(pattern3_0) = C::real_reg(ctx, pattern2_0) {
-        let pattern4_0 = arg3;
-        let closure5 = || {
-            return Some(pattern3_0);
-        };
-        if let Some(pattern5_0) = closure5() {
-            if let Some(()) = C::same_reg(ctx, pattern4_0, pattern5_0) {
-                let pattern7_0 = arg4;
-                let pattern8_0 = arg5;
-                let pattern9_0 = arg6;
-                let pattern10_0 = arg7;
-                // Rule at src/isa/s390x/inst.isle line 1804.
-                let expr0_0 = MInst::RxSBG {
-                    op: pattern1_0.clone(),
-                    rd: pattern3_0,
-                    rn: pattern7_0,
-                    start_bit: pattern8_0,
-                    end_bit: pattern9_0,
-                    rotate_amt: pattern10_0,
-                };
-                let expr1_0 = C::inst_builder_push(ctx, pattern0_0, &expr0_0);
-                let expr2_0 = C::writable_reg_to_reg(ctx, pattern3_0);
-                return Some(expr2_0);
-            }
-        }
-    }
-    return None;
-}
-
-// Generated as internal constructor for term push_unary.
-pub fn constructor_push_unary<C: Context>(
-    ctx: &mut C,
-    arg0: &VecMInstBuilder,
-    arg1: &UnaryOp,
-    arg2: WritableReg,
-    arg3: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    if let Some(pattern3_0) = C::real_reg(ctx, pattern2_0) {
-        let pattern4_0 = arg3;
-        // Rule at src/isa/s390x/inst.isle line 1811.
-        let expr0_0 = MInst::UnaryRR {
-            op: pattern1_0.clone(),
-            rd: pattern3_0,
-            rn: pattern4_0,
-        };
-        let expr1_0 = C::inst_builder_push(ctx, pattern0_0, &expr0_0);
-        let expr2_0 = C::writable_reg_to_reg(ctx, pattern3_0);
-        return Some(expr2_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term push_atomic_cas32.
-pub fn constructor_push_atomic_cas32<C: Context>(
-    ctx: &mut C,
-    arg0: &VecMInstBuilder,
-    arg1: WritableReg,
-    arg2: Reg,
-    arg3: &MemArg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    if let Some(pattern2_0) = C::real_reg(ctx, pattern1_0) {
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/s390x/inst.isle line 1817.
-        let expr0_0 = MInst::AtomicCas32 {
-            rd: pattern2_0,
-            rn: pattern3_0,
-            mem: pattern4_0.clone(),
-        };
-        let expr1_0 = C::inst_builder_push(ctx, pattern0_0, &expr0_0);
-        let expr2_0 = C::writable_reg_to_reg(ctx, pattern2_0);
-        return Some(expr2_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term push_atomic_cas64.
-pub fn constructor_push_atomic_cas64<C: Context>(
-    ctx: &mut C,
-    arg0: &VecMInstBuilder,
-    arg1: WritableReg,
-    arg2: Reg,
-    arg3: &MemArg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    if let Some(pattern2_0) = C::real_reg(ctx, pattern1_0) {
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/s390x/inst.isle line 1823.
-        let expr0_0 = MInst::AtomicCas64 {
-            rd: pattern2_0,
-            rn: pattern3_0,
-            mem: pattern4_0.clone(),
-        };
-        let expr1_0 = C::inst_builder_push(ctx, pattern0_0, &expr0_0);
-        let expr2_0 = C::writable_reg_to_reg(ctx, pattern2_0);
-        return Some(expr2_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term push_break_if.
-pub fn constructor_push_break_if<C: Context>(
-    ctx: &mut C,
-    arg0: &VecMInstBuilder,
-    arg1: &ProducesFlags,
-    arg2: &Cond,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    if let &ProducesFlags::ProducesFlagsSideEffect {
-        inst: ref pattern2_0,
-    } = pattern1_0
-    {
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/inst.isle line 1829.
-        let expr0_0 = C::inst_builder_push(ctx, pattern0_0, pattern2_0);
-        let expr1_0 = MInst::CondBreak {
-            cond: pattern3_0.clone(),
-        };
-        let expr2_0 = C::inst_builder_push(ctx, pattern0_0, &expr1_0);
-        let expr3_0 = C::invalid_reg(ctx);
-        return Some(expr3_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term emit_loop.
-pub fn constructor_emit_loop<C: Context>(
-    ctx: &mut C,
-    arg0: &VecMInstBuilder,
-    arg1: &Cond,
-) -> Option<Unit> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 1836.
-    let expr0_0 = C::inst_builder_finish(ctx, pattern0_0);
-    let expr1_0 = MInst::Loop {
-        body: expr0_0,
-        cond: pattern1_0.clone(),
-    };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term emit_mov.
-pub fn constructor_emit_mov<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: WritableReg,
-    arg2: Reg,
-) -> Option<Unit> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == F32 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/inst.isle line 1851.
-        let expr0_0 = MInst::FpuMove32 {
-            rd: pattern2_0,
-            rn: pattern3_0,
-        };
-        let expr1_0 = C::emit(ctx, &expr0_0);
-        return Some(expr1_0);
-    }
-    if pattern0_0 == F64 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/inst.isle line 1854.
-        let expr0_0 = MInst::FpuMove64 {
-            rd: pattern2_0,
-            rn: pattern3_0,
-        };
-        let expr1_0 = C::emit(ctx, &expr0_0);
-        return Some(expr1_0);
-    }
-    if let Some(pattern1_0) = C::gpr32_ty(ctx, pattern0_0) {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/inst.isle line 1845.
-        let expr0_0 = MInst::Mov32 {
-            rd: pattern2_0,
-            rm: pattern3_0,
-        };
-        let expr1_0 = C::emit(ctx, &expr0_0);
-        return Some(expr1_0);
-    }
-    if let Some(pattern1_0) = C::gpr64_ty(ctx, pattern0_0) {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/inst.isle line 1848.
-        let expr0_0 = MInst::Mov64 {
-            rd: pattern2_0,
-            rm: pattern3_0,
-        };
-        let expr1_0 = C::emit(ctx, &expr0_0);
-        return Some(expr1_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term copy_writable_reg.
-pub fn constructor_copy_writable_reg<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-) -> Option<WritableReg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 1859.
-    let expr0_0 = C::temp_writable_reg(ctx, pattern0_0);
-    let expr1_0 = constructor_emit_mov(ctx, pattern0_0, expr0_0, pattern1_0)?;
-    return Some(expr0_0);
-}
-
-// Generated as internal constructor for term copy_reg.
-pub fn constructor_copy_reg<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 1866.
-    let expr0_0 = constructor_copy_writable_reg(ctx, pattern0_0, pattern1_0)?;
-    let expr1_0 = C::writable_reg_to_reg(ctx, expr0_0);
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term emit_load.
-pub fn constructor_emit_load<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: WritableReg,
-    arg2: &MemArg,
-) -> Option<Unit> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I32 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/inst.isle line 1870.
-        let expr0_0 = MInst::Load32 {
-            rd: pattern2_0,
-            mem: pattern3_0.clone(),
-        };
-        let expr1_0 = C::emit(ctx, &expr0_0);
-        return Some(expr1_0);
-    }
-    if pattern0_0 == I64 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/inst.isle line 1872.
-        let expr0_0 = MInst::Load64 {
-            rd: pattern2_0,
-            mem: pattern3_0.clone(),
-        };
-        let expr1_0 = C::emit(ctx, &expr0_0);
-        return Some(expr1_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term emit_imm.
-pub fn constructor_emit_imm<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: WritableReg,
-    arg2: u64,
-) -> Option<Unit> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == F32 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/inst.isle line 1928.
-        let expr0_0 = C::u64_as_u32(ctx, pattern3_0);
-        let expr1_0 = MInst::LoadFpuConst32 {
-            rd: pattern2_0,
-            const_data: expr0_0,
-        };
-        let expr2_0 = C::emit(ctx, &expr1_0);
-        return Some(expr2_0);
-    }
-    if pattern0_0 == F64 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/inst.isle line 1933.
-        let expr0_0 = MInst::LoadFpuConst64 {
-            rd: pattern2_0,
-            const_data: pattern3_0,
-        };
-        let expr1_0 = C::emit(ctx, &expr0_0);
-        return Some(expr1_0);
-    }
-    if let Some(pattern1_0) = C::fits_in_16(ctx, pattern0_0) {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/inst.isle line 1882.
-        let expr0_0 = C::u64_as_i16(ctx, pattern3_0);
-        let expr1_0 = MInst::Mov32SImm16 {
-            rd: pattern2_0,
-            imm: expr0_0,
-        };
-        let expr2_0 = C::emit(ctx, &expr1_0);
-        return Some(expr2_0);
-    }
-    if let Some(pattern1_0) = C::gpr32_ty(ctx, pattern0_0) {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        if let Some(pattern4_0) = C::i16_from_u64(ctx, pattern3_0) {
-            // Rule at src/isa/s390x/inst.isle line 1886.
-            let expr0_0 = MInst::Mov32SImm16 {
-                rd: pattern2_0,
-                imm: pattern4_0,
-            };
-            let expr1_0 = C::emit(ctx, &expr0_0);
-            return Some(expr1_0);
-        }
-        // Rule at src/isa/s390x/inst.isle line 1890.
-        let expr0_0 = C::u64_as_u32(ctx, pattern3_0);
-        let expr1_0 = MInst::Mov32Imm {
-            rd: pattern2_0,
-            imm: expr0_0,
-        };
-        let expr2_0 = C::emit(ctx, &expr1_0);
-        return Some(expr2_0);
-    }
-    if let Some(pattern1_0) = C::gpr64_ty(ctx, pattern0_0) {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        if let Some(pattern4_0) = C::u64_nonzero_hipart(ctx, pattern3_0) {
-            if let Some(pattern5_0) = C::u64_nonzero_lopart(ctx, pattern3_0) {
-                // Rule at src/isa/s390x/inst.isle line 1910.
-                let expr0_0 = constructor_emit_imm(ctx, pattern1_0, pattern2_0, pattern4_0)?;
-                let expr1_0 = constructor_emit_insert_imm(ctx, pattern2_0, pattern5_0)?;
-                return Some(expr1_0);
-            }
-        }
-        if let Some(pattern4_0) = C::i16_from_u64(ctx, pattern3_0) {
-            // Rule at src/isa/s390x/inst.isle line 1894.
-            let expr0_0 = MInst::Mov64SImm16 {
-                rd: pattern2_0,
-                imm: pattern4_0,
-            };
-            let expr1_0 = C::emit(ctx, &expr0_0);
-            return Some(expr1_0);
-        }
-        if let Some(pattern4_0) = C::i32_from_u64(ctx, pattern3_0) {
-            // Rule at src/isa/s390x/inst.isle line 1898.
-            let expr0_0 = MInst::Mov64SImm32 {
-                rd: pattern2_0,
-                imm: pattern4_0,
-            };
-            let expr1_0 = C::emit(ctx, &expr0_0);
-            return Some(expr1_0);
-        }
-        if let Some(pattern4_0) = C::uimm32shifted_from_u64(ctx, pattern3_0) {
-            // Rule at src/isa/s390x/inst.isle line 1906.
-            let expr0_0 = MInst::Mov64UImm32Shifted {
-                rd: pattern2_0,
-                imm: pattern4_0,
-            };
-            let expr1_0 = C::emit(ctx, &expr0_0);
-            return Some(expr1_0);
-        }
-        if let Some(pattern4_0) = C::uimm16shifted_from_u64(ctx, pattern3_0) {
-            // Rule at src/isa/s390x/inst.isle line 1902.
-            let expr0_0 = MInst::Mov64UImm16Shifted {
-                rd: pattern2_0,
-                imm: pattern4_0,
-            };
-            let expr1_0 = C::emit(ctx, &expr0_0);
-            return Some(expr1_0);
-        }
-    }
-    return None;
-}
-
-// Generated as internal constructor for term emit_insert_imm.
-pub fn constructor_emit_insert_imm<C: Context>(
-    ctx: &mut C,
-    arg0: WritableReg,
-    arg1: u64,
-) -> Option<Unit> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    if let Some(pattern2_0) = C::uimm32shifted_from_u64(ctx, pattern1_0) {
-        // Rule at src/isa/s390x/inst.isle line 1923.
-        let expr0_0 = MInst::Insert64UImm32Shifted {
-            rd: pattern0_0,
-            imm: pattern2_0,
-        };
-        let expr1_0 = C::emit(ctx, &expr0_0);
-        return Some(expr1_0);
-    }
-    if let Some(pattern2_0) = C::uimm16shifted_from_u64(ctx, pattern1_0) {
-        // Rule at src/isa/s390x/inst.isle line 1919.
-        let expr0_0 = MInst::Insert64UImm16Shifted {
-            rd: pattern0_0,
-            imm: pattern2_0,
-        };
-        let expr1_0 = C::emit(ctx, &expr0_0);
-        return Some(expr1_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term imm.
-pub fn constructor_imm<C: Context>(ctx: &mut C, arg0: Type, arg1: u64) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 1938.
-    let expr0_0 = C::temp_writable_reg(ctx, pattern0_0);
-    let expr1_0 = constructor_emit_imm(ctx, pattern0_0, expr0_0, pattern1_0)?;
-    let expr2_0 = C::writable_reg_to_reg(ctx, expr0_0);
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term imm_regpair_lo.
-pub fn constructor_imm_regpair_lo<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: u64,
-    arg2: &RegPair,
-) -> Option<RegPair> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 1946.
-    let expr0_0 = constructor_copy_writable_regpair(ctx, pattern2_0)?;
-    let expr1_0 = constructor_writable_regpair_lo(ctx, &expr0_0)?;
-    let expr2_0 = constructor_emit_imm(ctx, pattern0_0, expr1_0, pattern1_0)?;
-    let expr3_0 = constructor_writable_regpair_to_regpair(ctx, &expr0_0)?;
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term imm_regpair_hi.
-pub fn constructor_imm_regpair_hi<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: u64,
-    arg2: &RegPair,
-) -> Option<RegPair> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 1954.
-    let expr0_0 = constructor_copy_writable_regpair(ctx, pattern2_0)?;
-    let expr1_0 = constructor_writable_regpair_hi(ctx, &expr0_0)?;
-    let expr2_0 = constructor_emit_imm(ctx, pattern0_0, expr1_0, pattern1_0)?;
-    let expr3_0 = constructor_writable_regpair_to_regpair(ctx, &expr0_0)?;
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term ty_ext32.
-pub fn constructor_ty_ext32<C: Context>(ctx: &mut C, arg0: Type) -> Option<Type> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I8 {
-        // Rule at src/isa/s390x/inst.isle line 1964.
-        let expr0_0: Type = I32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I16 {
-        // Rule at src/isa/s390x/inst.isle line 1965.
-        let expr0_0: Type = I32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I32 {
-        // Rule at src/isa/s390x/inst.isle line 1966.
-        let expr0_0: Type = I32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I64 {
-        // Rule at src/isa/s390x/inst.isle line 1967.
-        let expr0_0: Type = I64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term ty_ext64.
-pub fn constructor_ty_ext64<C: Context>(ctx: &mut C, arg0: Type) -> Option<Type> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I8 {
-        // Rule at src/isa/s390x/inst.isle line 1971.
-        let expr0_0: Type = I64;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I16 {
-        // Rule at src/isa/s390x/inst.isle line 1972.
-        let expr0_0: Type = I64;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I32 {
-        // Rule at src/isa/s390x/inst.isle line 1973.
-        let expr0_0: Type = I64;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I64 {
-        // Rule at src/isa/s390x/inst.isle line 1974.
-        let expr0_0: Type = I64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term emit_zext32_reg.
-pub fn constructor_emit_zext32_reg<C: Context>(
-    ctx: &mut C,
-    arg0: WritableReg,
-    arg1: Type,
-    arg2: Reg,
-) -> Option<Unit> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 1979.
-    let expr0_0: bool = false;
-    let expr1_0 = C::ty_bits(ctx, pattern1_0);
-    let expr2_0: u8 = 32;
-    let expr3_0 = MInst::Extend {
-        rd: pattern0_0,
-        rn: pattern2_0,
-        signed: expr0_0,
-        from_bits: expr1_0,
-        to_bits: expr2_0,
-    };
-    let expr4_0 = C::emit(ctx, &expr3_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term emit_sext32_reg.
-pub fn constructor_emit_sext32_reg<C: Context>(
-    ctx: &mut C,
-    arg0: WritableReg,
-    arg1: Type,
-    arg2: Reg,
-) -> Option<Unit> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 1985.
-    let expr0_0: bool = true;
-    let expr1_0 = C::ty_bits(ctx, pattern1_0);
-    let expr2_0: u8 = 32;
-    let expr3_0 = MInst::Extend {
-        rd: pattern0_0,
-        rn: pattern2_0,
-        signed: expr0_0,
-        from_bits: expr1_0,
-        to_bits: expr2_0,
-    };
-    let expr4_0 = C::emit(ctx, &expr3_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term emit_zext64_reg.
-pub fn constructor_emit_zext64_reg<C: Context>(
-    ctx: &mut C,
-    arg0: WritableReg,
-    arg1: Type,
-    arg2: Reg,
-) -> Option<Unit> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 1991.
-    let expr0_0: bool = false;
-    let expr1_0 = C::ty_bits(ctx, pattern1_0);
-    let expr2_0: u8 = 64;
-    let expr3_0 = MInst::Extend {
-        rd: pattern0_0,
-        rn: pattern2_0,
-        signed: expr0_0,
-        from_bits: expr1_0,
-        to_bits: expr2_0,
-    };
-    let expr4_0 = C::emit(ctx, &expr3_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term emit_sext64_reg.
-pub fn constructor_emit_sext64_reg<C: Context>(
-    ctx: &mut C,
-    arg0: WritableReg,
-    arg1: Type,
-    arg2: Reg,
-) -> Option<Unit> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 1997.
-    let expr0_0: bool = true;
-    let expr1_0 = C::ty_bits(ctx, pattern1_0);
-    let expr2_0: u8 = 64;
-    let expr3_0 = MInst::Extend {
-        rd: pattern0_0,
-        rn: pattern2_0,
-        signed: expr0_0,
-        from_bits: expr1_0,
-        to_bits: expr2_0,
-    };
-    let expr4_0 = C::emit(ctx, &expr3_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term zext32_reg.
-pub fn constructor_zext32_reg<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 2003.
-    let expr0_0: Type = I32;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = constructor_emit_zext32_reg(ctx, expr1_0, pattern0_0, pattern1_0)?;
-    let expr3_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term sext32_reg.
-pub fn constructor_sext32_reg<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 2011.
-    let expr0_0: Type = I32;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = constructor_emit_sext32_reg(ctx, expr1_0, pattern0_0, pattern1_0)?;
-    let expr3_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term zext64_reg.
-pub fn constructor_zext64_reg<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 2019.
-    let expr0_0: Type = I64;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = constructor_emit_zext64_reg(ctx, expr1_0, pattern0_0, pattern1_0)?;
-    let expr3_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term sext64_reg.
-pub fn constructor_sext64_reg<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 2027.
-    let expr0_0: Type = I64;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = constructor_emit_sext64_reg(ctx, expr1_0, pattern0_0, pattern1_0)?;
-    let expr3_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term emit_zext32_mem.
-pub fn constructor_emit_zext32_mem<C: Context>(
-    ctx: &mut C,
-    arg0: WritableReg,
-    arg1: Type,
-    arg2: &MemArg,
-) -> Option<Unit> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    if pattern1_0 == I8 {
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/inst.isle line 2035.
-        let expr0_0 = MInst::Load32ZExt8 {
-            rd: pattern0_0,
-            mem: pattern3_0.clone(),
-        };
-        let expr1_0 = C::emit(ctx, &expr0_0);
-        return Some(expr1_0);
-    }
-    if pattern1_0 == I16 {
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/inst.isle line 2036.
-        let expr0_0 = MInst::Load32ZExt16 {
-            rd: pattern0_0,
-            mem: pattern3_0.clone(),
-        };
-        let expr1_0 = C::emit(ctx, &expr0_0);
-        return Some(expr1_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term emit_sext32_mem.
-pub fn constructor_emit_sext32_mem<C: Context>(
-    ctx: &mut C,
-    arg0: WritableReg,
-    arg1: Type,
-    arg2: &MemArg,
-) -> Option<Unit> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    if pattern1_0 == I8 {
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/inst.isle line 2040.
-        let expr0_0 = MInst::Load32SExt8 {
-            rd: pattern0_0,
-            mem: pattern3_0.clone(),
-        };
-        let expr1_0 = C::emit(ctx, &expr0_0);
-        return Some(expr1_0);
-    }
-    if pattern1_0 == I16 {
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/inst.isle line 2041.
-        let expr0_0 = MInst::Load32SExt16 {
-            rd: pattern0_0,
-            mem: pattern3_0.clone(),
-        };
-        let expr1_0 = C::emit(ctx, &expr0_0);
-        return Some(expr1_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term emit_zext64_mem.
-pub fn constructor_emit_zext64_mem<C: Context>(
-    ctx: &mut C,
-    arg0: WritableReg,
-    arg1: Type,
-    arg2: &MemArg,
-) -> Option<Unit> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    if pattern1_0 == I8 {
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/inst.isle line 2045.
-        let expr0_0 = MInst::Load64ZExt8 {
-            rd: pattern0_0,
-            mem: pattern3_0.clone(),
-        };
-        let expr1_0 = C::emit(ctx, &expr0_0);
-        return Some(expr1_0);
-    }
-    if pattern1_0 == I16 {
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/inst.isle line 2046.
-        let expr0_0 = MInst::Load64ZExt16 {
-            rd: pattern0_0,
-            mem: pattern3_0.clone(),
-        };
-        let expr1_0 = C::emit(ctx, &expr0_0);
-        return Some(expr1_0);
-    }
-    if pattern1_0 == I32 {
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/inst.isle line 2047.
-        let expr0_0 = MInst::Load64ZExt32 {
-            rd: pattern0_0,
-            mem: pattern3_0.clone(),
-        };
-        let expr1_0 = C::emit(ctx, &expr0_0);
-        return Some(expr1_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term emit_sext64_mem.
-pub fn constructor_emit_sext64_mem<C: Context>(
-    ctx: &mut C,
-    arg0: WritableReg,
-    arg1: Type,
-    arg2: &MemArg,
-) -> Option<Unit> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    if pattern1_0 == I8 {
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/inst.isle line 2051.
-        let expr0_0 = MInst::Load64SExt8 {
-            rd: pattern0_0,
-            mem: pattern3_0.clone(),
-        };
-        let expr1_0 = C::emit(ctx, &expr0_0);
-        return Some(expr1_0);
-    }
-    if pattern1_0 == I16 {
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/inst.isle line 2052.
-        let expr0_0 = MInst::Load64SExt16 {
-            rd: pattern0_0,
-            mem: pattern3_0.clone(),
-        };
-        let expr1_0 = C::emit(ctx, &expr0_0);
-        return Some(expr1_0);
-    }
-    if pattern1_0 == I32 {
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/inst.isle line 2053.
-        let expr0_0 = MInst::Load64SExt32 {
-            rd: pattern0_0,
-            mem: pattern3_0.clone(),
-        };
-        let expr1_0 = C::emit(ctx, &expr0_0);
-        return Some(expr1_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term zext32_mem.
-pub fn constructor_zext32_mem<C: Context>(ctx: &mut C, arg0: Type, arg1: &MemArg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 2057.
-    let expr0_0: Type = I32;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = constructor_emit_zext32_mem(ctx, expr1_0, pattern0_0, pattern1_0)?;
-    let expr3_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term sext32_mem.
-pub fn constructor_sext32_mem<C: Context>(ctx: &mut C, arg0: Type, arg1: &MemArg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 2064.
-    let expr0_0: Type = I32;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = constructor_emit_sext32_mem(ctx, expr1_0, pattern0_0, pattern1_0)?;
-    let expr3_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term zext64_mem.
-pub fn constructor_zext64_mem<C: Context>(ctx: &mut C, arg0: Type, arg1: &MemArg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 2071.
-    let expr0_0: Type = I64;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = constructor_emit_zext64_mem(ctx, expr1_0, pattern0_0, pattern1_0)?;
-    let expr3_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term sext64_mem.
-pub fn constructor_sext64_mem<C: Context>(ctx: &mut C, arg0: Type, arg1: &MemArg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 2078.
-    let expr0_0: Type = I64;
-    let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
-    let expr2_0 = constructor_emit_sext64_mem(ctx, expr1_0, pattern0_0, pattern1_0)?;
-    let expr3_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term emit_put_in_reg_zext32.
-pub fn constructor_emit_put_in_reg_zext32<C: Context>(
-    ctx: &mut C,
-    arg0: WritableReg,
-    arg1: Value,
-) -> Option<Unit> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = C::value_type(ctx, pattern1_0);
-    if let Some(pattern3_0) = C::u64_from_value(ctx, pattern1_0) {
-        // Rule at src/isa/s390x/inst.isle line 2086.
-        let expr0_0 = constructor_ty_ext32(ctx, pattern2_0)?;
-        let expr1_0 = constructor_emit_imm(ctx, expr0_0, pattern0_0, pattern3_0)?;
-        return Some(expr1_0);
-    }
-    if let Some(pattern3_0) = C::fits_in_16(ctx, pattern2_0) {
-        if let Some(pattern4_0) = C::sinkable_inst(ctx, pattern1_0) {
-            let pattern5_0 = C::inst_data(ctx, pattern4_0);
-            if let &InstructionData::Load {
-                opcode: ref pattern6_0,
-                arg: pattern6_1,
-                flags: pattern6_2,
-                offset: pattern6_3,
-            } = &pattern5_0
-            {
-                if let &Opcode::Load = pattern6_0 {
-                    if let Some(()) = C::bigendian(ctx, pattern6_2) {
-                        // Rule at src/isa/s390x/inst.isle line 2088.
-                        let expr0_0 = constructor_sink_load(ctx, pattern4_0)?;
-                        let expr1_0 =
-                            constructor_emit_zext32_mem(ctx, pattern0_0, pattern3_0, &expr0_0)?;
-                        return Some(expr1_0);
-                    }
-                }
-            }
-        }
-        // Rule at src/isa/s390x/inst.isle line 2090.
-        let expr0_0 = C::put_in_reg(ctx, pattern1_0);
-        let expr1_0 = constructor_emit_zext32_reg(ctx, pattern0_0, pattern3_0, expr0_0)?;
-        return Some(expr1_0);
-    }
-    if let Some(pattern3_0) = C::ty_32_or_64(ctx, pattern2_0) {
-        // Rule at src/isa/s390x/inst.isle line 2092.
-        let expr0_0 = C::put_in_reg(ctx, pattern1_0);
-        let expr1_0 = constructor_emit_mov(ctx, pattern3_0, pattern0_0, expr0_0)?;
-        return Some(expr1_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term emit_put_in_reg_sext32.
-pub fn constructor_emit_put_in_reg_sext32<C: Context>(
-    ctx: &mut C,
-    arg0: WritableReg,
-    arg1: Value,
-) -> Option<Unit> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = C::value_type(ctx, pattern1_0);
-    if let Some(pattern3_0) = C::u64_from_signed_value(ctx, pattern1_0) {
-        // Rule at src/isa/s390x/inst.isle line 2097.
-        let expr0_0 = constructor_ty_ext32(ctx, pattern2_0)?;
-        let expr1_0 = constructor_emit_imm(ctx, expr0_0, pattern0_0, pattern3_0)?;
-        return Some(expr1_0);
-    }
-    if let Some(pattern3_0) = C::fits_in_16(ctx, pattern2_0) {
-        if let Some(pattern4_0) = C::sinkable_inst(ctx, pattern1_0) {
-            let pattern5_0 = C::inst_data(ctx, pattern4_0);
-            if let &InstructionData::Load {
-                opcode: ref pattern6_0,
-                arg: pattern6_1,
-                flags: pattern6_2,
-                offset: pattern6_3,
-            } = &pattern5_0
-            {
-                if let &Opcode::Load = pattern6_0 {
-                    if let Some(()) = C::bigendian(ctx, pattern6_2) {
-                        // Rule at src/isa/s390x/inst.isle line 2099.
-                        let expr0_0 = constructor_sink_load(ctx, pattern4_0)?;
-                        let expr1_0 =
-                            constructor_emit_sext32_mem(ctx, pattern0_0, pattern3_0, &expr0_0)?;
-                        return Some(expr1_0);
-                    }
-                }
-            }
-        }
-        // Rule at src/isa/s390x/inst.isle line 2101.
-        let expr0_0 = C::put_in_reg(ctx, pattern1_0);
-        let expr1_0 = constructor_emit_sext32_reg(ctx, pattern0_0, pattern3_0, expr0_0)?;
-        return Some(expr1_0);
-    }
-    if let Some(pattern3_0) = C::ty_32_or_64(ctx, pattern2_0) {
-        // Rule at src/isa/s390x/inst.isle line 2103.
-        let expr0_0 = C::put_in_reg(ctx, pattern1_0);
-        let expr1_0 = constructor_emit_mov(ctx, pattern3_0, pattern0_0, expr0_0)?;
-        return Some(expr1_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term emit_put_in_reg_zext64.
-pub fn constructor_emit_put_in_reg_zext64<C: Context>(
-    ctx: &mut C,
-    arg0: WritableReg,
-    arg1: Value,
-) -> Option<Unit> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = C::value_type(ctx, pattern1_0);
-    if let Some(pattern3_0) = C::u64_from_value(ctx, pattern1_0) {
-        // Rule at src/isa/s390x/inst.isle line 2108.
-        let expr0_0 = constructor_ty_ext64(ctx, pattern2_0)?;
-        let expr1_0 = constructor_emit_imm(ctx, expr0_0, pattern0_0, pattern3_0)?;
-        return Some(expr1_0);
-    }
-    if let Some(pattern3_0) = C::gpr32_ty(ctx, pattern2_0) {
-        if let Some(pattern4_0) = C::sinkable_inst(ctx, pattern1_0) {
-            let pattern5_0 = C::inst_data(ctx, pattern4_0);
-            if let &InstructionData::Load {
-                opcode: ref pattern6_0,
-                arg: pattern6_1,
-                flags: pattern6_2,
-                offset: pattern6_3,
-            } = &pattern5_0
-            {
-                if let &Opcode::Load = pattern6_0 {
-                    if let Some(()) = C::bigendian(ctx, pattern6_2) {
-                        // Rule at src/isa/s390x/inst.isle line 2110.
-                        let expr0_0 = constructor_sink_load(ctx, pattern4_0)?;
-                        let expr1_0 =
-                            constructor_emit_zext64_mem(ctx, pattern0_0, pattern3_0, &expr0_0)?;
-                        return Some(expr1_0);
-                    }
-                }
-            }
-        }
-        // Rule at src/isa/s390x/inst.isle line 2112.
-        let expr0_0 = C::put_in_reg(ctx, pattern1_0);
-        let expr1_0 = constructor_emit_zext64_reg(ctx, pattern0_0, pattern3_0, expr0_0)?;
-        return Some(expr1_0);
-    }
-    if let Some(pattern3_0) = C::gpr64_ty(ctx, pattern2_0) {
-        // Rule at src/isa/s390x/inst.isle line 2114.
-        let expr0_0 = C::put_in_reg(ctx, pattern1_0);
-        let expr1_0 = constructor_emit_mov(ctx, pattern3_0, pattern0_0, expr0_0)?;
-        return Some(expr1_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term emit_put_in_reg_sext64.
-pub fn constructor_emit_put_in_reg_sext64<C: Context>(
-    ctx: &mut C,
-    arg0: WritableReg,
-    arg1: Value,
-) -> Option<Unit> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = C::value_type(ctx, pattern1_0);
-    if let Some(pattern3_0) = C::u64_from_signed_value(ctx, pattern1_0) {
-        // Rule at src/isa/s390x/inst.isle line 2119.
-        let expr0_0 = constructor_ty_ext64(ctx, pattern2_0)?;
-        let expr1_0 = constructor_emit_imm(ctx, expr0_0, pattern0_0, pattern3_0)?;
-        return Some(expr1_0);
-    }
-    if let Some(pattern3_0) = C::gpr32_ty(ctx, pattern2_0) {
-        if let Some(pattern4_0) = C::sinkable_inst(ctx, pattern1_0) {
-            let pattern5_0 = C::inst_data(ctx, pattern4_0);
-            if let &InstructionData::Load {
-                opcode: ref pattern6_0,
-                arg: pattern6_1,
-                flags: pattern6_2,
-                offset: pattern6_3,
-            } = &pattern5_0
-            {
-                if let &Opcode::Load = pattern6_0 {
-                    if let Some(()) = C::bigendian(ctx, pattern6_2) {
-                        // Rule at src/isa/s390x/inst.isle line 2121.
-                        let expr0_0 = constructor_sink_load(ctx, pattern4_0)?;
-                        let expr1_0 =
-                            constructor_emit_sext64_mem(ctx, pattern0_0, pattern3_0, &expr0_0)?;
-                        return Some(expr1_0);
-                    }
-                }
-            }
-        }
-        // Rule at src/isa/s390x/inst.isle line 2123.
-        let expr0_0 = C::put_in_reg(ctx, pattern1_0);
-        let expr1_0 = constructor_emit_sext64_reg(ctx, pattern0_0, pattern3_0, expr0_0)?;
-        return Some(expr1_0);
-    }
-    if let Some(pattern3_0) = C::gpr64_ty(ctx, pattern2_0) {
-        // Rule at src/isa/s390x/inst.isle line 2125.
-        let expr0_0 = C::put_in_reg(ctx, pattern1_0);
-        let expr1_0 = constructor_emit_mov(ctx, pattern3_0, pattern0_0, expr0_0)?;
-        return Some(expr1_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term put_in_reg_zext32.
-pub fn constructor_put_in_reg_zext32<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = C::value_type(ctx, pattern0_0);
-    if let Some(pattern2_0) = C::u64_from_value(ctx, pattern0_0) {
-        // Rule at src/isa/s390x/inst.isle line 2130.
-        let expr0_0 = constructor_ty_ext32(ctx, pattern1_0)?;
-        let expr1_0 = constructor_imm(ctx, expr0_0, pattern2_0)?;
-        return Some(expr1_0);
-    }
-    if let Some(pattern2_0) = C::fits_in_16(ctx, pattern1_0) {
-        if let Some(pattern3_0) = C::sinkable_inst(ctx, pattern0_0) {
-            let pattern4_0 = C::inst_data(ctx, pattern3_0);
-            if let &InstructionData::Load {
-                opcode: ref pattern5_0,
-                arg: pattern5_1,
-                flags: pattern5_2,
-                offset: pattern5_3,
-            } = &pattern4_0
-            {
-                if let &Opcode::Load = pattern5_0 {
-                    if let Some(()) = C::bigendian(ctx, pattern5_2) {
-                        // Rule at src/isa/s390x/inst.isle line 2132.
-                        let expr0_0 = constructor_sink_load(ctx, pattern3_0)?;
-                        let expr1_0 = constructor_zext32_mem(ctx, pattern2_0, &expr0_0)?;
-                        return Some(expr1_0);
-                    }
-                }
-            }
-        }
-        // Rule at src/isa/s390x/inst.isle line 2134.
-        let expr0_0 = C::put_in_reg(ctx, pattern0_0);
-        let expr1_0 = constructor_zext32_reg(ctx, pattern2_0, expr0_0)?;
-        return Some(expr1_0);
-    }
-    if let Some(pattern2_0) = C::ty_32_or_64(ctx, pattern1_0) {
-        // Rule at src/isa/s390x/inst.isle line 2136.
-        let expr0_0 = C::put_in_reg(ctx, pattern0_0);
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term put_in_reg_sext32.
-pub fn constructor_put_in_reg_sext32<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = C::value_type(ctx, pattern0_0);
-    if let Some(pattern2_0) = C::u64_from_signed_value(ctx, pattern0_0) {
-        // Rule at src/isa/s390x/inst.isle line 2141.
-        let expr0_0 = constructor_ty_ext32(ctx, pattern1_0)?;
-        let expr1_0 = constructor_imm(ctx, expr0_0, pattern2_0)?;
-        return Some(expr1_0);
-    }
-    if let Some(pattern2_0) = C::fits_in_16(ctx, pattern1_0) {
-        if let Some(pattern3_0) = C::sinkable_inst(ctx, pattern0_0) {
-            let pattern4_0 = C::inst_data(ctx, pattern3_0);
-            if let &InstructionData::Load {
-                opcode: ref pattern5_0,
-                arg: pattern5_1,
-                flags: pattern5_2,
-                offset: pattern5_3,
-            } = &pattern4_0
-            {
-                if let &Opcode::Load = pattern5_0 {
-                    if let Some(()) = C::bigendian(ctx, pattern5_2) {
-                        // Rule at src/isa/s390x/inst.isle line 2143.
-                        let expr0_0 = constructor_sink_load(ctx, pattern3_0)?;
-                        let expr1_0 = constructor_sext32_mem(ctx, pattern2_0, &expr0_0)?;
-                        return Some(expr1_0);
-                    }
-                }
-            }
-        }
-        // Rule at src/isa/s390x/inst.isle line 2145.
-        let expr0_0 = C::put_in_reg(ctx, pattern0_0);
-        let expr1_0 = constructor_sext32_reg(ctx, pattern2_0, expr0_0)?;
-        return Some(expr1_0);
-    }
-    if let Some(pattern2_0) = C::ty_32_or_64(ctx, pattern1_0) {
-        // Rule at src/isa/s390x/inst.isle line 2147.
-        let expr0_0 = C::put_in_reg(ctx, pattern0_0);
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term put_in_reg_zext64.
-pub fn constructor_put_in_reg_zext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = C::value_type(ctx, pattern0_0);
-    if let Some(pattern2_0) = C::u64_from_value(ctx, pattern0_0) {
-        // Rule at src/isa/s390x/inst.isle line 2152.
-        let expr0_0 = constructor_ty_ext64(ctx, pattern1_0)?;
-        let expr1_0 = constructor_imm(ctx, expr0_0, pattern2_0)?;
-        return Some(expr1_0);
-    }
-    if let Some(pattern2_0) = C::gpr32_ty(ctx, pattern1_0) {
-        if let Some(pattern3_0) = C::sinkable_inst(ctx, pattern0_0) {
-            let pattern4_0 = C::inst_data(ctx, pattern3_0);
-            if let &InstructionData::Load {
-                opcode: ref pattern5_0,
-                arg: pattern5_1,
-                flags: pattern5_2,
-                offset: pattern5_3,
-            } = &pattern4_0
-            {
-                if let &Opcode::Load = pattern5_0 {
-                    if let Some(()) = C::bigendian(ctx, pattern5_2) {
-                        // Rule at src/isa/s390x/inst.isle line 2154.
-                        let expr0_0 = constructor_sink_load(ctx, pattern3_0)?;
-                        let expr1_0 = constructor_zext64_mem(ctx, pattern2_0, &expr0_0)?;
-                        return Some(expr1_0);
-                    }
-                }
-            }
-        }
-        // Rule at src/isa/s390x/inst.isle line 2156.
-        let expr0_0 = C::put_in_reg(ctx, pattern0_0);
-        let expr1_0 = constructor_zext64_reg(ctx, pattern2_0, expr0_0)?;
-        return Some(expr1_0);
-    }
-    if let Some(pattern2_0) = C::gpr64_ty(ctx, pattern1_0) {
-        // Rule at src/isa/s390x/inst.isle line 2158.
-        let expr0_0 = C::put_in_reg(ctx, pattern0_0);
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term put_in_reg_sext64.
-pub fn constructor_put_in_reg_sext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = C::value_type(ctx, pattern0_0);
-    if let Some(pattern2_0) = C::u64_from_signed_value(ctx, pattern0_0) {
-        // Rule at src/isa/s390x/inst.isle line 2163.
-        let expr0_0 = constructor_ty_ext64(ctx, pattern1_0)?;
-        let expr1_0 = constructor_imm(ctx, expr0_0, pattern2_0)?;
-        return Some(expr1_0);
-    }
-    if let Some(pattern2_0) = C::gpr32_ty(ctx, pattern1_0) {
-        if let Some(pattern3_0) = C::sinkable_inst(ctx, pattern0_0) {
-            let pattern4_0 = C::inst_data(ctx, pattern3_0);
-            if let &InstructionData::Load {
-                opcode: ref pattern5_0,
-                arg: pattern5_1,
-                flags: pattern5_2,
-                offset: pattern5_3,
-            } = &pattern4_0
-            {
-                if let &Opcode::Load = pattern5_0 {
-                    if let Some(()) = C::bigendian(ctx, pattern5_2) {
-                        // Rule at src/isa/s390x/inst.isle line 2165.
-                        let expr0_0 = constructor_sink_load(ctx, pattern3_0)?;
-                        let expr1_0 = constructor_sext64_mem(ctx, pattern2_0, &expr0_0)?;
-                        return Some(expr1_0);
-                    }
-                }
-            }
-        }
-        // Rule at src/isa/s390x/inst.isle line 2167.
-        let expr0_0 = C::put_in_reg(ctx, pattern0_0);
-        let expr1_0 = constructor_sext64_reg(ctx, pattern2_0, expr0_0)?;
-        return Some(expr1_0);
-    }
-    if let Some(pattern2_0) = C::gpr64_ty(ctx, pattern1_0) {
-        // Rule at src/isa/s390x/inst.isle line 2169.
-        let expr0_0 = C::put_in_reg(ctx, pattern0_0);
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term put_in_regpair_lo_zext32.
-pub fn constructor_put_in_regpair_lo_zext32<C: Context>(
-    ctx: &mut C,
-    arg0: Value,
-    arg1: &RegPair,
-) -> Option<RegPair> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 2175.
-    let expr0_0 = constructor_copy_writable_regpair(ctx, pattern1_0)?;
-    let expr1_0 = constructor_writable_regpair_lo(ctx, &expr0_0)?;
-    let expr2_0 = constructor_emit_put_in_reg_zext32(ctx, expr1_0, pattern0_0)?;
-    let expr3_0 = constructor_writable_regpair_to_regpair(ctx, &expr0_0)?;
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term put_in_regpair_lo_sext32.
-pub fn constructor_put_in_regpair_lo_sext32<C: Context>(
-    ctx: &mut C,
-    arg0: Value,
-    arg1: &RegPair,
-) -> Option<RegPair> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 2183.
-    let expr0_0 = constructor_copy_writable_regpair(ctx, pattern1_0)?;
-    let expr1_0 = constructor_writable_regpair_lo(ctx, &expr0_0)?;
-    let expr2_0 = constructor_emit_put_in_reg_sext32(ctx, expr1_0, pattern0_0)?;
-    let expr3_0 = constructor_writable_regpair_to_regpair(ctx, &expr0_0)?;
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term put_in_regpair_lo_zext64.
-pub fn constructor_put_in_regpair_lo_zext64<C: Context>(
-    ctx: &mut C,
-    arg0: Value,
-    arg1: &RegPair,
-) -> Option<RegPair> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 2191.
-    let expr0_0 = constructor_copy_writable_regpair(ctx, pattern1_0)?;
-    let expr1_0 = constructor_writable_regpair_lo(ctx, &expr0_0)?;
-    let expr2_0 = constructor_emit_put_in_reg_zext64(ctx, expr1_0, pattern0_0)?;
-    let expr3_0 = constructor_writable_regpair_to_regpair(ctx, &expr0_0)?;
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term put_in_regpair_lo_sext64.
-pub fn constructor_put_in_regpair_lo_sext64<C: Context>(
-    ctx: &mut C,
-    arg0: Value,
-    arg1: &RegPair,
-) -> Option<RegPair> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 2199.
-    let expr0_0 = constructor_copy_writable_regpair(ctx, pattern1_0)?;
-    let expr1_0 = constructor_writable_regpair_lo(ctx, &expr0_0)?;
-    let expr2_0 = constructor_emit_put_in_reg_sext64(ctx, expr1_0, pattern0_0)?;
-    let expr3_0 = constructor_writable_regpair_to_regpair(ctx, &expr0_0)?;
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term emit_cmov_imm.
-pub fn constructor_emit_cmov_imm<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: WritableReg,
-    arg2: &Cond,
-    arg3: i16,
-) -> Option<ConsumesFlags> {
-    let pattern0_0 = arg0;
-    if let Some(pattern1_0) = C::gpr32_ty(ctx, pattern0_0) {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/s390x/inst.isle line 2209.
-        let expr0_0 = MInst::CMov32SImm16 {
-            rd: pattern2_0,
-            cond: pattern3_0.clone(),
-            imm: pattern4_0,
-        };
-        let expr1_0 = C::writable_reg_to_reg(ctx, pattern2_0);
-        let expr2_0 = ConsumesFlags::ConsumesFlagsReturnsReg {
-            inst: expr0_0,
-            result: expr1_0,
-        };
-        return Some(expr2_0);
-    }
-    if let Some(pattern1_0) = C::gpr64_ty(ctx, pattern0_0) {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/s390x/inst.isle line 2212.
-        let expr0_0 = MInst::CMov64SImm16 {
-            rd: pattern2_0,
-            cond: pattern3_0.clone(),
-            imm: pattern4_0,
-        };
-        let expr1_0 = C::writable_reg_to_reg(ctx, pattern2_0);
-        let expr2_0 = ConsumesFlags::ConsumesFlagsReturnsReg {
-            inst: expr0_0,
-            result: expr1_0,
-        };
-        return Some(expr2_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term cmov_imm.
-pub fn constructor_cmov_imm<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &Cond,
-    arg2: i16,
-    arg3: Reg,
-) -> Option<ConsumesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/s390x/inst.isle line 2218.
-    let expr0_0 = constructor_copy_writable_reg(ctx, pattern0_0, pattern3_0)?;
-    let expr1_0 = constructor_emit_cmov_imm(ctx, pattern0_0, expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term cmov_imm_regpair_lo.
-pub fn constructor_cmov_imm_regpair_lo<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &ProducesFlags,
-    arg2: &Cond,
-    arg3: i16,
-    arg4: &RegPair,
-) -> Option<RegPair> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    let pattern4_0 = arg4;
-    // Rule at src/isa/s390x/inst.isle line 2225.
-    let expr0_0 = constructor_copy_writable_regpair(ctx, pattern4_0)?;
-    let expr1_0 = constructor_writable_regpair_lo(ctx, &expr0_0)?;
-    let expr2_0 = constructor_emit_cmov_imm(ctx, pattern0_0, expr1_0, pattern2_0, pattern3_0)?;
-    let expr3_0 = constructor_with_flags_reg(ctx, pattern1_0, &expr2_0)?;
-    let expr4_0 = constructor_writable_regpair_to_regpair(ctx, &expr0_0)?;
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term cmov_imm_regpair_hi.
-pub fn constructor_cmov_imm_regpair_hi<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &ProducesFlags,
-    arg2: &Cond,
-    arg3: i16,
-    arg4: &RegPair,
-) -> Option<RegPair> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    let pattern4_0 = arg4;
-    // Rule at src/isa/s390x/inst.isle line 2234.
-    let expr0_0 = constructor_copy_writable_regpair(ctx, pattern4_0)?;
-    let expr1_0 = constructor_writable_regpair_hi(ctx, &expr0_0)?;
-    let expr2_0 = constructor_emit_cmov_imm(ctx, pattern0_0, expr1_0, pattern2_0, pattern3_0)?;
-    let expr3_0 = constructor_with_flags_reg(ctx, pattern1_0, &expr2_0)?;
-    let expr4_0 = constructor_writable_regpair_to_regpair(ctx, &expr0_0)?;
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term emit_cmov_reg.
-pub fn constructor_emit_cmov_reg<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: WritableReg,
-    arg2: &Cond,
-    arg3: Reg,
-) -> Option<ConsumesFlags> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == F32 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/s390x/inst.isle line 2248.
-        let expr0_0 = MInst::FpuCMov32 {
-            rd: pattern2_0,
-            cond: pattern3_0.clone(),
-            rm: pattern4_0,
-        };
-        let expr1_0 = C::writable_reg_to_reg(ctx, pattern2_0);
-        let expr2_0 = ConsumesFlags::ConsumesFlagsReturnsReg {
-            inst: expr0_0,
-            result: expr1_0,
-        };
-        return Some(expr2_0);
-    }
-    if pattern0_0 == F64 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/s390x/inst.isle line 2251.
-        let expr0_0 = MInst::FpuCMov64 {
-            rd: pattern2_0,
-            cond: pattern3_0.clone(),
-            rm: pattern4_0,
-        };
-        let expr1_0 = C::writable_reg_to_reg(ctx, pattern2_0);
-        let expr2_0 = ConsumesFlags::ConsumesFlagsReturnsReg {
-            inst: expr0_0,
-            result: expr1_0,
-        };
-        return Some(expr2_0);
-    }
-    if let Some(pattern1_0) = C::gpr32_ty(ctx, pattern0_0) {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/s390x/inst.isle line 2242.
-        let expr0_0 = MInst::CMov32 {
-            rd: pattern2_0,
-            cond: pattern3_0.clone(),
-            rm: pattern4_0,
-        };
-        let expr1_0 = C::writable_reg_to_reg(ctx, pattern2_0);
-        let expr2_0 = ConsumesFlags::ConsumesFlagsReturnsReg {
-            inst: expr0_0,
-            result: expr1_0,
-        };
-        return Some(expr2_0);
-    }
-    if let Some(pattern1_0) = C::gpr64_ty(ctx, pattern0_0) {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/s390x/inst.isle line 2245.
-        let expr0_0 = MInst::CMov64 {
-            rd: pattern2_0,
-            cond: pattern3_0.clone(),
-            rm: pattern4_0,
-        };
-        let expr1_0 = C::writable_reg_to_reg(ctx, pattern2_0);
-        let expr2_0 = ConsumesFlags::ConsumesFlagsReturnsReg {
-            inst: expr0_0,
-            result: expr1_0,
-        };
-        return Some(expr2_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term cmov_reg.
-pub fn constructor_cmov_reg<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &Cond,
-    arg2: Reg,
-    arg3: Reg,
-) -> Option<ConsumesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/s390x/inst.isle line 2257.
-    let expr0_0 = constructor_copy_writable_reg(ctx, pattern0_0, pattern3_0)?;
-    let expr1_0 = constructor_emit_cmov_reg(ctx, pattern0_0, expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term trap_if.
-pub fn constructor_trap_if<C: Context>(
-    ctx: &mut C,
-    arg0: &ProducesFlags,
-    arg1: &Cond,
-    arg2: &TrapCode,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    match pattern0_0 {
-        &ProducesFlags::ProducesFlagsSideEffect {
-            inst: ref pattern1_0,
-        } => {
-            let pattern2_0 = arg1;
-            let pattern3_0 = arg2;
-            // Rule at src/isa/s390x/inst.isle line 2269.
-            let expr0_0 = C::emit(ctx, pattern1_0);
-            let expr1_0 = MInst::TrapIf {
-                cond: pattern2_0.clone(),
-                trap_code: pattern3_0.clone(),
-            };
-            let expr2_0 = C::emit(ctx, &expr1_0);
-            let expr3_0 = C::invalid_reg(ctx);
-            return Some(expr3_0);
-        }
-        &ProducesFlags::ProducesFlagsReturnsReg {
-            inst: ref pattern1_0,
-            result: pattern1_1,
-        } => {
-            let pattern2_0 = arg1;
-            let pattern3_0 = arg2;
-            // Rule at src/isa/s390x/inst.isle line 2265.
-            let expr0_0 = C::emit(ctx, pattern1_0);
-            let expr1_0 = MInst::TrapIf {
-                cond: pattern2_0.clone(),
-                trap_code: pattern3_0.clone(),
-            };
-            let expr2_0 = C::emit(ctx, &expr1_0);
-            return Some(pattern1_1);
-        }
-        _ => {}
-    }
-    return None;
-}
-
-// Generated as internal constructor for term icmps_reg_and_trap.
-pub fn constructor_icmps_reg_and_trap<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-    arg3: &Cond,
-    arg4: &TrapCode,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    let pattern4_0 = arg4;
-    // Rule at src/isa/s390x/inst.isle line 2275.
-    let expr0_0 = constructor_cmpop_cmps(ctx, pattern0_0)?;
-    let expr1_0 = MInst::CmpTrapRR {
-        op: expr0_0,
-        rn: pattern1_0,
-        rm: pattern2_0,
-        cond: pattern3_0.clone(),
-        trap_code: pattern4_0.clone(),
-    };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = C::invalid_reg(ctx);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term icmps_simm16_and_trap.
-pub fn constructor_icmps_simm16_and_trap<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: i16,
-    arg3: &Cond,
-    arg4: &TrapCode,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    let pattern4_0 = arg4;
-    // Rule at src/isa/s390x/inst.isle line 2281.
-    let expr0_0 = constructor_cmpop_cmps(ctx, pattern0_0)?;
-    let expr1_0 = MInst::CmpTrapRSImm16 {
-        op: expr0_0,
-        rn: pattern1_0,
-        imm: pattern2_0,
-        cond: pattern3_0.clone(),
-        trap_code: pattern4_0.clone(),
-    };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = C::invalid_reg(ctx);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term icmpu_reg_and_trap.
-pub fn constructor_icmpu_reg_and_trap<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-    arg3: &Cond,
-    arg4: &TrapCode,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    let pattern4_0 = arg4;
-    // Rule at src/isa/s390x/inst.isle line 2287.
-    let expr0_0 = constructor_cmpop_cmpu(ctx, pattern0_0)?;
-    let expr1_0 = MInst::CmpTrapRR {
-        op: expr0_0,
-        rn: pattern1_0,
-        rm: pattern2_0,
-        cond: pattern3_0.clone(),
-        trap_code: pattern4_0.clone(),
-    };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = C::invalid_reg(ctx);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term icmpu_uimm16_and_trap.
-pub fn constructor_icmpu_uimm16_and_trap<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: u16,
-    arg3: &Cond,
-    arg4: &TrapCode,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    let pattern4_0 = arg4;
-    // Rule at src/isa/s390x/inst.isle line 2293.
-    let expr0_0 = constructor_cmpop_cmpu(ctx, pattern0_0)?;
-    let expr1_0 = MInst::CmpTrapRUImm16 {
-        op: expr0_0,
-        rn: pattern1_0,
-        imm: pattern2_0,
-        cond: pattern3_0.clone(),
-        trap_code: pattern4_0.clone(),
-    };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = C::invalid_reg(ctx);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term trap_impl.
-pub fn constructor_trap_impl<C: Context>(
-    ctx: &mut C,
-    arg0: &TrapCode,
-) -> Option<SideEffectNoResult> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/s390x/inst.isle line 2299.
-    let expr0_0 = MInst::Trap {
-        trap_code: pattern0_0.clone(),
-    };
-    let expr1_0 = SideEffectNoResult::Inst { inst: expr0_0 };
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term trap_if_impl.
-pub fn constructor_trap_if_impl<C: Context>(
-    ctx: &mut C,
-    arg0: &Cond,
-    arg1: &TrapCode,
-) -> Option<SideEffectNoResult> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 2303.
-    let expr0_0 = MInst::TrapIf {
-        cond: pattern0_0.clone(),
-        trap_code: pattern1_0.clone(),
-    };
-    let expr1_0 = SideEffectNoResult::Inst { inst: expr0_0 };
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term debugtrap_impl.
-pub fn constructor_debugtrap_impl<C: Context>(ctx: &mut C) -> Option<SideEffectNoResult> {
-    // Rule at src/isa/s390x/inst.isle line 2307.
-    let expr0_0 = MInst::Debugtrap;
-    let expr1_0 = SideEffectNoResult::Inst { inst: expr0_0 };
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term bool.
-pub fn constructor_bool<C: Context>(
-    ctx: &mut C,
-    arg0: &ProducesFlags,
-    arg1: &Cond,
-) -> Option<ProducesBool> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 2318.
-    let expr0_0 = ProducesBool::ProducesBool {
-        producer: pattern0_0.clone(),
-        cond: pattern1_0.clone(),
-    };
-    return Some(expr0_0);
-}
-
-// Generated as internal constructor for term invert_bool.
-pub fn constructor_invert_bool<C: Context>(
-    ctx: &mut C,
-    arg0: &ProducesBool,
-) -> Option<ProducesBool> {
-    let pattern0_0 = arg0;
-    if let &ProducesBool::ProducesBool {
-        producer: ref pattern1_0,
-        cond: ref pattern1_1,
-    } = pattern0_0
-    {
-        // Rule at src/isa/s390x/inst.isle line 2322.
-        let expr0_0 = C::invert_cond(ctx, pattern1_1);
-        let expr1_0 = constructor_bool(ctx, pattern1_0, &expr0_0)?;
-        return Some(expr1_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term emit_producer.
-pub fn constructor_emit_producer<C: Context>(ctx: &mut C, arg0: &ProducesFlags) -> Option<Unit> {
-    let pattern0_0 = arg0;
-    if let &ProducesFlags::ProducesFlagsSideEffect {
-        inst: ref pattern1_0,
-    } = pattern0_0
-    {
-        // Rule at src/isa/s390x/inst.isle line 2331.
-        let expr0_0 = C::emit(ctx, pattern1_0);
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term emit_consumer.
-pub fn constructor_emit_consumer<C: Context>(ctx: &mut C, arg0: &ConsumesFlags) -> Option<Unit> {
-    let pattern0_0 = arg0;
-    if let &ConsumesFlags::ConsumesFlagsReturnsReg {
-        inst: ref pattern1_0,
-        result: pattern1_1,
-    } = pattern0_0
-    {
-        // Rule at src/isa/s390x/inst.isle line 2333.
-        let expr0_0 = C::emit(ctx, pattern1_0);
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term select_bool_reg.
-pub fn constructor_select_bool_reg<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &ProducesBool,
-    arg2: Reg,
-    arg3: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    if let &ProducesBool::ProducesBool {
-        producer: ref pattern2_0,
-        cond: ref pattern2_1,
-    } = pattern1_0
-    {
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/s390x/inst.isle line 2337.
-        let expr0_0 = C::temp_writable_reg(ctx, pattern0_0);
-        let expr1_0 = constructor_emit_producer(ctx, pattern2_0)?;
-        let expr2_0 = constructor_emit_mov(ctx, pattern0_0, expr0_0, pattern4_0)?;
-        let expr3_0 = constructor_emit_cmov_reg(ctx, pattern0_0, expr0_0, pattern2_1, pattern3_0)?;
-        let expr4_0 = constructor_emit_consumer(ctx, &expr3_0)?;
-        let expr5_0 = C::writable_reg_to_reg(ctx, expr0_0);
-        return Some(expr5_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term select_bool_imm.
-pub fn constructor_select_bool_imm<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &ProducesBool,
-    arg2: i16,
-    arg3: u64,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    if let &ProducesBool::ProducesBool {
-        producer: ref pattern2_0,
-        cond: ref pattern2_1,
-    } = pattern1_0
-    {
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/s390x/inst.isle line 2346.
-        let expr0_0 = C::temp_writable_reg(ctx, pattern0_0);
-        let expr1_0 = constructor_emit_producer(ctx, pattern2_0)?;
-        let expr2_0 = constructor_emit_imm(ctx, pattern0_0, expr0_0, pattern4_0)?;
-        let expr3_0 = constructor_emit_cmov_imm(ctx, pattern0_0, expr0_0, pattern2_1, pattern3_0)?;
-        let expr4_0 = constructor_emit_consumer(ctx, &expr3_0)?;
-        let expr5_0 = C::writable_reg_to_reg(ctx, expr0_0);
-        return Some(expr5_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term lower_bool.
-pub fn constructor_lower_bool<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &ProducesBool,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == B1 {
-        let pattern2_0 = arg1;
-        // Rule at src/isa/s390x/inst.isle line 2356.
-        let expr0_0: Type = B1;
-        let expr1_0: i16 = 1;
-        let expr2_0: u64 = 0;
-        let expr3_0 = constructor_select_bool_imm(ctx, expr0_0, pattern2_0, expr1_0, expr2_0)?;
-        return Some(expr3_0);
-    }
-    if pattern0_0 == B8 {
-        let pattern2_0 = arg1;
-        // Rule at src/isa/s390x/inst.isle line 2357.
-        let expr0_0: Type = B8;
-        let expr1_0: i16 = -1;
-        let expr2_0: u64 = 0;
-        let expr3_0 = constructor_select_bool_imm(ctx, expr0_0, pattern2_0, expr1_0, expr2_0)?;
-        return Some(expr3_0);
-    }
-    if pattern0_0 == B16 {
-        let pattern2_0 = arg1;
-        // Rule at src/isa/s390x/inst.isle line 2358.
-        let expr0_0: Type = B16;
-        let expr1_0: i16 = -1;
-        let expr2_0: u64 = 0;
-        let expr3_0 = constructor_select_bool_imm(ctx, expr0_0, pattern2_0, expr1_0, expr2_0)?;
-        return Some(expr3_0);
-    }
-    if pattern0_0 == B32 {
-        let pattern2_0 = arg1;
-        // Rule at src/isa/s390x/inst.isle line 2359.
-        let expr0_0: Type = B32;
-        let expr1_0: i16 = -1;
-        let expr2_0: u64 = 0;
-        let expr3_0 = constructor_select_bool_imm(ctx, expr0_0, pattern2_0, expr1_0, expr2_0)?;
-        return Some(expr3_0);
-    }
-    if pattern0_0 == B64 {
-        let pattern2_0 = arg1;
-        // Rule at src/isa/s390x/inst.isle line 2360.
-        let expr0_0: Type = B64;
-        let expr1_0: i16 = -1;
-        let expr2_0: u64 = 0;
-        let expr3_0 = constructor_select_bool_imm(ctx, expr0_0, pattern2_0, expr1_0, expr2_0)?;
-        return Some(expr3_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term cond_br_bool.
-pub fn constructor_cond_br_bool<C: Context>(
-    ctx: &mut C,
-    arg0: &ProducesBool,
-    arg1: MachLabel,
-    arg2: MachLabel,
-) -> Option<SideEffectNoResult> {
-    let pattern0_0 = arg0;
-    if let &ProducesBool::ProducesBool {
-        producer: ref pattern1_0,
-        cond: ref pattern1_1,
-    } = pattern0_0
-    {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/inst.isle line 2364.
-        let expr0_0 = constructor_emit_producer(ctx, pattern1_0)?;
-        let expr1_0 = constructor_cond_br(ctx, pattern2_0, pattern3_0, pattern1_1)?;
-        return Some(expr1_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term oneway_cond_br_bool.
-pub fn constructor_oneway_cond_br_bool<C: Context>(
-    ctx: &mut C,
-    arg0: &ProducesBool,
-    arg1: MachLabel,
-) -> Option<SideEffectNoResult> {
-    let pattern0_0 = arg0;
-    if let &ProducesBool::ProducesBool {
-        producer: ref pattern1_0,
-        cond: ref pattern1_1,
-    } = pattern0_0
-    {
-        let pattern2_0 = arg1;
-        // Rule at src/isa/s390x/inst.isle line 2370.
-        let expr0_0 = constructor_emit_producer(ctx, pattern1_0)?;
-        let expr1_0 = constructor_oneway_cond_br(ctx, pattern2_0, pattern1_1)?;
-        return Some(expr1_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term trap_if_bool.
-pub fn constructor_trap_if_bool<C: Context>(
-    ctx: &mut C,
-    arg0: &ProducesBool,
-    arg1: &TrapCode,
-) -> Option<SideEffectNoResult> {
-    let pattern0_0 = arg0;
-    if let &ProducesBool::ProducesBool {
-        producer: ref pattern1_0,
-        cond: ref pattern1_1,
-    } = pattern0_0
-    {
-        let pattern2_0 = arg1;
-        // Rule at src/isa/s390x/inst.isle line 2376.
-        let expr0_0 = constructor_emit_producer(ctx, pattern1_0)?;
-        let expr1_0 = constructor_trap_if_impl(ctx, pattern1_1, pattern2_0)?;
-        return Some(expr1_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term casloop_val_reg.
-pub fn constructor_casloop_val_reg<C: Context>(ctx: &mut C) -> Option<WritableReg> {
-    // Rule at src/isa/s390x/inst.isle line 2390.
-    let expr0_0: u8 = 0;
-    let expr1_0 = C::writable_gpr(ctx, expr0_0);
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term casloop_tmp_reg.
-pub fn constructor_casloop_tmp_reg<C: Context>(ctx: &mut C) -> Option<WritableReg> {
-    // Rule at src/isa/s390x/inst.isle line 2394.
-    let expr0_0: u8 = 1;
-    let expr1_0 = C::writable_gpr(ctx, expr0_0);
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term casloop_emit.
-pub fn constructor_casloop_emit<C: Context>(
-    ctx: &mut C,
-    arg0: &VecMInstBuilder,
-    arg1: Type,
-    arg2: MemFlags,
-    arg3: Reg,
-    arg4: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    let pattern4_0 = arg4;
-    // Rule at src/isa/s390x/inst.isle line 2403.
-    let expr0_0: i64 = 0;
-    let expr1_0 = C::memarg_reg_plus_off(ctx, pattern3_0, expr0_0, pattern2_0);
-    let expr2_0 = constructor_ty_ext32(ctx, pattern1_0)?;
-    let expr3_0 = constructor_casloop_val_reg(ctx)?;
-    let expr4_0 =
-        constructor_push_atomic_cas(ctx, pattern0_0, expr2_0, expr3_0, pattern4_0, &expr1_0)?;
-    let expr5_0 = constructor_ty_ext32(ctx, pattern1_0)?;
-    let expr6_0 = constructor_casloop_val_reg(ctx)?;
-    let expr7_0 = constructor_emit_load(ctx, expr5_0, expr6_0, &expr1_0)?;
-    let expr8_0 = IntCC::NotEqual;
-    let expr9_0 = C::intcc_as_cond(ctx, &expr8_0);
-    let expr10_0 = constructor_emit_loop(ctx, pattern0_0, &expr9_0)?;
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term casloop_result.
-pub fn constructor_casloop_result<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: MemFlags,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    if let Some(pattern1_0) = C::ty_32_or_64(ctx, pattern0_0) {
-        let pattern2_0 = arg1;
-        if let Some(()) = C::littleendian(ctx, pattern2_0) {
-            let pattern4_0 = arg2;
-            // Rule at src/isa/s390x/inst.isle line 2421.
-            let expr0_0 = constructor_bswap_reg(ctx, pattern1_0, pattern4_0)?;
-            return Some(expr0_0);
-        }
-        if let Some(()) = C::bigendian(ctx, pattern2_0) {
-            let pattern4_0 = arg2;
-            // Rule at src/isa/s390x/inst.isle line 2419.
-            let expr0_0 = constructor_copy_reg(ctx, pattern1_0, pattern4_0)?;
-            return Some(expr0_0);
-        }
-    }
-    return None;
-}
-
-// Generated as internal constructor for term casloop.
-pub fn constructor_casloop<C: Context>(
-    ctx: &mut C,
-    arg0: &VecMInstBuilder,
-    arg1: Type,
-    arg2: MemFlags,
-    arg3: Reg,
-    arg4: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    let pattern4_0 = arg4;
-    // Rule at src/isa/s390x/inst.isle line 2426.
-    let expr0_0 = constructor_casloop_emit(
-        ctx, pattern0_0, pattern1_0, pattern2_0, pattern3_0, pattern4_0,
-    )?;
-    let expr1_0 = constructor_casloop_result(ctx, pattern1_0, pattern2_0, expr0_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term casloop_bitshift.
-pub fn constructor_casloop_bitshift<C: Context>(ctx: &mut C, arg0: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/s390x/inst.isle line 2441.
-    let expr0_0: Type = I32;
-    let expr1_0: u8 = 3;
-    let expr2_0 = constructor_lshl_imm(ctx, expr0_0, pattern0_0, expr1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term casloop_aligned_addr.
-pub fn constructor_casloop_aligned_addr<C: Context>(ctx: &mut C, arg0: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/s390x/inst.isle line 2446.
-    let expr0_0: Type = I64;
-    let expr1_0: u16 = 65532;
-    let expr2_0: u8 = 0;
-    let expr3_0 = C::uimm16shifted(ctx, expr1_0, expr2_0);
-    let expr4_0 = constructor_and_uimm16shifted(ctx, expr0_0, pattern0_0, expr3_0)?;
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term casloop_rotate_in.
-pub fn constructor_casloop_rotate_in<C: Context>(
-    ctx: &mut C,
-    arg0: &VecMInstBuilder,
-    arg1: Type,
-    arg2: MemFlags,
-    arg3: Reg,
-    arg4: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    if pattern1_0 == I8 {
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        let pattern5_0 = arg4;
-        // Rule at src/isa/s390x/inst.isle line 2456.
-        let expr0_0: Type = I32;
-        let expr1_0 = constructor_casloop_tmp_reg(ctx)?;
-        let expr2_0: u8 = 0;
-        let expr3_0 = constructor_push_rot_imm_reg(
-            ctx, pattern0_0, expr0_0, expr1_0, pattern5_0, expr2_0, pattern4_0,
-        )?;
-        return Some(expr3_0);
-    }
-    if pattern1_0 == I16 {
-        let pattern3_0 = arg2;
-        if let Some(()) = C::littleendian(ctx, pattern3_0) {
-            let pattern5_0 = arg3;
-            let pattern6_0 = arg4;
-            // Rule at src/isa/s390x/inst.isle line 2460.
-            let expr0_0: Type = I32;
-            let expr1_0 = constructor_casloop_tmp_reg(ctx)?;
-            let expr2_0: u8 = 16;
-            let expr3_0 = constructor_push_rot_imm_reg(
-                ctx, pattern0_0, expr0_0, expr1_0, pattern6_0, expr2_0, pattern5_0,
-            )?;
-            return Some(expr3_0);
-        }
-        if let Some(()) = C::bigendian(ctx, pattern3_0) {
-            let pattern5_0 = arg3;
-            let pattern6_0 = arg4;
-            // Rule at src/isa/s390x/inst.isle line 2458.
-            let expr0_0: Type = I32;
-            let expr1_0 = constructor_casloop_tmp_reg(ctx)?;
-            let expr2_0: u8 = 0;
-            let expr3_0 = constructor_push_rot_imm_reg(
-                ctx, pattern0_0, expr0_0, expr1_0, pattern6_0, expr2_0, pattern5_0,
-            )?;
-            return Some(expr3_0);
-        }
-    }
-    return None;
-}
-
-// Generated as internal constructor for term casloop_rotate_out.
-pub fn constructor_casloop_rotate_out<C: Context>(
-    ctx: &mut C,
-    arg0: &VecMInstBuilder,
-    arg1: Type,
-    arg2: MemFlags,
-    arg3: Reg,
-    arg4: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    if pattern1_0 == I8 {
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        let pattern5_0 = arg4;
-        // Rule at src/isa/s390x/inst.isle line 2469.
-        let expr0_0: Type = I32;
-        let expr1_0 = constructor_casloop_tmp_reg(ctx)?;
-        let expr2_0: u8 = 0;
-        let expr3_0: Type = I32;
-        let expr4_0 = constructor_neg_reg(ctx, expr3_0, pattern4_0)?;
-        let expr5_0 = constructor_push_rot_imm_reg(
-            ctx, pattern0_0, expr0_0, expr1_0, pattern5_0, expr2_0, expr4_0,
-        )?;
-        return Some(expr5_0);
-    }
-    if pattern1_0 == I16 {
-        let pattern3_0 = arg2;
-        if let Some(()) = C::littleendian(ctx, pattern3_0) {
-            let pattern5_0 = arg3;
-            let pattern6_0 = arg4;
-            // Rule at src/isa/s390x/inst.isle line 2473.
-            let expr0_0: Type = I32;
-            let expr1_0 = constructor_casloop_tmp_reg(ctx)?;
-            let expr2_0: u8 = 16;
-            let expr3_0 = constructor_push_rot_imm_reg(
-                ctx, pattern0_0, expr0_0, expr1_0, pattern6_0, expr2_0, pattern5_0,
-            )?;
-            return Some(expr3_0);
-        }
-        if let Some(()) = C::bigendian(ctx, pattern3_0) {
-            let pattern5_0 = arg3;
-            let pattern6_0 = arg4;
-            // Rule at src/isa/s390x/inst.isle line 2471.
-            let expr0_0: Type = I32;
-            let expr1_0 = constructor_casloop_tmp_reg(ctx)?;
-            let expr2_0: u8 = 0;
-            let expr3_0 = constructor_push_rot_imm_reg(
-                ctx, pattern0_0, expr0_0, expr1_0, pattern6_0, expr2_0, pattern5_0,
-            )?;
-            return Some(expr3_0);
-        }
-    }
-    return None;
-}
-
-// Generated as internal constructor for term casloop_rotate_result.
-pub fn constructor_casloop_rotate_result<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: MemFlags,
-    arg2: Reg,
-    arg3: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I8 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/s390x/inst.isle line 2484.
-        let expr0_0: Type = I32;
-        let expr1_0: u8 = 8;
-        let expr2_0 = constructor_rot_imm_reg(ctx, expr0_0, pattern4_0, expr1_0, pattern3_0)?;
-        return Some(expr2_0);
-    }
-    if pattern0_0 == I16 {
-        let pattern2_0 = arg1;
-        if let Some(()) = C::littleendian(ctx, pattern2_0) {
-            let pattern4_0 = arg2;
-            let pattern5_0 = arg3;
-            // Rule at src/isa/s390x/inst.isle line 2488.
-            let expr0_0: Type = I32;
-            let expr1_0: Type = I32;
-            let expr2_0 = constructor_rot_reg(ctx, expr1_0, pattern5_0, pattern4_0)?;
-            let expr3_0 = constructor_bswap_reg(ctx, expr0_0, expr2_0)?;
-            return Some(expr3_0);
-        }
-        if let Some(()) = C::bigendian(ctx, pattern2_0) {
-            let pattern4_0 = arg2;
-            let pattern5_0 = arg3;
-            // Rule at src/isa/s390x/inst.isle line 2486.
-            let expr0_0: Type = I32;
-            let expr1_0: u8 = 16;
-            let expr2_0 = constructor_rot_imm_reg(ctx, expr0_0, pattern5_0, expr1_0, pattern4_0)?;
-            return Some(expr2_0);
-        }
-    }
-    return None;
-}
-
-// Generated as internal constructor for term casloop_subword.
-pub fn constructor_casloop_subword<C: Context>(
-    ctx: &mut C,
-    arg0: &VecMInstBuilder,
-    arg1: Type,
-    arg2: MemFlags,
-    arg3: Reg,
-    arg4: Reg,
-    arg5: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    let pattern4_0 = arg4;
-    let pattern5_0 = arg5;
-    // Rule at src/isa/s390x/inst.isle line 2493.
-    let expr0_0 = constructor_casloop_emit(
-        ctx, pattern0_0, pattern1_0, pattern2_0, pattern3_0, pattern5_0,
-    )?;
-    let expr1_0 =
-        constructor_casloop_rotate_result(ctx, pattern1_0, pattern2_0, pattern4_0, expr0_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term clz_reg.
-pub fn constructor_clz_reg<C: Context>(ctx: &mut C, arg0: i16, arg1: Reg) -> Option<RegPair> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == 64 {
-        let pattern2_0 = arg1;
-        // Rule at src/isa/s390x/inst.isle line 2504.
-        let expr0_0 = constructor_temp_writable_regpair(ctx)?;
-        let expr1_0 = MInst::Flogr { rn: pattern2_0 };
-        let expr2_0 = C::emit(ctx, &expr1_0);
-        let expr3_0 = constructor_writable_regpair_to_regpair(ctx, &expr0_0)?;
-        return Some(expr3_0);
-    }
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 2513.
-    let expr0_0 = constructor_temp_writable_regpair(ctx)?;
-    let expr1_0 = MInst::Flogr { rn: pattern1_0 };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = constructor_writable_regpair_hi(ctx, &expr0_0)?;
-    let expr4_0 = IntCC::Equal;
-    let expr5_0 = C::intcc_as_cond(ctx, &expr4_0);
-    let expr6_0 = MInst::CMov64SImm16 {
-        rd: expr3_0,
-        cond: expr5_0,
-        imm: pattern0_0,
-    };
-    let expr7_0 = C::emit(ctx, &expr6_0);
-    let expr8_0 = constructor_writable_regpair_to_regpair(ctx, &expr0_0)?;
-    return Some(expr8_0);
-}
-
-// Generated as internal constructor for term aluop_add.
-pub fn constructor_aluop_add<C: Context>(ctx: &mut C, arg0: Type) -> Option<ALUOp> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I8 {
-        // Rule at src/isa/s390x/inst.isle line 2524.
-        let expr0_0 = ALUOp::Add32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I16 {
-        // Rule at src/isa/s390x/inst.isle line 2525.
-        let expr0_0 = ALUOp::Add32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I32 {
-        // Rule at src/isa/s390x/inst.isle line 2526.
-        let expr0_0 = ALUOp::Add32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I64 {
-        // Rule at src/isa/s390x/inst.isle line 2527.
-        let expr0_0 = ALUOp::Add64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term aluop_add_sext16.
-pub fn constructor_aluop_add_sext16<C: Context>(ctx: &mut C, arg0: Type) -> Option<ALUOp> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I16 {
-        // Rule at src/isa/s390x/inst.isle line 2530.
-        let expr0_0 = ALUOp::Add32Ext16;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I32 {
-        // Rule at src/isa/s390x/inst.isle line 2531.
-        let expr0_0 = ALUOp::Add32Ext16;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I64 {
-        // Rule at src/isa/s390x/inst.isle line 2532.
-        let expr0_0 = ALUOp::Add64Ext16;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term aluop_add_sext32.
-pub fn constructor_aluop_add_sext32<C: Context>(ctx: &mut C, arg0: Type) -> Option<ALUOp> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I64 {
-        // Rule at src/isa/s390x/inst.isle line 2535.
-        let expr0_0 = ALUOp::Add64Ext32;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term add_reg.
-pub fn constructor_add_reg<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2538.
-    let expr0_0 = constructor_aluop_add(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_rrr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term add_reg_sext32.
-pub fn constructor_add_reg_sext32<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2541.
-    let expr0_0 = constructor_aluop_add_sext32(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_rr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term add_simm16.
-pub fn constructor_add_simm16<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: i16,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2544.
-    let expr0_0 = constructor_aluop_add(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_rrsimm16(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term add_simm32.
-pub fn constructor_add_simm32<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: i32,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2547.
-    let expr0_0 = constructor_aluop_add(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_rsimm32(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term add_mem.
-pub fn constructor_add_mem<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: &MemArg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2550.
-    let expr0_0 = constructor_aluop_add(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_rx(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term add_mem_sext16.
-pub fn constructor_add_mem_sext16<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: &MemArg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2553.
-    let expr0_0 = constructor_aluop_add_sext16(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_rx(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term add_mem_sext32.
-pub fn constructor_add_mem_sext32<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: &MemArg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2556.
-    let expr0_0 = constructor_aluop_add_sext32(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_rx(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term aluop_add_logical.
-pub fn constructor_aluop_add_logical<C: Context>(ctx: &mut C, arg0: Type) -> Option<ALUOp> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I32 {
-        // Rule at src/isa/s390x/inst.isle line 2562.
-        let expr0_0 = ALUOp::AddLogical32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I64 {
-        // Rule at src/isa/s390x/inst.isle line 2563.
-        let expr0_0 = ALUOp::AddLogical64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term aluop_add_logical_zext32.
-pub fn constructor_aluop_add_logical_zext32<C: Context>(ctx: &mut C, arg0: Type) -> Option<ALUOp> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I64 {
-        // Rule at src/isa/s390x/inst.isle line 2566.
-        let expr0_0 = ALUOp::AddLogical64Ext32;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term add_logical_reg.
-pub fn constructor_add_logical_reg<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2569.
-    let expr0_0 = constructor_aluop_add_logical(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_rrr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term add_logical_reg_zext32.
-pub fn constructor_add_logical_reg_zext32<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2572.
-    let expr0_0 = constructor_aluop_add_logical_zext32(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_rr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term add_logical_zimm32.
-pub fn constructor_add_logical_zimm32<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: u32,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2575.
-    let expr0_0 = constructor_aluop_add_logical(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_ruimm32(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term add_logical_mem.
-pub fn constructor_add_logical_mem<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: &MemArg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2578.
-    let expr0_0 = constructor_aluop_add_logical(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_rx(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term add_logical_mem_zext32.
-pub fn constructor_add_logical_mem_zext32<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: &MemArg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2581.
-    let expr0_0 = constructor_aluop_add_logical_zext32(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_rx(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term aluop_sub.
-pub fn constructor_aluop_sub<C: Context>(ctx: &mut C, arg0: Type) -> Option<ALUOp> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I8 {
-        // Rule at src/isa/s390x/inst.isle line 2587.
-        let expr0_0 = ALUOp::Sub32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I16 {
-        // Rule at src/isa/s390x/inst.isle line 2588.
-        let expr0_0 = ALUOp::Sub32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I32 {
-        // Rule at src/isa/s390x/inst.isle line 2589.
-        let expr0_0 = ALUOp::Sub32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I64 {
-        // Rule at src/isa/s390x/inst.isle line 2590.
-        let expr0_0 = ALUOp::Sub64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term aluop_sub_sext16.
-pub fn constructor_aluop_sub_sext16<C: Context>(ctx: &mut C, arg0: Type) -> Option<ALUOp> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I16 {
-        // Rule at src/isa/s390x/inst.isle line 2593.
-        let expr0_0 = ALUOp::Sub32Ext16;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I32 {
-        // Rule at src/isa/s390x/inst.isle line 2594.
-        let expr0_0 = ALUOp::Sub32Ext16;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I64 {
-        // Rule at src/isa/s390x/inst.isle line 2595.
-        let expr0_0 = ALUOp::Sub64Ext16;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term aluop_sub_sext32.
-pub fn constructor_aluop_sub_sext32<C: Context>(ctx: &mut C, arg0: Type) -> Option<ALUOp> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I64 {
-        // Rule at src/isa/s390x/inst.isle line 2598.
-        let expr0_0 = ALUOp::Sub64Ext32;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term sub_reg.
-pub fn constructor_sub_reg<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2601.
-    let expr0_0 = constructor_aluop_sub(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_rrr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term sub_reg_sext32.
-pub fn constructor_sub_reg_sext32<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2604.
-    let expr0_0 = constructor_aluop_sub_sext32(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_rr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term sub_mem.
-pub fn constructor_sub_mem<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: &MemArg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2607.
-    let expr0_0 = constructor_aluop_sub(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_rx(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term sub_mem_sext16.
-pub fn constructor_sub_mem_sext16<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: &MemArg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2610.
-    let expr0_0 = constructor_aluop_sub_sext16(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_rx(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term sub_mem_sext32.
-pub fn constructor_sub_mem_sext32<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: &MemArg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2613.
-    let expr0_0 = constructor_aluop_sub_sext32(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_rx(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term aluop_sub_logical.
-pub fn constructor_aluop_sub_logical<C: Context>(ctx: &mut C, arg0: Type) -> Option<ALUOp> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I32 {
-        // Rule at src/isa/s390x/inst.isle line 2619.
-        let expr0_0 = ALUOp::SubLogical32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I64 {
-        // Rule at src/isa/s390x/inst.isle line 2620.
-        let expr0_0 = ALUOp::SubLogical64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term aluop_sub_logical_zext32.
-pub fn constructor_aluop_sub_logical_zext32<C: Context>(ctx: &mut C, arg0: Type) -> Option<ALUOp> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I64 {
-        // Rule at src/isa/s390x/inst.isle line 2623.
-        let expr0_0 = ALUOp::SubLogical64Ext32;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term sub_logical_reg.
-pub fn constructor_sub_logical_reg<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2626.
-    let expr0_0 = constructor_aluop_sub_logical(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_rrr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term sub_logical_reg_zext32.
-pub fn constructor_sub_logical_reg_zext32<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2629.
-    let expr0_0 = constructor_aluop_sub_logical_zext32(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_rr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term sub_logical_zimm32.
-pub fn constructor_sub_logical_zimm32<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: u32,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2632.
-    let expr0_0 = constructor_aluop_sub_logical(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_ruimm32(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term sub_logical_mem.
-pub fn constructor_sub_logical_mem<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: &MemArg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2635.
-    let expr0_0 = constructor_aluop_sub_logical(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_rx(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term sub_logical_mem_zext32.
-pub fn constructor_sub_logical_mem_zext32<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: &MemArg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2638.
-    let expr0_0 = constructor_aluop_sub_logical(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_rx(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term aluop_mul.
-pub fn constructor_aluop_mul<C: Context>(ctx: &mut C, arg0: Type) -> Option<ALUOp> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I8 {
-        // Rule at src/isa/s390x/inst.isle line 2644.
-        let expr0_0 = ALUOp::Mul32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I16 {
-        // Rule at src/isa/s390x/inst.isle line 2645.
-        let expr0_0 = ALUOp::Mul32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I32 {
-        // Rule at src/isa/s390x/inst.isle line 2646.
-        let expr0_0 = ALUOp::Mul32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I64 {
-        // Rule at src/isa/s390x/inst.isle line 2647.
-        let expr0_0 = ALUOp::Mul64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term aluop_mul_sext16.
-pub fn constructor_aluop_mul_sext16<C: Context>(ctx: &mut C, arg0: Type) -> Option<ALUOp> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I16 {
-        // Rule at src/isa/s390x/inst.isle line 2650.
-        let expr0_0 = ALUOp::Mul32Ext16;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I32 {
-        // Rule at src/isa/s390x/inst.isle line 2651.
-        let expr0_0 = ALUOp::Mul32Ext16;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I64 {
-        // Rule at src/isa/s390x/inst.isle line 2652.
-        let expr0_0 = ALUOp::Mul64Ext16;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term aluop_mul_sext32.
-pub fn constructor_aluop_mul_sext32<C: Context>(ctx: &mut C, arg0: Type) -> Option<ALUOp> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I64 {
-        // Rule at src/isa/s390x/inst.isle line 2655.
-        let expr0_0 = ALUOp::Mul64Ext32;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term mul_reg.
-pub fn constructor_mul_reg<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2658.
-    let expr0_0 = constructor_aluop_mul(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_rrr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term mul_reg_sext32.
-pub fn constructor_mul_reg_sext32<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2661.
-    let expr0_0 = constructor_aluop_mul_sext32(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_rr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term mul_simm16.
-pub fn constructor_mul_simm16<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: i16,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2664.
-    let expr0_0 = constructor_aluop_mul(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_rsimm16(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term mul_simm32.
-pub fn constructor_mul_simm32<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: i32,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2667.
-    let expr0_0 = constructor_aluop_mul(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_rsimm32(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term mul_mem.
-pub fn constructor_mul_mem<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: &MemArg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2670.
-    let expr0_0 = constructor_aluop_mul(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_rx(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term mul_mem_sext16.
-pub fn constructor_mul_mem_sext16<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: &MemArg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2673.
-    let expr0_0 = constructor_aluop_mul_sext16(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_rx(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term mul_mem_sext32.
-pub fn constructor_mul_mem_sext32<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: &MemArg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2676.
-    let expr0_0 = constructor_aluop_mul_sext32(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_rx(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term udivmod.
-pub fn constructor_udivmod<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &RegPair,
-    arg2: Reg,
-) -> Option<RegPair> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I32 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/inst.isle line 2682.
-        let expr0_0 = constructor_udivmod32(ctx, pattern2_0, pattern3_0)?;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I64 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/inst.isle line 2683.
-        let expr0_0 = constructor_udivmod64(ctx, pattern2_0, pattern3_0)?;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term sdivmod.
-pub fn constructor_sdivmod<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &RegPair,
-    arg2: Reg,
-) -> Option<RegPair> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I32 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/inst.isle line 2689.
-        let expr0_0 = constructor_sdivmod32(ctx, pattern2_0, pattern3_0)?;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I64 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/inst.isle line 2690.
-        let expr0_0 = constructor_sdivmod64(ctx, pattern2_0, pattern3_0)?;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term aluop_and.
-pub fn constructor_aluop_and<C: Context>(ctx: &mut C, arg0: Type) -> Option<ALUOp> {
-    let pattern0_0 = arg0;
-    if let Some(pattern1_0) = C::gpr32_ty(ctx, pattern0_0) {
-        // Rule at src/isa/s390x/inst.isle line 2696.
-        let expr0_0 = ALUOp::And32;
-        return Some(expr0_0);
-    }
-    if let Some(pattern1_0) = C::gpr64_ty(ctx, pattern0_0) {
-        // Rule at src/isa/s390x/inst.isle line 2697.
-        let expr0_0 = ALUOp::And64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term and_reg.
-pub fn constructor_and_reg<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2700.
-    let expr0_0 = constructor_aluop_and(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_rrr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term and_uimm16shifted.
-pub fn constructor_and_uimm16shifted<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: UImm16Shifted,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2703.
-    let expr0_0 = constructor_aluop_and(ctx, pattern0_0)?;
-    let expr1_0 =
-        constructor_alu_ruimm16shifted(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term and_uimm32shifted.
-pub fn constructor_and_uimm32shifted<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: UImm32Shifted,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2706.
-    let expr0_0 = constructor_aluop_and(ctx, pattern0_0)?;
-    let expr1_0 =
-        constructor_alu_ruimm32shifted(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term and_mem.
-pub fn constructor_and_mem<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: &MemArg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2709.
-    let expr0_0 = constructor_aluop_and(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_rx(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term aluop_or.
-pub fn constructor_aluop_or<C: Context>(ctx: &mut C, arg0: Type) -> Option<ALUOp> {
-    let pattern0_0 = arg0;
-    if let Some(pattern1_0) = C::gpr32_ty(ctx, pattern0_0) {
-        // Rule at src/isa/s390x/inst.isle line 2715.
-        let expr0_0 = ALUOp::Orr32;
-        return Some(expr0_0);
-    }
-    if let Some(pattern1_0) = C::gpr64_ty(ctx, pattern0_0) {
-        // Rule at src/isa/s390x/inst.isle line 2716.
-        let expr0_0 = ALUOp::Orr64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term or_reg.
-pub fn constructor_or_reg<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2719.
-    let expr0_0 = constructor_aluop_or(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_rrr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term or_uimm16shifted.
-pub fn constructor_or_uimm16shifted<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: UImm16Shifted,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2722.
-    let expr0_0 = constructor_aluop_or(ctx, pattern0_0)?;
-    let expr1_0 =
-        constructor_alu_ruimm16shifted(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term or_uimm32shifted.
-pub fn constructor_or_uimm32shifted<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: UImm32Shifted,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2725.
-    let expr0_0 = constructor_aluop_or(ctx, pattern0_0)?;
-    let expr1_0 =
-        constructor_alu_ruimm32shifted(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term or_mem.
-pub fn constructor_or_mem<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: &MemArg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2728.
-    let expr0_0 = constructor_aluop_or(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_rx(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term aluop_xor.
-pub fn constructor_aluop_xor<C: Context>(ctx: &mut C, arg0: Type) -> Option<ALUOp> {
-    let pattern0_0 = arg0;
-    if let Some(pattern1_0) = C::gpr32_ty(ctx, pattern0_0) {
-        // Rule at src/isa/s390x/inst.isle line 2734.
-        let expr0_0 = ALUOp::Xor32;
-        return Some(expr0_0);
-    }
-    if let Some(pattern1_0) = C::gpr64_ty(ctx, pattern0_0) {
-        // Rule at src/isa/s390x/inst.isle line 2735.
-        let expr0_0 = ALUOp::Xor64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term xor_reg.
-pub fn constructor_xor_reg<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2738.
-    let expr0_0 = constructor_aluop_xor(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_rrr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term xor_uimm32shifted.
-pub fn constructor_xor_uimm32shifted<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: UImm32Shifted,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2741.
-    let expr0_0 = constructor_aluop_xor(ctx, pattern0_0)?;
-    let expr1_0 =
-        constructor_alu_ruimm32shifted(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term xor_mem.
-pub fn constructor_xor_mem<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: &MemArg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2744.
-    let expr0_0 = constructor_aluop_xor(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_rx(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term push_xor_uimm32shifted.
-pub fn constructor_push_xor_uimm32shifted<C: Context>(
-    ctx: &mut C,
-    arg0: &VecMInstBuilder,
-    arg1: Type,
-    arg2: WritableReg,
-    arg3: Reg,
-    arg4: UImm32Shifted,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    let pattern4_0 = arg4;
-    // Rule at src/isa/s390x/inst.isle line 2747.
-    let expr0_0 = constructor_aluop_xor(ctx, pattern1_0)?;
-    let expr1_0 = constructor_push_alu_uimm32shifted(
-        ctx, pattern0_0, &expr0_0, pattern2_0, pattern3_0, pattern4_0,
-    )?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term not_reg.
-pub fn constructor_not_reg<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    if let Some(pattern1_0) = C::gpr32_ty(ctx, pattern0_0) {
-        let pattern2_0 = arg1;
-        // Rule at src/isa/s390x/inst.isle line 2753.
-        let expr0_0: u32 = 4294967295;
-        let expr1_0: u8 = 0;
-        let expr2_0 = C::uimm32shifted(ctx, expr0_0, expr1_0);
-        let expr3_0 = constructor_xor_uimm32shifted(ctx, pattern1_0, pattern2_0, expr2_0)?;
-        return Some(expr3_0);
-    }
-    if let Some(pattern1_0) = C::gpr64_ty(ctx, pattern0_0) {
-        let pattern2_0 = arg1;
-        // Rule at src/isa/s390x/inst.isle line 2755.
-        let expr0_0: u32 = 4294967295;
-        let expr1_0: u8 = 0;
-        let expr2_0 = C::uimm32shifted(ctx, expr0_0, expr1_0);
-        let expr3_0 = constructor_xor_uimm32shifted(ctx, pattern1_0, pattern2_0, expr2_0)?;
-        let expr4_0: u32 = 4294967295;
-        let expr5_0: u8 = 32;
-        let expr6_0 = C::uimm32shifted(ctx, expr4_0, expr5_0);
-        let expr7_0 = constructor_xor_uimm32shifted(ctx, pattern1_0, expr3_0, expr6_0)?;
-        return Some(expr7_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term push_not_reg.
-pub fn constructor_push_not_reg<C: Context>(
-    ctx: &mut C,
-    arg0: &VecMInstBuilder,
-    arg1: Type,
-    arg2: WritableReg,
-    arg3: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    if let Some(pattern2_0) = C::gpr32_ty(ctx, pattern1_0) {
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/s390x/inst.isle line 2761.
-        let expr0_0: u32 = 4294967295;
-        let expr1_0: u8 = 0;
-        let expr2_0 = C::uimm32shifted(ctx, expr0_0, expr1_0);
-        let expr3_0 = constructor_push_xor_uimm32shifted(
-            ctx, pattern0_0, pattern2_0, pattern3_0, pattern4_0, expr2_0,
-        )?;
-        return Some(expr3_0);
-    }
-    if let Some(pattern2_0) = C::gpr64_ty(ctx, pattern1_0) {
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/s390x/inst.isle line 2763.
-        let expr0_0: u32 = 4294967295;
-        let expr1_0: u8 = 0;
-        let expr2_0 = C::uimm32shifted(ctx, expr0_0, expr1_0);
-        let expr3_0 = constructor_push_xor_uimm32shifted(
-            ctx, pattern0_0, pattern2_0, pattern3_0, pattern4_0, expr2_0,
-        )?;
-        let expr4_0: u32 = 4294967295;
-        let expr5_0: u8 = 32;
-        let expr6_0 = C::uimm32shifted(ctx, expr4_0, expr5_0);
-        let expr7_0 = constructor_push_xor_uimm32shifted(
-            ctx, pattern0_0, pattern2_0, pattern3_0, expr3_0, expr6_0,
-        )?;
-        return Some(expr7_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term aluop_and_not.
-pub fn constructor_aluop_and_not<C: Context>(ctx: &mut C, arg0: Type) -> Option<ALUOp> {
-    let pattern0_0 = arg0;
-    if let Some(pattern1_0) = C::gpr32_ty(ctx, pattern0_0) {
-        // Rule at src/isa/s390x/inst.isle line 2771.
-        let expr0_0 = ALUOp::AndNot32;
-        return Some(expr0_0);
-    }
-    if let Some(pattern1_0) = C::gpr64_ty(ctx, pattern0_0) {
-        // Rule at src/isa/s390x/inst.isle line 2772.
-        let expr0_0 = ALUOp::AndNot64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term and_not_reg.
-pub fn constructor_and_not_reg<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2775.
-    let expr0_0 = constructor_aluop_and_not(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_rrr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term aluop_or_not.
-pub fn constructor_aluop_or_not<C: Context>(ctx: &mut C, arg0: Type) -> Option<ALUOp> {
-    let pattern0_0 = arg0;
-    if let Some(pattern1_0) = C::gpr32_ty(ctx, pattern0_0) {
-        // Rule at src/isa/s390x/inst.isle line 2781.
-        let expr0_0 = ALUOp::OrrNot32;
-        return Some(expr0_0);
-    }
-    if let Some(pattern1_0) = C::gpr64_ty(ctx, pattern0_0) {
-        // Rule at src/isa/s390x/inst.isle line 2782.
-        let expr0_0 = ALUOp::OrrNot64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term or_not_reg.
-pub fn constructor_or_not_reg<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2785.
-    let expr0_0 = constructor_aluop_or_not(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_rrr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term aluop_xor_not.
-pub fn constructor_aluop_xor_not<C: Context>(ctx: &mut C, arg0: Type) -> Option<ALUOp> {
-    let pattern0_0 = arg0;
-    if let Some(pattern1_0) = C::gpr32_ty(ctx, pattern0_0) {
-        // Rule at src/isa/s390x/inst.isle line 2791.
-        let expr0_0 = ALUOp::XorNot32;
-        return Some(expr0_0);
-    }
-    if let Some(pattern1_0) = C::gpr64_ty(ctx, pattern0_0) {
-        // Rule at src/isa/s390x/inst.isle line 2792.
-        let expr0_0 = ALUOp::XorNot64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term xor_not_reg.
-pub fn constructor_xor_not_reg<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2795.
-    let expr0_0 = constructor_aluop_xor_not(ctx, pattern0_0)?;
-    let expr1_0 = constructor_alu_rrr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term unaryop_abs.
-pub fn constructor_unaryop_abs<C: Context>(ctx: &mut C, arg0: Type) -> Option<UnaryOp> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I32 {
-        // Rule at src/isa/s390x/inst.isle line 2801.
-        let expr0_0 = UnaryOp::Abs32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I64 {
-        // Rule at src/isa/s390x/inst.isle line 2802.
-        let expr0_0 = UnaryOp::Abs64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term unaryop_abs_sext32.
-pub fn constructor_unaryop_abs_sext32<C: Context>(ctx: &mut C, arg0: Type) -> Option<UnaryOp> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I64 {
-        // Rule at src/isa/s390x/inst.isle line 2805.
-        let expr0_0 = UnaryOp::Abs64Ext32;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term abs_reg.
-pub fn constructor_abs_reg<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 2808.
-    let expr0_0 = constructor_unaryop_abs(ctx, pattern0_0)?;
-    let expr1_0 = constructor_unary_rr(ctx, pattern0_0, &expr0_0, pattern1_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term abs_reg_sext32.
-pub fn constructor_abs_reg_sext32<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 2811.
-    let expr0_0 = constructor_unaryop_abs_sext32(ctx, pattern0_0)?;
-    let expr1_0 = constructor_unary_rr(ctx, pattern0_0, &expr0_0, pattern1_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term unaryop_neg.
-pub fn constructor_unaryop_neg<C: Context>(ctx: &mut C, arg0: Type) -> Option<UnaryOp> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I8 {
-        // Rule at src/isa/s390x/inst.isle line 2817.
-        let expr0_0 = UnaryOp::Neg32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I16 {
-        // Rule at src/isa/s390x/inst.isle line 2818.
-        let expr0_0 = UnaryOp::Neg32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I32 {
-        // Rule at src/isa/s390x/inst.isle line 2819.
-        let expr0_0 = UnaryOp::Neg32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I64 {
-        // Rule at src/isa/s390x/inst.isle line 2820.
-        let expr0_0 = UnaryOp::Neg64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term unaryop_neg_sext32.
-pub fn constructor_unaryop_neg_sext32<C: Context>(ctx: &mut C, arg0: Type) -> Option<UnaryOp> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I64 {
-        // Rule at src/isa/s390x/inst.isle line 2823.
-        let expr0_0 = UnaryOp::Neg64Ext32;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term neg_reg.
-pub fn constructor_neg_reg<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 2826.
-    let expr0_0 = constructor_unaryop_neg(ctx, pattern0_0)?;
-    let expr1_0 = constructor_unary_rr(ctx, pattern0_0, &expr0_0, pattern1_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term neg_reg_sext32.
-pub fn constructor_neg_reg_sext32<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 2829.
-    let expr0_0 = constructor_unaryop_neg_sext32(ctx, pattern0_0)?;
-    let expr1_0 = constructor_unary_rr(ctx, pattern0_0, &expr0_0, pattern1_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term unaryop_bswap.
-pub fn constructor_unaryop_bswap<C: Context>(ctx: &mut C, arg0: Type) -> Option<UnaryOp> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I32 {
-        // Rule at src/isa/s390x/inst.isle line 2835.
-        let expr0_0 = UnaryOp::BSwap32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I64 {
-        // Rule at src/isa/s390x/inst.isle line 2836.
-        let expr0_0 = UnaryOp::BSwap64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term bswap_reg.
-pub fn constructor_bswap_reg<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 2839.
-    let expr0_0 = constructor_unaryop_bswap(ctx, pattern0_0)?;
-    let expr1_0 = constructor_unary_rr(ctx, pattern0_0, &expr0_0, pattern1_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term push_bswap_reg.
-pub fn constructor_push_bswap_reg<C: Context>(
-    ctx: &mut C,
-    arg0: &VecMInstBuilder,
-    arg1: Type,
-    arg2: WritableReg,
-    arg3: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/s390x/inst.isle line 2842.
-    let expr0_0 = constructor_unaryop_bswap(ctx, pattern1_0)?;
-    let expr1_0 = constructor_push_unary(ctx, pattern0_0, &expr0_0, pattern2_0, pattern3_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term shiftop_rot.
-pub fn constructor_shiftop_rot<C: Context>(ctx: &mut C, arg0: Type) -> Option<ShiftOp> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I32 {
-        // Rule at src/isa/s390x/inst.isle line 2848.
-        let expr0_0 = ShiftOp::RotL32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I64 {
-        // Rule at src/isa/s390x/inst.isle line 2849.
-        let expr0_0 = ShiftOp::RotL64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term rot_reg.
-pub fn constructor_rot_reg<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2852.
-    let expr0_0 = constructor_shiftop_rot(ctx, pattern0_0)?;
-    let expr1_0: u8 = 0;
-    let expr2_0 = constructor_shift_rr(ctx, pattern0_0, &expr0_0, pattern1_0, expr1_0, pattern2_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term rot_imm.
-pub fn constructor_rot_imm<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: u8,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2856.
-    let expr0_0 = constructor_shiftop_rot(ctx, pattern0_0)?;
-    let expr1_0 = C::zero_reg(ctx);
-    let expr2_0 = constructor_shift_rr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0, expr1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term rot_imm_reg.
-pub fn constructor_rot_imm_reg<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: u8,
-    arg3: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/s390x/inst.isle line 2860.
-    let expr0_0 = constructor_shiftop_rot(ctx, pattern0_0)?;
-    let expr1_0 = constructor_shift_rr(
-        ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0, pattern3_0,
-    )?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term push_rot_imm_reg.
-pub fn constructor_push_rot_imm_reg<C: Context>(
-    ctx: &mut C,
-    arg0: &VecMInstBuilder,
-    arg1: Type,
-    arg2: WritableReg,
-    arg3: Reg,
-    arg4: u8,
-    arg5: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    let pattern4_0 = arg4;
-    let pattern5_0 = arg5;
-    // Rule at src/isa/s390x/inst.isle line 2864.
-    let expr0_0 = constructor_shiftop_rot(ctx, pattern1_0)?;
-    let expr1_0 = constructor_push_shift(
-        ctx, pattern0_0, &expr0_0, pattern2_0, pattern3_0, pattern4_0, pattern5_0,
-    )?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term shiftop_lshl.
-pub fn constructor_shiftop_lshl<C: Context>(ctx: &mut C, arg0: Type) -> Option<ShiftOp> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I8 {
-        // Rule at src/isa/s390x/inst.isle line 2871.
-        let expr0_0 = ShiftOp::LShL32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I16 {
-        // Rule at src/isa/s390x/inst.isle line 2872.
-        let expr0_0 = ShiftOp::LShL32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I32 {
-        // Rule at src/isa/s390x/inst.isle line 2873.
-        let expr0_0 = ShiftOp::LShL32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I64 {
-        // Rule at src/isa/s390x/inst.isle line 2874.
-        let expr0_0 = ShiftOp::LShL64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term lshl_reg.
-pub fn constructor_lshl_reg<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2877.
-    let expr0_0 = constructor_shiftop_lshl(ctx, pattern0_0)?;
-    let expr1_0: u8 = 0;
-    let expr2_0 = constructor_shift_rr(ctx, pattern0_0, &expr0_0, pattern1_0, expr1_0, pattern2_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term lshl_imm.
-pub fn constructor_lshl_imm<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: u8,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2881.
-    let expr0_0 = constructor_shiftop_lshl(ctx, pattern0_0)?;
-    let expr1_0 = C::zero_reg(ctx);
-    let expr2_0 = constructor_shift_rr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0, expr1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term shiftop_lshr.
-pub fn constructor_shiftop_lshr<C: Context>(ctx: &mut C, arg0: Type) -> Option<ShiftOp> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I32 {
-        // Rule at src/isa/s390x/inst.isle line 2888.
-        let expr0_0 = ShiftOp::LShR32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I64 {
-        // Rule at src/isa/s390x/inst.isle line 2889.
-        let expr0_0 = ShiftOp::LShR64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term lshr_reg.
-pub fn constructor_lshr_reg<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2892.
-    let expr0_0 = constructor_shiftop_lshr(ctx, pattern0_0)?;
-    let expr1_0: u8 = 0;
-    let expr2_0 = constructor_shift_rr(ctx, pattern0_0, &expr0_0, pattern1_0, expr1_0, pattern2_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term lshr_imm.
-pub fn constructor_lshr_imm<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: u8,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2896.
-    let expr0_0 = constructor_shiftop_lshr(ctx, pattern0_0)?;
-    let expr1_0 = C::zero_reg(ctx);
-    let expr2_0 = constructor_shift_rr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0, expr1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term shiftop_ashr.
-pub fn constructor_shiftop_ashr<C: Context>(ctx: &mut C, arg0: Type) -> Option<ShiftOp> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I32 {
-        // Rule at src/isa/s390x/inst.isle line 2903.
-        let expr0_0 = ShiftOp::AShR32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I64 {
-        // Rule at src/isa/s390x/inst.isle line 2904.
-        let expr0_0 = ShiftOp::AShR64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term ashr_reg.
-pub fn constructor_ashr_reg<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2907.
-    let expr0_0 = constructor_shiftop_ashr(ctx, pattern0_0)?;
-    let expr1_0: u8 = 0;
-    let expr2_0 = constructor_shift_rr(ctx, pattern0_0, &expr0_0, pattern1_0, expr1_0, pattern2_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term ashr_imm.
-pub fn constructor_ashr_imm<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: u8,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2911.
-    let expr0_0 = constructor_shiftop_ashr(ctx, pattern0_0)?;
-    let expr1_0 = C::zero_reg(ctx);
-    let expr2_0 = constructor_shift_rr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0, expr1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term popcnt_byte.
-pub fn constructor_popcnt_byte<C: Context>(ctx: &mut C, arg0: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/s390x/inst.isle line 2918.
-    let expr0_0: Type = I64;
-    let expr1_0 = UnaryOp::PopcntByte;
-    let expr2_0 = constructor_unary_rr(ctx, expr0_0, &expr1_0, pattern0_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term popcnt_reg.
-pub fn constructor_popcnt_reg<C: Context>(ctx: &mut C, arg0: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/s390x/inst.isle line 2921.
-    let expr0_0: Type = I64;
-    let expr1_0 = UnaryOp::PopcntReg;
-    let expr2_0 = constructor_unary_rr(ctx, expr0_0, &expr1_0, pattern0_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term atomic_rmw_and.
-pub fn constructor_atomic_rmw_and<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: &MemArg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I32 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/inst.isle line 2927.
-        let expr0_0: Type = I32;
-        let expr1_0 = ALUOp::And32;
-        let expr2_0 = constructor_atomic_rmw_impl(ctx, expr0_0, &expr1_0, pattern2_0, pattern3_0)?;
-        return Some(expr2_0);
-    }
-    if pattern0_0 == I64 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/inst.isle line 2928.
-        let expr0_0: Type = I64;
-        let expr1_0 = ALUOp::And64;
-        let expr2_0 = constructor_atomic_rmw_impl(ctx, expr0_0, &expr1_0, pattern2_0, pattern3_0)?;
-        return Some(expr2_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term atomic_rmw_or.
-pub fn constructor_atomic_rmw_or<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: &MemArg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I32 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/inst.isle line 2931.
-        let expr0_0: Type = I32;
-        let expr1_0 = ALUOp::Orr32;
-        let expr2_0 = constructor_atomic_rmw_impl(ctx, expr0_0, &expr1_0, pattern2_0, pattern3_0)?;
-        return Some(expr2_0);
-    }
-    if pattern0_0 == I64 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/inst.isle line 2932.
-        let expr0_0: Type = I64;
-        let expr1_0 = ALUOp::Orr64;
-        let expr2_0 = constructor_atomic_rmw_impl(ctx, expr0_0, &expr1_0, pattern2_0, pattern3_0)?;
-        return Some(expr2_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term atomic_rmw_xor.
-pub fn constructor_atomic_rmw_xor<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: &MemArg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I32 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/inst.isle line 2935.
-        let expr0_0: Type = I32;
-        let expr1_0 = ALUOp::Xor32;
-        let expr2_0 = constructor_atomic_rmw_impl(ctx, expr0_0, &expr1_0, pattern2_0, pattern3_0)?;
-        return Some(expr2_0);
-    }
-    if pattern0_0 == I64 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/inst.isle line 2936.
-        let expr0_0: Type = I64;
-        let expr1_0 = ALUOp::Xor64;
-        let expr2_0 = constructor_atomic_rmw_impl(ctx, expr0_0, &expr1_0, pattern2_0, pattern3_0)?;
-        return Some(expr2_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term atomic_rmw_add.
-pub fn constructor_atomic_rmw_add<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: &MemArg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I32 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/inst.isle line 2939.
-        let expr0_0: Type = I32;
-        let expr1_0 = ALUOp::Add32;
-        let expr2_0 = constructor_atomic_rmw_impl(ctx, expr0_0, &expr1_0, pattern2_0, pattern3_0)?;
-        return Some(expr2_0);
-    }
-    if pattern0_0 == I64 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/inst.isle line 2940.
-        let expr0_0: Type = I64;
-        let expr1_0 = ALUOp::Add64;
-        let expr2_0 = constructor_atomic_rmw_impl(ctx, expr0_0, &expr1_0, pattern2_0, pattern3_0)?;
-        return Some(expr2_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term atomic_cas_impl.
-pub fn constructor_atomic_cas_impl<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-    arg3: &MemArg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I32 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/s390x/inst.isle line 2946.
-        let expr0_0 = constructor_atomic_cas32(ctx, pattern2_0, pattern3_0, pattern4_0)?;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I64 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/s390x/inst.isle line 2947.
-        let expr0_0 = constructor_atomic_cas64(ctx, pattern2_0, pattern3_0, pattern4_0)?;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term push_atomic_cas.
-pub fn constructor_push_atomic_cas<C: Context>(
-    ctx: &mut C,
-    arg0: &VecMInstBuilder,
-    arg1: Type,
-    arg2: WritableReg,
-    arg3: Reg,
-    arg4: &MemArg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    if pattern1_0 == I32 {
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        let pattern5_0 = arg4;
-        // Rule at src/isa/s390x/inst.isle line 2950.
-        let expr0_0 =
-            constructor_push_atomic_cas32(ctx, pattern0_0, pattern3_0, pattern4_0, pattern5_0)?;
-        return Some(expr0_0);
-    }
-    if pattern1_0 == I64 {
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        let pattern5_0 = arg4;
-        // Rule at src/isa/s390x/inst.isle line 2951.
-        let expr0_0 =
-            constructor_push_atomic_cas64(ctx, pattern0_0, pattern3_0, pattern4_0, pattern5_0)?;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term fpuop2_add.
-pub fn constructor_fpuop2_add<C: Context>(ctx: &mut C, arg0: Type) -> Option<FPUOp2> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == F32 {
-        // Rule at src/isa/s390x/inst.isle line 2957.
-        let expr0_0 = FPUOp2::Add32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == F64 {
-        // Rule at src/isa/s390x/inst.isle line 2958.
-        let expr0_0 = FPUOp2::Add64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term fadd_reg.
-pub fn constructor_fadd_reg<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2961.
-    let expr0_0 = constructor_fpuop2_add(ctx, pattern0_0)?;
-    let expr1_0 = constructor_fpu_rrr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term fpuop2_sub.
-pub fn constructor_fpuop2_sub<C: Context>(ctx: &mut C, arg0: Type) -> Option<FPUOp2> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == F32 {
-        // Rule at src/isa/s390x/inst.isle line 2967.
-        let expr0_0 = FPUOp2::Sub32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == F64 {
-        // Rule at src/isa/s390x/inst.isle line 2968.
-        let expr0_0 = FPUOp2::Sub64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term fsub_reg.
-pub fn constructor_fsub_reg<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2971.
-    let expr0_0 = constructor_fpuop2_sub(ctx, pattern0_0)?;
-    let expr1_0 = constructor_fpu_rrr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term fpuop2_mul.
-pub fn constructor_fpuop2_mul<C: Context>(ctx: &mut C, arg0: Type) -> Option<FPUOp2> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == F32 {
-        // Rule at src/isa/s390x/inst.isle line 2977.
-        let expr0_0 = FPUOp2::Mul32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == F64 {
-        // Rule at src/isa/s390x/inst.isle line 2978.
-        let expr0_0 = FPUOp2::Mul64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term fmul_reg.
-pub fn constructor_fmul_reg<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2981.
-    let expr0_0 = constructor_fpuop2_mul(ctx, pattern0_0)?;
-    let expr1_0 = constructor_fpu_rrr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term fpuop2_div.
-pub fn constructor_fpuop2_div<C: Context>(ctx: &mut C, arg0: Type) -> Option<FPUOp2> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == F32 {
-        // Rule at src/isa/s390x/inst.isle line 2987.
-        let expr0_0 = FPUOp2::Div32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == F64 {
-        // Rule at src/isa/s390x/inst.isle line 2988.
-        let expr0_0 = FPUOp2::Div64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term fdiv_reg.
-pub fn constructor_fdiv_reg<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 2991.
-    let expr0_0 = constructor_fpuop2_div(ctx, pattern0_0)?;
-    let expr1_0 = constructor_fpu_rrr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term fpuop2_min.
-pub fn constructor_fpuop2_min<C: Context>(ctx: &mut C, arg0: Type) -> Option<FPUOp2> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == F32 {
-        // Rule at src/isa/s390x/inst.isle line 2997.
-        let expr0_0 = FPUOp2::Min32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == F64 {
-        // Rule at src/isa/s390x/inst.isle line 2998.
-        let expr0_0 = FPUOp2::Min64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term fmin_reg.
-pub fn constructor_fmin_reg<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 3001.
-    let expr0_0 = constructor_fpuop2_min(ctx, pattern0_0)?;
-    let expr1_0 = constructor_fpuvec_rrr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term fpuop2_max.
-pub fn constructor_fpuop2_max<C: Context>(ctx: &mut C, arg0: Type) -> Option<FPUOp2> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == F32 {
-        // Rule at src/isa/s390x/inst.isle line 3007.
-        let expr0_0 = FPUOp2::Max32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == F64 {
-        // Rule at src/isa/s390x/inst.isle line 3008.
-        let expr0_0 = FPUOp2::Max64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term fmax_reg.
-pub fn constructor_fmax_reg<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 3011.
-    let expr0_0 = constructor_fpuop2_max(ctx, pattern0_0)?;
-    let expr1_0 = constructor_fpuvec_rrr(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term fpuop3_fma.
-pub fn constructor_fpuop3_fma<C: Context>(ctx: &mut C, arg0: Type) -> Option<FPUOp3> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == F32 {
-        // Rule at src/isa/s390x/inst.isle line 3017.
-        let expr0_0 = FPUOp3::MAdd32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == F64 {
-        // Rule at src/isa/s390x/inst.isle line 3018.
-        let expr0_0 = FPUOp3::MAdd64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term fma_reg.
-pub fn constructor_fma_reg<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-    arg3: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/s390x/inst.isle line 3021.
-    let expr0_0 = constructor_fpuop3_fma(ctx, pattern0_0)?;
-    let expr1_0 = constructor_fpu_rrrr(
-        ctx, pattern0_0, &expr0_0, pattern3_0, pattern1_0, pattern2_0,
-    )?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term fpuop1_sqrt.
-pub fn constructor_fpuop1_sqrt<C: Context>(ctx: &mut C, arg0: Type) -> Option<FPUOp1> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == F32 {
-        // Rule at src/isa/s390x/inst.isle line 3027.
-        let expr0_0 = FPUOp1::Sqrt32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == F64 {
-        // Rule at src/isa/s390x/inst.isle line 3028.
-        let expr0_0 = FPUOp1::Sqrt64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term sqrt_reg.
-pub fn constructor_sqrt_reg<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 3031.
-    let expr0_0 = constructor_fpuop1_sqrt(ctx, pattern0_0)?;
-    let expr1_0 = constructor_fpu_rr(ctx, pattern0_0, &expr0_0, pattern1_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term fpuop1_neg.
-pub fn constructor_fpuop1_neg<C: Context>(ctx: &mut C, arg0: Type) -> Option<FPUOp1> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == F32 {
-        // Rule at src/isa/s390x/inst.isle line 3037.
-        let expr0_0 = FPUOp1::Neg32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == F64 {
-        // Rule at src/isa/s390x/inst.isle line 3038.
-        let expr0_0 = FPUOp1::Neg64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term fneg_reg.
-pub fn constructor_fneg_reg<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 3041.
-    let expr0_0 = constructor_fpuop1_neg(ctx, pattern0_0)?;
-    let expr1_0 = constructor_fpu_rr(ctx, pattern0_0, &expr0_0, pattern1_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term fpuop1_abs.
-pub fn constructor_fpuop1_abs<C: Context>(ctx: &mut C, arg0: Type) -> Option<FPUOp1> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == F32 {
-        // Rule at src/isa/s390x/inst.isle line 3047.
-        let expr0_0 = FPUOp1::Abs32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == F64 {
-        // Rule at src/isa/s390x/inst.isle line 3048.
-        let expr0_0 = FPUOp1::Abs64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term fabs_reg.
-pub fn constructor_fabs_reg<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 3051.
-    let expr0_0 = constructor_fpuop1_abs(ctx, pattern0_0)?;
-    let expr1_0 = constructor_fpu_rr(ctx, pattern0_0, &expr0_0, pattern1_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term fpuroundmode_ceil.
-pub fn constructor_fpuroundmode_ceil<C: Context>(ctx: &mut C, arg0: Type) -> Option<FpuRoundMode> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == F32 {
-        // Rule at src/isa/s390x/inst.isle line 3057.
-        let expr0_0 = FpuRoundMode::Plus32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == F64 {
-        // Rule at src/isa/s390x/inst.isle line 3058.
-        let expr0_0 = FpuRoundMode::Plus64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term ceil_reg.
-pub fn constructor_ceil_reg<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 3061.
-    let expr0_0 = constructor_fpuroundmode_ceil(ctx, pattern0_0)?;
-    let expr1_0 = constructor_fpu_round(ctx, pattern0_0, &expr0_0, pattern1_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term fpuroundmode_floor.
-pub fn constructor_fpuroundmode_floor<C: Context>(ctx: &mut C, arg0: Type) -> Option<FpuRoundMode> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == F32 {
-        // Rule at src/isa/s390x/inst.isle line 3067.
-        let expr0_0 = FpuRoundMode::Minus32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == F64 {
-        // Rule at src/isa/s390x/inst.isle line 3068.
-        let expr0_0 = FpuRoundMode::Minus64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term floor_reg.
-pub fn constructor_floor_reg<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 3071.
-    let expr0_0 = constructor_fpuroundmode_floor(ctx, pattern0_0)?;
-    let expr1_0 = constructor_fpu_round(ctx, pattern0_0, &expr0_0, pattern1_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term fpuroundmode_trunc.
-pub fn constructor_fpuroundmode_trunc<C: Context>(ctx: &mut C, arg0: Type) -> Option<FpuRoundMode> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == F32 {
-        // Rule at src/isa/s390x/inst.isle line 3077.
-        let expr0_0 = FpuRoundMode::Zero32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == F64 {
-        // Rule at src/isa/s390x/inst.isle line 3078.
-        let expr0_0 = FpuRoundMode::Zero64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term trunc_reg.
-pub fn constructor_trunc_reg<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 3081.
-    let expr0_0 = constructor_fpuroundmode_trunc(ctx, pattern0_0)?;
-    let expr1_0 = constructor_fpu_round(ctx, pattern0_0, &expr0_0, pattern1_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term fpuroundmode_nearest.
-pub fn constructor_fpuroundmode_nearest<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-) -> Option<FpuRoundMode> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == F32 {
-        // Rule at src/isa/s390x/inst.isle line 3087.
-        let expr0_0 = FpuRoundMode::Nearest32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == F64 {
-        // Rule at src/isa/s390x/inst.isle line 3088.
-        let expr0_0 = FpuRoundMode::Nearest64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term nearest_reg.
-pub fn constructor_nearest_reg<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/s390x/inst.isle line 3091.
-    let expr0_0 = constructor_fpuroundmode_nearest(ctx, pattern0_0)?;
-    let expr1_0 = constructor_fpu_round(ctx, pattern0_0, &expr0_0, pattern1_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term fpuop1_promote.
-pub fn constructor_fpuop1_promote<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Type,
-) -> Option<FPUOp1> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == F64 {
-        let pattern2_0 = arg1;
-        if pattern2_0 == F32 {
-            // Rule at src/isa/s390x/inst.isle line 3097.
-            let expr0_0 = FPUOp1::Cvt32To64;
-            return Some(expr0_0);
-        }
-    }
-    return None;
-}
-
-// Generated as internal constructor for term fpromote_reg.
-pub fn constructor_fpromote_reg<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Type,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 3100.
-    let expr0_0 = constructor_fpuop1_promote(ctx, pattern0_0, pattern1_0)?;
-    let expr1_0 = constructor_fpu_rr(ctx, pattern0_0, &expr0_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term fpuop1_demote.
-pub fn constructor_fpuop1_demote<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Type,
-) -> Option<FPUOp1> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == F32 {
-        let pattern2_0 = arg1;
-        if pattern2_0 == F64 {
-            // Rule at src/isa/s390x/inst.isle line 3107.
-            let expr0_0 = FPUOp1::Cvt64To32;
-            return Some(expr0_0);
-        }
-    }
-    return None;
-}
-
-// Generated as internal constructor for term fdemote_reg.
-pub fn constructor_fdemote_reg<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Type,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 3110.
-    let expr0_0 = constructor_fpuop1_demote(ctx, pattern0_0, pattern1_0)?;
-    let expr1_0 = constructor_fpu_rr(ctx, pattern0_0, &expr0_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term uint_to_fpu_op.
-pub fn constructor_uint_to_fpu_op<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Type,
-) -> Option<IntToFpuOp> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == F32 {
-        let pattern2_0 = arg1;
-        if pattern2_0 == I32 {
-            // Rule at src/isa/s390x/inst.isle line 3117.
-            let expr0_0 = IntToFpuOp::U32ToF32;
-            return Some(expr0_0);
-        }
-        if pattern2_0 == I64 {
-            // Rule at src/isa/s390x/inst.isle line 3119.
-            let expr0_0 = IntToFpuOp::U64ToF32;
-            return Some(expr0_0);
-        }
-    }
-    if pattern0_0 == F64 {
-        let pattern2_0 = arg1;
-        if pattern2_0 == I32 {
-            // Rule at src/isa/s390x/inst.isle line 3118.
-            let expr0_0 = IntToFpuOp::U32ToF64;
-            return Some(expr0_0);
-        }
-        if pattern2_0 == I64 {
-            // Rule at src/isa/s390x/inst.isle line 3120.
-            let expr0_0 = IntToFpuOp::U64ToF64;
-            return Some(expr0_0);
-        }
-    }
-    return None;
-}
-
-// Generated as internal constructor for term fcvt_from_uint_reg.
-pub fn constructor_fcvt_from_uint_reg<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Type,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 3123.
-    let expr0_0 = constructor_uint_to_fpu_op(ctx, pattern0_0, pattern1_0)?;
-    let expr1_0 = constructor_int_to_fpu(ctx, pattern0_0, &expr0_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term sint_to_fpu_op.
-pub fn constructor_sint_to_fpu_op<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Type,
-) -> Option<IntToFpuOp> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == F32 {
-        let pattern2_0 = arg1;
-        if pattern2_0 == I32 {
-            // Rule at src/isa/s390x/inst.isle line 3130.
-            let expr0_0 = IntToFpuOp::I32ToF32;
-            return Some(expr0_0);
-        }
-        if pattern2_0 == I64 {
-            // Rule at src/isa/s390x/inst.isle line 3132.
-            let expr0_0 = IntToFpuOp::I64ToF32;
-            return Some(expr0_0);
-        }
-    }
-    if pattern0_0 == F64 {
-        let pattern2_0 = arg1;
-        if pattern2_0 == I32 {
-            // Rule at src/isa/s390x/inst.isle line 3131.
-            let expr0_0 = IntToFpuOp::I32ToF64;
-            return Some(expr0_0);
-        }
-        if pattern2_0 == I64 {
-            // Rule at src/isa/s390x/inst.isle line 3133.
-            let expr0_0 = IntToFpuOp::I64ToF64;
-            return Some(expr0_0);
-        }
-    }
-    return None;
-}
-
-// Generated as internal constructor for term fcvt_from_sint_reg.
-pub fn constructor_fcvt_from_sint_reg<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Type,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 3136.
-    let expr0_0 = constructor_sint_to_fpu_op(ctx, pattern0_0, pattern1_0)?;
-    let expr1_0 = constructor_int_to_fpu(ctx, pattern0_0, &expr0_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term fpu_to_uint_op.
-pub fn constructor_fpu_to_uint_op<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Type,
-) -> Option<FpuToIntOp> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I32 {
-        let pattern2_0 = arg1;
-        if pattern2_0 == F32 {
-            // Rule at src/isa/s390x/inst.isle line 3143.
-            let expr0_0 = FpuToIntOp::F32ToU32;
-            return Some(expr0_0);
-        }
-        if pattern2_0 == F64 {
-            // Rule at src/isa/s390x/inst.isle line 3144.
-            let expr0_0 = FpuToIntOp::F64ToU32;
-            return Some(expr0_0);
-        }
-    }
-    if pattern0_0 == I64 {
-        let pattern2_0 = arg1;
-        if pattern2_0 == F32 {
-            // Rule at src/isa/s390x/inst.isle line 3145.
-            let expr0_0 = FpuToIntOp::F32ToU64;
-            return Some(expr0_0);
-        }
-        if pattern2_0 == F64 {
-            // Rule at src/isa/s390x/inst.isle line 3146.
-            let expr0_0 = FpuToIntOp::F64ToU64;
-            return Some(expr0_0);
-        }
-    }
-    return None;
-}
-
-// Generated as internal constructor for term fcvt_to_uint_reg_with_flags.
-pub fn constructor_fcvt_to_uint_reg_with_flags<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Type,
-    arg2: Reg,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 3149.
-    let expr0_0 = constructor_fpu_to_uint_op(ctx, pattern0_0, pattern1_0)?;
-    let expr1_0 = constructor_fpu_to_int(ctx, pattern0_0, &expr0_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term fcvt_to_uint_reg.
-pub fn constructor_fcvt_to_uint_reg<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Type,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 3153.
-    let expr0_0 = constructor_fcvt_to_uint_reg_with_flags(ctx, pattern0_0, pattern1_0, pattern2_0)?;
-    let expr1_0 = constructor_drop_flags(ctx, &expr0_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term fpu_to_sint_op.
-pub fn constructor_fpu_to_sint_op<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Type,
-) -> Option<FpuToIntOp> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I32 {
-        let pattern2_0 = arg1;
-        if pattern2_0 == F32 {
-            // Rule at src/isa/s390x/inst.isle line 3160.
-            let expr0_0 = FpuToIntOp::F32ToI32;
-            return Some(expr0_0);
-        }
-        if pattern2_0 == F64 {
-            // Rule at src/isa/s390x/inst.isle line 3161.
-            let expr0_0 = FpuToIntOp::F64ToI32;
-            return Some(expr0_0);
-        }
-    }
-    if pattern0_0 == I64 {
-        let pattern2_0 = arg1;
-        if pattern2_0 == F32 {
-            // Rule at src/isa/s390x/inst.isle line 3162.
-            let expr0_0 = FpuToIntOp::F32ToI64;
-            return Some(expr0_0);
-        }
-        if pattern2_0 == F64 {
-            // Rule at src/isa/s390x/inst.isle line 3163.
-            let expr0_0 = FpuToIntOp::F64ToI64;
-            return Some(expr0_0);
-        }
-    }
-    return None;
-}
-
-// Generated as internal constructor for term fcvt_to_sint_reg_with_flags.
-pub fn constructor_fcvt_to_sint_reg_with_flags<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Type,
-    arg2: Reg,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 3166.
-    let expr0_0 = constructor_fpu_to_sint_op(ctx, pattern0_0, pattern1_0)?;
-    let expr1_0 = constructor_fpu_to_int(ctx, pattern0_0, &expr0_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term fcvt_to_sint_reg.
-pub fn constructor_fcvt_to_sint_reg<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Type,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 3170.
-    let expr0_0 = constructor_fcvt_to_sint_reg_with_flags(ctx, pattern0_0, pattern1_0, pattern2_0)?;
-    let expr1_0 = constructor_drop_flags(ctx, &expr0_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term cmpop_cmps.
-pub fn constructor_cmpop_cmps<C: Context>(ctx: &mut C, arg0: Type) -> Option<CmpOp> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I32 {
-        // Rule at src/isa/s390x/inst.isle line 3177.
-        let expr0_0 = CmpOp::CmpS32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I64 {
-        // Rule at src/isa/s390x/inst.isle line 3178.
-        let expr0_0 = CmpOp::CmpS64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term cmpop_cmps_sext16.
-pub fn constructor_cmpop_cmps_sext16<C: Context>(ctx: &mut C, arg0: Type) -> Option<CmpOp> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I32 {
-        // Rule at src/isa/s390x/inst.isle line 3181.
-        let expr0_0 = CmpOp::CmpS32Ext16;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I64 {
-        // Rule at src/isa/s390x/inst.isle line 3182.
-        let expr0_0 = CmpOp::CmpS64Ext16;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term cmpop_cmps_sext32.
-pub fn constructor_cmpop_cmps_sext32<C: Context>(ctx: &mut C, arg0: Type) -> Option<CmpOp> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I64 {
-        // Rule at src/isa/s390x/inst.isle line 3185.
-        let expr0_0 = CmpOp::CmpS64Ext32;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term icmps_reg.
-pub fn constructor_icmps_reg<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 3188.
-    let expr0_0 = constructor_cmpop_cmps(ctx, pattern0_0)?;
-    let expr1_0 = constructor_cmp_rr(ctx, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term icmps_reg_sext32.
-pub fn constructor_icmps_reg_sext32<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 3191.
-    let expr0_0 = constructor_cmpop_cmps_sext32(ctx, pattern0_0)?;
-    let expr1_0 = constructor_cmp_rr(ctx, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term icmps_simm16.
-pub fn constructor_icmps_simm16<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: i16,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 3194.
-    let expr0_0 = constructor_cmpop_cmps(ctx, pattern0_0)?;
-    let expr1_0 = constructor_cmp_rsimm16(ctx, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term icmps_simm32.
-pub fn constructor_icmps_simm32<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: i32,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 3197.
-    let expr0_0 = constructor_cmpop_cmps(ctx, pattern0_0)?;
-    let expr1_0 = constructor_cmp_rsimm32(ctx, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term icmps_mem.
-pub fn constructor_icmps_mem<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: &MemArg,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 3200.
-    let expr0_0 = constructor_cmpop_cmps(ctx, pattern0_0)?;
-    let expr1_0 = constructor_cmp_rx(ctx, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term icmps_mem_sext16.
-pub fn constructor_icmps_mem_sext16<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: &MemArg,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 3203.
-    let expr0_0 = constructor_cmpop_cmps_sext16(ctx, pattern0_0)?;
-    let expr1_0 = constructor_cmp_rx(ctx, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term icmps_mem_sext32.
-pub fn constructor_icmps_mem_sext32<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: &MemArg,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 3206.
-    let expr0_0 = constructor_cmpop_cmps_sext32(ctx, pattern0_0)?;
-    let expr1_0 = constructor_cmp_rx(ctx, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term cmpop_cmpu.
-pub fn constructor_cmpop_cmpu<C: Context>(ctx: &mut C, arg0: Type) -> Option<CmpOp> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I32 {
-        // Rule at src/isa/s390x/inst.isle line 3212.
-        let expr0_0 = CmpOp::CmpL32;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I64 {
-        // Rule at src/isa/s390x/inst.isle line 3213.
-        let expr0_0 = CmpOp::CmpL64;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term cmpop_cmpu_zext16.
-pub fn constructor_cmpop_cmpu_zext16<C: Context>(ctx: &mut C, arg0: Type) -> Option<CmpOp> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I32 {
-        // Rule at src/isa/s390x/inst.isle line 3216.
-        let expr0_0 = CmpOp::CmpL32Ext16;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I64 {
-        // Rule at src/isa/s390x/inst.isle line 3217.
-        let expr0_0 = CmpOp::CmpL64Ext16;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term cmpop_cmpu_zext32.
-pub fn constructor_cmpop_cmpu_zext32<C: Context>(ctx: &mut C, arg0: Type) -> Option<CmpOp> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I64 {
-        // Rule at src/isa/s390x/inst.isle line 3220.
-        let expr0_0 = CmpOp::CmpL64Ext32;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term icmpu_reg.
-pub fn constructor_icmpu_reg<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 3223.
-    let expr0_0 = constructor_cmpop_cmpu(ctx, pattern0_0)?;
-    let expr1_0 = constructor_cmp_rr(ctx, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term icmpu_reg_zext32.
-pub fn constructor_icmpu_reg_zext32<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 3226.
-    let expr0_0 = constructor_cmpop_cmpu_zext32(ctx, pattern0_0)?;
-    let expr1_0 = constructor_cmp_rr(ctx, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term icmpu_uimm32.
-pub fn constructor_icmpu_uimm32<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: u32,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 3229.
-    let expr0_0 = constructor_cmpop_cmpu(ctx, pattern0_0)?;
-    let expr1_0 = constructor_cmp_ruimm32(ctx, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term icmpu_mem.
-pub fn constructor_icmpu_mem<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: &MemArg,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 3232.
-    let expr0_0 = constructor_cmpop_cmpu(ctx, pattern0_0)?;
-    let expr1_0 = constructor_cmp_rx(ctx, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term icmpu_mem_zext16.
-pub fn constructor_icmpu_mem_zext16<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: &MemArg,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 3235.
-    let expr0_0 = constructor_cmpop_cmpu_zext16(ctx, pattern0_0)?;
-    let expr1_0 = constructor_cmp_rx(ctx, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term icmpu_mem_zext32.
-pub fn constructor_icmpu_mem_zext32<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: &MemArg,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/s390x/inst.isle line 3238.
-    let expr0_0 = constructor_cmpop_cmpu_zext32(ctx, pattern0_0)?;
-    let expr1_0 = constructor_cmp_rx(ctx, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term fcmp_reg.
-pub fn constructor_fcmp_reg<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Reg,
-    arg2: Reg,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == F32 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/inst.isle line 3244.
-        let expr0_0 = constructor_fpu_cmp32(ctx, pattern2_0, pattern3_0)?;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == F64 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/inst.isle line 3245.
-        let expr0_0 = constructor_fpu_cmp64(ctx, pattern2_0, pattern3_0)?;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term lower.
-pub fn constructor_lower<C: Context>(ctx: &mut C, arg0: Inst) -> Option<InstOutput> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = C::inst_data(ctx, pattern0_0);
-    match &pattern1_0 {
-        &InstructionData::NullAry {
-            opcode: ref pattern2_0,
-        } => {
-            match pattern2_0 {
-                &Opcode::Debugtrap => {
-                    // Rule at src/isa/s390x/lower.isle line 2169.
-                    let expr0_0 = constructor_debugtrap_impl(ctx)?;
-                    let expr1_0 = constructor_side_effect(ctx, &expr0_0)?;
-                    return Some(expr1_0);
-                }
-                &Opcode::Nop => {
-                    // Rule at src/isa/s390x/lower.isle line 47.
-                    let expr0_0 = C::invalid_reg(ctx);
-                    let expr1_0 = constructor_output_reg(ctx, expr0_0)?;
-                    return Some(expr1_0);
-                }
-                &Opcode::Fence => {
-                    // Rule at src/isa/s390x/lower.isle line 1882.
-                    let expr0_0 = constructor_fence_impl(ctx)?;
-                    let expr1_0 = constructor_side_effect(ctx, &expr0_0)?;
-                    return Some(expr1_0);
-                }
-                _ => {}
-            }
-        }
-        &InstructionData::FuncAddr {
-            opcode: ref pattern2_0,
-            func_ref: pattern2_1,
-        } => {
-            if let &Opcode::FuncAddr = pattern2_0 {
-                let (pattern4_0, pattern4_1, pattern4_2) = C::func_ref_data(ctx, pattern2_1);
-                if let Some(()) = C::reloc_distance_near(ctx, pattern4_2) {
-                    // Rule at src/isa/s390x/lower.isle line 1159.
-                    let expr0_0: i32 = 0;
-                    let expr1_0 = C::memflags_trusted(ctx);
-                    let expr2_0 = C::memarg_symbol(ctx, pattern4_1, expr0_0, expr1_0);
-                    let expr3_0 = constructor_load_addr(ctx, &expr2_0)?;
-                    let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                    return Some(expr4_0);
-                }
-                // Rule at src/isa/s390x/lower.isle line 1163.
-                let expr0_0: i64 = 0;
-                let expr1_0 = constructor_load_ext_name_far(ctx, pattern4_1, expr0_0)?;
-                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                return Some(expr2_0);
-            }
-        }
-        &InstructionData::UnaryGlobalValue {
-            opcode: ref pattern2_0,
-            global_value: pattern2_1,
-        } => {
-            if let &Opcode::SymbolValue = pattern2_0 {
-                if let Some((pattern4_0, pattern4_1, pattern4_2)) =
-                    C::symbol_value_data(ctx, pattern2_1)
-                {
-                    if let Some(()) = C::reloc_distance_near(ctx, pattern4_1) {
-                        let pattern6_0 = 0;
-                        if let Some(pattern7_0) =
-                            C::memarg_symbol_offset_sum(ctx, pattern4_2, pattern6_0)
-                        {
-                            // Rule at src/isa/s390x/lower.isle line 1170.
-                            let expr0_0 = C::memflags_trusted(ctx);
-                            let expr1_0 = C::memarg_symbol(ctx, pattern4_0, pattern7_0, expr0_0);
-                            let expr2_0 = constructor_load_addr(ctx, &expr1_0)?;
-                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                    }
-                    // Rule at src/isa/s390x/lower.isle line 1175.
-                    let expr0_0 = constructor_load_ext_name_far(ctx, pattern4_0, pattern4_2)?;
-                    let expr1_0 = constructor_output_reg(ctx, expr0_0)?;
-                    return Some(expr1_0);
-                }
-            }
-        }
-        &InstructionData::UnaryIeee32 {
-            opcode: ref pattern2_0,
-            imm: pattern2_1,
-        } => {
-            if let &Opcode::F32const = pattern2_0 {
-                let pattern4_0 = C::u64_from_ieee32(ctx, pattern2_1);
-                // Rule at src/isa/s390x/lower.isle line 29.
-                let expr0_0: Type = F32;
-                let expr1_0 = constructor_imm(ctx, expr0_0, pattern4_0)?;
-                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                return Some(expr2_0);
-            }
-        }
-        &InstructionData::UnaryIeee64 {
-            opcode: ref pattern2_0,
-            imm: pattern2_1,
-        } => {
-            if let &Opcode::F64const = pattern2_0 {
-                let pattern4_0 = C::u64_from_ieee64(ctx, pattern2_1);
-                // Rule at src/isa/s390x/lower.isle line 35.
-                let expr0_0: Type = F64;
-                let expr1_0 = constructor_imm(ctx, expr0_0, pattern4_0)?;
-                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                return Some(expr2_0);
-            }
-        }
-        &InstructionData::Trap {
-            opcode: ref pattern2_0,
-            code: ref pattern2_1,
-        } => {
-            match pattern2_0 {
-                &Opcode::Trap => {
-                    // Rule at src/isa/s390x/lower.isle line 2139.
-                    let expr0_0 = constructor_trap_impl(ctx, pattern2_1)?;
-                    let expr1_0 = constructor_safepoint(ctx, &expr0_0)?;
-                    return Some(expr1_0);
-                }
-                &Opcode::ResumableTrap => {
-                    // Rule at src/isa/s390x/lower.isle line 2145.
-                    let expr0_0 = constructor_trap_impl(ctx, pattern2_1)?;
-                    let expr1_0 = constructor_safepoint(ctx, &expr0_0)?;
-                    return Some(expr1_0);
-                }
-                _ => {}
-            }
-        }
-        &InstructionData::StoreNoOffset {
-            opcode: ref pattern2_0,
-            args: ref pattern2_1,
-            flags: pattern2_2,
-        } => {
-            if let &Opcode::AtomicStore = pattern2_0 {
-                let (pattern4_0, pattern4_1) = C::unpack_value_array_2(ctx, pattern2_1);
-                let pattern5_0 = C::value_type(ctx, pattern4_0);
-                if pattern5_0 == I8 {
-                    // Rule at src/isa/s390x/lower.isle line 1863.
-                    let expr0_0 = C::zero_offset(ctx);
-                    let expr1_0 =
-                        constructor_istore8_impl(ctx, pattern2_2, pattern4_0, pattern4_1, expr0_0)?;
-                    let expr2_0 = constructor_atomic_store_impl(ctx, &expr1_0)?;
-                    return Some(expr2_0);
-                }
-                if pattern5_0 == I16 {
-                    // Rule at src/isa/s390x/lower.isle line 1867.
-                    let expr0_0 = C::zero_offset(ctx);
-                    let expr1_0 = constructor_istore16_impl(
-                        ctx, pattern2_2, pattern4_0, pattern4_1, expr0_0,
-                    )?;
-                    let expr2_0 = constructor_atomic_store_impl(ctx, &expr1_0)?;
-                    return Some(expr2_0);
-                }
-                if pattern5_0 == I32 {
-                    // Rule at src/isa/s390x/lower.isle line 1871.
-                    let expr0_0 = C::zero_offset(ctx);
-                    let expr1_0 = constructor_istore32_impl(
-                        ctx, pattern2_2, pattern4_0, pattern4_1, expr0_0,
-                    )?;
-                    let expr2_0 = constructor_atomic_store_impl(ctx, &expr1_0)?;
-                    return Some(expr2_0);
-                }
-                if pattern5_0 == I64 {
-                    // Rule at src/isa/s390x/lower.isle line 1875.
-                    let expr0_0 = C::zero_offset(ctx);
-                    let expr1_0 = constructor_istore64_impl(
-                        ctx, pattern2_2, pattern4_0, pattern4_1, expr0_0,
-                    )?;
-                    let expr2_0 = constructor_atomic_store_impl(ctx, &expr1_0)?;
-                    return Some(expr2_0);
-                }
-            }
-        }
-        &InstructionData::Store {
-            opcode: ref pattern2_0,
-            args: ref pattern2_1,
-            flags: pattern2_2,
-            offset: pattern2_3,
-        } => {
-            match pattern2_0 {
-                &Opcode::Store => {
-                    let (pattern4_0, pattern4_1) = C::unpack_value_array_2(ctx, pattern2_1);
-                    let pattern5_0 = C::value_type(ctx, pattern4_0);
-                    if pattern5_0 == I8 {
-                        // Rule at src/isa/s390x/lower.isle line 1354.
-                        let expr0_0 = constructor_istore8_impl(
-                            ctx, pattern2_2, pattern4_0, pattern4_1, pattern2_3,
-                        )?;
-                        let expr1_0 = constructor_side_effect(ctx, &expr0_0)?;
-                        return Some(expr1_0);
-                    }
-                    if pattern5_0 == I16 {
-                        // Rule at src/isa/s390x/lower.isle line 1358.
-                        let expr0_0 = constructor_istore16_impl(
-                            ctx, pattern2_2, pattern4_0, pattern4_1, pattern2_3,
-                        )?;
-                        let expr1_0 = constructor_side_effect(ctx, &expr0_0)?;
-                        return Some(expr1_0);
-                    }
-                    if pattern5_0 == I32 {
-                        // Rule at src/isa/s390x/lower.isle line 1362.
-                        let expr0_0 = constructor_istore32_impl(
-                            ctx, pattern2_2, pattern4_0, pattern4_1, pattern2_3,
-                        )?;
-                        let expr1_0 = constructor_side_effect(ctx, &expr0_0)?;
-                        return Some(expr1_0);
-                    }
-                    if pattern5_0 == I64 {
-                        // Rule at src/isa/s390x/lower.isle line 1366.
-                        let expr0_0 = constructor_istore64_impl(
-                            ctx, pattern2_2, pattern4_0, pattern4_1, pattern2_3,
-                        )?;
-                        let expr1_0 = constructor_side_effect(ctx, &expr0_0)?;
-                        return Some(expr1_0);
-                    }
-                    if pattern5_0 == R64 {
-                        // Rule at src/isa/s390x/lower.isle line 1370.
-                        let expr0_0 = constructor_istore64_impl(
-                            ctx, pattern2_2, pattern4_0, pattern4_1, pattern2_3,
-                        )?;
-                        let expr1_0 = constructor_side_effect(ctx, &expr0_0)?;
-                        return Some(expr1_0);
-                    }
-                    if pattern5_0 == F32 {
-                        if let Some(()) = C::bigendian(ctx, pattern2_2) {
-                            // Rule at src/isa/s390x/lower.isle line 1374.
-                            let expr0_0 = C::put_in_reg(ctx, pattern4_0);
-                            let expr1_0 =
-                                constructor_lower_address(ctx, pattern2_2, pattern4_1, pattern2_3)?;
-                            let expr2_0 = constructor_fpu_store32(ctx, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_side_effect(ctx, &expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        if let Some(()) = C::vxrs_ext2_enabled(ctx, pattern5_0) {
-                            if let Some(()) = C::littleendian(ctx, pattern2_2) {
-                                // Rule at src/isa/s390x/lower.isle line 1380.
-                                let expr0_0 = C::put_in_reg(ctx, pattern4_0);
-                                let expr1_0 = constructor_lower_address(
-                                    ctx, pattern2_2, pattern4_1, pattern2_3,
-                                )?;
-                                let expr2_0 = constructor_fpu_storerev32(ctx, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_side_effect(ctx, &expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                        }
-                        if let Some(()) = C::vxrs_ext2_disabled(ctx, pattern5_0) {
-                            if let Some(()) = C::littleendian(ctx, pattern2_2) {
-                                // Rule at src/isa/s390x/lower.isle line 1386.
-                                let expr0_0: Type = I64;
-                                let expr1_0 = C::put_in_reg(ctx, pattern4_0);
-                                let expr2_0 = constructor_mov_from_fpr(ctx, expr1_0)?;
-                                let expr3_0: u8 = 32;
-                                let expr4_0 = constructor_lshr_imm(ctx, expr0_0, expr2_0, expr3_0)?;
-                                let expr5_0 = constructor_lower_address(
-                                    ctx, pattern2_2, pattern4_1, pattern2_3,
-                                )?;
-                                let expr6_0 = constructor_storerev32(ctx, expr4_0, &expr5_0)?;
-                                let expr7_0 = constructor_side_effect(ctx, &expr6_0)?;
-                                return Some(expr7_0);
-                            }
-                        }
-                    }
-                    if pattern5_0 == F64 {
-                        if let Some(()) = C::bigendian(ctx, pattern2_2) {
-                            // Rule at src/isa/s390x/lower.isle line 1392.
-                            let expr0_0 = C::put_in_reg(ctx, pattern4_0);
-                            let expr1_0 =
-                                constructor_lower_address(ctx, pattern2_2, pattern4_1, pattern2_3)?;
-                            let expr2_0 = constructor_fpu_store64(ctx, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_side_effect(ctx, &expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        if let Some(()) = C::vxrs_ext2_enabled(ctx, pattern5_0) {
-                            if let Some(()) = C::littleendian(ctx, pattern2_2) {
-                                // Rule at src/isa/s390x/lower.isle line 1398.
-                                let expr0_0 = C::put_in_reg(ctx, pattern4_0);
-                                let expr1_0 = constructor_lower_address(
-                                    ctx, pattern2_2, pattern4_1, pattern2_3,
-                                )?;
-                                let expr2_0 = constructor_fpu_storerev64(ctx, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_side_effect(ctx, &expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                        }
-                        if let Some(()) = C::vxrs_ext2_disabled(ctx, pattern5_0) {
-                            if let Some(()) = C::littleendian(ctx, pattern2_2) {
-                                // Rule at src/isa/s390x/lower.isle line 1404.
-                                let expr0_0 = C::put_in_reg(ctx, pattern4_0);
-                                let expr1_0 = constructor_mov_from_fpr(ctx, expr0_0)?;
-                                let expr2_0 = constructor_lower_address(
-                                    ctx, pattern2_2, pattern4_1, pattern2_3,
-                                )?;
-                                let expr3_0 = constructor_storerev64(ctx, expr1_0, &expr2_0)?;
-                                let expr4_0 = constructor_side_effect(ctx, &expr3_0)?;
-                                return Some(expr4_0);
-                            }
-                        }
-                    }
-                }
-                &Opcode::Istore8 => {
-                    let (pattern4_0, pattern4_1) = C::unpack_value_array_2(ctx, pattern2_1);
-                    // Rule at src/isa/s390x/lower.isle line 1413.
-                    let expr0_0 = constructor_istore8_impl(
-                        ctx, pattern2_2, pattern4_0, pattern4_1, pattern2_3,
-                    )?;
-                    let expr1_0 = constructor_side_effect(ctx, &expr0_0)?;
-                    return Some(expr1_0);
-                }
-                &Opcode::Istore16 => {
-                    let (pattern4_0, pattern4_1) = C::unpack_value_array_2(ctx, pattern2_1);
-                    // Rule at src/isa/s390x/lower.isle line 1431.
-                    let expr0_0 = constructor_istore16_impl(
-                        ctx, pattern2_2, pattern4_0, pattern4_1, pattern2_3,
-                    )?;
-                    let expr1_0 = constructor_side_effect(ctx, &expr0_0)?;
-                    return Some(expr1_0);
-                }
-                &Opcode::Istore32 => {
-                    let (pattern4_0, pattern4_1) = C::unpack_value_array_2(ctx, pattern2_1);
-                    // Rule at src/isa/s390x/lower.isle line 1457.
-                    let expr0_0 = constructor_istore32_impl(
-                        ctx, pattern2_2, pattern4_0, pattern4_1, pattern2_3,
-                    )?;
-                    let expr1_0 = constructor_side_effect(ctx, &expr0_0)?;
-                    return Some(expr1_0);
-                }
-                _ => {}
-            }
-        }
-        &InstructionData::Unary {
-            opcode: ref pattern2_0,
-            arg: pattern2_1,
-        } => {
-            match pattern2_0 {
-                &Opcode::Copy => {
-                    // Rule at src/isa/s390x/lower.isle line 53.
-                    let expr0_0 = constructor_output_value(ctx, pattern2_1)?;
-                    return Some(expr0_0);
-                }
-                &Opcode::Breduce => {
-                    // Rule at src/isa/s390x/lower.isle line 752.
-                    let expr0_0 = constructor_output_value(ctx, pattern2_1)?;
-                    return Some(expr0_0);
-                }
-                &Opcode::Ireduce => {
-                    // Rule at src/isa/s390x/lower.isle line 596.
-                    let expr0_0 = constructor_output_value(ctx, pattern2_1)?;
-                    return Some(expr0_0);
-                }
-                _ => {}
-            }
-        }
-        &InstructionData::IntCondTrap {
-            opcode: ref pattern2_0,
-            arg: pattern2_1,
-            cond: ref pattern2_2,
-            code: ref pattern2_3,
-        } => {
-            if let &Opcode::Trapif = pattern2_0 {
-                if let Some(pattern4_0) = C::def_inst(ctx, pattern2_1) {
-                    let pattern5_0 = C::inst_data(ctx, pattern4_0);
-                    if let &InstructionData::Binary {
-                        opcode: ref pattern6_0,
-                        args: ref pattern6_1,
-                    } = &pattern5_0
-                    {
-                        match pattern6_0 {
-                            &Opcode::Ifcmp => {
-                                let (pattern8_0, pattern8_1) =
-                                    C::unpack_value_array_2(ctx, pattern6_1);
-                                // Rule at src/isa/s390x/lower.isle line 2181.
-                                let expr0_0: bool = false;
-                                let expr1_0 = constructor_icmp_val(
-                                    ctx, expr0_0, pattern2_2, pattern8_0, pattern8_1,
-                                )?;
-                                let expr2_0 = constructor_trap_if_bool(ctx, &expr1_0, pattern2_3)?;
-                                let expr3_0 = constructor_safepoint(ctx, &expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            &Opcode::IaddIfcout => {
-                                let (pattern8_0, pattern8_1) =
-                                    C::unpack_value_array_2(ctx, pattern6_1);
-                                if let &IntCC::UnsignedGreaterThan = pattern2_2 {
-                                    // Rule at src/isa/s390x/lower.isle line 2206.
-                                    let expr0_0: u8 = 3;
-                                    let expr1_0 = C::mask_as_cond(ctx, expr0_0);
-                                    let expr2_0 =
-                                        constructor_trap_if_impl(ctx, &expr1_0, pattern2_3)?;
-                                    let expr3_0 = constructor_side_effect(ctx, &expr2_0)?;
-                                    return Some(expr3_0);
-                                }
-                            }
-                            _ => {}
-                        }
-                    }
-                }
-            }
-        }
-        &InstructionData::CondTrap {
-            opcode: ref pattern2_0,
-            arg: pattern2_1,
-            code: ref pattern2_2,
-        } => {
-            match pattern2_0 {
-                &Opcode::Trapz => {
-                    // Rule at src/isa/s390x/lower.isle line 2151.
-                    let expr0_0 = constructor_value_nonzero(ctx, pattern2_1)?;
-                    let expr1_0 = constructor_invert_bool(ctx, &expr0_0)?;
-                    let expr2_0 = constructor_trap_if_bool(ctx, &expr1_0, pattern2_2)?;
-                    let expr3_0 = constructor_safepoint(ctx, &expr2_0)?;
-                    return Some(expr3_0);
-                }
-                &Opcode::Trapnz => {
-                    // Rule at src/isa/s390x/lower.isle line 2157.
-                    let expr0_0 = constructor_value_nonzero(ctx, pattern2_1)?;
-                    let expr1_0 = constructor_trap_if_bool(ctx, &expr0_0, pattern2_2)?;
-                    let expr2_0 = constructor_safepoint(ctx, &expr1_0)?;
-                    return Some(expr2_0);
-                }
-                &Opcode::ResumableTrapnz => {
-                    // Rule at src/isa/s390x/lower.isle line 2163.
-                    let expr0_0 = constructor_value_nonzero(ctx, pattern2_1)?;
-                    let expr1_0 = constructor_trap_if_bool(ctx, &expr0_0, pattern2_2)?;
-                    let expr2_0 = constructor_safepoint(ctx, &expr1_0)?;
-                    return Some(expr2_0);
-                }
-                _ => {}
-            }
-        }
-        _ => {}
-    }
-    if let Some(pattern1_0) = C::first_result(ctx, pattern0_0) {
-        let pattern2_0 = C::value_type(ctx, pattern1_0);
-        if pattern2_0 == B1 {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            if let &InstructionData::Unary {
-                opcode: ref pattern5_0,
-                arg: pattern5_1,
-            } = &pattern4_0
-            {
-                match pattern5_0 {
-                    &Opcode::IsNull => {
-                        let pattern7_0 = C::value_type(ctx, pattern5_1);
-                        if pattern7_0 == R64 {
-                            // Rule at src/isa/s390x/lower.isle line 2017.
-                            let expr0_0: Type = B1;
-                            let expr1_0: Type = I64;
-                            let expr2_0 = C::put_in_reg(ctx, pattern5_1);
-                            let expr3_0: i16 = 0;
-                            let expr4_0 = constructor_icmps_simm16(ctx, expr1_0, expr2_0, expr3_0)?;
-                            let expr5_0 = IntCC::Equal;
-                            let expr6_0 = C::intcc_as_cond(ctx, &expr5_0);
-                            let expr7_0 = constructor_bool(ctx, &expr4_0, &expr6_0)?;
-                            let expr8_0 = constructor_lower_bool(ctx, expr0_0, &expr7_0)?;
-                            let expr9_0 = constructor_output_reg(ctx, expr8_0)?;
-                            return Some(expr9_0);
-                        }
-                    }
-                    &Opcode::IsInvalid => {
-                        let pattern7_0 = C::value_type(ctx, pattern5_1);
-                        if pattern7_0 == R64 {
-                            // Rule at src/isa/s390x/lower.isle line 2023.
-                            let expr0_0: Type = B1;
-                            let expr1_0: Type = I64;
-                            let expr2_0 = C::put_in_reg(ctx, pattern5_1);
-                            let expr3_0: i16 = -1;
-                            let expr4_0 = constructor_icmps_simm16(ctx, expr1_0, expr2_0, expr3_0)?;
-                            let expr5_0 = IntCC::Equal;
-                            let expr6_0 = C::intcc_as_cond(ctx, &expr5_0);
-                            let expr7_0 = constructor_bool(ctx, &expr4_0, &expr6_0)?;
-                            let expr8_0 = constructor_lower_bool(ctx, expr0_0, &expr7_0)?;
-                            let expr9_0 = constructor_output_reg(ctx, expr8_0)?;
-                            return Some(expr9_0);
-                        }
-                    }
-                    _ => {}
-                }
-            }
-        }
-        if pattern2_0 == I8 {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            match &pattern4_0 {
-                &InstructionData::Unary {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                } => {
-                    if let &Opcode::Popcnt = pattern5_0 {
-                        // Rule at src/isa/s390x/lower.isle line 884.
-                        let expr0_0 = C::put_in_reg(ctx, pattern5_1);
-                        let expr1_0 = constructor_popcnt_byte(ctx, expr0_0)?;
-                        let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                        return Some(expr2_0);
-                    }
-                }
-                &InstructionData::LoadNoOffset {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                    flags: pattern5_2,
-                } => {
-                    if let &Opcode::AtomicLoad = pattern5_0 {
-                        // Rule at src/isa/s390x/lower.isle line 1826.
-                        let expr0_0: Type = I8;
-                        let expr1_0 = C::zero_offset(ctx);
-                        let expr2_0 =
-                            constructor_lower_address(ctx, pattern5_2, pattern5_1, expr1_0)?;
-                        let expr3_0 = constructor_zext32_mem(ctx, expr0_0, &expr2_0)?;
-                        let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                        return Some(expr4_0);
-                    }
-                }
-                &InstructionData::Load {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                    flags: pattern5_2,
-                    offset: pattern5_3,
-                } => {
-                    if let &Opcode::Load = pattern5_0 {
-                        // Rule at src/isa/s390x/lower.isle line 1182.
-                        let expr0_0: Type = I8;
-                        let expr1_0 =
-                            constructor_lower_address(ctx, pattern5_2, pattern5_1, pattern5_3)?;
-                        let expr2_0 = constructor_zext32_mem(ctx, expr0_0, &expr1_0)?;
-                        let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                        return Some(expr3_0);
-                    }
-                }
-                _ => {}
-            }
-        }
-        if pattern2_0 == I16 {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            match &pattern4_0 {
-                &InstructionData::LoadNoOffset {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                    flags: pattern5_2,
-                } => {
-                    if let &Opcode::AtomicLoad = pattern5_0 {
-                        if let Some(()) = C::littleendian(ctx, pattern5_2) {
-                            // Rule at src/isa/s390x/lower.isle line 1834.
-                            let expr0_0 = C::zero_offset(ctx);
-                            let expr1_0 =
-                                constructor_lower_address(ctx, pattern5_2, pattern5_1, expr0_0)?;
-                            let expr2_0 = constructor_loadrev16(ctx, &expr1_0)?;
-                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        if let Some(()) = C::bigendian(ctx, pattern5_2) {
-                            // Rule at src/isa/s390x/lower.isle line 1830.
-                            let expr0_0: Type = I16;
-                            let expr1_0 = C::zero_offset(ctx);
-                            let expr2_0 =
-                                constructor_lower_address(ctx, pattern5_2, pattern5_1, expr1_0)?;
-                            let expr3_0 = constructor_zext32_mem(ctx, expr0_0, &expr2_0)?;
-                            let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                            return Some(expr4_0);
-                        }
-                    }
-                }
-                &InstructionData::Load {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                    flags: pattern5_2,
-                    offset: pattern5_3,
-                } => {
-                    if let &Opcode::Load = pattern5_0 {
-                        if let Some(()) = C::littleendian(ctx, pattern5_2) {
-                            // Rule at src/isa/s390x/lower.isle line 1190.
-                            let expr0_0 =
-                                constructor_lower_address(ctx, pattern5_2, pattern5_1, pattern5_3)?;
-                            let expr1_0 = constructor_loadrev16(ctx, &expr0_0)?;
-                            let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                            return Some(expr2_0);
-                        }
-                        if let Some(()) = C::bigendian(ctx, pattern5_2) {
-                            // Rule at src/isa/s390x/lower.isle line 1186.
-                            let expr0_0: Type = I16;
-                            let expr1_0 =
-                                constructor_lower_address(ctx, pattern5_2, pattern5_1, pattern5_3)?;
-                            let expr2_0 = constructor_zext32_mem(ctx, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                    }
-                }
-                _ => {}
-            }
-        }
-        if pattern2_0 == I32 {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            match &pattern4_0 {
-                &InstructionData::Binary {
-                    opcode: ref pattern5_0,
-                    args: ref pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Umulhi => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/s390x/lower.isle line 252.
-                            let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_reg_zext64(ctx, pattern7_1)?;
-                            let expr2_0: Type = I64;
-                            let expr3_0 = constructor_mul_reg(ctx, expr2_0, expr0_0, expr1_0)?;
-                            let expr4_0: Type = I64;
-                            let expr5_0: u8 = 32;
-                            let expr6_0 = constructor_lshr_imm(ctx, expr4_0, expr3_0, expr5_0)?;
-                            let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
-                            return Some(expr7_0);
-                        }
-                        &Opcode::Smulhi => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/s390x/lower.isle line 274.
-                            let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_reg_sext64(ctx, pattern7_1)?;
-                            let expr2_0: Type = I64;
-                            let expr3_0 = constructor_mul_reg(ctx, expr2_0, expr0_0, expr1_0)?;
-                            let expr4_0: Type = I64;
-                            let expr5_0: u8 = 32;
-                            let expr6_0 = constructor_ashr_imm(ctx, expr4_0, expr3_0, expr5_0)?;
-                            let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
-                            return Some(expr7_0);
-                        }
-                        _ => {}
-                    }
-                }
-                &InstructionData::Unary {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                } => {
-                    if let &Opcode::Bitcast = pattern5_0 {
-                        let pattern7_0 = C::value_type(ctx, pattern5_1);
-                        if pattern7_0 == F32 {
-                            // Rule at src/isa/s390x/lower.isle line 1145.
-                            let expr0_0: Type = I64;
-                            let expr1_0 = C::put_in_reg(ctx, pattern5_1);
-                            let expr2_0 = constructor_mov_from_fpr(ctx, expr1_0)?;
-                            let expr3_0: u8 = 32;
-                            let expr4_0 = constructor_lshr_imm(ctx, expr0_0, expr2_0, expr3_0)?;
-                            let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
-                            return Some(expr5_0);
-                        }
-                    }
-                }
-                &InstructionData::LoadNoOffset {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                    flags: pattern5_2,
-                } => {
-                    if let &Opcode::AtomicLoad = pattern5_0 {
-                        if let Some(()) = C::littleendian(ctx, pattern5_2) {
-                            // Rule at src/isa/s390x/lower.isle line 1842.
-                            let expr0_0 = C::zero_offset(ctx);
-                            let expr1_0 =
-                                constructor_lower_address(ctx, pattern5_2, pattern5_1, expr0_0)?;
-                            let expr2_0 = constructor_loadrev32(ctx, &expr1_0)?;
-                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        if let Some(()) = C::bigendian(ctx, pattern5_2) {
-                            // Rule at src/isa/s390x/lower.isle line 1838.
-                            let expr0_0 = C::zero_offset(ctx);
-                            let expr1_0 =
-                                constructor_lower_address(ctx, pattern5_2, pattern5_1, expr0_0)?;
-                            let expr2_0 = constructor_load32(ctx, &expr1_0)?;
-                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                    }
-                }
-                &InstructionData::Load {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                    flags: pattern5_2,
-                    offset: pattern5_3,
-                } => {
-                    if let &Opcode::Load = pattern5_0 {
-                        if let Some(()) = C::littleendian(ctx, pattern5_2) {
-                            // Rule at src/isa/s390x/lower.isle line 1198.
-                            let expr0_0 =
-                                constructor_lower_address(ctx, pattern5_2, pattern5_1, pattern5_3)?;
-                            let expr1_0 = constructor_loadrev32(ctx, &expr0_0)?;
-                            let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                            return Some(expr2_0);
-                        }
-                        if let Some(()) = C::bigendian(ctx, pattern5_2) {
-                            // Rule at src/isa/s390x/lower.isle line 1194.
-                            let expr0_0 =
-                                constructor_lower_address(ctx, pattern5_2, pattern5_1, pattern5_3)?;
-                            let expr1_0 = constructor_load32(ctx, &expr0_0)?;
-                            let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                            return Some(expr2_0);
-                        }
-                    }
-                }
-                _ => {}
-            }
-        }
-        if pattern2_0 == I64 {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            match &pattern4_0 {
-                &InstructionData::Binary {
-                    opcode: ref pattern5_0,
-                    args: ref pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Umulhi => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/s390x/lower.isle line 259.
-                            let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                            let expr1_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr2_0 = constructor_umul_wide(ctx, expr0_0, expr1_0)?;
-                            let expr3_0: Type = I64;
-                            let expr4_0 = constructor_regpair_hi(ctx, &expr2_0)?;
-                            let expr5_0 = constructor_copy_reg(ctx, expr3_0, expr4_0)?;
-                            let expr6_0 = constructor_output_reg(ctx, expr5_0)?;
-                            return Some(expr6_0);
-                        }
-                        &Opcode::Smulhi => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/s390x/lower.isle line 281.
-                            let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                            let expr1_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr2_0 = constructor_smul_wide(ctx, expr0_0, expr1_0)?;
-                            let expr3_0: Type = I64;
-                            let expr4_0 = constructor_regpair_hi(ctx, &expr2_0)?;
-                            let expr5_0 = constructor_copy_reg(ctx, expr3_0, expr4_0)?;
-                            let expr6_0 = constructor_output_reg(ctx, expr5_0)?;
-                            return Some(expr6_0);
-                        }
-                        _ => {}
-                    }
-                }
-                &InstructionData::Unary {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                } => {
-                    if let &Opcode::Bitcast = pattern5_0 {
-                        let pattern7_0 = C::value_type(ctx, pattern5_1);
-                        if pattern7_0 == F64 {
-                            // Rule at src/isa/s390x/lower.isle line 1135.
-                            let expr0_0 = C::put_in_reg(ctx, pattern5_1);
-                            let expr1_0 = constructor_mov_from_fpr(ctx, expr0_0)?;
-                            let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                            return Some(expr2_0);
-                        }
-                    }
-                }
-                &InstructionData::LoadNoOffset {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                    flags: pattern5_2,
-                } => {
-                    if let &Opcode::AtomicLoad = pattern5_0 {
-                        if let Some(()) = C::littleendian(ctx, pattern5_2) {
-                            // Rule at src/isa/s390x/lower.isle line 1850.
-                            let expr0_0 = C::zero_offset(ctx);
-                            let expr1_0 =
-                                constructor_lower_address(ctx, pattern5_2, pattern5_1, expr0_0)?;
-                            let expr2_0 = constructor_loadrev64(ctx, &expr1_0)?;
-                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        if let Some(()) = C::bigendian(ctx, pattern5_2) {
-                            // Rule at src/isa/s390x/lower.isle line 1846.
-                            let expr0_0 = C::zero_offset(ctx);
-                            let expr1_0 =
-                                constructor_lower_address(ctx, pattern5_2, pattern5_1, expr0_0)?;
-                            let expr2_0 = constructor_load64(ctx, &expr1_0)?;
-                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                    }
-                }
-                &InstructionData::Load {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                    flags: pattern5_2,
-                    offset: pattern5_3,
-                } => {
-                    if let &Opcode::Load = pattern5_0 {
-                        if let Some(()) = C::littleendian(ctx, pattern5_2) {
-                            // Rule at src/isa/s390x/lower.isle line 1206.
-                            let expr0_0 =
-                                constructor_lower_address(ctx, pattern5_2, pattern5_1, pattern5_3)?;
-                            let expr1_0 = constructor_loadrev64(ctx, &expr0_0)?;
-                            let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                            return Some(expr2_0);
-                        }
-                        if let Some(()) = C::bigendian(ctx, pattern5_2) {
-                            // Rule at src/isa/s390x/lower.isle line 1202.
-                            let expr0_0 =
-                                constructor_lower_address(ctx, pattern5_2, pattern5_1, pattern5_3)?;
-                            let expr1_0 = constructor_load64(ctx, &expr0_0)?;
-                            let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                            return Some(expr2_0);
-                        }
-                    }
-                }
-                _ => {}
-            }
-        }
-        if pattern2_0 == R64 {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            if let &InstructionData::Load {
-                opcode: ref pattern5_0,
-                arg: pattern5_1,
-                flags: pattern5_2,
-                offset: pattern5_3,
-            } = &pattern4_0
-            {
-                if let &Opcode::Load = pattern5_0 {
-                    if let Some(()) = C::littleendian(ctx, pattern5_2) {
-                        // Rule at src/isa/s390x/lower.isle line 1214.
-                        let expr0_0 =
-                            constructor_lower_address(ctx, pattern5_2, pattern5_1, pattern5_3)?;
-                        let expr1_0 = constructor_loadrev64(ctx, &expr0_0)?;
-                        let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                        return Some(expr2_0);
-                    }
-                    if let Some(()) = C::bigendian(ctx, pattern5_2) {
-                        // Rule at src/isa/s390x/lower.isle line 1210.
-                        let expr0_0 =
-                            constructor_lower_address(ctx, pattern5_2, pattern5_1, pattern5_3)?;
-                        let expr1_0 = constructor_load64(ctx, &expr0_0)?;
-                        let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                        return Some(expr2_0);
-                    }
-                }
-            }
-        }
-        if pattern2_0 == F32 {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            match &pattern4_0 {
-                &InstructionData::Unary {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                } => {
-                    if let &Opcode::Bitcast = pattern5_0 {
-                        let pattern7_0 = C::value_type(ctx, pattern5_1);
-                        if pattern7_0 == I32 {
-                            // Rule at src/isa/s390x/lower.isle line 1140.
-                            let expr0_0: Type = I64;
-                            let expr1_0 = C::put_in_reg(ctx, pattern5_1);
-                            let expr2_0: u8 = 32;
-                            let expr3_0 = constructor_lshl_imm(ctx, expr0_0, expr1_0, expr2_0)?;
-                            let expr4_0 = constructor_mov_to_fpr(ctx, expr3_0)?;
-                            let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
-                            return Some(expr5_0);
-                        }
-                    }
-                }
-                &InstructionData::Load {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                    flags: pattern5_2,
-                    offset: pattern5_3,
-                } => {
-                    if let &Opcode::Load = pattern5_0 {
-                        if let Some(()) = C::bigendian(ctx, pattern5_2) {
-                            // Rule at src/isa/s390x/lower.isle line 1218.
-                            let expr0_0 =
-                                constructor_lower_address(ctx, pattern5_2, pattern5_1, pattern5_3)?;
-                            let expr1_0 = constructor_fpu_load32(ctx, &expr0_0)?;
-                            let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                            return Some(expr2_0);
-                        }
-                    }
-                }
-                _ => {}
-            }
-        }
-        if pattern2_0 == F64 {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            match &pattern4_0 {
-                &InstructionData::Unary {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                } => {
-                    if let &Opcode::Bitcast = pattern5_0 {
-                        let pattern7_0 = C::value_type(ctx, pattern5_1);
-                        if pattern7_0 == I64 {
-                            // Rule at src/isa/s390x/lower.isle line 1131.
-                            let expr0_0 = C::put_in_reg(ctx, pattern5_1);
-                            let expr1_0 = constructor_mov_to_fpr(ctx, expr0_0)?;
-                            let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                            return Some(expr2_0);
-                        }
-                    }
-                }
-                &InstructionData::Load {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                    flags: pattern5_2,
-                    offset: pattern5_3,
-                } => {
-                    if let &Opcode::Load = pattern5_0 {
-                        if let Some(()) = C::bigendian(ctx, pattern5_2) {
-                            // Rule at src/isa/s390x/lower.isle line 1233.
-                            let expr0_0 =
-                                constructor_lower_address(ctx, pattern5_2, pattern5_1, pattern5_3)?;
-                            let expr1_0 = constructor_fpu_load64(ctx, &expr0_0)?;
-                            let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                            return Some(expr2_0);
-                        }
-                    }
-                }
-                _ => {}
-            }
-        }
-        let pattern3_0 = C::inst_data(ctx, pattern0_0);
-        match &pattern3_0 {
-            &InstructionData::NullAry {
-                opcode: ref pattern4_0,
-            } => {
-                if let &Opcode::Null = pattern4_0 {
-                    // Rule at src/isa/s390x/lower.isle line 41.
-                    let expr0_0: u64 = 0;
-                    let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
-                    let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                    return Some(expr2_0);
-                }
-            }
-            &InstructionData::UnaryImm {
-                opcode: ref pattern4_0,
-                imm: pattern4_1,
-            } => {
-                if let &Opcode::Iconst = pattern4_0 {
-                    let pattern6_0 = C::u64_from_imm64(ctx, pattern4_1);
-                    // Rule at src/isa/s390x/lower.isle line 15.
-                    let expr0_0 = constructor_imm(ctx, pattern2_0, pattern6_0)?;
-                    let expr1_0 = constructor_output_reg(ctx, expr0_0)?;
-                    return Some(expr1_0);
-                }
-            }
-            &InstructionData::StackLoad {
-                opcode: ref pattern4_0,
-                stack_slot: pattern4_1,
-                offset: pattern4_2,
-            } => {
-                if let &Opcode::StackAddr = pattern4_0 {
-                    // Rule at src/isa/s390x/lower.isle line 1152.
-                    let expr0_0 =
-                        constructor_stack_addr_impl(ctx, pattern2_0, pattern4_1, pattern4_2)?;
-                    let expr1_0 = constructor_output_reg(ctx, expr0_0)?;
-                    return Some(expr1_0);
-                }
-            }
-            &InstructionData::UnaryBool {
-                opcode: ref pattern4_0,
-                imm: pattern4_1,
-            } => {
-                if let &Opcode::Bconst = pattern4_0 {
-                    if pattern4_1 == true {
-                        // Rule at src/isa/s390x/lower.isle line 23.
-                        let expr0_0: u64 = 1;
-                        let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
-                        let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                        return Some(expr2_0);
-                    }
-                    if pattern4_1 == false {
-                        // Rule at src/isa/s390x/lower.isle line 21.
-                        let expr0_0: u64 = 0;
-                        let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
-                        let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                        return Some(expr2_0);
-                    }
-                }
-            }
-            &InstructionData::Binary {
-                opcode: ref pattern4_0,
-                args: ref pattern4_1,
-            } => {
-                match pattern4_0 {
-                    &Opcode::Fadd => {
-                        let (pattern6_0, pattern6_1) = C::unpack_value_array_2(ctx, pattern4_1);
-                        // Rule at src/isa/s390x/lower.isle line 920.
-                        let expr0_0 = C::put_in_reg(ctx, pattern6_0);
-                        let expr1_0 = C::put_in_reg(ctx, pattern6_1);
-                        let expr2_0 = constructor_fadd_reg(ctx, pattern2_0, expr0_0, expr1_0)?;
-                        let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                        return Some(expr3_0);
-                    }
-                    &Opcode::Fsub => {
-                        let (pattern6_0, pattern6_1) = C::unpack_value_array_2(ctx, pattern4_1);
-                        // Rule at src/isa/s390x/lower.isle line 927.
-                        let expr0_0 = C::put_in_reg(ctx, pattern6_0);
-                        let expr1_0 = C::put_in_reg(ctx, pattern6_1);
-                        let expr2_0 = constructor_fsub_reg(ctx, pattern2_0, expr0_0, expr1_0)?;
-                        let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                        return Some(expr3_0);
-                    }
-                    &Opcode::Fmul => {
-                        let (pattern6_0, pattern6_1) = C::unpack_value_array_2(ctx, pattern4_1);
-                        // Rule at src/isa/s390x/lower.isle line 934.
-                        let expr0_0 = C::put_in_reg(ctx, pattern6_0);
-                        let expr1_0 = C::put_in_reg(ctx, pattern6_1);
-                        let expr2_0 = constructor_fmul_reg(ctx, pattern2_0, expr0_0, expr1_0)?;
-                        let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                        return Some(expr3_0);
-                    }
-                    &Opcode::Fdiv => {
-                        let (pattern6_0, pattern6_1) = C::unpack_value_array_2(ctx, pattern4_1);
-                        // Rule at src/isa/s390x/lower.isle line 941.
-                        let expr0_0 = C::put_in_reg(ctx, pattern6_0);
-                        let expr1_0 = C::put_in_reg(ctx, pattern6_1);
-                        let expr2_0 = constructor_fdiv_reg(ctx, pattern2_0, expr0_0, expr1_0)?;
-                        let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                        return Some(expr3_0);
-                    }
-                    &Opcode::Fcopysign => {
-                        let (pattern6_0, pattern6_1) = C::unpack_value_array_2(ctx, pattern4_1);
-                        // Rule at src/isa/s390x/lower.isle line 962.
-                        let expr0_0 = C::put_in_reg(ctx, pattern6_0);
-                        let expr1_0 = C::put_in_reg(ctx, pattern6_1);
-                        let expr2_0 = constructor_fpu_copysign(ctx, pattern2_0, expr0_0, expr1_0)?;
-                        let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                        return Some(expr3_0);
-                    }
-                    &Opcode::Fmin => {
-                        let (pattern6_0, pattern6_1) = C::unpack_value_array_2(ctx, pattern4_1);
-                        // Rule at src/isa/s390x/lower.isle line 948.
-                        let expr0_0 = C::put_in_reg(ctx, pattern6_0);
-                        let expr1_0 = C::put_in_reg(ctx, pattern6_1);
-                        let expr2_0 = constructor_fmin_reg(ctx, pattern2_0, expr0_0, expr1_0)?;
-                        let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                        return Some(expr3_0);
-                    }
-                    &Opcode::Fmax => {
-                        let (pattern6_0, pattern6_1) = C::unpack_value_array_2(ctx, pattern4_1);
-                        // Rule at src/isa/s390x/lower.isle line 955.
-                        let expr0_0 = C::put_in_reg(ctx, pattern6_0);
-                        let expr1_0 = C::put_in_reg(ctx, pattern6_1);
-                        let expr2_0 = constructor_fmax_reg(ctx, pattern2_0, expr0_0, expr1_0)?;
-                        let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                        return Some(expr3_0);
-                    }
-                    _ => {}
-                }
-            }
-            &InstructionData::FloatCompare {
-                opcode: ref pattern4_0,
-                args: ref pattern4_1,
-                cond: ref pattern4_2,
-            } => {
-                if let &Opcode::Fcmp = pattern4_0 {
-                    let (pattern6_0, pattern6_1) = C::unpack_value_array_2(ctx, pattern4_1);
-                    // Rule at src/isa/s390x/lower.isle line 2004.
-                    let expr0_0 = constructor_fcmp_val(ctx, pattern4_2, pattern6_0, pattern6_1)?;
-                    let expr1_0 = constructor_lower_bool(ctx, pattern2_0, &expr0_0)?;
-                    let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                    return Some(expr2_0);
-                }
-            }
-            &InstructionData::IntCompare {
-                opcode: ref pattern4_0,
-                args: ref pattern4_1,
-                cond: ref pattern4_2,
-            } => {
-                if let &Opcode::Icmp = pattern4_0 {
-                    let (pattern6_0, pattern6_1) = C::unpack_value_array_2(ctx, pattern4_1);
-                    // Rule at src/isa/s390x/lower.isle line 1915.
-                    let expr0_0: bool = true;
-                    let expr1_0 =
-                        constructor_icmp_val(ctx, expr0_0, pattern4_2, pattern6_0, pattern6_1)?;
-                    let expr2_0 = constructor_lower_bool(ctx, pattern2_0, &expr1_0)?;
-                    let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                    return Some(expr3_0);
-                }
-            }
-            &InstructionData::Ternary {
-                opcode: ref pattern4_0,
-                args: ref pattern4_1,
-            } => {
-                match pattern4_0 {
-                    &Opcode::Select => {
-                        let (pattern6_0, pattern6_1, pattern6_2) =
-                            C::unpack_value_array_3(ctx, pattern4_1);
-                        // Rule at src/isa/s390x/lower.isle line 2046.
-                        let expr0_0 = constructor_value_nonzero(ctx, pattern6_0)?;
-                        let expr1_0 = C::put_in_reg(ctx, pattern6_1);
-                        let expr2_0 = C::put_in_reg(ctx, pattern6_2);
-                        let expr3_0 = constructor_select_bool_reg(
-                            ctx, pattern2_0, &expr0_0, expr1_0, expr2_0,
-                        )?;
-                        let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                        return Some(expr4_0);
-                    }
-                    &Opcode::Fma => {
-                        let (pattern6_0, pattern6_1, pattern6_2) =
-                            C::unpack_value_array_3(ctx, pattern4_1);
-                        // Rule at src/isa/s390x/lower.isle line 969.
-                        let expr0_0 = C::put_in_reg(ctx, pattern6_0);
-                        let expr1_0 = C::put_in_reg(ctx, pattern6_1);
-                        let expr2_0 = C::put_in_reg(ctx, pattern6_2);
-                        let expr3_0 =
-                            constructor_fma_reg(ctx, pattern2_0, expr0_0, expr1_0, expr2_0)?;
-                        let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                        return Some(expr4_0);
-                    }
-                    _ => {}
-                }
-            }
-            &InstructionData::IntSelect {
-                opcode: ref pattern4_0,
-                args: ref pattern4_1,
-                cond: ref pattern4_2,
-            } => {
-                if let &Opcode::SelectifSpectreGuard = pattern4_0 {
-                    let (pattern6_0, pattern6_1, pattern6_2) =
-                        C::unpack_value_array_3(ctx, pattern4_1);
-                    if let Some(pattern7_0) = C::def_inst(ctx, pattern6_0) {
-                        let pattern8_0 = C::inst_data(ctx, pattern7_0);
-                        if let &InstructionData::Binary {
-                            opcode: ref pattern9_0,
-                            args: ref pattern9_1,
-                        } = &pattern8_0
-                        {
-                            if let &Opcode::Ifcmp = pattern9_0 {
-                                let (pattern11_0, pattern11_1) =
-                                    C::unpack_value_array_2(ctx, pattern9_1);
-                                // Rule at src/isa/s390x/lower.isle line 2058.
-                                let expr0_0: bool = false;
-                                let expr1_0 = constructor_icmp_val(
-                                    ctx,
-                                    expr0_0,
-                                    pattern4_2,
-                                    pattern11_0,
-                                    pattern11_1,
-                                )?;
-                                let expr2_0 = C::put_in_reg(ctx, pattern6_1);
-                                let expr3_0 = C::put_in_reg(ctx, pattern6_2);
-                                let expr4_0 = constructor_select_bool_reg(
-                                    ctx, pattern2_0, &expr1_0, expr2_0, expr3_0,
-                                )?;
-                                let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
-                                return Some(expr5_0);
-                            }
-                        }
-                    }
-                }
-            }
-            &InstructionData::Unary {
-                opcode: ref pattern4_0,
-                arg: pattern4_1,
-            } => {
-                match pattern4_0 {
-                    &Opcode::Sqrt => {
-                        // Rule at src/isa/s390x/lower.isle line 976.
-                        let expr0_0 = C::put_in_reg(ctx, pattern4_1);
-                        let expr1_0 = constructor_sqrt_reg(ctx, pattern2_0, expr0_0)?;
-                        let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                        return Some(expr2_0);
-                    }
-                    &Opcode::Fneg => {
-                        // Rule at src/isa/s390x/lower.isle line 983.
-                        let expr0_0 = C::put_in_reg(ctx, pattern4_1);
-                        let expr1_0 = constructor_fneg_reg(ctx, pattern2_0, expr0_0)?;
-                        let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                        return Some(expr2_0);
-                    }
-                    &Opcode::Fabs => {
-                        // Rule at src/isa/s390x/lower.isle line 990.
-                        let expr0_0 = C::put_in_reg(ctx, pattern4_1);
-                        let expr1_0 = constructor_fabs_reg(ctx, pattern2_0, expr0_0)?;
-                        let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                        return Some(expr2_0);
-                    }
-                    &Opcode::Ceil => {
-                        // Rule at src/isa/s390x/lower.isle line 997.
-                        let expr0_0 = C::put_in_reg(ctx, pattern4_1);
-                        let expr1_0 = constructor_ceil_reg(ctx, pattern2_0, expr0_0)?;
-                        let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                        return Some(expr2_0);
-                    }
-                    &Opcode::Floor => {
-                        // Rule at src/isa/s390x/lower.isle line 1004.
-                        let expr0_0 = C::put_in_reg(ctx, pattern4_1);
-                        let expr1_0 = constructor_floor_reg(ctx, pattern2_0, expr0_0)?;
-                        let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                        return Some(expr2_0);
-                    }
-                    &Opcode::Trunc => {
-                        // Rule at src/isa/s390x/lower.isle line 1011.
-                        let expr0_0 = C::put_in_reg(ctx, pattern4_1);
-                        let expr1_0 = constructor_trunc_reg(ctx, pattern2_0, expr0_0)?;
-                        let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                        return Some(expr2_0);
-                    }
-                    &Opcode::Nearest => {
-                        // Rule at src/isa/s390x/lower.isle line 1018.
-                        let expr0_0 = C::put_in_reg(ctx, pattern4_1);
-                        let expr1_0 = constructor_nearest_reg(ctx, pattern2_0, expr0_0)?;
-                        let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                        return Some(expr2_0);
-                    }
-                    &Opcode::Bextend => {
-                        // Rule at src/isa/s390x/lower.isle line 760.
-                        let expr0_0 = constructor_cast_bool(ctx, pattern2_0, pattern4_1)?;
-                        let expr1_0 = constructor_output_reg(ctx, expr0_0)?;
-                        return Some(expr1_0);
-                    }
-                    &Opcode::Bmask => {
-                        // Rule at src/isa/s390x/lower.isle line 762.
-                        let expr0_0 = constructor_cast_bool(ctx, pattern2_0, pattern4_1)?;
-                        let expr1_0 = constructor_output_reg(ctx, expr0_0)?;
-                        return Some(expr1_0);
-                    }
-                    &Opcode::Fpromote => {
-                        let pattern6_0 = C::value_type(ctx, pattern4_1);
-                        // Rule at src/isa/s390x/lower.isle line 1025.
-                        let expr0_0 = C::put_in_reg(ctx, pattern4_1);
-                        let expr1_0 =
-                            constructor_fpromote_reg(ctx, pattern2_0, pattern6_0, expr0_0)?;
-                        let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                        return Some(expr2_0);
-                    }
-                    &Opcode::Fdemote => {
-                        let pattern6_0 = C::value_type(ctx, pattern4_1);
-                        // Rule at src/isa/s390x/lower.isle line 1032.
-                        let expr0_0 = C::put_in_reg(ctx, pattern4_1);
-                        let expr1_0 =
-                            constructor_fdemote_reg(ctx, pattern2_0, pattern6_0, expr0_0)?;
-                        let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                        return Some(expr2_0);
-                    }
-                    &Opcode::FcvtFromUint => {
-                        let pattern6_0 = C::value_type(ctx, pattern4_1);
-                        // Rule at src/isa/s390x/lower.isle line 1039.
-                        let expr0_0 = constructor_ty_ext32(ctx, pattern6_0)?;
-                        let expr1_0 = constructor_put_in_reg_zext32(ctx, pattern4_1)?;
-                        let expr2_0 =
-                            constructor_fcvt_from_uint_reg(ctx, pattern2_0, expr0_0, expr1_0)?;
-                        let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                        return Some(expr3_0);
-                    }
-                    &Opcode::FcvtFromSint => {
-                        let pattern6_0 = C::value_type(ctx, pattern4_1);
-                        // Rule at src/isa/s390x/lower.isle line 1047.
-                        let expr0_0 = constructor_ty_ext32(ctx, pattern6_0)?;
-                        let expr1_0 = constructor_put_in_reg_sext32(ctx, pattern4_1)?;
-                        let expr2_0 =
-                            constructor_fcvt_from_sint_reg(ctx, pattern2_0, expr0_0, expr1_0)?;
-                        let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                        return Some(expr3_0);
-                    }
-                    _ => {}
-                }
-            }
-            _ => {}
-        }
-        if let Some(()) = C::mie2_enabled(ctx, pattern2_0) {
-            if let Some(pattern4_0) = C::fits_in_64(ctx, pattern2_0) {
-                let pattern5_0 = C::inst_data(ctx, pattern0_0);
-                match &pattern5_0 {
-                    &InstructionData::Binary {
-                        opcode: ref pattern6_0,
-                        args: ref pattern6_1,
-                    } => {
-                        match pattern6_0 {
-                            &Opcode::BandNot => {
-                                let (pattern8_0, pattern8_1) =
-                                    C::unpack_value_array_2(ctx, pattern6_1);
-                                // Rule at src/isa/s390x/lower.isle line 702.
-                                let expr0_0 = C::put_in_reg(ctx, pattern8_0);
-                                let expr1_0 = C::put_in_reg(ctx, pattern8_1);
-                                let expr2_0 =
-                                    constructor_and_not_reg(ctx, pattern4_0, expr0_0, expr1_0)?;
-                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            &Opcode::BorNot => {
-                                let (pattern8_0, pattern8_1) =
-                                    C::unpack_value_array_2(ctx, pattern6_1);
-                                // Rule at src/isa/s390x/lower.isle line 713.
-                                let expr0_0 = C::put_in_reg(ctx, pattern8_0);
-                                let expr1_0 = C::put_in_reg(ctx, pattern8_1);
-                                let expr2_0 =
-                                    constructor_or_not_reg(ctx, pattern4_0, expr0_0, expr1_0)?;
-                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            &Opcode::BxorNot => {
-                                let (pattern8_0, pattern8_1) =
-                                    C::unpack_value_array_2(ctx, pattern6_1);
-                                // Rule at src/isa/s390x/lower.isle line 724.
-                                let expr0_0 = C::put_in_reg(ctx, pattern8_0);
-                                let expr1_0 = C::put_in_reg(ctx, pattern8_1);
-                                let expr2_0 =
-                                    constructor_xor_not_reg(ctx, pattern4_0, expr0_0, expr1_0)?;
-                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            _ => {}
-                        }
-                    }
-                    &InstructionData::Ternary {
-                        opcode: ref pattern6_0,
-                        args: ref pattern6_1,
-                    } => {
-                        if let &Opcode::Bitselect = pattern6_0 {
-                            let (pattern8_0, pattern8_1, pattern8_2) =
-                                C::unpack_value_array_3(ctx, pattern6_1);
-                            // Rule at src/isa/s390x/lower.isle line 735.
-                            let expr0_0 = C::put_in_reg(ctx, pattern8_0);
-                            let expr1_0 = C::put_in_reg(ctx, pattern8_1);
-                            let expr2_0 = constructor_and_reg(ctx, pattern4_0, expr1_0, expr0_0)?;
-                            let expr3_0 = C::put_in_reg(ctx, pattern8_2);
-                            let expr4_0 =
-                                constructor_and_not_reg(ctx, pattern4_0, expr3_0, expr0_0)?;
-                            let expr5_0 = constructor_or_reg(ctx, pattern4_0, expr4_0, expr2_0)?;
-                            let expr6_0 = constructor_output_reg(ctx, expr5_0)?;
-                            return Some(expr6_0);
-                        }
-                    }
-                    &InstructionData::Unary {
-                        opcode: ref pattern6_0,
-                        arg: pattern6_1,
-                    } => {
-                        match pattern6_0 {
-                            &Opcode::Bnot => {
-                                // Rule at src/isa/s390x/lower.isle line 625.
-                                let expr0_0 = C::put_in_reg(ctx, pattern6_1);
-                                let expr1_0 =
-                                    constructor_or_not_reg(ctx, pattern4_0, expr0_0, expr0_0)?;
-                                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            &Opcode::Popcnt => {
-                                // Rule at src/isa/s390x/lower.isle line 889.
-                                let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern6_1)?;
-                                let expr1_0 = constructor_popcnt_reg(ctx, expr0_0)?;
-                                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            _ => {}
-                        }
-                    }
-                    _ => {}
-                }
-            }
-        }
-        if let Some(()) = C::mie2_disabled(ctx, pattern2_0) {
-            if pattern2_0 == I16 {
-                let pattern5_0 = C::inst_data(ctx, pattern0_0);
-                if let &InstructionData::Unary {
-                    opcode: ref pattern6_0,
-                    arg: pattern6_1,
-                } = &pattern5_0
-                {
-                    if let &Opcode::Popcnt = pattern6_0 {
-                        // Rule at src/isa/s390x/lower.isle line 898.
-                        let expr0_0 = C::put_in_reg(ctx, pattern6_1);
-                        let expr1_0 = constructor_popcnt_byte(ctx, expr0_0)?;
-                        let expr2_0: Type = I32;
-                        let expr3_0: Type = I32;
-                        let expr4_0: u8 = 8;
-                        let expr5_0 = constructor_lshl_imm(ctx, expr3_0, expr1_0, expr4_0)?;
-                        let expr6_0 = constructor_add_reg(ctx, expr2_0, expr1_0, expr5_0)?;
-                        let expr7_0: Type = I32;
-                        let expr8_0: u8 = 8;
-                        let expr9_0 = constructor_lshr_imm(ctx, expr7_0, expr6_0, expr8_0)?;
-                        let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
-                        return Some(expr10_0);
-                    }
-                }
-            }
-            if pattern2_0 == I32 {
-                let pattern5_0 = C::inst_data(ctx, pattern0_0);
-                if let &InstructionData::Unary {
-                    opcode: ref pattern6_0,
-                    arg: pattern6_1,
-                } = &pattern5_0
-                {
-                    if let &Opcode::Popcnt = pattern6_0 {
-                        // Rule at src/isa/s390x/lower.isle line 903.
-                        let expr0_0 = C::put_in_reg(ctx, pattern6_1);
-                        let expr1_0 = constructor_popcnt_byte(ctx, expr0_0)?;
-                        let expr2_0: Type = I32;
-                        let expr3_0: Type = I32;
-                        let expr4_0: u8 = 16;
-                        let expr5_0 = constructor_lshl_imm(ctx, expr3_0, expr1_0, expr4_0)?;
-                        let expr6_0 = constructor_add_reg(ctx, expr2_0, expr1_0, expr5_0)?;
-                        let expr7_0: Type = I32;
-                        let expr8_0: Type = I32;
-                        let expr9_0: u8 = 8;
-                        let expr10_0 = constructor_lshl_imm(ctx, expr8_0, expr6_0, expr9_0)?;
-                        let expr11_0 = constructor_add_reg(ctx, expr7_0, expr6_0, expr10_0)?;
-                        let expr12_0: Type = I32;
-                        let expr13_0: u8 = 24;
-                        let expr14_0 = constructor_lshr_imm(ctx, expr12_0, expr11_0, expr13_0)?;
-                        let expr15_0 = constructor_output_reg(ctx, expr14_0)?;
-                        return Some(expr15_0);
-                    }
-                }
-            }
-            if pattern2_0 == I64 {
-                let pattern5_0 = C::inst_data(ctx, pattern0_0);
-                if let &InstructionData::Unary {
-                    opcode: ref pattern6_0,
-                    arg: pattern6_1,
-                } = &pattern5_0
-                {
-                    if let &Opcode::Popcnt = pattern6_0 {
-                        // Rule at src/isa/s390x/lower.isle line 909.
-                        let expr0_0 = C::put_in_reg(ctx, pattern6_1);
-                        let expr1_0 = constructor_popcnt_byte(ctx, expr0_0)?;
-                        let expr2_0: Type = I64;
-                        let expr3_0: Type = I64;
-                        let expr4_0: u8 = 32;
-                        let expr5_0 = constructor_lshl_imm(ctx, expr3_0, expr1_0, expr4_0)?;
-                        let expr6_0 = constructor_add_reg(ctx, expr2_0, expr1_0, expr5_0)?;
-                        let expr7_0: Type = I64;
-                        let expr8_0: Type = I64;
-                        let expr9_0: u8 = 16;
-                        let expr10_0 = constructor_lshl_imm(ctx, expr8_0, expr6_0, expr9_0)?;
-                        let expr11_0 = constructor_add_reg(ctx, expr7_0, expr6_0, expr10_0)?;
-                        let expr12_0: Type = I64;
-                        let expr13_0: Type = I64;
-                        let expr14_0: u8 = 8;
-                        let expr15_0 = constructor_lshl_imm(ctx, expr13_0, expr11_0, expr14_0)?;
-                        let expr16_0 = constructor_add_reg(ctx, expr12_0, expr11_0, expr15_0)?;
-                        let expr17_0: Type = I64;
-                        let expr18_0: u8 = 56;
-                        let expr19_0 = constructor_lshr_imm(ctx, expr17_0, expr16_0, expr18_0)?;
-                        let expr20_0 = constructor_output_reg(ctx, expr19_0)?;
-                        return Some(expr20_0);
-                    }
-                }
-            }
-            if let Some(pattern4_0) = C::fits_in_64(ctx, pattern2_0) {
-                let pattern5_0 = C::inst_data(ctx, pattern0_0);
-                match &pattern5_0 {
-                    &InstructionData::Binary {
-                        opcode: ref pattern6_0,
-                        args: ref pattern6_1,
-                    } => {
-                        match pattern6_0 {
-                            &Opcode::BandNot => {
-                                let (pattern8_0, pattern8_1) =
-                                    C::unpack_value_array_2(ctx, pattern6_1);
-                                // Rule at src/isa/s390x/lower.isle line 706.
-                                let expr0_0 = C::put_in_reg(ctx, pattern8_0);
-                                let expr1_0 = C::put_in_reg(ctx, pattern8_1);
-                                let expr2_0 =
-                                    constructor_and_reg(ctx, pattern4_0, expr0_0, expr1_0)?;
-                                let expr3_0 = constructor_not_reg(ctx, pattern4_0, expr2_0)?;
-                                let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                                return Some(expr4_0);
-                            }
-                            &Opcode::BorNot => {
-                                let (pattern8_0, pattern8_1) =
-                                    C::unpack_value_array_2(ctx, pattern6_1);
-                                // Rule at src/isa/s390x/lower.isle line 717.
-                                let expr0_0 = C::put_in_reg(ctx, pattern8_0);
-                                let expr1_0 = C::put_in_reg(ctx, pattern8_1);
-                                let expr2_0 =
-                                    constructor_or_reg(ctx, pattern4_0, expr0_0, expr1_0)?;
-                                let expr3_0 = constructor_not_reg(ctx, pattern4_0, expr2_0)?;
-                                let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                                return Some(expr4_0);
-                            }
-                            &Opcode::BxorNot => {
-                                let (pattern8_0, pattern8_1) =
-                                    C::unpack_value_array_2(ctx, pattern6_1);
-                                // Rule at src/isa/s390x/lower.isle line 728.
-                                let expr0_0 = C::put_in_reg(ctx, pattern8_0);
-                                let expr1_0 = C::put_in_reg(ctx, pattern8_1);
-                                let expr2_0 =
-                                    constructor_xor_reg(ctx, pattern4_0, expr0_0, expr1_0)?;
-                                let expr3_0 = constructor_not_reg(ctx, pattern4_0, expr2_0)?;
-                                let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                                return Some(expr4_0);
-                            }
-                            _ => {}
-                        }
-                    }
-                    &InstructionData::Ternary {
-                        opcode: ref pattern6_0,
-                        args: ref pattern6_1,
-                    } => {
-                        if let &Opcode::Bitselect = pattern6_0 {
-                            let (pattern8_0, pattern8_1, pattern8_2) =
-                                C::unpack_value_array_3(ctx, pattern6_1);
-                            // Rule at src/isa/s390x/lower.isle line 742.
-                            let expr0_0 = C::put_in_reg(ctx, pattern8_0);
-                            let expr1_0 = C::put_in_reg(ctx, pattern8_1);
-                            let expr2_0 = constructor_and_reg(ctx, pattern4_0, expr1_0, expr0_0)?;
-                            let expr3_0 = C::put_in_reg(ctx, pattern8_2);
-                            let expr4_0 = constructor_and_reg(ctx, pattern4_0, expr3_0, expr0_0)?;
-                            let expr5_0 = constructor_not_reg(ctx, pattern4_0, expr4_0)?;
-                            let expr6_0 = constructor_or_reg(ctx, pattern4_0, expr5_0, expr2_0)?;
-                            let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
-                            return Some(expr7_0);
-                        }
-                    }
-                    &InstructionData::Unary {
-                        opcode: ref pattern6_0,
-                        arg: pattern6_1,
-                    } => {
-                        if let &Opcode::Bnot = pattern6_0 {
-                            // Rule at src/isa/s390x/lower.isle line 630.
-                            let expr0_0 = C::put_in_reg(ctx, pattern6_1);
-                            let expr1_0 = constructor_not_reg(ctx, pattern4_0, expr0_0)?;
-                            let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                            return Some(expr2_0);
-                        }
-                    }
-                    _ => {}
-                }
-            }
-        }
-        if let Some(()) = C::vxrs_ext2_enabled(ctx, pattern2_0) {
-            if pattern2_0 == F32 {
-                let pattern5_0 = C::inst_data(ctx, pattern0_0);
-                if let &InstructionData::Load {
-                    opcode: ref pattern6_0,
-                    arg: pattern6_1,
-                    flags: pattern6_2,
-                    offset: pattern6_3,
-                } = &pattern5_0
-                {
-                    if let &Opcode::Load = pattern6_0 {
-                        if let Some(()) = C::littleendian(ctx, pattern6_2) {
-                            // Rule at src/isa/s390x/lower.isle line 1222.
-                            let expr0_0 =
-                                constructor_lower_address(ctx, pattern6_2, pattern6_1, pattern6_3)?;
-                            let expr1_0 = constructor_fpu_loadrev32(ctx, &expr0_0)?;
-                            let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                            return Some(expr2_0);
-                        }
-                    }
-                }
-            }
-            if pattern2_0 == F64 {
-                let pattern5_0 = C::inst_data(ctx, pattern0_0);
-                if let &InstructionData::Load {
-                    opcode: ref pattern6_0,
-                    arg: pattern6_1,
-                    flags: pattern6_2,
-                    offset: pattern6_3,
-                } = &pattern5_0
-                {
-                    if let &Opcode::Load = pattern6_0 {
-                        if let Some(()) = C::littleendian(ctx, pattern6_2) {
-                            // Rule at src/isa/s390x/lower.isle line 1237.
-                            let expr0_0 =
-                                constructor_lower_address(ctx, pattern6_2, pattern6_1, pattern6_3)?;
-                            let expr1_0 = constructor_fpu_loadrev64(ctx, &expr0_0)?;
-                            let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                            return Some(expr2_0);
-                        }
-                    }
-                }
-            }
-        }
-        if let Some(()) = C::vxrs_ext2_disabled(ctx, pattern2_0) {
-            if pattern2_0 == F32 {
-                let pattern5_0 = C::inst_data(ctx, pattern0_0);
-                if let &InstructionData::Load {
-                    opcode: ref pattern6_0,
-                    arg: pattern6_1,
-                    flags: pattern6_2,
-                    offset: pattern6_3,
-                } = &pattern5_0
-                {
-                    if let &Opcode::Load = pattern6_0 {
-                        if let Some(()) = C::littleendian(ctx, pattern6_2) {
-                            // Rule at src/isa/s390x/lower.isle line 1227.
-                            let expr0_0 =
-                                constructor_lower_address(ctx, pattern6_2, pattern6_1, pattern6_3)?;
-                            let expr1_0 = constructor_loadrev32(ctx, &expr0_0)?;
-                            let expr2_0: Type = I64;
-                            let expr3_0: u8 = 32;
-                            let expr4_0 = constructor_lshl_imm(ctx, expr2_0, expr1_0, expr3_0)?;
-                            let expr5_0 = constructor_mov_to_fpr(ctx, expr4_0)?;
-                            let expr6_0 = constructor_output_reg(ctx, expr5_0)?;
-                            return Some(expr6_0);
-                        }
-                    }
-                }
-            }
-            if pattern2_0 == F64 {
-                let pattern5_0 = C::inst_data(ctx, pattern0_0);
-                if let &InstructionData::Load {
-                    opcode: ref pattern6_0,
-                    arg: pattern6_1,
-                    flags: pattern6_2,
-                    offset: pattern6_3,
-                } = &pattern5_0
-                {
-                    if let &Opcode::Load = pattern6_0 {
-                        if let Some(()) = C::littleendian(ctx, pattern6_2) {
-                            // Rule at src/isa/s390x/lower.isle line 1242.
-                            let expr0_0 =
-                                constructor_lower_address(ctx, pattern6_2, pattern6_1, pattern6_3)?;
-                            let expr1_0 = constructor_loadrev64(ctx, &expr0_0)?;
-                            let expr2_0 = constructor_mov_to_fpr(ctx, expr1_0)?;
-                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                    }
-                }
-            }
-        }
-        if let Some(pattern3_0) = C::fits_in_16(ctx, pattern2_0) {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            if let &InstructionData::Unary {
-                opcode: ref pattern5_0,
-                arg: pattern5_1,
-            } = &pattern4_0
-            {
-                if let &Opcode::Bint = pattern5_0 {
-                    // Rule at src/isa/s390x/lower.isle line 796.
-                    let expr0_0 = C::put_in_reg(ctx, pattern5_1);
-                    let expr1_0: u16 = 1;
-                    let expr2_0: u8 = 0;
-                    let expr3_0 = C::uimm16shifted(ctx, expr1_0, expr2_0);
-                    let expr4_0 = constructor_and_uimm16shifted(ctx, pattern3_0, expr0_0, expr3_0)?;
-                    let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
-                    return Some(expr5_0);
-                }
-            }
-        }
-        if let Some(pattern3_0) = C::fits_in_32(ctx, pattern2_0) {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            if let &InstructionData::Unary {
-                opcode: ref pattern5_0,
-                arg: pattern5_1,
-            } = &pattern4_0
-            {
-                if let &Opcode::Bint = pattern5_0 {
-                    // Rule at src/isa/s390x/lower.isle line 800.
-                    let expr0_0 = C::put_in_reg(ctx, pattern5_1);
-                    let expr1_0: u32 = 1;
-                    let expr2_0: u8 = 0;
-                    let expr3_0 = C::uimm32shifted(ctx, expr1_0, expr2_0);
-                    let expr4_0 = constructor_and_uimm32shifted(ctx, pattern3_0, expr0_0, expr3_0)?;
-                    let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
-                    return Some(expr5_0);
-                }
-            }
-        }
-        if let Some(pattern3_0) = C::fits_in_64(ctx, pattern2_0) {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            match &pattern4_0 {
-                &InstructionData::Binary {
-                    opcode: ref pattern5_0,
-                    args: ref pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Iadd => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            if let Some(pattern8_0) = C::i16_from_value(ctx, pattern7_0) {
-                                // Rule at src/isa/s390x/lower.isle line 72.
-                                let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                let expr1_0 =
-                                    constructor_add_simm16(ctx, pattern3_0, expr0_0, pattern8_0)?;
-                                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            if let Some(pattern8_0) = C::i32_from_value(ctx, pattern7_0) {
-                                // Rule at src/isa/s390x/lower.isle line 76.
-                                let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                let expr1_0 =
-                                    constructor_add_simm32(ctx, pattern3_0, expr0_0, pattern8_0)?;
-                                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
-                                let pattern9_0 = C::inst_data(ctx, pattern8_0);
-                                if let &InstructionData::Unary {
-                                    opcode: ref pattern10_0,
-                                    arg: pattern10_1,
-                                } = &pattern9_0
-                                {
-                                    if let &Opcode::Sextend = pattern10_0 {
-                                        let pattern12_0 = C::value_type(ctx, pattern10_1);
-                                        if pattern12_0 == I32 {
-                                            // Rule at src/isa/s390x/lower.isle line 66.
-                                            let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                            let expr1_0 = C::put_in_reg(ctx, pattern10_1);
-                                            let expr2_0 = constructor_add_reg_sext32(
-                                                ctx, pattern3_0, expr0_0, expr1_0,
-                                            )?;
-                                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                            return Some(expr3_0);
-                                        }
-                                    }
-                                }
-                            }
-                            if let Some(pattern8_0) = C::sinkable_inst(ctx, pattern7_0) {
-                                let pattern9_0 = C::inst_data(ctx, pattern8_0);
-                                if let &InstructionData::Load {
-                                    opcode: ref pattern10_0,
-                                    arg: pattern10_1,
-                                    flags: pattern10_2,
-                                    offset: pattern10_3,
-                                } = &pattern9_0
-                                {
-                                    match pattern10_0 {
-                                        &Opcode::Sload16 => {
-                                            if let Some(()) = C::bigendian(ctx, pattern10_2) {
-                                                // Rule at src/isa/s390x/lower.isle line 94.
-                                                let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                                let expr1_0 =
-                                                    constructor_sink_sload16(ctx, pattern8_0)?;
-                                                let expr2_0 = constructor_add_mem_sext16(
-                                                    ctx, pattern3_0, expr0_0, &expr1_0,
-                                                )?;
-                                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                                return Some(expr3_0);
-                                            }
-                                        }
-                                        &Opcode::Sload32 => {
-                                            if let Some(()) = C::bigendian(ctx, pattern10_2) {
-                                                // Rule at src/isa/s390x/lower.isle line 98.
-                                                let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                                let expr1_0 =
-                                                    constructor_sink_sload32(ctx, pattern8_0)?;
-                                                let expr2_0 = constructor_add_mem_sext32(
-                                                    ctx, pattern3_0, expr0_0, &expr1_0,
-                                                )?;
-                                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                                return Some(expr3_0);
-                                            }
-                                        }
-                                        _ => {}
-                                    }
-                                }
-                            }
-                            let pattern8_0 = C::value_type(ctx, pattern7_0);
-                            if pattern8_0 == I16 {
-                                if let Some(pattern10_0) = C::sinkable_inst(ctx, pattern7_0) {
-                                    let pattern11_0 = C::inst_data(ctx, pattern10_0);
-                                    if let &InstructionData::Load {
-                                        opcode: ref pattern12_0,
-                                        arg: pattern12_1,
-                                        flags: pattern12_2,
-                                        offset: pattern12_3,
-                                    } = &pattern11_0
-                                    {
-                                        if let &Opcode::Load = pattern12_0 {
-                                            if let Some(()) = C::bigendian(ctx, pattern12_2) {
-                                                // Rule at src/isa/s390x/lower.isle line 88.
-                                                let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                                let expr1_0 =
-                                                    constructor_sink_load(ctx, pattern10_0)?;
-                                                let expr2_0 = constructor_add_mem_sext16(
-                                                    ctx, pattern3_0, expr0_0, &expr1_0,
-                                                )?;
-                                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                                return Some(expr3_0);
-                                            }
-                                        }
-                                    }
-                                }
-                            }
-                            if let Some(pattern9_0) = C::ty_32_or_64(ctx, pattern8_0) {
-                                if let Some(pattern10_0) = C::sinkable_inst(ctx, pattern7_0) {
-                                    let pattern11_0 = C::inst_data(ctx, pattern10_0);
-                                    if let &InstructionData::Load {
-                                        opcode: ref pattern12_0,
-                                        arg: pattern12_1,
-                                        flags: pattern12_2,
-                                        offset: pattern12_3,
-                                    } = &pattern11_0
-                                    {
-                                        if let &Opcode::Load = pattern12_0 {
-                                            if let Some(()) = C::bigendian(ctx, pattern12_2) {
-                                                // Rule at src/isa/s390x/lower.isle line 82.
-                                                let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                                let expr1_0 =
-                                                    constructor_sink_load(ctx, pattern10_0)?;
-                                                let expr2_0 = constructor_add_mem(
-                                                    ctx, pattern3_0, expr0_0, &expr1_0,
-                                                )?;
-                                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                                return Some(expr3_0);
-                                            }
-                                        }
-                                    }
-                                }
-                            }
-                            if let Some(pattern8_0) = C::i16_from_value(ctx, pattern7_1) {
-                                // Rule at src/isa/s390x/lower.isle line 70.
-                                let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                let expr1_0 =
-                                    constructor_add_simm16(ctx, pattern3_0, expr0_0, pattern8_0)?;
-                                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            if let Some(pattern8_0) = C::i32_from_value(ctx, pattern7_1) {
-                                // Rule at src/isa/s390x/lower.isle line 74.
-                                let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                let expr1_0 =
-                                    constructor_add_simm32(ctx, pattern3_0, expr0_0, pattern8_0)?;
-                                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
-                                let pattern9_0 = C::inst_data(ctx, pattern8_0);
-                                if let &InstructionData::Unary {
-                                    opcode: ref pattern10_0,
-                                    arg: pattern10_1,
-                                } = &pattern9_0
-                                {
-                                    if let &Opcode::Sextend = pattern10_0 {
-                                        let pattern12_0 = C::value_type(ctx, pattern10_1);
-                                        if pattern12_0 == I32 {
-                                            // Rule at src/isa/s390x/lower.isle line 64.
-                                            let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                            let expr1_0 = C::put_in_reg(ctx, pattern10_1);
-                                            let expr2_0 = constructor_add_reg_sext32(
-                                                ctx, pattern3_0, expr0_0, expr1_0,
-                                            )?;
-                                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                            return Some(expr3_0);
-                                        }
-                                    }
-                                }
-                            }
-                            if let Some(pattern8_0) = C::sinkable_inst(ctx, pattern7_1) {
-                                let pattern9_0 = C::inst_data(ctx, pattern8_0);
-                                if let &InstructionData::Load {
-                                    opcode: ref pattern10_0,
-                                    arg: pattern10_1,
-                                    flags: pattern10_2,
-                                    offset: pattern10_3,
-                                } = &pattern9_0
-                                {
-                                    match pattern10_0 {
-                                        &Opcode::Sload16 => {
-                                            if let Some(()) = C::bigendian(ctx, pattern10_2) {
-                                                // Rule at src/isa/s390x/lower.isle line 92.
-                                                let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                                let expr1_0 =
-                                                    constructor_sink_sload16(ctx, pattern8_0)?;
-                                                let expr2_0 = constructor_add_mem_sext16(
-                                                    ctx, pattern3_0, expr0_0, &expr1_0,
-                                                )?;
-                                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                                return Some(expr3_0);
-                                            }
-                                        }
-                                        &Opcode::Sload32 => {
-                                            if let Some(()) = C::bigendian(ctx, pattern10_2) {
-                                                // Rule at src/isa/s390x/lower.isle line 96.
-                                                let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                                let expr1_0 =
-                                                    constructor_sink_sload32(ctx, pattern8_0)?;
-                                                let expr2_0 = constructor_add_mem_sext32(
-                                                    ctx, pattern3_0, expr0_0, &expr1_0,
-                                                )?;
-                                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                                return Some(expr3_0);
-                                            }
-                                        }
-                                        _ => {}
-                                    }
-                                }
-                            }
-                            let pattern8_0 = C::value_type(ctx, pattern7_1);
-                            if pattern8_0 == I16 {
-                                if let Some(pattern10_0) = C::sinkable_inst(ctx, pattern7_1) {
-                                    let pattern11_0 = C::inst_data(ctx, pattern10_0);
-                                    if let &InstructionData::Load {
-                                        opcode: ref pattern12_0,
-                                        arg: pattern12_1,
-                                        flags: pattern12_2,
-                                        offset: pattern12_3,
-                                    } = &pattern11_0
-                                    {
-                                        if let &Opcode::Load = pattern12_0 {
-                                            if let Some(()) = C::bigendian(ctx, pattern12_2) {
-                                                // Rule at src/isa/s390x/lower.isle line 86.
-                                                let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                                let expr1_0 =
-                                                    constructor_sink_load(ctx, pattern10_0)?;
-                                                let expr2_0 = constructor_add_mem_sext16(
-                                                    ctx, pattern3_0, expr0_0, &expr1_0,
-                                                )?;
-                                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                                return Some(expr3_0);
-                                            }
-                                        }
-                                    }
-                                }
-                            }
-                            if let Some(pattern9_0) = C::ty_32_or_64(ctx, pattern8_0) {
-                                if let Some(pattern10_0) = C::sinkable_inst(ctx, pattern7_1) {
-                                    let pattern11_0 = C::inst_data(ctx, pattern10_0);
-                                    if let &InstructionData::Load {
-                                        opcode: ref pattern12_0,
-                                        arg: pattern12_1,
-                                        flags: pattern12_2,
-                                        offset: pattern12_3,
-                                    } = &pattern11_0
-                                    {
-                                        if let &Opcode::Load = pattern12_0 {
-                                            if let Some(()) = C::bigendian(ctx, pattern12_2) {
-                                                // Rule at src/isa/s390x/lower.isle line 80.
-                                                let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                                let expr1_0 =
-                                                    constructor_sink_load(ctx, pattern10_0)?;
-                                                let expr2_0 = constructor_add_mem(
-                                                    ctx, pattern3_0, expr0_0, &expr1_0,
-                                                )?;
-                                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                                return Some(expr3_0);
-                                            }
-                                        }
-                                    }
-                                }
-                            }
-                            // Rule at src/isa/s390x/lower.isle line 60.
-                            let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                            let expr1_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr2_0 = constructor_add_reg(ctx, pattern3_0, expr0_0, expr1_0)?;
-                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Isub => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            if let Some(pattern8_0) = C::i16_from_negated_value(ctx, pattern7_1) {
-                                // Rule at src/isa/s390x/lower.isle line 113.
-                                let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                let expr1_0 =
-                                    constructor_add_simm16(ctx, pattern3_0, expr0_0, pattern8_0)?;
-                                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            if let Some(pattern8_0) = C::i32_from_negated_value(ctx, pattern7_1) {
-                                // Rule at src/isa/s390x/lower.isle line 115.
-                                let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                let expr1_0 =
-                                    constructor_add_simm32(ctx, pattern3_0, expr0_0, pattern8_0)?;
-                                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
-                                let pattern9_0 = C::inst_data(ctx, pattern8_0);
-                                if let &InstructionData::Unary {
-                                    opcode: ref pattern10_0,
-                                    arg: pattern10_1,
-                                } = &pattern9_0
-                                {
-                                    if let &Opcode::Sextend = pattern10_0 {
-                                        let pattern12_0 = C::value_type(ctx, pattern10_1);
-                                        if pattern12_0 == I32 {
-                                            // Rule at src/isa/s390x/lower.isle line 109.
-                                            let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                            let expr1_0 = C::put_in_reg(ctx, pattern10_1);
-                                            let expr2_0 = constructor_sub_reg_sext32(
-                                                ctx, pattern3_0, expr0_0, expr1_0,
-                                            )?;
-                                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                            return Some(expr3_0);
-                                        }
-                                    }
-                                }
-                            }
-                            if let Some(pattern8_0) = C::sinkable_inst(ctx, pattern7_1) {
-                                let pattern9_0 = C::inst_data(ctx, pattern8_0);
-                                if let &InstructionData::Load {
-                                    opcode: ref pattern10_0,
-                                    arg: pattern10_1,
-                                    flags: pattern10_2,
-                                    offset: pattern10_3,
-                                } = &pattern9_0
-                                {
-                                    match pattern10_0 {
-                                        &Opcode::Sload16 => {
-                                            if let Some(()) = C::bigendian(ctx, pattern10_2) {
-                                                // Rule at src/isa/s390x/lower.isle line 127.
-                                                let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                                let expr1_0 =
-                                                    constructor_sink_sload16(ctx, pattern8_0)?;
-                                                let expr2_0 = constructor_sub_mem_sext16(
-                                                    ctx, pattern3_0, expr0_0, &expr1_0,
-                                                )?;
-                                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                                return Some(expr3_0);
-                                            }
-                                        }
-                                        &Opcode::Sload32 => {
-                                            if let Some(()) = C::bigendian(ctx, pattern10_2) {
-                                                // Rule at src/isa/s390x/lower.isle line 129.
-                                                let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                                let expr1_0 =
-                                                    constructor_sink_sload32(ctx, pattern8_0)?;
-                                                let expr2_0 = constructor_sub_mem_sext32(
-                                                    ctx, pattern3_0, expr0_0, &expr1_0,
-                                                )?;
-                                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                                return Some(expr3_0);
-                                            }
-                                        }
-                                        _ => {}
-                                    }
-                                }
-                            }
-                            let pattern8_0 = C::value_type(ctx, pattern7_1);
-                            if pattern8_0 == I16 {
-                                if let Some(pattern10_0) = C::sinkable_inst(ctx, pattern7_1) {
-                                    let pattern11_0 = C::inst_data(ctx, pattern10_0);
-                                    if let &InstructionData::Load {
-                                        opcode: ref pattern12_0,
-                                        arg: pattern12_1,
-                                        flags: pattern12_2,
-                                        offset: pattern12_3,
-                                    } = &pattern11_0
-                                    {
-                                        if let &Opcode::Load = pattern12_0 {
-                                            if let Some(()) = C::bigendian(ctx, pattern12_2) {
-                                                // Rule at src/isa/s390x/lower.isle line 123.
-                                                let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                                let expr1_0 =
-                                                    constructor_sink_load(ctx, pattern10_0)?;
-                                                let expr2_0 = constructor_sub_mem_sext16(
-                                                    ctx, pattern3_0, expr0_0, &expr1_0,
-                                                )?;
-                                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                                return Some(expr3_0);
-                                            }
-                                        }
-                                    }
-                                }
-                            }
-                            if let Some(pattern9_0) = C::ty_32_or_64(ctx, pattern8_0) {
-                                if let Some(pattern10_0) = C::sinkable_inst(ctx, pattern7_1) {
-                                    let pattern11_0 = C::inst_data(ctx, pattern10_0);
-                                    if let &InstructionData::Load {
-                                        opcode: ref pattern12_0,
-                                        arg: pattern12_1,
-                                        flags: pattern12_2,
-                                        offset: pattern12_3,
-                                    } = &pattern11_0
-                                    {
-                                        if let &Opcode::Load = pattern12_0 {
-                                            if let Some(()) = C::bigendian(ctx, pattern12_2) {
-                                                // Rule at src/isa/s390x/lower.isle line 119.
-                                                let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                                let expr1_0 =
-                                                    constructor_sink_load(ctx, pattern10_0)?;
-                                                let expr2_0 = constructor_sub_mem(
-                                                    ctx, pattern3_0, expr0_0, &expr1_0,
-                                                )?;
-                                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                                return Some(expr3_0);
-                                            }
-                                        }
-                                    }
-                                }
-                            }
-                            // Rule at src/isa/s390x/lower.isle line 105.
-                            let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                            let expr1_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr2_0 = constructor_sub_reg(ctx, pattern3_0, expr0_0, expr1_0)?;
-                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Imul => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            if let Some(pattern8_0) = C::i16_from_value(ctx, pattern7_0) {
-                                // Rule at src/isa/s390x/lower.isle line 212.
-                                let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                let expr1_0 =
-                                    constructor_mul_simm16(ctx, pattern3_0, expr0_0, pattern8_0)?;
-                                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            if let Some(pattern8_0) = C::i32_from_value(ctx, pattern7_0) {
-                                // Rule at src/isa/s390x/lower.isle line 216.
-                                let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                let expr1_0 =
-                                    constructor_mul_simm32(ctx, pattern3_0, expr0_0, pattern8_0)?;
-                                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
-                                let pattern9_0 = C::inst_data(ctx, pattern8_0);
-                                if let &InstructionData::Unary {
-                                    opcode: ref pattern10_0,
-                                    arg: pattern10_1,
-                                } = &pattern9_0
-                                {
-                                    if let &Opcode::Sextend = pattern10_0 {
-                                        let pattern12_0 = C::value_type(ctx, pattern10_1);
-                                        if pattern12_0 == I32 {
-                                            // Rule at src/isa/s390x/lower.isle line 206.
-                                            let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                            let expr1_0 = C::put_in_reg(ctx, pattern10_1);
-                                            let expr2_0 = constructor_mul_reg_sext32(
-                                                ctx, pattern3_0, expr0_0, expr1_0,
-                                            )?;
-                                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                            return Some(expr3_0);
-                                        }
-                                    }
-                                }
-                            }
-                            if let Some(pattern8_0) = C::sinkable_inst(ctx, pattern7_0) {
-                                let pattern9_0 = C::inst_data(ctx, pattern8_0);
-                                if let &InstructionData::Load {
-                                    opcode: ref pattern10_0,
-                                    arg: pattern10_1,
-                                    flags: pattern10_2,
-                                    offset: pattern10_3,
-                                } = &pattern9_0
-                                {
-                                    match pattern10_0 {
-                                        &Opcode::Sload16 => {
-                                            if let Some(()) = C::bigendian(ctx, pattern10_2) {
-                                                // Rule at src/isa/s390x/lower.isle line 234.
-                                                let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                                let expr1_0 =
-                                                    constructor_sink_sload16(ctx, pattern8_0)?;
-                                                let expr2_0 = constructor_mul_mem_sext16(
-                                                    ctx, pattern3_0, expr0_0, &expr1_0,
-                                                )?;
-                                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                                return Some(expr3_0);
-                                            }
-                                        }
-                                        &Opcode::Sload32 => {
-                                            if let Some(()) = C::bigendian(ctx, pattern10_2) {
-                                                // Rule at src/isa/s390x/lower.isle line 238.
-                                                let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                                let expr1_0 =
-                                                    constructor_sink_sload32(ctx, pattern8_0)?;
-                                                let expr2_0 = constructor_mul_mem_sext32(
-                                                    ctx, pattern3_0, expr0_0, &expr1_0,
-                                                )?;
-                                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                                return Some(expr3_0);
-                                            }
-                                        }
-                                        _ => {}
-                                    }
-                                }
-                            }
-                            let pattern8_0 = C::value_type(ctx, pattern7_0);
-                            if pattern8_0 == I16 {
-                                if let Some(pattern10_0) = C::sinkable_inst(ctx, pattern7_0) {
-                                    let pattern11_0 = C::inst_data(ctx, pattern10_0);
-                                    if let &InstructionData::Load {
-                                        opcode: ref pattern12_0,
-                                        arg: pattern12_1,
-                                        flags: pattern12_2,
-                                        offset: pattern12_3,
-                                    } = &pattern11_0
-                                    {
-                                        if let &Opcode::Load = pattern12_0 {
-                                            if let Some(()) = C::bigendian(ctx, pattern12_2) {
-                                                // Rule at src/isa/s390x/lower.isle line 228.
-                                                let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                                let expr1_0 =
-                                                    constructor_sink_load(ctx, pattern10_0)?;
-                                                let expr2_0 = constructor_mul_mem_sext16(
-                                                    ctx, pattern3_0, expr0_0, &expr1_0,
-                                                )?;
-                                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                                return Some(expr3_0);
-                                            }
-                                        }
-                                    }
-                                }
-                            }
-                            if let Some(pattern9_0) = C::ty_32_or_64(ctx, pattern8_0) {
-                                if let Some(pattern10_0) = C::sinkable_inst(ctx, pattern7_0) {
-                                    let pattern11_0 = C::inst_data(ctx, pattern10_0);
-                                    if let &InstructionData::Load {
-                                        opcode: ref pattern12_0,
-                                        arg: pattern12_1,
-                                        flags: pattern12_2,
-                                        offset: pattern12_3,
-                                    } = &pattern11_0
-                                    {
-                                        if let &Opcode::Load = pattern12_0 {
-                                            if let Some(()) = C::bigendian(ctx, pattern12_2) {
-                                                // Rule at src/isa/s390x/lower.isle line 222.
-                                                let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                                let expr1_0 =
-                                                    constructor_sink_load(ctx, pattern10_0)?;
-                                                let expr2_0 = constructor_mul_mem(
-                                                    ctx, pattern3_0, expr0_0, &expr1_0,
-                                                )?;
-                                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                                return Some(expr3_0);
-                                            }
-                                        }
-                                    }
-                                }
-                            }
-                            if let Some(pattern8_0) = C::i16_from_value(ctx, pattern7_1) {
-                                // Rule at src/isa/s390x/lower.isle line 210.
-                                let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                let expr1_0 =
-                                    constructor_mul_simm16(ctx, pattern3_0, expr0_0, pattern8_0)?;
-                                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            if let Some(pattern8_0) = C::i32_from_value(ctx, pattern7_1) {
-                                // Rule at src/isa/s390x/lower.isle line 214.
-                                let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                let expr1_0 =
-                                    constructor_mul_simm32(ctx, pattern3_0, expr0_0, pattern8_0)?;
-                                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
-                                let pattern9_0 = C::inst_data(ctx, pattern8_0);
-                                if let &InstructionData::Unary {
-                                    opcode: ref pattern10_0,
-                                    arg: pattern10_1,
-                                } = &pattern9_0
-                                {
-                                    if let &Opcode::Sextend = pattern10_0 {
-                                        let pattern12_0 = C::value_type(ctx, pattern10_1);
-                                        if pattern12_0 == I32 {
-                                            // Rule at src/isa/s390x/lower.isle line 204.
-                                            let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                            let expr1_0 = C::put_in_reg(ctx, pattern10_1);
-                                            let expr2_0 = constructor_mul_reg_sext32(
-                                                ctx, pattern3_0, expr0_0, expr1_0,
-                                            )?;
-                                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                            return Some(expr3_0);
-                                        }
-                                    }
-                                }
-                            }
-                            if let Some(pattern8_0) = C::sinkable_inst(ctx, pattern7_1) {
-                                let pattern9_0 = C::inst_data(ctx, pattern8_0);
-                                if let &InstructionData::Load {
-                                    opcode: ref pattern10_0,
-                                    arg: pattern10_1,
-                                    flags: pattern10_2,
-                                    offset: pattern10_3,
-                                } = &pattern9_0
-                                {
-                                    match pattern10_0 {
-                                        &Opcode::Sload16 => {
-                                            if let Some(()) = C::bigendian(ctx, pattern10_2) {
-                                                // Rule at src/isa/s390x/lower.isle line 232.
-                                                let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                                let expr1_0 =
-                                                    constructor_sink_sload16(ctx, pattern8_0)?;
-                                                let expr2_0 = constructor_mul_mem_sext16(
-                                                    ctx, pattern3_0, expr0_0, &expr1_0,
-                                                )?;
-                                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                                return Some(expr3_0);
-                                            }
-                                        }
-                                        &Opcode::Sload32 => {
-                                            if let Some(()) = C::bigendian(ctx, pattern10_2) {
-                                                // Rule at src/isa/s390x/lower.isle line 236.
-                                                let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                                let expr1_0 =
-                                                    constructor_sink_sload32(ctx, pattern8_0)?;
-                                                let expr2_0 = constructor_mul_mem_sext32(
-                                                    ctx, pattern3_0, expr0_0, &expr1_0,
-                                                )?;
-                                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                                return Some(expr3_0);
-                                            }
-                                        }
-                                        _ => {}
-                                    }
-                                }
-                            }
-                            let pattern8_0 = C::value_type(ctx, pattern7_1);
-                            if pattern8_0 == I16 {
-                                if let Some(pattern10_0) = C::sinkable_inst(ctx, pattern7_1) {
-                                    let pattern11_0 = C::inst_data(ctx, pattern10_0);
-                                    if let &InstructionData::Load {
-                                        opcode: ref pattern12_0,
-                                        arg: pattern12_1,
-                                        flags: pattern12_2,
-                                        offset: pattern12_3,
-                                    } = &pattern11_0
-                                    {
-                                        if let &Opcode::Load = pattern12_0 {
-                                            if let Some(()) = C::bigendian(ctx, pattern12_2) {
-                                                // Rule at src/isa/s390x/lower.isle line 226.
-                                                let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                                let expr1_0 =
-                                                    constructor_sink_load(ctx, pattern10_0)?;
-                                                let expr2_0 = constructor_mul_mem_sext16(
-                                                    ctx, pattern3_0, expr0_0, &expr1_0,
-                                                )?;
-                                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                                return Some(expr3_0);
-                                            }
-                                        }
-                                    }
-                                }
-                            }
-                            if let Some(pattern9_0) = C::ty_32_or_64(ctx, pattern8_0) {
-                                if let Some(pattern10_0) = C::sinkable_inst(ctx, pattern7_1) {
-                                    let pattern11_0 = C::inst_data(ctx, pattern10_0);
-                                    if let &InstructionData::Load {
-                                        opcode: ref pattern12_0,
-                                        arg: pattern12_1,
-                                        flags: pattern12_2,
-                                        offset: pattern12_3,
-                                    } = &pattern11_0
-                                    {
-                                        if let &Opcode::Load = pattern12_0 {
-                                            if let Some(()) = C::bigendian(ctx, pattern12_2) {
-                                                // Rule at src/isa/s390x/lower.isle line 220.
-                                                let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                                let expr1_0 =
-                                                    constructor_sink_load(ctx, pattern10_0)?;
-                                                let expr2_0 = constructor_mul_mem(
-                                                    ctx, pattern3_0, expr0_0, &expr1_0,
-                                                )?;
-                                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                                return Some(expr3_0);
-                                            }
-                                        }
-                                    }
-                                }
-                            }
-                            // Rule at src/isa/s390x/lower.isle line 200.
-                            let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                            let expr1_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr2_0 = constructor_mul_reg(ctx, pattern3_0, expr0_0, expr1_0)?;
-                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Udiv => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/s390x/lower.isle line 303.
-                            let expr0_0 = constructor_zero_divisor_check_needed(ctx, pattern7_1)?;
-                            let expr1_0 = constructor_ty_ext32(ctx, pattern3_0)?;
-                            let expr2_0: u64 = 0;
-                            let expr3_0 = constructor_uninitialized_regpair(ctx)?;
-                            let expr4_0 =
-                                constructor_imm_regpair_hi(ctx, expr1_0, expr2_0, &expr3_0)?;
-                            let expr5_0 =
-                                constructor_put_in_regpair_lo_zext32(ctx, pattern7_0, &expr4_0)?;
-                            let expr6_0 = constructor_put_in_reg_zext32(ctx, pattern7_1)?;
-                            let expr7_0 = constructor_ty_ext32(ctx, pattern3_0)?;
-                            let expr8_0 = constructor_maybe_trap_if_zero_divisor(
-                                ctx, expr0_0, expr7_0, expr6_0,
-                            )?;
-                            let expr9_0 = constructor_udivmod(ctx, expr7_0, &expr5_0, expr6_0)?;
-                            let expr10_0 = constructor_regpair_lo(ctx, &expr9_0)?;
-                            let expr11_0 = constructor_copy_reg(ctx, pattern3_0, expr10_0)?;
-                            let expr12_0 = constructor_output_reg(ctx, expr11_0)?;
-                            return Some(expr12_0);
-                        }
-                        &Opcode::Sdiv => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/s390x/lower.isle line 375.
-                            let expr0_0 = constructor_zero_divisor_check_needed(ctx, pattern7_1)?;
-                            let expr1_0 = constructor_div_overflow_check_needed(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_uninitialized_regpair(ctx)?;
-                            let expr3_0 =
-                                constructor_put_in_regpair_lo_sext64(ctx, pattern7_0, &expr2_0)?;
-                            let expr4_0 = constructor_put_in_reg_sext32(ctx, pattern7_1)?;
-                            let expr5_0 = constructor_ty_ext32(ctx, pattern3_0)?;
-                            let expr6_0 = constructor_maybe_trap_if_zero_divisor(
-                                ctx, expr0_0, expr5_0, expr4_0,
-                            )?;
-                            let expr7_0 = constructor_maybe_trap_if_sdiv_overflow(
-                                ctx, expr1_0, expr5_0, pattern3_0, &expr3_0, expr4_0,
-                            )?;
-                            let expr8_0 = constructor_sdivmod(ctx, expr5_0, &expr3_0, expr4_0)?;
-                            let expr9_0 = constructor_regpair_lo(ctx, &expr8_0)?;
-                            let expr10_0 = constructor_copy_reg(ctx, pattern3_0, expr9_0)?;
-                            let expr11_0 = constructor_output_reg(ctx, expr10_0)?;
-                            return Some(expr11_0);
-                        }
-                        &Opcode::Urem => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/s390x/lower.isle line 326.
-                            let expr0_0 = constructor_zero_divisor_check_needed(ctx, pattern7_1)?;
-                            let expr1_0: u64 = 0;
-                            let expr2_0 = constructor_uninitialized_regpair(ctx)?;
-                            let expr3_0 =
-                                constructor_imm_regpair_hi(ctx, pattern3_0, expr1_0, &expr2_0)?;
-                            let expr4_0 =
-                                constructor_put_in_regpair_lo_zext32(ctx, pattern7_0, &expr3_0)?;
-                            let expr5_0 = constructor_put_in_reg_zext32(ctx, pattern7_1)?;
-                            let expr6_0 = constructor_ty_ext32(ctx, pattern3_0)?;
-                            let expr7_0 = constructor_maybe_trap_if_zero_divisor(
-                                ctx, expr0_0, expr6_0, expr5_0,
-                            )?;
-                            let expr8_0 = constructor_udivmod(ctx, expr6_0, &expr4_0, expr5_0)?;
-                            let expr9_0 = constructor_regpair_hi(ctx, &expr8_0)?;
-                            let expr10_0 = constructor_copy_reg(ctx, pattern3_0, expr9_0)?;
-                            let expr11_0 = constructor_output_reg(ctx, expr10_0)?;
-                            return Some(expr11_0);
-                        }
-                        &Opcode::Srem => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/s390x/lower.isle line 398.
-                            let expr0_0 = constructor_zero_divisor_check_needed(ctx, pattern7_1)?;
-                            let expr1_0 = constructor_div_overflow_check_needed(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_uninitialized_regpair(ctx)?;
-                            let expr3_0 =
-                                constructor_put_in_regpair_lo_sext64(ctx, pattern7_0, &expr2_0)?;
-                            let expr4_0 = constructor_put_in_reg_sext32(ctx, pattern7_1)?;
-                            let expr5_0 = constructor_ty_ext32(ctx, pattern3_0)?;
-                            let expr6_0 = constructor_maybe_trap_if_zero_divisor(
-                                ctx, expr0_0, expr5_0, expr4_0,
-                            )?;
-                            let expr7_0 = constructor_maybe_avoid_srem_overflow(
-                                ctx, expr1_0, expr5_0, &expr3_0, expr4_0,
-                            )?;
-                            let expr8_0 = constructor_sdivmod(ctx, expr5_0, &expr7_0, expr4_0)?;
-                            let expr9_0 = constructor_regpair_hi(ctx, &expr8_0)?;
-                            let expr10_0 = constructor_copy_reg(ctx, pattern3_0, expr9_0)?;
-                            let expr11_0 = constructor_output_reg(ctx, expr10_0)?;
-                            return Some(expr11_0);
-                        }
-                        &Opcode::IaddIfcout => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            if let Some(pattern8_0) = C::u32_from_value(ctx, pattern7_0) {
-                                // Rule at src/isa/s390x/lower.isle line 170.
-                                let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                let expr1_0 = constructor_add_logical_zimm32(
-                                    ctx, pattern3_0, expr0_0, pattern8_0,
-                                )?;
-                                let expr2_0 = constructor_output_ifcout(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
-                                let pattern9_0 = C::inst_data(ctx, pattern8_0);
-                                if let &InstructionData::Unary {
-                                    opcode: ref pattern10_0,
-                                    arg: pattern10_1,
-                                } = &pattern9_0
-                                {
-                                    if let &Opcode::Uextend = pattern10_0 {
-                                        let pattern12_0 = C::value_type(ctx, pattern10_1);
-                                        if pattern12_0 == I32 {
-                                            // Rule at src/isa/s390x/lower.isle line 164.
-                                            let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                            let expr1_0 = C::put_in_reg(ctx, pattern10_1);
-                                            let expr2_0 = constructor_add_logical_reg_zext32(
-                                                ctx, pattern3_0, expr0_0, expr1_0,
-                                            )?;
-                                            let expr3_0 = constructor_output_ifcout(ctx, expr2_0)?;
-                                            return Some(expr3_0);
-                                        }
-                                    }
-                                }
-                            }
-                            if let Some(pattern8_0) = C::sinkable_inst(ctx, pattern7_0) {
-                                let pattern9_0 = C::inst_data(ctx, pattern8_0);
-                                if let &InstructionData::Load {
-                                    opcode: ref pattern10_0,
-                                    arg: pattern10_1,
-                                    flags: pattern10_2,
-                                    offset: pattern10_3,
-                                } = &pattern9_0
-                                {
-                                    if let &Opcode::Uload32 = pattern10_0 {
-                                        if let Some(()) = C::bigendian(ctx, pattern10_2) {
-                                            // Rule at src/isa/s390x/lower.isle line 182.
-                                            let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                            let expr1_0 =
-                                                constructor_sink_uload32(ctx, pattern8_0)?;
-                                            let expr2_0 = constructor_add_logical_mem_zext32(
-                                                ctx, pattern3_0, expr0_0, &expr1_0,
-                                            )?;
-                                            let expr3_0 = constructor_output_ifcout(ctx, expr2_0)?;
-                                            return Some(expr3_0);
-                                        }
-                                    }
-                                }
-                            }
-                            let pattern8_0 = C::value_type(ctx, pattern7_0);
-                            if let Some(pattern9_0) = C::ty_32_or_64(ctx, pattern8_0) {
-                                if let Some(pattern10_0) = C::sinkable_inst(ctx, pattern7_0) {
-                                    let pattern11_0 = C::inst_data(ctx, pattern10_0);
-                                    if let &InstructionData::Load {
-                                        opcode: ref pattern12_0,
-                                        arg: pattern12_1,
-                                        flags: pattern12_2,
-                                        offset: pattern12_3,
-                                    } = &pattern11_0
-                                    {
-                                        if let &Opcode::Load = pattern12_0 {
-                                            if let Some(()) = C::bigendian(ctx, pattern12_2) {
-                                                // Rule at src/isa/s390x/lower.isle line 176.
-                                                let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                                let expr1_0 =
-                                                    constructor_sink_load(ctx, pattern10_0)?;
-                                                let expr2_0 = constructor_add_logical_mem(
-                                                    ctx, pattern3_0, expr0_0, &expr1_0,
-                                                )?;
-                                                let expr3_0 =
-                                                    constructor_output_ifcout(ctx, expr2_0)?;
-                                                return Some(expr3_0);
-                                            }
-                                        }
-                                    }
-                                }
-                            }
-                            if let Some(pattern8_0) = C::u32_from_value(ctx, pattern7_1) {
-                                // Rule at src/isa/s390x/lower.isle line 168.
-                                let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                let expr1_0 = constructor_add_logical_zimm32(
-                                    ctx, pattern3_0, expr0_0, pattern8_0,
-                                )?;
-                                let expr2_0 = constructor_output_ifcout(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
-                                let pattern9_0 = C::inst_data(ctx, pattern8_0);
-                                if let &InstructionData::Unary {
-                                    opcode: ref pattern10_0,
-                                    arg: pattern10_1,
-                                } = &pattern9_0
-                                {
-                                    if let &Opcode::Uextend = pattern10_0 {
-                                        let pattern12_0 = C::value_type(ctx, pattern10_1);
-                                        if pattern12_0 == I32 {
-                                            // Rule at src/isa/s390x/lower.isle line 162.
-                                            let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                            let expr1_0 = C::put_in_reg(ctx, pattern10_1);
-                                            let expr2_0 = constructor_add_logical_reg_zext32(
-                                                ctx, pattern3_0, expr0_0, expr1_0,
-                                            )?;
-                                            let expr3_0 = constructor_output_ifcout(ctx, expr2_0)?;
-                                            return Some(expr3_0);
-                                        }
-                                    }
-                                }
-                            }
-                            if let Some(pattern8_0) = C::sinkable_inst(ctx, pattern7_1) {
-                                let pattern9_0 = C::inst_data(ctx, pattern8_0);
-                                if let &InstructionData::Load {
-                                    opcode: ref pattern10_0,
-                                    arg: pattern10_1,
-                                    flags: pattern10_2,
-                                    offset: pattern10_3,
-                                } = &pattern9_0
-                                {
-                                    if let &Opcode::Uload32 = pattern10_0 {
-                                        if let Some(()) = C::bigendian(ctx, pattern10_2) {
-                                            // Rule at src/isa/s390x/lower.isle line 180.
-                                            let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                            let expr1_0 =
-                                                constructor_sink_uload32(ctx, pattern8_0)?;
-                                            let expr2_0 = constructor_add_logical_mem_zext32(
-                                                ctx, pattern3_0, expr0_0, &expr1_0,
-                                            )?;
-                                            let expr3_0 = constructor_output_ifcout(ctx, expr2_0)?;
-                                            return Some(expr3_0);
-                                        }
-                                    }
-                                }
-                            }
-                            let pattern8_0 = C::value_type(ctx, pattern7_1);
-                            if let Some(pattern9_0) = C::ty_32_or_64(ctx, pattern8_0) {
-                                if let Some(pattern10_0) = C::sinkable_inst(ctx, pattern7_1) {
-                                    let pattern11_0 = C::inst_data(ctx, pattern10_0);
-                                    if let &InstructionData::Load {
-                                        opcode: ref pattern12_0,
-                                        arg: pattern12_1,
-                                        flags: pattern12_2,
-                                        offset: pattern12_3,
-                                    } = &pattern11_0
-                                    {
-                                        if let &Opcode::Load = pattern12_0 {
-                                            if let Some(()) = C::bigendian(ctx, pattern12_2) {
-                                                // Rule at src/isa/s390x/lower.isle line 174.
-                                                let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                                let expr1_0 =
-                                                    constructor_sink_load(ctx, pattern10_0)?;
-                                                let expr2_0 = constructor_add_logical_mem(
-                                                    ctx, pattern3_0, expr0_0, &expr1_0,
-                                                )?;
-                                                let expr3_0 =
-                                                    constructor_output_ifcout(ctx, expr2_0)?;
-                                                return Some(expr3_0);
-                                            }
-                                        }
-                                    }
-                                }
-                            }
-                            // Rule at src/isa/s390x/lower.isle line 158.
-                            let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                            let expr1_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr2_0 =
-                                constructor_add_logical_reg(ctx, pattern3_0, expr0_0, expr1_0)?;
-                            let expr3_0 = constructor_output_ifcout(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Band => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            let pattern8_0 = C::value_type(ctx, pattern7_0);
-                            if let Some(pattern9_0) = C::ty_32_or_64(ctx, pattern8_0) {
-                                if let Some(pattern10_0) = C::sinkable_inst(ctx, pattern7_0) {
-                                    let pattern11_0 = C::inst_data(ctx, pattern10_0);
-                                    if let &InstructionData::Load {
-                                        opcode: ref pattern12_0,
-                                        arg: pattern12_1,
-                                        flags: pattern12_2,
-                                        offset: pattern12_3,
-                                    } = &pattern11_0
-                                    {
-                                        if let &Opcode::Load = pattern12_0 {
-                                            if let Some(()) = C::bigendian(ctx, pattern12_2) {
-                                                // Rule at src/isa/s390x/lower.isle line 653.
-                                                let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                                let expr1_0 =
-                                                    constructor_sink_load(ctx, pattern10_0)?;
-                                                let expr2_0 = constructor_and_mem(
-                                                    ctx, pattern3_0, expr0_0, &expr1_0,
-                                                )?;
-                                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                                return Some(expr3_0);
-                                            }
-                                        }
-                                    }
-                                }
-                            }
-                            if let Some(pattern8_0) =
-                                C::uimm32shifted_from_inverted_value(ctx, pattern7_0)
-                            {
-                                // Rule at src/isa/s390x/lower.isle line 647.
-                                let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                let expr1_0 = constructor_and_uimm32shifted(
-                                    ctx, pattern3_0, expr0_0, pattern8_0,
-                                )?;
-                                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            if let Some(pattern8_0) =
-                                C::uimm16shifted_from_inverted_value(ctx, pattern7_0)
-                            {
-                                // Rule at src/isa/s390x/lower.isle line 643.
-                                let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                let expr1_0 = constructor_and_uimm16shifted(
-                                    ctx, pattern3_0, expr0_0, pattern8_0,
-                                )?;
-                                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            let pattern8_0 = C::value_type(ctx, pattern7_1);
-                            if let Some(pattern9_0) = C::ty_32_or_64(ctx, pattern8_0) {
-                                if let Some(pattern10_0) = C::sinkable_inst(ctx, pattern7_1) {
-                                    let pattern11_0 = C::inst_data(ctx, pattern10_0);
-                                    if let &InstructionData::Load {
-                                        opcode: ref pattern12_0,
-                                        arg: pattern12_1,
-                                        flags: pattern12_2,
-                                        offset: pattern12_3,
-                                    } = &pattern11_0
-                                    {
-                                        if let &Opcode::Load = pattern12_0 {
-                                            if let Some(()) = C::bigendian(ctx, pattern12_2) {
-                                                // Rule at src/isa/s390x/lower.isle line 651.
-                                                let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                                let expr1_0 =
-                                                    constructor_sink_load(ctx, pattern10_0)?;
-                                                let expr2_0 = constructor_and_mem(
-                                                    ctx, pattern3_0, expr0_0, &expr1_0,
-                                                )?;
-                                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                                return Some(expr3_0);
-                                            }
-                                        }
-                                    }
-                                }
-                            }
-                            if let Some(pattern8_0) =
-                                C::uimm32shifted_from_inverted_value(ctx, pattern7_1)
-                            {
-                                // Rule at src/isa/s390x/lower.isle line 645.
-                                let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                let expr1_0 = constructor_and_uimm32shifted(
-                                    ctx, pattern3_0, expr0_0, pattern8_0,
-                                )?;
-                                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            if let Some(pattern8_0) =
-                                C::uimm16shifted_from_inverted_value(ctx, pattern7_1)
-                            {
-                                // Rule at src/isa/s390x/lower.isle line 641.
-                                let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                let expr1_0 = constructor_and_uimm16shifted(
-                                    ctx, pattern3_0, expr0_0, pattern8_0,
-                                )?;
-                                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            // Rule at src/isa/s390x/lower.isle line 637.
-                            let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                            let expr1_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr2_0 = constructor_and_reg(ctx, pattern3_0, expr0_0, expr1_0)?;
-                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Bor => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            let pattern8_0 = C::value_type(ctx, pattern7_0);
-                            if let Some(pattern9_0) = C::ty_32_or_64(ctx, pattern8_0) {
-                                if let Some(pattern10_0) = C::sinkable_inst(ctx, pattern7_0) {
-                                    let pattern11_0 = C::inst_data(ctx, pattern10_0);
-                                    if let &InstructionData::Load {
-                                        opcode: ref pattern12_0,
-                                        arg: pattern12_1,
-                                        flags: pattern12_2,
-                                        offset: pattern12_3,
-                                    } = &pattern11_0
-                                    {
-                                        if let &Opcode::Load = pattern12_0 {
-                                            if let Some(()) = C::bigendian(ctx, pattern12_2) {
-                                                // Rule at src/isa/s390x/lower.isle line 676.
-                                                let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                                let expr1_0 =
-                                                    constructor_sink_load(ctx, pattern10_0)?;
-                                                let expr2_0 = constructor_or_mem(
-                                                    ctx, pattern3_0, expr0_0, &expr1_0,
-                                                )?;
-                                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                                return Some(expr3_0);
-                                            }
-                                        }
-                                    }
-                                }
-                            }
-                            if let Some(pattern8_0) = C::uimm32shifted_from_value(ctx, pattern7_0) {
-                                // Rule at src/isa/s390x/lower.isle line 670.
-                                let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                let expr1_0 = constructor_or_uimm32shifted(
-                                    ctx, pattern3_0, expr0_0, pattern8_0,
-                                )?;
-                                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            if let Some(pattern8_0) = C::uimm16shifted_from_value(ctx, pattern7_0) {
-                                // Rule at src/isa/s390x/lower.isle line 666.
-                                let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                let expr1_0 = constructor_or_uimm16shifted(
-                                    ctx, pattern3_0, expr0_0, pattern8_0,
-                                )?;
-                                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            let pattern8_0 = C::value_type(ctx, pattern7_1);
-                            if let Some(pattern9_0) = C::ty_32_or_64(ctx, pattern8_0) {
-                                if let Some(pattern10_0) = C::sinkable_inst(ctx, pattern7_1) {
-                                    let pattern11_0 = C::inst_data(ctx, pattern10_0);
-                                    if let &InstructionData::Load {
-                                        opcode: ref pattern12_0,
-                                        arg: pattern12_1,
-                                        flags: pattern12_2,
-                                        offset: pattern12_3,
-                                    } = &pattern11_0
-                                    {
-                                        if let &Opcode::Load = pattern12_0 {
-                                            if let Some(()) = C::bigendian(ctx, pattern12_2) {
-                                                // Rule at src/isa/s390x/lower.isle line 674.
-                                                let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                                let expr1_0 =
-                                                    constructor_sink_load(ctx, pattern10_0)?;
-                                                let expr2_0 = constructor_or_mem(
-                                                    ctx, pattern3_0, expr0_0, &expr1_0,
-                                                )?;
-                                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                                return Some(expr3_0);
-                                            }
-                                        }
-                                    }
-                                }
-                            }
-                            if let Some(pattern8_0) = C::uimm32shifted_from_value(ctx, pattern7_1) {
-                                // Rule at src/isa/s390x/lower.isle line 668.
-                                let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                let expr1_0 = constructor_or_uimm32shifted(
-                                    ctx, pattern3_0, expr0_0, pattern8_0,
-                                )?;
-                                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            if let Some(pattern8_0) = C::uimm16shifted_from_value(ctx, pattern7_1) {
-                                // Rule at src/isa/s390x/lower.isle line 664.
-                                let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                let expr1_0 = constructor_or_uimm16shifted(
-                                    ctx, pattern3_0, expr0_0, pattern8_0,
-                                )?;
-                                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            // Rule at src/isa/s390x/lower.isle line 660.
-                            let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                            let expr1_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr2_0 = constructor_or_reg(ctx, pattern3_0, expr0_0, expr1_0)?;
-                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Bxor => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            let pattern8_0 = C::value_type(ctx, pattern7_0);
-                            if let Some(pattern9_0) = C::ty_32_or_64(ctx, pattern8_0) {
-                                if let Some(pattern10_0) = C::sinkable_inst(ctx, pattern7_0) {
-                                    let pattern11_0 = C::inst_data(ctx, pattern10_0);
-                                    if let &InstructionData::Load {
-                                        opcode: ref pattern12_0,
-                                        arg: pattern12_1,
-                                        flags: pattern12_2,
-                                        offset: pattern12_3,
-                                    } = &pattern11_0
-                                    {
-                                        if let &Opcode::Load = pattern12_0 {
-                                            if let Some(()) = C::bigendian(ctx, pattern12_2) {
-                                                // Rule at src/isa/s390x/lower.isle line 695.
-                                                let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                                let expr1_0 =
-                                                    constructor_sink_load(ctx, pattern10_0)?;
-                                                let expr2_0 = constructor_xor_mem(
-                                                    ctx, pattern3_0, expr0_0, &expr1_0,
-                                                )?;
-                                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                                return Some(expr3_0);
-                                            }
-                                        }
-                                    }
-                                }
-                            }
-                            if let Some(pattern8_0) = C::uimm32shifted_from_value(ctx, pattern7_0) {
-                                // Rule at src/isa/s390x/lower.isle line 689.
-                                let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                let expr1_0 = constructor_xor_uimm32shifted(
-                                    ctx, pattern3_0, expr0_0, pattern8_0,
-                                )?;
-                                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            let pattern8_0 = C::value_type(ctx, pattern7_1);
-                            if let Some(pattern9_0) = C::ty_32_or_64(ctx, pattern8_0) {
-                                if let Some(pattern10_0) = C::sinkable_inst(ctx, pattern7_1) {
-                                    let pattern11_0 = C::inst_data(ctx, pattern10_0);
-                                    if let &InstructionData::Load {
-                                        opcode: ref pattern12_0,
-                                        arg: pattern12_1,
-                                        flags: pattern12_2,
-                                        offset: pattern12_3,
-                                    } = &pattern11_0
-                                    {
-                                        if let &Opcode::Load = pattern12_0 {
-                                            if let Some(()) = C::bigendian(ctx, pattern12_2) {
-                                                // Rule at src/isa/s390x/lower.isle line 693.
-                                                let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                                let expr1_0 =
-                                                    constructor_sink_load(ctx, pattern10_0)?;
-                                                let expr2_0 = constructor_xor_mem(
-                                                    ctx, pattern3_0, expr0_0, &expr1_0,
-                                                )?;
-                                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                                return Some(expr3_0);
-                                            }
-                                        }
-                                    }
-                                }
-                            }
-                            if let Some(pattern8_0) = C::uimm32shifted_from_value(ctx, pattern7_1) {
-                                // Rule at src/isa/s390x/lower.isle line 687.
-                                let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                                let expr1_0 = constructor_xor_uimm32shifted(
-                                    ctx, pattern3_0, expr0_0, pattern8_0,
-                                )?;
-                                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            // Rule at src/isa/s390x/lower.isle line 683.
-                            let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                            let expr1_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr2_0 = constructor_xor_reg(ctx, pattern3_0, expr0_0, expr1_0)?;
-                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Ishl => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            if let Some(pattern8_0) = C::i64_from_value(ctx, pattern7_1) {
-                                // Rule at src/isa/s390x/lower.isle line 482.
-                                let expr0_0 = C::mask_amt_imm(ctx, pattern3_0, pattern8_0);
-                                let expr1_0 = C::put_in_reg(ctx, pattern7_0);
-                                let expr2_0 =
-                                    constructor_lshl_imm(ctx, pattern3_0, expr1_0, expr0_0)?;
-                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            // Rule at src/isa/s390x/lower.isle line 477.
-                            let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr1_0 = constructor_mask_amt_reg(ctx, pattern3_0, expr0_0)?;
-                            let expr2_0 = C::put_in_reg(ctx, pattern7_0);
-                            let expr3_0 = constructor_lshl_reg(ctx, pattern3_0, expr2_0, expr1_0)?;
-                            let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                            return Some(expr4_0);
-                        }
-                        &Opcode::Ushr => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            if let Some(pattern8_0) = C::i64_from_value(ctx, pattern7_1) {
-                                // Rule at src/isa/s390x/lower.isle line 498.
-                                let expr0_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
-                                let expr1_0 = C::mask_amt_imm(ctx, pattern3_0, pattern8_0);
-                                let expr2_0 = constructor_ty_ext32(ctx, pattern3_0)?;
-                                let expr3_0 = constructor_lshr_imm(ctx, expr2_0, expr0_0, expr1_0)?;
-                                let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                                return Some(expr4_0);
-                            }
-                            // Rule at src/isa/s390x/lower.isle line 491.
-                            let expr0_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
-                            let expr1_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr2_0 = constructor_mask_amt_reg(ctx, pattern3_0, expr1_0)?;
-                            let expr3_0 = constructor_ty_ext32(ctx, pattern3_0)?;
-                            let expr4_0 = constructor_lshr_reg(ctx, expr3_0, expr0_0, expr2_0)?;
-                            let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
-                            return Some(expr5_0);
-                        }
-                        &Opcode::Sshr => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            if let Some(pattern8_0) = C::i64_from_value(ctx, pattern7_1) {
-                                // Rule at src/isa/s390x/lower.isle line 515.
-                                let expr0_0 = constructor_put_in_reg_sext32(ctx, pattern7_0)?;
-                                let expr1_0 = C::mask_amt_imm(ctx, pattern3_0, pattern8_0);
-                                let expr2_0 = constructor_ty_ext32(ctx, pattern3_0)?;
-                                let expr3_0 = constructor_ashr_imm(ctx, expr2_0, expr0_0, expr1_0)?;
-                                let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                                return Some(expr4_0);
-                            }
-                            // Rule at src/isa/s390x/lower.isle line 508.
-                            let expr0_0 = constructor_put_in_reg_sext32(ctx, pattern7_0)?;
-                            let expr1_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr2_0 = constructor_mask_amt_reg(ctx, pattern3_0, expr1_0)?;
-                            let expr3_0 = constructor_ty_ext32(ctx, pattern3_0)?;
-                            let expr4_0 = constructor_ashr_reg(ctx, expr3_0, expr0_0, expr2_0)?;
-                            let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
-                            return Some(expr5_0);
-                        }
-                        _ => {}
-                    }
-                }
-                &InstructionData::Unary {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Ineg => {
-                            if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
-                                let pattern8_0 = C::inst_data(ctx, pattern7_0);
-                                if let &InstructionData::Unary {
-                                    opcode: ref pattern9_0,
-                                    arg: pattern9_1,
-                                } = &pattern8_0
-                                {
-                                    if let &Opcode::Sextend = pattern9_0 {
-                                        let pattern11_0 = C::value_type(ctx, pattern9_1);
-                                        if pattern11_0 == I32 {
-                                            // Rule at src/isa/s390x/lower.isle line 193.
-                                            let expr0_0 = C::put_in_reg(ctx, pattern9_1);
-                                            let expr1_0 = constructor_neg_reg_sext32(
-                                                ctx, pattern3_0, expr0_0,
-                                            )?;
-                                            let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                                            return Some(expr2_0);
-                                        }
-                                    }
-                                }
-                            }
-                            // Rule at src/isa/s390x/lower.isle line 189.
-                            let expr0_0 = C::put_in_reg(ctx, pattern5_1);
-                            let expr1_0 = constructor_neg_reg(ctx, pattern3_0, expr0_0)?;
-                            let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                            return Some(expr2_0);
-                        }
-                        &Opcode::Iabs => {
-                            if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
-                                let pattern8_0 = C::inst_data(ctx, pattern7_0);
-                                if let &InstructionData::Unary {
-                                    opcode: ref pattern9_0,
-                                    arg: pattern9_1,
-                                } = &pattern8_0
-                                {
-                                    if let &Opcode::Sextend = pattern9_0 {
-                                        let pattern11_0 = C::value_type(ctx, pattern9_1);
-                                        if pattern11_0 == I32 {
-                                            // Rule at src/isa/s390x/lower.isle line 141.
-                                            let expr0_0 = C::put_in_reg(ctx, pattern9_1);
-                                            let expr1_0 = constructor_abs_reg_sext32(
-                                                ctx, pattern3_0, expr0_0,
-                                            )?;
-                                            let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                                            return Some(expr2_0);
-                                        }
-                                    }
-                                }
-                            }
-                            // Rule at src/isa/s390x/lower.isle line 137.
-                            let expr0_0 = constructor_ty_ext32(ctx, pattern3_0)?;
-                            let expr1_0 = constructor_put_in_reg_sext32(ctx, pattern5_1)?;
-                            let expr2_0 = constructor_abs_reg(ctx, expr0_0, expr1_0)?;
-                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Clz => {
-                            // Rule at src/isa/s390x/lower.isle line 821.
-                            let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern5_1)?;
-                            let expr1_0: i16 = 64;
-                            let expr2_0 = constructor_clz_reg(ctx, expr1_0, expr0_0)?;
-                            let expr3_0 = constructor_regpair_hi(ctx, &expr2_0)?;
-                            let expr4_0 = constructor_clz_offset(ctx, pattern3_0, expr3_0)?;
-                            let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
-                            return Some(expr5_0);
-                        }
-                        &Opcode::Cls => {
-                            // Rule at src/isa/s390x/lower.isle line 836.
-                            let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern5_1)?;
-                            let expr1_0: Type = I64;
-                            let expr2_0: u8 = 63;
-                            let expr3_0 = constructor_ashr_imm(ctx, expr1_0, expr0_0, expr2_0)?;
-                            let expr4_0: Type = I64;
-                            let expr5_0 = constructor_xor_reg(ctx, expr4_0, expr0_0, expr3_0)?;
-                            let expr6_0: i16 = 64;
-                            let expr7_0 = constructor_clz_reg(ctx, expr6_0, expr5_0)?;
-                            let expr8_0 = constructor_regpair_hi(ctx, &expr7_0)?;
-                            let expr9_0 = constructor_clz_offset(ctx, pattern3_0, expr8_0)?;
-                            let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
-                            return Some(expr10_0);
-                        }
-                        &Opcode::Bint => {
-                            // Rule at src/isa/s390x/lower.isle line 804.
-                            let expr0_0 = C::put_in_reg(ctx, pattern5_1);
-                            let expr1_0: u64 = 1;
-                            let expr2_0 = constructor_imm(ctx, pattern3_0, expr1_0)?;
-                            let expr3_0 = constructor_and_reg(ctx, pattern3_0, expr0_0, expr2_0)?;
-                            let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                            return Some(expr4_0);
-                        }
-                        _ => {}
-                    }
-                }
-                _ => {}
-            }
-        }
-        if let Some(pattern3_0) = C::ty_32_or_64(ctx, pattern2_0) {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            match &pattern4_0 {
-                &InstructionData::Binary {
-                    opcode: ref pattern5_0,
-                    args: ref pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Rotl => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            if let Some(pattern8_0) = C::i64_from_value(ctx, pattern7_1) {
-                                // Rule at src/isa/s390x/lower.isle line 528.
-                                let expr0_0 = C::mask_amt_imm(ctx, pattern3_0, pattern8_0);
-                                let expr1_0 = C::put_in_reg(ctx, pattern7_0);
-                                let expr2_0 =
-                                    constructor_rot_imm(ctx, pattern3_0, expr1_0, expr0_0)?;
-                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            // Rule at src/isa/s390x/lower.isle line 524.
-                            let expr0_0 = C::put_in_reg(ctx, pattern7_0);
-                            let expr1_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr2_0 = constructor_rot_reg(ctx, pattern3_0, expr0_0, expr1_0)?;
-                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Rotr => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            if let Some(pattern8_0) = C::i64_from_negated_value(ctx, pattern7_1) {
-                                // Rule at src/isa/s390x/lower.isle line 566.
-                                let expr0_0 = C::mask_amt_imm(ctx, pattern3_0, pattern8_0);
-                                let expr1_0 = C::put_in_reg(ctx, pattern7_0);
-                                let expr2_0 =
-                                    constructor_rot_imm(ctx, pattern3_0, expr1_0, expr0_0)?;
-                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            // Rule at src/isa/s390x/lower.isle line 560.
-                            let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr1_0 = constructor_neg_reg(ctx, pattern3_0, expr0_0)?;
-                            let expr2_0 = C::put_in_reg(ctx, pattern7_0);
-                            let expr3_0 = constructor_rot_reg(ctx, pattern3_0, expr2_0, expr1_0)?;
-                            let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                            return Some(expr4_0);
-                        }
-                        _ => {}
-                    }
-                }
-                &InstructionData::AtomicRmw {
-                    opcode: ref pattern5_0,
-                    args: ref pattern5_1,
-                    flags: pattern5_2,
-                    op: ref pattern5_3,
-                } => {
-                    if let &Opcode::AtomicRmw = pattern5_0 {
-                        let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                        if let Some(()) = C::littleendian(ctx, pattern5_2) {
-                            match pattern5_3 {
-                                &AtomicRmwOp::And => {
-                                    // Rule at src/isa/s390x/lower.isle line 1505.
-                                    let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                    let expr1_0 = constructor_bswap_reg(ctx, pattern3_0, expr0_0)?;
-                                    let expr2_0 = C::zero_offset(ctx);
-                                    let expr3_0 = constructor_lower_address(
-                                        ctx, pattern5_2, pattern7_0, expr2_0,
-                                    )?;
-                                    let expr4_0 = constructor_atomic_rmw_and(
-                                        ctx, pattern3_0, expr1_0, &expr3_0,
-                                    )?;
-                                    let expr5_0 = constructor_bswap_reg(ctx, pattern3_0, expr4_0)?;
-                                    let expr6_0 = constructor_output_reg(ctx, expr5_0)?;
-                                    return Some(expr6_0);
-                                }
-                                &AtomicRmwOp::Or => {
-                                    // Rule at src/isa/s390x/lower.isle line 1517.
-                                    let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                    let expr1_0 = constructor_bswap_reg(ctx, pattern3_0, expr0_0)?;
-                                    let expr2_0 = C::zero_offset(ctx);
-                                    let expr3_0 = constructor_lower_address(
-                                        ctx, pattern5_2, pattern7_0, expr2_0,
-                                    )?;
-                                    let expr4_0 = constructor_atomic_rmw_or(
-                                        ctx, pattern3_0, expr1_0, &expr3_0,
-                                    )?;
-                                    let expr5_0 = constructor_bswap_reg(ctx, pattern3_0, expr4_0)?;
-                                    let expr6_0 = constructor_output_reg(ctx, expr5_0)?;
-                                    return Some(expr6_0);
-                                }
-                                &AtomicRmwOp::Xor => {
-                                    // Rule at src/isa/s390x/lower.isle line 1529.
-                                    let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                    let expr1_0 = constructor_bswap_reg(ctx, pattern3_0, expr0_0)?;
-                                    let expr2_0 = C::zero_offset(ctx);
-                                    let expr3_0 = constructor_lower_address(
-                                        ctx, pattern5_2, pattern7_0, expr2_0,
-                                    )?;
-                                    let expr4_0 = constructor_atomic_rmw_xor(
-                                        ctx, pattern3_0, expr1_0, &expr3_0,
-                                    )?;
-                                    let expr5_0 = constructor_bswap_reg(ctx, pattern3_0, expr4_0)?;
-                                    let expr6_0 = constructor_output_reg(ctx, expr5_0)?;
-                                    return Some(expr6_0);
-                                }
-                                _ => {}
-                            }
-                        }
-                        if let Some(()) = C::bigendian(ctx, pattern5_2) {
-                            match pattern5_3 {
-                                &AtomicRmwOp::Add => {
-                                    // Rule at src/isa/s390x/lower.isle line 1535.
-                                    let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                    let expr1_0 = C::zero_offset(ctx);
-                                    let expr2_0 = constructor_lower_address(
-                                        ctx, pattern5_2, pattern7_0, expr1_0,
-                                    )?;
-                                    let expr3_0 = constructor_atomic_rmw_add(
-                                        ctx, pattern3_0, expr0_0, &expr2_0,
-                                    )?;
-                                    let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                                    return Some(expr4_0);
-                                }
-                                &AtomicRmwOp::And => {
-                                    // Rule at src/isa/s390x/lower.isle line 1499.
-                                    let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                    let expr1_0 = C::zero_offset(ctx);
-                                    let expr2_0 = constructor_lower_address(
-                                        ctx, pattern5_2, pattern7_0, expr1_0,
-                                    )?;
-                                    let expr3_0 = constructor_atomic_rmw_and(
-                                        ctx, pattern3_0, expr0_0, &expr2_0,
-                                    )?;
-                                    let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                                    return Some(expr4_0);
-                                }
-                                &AtomicRmwOp::Or => {
-                                    // Rule at src/isa/s390x/lower.isle line 1511.
-                                    let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                    let expr1_0 = C::zero_offset(ctx);
-                                    let expr2_0 = constructor_lower_address(
-                                        ctx, pattern5_2, pattern7_0, expr1_0,
-                                    )?;
-                                    let expr3_0 = constructor_atomic_rmw_or(
-                                        ctx, pattern3_0, expr0_0, &expr2_0,
-                                    )?;
-                                    let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                                    return Some(expr4_0);
-                                }
-                                &AtomicRmwOp::Sub => {
-                                    // Rule at src/isa/s390x/lower.isle line 1541.
-                                    let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                    let expr1_0 = constructor_neg_reg(ctx, pattern3_0, expr0_0)?;
-                                    let expr2_0 = C::zero_offset(ctx);
-                                    let expr3_0 = constructor_lower_address(
-                                        ctx, pattern5_2, pattern7_0, expr2_0,
-                                    )?;
-                                    let expr4_0 = constructor_atomic_rmw_add(
-                                        ctx, pattern3_0, expr1_0, &expr3_0,
-                                    )?;
-                                    let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
-                                    return Some(expr5_0);
-                                }
-                                &AtomicRmwOp::Xor => {
-                                    // Rule at src/isa/s390x/lower.isle line 1523.
-                                    let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                                    let expr1_0 = C::zero_offset(ctx);
-                                    let expr2_0 = constructor_lower_address(
-                                        ctx, pattern5_2, pattern7_0, expr1_0,
-                                    )?;
-                                    let expr3_0 = constructor_atomic_rmw_xor(
-                                        ctx, pattern3_0, expr0_0, &expr2_0,
-                                    )?;
-                                    let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                                    return Some(expr4_0);
-                                }
-                                _ => {}
-                            }
-                        }
-                        // Rule at src/isa/s390x/lower.isle line 1550.
-                        let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                        let expr1_0 = C::put_in_reg(ctx, pattern7_0);
-                        let expr2_0 = C::inst_builder_new(ctx);
-                        let expr3_0 = constructor_casloop_val_reg(ctx)?;
-                        let expr4_0 = C::writable_reg_to_reg(ctx, expr3_0);
-                        let expr5_0 = constructor_casloop_tmp_reg(ctx)?;
-                        let expr6_0 = constructor_atomic_rmw_body(
-                            ctx, &expr2_0, pattern3_0, pattern5_2, pattern5_3, expr5_0, expr4_0,
-                            expr0_0,
-                        )?;
-                        let expr7_0 = constructor_casloop(
-                            ctx, &expr2_0, pattern3_0, pattern5_2, expr1_0, expr6_0,
-                        )?;
-                        let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
-                        return Some(expr8_0);
-                    }
-                }
-                &InstructionData::AtomicCas {
-                    opcode: ref pattern5_0,
-                    args: ref pattern5_1,
-                    flags: pattern5_2,
-                } => {
-                    if let &Opcode::AtomicCas = pattern5_0 {
-                        let (pattern7_0, pattern7_1, pattern7_2) =
-                            C::unpack_value_array_3(ctx, pattern5_1);
-                        if let Some(()) = C::littleendian(ctx, pattern5_2) {
-                            // Rule at src/isa/s390x/lower.isle line 1762.
-                            let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr1_0 = constructor_bswap_reg(ctx, pattern3_0, expr0_0)?;
-                            let expr2_0 = C::put_in_reg(ctx, pattern7_2);
-                            let expr3_0 = constructor_bswap_reg(ctx, pattern3_0, expr2_0)?;
-                            let expr4_0 = C::zero_offset(ctx);
-                            let expr5_0 =
-                                constructor_lower_address(ctx, pattern5_2, pattern7_0, expr4_0)?;
-                            let expr6_0 = constructor_atomic_cas_impl(
-                                ctx, pattern3_0, expr1_0, expr3_0, &expr5_0,
-                            )?;
-                            let expr7_0 = constructor_bswap_reg(ctx, pattern3_0, expr6_0)?;
-                            let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
-                            return Some(expr8_0);
-                        }
-                        if let Some(()) = C::bigendian(ctx, pattern5_2) {
-                            // Rule at src/isa/s390x/lower.isle line 1755.
-                            let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr1_0 = C::put_in_reg(ctx, pattern7_2);
-                            let expr2_0 = C::zero_offset(ctx);
-                            let expr3_0 =
-                                constructor_lower_address(ctx, pattern5_2, pattern7_0, expr2_0)?;
-                            let expr4_0 = constructor_atomic_cas_impl(
-                                ctx, pattern3_0, expr0_0, expr1_0, &expr3_0,
-                            )?;
-                            let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
-                            return Some(expr5_0);
-                        }
-                    }
-                }
-                &InstructionData::Unary {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::FcvtToUint => {
-                            let pattern7_0 = C::value_type(ctx, pattern5_1);
-                            // Rule at src/isa/s390x/lower.isle line 1057.
-                            let expr0_0 = C::put_in_reg(ctx, pattern5_1);
-                            let expr1_0 = constructor_fcmp_reg(ctx, pattern7_0, expr0_0, expr0_0)?;
-                            let expr2_0 = FloatCC::Unordered;
-                            let expr3_0 = C::floatcc_as_cond(ctx, &expr2_0);
-                            let expr4_0 = C::trap_code_bad_conversion_to_integer(ctx);
-                            let expr5_0 = constructor_trap_if(ctx, &expr1_0, &expr3_0, &expr4_0)?;
-                            let expr6_0 = constructor_fcvt_to_uint_reg_with_flags(
-                                ctx, pattern3_0, pattern7_0, expr0_0,
-                            )?;
-                            let expr7_0 = FloatCC::Unordered;
-                            let expr8_0 = C::floatcc_as_cond(ctx, &expr7_0);
-                            let expr9_0 = C::trap_code_integer_overflow(ctx);
-                            let expr10_0 = constructor_trap_if(ctx, &expr6_0, &expr8_0, &expr9_0)?;
-                            let expr11_0 = constructor_output_reg(ctx, expr10_0)?;
-                            return Some(expr11_0);
-                        }
-                        &Opcode::FcvtToUintSat => {
-                            let pattern7_0 = C::value_type(ctx, pattern5_1);
-                            // Rule at src/isa/s390x/lower.isle line 1098.
-                            let expr0_0 = C::put_in_reg(ctx, pattern5_1);
-                            let expr1_0 =
-                                constructor_fcvt_to_uint_reg(ctx, pattern3_0, pattern7_0, expr0_0)?;
-                            let expr2_0 = constructor_fcmp_reg(ctx, pattern7_0, expr0_0, expr0_0)?;
-                            let expr3_0 = FloatCC::Unordered;
-                            let expr4_0 = C::floatcc_as_cond(ctx, &expr3_0);
-                            let expr5_0: i16 = 0;
-                            let expr6_0 =
-                                constructor_cmov_imm(ctx, pattern3_0, &expr4_0, expr5_0, expr1_0)?;
-                            let expr7_0 = constructor_with_flags_reg(ctx, &expr2_0, &expr6_0)?;
-                            let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
-                            return Some(expr8_0);
-                        }
-                        &Opcode::FcvtToSint => {
-                            let pattern7_0 = C::value_type(ctx, pattern5_1);
-                            // Rule at src/isa/s390x/lower.isle line 1078.
-                            let expr0_0 = C::put_in_reg(ctx, pattern5_1);
-                            let expr1_0 = constructor_fcmp_reg(ctx, pattern7_0, expr0_0, expr0_0)?;
-                            let expr2_0 = FloatCC::Unordered;
-                            let expr3_0 = C::floatcc_as_cond(ctx, &expr2_0);
-                            let expr4_0 = C::trap_code_bad_conversion_to_integer(ctx);
-                            let expr5_0 = constructor_trap_if(ctx, &expr1_0, &expr3_0, &expr4_0)?;
-                            let expr6_0 = constructor_fcvt_to_sint_reg_with_flags(
-                                ctx, pattern3_0, pattern7_0, expr0_0,
-                            )?;
-                            let expr7_0 = FloatCC::Unordered;
-                            let expr8_0 = C::floatcc_as_cond(ctx, &expr7_0);
-                            let expr9_0 = C::trap_code_integer_overflow(ctx);
-                            let expr10_0 = constructor_trap_if(ctx, &expr6_0, &expr8_0, &expr9_0)?;
-                            let expr11_0 = constructor_output_reg(ctx, expr10_0)?;
-                            return Some(expr11_0);
-                        }
-                        &Opcode::FcvtToSintSat => {
-                            let pattern7_0 = C::value_type(ctx, pattern5_1);
-                            // Rule at src/isa/s390x/lower.isle line 1115.
-                            let expr0_0 = C::put_in_reg(ctx, pattern5_1);
-                            let expr1_0 =
-                                constructor_fcvt_to_sint_reg(ctx, pattern3_0, pattern7_0, expr0_0)?;
-                            let expr2_0 = constructor_fcmp_reg(ctx, pattern7_0, expr0_0, expr0_0)?;
-                            let expr3_0 = FloatCC::Unordered;
-                            let expr4_0 = C::floatcc_as_cond(ctx, &expr3_0);
-                            let expr5_0: i16 = 0;
-                            let expr6_0 =
-                                constructor_cmov_imm(ctx, pattern3_0, &expr4_0, expr5_0, expr1_0)?;
-                            let expr7_0 = constructor_with_flags_reg(ctx, &expr2_0, &expr6_0)?;
-                            let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
-                            return Some(expr8_0);
-                        }
-                        _ => {}
-                    }
-                }
-                _ => {}
-            }
-        }
-        if let Some(pattern3_0) = C::ty_8_or_16(ctx, pattern2_0) {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            match &pattern4_0 {
-                &InstructionData::Binary {
-                    opcode: ref pattern5_0,
-                    args: ref pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Umulhi => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/s390x/lower.isle line 245.
-                            let expr0_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_reg_zext32(ctx, pattern7_1)?;
-                            let expr2_0: Type = I32;
-                            let expr3_0 = constructor_mul_reg(ctx, expr2_0, expr0_0, expr1_0)?;
-                            let expr4_0: Type = I32;
-                            let expr5_0 = C::ty_bits(ctx, pattern3_0);
-                            let expr6_0 = constructor_lshr_imm(ctx, expr4_0, expr3_0, expr5_0)?;
-                            let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
-                            return Some(expr7_0);
-                        }
-                        &Opcode::Smulhi => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/s390x/lower.isle line 267.
-                            let expr0_0 = constructor_put_in_reg_sext32(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_reg_sext32(ctx, pattern7_1)?;
-                            let expr2_0: Type = I32;
-                            let expr3_0 = constructor_mul_reg(ctx, expr2_0, expr0_0, expr1_0)?;
-                            let expr4_0: Type = I32;
-                            let expr5_0 = C::ty_bits(ctx, pattern3_0);
-                            let expr6_0 = constructor_ashr_imm(ctx, expr4_0, expr3_0, expr5_0)?;
-                            let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
-                            return Some(expr7_0);
-                        }
-                        &Opcode::Rotl => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            if let Some(pattern8_0) = C::i64_from_value(ctx, pattern7_1) {
-                                if let Some(pattern9_0) = C::i64_from_negated_value(ctx, pattern7_1)
-                                {
-                                    // Rule at src/isa/s390x/lower.isle line 546.
-                                    let expr0_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
-                                    let expr1_0 = constructor_ty_ext32(ctx, pattern3_0)?;
-                                    let expr2_0 = C::mask_amt_imm(ctx, pattern3_0, pattern8_0);
-                                    let expr3_0 = C::mask_amt_imm(ctx, pattern3_0, pattern9_0);
-                                    let expr4_0 =
-                                        constructor_lshl_imm(ctx, expr1_0, expr0_0, expr2_0)?;
-                                    let expr5_0 =
-                                        constructor_lshr_imm(ctx, expr1_0, expr0_0, expr3_0)?;
-                                    let expr6_0 =
-                                        constructor_or_reg(ctx, pattern3_0, expr4_0, expr5_0)?;
-                                    let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
-                                    return Some(expr7_0);
-                                }
-                            }
-                            // Rule at src/isa/s390x/lower.isle line 534.
-                            let expr0_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_ty_ext32(ctx, pattern3_0)?;
-                            let expr2_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr3_0 = constructor_neg_reg(ctx, pattern3_0, expr2_0)?;
-                            let expr4_0 = constructor_mask_amt_reg(ctx, pattern3_0, expr2_0)?;
-                            let expr5_0 = constructor_mask_amt_reg(ctx, pattern3_0, expr3_0)?;
-                            let expr6_0 = constructor_lshl_reg(ctx, expr1_0, expr0_0, expr4_0)?;
-                            let expr7_0 = constructor_lshr_reg(ctx, expr1_0, expr0_0, expr5_0)?;
-                            let expr8_0 = constructor_or_reg(ctx, pattern3_0, expr6_0, expr7_0)?;
-                            let expr9_0 = constructor_output_reg(ctx, expr8_0)?;
-                            return Some(expr9_0);
-                        }
-                        &Opcode::Rotr => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            if let Some(pattern8_0) = C::i64_from_value(ctx, pattern7_1) {
-                                if let Some(pattern9_0) = C::i64_from_negated_value(ctx, pattern7_1)
-                                {
-                                    // Rule at src/isa/s390x/lower.isle line 584.
-                                    let expr0_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
-                                    let expr1_0 = constructor_ty_ext32(ctx, pattern3_0)?;
-                                    let expr2_0 = C::mask_amt_imm(ctx, pattern3_0, pattern8_0);
-                                    let expr3_0 = C::mask_amt_imm(ctx, pattern3_0, pattern9_0);
-                                    let expr4_0 =
-                                        constructor_lshl_imm(ctx, expr1_0, expr0_0, expr3_0)?;
-                                    let expr5_0 =
-                                        constructor_lshr_imm(ctx, expr1_0, expr0_0, expr2_0)?;
-                                    let expr6_0 =
-                                        constructor_or_reg(ctx, pattern3_0, expr4_0, expr5_0)?;
-                                    let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
-                                    return Some(expr7_0);
-                                }
-                            }
-                            // Rule at src/isa/s390x/lower.isle line 572.
-                            let expr0_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_ty_ext32(ctx, pattern3_0)?;
-                            let expr2_0 = C::put_in_reg(ctx, pattern7_1);
-                            let expr3_0 = constructor_neg_reg(ctx, pattern3_0, expr2_0)?;
-                            let expr4_0 = constructor_mask_amt_reg(ctx, pattern3_0, expr2_0)?;
-                            let expr5_0 = constructor_mask_amt_reg(ctx, pattern3_0, expr3_0)?;
-                            let expr6_0 = constructor_lshl_reg(ctx, expr1_0, expr0_0, expr5_0)?;
-                            let expr7_0 = constructor_lshr_reg(ctx, expr1_0, expr0_0, expr4_0)?;
-                            let expr8_0 = constructor_or_reg(ctx, pattern3_0, expr6_0, expr7_0)?;
-                            let expr9_0 = constructor_output_reg(ctx, expr8_0)?;
-                            return Some(expr9_0);
-                        }
-                        _ => {}
-                    }
-                }
-                &InstructionData::AtomicRmw {
-                    opcode: ref pattern5_0,
-                    args: ref pattern5_1,
-                    flags: pattern5_2,
-                    op: ref pattern5_3,
-                } => {
-                    if let &Opcode::AtomicRmw = pattern5_0 {
-                        let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                        // Rule at src/isa/s390x/lower.isle line 1562.
-                        let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                        let expr1_0 = C::put_in_reg(ctx, pattern7_0);
-                        let expr2_0 = constructor_casloop_bitshift(ctx, expr1_0)?;
-                        let expr3_0 = constructor_casloop_aligned_addr(ctx, expr1_0)?;
-                        let expr4_0 = C::inst_builder_new(ctx);
-                        let expr5_0 = constructor_casloop_val_reg(ctx)?;
-                        let expr6_0 = C::writable_reg_to_reg(ctx, expr5_0);
-                        let expr7_0 = constructor_casloop_rotate_in(
-                            ctx, &expr4_0, pattern3_0, pattern5_2, expr2_0, expr6_0,
-                        )?;
-                        let expr8_0 = constructor_casloop_tmp_reg(ctx)?;
-                        let expr9_0 = constructor_atomic_rmw_body(
-                            ctx, &expr4_0, pattern3_0, pattern5_2, pattern5_3, expr8_0, expr7_0,
-                            expr0_0,
-                        )?;
-                        let expr10_0 = constructor_casloop_rotate_out(
-                            ctx, &expr4_0, pattern3_0, pattern5_2, expr2_0, expr9_0,
-                        )?;
-                        let expr11_0 = constructor_casloop_subword(
-                            ctx, &expr4_0, pattern3_0, pattern5_2, expr3_0, expr2_0, expr10_0,
-                        )?;
-                        let expr12_0 = constructor_output_reg(ctx, expr11_0)?;
-                        return Some(expr12_0);
-                    }
-                }
-                &InstructionData::AtomicCas {
-                    opcode: ref pattern5_0,
-                    args: ref pattern5_1,
-                    flags: pattern5_2,
-                } => {
-                    if let &Opcode::AtomicCas = pattern5_0 {
-                        let (pattern7_0, pattern7_1, pattern7_2) =
-                            C::unpack_value_array_3(ctx, pattern5_1);
-                        // Rule at src/isa/s390x/lower.isle line 1769.
-                        let expr0_0 = C::put_in_reg(ctx, pattern7_1);
-                        let expr1_0 = C::put_in_reg(ctx, pattern7_2);
-                        let expr2_0 = C::put_in_reg(ctx, pattern7_0);
-                        let expr3_0 = constructor_casloop_bitshift(ctx, expr2_0)?;
-                        let expr4_0 = constructor_casloop_aligned_addr(ctx, expr2_0)?;
-                        let expr5_0 = C::inst_builder_new(ctx);
-                        let expr6_0 = constructor_casloop_val_reg(ctx)?;
-                        let expr7_0 = C::writable_reg_to_reg(ctx, expr6_0);
-                        let expr8_0 = constructor_casloop_rotate_in(
-                            ctx, &expr5_0, pattern3_0, pattern5_2, expr3_0, expr7_0,
-                        )?;
-                        let expr9_0 = constructor_casloop_tmp_reg(ctx)?;
-                        let expr10_0 = constructor_atomic_cas_body(
-                            ctx, &expr5_0, pattern3_0, pattern5_2, expr9_0, expr8_0, expr0_0,
-                            expr1_0,
-                        )?;
-                        let expr11_0 = constructor_casloop_rotate_out(
-                            ctx, &expr5_0, pattern3_0, pattern5_2, expr3_0, expr10_0,
-                        )?;
-                        let expr12_0 = constructor_casloop_subword(
-                            ctx, &expr5_0, pattern3_0, pattern5_2, expr4_0, expr3_0, expr11_0,
-                        )?;
-                        let expr13_0 = constructor_output_reg(ctx, expr12_0)?;
-                        return Some(expr13_0);
-                    }
-                }
-                _ => {}
-            }
-        }
-        if let Some(pattern3_0) = C::gpr32_ty(ctx, pattern2_0) {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            match &pattern4_0 {
-                &InstructionData::Unary {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Ctz => {
-                            // Rule at src/isa/s390x/lower.isle line 859.
-                            let expr0_0: Type = I64;
-                            let expr1_0 = C::put_in_reg(ctx, pattern5_1);
-                            let expr2_0 = constructor_ctz_guardbit(ctx, pattern3_0)?;
-                            let expr3_0 =
-                                constructor_or_uimm16shifted(ctx, expr0_0, expr1_0, expr2_0)?;
-                            let expr4_0: Type = I64;
-                            let expr5_0: Type = I64;
-                            let expr6_0 = constructor_neg_reg(ctx, expr5_0, expr3_0)?;
-                            let expr7_0 = constructor_and_reg(ctx, expr4_0, expr3_0, expr6_0)?;
-                            let expr8_0: i16 = 64;
-                            let expr9_0 = constructor_clz_reg(ctx, expr8_0, expr7_0)?;
-                            let expr10_0: u64 = 63;
-                            let expr11_0 = constructor_imm(ctx, pattern3_0, expr10_0)?;
-                            let expr12_0 = constructor_regpair_hi(ctx, &expr9_0)?;
-                            let expr13_0 =
-                                constructor_sub_reg(ctx, pattern3_0, expr11_0, expr12_0)?;
-                            let expr14_0 = constructor_output_reg(ctx, expr13_0)?;
-                            return Some(expr14_0);
-                        }
-                        &Opcode::Uextend => {
-                            // Rule at src/isa/s390x/lower.isle line 603.
-                            let expr0_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
-                            let expr1_0 = constructor_output_reg(ctx, expr0_0)?;
-                            return Some(expr1_0);
-                        }
-                        &Opcode::Sextend => {
-                            // Rule at src/isa/s390x/lower.isle line 614.
-                            let expr0_0 = constructor_put_in_reg_sext32(ctx, pattern5_1)?;
-                            let expr1_0 = constructor_output_reg(ctx, expr0_0)?;
-                            return Some(expr1_0);
-                        }
-                        _ => {}
-                    }
-                }
-                &InstructionData::Load {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                    flags: pattern5_2,
-                    offset: pattern5_3,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Uload8 => {
-                            // Rule at src/isa/s390x/lower.isle line 1251.
-                            let expr0_0: Type = I8;
-                            let expr1_0 =
-                                constructor_lower_address(ctx, pattern5_2, pattern5_1, pattern5_3)?;
-                            let expr2_0 = constructor_zext32_mem(ctx, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Sload8 => {
-                            // Rule at src/isa/s390x/lower.isle line 1262.
-                            let expr0_0: Type = I8;
-                            let expr1_0 =
-                                constructor_lower_address(ctx, pattern5_2, pattern5_1, pattern5_3)?;
-                            let expr2_0 = constructor_sext32_mem(ctx, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Uload16 => {
-                            if let Some(()) = C::littleendian(ctx, pattern5_2) {
-                                // Rule at src/isa/s390x/lower.isle line 1278.
-                                let expr0_0 = constructor_lower_address(
-                                    ctx, pattern5_2, pattern5_1, pattern5_3,
-                                )?;
-                                let expr1_0 = constructor_loadrev16(ctx, &expr0_0)?;
-                                let expr2_0: Type = I16;
-                                let expr3_0 = constructor_zext32_reg(ctx, expr2_0, expr1_0)?;
-                                let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                                return Some(expr4_0);
-                            }
-                            if let Some(()) = C::bigendian(ctx, pattern5_2) {
-                                // Rule at src/isa/s390x/lower.isle line 1273.
-                                let expr0_0: Type = I16;
-                                let expr1_0 = constructor_lower_address(
-                                    ctx, pattern5_2, pattern5_1, pattern5_3,
-                                )?;
-                                let expr2_0 = constructor_zext32_mem(ctx, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                        }
-                        &Opcode::Sload16 => {
-                            if let Some(()) = C::littleendian(ctx, pattern5_2) {
-                                // Rule at src/isa/s390x/lower.isle line 1303.
-                                let expr0_0 = constructor_lower_address(
-                                    ctx, pattern5_2, pattern5_1, pattern5_3,
-                                )?;
-                                let expr1_0 = constructor_loadrev16(ctx, &expr0_0)?;
-                                let expr2_0: Type = I16;
-                                let expr3_0 = constructor_sext32_reg(ctx, expr2_0, expr1_0)?;
-                                let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                                return Some(expr4_0);
-                            }
-                            if let Some(()) = C::bigendian(ctx, pattern5_2) {
-                                // Rule at src/isa/s390x/lower.isle line 1298.
-                                let expr0_0: Type = I16;
-                                let expr1_0 = constructor_lower_address(
-                                    ctx, pattern5_2, pattern5_1, pattern5_3,
-                                )?;
-                                let expr2_0 = constructor_sext32_mem(ctx, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                        }
-                        _ => {}
-                    }
-                }
-                _ => {}
-            }
-        }
-        if let Some(pattern3_0) = C::gpr64_ty(ctx, pattern2_0) {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            match &pattern4_0 {
-                &InstructionData::Unary {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Ctz => {
-                            // Rule at src/isa/s390x/lower.isle line 874.
-                            let expr0_0 = C::put_in_reg(ctx, pattern5_1);
-                            let expr1_0: Type = I64;
-                            let expr2_0: Type = I64;
-                            let expr3_0 = constructor_neg_reg(ctx, expr2_0, expr0_0)?;
-                            let expr4_0 = constructor_and_reg(ctx, expr1_0, expr0_0, expr3_0)?;
-                            let expr5_0: i16 = -1;
-                            let expr6_0 = constructor_clz_reg(ctx, expr5_0, expr4_0)?;
-                            let expr7_0: Type = I64;
-                            let expr8_0: Type = I64;
-                            let expr9_0: u64 = 63;
-                            let expr10_0 = constructor_imm(ctx, expr8_0, expr9_0)?;
-                            let expr11_0 = constructor_regpair_hi(ctx, &expr6_0)?;
-                            let expr12_0 = constructor_sub_reg(ctx, expr7_0, expr10_0, expr11_0)?;
-                            let expr13_0 = constructor_output_reg(ctx, expr12_0)?;
-                            return Some(expr13_0);
-                        }
-                        &Opcode::Uextend => {
-                            // Rule at src/isa/s390x/lower.isle line 607.
-                            let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern5_1)?;
-                            let expr1_0 = constructor_output_reg(ctx, expr0_0)?;
-                            return Some(expr1_0);
-                        }
-                        &Opcode::Sextend => {
-                            // Rule at src/isa/s390x/lower.isle line 618.
-                            let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern5_1)?;
-                            let expr1_0 = constructor_output_reg(ctx, expr0_0)?;
-                            return Some(expr1_0);
-                        }
-                        _ => {}
-                    }
-                }
-                &InstructionData::Load {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                    flags: pattern5_2,
-                    offset: pattern5_3,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Uload8 => {
-                            // Rule at src/isa/s390x/lower.isle line 1255.
-                            let expr0_0: Type = I8;
-                            let expr1_0 =
-                                constructor_lower_address(ctx, pattern5_2, pattern5_1, pattern5_3)?;
-                            let expr2_0 = constructor_zext64_mem(ctx, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Sload8 => {
-                            // Rule at src/isa/s390x/lower.isle line 1266.
-                            let expr0_0: Type = I8;
-                            let expr1_0 =
-                                constructor_lower_address(ctx, pattern5_2, pattern5_1, pattern5_3)?;
-                            let expr2_0 = constructor_sext64_mem(ctx, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Uload16 => {
-                            if let Some(()) = C::littleendian(ctx, pattern5_2) {
-                                // Rule at src/isa/s390x/lower.isle line 1289.
-                                let expr0_0 = constructor_lower_address(
-                                    ctx, pattern5_2, pattern5_1, pattern5_3,
-                                )?;
-                                let expr1_0 = constructor_loadrev16(ctx, &expr0_0)?;
-                                let expr2_0: Type = I16;
-                                let expr3_0 = constructor_zext64_reg(ctx, expr2_0, expr1_0)?;
-                                let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                                return Some(expr4_0);
-                            }
-                            if let Some(()) = C::bigendian(ctx, pattern5_2) {
-                                // Rule at src/isa/s390x/lower.isle line 1284.
-                                let expr0_0: Type = I16;
-                                let expr1_0 = constructor_lower_address(
-                                    ctx, pattern5_2, pattern5_1, pattern5_3,
-                                )?;
-                                let expr2_0 = constructor_zext64_mem(ctx, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                        }
-                        &Opcode::Sload16 => {
-                            if let Some(()) = C::littleendian(ctx, pattern5_2) {
-                                // Rule at src/isa/s390x/lower.isle line 1314.
-                                let expr0_0 = constructor_lower_address(
-                                    ctx, pattern5_2, pattern5_1, pattern5_3,
-                                )?;
-                                let expr1_0 = constructor_loadrev16(ctx, &expr0_0)?;
-                                let expr2_0: Type = I16;
-                                let expr3_0 = constructor_sext64_reg(ctx, expr2_0, expr1_0)?;
-                                let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                                return Some(expr4_0);
-                            }
-                            if let Some(()) = C::bigendian(ctx, pattern5_2) {
-                                // Rule at src/isa/s390x/lower.isle line 1309.
-                                let expr0_0: Type = I16;
-                                let expr1_0 = constructor_lower_address(
-                                    ctx, pattern5_2, pattern5_1, pattern5_3,
-                                )?;
-                                let expr2_0 = constructor_sext64_mem(ctx, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                        }
-                        &Opcode::Uload32 => {
-                            if let Some(()) = C::littleendian(ctx, pattern5_2) {
-                                // Rule at src/isa/s390x/lower.isle line 1328.
-                                let expr0_0 = constructor_lower_address(
-                                    ctx, pattern5_2, pattern5_1, pattern5_3,
-                                )?;
-                                let expr1_0 = constructor_loadrev32(ctx, &expr0_0)?;
-                                let expr2_0: Type = I32;
-                                let expr3_0 = constructor_zext64_reg(ctx, expr2_0, expr1_0)?;
-                                let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                                return Some(expr4_0);
-                            }
-                            if let Some(()) = C::bigendian(ctx, pattern5_2) {
-                                // Rule at src/isa/s390x/lower.isle line 1323.
-                                let expr0_0: Type = I32;
-                                let expr1_0 = constructor_lower_address(
-                                    ctx, pattern5_2, pattern5_1, pattern5_3,
-                                )?;
-                                let expr2_0 = constructor_zext64_mem(ctx, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                        }
-                        &Opcode::Sload32 => {
-                            if let Some(()) = C::littleendian(ctx, pattern5_2) {
-                                // Rule at src/isa/s390x/lower.isle line 1342.
-                                let expr0_0 = constructor_lower_address(
-                                    ctx, pattern5_2, pattern5_1, pattern5_3,
-                                )?;
-                                let expr1_0 = constructor_loadrev32(ctx, &expr0_0)?;
-                                let expr2_0: Type = I32;
-                                let expr3_0 = constructor_sext64_reg(ctx, expr2_0, expr1_0)?;
-                                let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
-                                return Some(expr4_0);
-                            }
-                            if let Some(()) = C::bigendian(ctx, pattern5_2) {
-                                // Rule at src/isa/s390x/lower.isle line 1337.
-                                let expr0_0: Type = I32;
-                                let expr1_0 = constructor_lower_address(
-                                    ctx, pattern5_2, pattern5_1, pattern5_3,
-                                )?;
-                                let expr2_0 = constructor_sext64_mem(ctx, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                        }
-                        _ => {}
-                    }
-                }
-                _ => {}
-            }
-        }
-    }
-    return None;
-}
-
-// Generated as internal constructor for term lower_branch.
-pub fn constructor_lower_branch<C: Context>(
-    ctx: &mut C,
-    arg0: Inst,
-    arg1: &VecMachLabel,
-) -> Option<InstOutput> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = C::inst_data(ctx, pattern0_0);
-    match &pattern1_0 {
-        &InstructionData::BranchTable {
-            opcode: ref pattern2_0,
-            arg: pattern2_1,
-            destination: pattern2_2,
-            table: pattern2_3,
-        } => {
-            if let &Opcode::BrTable = pattern2_0 {
-                let pattern4_0 = arg1;
-                // Rule at src/isa/s390x/lower.isle line 2076.
-                let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern2_1)?;
-                let expr1_0: Type = I64;
-                let expr2_0 = C::vec_length_minus1(ctx, pattern4_0);
-                let expr3_0 = constructor_icmpu_uimm32(ctx, expr1_0, expr0_0, expr2_0)?;
-                let expr4_0 = IntCC::UnsignedGreaterThanOrEqual;
-                let expr5_0 = C::intcc_as_cond(ctx, &expr4_0);
-                let expr6_0 = constructor_bool(ctx, &expr3_0, &expr5_0)?;
-                let expr7_0: u8 = 0;
-                let expr8_0 = C::vec_element(ctx, pattern4_0, expr7_0);
-                let expr9_0 = constructor_oneway_cond_br_bool(ctx, &expr6_0, expr8_0)?;
-                let expr10_0 = constructor_side_effect(ctx, &expr9_0)?;
-                let expr11_0: Type = I64;
-                let expr12_0: u8 = 2;
-                let expr13_0 = constructor_lshl_imm(ctx, expr11_0, expr0_0, expr12_0)?;
-                let expr14_0 = constructor_jt_sequence(ctx, expr13_0, pattern4_0)?;
-                let expr15_0 = constructor_side_effect(ctx, &expr14_0)?;
-                return Some(expr15_0);
-            }
-        }
-        &InstructionData::Branch {
-            opcode: ref pattern2_0,
-            args: pattern2_1,
-            destination: pattern2_2,
-        } => {
-            match pattern2_0 {
-                &Opcode::Brz => {
-                    let pattern4_0 = C::value_list_slice(ctx, pattern2_1);
-                    if let Some((pattern5_0, pattern5_1)) = C::value_slice_unwrap(ctx, pattern4_0) {
-                        let pattern6_0 = arg1;
-                        // Rule at src/isa/s390x/lower.isle line 2109.
-                        let expr0_0 = constructor_value_nonzero(ctx, pattern5_0)?;
-                        let expr1_0 = constructor_invert_bool(ctx, &expr0_0)?;
-                        let expr2_0: u8 = 0;
-                        let expr3_0 = C::vec_element(ctx, pattern6_0, expr2_0);
-                        let expr4_0: u8 = 1;
-                        let expr5_0 = C::vec_element(ctx, pattern6_0, expr4_0);
-                        let expr6_0 = constructor_cond_br_bool(ctx, &expr1_0, expr3_0, expr5_0)?;
-                        let expr7_0 = constructor_side_effect(ctx, &expr6_0)?;
-                        return Some(expr7_0);
-                    }
-                }
-                &Opcode::Brnz => {
-                    let pattern4_0 = C::value_list_slice(ctx, pattern2_1);
-                    if let Some((pattern5_0, pattern5_1)) = C::value_slice_unwrap(ctx, pattern4_0) {
-                        let pattern6_0 = arg1;
-                        // Rule at src/isa/s390x/lower.isle line 2120.
-                        let expr0_0 = constructor_value_nonzero(ctx, pattern5_0)?;
-                        let expr1_0: u8 = 0;
-                        let expr2_0 = C::vec_element(ctx, pattern6_0, expr1_0);
-                        let expr3_0: u8 = 1;
-                        let expr4_0 = C::vec_element(ctx, pattern6_0, expr3_0);
-                        let expr5_0 = constructor_cond_br_bool(ctx, &expr0_0, expr2_0, expr4_0)?;
-                        let expr6_0 = constructor_side_effect(ctx, &expr5_0)?;
-                        return Some(expr6_0);
-                    }
-                }
-                _ => {}
-            }
-        }
-        &InstructionData::Jump {
-            opcode: ref pattern2_0,
-            args: pattern2_1,
-            destination: pattern2_2,
-        } => {
-            if let &Opcode::Jump = pattern2_0 {
-                let pattern4_0 = C::value_list_slice(ctx, pattern2_1);
-                let pattern5_0 = arg1;
-                // Rule at src/isa/s390x/lower.isle line 2068.
-                let expr0_0: u8 = 0;
-                let expr1_0 = C::vec_element(ctx, pattern5_0, expr0_0);
-                let expr2_0 = constructor_jump_impl(ctx, expr1_0)?;
-                let expr3_0 = constructor_side_effect(ctx, &expr2_0)?;
-                return Some(expr3_0);
-            }
-        }
-        &InstructionData::BranchInt {
-            opcode: ref pattern2_0,
-            args: pattern2_1,
-            cond: ref pattern2_2,
-            destination: pattern2_3,
-        } => {
-            if let &Opcode::Brif = pattern2_0 {
-                let pattern4_0 = C::value_list_slice(ctx, pattern2_1);
-                if let Some((pattern5_0, pattern5_1)) = C::value_slice_unwrap(ctx, pattern4_0) {
-                    if let Some(pattern6_0) = C::def_inst(ctx, pattern5_0) {
-                        let pattern7_0 = C::inst_data(ctx, pattern6_0);
-                        if let &InstructionData::Binary {
-                            opcode: ref pattern8_0,
-                            args: ref pattern8_1,
-                        } = &pattern7_0
-                        {
-                            if let &Opcode::Ifcmp = pattern8_0 {
-                                let (pattern10_0, pattern10_1) =
-                                    C::unpack_value_array_2(ctx, pattern8_1);
-                                let pattern11_0 = arg1;
-                                // Rule at src/isa/s390x/lower.isle line 2131.
-                                let expr0_0: bool = false;
-                                let expr1_0 = constructor_icmp_val(
-                                    ctx,
-                                    expr0_0,
-                                    pattern2_2,
-                                    pattern10_0,
-                                    pattern10_1,
-                                )?;
-                                let expr2_0: u8 = 0;
-                                let expr3_0 = C::vec_element(ctx, pattern11_0, expr2_0);
-                                let expr4_0: u8 = 1;
-                                let expr5_0 = C::vec_element(ctx, pattern11_0, expr4_0);
-                                let expr6_0 =
-                                    constructor_cond_br_bool(ctx, &expr1_0, expr3_0, expr5_0)?;
-                                let expr7_0 = constructor_side_effect(ctx, &expr6_0)?;
-                                return Some(expr7_0);
-                            }
-                        }
-                    }
-                }
-            }
-        }
-        _ => {}
-    }
-    return None;
-}
-
-// Generated as internal constructor for term output_ifcout.
-pub fn constructor_output_ifcout<C: Context>(ctx: &mut C, arg0: Reg) -> Option<InstOutput> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/s390x/lower.isle line 154.
-    let expr0_0 = C::value_reg(ctx, pattern0_0);
-    let expr1_0 = C::value_regs_invalid(ctx);
-    let expr2_0 = C::output_pair(ctx, expr0_0, expr1_0);
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term zero_divisor_check_needed.
-pub fn constructor_zero_divisor_check_needed<C: Context>(ctx: &mut C, arg0: Value) -> Option<bool> {
-    let pattern0_0 = arg0;
-    if let Some(pattern1_0) = C::i64_from_value(ctx, pattern0_0) {
-        let pattern2_0 = 0;
-        if let Some(pattern3_0) = C::i64_nonequal(ctx, pattern1_0, pattern2_0) {
-            // Rule at src/isa/s390x/lower.isle line 344.
-            let expr0_0: bool = false;
-            return Some(expr0_0);
-        }
-    }
-    let pattern1_0 = C::value_type(ctx, pattern0_0);
-    if let Some(()) = C::allow_div_traps(ctx, pattern1_0) {
-        // Rule at src/isa/s390x/lower.isle line 345.
-        let expr0_0: bool = false;
-        return Some(expr0_0);
-    }
-    // Rule at src/isa/s390x/lower.isle line 346.
-    let expr0_0: bool = true;
-    return Some(expr0_0);
-}
-
-// Generated as internal constructor for term maybe_trap_if_zero_divisor.
-pub fn constructor_maybe_trap_if_zero_divisor<C: Context>(
-    ctx: &mut C,
-    arg0: bool,
-    arg1: Type,
-    arg2: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == true {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/lower.isle line 352.
-        let expr0_0: i16 = 0;
-        let expr1_0 = IntCC::Equal;
-        let expr2_0 = C::intcc_as_cond(ctx, &expr1_0);
-        let expr3_0 = C::trap_code_division_by_zero(ctx);
-        let expr4_0 = constructor_icmps_simm16_and_trap(
-            ctx, pattern2_0, pattern3_0, expr0_0, &expr2_0, &expr3_0,
-        )?;
-        return Some(expr4_0);
-    }
-    if pattern0_0 == false {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/s390x/lower.isle line 351.
-        let expr0_0 = C::invalid_reg(ctx);
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term div_overflow_check_needed.
-pub fn constructor_div_overflow_check_needed<C: Context>(ctx: &mut C, arg0: Value) -> Option<bool> {
-    let pattern0_0 = arg0;
-    if let Some(pattern1_0) = C::i64_from_value(ctx, pattern0_0) {
-        let pattern2_0 = -1;
-        if let Some(pattern3_0) = C::i64_nonequal(ctx, pattern1_0, pattern2_0) {
-            // Rule at src/isa/s390x/lower.isle line 425.
-            let expr0_0: bool = false;
-            return Some(expr0_0);
-        }
-    }
-    // Rule at src/isa/s390x/lower.isle line 426.
-    let expr0_0: bool = true;
-    return Some(expr0_0);
-}
-
-// Generated as internal constructor for term maybe_trap_if_sdiv_overflow.
-pub fn constructor_maybe_trap_if_sdiv_overflow<C: Context>(
-    ctx: &mut C,
-    arg0: bool,
-    arg1: Type,
-    arg2: Type,
-    arg3: &RegPair,
-    arg4: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == true {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        let pattern5_0 = arg4;
-        // Rule at src/isa/s390x/lower.isle line 439.
-        let expr0_0 = constructor_int_max(ctx, pattern3_0)?;
-        let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
-        let expr2_0 = constructor_regpair_lo(ctx, pattern4_0)?;
-        let expr3_0 = constructor_xor_reg(ctx, pattern2_0, expr1_0, expr2_0)?;
-        let expr4_0 = constructor_and_reg(ctx, pattern2_0, expr3_0, pattern5_0)?;
-        let expr5_0: i16 = -1;
-        let expr6_0 = IntCC::Equal;
-        let expr7_0 = C::intcc_as_cond(ctx, &expr6_0);
-        let expr8_0 = C::trap_code_integer_overflow(ctx);
-        let expr9_0 = constructor_icmps_simm16_and_trap(
-            ctx, pattern2_0, expr4_0, expr5_0, &expr7_0, &expr8_0,
-        )?;
-        return Some(expr9_0);
-    }
-    if pattern0_0 == false {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        let pattern5_0 = arg4;
-        // Rule at src/isa/s390x/lower.isle line 438.
-        let expr0_0 = C::invalid_reg(ctx);
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term int_max.
-pub fn constructor_int_max<C: Context>(ctx: &mut C, arg0: Type) -> Option<u64> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I8 {
-        // Rule at src/isa/s390x/lower.isle line 447.
-        let expr0_0: u64 = 127;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I16 {
-        // Rule at src/isa/s390x/lower.isle line 448.
-        let expr0_0: u64 = 32767;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I32 {
-        // Rule at src/isa/s390x/lower.isle line 449.
-        let expr0_0: u64 = 2147483647;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == I64 {
-        // Rule at src/isa/s390x/lower.isle line 450.
-        let expr0_0: u64 = 9223372036854775807;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term maybe_avoid_srem_overflow.
-pub fn constructor_maybe_avoid_srem_overflow<C: Context>(
-    ctx: &mut C,
-    arg0: bool,
-    arg1: Type,
-    arg2: &RegPair,
-    arg3: Reg,
-) -> Option<RegPair> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == true {
-        let pattern2_0 = arg1;
-        if pattern2_0 == I32 {
-            let pattern4_0 = arg2;
-            let pattern5_0 = arg3;
-            // Rule at src/isa/s390x/lower.isle line 468.
-            return Some(pattern4_0.clone());
-        }
-        if pattern2_0 == I64 {
-            let pattern4_0 = arg2;
-            let pattern5_0 = arg3;
-            // Rule at src/isa/s390x/lower.isle line 469.
-            let expr0_0: Type = I64;
-            let expr1_0: Type = I64;
-            let expr2_0: i16 = -1;
-            let expr3_0 = constructor_icmps_simm16(ctx, expr1_0, pattern5_0, expr2_0)?;
-            let expr4_0 = IntCC::Equal;
-            let expr5_0 = C::intcc_as_cond(ctx, &expr4_0);
-            let expr6_0: i16 = 0;
-            let expr7_0 = constructor_cmov_imm_regpair_lo(
-                ctx, expr0_0, &expr3_0, &expr5_0, expr6_0, pattern4_0,
-            )?;
-            return Some(expr7_0);
-        }
-    }
-    if pattern0_0 == false {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/s390x/lower.isle line 467.
-        return Some(pattern3_0.clone());
-    }
-    return None;
-}
-
-// Generated as internal constructor for term cast_bool.
-pub fn constructor_cast_bool<C: Context>(ctx: &mut C, arg0: Type, arg1: Value) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == B1 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = C::value_type(ctx, pattern2_0);
-        if pattern3_0 == B1 {
-            // Rule at src/isa/s390x/lower.isle line 766.
-            let expr0_0 = C::put_in_reg(ctx, pattern2_0);
-            return Some(expr0_0);
-        }
-        if pattern3_0 == B8 {
-            // Rule at src/isa/s390x/lower.isle line 767.
-            let expr0_0 = C::put_in_reg(ctx, pattern2_0);
-            return Some(expr0_0);
-        }
-    }
-    if pattern0_0 == B8 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = C::value_type(ctx, pattern2_0);
-        if pattern3_0 == B8 {
-            // Rule at src/isa/s390x/lower.isle line 768.
-            let expr0_0 = C::put_in_reg(ctx, pattern2_0);
-            return Some(expr0_0);
-        }
-    }
-    if pattern0_0 == I8 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = C::value_type(ctx, pattern2_0);
-        if pattern3_0 == B8 {
-            // Rule at src/isa/s390x/lower.isle line 769.
-            let expr0_0 = C::put_in_reg(ctx, pattern2_0);
-            return Some(expr0_0);
-        }
-    }
-    if let Some(pattern1_0) = C::fits_in_16(ctx, pattern0_0) {
-        let pattern2_0 = arg1;
-        let pattern3_0 = C::value_type(ctx, pattern2_0);
-        if pattern3_0 == B16 {
-            // Rule at src/isa/s390x/lower.isle line 770.
-            let expr0_0 = C::put_in_reg(ctx, pattern2_0);
-            return Some(expr0_0);
-        }
-    }
-    if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
-        let pattern2_0 = arg1;
-        let pattern3_0 = C::value_type(ctx, pattern2_0);
-        if pattern3_0 == B32 {
-            // Rule at src/isa/s390x/lower.isle line 771.
-            let expr0_0 = C::put_in_reg(ctx, pattern2_0);
-            return Some(expr0_0);
-        }
-    }
-    if let Some(pattern1_0) = C::fits_in_64(ctx, pattern0_0) {
-        let pattern2_0 = arg1;
-        let pattern3_0 = C::value_type(ctx, pattern2_0);
-        if pattern3_0 == B64 {
-            // Rule at src/isa/s390x/lower.isle line 772.
-            let expr0_0 = C::put_in_reg(ctx, pattern2_0);
-            return Some(expr0_0);
-        }
-    }
-    if let Some(pattern1_0) = C::gpr32_ty(ctx, pattern0_0) {
-        let pattern2_0 = arg1;
-        let pattern3_0 = C::value_type(ctx, pattern2_0);
-        if pattern3_0 == B1 {
-            // Rule at src/isa/s390x/lower.isle line 775.
-            let expr0_0: Type = I32;
-            let expr1_0: Type = I32;
-            let expr2_0 = C::put_in_reg(ctx, pattern2_0);
-            let expr3_0: u8 = 31;
-            let expr4_0 = constructor_lshl_imm(ctx, expr1_0, expr2_0, expr3_0)?;
-            let expr5_0: u8 = 31;
-            let expr6_0 = constructor_ashr_imm(ctx, expr0_0, expr4_0, expr5_0)?;
-            return Some(expr6_0);
-        }
-        if pattern3_0 == B8 {
-            // Rule at src/isa/s390x/lower.isle line 781.
-            let expr0_0: Type = I8;
-            let expr1_0 = C::put_in_reg(ctx, pattern2_0);
-            let expr2_0 = constructor_sext32_reg(ctx, expr0_0, expr1_0)?;
-            return Some(expr2_0);
-        }
-        if pattern3_0 == B16 {
-            // Rule at src/isa/s390x/lower.isle line 783.
-            let expr0_0: Type = I16;
-            let expr1_0 = C::put_in_reg(ctx, pattern2_0);
-            let expr2_0 = constructor_sext32_reg(ctx, expr0_0, expr1_0)?;
-            return Some(expr2_0);
-        }
-    }
-    if let Some(pattern1_0) = C::gpr64_ty(ctx, pattern0_0) {
-        let pattern2_0 = arg1;
-        let pattern3_0 = C::value_type(ctx, pattern2_0);
-        if pattern3_0 == B1 {
-            // Rule at src/isa/s390x/lower.isle line 777.
-            let expr0_0: Type = I64;
-            let expr1_0: Type = I64;
-            let expr2_0 = C::put_in_reg(ctx, pattern2_0);
-            let expr3_0: u8 = 63;
-            let expr4_0 = constructor_lshl_imm(ctx, expr1_0, expr2_0, expr3_0)?;
-            let expr5_0: u8 = 63;
-            let expr6_0 = constructor_ashr_imm(ctx, expr0_0, expr4_0, expr5_0)?;
-            return Some(expr6_0);
-        }
-        if pattern3_0 == B8 {
-            // Rule at src/isa/s390x/lower.isle line 785.
-            let expr0_0: Type = I8;
-            let expr1_0 = C::put_in_reg(ctx, pattern2_0);
-            let expr2_0 = constructor_sext64_reg(ctx, expr0_0, expr1_0)?;
-            return Some(expr2_0);
-        }
-        if pattern3_0 == B16 {
-            // Rule at src/isa/s390x/lower.isle line 787.
-            let expr0_0: Type = I16;
-            let expr1_0 = C::put_in_reg(ctx, pattern2_0);
-            let expr2_0 = constructor_sext64_reg(ctx, expr0_0, expr1_0)?;
-            return Some(expr2_0);
-        }
-        if pattern3_0 == B32 {
-            // Rule at src/isa/s390x/lower.isle line 789.
-            let expr0_0: Type = I32;
-            let expr1_0 = C::put_in_reg(ctx, pattern2_0);
-            let expr2_0 = constructor_sext64_reg(ctx, expr0_0, expr1_0)?;
-            return Some(expr2_0);
-        }
-    }
-    return None;
-}
-
-// Generated as internal constructor for term clz_offset.
-pub fn constructor_clz_offset<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I8 {
-        let pattern2_0 = arg1;
-        // Rule at src/isa/s390x/lower.isle line 814.
-        let expr0_0: Type = I8;
-        let expr1_0: i16 = -56;
-        let expr2_0 = constructor_add_simm16(ctx, expr0_0, pattern2_0, expr1_0)?;
-        return Some(expr2_0);
-    }
-    if pattern0_0 == I16 {
-        let pattern2_0 = arg1;
-        // Rule at src/isa/s390x/lower.isle line 815.
-        let expr0_0: Type = I16;
-        let expr1_0: i16 = -48;
-        let expr2_0 = constructor_add_simm16(ctx, expr0_0, pattern2_0, expr1_0)?;
-        return Some(expr2_0);
-    }
-    if pattern0_0 == I32 {
-        let pattern2_0 = arg1;
-        // Rule at src/isa/s390x/lower.isle line 816.
-        let expr0_0: Type = I32;
-        let expr1_0: i16 = -32;
-        let expr2_0 = constructor_add_simm16(ctx, expr0_0, pattern2_0, expr1_0)?;
-        return Some(expr2_0);
-    }
-    if pattern0_0 == I64 {
-        let pattern2_0 = arg1;
-        // Rule at src/isa/s390x/lower.isle line 817.
-        let expr0_0: Type = I64;
-        let expr1_0 = constructor_copy_reg(ctx, expr0_0, pattern2_0)?;
-        return Some(expr1_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term ctz_guardbit.
-pub fn constructor_ctz_guardbit<C: Context>(ctx: &mut C, arg0: Type) -> Option<UImm16Shifted> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I8 {
-        // Rule at src/isa/s390x/lower.isle line 866.
-        let expr0_0: u16 = 256;
-        let expr1_0: u8 = 0;
-        let expr2_0 = C::uimm16shifted(ctx, expr0_0, expr1_0);
-        return Some(expr2_0);
-    }
-    if pattern0_0 == I16 {
-        // Rule at src/isa/s390x/lower.isle line 867.
-        let expr0_0: u16 = 1;
-        let expr1_0: u8 = 16;
-        let expr2_0 = C::uimm16shifted(ctx, expr0_0, expr1_0);
-        return Some(expr2_0);
-    }
-    if pattern0_0 == I32 {
-        // Rule at src/isa/s390x/lower.isle line 868.
-        let expr0_0: u16 = 1;
-        let expr1_0: u8 = 32;
-        let expr2_0 = C::uimm16shifted(ctx, expr0_0, expr1_0);
-        return Some(expr2_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term istore8_impl.
-pub fn constructor_istore8_impl<C: Context>(
-    ctx: &mut C,
-    arg0: MemFlags,
-    arg1: Value,
-    arg2: Value,
-    arg3: Offset32,
-) -> Option<SideEffectNoResult> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    if let Some(pattern2_0) = C::u8_from_value(ctx, pattern1_0) {
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/s390x/lower.isle line 1424.
-        let expr0_0 = constructor_lower_address(ctx, pattern0_0, pattern3_0, pattern4_0)?;
-        let expr1_0 = constructor_store8_imm(ctx, pattern2_0, &expr0_0)?;
-        return Some(expr1_0);
-    }
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/s390x/lower.isle line 1420.
-    let expr0_0 = C::put_in_reg(ctx, pattern1_0);
-    let expr1_0 = constructor_lower_address(ctx, pattern0_0, pattern2_0, pattern3_0)?;
-    let expr2_0 = constructor_store8(ctx, expr0_0, &expr1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term istore16_impl.
-pub fn constructor_istore16_impl<C: Context>(
-    ctx: &mut C,
-    arg0: MemFlags,
-    arg1: Value,
-    arg2: Value,
-    arg3: Offset32,
-) -> Option<SideEffectNoResult> {
-    let pattern0_0 = arg0;
-    if let Some(()) = C::littleendian(ctx, pattern0_0) {
-        let pattern2_0 = arg1;
-        if let Some(pattern3_0) = C::i16_from_swapped_value(ctx, pattern2_0) {
-            let pattern4_0 = arg2;
-            let pattern5_0 = arg3;
-            // Rule at src/isa/s390x/lower.isle line 1450.
-            let expr0_0 = constructor_lower_address(ctx, pattern0_0, pattern4_0, pattern5_0)?;
-            let expr1_0 = constructor_store16_imm(ctx, pattern3_0, &expr0_0)?;
-            return Some(expr1_0);
-        }
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/s390x/lower.isle line 1442.
-        let expr0_0 = C::put_in_reg(ctx, pattern2_0);
-        let expr1_0 = constructor_lower_address(ctx, pattern0_0, pattern3_0, pattern4_0)?;
-        let expr2_0 = constructor_storerev16(ctx, expr0_0, &expr1_0)?;
-        return Some(expr2_0);
-    }
-    if let Some(()) = C::bigendian(ctx, pattern0_0) {
-        let pattern2_0 = arg1;
-        if let Some(pattern3_0) = C::i16_from_value(ctx, pattern2_0) {
-            let pattern4_0 = arg2;
-            let pattern5_0 = arg3;
-            // Rule at src/isa/s390x/lower.isle line 1446.
-            let expr0_0 = constructor_lower_address(ctx, pattern0_0, pattern4_0, pattern5_0)?;
-            let expr1_0 = constructor_store16_imm(ctx, pattern3_0, &expr0_0)?;
-            return Some(expr1_0);
-        }
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/s390x/lower.isle line 1438.
-        let expr0_0 = C::put_in_reg(ctx, pattern2_0);
-        let expr1_0 = constructor_lower_address(ctx, pattern0_0, pattern3_0, pattern4_0)?;
-        let expr2_0 = constructor_store16(ctx, expr0_0, &expr1_0)?;
-        return Some(expr2_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term istore32_impl.
-pub fn constructor_istore32_impl<C: Context>(
-    ctx: &mut C,
-    arg0: MemFlags,
-    arg1: Value,
-    arg2: Value,
-    arg3: Offset32,
-) -> Option<SideEffectNoResult> {
-    let pattern0_0 = arg0;
-    if let Some(()) = C::littleendian(ctx, pattern0_0) {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/s390x/lower.isle line 1472.
-        let expr0_0 = C::put_in_reg(ctx, pattern2_0);
-        let expr1_0 = constructor_lower_address(ctx, pattern0_0, pattern3_0, pattern4_0)?;
-        let expr2_0 = constructor_storerev32(ctx, expr0_0, &expr1_0)?;
-        return Some(expr2_0);
-    }
-    if let Some(()) = C::bigendian(ctx, pattern0_0) {
-        let pattern2_0 = arg1;
-        if let Some(pattern3_0) = C::i16_from_value(ctx, pattern2_0) {
-            let pattern4_0 = arg2;
-            let pattern5_0 = arg3;
-            // Rule at src/isa/s390x/lower.isle line 1468.
-            let expr0_0 = constructor_lower_address(ctx, pattern0_0, pattern4_0, pattern5_0)?;
-            let expr1_0 = constructor_store32_simm16(ctx, pattern3_0, &expr0_0)?;
-            return Some(expr1_0);
-        }
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/s390x/lower.isle line 1464.
-        let expr0_0 = C::put_in_reg(ctx, pattern2_0);
-        let expr1_0 = constructor_lower_address(ctx, pattern0_0, pattern3_0, pattern4_0)?;
-        let expr2_0 = constructor_store32(ctx, expr0_0, &expr1_0)?;
-        return Some(expr2_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term istore64_impl.
-pub fn constructor_istore64_impl<C: Context>(
-    ctx: &mut C,
-    arg0: MemFlags,
-    arg1: Value,
-    arg2: Value,
-    arg3: Offset32,
-) -> Option<SideEffectNoResult> {
-    let pattern0_0 = arg0;
-    if let Some(()) = C::littleendian(ctx, pattern0_0) {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/s390x/lower.isle line 1490.
-        let expr0_0 = C::put_in_reg(ctx, pattern2_0);
-        let expr1_0 = constructor_lower_address(ctx, pattern0_0, pattern3_0, pattern4_0)?;
-        let expr2_0 = constructor_storerev64(ctx, expr0_0, &expr1_0)?;
-        return Some(expr2_0);
-    }
-    if let Some(()) = C::bigendian(ctx, pattern0_0) {
-        let pattern2_0 = arg1;
-        if let Some(pattern3_0) = C::i16_from_value(ctx, pattern2_0) {
-            let pattern4_0 = arg2;
-            let pattern5_0 = arg3;
-            // Rule at src/isa/s390x/lower.isle line 1486.
-            let expr0_0 = constructor_lower_address(ctx, pattern0_0, pattern4_0, pattern5_0)?;
-            let expr1_0 = constructor_store64_simm16(ctx, pattern3_0, &expr0_0)?;
-            return Some(expr1_0);
-        }
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/s390x/lower.isle line 1482.
-        let expr0_0 = C::put_in_reg(ctx, pattern2_0);
-        let expr1_0 = constructor_lower_address(ctx, pattern0_0, pattern3_0, pattern4_0)?;
-        let expr2_0 = constructor_store64(ctx, expr0_0, &expr1_0)?;
-        return Some(expr2_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term atomic_rmw_body.
-pub fn constructor_atomic_rmw_body<C: Context>(
-    ctx: &mut C,
-    arg0: &VecMInstBuilder,
-    arg1: Type,
-    arg2: MemFlags,
-    arg3: &AtomicRmwOp,
-    arg4: WritableReg,
-    arg5: Reg,
-    arg6: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    if let Some(()) = C::mie2_enabled(ctx, pattern1_0) {
-        if let Some(pattern3_0) = C::ty_32_or_64(ctx, pattern1_0) {
-            let pattern4_0 = arg2;
-            if let Some(()) = C::littleendian(ctx, pattern4_0) {
-                let pattern6_0 = arg3;
-                if let &AtomicRmwOp::Nand = pattern6_0 {
-                    let pattern8_0 = arg4;
-                    let pattern9_0 = arg5;
-                    let pattern10_0 = arg6;
-                    // Rule at src/isa/s390x/lower.isle line 1598.
-                    let expr0_0 = constructor_aluop_and_not(ctx, pattern3_0)?;
-                    let expr1_0 = constructor_bswap_reg(ctx, pattern3_0, pattern10_0)?;
-                    let expr2_0 = constructor_push_alu_reg(
-                        ctx, pattern0_0, &expr0_0, pattern8_0, pattern9_0, expr1_0,
-                    )?;
-                    return Some(expr2_0);
-                }
-            }
-            if let Some(()) = C::bigendian(ctx, pattern4_0) {
-                let pattern6_0 = arg3;
-                if let &AtomicRmwOp::Nand = pattern6_0 {
-                    let pattern8_0 = arg4;
-                    let pattern9_0 = arg5;
-                    let pattern10_0 = arg6;
-                    // Rule at src/isa/s390x/lower.isle line 1595.
-                    let expr0_0 = constructor_aluop_and_not(ctx, pattern3_0)?;
-                    let expr1_0 = constructor_push_alu_reg(
-                        ctx,
-                        pattern0_0,
-                        &expr0_0,
-                        pattern8_0,
-                        pattern9_0,
-                        pattern10_0,
-                    )?;
-                    return Some(expr1_0);
-                }
-            }
-        }
-    }
-    if let Some(()) = C::mie2_disabled(ctx, pattern1_0) {
-        if let Some(pattern3_0) = C::ty_32_or_64(ctx, pattern1_0) {
-            let pattern4_0 = arg2;
-            if let Some(()) = C::littleendian(ctx, pattern4_0) {
-                let pattern6_0 = arg3;
-                if let &AtomicRmwOp::Nand = pattern6_0 {
-                    let pattern8_0 = arg4;
-                    let pattern9_0 = arg5;
-                    let pattern10_0 = arg6;
-                    // Rule at src/isa/s390x/lower.isle line 1605.
-                    let expr0_0 = constructor_aluop_and(ctx, pattern3_0)?;
-                    let expr1_0 = constructor_bswap_reg(ctx, pattern3_0, pattern10_0)?;
-                    let expr2_0 = constructor_push_alu_reg(
-                        ctx, pattern0_0, &expr0_0, pattern8_0, pattern9_0, expr1_0,
-                    )?;
-                    let expr3_0 =
-                        constructor_push_not_reg(ctx, pattern0_0, pattern3_0, pattern8_0, expr2_0)?;
-                    return Some(expr3_0);
-                }
-            }
-            if let Some(()) = C::bigendian(ctx, pattern4_0) {
-                let pattern6_0 = arg3;
-                if let &AtomicRmwOp::Nand = pattern6_0 {
-                    let pattern8_0 = arg4;
-                    let pattern9_0 = arg5;
-                    let pattern10_0 = arg6;
-                    // Rule at src/isa/s390x/lower.isle line 1601.
-                    let expr0_0 = constructor_aluop_and(ctx, pattern3_0)?;
-                    let expr1_0 = constructor_push_alu_reg(
-                        ctx,
-                        pattern0_0,
-                        &expr0_0,
-                        pattern8_0,
-                        pattern9_0,
-                        pattern10_0,
-                    )?;
-                    let expr2_0 =
-                        constructor_push_not_reg(ctx, pattern0_0, pattern3_0, pattern8_0, expr1_0)?;
-                    return Some(expr2_0);
-                }
-            }
-        }
-    }
-    if let Some(pattern2_0) = C::ty_32_or_64(ctx, pattern1_0) {
-        let pattern3_0 = arg2;
-        if let Some(()) = C::littleendian(ctx, pattern3_0) {
-            let pattern5_0 = arg3;
-            if let &AtomicRmwOp::Xchg = pattern5_0 {
-                let pattern7_0 = arg4;
-                let pattern8_0 = arg5;
-                let pattern9_0 = arg6;
-                // Rule at src/isa/s390x/lower.isle line 1587.
-                let expr0_0 = constructor_bswap_reg(ctx, pattern2_0, pattern9_0)?;
-                return Some(expr0_0);
-            }
-        }
-        if let Some(()) = C::bigendian(ctx, pattern3_0) {
-            let pattern5_0 = arg3;
-            if let &AtomicRmwOp::Xchg = pattern5_0 {
-                let pattern7_0 = arg4;
-                let pattern8_0 = arg5;
-                let pattern9_0 = arg6;
-                // Rule at src/isa/s390x/lower.isle line 1584.
-                return Some(pattern9_0);
-            }
-        }
-    }
-    if let Some(pattern2_0) = C::ty_8_or_16(ctx, pattern1_0) {
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        match pattern4_0 {
-            &AtomicRmwOp::And => {
-                let pattern6_0 = arg4;
-                let pattern7_0 = arg5;
-                let pattern8_0 = arg6;
-                // Rule at src/isa/s390x/lower.isle line 1615.
-                let expr0_0 = RxSBGOp::And;
-                let expr1_0 = constructor_atomic_rmw_body_rxsbg(
-                    ctx, pattern0_0, pattern2_0, pattern3_0, &expr0_0, pattern6_0, pattern7_0,
-                    pattern8_0,
-                )?;
-                return Some(expr1_0);
-            }
-            &AtomicRmwOp::Nand => {
-                let pattern6_0 = arg4;
-                let pattern7_0 = arg5;
-                let pattern8_0 = arg6;
-                // Rule at src/isa/s390x/lower.isle line 1621.
-                let expr0_0 = RxSBGOp::And;
-                let expr1_0 = constructor_atomic_rmw_body_rxsbg(
-                    ctx, pattern0_0, pattern2_0, pattern3_0, &expr0_0, pattern6_0, pattern7_0,
-                    pattern8_0,
-                )?;
-                let expr2_0 = constructor_atomic_rmw_body_invert(
-                    ctx, pattern0_0, pattern2_0, pattern3_0, pattern6_0, expr1_0,
-                )?;
-                return Some(expr2_0);
-            }
-            &AtomicRmwOp::Or => {
-                let pattern6_0 = arg4;
-                let pattern7_0 = arg5;
-                let pattern8_0 = arg6;
-                // Rule at src/isa/s390x/lower.isle line 1617.
-                let expr0_0 = RxSBGOp::Or;
-                let expr1_0 = constructor_atomic_rmw_body_rxsbg(
-                    ctx, pattern0_0, pattern2_0, pattern3_0, &expr0_0, pattern6_0, pattern7_0,
-                    pattern8_0,
-                )?;
-                return Some(expr1_0);
-            }
-            &AtomicRmwOp::Xchg => {
-                let pattern6_0 = arg4;
-                let pattern7_0 = arg5;
-                let pattern8_0 = arg6;
-                // Rule at src/isa/s390x/lower.isle line 1613.
-                let expr0_0 = RxSBGOp::Insert;
-                let expr1_0 = constructor_atomic_rmw_body_rxsbg(
-                    ctx, pattern0_0, pattern2_0, pattern3_0, &expr0_0, pattern6_0, pattern7_0,
-                    pattern8_0,
-                )?;
-                return Some(expr1_0);
-            }
-            &AtomicRmwOp::Xor => {
-                let pattern6_0 = arg4;
-                let pattern7_0 = arg5;
-                let pattern8_0 = arg6;
-                // Rule at src/isa/s390x/lower.isle line 1619.
-                let expr0_0 = RxSBGOp::Xor;
-                let expr1_0 = constructor_atomic_rmw_body_rxsbg(
-                    ctx, pattern0_0, pattern2_0, pattern3_0, &expr0_0, pattern6_0, pattern7_0,
-                    pattern8_0,
-                )?;
-                return Some(expr1_0);
-            }
-            _ => {}
-        }
-    }
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    match pattern3_0 {
-        &AtomicRmwOp::Add => {
-            let pattern5_0 = arg4;
-            let pattern6_0 = arg5;
-            let pattern7_0 = arg6;
-            // Rule at src/isa/s390x/lower.isle line 1653.
-            let expr0_0 = constructor_ty_ext32(ctx, pattern1_0)?;
-            let expr1_0 = constructor_aluop_add(ctx, expr0_0)?;
-            let expr2_0 = constructor_atomic_rmw_body_addsub(
-                ctx, pattern0_0, pattern1_0, pattern2_0, &expr1_0, pattern5_0, pattern6_0,
-                pattern7_0,
-            )?;
-            return Some(expr2_0);
-        }
-        &AtomicRmwOp::Smax => {
-            let pattern5_0 = arg4;
-            let pattern6_0 = arg5;
-            let pattern7_0 = arg6;
-            // Rule at src/isa/s390x/lower.isle line 1694.
-            let expr0_0 = constructor_ty_ext32(ctx, pattern1_0)?;
-            let expr1_0 = constructor_cmpop_cmps(ctx, expr0_0)?;
-            let expr2_0 = IntCC::SignedGreaterThan;
-            let expr3_0 = C::intcc_as_cond(ctx, &expr2_0);
-            let expr4_0 = constructor_atomic_rmw_body_minmax(
-                ctx, pattern0_0, pattern1_0, pattern2_0, &expr1_0, &expr3_0, pattern5_0,
-                pattern6_0, pattern7_0,
-            )?;
-            return Some(expr4_0);
-        }
-        &AtomicRmwOp::Smin => {
-            let pattern5_0 = arg4;
-            let pattern6_0 = arg5;
-            let pattern7_0 = arg6;
-            // Rule at src/isa/s390x/lower.isle line 1691.
-            let expr0_0 = constructor_ty_ext32(ctx, pattern1_0)?;
-            let expr1_0 = constructor_cmpop_cmps(ctx, expr0_0)?;
-            let expr2_0 = IntCC::SignedLessThan;
-            let expr3_0 = C::intcc_as_cond(ctx, &expr2_0);
-            let expr4_0 = constructor_atomic_rmw_body_minmax(
-                ctx, pattern0_0, pattern1_0, pattern2_0, &expr1_0, &expr3_0, pattern5_0,
-                pattern6_0, pattern7_0,
-            )?;
-            return Some(expr4_0);
-        }
-        &AtomicRmwOp::Sub => {
-            let pattern5_0 = arg4;
-            let pattern6_0 = arg5;
-            let pattern7_0 = arg6;
-            // Rule at src/isa/s390x/lower.isle line 1655.
-            let expr0_0 = constructor_ty_ext32(ctx, pattern1_0)?;
-            let expr1_0 = constructor_aluop_sub(ctx, expr0_0)?;
-            let expr2_0 = constructor_atomic_rmw_body_addsub(
-                ctx, pattern0_0, pattern1_0, pattern2_0, &expr1_0, pattern5_0, pattern6_0,
-                pattern7_0,
-            )?;
-            return Some(expr2_0);
-        }
-        &AtomicRmwOp::Umax => {
-            let pattern5_0 = arg4;
-            let pattern6_0 = arg5;
-            let pattern7_0 = arg6;
-            // Rule at src/isa/s390x/lower.isle line 1700.
-            let expr0_0 = constructor_ty_ext32(ctx, pattern1_0)?;
-            let expr1_0 = constructor_cmpop_cmpu(ctx, expr0_0)?;
-            let expr2_0 = IntCC::UnsignedGreaterThan;
-            let expr3_0 = C::intcc_as_cond(ctx, &expr2_0);
-            let expr4_0 = constructor_atomic_rmw_body_minmax(
-                ctx, pattern0_0, pattern1_0, pattern2_0, &expr1_0, &expr3_0, pattern5_0,
-                pattern6_0, pattern7_0,
-            )?;
-            return Some(expr4_0);
-        }
-        &AtomicRmwOp::Umin => {
-            let pattern5_0 = arg4;
-            let pattern6_0 = arg5;
-            let pattern7_0 = arg6;
-            // Rule at src/isa/s390x/lower.isle line 1697.
-            let expr0_0 = constructor_ty_ext32(ctx, pattern1_0)?;
-            let expr1_0 = constructor_cmpop_cmpu(ctx, expr0_0)?;
-            let expr2_0 = IntCC::UnsignedLessThan;
-            let expr3_0 = C::intcc_as_cond(ctx, &expr2_0);
-            let expr4_0 = constructor_atomic_rmw_body_minmax(
-                ctx, pattern0_0, pattern1_0, pattern2_0, &expr1_0, &expr3_0, pattern5_0,
-                pattern6_0, pattern7_0,
-            )?;
-            return Some(expr4_0);
-        }
-        _ => {}
-    }
-    return None;
-}
-
-// Generated as internal constructor for term atomic_rmw_body_rxsbg.
-pub fn constructor_atomic_rmw_body_rxsbg<C: Context>(
-    ctx: &mut C,
-    arg0: &VecMInstBuilder,
-    arg1: Type,
-    arg2: MemFlags,
-    arg3: &RxSBGOp,
-    arg4: WritableReg,
-    arg5: Reg,
-    arg6: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    if pattern1_0 == I8 {
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        let pattern5_0 = arg4;
-        let pattern6_0 = arg5;
-        let pattern7_0 = arg6;
-        // Rule at src/isa/s390x/lower.isle line 1629.
-        let expr0_0: u8 = 32;
-        let expr1_0: u8 = 40;
-        let expr2_0: i8 = 24;
-        let expr3_0 = constructor_push_rxsbg(
-            ctx, pattern0_0, pattern4_0, pattern5_0, pattern6_0, pattern7_0, expr0_0, expr1_0,
-            expr2_0,
-        )?;
-        return Some(expr3_0);
-    }
-    if pattern1_0 == I16 {
-        let pattern3_0 = arg2;
-        if let Some(()) = C::littleendian(ctx, pattern3_0) {
-            let pattern5_0 = arg3;
-            let pattern6_0 = arg4;
-            let pattern7_0 = arg5;
-            let pattern8_0 = arg6;
-            // Rule at src/isa/s390x/lower.isle line 1637.
-            let expr0_0: Type = I32;
-            let expr1_0 = constructor_bswap_reg(ctx, expr0_0, pattern8_0)?;
-            let expr2_0: u8 = 48;
-            let expr3_0: u8 = 64;
-            let expr4_0: i8 = -16;
-            let expr5_0 = constructor_push_rxsbg(
-                ctx, pattern0_0, pattern5_0, pattern6_0, pattern7_0, expr1_0, expr2_0, expr3_0,
-                expr4_0,
-            )?;
-            return Some(expr5_0);
-        }
-        if let Some(()) = C::bigendian(ctx, pattern3_0) {
-            let pattern5_0 = arg3;
-            let pattern6_0 = arg4;
-            let pattern7_0 = arg5;
-            let pattern8_0 = arg6;
-            // Rule at src/isa/s390x/lower.isle line 1633.
-            let expr0_0: u8 = 32;
-            let expr1_0: u8 = 48;
-            let expr2_0: i8 = 16;
-            let expr3_0 = constructor_push_rxsbg(
-                ctx, pattern0_0, pattern5_0, pattern6_0, pattern7_0, pattern8_0, expr0_0, expr1_0,
-                expr2_0,
-            )?;
-            return Some(expr3_0);
-        }
-    }
-    return None;
-}
-
-// Generated as internal constructor for term atomic_rmw_body_invert.
-pub fn constructor_atomic_rmw_body_invert<C: Context>(
-    ctx: &mut C,
-    arg0: &VecMInstBuilder,
-    arg1: Type,
-    arg2: MemFlags,
-    arg3: WritableReg,
-    arg4: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    if pattern1_0 == I8 {
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        let pattern5_0 = arg4;
-        // Rule at src/isa/s390x/lower.isle line 1643.
-        let expr0_0: Type = I32;
-        let expr1_0: u32 = 4278190080;
-        let expr2_0: u8 = 0;
-        let expr3_0 = C::uimm32shifted(ctx, expr1_0, expr2_0);
-        let expr4_0 = constructor_push_xor_uimm32shifted(
-            ctx, pattern0_0, expr0_0, pattern4_0, pattern5_0, expr3_0,
-        )?;
-        return Some(expr4_0);
-    }
-    if pattern1_0 == I16 {
-        let pattern3_0 = arg2;
-        if let Some(()) = C::littleendian(ctx, pattern3_0) {
-            let pattern5_0 = arg3;
-            let pattern6_0 = arg4;
-            // Rule at src/isa/s390x/lower.isle line 1649.
-            let expr0_0: Type = I32;
-            let expr1_0: u32 = 65535;
-            let expr2_0: u8 = 0;
-            let expr3_0 = C::uimm32shifted(ctx, expr1_0, expr2_0);
-            let expr4_0 = constructor_push_xor_uimm32shifted(
-                ctx, pattern0_0, expr0_0, pattern5_0, pattern6_0, expr3_0,
-            )?;
-            return Some(expr4_0);
-        }
-        if let Some(()) = C::bigendian(ctx, pattern3_0) {
-            let pattern5_0 = arg3;
-            let pattern6_0 = arg4;
-            // Rule at src/isa/s390x/lower.isle line 1646.
-            let expr0_0: Type = I32;
-            let expr1_0: u32 = 4294901760;
-            let expr2_0: u8 = 0;
-            let expr3_0 = C::uimm32shifted(ctx, expr1_0, expr2_0);
-            let expr4_0 = constructor_push_xor_uimm32shifted(
-                ctx, pattern0_0, expr0_0, pattern5_0, pattern6_0, expr3_0,
-            )?;
-            return Some(expr4_0);
-        }
-    }
-    return None;
-}
-
-// Generated as internal constructor for term atomic_rmw_body_addsub.
-pub fn constructor_atomic_rmw_body_addsub<C: Context>(
-    ctx: &mut C,
-    arg0: &VecMInstBuilder,
-    arg1: Type,
-    arg2: MemFlags,
-    arg3: &ALUOp,
-    arg4: WritableReg,
-    arg5: Reg,
-    arg6: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    if pattern1_0 == I8 {
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        let pattern5_0 = arg4;
-        let pattern6_0 = arg5;
-        let pattern7_0 = arg6;
-        // Rule at src/isa/s390x/lower.isle line 1672.
-        let expr0_0: Type = I32;
-        let expr1_0: u8 = 24;
-        let expr2_0 = constructor_lshl_imm(ctx, expr0_0, pattern7_0, expr1_0)?;
-        let expr3_0 =
-            constructor_push_alu_reg(ctx, pattern0_0, pattern4_0, pattern5_0, pattern6_0, expr2_0)?;
-        return Some(expr3_0);
-    }
-    if pattern1_0 == I16 {
-        let pattern3_0 = arg2;
-        if let Some(()) = C::littleendian(ctx, pattern3_0) {
-            let pattern5_0 = arg3;
-            let pattern6_0 = arg4;
-            let pattern7_0 = arg5;
-            let pattern8_0 = arg6;
-            // Rule at src/isa/s390x/lower.isle line 1684.
-            let expr0_0: Type = I32;
-            let expr1_0: u8 = 16;
-            let expr2_0 = constructor_lshl_imm(ctx, expr0_0, pattern8_0, expr1_0)?;
-            let expr3_0: Type = I32;
-            let expr4_0 =
-                constructor_push_bswap_reg(ctx, pattern0_0, expr3_0, pattern6_0, pattern7_0)?;
-            let expr5_0 = constructor_push_alu_reg(
-                ctx, pattern0_0, pattern5_0, pattern6_0, expr4_0, expr2_0,
-            )?;
-            let expr6_0: Type = I32;
-            let expr7_0 =
-                constructor_push_bswap_reg(ctx, pattern0_0, expr6_0, pattern6_0, expr5_0)?;
-            return Some(expr7_0);
-        }
-        if let Some(()) = C::bigendian(ctx, pattern3_0) {
-            let pattern5_0 = arg3;
-            let pattern6_0 = arg4;
-            let pattern7_0 = arg5;
-            let pattern8_0 = arg6;
-            // Rule at src/isa/s390x/lower.isle line 1676.
-            let expr0_0: Type = I32;
-            let expr1_0: u8 = 16;
-            let expr2_0 = constructor_lshl_imm(ctx, expr0_0, pattern8_0, expr1_0)?;
-            let expr3_0 = constructor_push_alu_reg(
-                ctx, pattern0_0, pattern5_0, pattern6_0, pattern7_0, expr2_0,
-            )?;
-            return Some(expr3_0);
-        }
-    }
-    if let Some(pattern2_0) = C::ty_32_or_64(ctx, pattern1_0) {
-        let pattern3_0 = arg2;
-        if let Some(()) = C::littleendian(ctx, pattern3_0) {
-            let pattern5_0 = arg3;
-            let pattern6_0 = arg4;
-            let pattern7_0 = arg5;
-            let pattern8_0 = arg6;
-            // Rule at src/isa/s390x/lower.isle line 1666.
-            let expr0_0 =
-                constructor_push_bswap_reg(ctx, pattern0_0, pattern2_0, pattern6_0, pattern7_0)?;
-            let expr1_0 = constructor_push_alu_reg(
-                ctx, pattern0_0, pattern5_0, pattern6_0, expr0_0, pattern8_0,
-            )?;
-            let expr2_0 =
-                constructor_push_bswap_reg(ctx, pattern0_0, pattern2_0, pattern6_0, expr1_0)?;
-            return Some(expr2_0);
-        }
-        if let Some(()) = C::bigendian(ctx, pattern3_0) {
-            let pattern5_0 = arg3;
-            let pattern6_0 = arg4;
-            let pattern7_0 = arg5;
-            let pattern8_0 = arg6;
-            // Rule at src/isa/s390x/lower.isle line 1662.
-            let expr0_0 = constructor_push_alu_reg(
-                ctx, pattern0_0, pattern5_0, pattern6_0, pattern7_0, pattern8_0,
-            )?;
-            return Some(expr0_0);
-        }
-    }
-    return None;
-}
-
-// Generated as internal constructor for term atomic_rmw_body_minmax.
-pub fn constructor_atomic_rmw_body_minmax<C: Context>(
-    ctx: &mut C,
-    arg0: &VecMInstBuilder,
-    arg1: Type,
-    arg2: MemFlags,
-    arg3: &CmpOp,
-    arg4: &Cond,
-    arg5: WritableReg,
-    arg6: Reg,
-    arg7: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    if pattern1_0 == I8 {
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        let pattern5_0 = arg4;
-        let pattern6_0 = arg5;
-        let pattern7_0 = arg6;
-        let pattern8_0 = arg7;
-        // Rule at src/isa/s390x/lower.isle line 1729.
-        let expr0_0: Type = I32;
-        let expr1_0: u8 = 24;
-        let expr2_0 = constructor_lshl_imm(ctx, expr0_0, pattern8_0, expr1_0)?;
-        let expr3_0 = constructor_cmp_rr(ctx, pattern4_0, expr2_0, pattern7_0)?;
-        let expr4_0 = C::invert_cond(ctx, pattern5_0);
-        let expr5_0 = constructor_push_break_if(ctx, pattern0_0, &expr3_0, &expr4_0)?;
-        let expr6_0 = RxSBGOp::Insert;
-        let expr7_0: u8 = 32;
-        let expr8_0: u8 = 40;
-        let expr9_0: i8 = 0;
-        let expr10_0 = constructor_push_rxsbg(
-            ctx, pattern0_0, &expr6_0, pattern6_0, pattern7_0, expr2_0, expr7_0, expr8_0, expr9_0,
-        )?;
-        return Some(expr10_0);
-    }
-    if pattern1_0 == I16 {
-        let pattern3_0 = arg2;
-        if let Some(()) = C::littleendian(ctx, pattern3_0) {
-            let pattern5_0 = arg3;
-            let pattern6_0 = arg4;
-            let pattern7_0 = arg5;
-            let pattern8_0 = arg6;
-            let pattern9_0 = arg7;
-            // Rule at src/isa/s390x/lower.isle line 1742.
-            let expr0_0: Type = I32;
-            let expr1_0: u8 = 16;
-            let expr2_0 = constructor_lshl_imm(ctx, expr0_0, pattern9_0, expr1_0)?;
-            let expr3_0: Type = I32;
-            let expr4_0 =
-                constructor_push_bswap_reg(ctx, pattern0_0, expr3_0, pattern7_0, pattern8_0)?;
-            let expr5_0 = constructor_cmp_rr(ctx, pattern5_0, expr2_0, expr4_0)?;
-            let expr6_0 = C::invert_cond(ctx, pattern6_0);
-            let expr7_0 = constructor_push_break_if(ctx, pattern0_0, &expr5_0, &expr6_0)?;
-            let expr8_0 = RxSBGOp::Insert;
-            let expr9_0: u8 = 32;
-            let expr10_0: u8 = 48;
-            let expr11_0: i8 = 0;
-            let expr12_0 = constructor_push_rxsbg(
-                ctx, pattern0_0, &expr8_0, pattern7_0, expr4_0, expr2_0, expr9_0, expr10_0,
-                expr11_0,
-            )?;
-            let expr13_0: Type = I32;
-            let expr14_0 =
-                constructor_push_bswap_reg(ctx, pattern0_0, expr13_0, pattern7_0, expr12_0)?;
-            return Some(expr14_0);
-        }
-        if let Some(()) = C::bigendian(ctx, pattern3_0) {
-            let pattern5_0 = arg3;
-            let pattern6_0 = arg4;
-            let pattern7_0 = arg5;
-            let pattern8_0 = arg6;
-            let pattern9_0 = arg7;
-            // Rule at src/isa/s390x/lower.isle line 1735.
-            let expr0_0: Type = I32;
-            let expr1_0: u8 = 16;
-            let expr2_0 = constructor_lshl_imm(ctx, expr0_0, pattern9_0, expr1_0)?;
-            let expr3_0 = constructor_cmp_rr(ctx, pattern5_0, expr2_0, pattern8_0)?;
-            let expr4_0 = C::invert_cond(ctx, pattern6_0);
-            let expr5_0 = constructor_push_break_if(ctx, pattern0_0, &expr3_0, &expr4_0)?;
-            let expr6_0 = RxSBGOp::Insert;
-            let expr7_0: u8 = 32;
-            let expr8_0: u8 = 48;
-            let expr9_0: i8 = 0;
-            let expr10_0 = constructor_push_rxsbg(
-                ctx, pattern0_0, &expr6_0, pattern7_0, pattern8_0, expr2_0, expr7_0, expr8_0,
-                expr9_0,
-            )?;
-            return Some(expr10_0);
-        }
-    }
-    if let Some(pattern2_0) = C::ty_32_or_64(ctx, pattern1_0) {
-        let pattern3_0 = arg2;
-        if let Some(()) = C::littleendian(ctx, pattern3_0) {
-            let pattern5_0 = arg3;
-            let pattern6_0 = arg4;
-            let pattern7_0 = arg5;
-            let pattern8_0 = arg6;
-            let pattern9_0 = arg7;
-            // Rule at src/isa/s390x/lower.isle line 1717.
-            let expr0_0 =
-                constructor_push_bswap_reg(ctx, pattern0_0, pattern2_0, pattern7_0, pattern8_0)?;
-            let expr1_0 = constructor_cmp_rr(ctx, pattern5_0, pattern9_0, expr0_0)?;
-            let expr2_0 = C::invert_cond(ctx, pattern6_0);
-            let expr3_0 = constructor_push_break_if(ctx, pattern0_0, &expr1_0, &expr2_0)?;
-            let expr4_0 =
-                constructor_push_bswap_reg(ctx, pattern0_0, pattern2_0, pattern7_0, pattern9_0)?;
-            return Some(expr4_0);
-        }
-        if let Some(()) = C::bigendian(ctx, pattern3_0) {
-            let pattern5_0 = arg3;
-            let pattern6_0 = arg4;
-            let pattern7_0 = arg5;
-            let pattern8_0 = arg6;
-            let pattern9_0 = arg7;
-            // Rule at src/isa/s390x/lower.isle line 1710.
-            let expr0_0 = constructor_cmp_rr(ctx, pattern5_0, pattern9_0, pattern8_0)?;
-            let expr1_0 = C::invert_cond(ctx, pattern6_0);
-            let expr2_0 = constructor_push_break_if(ctx, pattern0_0, &expr0_0, &expr1_0)?;
-            return Some(pattern9_0);
-        }
-    }
-    return None;
-}
-
-// Generated as internal constructor for term atomic_cas_body.
-pub fn constructor_atomic_cas_body<C: Context>(
-    ctx: &mut C,
-    arg0: &VecMInstBuilder,
-    arg1: Type,
-    arg2: MemFlags,
-    arg3: WritableReg,
-    arg4: Reg,
-    arg5: Reg,
-    arg6: Reg,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    if pattern1_0 == I8 {
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        let pattern5_0 = arg4;
-        let pattern6_0 = arg5;
-        let pattern7_0 = arg6;
-        // Rule at src/isa/s390x/lower.isle line 1794.
-        let expr0_0 = RxSBGOp::Xor;
-        let expr1_0: u8 = 32;
-        let expr2_0: u8 = 40;
-        let expr3_0: i8 = 24;
-        let expr4_0 = constructor_rxsbg_test(
-            ctx, &expr0_0, pattern5_0, pattern6_0, expr1_0, expr2_0, expr3_0,
-        )?;
-        let expr5_0 = IntCC::NotEqual;
-        let expr6_0 = C::intcc_as_cond(ctx, &expr5_0);
-        let expr7_0 = constructor_push_break_if(ctx, pattern0_0, &expr4_0, &expr6_0)?;
-        let expr8_0 = RxSBGOp::Insert;
-        let expr9_0: u8 = 32;
-        let expr10_0: u8 = 40;
-        let expr11_0: i8 = 24;
-        let expr12_0 = constructor_push_rxsbg(
-            ctx, pattern0_0, &expr8_0, pattern4_0, pattern5_0, pattern7_0, expr9_0, expr10_0,
-            expr11_0,
-        )?;
-        return Some(expr12_0);
-    }
-    if pattern1_0 == I16 {
-        let pattern3_0 = arg2;
-        if let Some(()) = C::littleendian(ctx, pattern3_0) {
-            let pattern5_0 = arg3;
-            let pattern6_0 = arg4;
-            let pattern7_0 = arg5;
-            let pattern8_0 = arg6;
-            // Rule at src/isa/s390x/lower.isle line 1812.
-            let expr0_0: Type = I32;
-            let expr1_0 = constructor_bswap_reg(ctx, expr0_0, pattern7_0)?;
-            let expr2_0: Type = I32;
-            let expr3_0 = constructor_bswap_reg(ctx, expr2_0, pattern8_0)?;
-            let expr4_0 = RxSBGOp::Xor;
-            let expr5_0: u8 = 48;
-            let expr6_0: u8 = 64;
-            let expr7_0: i8 = -16;
-            let expr8_0 = constructor_rxsbg_test(
-                ctx, &expr4_0, pattern6_0, expr1_0, expr5_0, expr6_0, expr7_0,
-            )?;
-            let expr9_0 = IntCC::NotEqual;
-            let expr10_0 = C::intcc_as_cond(ctx, &expr9_0);
-            let expr11_0 = constructor_push_break_if(ctx, pattern0_0, &expr8_0, &expr10_0)?;
-            let expr12_0 = RxSBGOp::Insert;
-            let expr13_0: u8 = 48;
-            let expr14_0: u8 = 64;
-            let expr15_0: i8 = -16;
-            let expr16_0 = constructor_push_rxsbg(
-                ctx, pattern0_0, &expr12_0, pattern5_0, pattern6_0, expr3_0, expr13_0, expr14_0,
-                expr15_0,
-            )?;
-            return Some(expr16_0);
-        }
-        if let Some(()) = C::bigendian(ctx, pattern3_0) {
-            let pattern5_0 = arg3;
-            let pattern6_0 = arg4;
-            let pattern7_0 = arg5;
-            let pattern8_0 = arg6;
-            // Rule at src/isa/s390x/lower.isle line 1801.
-            let expr0_0 = RxSBGOp::Xor;
-            let expr1_0: u8 = 32;
-            let expr2_0: u8 = 48;
-            let expr3_0: i8 = 16;
-            let expr4_0 = constructor_rxsbg_test(
-                ctx, &expr0_0, pattern6_0, pattern7_0, expr1_0, expr2_0, expr3_0,
-            )?;
-            let expr5_0 = IntCC::NotEqual;
-            let expr6_0 = C::intcc_as_cond(ctx, &expr5_0);
-            let expr7_0 = constructor_push_break_if(ctx, pattern0_0, &expr4_0, &expr6_0)?;
-            let expr8_0 = RxSBGOp::Insert;
-            let expr9_0: u8 = 32;
-            let expr10_0: u8 = 48;
-            let expr11_0: i8 = 16;
-            let expr12_0 = constructor_push_rxsbg(
-                ctx, pattern0_0, &expr8_0, pattern5_0, pattern6_0, pattern8_0, expr9_0, expr10_0,
-                expr11_0,
-            )?;
-            return Some(expr12_0);
-        }
-    }
-    return None;
-}
-
-// Generated as internal constructor for term atomic_store_impl.
-pub fn constructor_atomic_store_impl<C: Context>(
-    ctx: &mut C,
-    arg0: &SideEffectNoResult,
-) -> Option<InstOutput> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/s390x/lower.isle line 1858.
-    let expr0_0 = constructor_side_effect(ctx, pattern0_0)?;
-    let expr1_0 = constructor_fence_impl(ctx)?;
-    let expr2_0 = constructor_side_effect(ctx, &expr1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term icmp_val.
-pub fn constructor_icmp_val<C: Context>(
-    ctx: &mut C,
-    arg0: bool,
-    arg1: &IntCC,
-    arg2: Value,
-    arg3: Value,
-) -> Option<ProducesBool> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    if let Some(()) = C::signed(ctx, pattern1_0) {
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/s390x/lower.isle line 1925.
-        let expr0_0 = constructor_icmps_val(ctx, pattern0_0, pattern3_0, pattern4_0)?;
-        let expr1_0 = C::intcc_as_cond(ctx, pattern1_0);
-        let expr2_0 = constructor_bool(ctx, &expr0_0, &expr1_0)?;
-        return Some(expr2_0);
-    }
-    if let Some(()) = C::unsigned(ctx, pattern1_0) {
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/s390x/lower.isle line 1928.
-        let expr0_0 = constructor_icmpu_val(ctx, pattern0_0, pattern3_0, pattern4_0)?;
-        let expr1_0 = C::intcc_as_cond(ctx, pattern1_0);
-        let expr2_0 = constructor_bool(ctx, &expr0_0, &expr1_0)?;
-        return Some(expr2_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term icmps_val.
-pub fn constructor_icmps_val<C: Context>(
-    ctx: &mut C,
-    arg0: bool,
-    arg1: Value,
-    arg2: Value,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == true {
-        let pattern2_0 = arg1;
-        let pattern3_0 = C::value_type(ctx, pattern2_0);
-        if let Some(pattern4_0) = C::fits_in_64(ctx, pattern3_0) {
-            let pattern5_0 = arg2;
-            if let Some(pattern6_0) = C::sinkable_inst(ctx, pattern5_0) {
-                let pattern7_0 = C::inst_data(ctx, pattern6_0);
-                if let &InstructionData::Load {
-                    opcode: ref pattern8_0,
-                    arg: pattern8_1,
-                    flags: pattern8_2,
-                    offset: pattern8_3,
-                } = &pattern7_0
-                {
-                    match pattern8_0 {
-                        &Opcode::Sload16 => {
-                            if let Some(()) = C::bigendian(ctx, pattern8_2) {
-                                // Rule at src/isa/s390x/lower.isle line 1958.
-                                let expr0_0 = C::put_in_reg(ctx, pattern2_0);
-                                let expr1_0 = constructor_sink_sload16(ctx, pattern6_0)?;
-                                let expr2_0 = constructor_icmps_mem_sext16(
-                                    ctx, pattern4_0, expr0_0, &expr1_0,
-                                )?;
-                                return Some(expr2_0);
-                            }
-                        }
-                        &Opcode::Sload32 => {
-                            if let Some(()) = C::bigendian(ctx, pattern8_2) {
-                                // Rule at src/isa/s390x/lower.isle line 1960.
-                                let expr0_0 = C::put_in_reg(ctx, pattern2_0);
-                                let expr1_0 = constructor_sink_sload32(ctx, pattern6_0)?;
-                                let expr2_0 = constructor_icmps_mem_sext32(
-                                    ctx, pattern4_0, expr0_0, &expr1_0,
-                                )?;
-                                return Some(expr2_0);
-                            }
-                        }
-                        _ => {}
-                    }
-                }
-            }
-            let pattern6_0 = C::value_type(ctx, pattern5_0);
-            if pattern6_0 == I16 {
-                if let Some(pattern8_0) = C::sinkable_inst(ctx, pattern5_0) {
-                    let pattern9_0 = C::inst_data(ctx, pattern8_0);
-                    if let &InstructionData::Load {
-                        opcode: ref pattern10_0,
-                        arg: pattern10_1,
-                        flags: pattern10_2,
-                        offset: pattern10_3,
-                    } = &pattern9_0
-                    {
-                        if let &Opcode::Load = pattern10_0 {
-                            if let Some(()) = C::bigendian(ctx, pattern10_2) {
-                                // Rule at src/isa/s390x/lower.isle line 1954.
-                                let expr0_0 = constructor_ty_ext32(ctx, pattern4_0)?;
-                                let expr1_0 = constructor_put_in_reg_sext32(ctx, pattern2_0)?;
-                                let expr2_0 = constructor_sink_load(ctx, pattern8_0)?;
-                                let expr3_0 =
-                                    constructor_icmps_mem_sext16(ctx, expr0_0, expr1_0, &expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                        }
-                    }
-                }
-            }
-            if let Some(pattern7_0) = C::ty_32_or_64(ctx, pattern6_0) {
-                if let Some(pattern8_0) = C::sinkable_inst(ctx, pattern5_0) {
-                    let pattern9_0 = C::inst_data(ctx, pattern8_0);
-                    if let &InstructionData::Load {
-                        opcode: ref pattern10_0,
-                        arg: pattern10_1,
-                        flags: pattern10_2,
-                        offset: pattern10_3,
-                    } = &pattern9_0
-                    {
-                        if let &Opcode::Load = pattern10_0 {
-                            if let Some(()) = C::bigendian(ctx, pattern10_2) {
-                                // Rule at src/isa/s390x/lower.isle line 1950.
-                                let expr0_0 = C::put_in_reg(ctx, pattern2_0);
-                                let expr1_0 = constructor_sink_load(ctx, pattern8_0)?;
-                                let expr2_0 =
-                                    constructor_icmps_mem(ctx, pattern4_0, expr0_0, &expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                        }
-                    }
-                }
-            }
-        }
-    }
-    let pattern1_0 = arg1;
-    let pattern2_0 = C::value_type(ctx, pattern1_0);
-    if let Some(pattern3_0) = C::fits_in_64(ctx, pattern2_0) {
-        let pattern4_0 = arg2;
-        if let Some(pattern5_0) = C::i16_from_value(ctx, pattern4_0) {
-            // Rule at src/isa/s390x/lower.isle line 1944.
-            let expr0_0 = constructor_ty_ext32(ctx, pattern3_0)?;
-            let expr1_0 = constructor_put_in_reg_sext32(ctx, pattern1_0)?;
-            let expr2_0 = constructor_icmps_simm16(ctx, expr0_0, expr1_0, pattern5_0)?;
-            return Some(expr2_0);
-        }
-        if let Some(pattern5_0) = C::i32_from_value(ctx, pattern4_0) {
-            // Rule at src/isa/s390x/lower.isle line 1946.
-            let expr0_0 = constructor_ty_ext32(ctx, pattern3_0)?;
-            let expr1_0 = constructor_put_in_reg_sext32(ctx, pattern1_0)?;
-            let expr2_0 = constructor_icmps_simm32(ctx, expr0_0, expr1_0, pattern5_0)?;
-            return Some(expr2_0);
-        }
-        if let Some(pattern5_0) = C::def_inst(ctx, pattern4_0) {
-            let pattern6_0 = C::inst_data(ctx, pattern5_0);
-            if let &InstructionData::Unary {
-                opcode: ref pattern7_0,
-                arg: pattern7_1,
-            } = &pattern6_0
-            {
-                if let &Opcode::Sextend = pattern7_0 {
-                    let pattern9_0 = C::value_type(ctx, pattern7_1);
-                    if pattern9_0 == I32 {
-                        // Rule at src/isa/s390x/lower.isle line 1940.
-                        let expr0_0 = C::put_in_reg(ctx, pattern1_0);
-                        let expr1_0 = C::put_in_reg(ctx, pattern7_1);
-                        let expr2_0 =
-                            constructor_icmps_reg_sext32(ctx, pattern3_0, expr0_0, expr1_0)?;
-                        return Some(expr2_0);
-                    }
-                }
-            }
-        }
-        // Rule at src/isa/s390x/lower.isle line 1936.
-        let expr0_0 = constructor_ty_ext32(ctx, pattern3_0)?;
-        let expr1_0 = constructor_put_in_reg_sext32(ctx, pattern1_0)?;
-        let expr2_0 = constructor_put_in_reg_sext32(ctx, pattern4_0)?;
-        let expr3_0 = constructor_icmps_reg(ctx, expr0_0, expr1_0, expr2_0)?;
-        return Some(expr3_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term icmpu_val.
-pub fn constructor_icmpu_val<C: Context>(
-    ctx: &mut C,
-    arg0: bool,
-    arg1: Value,
-    arg2: Value,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == true {
-        let pattern2_0 = arg1;
-        let pattern3_0 = C::value_type(ctx, pattern2_0);
-        if let Some(pattern4_0) = C::fits_in_64(ctx, pattern3_0) {
-            let pattern5_0 = arg2;
-            if let Some(pattern6_0) = C::sinkable_inst(ctx, pattern5_0) {
-                let pattern7_0 = C::inst_data(ctx, pattern6_0);
-                if let &InstructionData::Load {
-                    opcode: ref pattern8_0,
-                    arg: pattern8_1,
-                    flags: pattern8_2,
-                    offset: pattern8_3,
-                } = &pattern7_0
-                {
-                    match pattern8_0 {
-                        &Opcode::Uload16 => {
-                            if let Some(pattern10_0) = C::def_inst(ctx, pattern8_1) {
-                                let pattern11_0 = C::inst_data(ctx, pattern10_0);
-                                if let &InstructionData::UnaryGlobalValue {
-                                    opcode: ref pattern12_0,
-                                    global_value: pattern12_1,
-                                } = &pattern11_0
-                                {
-                                    if let &Opcode::SymbolValue = pattern12_0 {
-                                        if let Some((pattern14_0, pattern14_1, pattern14_2)) =
-                                            C::symbol_value_data(ctx, pattern12_1)
-                                        {
-                                            if let Some(()) =
-                                                C::reloc_distance_near(ctx, pattern14_1)
-                                            {
-                                                let pattern16_0 =
-                                                    C::i64_from_offset(ctx, pattern8_3);
-                                                let closure17 = || {
-                                                    return Some(pattern14_2);
-                                                };
-                                                if let Some(pattern17_0) = closure17() {
-                                                    if let Some(pattern18_0) =
-                                                        C::memarg_symbol_offset_sum(
-                                                            ctx,
-                                                            pattern16_0,
-                                                            pattern17_0,
-                                                        )
-                                                    {
-                                                        let pattern19_0 =
-                                                            C::inst_data(ctx, pattern6_0);
-                                                        if let &InstructionData::Load {
-                                                            opcode: ref pattern20_0,
-                                                            arg: pattern20_1,
-                                                            flags: pattern20_2,
-                                                            offset: pattern20_3,
-                                                        } = &pattern19_0
-                                                        {
-                                                            if let &Opcode::Uload16 = pattern20_0 {
-                                                                if let Some(()) =
-                                                                    C::bigendian(ctx, pattern20_2)
-                                                                {
-                                                                    // Rule at src/isa/s390x/lower.isle line 1993.
-                                                                    let expr0_0 = C::put_in_reg(
-                                                                        ctx, pattern2_0,
-                                                                    );
-                                                                    let expr1_0 =
-                                                                        constructor_sink_uload16(
-                                                                            ctx, pattern6_0,
-                                                                        )?;
-                                                                    let expr2_0 = constructor_icmpu_mem_zext16(ctx, pattern4_0, expr0_0, &expr1_0)?;
-                                                                    return Some(expr2_0);
-                                                                }
-                                                            }
-                                                        }
-                                                    }
-                                                }
-                                            }
-                                        }
-                                    }
-                                }
-                            }
-                        }
-                        &Opcode::Uload32 => {
-                            if let Some(()) = C::bigendian(ctx, pattern8_2) {
-                                // Rule at src/isa/s390x/lower.isle line 1996.
-                                let expr0_0 = C::put_in_reg(ctx, pattern2_0);
-                                let expr1_0 = constructor_sink_uload32(ctx, pattern6_0)?;
-                                let expr2_0 = constructor_icmpu_mem_zext32(
-                                    ctx, pattern4_0, expr0_0, &expr1_0,
-                                )?;
-                                return Some(expr2_0);
-                            }
-                        }
-                        _ => {}
-                    }
-                }
-            }
-            let pattern6_0 = C::value_type(ctx, pattern5_0);
-            if pattern6_0 == I16 {
-                if let Some(pattern8_0) = C::sinkable_inst(ctx, pattern5_0) {
-                    let pattern9_0 = C::inst_data(ctx, pattern8_0);
-                    if let &InstructionData::Load {
-                        opcode: ref pattern10_0,
-                        arg: pattern10_1,
-                        flags: pattern10_2,
-                        offset: pattern10_3,
-                    } = &pattern9_0
-                    {
-                        if let &Opcode::Load = pattern10_0 {
-                            if let Some(pattern12_0) = C::def_inst(ctx, pattern10_1) {
-                                let pattern13_0 = C::inst_data(ctx, pattern12_0);
-                                if let &InstructionData::UnaryGlobalValue {
-                                    opcode: ref pattern14_0,
-                                    global_value: pattern14_1,
-                                } = &pattern13_0
-                                {
-                                    if let &Opcode::SymbolValue = pattern14_0 {
-                                        if let Some((pattern16_0, pattern16_1, pattern16_2)) =
-                                            C::symbol_value_data(ctx, pattern14_1)
-                                        {
-                                            if let Some(()) =
-                                                C::reloc_distance_near(ctx, pattern16_1)
-                                            {
-                                                let pattern18_0 =
-                                                    C::i64_from_offset(ctx, pattern10_3);
-                                                let closure19 = || {
-                                                    return Some(pattern16_2);
-                                                };
-                                                if let Some(pattern19_0) = closure19() {
-                                                    if let Some(pattern20_0) =
-                                                        C::memarg_symbol_offset_sum(
-                                                            ctx,
-                                                            pattern18_0,
-                                                            pattern19_0,
-                                                        )
-                                                    {
-                                                        let pattern21_0 =
-                                                            C::inst_data(ctx, pattern8_0);
-                                                        if let &InstructionData::Load {
-                                                            opcode: ref pattern22_0,
-                                                            arg: pattern22_1,
-                                                            flags: pattern22_2,
-                                                            offset: pattern22_3,
-                                                        } = &pattern21_0
-                                                        {
-                                                            if let &Opcode::Load = pattern22_0 {
-                                                                if let Some(()) =
-                                                                    C::bigendian(ctx, pattern22_2)
-                                                                {
-                                                                    // Rule at src/isa/s390x/lower.isle line 1986.
-                                                                    let expr0_0 =
-                                                                        constructor_ty_ext32(
-                                                                            ctx, pattern4_0,
-                                                                        )?;
-                                                                    let expr1_0 = constructor_put_in_reg_zext32(ctx, pattern2_0)?;
-                                                                    let expr2_0 =
-                                                                        constructor_sink_load(
-                                                                            ctx, pattern8_0,
-                                                                        )?;
-                                                                    let expr3_0 = constructor_icmpu_mem_zext16(ctx, expr0_0, expr1_0, &expr2_0)?;
-                                                                    return Some(expr3_0);
-                                                                }
-                                                            }
-                                                        }
-                                                    }
-                                                }
-                                            }
-                                        }
-                                    }
-                                }
-                            }
-                        }
-                    }
-                }
-            }
-            if let Some(pattern7_0) = C::ty_32_or_64(ctx, pattern6_0) {
-                if let Some(pattern8_0) = C::sinkable_inst(ctx, pattern5_0) {
-                    let pattern9_0 = C::inst_data(ctx, pattern8_0);
-                    if let &InstructionData::Load {
-                        opcode: ref pattern10_0,
-                        arg: pattern10_1,
-                        flags: pattern10_2,
-                        offset: pattern10_3,
-                    } = &pattern9_0
-                    {
-                        if let &Opcode::Load = pattern10_0 {
-                            if let Some(()) = C::bigendian(ctx, pattern10_2) {
-                                // Rule at src/isa/s390x/lower.isle line 1980.
-                                let expr0_0 = C::put_in_reg(ctx, pattern2_0);
-                                let expr1_0 = constructor_sink_load(ctx, pattern8_0)?;
-                                let expr2_0 =
-                                    constructor_icmpu_mem(ctx, pattern4_0, expr0_0, &expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                        }
-                    }
-                }
-            }
-        }
-    }
-    let pattern1_0 = arg1;
-    let pattern2_0 = C::value_type(ctx, pattern1_0);
-    if let Some(pattern3_0) = C::fits_in_64(ctx, pattern2_0) {
-        let pattern4_0 = arg2;
-        if let Some(pattern5_0) = C::u32_from_value(ctx, pattern4_0) {
-            // Rule at src/isa/s390x/lower.isle line 1976.
-            let expr0_0 = constructor_ty_ext32(ctx, pattern3_0)?;
-            let expr1_0 = constructor_put_in_reg_zext32(ctx, pattern1_0)?;
-            let expr2_0 = constructor_icmpu_uimm32(ctx, expr0_0, expr1_0, pattern5_0)?;
-            return Some(expr2_0);
-        }
-        if let Some(pattern5_0) = C::def_inst(ctx, pattern4_0) {
-            let pattern6_0 = C::inst_data(ctx, pattern5_0);
-            if let &InstructionData::Unary {
-                opcode: ref pattern7_0,
-                arg: pattern7_1,
-            } = &pattern6_0
-            {
-                if let &Opcode::Uextend = pattern7_0 {
-                    let pattern9_0 = C::value_type(ctx, pattern7_1);
-                    if pattern9_0 == I32 {
-                        // Rule at src/isa/s390x/lower.isle line 1972.
-                        let expr0_0 = C::put_in_reg(ctx, pattern1_0);
-                        let expr1_0 = C::put_in_reg(ctx, pattern7_1);
-                        let expr2_0 =
-                            constructor_icmpu_reg_zext32(ctx, pattern3_0, expr0_0, expr1_0)?;
-                        return Some(expr2_0);
-                    }
-                }
-            }
-        }
-        // Rule at src/isa/s390x/lower.isle line 1968.
-        let expr0_0 = constructor_ty_ext32(ctx, pattern3_0)?;
-        let expr1_0 = constructor_put_in_reg_zext32(ctx, pattern1_0)?;
-        let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern4_0)?;
-        let expr3_0 = constructor_icmpu_reg(ctx, expr0_0, expr1_0, expr2_0)?;
-        return Some(expr3_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term fcmp_val.
-pub fn constructor_fcmp_val<C: Context>(
-    ctx: &mut C,
-    arg0: &FloatCC,
-    arg1: Value,
-    arg2: Value,
-) -> Option<ProducesBool> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = C::value_type(ctx, pattern1_0);
-    let pattern3_0 = arg2;
-    // Rule at src/isa/s390x/lower.isle line 2009.
-    let expr0_0 = C::put_in_reg(ctx, pattern1_0);
-    let expr1_0 = C::put_in_reg(ctx, pattern3_0);
-    let expr2_0 = constructor_fcmp_reg(ctx, pattern2_0, expr0_0, expr1_0)?;
-    let expr3_0 = C::floatcc_as_cond(ctx, pattern0_0);
-    let expr4_0 = constructor_bool(ctx, &expr2_0, &expr3_0)?;
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term value_nonzero.
-pub fn constructor_value_nonzero<C: Context>(ctx: &mut C, arg0: Value) -> Option<ProducesBool> {
-    let pattern0_0 = arg0;
-    if let Some(pattern1_0) = C::def_inst(ctx, pattern0_0) {
-        let pattern2_0 = C::inst_data(ctx, pattern1_0);
-        match &pattern2_0 {
-            &InstructionData::FloatCompare {
-                opcode: ref pattern3_0,
-                args: ref pattern3_1,
-                cond: ref pattern3_2,
-            } => {
-                if let &Opcode::Fcmp = pattern3_0 {
-                    let (pattern5_0, pattern5_1) = C::unpack_value_array_2(ctx, pattern3_1);
-                    // Rule at src/isa/s390x/lower.isle line 2037.
-                    let expr0_0 = constructor_fcmp_val(ctx, pattern3_2, pattern5_0, pattern5_1)?;
-                    return Some(expr0_0);
-                }
-            }
-            &InstructionData::IntCompare {
-                opcode: ref pattern3_0,
-                args: ref pattern3_1,
-                cond: ref pattern3_2,
-            } => {
-                if let &Opcode::Icmp = pattern3_0 {
-                    let (pattern5_0, pattern5_1) = C::unpack_value_array_2(ctx, pattern3_1);
-                    // Rule at src/isa/s390x/lower.isle line 2036.
-                    let expr0_0: bool = false;
-                    let expr1_0 =
-                        constructor_icmp_val(ctx, expr0_0, pattern3_2, pattern5_0, pattern5_1)?;
-                    return Some(expr1_0);
-                }
-            }
-            &InstructionData::Unary {
-                opcode: ref pattern3_0,
-                arg: pattern3_1,
-            } => {
-                if let &Opcode::Bint = pattern3_0 {
-                    // Rule at src/isa/s390x/lower.isle line 2035.
-                    let expr0_0 = constructor_value_nonzero(ctx, pattern3_1)?;
-                    return Some(expr0_0);
-                }
-            }
-            _ => {}
-        }
-    }
-    let pattern1_0 = C::value_type(ctx, pattern0_0);
-    if let Some(pattern2_0) = C::gpr32_ty(ctx, pattern1_0) {
-        // Rule at src/isa/s390x/lower.isle line 2038.
-        let expr0_0: Type = I32;
-        let expr1_0 = constructor_put_in_reg_sext32(ctx, pattern0_0)?;
-        let expr2_0: i16 = 0;
-        let expr3_0 = constructor_icmps_simm16(ctx, expr0_0, expr1_0, expr2_0)?;
-        let expr4_0 = IntCC::NotEqual;
-        let expr5_0 = C::intcc_as_cond(ctx, &expr4_0);
-        let expr6_0 = constructor_bool(ctx, &expr3_0, &expr5_0)?;
-        return Some(expr6_0);
-    }
-    if let Some(pattern2_0) = C::gpr64_ty(ctx, pattern1_0) {
-        // Rule at src/isa/s390x/lower.isle line 2041.
-        let expr0_0: Type = I64;
-        let expr1_0 = C::put_in_reg(ctx, pattern0_0);
-        let expr2_0: i16 = 0;
-        let expr3_0 = constructor_icmps_simm16(ctx, expr0_0, expr1_0, expr2_0)?;
-        let expr4_0 = IntCC::NotEqual;
-        let expr5_0 = C::intcc_as_cond(ctx, &expr4_0);
-        let expr6_0 = constructor_bool(ctx, &expr3_0, &expr5_0)?;
-        return Some(expr6_0);
-    }
-    return None;
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/mod.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/mod.rs
deleted file mode 100644
index e9325c634..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/mod.rs
+++ /dev/null
@@ -1,307 +0,0 @@
-//! IBM Z 64-bit Instruction Set Architecture.
-
-use crate::ir::condcodes::IntCC;
-use crate::ir::Function;
-use crate::isa::s390x::settings as s390x_settings;
-#[cfg(feature = "unwind")]
-use crate::isa::unwind::systemv::RegisterMappingError;
-use crate::isa::{Builder as IsaBuilder, TargetIsa};
-use crate::machinst::{
-    compile, MachCompileResult, MachTextSectionBuilder, TextSectionBuilder, VCode,
-};
-use crate::result::CodegenResult;
-use crate::settings as shared_settings;
-
-use alloc::{boxed::Box, vec::Vec};
-use core::fmt;
-
-use regalloc::{PrettyPrint, RealRegUniverse, Reg};
-use target_lexicon::{Architecture, Triple};
-
-// New backend:
-mod abi;
-pub(crate) mod inst;
-mod lower;
-mod settings;
-
-use inst::create_reg_universe;
-
-use self::inst::EmitInfo;
-
-/// A IBM Z backend.
-pub struct S390xBackend {
-    triple: Triple,
-    flags: shared_settings::Flags,
-    isa_flags: s390x_settings::Flags,
-    reg_universe: RealRegUniverse,
-}
-
-impl S390xBackend {
-    /// Create a new IBM Z backend with the given (shared) flags.
-    pub fn new_with_flags(
-        triple: Triple,
-        flags: shared_settings::Flags,
-        isa_flags: s390x_settings::Flags,
-    ) -> S390xBackend {
-        let reg_universe = create_reg_universe(&flags);
-        S390xBackend {
-            triple,
-            flags,
-            isa_flags,
-            reg_universe,
-        }
-    }
-
-    /// This performs lowering to VCode, register-allocates the code, computes block layout and
-    /// finalizes branches. The result is ready for binary emission.
-    fn compile_vcode(
-        &self,
-        func: &Function,
-        flags: shared_settings::Flags,
-    ) -> CodegenResult<VCode<inst::Inst>> {
-        let emit_info = EmitInfo::new(flags.clone(), self.isa_flags.clone());
-        let abi = Box::new(abi::S390xABICallee::new(func, flags, self.isa_flags())?);
-        compile::compile::<S390xBackend>(func, self, abi, &self.reg_universe, emit_info)
-    }
-}
-
-impl TargetIsa for S390xBackend {
-    fn compile_function(
-        &self,
-        func: &Function,
-        want_disasm: bool,
-    ) -> CodegenResult<MachCompileResult> {
-        let flags = self.flags();
-        let vcode = self.compile_vcode(func, flags.clone())?;
-        let (buffer, bb_starts, bb_edges) = vcode.emit();
-        let frame_size = vcode.frame_size();
-        let value_labels_ranges = vcode.value_labels_ranges();
-        let stackslot_offsets = vcode.stackslot_offsets().clone();
-
-        let disasm = if want_disasm {
-            Some(vcode.show_rru(Some(&create_reg_universe(flags))))
-        } else {
-            None
-        };
-
-        let buffer = buffer.finish();
-
-        Ok(MachCompileResult {
-            buffer,
-            frame_size,
-            disasm,
-            value_labels_ranges,
-            stackslot_offsets,
-            bb_starts,
-            bb_edges,
-        })
-    }
-
-    fn name(&self) -> &'static str {
-        "s390x"
-    }
-
-    fn triple(&self) -> &Triple {
-        &self.triple
-    }
-
-    fn flags(&self) -> &shared_settings::Flags {
-        &self.flags
-    }
-
-    fn isa_flags(&self) -> Vec<shared_settings::Value> {
-        self.isa_flags.iter().collect()
-    }
-
-    fn unsigned_add_overflow_condition(&self) -> IntCC {
-        // The ADD LOGICAL family of instructions set the condition code
-        // differently from normal comparisons, in a way that cannot be
-        // represented by any of the standard IntCC values.  So we use a
-        // dummy value here, which gets remapped to the correct condition
-        // code mask during lowering.
-        IntCC::UnsignedGreaterThan
-    }
-
-    #[cfg(feature = "unwind")]
-    fn emit_unwind_info(
-        &self,
-        result: &MachCompileResult,
-        kind: crate::machinst::UnwindInfoKind,
-    ) -> CodegenResult<Option<crate::isa::unwind::UnwindInfo>> {
-        use crate::isa::unwind::UnwindInfo;
-        use crate::machinst::UnwindInfoKind;
-        Ok(match kind {
-            UnwindInfoKind::SystemV => {
-                let mapper = self::inst::unwind::systemv::RegisterMapper;
-                Some(UnwindInfo::SystemV(
-                    crate::isa::unwind::systemv::create_unwind_info_from_insts(
-                        &result.buffer.unwind_info[..],
-                        result.buffer.data().len(),
-                        &mapper,
-                    )?,
-                ))
-            }
-            _ => None,
-        })
-    }
-
-    #[cfg(feature = "unwind")]
-    fn create_systemv_cie(&self) -> Option<gimli::write::CommonInformationEntry> {
-        Some(inst::unwind::systemv::create_cie())
-    }
-
-    #[cfg(feature = "unwind")]
-    fn map_regalloc_reg_to_dwarf(&self, reg: Reg) -> Result<u16, RegisterMappingError> {
-        inst::unwind::systemv::map_reg(reg).map(|reg| reg.0)
-    }
-
-    fn text_section_builder(&self, num_funcs: u32) -> Box<dyn TextSectionBuilder> {
-        Box::new(MachTextSectionBuilder::<inst::Inst>::new(num_funcs))
-    }
-}
-
-impl fmt::Display for S390xBackend {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        f.debug_struct("MachBackend")
-            .field("name", &self.name())
-            .field("triple", &self.triple())
-            .field("flags", &format!("{}", self.flags()))
-            .finish()
-    }
-}
-
-/// Create a new `isa::Builder`.
-pub fn isa_builder(triple: Triple) -> IsaBuilder {
-    assert!(triple.architecture == Architecture::S390x);
-    IsaBuilder {
-        triple,
-        setup: s390x_settings::builder(),
-        constructor: |triple, shared_flags, builder| {
-            let isa_flags = s390x_settings::Flags::new(&shared_flags, builder);
-            let backend = S390xBackend::new_with_flags(triple, shared_flags, isa_flags);
-            Ok(Box::new(backend))
-        },
-    }
-}
-
-#[cfg(test)]
-mod test {
-    use super::*;
-    use crate::cursor::{Cursor, FuncCursor};
-    use crate::ir::types::*;
-    use crate::ir::{AbiParam, ExternalName, Function, InstBuilder, Signature};
-    use crate::isa::CallConv;
-    use crate::settings;
-    use crate::settings::Configurable;
-    use core::str::FromStr;
-    use target_lexicon::Triple;
-
-    #[test]
-    fn test_compile_function() {
-        let name = ExternalName::testcase("test0");
-        let mut sig = Signature::new(CallConv::SystemV);
-        sig.params.push(AbiParam::new(I32));
-        sig.returns.push(AbiParam::new(I32));
-        let mut func = Function::with_name_signature(name, sig);
-
-        let bb0 = func.dfg.make_block();
-        let arg0 = func.dfg.append_block_param(bb0, I32);
-
-        let mut pos = FuncCursor::new(&mut func);
-        pos.insert_block(bb0);
-        let v0 = pos.ins().iconst(I32, 0x1234);
-        let v1 = pos.ins().iadd(arg0, v0);
-        pos.ins().return_(&[v1]);
-
-        let mut shared_flags_builder = settings::builder();
-        shared_flags_builder.set("opt_level", "none").unwrap();
-        let shared_flags = settings::Flags::new(shared_flags_builder);
-        let isa_flags = s390x_settings::Flags::new(&shared_flags, s390x_settings::builder());
-        let backend = S390xBackend::new_with_flags(
-            Triple::from_str("s390x").unwrap(),
-            shared_flags,
-            isa_flags,
-        );
-        let result = backend
-            .compile_function(&mut func, /* want_disasm = */ false)
-            .unwrap();
-        let code = result.buffer.data();
-
-        // ahi %r2, 0x1234
-        // br %r14
-        let golden = vec![0xa7, 0x2a, 0x12, 0x34, 0x07, 0xfe];
-
-        assert_eq!(code, &golden[..]);
-    }
-
-    #[test]
-    fn test_branch_lowering() {
-        let name = ExternalName::testcase("test0");
-        let mut sig = Signature::new(CallConv::SystemV);
-        sig.params.push(AbiParam::new(I32));
-        sig.returns.push(AbiParam::new(I32));
-        let mut func = Function::with_name_signature(name, sig);
-
-        let bb0 = func.dfg.make_block();
-        let arg0 = func.dfg.append_block_param(bb0, I32);
-        let bb1 = func.dfg.make_block();
-        let bb2 = func.dfg.make_block();
-        let bb3 = func.dfg.make_block();
-
-        let mut pos = FuncCursor::new(&mut func);
-        pos.insert_block(bb0);
-        let v0 = pos.ins().iconst(I32, 0x1234);
-        let v1 = pos.ins().iadd(arg0, v0);
-        pos.ins().brnz(v1, bb1, &[]);
-        pos.ins().jump(bb2, &[]);
-        pos.insert_block(bb1);
-        pos.ins().brnz(v1, bb2, &[]);
-        pos.ins().jump(bb3, &[]);
-        pos.insert_block(bb2);
-        let v2 = pos.ins().iadd(v1, v0);
-        pos.ins().brnz(v2, bb2, &[]);
-        pos.ins().jump(bb1, &[]);
-        pos.insert_block(bb3);
-        let v3 = pos.ins().isub(v1, v0);
-        pos.ins().return_(&[v3]);
-
-        let mut shared_flags_builder = settings::builder();
-        shared_flags_builder.set("opt_level", "none").unwrap();
-        let shared_flags = settings::Flags::new(shared_flags_builder);
-        let isa_flags = s390x_settings::Flags::new(&shared_flags, s390x_settings::builder());
-        let backend = S390xBackend::new_with_flags(
-            Triple::from_str("s390x").unwrap(),
-            shared_flags,
-            isa_flags,
-        );
-        let result = backend
-            .compile_function(&mut func, /* want_disasm = */ false)
-            .unwrap();
-        let code = result.buffer.data();
-
-        // FIXME: the branching logic should be optimized more
-
-        // ahi %r2, 4660
-        // chi %r2, 0
-        // jglh label1 ; jg label2
-        // jg label6
-        // jg label3
-        // ahik %r3, %r2, 4660
-        // chi %r3, 0
-        // jglh label4 ; jg label5
-        // jg label3
-        // jg label6
-        // chi %r2, 0
-        // jglh label7 ; jg label8
-        // jg label3
-        // ahi %r2, -4660
-        // br %r14
-        let golden = vec![
-            167, 42, 18, 52, 167, 46, 0, 0, 192, 100, 0, 0, 0, 11, 236, 50, 18, 52, 0, 216, 167,
-            62, 0, 0, 192, 100, 255, 255, 255, 251, 167, 46, 0, 0, 192, 100, 255, 255, 255, 246,
-            167, 42, 237, 204, 7, 254,
-        ];
-
-        assert_eq!(code, &golden[..]);
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/settings.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/settings.rs
deleted file mode 100644
index 69859cee4..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/s390x/settings.rs
+++ /dev/null
@@ -1,9 +0,0 @@
-//! S390X Settings.
-
-use crate::settings::{self, detail, Builder, Value};
-use core::fmt;
-
-// Include code generated by `cranelift-codegen/meta/src/gen_settings.rs:`. This file contains a
-// public `Flags` struct with an impl for all of the settings defined in
-// `cranelift-codegen/meta/src/isa/s390x/settings.rs`.
-include!(concat!(env!("OUT_DIR"), "/settings-s390x.rs"));
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/unwind.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/unwind.rs
deleted file mode 100644
index 4dd8ae78d..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/unwind.rs
+++ /dev/null
@@ -1,182 +0,0 @@
-//! Represents information relating to function unwinding.
-
-use regalloc::RealReg;
-
-#[cfg(feature = "enable-serde")]
-use serde::{Deserialize, Serialize};
-
-#[cfg(feature = "unwind")]
-pub mod systemv;
-
-#[cfg(feature = "unwind")]
-pub mod winx64;
-
-/// Represents unwind information for a single function.
-#[derive(Clone, Debug, PartialEq, Eq)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-#[non_exhaustive]
-pub enum UnwindInfo {
-    /// Windows x64 ABI unwind information.
-    #[cfg(feature = "unwind")]
-    WindowsX64(winx64::UnwindInfo),
-    /// System V ABI unwind information.
-    #[cfg(feature = "unwind")]
-    SystemV(systemv::UnwindInfo),
-}
-
-/// Unwind pseudoinstruction used in VCode backends: represents that
-/// at the present location, an action has just been taken.
-///
-/// VCode backends always emit unwind info that is relative to a frame
-/// pointer, because we are planning to allow for dynamic frame allocation,
-/// and because it makes the design quite a lot simpler in general: we don't
-/// have to be precise about SP adjustments throughout the body of the function.
-///
-/// We include only unwind info for prologues at this time. Note that unwind
-/// info for epilogues is only necessary if one expects to unwind while within
-/// the last few instructions of the function (after FP has been restored) or
-/// if one wishes to instruction-step through the epilogue and see a backtrace
-/// at every point. This is not necessary for correct operation otherwise and so
-/// we simplify the world a bit by omitting epilogue information. (Note that
-/// some platforms also don't require or have a way to describe unwind
-/// information for epilogues at all: for example, on Windows, the `UNWIND_INFO`
-/// format only stores information for the function prologue.)
-///
-/// Because we are defining an abstraction over multiple unwind formats (at
-/// least Windows/fastcall and System V) and multiple architectures (at least
-/// x86-64 and aarch64), we have to be a little bit flexible in how we describe
-/// the frame. However, it turns out that a least-common-denominator prologue
-/// works for all of the cases we have to worry about today!
-///
-/// We assume the stack looks something like this:
-///
-///
-/// ```plain
-///                  +----------------------------------------------+
-///                  | stack arg area, etc (according to ABI)       |
-///                  | ...                                          |
-///   SP at call --> +----------------------------------------------+
-///                  | return address (pushed by HW or SW)          |
-///                  +----------------------------------------------+
-///                  | old frame pointer (FP)                       |
-///   FP in this --> +----------------------------------------------+
-///   function       | clobbered callee-save registers              |
-///                  | ...                                          |
-///   start of   --> +----------------------------------------------+
-///   clobbers       | (rest of function's frame, irrelevant here)  |
-///                  | ...                                          |
-///   SP in this --> +----------------------------------------------+
-///   function
-/// ```
-///
-/// We assume that the prologue consists of:
-///
-/// * `PushFrameRegs`: A push operation that adds the old FP to the stack (and
-///    maybe the link register, on architectures that do not push return addresses
-///    in hardware)
-/// * `DefineFrame`: An update that sets FP to SP to establish a new frame
-/// * `SaveReg`: A number of stores or pushes to the stack to save clobbered registers
-///
-/// Each of these steps has a corresponding pseudo-instruction. At each step,
-/// we need some information to determine where the current stack frame is
-/// relative to SP or FP. When the `PushFrameRegs` occurs, we need to know how
-/// much SP was decremented by, so we can allow the unwinder to continue to find
-/// the caller's frame. When we define the new frame, we need to know where FP
-/// is in relation to "SP at call" and also "start of clobbers", because
-/// different unwind formats define one or the other of those as the anchor by
-/// which we define the frame. Finally, when registers are saved, we need to
-/// know which ones, and where.
-///
-/// Different unwind formats work differently; here is a whirlwind tour of how
-/// they define frames to help understanding:
-///
-/// - Windows unwind information defines a frame that must start below the
-///   clobber area, because all clobber-save offsets are non-negative. We set it
-///   at the "start of clobbers" in the figure above. The `UNWIND_INFO` contains
-///   a "frame pointer offset" field; when we define the new frame, the frame is
-///   understood to be the value of FP (`RBP`) *minus* this offset. In other
-///   words, the FP is *at the frame pointer offset* relative to the
-///   start-of-clobber-frame. We use the "FP offset down to clobber area" offset
-///   to generate this info.
-///
-/// - System V unwind information defines a frame in terms of the CFA
-///   (call-frame address), which is equal to the "SP at call" above. SysV
-///   allows negative offsets, so there is no issue defining clobber-save
-///   locations in terms of CFA. The format allows us to define CFA flexibly in
-///   terms of any register plus an offset; we define it in terms of FP plus
-///   the clobber-to-caller-SP offset once FP is established.
-///
-/// Note that certain architectures impose limits on offsets: for example, on
-/// Windows, the base of the clobber area must not be more than 240 bytes below
-/// FP.
-///
-/// Unwind pseudoinstructions are emitted inline by ABI code as it generates
-/// a prologue. Thus, for the usual case, a prologue might look like (using x64
-/// as an example):
-///
-/// ```plain
-/// push rbp
-/// unwind UnwindInst::PushFrameRegs { offset_upward_to_caller_sp: 16 }
-/// mov rbp, rsp
-/// unwind UnwindInst::DefineNewFrame { offset_upward_to_caller_sp: 16,
-///                                     offset_downward_to_clobbers: 16 }
-/// sub rsp, 32
-/// mov [rsp+16], r12
-/// unwind UnwindInst::SaveReg { reg: R12, clobber_offset: 0 }
-/// mov [rsp+24], r13
-/// unwind UnwindInst::SaveReg { reg: R13, clobber_offset: 8 }
-/// ...
-/// ```
-#[derive(Clone, Debug, PartialEq, Eq)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub enum UnwindInst {
-    /// The frame-pointer register for this architecture has just been pushed to
-    /// the stack (and on architectures where return-addresses are not pushed by
-    /// hardware, the link register as well). The FP has not been set to this
-    /// frame yet. The current location of SP is such that
-    /// `offset_upward_to_caller_sp` is the distance to SP-at-callsite (our
-    /// caller's frame).
-    PushFrameRegs {
-        /// The offset from the current SP (after push) to the SP at
-        /// caller's callsite.
-        offset_upward_to_caller_sp: u32,
-    },
-    /// The frame-pointer register for this architecture has just been
-    /// set to the current stack location. We wish to define a new
-    /// frame that is anchored on this new FP value. Offsets are provided
-    /// upward to the caller's stack frame and downward toward the clobber
-    /// area. We expect this pseudo-op to come after `PushFrameRegs`.
-    DefineNewFrame {
-        /// The offset from the current SP and FP value upward to the value of
-        /// SP at the callsite that invoked us.
-        offset_upward_to_caller_sp: u32,
-        /// The offset from the current SP and FP value downward to the start of
-        /// the clobber area.
-        offset_downward_to_clobbers: u32,
-    },
-    /// The stack pointer was adjusted to allocate the stack.
-    StackAlloc {
-        /// Size to allocate.
-        size: u32,
-    },
-    /// The stack slot at the given offset from the clobber-area base has been
-    /// used to save the given register.
-    ///
-    /// Given that `CreateFrame` has occurred first with some
-    /// `offset_downward_to_clobbers`, `SaveReg` with `clobber_offset` indicates
-    /// that the value of `reg` is saved on the stack at address `FP -
-    /// offset_downward_to_clobbers + clobber_offset`.
-    SaveReg {
-        /// The offset from the start of the clobber area to this register's
-        /// stack location.
-        clobber_offset: u32,
-        /// The saved register.
-        reg: RealReg,
-    },
-    /// Defines if the aarch64-specific pointer authentication available for ARM v8.3+ devices
-    /// is enabled for certain pointers or not.
-    Aarch64SetPointerAuth {
-        /// Whether return addresses (hold in LR) contain a pointer-authentication code.
-        return_addresses: bool,
-    },
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/unwind/systemv.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/unwind/systemv.rs
deleted file mode 100644
index b914f13a7..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/unwind/systemv.rs
+++ /dev/null
@@ -1,271 +0,0 @@
-//! System V ABI unwind information.
-
-use crate::binemit::CodeOffset;
-use crate::isa::unwind::UnwindInst;
-use crate::result::{CodegenError, CodegenResult};
-use alloc::vec::Vec;
-use gimli::write::{Address, FrameDescriptionEntry};
-
-#[cfg(feature = "enable-serde")]
-use serde::{Deserialize, Serialize};
-
-type Register = u16;
-
-/// Enumerate the errors possible in mapping Cranelift registers to their DWARF equivalent.
-#[allow(missing_docs)]
-#[derive(Debug, PartialEq, Eq)]
-pub enum RegisterMappingError {
-    MissingBank,
-    UnsupportedArchitecture,
-    UnsupportedRegisterBank(&'static str),
-}
-
-// This is manually implementing Error and Display instead of using thiserror to reduce the amount
-// of dependencies used by Cranelift.
-impl std::error::Error for RegisterMappingError {}
-
-impl std::fmt::Display for RegisterMappingError {
-    fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result {
-        match self {
-            RegisterMappingError::MissingBank => write!(f, "unable to find bank for register info"),
-            RegisterMappingError::UnsupportedArchitecture => write!(
-                f,
-                "register mapping is currently only implemented for x86_64"
-            ),
-            RegisterMappingError::UnsupportedRegisterBank(bank) => {
-                write!(f, "unsupported register bank: {}", bank)
-            }
-        }
-    }
-}
-
-// This mirrors gimli's CallFrameInstruction, but is serializable
-// This excludes CfaExpression, Expression, ValExpression due to
-// https://github.com/gimli-rs/gimli/issues/513.
-// TODO: if gimli ever adds serialization support, remove this type
-#[derive(Clone, Debug, PartialEq, Eq)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub(crate) enum CallFrameInstruction {
-    Cfa(Register, i32),
-    CfaRegister(Register),
-    CfaOffset(i32),
-    Restore(Register),
-    Undefined(Register),
-    SameValue(Register),
-    Offset(Register, i32),
-    ValOffset(Register, i32),
-    Register(Register, Register),
-    RememberState,
-    RestoreState,
-    ArgsSize(u32),
-    /// Enables or disables pointer authentication on aarch64 platforms post ARMv8.3.  This
-    /// particular item maps to gimli::ValExpression(RA_SIGN_STATE, lit0/lit1).
-    Aarch64SetPointerAuth {
-        return_addresses: bool,
-    },
-}
-
-impl From<gimli::write::CallFrameInstruction> for CallFrameInstruction {
-    fn from(cfi: gimli::write::CallFrameInstruction) -> Self {
-        use gimli::write::CallFrameInstruction;
-
-        match cfi {
-            CallFrameInstruction::Cfa(reg, offset) => Self::Cfa(reg.0, offset),
-            CallFrameInstruction::CfaRegister(reg) => Self::CfaRegister(reg.0),
-            CallFrameInstruction::CfaOffset(offset) => Self::CfaOffset(offset),
-            CallFrameInstruction::Restore(reg) => Self::Restore(reg.0),
-            CallFrameInstruction::Undefined(reg) => Self::Undefined(reg.0),
-            CallFrameInstruction::SameValue(reg) => Self::SameValue(reg.0),
-            CallFrameInstruction::Offset(reg, offset) => Self::Offset(reg.0, offset),
-            CallFrameInstruction::ValOffset(reg, offset) => Self::ValOffset(reg.0, offset),
-            CallFrameInstruction::Register(reg1, reg2) => Self::Register(reg1.0, reg2.0),
-            CallFrameInstruction::RememberState => Self::RememberState,
-            CallFrameInstruction::RestoreState => Self::RestoreState,
-            CallFrameInstruction::ArgsSize(size) => Self::ArgsSize(size),
-            _ => {
-                // Cranelift's unwind support does not generate `CallFrameInstruction`s with
-                // Expression at this moment, and it is not trivial to
-                // serialize such instructions.
-                panic!("CallFrameInstruction with Expression not supported");
-            }
-        }
-    }
-}
-
-impl Into<gimli::write::CallFrameInstruction> for CallFrameInstruction {
-    fn into(self) -> gimli::write::CallFrameInstruction {
-        use gimli::{write::CallFrameInstruction, write::Expression, Register};
-
-        match self {
-            Self::Cfa(reg, offset) => CallFrameInstruction::Cfa(Register(reg), offset),
-            Self::CfaRegister(reg) => CallFrameInstruction::CfaRegister(Register(reg)),
-            Self::CfaOffset(offset) => CallFrameInstruction::CfaOffset(offset),
-            Self::Restore(reg) => CallFrameInstruction::Restore(Register(reg)),
-            Self::Undefined(reg) => CallFrameInstruction::Undefined(Register(reg)),
-            Self::SameValue(reg) => CallFrameInstruction::SameValue(Register(reg)),
-            Self::Offset(reg, offset) => CallFrameInstruction::Offset(Register(reg), offset),
-            Self::ValOffset(reg, offset) => CallFrameInstruction::ValOffset(Register(reg), offset),
-            Self::Register(reg1, reg2) => {
-                CallFrameInstruction::Register(Register(reg1), Register(reg2))
-            }
-            Self::RememberState => CallFrameInstruction::RememberState,
-            Self::RestoreState => CallFrameInstruction::RestoreState,
-            Self::ArgsSize(size) => CallFrameInstruction::ArgsSize(size),
-            Self::Aarch64SetPointerAuth { return_addresses } => {
-                // To enable pointer authentication for return addresses in dwarf directives, we
-                // use a small dwarf expression that sets the value of the pseudo-register
-                // RA_SIGN_STATE (RA stands for return address) to 0 or 1. This behavior is
-                // documented in
-                // https://github.com/ARM-software/abi-aa/blob/master/aadwarf64/aadwarf64.rst#41dwarf-register-names.
-                let mut expr = Expression::new();
-                expr.op(if return_addresses {
-                    gimli::DW_OP_lit1
-                } else {
-                    gimli::DW_OP_lit0
-                });
-                const RA_SIGN_STATE: Register = Register(34);
-                CallFrameInstruction::ValExpression(RA_SIGN_STATE, expr)
-            }
-        }
-    }
-}
-
-/// Maps UnwindInfo register to gimli's index space.
-pub(crate) trait RegisterMapper<Reg> {
-    /// Maps Reg.
-    fn map(&self, reg: Reg) -> Result<Register, RegisterMappingError>;
-    /// Gets stack pointer register.
-    fn sp(&self) -> Register;
-    /// Gets the frame pointer register, if any.
-    fn fp(&self) -> Option<Register> {
-        None
-    }
-    /// Gets the link register, if any.
-    fn lr(&self) -> Option<Register> {
-        None
-    }
-    /// What is the offset from saved FP to saved LR?
-    fn lr_offset(&self) -> Option<u32> {
-        None
-    }
-}
-
-/// Represents unwind information for a single System V ABI function.
-///
-/// This representation is not ISA specific.
-#[derive(Clone, Debug, PartialEq, Eq)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub struct UnwindInfo {
-    instructions: Vec<(u32, CallFrameInstruction)>,
-    len: u32,
-}
-
-pub(crate) fn create_unwind_info_from_insts<MR: RegisterMapper<regalloc::Reg>>(
-    insts: &[(CodeOffset, UnwindInst)],
-    code_len: usize,
-    mr: &MR,
-) -> CodegenResult<UnwindInfo> {
-    let mut instructions = vec![];
-
-    let mut cfa_offset = 0;
-    let mut clobber_offset_to_cfa = 0;
-    for &(instruction_offset, ref inst) in insts {
-        match inst {
-            &UnwindInst::PushFrameRegs {
-                offset_upward_to_caller_sp,
-            } => {
-                // Define CFA in terms of current SP (SP changed and we haven't
-                // set FP yet).
-                instructions.push((
-                    instruction_offset,
-                    CallFrameInstruction::CfaOffset(offset_upward_to_caller_sp as i32),
-                ));
-                // Note that we saved the old FP value on the stack.  Use of this
-                // operation implies that the target defines a FP register.
-                instructions.push((
-                    instruction_offset,
-                    CallFrameInstruction::Offset(
-                        mr.fp().unwrap(),
-                        -(offset_upward_to_caller_sp as i32),
-                    ),
-                ));
-                // If there is a link register on this architecture, note that
-                // we saved it as well.
-                if let Some(lr) = mr.lr() {
-                    instructions.push((
-                        instruction_offset,
-                        CallFrameInstruction::Offset(
-                            lr,
-                            -(offset_upward_to_caller_sp as i32)
-                                + mr.lr_offset().expect("LR offset not provided") as i32,
-                        ),
-                    ));
-                }
-            }
-            &UnwindInst::DefineNewFrame {
-                offset_upward_to_caller_sp,
-                offset_downward_to_clobbers,
-            } => {
-                // Define CFA in terms of FP. Note that we assume it was already
-                // defined correctly in terms of the current SP, and FP has just
-                // been set to the current SP, so we do not need to change the
-                // offset, only the register.  (This is done only if the target
-                // defines a frame pointer register.)
-                if let Some(fp) = mr.fp() {
-                    instructions.push((instruction_offset, CallFrameInstruction::CfaRegister(fp)));
-                }
-                // Record initial CFA offset.  This will be used with later
-                // StackAlloc calls if we do not have a frame pointer.
-                cfa_offset = offset_upward_to_caller_sp;
-                // Record distance from CFA downward to clobber area so we can
-                // express clobber offsets later in terms of CFA.
-                clobber_offset_to_cfa = offset_upward_to_caller_sp + offset_downward_to_clobbers;
-            }
-            &UnwindInst::StackAlloc { size } => {
-                // If we do not use a frame pointer, we need to update the
-                // CFA offset whenever the stack pointer changes.
-                if mr.fp().is_none() {
-                    cfa_offset += size;
-                    instructions.push((
-                        instruction_offset,
-                        CallFrameInstruction::CfaOffset(cfa_offset as i32),
-                    ));
-                }
-            }
-            &UnwindInst::SaveReg {
-                clobber_offset,
-                reg,
-            } => {
-                let reg = mr
-                    .map(reg.to_reg())
-                    .map_err(|e| CodegenError::RegisterMappingError(e))?;
-                let off = (clobber_offset as i32) - (clobber_offset_to_cfa as i32);
-                instructions.push((instruction_offset, CallFrameInstruction::Offset(reg, off)));
-            }
-            &UnwindInst::Aarch64SetPointerAuth { return_addresses } => {
-                instructions.push((
-                    instruction_offset,
-                    CallFrameInstruction::Aarch64SetPointerAuth { return_addresses },
-                ));
-            }
-        }
-    }
-
-    Ok(UnwindInfo {
-        instructions,
-        len: code_len as u32,
-    })
-}
-
-impl UnwindInfo {
-    /// Converts the unwind information into a `FrameDescriptionEntry`.
-    pub fn to_fde(&self, address: Address) -> gimli::write::FrameDescriptionEntry {
-        let mut fde = FrameDescriptionEntry::new(address, self.len);
-
-        for (offset, inst) in &self.instructions {
-            fde.add_instruction(*offset, inst.clone().into());
-        }
-
-        fde
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/unwind/winx64.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/unwind/winx64.rs
deleted file mode 100644
index 68cb38b75..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/unwind/winx64.rs
+++ /dev/null
@@ -1,334 +0,0 @@
-//! Windows x64 ABI unwind information.
-
-use crate::result::{CodegenError, CodegenResult};
-use alloc::vec::Vec;
-use log::warn;
-#[cfg(feature = "enable-serde")]
-use serde::{Deserialize, Serialize};
-
-use crate::binemit::CodeOffset;
-use crate::isa::unwind::UnwindInst;
-
-/// Maximum (inclusive) size of a "small" stack allocation
-const SMALL_ALLOC_MAX_SIZE: u32 = 128;
-/// Maximum (inclusive) size of a "large" stack allocation that can represented in 16-bits
-const LARGE_ALLOC_16BIT_MAX_SIZE: u32 = 524280;
-
-struct Writer<'a> {
-    buf: &'a mut [u8],
-    offset: usize,
-}
-
-impl<'a> Writer<'a> {
-    pub fn new(buf: &'a mut [u8]) -> Self {
-        Self { buf, offset: 0 }
-    }
-
-    fn write_u8(&mut self, v: u8) {
-        self.buf[self.offset] = v;
-        self.offset += 1;
-    }
-
-    fn write_u16_le(&mut self, v: u16) {
-        self.buf[self.offset..(self.offset + 2)].copy_from_slice(&v.to_le_bytes());
-        self.offset += 2;
-    }
-
-    fn write_u32_le(&mut self, v: u32) {
-        self.buf[self.offset..(self.offset + 4)].copy_from_slice(&v.to_le_bytes());
-        self.offset += 4;
-    }
-}
-
-/// The supported unwind codes for the x64 Windows ABI.
-///
-/// See: <https://docs.microsoft.com/en-us/cpp/build/exception-handling-x64>
-/// Only what is needed to describe the prologues generated by the Cranelift x86 ISA are represented here.
-/// Note: the Cranelift x86 ISA RU enum matches the Windows unwind GPR encoding values.
-#[allow(dead_code)]
-#[derive(Clone, Debug, PartialEq, Eq)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub(crate) enum UnwindCode {
-    PushRegister {
-        instruction_offset: u8,
-        reg: u8,
-    },
-    SaveReg {
-        instruction_offset: u8,
-        reg: u8,
-        stack_offset: u32,
-    },
-    SaveXmm {
-        instruction_offset: u8,
-        reg: u8,
-        stack_offset: u32,
-    },
-    StackAlloc {
-        instruction_offset: u8,
-        size: u32,
-    },
-    SetFPReg {
-        instruction_offset: u8,
-    },
-}
-
-impl UnwindCode {
-    fn emit(&self, writer: &mut Writer) {
-        enum UnwindOperation {
-            PushNonvolatileRegister = 0,
-            LargeStackAlloc = 1,
-            SmallStackAlloc = 2,
-            SetFPReg = 3,
-            SaveNonVolatileRegister = 4,
-            SaveNonVolatileRegisterFar = 5,
-            SaveXmm128 = 8,
-            SaveXmm128Far = 9,
-        }
-
-        match self {
-            Self::PushRegister {
-                instruction_offset,
-                reg,
-            } => {
-                writer.write_u8(*instruction_offset);
-                writer.write_u8((*reg << 4) | (UnwindOperation::PushNonvolatileRegister as u8));
-            }
-            Self::SaveReg {
-                instruction_offset,
-                reg,
-                stack_offset,
-            }
-            | Self::SaveXmm {
-                instruction_offset,
-                reg,
-                stack_offset,
-            } => {
-                let is_xmm = match self {
-                    Self::SaveXmm { .. } => true,
-                    _ => false,
-                };
-                let (op_small, op_large) = if is_xmm {
-                    (UnwindOperation::SaveXmm128, UnwindOperation::SaveXmm128Far)
-                } else {
-                    (
-                        UnwindOperation::SaveNonVolatileRegister,
-                        UnwindOperation::SaveNonVolatileRegisterFar,
-                    )
-                };
-                writer.write_u8(*instruction_offset);
-                let scaled_stack_offset = stack_offset / 16;
-                if scaled_stack_offset <= core::u16::MAX as u32 {
-                    writer.write_u8((*reg << 4) | (op_small as u8));
-                    writer.write_u16_le(scaled_stack_offset as u16);
-                } else {
-                    writer.write_u8((*reg << 4) | (op_large as u8));
-                    writer.write_u16_le(*stack_offset as u16);
-                    writer.write_u16_le((stack_offset >> 16) as u16);
-                }
-            }
-            Self::StackAlloc {
-                instruction_offset,
-                size,
-            } => {
-                // Stack allocations on Windows must be a multiple of 8 and be at least 1 slot
-                assert!(*size >= 8);
-                assert!((*size % 8) == 0);
-
-                writer.write_u8(*instruction_offset);
-                if *size <= SMALL_ALLOC_MAX_SIZE {
-                    writer.write_u8(
-                        ((((*size - 8) / 8) as u8) << 4) | UnwindOperation::SmallStackAlloc as u8,
-                    );
-                } else if *size <= LARGE_ALLOC_16BIT_MAX_SIZE {
-                    writer.write_u8(UnwindOperation::LargeStackAlloc as u8);
-                    writer.write_u16_le((*size / 8) as u16);
-                } else {
-                    writer.write_u8((1 << 4) | (UnwindOperation::LargeStackAlloc as u8));
-                    writer.write_u32_le(*size);
-                }
-            }
-            Self::SetFPReg { instruction_offset } => {
-                writer.write_u8(*instruction_offset);
-                writer.write_u8(UnwindOperation::SetFPReg as u8);
-            }
-        }
-    }
-
-    fn node_count(&self) -> usize {
-        match self {
-            Self::StackAlloc { size, .. } => {
-                if *size <= SMALL_ALLOC_MAX_SIZE {
-                    1
-                } else if *size <= LARGE_ALLOC_16BIT_MAX_SIZE {
-                    2
-                } else {
-                    3
-                }
-            }
-            Self::SaveXmm { stack_offset, .. } | Self::SaveReg { stack_offset, .. } => {
-                if *stack_offset <= core::u16::MAX as u32 {
-                    2
-                } else {
-                    3
-                }
-            }
-            _ => 1,
-        }
-    }
-}
-
-pub(crate) enum MappedRegister {
-    Int(u8),
-    Xmm(u8),
-}
-
-/// Maps UnwindInfo register to Windows x64 unwind data.
-pub(crate) trait RegisterMapper<Reg> {
-    /// Maps a Reg to a Windows unwind register number.
-    fn map(reg: Reg) -> MappedRegister;
-}
-
-/// Represents Windows x64 unwind information.
-///
-/// For information about Windows x64 unwind info, see:
-/// <https://docs.microsoft.com/en-us/cpp/build/exception-handling-x64>
-#[derive(Clone, Debug, PartialEq, Eq)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub struct UnwindInfo {
-    pub(crate) flags: u8,
-    pub(crate) prologue_size: u8,
-    pub(crate) frame_register: Option<u8>,
-    pub(crate) frame_register_offset: u8,
-    pub(crate) unwind_codes: Vec<UnwindCode>,
-}
-
-impl UnwindInfo {
-    /// Gets the emit size of the unwind information, in bytes.
-    pub fn emit_size(&self) -> usize {
-        let node_count = self.node_count();
-
-        // Calculation of the size requires no SEH handler or chained info
-        assert!(self.flags == 0);
-
-        // Size of fixed part of UNWIND_INFO is 4 bytes
-        // Then comes the UNWIND_CODE nodes (2 bytes each)
-        // Then comes 2 bytes of padding for the unwind codes if necessary
-        // Next would come the SEH data, but we assert above that the function doesn't have SEH data
-
-        4 + (node_count * 2) + if (node_count & 1) == 1 { 2 } else { 0 }
-    }
-
-    /// Emits the unwind information into the given mutable byte slice.
-    ///
-    /// This function will panic if the slice is not at least `emit_size` in length.
-    pub fn emit(&self, buf: &mut [u8]) {
-        const UNWIND_INFO_VERSION: u8 = 1;
-
-        let node_count = self.node_count();
-        assert!(node_count <= 256);
-
-        let mut writer = Writer::new(buf);
-
-        writer.write_u8((self.flags << 3) | UNWIND_INFO_VERSION);
-        writer.write_u8(self.prologue_size);
-        writer.write_u8(node_count as u8);
-
-        if let Some(reg) = self.frame_register {
-            writer.write_u8((self.frame_register_offset << 4) | reg);
-        } else {
-            writer.write_u8(0);
-        }
-
-        // Unwind codes are written in reverse order (prologue offset descending)
-        for code in self.unwind_codes.iter().rev() {
-            code.emit(&mut writer);
-        }
-
-        // To keep a 32-bit alignment, emit 2 bytes of padding if there's an odd number of 16-bit nodes
-        if (node_count & 1) == 1 {
-            writer.write_u16_le(0);
-        }
-
-        // Ensure the correct number of bytes was emitted
-        assert_eq!(writer.offset, self.emit_size());
-    }
-
-    fn node_count(&self) -> usize {
-        self.unwind_codes
-            .iter()
-            .fold(0, |nodes, c| nodes + c.node_count())
-    }
-}
-
-const UNWIND_RBP_REG: u8 = 5;
-
-pub(crate) fn create_unwind_info_from_insts<MR: RegisterMapper<regalloc::Reg>>(
-    insts: &[(CodeOffset, UnwindInst)],
-) -> CodegenResult<UnwindInfo> {
-    let mut unwind_codes = vec![];
-    let mut frame_register_offset = 0;
-    let mut max_unwind_offset = 0;
-    for &(instruction_offset, ref inst) in insts {
-        let instruction_offset = ensure_unwind_offset(instruction_offset)?;
-        match inst {
-            &UnwindInst::PushFrameRegs { .. } => {
-                unwind_codes.push(UnwindCode::PushRegister {
-                    instruction_offset,
-                    reg: UNWIND_RBP_REG,
-                });
-            }
-            &UnwindInst::DefineNewFrame {
-                offset_downward_to_clobbers,
-                ..
-            } => {
-                frame_register_offset = ensure_unwind_offset(offset_downward_to_clobbers)?;
-                unwind_codes.push(UnwindCode::SetFPReg { instruction_offset });
-            }
-            &UnwindInst::StackAlloc { size } => {
-                unwind_codes.push(UnwindCode::StackAlloc {
-                    instruction_offset,
-                    size,
-                });
-            }
-            &UnwindInst::SaveReg {
-                clobber_offset,
-                reg,
-            } => match MR::map(reg.to_reg()) {
-                MappedRegister::Int(reg) => {
-                    unwind_codes.push(UnwindCode::SaveReg {
-                        instruction_offset,
-                        reg,
-                        stack_offset: clobber_offset,
-                    });
-                }
-                MappedRegister::Xmm(reg) => {
-                    unwind_codes.push(UnwindCode::SaveXmm {
-                        instruction_offset,
-                        reg,
-                        stack_offset: clobber_offset,
-                    });
-                }
-            },
-            &UnwindInst::Aarch64SetPointerAuth { .. } => {
-                unreachable!("no aarch64 on x64");
-            }
-        }
-        max_unwind_offset = instruction_offset;
-    }
-
-    Ok(UnwindInfo {
-        flags: 0,
-        prologue_size: max_unwind_offset,
-        frame_register: Some(UNWIND_RBP_REG),
-        frame_register_offset,
-        unwind_codes,
-    })
-}
-
-fn ensure_unwind_offset(offset: u32) -> CodegenResult<u8> {
-    if offset > 255 {
-        warn!("function prologues cannot exceed 255 bytes in size for Windows x64");
-        return Err(CodegenError::CodeTooLarge);
-    }
-    Ok(offset as u8)
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/abi.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/abi.rs
deleted file mode 100644
index 9687ac5f2..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/abi.rs
+++ /dev/null
@@ -1,1041 +0,0 @@
-//! Implementation of the standard x64 ABI.
-
-use crate::ir::types::*;
-use crate::ir::{self, types, ExternalName, LibCall, MemFlags, Opcode, TrapCode, Type};
-use crate::isa;
-use crate::isa::{unwind::UnwindInst, x64::inst::*, CallConv};
-use crate::machinst::abi_impl::*;
-use crate::machinst::*;
-use crate::settings;
-use crate::{CodegenError, CodegenResult};
-use alloc::boxed::Box;
-use alloc::vec::Vec;
-use args::*;
-use regalloc::{RealReg, Reg, RegClass, Set, Writable};
-use smallvec::{smallvec, SmallVec};
-use std::convert::TryFrom;
-
-/// This is the limit for the size of argument and return-value areas on the
-/// stack. We place a reasonable limit here to avoid integer overflow issues
-/// with 32-bit arithmetic: for now, 128 MB.
-static STACK_ARG_RET_SIZE_LIMIT: u64 = 128 * 1024 * 1024;
-
-/// Offset in stack-arg area to callee-TLS slot in Baldrdash-2020 calling convention.
-static BALDRDASH_CALLEE_TLS_OFFSET: i64 = 0;
-/// Offset in stack-arg area to caller-TLS slot in Baldrdash-2020 calling convention.
-static BALDRDASH_CALLER_TLS_OFFSET: i64 = 8;
-
-/// Try to fill a Baldrdash register, returning it if it was found.
-fn try_fill_baldrdash_reg(call_conv: CallConv, param: &ir::AbiParam) -> Option<ABIArg> {
-    if call_conv.extends_baldrdash() {
-        match &param.purpose {
-            &ir::ArgumentPurpose::VMContext => {
-                // This is SpiderMonkey's `WasmTlsReg`.
-                Some(ABIArg::reg(
-                    regs::r14().to_real_reg(),
-                    types::I64,
-                    param.extension,
-                    param.purpose,
-                ))
-            }
-            &ir::ArgumentPurpose::SignatureId => {
-                // This is SpiderMonkey's `WasmTableCallSigReg`.
-                Some(ABIArg::reg(
-                    regs::r10().to_real_reg(),
-                    types::I64,
-                    param.extension,
-                    param.purpose,
-                ))
-            }
-            &ir::ArgumentPurpose::CalleeTLS => {
-                // This is SpiderMonkey's callee TLS slot in the extended frame of Wasm's ABI-2020.
-                assert!(call_conv == isa::CallConv::Baldrdash2020);
-                Some(ABIArg::stack(
-                    BALDRDASH_CALLEE_TLS_OFFSET,
-                    ir::types::I64,
-                    ir::ArgumentExtension::None,
-                    param.purpose,
-                ))
-            }
-            &ir::ArgumentPurpose::CallerTLS => {
-                // This is SpiderMonkey's caller TLS slot in the extended frame of Wasm's ABI-2020.
-                assert!(call_conv == isa::CallConv::Baldrdash2020);
-                Some(ABIArg::stack(
-                    BALDRDASH_CALLER_TLS_OFFSET,
-                    ir::types::I64,
-                    ir::ArgumentExtension::None,
-                    param.purpose,
-                ))
-            }
-            _ => None,
-        }
-    } else {
-        None
-    }
-}
-
-/// Support for the x64 ABI from the callee side (within a function body).
-pub(crate) type X64ABICallee = ABICalleeImpl<X64ABIMachineSpec>;
-
-/// Support for the x64 ABI from the caller side (at a callsite).
-pub(crate) type X64ABICaller = ABICallerImpl<X64ABIMachineSpec>;
-
-/// Implementation of ABI primitives for x64.
-pub(crate) struct X64ABIMachineSpec;
-
-impl ABIMachineSpec for X64ABIMachineSpec {
-    type I = Inst;
-
-    fn word_bits() -> u32 {
-        64
-    }
-
-    /// Return required stack alignment in bytes.
-    fn stack_align(_call_conv: isa::CallConv) -> u32 {
-        16
-    }
-
-    fn compute_arg_locs(
-        call_conv: isa::CallConv,
-        flags: &settings::Flags,
-        params: &[ir::AbiParam],
-        args_or_rets: ArgsOrRets,
-        add_ret_area_ptr: bool,
-    ) -> CodegenResult<(Vec<ABIArg>, i64, Option<usize>)> {
-        let is_baldrdash = call_conv.extends_baldrdash();
-        let is_fastcall = call_conv.extends_windows_fastcall();
-        let has_baldrdash_tls = call_conv == isa::CallConv::Baldrdash2020;
-
-        let mut next_gpr = 0;
-        let mut next_vreg = 0;
-        let mut next_stack: u64 = 0;
-        let mut next_param_idx = 0; // Fastcall cares about overall param index
-        let mut ret = vec![];
-
-        if args_or_rets == ArgsOrRets::Args && is_fastcall {
-            // Fastcall always reserves 32 bytes of shadow space corresponding to
-            // the four initial in-arg parameters.
-            //
-            // (See:
-            // https://docs.microsoft.com/en-us/cpp/build/x64-calling-convention?view=msvc-160)
-            next_stack = 32;
-        }
-
-        if args_or_rets == ArgsOrRets::Args && has_baldrdash_tls {
-            // Baldrdash ABI-2020 always has two stack-arg slots reserved, for the callee and
-            // caller TLS-register values, respectively.
-            next_stack = 16;
-        }
-
-        for i in 0..params.len() {
-            // Process returns backward, according to the SpiderMonkey ABI (which we
-            // adopt internally if `is_baldrdash` is set).
-            let param = match (args_or_rets, is_baldrdash) {
-                (ArgsOrRets::Args, _) => &params[i],
-                (ArgsOrRets::Rets, false) => &params[i],
-                (ArgsOrRets::Rets, true) => &params[params.len() - 1 - i],
-            };
-
-            // Validate "purpose".
-            match &param.purpose {
-                &ir::ArgumentPurpose::VMContext
-                | &ir::ArgumentPurpose::Normal
-                | &ir::ArgumentPurpose::StackLimit
-                | &ir::ArgumentPurpose::SignatureId
-                | &ir::ArgumentPurpose::CalleeTLS
-                | &ir::ArgumentPurpose::CallerTLS
-                | &ir::ArgumentPurpose::StructReturn
-                | &ir::ArgumentPurpose::StructArgument(_) => {}
-                _ => panic!(
-                    "Unsupported argument purpose {:?} in signature: {:?}",
-                    param.purpose, params
-                ),
-            }
-
-            if let Some(param) = try_fill_baldrdash_reg(call_conv, param) {
-                ret.push(param);
-                continue;
-            }
-
-            if let ir::ArgumentPurpose::StructArgument(size) = param.purpose {
-                let offset = next_stack as i64;
-                let size = size as u64;
-                assert!(size % 8 == 0, "StructArgument size is not properly aligned");
-                next_stack += size;
-                ret.push(ABIArg::StructArg {
-                    offset,
-                    size,
-                    purpose: param.purpose,
-                });
-                continue;
-            }
-
-            // Find regclass(es) of the register(s) used to store a value of this type.
-            let (rcs, reg_tys) = Inst::rc_for_type(param.value_type)?;
-
-            // Now assign ABIArgSlots for each register-sized part.
-            //
-            // Note that the handling of `i128` values is unique here:
-            //
-            // - If `enable_llvm_abi_extensions` is set in the flags, each
-            //   `i128` is split into two `i64`s and assigned exactly as if it
-            //   were two consecutive 64-bit args. This is consistent with LLVM's
-            //   behavior, and is needed for some uses of Cranelift (e.g., the
-            //   rustc backend).
-            //
-            // - Otherwise, both SysV and Fastcall specify behavior (use of
-            //   vector register, a register pair, or passing by reference
-            //   depending on the case), but for simplicity, we will just panic if
-            //   an i128 type appears in a signature and the LLVM extensions flag
-            //   is not set.
-            //
-            // For examples of how rustc compiles i128 args and return values on
-            // both SysV and Fastcall platforms, see:
-            // https://godbolt.org/z/PhG3ob
-
-            if param.value_type.bits() > 64
-                && !param.value_type.is_vector()
-                && !flags.enable_llvm_abi_extensions()
-            {
-                panic!(
-                    "i128 args/return values not supported unless LLVM ABI extensions are enabled"
-                );
-            }
-
-            let mut slots = vec![];
-            for (rc, reg_ty) in rcs.iter().zip(reg_tys.iter()) {
-                let intreg = *rc == RegClass::I64;
-                let nextreg = if intreg {
-                    match args_or_rets {
-                        ArgsOrRets::Args => {
-                            get_intreg_for_arg(&call_conv, next_gpr, next_param_idx)
-                        }
-                        ArgsOrRets::Rets => {
-                            get_intreg_for_retval(&call_conv, next_gpr, next_param_idx)
-                        }
-                    }
-                } else {
-                    match args_or_rets {
-                        ArgsOrRets::Args => {
-                            get_fltreg_for_arg(&call_conv, next_vreg, next_param_idx)
-                        }
-                        ArgsOrRets::Rets => {
-                            get_fltreg_for_retval(&call_conv, next_vreg, next_param_idx)
-                        }
-                    }
-                };
-                next_param_idx += 1;
-                if let Some(reg) = nextreg {
-                    if intreg {
-                        next_gpr += 1;
-                    } else {
-                        next_vreg += 1;
-                    }
-                    slots.push(ABIArgSlot::Reg {
-                        reg: reg.to_real_reg(),
-                        ty: *reg_ty,
-                        extension: param.extension,
-                    });
-                } else {
-                    // Compute size. For the wasmtime ABI it differs from native
-                    // ABIs in how multiple values are returned, so we take a
-                    // leaf out of arm64's book by not rounding everything up to
-                    // 8 bytes. For all ABI arguments, and other ABI returns,
-                    // though, each slot takes a minimum of 8 bytes.
-                    //
-                    // Note that in all cases 16-byte stack alignment happens
-                    // separately after all args.
-                    let size = (reg_ty.bits() / 8) as u64;
-                    let size = if args_or_rets == ArgsOrRets::Rets && call_conv.extends_wasmtime() {
-                        size
-                    } else {
-                        std::cmp::max(size, 8)
-                    };
-                    // Align.
-                    debug_assert!(size.is_power_of_two());
-                    next_stack = align_to(next_stack, size);
-                    slots.push(ABIArgSlot::Stack {
-                        offset: next_stack as i64,
-                        ty: *reg_ty,
-                        extension: param.extension,
-                    });
-                    next_stack += size;
-                }
-            }
-
-            ret.push(ABIArg::Slots {
-                slots,
-                purpose: param.purpose,
-            });
-        }
-
-        if args_or_rets == ArgsOrRets::Rets && is_baldrdash {
-            ret.reverse();
-        }
-
-        let extra_arg = if add_ret_area_ptr {
-            debug_assert!(args_or_rets == ArgsOrRets::Args);
-            if let Some(reg) = get_intreg_for_arg(&call_conv, next_gpr, next_param_idx) {
-                ret.push(ABIArg::reg(
-                    reg.to_real_reg(),
-                    types::I64,
-                    ir::ArgumentExtension::None,
-                    ir::ArgumentPurpose::Normal,
-                ));
-            } else {
-                ret.push(ABIArg::stack(
-                    next_stack as i64,
-                    types::I64,
-                    ir::ArgumentExtension::None,
-                    ir::ArgumentPurpose::Normal,
-                ));
-                next_stack += 8;
-            }
-            Some(ret.len() - 1)
-        } else {
-            None
-        };
-
-        next_stack = align_to(next_stack, 16);
-
-        // To avoid overflow issues, limit the arg/return size to something reasonable.
-        if next_stack > STACK_ARG_RET_SIZE_LIMIT {
-            return Err(CodegenError::ImplLimitExceeded);
-        }
-
-        Ok((ret, next_stack as i64, extra_arg))
-    }
-
-    fn fp_to_arg_offset(call_conv: isa::CallConv, flags: &settings::Flags) -> i64 {
-        if call_conv.extends_baldrdash() {
-            let num_words = flags.baldrdash_prologue_words() as i64;
-            debug_assert!(num_words > 0, "baldrdash must set baldrdash_prologue_words");
-            num_words * 8
-        } else {
-            16 // frame pointer + return address.
-        }
-    }
-
-    fn gen_load_stack(mem: StackAMode, into_reg: Writable<Reg>, ty: Type) -> Self::I {
-        // For integer-typed values, we always load a full 64 bits (and we always spill a full 64
-        // bits as well -- see `Inst::store()`).
-        let ty = match ty {
-            types::B1
-            | types::B8
-            | types::I8
-            | types::B16
-            | types::I16
-            | types::B32
-            | types::I32 => types::I64,
-            _ => ty,
-        };
-        Inst::load(ty, mem, into_reg, ExtKind::None)
-    }
-
-    fn gen_store_stack(mem: StackAMode, from_reg: Reg, ty: Type) -> Self::I {
-        Inst::store(ty, from_reg, mem)
-    }
-
-    fn gen_move(to_reg: Writable<Reg>, from_reg: Reg, ty: Type) -> Self::I {
-        Inst::gen_move(to_reg, from_reg, ty)
-    }
-
-    /// Generate an integer-extend operation.
-    fn gen_extend(
-        to_reg: Writable<Reg>,
-        from_reg: Reg,
-        is_signed: bool,
-        from_bits: u8,
-        to_bits: u8,
-    ) -> Self::I {
-        let ext_mode = ExtMode::new(from_bits as u16, to_bits as u16)
-            .unwrap_or_else(|| panic!("invalid extension: {} -> {}", from_bits, to_bits));
-        if is_signed {
-            Inst::movsx_rm_r(ext_mode, RegMem::reg(from_reg), to_reg)
-        } else {
-            Inst::movzx_rm_r(ext_mode, RegMem::reg(from_reg), to_reg)
-        }
-    }
-
-    fn gen_ret() -> Self::I {
-        Inst::ret()
-    }
-
-    fn gen_epilogue_placeholder() -> Self::I {
-        Inst::epilogue_placeholder()
-    }
-
-    fn gen_add_imm(into_reg: Writable<Reg>, from_reg: Reg, imm: u32) -> SmallInstVec<Self::I> {
-        let mut ret = SmallVec::new();
-        if from_reg != into_reg.to_reg() {
-            ret.push(Inst::gen_move(into_reg, from_reg, I64));
-        }
-        ret.push(Inst::alu_rmi_r(
-            OperandSize::Size64,
-            AluRmiROpcode::Add,
-            RegMemImm::imm(imm),
-            into_reg,
-        ));
-        ret
-    }
-
-    fn gen_stack_lower_bound_trap(limit_reg: Reg) -> SmallInstVec<Self::I> {
-        smallvec![
-            Inst::cmp_rmi_r(OperandSize::Size64, RegMemImm::reg(regs::rsp()), limit_reg),
-            Inst::TrapIf {
-                // NBE == "> unsigned"; args above are reversed; this tests limit_reg > rsp.
-                cc: CC::NBE,
-                trap_code: TrapCode::StackOverflow,
-            },
-        ]
-    }
-
-    fn gen_get_stack_addr(mem: StackAMode, into_reg: Writable<Reg>, _ty: Type) -> Self::I {
-        let mem: SyntheticAmode = mem.into();
-        Inst::lea(mem, into_reg)
-    }
-
-    fn get_stacklimit_reg() -> Reg {
-        debug_assert!(
-            !is_callee_save_systemv(regs::r10().to_real_reg())
-                && !is_callee_save_baldrdash(regs::r10().to_real_reg())
-        );
-
-        // As per comment on trait definition, we must return a caller-save
-        // register here.
-        regs::r10()
-    }
-
-    fn gen_load_base_offset(into_reg: Writable<Reg>, base: Reg, offset: i32, ty: Type) -> Self::I {
-        // Only ever used for I64s; if that changes, see if the ExtKind below needs to be changed.
-        assert_eq!(ty, I64);
-        let simm32 = offset as u32;
-        let mem = Amode::imm_reg(simm32, base);
-        Inst::load(ty, mem, into_reg, ExtKind::None)
-    }
-
-    fn gen_store_base_offset(base: Reg, offset: i32, from_reg: Reg, ty: Type) -> Self::I {
-        let simm32 = offset as u32;
-        let mem = Amode::imm_reg(simm32, base);
-        Inst::store(ty, from_reg, mem)
-    }
-
-    fn gen_sp_reg_adjust(amount: i32) -> SmallInstVec<Self::I> {
-        let (alu_op, amount) = if amount >= 0 {
-            (AluRmiROpcode::Add, amount)
-        } else {
-            (AluRmiROpcode::Sub, -amount)
-        };
-
-        let amount = amount as u32;
-
-        smallvec![Inst::alu_rmi_r(
-            OperandSize::Size64,
-            alu_op,
-            RegMemImm::imm(amount),
-            Writable::from_reg(regs::rsp()),
-        )]
-    }
-
-    fn gen_nominal_sp_adj(offset: i32) -> Self::I {
-        Inst::VirtualSPOffsetAdj {
-            offset: offset as i64,
-        }
-    }
-
-    fn gen_prologue_frame_setup(flags: &settings::Flags) -> SmallInstVec<Self::I> {
-        let r_rsp = regs::rsp();
-        let r_rbp = regs::rbp();
-        let w_rbp = Writable::from_reg(r_rbp);
-        let mut insts = SmallVec::new();
-        // `push %rbp`
-        // RSP before the call will be 0 % 16.  So here, it is 8 % 16.
-        insts.push(Inst::push64(RegMemImm::reg(r_rbp)));
-
-        if flags.unwind_info() {
-            insts.push(Inst::Unwind {
-                inst: UnwindInst::PushFrameRegs {
-                    offset_upward_to_caller_sp: 16, // RBP, return address
-                },
-            });
-        }
-
-        // `mov %rsp, %rbp`
-        // RSP is now 0 % 16
-        insts.push(Inst::mov_r_r(OperandSize::Size64, r_rsp, w_rbp));
-        insts
-    }
-
-    fn gen_epilogue_frame_restore(_: &settings::Flags) -> SmallInstVec<Self::I> {
-        let mut insts = SmallVec::new();
-        // `mov %rbp, %rsp`
-        insts.push(Inst::mov_r_r(
-            OperandSize::Size64,
-            regs::rbp(),
-            Writable::from_reg(regs::rsp()),
-        ));
-        // `pop %rbp`
-        insts.push(Inst::pop64(Writable::from_reg(regs::rbp())));
-        insts
-    }
-
-    fn gen_probestack(frame_size: u32) -> SmallInstVec<Self::I> {
-        let mut insts = SmallVec::new();
-        insts.push(Inst::imm(
-            OperandSize::Size32,
-            frame_size as u64,
-            Writable::from_reg(regs::rax()),
-        ));
-        insts.push(Inst::CallKnown {
-            dest: ExternalName::LibCall(LibCall::Probestack),
-            uses: vec![regs::rax()],
-            defs: vec![],
-            opcode: Opcode::Call,
-        });
-        insts
-    }
-
-    fn gen_clobber_save(
-        _call_conv: isa::CallConv,
-        setup_frame: bool,
-        flags: &settings::Flags,
-        clobbered_callee_saves: &Vec<Writable<RealReg>>,
-        fixed_frame_storage_size: u32,
-        _outgoing_args_size: u32,
-    ) -> (u64, SmallVec<[Self::I; 16]>) {
-        let mut insts = SmallVec::new();
-        let clobbered_size = compute_clobber_size(&clobbered_callee_saves);
-
-        if flags.unwind_info() && setup_frame {
-            // Emit unwind info: start the frame. The frame (from unwind
-            // consumers' point of view) starts at clobbbers, just below
-            // the FP and return address. Spill slots and stack slots are
-            // part of our actual frame but do not concern the unwinder.
-            insts.push(Inst::Unwind {
-                inst: UnwindInst::DefineNewFrame {
-                    offset_downward_to_clobbers: clobbered_size,
-                    offset_upward_to_caller_sp: 16, // RBP, return address
-                },
-            });
-        }
-
-        // Adjust the stack pointer downward for clobbers and the function fixed
-        // frame (spillslots and storage slots).
-        let stack_size = fixed_frame_storage_size + clobbered_size;
-        if stack_size > 0 {
-            insts.push(Inst::alu_rmi_r(
-                OperandSize::Size64,
-                AluRmiROpcode::Sub,
-                RegMemImm::imm(stack_size),
-                Writable::from_reg(regs::rsp()),
-            ));
-        }
-        // Store each clobbered register in order at offsets from RSP,
-        // placing them above the fixed frame slots.
-        let mut cur_offset = fixed_frame_storage_size;
-        for reg in clobbered_callee_saves {
-            let r_reg = reg.to_reg();
-            let off = cur_offset;
-            match r_reg.get_class() {
-                RegClass::I64 => {
-                    insts.push(Inst::store(
-                        types::I64,
-                        r_reg.to_reg(),
-                        Amode::imm_reg(cur_offset, regs::rsp()),
-                    ));
-                    cur_offset += 8;
-                }
-                RegClass::V128 => {
-                    cur_offset = align_to(cur_offset, 16);
-                    insts.push(Inst::store(
-                        types::I8X16,
-                        r_reg.to_reg(),
-                        Amode::imm_reg(cur_offset, regs::rsp()),
-                    ));
-                    cur_offset += 16;
-                }
-                _ => unreachable!(),
-            };
-            if flags.unwind_info() {
-                insts.push(Inst::Unwind {
-                    inst: UnwindInst::SaveReg {
-                        clobber_offset: off - fixed_frame_storage_size,
-                        reg: r_reg,
-                    },
-                });
-            }
-        }
-
-        (clobbered_size as u64, insts)
-    }
-
-    fn gen_clobber_restore(
-        call_conv: isa::CallConv,
-        flags: &settings::Flags,
-        clobbers: &Set<Writable<RealReg>>,
-        fixed_frame_storage_size: u32,
-        _outgoing_args_size: u32,
-    ) -> SmallVec<[Self::I; 16]> {
-        let mut insts = SmallVec::new();
-
-        let clobbered_callee_saves = Self::get_clobbered_callee_saves(call_conv, clobbers);
-        let stack_size = fixed_frame_storage_size + compute_clobber_size(&clobbered_callee_saves);
-
-        // Restore regs by loading from offsets of RSP. RSP will be
-        // returned to nominal-RSP at this point, so we can use the
-        // same offsets that we used when saving clobbers above.
-        let mut cur_offset = fixed_frame_storage_size;
-        for reg in &clobbered_callee_saves {
-            let rreg = reg.to_reg();
-            match rreg.get_class() {
-                RegClass::I64 => {
-                    insts.push(Inst::mov64_m_r(
-                        Amode::imm_reg(cur_offset, regs::rsp()),
-                        Writable::from_reg(rreg.to_reg()),
-                    ));
-                    cur_offset += 8;
-                }
-                RegClass::V128 => {
-                    cur_offset = align_to(cur_offset, 16);
-                    insts.push(Inst::load(
-                        types::I8X16,
-                        Amode::imm_reg(cur_offset, regs::rsp()),
-                        Writable::from_reg(rreg.to_reg()),
-                        ExtKind::None,
-                    ));
-                    cur_offset += 16;
-                }
-                _ => unreachable!(),
-            }
-        }
-        // Adjust RSP back upward.
-        if stack_size > 0 {
-            insts.push(Inst::alu_rmi_r(
-                OperandSize::Size64,
-                AluRmiROpcode::Add,
-                RegMemImm::imm(stack_size),
-                Writable::from_reg(regs::rsp()),
-            ));
-        }
-
-        // If this is Baldrdash-2020, restore the callee (i.e., our) TLS
-        // register. We may have allocated it for something else and clobbered
-        // it, but the ABI expects us to leave the TLS register unchanged.
-        if call_conv == isa::CallConv::Baldrdash2020 {
-            let off = BALDRDASH_CALLEE_TLS_OFFSET + Self::fp_to_arg_offset(call_conv, flags);
-            insts.push(Inst::mov64_m_r(
-                Amode::imm_reg(off as u32, regs::rbp()),
-                Writable::from_reg(regs::r14()),
-            ));
-        }
-
-        insts
-    }
-
-    /// Generate a call instruction/sequence.
-    fn gen_call(
-        dest: &CallDest,
-        uses: Vec<Reg>,
-        defs: Vec<Writable<Reg>>,
-        opcode: ir::Opcode,
-        tmp: Writable<Reg>,
-        _callee_conv: isa::CallConv,
-        _caller_conv: isa::CallConv,
-    ) -> SmallVec<[(InstIsSafepoint, Self::I); 2]> {
-        let mut insts = SmallVec::new();
-        match dest {
-            &CallDest::ExtName(ref name, RelocDistance::Near) => {
-                insts.push((
-                    InstIsSafepoint::Yes,
-                    Inst::call_known(name.clone(), uses, defs, opcode),
-                ));
-            }
-            &CallDest::ExtName(ref name, RelocDistance::Far) => {
-                insts.push((
-                    InstIsSafepoint::No,
-                    Inst::LoadExtName {
-                        dst: tmp,
-                        name: Box::new(name.clone()),
-                        offset: 0,
-                    },
-                ));
-                insts.push((
-                    InstIsSafepoint::Yes,
-                    Inst::call_unknown(RegMem::reg(tmp.to_reg()), uses, defs, opcode),
-                ));
-            }
-            &CallDest::Reg(reg) => {
-                insts.push((
-                    InstIsSafepoint::Yes,
-                    Inst::call_unknown(RegMem::reg(reg), uses, defs, opcode),
-                ));
-            }
-        }
-        insts
-    }
-
-    fn gen_memcpy(
-        call_conv: isa::CallConv,
-        dst: Reg,
-        src: Reg,
-        size: usize,
-    ) -> SmallVec<[Self::I; 8]> {
-        // Baldrdash should not use struct args.
-        assert!(!call_conv.extends_baldrdash());
-        let mut insts = SmallVec::new();
-        let arg0 = get_intreg_for_arg(&call_conv, 0, 0).unwrap();
-        let arg1 = get_intreg_for_arg(&call_conv, 1, 1).unwrap();
-        let arg2 = get_intreg_for_arg(&call_conv, 2, 2).unwrap();
-        // We need a register to load the address of `memcpy()` below and we
-        // don't have a lowering context to allocate a temp here; so just use a
-        // register we know we are free to mutate as part of this sequence
-        // (because it is clobbered by the call as per the ABI anyway).
-        let memcpy_addr = get_intreg_for_arg(&call_conv, 3, 3).unwrap();
-        insts.push(Inst::gen_move(Writable::from_reg(arg0), dst, I64));
-        insts.push(Inst::gen_move(Writable::from_reg(arg1), src, I64));
-        insts.extend(
-            Inst::gen_constant(
-                ValueRegs::one(Writable::from_reg(arg2)),
-                size as u128,
-                I64,
-                |_| panic!("tmp should not be needed"),
-            )
-            .into_iter(),
-        );
-        // We use an indirect call and a full LoadExtName because we do not have
-        // information about the libcall `RelocDistance` here, so we
-        // conservatively use the more flexible calling sequence.
-        insts.push(Inst::LoadExtName {
-            dst: Writable::from_reg(memcpy_addr),
-            name: Box::new(ExternalName::LibCall(LibCall::Memcpy)),
-            offset: 0,
-        });
-        insts.push(Inst::call_unknown(
-            RegMem::reg(memcpy_addr),
-            /* uses = */ vec![arg0, arg1, arg2],
-            /* defs = */ Self::get_regs_clobbered_by_call(call_conv),
-            Opcode::Call,
-        ));
-        insts
-    }
-
-    fn get_number_of_spillslots_for_value(rc: RegClass) -> u32 {
-        // We allocate in terms of 8-byte slots.
-        match rc {
-            RegClass::I64 => 1,
-            RegClass::V128 => 2,
-            _ => panic!("Unexpected register class!"),
-        }
-    }
-
-    fn get_virtual_sp_offset_from_state(s: &<Self::I as MachInstEmit>::State) -> i64 {
-        s.virtual_sp_offset
-    }
-
-    fn get_nominal_sp_to_fp(s: &<Self::I as MachInstEmit>::State) -> i64 {
-        s.nominal_sp_to_fp
-    }
-
-    fn get_regs_clobbered_by_call(call_conv_of_callee: isa::CallConv) -> Vec<Writable<Reg>> {
-        let mut caller_saved = vec![
-            // intersection of Systemv and FastCall calling conventions:
-            // - GPR: all except RDI, RSI, RBX, RBP, R12 to R15.
-            //        SysV adds RDI, RSI (FastCall makes these callee-saved).
-            Writable::from_reg(regs::rax()),
-            Writable::from_reg(regs::rcx()),
-            Writable::from_reg(regs::rdx()),
-            Writable::from_reg(regs::r8()),
-            Writable::from_reg(regs::r9()),
-            Writable::from_reg(regs::r10()),
-            Writable::from_reg(regs::r11()),
-            // - XMM: XMM0-5. SysV adds the rest (XMM6-XMM15).
-            Writable::from_reg(regs::xmm0()),
-            Writable::from_reg(regs::xmm1()),
-            Writable::from_reg(regs::xmm2()),
-            Writable::from_reg(regs::xmm3()),
-            Writable::from_reg(regs::xmm4()),
-            Writable::from_reg(regs::xmm5()),
-        ];
-
-        if !call_conv_of_callee.extends_windows_fastcall() {
-            caller_saved.push(Writable::from_reg(regs::rsi()));
-            caller_saved.push(Writable::from_reg(regs::rdi()));
-            caller_saved.push(Writable::from_reg(regs::xmm6()));
-            caller_saved.push(Writable::from_reg(regs::xmm7()));
-            caller_saved.push(Writable::from_reg(regs::xmm8()));
-            caller_saved.push(Writable::from_reg(regs::xmm9()));
-            caller_saved.push(Writable::from_reg(regs::xmm10()));
-            caller_saved.push(Writable::from_reg(regs::xmm11()));
-            caller_saved.push(Writable::from_reg(regs::xmm12()));
-            caller_saved.push(Writable::from_reg(regs::xmm13()));
-            caller_saved.push(Writable::from_reg(regs::xmm14()));
-            caller_saved.push(Writable::from_reg(regs::xmm15()));
-        }
-
-        if call_conv_of_callee.extends_baldrdash() {
-            caller_saved.push(Writable::from_reg(regs::r12()));
-            caller_saved.push(Writable::from_reg(regs::r13()));
-            // Not r14; implicitly preserved in the entry.
-            caller_saved.push(Writable::from_reg(regs::r15()));
-            caller_saved.push(Writable::from_reg(regs::rbx()));
-        }
-
-        caller_saved
-    }
-
-    fn get_ext_mode(
-        call_conv: isa::CallConv,
-        specified: ir::ArgumentExtension,
-    ) -> ir::ArgumentExtension {
-        if call_conv.extends_baldrdash() {
-            // Baldrdash (SpiderMonkey) always extends args and return values to the full register.
-            specified
-        } else {
-            // No other supported ABI on x64 does so.
-            ir::ArgumentExtension::None
-        }
-    }
-
-    fn get_clobbered_callee_saves(
-        call_conv: CallConv,
-        regs: &Set<Writable<RealReg>>,
-    ) -> Vec<Writable<RealReg>> {
-        let mut regs: Vec<Writable<RealReg>> = match call_conv {
-            CallConv::BaldrdashSystemV | CallConv::Baldrdash2020 => regs
-                .iter()
-                .cloned()
-                .filter(|r| is_callee_save_baldrdash(r.to_reg()))
-                .collect(),
-            CallConv::BaldrdashWindows => {
-                todo!("baldrdash windows");
-            }
-            CallConv::Fast | CallConv::Cold | CallConv::SystemV | CallConv::WasmtimeSystemV => regs
-                .iter()
-                .cloned()
-                .filter(|r| is_callee_save_systemv(r.to_reg()))
-                .collect(),
-            CallConv::WindowsFastcall | CallConv::WasmtimeFastcall => regs
-                .iter()
-                .cloned()
-                .filter(|r| is_callee_save_fastcall(r.to_reg()))
-                .collect(),
-            CallConv::Probestack => todo!("probestack?"),
-            CallConv::AppleAarch64 | CallConv::WasmtimeAppleAarch64 => unreachable!(),
-        };
-        // Sort registers for deterministic code output. We can do an unstable sort because the
-        // registers will be unique (there are no dups).
-        regs.sort_unstable_by_key(|r| r.to_reg().get_index());
-        regs
-    }
-
-    fn is_frame_setup_needed(
-        _is_leaf: bool,
-        _stack_args_size: u32,
-        _num_clobbered_callee_saves: usize,
-        _fixed_frame_storage_size: u32,
-    ) -> bool {
-        true
-    }
-}
-
-impl From<StackAMode> for SyntheticAmode {
-    fn from(amode: StackAMode) -> Self {
-        // We enforce a 128 MB stack-frame size limit above, so these
-        // `expect()`s should never fail.
-        match amode {
-            StackAMode::FPOffset(off, _ty) => {
-                let off = i32::try_from(off)
-                    .expect("Offset in FPOffset is greater than 2GB; should hit impl limit first");
-                let simm32 = off as u32;
-                SyntheticAmode::Real(Amode::ImmReg {
-                    simm32,
-                    base: regs::rbp(),
-                    flags: MemFlags::trusted(),
-                })
-            }
-            StackAMode::NominalSPOffset(off, _ty) => {
-                let off = i32::try_from(off).expect(
-                    "Offset in NominalSPOffset is greater than 2GB; should hit impl limit first",
-                );
-                let simm32 = off as u32;
-                SyntheticAmode::nominal_sp_offset(simm32)
-            }
-            StackAMode::SPOffset(off, _ty) => {
-                let off = i32::try_from(off)
-                    .expect("Offset in SPOffset is greater than 2GB; should hit impl limit first");
-                let simm32 = off as u32;
-                SyntheticAmode::Real(Amode::ImmReg {
-                    simm32,
-                    base: regs::rsp(),
-                    flags: MemFlags::trusted(),
-                })
-            }
-        }
-    }
-}
-
-fn get_intreg_for_arg(call_conv: &CallConv, idx: usize, arg_idx: usize) -> Option<Reg> {
-    let is_fastcall = call_conv.extends_windows_fastcall();
-
-    // Fastcall counts by absolute argument number; SysV counts by argument of
-    // this (integer) class.
-    let i = if is_fastcall { arg_idx } else { idx };
-    match (i, is_fastcall) {
-        (0, false) => Some(regs::rdi()),
-        (1, false) => Some(regs::rsi()),
-        (2, false) => Some(regs::rdx()),
-        (3, false) => Some(regs::rcx()),
-        (4, false) => Some(regs::r8()),
-        (5, false) => Some(regs::r9()),
-        (0, true) => Some(regs::rcx()),
-        (1, true) => Some(regs::rdx()),
-        (2, true) => Some(regs::r8()),
-        (3, true) => Some(regs::r9()),
-        _ => None,
-    }
-}
-
-fn get_fltreg_for_arg(call_conv: &CallConv, idx: usize, arg_idx: usize) -> Option<Reg> {
-    let is_fastcall = call_conv.extends_windows_fastcall();
-
-    // Fastcall counts by absolute argument number; SysV counts by argument of
-    // this (floating-point) class.
-    let i = if is_fastcall { arg_idx } else { idx };
-    match (i, is_fastcall) {
-        (0, false) => Some(regs::xmm0()),
-        (1, false) => Some(regs::xmm1()),
-        (2, false) => Some(regs::xmm2()),
-        (3, false) => Some(regs::xmm3()),
-        (4, false) => Some(regs::xmm4()),
-        (5, false) => Some(regs::xmm5()),
-        (6, false) => Some(regs::xmm6()),
-        (7, false) => Some(regs::xmm7()),
-        (0, true) => Some(regs::xmm0()),
-        (1, true) => Some(regs::xmm1()),
-        (2, true) => Some(regs::xmm2()),
-        (3, true) => Some(regs::xmm3()),
-        _ => None,
-    }
-}
-
-fn get_intreg_for_retval(
-    call_conv: &CallConv,
-    intreg_idx: usize,
-    retval_idx: usize,
-) -> Option<Reg> {
-    match call_conv {
-        CallConv::Fast | CallConv::Cold | CallConv::SystemV => match intreg_idx {
-            0 => Some(regs::rax()),
-            1 => Some(regs::rdx()),
-            _ => None,
-        },
-        CallConv::BaldrdashSystemV
-        | CallConv::Baldrdash2020
-        | CallConv::WasmtimeSystemV
-        | CallConv::WasmtimeFastcall => {
-            if intreg_idx == 0 && retval_idx == 0 {
-                Some(regs::rax())
-            } else {
-                None
-            }
-        }
-        CallConv::WindowsFastcall => match intreg_idx {
-            0 => Some(regs::rax()),
-            1 => Some(regs::rdx()), // The Rust ABI for i128s needs this.
-            _ => None,
-        },
-        CallConv::BaldrdashWindows | CallConv::Probestack => todo!(),
-        CallConv::AppleAarch64 | CallConv::WasmtimeAppleAarch64 => unreachable!(),
-    }
-}
-
-fn get_fltreg_for_retval(
-    call_conv: &CallConv,
-    fltreg_idx: usize,
-    retval_idx: usize,
-) -> Option<Reg> {
-    match call_conv {
-        CallConv::Fast | CallConv::Cold | CallConv::SystemV => match fltreg_idx {
-            0 => Some(regs::xmm0()),
-            1 => Some(regs::xmm1()),
-            _ => None,
-        },
-        CallConv::BaldrdashSystemV
-        | CallConv::Baldrdash2020
-        | CallConv::WasmtimeFastcall
-        | CallConv::WasmtimeSystemV => {
-            if fltreg_idx == 0 && retval_idx == 0 {
-                Some(regs::xmm0())
-            } else {
-                None
-            }
-        }
-        CallConv::WindowsFastcall => match fltreg_idx {
-            0 => Some(regs::xmm0()),
-            _ => None,
-        },
-        CallConv::BaldrdashWindows | CallConv::Probestack => todo!(),
-        CallConv::AppleAarch64 | CallConv::WasmtimeAppleAarch64 => unreachable!(),
-    }
-}
-
-fn is_callee_save_systemv(r: RealReg) -> bool {
-    use regs::*;
-    match r.get_class() {
-        RegClass::I64 => match r.get_hw_encoding() as u8 {
-            ENC_RBX | ENC_RBP | ENC_R12 | ENC_R13 | ENC_R14 | ENC_R15 => true,
-            _ => false,
-        },
-        RegClass::V128 => false,
-        _ => unimplemented!(),
-    }
-}
-
-fn is_callee_save_baldrdash(r: RealReg) -> bool {
-    use regs::*;
-    match r.get_class() {
-        RegClass::I64 => {
-            if r.get_hw_encoding() as u8 == ENC_R14 {
-                // r14 is the WasmTlsReg and is preserved implicitly.
-                false
-            } else {
-                // Defer to native for the other ones.
-                is_callee_save_systemv(r)
-            }
-        }
-        RegClass::V128 => false,
-        _ => unimplemented!(),
-    }
-}
-
-fn is_callee_save_fastcall(r: RealReg) -> bool {
-    use regs::*;
-    match r.get_class() {
-        RegClass::I64 => match r.get_hw_encoding() as u8 {
-            ENC_RBX | ENC_RBP | ENC_RSI | ENC_RDI | ENC_R12 | ENC_R13 | ENC_R14 | ENC_R15 => true,
-            _ => false,
-        },
-        RegClass::V128 => match r.get_hw_encoding() as u8 {
-            6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 => true,
-            _ => false,
-        },
-        _ => panic!("Unknown register class: {:?}", r.get_class()),
-    }
-}
-
-fn compute_clobber_size(clobbers: &Vec<Writable<RealReg>>) -> u32 {
-    let mut clobbered_size = 0;
-    for reg in clobbers {
-        match reg.to_reg().get_class() {
-            RegClass::I64 => {
-                clobbered_size += 8;
-            }
-            RegClass::V128 => {
-                clobbered_size = align_to(clobbered_size, 16);
-                clobbered_size += 16;
-            }
-            _ => unreachable!(),
-        }
-    }
-    align_to(clobbered_size, 16)
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/encoding/evex.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/encoding/evex.rs
deleted file mode 100644
index 80a3c86bd..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/encoding/evex.rs
+++ /dev/null
@@ -1,403 +0,0 @@
-//! Encodes EVEX instructions. These instructions are those added by the AVX-512 extensions. The
-//! EVEX encoding requires a 4-byte prefix:
-//!
-//! Byte 0:  0x62
-//!         ┌───┬───┬───┬───┬───┬───┬───┬───┐
-//! Byte 1: │ R │ X │ B │ R'│ 0 │ 0 │ m │ m │
-//!         ├───┼───┼───┼───┼───┼───┼───┼───┤
-//! Byte 2: │ W │ v │ v │ v │ v │ 1 │ p │ p │
-//!         ├───┼───┼───┼───┼───┼───┼───┼───┤
-//! Byte 3: │ z │ L'│ L │ b │ V'│ a │ a │ a │
-//!         └───┴───┴───┴───┴───┴───┴───┴───┘
-//!
-//! The prefix is then followeded by the opcode byte, the ModR/M byte, and other optional suffixes
-//! (e.g. SIB byte, displacements, immediates) based on the instruction (see section 2.6, Intel
-//! Software Development Manual, volume 2A).
-use super::rex::{encode_modrm, LegacyPrefixes, OpcodeMap};
-use super::ByteSink;
-use core::ops::RangeInclusive;
-
-/// Constructs an EVEX-encoded instruction using a builder pattern. This approach makes it visually
-/// easier to transform something the manual's syntax, `EVEX.256.66.0F38.W1 1F /r` to code:
-/// `EvexInstruction::new().length(...).prefix(...).map(...).w(true).opcode(0x1F).reg(...).rm(...)`.
-pub struct EvexInstruction {
-    bits: u32,
-    opcode: u8,
-    reg: Register,
-    rm: Register,
-}
-
-/// Because some of the bit flags in the EVEX prefix are reversed and users of `EvexInstruction` may
-/// choose to skip setting fields, here we set some sane defaults. Note that:
-/// - the first byte is always `0x62` but you will notice it at the end of the default `bits` value
-///   implemented--remember the little-endian order
-/// - some bits are always set to certain values: bits 10-11 to 0, bit 18 to 1
-/// - the other bits set correspond to reversed bits: R, X, B, R' (byte 1), vvvv (byte 2), V' (byte
-///   3).
-///
-/// See the `default_emission` test for what these defaults are equivalent to (e.g. using RAX,
-/// unsetting the W bit, etc.)
-impl Default for EvexInstruction {
-    fn default() -> Self {
-        Self {
-            bits: 0x08_7C_F0_62,
-            opcode: 0,
-            reg: Register::default(),
-            rm: Register::default(),
-        }
-    }
-}
-
-#[allow(non_upper_case_globals)] // This makes it easier to match the bit range names to the manual's names.
-impl EvexInstruction {
-    /// Construct a default EVEX instruction.
-    pub fn new() -> Self {
-        Self::default()
-    }
-
-    /// Set the length of the instruction . Note that there are sets of instructions (i.e. rounding,
-    /// memory broadcast) that modify the same underlying bits--at some point (TODO) we can add a
-    /// way to set those context bits and verify that both are not used (e.g. rounding AND length).
-    /// For now, this method is very convenient.
-    #[inline(always)]
-    pub fn length(mut self, length: EvexVectorLength) -> Self {
-        self.write(Self::LL, EvexContext::Other { length }.bits() as u32);
-        self
-    }
-
-    /// Set the legacy prefix byte of the instruction: None | 66 | F0 | F2 | F3. EVEX instructions
-    /// pack these into the prefix, not as separate bytes.
-    #[inline(always)]
-    pub fn prefix(mut self, prefix: LegacyPrefixes) -> Self {
-        self.write(Self::pp, prefix.bits() as u32);
-        self
-    }
-
-    /// Set the opcode map byte of the instruction: None | 0F | 0F38 | 0F3A. EVEX instructions pack
-    /// these into the prefix, not as separate bytes.
-    #[inline(always)]
-    pub fn map(mut self, map: OpcodeMap) -> Self {
-        self.write(Self::mm, map.bits() as u32);
-        self
-    }
-
-    /// Set the W bit, typically used to indicate an instruction using 64 bits of an operand (e.g.
-    /// 64 bit lanes). EVEX packs this bit in the EVEX prefix; previous encodings used the REX
-    /// prefix.
-    #[inline(always)]
-    pub fn w(mut self, w: bool) -> Self {
-        self.write(Self::W, w as u32);
-        self
-    }
-
-    /// Set the instruction opcode byte.
-    #[inline(always)]
-    pub fn opcode(mut self, opcode: u8) -> Self {
-        self.opcode = opcode;
-        self
-    }
-
-    /// Set the register to use for the `reg` bits; many instructions use this as the write operand.
-    /// Setting this affects both the ModRM byte (`reg` section) and the EVEX prefix (the extension
-    /// bits for register encodings > 8).
-    #[inline(always)]
-    pub fn reg(mut self, reg: impl Into<Register>) -> Self {
-        self.reg = reg.into();
-        let r = !(self.reg.0 >> 3) & 1;
-        let r_ = !(self.reg.0 >> 4) & 1;
-        self.write(Self::R, r as u32);
-        self.write(Self::R_, r_ as u32);
-        self
-    }
-
-    /// Set the mask to use. See section 2.6 in the Intel Software Developer's Manual, volume 2A for
-    /// more details.
-    #[allow(dead_code)]
-    #[inline(always)]
-    pub fn mask(mut self, mask: EvexMasking) -> Self {
-        self.write(Self::aaa, mask.aaa_bits() as u32);
-        self.write(Self::z, mask.z_bit() as u32);
-        self
-    }
-
-    /// Set the `vvvvv` register; some instructions allow using this as a second, non-destructive
-    /// source register in 3-operand instructions (e.g. 2 read, 1 write).
-    #[allow(dead_code)]
-    #[inline(always)]
-    pub fn vvvvv(mut self, reg: impl Into<Register>) -> Self {
-        let reg = reg.into();
-        self.write(Self::vvvv, !(reg.0 as u32) & 0b1111);
-        self.write(Self::V_, !(reg.0 as u32 >> 4) & 0b1);
-        self
-    }
-
-    /// Set the register to use for the `rm` bits; many instructions use this as the "read from
-    /// register/memory" operand. Currently this does not support memory addressing (TODO).Setting
-    /// this affects both the ModRM byte (`rm` section) and the EVEX prefix (the extension bits for
-    /// register encodings > 8).
-    #[inline(always)]
-    pub fn rm(mut self, reg: impl Into<Register>) -> Self {
-        self.rm = reg.into();
-        let b = !(self.rm.0 >> 3) & 1;
-        let x = !(self.rm.0 >> 4) & 1;
-        self.write(Self::X, x as u32);
-        self.write(Self::B, b as u32);
-        self
-    }
-
-    /// Emit the EVEX-encoded instruction to the code sink:
-    /// - first, the 4-byte EVEX prefix;
-    /// - then, the opcode byte;
-    /// - finally, the ModR/M byte.
-    ///
-    /// Eventually this method should support encodings of more than just the reg-reg addressing mode (TODO).
-    pub fn encode<CS: ByteSink + ?Sized>(&self, sink: &mut CS) {
-        sink.put4(self.bits);
-        sink.put1(self.opcode);
-        sink.put1(encode_modrm(3, self.reg.0 & 7, self.rm.0 & 7));
-    }
-
-    // In order to simplify the encoding of the various bit ranges in the prefix, we specify those
-    // ranges according to the table below (extracted from the Intel Software Development Manual,
-    // volume 2A). Remember that, because we pack the 4-byte prefix into a little-endian `u32`, this
-    // chart should be read from right-to-left, top-to-bottom. Note also that we start ranges at bit
-    // 8, leaving bits 0-7 for the mandatory `0x62`.
-    //         ┌───┬───┬───┬───┬───┬───┬───┬───┐
-    // Byte 1: │ R │ X │ B │ R'│ 0 │ 0 │ m │ m │
-    //         ├───┼───┼───┼───┼───┼───┼───┼───┤
-    // Byte 2: │ W │ v │ v │ v │ v │ 1 │ p │ p │
-    //         ├───┼───┼───┼───┼───┼───┼───┼───┤
-    // Byte 3: │ z │ L'│ L │ b │ V'│ a │ a │ a │
-    //         └───┴───┴───┴───┴───┴───┴───┴───┘
-
-    // Byte 1:
-    const mm: RangeInclusive<u8> = 8..=9;
-    const R_: RangeInclusive<u8> = 12..=12;
-    const B: RangeInclusive<u8> = 13..=13;
-    const X: RangeInclusive<u8> = 14..=14;
-    const R: RangeInclusive<u8> = 15..=15;
-
-    // Byte 2:
-    const pp: RangeInclusive<u8> = 16..=17;
-    const vvvv: RangeInclusive<u8> = 19..=22;
-    const W: RangeInclusive<u8> = 23..=23;
-
-    // Byte 3:
-    const aaa: RangeInclusive<u8> = 24..=26;
-    const V_: RangeInclusive<u8> = 27..=27;
-    #[allow(dead_code)] // Will be used once broadcast and rounding controls are exposed.
-    const b: RangeInclusive<u8> = 28..=28;
-    const LL: RangeInclusive<u8> = 29..=30;
-    const z: RangeInclusive<u8> = 31..=31;
-
-    // A convenience method for writing the `value` bits to the given range in `self.bits`.
-    #[inline]
-    fn write(&mut self, range: RangeInclusive<u8>, value: u32) {
-        assert!(ExactSizeIterator::len(&range) > 0);
-        let size = range.end() - range.start() + 1; // Calculate the number of bits in the range.
-        let mask: u32 = (1 << size) - 1; // Generate a bit mask.
-        debug_assert!(
-            value <= mask,
-            "The written value should have fewer than {} bits.",
-            size
-        );
-        let mask_complement = !(mask << *range.start()); // Create the bitwise complement for the clear mask.
-        self.bits &= mask_complement; // Clear the bits in `range`; otherwise the OR below may allow previously-set bits to slip through.
-        let value = value << *range.start(); // Place the value in the correct location (assumes `value <= mask`).
-        self.bits |= value; // Modify the bits in `range`.
-    }
-}
-
-/// Describe the register index to use. This wrapper is a type-safe way to pass
-/// around the registers defined in `inst/regs.rs`.
-#[derive(Copy, Clone, Default)]
-pub struct Register(u8);
-impl From<u8> for Register {
-    fn from(reg: u8) -> Self {
-        debug_assert!(reg < 16);
-        Self(reg)
-    }
-}
-impl Into<u8> for Register {
-    fn into(self) -> u8 {
-        self.0
-    }
-}
-
-/// Defines the EVEX context for the `L'`, `L`, and `b` bits (bits 6:4 of EVEX P2 byte). Table 2-36 in
-/// section 2.6.10 (Intel Software Development Manual, volume 2A) describes how these bits can be
-/// used together for certain classes of instructions; i.e., special care should be taken to ensure
-/// that instructions use an applicable correct `EvexContext`. Table 2-39 contains cases where
-/// opcodes can result in an #UD.
-#[allow(dead_code, missing_docs)] // Rounding and broadcast modes are not yet used.
-pub enum EvexContext {
-    RoundingRegToRegFP {
-        rc: EvexRoundingControl,
-    },
-    NoRoundingFP {
-        sae: bool,
-        length: EvexVectorLength,
-    },
-    MemoryOp {
-        broadcast: bool,
-        length: EvexVectorLength,
-    },
-    Other {
-        length: EvexVectorLength,
-    },
-}
-
-impl Default for EvexContext {
-    fn default() -> Self {
-        Self::Other {
-            length: EvexVectorLength::default(),
-        }
-    }
-}
-
-impl EvexContext {
-    /// Encode the `L'`, `L`, and `b` bits (bits 6:4 of EVEX P2 byte) for merging with the P2 byte.
-    pub fn bits(&self) -> u8 {
-        match self {
-            Self::RoundingRegToRegFP { rc } => 0b001 | rc.bits() << 1,
-            Self::NoRoundingFP { sae, length } => (*sae as u8) | length.bits() << 1,
-            Self::MemoryOp { broadcast, length } => (*broadcast as u8) | length.bits() << 1,
-            Self::Other { length } => length.bits() << 1,
-        }
-    }
-}
-
-/// The EVEX format allows choosing a vector length in the `L'` and `L` bits; see `EvexContext`.
-#[allow(dead_code, missing_docs)] // Wider-length vectors are not yet used.
-pub enum EvexVectorLength {
-    V128,
-    V256,
-    V512,
-}
-
-impl EvexVectorLength {
-    /// Encode the `L'` and `L` bits for merging with the P2 byte.
-    fn bits(&self) -> u8 {
-        match self {
-            Self::V128 => 0b00,
-            Self::V256 => 0b01,
-            Self::V512 => 0b10,
-            // 0b11 is reserved (#UD).
-        }
-    }
-}
-
-impl Default for EvexVectorLength {
-    fn default() -> Self {
-        Self::V128
-    }
-}
-
-/// The EVEX format allows defining rounding control in the `L'` and `L` bits; see `EvexContext`.
-#[allow(dead_code, missing_docs)] // Rounding controls are not yet used.
-pub enum EvexRoundingControl {
-    RNE,
-    RD,
-    RU,
-    RZ,
-}
-
-impl EvexRoundingControl {
-    /// Encode the `L'` and `L` bits for merging with the P2 byte.
-    fn bits(&self) -> u8 {
-        match self {
-            Self::RNE => 0b00,
-            Self::RD => 0b01,
-            Self::RU => 0b10,
-            Self::RZ => 0b11,
-        }
-    }
-}
-
-/// Defines the EVEX masking behavior; masking support is described in section 2.6.4 of the Intel
-/// Software Development Manual, volume 2A.
-#[allow(dead_code, missing_docs)] // Masking is not yet used.
-pub enum EvexMasking {
-    None,
-    Merging { k: u8 },
-    Zeroing { k: u8 },
-}
-
-impl Default for EvexMasking {
-    fn default() -> Self {
-        EvexMasking::None
-    }
-}
-
-impl EvexMasking {
-    /// Encode the `z` bit for merging with the P2 byte.
-    pub fn z_bit(&self) -> u8 {
-        match self {
-            Self::None | Self::Merging { .. } => 0,
-            Self::Zeroing { .. } => 1,
-        }
-    }
-
-    /// Encode the `aaa` bits for merging with the P2 byte.
-    pub fn aaa_bits(&self) -> u8 {
-        match self {
-            Self::None => 0b000,
-            Self::Merging { k } | Self::Zeroing { k } => {
-                debug_assert!(*k <= 7);
-                *k
-            }
-        }
-    }
-}
-
-#[cfg(test)]
-mod tests {
-    use super::*;
-    use crate::isa::x64::inst::regs;
-    use std::vec::Vec;
-
-    // As a sanity test, we verify that the output of `xed-asmparse-main 'vpabsq xmm0{k0},
-    // xmm1'` matches this EVEX encoding machinery.
-    #[test]
-    fn vpabsq() {
-        let dst = regs::xmm0();
-        let src = regs::xmm1();
-        let mut sink0 = Vec::new();
-
-        EvexInstruction::new()
-            .prefix(LegacyPrefixes::_66)
-            .map(OpcodeMap::_0F38)
-            .w(true)
-            .opcode(0x1F)
-            .reg(dst.get_hw_encoding())
-            .rm(src.get_hw_encoding())
-            .length(EvexVectorLength::V128)
-            .encode(&mut sink0);
-
-        assert_eq!(sink0, vec![0x62, 0xf2, 0xfd, 0x08, 0x1f, 0xc1]);
-    }
-
-    /// Verify that the defaults are equivalent to an instruction with a `0x00` opcode using the
-    /// "0" register (i.e. `rax`), with sane defaults for the various configurable parameters. This
-    /// test is more interesting than it may appear because some of the parameters have flipped-bit
-    /// representations (e.g. `vvvvv`) so emitting 0s as a default will not work.
-    #[test]
-    fn default_emission() {
-        let mut sink0 = Vec::new();
-        EvexInstruction::new().encode(&mut sink0);
-
-        let mut sink1 = Vec::new();
-        EvexInstruction::new()
-            .length(EvexVectorLength::V128)
-            .prefix(LegacyPrefixes::None)
-            .map(OpcodeMap::None)
-            .w(false)
-            .opcode(0x00)
-            .reg(regs::rax().get_hw_encoding())
-            .rm(regs::rax().get_hw_encoding())
-            .mask(EvexMasking::None)
-            .encode(&mut sink1);
-
-        assert_eq!(sink0, sink1);
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/encoding/mod.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/encoding/mod.rs
deleted file mode 100644
index 9dd269764..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/encoding/mod.rs
+++ /dev/null
@@ -1,60 +0,0 @@
-//! Contains the encoding machinery for the various x64 instruction formats.
-use crate::{isa::x64, machinst::MachBuffer};
-use std::vec::Vec;
-
-pub mod evex;
-pub mod rex;
-pub mod vex;
-
-/// The encoding formats in this module all require a way of placing bytes into
-/// a buffer.
-pub trait ByteSink {
-    /// Add 1 byte to the code section.
-    fn put1(&mut self, _: u8);
-
-    /// Add 2 bytes to the code section.
-    fn put2(&mut self, _: u16);
-
-    /// Add 4 bytes to the code section.
-    fn put4(&mut self, _: u32);
-
-    /// Add 8 bytes to the code section.
-    fn put8(&mut self, _: u64);
-}
-
-impl ByteSink for MachBuffer<x64::inst::Inst> {
-    fn put1(&mut self, value: u8) {
-        self.put1(value)
-    }
-
-    fn put2(&mut self, value: u16) {
-        self.put2(value)
-    }
-
-    fn put4(&mut self, value: u32) {
-        self.put4(value)
-    }
-
-    fn put8(&mut self, value: u64) {
-        self.put8(value)
-    }
-}
-
-/// Provide a convenient implementation for testing.
-impl ByteSink for Vec<u8> {
-    fn put1(&mut self, v: u8) {
-        self.extend_from_slice(&[v])
-    }
-
-    fn put2(&mut self, v: u16) {
-        self.extend_from_slice(&v.to_le_bytes())
-    }
-
-    fn put4(&mut self, v: u32) {
-        self.extend_from_slice(&v.to_le_bytes())
-    }
-
-    fn put8(&mut self, v: u64) {
-        self.extend_from_slice(&v.to_le_bytes())
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/encoding/rex.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/encoding/rex.rs
deleted file mode 100644
index 509309205..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/encoding/rex.rs
+++ /dev/null
@@ -1,506 +0,0 @@
-//! Encodes instructions in the standard x86 encoding mode. This is called IA-32E mode in the Intel
-//! manuals but corresponds to the addition of the REX-prefix format (hence the name of this module)
-//! that allowed encoding instructions in both compatibility mode (32-bit instructions running on a
-//! 64-bit OS) and in 64-bit mode (using the full 64-bit address space).
-//!
-//! For all of the routines that take both a memory-or-reg operand (sometimes called "E" in the
-//! Intel documentation, see the Intel Developer's manual, vol. 2, section A.2) and a reg-only
-//! operand ("G" in Intelese), the order is always G first, then E. The term "enc" in the following
-//! means "hardware register encoding number".
-
-use crate::{
-    ir::TrapCode,
-    isa::x64::inst::{
-        args::{Amode, OperandSize},
-        regs, EmitInfo, EmitState, Inst, LabelUse,
-    },
-    machinst::MachBuffer,
-};
-use regalloc::{Reg, RegClass};
-
-pub(crate) fn low8_will_sign_extend_to_64(x: u32) -> bool {
-    let xs = (x as i32) as i64;
-    xs == ((xs << 56) >> 56)
-}
-
-pub(crate) fn low8_will_sign_extend_to_32(x: u32) -> bool {
-    let xs = x as i32;
-    xs == ((xs << 24) >> 24)
-}
-
-/// Encode the ModR/M byte.
-#[inline(always)]
-pub fn encode_modrm(m0d: u8, enc_reg_g: u8, rm_e: u8) -> u8 {
-    debug_assert!(m0d < 4);
-    debug_assert!(enc_reg_g < 8);
-    debug_assert!(rm_e < 8);
-    ((m0d & 3) << 6) | ((enc_reg_g & 7) << 3) | (rm_e & 7)
-}
-
-#[inline(always)]
-pub(crate) fn encode_sib(shift: u8, enc_index: u8, enc_base: u8) -> u8 {
-    debug_assert!(shift < 4);
-    debug_assert!(enc_index < 8);
-    debug_assert!(enc_base < 8);
-    ((shift & 3) << 6) | ((enc_index & 7) << 3) | (enc_base & 7)
-}
-
-/// Get the encoding number of a GPR.
-#[inline(always)]
-pub(crate) fn int_reg_enc(reg: impl Into<Reg>) -> u8 {
-    let reg = reg.into();
-    debug_assert!(reg.is_real());
-    debug_assert_eq!(reg.get_class(), RegClass::I64);
-    reg.get_hw_encoding()
-}
-
-/// Get the encoding number of any register.
-#[inline(always)]
-pub(crate) fn reg_enc(reg: impl Into<Reg>) -> u8 {
-    let reg = reg.into();
-    debug_assert!(reg.is_real());
-    reg.get_hw_encoding()
-}
-
-/// A small bit field to record a REX prefix specification:
-/// - bit 0 set to 1 indicates REX.W must be 0 (cleared).
-/// - bit 1 set to 1 indicates the REX prefix must always be emitted.
-#[repr(transparent)]
-#[derive(Clone, Copy)]
-pub(crate) struct RexFlags(u8);
-
-impl RexFlags {
-    /// By default, set the W field, and don't always emit.
-    #[inline(always)]
-    pub(crate) fn set_w() -> Self {
-        Self(0)
-    }
-    /// Creates a new RexPrefix for which the REX.W bit will be cleared.
-    #[inline(always)]
-    pub(crate) fn clear_w() -> Self {
-        Self(1)
-    }
-
-    #[inline(always)]
-    pub(crate) fn always_emit(&mut self) -> &mut Self {
-        self.0 = self.0 | 2;
-        self
-    }
-
-    #[inline(always)]
-    pub(crate) fn always_emit_if_8bit_needed(&mut self, reg: Reg) -> &mut Self {
-        let enc_reg = int_reg_enc(reg);
-        if enc_reg >= 4 && enc_reg <= 7 {
-            self.always_emit();
-        }
-        self
-    }
-
-    #[inline(always)]
-    pub(crate) fn must_clear_w(&self) -> bool {
-        (self.0 & 1) != 0
-    }
-    #[inline(always)]
-    pub(crate) fn must_always_emit(&self) -> bool {
-        (self.0 & 2) != 0
-    }
-
-    #[inline(always)]
-    pub(crate) fn emit_two_op(&self, sink: &mut MachBuffer<Inst>, enc_g: u8, enc_e: u8) {
-        let w = if self.must_clear_w() { 0 } else { 1 };
-        let r = (enc_g >> 3) & 1;
-        let x = 0;
-        let b = (enc_e >> 3) & 1;
-        let rex = 0x40 | (w << 3) | (r << 2) | (x << 1) | b;
-        if rex != 0x40 || self.must_always_emit() {
-            sink.put1(rex);
-        }
-    }
-
-    #[inline(always)]
-    pub fn emit_three_op(
-        &self,
-        sink: &mut MachBuffer<Inst>,
-        enc_g: u8,
-        enc_index: u8,
-        enc_base: u8,
-    ) {
-        let w = if self.must_clear_w() { 0 } else { 1 };
-        let r = (enc_g >> 3) & 1;
-        let x = (enc_index >> 3) & 1;
-        let b = (enc_base >> 3) & 1;
-        let rex = 0x40 | (w << 3) | (r << 2) | (x << 1) | b;
-        if rex != 0x40 || self.must_always_emit() {
-            sink.put1(rex);
-        }
-    }
-}
-
-/// Generate the proper Rex flags for the given operand size.
-impl From<OperandSize> for RexFlags {
-    fn from(size: OperandSize) -> Self {
-        match size {
-            OperandSize::Size64 => RexFlags::set_w(),
-            _ => RexFlags::clear_w(),
-        }
-    }
-}
-/// Generate Rex flags for an OperandSize/register tuple.
-impl From<(OperandSize, Reg)> for RexFlags {
-    fn from((size, reg): (OperandSize, Reg)) -> Self {
-        let mut rex = RexFlags::from(size);
-        if size == OperandSize::Size8 {
-            rex.always_emit_if_8bit_needed(reg);
-        }
-        rex
-    }
-}
-
-/// Allows using the same opcode byte in different "opcode maps" to allow for more instruction
-/// encodings. See appendix A in the Intel Software Developer's Manual, volume 2A, for more details.
-#[allow(missing_docs)]
-pub enum OpcodeMap {
-    None,
-    _0F,
-    _0F38,
-    _0F3A,
-}
-
-impl OpcodeMap {
-    /// Normally the opcode map is specified as bytes in the instruction, but some x64 encoding
-    /// formats pack this information as bits in a prefix (e.g. EVEX).
-    pub(crate) fn bits(&self) -> u8 {
-        match self {
-            OpcodeMap::None => 0b00,
-            OpcodeMap::_0F => 0b01,
-            OpcodeMap::_0F38 => 0b10,
-            OpcodeMap::_0F3A => 0b11,
-        }
-    }
-}
-
-impl Default for OpcodeMap {
-    fn default() -> Self {
-        Self::None
-    }
-}
-
-/// We may need to include one or more legacy prefix bytes before the REX prefix.  This enum
-/// covers only the small set of possibilities that we actually need.
-pub enum LegacyPrefixes {
-    /// No prefix bytes.
-    None,
-    /// Operand Size Override -- here, denoting "16-bit operation".
-    _66,
-    /// The Lock prefix.
-    _F0,
-    /// Operand size override and Lock.
-    _66F0,
-    /// REPNE, but no specific meaning here -- is just an opcode extension.
-    _F2,
-    /// REP/REPE, but no specific meaning here -- is just an opcode extension.
-    _F3,
-    /// Operand size override and same effect as F3.
-    _66F3,
-}
-
-impl LegacyPrefixes {
-    /// Emit the legacy prefix as bytes (e.g. in REX instructions).
-    #[inline(always)]
-    pub(crate) fn emit(&self, sink: &mut MachBuffer<Inst>) {
-        match self {
-            Self::_66 => sink.put1(0x66),
-            Self::_F0 => sink.put1(0xF0),
-            Self::_66F0 => {
-                // I don't think the order matters, but in any case, this is the same order that
-                // the GNU assembler uses.
-                sink.put1(0x66);
-                sink.put1(0xF0);
-            }
-            Self::_F2 => sink.put1(0xF2),
-            Self::_F3 => sink.put1(0xF3),
-            Self::_66F3 => {
-                sink.put1(0x66);
-                sink.put1(0xF3);
-            }
-            Self::None => (),
-        }
-    }
-
-    /// Emit the legacy prefix as bits (e.g. for EVEX instructions).
-    #[inline(always)]
-    pub(crate) fn bits(&self) -> u8 {
-        match self {
-            Self::None => 0b00,
-            Self::_66 => 0b01,
-            Self::_F3 => 0b10,
-            Self::_F2 => 0b11,
-            _ => panic!(
-                "VEX and EVEX bits can only be extracted from single prefixes: None, 66, F3, F2"
-            ),
-        }
-    }
-}
-
-impl Default for LegacyPrefixes {
-    fn default() -> Self {
-        Self::None
-    }
-}
-
-/// This is the core 'emit' function for instructions that reference memory.
-///
-/// For an instruction that has as operands a reg encoding `enc_g` and a memory address `mem_e`,
-/// create and emit:
-/// - first the legacy prefixes, if any
-/// - then the REX prefix, if needed
-/// - then caller-supplied opcode byte(s) (`opcodes` and `num_opcodes`),
-/// - then the MOD/RM byte,
-/// - then optionally, a SIB byte,
-/// - and finally optionally an immediate that will be derived from the `mem_e` operand.
-///
-/// For most instructions up to and including SSE4.2, that will be the whole instruction: this is
-/// what we call "standard" instructions, and abbreviate "std" in the name here. VEX-prefixed
-/// instructions will require their own emitter functions.
-///
-/// This will also work for 32-bits x86 instructions, assuming no REX prefix is provided.
-///
-/// The opcodes are written bigendianly for the convenience of callers.  For example, if the opcode
-/// bytes to be emitted are, in this order, F3 0F 27, then the caller should pass `opcodes` ==
-/// 0xF3_0F_27 and `num_opcodes` == 3.
-///
-/// The register operand is represented here not as a `Reg` but as its hardware encoding, `enc_g`.
-/// `rex` can specify special handling for the REX prefix.  By default, the REX prefix will
-/// indicate a 64-bit operation and will be deleted if it is redundant (0x40).  Note that for a
-/// 64-bit operation, the REX prefix will normally never be redundant, since REX.W must be 1 to
-/// indicate a 64-bit operation.
-pub(crate) fn emit_std_enc_mem(
-    sink: &mut MachBuffer<Inst>,
-    state: &EmitState,
-    info: &EmitInfo,
-    prefixes: LegacyPrefixes,
-    opcodes: u32,
-    mut num_opcodes: usize,
-    enc_g: u8,
-    mem_e: &Amode,
-    rex: RexFlags,
-) {
-    // General comment for this function: the registers in `mem_e` must be
-    // 64-bit integer registers, because they are part of an address
-    // expression.  But `enc_g` can be derived from a register of any class.
-
-    let srcloc = state.cur_srcloc();
-    let can_trap = mem_e.can_trap();
-    if can_trap {
-        sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
-    }
-
-    prefixes.emit(sink);
-
-    match mem_e {
-        Amode::ImmReg { simm32, base, .. } => {
-            // If this is an access based off of RSP, it may trap with a stack overflow if it's the
-            // first touch of a new stack page.
-            if *base == regs::rsp() && !can_trap && info.flags.enable_probestack() {
-                sink.add_trap(srcloc, TrapCode::StackOverflow);
-            }
-
-            // First, the REX byte.
-            let enc_e = int_reg_enc(*base);
-            rex.emit_two_op(sink, enc_g, enc_e);
-
-            // Now the opcode(s).  These include any other prefixes the caller
-            // hands to us.
-            while num_opcodes > 0 {
-                num_opcodes -= 1;
-                sink.put1(((opcodes >> (num_opcodes << 3)) & 0xFF) as u8);
-            }
-
-            // Now the mod/rm and associated immediates.  This is
-            // significantly complicated due to the multiple special cases.
-            if *simm32 == 0
-                && enc_e != regs::ENC_RSP
-                && enc_e != regs::ENC_RBP
-                && enc_e != regs::ENC_R12
-                && enc_e != regs::ENC_R13
-            {
-                // FIXME JRS 2020Feb11: those four tests can surely be
-                // replaced by a single mask-and-compare check.  We should do
-                // that because this routine is likely to be hot.
-                sink.put1(encode_modrm(0, enc_g & 7, enc_e & 7));
-            } else if *simm32 == 0 && (enc_e == regs::ENC_RSP || enc_e == regs::ENC_R12) {
-                sink.put1(encode_modrm(0, enc_g & 7, 4));
-                sink.put1(0x24);
-            } else if low8_will_sign_extend_to_32(*simm32)
-                && enc_e != regs::ENC_RSP
-                && enc_e != regs::ENC_R12
-            {
-                sink.put1(encode_modrm(1, enc_g & 7, enc_e & 7));
-                sink.put1((simm32 & 0xFF) as u8);
-            } else if enc_e != regs::ENC_RSP && enc_e != regs::ENC_R12 {
-                sink.put1(encode_modrm(2, enc_g & 7, enc_e & 7));
-                sink.put4(*simm32);
-            } else if (enc_e == regs::ENC_RSP || enc_e == regs::ENC_R12)
-                && low8_will_sign_extend_to_32(*simm32)
-            {
-                // REX.B distinguishes RSP from R12
-                sink.put1(encode_modrm(1, enc_g & 7, 4));
-                sink.put1(0x24);
-                sink.put1((simm32 & 0xFF) as u8);
-            } else if enc_e == regs::ENC_R12 || enc_e == regs::ENC_RSP {
-                //.. wait for test case for RSP case
-                // REX.B distinguishes RSP from R12
-                sink.put1(encode_modrm(2, enc_g & 7, 4));
-                sink.put1(0x24);
-                sink.put4(*simm32);
-            } else {
-                unreachable!("ImmReg");
-            }
-        }
-
-        Amode::ImmRegRegShift {
-            simm32,
-            base: reg_base,
-            index: reg_index,
-            shift,
-            ..
-        } => {
-            // If this is an access based off of RSP, it may trap with a stack overflow if it's the
-            // first touch of a new stack page.
-            if *reg_base == regs::rsp() && !can_trap && info.flags.enable_probestack() {
-                sink.add_trap(srcloc, TrapCode::StackOverflow);
-            }
-
-            let enc_base = int_reg_enc(*reg_base);
-            let enc_index = int_reg_enc(*reg_index);
-
-            // The rex byte.
-            rex.emit_three_op(sink, enc_g, enc_index, enc_base);
-
-            // All other prefixes and opcodes.
-            while num_opcodes > 0 {
-                num_opcodes -= 1;
-                sink.put1(((opcodes >> (num_opcodes << 3)) & 0xFF) as u8);
-            }
-
-            // modrm, SIB, immediates.
-            if low8_will_sign_extend_to_32(*simm32) && enc_index != regs::ENC_RSP {
-                sink.put1(encode_modrm(1, enc_g & 7, 4));
-                sink.put1(encode_sib(*shift, enc_index & 7, enc_base & 7));
-                sink.put1(*simm32 as u8);
-            } else if enc_index != regs::ENC_RSP {
-                sink.put1(encode_modrm(2, enc_g & 7, 4));
-                sink.put1(encode_sib(*shift, enc_index & 7, enc_base & 7));
-                sink.put4(*simm32);
-            } else {
-                panic!("ImmRegRegShift");
-            }
-        }
-
-        Amode::RipRelative { ref target } => {
-            // First, the REX byte, with REX.B = 0.
-            rex.emit_two_op(sink, enc_g, 0);
-
-            // Now the opcode(s).  These include any other prefixes the caller
-            // hands to us.
-            while num_opcodes > 0 {
-                num_opcodes -= 1;
-                sink.put1(((opcodes >> (num_opcodes << 3)) & 0xFF) as u8);
-            }
-
-            // RIP-relative is mod=00, rm=101.
-            sink.put1(encode_modrm(0, enc_g & 7, 0b101));
-
-            let offset = sink.cur_offset();
-            sink.use_label_at_offset(offset, *target, LabelUse::JmpRel32);
-            sink.put4(0);
-        }
-    }
-}
-
-/// This is the core 'emit' function for instructions that do not reference memory.
-///
-/// This is conceptually the same as emit_modrm_sib_enc_ge, except it is for the case where the E
-/// operand is a register rather than memory.  Hence it is much simpler.
-pub(crate) fn emit_std_enc_enc(
-    sink: &mut MachBuffer<Inst>,
-    prefixes: LegacyPrefixes,
-    opcodes: u32,
-    mut num_opcodes: usize,
-    enc_g: u8,
-    enc_e: u8,
-    rex: RexFlags,
-) {
-    // EncG and EncE can be derived from registers of any class, and they
-    // don't even have to be from the same class.  For example, for an
-    // integer-to-FP conversion insn, one might be RegClass::I64 and the other
-    // RegClass::V128.
-
-    // The legacy prefixes.
-    prefixes.emit(sink);
-
-    // The rex byte.
-    rex.emit_two_op(sink, enc_g, enc_e);
-
-    // All other prefixes and opcodes.
-    while num_opcodes > 0 {
-        num_opcodes -= 1;
-        sink.put1(((opcodes >> (num_opcodes << 3)) & 0xFF) as u8);
-    }
-
-    // Now the mod/rm byte.  The instruction we're generating doesn't access
-    // memory, so there is no SIB byte or immediate -- we're done.
-    sink.put1(encode_modrm(3, enc_g & 7, enc_e & 7));
-}
-
-// These are merely wrappers for the above two functions that facilitate passing
-// actual `Reg`s rather than their encodings.
-
-pub(crate) fn emit_std_reg_mem(
-    sink: &mut MachBuffer<Inst>,
-    state: &EmitState,
-    info: &EmitInfo,
-    prefixes: LegacyPrefixes,
-    opcodes: u32,
-    num_opcodes: usize,
-    reg_g: Reg,
-    mem_e: &Amode,
-    rex: RexFlags,
-) {
-    let enc_g = reg_enc(reg_g);
-    emit_std_enc_mem(
-        sink,
-        state,
-        info,
-        prefixes,
-        opcodes,
-        num_opcodes,
-        enc_g,
-        mem_e,
-        rex,
-    );
-}
-
-pub(crate) fn emit_std_reg_reg(
-    sink: &mut MachBuffer<Inst>,
-    prefixes: LegacyPrefixes,
-    opcodes: u32,
-    num_opcodes: usize,
-    reg_g: Reg,
-    reg_e: Reg,
-    rex: RexFlags,
-) {
-    let enc_g = reg_enc(reg_g);
-    let enc_e = reg_enc(reg_e);
-    emit_std_enc_enc(sink, prefixes, opcodes, num_opcodes, enc_g, enc_e, rex);
-}
-
-/// Write a suitable number of bits from an imm64 to the sink.
-pub(crate) fn emit_simm(sink: &mut MachBuffer<Inst>, size: u8, simm32: u32) {
-    match size {
-        8 | 4 => sink.put4(simm32),
-        2 => sink.put2(simm32 as u16),
-        1 => sink.put1(simm32 as u8),
-        _ => unreachable!(),
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/encoding/vex.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/encoding/vex.rs
deleted file mode 100644
index f2f3feebb..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/encoding/vex.rs
+++ /dev/null
@@ -1,2 +0,0 @@
-//! Encodes VEX instructions. These instructions are those added by the Advanced Vector Extensions
-//! (AVX).
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/inst.isle b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/inst.isle
deleted file mode 100644
index c2ff73056..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/inst.isle
+++ /dev/null
@@ -1,2579 +0,0 @@
-;; Extern type definitions and constructors for the x64 `MachInst` type.
-
-;;;; `MInst` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Don't build `MInst` variants directly, in general. Instead, use the
-;; instruction-emitting helpers defined further down.
-
-(type MInst nodebug
-      (enum
-       ;; Nops of various sizes, including zero.
-       (Nop (len u8))
-
-       ;; =========================================
-       ;; Integer instructions.
-
-       ;; Integer arithmetic/bit-twiddling.
-       (AluRmiR (size OperandSize) ;; 4 or 8
-                (op AluRmiROpcode)
-                (src1 Gpr)
-                (src2 GprMemImm)
-                (dst WritableGpr))
-
-       ;; Instructions on general-purpose registers that only read src and
-       ;; defines dst (dst is not modified). `bsr`, etc.
-       (UnaryRmR (size OperandSize) ;; 2, 4, or 8
-                 (op UnaryRmROpcode)
-                 (src GprMem)
-                 (dst WritableGpr))
-
-       ;; Bitwise not.
-       (Not (size OperandSize) ;; 1, 2, 4, or 8
-            (src Gpr)
-            (dst WritableGpr))
-
-       ;; Integer negation.
-       (Neg (size OperandSize) ;; 1, 2, 4, or 8
-            (src Gpr)
-            (dst WritableGpr))
-
-       ;; Integer quotient and remainder: (div idiv) $rax $rdx (reg addr)
-       (Div (size OperandSize) ;; 1, 2, 4, or 8
-            (signed bool)
-            (divisor GprMem)
-            (dividend Gpr)
-            (dst_quotient WritableGpr)
-            (dst_remainder WritableGpr))
-
-       ;; The high (and low) bits of a (un)signed multiply: `RDX:RAX := RAX *
-       ;; rhs`.
-       (MulHi (size OperandSize)
-              (signed bool)
-              (src1 Gpr)
-              (src2 GprMem)
-              (dst_lo WritableGpr)
-              (dst_hi WritableGpr))
-
-       ;; A synthetic sequence to implement the right inline checks for
-       ;; remainder and division, assuming the dividend is in %rax.
-       ;;
-       ;; Puts the result back into %rax if is_div, %rdx if !is_div, to mimic
-       ;; what the div instruction does.
-       ;;
-       ;; The generated code sequence is described in the emit's function match
-       ;; arm for this instruction.
-       ;;
-       ;; Note: %rdx is marked as modified by this instruction, to avoid an
-       ;; early clobber problem with the temporary and divisor registers. Make
-       ;; sure to zero %rdx right before this instruction, or you might run into
-       ;; regalloc failures where %rdx is live before its first def!
-       (CheckedDivOrRemSeq (kind DivOrRemKind)
-                           (size OperandSize)
-                           (dividend Gpr)
-                           ;; The divisor operand. Note it's marked as modified
-                           ;; so that it gets assigned a register different from
-                           ;; the temporary.
-                           (divisor WritableGpr)
-                           (dst_quotient WritableGpr)
-                           (dst_remainder WritableGpr)
-                           (tmp OptionWritableGpr))
-
-       ;; Do a sign-extend based on the sign of the value in rax into rdx: (cwd
-       ;; cdq cqo) or al into ah: (cbw)
-       (SignExtendData (size OperandSize) ;; 1, 2, 4, or 8
-                       (src Gpr)
-                       (dst WritableGpr))
-
-       ;; Constant materialization: (imm32 imm64) reg.
-       ;;
-       ;; Either: movl $imm32, %reg32 or movabsq $imm64, %reg32.
-       (Imm (dst_size OperandSize) ;; 4 or 8
-            (simm64 u64)
-            (dst WritableGpr))
-
-       ;; GPR to GPR move: mov (64 32) reg reg.
-       (MovRR (size OperandSize) ;; 4 or 8
-              (src Gpr)
-              (dst WritableGpr))
-
-       ;; Zero-extended loads, except for 64 bits: movz (bl bq wl wq lq) addr
-       ;; reg.
-       ;;
-       ;; Note that the lq variant doesn't really exist since the default
-       ;; zero-extend rule makes it unnecessary. For that case we emit the
-       ;; equivalent "movl AM, reg32".
-       (MovzxRmR (ext_mode ExtMode)
-                 (src GprMem)
-                 (dst WritableGpr))
-
-       ;; A plain 64-bit integer load, since MovZX_RM_R can't represent that.
-       (Mov64MR (src SyntheticAmode)
-                (dst WritableGpr))
-
-       ;; Loads the memory address of addr into dst.
-       (LoadEffectiveAddress (addr SyntheticAmode)
-                             (dst WritableGpr))
-
-       ;; Sign-extended loads and moves: movs (bl bq wl wq lq) addr reg.
-       (MovsxRmR (ext_mode ExtMode)
-                 (src GprMem)
-                 (dst WritableGpr))
-
-       ;; Integer stores: mov (b w l q) reg addr.
-       (MovRM (size OperandSize) ;; 1, 2, 4, or 8
-              (src Gpr)
-              (dst SyntheticAmode))
-
-       ;; Arithmetic shifts: (shl shr sar) (b w l q) imm reg.
-       (ShiftR (size OperandSize) ;; 1, 2, 4, or 8
-               (kind ShiftKind)
-               (src Gpr)
-               ;; shift count: `Imm8Gpr::Imm8(0 .. #bits-in-type - 1)` or
-               ;; `Imm8Reg::Gpr(r)` where `r` get's move mitosis'd into `%cl`.
-               (num_bits Imm8Gpr)
-               (dst WritableGpr))
-
-       ;; Arithmetic SIMD shifts.
-       (XmmRmiReg (opcode SseOpcode)
-                  (src1 Xmm)
-                  (src2 XmmMemImm)
-                  (dst WritableXmm))
-
-       ;; Integer comparisons/tests: cmp or test (b w l q) (reg addr imm) reg.
-       (CmpRmiR (size OperandSize) ;; 1, 2, 4, or 8
-                (opcode CmpOpcode)
-                (src GprMemImm)
-                (dst Gpr))
-
-       ;; Materializes the requested condition code in the destinaton reg.
-       (Setcc (cc CC)
-              (dst WritableGpr))
-
-       ;; =========================================
-       ;; Conditional moves.
-
-       ;; GPR conditional move; overwrites the destination register.
-       (Cmove (size OperandSize)
-              (cc CC)
-              (consequent GprMem)
-              (alternative Gpr)
-              (dst WritableGpr))
-
-       ;; XMM conditional move; overwrites the destination register.
-       (XmmCmove (size OperandSize)
-                 (cc CC)
-                 (consequent XmmMem)
-                 (alternative Xmm)
-                 (dst WritableXmm))
-
-       ;; =========================================
-       ;; Stack manipulation.
-
-       ;; pushq (reg addr imm)
-       (Push64 (src GprMemImm))
-
-       ;; popq reg
-       (Pop64 (dst WritableGpr))
-
-       ;; =========================================
-       ;; Floating-point operations.
-
-       ;; XMM (scalar or vector) binary op: (add sub and or xor mul adc? sbb?)
-       ;; (32 64) (reg addr) reg
-       (XmmRmR (op SseOpcode)
-               (src1 Xmm)
-               (src2 XmmMem)
-               (dst WritableXmm))
-
-       ;; XMM (scalar or vector) binary op that relies on the EVEX prefix.
-       (XmmRmREvex (op Avx512Opcode)
-                   (src1 XmmMem)
-                   (src2 Xmm)
-                   (dst WritableXmm))
-
-       ;; XMM (scalar or vector) unary op: mov between XMM registers (32 64)
-       ;; (reg addr) reg, sqrt, etc.
-       ;;
-       ;; This differs from XMM_RM_R in that the dst register of XmmUnaryRmR is
-       ;; not used in the computation of the instruction dst value and so does
-       ;; not have to be a previously valid value. This is characteristic of mov
-       ;; instructions.
-       (XmmUnaryRmR (op SseOpcode)
-                    (src XmmMem)
-                    (dst WritableXmm))
-
-       ;; XMM (scalar or vector) unary op that relies on the EVEX prefix.
-       (XmmUnaryRmREvex (op Avx512Opcode)
-                        (src XmmMem)
-                        (dst WritableXmm))
-
-       ;; XMM (scalar or vector) unary op (from xmm to reg/mem): stores, movd,
-       ;; movq
-       (XmmMovRM (op SseOpcode)
-                 (src Reg)
-                 (dst SyntheticAmode))
-
-       ;; XMM (vector) unary op (to move a constant value into an xmm register):
-       ;; movups
-       (XmmLoadConst (src VCodeConstant)
-                     (dst WritableReg)
-                     (ty Type))
-
-       ;; XMM (scalar) unary op (from xmm to integer reg): movd, movq,
-       ;; cvtts{s,d}2si
-       (XmmToGpr (op SseOpcode)
-                 (src Xmm)
-                 (dst WritableGpr)
-                 (dst_size OperandSize))
-
-       ;; XMM (scalar) unary op (from integer to float reg): movd, movq,
-       ;; cvtsi2s{s,d}
-       (GprToXmm (op SseOpcode)
-                 (src GprMem)
-                 (dst WritableXmm)
-                 (src_size OperandSize))
-
-       ;; Converts an unsigned int64 to a float32/float64.
-       (CvtUint64ToFloatSeq (dst_size OperandSize) ;; 4 or 8
-                            ;; A copy of the source register, fed by
-                            ;; lowering. It is marked as modified during
-                            ;; register allocation to make sure that the
-                            ;; temporary registers differ from the src register,
-                            ;; since both registers are live at the same time in
-                            ;; the generated code sequence.
-                            (src WritableGpr)
-                            (dst WritableXmm)
-                            (tmp_gpr1 WritableGpr)
-                            (tmp_gpr2 WritableGpr))
-
-       ;; Converts a scalar xmm to a signed int32/int64.
-       (CvtFloatToSintSeq (dst_size OperandSize)
-                          (src_size OperandSize)
-                          (is_saturating bool)
-                          ;; A copy of the source register, fed by
-                          ;; lowering. It is marked as modified during
-                          ;; register allocation to make sure that the
-                          ;; temporary registers differ from the src register,
-                          ;; since both registers are live at the same time in
-                          ;; the generated code sequence.
-                          (src WritableXmm)
-                          (dst WritableGpr)
-                          (tmp_gpr WritableGpr)
-                          (tmp_xmm WritableXmm))
-
-       ;; Converts a scalar xmm to an unsigned int32/int64.
-       (CvtFloatToUintSeq (dst_size OperandSize)
-                          (src_size OperandSize)
-                          (is_saturating bool)
-                          ;; A copy of the source register, fed by
-                          ;; lowering. It is marked as modified during
-                          ;; register allocation to make sure that the
-                          ;; temporary registers differ from the src register,
-                          ;; since both registers are live at the same time in
-                          ;; the generated code sequence.
-                          (src WritableXmm)
-                          (dst WritableGpr)
-                          (tmp_gpr WritableGpr)
-                          (tmp_xmm WritableXmm))
-
-       ;; A sequence to compute min/max with the proper NaN semantics for xmm
-       ;; registers.
-       (XmmMinMaxSeq (size OperandSize)
-                     (is_min bool)
-                     (lhs Xmm)
-                     (rhs Xmm)
-                     (dst WritableXmm))
-
-       ;; Float comparisons/tests: cmp (b w l q) (reg addr imm) reg.
-       (XmmCmpRmR (op SseOpcode)
-                  (src XmmMem)
-                  (dst Xmm))
-
-       ;; A binary XMM instruction with an 8-bit immediate: e.g. cmp (ps pd) imm
-       ;; (reg addr) reg
-       ;;
-       ;; Note: this has to use `Reg*`, not `Xmm*`, operands because it is used
-       ;; in various lane insertion and extraction instructions that move
-       ;; between XMMs and GPRs.
-       (XmmRmRImm (op SseOpcode)
-                  (src1 Reg)
-                  (src2 RegMem)
-                  (dst WritableReg)
-                  (imm u8)
-                  (size OperandSize))
-
-       ;; =========================================
-       ;; Control flow instructions.
-
-       ;; Direct call: call simm32.
-       (CallKnown (dest ExternalName)
-                  (uses VecReg)
-                  (defs VecWritableReg)
-                  (opcode Opcode))
-
-       ;; Indirect call: callq (reg mem)
-       (CallUnknown (dest RegMem)
-                    (uses VecReg)
-                    (defs VecWritableReg)
-                    (opcode Opcode))
-
-       ;; Return.
-       (Ret)
-
-       ;; A placeholder instruction, generating no code, meaning that a function
-       ;; epilogue must be inserted there.
-       (EpiloguePlaceholder)
-
-       ;; Jump to a known target: jmp simm32.
-       (JmpKnown (dst MachLabel))
-
-
-       ;; One-way conditional branch: jcond cond target.
-       ;;
-       ;; This instruction is useful when we have conditional jumps depending on
-       ;; more than two conditions, see for instance the lowering of Brz/brnz
-       ;; with Fcmp inputs.
-       ;;
-       ;; A note of caution: in contexts where the branch target is another
-       ;; block, this has to be the same successor as the one specified in the
-       ;; terminator branch of the current block.  Otherwise, this might confuse
-       ;; register allocation by creating new invisible edges.
-       (JmpIf (cc CC)
-              (taken MachLabel))
-
-       ;; Two-way conditional branch: jcond cond target target.
-       ;;
-       ;; Emitted as a compound sequence; the MachBuffer will shrink it as
-       ;; appropriate.
-       (JmpCond (cc CC)
-                (taken MachLabel)
-                (not_taken MachLabel))
-
-       ;; Jump-table sequence, as one compound instruction (see note in lower.rs
-       ;; for rationale).
-       ;;
-       ;; The generated code sequence is described in the emit's function match
-       ;; arm for this instruction.
-       ;;
-       ;; See comment in lowering about the temporaries signedness.
-       (JmpTableSeq (idx Reg)
-                    (tmp1 WritableReg)
-                    (tmp2 WritableReg)
-                    (default_target MachLabel)
-                    (targets VecMachLabel)
-                    (targets_for_term VecMachLabel))
-
-       ;; Indirect jump: jmpq (reg mem).
-       (JmpUnknown (target RegMem))
-
-       ;; Traps if the condition code is set.
-       (TrapIf (cc CC)
-               (trap_code TrapCode))
-
-       ;; A debug trap.
-       (Hlt)
-
-       ;; An instruction that will always trigger the illegal instruction
-       ;; exception.
-       (Ud2 (trap_code TrapCode))
-
-       ;; Loads an external symbol in a register, with a relocation:
-       ;;
-       ;; movq $name@GOTPCREL(%rip), dst    if PIC is enabled, or
-       ;; movabsq $name, dst                otherwise.
-       (LoadExtName (dst WritableReg)
-                    (name BoxExternalName)
-                    (offset i64))
-
-       ;; =========================================
-       ;; Instructions pertaining to atomic memory accesses.
-
-       ;; A standard (native) `lock cmpxchg src, (amode)`, with register
-       ;; conventions:
-       ;;
-       ;; `mem`          (read) address
-       ;; `replacement`  (read) replacement value
-       ;; %rax           (modified) in: expected value, out: value that was actually at `dst`
-       ;; %rflags is written.  Do not assume anything about it after the instruction.
-       ;;
-       ;; The instruction "succeeded" iff the lowest `ty` bits of %rax
-       ;; afterwards are the same as they were before.
-       (LockCmpxchg (ty Type) ;; I8, I16, I32, or I64
-                    (replacement Reg)
-                    (expected Reg)
-                    (mem SyntheticAmode)
-                    (dst_old WritableReg))
-
-       ;; A synthetic instruction, based on a loop around a native `lock
-       ;; cmpxchg` instruction.
-       ;;
-       ;; This atomically modifies a value in memory and returns the old value.
-       ;; The sequence consists of an initial "normal" load from `dst`, followed
-       ;; by a loop which computes the new value and tries to compare-and-swap
-       ;; ("CAS") it into `dst`, using the native instruction `lock
-       ;; cmpxchg{b,w,l,q}` .  The loop iterates until the CAS is successful.
-       ;; If there is no contention, there will be only one pass through the
-       ;; loop body.  The sequence does *not* perform any explicit memory fence
-       ;; instructions (mfence/sfence/lfence).
-       ;;
-       ;; Note that the transaction is atomic in the sense that, as observed by
-       ;; some other thread, `dst` either has the initial or final value, but no
-       ;; other.  It isn't atomic in the sense of guaranteeing that no other
-       ;; thread writes to `dst` in between the initial load and the CAS -- but
-       ;; that would cause the CAS to fail unless the other thread's last write
-       ;; before the CAS wrote the same value that was already there.  In other
-       ;; words, this implementation suffers (unavoidably) from the A-B-A
-       ;; problem.
-       ;;
-       ;; This instruction sequence has fixed register uses as follows:
-       ;;
-       ;; %r9   (read) address
-       ;; %r10  (read) second operand for `op`
-       ;; %r11  (written) scratch reg; value afterwards has no meaning
-       ;; %rax  (written) the old value at %r9
-       ;; %rflags is written.  Do not assume anything about it after the instruction.
-       (AtomicRmwSeq (ty Type) ;; I8, I16, I32, or I64
-                     (op AtomicRmwOp)
-                     (address Reg)
-                     (operand Reg)
-                     (temp WritableReg)
-                     (dst_old WritableReg))
-
-       ;; A memory fence (mfence, lfence or sfence).
-       (Fence (kind FenceKind))
-
-       ;; =========================================
-       ;; Meta-instructions generating no code.
-
-       ;; Marker, no-op in generated code: SP "virtual offset" is adjusted.
-       ;;
-       ;; This controls how `MemArg::NominalSPOffset` args are lowered.
-       (VirtualSPOffsetAdj (offset i64))
-
-       ;; Provides a way to tell the register allocator that the upcoming
-       ;; sequence of instructions will overwrite `dst` so it should be
-       ;; considered as a `def`; use this with care.
-       ;;
-       ;; This is useful when we have a sequence of instructions whose register
-       ;; usages are nominally `mod`s, but such that the combination of
-       ;; operations creates a result that is independent of the initial
-       ;; register value. It's thus semantically a `def`, not a `mod`, when all
-       ;; the instructions are taken together, so we want to ensure the register
-       ;; is defined (its live-range starts) prior to the sequence to keep
-       ;; analyses happy.
-       ;;
-       ;; One alternative would be a compound instruction that somehow
-       ;; encapsulates the others and reports its own `def`s/`use`s/`mod`s; this
-       ;; adds complexity (the instruction list is no longer flat) and requires
-       ;; knowledge about semantics and initial-value independence anyway.
-       (XmmUninitializedValue (dst WritableXmm))
-
-       ;; A call to the `ElfTlsGetAddr` libcall. Returns address of TLS symbol
-       ;; in `rax`.
-       (ElfTlsGetAddr (symbol ExternalName))
-
-       ;; A Mach-O TLS symbol access. Returns address of the TLS symbol in
-       ;; `rax`.
-       (MachOTlsGetAddr (symbol ExternalName))
-
-       ;; A definition of a value label.
-       (ValueLabelMarker (reg Reg)
-                         (label ValueLabel))
-
-       ;; An unwind pseudoinstruction describing the state of the machine at
-       ;; this program point.
-       (Unwind (inst UnwindInst))))
-
-(type OperandSize extern
-      (enum Size8
-            Size16
-            Size32
-            Size64))
-
-(type VCodeConstant (primitive VCodeConstant))
-
-(type FenceKind extern
-      (enum MFence
-            LFence
-            SFence))
-
-;; Get the `OperandSize` for a given `Type`, rounding smaller types up to 32 bits.
-(decl operand_size_of_type_32_64 (Type) OperandSize)
-(extern constructor operand_size_of_type_32_64 operand_size_of_type_32_64)
-
-;; Get the true `OperandSize` for a given `Type`, with no rounding.
-(decl raw_operand_size_of_type (Type) OperandSize)
-(extern constructor raw_operand_size_of_type raw_operand_size_of_type)
-
-;; Get the bit width of an `OperandSize`.
-(decl operand_size_bits (OperandSize) u16)
-(rule (operand_size_bits (OperandSize.Size8)) 8)
-(rule (operand_size_bits (OperandSize.Size16)) 16)
-(rule (operand_size_bits (OperandSize.Size32)) 32)
-(rule (operand_size_bits (OperandSize.Size64)) 64)
-
-(type AluRmiROpcode extern
-      (enum Add
-            Adc
-            Sub
-            Sbb
-            And
-            Or
-            Xor
-            Mul
-            And8
-            Or8))
-
-(type UnaryRmROpcode extern
-      (enum Bsr
-            Bsf
-            Lzcnt
-            Tzcnt
-            Popcnt))
-
-(type DivOrRemKind extern
-      (enum SignedDiv
-            UnsignedDiv
-            SignedRem
-            UnsignedRem))
-
-(type SseOpcode extern
-      (enum Addps
-            Addpd
-            Addss
-            Addsd
-            Andps
-            Andpd
-            Andnps
-            Andnpd
-            Blendvpd
-            Blendvps
-            Comiss
-            Comisd
-            Cmpps
-            Cmppd
-            Cmpss
-            Cmpsd
-            Cvtdq2ps
-            Cvtdq2pd
-            Cvtpd2ps
-            Cvtps2pd
-            Cvtsd2ss
-            Cvtsd2si
-            Cvtsi2ss
-            Cvtsi2sd
-            Cvtss2si
-            Cvtss2sd
-            Cvttpd2dq
-            Cvttps2dq
-            Cvttss2si
-            Cvttsd2si
-            Divps
-            Divpd
-            Divss
-            Divsd
-            Insertps
-            Maxps
-            Maxpd
-            Maxss
-            Maxsd
-            Minps
-            Minpd
-            Minss
-            Minsd
-            Movaps
-            Movapd
-            Movd
-            Movdqa
-            Movdqu
-            Movlhps
-            Movmskps
-            Movmskpd
-            Movq
-            Movss
-            Movsd
-            Movups
-            Movupd
-            Mulps
-            Mulpd
-            Mulss
-            Mulsd
-            Orps
-            Orpd
-            Pabsb
-            Pabsw
-            Pabsd
-            Packssdw
-            Packsswb
-            Packusdw
-            Packuswb
-            Paddb
-            Paddd
-            Paddq
-            Paddw
-            Paddsb
-            Paddsw
-            Paddusb
-            Paddusw
-            Palignr
-            Pand
-            Pandn
-            Pavgb
-            Pavgw
-            Pblendvb
-            Pcmpeqb
-            Pcmpeqw
-            Pcmpeqd
-            Pcmpeqq
-            Pcmpgtb
-            Pcmpgtw
-            Pcmpgtd
-            Pcmpgtq
-            Pextrb
-            Pextrw
-            Pextrd
-            Pinsrb
-            Pinsrw
-            Pinsrd
-            Pmaddubsw
-            Pmaddwd
-            Pmaxsb
-            Pmaxsw
-            Pmaxsd
-            Pmaxub
-            Pmaxuw
-            Pmaxud
-            Pminsb
-            Pminsw
-            Pminsd
-            Pminub
-            Pminuw
-            Pminud
-            Pmovmskb
-            Pmovsxbd
-            Pmovsxbw
-            Pmovsxbq
-            Pmovsxwd
-            Pmovsxwq
-            Pmovsxdq
-            Pmovzxbd
-            Pmovzxbw
-            Pmovzxbq
-            Pmovzxwd
-            Pmovzxwq
-            Pmovzxdq
-            Pmuldq
-            Pmulhw
-            Pmulhuw
-            Pmulhrsw
-            Pmulld
-            Pmullw
-            Pmuludq
-            Por
-            Pshufb
-            Pshufd
-            Psllw
-            Pslld
-            Psllq
-            Psraw
-            Psrad
-            Psrlw
-            Psrld
-            Psrlq
-            Psubb
-            Psubd
-            Psubq
-            Psubw
-            Psubsb
-            Psubsw
-            Psubusb
-            Psubusw
-            Ptest
-            Punpckhbw
-            Punpckhwd
-            Punpcklbw
-            Punpcklwd
-            Pxor
-            Rcpss
-            Roundps
-            Roundpd
-            Roundss
-            Roundsd
-            Rsqrtss
-            Shufps
-            Sqrtps
-            Sqrtpd
-            Sqrtss
-            Sqrtsd
-            Subps
-            Subpd
-            Subss
-            Subsd
-            Ucomiss
-            Ucomisd
-            Unpcklps
-            Xorps
-            Xorpd))
-
-(type CmpOpcode extern
-      (enum Cmp
-            Test))
-
-(type RegMemImm extern
-      (enum
-       (Reg (reg Reg))
-       (Mem (addr SyntheticAmode))
-       (Imm (simm32 u32))))
-
-;; Put the given clif value into a `RegMemImm` operand.
-;;
-;; Asserts that the value fits into a single register, and doesn't require
-;; multiple registers for its representation (like `i128` for example).
-;;
-;; As a side effect, this marks the value as used.
-(decl put_in_reg_mem_imm (Value) RegMemImm)
-(extern constructor put_in_reg_mem_imm put_in_reg_mem_imm)
-
-(type RegMem extern
-      (enum
-       (Reg (reg Reg))
-       (Mem (addr SyntheticAmode))))
-
-;; Put the given clif value into a `RegMem` operand.
-;;
-;; Asserts that the value fits into a single register, and doesn't require
-;; multiple registers for its representation (like `i128` for example).
-;;
-;; As a side effect, this marks the value as used.
-(decl put_in_reg_mem (Value) RegMem)
-(extern constructor put_in_reg_mem put_in_reg_mem)
-
-(type SyntheticAmode extern (enum))
-
-(decl synthetic_amode_to_reg_mem (SyntheticAmode) RegMem)
-(extern constructor synthetic_amode_to_reg_mem synthetic_amode_to_reg_mem)
-
-(type Amode extern (enum))
-
-(decl amode_imm_reg_reg_shift (u32 Gpr Gpr u8) Amode)
-(extern constructor amode_imm_reg_reg_shift amode_imm_reg_reg_shift)
-
-(decl amode_to_synthetic_amode (Amode) SyntheticAmode)
-(extern constructor amode_to_synthetic_amode amode_to_synthetic_amode)
-
-(type ShiftKind extern
-      (enum ShiftLeft
-            ShiftRightLogical
-            ShiftRightArithmetic
-            RotateLeft
-            RotateRight))
-
-(type Imm8Reg extern
-      (enum (Imm8 (imm u8))
-            (Reg (reg Reg))))
-
-;; Put the given clif value into a `Imm8Reg` operand, masked to the bit width of
-;; the given type.
-;;
-;; Asserts that the value fits into a single register, and doesn't require
-;; multiple registers for its representation (like `i128` for example).
-;;
-;; As a side effect, this marks the value as used.
-;;
-;; This is used when lowering various shifts and rotates.
-(decl put_masked_in_imm8_gpr (Value Type) Imm8Gpr)
-(extern constructor put_masked_in_imm8_gpr put_masked_in_imm8_gpr)
-
-(type CC extern
-      (enum O
-            NO
-            B
-            NB
-            Z
-            NZ
-            BE
-            NBE
-            S
-            NS
-            L
-            NL
-            LE
-            NLE
-            P
-            NP))
-
-(type Avx512Opcode extern
-      (enum Vcvtudq2ps
-            Vpabsq
-            Vpermi2b
-            Vpmullq
-            Vpopcntb))
-
-(type FcmpImm extern
-      (enum Equal
-            LessThan
-            LessThanOrEqual
-            Unordered
-            NotEqual
-            UnorderedOrGreaterThanOrEqual
-            UnorderedOrGreaterThan
-            Ordered))
-
-(decl encode_fcmp_imm (FcmpImm) u8)
-(extern constructor encode_fcmp_imm encode_fcmp_imm)
-
-;;;; Newtypes for Different Register Classes ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(type Gpr (primitive Gpr))
-(type WritableGpr (primitive WritableGpr))
-(type OptionWritableGpr (primitive OptionWritableGpr))
-(type GprMem extern (enum))
-(type GprMemImm extern (enum))
-(type Imm8Gpr extern (enum))
-
-(type Xmm (primitive Xmm))
-(type WritableXmm (primitive WritableXmm))
-(type OptionWritableXmm (primitive OptionWritableXmm))
-(type XmmMem extern (enum))
-(type XmmMemImm extern (enum))
-
-;; Convert an `Imm8Reg` into an `Imm8Gpr`.
-(decl imm8_reg_to_imm8_gpr (Imm8Reg) Imm8Gpr)
-(extern constructor imm8_reg_to_imm8_gpr imm8_reg_to_imm8_gpr)
-
-;; Convert a `WritableGpr` to a `WritableReg`.
-(decl writable_gpr_to_reg (WritableGpr) WritableReg)
-(extern constructor writable_gpr_to_reg writable_gpr_to_reg)
-
-;; Convert a `WritableXmm` to a `WritableReg`.
-(decl writable_xmm_to_reg (WritableXmm) WritableReg)
-(extern constructor writable_xmm_to_reg writable_xmm_to_reg)
-
-;; Convert a `WritableReg` to a `WritableXmm`.
-(decl writable_reg_to_xmm (WritableReg) WritableXmm)
-(extern constructor writable_reg_to_xmm writable_reg_to_xmm)
-
-;; Convert a `WritableXmm` to an `Xmm`.
-(decl writable_xmm_to_xmm (WritableXmm) Xmm)
-(extern constructor writable_xmm_to_xmm writable_xmm_to_xmm)
-
-;; Convert a `WritableGpr` to an `Gpr`.
-(decl writable_gpr_to_gpr (WritableGpr) Gpr)
-(extern constructor writable_gpr_to_gpr writable_gpr_to_gpr)
-
-;; Convert an `Gpr` to a `Reg`.
-(decl gpr_to_reg (Gpr) Reg)
-(extern constructor gpr_to_reg gpr_to_reg)
-
-;; Convert an `Gpr` to a `GprMem`.
-(decl gpr_to_gpr_mem (Gpr) GprMem)
-(extern constructor gpr_to_gpr_mem gpr_to_gpr_mem)
-
-;; Convert an `Gpr` to a `GprMemImm`.
-(decl gpr_to_gpr_mem_imm (Gpr) GprMemImm)
-(extern constructor gpr_to_gpr_mem_imm gpr_to_gpr_mem_imm)
-
-;; Convert an `Xmm` to a `Reg`.
-(decl xmm_to_reg (Xmm) Reg)
-(extern constructor xmm_to_reg xmm_to_reg)
-
-;; Convert an `Xmm` into an `XmmMemImm`.
-(decl xmm_to_xmm_mem_imm (Xmm) XmmMemImm)
-(extern constructor xmm_to_xmm_mem_imm xmm_to_xmm_mem_imm)
-
-;; Allocate a new temporary GPR register.
-(decl temp_writable_gpr () WritableGpr)
-(extern constructor temp_writable_gpr temp_writable_gpr)
-
-;; Allocate a new temporary XMM register.
-(decl temp_writable_xmm () WritableXmm)
-(extern constructor temp_writable_xmm temp_writable_xmm)
-
-;; Construct a new `XmmMem` from the given `RegMem`.
-;;
-;; Asserts that the `RegMem`'s register, if any, is an XMM register.
-(decl reg_mem_to_xmm_mem (RegMem) XmmMem)
-(extern constructor reg_mem_to_xmm_mem reg_mem_to_xmm_mem)
-
-;; Construct a new `GprMemImm` from the given `RegMemImm`.
-;;
-;; Asserts that the `RegMemImm`'s register, if any, is an GPR register.
-(decl gpr_mem_imm_new (RegMemImm) GprMemImm)
-(extern constructor gpr_mem_imm_new gpr_mem_imm_new)
-
-;; Construct a new `XmmMemImm` from the given `RegMemImm`.
-;;
-;; Asserts that the `RegMemImm`'s register, if any, is an XMM register.
-(decl xmm_mem_imm_new (RegMemImm) XmmMemImm)
-(extern constructor xmm_mem_imm_new xmm_mem_imm_new)
-
-;; Construct a new `XmmMem` from an `Xmm`.
-(decl xmm_to_xmm_mem (Xmm) XmmMem)
-(extern constructor xmm_to_xmm_mem xmm_to_xmm_mem)
-
-;; Construct a new `XmmMem` from an `RegMem`.
-(decl xmm_mem_to_reg_mem (XmmMem) RegMem)
-(extern constructor xmm_mem_to_reg_mem xmm_mem_to_reg_mem)
-
-;; Convert a `GprMem` to a `RegMem`.
-(decl gpr_mem_to_reg_mem (GprMem) RegMem)
-(extern constructor gpr_mem_to_reg_mem gpr_mem_to_reg_mem)
-
-;; Construct a new `Xmm` from a `Reg`.
-;;
-;; Asserts that the register is a XMM.
-(decl xmm_new (Reg) Xmm)
-(extern constructor xmm_new xmm_new)
-
-;; Construct a new `Gpr` from a `Reg`.
-;;
-;; Asserts that the register is a GPR.
-(decl gpr_new (Reg) Gpr)
-(extern constructor gpr_new gpr_new)
-
-;; Construct a new `GprMem` from a `RegMem`.
-;;
-;; Asserts that the `RegMem`'s register, if any, is a GPR.
-(decl reg_mem_to_gpr_mem (RegMem) GprMem)
-(extern constructor reg_mem_to_gpr_mem reg_mem_to_gpr_mem)
-
-;; Construct a `GprMem` from a `Reg`.
-;;
-;; Asserts that the `Reg` is a GPR.
-(decl reg_to_gpr_mem (Reg) GprMem)
-(extern constructor reg_to_gpr_mem reg_to_gpr_mem)
-
-;; Construct a `GprMemImm` from a `Reg`.
-;;
-;; Asserts that the `Reg` is a GPR.
-(decl reg_to_gpr_mem_imm (Reg) GprMemImm)
-(rule (reg_to_gpr_mem_imm r)
-      (gpr_to_gpr_mem_imm (gpr_new r)))
-
-;; Put a value into a GPR.
-;;
-;; Asserts that the value goes into a GPR.
-(decl put_in_gpr (Value) Gpr)
-(rule (put_in_gpr val)
-      (gpr_new (put_in_reg val)))
-
-;; Put a value into a `GprMem`.
-;;
-;; Asserts that the value goes into a GPR.
-(decl put_in_gpr_mem (Value) GprMem)
-(rule (put_in_gpr_mem val)
-      (reg_mem_to_gpr_mem (put_in_reg_mem val)))
-
-;; Put a value into a `GprMemImm`.
-;;
-;; Asserts that the value goes into a GPR.
-(decl put_in_gpr_mem_imm (Value) GprMemImm)
-(rule (put_in_gpr_mem_imm val)
-      (gpr_mem_imm_new (put_in_reg_mem_imm val)))
-
-;; Put a value into a XMM.
-;;
-;; Asserts that the value goes into a XMM.
-(decl put_in_xmm (Value) Xmm)
-(rule (put_in_xmm val)
-      (xmm_new (put_in_reg val)))
-
-;; Put a value into a `XmmMem`.
-;;
-;; Asserts that the value goes into a XMM.
-(decl put_in_xmm_mem (Value) XmmMem)
-(rule (put_in_xmm_mem val)
-      (reg_mem_to_xmm_mem (put_in_reg_mem val)))
-
-;; Put a value into a `XmmMemImm`.
-;;
-;; Asserts that the value goes into a XMM.
-(decl put_in_xmm_mem_imm (Value) XmmMemImm)
-(rule (put_in_xmm_mem_imm val)
-      (xmm_mem_imm_new (put_in_reg_mem_imm val)))
-
-;; Construct an `InstOutput` out of a single GPR register.
-(decl output_gpr (Gpr) InstOutput)
-(rule (output_gpr x)
-      (output_reg (gpr_to_reg x)))
-
-;; Construct a `ValueRegs` out of two GPR registers.
-(decl value_gprs (Gpr Gpr) ValueRegs)
-(rule (value_gprs x y)
-      (value_regs (gpr_to_reg x) (gpr_to_reg y)))
-
-;; Construct an `InstOutput` out of a single XMM register.
-(decl output_xmm (Xmm) InstOutput)
-(rule (output_xmm x)
-      (output_reg (xmm_to_reg x)))
-
-;; Get the `n`th reg in a `ValueRegs` and construct a GPR from it.
-;;
-;; Asserts that the register is a GPR.
-(decl value_regs_get_gpr (ValueRegs usize) Gpr)
-(rule (value_regs_get_gpr regs n)
-      (gpr_new (value_regs_get regs n)))
-
-;; Convert a `Gpr` to an `Imm8Gpr`.
-(decl gpr_to_imm8_gpr (Gpr) Imm8Gpr)
-(extern constructor gpr_to_imm8_gpr gpr_to_imm8_gpr)
-
-;; Convert an 8-bit immediate into an `Imm8Gpr`.
-(decl imm8_to_imm8_gpr (u8) Imm8Gpr)
-(extern constructor imm8_to_imm8_gpr imm8_to_imm8_gpr)
-
-;; Get the low half of the given `Value` as a GPR.
-(decl lo_gpr (Value) Gpr)
-(rule (lo_gpr regs) (gpr_new (lo_reg regs)))
-
-;;;; Helpers for Getting Particular Physical Registers ;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; These should only be used for legalization purposes, when we can't otherwise
-;; rely on something like `Inst::mov_mitosis` to put an operand into the
-;; appropriate physical register for whatever reason.
-
-(decl xmm0 () WritableXmm)
-(extern constructor xmm0 xmm0)
-
-;;;; Helpers for determining the register class of a value type ;;;;;;;;;;;;;;;;
-
-(decl is_xmm_type (Type) Type)
-(extern extractor is_xmm_type is_xmm_type)
-
-(decl is_gpr_type (Type) Type)
-(extern extractor is_gpr_type is_gpr_type)
-
-(decl is_single_register_type (Type) Type)
-(extern extractor is_single_register_type is_single_register_type)
-
-;;;; Helpers for Querying Enabled ISA Extensions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl avx512vl_enabled () Type)
-(extern extractor avx512vl_enabled avx512vl_enabled)
-
-(decl avx512dq_enabled () Type)
-(extern extractor avx512dq_enabled avx512dq_enabled)
-
-(decl avx512f_enabled () Type)
-(extern extractor avx512f_enabled avx512f_enabled)
-
-(decl avx512bitalg_enabled () Type)
-(extern extractor avx512bitalg_enabled avx512bitalg_enabled)
-
-(decl use_lzcnt () Type)
-(extern extractor use_lzcnt use_lzcnt)
-
-(decl use_bmi1 () Type)
-(extern extractor use_bmi1 use_bmi1)
-
-(decl use_popcnt () Type)
-(extern extractor use_popcnt use_popcnt)
-
-;;;; Helpers for Merging and Sinking Immediates/Loads  ;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Extract a constant `Imm8Reg.Imm8` from a value operand.
-(decl imm8_from_value (Imm8Reg) Value)
-(extern extractor imm8_from_value imm8_from_value)
-
-;; Mask a constant to the bit-width of the given type and package it into an
-;; `Imm8Reg.Imm8`. This is used for shifts and rotates, so that we don't try and
-;; shift/rotate more bits than the type has available, per Cranelift's
-;; semantics.
-(decl const_to_type_masked_imm8 (u64 Type) Imm8Gpr)
-(extern constructor const_to_type_masked_imm8 const_to_type_masked_imm8)
-
-;; Extract a constant `GprMemImm.Imm` from a value operand.
-(decl simm32_from_value (GprMemImm) Value)
-(extern extractor simm32_from_value simm32_from_value)
-
-;; Extract a constant `RegMemImm.Imm` from an `Imm64` immediate.
-(decl simm32_from_imm64 (GprMemImm) Imm64)
-(extern extractor simm32_from_imm64 simm32_from_imm64)
-
-;; A load that can be sunk into another operation.
-(type SinkableLoad extern (enum))
-
-;; Extract a `SinkableLoad` that works with `RegMemImm.Mem` from a value
-;; operand.
-(decl sinkable_load (SinkableLoad) Value)
-(extern extractor sinkable_load sinkable_load)
-
-;; Sink a `SinkableLoad` into a `RegMemImm.Mem`.
-;;
-;; This is a side-effectful operation that notifies the context that the
-;; instruction that produced the `SinkableImm` has been sunk into another
-;; instruction, and no longer needs to be lowered.
-(decl sink_load (SinkableLoad) RegMemImm)
-(extern constructor sink_load sink_load)
-
-(decl sink_load_to_gpr_mem_imm (SinkableLoad) GprMemImm)
-(rule (sink_load_to_gpr_mem_imm load)
-      (gpr_mem_imm_new (sink_load load)))
-
-;;;; Helpers for Sign/Zero Extending ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(type ExtKind extern
-      (enum None
-            SignExtend
-            ZeroExtend))
-
-(type ExtendKind (enum Sign Zero))
-
-(type ExtMode extern (enum BL BQ WL WQ LQ))
-
-;; `ExtMode::new`
-(decl ext_mode (u16 u16) ExtMode)
-(extern constructor ext_mode ext_mode)
-
-;; Put the given value into a register, but extended as the given type.
-(decl extend_to_gpr (Value Type ExtendKind) Gpr)
-
-;; If the value is already of the requested type, no extending is necessary.
-(rule (extend_to_gpr (and val (value_type ty)) =ty _kind)
-      (put_in_gpr val))
-
-(rule (extend_to_gpr (and val (value_type from_ty))
-                     to_ty
-                     kind)
-      (let ((from_bits u16 (ty_bits_u16 from_ty))
-            ;; Use `operand_size_of_type` so that the we clamp the output to 32-
-            ;; or 64-bit width types.
-            (to_bits u16 (operand_size_bits (operand_size_of_type_32_64 to_ty))))
-        (extend kind
-                to_ty
-                (ext_mode from_bits to_bits)
-                (put_in_gpr_mem val))))
-
-;; Do a sign or zero extension of the given `GprMem`.
-(decl extend (ExtendKind Type ExtMode GprMem) Gpr)
-
-;; Zero extending uses `movzx`.
-(rule (extend (ExtendKind.Zero) ty mode src)
-      (movzx ty mode src))
-
-;; Sign extending uses `movsx`.
-(rule (extend (ExtendKind.Sign) ty mode src)
-      (movsx ty mode src))
-
-;;;; Helpers for Working SSE tidbits ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Determine the appropriate operation for xor-ing vectors of the specified type
-(decl sse_xor_op (Type) SseOpcode)
-(rule (sse_xor_op $F32X4) (SseOpcode.Xorps))
-(rule (sse_xor_op $F64X2) (SseOpcode.Xorpd))
-(rule (sse_xor_op (multi_lane _bits _lanes)) (SseOpcode.Pxor))
-
-;; Performs an xor operation of the two operands specified.
-(decl sse_xor (Type Xmm XmmMem) Xmm)
-(rule (sse_xor ty x y) (xmm_rm_r ty (sse_xor_op ty) x y))
-
-;; Determine the appropriate operation to compare two vectors of the specified
-;; type.
-(decl sse_cmp_op (Type) SseOpcode)
-(rule (sse_cmp_op (multi_lane 8 16)) (SseOpcode.Pcmpeqb))
-(rule (sse_cmp_op (multi_lane 16 8)) (SseOpcode.Pcmpeqw))
-(rule (sse_cmp_op (multi_lane 32 4)) (SseOpcode.Pcmpeqd))
-(rule (sse_cmp_op (multi_lane 64 2)) (SseOpcode.Pcmpeqq))
-(rule (sse_cmp_op $F32X4) (SseOpcode.Cmpps))
-(rule (sse_cmp_op $F64X2) (SseOpcode.Cmppd))
-
-;; Generates a register value which has an all-ones pattern of the specified
-;; type.
-;;
-;; Note that this is accomplished by comparing a fresh register with itself,
-;; which for integers is always true. Also note that the comparison is always
-;; done for integers, it doesn't actually take the input `ty` into account. This
-;; is because we're comparing a fresh register to itself and we don't know the
-;; previous contents of the register. If a floating-point comparison is used
-;; then it runs the risk of comparing NaN against NaN and not actually producing
-;; an all-ones mask. By using integer comparision operations we're guaranteeed
-;; that everything is equal to itself.
-(decl vector_all_ones (Type) Xmm)
-(rule (vector_all_ones ty)
-      (let ((r WritableXmm (temp_writable_xmm))
-            (_ Unit (emit (MInst.XmmRmR (sse_cmp_op $I32X4)
-                                        r
-                                        r
-                                        r))))
-        r))
-
-;; Helper for creating an SSE register holding an `i64x2` from two `i64` values.
-(decl make_i64x2_from_lanes (GprMem GprMem) Xmm)
-(rule (make_i64x2_from_lanes lo hi)
-      (let ((dst_xmm WritableXmm (temp_writable_xmm))
-            (dst_reg WritableReg dst_xmm)
-            (_0 Unit (emit (MInst.XmmUninitializedValue dst_xmm)))
-            (_1 Unit (emit (MInst.XmmRmRImm (SseOpcode.Pinsrd)
-                                            dst_reg
-                                            lo
-                                            dst_reg
-                                            0
-                                            (OperandSize.Size64))))
-            (_2 Unit (emit (MInst.XmmRmRImm (SseOpcode.Pinsrd)
-                                            dst_reg
-                                            hi
-                                            dst_reg
-                                            1
-                                            (OperandSize.Size64)))))
-        dst_xmm))
-
-;; Move a `RegMemImm.Reg` operand to an XMM register, if necessary.
-(decl mov_rmi_to_xmm (RegMemImm) XmmMemImm)
-(rule (mov_rmi_to_xmm rmi @ (RegMemImm.Mem _)) (xmm_mem_imm_new rmi))
-(rule (mov_rmi_to_xmm rmi @ (RegMemImm.Imm _)) (xmm_mem_imm_new rmi))
-(rule (mov_rmi_to_xmm (RegMemImm.Reg r))
-      (gpr_to_xmm (SseOpcode.Movd)
-                  r
-                  (OperandSize.Size32)))
-
-;;;; Helpers for Emitting Loads ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Load a value into a register.
-(decl x64_load (Type SyntheticAmode ExtKind) Reg)
-
-(rule (x64_load (fits_in_32 ty) addr (ExtKind.SignExtend))
-      (movsx ty
-             (ext_mode (ty_bytes ty) 8)
-             addr))
-
-(rule (x64_load $I64 addr _ext_kind)
-      (let ((dst WritableGpr (temp_writable_gpr))
-            (_ Unit (emit (MInst.Mov64MR addr dst))))
-        dst))
-
-(rule (x64_load $F32 addr _ext_kind)
-      (xmm_unary_rm_r (SseOpcode.Movss)
-                      addr))
-
-(rule (x64_load $F64 addr _ext_kind)
-      (xmm_unary_rm_r (SseOpcode.Movsd)
-                      addr))
-
-(rule (x64_load $F32X4 addr _ext_kind)
-      (xmm_unary_rm_r (SseOpcode.Movups)
-                      addr))
-
-(rule (x64_load $F64X2 addr _ext_kind)
-      (xmm_unary_rm_r (SseOpcode.Movupd)
-                      addr))
-
-(rule (x64_load (multi_lane _bits _lanes) addr _ext_kind)
-      (xmm_unary_rm_r (SseOpcode.Movdqu)
-                      addr))
-
-;; Load a constant into an XMM register.
-(decl xmm_load_const (Type VCodeConstant) Xmm)
-(rule (xmm_load_const ty const)
-      (let ((dst WritableXmm (temp_writable_xmm))
-            (_ Unit (emit (MInst.XmmLoadConst const dst ty))))
-        dst))
-
-;;;; Instruction Constructors ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; These constructors create SSA-style `MInst`s. It is their responsibility to
-;; maintain the invariant that each temporary register they allocate and define
-;; only gets defined the once.
-
-;; Helper for emitting `MInst.AluRmiR` instructions.
-(decl alu_rmi_r (Type AluRmiROpcode Gpr GprMemImm) Gpr)
-(rule (alu_rmi_r ty opcode src1 src2)
-      (let ((dst WritableGpr (temp_writable_gpr))
-            (size OperandSize (operand_size_of_type_32_64 ty))
-            (_ Unit (emit (MInst.AluRmiR size opcode src1 src2 dst))))
-        dst))
-
-;; Helper for emitting `add` instructions.
-(decl add (Type Gpr GprMemImm) Gpr)
-(rule (add ty src1 src2)
-      (alu_rmi_r ty
-                 (AluRmiROpcode.Add)
-                 src1
-                 src2))
-
-;; Helper for creating `add` instructions whose flags are also used.
-(decl add_with_flags_paired (Type Gpr GprMemImm) ProducesFlags)
-(rule (add_with_flags_paired ty src1 src2)
-      (let ((dst WritableGpr (temp_writable_gpr)))
-        (ProducesFlags.ProducesFlagsReturnsResultWithConsumer
-         (MInst.AluRmiR (operand_size_of_type_32_64 ty)
-                        (AluRmiROpcode.Add)
-                        src1
-                        src2
-                        dst)
-         dst)))
-
-;; Helper for creating `adc` instructions.
-(decl adc_paired (Type Gpr GprMemImm) ConsumesFlags)
-(rule (adc_paired ty src1 src2)
-      (let ((dst WritableGpr (temp_writable_gpr)))
-        (ConsumesFlags.ConsumesFlagsReturnsResultWithProducer
-         (MInst.AluRmiR (operand_size_of_type_32_64 ty)
-                        (AluRmiROpcode.Adc)
-                        src1
-                        src2
-                        dst)
-         dst)))
-
-;; Helper for emitting `sub` instructions.
-(decl sub (Type Gpr GprMemImm) Gpr)
-(rule (sub ty src1 src2)
-      (alu_rmi_r ty
-                 (AluRmiROpcode.Sub)
-                 src1
-                 src2))
-
-;; Helper for creating `sub` instructions whose flags are also used.
-(decl sub_with_flags_paired (Type Gpr GprMemImm) ProducesFlags)
-(rule (sub_with_flags_paired ty src1 src2)
-      (let ((dst WritableGpr (temp_writable_gpr)))
-        (ProducesFlags.ProducesFlagsReturnsResultWithConsumer
-         (MInst.AluRmiR (operand_size_of_type_32_64 ty)
-                        (AluRmiROpcode.Sub)
-                        src1
-                        src2
-                        dst)
-         dst)))
-
-;; Helper for creating `sbb` instructions.
-(decl sbb_paired (Type Gpr GprMemImm) ConsumesFlags)
-(rule (sbb_paired ty src1 src2)
-      (let ((dst WritableGpr (temp_writable_gpr)))
-        (ConsumesFlags.ConsumesFlagsReturnsResultWithProducer
-         (MInst.AluRmiR (operand_size_of_type_32_64 ty)
-                        (AluRmiROpcode.Sbb)
-                        src1
-                        src2
-                        dst)
-         dst)))
-
-;; Helper for creating `mul` instructions.
-(decl mul (Type Gpr GprMemImm) Gpr)
-(rule (mul ty src1 src2)
-      (alu_rmi_r ty
-                 (AluRmiROpcode.Mul)
-                 src1
-                 src2))
-
-;; Helper for emitting `and` instructions.
-(decl x64_and (Type Gpr GprMemImm) Gpr)
-(rule (x64_and ty src1 src2)
-      (alu_rmi_r ty
-                 (AluRmiROpcode.And)
-                 src1
-                 src2))
-
-;; Helper for emitting `or` instructions.
-(decl or (Type Gpr GprMemImm) Gpr)
-(rule (or ty src1 src2)
-      (alu_rmi_r ty
-                 (AluRmiROpcode.Or)
-                 src1
-                 src2))
-
-;; Helper for emitting `xor` instructions.
-(decl xor (Type Gpr GprMemImm) Gpr)
-(rule (xor ty src1 src2)
-      (alu_rmi_r ty
-                 (AluRmiROpcode.Xor)
-                 src1
-                 src2))
-
-;; Helper for emitting immediates.
-(decl imm (Type u64) Reg)
-
-;; Integer immediates.
-(rule (imm (fits_in_64 ty) simm64)
-      (let ((dst WritableGpr (temp_writable_gpr))
-            (size OperandSize (operand_size_of_type_32_64 ty))
-            (_ Unit (emit (MInst.Imm size simm64 dst))))
-        dst))
-
-;; `f32` immediates.
-(rule (imm $F32 bits)
-      (gpr_to_xmm (SseOpcode.Movd)
-                  (imm $I32 bits)
-                  (OperandSize.Size32)))
-
-;; `f64` immediates.
-(rule (imm $F64 bits)
-      (gpr_to_xmm (SseOpcode.Movq)
-                  (imm $I64 bits)
-                  (OperandSize.Size64)))
-
-;; Helper for emitting immediates with an `i64` value. Note that
-;; integer constants in ISLE are always parsed as `i64`s; this enables
-;; negative numbers to be used as immediates.
-(decl imm_i64 (Type i64) Reg)
-(rule (imm_i64 ty value)
-      (imm ty (i64_as_u64 value)))
-
-(decl nonzero_u64_fits_in_u32 (u64) u64)
-(extern extractor nonzero_u64_fits_in_u32 nonzero_u64_fits_in_u32)
-
-;; Special case for when a 64-bit immediate fits into 32-bits. We can use a
-;; 32-bit move that zero-extends the value, which has a smaller encoding.
-(rule (imm $I64 (nonzero_u64_fits_in_u32 x))
-      (let ((dst WritableGpr (temp_writable_gpr))
-            (_ Unit (emit (MInst.Imm (OperandSize.Size32) x dst))))
-        dst))
-
-;; Special case for integer zero immediates: turn them into an `xor r, r`.
-(rule (imm (fits_in_64 ty) 0)
-      (let ((wgpr WritableGpr (temp_writable_gpr))
-            (g Gpr wgpr)
-            (size OperandSize (operand_size_of_type_32_64 ty))
-            (_ Unit (emit (MInst.AluRmiR size
-                                         (AluRmiROpcode.Xor)
-                                         g
-                                         g
-                                         wgpr))))
-        (gpr_to_reg g)))
-
-;; Special case for zero immediates with vector types, they turn into an xor
-;; specific to the vector type.
-(rule (imm ty @ (multi_lane _bits _lanes) 0)
-      (let ((wr WritableXmm (temp_writable_xmm))
-            (r Xmm wr)
-            (_ Unit (emit (MInst.XmmRmR (sse_xor_op ty)
-                                        r
-                                        r
-                                        wr))))
-        (xmm_to_reg r)))
-
-;; Special case for `f32` zero immediates to use `xorps`.
-(rule (imm $F32 0)
-      (let ((wr WritableXmm (temp_writable_xmm))
-            (r Xmm wr)
-            (_ Unit (emit (MInst.XmmRmR (SseOpcode.Xorps)
-                                        r
-                                        r
-                                        wr))))
-        (xmm_to_reg r)))
-
-;; TODO: use cmpeqps for all 1s
-
-;; Special case for `f64` zero immediates to use `xorpd`.
-(rule (imm $F64 0)
-      (let ((wr WritableXmm (temp_writable_xmm))
-            (r Xmm wr)
-            (_ Unit (emit (MInst.XmmRmR (SseOpcode.Xorpd)
-                                        r
-                                        r
-                                        wr))))
-        (xmm_to_reg r)))
-
-;; TODO: use cmpeqpd for all 1s
-
-;; Helper for creating `MInst.ShifR` instructions.
-(decl shift_r (Type ShiftKind Gpr Imm8Gpr) Gpr)
-(rule (shift_r ty kind src1 src2)
-      (let ((dst WritableGpr (temp_writable_gpr))
-            ;; Use actual 8/16-bit instructions when appropriate: we
-            ;; rely on their shift-amount-masking semantics.
-            (size OperandSize (raw_operand_size_of_type ty))
-            (_ Unit (emit (MInst.ShiftR size kind src1 src2 dst))))
-        dst))
-
-;; Helper for creating `rotl` instructions.
-(decl x64_rotl (Type Gpr Imm8Gpr) Gpr)
-(rule (x64_rotl ty src1 src2)
-      (shift_r ty (ShiftKind.RotateLeft) src1 src2))
-
-;; Helper for creating `rotr` instructions.
-(decl x64_rotr (Type Gpr Imm8Gpr) Gpr)
-(rule (x64_rotr ty src1 src2)
-      (shift_r ty (ShiftKind.RotateRight) src1 src2))
-
-;; Helper for creating `shl` instructions.
-(decl shl (Type Gpr Imm8Gpr) Gpr)
-(rule (shl ty src1 src2)
-      (shift_r ty (ShiftKind.ShiftLeft) src1 src2))
-
-;; Helper for creating logical shift-right instructions.
-(decl shr (Type Gpr Imm8Gpr) Gpr)
-(rule (shr ty src1 src2)
-      (shift_r ty (ShiftKind.ShiftRightLogical) src1 src2))
-
-;; Helper for creating arithmetic shift-right instructions.
-(decl sar (Type Gpr Imm8Gpr) Gpr)
-(rule (sar ty src1 src2)
-      (shift_r ty (ShiftKind.ShiftRightArithmetic) src1 src2))
-
-;; Helper for creating `MInst.CmpRmiR` instructions.
-(decl cmp_rmi_r (OperandSize CmpOpcode GprMemImm Gpr) ProducesFlags)
-(rule (cmp_rmi_r size opcode src1 src2)
-      (ProducesFlags.ProducesFlagsSideEffect
-       (MInst.CmpRmiR size
-                      opcode
-                      src1
-                      src2)))
-
-;; Helper for creating `cmp` instructions.
-(decl cmp (OperandSize GprMemImm Gpr) ProducesFlags)
-(rule (cmp size src1 src2)
-      (cmp_rmi_r size (CmpOpcode.Cmp) src1 src2))
-
-;; Helper for creating `cmp` instructions with an immediate.
-(decl cmp_imm (OperandSize u32 Gpr) ProducesFlags)
-(rule (cmp_imm size src1 src2)
-      (cmp_rmi_r size (CmpOpcode.Cmp) (RegMemImm.Imm src1) src2))
-
-;; Helper for creating `MInst.XmmCmpRmR` instructions.
-(decl xmm_cmp_rm_r (SseOpcode XmmMem Xmm) ProducesFlags)
-(rule (xmm_cmp_rm_r opcode src1 src2)
-      (ProducesFlags.ProducesFlagsSideEffect
-       (MInst.XmmCmpRmR opcode src1 src2)))
-
-;; Helper for creating `fpcmp` instructions (cannot use `fcmp` as it is taken by
-;; `clif.isle`).
-(decl fpcmp (Value Value) ProducesFlags)
-(rule (fpcmp src1 @ (value_type $F32) src2)
-      (xmm_cmp_rm_r (SseOpcode.Ucomiss) (put_in_xmm_mem src1) (put_in_xmm src2)))
-(rule (fpcmp src1 @ (value_type $F64) src2)
-      (xmm_cmp_rm_r (SseOpcode.Ucomisd) (put_in_xmm_mem src1) (put_in_xmm src2)))
-
-;; Helper for creating `test` instructions.
-(decl test (OperandSize GprMemImm Gpr) ProducesFlags)
-(rule (test size src1 src2)
-      (cmp_rmi_r size (CmpOpcode.Test) src1 src2))
-
-;; Helper for creating `cmove` instructions. Note that these instructions do not
-;; always result in a single emitted x86 instruction; e.g., XmmCmove uses jumps
-;; to conditionally move the selected value into an XMM register.
-(decl cmove (Type CC GprMem Gpr) ConsumesFlags)
-(rule (cmove ty cc consequent alternative)
-      (let ((dst WritableGpr (temp_writable_gpr))
-            (size OperandSize (operand_size_of_type_32_64 ty)))
-        (ConsumesFlags.ConsumesFlagsReturnsReg
-         (MInst.Cmove size cc consequent alternative dst)
-         dst)))
-
-(decl cmove_xmm (Type CC XmmMem Xmm) ConsumesFlags)
-(rule (cmove_xmm ty cc consequent alternative)
-      (let ((dst WritableXmm (temp_writable_xmm))
-            (size OperandSize (operand_size_of_type_32_64 ty)))
-        (ConsumesFlags.ConsumesFlagsReturnsReg
-         (MInst.XmmCmove size cc consequent alternative dst)
-         dst)))
-
-;; Helper for creating `cmove` instructions directly from values. This allows us
-;; to special-case the `I128` types and default to the `cmove` helper otherwise.
-;; It also eliminates some `put_in_reg*` boilerplate in the lowering ISLE code.
-(decl cmove_from_values (Type CC Value Value) ConsumesFlags)
-(rule (cmove_from_values $I128 cc consequent alternative)
-      (let ((cons ValueRegs consequent)
-            (alt ValueRegs alternative)
-            (dst1 WritableGpr (temp_writable_gpr))
-            (dst2 WritableGpr (temp_writable_gpr))
-            (size OperandSize (OperandSize.Size64))
-            (lower_cmove MInst (MInst.Cmove
-                                size cc
-                                (value_regs_get_gpr cons 0)
-                                (value_regs_get_gpr alt 0)
-                                dst1))
-            (upper_cmove MInst (MInst.Cmove
-                                size cc
-                                (value_regs_get_gpr cons 1)
-                                (value_regs_get_gpr alt 1)
-                                dst2)))
-        (ConsumesFlags.ConsumesFlagsTwiceReturnsValueRegs
-         lower_cmove
-         upper_cmove
-         (value_regs dst1 dst2))))
-
-(rule (cmove_from_values (is_gpr_type (is_single_register_type ty)) cc consequent alternative)
-      (cmove ty cc consequent alternative))
-
-(rule (cmove_from_values (is_xmm_type (is_single_register_type ty)) cc consequent alternative)
-      (cmove_xmm ty cc consequent alternative))
-
-;; Helper for creating `cmove` instructions with the logical OR of multiple
-;; flags. Note that these instructions will always result in more than one
-;; emitted x86 instruction.
-(decl cmove_or (Type CC CC GprMem Gpr) ConsumesFlags)
-(rule (cmove_or ty cc1 cc2 consequent alternative)
-      (let ((dst WritableGpr (temp_writable_gpr))
-            (tmp WritableGpr (temp_writable_gpr))
-            (size OperandSize (operand_size_of_type_32_64 ty))
-            (cmove1 MInst (MInst.Cmove size cc1 consequent alternative tmp))
-            (cmove2 MInst (MInst.Cmove size cc2 consequent tmp dst)))
-        (ConsumesFlags.ConsumesFlagsTwiceReturnsValueRegs
-         cmove1
-         cmove2
-         dst)))
-
-(decl cmove_or_xmm (Type CC CC XmmMem Xmm) ConsumesFlags)
-(rule (cmove_or_xmm ty cc1 cc2 consequent alternative)
-      (let ((dst WritableXmm (temp_writable_xmm))
-            (tmp WritableXmm (temp_writable_xmm))
-            (size OperandSize (operand_size_of_type_32_64 ty))
-            (cmove1 MInst (MInst.XmmCmove size cc1 consequent alternative tmp))
-            (cmove2 MInst (MInst.XmmCmove size cc2 consequent tmp dst)))
-        (ConsumesFlags.ConsumesFlagsTwiceReturnsValueRegs
-         cmove1
-         cmove2
-         dst)))
-
-;; Helper for creating `cmove_or` instructions directly from values. This allows
-;; us to special-case the `I128` types and default to the `cmove_or` helper
-;; otherwise.
-(decl cmove_or_from_values (Type CC CC Value Value) ConsumesFlags)
-(rule (cmove_or_from_values $I128 cc1 cc2 consequent alternative)
-      (let ((cons ValueRegs consequent)
-            (alt ValueRegs alternative)
-            (dst1 WritableGpr (temp_writable_gpr))
-            (dst2 WritableGpr (temp_writable_gpr))
-            (tmp1 WritableGpr (temp_writable_gpr))
-            (tmp2 WritableGpr (temp_writable_gpr))
-            (size OperandSize (OperandSize.Size64))
-            (cmove1 MInst (MInst.Cmove size cc1 (value_regs_get_gpr cons 0) (value_regs_get_gpr alt 0) tmp1))
-            (cmove2 MInst (MInst.Cmove size cc1 (value_regs_get_gpr cons 0) tmp1 dst1))
-            (cmove3 MInst (MInst.Cmove size cc1 (value_regs_get_gpr cons 1) (value_regs_get_gpr alt 1) tmp2))
-            (cmove4 MInst (MInst.Cmove size cc1 (value_regs_get_gpr cons 1) tmp2 dst2)))
-        (ConsumesFlags.ConsumesFlagsFourTimesReturnsValueRegs
-         cmove1
-         cmove2
-         cmove3
-         cmove4
-         (value_regs dst1 dst2))))
-
-(rule (cmove_or_from_values (is_gpr_type (is_single_register_type ty)) cc1 cc2 consequent alternative)
-      (cmove_or ty cc1 cc2 consequent alternative))
-
-(rule (cmove_or_from_values (is_xmm_type (is_single_register_type ty)) cc1 cc2 consequent alternative)
-      (cmove_or_xmm ty cc1 cc2 consequent alternative))
-
-;; Helper for creating `MInst.Setcc` instructions.
-(decl setcc (CC) ConsumesFlags)
-(rule (setcc cc)
-      (let ((dst WritableGpr (temp_writable_gpr)))
-        (ConsumesFlags.ConsumesFlagsReturnsReg
-         (MInst.Setcc cc dst)
-         dst)))
-
-;; Helper for creating `MInst.MovzxRmR` instructions.
-(decl movzx (Type ExtMode GprMem) Gpr)
-(rule (movzx ty mode src)
-      (let ((dst WritableGpr (temp_writable_gpr))
-            (_ Unit (emit (MInst.MovzxRmR mode src dst))))
-        dst))
-
-;; Helper for creating `MInst.MovsxRmR` instructions.
-(decl movsx (Type ExtMode GprMem) Gpr)
-(rule (movsx ty mode src)
-      (let ((dst WritableGpr (temp_writable_gpr))
-            (_ Unit (emit (MInst.MovsxRmR mode src dst))))
-        dst))
-
-;; Helper for creating `MInst.XmmRmR` instructions.
-(decl xmm_rm_r (Type SseOpcode Xmm XmmMem) Xmm)
-(rule (xmm_rm_r ty op src1 src2)
-      (let ((dst WritableXmm (temp_writable_xmm))
-            (_ Unit (emit (MInst.XmmRmR op src1 src2 dst))))
-        dst))
-
-;; Helper for creating `paddb` instructions.
-(decl paddb (Xmm XmmMem) Xmm)
-(rule (paddb src1 src2)
-      (xmm_rm_r $I8X16 (SseOpcode.Paddb) src1 src2))
-
-;; Helper for creating `paddw` instructions.
-(decl paddw (Xmm XmmMem) Xmm)
-(rule (paddw src1 src2)
-      (xmm_rm_r $I16X8 (SseOpcode.Paddw) src1 src2))
-
-;; Helper for creating `paddd` instructions.
-(decl paddd (Xmm XmmMem) Xmm)
-(rule (paddd src1 src2)
-      (xmm_rm_r $I32X4 (SseOpcode.Paddd) src1 src2))
-
-;; Helper for creating `paddq` instructions.
-(decl paddq (Xmm XmmMem) Xmm)
-(rule (paddq src1 src2)
-      (xmm_rm_r $I64X2 (SseOpcode.Paddq) src1 src2))
-
-;; Helper for creating `paddsb` instructions.
-(decl paddsb (Xmm XmmMem) Xmm)
-(rule (paddsb src1 src2)
-      (xmm_rm_r $I8X16 (SseOpcode.Paddsb) src1 src2))
-
-;; Helper for creating `paddsw` instructions.
-(decl paddsw (Xmm XmmMem) Xmm)
-(rule (paddsw src1 src2)
-      (xmm_rm_r $I16X8 (SseOpcode.Paddsw) src1 src2))
-
-;; Helper for creating `paddusb` instructions.
-(decl paddusb (Xmm XmmMem) Xmm)
-(rule (paddusb src1 src2)
-      (xmm_rm_r $I8X16 (SseOpcode.Paddusb) src1 src2))
-
-;; Helper for creating `paddusw` instructions.
-(decl paddusw (Xmm XmmMem) Xmm)
-(rule (paddusw src1 src2)
-      (xmm_rm_r $I16X8 (SseOpcode.Paddusw) src1 src2))
-
-;; Helper for creating `psubb` instructions.
-(decl psubb (Xmm XmmMem) Xmm)
-(rule (psubb src1 src2)
-      (xmm_rm_r $I8X16 (SseOpcode.Psubb) src1 src2))
-
-;; Helper for creating `psubw` instructions.
-(decl psubw (Xmm XmmMem) Xmm)
-(rule (psubw src1 src2)
-      (xmm_rm_r $I16X8 (SseOpcode.Psubw) src1 src2))
-
-;; Helper for creating `psubd` instructions.
-(decl psubd (Xmm XmmMem) Xmm)
-(rule (psubd src1 src2)
-      (xmm_rm_r $I32X4 (SseOpcode.Psubd) src1 src2))
-
-;; Helper for creating `psubq` instructions.
-(decl psubq (Xmm XmmMem) Xmm)
-(rule (psubq src1 src2)
-      (xmm_rm_r $I64X2 (SseOpcode.Psubq) src1 src2))
-
-;; Helper for creating `psubsb` instructions.
-(decl psubsb (Xmm XmmMem) Xmm)
-(rule (psubsb src1 src2)
-      (xmm_rm_r $I8X16 (SseOpcode.Psubsb) src1 src2))
-
-;; Helper for creating `psubsw` instructions.
-(decl psubsw (Xmm XmmMem) Xmm)
-(rule (psubsw src1 src2)
-      (xmm_rm_r $I16X8 (SseOpcode.Psubsw) src1 src2))
-
-;; Helper for creating `psubusb` instructions.
-(decl psubusb (Xmm XmmMem) Xmm)
-(rule (psubusb src1 src2)
-      (xmm_rm_r $I8X16 (SseOpcode.Psubusb) src1 src2))
-
-;; Helper for creating `psubusw` instructions.
-(decl psubusw (Xmm XmmMem) Xmm)
-(rule (psubusw src1 src2)
-      (xmm_rm_r $I16X8 (SseOpcode.Psubusw) src1 src2))
-
-;; Helper for creating `pavgb` instructions.
-(decl pavgb (Xmm XmmMem) Xmm)
-(rule (pavgb src1 src2)
-      (xmm_rm_r $I8X16 (SseOpcode.Pavgb) src1 src2))
-
-;; Helper for creating `pavgw` instructions.
-(decl pavgw (Xmm XmmMem) Xmm)
-(rule (pavgw src1 src2)
-      (xmm_rm_r $I16X8 (SseOpcode.Pavgw) src1 src2))
-
-;; Helper for creating `pand` instructions.
-(decl pand (Xmm XmmMem) Xmm)
-(rule (pand src1 src2)
-      (xmm_rm_r $F32X4 (SseOpcode.Pand) src1 src2))
-
-;; Helper for creating `andps` instructions.
-(decl andps (Xmm XmmMem) Xmm)
-(rule (andps src1 src2)
-      (xmm_rm_r $F32X4 (SseOpcode.Andps) src1 src2))
-
-;; Helper for creating `andpd` instructions.
-(decl andpd (Xmm XmmMem) Xmm)
-(rule (andpd src1 src2)
-      (xmm_rm_r $F64X2 (SseOpcode.Andpd) src1 src2))
-
-;; Helper for creating `por` instructions.
-(decl por (Xmm XmmMem) Xmm)
-(rule (por src1 src2)
-      (xmm_rm_r $F32X4 (SseOpcode.Por) src1 src2))
-
-;; Helper for creating `orps` instructions.
-(decl orps (Xmm XmmMem) Xmm)
-(rule (orps src1 src2)
-      (xmm_rm_r $F32X4 (SseOpcode.Orps) src1 src2))
-
-;; Helper for creating `orpd` instructions.
-(decl orpd (Xmm XmmMem) Xmm)
-(rule (orpd src1 src2)
-      (xmm_rm_r $F64X2 (SseOpcode.Orpd) src1 src2))
-
-;; Helper for creating `pxor` instructions.
-(decl pxor (Xmm XmmMem) Xmm)
-(rule (pxor src1 src2)
-      (xmm_rm_r $I8X16 (SseOpcode.Pxor) src1 src2))
-
-;; Helper for creating `xorps` instructions.
-(decl xorps (Xmm XmmMem) Xmm)
-(rule (xorps src1 src2)
-      (xmm_rm_r $F32X4 (SseOpcode.Xorps) src1 src2))
-
-;; Helper for creating `xorpd` instructions.
-(decl xorpd (Xmm XmmMem) Xmm)
-(rule (xorpd src1 src2)
-      (xmm_rm_r $F64X2 (SseOpcode.Xorpd) src1 src2))
-
-;; Helper for creating `pmullw` instructions.
-(decl pmullw (Xmm XmmMem) Xmm)
-(rule (pmullw src1 src2)
-      (xmm_rm_r $I16X8 (SseOpcode.Pmullw) src1 src2))
-
-;; Helper for creating `pmulld` instructions.
-(decl pmulld (Xmm XmmMem) Xmm)
-(rule (pmulld src1 src2)
-      (xmm_rm_r $I16X8 (SseOpcode.Pmulld) src1 src2))
-
-;; Helper for creating `pmulhw` instructions.
-(decl pmulhw (Xmm XmmMem) Xmm)
-(rule (pmulhw src1 src2)
-      (xmm_rm_r $I16X8 (SseOpcode.Pmulhw) src1 src2))
-
-;; Helper for creating `pmulhuw` instructions.
-(decl pmulhuw (Xmm XmmMem) Xmm)
-(rule (pmulhuw src1 src2)
-      (xmm_rm_r $I16X8 (SseOpcode.Pmulhuw) src1 src2))
-
-;; Helper for creating `pmuldq` instructions.
-(decl pmuldq (Xmm XmmMem) Xmm)
-(rule (pmuldq src1 src2)
-      (xmm_rm_r $I16X8 (SseOpcode.Pmuldq) src1 src2))
-
-;; Helper for creating `pmuludq` instructions.
-(decl pmuludq (Xmm XmmMem) Xmm)
-(rule (pmuludq src1 src2)
-      (xmm_rm_r $I64X2 (SseOpcode.Pmuludq) src1 src2))
-
-;; Helper for creating `punpckhwd` instructions.
-(decl punpckhwd (Xmm XmmMem) Xmm)
-(rule (punpckhwd src1 src2)
-      (xmm_rm_r $I16X8 (SseOpcode.Punpckhwd) src1 src2))
-
-;; Helper for creating `punpcklwd` instructions.
-(decl punpcklwd (Xmm XmmMem) Xmm)
-(rule (punpcklwd src1 src2)
-      (xmm_rm_r $I16X8 (SseOpcode.Punpcklwd) src1 src2))
-
-;; Helper for creating `andnps` instructions.
-(decl andnps (Xmm XmmMem) Xmm)
-(rule (andnps src1 src2)
-      (xmm_rm_r $F32X4 (SseOpcode.Andnps) src1 src2))
-
-;; Helper for creating `andnpd` instructions.
-(decl andnpd (Xmm XmmMem) Xmm)
-(rule (andnpd src1 src2)
-      (xmm_rm_r $F64X2 (SseOpcode.Andnpd) src1 src2))
-
-;; Helper for creating `pandn` instructions.
-(decl pandn (Xmm XmmMem) Xmm)
-(rule (pandn src1 src2)
-      (xmm_rm_r $F64X2 (SseOpcode.Pandn) src1 src2))
-
-;; Helper for creating `addss` instructions.
-(decl addss (Xmm XmmMem) Xmm)
-(rule (addss src1 src2)
-      (xmm_rm_r $F32 (SseOpcode.Addss) src1 src2))
-
-;; Helper for creating `addsd` instructions.
-(decl addsd (Xmm XmmMem) Xmm)
-(rule (addsd src1 src2)
-      (xmm_rm_r $F64 (SseOpcode.Addsd) src1 src2))
-
-;; Helper for creating `addps` instructions.
-(decl addps (Xmm XmmMem) Xmm)
-(rule (addps src1 src2)
-      (xmm_rm_r $F32 (SseOpcode.Addps) src1 src2))
-
-;; Helper for creating `addpd` instructions.
-(decl addpd (Xmm XmmMem) Xmm)
-(rule (addpd src1 src2)
-      (xmm_rm_r $F32 (SseOpcode.Addpd) src1 src2))
-
-;; Helper for creating `subss` instructions.
-(decl subss (Xmm XmmMem) Xmm)
-(rule (subss src1 src2)
-      (xmm_rm_r $F32 (SseOpcode.Subss) src1 src2))
-
-;; Helper for creating `subsd` instructions.
-(decl subsd (Xmm XmmMem) Xmm)
-(rule (subsd src1 src2)
-      (xmm_rm_r $F64 (SseOpcode.Subsd) src1 src2))
-
-;; Helper for creating `subps` instructions.
-(decl subps (Xmm XmmMem) Xmm)
-(rule (subps src1 src2)
-      (xmm_rm_r $F32 (SseOpcode.Subps) src1 src2))
-
-;; Helper for creating `subpd` instructions.
-(decl subpd (Xmm XmmMem) Xmm)
-(rule (subpd src1 src2)
-      (xmm_rm_r $F32 (SseOpcode.Subpd) src1 src2))
-
-;; Helper for creating `mulss` instructions.
-(decl mulss (Xmm XmmMem) Xmm)
-(rule (mulss src1 src2)
-      (xmm_rm_r $F32 (SseOpcode.Mulss) src1 src2))
-
-;; Helper for creating `mulsd` instructions.
-(decl mulsd (Xmm XmmMem) Xmm)
-(rule (mulsd src1 src2)
-      (xmm_rm_r $F64 (SseOpcode.Mulsd) src1 src2))
-
-;; Helper for creating `mulps` instructions.
-(decl mulps (Xmm XmmMem) Xmm)
-(rule (mulps src1 src2)
-      (xmm_rm_r $F32 (SseOpcode.Mulps) src1 src2))
-
-;; Helper for creating `mulpd` instructions.
-(decl mulpd (Xmm XmmMem) Xmm)
-(rule (mulpd src1 src2)
-      (xmm_rm_r $F32 (SseOpcode.Mulpd) src1 src2))
-
-;; Helper for creating `divss` instructions.
-(decl divss (Xmm XmmMem) Xmm)
-(rule (divss src1 src2)
-      (xmm_rm_r $F32 (SseOpcode.Divss) src1 src2))
-
-;; Helper for creating `divsd` instructions.
-(decl divsd (Xmm XmmMem) Xmm)
-(rule (divsd src1 src2)
-      (xmm_rm_r $F64 (SseOpcode.Divsd) src1 src2))
-
-;; Helper for creating `divps` instructions.
-(decl divps (Xmm XmmMem) Xmm)
-(rule (divps src1 src2)
-      (xmm_rm_r $F32 (SseOpcode.Divps) src1 src2))
-
-;; Helper for creating `divpd` instructions.
-(decl divpd (Xmm XmmMem) Xmm)
-(rule (divpd src1 src2)
-      (xmm_rm_r $F32 (SseOpcode.Divpd) src1 src2))
-
-(decl sse_blend_op (Type) SseOpcode)
-(rule (sse_blend_op $F32X4) (SseOpcode.Blendvps))
-(rule (sse_blend_op $F64X2) (SseOpcode.Blendvpd))
-(rule (sse_blend_op (multi_lane _bits _lanes)) (SseOpcode.Pblendvb))
-
-(decl sse_mov_op (Type) SseOpcode)
-(rule (sse_mov_op $F32X4) (SseOpcode.Movaps))
-(rule (sse_mov_op $F64X2) (SseOpcode.Movapd))
-(rule (sse_mov_op (multi_lane _bits _lanes)) (SseOpcode.Movdqa))
-
-;; Helper for creating `blendvp{d,s}` and `pblendvb` instructions.
-(decl sse_blend (Type XmmMem XmmMem Xmm) Xmm)
-(rule (sse_blend ty mask src1 src2)
-      ;; Move the mask into `xmm0`, as blend instructions implicitly operate on
-      ;; that register. (This kind of thing would normally happen inside of
-      ;; `Inst::mov_mitosis`, but has to happen here, where we still have the
-      ;; mask register, because the mask is implicit and doesn't appear in the
-      ;; `Inst` itself.)
-      (let ((mask2 WritableXmm (xmm0))
-            (_ Unit (emit (MInst.XmmUnaryRmR (sse_mov_op ty)
-                                             mask
-                                             mask2))))
-        (xmm_rm_r ty (sse_blend_op ty) src2 src1)))
-
-;; Helper for creating `blendvpd` instructions.
-(decl blendvpd (Xmm XmmMem Xmm) Xmm)
-(rule (blendvpd src1 src2 mask)
-      ;; Move the mask into `xmm0`, as `blendvpd` implicitly operates on that
-      ;; register. (This kind of thing would normally happen inside of
-      ;; `Inst::mov_mitosis`, but has to happen here, where we still have the
-      ;; mask register, because the mask is implicit and doesn't appear in the
-      ;; `Inst` itself.)
-      (let ((mask2 WritableXmm (xmm0))
-            (_ Unit (emit (MInst.XmmUnaryRmR (SseOpcode.Movapd)
-                                             mask
-                                             mask2))))
-        (xmm_rm_r $F64X2 (SseOpcode.Blendvpd) src1 src2)))
-
-;; Helper for creating `movsd` instructions.
-(decl movsd (Xmm XmmMem) Xmm)
-(rule (movsd src1 src2)
-      (xmm_rm_r $I8X16 (SseOpcode.Movsd) src1 src2))
-
-;; Helper for creating `movlhps` instructions.
-(decl movlhps (Xmm XmmMem) Xmm)
-(rule (movlhps src1 src2)
-      (xmm_rm_r $I8X16 (SseOpcode.Movlhps) src1 src2))
-
-;; Helper for creating `pmaxsb` instructions.
-(decl pmaxsb (Xmm XmmMem) Xmm)
-(rule (pmaxsb src1 src2)
-      (xmm_rm_r $I8X16 (SseOpcode.Pmaxsb) src1 src2))
-
-;; Helper for creating `pmaxsw` instructions.
-(decl pmaxsw (Xmm XmmMem) Xmm)
-(rule (pmaxsw src1 src2)
-      (xmm_rm_r $I8X16 (SseOpcode.Pmaxsw) src1 src2))
-
-;; Helper for creating `pmaxsd` instructions.
-(decl pmaxsd (Xmm XmmMem) Xmm)
-(rule (pmaxsd src1 src2)
-      (xmm_rm_r $I8X16 (SseOpcode.Pmaxsd) src1 src2))
-
-;; Helper for creating `pminsb` instructions.
-(decl pminsb (Xmm XmmMem) Xmm)
-(rule (pminsb src1 src2)
-      (xmm_rm_r $I8X16 (SseOpcode.Pminsb) src1 src2))
-
-;; Helper for creating `pminsw` instructions.
-(decl pminsw (Xmm XmmMem) Xmm)
-(rule (pminsw src1 src2)
-      (xmm_rm_r $I8X16 (SseOpcode.Pminsw) src1 src2))
-
-;; Helper for creating `pminsd` instructions.
-(decl pminsd (Xmm XmmMem) Xmm)
-(rule (pminsd src1 src2)
-      (xmm_rm_r $I8X16 (SseOpcode.Pminsd) src1 src2))
-
-;; Helper for creating `pmaxub` instructions.
-(decl pmaxub (Xmm XmmMem) Xmm)
-(rule (pmaxub src1 src2)
-      (xmm_rm_r $I8X16 (SseOpcode.Pmaxub) src1 src2))
-
-;; Helper for creating `pmaxuw` instructions.
-(decl pmaxuw (Xmm XmmMem) Xmm)
-(rule (pmaxuw src1 src2)
-      (xmm_rm_r $I8X16 (SseOpcode.Pmaxuw) src1 src2))
-
-;; Helper for creating `pmaxud` instructions.
-(decl pmaxud (Xmm XmmMem) Xmm)
-(rule (pmaxud src1 src2)
-      (xmm_rm_r $I8X16 (SseOpcode.Pmaxud) src1 src2))
-
-;; Helper for creating `pminub` instructions.
-(decl pminub (Xmm XmmMem) Xmm)
-(rule (pminub src1 src2)
-      (xmm_rm_r $I8X16 (SseOpcode.Pminub) src1 src2))
-
-;; Helper for creating `pminuw` instructions.
-(decl pminuw (Xmm XmmMem) Xmm)
-(rule (pminuw src1 src2)
-      (xmm_rm_r $I8X16 (SseOpcode.Pminuw) src1 src2))
-
-;; Helper for creating `pminud` instructions.
-(decl pminud (Xmm XmmMem) Xmm)
-(rule (pminud src1 src2)
-      (xmm_rm_r $I8X16 (SseOpcode.Pminud) src1 src2))
-
-;; Helper for creating `punpcklbw` instructions.
-(decl punpcklbw (Xmm XmmMem) Xmm)
-(rule (punpcklbw src1 src2)
-      (xmm_rm_r $I8X16 (SseOpcode.Punpcklbw) src1 src2))
-
-;; Helper for creating `punpckhbw` instructions.
-(decl punpckhbw (Xmm XmmMem) Xmm)
-(rule (punpckhbw src1 src2)
-      (xmm_rm_r $I8X16 (SseOpcode.Punpckhbw) src1 src2))
-
-;; Helper for creating `packsswb` instructions.
-(decl packsswb (Xmm XmmMem) Xmm)
-(rule (packsswb src1 src2)
-      (xmm_rm_r $I8X16 (SseOpcode.Packsswb) src1 src2))
-
-;; Helper for creating `MInst.XmmRmRImm` instructions.
-(decl xmm_rm_r_imm (SseOpcode Reg RegMem u8 OperandSize) Xmm)
-(rule (xmm_rm_r_imm op src1 src2 imm size)
-      (let ((dst WritableXmm (temp_writable_xmm))
-            (_ Unit (emit (MInst.XmmRmRImm op
-                                           src1
-                                           src2
-                                           dst
-                                           imm
-                                           size))))
-        dst))
-
-;; Helper for creating `palignr` instructions.
-(decl palignr (Xmm XmmMem u8 OperandSize) Xmm)
-(rule (palignr src1 src2 imm size)
-      (xmm_rm_r_imm (SseOpcode.Palignr)
-                    src1
-                    src2
-                    imm
-                    size))
-
-;; Helper for creating `cmpps` instructions.
-(decl cmpps (Xmm XmmMem FcmpImm) Xmm)
-(rule (cmpps src1 src2 imm)
-      (xmm_rm_r_imm (SseOpcode.Cmpps)
-                    src1
-                    src2
-                    (encode_fcmp_imm imm)
-                    (OperandSize.Size32)))
-
-;; Helper for creating `pinsrb` instructions.
-(decl pinsrb (Xmm GprMem u8) Xmm)
-(rule (pinsrb src1 src2 lane)
-      (xmm_rm_r_imm (SseOpcode.Pinsrb)
-                    src1
-                    src2
-                    lane
-                    (OperandSize.Size32)))
-
-;; Helper for creating `pinsrw` instructions.
-(decl pinsrw (Xmm GprMem u8) Xmm)
-(rule (pinsrw src1 src2 lane)
-      (xmm_rm_r_imm (SseOpcode.Pinsrw)
-                    src1
-                    src2
-                    lane
-                    (OperandSize.Size32)))
-
-;; Helper for creating `pinsrd` instructions.
-(decl pinsrd (Xmm GprMem u8 OperandSize) Xmm)
-(rule (pinsrd src1 src2 lane size)
-      (xmm_rm_r_imm (SseOpcode.Pinsrd)
-                    src1
-                    src2
-                    lane
-                    size))
-
-;; Helper for creating `pmaddwd` instructions.
-(decl pmaddwd (Xmm XmmMem) Xmm)
-(rule (pmaddwd src1 src2)
-      (let ((dst WritableXmm (temp_writable_xmm))
-            (_ Unit (emit (MInst.XmmRmR (SseOpcode.Pmaddwd)
-                                        src1
-                                        src2
-                                        dst))))
-        dst))
-
-;; Helper for creating `insertps` instructions.
-(decl insertps (Xmm XmmMem u8) Xmm)
-(rule (insertps src1 src2 lane)
-      (xmm_rm_r_imm (SseOpcode.Insertps)
-                    src1
-                    src2
-                    lane
-                    (OperandSize.Size32)))
-
-;; Helper for creating `pshufd` instructions.
-(decl pshufd (XmmMem u8 OperandSize) Xmm)
-(rule (pshufd src imm size)
-      (let ((dst WritableXmm (temp_writable_xmm))
-            (_ Unit (emit (MInst.XmmRmRImm (SseOpcode.Pshufd)
-                                           dst
-                                           src
-                                           dst
-                                           imm
-                                           size))))
-        dst))
-
-;; Helper for creating `pshufb` instructions.
-(decl pshufb (Xmm XmmMem) Xmm)
-(rule (pshufb src1 src2)
-      (let ((dst WritableXmm (temp_writable_xmm))
-            (_ Unit (emit (MInst.XmmRmR (SseOpcode.Pshufb)
-                                        src1
-                                        src2
-                                        dst))))
-        dst))
-
-;; Helper for creating `MInst.XmmUnaryRmR` instructions.
-(decl xmm_unary_rm_r (SseOpcode XmmMem) Xmm)
-(rule (xmm_unary_rm_r op src)
-      (let ((dst WritableXmm (temp_writable_xmm))
-            (_ Unit (emit (MInst.XmmUnaryRmR op src dst))))
-        dst))
-
-;; Helper for creating `pmovsxbw` instructions.
-(decl pmovsxbw (XmmMem) Xmm)
-(rule (pmovsxbw src)
-      (xmm_unary_rm_r (SseOpcode.Pmovsxbw) src))
-
-;; Helper for creating `pmovzxbw` instructions.
-(decl pmovzxbw (XmmMem) Xmm)
-(rule (pmovzxbw src)
-      (xmm_unary_rm_r (SseOpcode.Pmovzxbw) src))
-
-;; Helper for creating `pabsb` instructions.
-(decl pabsb (XmmMem) Xmm)
-(rule (pabsb src)
-      (xmm_unary_rm_r (SseOpcode.Pabsb) src))
-
-;; Helper for creating `pabsw` instructions.
-(decl pabsw (XmmMem) Xmm)
-(rule (pabsw src)
-      (xmm_unary_rm_r (SseOpcode.Pabsw) src))
-
-;; Helper for creating `pabsd` instructions.
-(decl pabsd (XmmMem) Xmm)
-(rule (pabsd src)
-      (xmm_unary_rm_r (SseOpcode.Pabsd) src))
-
-;; Helper for creating `MInst.XmmUnaryRmREvex` instructions.
-(decl xmm_unary_rm_r_evex (Avx512Opcode XmmMem) Xmm)
-(rule (xmm_unary_rm_r_evex op src)
-      (let ((dst WritableXmm (temp_writable_xmm))
-            (_ Unit (emit (MInst.XmmUnaryRmREvex op src dst))))
-        dst))
-
-;; Helper for creating `vpabsq` instructions.
-(decl vpabsq (XmmMem) Xmm)
-(rule (vpabsq src)
-      (xmm_unary_rm_r_evex (Avx512Opcode.Vpabsq) src))
-
-;; Helper for creating `vpopcntb` instructions.
-(decl vpopcntb (XmmMem) Xmm)
-(rule (vpopcntb src)
-      (xmm_unary_rm_r_evex (Avx512Opcode.Vpopcntb) src))
-
-;; Helper for creating `MInst.XmmRmREvex` instructions.
-(decl xmm_rm_r_evex (Avx512Opcode XmmMem Xmm) Xmm)
-(rule (xmm_rm_r_evex op src1 src2)
-      (let ((dst WritableXmm (temp_writable_xmm))
-            (_ Unit (emit (MInst.XmmRmREvex op
-                                            src1
-                                            src2
-                                            dst))))
-        dst))
-
-;; Helper for creating `vpmullq` instructions.
-;;
-;; Requires AVX-512 vl and dq.
-(decl vpmullq (XmmMem Xmm) Xmm)
-(rule (vpmullq src1 src2)
-      (xmm_rm_r_evex (Avx512Opcode.Vpmullq)
-                     src1
-                     src2))
-
-;; Helper for creating `MInst.MulHi` instructions.
-;;
-;; Returns the (lo, hi) register halves of the multiplication.
-(decl mul_hi (Type bool Gpr GprMem) ValueRegs)
-(rule (mul_hi ty signed src1 src2)
-      (let ((dst_lo WritableGpr (temp_writable_gpr))
-            (dst_hi WritableGpr (temp_writable_gpr))
-            (size OperandSize (operand_size_of_type_32_64 ty))
-            (_ Unit (emit (MInst.MulHi size
-                                       signed
-                                       src1
-                                       src2
-                                       dst_lo
-                                       dst_hi))))
-        (value_gprs dst_lo dst_hi)))
-
-;; Helper for creating `mul` instructions that return both the lower and
-;; (unsigned) higher halves of the result.
-(decl mulhi_u (Type Gpr GprMem) ValueRegs)
-(rule (mulhi_u ty src1 src2)
-      (mul_hi ty $false src1 src2))
-
-;; Helper for creating `MInst.XmmRmiXmm` instructions.
-(decl xmm_rmi_xmm (SseOpcode Xmm XmmMemImm) Xmm)
-(rule (xmm_rmi_xmm op src1 src2)
-      (let ((dst WritableXmm (temp_writable_xmm))
-            (_ Unit (emit (MInst.XmmRmiReg op
-                                           src1
-                                           src2
-                                           dst))))
-        dst))
-
-;; Helper for creating `psllw` instructions.
-(decl psllw (Xmm XmmMemImm) Xmm)
-(rule (psllw src1 src2)
-      (xmm_rmi_xmm (SseOpcode.Psllw) src1 src2))
-
-;; Helper for creating `pslld` instructions.
-(decl pslld (Xmm XmmMemImm) Xmm)
-(rule (pslld src1 src2)
-      (xmm_rmi_xmm (SseOpcode.Pslld) src1 src2))
-
-;; Helper for creating `psllq` instructions.
-(decl psllq (Xmm XmmMemImm) Xmm)
-(rule (psllq src1 src2)
-      (xmm_rmi_xmm (SseOpcode.Psllq) src1 src2))
-
-;; Helper for creating `psrlw` instructions.
-(decl psrlw (Xmm XmmMemImm) Xmm)
-(rule (psrlw src1 src2)
-      (xmm_rmi_xmm (SseOpcode.Psrlw) src1 src2))
-
-;; Helper for creating `psrld` instructions.
-(decl psrld (Xmm XmmMemImm) Xmm)
-(rule (psrld src1 src2)
-      (xmm_rmi_xmm (SseOpcode.Psrld) src1 src2))
-
-;; Helper for creating `psrlq` instructions.
-(decl psrlq (Xmm XmmMemImm) Xmm)
-(rule (psrlq src1 src2)
-      (xmm_rmi_xmm (SseOpcode.Psrlq) src1 src2))
-
-;; Helper for creating `psraw` instructions.
-(decl psraw (Xmm XmmMemImm) Xmm)
-(rule (psraw src1 src2)
-      (xmm_rmi_xmm (SseOpcode.Psraw) src1 src2))
-
-;; Helper for creating `psrad` instructions.
-(decl psrad (Xmm XmmMemImm) Xmm)
-(rule (psrad src1 src2)
-      (xmm_rmi_xmm (SseOpcode.Psrad) src1 src2))
-
-;; Helper for creating `pextrd` instructions.
-(decl pextrd (Type Xmm u8) Gpr)
-(rule (pextrd ty src lane)
-      (let ((dst WritableGpr (temp_writable_gpr))
-            (_ Unit (emit (MInst.XmmRmRImm (SseOpcode.Pextrd)
-                                           dst
-                                           src
-                                           dst
-                                           lane
-                                           (operand_size_of_type_32_64 (lane_type ty))))))
-        dst))
-
-;; Helper for creating `cmppd` instructions.
-;;
-;; Note that `Size32` is intentional despite this being used for 64-bit
-;; operations, since this presumably induces the correct encoding of the
-;; instruction.
-(decl cmppd (Xmm XmmMem FcmpImm) Xmm)
-(rule (cmppd src1 src2 imm)
-      (xmm_rm_r_imm (SseOpcode.Cmppd)
-                    src1
-                    src2
-                    (encode_fcmp_imm imm)
-                    (OperandSize.Size32)))
-
-;; Helper for creating `MInst.GprToXmm` instructions.
-(decl gpr_to_xmm (SseOpcode GprMem OperandSize) Xmm)
-(rule (gpr_to_xmm op src size)
-      (let ((dst WritableXmm (temp_writable_xmm))
-            (_ Unit (emit (MInst.GprToXmm op src dst size))))
-        dst))
-
-;; Helper for creating `not` instructions.
-(decl not (Type Gpr) Gpr)
-(rule (not ty src)
-      (let ((dst WritableGpr (temp_writable_gpr))
-            (size OperandSize (operand_size_of_type_32_64 ty))
-            (_ Unit (emit (MInst.Not size src dst))))
-        dst))
-
-;; Helper for creating `neg` instructions.
-(decl neg (Type Gpr) Gpr)
-(rule (neg ty src)
-      (let ((dst WritableGpr (temp_writable_gpr))
-            (size OperandSize (operand_size_of_type_32_64 ty))
-            (_ Unit (emit (MInst.Neg size src dst))))
-        dst))
-
-(decl lea (SyntheticAmode) Gpr)
-(rule (lea addr)
-      (let ((dst WritableGpr (temp_writable_gpr))
-            (_ Unit (emit (MInst.LoadEffectiveAddress addr dst))))
-        dst))
-
-;; Helper for creating `ud2` instructions.
-(decl ud2 (TrapCode) SideEffectNoResult)
-(rule (ud2 code)
-      (SideEffectNoResult.Inst (MInst.Ud2 code)))
-
-;; Helper for creating `hlt` instructions.
-(decl hlt () SideEffectNoResult)
-(rule (hlt)
-      (SideEffectNoResult.Inst (MInst.Hlt)))
-
-;; Helper for creating `lzcnt` instructions.
-(decl lzcnt (Type Gpr) Gpr)
-(rule (lzcnt ty src)
-      (let ((dst WritableGpr (temp_writable_gpr))
-            (size OperandSize (operand_size_of_type_32_64 ty))
-            (_ Unit (emit (MInst.UnaryRmR size (UnaryRmROpcode.Lzcnt) src dst))))
-        dst))
-
-;; Helper for creating `tzcnt` instructions.
-(decl tzcnt (Type Gpr) Gpr)
-(rule (tzcnt ty src)
-      (let ((dst WritableGpr (temp_writable_gpr))
-            (size OperandSize (operand_size_of_type_32_64 ty))
-            (_ Unit (emit (MInst.UnaryRmR size (UnaryRmROpcode.Tzcnt) src dst))))
-        dst))
-
-;; Helper for creating `bsr` instructions.
-(decl bsr (Type Gpr) ProducesFlags)
-(rule (bsr ty src)
-      (let ((dst WritableGpr (temp_writable_gpr))
-            (size OperandSize (operand_size_of_type_32_64 ty))
-            (inst MInst (MInst.UnaryRmR size (UnaryRmROpcode.Bsr) src dst)))
-        (ProducesFlags.ProducesFlagsReturnsReg inst dst)))
-
-;; Helper for creating `bsr + cmov` instruction pairs that produce the
-;; result of the `bsr`, or `alt` if the input was zero.
-(decl bsr_or_else (Type Gpr Gpr) Gpr)
-(rule (bsr_or_else ty src alt)
-      (let ((bsr ProducesFlags (bsr ty src))
-            ;; Manually extract the result from the bsr, then ignore
-            ;; it below, since we need to thread it into the cmove
-            ;; before we pass the cmove to with_flags_reg.
-            (bsr_result Gpr (produces_flags_get_reg bsr))
-            (cmove ConsumesFlags (cmove ty (CC.Z) alt bsr_result)))
-        (with_flags_reg (produces_flags_ignore bsr) cmove)))
-
-;; Helper for creating `bsf` instructions.
-(decl bsf (Type Gpr) ProducesFlags)
-(rule (bsf ty src)
-      (let ((dst WritableGpr (temp_writable_gpr))
-            (size OperandSize (operand_size_of_type_32_64 ty))
-            (inst MInst (MInst.UnaryRmR size (UnaryRmROpcode.Bsf) src dst)))
-        (ProducesFlags.ProducesFlagsReturnsReg inst dst)))
-
-;; Helper for creating `bsf + cmov` instruction pairs that produce the
-;; result of the `bsf`, or `alt` if the input was zero.
-(decl bsf_or_else (Type Gpr Gpr) Gpr)
-(rule (bsf_or_else ty src alt)
-      (let ((bsf ProducesFlags (bsf ty src))
-            ;; Manually extract the result from the bsf, then ignore
-            ;; it below, since we need to thread it into the cmove
-            ;; before we pass the cmove to with_flags_reg.
-            (bsf_result Gpr (produces_flags_get_reg bsf))
-            (cmove ConsumesFlags (cmove ty (CC.Z) alt bsf_result)))
-        (with_flags_reg (produces_flags_ignore bsf) cmove)))
-
-;; Helper for creating `popcnt` instructions.
-(decl x64_popcnt (Type Gpr) Gpr)
-(rule (x64_popcnt ty src)
-      (let ((dst WritableGpr (temp_writable_gpr))
-            (size OperandSize (operand_size_of_type_32_64 ty))
-            (_ Unit (emit (MInst.UnaryRmR size (UnaryRmROpcode.Popcnt) src dst))))
-        dst))
-
-;; Helper for creating `xmm_min_max_seq` psuedo-instructions.
-(decl xmm_min_max_seq (Type bool Xmm Xmm) Xmm)
-(rule (xmm_min_max_seq ty is_min lhs rhs)
-      (let ((dst WritableXmm (temp_writable_xmm))
-            (size OperandSize (operand_size_of_type_32_64 ty))
-            (_ Unit (emit (MInst.XmmMinMaxSeq size is_min lhs rhs dst))))
-        dst))
-
-;; Helper for creating `minss` instructions.
-(decl minss (Xmm Xmm) Xmm)
-(rule (minss x y)
-      (let ((dst WritableXmm (temp_writable_xmm))
-            (_ Unit (emit (MInst.XmmRmR (SseOpcode.Minss) x y dst))))
-        dst))
-
-;; Helper for creating `minsd` instructions.
-(decl minsd (Xmm Xmm) Xmm)
-(rule (minsd x y)
-      (let ((dst WritableXmm (temp_writable_xmm))
-            (_ Unit (emit (MInst.XmmRmR (SseOpcode.Minsd) x y dst))))
-        dst))
-
-
-;; Helper for creating `minps` instructions.
-(decl minps (Xmm Xmm) Xmm)
-(rule (minps x y)
-      (let ((dst WritableXmm (temp_writable_xmm))
-            (_ Unit (emit (MInst.XmmRmR (SseOpcode.Minps) x y dst))))
-        dst))
-
-;; Helper for creating `minpd` instructions.
-(decl minpd (Xmm Xmm) Xmm)
-(rule (minpd x y)
-      (let ((dst WritableXmm (temp_writable_xmm))
-            (_ Unit (emit (MInst.XmmRmR (SseOpcode.Minpd) x y dst))))
-        dst))
-
-;; Helper for creating `maxss` instructions.
-(decl maxss (Xmm Xmm) Xmm)
-(rule (maxss x y)
-      (let ((dst WritableXmm (temp_writable_xmm))
-            (_ Unit (emit (MInst.XmmRmR (SseOpcode.Maxss) x y dst))))
-        dst))
-
-;; Helper for creating `maxsd` instructions.
-(decl maxsd (Xmm Xmm) Xmm)
-(rule (maxsd x y)
-      (let ((dst WritableXmm (temp_writable_xmm))
-            (_ Unit (emit (MInst.XmmRmR (SseOpcode.Maxsd) x y dst))))
-        dst))
-
-;; Helper for creating `maxps` instructions.
-(decl maxps (Xmm Xmm) Xmm)
-(rule (maxps x y)
-      (let ((dst WritableXmm (temp_writable_xmm))
-            (_ Unit (emit (MInst.XmmRmR (SseOpcode.Maxps) x y dst))))
-        dst))
-
-;; Helper for creating `maxpd` instructions.
-(decl maxpd (Xmm Xmm) Xmm)
-(rule (maxpd x y)
-      (let ((dst WritableXmm (temp_writable_xmm))
-            (_ Unit (emit (MInst.XmmRmR (SseOpcode.Maxpd) x y dst))))
-        dst))
-
-;;;; Automatic conversions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(convert Gpr InstOutput output_gpr)
-(convert Value Gpr put_in_gpr)
-(convert Value GprMem put_in_gpr_mem)
-(convert Value GprMemImm put_in_gpr_mem_imm)
-(convert Value RegMem put_in_reg_mem)
-(convert Value RegMemImm put_in_reg_mem_imm)
-(convert Gpr GprMemImm gpr_to_gpr_mem_imm)
-(convert Gpr GprMem gpr_to_gpr_mem)
-(convert Gpr Reg gpr_to_reg)
-(convert GprMem RegMem gpr_mem_to_reg_mem)
-(convert Reg Gpr gpr_new)
-(convert WritableGpr Gpr writable_gpr_to_gpr)
-(convert RegMemImm GprMemImm gpr_mem_imm_new)
-(convert RegMem GprMem reg_mem_to_gpr_mem)
-(convert Reg GprMem reg_to_gpr_mem)
-(convert Reg GprMemImm reg_to_gpr_mem_imm)
-(convert WritableGpr WritableReg writable_gpr_to_reg)
-(convert WritableGpr Reg writable_gpr_to_r_reg)
-(convert WritableGpr GprMem writable_gpr_to_gpr_mem)
-(convert WritableGpr ValueRegs writable_gpr_to_value_regs)
-
-(convert Xmm InstOutput output_xmm)
-(convert Value Xmm put_in_xmm)
-(convert Value XmmMem put_in_xmm_mem)
-(convert Value XmmMemImm put_in_xmm_mem_imm)
-(convert Xmm Reg xmm_to_reg)
-(convert Xmm RegMem xmm_to_reg_mem)
-(convert Reg Xmm xmm_new)
-(convert Reg XmmMem reg_to_xmm_mem)
-(convert RegMem XmmMem reg_mem_to_xmm_mem)
-(convert RegMemImm XmmMemImm mov_rmi_to_xmm)
-(convert Xmm XmmMem xmm_to_xmm_mem)
-(convert Xmm XmmMemImm xmm_to_xmm_mem_imm)
-(convert XmmMem RegMem xmm_mem_to_reg_mem)
-(convert WritableXmm Xmm writable_xmm_to_xmm)
-(convert WritableXmm WritableReg writable_xmm_to_reg)
-(convert WritableXmm Reg writable_xmm_to_r_reg)
-(convert WritableXmm XmmMem writable_xmm_to_xmm_mem)
-(convert WritableXmm ValueRegs writable_xmm_to_value_regs)
-
-(convert Gpr Imm8Gpr gpr_to_imm8_gpr)
-(convert Imm8Reg Imm8Gpr imm8_reg_to_imm8_gpr)
-
-(convert Amode SyntheticAmode amode_to_synthetic_amode)
-(convert SyntheticAmode GprMem synthetic_amode_to_gpr_mem)
-(convert SyntheticAmode XmmMem synthetic_amode_to_xmm_mem)
-
-(decl reg_to_xmm_mem (Reg) XmmMem)
-(rule (reg_to_xmm_mem r)
-      (xmm_to_xmm_mem (xmm_new r)))
-(decl xmm_to_reg_mem (Reg) XmmMem)
-(rule (xmm_to_reg_mem r)
-      (RegMem.Reg (xmm_to_reg r)))
-
-(decl writable_gpr_to_r_reg (WritableGpr) Reg)
-(rule (writable_gpr_to_r_reg w_gpr)
-      (writable_reg_to_reg (writable_gpr_to_reg w_gpr)))
-(decl writable_gpr_to_gpr_mem (WritableGpr) GprMem)
-(rule (writable_gpr_to_gpr_mem w_gpr)
-      (gpr_to_gpr_mem w_gpr))
-(decl writable_gpr_to_value_regs (WritableGpr) ValueRegs)
-(rule (writable_gpr_to_value_regs w_gpr)
-      (value_reg w_gpr))
-(decl writable_xmm_to_r_reg (WritableXmm) Reg)
-(rule (writable_xmm_to_r_reg w_xmm)
-      (writable_reg_to_reg (writable_xmm_to_reg w_xmm)))
-(decl writable_xmm_to_xmm_mem (WritableXmm) XmmMem)
-(rule (writable_xmm_to_xmm_mem w_xmm)
-      (xmm_to_xmm_mem (writable_xmm_to_xmm w_xmm)))
-(decl writable_xmm_to_value_regs (WritableXmm) ValueRegs)
-(rule (writable_xmm_to_value_regs w_xmm)
-      (value_reg w_xmm))
-
-(decl synthetic_amode_to_gpr_mem (SyntheticAmode) GprMem)
-(rule (synthetic_amode_to_gpr_mem amode)
-      (synthetic_amode_to_reg_mem amode))
-(decl synthetic_amode_to_xmm_mem (SyntheticAmode) XmmMem)
-(rule (synthetic_amode_to_xmm_mem amode)
-      (synthetic_amode_to_reg_mem amode))
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/inst/args.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/inst/args.rs
deleted file mode 100644
index 6ad2e0111..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/inst/args.rs
+++ /dev/null
@@ -1,1862 +0,0 @@
-//! Instruction operand sub-components (aka "parts"): definitions and printing.
-
-use super::regs::{self, show_ireg_sized};
-use super::EmitState;
-use crate::ir::condcodes::{FloatCC, IntCC};
-use crate::ir::{MemFlags, Type};
-use crate::isa::x64::inst::Inst;
-use crate::machinst::*;
-use regalloc::{
-    PrettyPrint, PrettyPrintSized, RealRegUniverse, Reg, RegClass, RegUsageCollector, Writable,
-};
-use smallvec::{smallvec, SmallVec};
-use std::fmt;
-use std::string::String;
-
-/// An extenstion trait for converting `Writable{Xmm,Gpr}` to `Writable<Reg>`.
-pub trait ToWritableReg {
-    fn to_writable_reg(&self) -> Writable<Reg>;
-}
-
-/// An extension trait for converting `Writable<Reg>` to `Writable{Xmm,Gpr}`.
-pub trait FromWritableReg: Sized {
-    fn from_writable_reg(w: Writable<Reg>) -> Option<Self>;
-}
-
-/// An extension trait for mapping register uses on `{Xmm,Gpr}`.
-pub trait MapUseExt {
-    fn map_use<RM>(&mut self, mapper: &RM)
-    where
-        RM: RegMapper;
-}
-
-/// An extension trait for mapping register mods and defs on
-/// `Writable{Xmm,Gpr}`.
-pub trait MapDefModExt {
-    fn map_def<RM>(&mut self, mapper: &RM)
-    where
-        RM: RegMapper;
-
-    fn map_mod<RM>(&mut self, mapper: &RM)
-    where
-        RM: RegMapper;
-}
-
-/// A macro for defining a newtype of `Reg` that enforces some invariant about
-/// the wrapped `Reg` (such as that it is of a particular register class).
-macro_rules! newtype_of_reg {
-    (
-        $newtype_reg:ident,
-        $newtype_writable_reg:ident,
-        $newtype_option_writable_reg:ident,
-        $newtype_reg_mem:ident,
-        $newtype_reg_mem_imm:ident,
-        $newtype_imm8_reg:ident,
-        |$check_reg:ident| $check:expr
-    ) => {
-        /// A newtype wrapper around `Reg`.
-        #[derive(Clone, Copy, Debug, PartialEq, Eq, Hash, PartialOrd, Ord)]
-        pub struct $newtype_reg(Reg);
-
-        impl PartialEq<Reg> for $newtype_reg {
-            fn eq(&self, other: &Reg) -> bool {
-                self.0 == *other
-            }
-        }
-
-        impl From<$newtype_reg> for Reg {
-            fn from(r: $newtype_reg) -> Self {
-                r.0
-            }
-        }
-
-        impl PrettyPrint for $newtype_reg {
-            fn show_rru(&self, mb_rru: Option<&RealRegUniverse>) -> String {
-                self.0.show_rru(mb_rru)
-            }
-        }
-
-        impl $newtype_reg {
-            /// Create this newtype from the given register, or return `None` if the register
-            /// is not a valid instance of this newtype.
-            pub fn new($check_reg: Reg) -> Option<Self> {
-                if $check {
-                    Some(Self($check_reg))
-                } else {
-                    None
-                }
-            }
-
-            /// Get this newtype's underlying `Reg`.
-            pub fn to_reg(self) -> Reg {
-                self.0
-            }
-        }
-
-        // Convenience impl so that people working with this newtype can use it
-        // "just like" a plain `Reg`.
-        //
-        // NB: We cannot implement `DerefMut` because that would let people do
-        // nasty stuff like `*my_gpr.deref_mut() = some_xmm_reg`, breaking the
-        // invariants that `Gpr` provides.
-        impl std::ops::Deref for $newtype_reg {
-            type Target = Reg;
-
-            fn deref(&self) -> &Reg {
-                &self.0
-            }
-        }
-
-        impl MapUseExt for $newtype_reg {
-            fn map_use<RM>(&mut self, mapper: &RM)
-            where
-                RM: RegMapper,
-            {
-                let mut reg = self.0;
-                mapper.map_use(&mut reg);
-                debug_assert!({
-                    let $check_reg = reg;
-                    $check
-                });
-                *self = $newtype_reg(reg);
-            }
-        }
-
-        pub type $newtype_writable_reg = Writable<$newtype_reg>;
-
-        #[allow(dead_code)] // Used by some newtypes and not others.
-        pub type $newtype_option_writable_reg = Option<Writable<$newtype_reg>>;
-
-        impl ToWritableReg for $newtype_writable_reg {
-            fn to_writable_reg(&self) -> Writable<Reg> {
-                Writable::from_reg(self.to_reg().to_reg())
-            }
-        }
-
-        impl FromWritableReg for $newtype_writable_reg {
-            fn from_writable_reg(w: Writable<Reg>) -> Option<Self> {
-                Some(Writable::from_reg($newtype_reg::new(w.to_reg())?))
-            }
-        }
-
-        impl MapDefModExt for $newtype_writable_reg {
-            fn map_def<RM>(&mut self, mapper: &RM)
-            where
-                RM: RegMapper,
-            {
-                let mut reg = self.to_writable_reg();
-                mapper.map_def(&mut reg);
-                debug_assert!({
-                    let $check_reg = reg.to_reg();
-                    $check
-                });
-                *self = Writable::from_reg($newtype_reg(reg.to_reg()));
-            }
-
-            fn map_mod<RM>(&mut self, mapper: &RM)
-            where
-                RM: RegMapper,
-            {
-                let mut reg = self.to_writable_reg();
-                mapper.map_mod(&mut reg);
-                debug_assert!({
-                    let $check_reg = reg.to_reg();
-                    $check
-                });
-                *self = Writable::from_reg($newtype_reg(reg.to_reg()));
-            }
-        }
-
-        /// A newtype wrapper around `RegMem` for general-purpose registers.
-        #[derive(Clone, Debug)]
-        pub struct $newtype_reg_mem(RegMem);
-
-        impl From<$newtype_reg_mem> for RegMem {
-            fn from(rm: $newtype_reg_mem) -> Self {
-                rm.0
-            }
-        }
-
-        impl From<$newtype_reg> for $newtype_reg_mem {
-            fn from(r: $newtype_reg) -> Self {
-                $newtype_reg_mem(RegMem::reg(r.into()))
-            }
-        }
-
-        impl $newtype_reg_mem {
-            /// Construct a `RegMem` newtype from the given `RegMem`, or return
-            /// `None` if the `RegMem` is not a valid instance of this `RegMem`
-            /// newtype.
-            pub fn new(rm: RegMem) -> Option<Self> {
-                match rm {
-                    RegMem::Mem { addr: _ } => Some(Self(rm)),
-                    RegMem::Reg { reg: $check_reg } if $check => Some(Self(rm)),
-                    RegMem::Reg { reg: _ } => None,
-                }
-            }
-
-            /// Convert this newtype into its underlying `RegMem`.
-            pub fn to_reg_mem(self) -> RegMem {
-                self.0
-            }
-
-            #[allow(dead_code)] // Used by some newtypes and not others.
-            pub fn map_uses<RM>(&mut self, mapper: &RM)
-            where
-                RM: RegMapper,
-            {
-                self.0.map_uses(mapper);
-                debug_assert!(match self.0 {
-                    RegMem::Reg { reg: $check_reg } => $check,
-                    _ => true,
-                });
-            }
-
-            #[allow(dead_code)] // Used by some newtypes and not others.
-            pub fn map_as_def<RM>(&mut self, mapper: &RM)
-            where
-                RM: RegMapper,
-            {
-                self.0.map_as_def(mapper);
-                debug_assert!(match self.0 {
-                    RegMem::Reg { reg: $check_reg } => $check,
-                    _ => true,
-                });
-            }
-
-            #[allow(dead_code)] // Used by some newtypes and not others.
-            pub fn get_regs_as_uses(&self, collector: &mut RegUsageCollector) {
-                self.0.get_regs_as_uses(collector);
-            }
-        }
-
-        impl PrettyPrint for $newtype_reg_mem {
-            fn show_rru(&self, mb_rru: Option<&RealRegUniverse>) -> String {
-                self.0.show_rru(mb_rru)
-            }
-        }
-
-        impl PrettyPrintSized for $newtype_reg_mem {
-            fn show_rru_sized(&self, mb_rru: Option<&RealRegUniverse>, size: u8) -> String {
-                self.0.show_rru_sized(mb_rru, size)
-            }
-        }
-
-        /// A newtype wrapper around `RegMemImm`.
-        #[derive(Clone, Debug)]
-        pub struct $newtype_reg_mem_imm(RegMemImm);
-
-        impl From<$newtype_reg_mem_imm> for RegMemImm {
-            fn from(rmi: $newtype_reg_mem_imm) -> RegMemImm {
-                rmi.0
-            }
-        }
-
-        impl From<$newtype_reg> for $newtype_reg_mem_imm {
-            fn from(r: $newtype_reg) -> Self {
-                $newtype_reg_mem_imm(RegMemImm::reg(r.into()))
-            }
-        }
-
-        impl $newtype_reg_mem_imm {
-            /// Construct this newtype from the given `RegMemImm`, or return
-            /// `None` if the `RegMemImm` is not a valid instance of this
-            /// newtype.
-            pub fn new(rmi: RegMemImm) -> Option<Self> {
-                match rmi {
-                    RegMemImm::Imm { .. } => Some(Self(rmi)),
-                    RegMemImm::Mem { addr: _ } => Some(Self(rmi)),
-                    RegMemImm::Reg { reg: $check_reg } if $check => Some(Self(rmi)),
-                    RegMemImm::Reg { reg: _ } => None,
-                }
-            }
-
-            /// Convert this newtype into its underlying `RegMemImm`.
-            #[allow(dead_code)] // Used by some newtypes and not others.
-            pub fn to_reg_mem_imm(self) -> RegMemImm {
-                self.0
-            }
-
-            #[allow(dead_code)] // Used by some newtypes and not others.
-            pub fn map_uses<RM>(&mut self, mapper: &RM)
-            where
-                RM: RegMapper,
-            {
-                self.0.map_uses(mapper);
-                debug_assert!(match self.0 {
-                    RegMemImm::Reg { reg: $check_reg } => $check,
-                    _ => true,
-                });
-            }
-
-            #[allow(dead_code)] // Used by some newtypes and not others.
-            pub fn map_as_def<RM>(&mut self, mapper: &RM)
-            where
-                RM: RegMapper,
-            {
-                self.0.map_as_def(mapper);
-                debug_assert!(match self.0 {
-                    RegMemImm::Reg { reg: $check_reg } => $check,
-                    _ => true,
-                });
-            }
-
-            #[allow(dead_code)] // Used by some newtypes and not others.
-            pub fn get_regs_as_uses(&self, collector: &mut RegUsageCollector) {
-                self.0.get_regs_as_uses(collector);
-            }
-        }
-
-        impl PrettyPrint for $newtype_reg_mem_imm {
-            fn show_rru(&self, mb_rru: Option<&RealRegUniverse>) -> String {
-                self.0.show_rru(mb_rru)
-            }
-        }
-
-        impl PrettyPrintSized for $newtype_reg_mem_imm {
-            fn show_rru_sized(&self, mb_rru: Option<&RealRegUniverse>, size: u8) -> String {
-                self.0.show_rru_sized(mb_rru, size)
-            }
-        }
-
-        /// A newtype wrapper around `Imm8Reg`.
-        #[derive(Clone, Debug)]
-        #[allow(dead_code)] // Used by some newtypes and not others.
-        pub struct $newtype_imm8_reg(Imm8Reg);
-
-        impl From<$newtype_reg> for $newtype_imm8_reg {
-            fn from(r: $newtype_reg) -> Self {
-                Self(Imm8Reg::Reg { reg: r.to_reg() })
-            }
-        }
-
-        impl $newtype_imm8_reg {
-            /// Construct this newtype from the given `Imm8Reg`, or return
-            /// `None` if the `Imm8Reg` is not a valid instance of this newtype.
-            #[allow(dead_code)] // Used by some newtypes and not others.
-            pub fn new(imm8_reg: Imm8Reg) -> Option<Self> {
-                match imm8_reg {
-                    Imm8Reg::Imm8 { .. } => Some(Self(imm8_reg)),
-                    Imm8Reg::Reg { reg: $check_reg } if $check => Some(Self(imm8_reg)),
-                    Imm8Reg::Reg { reg: _ } => None,
-                }
-            }
-
-            /// Convert this newtype into its underlying `Imm8Reg`.
-            #[allow(dead_code)] // Used by some newtypes and not others.
-            pub fn to_imm8_reg(self) -> Imm8Reg {
-                self.0
-            }
-        }
-    };
-}
-
-// Define a newtype of `Reg` for general-purpose registers.
-newtype_of_reg!(
-    Gpr,
-    WritableGpr,
-    OptionWritableGpr,
-    GprMem,
-    GprMemImm,
-    Imm8Gpr,
-    |reg| reg.get_class() == RegClass::I64
-);
-
-// Define a newtype of `Reg` for XMM registers.
-newtype_of_reg!(
-    Xmm,
-    WritableXmm,
-    OptionWritableXmm,
-    XmmMem,
-    XmmMemImm,
-    Imm8Xmm,
-    |reg| reg.get_class() == RegClass::V128
-);
-
-/// A possible addressing mode (amode) that can be used in instructions.
-/// These denote a 64-bit value only.
-#[derive(Clone, Debug)]
-pub enum Amode {
-    /// Immediate sign-extended and a Register.
-    ImmReg {
-        simm32: u32,
-        base: Reg,
-        flags: MemFlags,
-    },
-
-    /// sign-extend-32-to-64(Immediate) + Register1 + (Register2 << Shift)
-    ImmRegRegShift {
-        simm32: u32,
-        base: Gpr,
-        index: Gpr,
-        shift: u8, /* 0 .. 3 only */
-        flags: MemFlags,
-    },
-
-    /// sign-extend-32-to-64(Immediate) + RIP (instruction pointer).
-    /// To wit: not supported in 32-bits mode.
-    RipRelative { target: MachLabel },
-}
-
-impl Amode {
-    pub(crate) fn imm_reg(simm32: u32, base: Reg) -> Self {
-        debug_assert!(base.get_class() == RegClass::I64);
-        Self::ImmReg {
-            simm32,
-            base,
-            flags: MemFlags::trusted(),
-        }
-    }
-
-    pub(crate) fn imm_reg_reg_shift(simm32: u32, base: Gpr, index: Gpr, shift: u8) -> Self {
-        debug_assert!(base.get_class() == RegClass::I64);
-        debug_assert!(index.get_class() == RegClass::I64);
-        debug_assert!(shift <= 3);
-        Self::ImmRegRegShift {
-            simm32,
-            base,
-            index,
-            shift,
-            flags: MemFlags::trusted(),
-        }
-    }
-
-    pub(crate) fn rip_relative(target: MachLabel) -> Self {
-        Self::RipRelative { target }
-    }
-
-    pub(crate) fn with_flags(&self, flags: MemFlags) -> Self {
-        match self {
-            &Self::ImmReg { simm32, base, .. } => Self::ImmReg {
-                simm32,
-                base,
-                flags,
-            },
-            &Self::ImmRegRegShift {
-                simm32,
-                base,
-                index,
-                shift,
-                ..
-            } => Self::ImmRegRegShift {
-                simm32,
-                base,
-                index,
-                shift,
-                flags,
-            },
-            _ => panic!("Amode {:?} cannot take memflags", self),
-        }
-    }
-
-    /// Add the regs mentioned by `self` to `collector`.
-    pub(crate) fn get_regs_as_uses(&self, collector: &mut RegUsageCollector) {
-        match self {
-            Amode::ImmReg { base, .. } => {
-                collector.add_use(*base);
-            }
-            Amode::ImmRegRegShift { base, index, .. } => {
-                collector.add_use(base.to_reg());
-                collector.add_use(index.to_reg());
-            }
-            Amode::RipRelative { .. } => {
-                // RIP isn't involved in regalloc.
-            }
-        }
-    }
-
-    pub(crate) fn get_flags(&self) -> MemFlags {
-        match self {
-            Amode::ImmReg { flags, .. } => *flags,
-            Amode::ImmRegRegShift { flags, .. } => *flags,
-            Amode::RipRelative { .. } => MemFlags::trusted(),
-        }
-    }
-
-    pub(crate) fn can_trap(&self) -> bool {
-        !self.get_flags().notrap()
-    }
-}
-
-impl PrettyPrint for Amode {
-    fn show_rru(&self, mb_rru: Option<&RealRegUniverse>) -> String {
-        match self {
-            Amode::ImmReg { simm32, base, .. } => {
-                format!("{}({})", *simm32 as i32, base.show_rru(mb_rru))
-            }
-            Amode::ImmRegRegShift {
-                simm32,
-                base,
-                index,
-                shift,
-                ..
-            } => format!(
-                "{}({},{},{})",
-                *simm32 as i32,
-                base.show_rru(mb_rru),
-                index.show_rru(mb_rru),
-                1 << shift
-            ),
-            Amode::RipRelative { ref target } => format!("label{}(%rip)", target.get()),
-        }
-    }
-}
-
-/// A Memory Address. These denote a 64-bit value only.
-/// Used for usual addressing modes as well as addressing modes used during compilation, when the
-/// moving SP offset is not known.
-#[derive(Clone, Debug)]
-pub enum SyntheticAmode {
-    /// A real amode.
-    Real(Amode),
-
-    /// A (virtual) offset to the "nominal SP" value, which will be recomputed as we push and pop
-    /// within the function.
-    NominalSPOffset { simm32: u32 },
-
-    /// A virtual offset to a constant that will be emitted in the constant section of the buffer.
-    ConstantOffset(VCodeConstant),
-}
-
-impl SyntheticAmode {
-    pub(crate) fn nominal_sp_offset(simm32: u32) -> Self {
-        SyntheticAmode::NominalSPOffset { simm32 }
-    }
-
-    /// Add the regs mentioned by `self` to `collector`.
-    pub(crate) fn get_regs_as_uses(&self, collector: &mut RegUsageCollector) {
-        match self {
-            SyntheticAmode::Real(addr) => addr.get_regs_as_uses(collector),
-            SyntheticAmode::NominalSPOffset { .. } => {
-                // Nothing to do; the base is SP and isn't involved in regalloc.
-            }
-            SyntheticAmode::ConstantOffset(_) => {}
-        }
-    }
-
-    pub(crate) fn map_uses<RM: RegMapper>(&mut self, map: &RM) {
-        match self {
-            SyntheticAmode::Real(addr) => addr.map_uses(map),
-            SyntheticAmode::NominalSPOffset { .. } => {
-                // Nothing to do.
-            }
-            SyntheticAmode::ConstantOffset(_) => {}
-        }
-    }
-
-    pub(crate) fn finalize(&self, state: &mut EmitState, buffer: &MachBuffer<Inst>) -> Amode {
-        match self {
-            SyntheticAmode::Real(addr) => addr.clone(),
-            SyntheticAmode::NominalSPOffset { simm32 } => {
-                let off = *simm32 as i64 + state.virtual_sp_offset;
-                // TODO will require a sequence of add etc.
-                assert!(
-                    off <= u32::max_value() as i64,
-                    "amode finalize: add sequence NYI"
-                );
-                Amode::imm_reg(off as u32, regs::rsp())
-            }
-            SyntheticAmode::ConstantOffset(c) => {
-                Amode::rip_relative(buffer.get_label_for_constant(*c))
-            }
-        }
-    }
-}
-
-impl Into<SyntheticAmode> for Amode {
-    fn into(self) -> SyntheticAmode {
-        SyntheticAmode::Real(self)
-    }
-}
-
-impl PrettyPrint for SyntheticAmode {
-    fn show_rru(&self, mb_rru: Option<&RealRegUniverse>) -> String {
-        match self {
-            SyntheticAmode::Real(addr) => addr.show_rru(mb_rru),
-            SyntheticAmode::NominalSPOffset { simm32 } => {
-                format!("rsp({} + virtual offset)", *simm32 as i32)
-            }
-            SyntheticAmode::ConstantOffset(c) => format!("const({:?})", c),
-        }
-    }
-}
-
-/// An operand which is either an integer Register, a value in Memory or an Immediate.  This can
-/// denote an 8, 16, 32 or 64 bit value.  For the Immediate form, in the 8- and 16-bit case, only
-/// the lower 8 or 16 bits of `simm32` is relevant.  In the 64-bit case, the value denoted by
-/// `simm32` is its sign-extension out to 64 bits.
-#[derive(Clone, Debug)]
-pub enum RegMemImm {
-    Reg { reg: Reg },
-    Mem { addr: SyntheticAmode },
-    Imm { simm32: u32 },
-}
-
-impl RegMemImm {
-    pub(crate) fn reg(reg: Reg) -> Self {
-        debug_assert!(reg.get_class() == RegClass::I64 || reg.get_class() == RegClass::V128);
-        Self::Reg { reg }
-    }
-    pub(crate) fn mem(addr: impl Into<SyntheticAmode>) -> Self {
-        Self::Mem { addr: addr.into() }
-    }
-    pub(crate) fn imm(simm32: u32) -> Self {
-        Self::Imm { simm32 }
-    }
-
-    /// Asserts that in register mode, the reg class is the one that's expected.
-    pub(crate) fn assert_regclass_is(&self, expected_reg_class: RegClass) {
-        if let Self::Reg { reg } = self {
-            debug_assert_eq!(reg.get_class(), expected_reg_class);
-        }
-    }
-
-    /// Add the regs mentioned by `self` to `collector`.
-    pub(crate) fn get_regs_as_uses(&self, collector: &mut RegUsageCollector) {
-        match self {
-            Self::Reg { reg } => collector.add_use(*reg),
-            Self::Mem { addr } => addr.get_regs_as_uses(collector),
-            Self::Imm { .. } => {}
-        }
-    }
-
-    pub(crate) fn to_reg(&self) -> Option<Reg> {
-        match self {
-            Self::Reg { reg } => Some(*reg),
-            _ => None,
-        }
-    }
-}
-
-impl PrettyPrint for RegMemImm {
-    fn show_rru(&self, mb_rru: Option<&RealRegUniverse>) -> String {
-        self.show_rru_sized(mb_rru, 8)
-    }
-}
-
-impl PrettyPrintSized for RegMemImm {
-    fn show_rru_sized(&self, mb_rru: Option<&RealRegUniverse>, size: u8) -> String {
-        match self {
-            Self::Reg { reg } => show_ireg_sized(*reg, mb_rru, size),
-            Self::Mem { addr } => addr.show_rru(mb_rru),
-            Self::Imm { simm32 } => format!("${}", *simm32 as i32),
-        }
-    }
-}
-
-/// An operand which is either an 8-bit integer immediate or a register.
-#[derive(Clone, Debug)]
-pub enum Imm8Reg {
-    Imm8 { imm: u8 },
-    Reg { reg: Reg },
-}
-
-impl From<u8> for Imm8Reg {
-    fn from(imm: u8) -> Self {
-        Self::Imm8 { imm }
-    }
-}
-
-impl From<Reg> for Imm8Reg {
-    fn from(reg: Reg) -> Self {
-        Self::Reg { reg }
-    }
-}
-
-/// An operand which is either an integer Register or a value in Memory.  This can denote an 8, 16,
-/// 32, 64, or 128 bit value.
-#[derive(Clone, Debug)]
-pub enum RegMem {
-    Reg { reg: Reg },
-    Mem { addr: SyntheticAmode },
-}
-
-impl RegMem {
-    pub(crate) fn reg(reg: Reg) -> Self {
-        debug_assert!(reg.get_class() == RegClass::I64 || reg.get_class() == RegClass::V128);
-        Self::Reg { reg }
-    }
-    pub(crate) fn mem(addr: impl Into<SyntheticAmode>) -> Self {
-        Self::Mem { addr: addr.into() }
-    }
-    /// Asserts that in register mode, the reg class is the one that's expected.
-    pub(crate) fn assert_regclass_is(&self, expected_reg_class: RegClass) {
-        if let Self::Reg { reg } = self {
-            debug_assert_eq!(reg.get_class(), expected_reg_class);
-        }
-    }
-    /// Add the regs mentioned by `self` to `collector`.
-    pub(crate) fn get_regs_as_uses(&self, collector: &mut RegUsageCollector) {
-        match self {
-            RegMem::Reg { reg } => collector.add_use(*reg),
-            RegMem::Mem { addr, .. } => addr.get_regs_as_uses(collector),
-        }
-    }
-    pub(crate) fn to_reg(&self) -> Option<Reg> {
-        match self {
-            RegMem::Reg { reg } => Some(*reg),
-            _ => None,
-        }
-    }
-}
-
-impl From<Writable<Reg>> for RegMem {
-    fn from(r: Writable<Reg>) -> Self {
-        RegMem::reg(r.to_reg())
-    }
-}
-
-impl PrettyPrint for RegMem {
-    fn show_rru(&self, mb_rru: Option<&RealRegUniverse>) -> String {
-        self.show_rru_sized(mb_rru, 8)
-    }
-}
-
-impl PrettyPrintSized for RegMem {
-    fn show_rru_sized(&self, mb_rru: Option<&RealRegUniverse>, size: u8) -> String {
-        match self {
-            RegMem::Reg { reg } => show_ireg_sized(*reg, mb_rru, size),
-            RegMem::Mem { addr, .. } => addr.show_rru(mb_rru),
-        }
-    }
-}
-
-/// Some basic ALU operations.  TODO: maybe add Adc, Sbb.
-#[derive(Copy, Clone, PartialEq)]
-pub enum AluRmiROpcode {
-    Add,
-    Adc,
-    Sub,
-    Sbb,
-    And,
-    Or,
-    Xor,
-    /// The signless, non-extending (N x N -> N, for N in {32,64}) variant.
-    Mul,
-    /// 8-bit form of And. Handled separately as we don't have full 8-bit op
-    /// support (we just use wider instructions). Used only with some sequences
-    /// with SETcc.
-    And8,
-    /// 8-bit form of Or.
-    Or8,
-}
-
-impl fmt::Debug for AluRmiROpcode {
-    fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result {
-        let name = match self {
-            AluRmiROpcode::Add => "add",
-            AluRmiROpcode::Adc => "adc",
-            AluRmiROpcode::Sub => "sub",
-            AluRmiROpcode::Sbb => "sbb",
-            AluRmiROpcode::And => "and",
-            AluRmiROpcode::Or => "or",
-            AluRmiROpcode::Xor => "xor",
-            AluRmiROpcode::Mul => "imul",
-            AluRmiROpcode::And8 => "and",
-            AluRmiROpcode::Or8 => "or",
-        };
-        write!(fmt, "{}", name)
-    }
-}
-
-impl fmt::Display for AluRmiROpcode {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        fmt::Debug::fmt(self, f)
-    }
-}
-
-impl AluRmiROpcode {
-    /// Is this a special-cased 8-bit ALU op?
-    pub fn is_8bit(self) -> bool {
-        match self {
-            AluRmiROpcode::And8 | AluRmiROpcode::Or8 => true,
-            _ => false,
-        }
-    }
-}
-
-#[derive(Clone, PartialEq)]
-pub enum UnaryRmROpcode {
-    /// Bit-scan reverse.
-    Bsr,
-    /// Bit-scan forward.
-    Bsf,
-    /// Counts leading zeroes (Leading Zero CouNT).
-    Lzcnt,
-    /// Counts trailing zeroes (Trailing Zero CouNT).
-    Tzcnt,
-    /// Counts the number of ones (POPulation CouNT).
-    Popcnt,
-}
-
-impl UnaryRmROpcode {
-    pub(crate) fn available_from(&self) -> SmallVec<[InstructionSet; 2]> {
-        match self {
-            UnaryRmROpcode::Bsr | UnaryRmROpcode::Bsf => smallvec![],
-            UnaryRmROpcode::Lzcnt => smallvec![InstructionSet::Lzcnt],
-            UnaryRmROpcode::Tzcnt => smallvec![InstructionSet::BMI1],
-            UnaryRmROpcode::Popcnt => smallvec![InstructionSet::Popcnt],
-        }
-    }
-}
-
-impl fmt::Debug for UnaryRmROpcode {
-    fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result {
-        match self {
-            UnaryRmROpcode::Bsr => write!(fmt, "bsr"),
-            UnaryRmROpcode::Bsf => write!(fmt, "bsf"),
-            UnaryRmROpcode::Lzcnt => write!(fmt, "lzcnt"),
-            UnaryRmROpcode::Tzcnt => write!(fmt, "tzcnt"),
-            UnaryRmROpcode::Popcnt => write!(fmt, "popcnt"),
-        }
-    }
-}
-
-impl fmt::Display for UnaryRmROpcode {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        fmt::Debug::fmt(self, f)
-    }
-}
-
-#[derive(Clone, Copy, PartialEq)]
-pub enum CmpOpcode {
-    /// CMP instruction: compute `a - b` and set flags from result.
-    Cmp,
-    /// TEST instruction: compute `a & b` and set flags from result.
-    Test,
-}
-
-#[derive(Debug)]
-pub(crate) enum InstructionSet {
-    SSE,
-    SSE2,
-    SSSE3,
-    SSE41,
-    SSE42,
-    Popcnt,
-    Lzcnt,
-    BMI1,
-    #[allow(dead_code)] // never constructed (yet).
-    BMI2,
-    AVX512BITALG,
-    AVX512DQ,
-    AVX512F,
-    AVX512VBMI,
-    AVX512VL,
-}
-
-/// Some SSE operations requiring 2 operands r/m and r.
-#[derive(Clone, Copy, PartialEq)]
-#[allow(dead_code)] // some variants here aren't used just yet
-pub enum SseOpcode {
-    Addps,
-    Addpd,
-    Addss,
-    Addsd,
-    Andps,
-    Andpd,
-    Andnps,
-    Andnpd,
-    Blendvpd,
-    Blendvps,
-    Comiss,
-    Comisd,
-    Cmpps,
-    Cmppd,
-    Cmpss,
-    Cmpsd,
-    Cvtdq2ps,
-    Cvtdq2pd,
-    Cvtpd2ps,
-    Cvtps2pd,
-    Cvtsd2ss,
-    Cvtsd2si,
-    Cvtsi2ss,
-    Cvtsi2sd,
-    Cvtss2si,
-    Cvtss2sd,
-    Cvttpd2dq,
-    Cvttps2dq,
-    Cvttss2si,
-    Cvttsd2si,
-    Divps,
-    Divpd,
-    Divss,
-    Divsd,
-    Insertps,
-    Maxps,
-    Maxpd,
-    Maxss,
-    Maxsd,
-    Minps,
-    Minpd,
-    Minss,
-    Minsd,
-    Movaps,
-    Movapd,
-    Movd,
-    Movdqa,
-    Movdqu,
-    Movlhps,
-    Movmskps,
-    Movmskpd,
-    Movq,
-    Movss,
-    Movsd,
-    Movups,
-    Movupd,
-    Mulps,
-    Mulpd,
-    Mulss,
-    Mulsd,
-    Orps,
-    Orpd,
-    Pabsb,
-    Pabsw,
-    Pabsd,
-    Packssdw,
-    Packsswb,
-    Packusdw,
-    Packuswb,
-    Paddb,
-    Paddd,
-    Paddq,
-    Paddw,
-    Paddsb,
-    Paddsw,
-    Paddusb,
-    Paddusw,
-    Palignr,
-    Pand,
-    Pandn,
-    Pavgb,
-    Pavgw,
-    Pblendvb,
-    Pcmpeqb,
-    Pcmpeqw,
-    Pcmpeqd,
-    Pcmpeqq,
-    Pcmpgtb,
-    Pcmpgtw,
-    Pcmpgtd,
-    Pcmpgtq,
-    Pextrb,
-    Pextrw,
-    Pextrd,
-    Pinsrb,
-    Pinsrw,
-    Pinsrd,
-    Pmaddubsw,
-    Pmaddwd,
-    Pmaxsb,
-    Pmaxsw,
-    Pmaxsd,
-    Pmaxub,
-    Pmaxuw,
-    Pmaxud,
-    Pminsb,
-    Pminsw,
-    Pminsd,
-    Pminub,
-    Pminuw,
-    Pminud,
-    Pmovmskb,
-    Pmovsxbd,
-    Pmovsxbw,
-    Pmovsxbq,
-    Pmovsxwd,
-    Pmovsxwq,
-    Pmovsxdq,
-    Pmovzxbd,
-    Pmovzxbw,
-    Pmovzxbq,
-    Pmovzxwd,
-    Pmovzxwq,
-    Pmovzxdq,
-    Pmuldq,
-    Pmulhw,
-    Pmulhuw,
-    Pmulhrsw,
-    Pmulld,
-    Pmullw,
-    Pmuludq,
-    Por,
-    Pshufb,
-    Pshufd,
-    Psllw,
-    Pslld,
-    Psllq,
-    Psraw,
-    Psrad,
-    Psrlw,
-    Psrld,
-    Psrlq,
-    Psubb,
-    Psubd,
-    Psubq,
-    Psubw,
-    Psubsb,
-    Psubsw,
-    Psubusb,
-    Psubusw,
-    Ptest,
-    Punpckhbw,
-    Punpckhwd,
-    Punpcklbw,
-    Punpcklwd,
-    Pxor,
-    Rcpss,
-    Roundps,
-    Roundpd,
-    Roundss,
-    Roundsd,
-    Rsqrtss,
-    Shufps,
-    Sqrtps,
-    Sqrtpd,
-    Sqrtss,
-    Sqrtsd,
-    Subps,
-    Subpd,
-    Subss,
-    Subsd,
-    Ucomiss,
-    Ucomisd,
-    Unpcklps,
-    Xorps,
-    Xorpd,
-}
-
-impl SseOpcode {
-    /// Which `InstructionSet` is the first supporting this opcode?
-    pub(crate) fn available_from(&self) -> InstructionSet {
-        use InstructionSet::*;
-        match self {
-            SseOpcode::Addps
-            | SseOpcode::Addss
-            | SseOpcode::Andps
-            | SseOpcode::Andnps
-            | SseOpcode::Comiss
-            | SseOpcode::Cmpps
-            | SseOpcode::Cmpss
-            | SseOpcode::Cvtsi2ss
-            | SseOpcode::Cvtss2si
-            | SseOpcode::Cvttss2si
-            | SseOpcode::Divps
-            | SseOpcode::Divss
-            | SseOpcode::Maxps
-            | SseOpcode::Maxss
-            | SseOpcode::Minps
-            | SseOpcode::Minss
-            | SseOpcode::Movaps
-            | SseOpcode::Movlhps
-            | SseOpcode::Movmskps
-            | SseOpcode::Movss
-            | SseOpcode::Movups
-            | SseOpcode::Mulps
-            | SseOpcode::Mulss
-            | SseOpcode::Orps
-            | SseOpcode::Rcpss
-            | SseOpcode::Rsqrtss
-            | SseOpcode::Shufps
-            | SseOpcode::Sqrtps
-            | SseOpcode::Sqrtss
-            | SseOpcode::Subps
-            | SseOpcode::Subss
-            | SseOpcode::Ucomiss
-            | SseOpcode::Unpcklps
-            | SseOpcode::Xorps => SSE,
-
-            SseOpcode::Addpd
-            | SseOpcode::Addsd
-            | SseOpcode::Andpd
-            | SseOpcode::Andnpd
-            | SseOpcode::Cmppd
-            | SseOpcode::Cmpsd
-            | SseOpcode::Comisd
-            | SseOpcode::Cvtdq2ps
-            | SseOpcode::Cvtdq2pd
-            | SseOpcode::Cvtpd2ps
-            | SseOpcode::Cvtps2pd
-            | SseOpcode::Cvtsd2ss
-            | SseOpcode::Cvtsd2si
-            | SseOpcode::Cvtsi2sd
-            | SseOpcode::Cvtss2sd
-            | SseOpcode::Cvttpd2dq
-            | SseOpcode::Cvttps2dq
-            | SseOpcode::Cvttsd2si
-            | SseOpcode::Divpd
-            | SseOpcode::Divsd
-            | SseOpcode::Maxpd
-            | SseOpcode::Maxsd
-            | SseOpcode::Minpd
-            | SseOpcode::Minsd
-            | SseOpcode::Movapd
-            | SseOpcode::Movd
-            | SseOpcode::Movmskpd
-            | SseOpcode::Movq
-            | SseOpcode::Movsd
-            | SseOpcode::Movupd
-            | SseOpcode::Movdqa
-            | SseOpcode::Movdqu
-            | SseOpcode::Mulpd
-            | SseOpcode::Mulsd
-            | SseOpcode::Orpd
-            | SseOpcode::Packssdw
-            | SseOpcode::Packsswb
-            | SseOpcode::Packuswb
-            | SseOpcode::Paddb
-            | SseOpcode::Paddd
-            | SseOpcode::Paddq
-            | SseOpcode::Paddw
-            | SseOpcode::Paddsb
-            | SseOpcode::Paddsw
-            | SseOpcode::Paddusb
-            | SseOpcode::Paddusw
-            | SseOpcode::Pand
-            | SseOpcode::Pandn
-            | SseOpcode::Pavgb
-            | SseOpcode::Pavgw
-            | SseOpcode::Pcmpeqb
-            | SseOpcode::Pcmpeqw
-            | SseOpcode::Pcmpeqd
-            | SseOpcode::Pcmpgtb
-            | SseOpcode::Pcmpgtw
-            | SseOpcode::Pcmpgtd
-            | SseOpcode::Pextrw
-            | SseOpcode::Pinsrw
-            | SseOpcode::Pmaddubsw
-            | SseOpcode::Pmaddwd
-            | SseOpcode::Pmaxsw
-            | SseOpcode::Pmaxub
-            | SseOpcode::Pminsw
-            | SseOpcode::Pminub
-            | SseOpcode::Pmovmskb
-            | SseOpcode::Pmulhw
-            | SseOpcode::Pmulhuw
-            | SseOpcode::Pmullw
-            | SseOpcode::Pmuludq
-            | SseOpcode::Por
-            | SseOpcode::Pshufd
-            | SseOpcode::Psllw
-            | SseOpcode::Pslld
-            | SseOpcode::Psllq
-            | SseOpcode::Psraw
-            | SseOpcode::Psrad
-            | SseOpcode::Psrlw
-            | SseOpcode::Psrld
-            | SseOpcode::Psrlq
-            | SseOpcode::Psubb
-            | SseOpcode::Psubd
-            | SseOpcode::Psubq
-            | SseOpcode::Psubw
-            | SseOpcode::Psubsb
-            | SseOpcode::Psubsw
-            | SseOpcode::Psubusb
-            | SseOpcode::Psubusw
-            | SseOpcode::Punpckhbw
-            | SseOpcode::Punpckhwd
-            | SseOpcode::Punpcklbw
-            | SseOpcode::Punpcklwd
-            | SseOpcode::Pxor
-            | SseOpcode::Sqrtpd
-            | SseOpcode::Sqrtsd
-            | SseOpcode::Subpd
-            | SseOpcode::Subsd
-            | SseOpcode::Ucomisd
-            | SseOpcode::Xorpd => SSE2,
-
-            SseOpcode::Pabsb
-            | SseOpcode::Pabsw
-            | SseOpcode::Pabsd
-            | SseOpcode::Palignr
-            | SseOpcode::Pmulhrsw
-            | SseOpcode::Pshufb => SSSE3,
-
-            SseOpcode::Blendvpd
-            | SseOpcode::Blendvps
-            | SseOpcode::Insertps
-            | SseOpcode::Packusdw
-            | SseOpcode::Pblendvb
-            | SseOpcode::Pcmpeqq
-            | SseOpcode::Pextrb
-            | SseOpcode::Pextrd
-            | SseOpcode::Pinsrb
-            | SseOpcode::Pinsrd
-            | SseOpcode::Pmaxsb
-            | SseOpcode::Pmaxsd
-            | SseOpcode::Pmaxuw
-            | SseOpcode::Pmaxud
-            | SseOpcode::Pminsb
-            | SseOpcode::Pminsd
-            | SseOpcode::Pminuw
-            | SseOpcode::Pminud
-            | SseOpcode::Pmovsxbd
-            | SseOpcode::Pmovsxbw
-            | SseOpcode::Pmovsxbq
-            | SseOpcode::Pmovsxwd
-            | SseOpcode::Pmovsxwq
-            | SseOpcode::Pmovsxdq
-            | SseOpcode::Pmovzxbd
-            | SseOpcode::Pmovzxbw
-            | SseOpcode::Pmovzxbq
-            | SseOpcode::Pmovzxwd
-            | SseOpcode::Pmovzxwq
-            | SseOpcode::Pmovzxdq
-            | SseOpcode::Pmuldq
-            | SseOpcode::Pmulld
-            | SseOpcode::Ptest
-            | SseOpcode::Roundps
-            | SseOpcode::Roundpd
-            | SseOpcode::Roundss
-            | SseOpcode::Roundsd => SSE41,
-
-            SseOpcode::Pcmpgtq => SSE42,
-        }
-    }
-
-    /// Returns the src operand size for an instruction.
-    pub(crate) fn src_size(&self) -> u8 {
-        match self {
-            SseOpcode::Movd => 4,
-            _ => 8,
-        }
-    }
-}
-
-impl fmt::Debug for SseOpcode {
-    fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result {
-        let name = match self {
-            SseOpcode::Addps => "addps",
-            SseOpcode::Addpd => "addpd",
-            SseOpcode::Addss => "addss",
-            SseOpcode::Addsd => "addsd",
-            SseOpcode::Andpd => "andpd",
-            SseOpcode::Andps => "andps",
-            SseOpcode::Andnps => "andnps",
-            SseOpcode::Andnpd => "andnpd",
-            SseOpcode::Blendvpd => "blendvpd",
-            SseOpcode::Blendvps => "blendvps",
-            SseOpcode::Cmpps => "cmpps",
-            SseOpcode::Cmppd => "cmppd",
-            SseOpcode::Cmpss => "cmpss",
-            SseOpcode::Cmpsd => "cmpsd",
-            SseOpcode::Comiss => "comiss",
-            SseOpcode::Comisd => "comisd",
-            SseOpcode::Cvtdq2ps => "cvtdq2ps",
-            SseOpcode::Cvtdq2pd => "cvtdq2pd",
-            SseOpcode::Cvtpd2ps => "cvtpd2ps",
-            SseOpcode::Cvtps2pd => "cvtps2pd",
-            SseOpcode::Cvtsd2ss => "cvtsd2ss",
-            SseOpcode::Cvtsd2si => "cvtsd2si",
-            SseOpcode::Cvtsi2ss => "cvtsi2ss",
-            SseOpcode::Cvtsi2sd => "cvtsi2sd",
-            SseOpcode::Cvtss2si => "cvtss2si",
-            SseOpcode::Cvtss2sd => "cvtss2sd",
-            SseOpcode::Cvttpd2dq => "cvttpd2dq",
-            SseOpcode::Cvttps2dq => "cvttps2dq",
-            SseOpcode::Cvttss2si => "cvttss2si",
-            SseOpcode::Cvttsd2si => "cvttsd2si",
-            SseOpcode::Divps => "divps",
-            SseOpcode::Divpd => "divpd",
-            SseOpcode::Divss => "divss",
-            SseOpcode::Divsd => "divsd",
-            SseOpcode::Insertps => "insertps",
-            SseOpcode::Maxps => "maxps",
-            SseOpcode::Maxpd => "maxpd",
-            SseOpcode::Maxss => "maxss",
-            SseOpcode::Maxsd => "maxsd",
-            SseOpcode::Minps => "minps",
-            SseOpcode::Minpd => "minpd",
-            SseOpcode::Minss => "minss",
-            SseOpcode::Minsd => "minsd",
-            SseOpcode::Movaps => "movaps",
-            SseOpcode::Movapd => "movapd",
-            SseOpcode::Movd => "movd",
-            SseOpcode::Movdqa => "movdqa",
-            SseOpcode::Movdqu => "movdqu",
-            SseOpcode::Movlhps => "movlhps",
-            SseOpcode::Movmskps => "movmskps",
-            SseOpcode::Movmskpd => "movmskpd",
-            SseOpcode::Movq => "movq",
-            SseOpcode::Movss => "movss",
-            SseOpcode::Movsd => "movsd",
-            SseOpcode::Movups => "movups",
-            SseOpcode::Movupd => "movupd",
-            SseOpcode::Mulps => "mulps",
-            SseOpcode::Mulpd => "mulpd",
-            SseOpcode::Mulss => "mulss",
-            SseOpcode::Mulsd => "mulsd",
-            SseOpcode::Orpd => "orpd",
-            SseOpcode::Orps => "orps",
-            SseOpcode::Pabsb => "pabsb",
-            SseOpcode::Pabsw => "pabsw",
-            SseOpcode::Pabsd => "pabsd",
-            SseOpcode::Packssdw => "packssdw",
-            SseOpcode::Packsswb => "packsswb",
-            SseOpcode::Packusdw => "packusdw",
-            SseOpcode::Packuswb => "packuswb",
-            SseOpcode::Paddb => "paddb",
-            SseOpcode::Paddd => "paddd",
-            SseOpcode::Paddq => "paddq",
-            SseOpcode::Paddw => "paddw",
-            SseOpcode::Paddsb => "paddsb",
-            SseOpcode::Paddsw => "paddsw",
-            SseOpcode::Paddusb => "paddusb",
-            SseOpcode::Paddusw => "paddusw",
-            SseOpcode::Palignr => "palignr",
-            SseOpcode::Pand => "pand",
-            SseOpcode::Pandn => "pandn",
-            SseOpcode::Pavgb => "pavgb",
-            SseOpcode::Pavgw => "pavgw",
-            SseOpcode::Pblendvb => "pblendvb",
-            SseOpcode::Pcmpeqb => "pcmpeqb",
-            SseOpcode::Pcmpeqw => "pcmpeqw",
-            SseOpcode::Pcmpeqd => "pcmpeqd",
-            SseOpcode::Pcmpeqq => "pcmpeqq",
-            SseOpcode::Pcmpgtb => "pcmpgtb",
-            SseOpcode::Pcmpgtw => "pcmpgtw",
-            SseOpcode::Pcmpgtd => "pcmpgtd",
-            SseOpcode::Pcmpgtq => "pcmpgtq",
-            SseOpcode::Pextrb => "pextrb",
-            SseOpcode::Pextrw => "pextrw",
-            SseOpcode::Pextrd => "pextrd",
-            SseOpcode::Pinsrb => "pinsrb",
-            SseOpcode::Pinsrw => "pinsrw",
-            SseOpcode::Pinsrd => "pinsrd",
-            SseOpcode::Pmaddubsw => "pmaddubsw",
-            SseOpcode::Pmaddwd => "pmaddwd",
-            SseOpcode::Pmaxsb => "pmaxsb",
-            SseOpcode::Pmaxsw => "pmaxsw",
-            SseOpcode::Pmaxsd => "pmaxsd",
-            SseOpcode::Pmaxub => "pmaxub",
-            SseOpcode::Pmaxuw => "pmaxuw",
-            SseOpcode::Pmaxud => "pmaxud",
-            SseOpcode::Pminsb => "pminsb",
-            SseOpcode::Pminsw => "pminsw",
-            SseOpcode::Pminsd => "pminsd",
-            SseOpcode::Pminub => "pminub",
-            SseOpcode::Pminuw => "pminuw",
-            SseOpcode::Pminud => "pminud",
-            SseOpcode::Pmovmskb => "pmovmskb",
-            SseOpcode::Pmovsxbd => "pmovsxbd",
-            SseOpcode::Pmovsxbw => "pmovsxbw",
-            SseOpcode::Pmovsxbq => "pmovsxbq",
-            SseOpcode::Pmovsxwd => "pmovsxwd",
-            SseOpcode::Pmovsxwq => "pmovsxwq",
-            SseOpcode::Pmovsxdq => "pmovsxdq",
-            SseOpcode::Pmovzxbd => "pmovzxbd",
-            SseOpcode::Pmovzxbw => "pmovzxbw",
-            SseOpcode::Pmovzxbq => "pmovzxbq",
-            SseOpcode::Pmovzxwd => "pmovzxwd",
-            SseOpcode::Pmovzxwq => "pmovzxwq",
-            SseOpcode::Pmovzxdq => "pmovzxdq",
-            SseOpcode::Pmuldq => "pmuldq",
-            SseOpcode::Pmulhw => "pmulhw",
-            SseOpcode::Pmulhuw => "pmulhuw",
-            SseOpcode::Pmulhrsw => "pmulhrsw",
-            SseOpcode::Pmulld => "pmulld",
-            SseOpcode::Pmullw => "pmullw",
-            SseOpcode::Pmuludq => "pmuludq",
-            SseOpcode::Por => "por",
-            SseOpcode::Pshufb => "pshufb",
-            SseOpcode::Pshufd => "pshufd",
-            SseOpcode::Psllw => "psllw",
-            SseOpcode::Pslld => "pslld",
-            SseOpcode::Psllq => "psllq",
-            SseOpcode::Psraw => "psraw",
-            SseOpcode::Psrad => "psrad",
-            SseOpcode::Psrlw => "psrlw",
-            SseOpcode::Psrld => "psrld",
-            SseOpcode::Psrlq => "psrlq",
-            SseOpcode::Psubb => "psubb",
-            SseOpcode::Psubd => "psubd",
-            SseOpcode::Psubq => "psubq",
-            SseOpcode::Psubw => "psubw",
-            SseOpcode::Psubsb => "psubsb",
-            SseOpcode::Psubsw => "psubsw",
-            SseOpcode::Psubusb => "psubusb",
-            SseOpcode::Psubusw => "psubusw",
-            SseOpcode::Ptest => "ptest",
-            SseOpcode::Punpckhbw => "punpckhbw",
-            SseOpcode::Punpckhwd => "punpckhwd",
-            SseOpcode::Punpcklbw => "punpcklbw",
-            SseOpcode::Punpcklwd => "punpcklwd",
-            SseOpcode::Pxor => "pxor",
-            SseOpcode::Rcpss => "rcpss",
-            SseOpcode::Roundps => "roundps",
-            SseOpcode::Roundpd => "roundpd",
-            SseOpcode::Roundss => "roundss",
-            SseOpcode::Roundsd => "roundsd",
-            SseOpcode::Rsqrtss => "rsqrtss",
-            SseOpcode::Shufps => "shufps",
-            SseOpcode::Sqrtps => "sqrtps",
-            SseOpcode::Sqrtpd => "sqrtpd",
-            SseOpcode::Sqrtss => "sqrtss",
-            SseOpcode::Sqrtsd => "sqrtsd",
-            SseOpcode::Subps => "subps",
-            SseOpcode::Subpd => "subpd",
-            SseOpcode::Subss => "subss",
-            SseOpcode::Subsd => "subsd",
-            SseOpcode::Ucomiss => "ucomiss",
-            SseOpcode::Ucomisd => "ucomisd",
-            SseOpcode::Unpcklps => "unpcklps",
-            SseOpcode::Xorps => "xorps",
-            SseOpcode::Xorpd => "xorpd",
-        };
-        write!(fmt, "{}", name)
-    }
-}
-
-impl fmt::Display for SseOpcode {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        fmt::Debug::fmt(self, f)
-    }
-}
-
-#[derive(Clone, PartialEq)]
-pub enum Avx512Opcode {
-    Vcvtudq2ps,
-    Vpabsq,
-    Vpermi2b,
-    Vpmullq,
-    Vpopcntb,
-}
-
-impl Avx512Opcode {
-    /// Which `InstructionSet`s support the opcode?
-    pub(crate) fn available_from(&self) -> SmallVec<[InstructionSet; 2]> {
-        match self {
-            Avx512Opcode::Vcvtudq2ps => {
-                smallvec![InstructionSet::AVX512F, InstructionSet::AVX512VL]
-            }
-            Avx512Opcode::Vpabsq => smallvec![InstructionSet::AVX512F, InstructionSet::AVX512VL],
-            Avx512Opcode::Vpermi2b => {
-                smallvec![InstructionSet::AVX512VL, InstructionSet::AVX512VBMI]
-            }
-            Avx512Opcode::Vpmullq => smallvec![InstructionSet::AVX512VL, InstructionSet::AVX512DQ],
-            Avx512Opcode::Vpopcntb => {
-                smallvec![InstructionSet::AVX512VL, InstructionSet::AVX512BITALG]
-            }
-        }
-    }
-}
-
-impl fmt::Debug for Avx512Opcode {
-    fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result {
-        let name = match self {
-            Avx512Opcode::Vcvtudq2ps => "vcvtudq2ps",
-            Avx512Opcode::Vpabsq => "vpabsq",
-            Avx512Opcode::Vpermi2b => "vpermi2b",
-            Avx512Opcode::Vpmullq => "vpmullq",
-            Avx512Opcode::Vpopcntb => "vpopcntb",
-        };
-        write!(fmt, "{}", name)
-    }
-}
-
-impl fmt::Display for Avx512Opcode {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        fmt::Debug::fmt(self, f)
-    }
-}
-
-/// This defines the ways a value can be extended: either signed- or zero-extension, or none for
-/// types that are not extended. Contrast with [ExtMode], which defines the widths from and to which
-/// values can be extended.
-#[allow(dead_code)]
-#[derive(Clone, PartialEq)]
-pub enum ExtKind {
-    None,
-    SignExtend,
-    ZeroExtend,
-}
-
-/// These indicate ways of extending (widening) a value, using the Intel
-/// naming: B(yte) = u8, W(ord) = u16, L(ong)word = u32, Q(uad)word = u64
-#[derive(Clone, PartialEq)]
-pub enum ExtMode {
-    /// Byte -> Longword.
-    BL,
-    /// Byte -> Quadword.
-    BQ,
-    /// Word -> Longword.
-    WL,
-    /// Word -> Quadword.
-    WQ,
-    /// Longword -> Quadword.
-    LQ,
-}
-
-impl ExtMode {
-    /// Calculate the `ExtMode` from passed bit lengths of the from/to types.
-    pub(crate) fn new(from_bits: u16, to_bits: u16) -> Option<ExtMode> {
-        match (from_bits, to_bits) {
-            (1, 8) | (1, 16) | (1, 32) | (8, 16) | (8, 32) => Some(ExtMode::BL),
-            (1, 64) | (8, 64) => Some(ExtMode::BQ),
-            (16, 32) => Some(ExtMode::WL),
-            (16, 64) => Some(ExtMode::WQ),
-            (32, 64) => Some(ExtMode::LQ),
-            _ => None,
-        }
-    }
-
-    /// Return the source register size in bytes.
-    pub(crate) fn src_size(&self) -> u8 {
-        match self {
-            ExtMode::BL | ExtMode::BQ => 1,
-            ExtMode::WL | ExtMode::WQ => 2,
-            ExtMode::LQ => 4,
-        }
-    }
-
-    /// Return the destination register size in bytes.
-    pub(crate) fn dst_size(&self) -> u8 {
-        match self {
-            ExtMode::BL | ExtMode::WL => 4,
-            ExtMode::BQ | ExtMode::WQ | ExtMode::LQ => 8,
-        }
-    }
-}
-
-impl fmt::Debug for ExtMode {
-    fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result {
-        let name = match self {
-            ExtMode::BL => "bl",
-            ExtMode::BQ => "bq",
-            ExtMode::WL => "wl",
-            ExtMode::WQ => "wq",
-            ExtMode::LQ => "lq",
-        };
-        write!(fmt, "{}", name)
-    }
-}
-
-impl fmt::Display for ExtMode {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        fmt::Debug::fmt(self, f)
-    }
-}
-
-/// These indicate the form of a scalar shift/rotate: left, signed right, unsigned right.
-#[derive(Clone, Copy)]
-pub enum ShiftKind {
-    ShiftLeft,
-    /// Inserts zeros in the most significant bits.
-    ShiftRightLogical,
-    /// Replicates the sign bit in the most significant bits.
-    ShiftRightArithmetic,
-    RotateLeft,
-    RotateRight,
-}
-
-impl fmt::Debug for ShiftKind {
-    fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result {
-        let name = match self {
-            ShiftKind::ShiftLeft => "shl",
-            ShiftKind::ShiftRightLogical => "shr",
-            ShiftKind::ShiftRightArithmetic => "sar",
-            ShiftKind::RotateLeft => "rol",
-            ShiftKind::RotateRight => "ror",
-        };
-        write!(fmt, "{}", name)
-    }
-}
-
-impl fmt::Display for ShiftKind {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        fmt::Debug::fmt(self, f)
-    }
-}
-
-/// What kind of division or remainer instruction this is?
-#[derive(Clone)]
-pub enum DivOrRemKind {
-    SignedDiv,
-    UnsignedDiv,
-    SignedRem,
-    UnsignedRem,
-}
-
-impl DivOrRemKind {
-    pub(crate) fn is_signed(&self) -> bool {
-        match self {
-            DivOrRemKind::SignedDiv | DivOrRemKind::SignedRem => true,
-            _ => false,
-        }
-    }
-
-    pub(crate) fn is_div(&self) -> bool {
-        match self {
-            DivOrRemKind::SignedDiv | DivOrRemKind::UnsignedDiv => true,
-            _ => false,
-        }
-    }
-}
-
-/// These indicate condition code tests.  Not all are represented since not all are useful in
-/// compiler-generated code.
-#[derive(Copy, Clone)]
-#[repr(u8)]
-pub enum CC {
-    ///  overflow
-    O = 0,
-    /// no overflow
-    NO = 1,
-
-    /// < unsigned
-    B = 2,
-    /// >= unsigned
-    NB = 3,
-
-    /// zero
-    Z = 4,
-    /// not-zero
-    NZ = 5,
-
-    /// <= unsigned
-    BE = 6,
-    /// > unsigned
-    NBE = 7,
-
-    /// negative
-    S = 8,
-    /// not-negative
-    NS = 9,
-
-    /// < signed
-    L = 12,
-    /// >= signed
-    NL = 13,
-
-    /// <= signed
-    LE = 14,
-    /// > signed
-    NLE = 15,
-
-    /// parity
-    P = 10,
-
-    /// not parity
-    NP = 11,
-}
-
-impl CC {
-    pub(crate) fn from_intcc(intcc: IntCC) -> Self {
-        match intcc {
-            IntCC::Equal => CC::Z,
-            IntCC::NotEqual => CC::NZ,
-            IntCC::SignedGreaterThanOrEqual => CC::NL,
-            IntCC::SignedGreaterThan => CC::NLE,
-            IntCC::SignedLessThanOrEqual => CC::LE,
-            IntCC::SignedLessThan => CC::L,
-            IntCC::UnsignedGreaterThanOrEqual => CC::NB,
-            IntCC::UnsignedGreaterThan => CC::NBE,
-            IntCC::UnsignedLessThanOrEqual => CC::BE,
-            IntCC::UnsignedLessThan => CC::B,
-            IntCC::Overflow => CC::O,
-            IntCC::NotOverflow => CC::NO,
-        }
-    }
-
-    pub(crate) fn invert(&self) -> Self {
-        match self {
-            CC::O => CC::NO,
-            CC::NO => CC::O,
-
-            CC::B => CC::NB,
-            CC::NB => CC::B,
-
-            CC::Z => CC::NZ,
-            CC::NZ => CC::Z,
-
-            CC::BE => CC::NBE,
-            CC::NBE => CC::BE,
-
-            CC::S => CC::NS,
-            CC::NS => CC::S,
-
-            CC::L => CC::NL,
-            CC::NL => CC::L,
-
-            CC::LE => CC::NLE,
-            CC::NLE => CC::LE,
-
-            CC::P => CC::NP,
-            CC::NP => CC::P,
-        }
-    }
-
-    pub(crate) fn from_floatcc(floatcc: FloatCC) -> Self {
-        match floatcc {
-            FloatCC::Ordered => CC::NP,
-            FloatCC::Unordered => CC::P,
-            // Alias for NE
-            FloatCC::OrderedNotEqual => CC::NZ,
-            // Alias for E
-            FloatCC::UnorderedOrEqual => CC::Z,
-            // Alias for A
-            FloatCC::GreaterThan => CC::NBE,
-            // Alias for AE
-            FloatCC::GreaterThanOrEqual => CC::NB,
-            FloatCC::UnorderedOrLessThan => CC::B,
-            FloatCC::UnorderedOrLessThanOrEqual => CC::BE,
-            FloatCC::Equal
-            | FloatCC::NotEqual
-            | FloatCC::LessThan
-            | FloatCC::LessThanOrEqual
-            | FloatCC::UnorderedOrGreaterThan
-            | FloatCC::UnorderedOrGreaterThanOrEqual => panic!(
-                "{:?} can't be lowered to a CC code; treat as special case.",
-                floatcc
-            ),
-        }
-    }
-
-    pub(crate) fn get_enc(self) -> u8 {
-        self as u8
-    }
-}
-
-impl fmt::Debug for CC {
-    fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result {
-        let name = match self {
-            CC::O => "o",
-            CC::NO => "no",
-            CC::B => "b",
-            CC::NB => "nb",
-            CC::Z => "z",
-            CC::NZ => "nz",
-            CC::BE => "be",
-            CC::NBE => "nbe",
-            CC::S => "s",
-            CC::NS => "ns",
-            CC::L => "l",
-            CC::NL => "nl",
-            CC::LE => "le",
-            CC::NLE => "nle",
-            CC::P => "p",
-            CC::NP => "np",
-        };
-        write!(fmt, "{}", name)
-    }
-}
-
-impl fmt::Display for CC {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        fmt::Debug::fmt(self, f)
-    }
-}
-
-/// Encode the ways that floats can be compared. This is used in float comparisons such as `cmpps`,
-/// e.g.; it is distinguished from other float comparisons (e.g. `ucomiss`) in that those use EFLAGS
-/// whereas [FcmpImm] is used as an immediate.
-#[derive(Clone, Copy)]
-pub enum FcmpImm {
-    Equal = 0x00,
-    LessThan = 0x01,
-    LessThanOrEqual = 0x02,
-    Unordered = 0x03,
-    NotEqual = 0x04,
-    UnorderedOrGreaterThanOrEqual = 0x05,
-    UnorderedOrGreaterThan = 0x06,
-    Ordered = 0x07,
-}
-
-impl FcmpImm {
-    pub(crate) fn encode(self) -> u8 {
-        self as u8
-    }
-}
-
-impl From<FloatCC> for FcmpImm {
-    fn from(cond: FloatCC) -> Self {
-        match cond {
-            FloatCC::Equal => FcmpImm::Equal,
-            FloatCC::LessThan => FcmpImm::LessThan,
-            FloatCC::LessThanOrEqual => FcmpImm::LessThanOrEqual,
-            FloatCC::Unordered => FcmpImm::Unordered,
-            FloatCC::NotEqual => FcmpImm::NotEqual,
-            FloatCC::UnorderedOrGreaterThanOrEqual => FcmpImm::UnorderedOrGreaterThanOrEqual,
-            FloatCC::UnorderedOrGreaterThan => FcmpImm::UnorderedOrGreaterThan,
-            FloatCC::Ordered => FcmpImm::Ordered,
-            _ => panic!("unable to create comparison predicate for {}", cond),
-        }
-    }
-}
-
-/// Encode the rounding modes used as part of the Rounding Control field.
-/// Note, these rounding immediates only consider the rounding control field
-/// (i.e. the rounding mode) which only take up the first two bits when encoded.
-/// However the rounding immediate which this field helps make up, also includes
-/// bits 3 and 4 which define the rounding select and precision mask respectively.
-/// These two bits are not defined here and are implictly set to zero when encoded.
-pub(crate) enum RoundImm {
-    RoundNearest = 0x00,
-    RoundDown = 0x01,
-    RoundUp = 0x02,
-    RoundZero = 0x03,
-}
-
-impl RoundImm {
-    pub(crate) fn encode(self) -> u8 {
-        self as u8
-    }
-}
-
-/// An operand's size in bits.
-#[derive(Clone, Copy, PartialEq)]
-pub enum OperandSize {
-    Size8,
-    Size16,
-    Size32,
-    Size64,
-}
-
-impl OperandSize {
-    pub(crate) fn from_bytes(num_bytes: u32) -> Self {
-        match num_bytes {
-            1 => OperandSize::Size8,
-            2 => OperandSize::Size16,
-            4 => OperandSize::Size32,
-            8 => OperandSize::Size64,
-            _ => unreachable!("Invalid OperandSize: {}", num_bytes),
-        }
-    }
-
-    // Computes the OperandSize for a given type.
-    // For vectors, the OperandSize of the lanes is returned.
-    pub(crate) fn from_ty(ty: Type) -> Self {
-        Self::from_bytes(ty.lane_type().bytes())
-    }
-
-    // Check that the value of self is one of the allowed sizes.
-    pub(crate) fn is_one_of(&self, sizes: &[Self]) -> bool {
-        sizes.iter().any(|val| *self == *val)
-    }
-
-    pub(crate) fn to_bytes(&self) -> u8 {
-        match self {
-            Self::Size8 => 1,
-            Self::Size16 => 2,
-            Self::Size32 => 4,
-            Self::Size64 => 8,
-        }
-    }
-
-    pub(crate) fn to_bits(&self) -> u8 {
-        self.to_bytes() * 8
-    }
-}
-
-/// An x64 memory fence kind.
-#[derive(Clone)]
-#[allow(dead_code)]
-pub enum FenceKind {
-    /// `mfence` instruction ("Memory Fence")
-    MFence,
-    /// `lfence` instruction ("Load Fence")
-    LFence,
-    /// `sfence` instruction ("Store Fence")
-    SFence,
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/inst/emit.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/inst/emit.rs
deleted file mode 100644
index 2ff056625..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/inst/emit.rs
+++ /dev/null
@@ -1,2915 +0,0 @@
-use crate::binemit::{Addend, Reloc};
-use crate::ir::immediates::{Ieee32, Ieee64};
-use crate::ir::LibCall;
-use crate::ir::TrapCode;
-use crate::isa::x64::encoding::evex::{EvexInstruction, EvexVectorLength};
-use crate::isa::x64::encoding::rex::{
-    emit_simm, emit_std_enc_enc, emit_std_enc_mem, emit_std_reg_mem, emit_std_reg_reg, int_reg_enc,
-    low8_will_sign_extend_to_32, low8_will_sign_extend_to_64, reg_enc, LegacyPrefixes, OpcodeMap,
-    RexFlags,
-};
-use crate::isa::x64::inst::args::*;
-use crate::isa::x64::inst::*;
-use crate::machinst::{inst_common, MachBuffer, MachInstEmit, MachLabel};
-use core::convert::TryInto;
-use regalloc::{Reg, Writable};
-
-/// A small helper to generate a signed conversion instruction.
-fn emit_signed_cvt(
-    sink: &mut MachBuffer<Inst>,
-    info: &EmitInfo,
-    state: &mut EmitState,
-    src: Reg,
-    dst: Writable<Reg>,
-    to_f64: bool,
-) {
-    // Handle an unsigned int, which is the "easy" case: a signed conversion will do the
-    // right thing.
-    let op = if to_f64 {
-        SseOpcode::Cvtsi2sd
-    } else {
-        SseOpcode::Cvtsi2ss
-    };
-    let inst = Inst::gpr_to_xmm(op, RegMem::reg(src), OperandSize::Size64, dst);
-    inst.emit(sink, info, state);
-}
-
-/// Emits a one way conditional jump if CC is set (true).
-fn one_way_jmp(sink: &mut MachBuffer<Inst>, cc: CC, label: MachLabel) {
-    let cond_start = sink.cur_offset();
-    let cond_disp_off = cond_start + 2;
-    sink.use_label_at_offset(cond_disp_off, label, LabelUse::JmpRel32);
-    sink.put1(0x0F);
-    sink.put1(0x80 + cc.get_enc());
-    sink.put4(0x0);
-}
-
-/// Emits a relocation, attaching the current source location as well.
-fn emit_reloc(
-    sink: &mut MachBuffer<Inst>,
-    state: &EmitState,
-    kind: Reloc,
-    name: &ExternalName,
-    addend: Addend,
-) {
-    let srcloc = state.cur_srcloc();
-    sink.add_reloc(srcloc, kind, name, addend);
-}
-
-/// The top-level emit function.
-///
-/// Important!  Do not add improved (shortened) encoding cases to existing
-/// instructions without also adding tests for those improved encodings.  That
-/// is a dangerous game that leads to hard-to-track-down errors in the emitted
-/// code.
-///
-/// For all instructions, make sure to have test coverage for all of the
-/// following situations.  Do this by creating the cross product resulting from
-/// applying the following rules to each operand:
-///
-/// (1) for any insn that mentions a register: one test using a register from
-///     the group [rax, rcx, rdx, rbx, rsp, rbp, rsi, rdi] and a second one
-///     using a register from the group [r8, r9, r10, r11, r12, r13, r14, r15].
-///     This helps detect incorrect REX prefix construction.
-///
-/// (2) for any insn that mentions a byte register: one test for each of the
-///     four encoding groups [al, cl, dl, bl], [spl, bpl, sil, dil],
-///     [r8b .. r11b] and [r12b .. r15b].  This checks that
-///     apparently-redundant REX prefixes are retained when required.
-///
-/// (3) for any insn that contains an immediate field, check the following
-///     cases: field is zero, field is in simm8 range (-128 .. 127), field is
-///     in simm32 range (-0x8000_0000 .. 0x7FFF_FFFF).  This is because some
-///     instructions that require a 32-bit immediate have a short-form encoding
-///     when the imm is in simm8 range.
-///
-/// Rules (1), (2) and (3) don't apply for registers within address expressions
-/// (`Addr`s).  Those are already pretty well tested, and the registers in them
-/// don't have any effect on the containing instruction (apart from possibly
-/// require REX prefix bits).
-///
-/// When choosing registers for a test, avoid using registers with the same
-/// offset within a given group.  For example, don't use rax and r8, since they
-/// both have the lowest 3 bits as 000, and so the test won't detect errors
-/// where those 3-bit register sub-fields are confused by the emitter.  Instead
-/// use (eg) rax (lo3 = 000) and r9 (lo3 = 001).  Similarly, don't use (eg) cl
-/// and bpl since they have the same offset in their group; use instead (eg) cl
-/// and sil.
-///
-/// For all instructions, also add a test that uses only low-half registers
-/// (rax .. rdi, xmm0 .. xmm7) etc, so as to check that any redundant REX
-/// prefixes are correctly omitted.  This low-half restriction must apply to
-/// _all_ registers in the insn, even those in address expressions.
-///
-/// Following these rules creates large numbers of test cases, but it's the
-/// only way to make the emitter reliable.
-///
-/// Known possible improvements:
-///
-/// * there's a shorter encoding for shl/shr/sar by a 1-bit immediate.  (Do we
-///   care?)
-pub(crate) fn emit(
-    inst: &Inst,
-    sink: &mut MachBuffer<Inst>,
-    info: &EmitInfo,
-    state: &mut EmitState,
-) {
-    let matches_isa_flags = |iset_requirement: &InstructionSet| -> bool {
-        match iset_requirement {
-            // Cranelift assumes SSE2 at least.
-            InstructionSet::SSE | InstructionSet::SSE2 => true,
-            InstructionSet::SSSE3 => info.isa_flags.use_ssse3(),
-            InstructionSet::SSE41 => info.isa_flags.use_sse41(),
-            InstructionSet::SSE42 => info.isa_flags.use_sse42(),
-            InstructionSet::Popcnt => info.isa_flags.use_popcnt(),
-            InstructionSet::Lzcnt => info.isa_flags.use_lzcnt(),
-            InstructionSet::BMI1 => info.isa_flags.use_bmi1(),
-            InstructionSet::BMI2 => info.isa_flags.has_bmi2(),
-            InstructionSet::AVX512BITALG => info.isa_flags.has_avx512bitalg(),
-            InstructionSet::AVX512DQ => info.isa_flags.has_avx512dq(),
-            InstructionSet::AVX512F => info.isa_flags.has_avx512f(),
-            InstructionSet::AVX512VBMI => info.isa_flags.has_avx512vbmi(),
-            InstructionSet::AVX512VL => info.isa_flags.has_avx512vl(),
-        }
-    };
-
-    // Certain instructions may be present in more than one ISA feature set; we must at least match
-    // one of them in the target CPU.
-    let isa_requirements = inst.available_in_any_isa();
-    if !isa_requirements.is_empty() && !isa_requirements.iter().all(matches_isa_flags) {
-        panic!(
-            "Cannot emit inst '{:?}' for target; failed to match ISA requirements: {:?}",
-            inst, isa_requirements
-        )
-    }
-
-    match inst {
-        Inst::AluRmiR {
-            size,
-            op,
-            src1,
-            src2,
-            dst: reg_g,
-        } => {
-            debug_assert_eq!(*src1, reg_g.to_reg());
-            let mut rex = RexFlags::from(*size);
-            if *op == AluRmiROpcode::Mul {
-                // We kinda freeloaded Mul into RMI_R_Op, but it doesn't fit the usual pattern, so
-                // we have to special-case it.
-                match src2.clone().to_reg_mem_imm() {
-                    RegMemImm::Reg { reg: reg_e } => {
-                        emit_std_reg_reg(
-                            sink,
-                            LegacyPrefixes::None,
-                            0x0FAF,
-                            2,
-                            reg_g.to_reg().to_reg(),
-                            reg_e,
-                            rex,
-                        );
-                    }
-
-                    RegMemImm::Mem { addr } => {
-                        let amode = addr.finalize(state, sink);
-                        emit_std_reg_mem(
-                            sink,
-                            state,
-                            info,
-                            LegacyPrefixes::None,
-                            0x0FAF,
-                            2,
-                            reg_g.to_reg().to_reg(),
-                            &amode,
-                            rex,
-                        );
-                    }
-
-                    RegMemImm::Imm { simm32 } => {
-                        let use_imm8 = low8_will_sign_extend_to_32(simm32);
-                        let opcode = if use_imm8 { 0x6B } else { 0x69 };
-                        // Yes, really, reg_g twice.
-                        emit_std_reg_reg(
-                            sink,
-                            LegacyPrefixes::None,
-                            opcode,
-                            1,
-                            reg_g.to_reg().to_reg(),
-                            reg_g.to_reg().to_reg(),
-                            rex,
-                        );
-                        emit_simm(sink, if use_imm8 { 1 } else { 4 }, simm32);
-                    }
-                }
-            } else {
-                let (opcode_r, opcode_m, subopcode_i, is_8bit) = match op {
-                    AluRmiROpcode::Add => (0x01, 0x03, 0, false),
-                    AluRmiROpcode::Adc => (0x11, 0x03, 0, false),
-                    AluRmiROpcode::Sub => (0x29, 0x2B, 5, false),
-                    AluRmiROpcode::Sbb => (0x19, 0x2B, 5, false),
-                    AluRmiROpcode::And => (0x21, 0x23, 4, false),
-                    AluRmiROpcode::Or => (0x09, 0x0B, 1, false),
-                    AluRmiROpcode::Xor => (0x31, 0x33, 6, false),
-                    AluRmiROpcode::And8 => (0x20, 0x22, 4, true),
-                    AluRmiROpcode::Or8 => (0x08, 0x0A, 1, true),
-                    AluRmiROpcode::Mul => panic!("unreachable"),
-                };
-                assert!(!(is_8bit && *size == OperandSize::Size64));
-
-                match src2.clone().to_reg_mem_imm() {
-                    RegMemImm::Reg { reg: reg_e } => {
-                        if is_8bit {
-                            rex.always_emit_if_8bit_needed(reg_e);
-                            rex.always_emit_if_8bit_needed(reg_g.to_reg().to_reg());
-                        }
-                        // GCC/llvm use the swapped operand encoding (viz., the R/RM vs RM/R
-                        // duality). Do this too, so as to be able to compare generated machine
-                        // code easily.
-                        emit_std_reg_reg(
-                            sink,
-                            LegacyPrefixes::None,
-                            opcode_r,
-                            1,
-                            reg_e,
-                            reg_g.to_reg().to_reg(),
-                            rex,
-                        );
-                    }
-
-                    RegMemImm::Mem { addr } => {
-                        if is_8bit {
-                            rex.always_emit_if_8bit_needed(reg_g.to_reg().to_reg());
-                        }
-                        // Here we revert to the "normal" G-E ordering.
-                        let amode = addr.finalize(state, sink);
-                        emit_std_reg_mem(
-                            sink,
-                            state,
-                            info,
-                            LegacyPrefixes::None,
-                            opcode_m,
-                            1,
-                            reg_g.to_reg().to_reg(),
-                            &amode,
-                            rex,
-                        );
-                    }
-
-                    RegMemImm::Imm { simm32 } => {
-                        assert!(!is_8bit);
-                        let use_imm8 = low8_will_sign_extend_to_32(simm32);
-                        let opcode = if use_imm8 { 0x83 } else { 0x81 };
-                        // And also here we use the "normal" G-E ordering.
-                        let enc_g = int_reg_enc(reg_g.to_reg().to_reg());
-                        emit_std_enc_enc(
-                            sink,
-                            LegacyPrefixes::None,
-                            opcode,
-                            1,
-                            subopcode_i,
-                            enc_g,
-                            rex,
-                        );
-                        emit_simm(sink, if use_imm8 { 1 } else { 4 }, simm32);
-                    }
-                }
-            }
-        }
-
-        Inst::UnaryRmR { size, op, src, dst } => {
-            let rex_flags = RexFlags::from(*size);
-            use UnaryRmROpcode::*;
-            let prefix = match size {
-                OperandSize::Size16 => match op {
-                    Bsr | Bsf => LegacyPrefixes::_66,
-                    Lzcnt | Tzcnt | Popcnt => LegacyPrefixes::_66F3,
-                },
-                OperandSize::Size32 | OperandSize::Size64 => match op {
-                    Bsr | Bsf => LegacyPrefixes::None,
-                    Lzcnt | Tzcnt | Popcnt => LegacyPrefixes::_F3,
-                },
-                _ => unreachable!(),
-            };
-
-            let (opcode, num_opcodes) = match op {
-                Bsr => (0x0fbd, 2),
-                Bsf => (0x0fbc, 2),
-                Lzcnt => (0x0fbd, 2),
-                Tzcnt => (0x0fbc, 2),
-                Popcnt => (0x0fb8, 2),
-            };
-
-            match src.clone().into() {
-                RegMem::Reg { reg: src } => emit_std_reg_reg(
-                    sink,
-                    prefix,
-                    opcode,
-                    num_opcodes,
-                    dst.to_reg().to_reg(),
-                    src,
-                    rex_flags,
-                ),
-                RegMem::Mem { addr: src } => {
-                    let amode = src.finalize(state, sink);
-                    emit_std_reg_mem(
-                        sink,
-                        state,
-                        info,
-                        prefix,
-                        opcode,
-                        num_opcodes,
-                        dst.to_reg().to_reg(),
-                        &amode,
-                        rex_flags,
-                    );
-                }
-            }
-        }
-
-        Inst::Not { size, src, dst } => {
-            debug_assert_eq!(*src, dst.to_reg());
-            let rex_flags = RexFlags::from((*size, dst.to_writable_reg().to_reg()));
-            let (opcode, prefix) = match size {
-                OperandSize::Size8 => (0xF6, LegacyPrefixes::None),
-                OperandSize::Size16 => (0xF7, LegacyPrefixes::_66),
-                OperandSize::Size32 => (0xF7, LegacyPrefixes::None),
-                OperandSize::Size64 => (0xF7, LegacyPrefixes::None),
-            };
-
-            let subopcode = 2;
-            let enc_src = int_reg_enc(dst.to_reg());
-            emit_std_enc_enc(sink, prefix, opcode, 1, subopcode, enc_src, rex_flags)
-        }
-
-        Inst::Neg { size, src, dst } => {
-            debug_assert_eq!(*src, dst.to_reg());
-            let rex_flags = RexFlags::from((*size, dst.to_writable_reg().to_reg()));
-            let (opcode, prefix) = match size {
-                OperandSize::Size8 => (0xF6, LegacyPrefixes::None),
-                OperandSize::Size16 => (0xF7, LegacyPrefixes::_66),
-                OperandSize::Size32 => (0xF7, LegacyPrefixes::None),
-                OperandSize::Size64 => (0xF7, LegacyPrefixes::None),
-            };
-
-            let subopcode = 3;
-            let enc_src = int_reg_enc(dst.to_reg());
-            emit_std_enc_enc(sink, prefix, opcode, 1, subopcode, enc_src, rex_flags)
-        }
-
-        Inst::Div {
-            size,
-            signed,
-            dividend,
-            divisor,
-            dst_quotient,
-            dst_remainder,
-        } => {
-            debug_assert_eq!(*dividend, regs::rax());
-            debug_assert_eq!(dst_quotient.to_reg(), regs::rax());
-            debug_assert_eq!(dst_remainder.to_reg(), regs::rdx());
-            let (opcode, prefix) = match size {
-                OperandSize::Size8 => (0xF6, LegacyPrefixes::None),
-                OperandSize::Size16 => (0xF7, LegacyPrefixes::_66),
-                OperandSize::Size32 => (0xF7, LegacyPrefixes::None),
-                OperandSize::Size64 => (0xF7, LegacyPrefixes::None),
-            };
-
-            let loc = state.cur_srcloc();
-            sink.add_trap(loc, TrapCode::IntegerDivisionByZero);
-
-            let subopcode = if *signed { 7 } else { 6 };
-            match divisor.clone().to_reg_mem() {
-                RegMem::Reg { reg } => {
-                    let src = int_reg_enc(reg);
-                    emit_std_enc_enc(
-                        sink,
-                        prefix,
-                        opcode,
-                        1,
-                        subopcode,
-                        src,
-                        RexFlags::from((*size, reg)),
-                    )
-                }
-                RegMem::Mem { addr: src } => {
-                    let amode = src.finalize(state, sink);
-                    emit_std_enc_mem(
-                        sink,
-                        state,
-                        info,
-                        prefix,
-                        opcode,
-                        1,
-                        subopcode,
-                        &amode,
-                        RexFlags::from(*size),
-                    );
-                }
-            }
-        }
-
-        Inst::MulHi {
-            size,
-            signed,
-            src1,
-            src2,
-            dst_lo,
-            dst_hi,
-        } => {
-            debug_assert_eq!(*src1, regs::rax());
-            debug_assert_eq!(dst_lo.to_reg(), regs::rax());
-            debug_assert_eq!(dst_hi.to_reg(), regs::rdx());
-
-            let rex_flags = RexFlags::from(*size);
-            let prefix = match size {
-                OperandSize::Size16 => LegacyPrefixes::_66,
-                OperandSize::Size32 => LegacyPrefixes::None,
-                OperandSize::Size64 => LegacyPrefixes::None,
-                _ => unreachable!(),
-            };
-
-            let subopcode = if *signed { 5 } else { 4 };
-            match src2.clone().to_reg_mem() {
-                RegMem::Reg { reg } => {
-                    let src = int_reg_enc(reg);
-                    emit_std_enc_enc(sink, prefix, 0xF7, 1, subopcode, src, rex_flags)
-                }
-                RegMem::Mem { addr: src } => {
-                    let amode = src.finalize(state, sink);
-                    emit_std_enc_mem(
-                        sink, state, info, prefix, 0xF7, 1, subopcode, &amode, rex_flags,
-                    );
-                }
-            }
-        }
-
-        Inst::SignExtendData { size, src, dst } => {
-            debug_assert_eq!(*src, regs::rax());
-            debug_assert_eq!(dst.to_reg(), regs::rdx());
-            match size {
-                OperandSize::Size8 => {
-                    sink.put1(0x66);
-                    sink.put1(0x98);
-                }
-                OperandSize::Size16 => {
-                    sink.put1(0x66);
-                    sink.put1(0x99);
-                }
-                OperandSize::Size32 => sink.put1(0x99),
-                OperandSize::Size64 => {
-                    sink.put1(0x48);
-                    sink.put1(0x99);
-                }
-            }
-        }
-
-        Inst::CheckedDivOrRemSeq {
-            kind,
-            size,
-            dividend,
-            divisor,
-            tmp,
-            dst_quotient,
-            dst_remainder,
-        } => {
-            debug_assert_eq!(*dividend, regs::rax());
-            debug_assert_eq!(dst_quotient.to_reg(), regs::rax());
-            debug_assert_eq!(dst_remainder.to_reg(), regs::rdx());
-
-            // Generates the following code sequence:
-            //
-            // ;; check divide by zero:
-            // cmp 0 %divisor
-            // jnz $after_trap
-            // ud2
-            // $after_trap:
-            //
-            // ;; for signed modulo/div:
-            // cmp -1 %divisor
-            // jnz $do_op
-            // ;;   for signed modulo, result is 0
-            //    mov #0, %rdx
-            //    j $done
-            // ;;   for signed div, check for integer overflow against INT_MIN of the right size
-            // cmp INT_MIN, %rax
-            // jnz $do_op
-            // ud2
-            //
-            // $do_op:
-            // ;; if signed
-            //     cdq ;; sign-extend from rax into rdx
-            // ;; else
-            //     mov #0, %rdx
-            // idiv %divisor
-            //
-            // $done:
-
-            // Check if the divisor is zero, first.
-            let inst = Inst::cmp_rmi_r(*size, RegMemImm::imm(0), divisor.to_reg().to_reg());
-            inst.emit(sink, info, state);
-
-            let inst = Inst::trap_if(CC::Z, TrapCode::IntegerDivisionByZero);
-            inst.emit(sink, info, state);
-
-            let (do_op, done_label) = if kind.is_signed() {
-                // Now check if the divisor is -1.
-                let inst =
-                    Inst::cmp_rmi_r(*size, RegMemImm::imm(0xffffffff), divisor.to_reg().to_reg());
-                inst.emit(sink, info, state);
-
-                let do_op = sink.get_label();
-
-                // If not equal, jump to do-op.
-                one_way_jmp(sink, CC::NZ, do_op);
-
-                // Here, divisor == -1.
-                if !kind.is_div() {
-                    // x % -1 = 0; put the result into the destination, $rdx.
-                    let done_label = sink.get_label();
-
-                    let inst = Inst::imm(OperandSize::Size64, 0, Writable::from_reg(regs::rdx()));
-                    inst.emit(sink, info, state);
-
-                    let inst = Inst::jmp_known(done_label);
-                    inst.emit(sink, info, state);
-
-                    (Some(do_op), Some(done_label))
-                } else {
-                    // Check for integer overflow.
-                    if *size == OperandSize::Size64 {
-                        let tmp = tmp.expect("temporary for i64 sdiv");
-
-                        let inst = Inst::imm(
-                            OperandSize::Size64,
-                            0x8000000000000000,
-                            tmp.to_writable_reg(),
-                        );
-                        inst.emit(sink, info, state);
-
-                        let inst = Inst::cmp_rmi_r(
-                            OperandSize::Size64,
-                            RegMemImm::reg(tmp.to_reg().to_reg()),
-                            regs::rax(),
-                        );
-                        inst.emit(sink, info, state);
-                    } else {
-                        let inst = Inst::cmp_rmi_r(*size, RegMemImm::imm(0x80000000), regs::rax());
-                        inst.emit(sink, info, state);
-                    }
-
-                    // If not equal, jump over the trap.
-                    let inst = Inst::trap_if(CC::Z, TrapCode::IntegerOverflow);
-                    inst.emit(sink, info, state);
-
-                    (Some(do_op), None)
-                }
-            } else {
-                (None, None)
-            };
-
-            if let Some(do_op) = do_op {
-                sink.bind_label(do_op);
-            }
-
-            // Fill in the high parts:
-            if kind.is_signed() {
-                // sign-extend the sign-bit of rax into rdx, for signed opcodes.
-                let inst = Inst::sign_extend_data(*size);
-                inst.emit(sink, info, state);
-            } else {
-                // zero for unsigned opcodes.
-                let inst = Inst::imm(OperandSize::Size64, 0, Writable::from_reg(regs::rdx()));
-                inst.emit(sink, info, state);
-            }
-
-            let inst = Inst::div(
-                *size,
-                kind.is_signed(),
-                RegMem::reg(divisor.to_reg().to_reg()),
-            );
-            inst.emit(sink, info, state);
-
-            // Lowering takes care of moving the result back into the right register, see comment
-            // there.
-
-            if let Some(done) = done_label {
-                sink.bind_label(done);
-            }
-        }
-
-        Inst::Imm {
-            dst_size,
-            simm64,
-            dst,
-        } => {
-            let enc_dst = int_reg_enc(dst.to_reg());
-            if *dst_size == OperandSize::Size64 {
-                if low32_will_sign_extend_to_64(*simm64) {
-                    // Sign-extended move imm32.
-                    emit_std_enc_enc(
-                        sink,
-                        LegacyPrefixes::None,
-                        0xC7,
-                        1,
-                        /* subopcode */ 0,
-                        enc_dst,
-                        RexFlags::set_w(),
-                    );
-                    sink.put4(*simm64 as u32);
-                } else {
-                    sink.put1(0x48 | ((enc_dst >> 3) & 1));
-                    sink.put1(0xB8 | (enc_dst & 7));
-                    sink.put8(*simm64);
-                }
-            } else {
-                if ((enc_dst >> 3) & 1) == 1 {
-                    sink.put1(0x41);
-                }
-                sink.put1(0xB8 | (enc_dst & 7));
-                sink.put4(*simm64 as u32);
-            }
-        }
-
-        Inst::MovRR { size, src, dst } => {
-            emit_std_reg_reg(
-                sink,
-                LegacyPrefixes::None,
-                0x89,
-                1,
-                src.to_reg(),
-                dst.to_reg().to_reg(),
-                RexFlags::from(*size),
-            );
-        }
-
-        Inst::MovzxRmR { ext_mode, src, dst } => {
-            let (opcodes, num_opcodes, mut rex_flags) = match ext_mode {
-                ExtMode::BL => {
-                    // MOVZBL is (REX.W==0) 0F B6 /r
-                    (0x0FB6, 2, RexFlags::clear_w())
-                }
-                ExtMode::BQ => {
-                    // MOVZBQ is (REX.W==1) 0F B6 /r
-                    // I'm not sure why the Intel manual offers different
-                    // encodings for MOVZBQ than for MOVZBL.  AIUI they should
-                    // achieve the same, since MOVZBL is just going to zero out
-                    // the upper half of the destination anyway.
-                    (0x0FB6, 2, RexFlags::set_w())
-                }
-                ExtMode::WL => {
-                    // MOVZWL is (REX.W==0) 0F B7 /r
-                    (0x0FB7, 2, RexFlags::clear_w())
-                }
-                ExtMode::WQ => {
-                    // MOVZWQ is (REX.W==1) 0F B7 /r
-                    (0x0FB7, 2, RexFlags::set_w())
-                }
-                ExtMode::LQ => {
-                    // This is just a standard 32 bit load, and we rely on the
-                    // default zero-extension rule to perform the extension.
-                    // Note that in reg/reg mode, gcc seems to use the swapped form R/RM, which we
-                    // don't do here, since it's the same encoding size.
-                    // MOV r/m32, r32 is (REX.W==0) 8B /r
-                    (0x8B, 1, RexFlags::clear_w())
-                }
-            };
-
-            match src.clone().to_reg_mem() {
-                RegMem::Reg { reg: src } => {
-                    match ext_mode {
-                        ExtMode::BL | ExtMode::BQ => {
-                            // A redundant REX prefix must be emitted for certain register inputs.
-                            rex_flags.always_emit_if_8bit_needed(src);
-                        }
-                        _ => {}
-                    }
-                    emit_std_reg_reg(
-                        sink,
-                        LegacyPrefixes::None,
-                        opcodes,
-                        num_opcodes,
-                        dst.to_reg().to_reg(),
-                        src,
-                        rex_flags,
-                    )
-                }
-
-                RegMem::Mem { addr: src } => {
-                    let src = &src.finalize(state, sink);
-
-                    emit_std_reg_mem(
-                        sink,
-                        state,
-                        info,
-                        LegacyPrefixes::None,
-                        opcodes,
-                        num_opcodes,
-                        dst.to_reg().to_reg(),
-                        src,
-                        rex_flags,
-                    )
-                }
-            }
-        }
-
-        Inst::Mov64MR { src, dst } => {
-            let src = &src.finalize(state, sink);
-
-            emit_std_reg_mem(
-                sink,
-                state,
-                info,
-                LegacyPrefixes::None,
-                0x8B,
-                1,
-                dst.to_reg().to_reg(),
-                src,
-                RexFlags::set_w(),
-            )
-        }
-
-        Inst::LoadEffectiveAddress { addr, dst } => {
-            let amode = addr.finalize(state, sink);
-
-            emit_std_reg_mem(
-                sink,
-                state,
-                info,
-                LegacyPrefixes::None,
-                0x8D,
-                1,
-                dst.to_reg().to_reg(),
-                &amode,
-                RexFlags::set_w(),
-            );
-        }
-
-        Inst::MovsxRmR { ext_mode, src, dst } => {
-            let (opcodes, num_opcodes, mut rex_flags) = match ext_mode {
-                ExtMode::BL => {
-                    // MOVSBL is (REX.W==0) 0F BE /r
-                    (0x0FBE, 2, RexFlags::clear_w())
-                }
-                ExtMode::BQ => {
-                    // MOVSBQ is (REX.W==1) 0F BE /r
-                    (0x0FBE, 2, RexFlags::set_w())
-                }
-                ExtMode::WL => {
-                    // MOVSWL is (REX.W==0) 0F BF /r
-                    (0x0FBF, 2, RexFlags::clear_w())
-                }
-                ExtMode::WQ => {
-                    // MOVSWQ is (REX.W==1) 0F BF /r
-                    (0x0FBF, 2, RexFlags::set_w())
-                }
-                ExtMode::LQ => {
-                    // MOVSLQ is (REX.W==1) 63 /r
-                    (0x63, 1, RexFlags::set_w())
-                }
-            };
-
-            match src.clone().to_reg_mem() {
-                RegMem::Reg { reg: src } => {
-                    match ext_mode {
-                        ExtMode::BL | ExtMode::BQ => {
-                            // A redundant REX prefix must be emitted for certain register inputs.
-                            rex_flags.always_emit_if_8bit_needed(src);
-                        }
-                        _ => {}
-                    }
-                    emit_std_reg_reg(
-                        sink,
-                        LegacyPrefixes::None,
-                        opcodes,
-                        num_opcodes,
-                        dst.to_reg().to_reg(),
-                        src,
-                        rex_flags,
-                    )
-                }
-
-                RegMem::Mem { addr: src } => {
-                    let src = &src.finalize(state, sink);
-
-                    emit_std_reg_mem(
-                        sink,
-                        state,
-                        info,
-                        LegacyPrefixes::None,
-                        opcodes,
-                        num_opcodes,
-                        dst.to_reg().to_reg(),
-                        src,
-                        rex_flags,
-                    )
-                }
-            }
-        }
-
-        Inst::MovRM { size, src, dst } => {
-            let dst = &dst.finalize(state, sink);
-
-            let prefix = match size {
-                OperandSize::Size16 => LegacyPrefixes::_66,
-                _ => LegacyPrefixes::None,
-            };
-
-            let opcode = match size {
-                OperandSize::Size8 => 0x88,
-                _ => 0x89,
-            };
-
-            // This is one of the few places where the presence of a
-            // redundant REX prefix changes the meaning of the
-            // instruction.
-            let rex = RexFlags::from((*size, src.to_reg()));
-
-            //  8-bit: MOV r8, r/m8 is (REX.W==0) 88 /r
-            // 16-bit: MOV r16, r/m16 is 66 (REX.W==0) 89 /r
-            // 32-bit: MOV r32, r/m32 is (REX.W==0) 89 /r
-            // 64-bit: MOV r64, r/m64 is (REX.W==1) 89 /r
-            emit_std_reg_mem(sink, state, info, prefix, opcode, 1, src.to_reg(), dst, rex);
-        }
-
-        Inst::ShiftR {
-            size,
-            kind,
-            src,
-            num_bits,
-            dst,
-        } => {
-            debug_assert_eq!(*src, dst.to_reg());
-            let subopcode = match kind {
-                ShiftKind::RotateLeft => 0,
-                ShiftKind::RotateRight => 1,
-                ShiftKind::ShiftLeft => 4,
-                ShiftKind::ShiftRightLogical => 5,
-                ShiftKind::ShiftRightArithmetic => 7,
-            };
-            let enc_dst = int_reg_enc(dst.to_reg());
-            let rex_flags = RexFlags::from((*size, dst.to_reg().to_reg()));
-            match num_bits.clone().to_imm8_reg() {
-                Imm8Reg::Reg { reg } => {
-                    debug_assert_eq!(reg, regs::rcx());
-                    let (opcode, prefix) = match size {
-                        OperandSize::Size8 => (0xD2, LegacyPrefixes::None),
-                        OperandSize::Size16 => (0xD3, LegacyPrefixes::_66),
-                        OperandSize::Size32 => (0xD3, LegacyPrefixes::None),
-                        OperandSize::Size64 => (0xD3, LegacyPrefixes::None),
-                    };
-
-                    // SHL/SHR/SAR %cl, reg8 is (REX.W==0) D2 /subopcode
-                    // SHL/SHR/SAR %cl, reg16 is 66 (REX.W==0) D3 /subopcode
-                    // SHL/SHR/SAR %cl, reg32 is (REX.W==0) D3 /subopcode
-                    // SHL/SHR/SAR %cl, reg64 is (REX.W==1) D3 /subopcode
-                    emit_std_enc_enc(sink, prefix, opcode, 1, subopcode, enc_dst, rex_flags);
-                }
-
-                Imm8Reg::Imm8 { imm: num_bits } => {
-                    let (opcode, prefix) = match size {
-                        OperandSize::Size8 => (0xC0, LegacyPrefixes::None),
-                        OperandSize::Size16 => (0xC1, LegacyPrefixes::_66),
-                        OperandSize::Size32 => (0xC1, LegacyPrefixes::None),
-                        OperandSize::Size64 => (0xC1, LegacyPrefixes::None),
-                    };
-
-                    // SHL/SHR/SAR $ib, reg8 is (REX.W==0) C0 /subopcode
-                    // SHL/SHR/SAR $ib, reg16 is 66 (REX.W==0) C1 /subopcode
-                    // SHL/SHR/SAR $ib, reg32 is (REX.W==0) C1 /subopcode ib
-                    // SHL/SHR/SAR $ib, reg64 is (REX.W==1) C1 /subopcode ib
-                    // When the shift amount is 1, there's an even shorter encoding, but we don't
-                    // bother with that nicety here.
-                    emit_std_enc_enc(sink, prefix, opcode, 1, subopcode, enc_dst, rex_flags);
-                    sink.put1(num_bits);
-                }
-            }
-        }
-
-        Inst::XmmRmiReg {
-            opcode,
-            src1,
-            src2,
-            dst,
-        } => {
-            debug_assert_eq!(*src1, dst.to_reg());
-            let rex = RexFlags::clear_w();
-            let prefix = LegacyPrefixes::_66;
-            let src2 = src2.clone().to_reg_mem_imm();
-            if let RegMemImm::Imm { simm32 } = src2 {
-                let (opcode_bytes, reg_digit) = match opcode {
-                    SseOpcode::Psllw => (0x0F71, 6),
-                    SseOpcode::Pslld => (0x0F72, 6),
-                    SseOpcode::Psllq => (0x0F73, 6),
-                    SseOpcode::Psraw => (0x0F71, 4),
-                    SseOpcode::Psrad => (0x0F72, 4),
-                    SseOpcode::Psrlw => (0x0F71, 2),
-                    SseOpcode::Psrld => (0x0F72, 2),
-                    SseOpcode::Psrlq => (0x0F73, 2),
-                    _ => panic!("invalid opcode: {}", opcode),
-                };
-                let dst_enc = reg_enc(dst.to_reg());
-                emit_std_enc_enc(sink, prefix, opcode_bytes, 2, reg_digit, dst_enc, rex);
-                let imm = (simm32)
-                    .try_into()
-                    .expect("the immediate must be convertible to a u8");
-                sink.put1(imm);
-            } else {
-                let opcode_bytes = match opcode {
-                    SseOpcode::Psllw => 0x0FF1,
-                    SseOpcode::Pslld => 0x0FF2,
-                    SseOpcode::Psllq => 0x0FF3,
-                    SseOpcode::Psraw => 0x0FE1,
-                    SseOpcode::Psrad => 0x0FE2,
-                    SseOpcode::Psrlw => 0x0FD1,
-                    SseOpcode::Psrld => 0x0FD2,
-                    SseOpcode::Psrlq => 0x0FD3,
-                    _ => panic!("invalid opcode: {}", opcode),
-                };
-
-                match src2 {
-                    RegMemImm::Reg { reg } => {
-                        emit_std_reg_reg(
-                            sink,
-                            prefix,
-                            opcode_bytes,
-                            2,
-                            dst.to_reg().to_reg(),
-                            reg,
-                            rex,
-                        );
-                    }
-                    RegMemImm::Mem { addr } => {
-                        let addr = &addr.finalize(state, sink);
-                        emit_std_reg_mem(
-                            sink,
-                            state,
-                            info,
-                            prefix,
-                            opcode_bytes,
-                            2,
-                            dst.to_reg().to_reg(),
-                            addr,
-                            rex,
-                        );
-                    }
-                    RegMemImm::Imm { .. } => unreachable!(),
-                }
-            };
-        }
-
-        Inst::CmpRmiR {
-            size,
-            src: src_e,
-            dst: reg_g,
-            opcode,
-        } => {
-            let is_cmp = match opcode {
-                CmpOpcode::Cmp => true,
-                CmpOpcode::Test => false,
-            };
-
-            let mut prefix = LegacyPrefixes::None;
-            if *size == OperandSize::Size16 {
-                prefix = LegacyPrefixes::_66;
-            }
-            // A redundant REX prefix can change the meaning of this instruction.
-            let mut rex = RexFlags::from((*size, reg_g.to_reg()));
-
-            match src_e.clone().to_reg_mem_imm() {
-                RegMemImm::Reg { reg: reg_e } => {
-                    if *size == OperandSize::Size8 {
-                        // Check whether the E register forces the use of a redundant REX.
-                        rex.always_emit_if_8bit_needed(reg_e);
-                    }
-
-                    // Use the swapped operands encoding for CMP, to stay consistent with the output of
-                    // gcc/llvm.
-                    let opcode = match (*size, is_cmp) {
-                        (OperandSize::Size8, true) => 0x38,
-                        (_, true) => 0x39,
-                        (OperandSize::Size8, false) => 0x84,
-                        (_, false) => 0x85,
-                    };
-                    emit_std_reg_reg(sink, prefix, opcode, 1, reg_e, reg_g.to_reg(), rex);
-                }
-
-                RegMemImm::Mem { addr } => {
-                    let addr = &addr.finalize(state, sink);
-                    // Whereas here we revert to the "normal" G-E ordering for CMP.
-                    let opcode = match (*size, is_cmp) {
-                        (OperandSize::Size8, true) => 0x3A,
-                        (_, true) => 0x3B,
-                        (OperandSize::Size8, false) => 0x84,
-                        (_, false) => 0x85,
-                    };
-                    emit_std_reg_mem(
-                        sink,
-                        state,
-                        info,
-                        prefix,
-                        opcode,
-                        1,
-                        reg_g.to_reg(),
-                        addr,
-                        rex,
-                    );
-                }
-
-                RegMemImm::Imm { simm32 } => {
-                    // FIXME JRS 2020Feb11: there are shorter encodings for
-                    // cmp $imm, rax/eax/ax/al.
-                    let use_imm8 = is_cmp && low8_will_sign_extend_to_32(simm32);
-
-                    // And also here we use the "normal" G-E ordering.
-                    let opcode = if is_cmp {
-                        if *size == OperandSize::Size8 {
-                            0x80
-                        } else if use_imm8 {
-                            0x83
-                        } else {
-                            0x81
-                        }
-                    } else {
-                        if *size == OperandSize::Size8 {
-                            0xF6
-                        } else {
-                            0xF7
-                        }
-                    };
-                    let subopcode = if is_cmp { 7 } else { 0 };
-
-                    let enc_g = int_reg_enc(reg_g.to_reg());
-                    emit_std_enc_enc(sink, prefix, opcode, 1, subopcode, enc_g, rex);
-                    emit_simm(sink, if use_imm8 { 1 } else { size.to_bytes() }, simm32);
-                }
-            }
-        }
-
-        Inst::Setcc { cc, dst } => {
-            let opcode = 0x0f90 + cc.get_enc() as u32;
-            let mut rex_flags = RexFlags::clear_w();
-            rex_flags.always_emit();
-            emit_std_enc_enc(
-                sink,
-                LegacyPrefixes::None,
-                opcode,
-                2,
-                0,
-                reg_enc(dst.to_reg()),
-                rex_flags,
-            );
-        }
-
-        Inst::Cmove {
-            size,
-            cc,
-            consequent,
-            alternative,
-            dst,
-        } => {
-            debug_assert_eq!(*alternative, dst.to_reg());
-            let rex_flags = RexFlags::from(*size);
-            let prefix = match size {
-                OperandSize::Size16 => LegacyPrefixes::_66,
-                OperandSize::Size32 => LegacyPrefixes::None,
-                OperandSize::Size64 => LegacyPrefixes::None,
-                _ => unreachable!("invalid size spec for cmove"),
-            };
-            let opcode = 0x0F40 + cc.get_enc() as u32;
-            match consequent.clone().to_reg_mem() {
-                RegMem::Reg { reg } => {
-                    emit_std_reg_reg(
-                        sink,
-                        prefix,
-                        opcode,
-                        2,
-                        dst.to_reg().to_reg(),
-                        reg,
-                        rex_flags,
-                    );
-                }
-                RegMem::Mem { addr } => {
-                    let addr = &addr.finalize(state, sink);
-                    emit_std_reg_mem(
-                        sink,
-                        state,
-                        info,
-                        prefix,
-                        opcode,
-                        2,
-                        dst.to_reg().to_reg(),
-                        addr,
-                        rex_flags,
-                    );
-                }
-            }
-        }
-
-        Inst::XmmCmove {
-            size,
-            cc,
-            consequent,
-            alternative,
-            dst,
-        } => {
-            debug_assert_eq!(*alternative, dst.to_reg());
-
-            // Lowering of the Select IR opcode when the input is an fcmp relies on the fact that
-            // this doesn't clobber flags. Make sure to not do so here.
-            let next = sink.get_label();
-
-            // Jump if cc is *not* set.
-            one_way_jmp(sink, cc.invert(), next);
-
-            let op = if *size == OperandSize::Size64 {
-                SseOpcode::Movsd
-            } else {
-                SseOpcode::Movss
-            };
-            let inst =
-                Inst::xmm_unary_rm_r(op, consequent.clone().to_reg_mem(), dst.to_writable_reg());
-            inst.emit(sink, info, state);
-
-            sink.bind_label(next);
-        }
-
-        Inst::Push64 { src } => {
-            if info.flags.enable_probestack() {
-                sink.add_trap(state.cur_srcloc(), TrapCode::StackOverflow);
-            }
-
-            match src.clone().to_reg_mem_imm() {
-                RegMemImm::Reg { reg } => {
-                    let enc_reg = int_reg_enc(reg);
-                    let rex = 0x40 | ((enc_reg >> 3) & 1);
-                    if rex != 0x40 {
-                        sink.put1(rex);
-                    }
-                    sink.put1(0x50 | (enc_reg & 7));
-                }
-
-                RegMemImm::Mem { addr } => {
-                    let addr = &addr.finalize(state, sink);
-                    emit_std_enc_mem(
-                        sink,
-                        state,
-                        info,
-                        LegacyPrefixes::None,
-                        0xFF,
-                        1,
-                        6, /*subopcode*/
-                        addr,
-                        RexFlags::clear_w(),
-                    );
-                }
-
-                RegMemImm::Imm { simm32 } => {
-                    if low8_will_sign_extend_to_64(simm32) {
-                        sink.put1(0x6A);
-                        sink.put1(simm32 as u8);
-                    } else {
-                        sink.put1(0x68);
-                        sink.put4(simm32);
-                    }
-                }
-            }
-        }
-
-        Inst::Pop64 { dst } => {
-            let enc_dst = int_reg_enc(dst.to_reg());
-            if enc_dst >= 8 {
-                // 0x41 == REX.{W=0, B=1}.  It seems that REX.W is irrelevant here.
-                sink.put1(0x41);
-            }
-            sink.put1(0x58 + (enc_dst & 7));
-        }
-
-        Inst::CallKnown { dest, opcode, .. } => {
-            if info.flags.enable_probestack() {
-                sink.add_trap(state.cur_srcloc(), TrapCode::StackOverflow);
-            }
-            if let Some(s) = state.take_stack_map() {
-                sink.add_stack_map(StackMapExtent::UpcomingBytes(5), s);
-            }
-            sink.put1(0xE8);
-            // The addend adjusts for the difference between the end of the instruction and the
-            // beginning of the immediate field.
-            emit_reloc(sink, state, Reloc::X86CallPCRel4, &dest, -4);
-            sink.put4(0);
-            if opcode.is_call() {
-                let loc = state.cur_srcloc();
-                sink.add_call_site(loc, *opcode);
-            }
-        }
-
-        Inst::CallUnknown { dest, opcode, .. } => {
-            if info.flags.enable_probestack() {
-                sink.add_trap(state.cur_srcloc(), TrapCode::StackOverflow);
-            }
-            let start_offset = sink.cur_offset();
-            match dest {
-                RegMem::Reg { reg } => {
-                    let reg_enc = int_reg_enc(*reg);
-                    emit_std_enc_enc(
-                        sink,
-                        LegacyPrefixes::None,
-                        0xFF,
-                        1,
-                        2, /*subopcode*/
-                        reg_enc,
-                        RexFlags::clear_w(),
-                    );
-                }
-
-                RegMem::Mem { addr } => {
-                    let addr = &addr.finalize(state, sink);
-                    emit_std_enc_mem(
-                        sink,
-                        state,
-                        info,
-                        LegacyPrefixes::None,
-                        0xFF,
-                        1,
-                        2, /*subopcode*/
-                        addr,
-                        RexFlags::clear_w(),
-                    );
-                }
-            }
-            if let Some(s) = state.take_stack_map() {
-                sink.add_stack_map(StackMapExtent::StartedAtOffset(start_offset), s);
-            }
-            if opcode.is_call() {
-                let loc = state.cur_srcloc();
-                sink.add_call_site(loc, *opcode);
-            }
-        }
-
-        Inst::Ret {} => sink.put1(0xC3),
-
-        Inst::JmpKnown { dst } => {
-            let br_start = sink.cur_offset();
-            let br_disp_off = br_start + 1;
-            let br_end = br_start + 5;
-
-            sink.use_label_at_offset(br_disp_off, *dst, LabelUse::JmpRel32);
-            sink.add_uncond_branch(br_start, br_end, *dst);
-
-            sink.put1(0xE9);
-            // Placeholder for the label value.
-            sink.put4(0x0);
-        }
-
-        Inst::JmpIf { cc, taken } => {
-            let cond_start = sink.cur_offset();
-            let cond_disp_off = cond_start + 2;
-
-            sink.use_label_at_offset(cond_disp_off, *taken, LabelUse::JmpRel32);
-            // Since this is not a terminator, don't enroll in the branch inversion mechanism.
-
-            sink.put1(0x0F);
-            sink.put1(0x80 + cc.get_enc());
-            // Placeholder for the label value.
-            sink.put4(0x0);
-        }
-
-        Inst::JmpCond {
-            cc,
-            taken,
-            not_taken,
-        } => {
-            // If taken.
-            let cond_start = sink.cur_offset();
-            let cond_disp_off = cond_start + 2;
-            let cond_end = cond_start + 6;
-
-            sink.use_label_at_offset(cond_disp_off, *taken, LabelUse::JmpRel32);
-            let inverted: [u8; 6] = [0x0F, 0x80 + (cc.invert().get_enc()), 0x00, 0x00, 0x00, 0x00];
-            sink.add_cond_branch(cond_start, cond_end, *taken, &inverted[..]);
-
-            sink.put1(0x0F);
-            sink.put1(0x80 + cc.get_enc());
-            // Placeholder for the label value.
-            sink.put4(0x0);
-
-            // If not taken.
-            let uncond_start = sink.cur_offset();
-            let uncond_disp_off = uncond_start + 1;
-            let uncond_end = uncond_start + 5;
-
-            sink.use_label_at_offset(uncond_disp_off, *not_taken, LabelUse::JmpRel32);
-            sink.add_uncond_branch(uncond_start, uncond_end, *not_taken);
-
-            sink.put1(0xE9);
-            // Placeholder for the label value.
-            sink.put4(0x0);
-        }
-
-        Inst::JmpUnknown { target } => {
-            match target {
-                RegMem::Reg { reg } => {
-                    let reg_enc = int_reg_enc(*reg);
-                    emit_std_enc_enc(
-                        sink,
-                        LegacyPrefixes::None,
-                        0xFF,
-                        1,
-                        4, /*subopcode*/
-                        reg_enc,
-                        RexFlags::clear_w(),
-                    );
-                }
-
-                RegMem::Mem { addr } => {
-                    let addr = &addr.finalize(state, sink);
-                    emit_std_enc_mem(
-                        sink,
-                        state,
-                        info,
-                        LegacyPrefixes::None,
-                        0xFF,
-                        1,
-                        4, /*subopcode*/
-                        addr,
-                        RexFlags::clear_w(),
-                    );
-                }
-            }
-        }
-
-        Inst::JmpTableSeq {
-            idx,
-            tmp1,
-            tmp2,
-            ref targets,
-            default_target,
-            ..
-        } => {
-            // This sequence is *one* instruction in the vcode, and is expanded only here at
-            // emission time, because we cannot allow the regalloc to insert spills/reloads in
-            // the middle; we depend on hardcoded PC-rel addressing below.
-            //
-            // We don't have to worry about emitting islands, because the only label-use type has a
-            // maximum range of 2 GB. If we later consider using shorter-range label references,
-            // this will need to be revisited.
-
-            // Save index in a tmp (the live range of ridx only goes to start of this
-            // sequence; rtmp1 or rtmp2 may overwrite it).
-
-            // We generate the following sequence:
-            // ;; generated by lowering: cmp #jmp_table_size, %idx
-            // jnb $default_target
-            // movl %idx, %tmp2
-            // lea start_of_jump_table_offset(%rip), %tmp1
-            // movslq [%tmp1, %tmp2, 4], %tmp2 ;; shift of 2, viz. multiply index by 4
-            // addq %tmp2, %tmp1
-            // j *%tmp1
-            // $start_of_jump_table:
-            // -- jump table entries
-            one_way_jmp(sink, CC::NB, *default_target); // idx unsigned >= jmp table size
-
-            // Copy the index (and make sure to clear the high 32-bits lane of tmp2).
-            let inst = Inst::movzx_rm_r(ExtMode::LQ, RegMem::reg(*idx), *tmp2);
-            inst.emit(sink, info, state);
-
-            // Load base address of jump table.
-            let start_of_jumptable = sink.get_label();
-            let inst = Inst::lea(Amode::rip_relative(start_of_jumptable), *tmp1);
-            inst.emit(sink, info, state);
-
-            // Load value out of the jump table. It's a relative offset to the target block, so it
-            // might be negative; use a sign-extension.
-            let inst = Inst::movsx_rm_r(
-                ExtMode::LQ,
-                RegMem::mem(Amode::imm_reg_reg_shift(
-                    0,
-                    Gpr::new(tmp1.to_reg()).unwrap(),
-                    Gpr::new(tmp2.to_reg()).unwrap(),
-                    2,
-                )),
-                *tmp2,
-            );
-            inst.emit(sink, info, state);
-
-            // Add base of jump table to jump-table-sourced block offset.
-            let inst = Inst::alu_rmi_r(
-                OperandSize::Size64,
-                AluRmiROpcode::Add,
-                RegMemImm::reg(tmp2.to_reg()),
-                *tmp1,
-            );
-            inst.emit(sink, info, state);
-
-            // Branch to computed address.
-            let inst = Inst::jmp_unknown(RegMem::reg(tmp1.to_reg()));
-            inst.emit(sink, info, state);
-
-            // Emit jump table (table of 32-bit offsets).
-            sink.bind_label(start_of_jumptable);
-            let jt_off = sink.cur_offset();
-            for &target in targets.iter() {
-                let word_off = sink.cur_offset();
-                // off_into_table is an addend here embedded in the label to be later patched at
-                // the end of codegen. The offset is initially relative to this jump table entry;
-                // with the extra addend, it'll be relative to the jump table's start, after
-                // patching.
-                let off_into_table = word_off - jt_off;
-                sink.use_label_at_offset(word_off, target, LabelUse::PCRel32);
-                sink.put4(off_into_table);
-            }
-        }
-
-        Inst::TrapIf { cc, trap_code } => {
-            let else_label = sink.get_label();
-
-            // Jump over if the invert of CC is set (i.e. CC is not set).
-            one_way_jmp(sink, cc.invert(), else_label);
-
-            // Trap!
-            let inst = Inst::trap(*trap_code);
-            inst.emit(sink, info, state);
-
-            sink.bind_label(else_label);
-        }
-
-        Inst::XmmUnaryRmR {
-            op,
-            src: src_e,
-            dst: reg_g,
-        } => {
-            let rex = RexFlags::clear_w();
-
-            let (prefix, opcode, num_opcodes) = match op {
-                SseOpcode::Cvtdq2pd => (LegacyPrefixes::_F3, 0x0FE6, 2),
-                SseOpcode::Cvtpd2ps => (LegacyPrefixes::_66, 0x0F5A, 2),
-                SseOpcode::Cvtps2pd => (LegacyPrefixes::None, 0x0F5A, 2),
-                SseOpcode::Cvtss2sd => (LegacyPrefixes::_F3, 0x0F5A, 2),
-                SseOpcode::Cvtsd2ss => (LegacyPrefixes::_F2, 0x0F5A, 2),
-                SseOpcode::Movaps => (LegacyPrefixes::None, 0x0F28, 2),
-                SseOpcode::Movapd => (LegacyPrefixes::_66, 0x0F28, 2),
-                SseOpcode::Movdqa => (LegacyPrefixes::_66, 0x0F6F, 2),
-                SseOpcode::Movdqu => (LegacyPrefixes::_F3, 0x0F6F, 2),
-                SseOpcode::Movsd => (LegacyPrefixes::_F2, 0x0F10, 2),
-                SseOpcode::Movss => (LegacyPrefixes::_F3, 0x0F10, 2),
-                SseOpcode::Movups => (LegacyPrefixes::None, 0x0F10, 2),
-                SseOpcode::Movupd => (LegacyPrefixes::_66, 0x0F10, 2),
-                SseOpcode::Pabsb => (LegacyPrefixes::_66, 0x0F381C, 3),
-                SseOpcode::Pabsw => (LegacyPrefixes::_66, 0x0F381D, 3),
-                SseOpcode::Pabsd => (LegacyPrefixes::_66, 0x0F381E, 3),
-                SseOpcode::Pmovsxbd => (LegacyPrefixes::_66, 0x0F3821, 3),
-                SseOpcode::Pmovsxbw => (LegacyPrefixes::_66, 0x0F3820, 3),
-                SseOpcode::Pmovsxbq => (LegacyPrefixes::_66, 0x0F3822, 3),
-                SseOpcode::Pmovsxwd => (LegacyPrefixes::_66, 0x0F3823, 3),
-                SseOpcode::Pmovsxwq => (LegacyPrefixes::_66, 0x0F3824, 3),
-                SseOpcode::Pmovsxdq => (LegacyPrefixes::_66, 0x0F3825, 3),
-                SseOpcode::Pmovzxbd => (LegacyPrefixes::_66, 0x0F3831, 3),
-                SseOpcode::Pmovzxbw => (LegacyPrefixes::_66, 0x0F3830, 3),
-                SseOpcode::Pmovzxbq => (LegacyPrefixes::_66, 0x0F3832, 3),
-                SseOpcode::Pmovzxwd => (LegacyPrefixes::_66, 0x0F3833, 3),
-                SseOpcode::Pmovzxwq => (LegacyPrefixes::_66, 0x0F3834, 3),
-                SseOpcode::Pmovzxdq => (LegacyPrefixes::_66, 0x0F3835, 3),
-                SseOpcode::Sqrtps => (LegacyPrefixes::None, 0x0F51, 2),
-                SseOpcode::Sqrtpd => (LegacyPrefixes::_66, 0x0F51, 2),
-                SseOpcode::Sqrtss => (LegacyPrefixes::_F3, 0x0F51, 2),
-                SseOpcode::Sqrtsd => (LegacyPrefixes::_F2, 0x0F51, 2),
-                _ => unimplemented!("Opcode {:?} not implemented", op),
-            };
-
-            match src_e.clone().to_reg_mem() {
-                RegMem::Reg { reg: reg_e } => {
-                    emit_std_reg_reg(
-                        sink,
-                        prefix,
-                        opcode,
-                        num_opcodes,
-                        reg_g.to_reg().to_reg(),
-                        reg_e,
-                        rex,
-                    );
-                }
-                RegMem::Mem { addr } => {
-                    let addr = &addr.finalize(state, sink);
-                    emit_std_reg_mem(
-                        sink,
-                        state,
-                        info,
-                        prefix,
-                        opcode,
-                        num_opcodes,
-                        reg_g.to_reg().to_reg(),
-                        addr,
-                        rex,
-                    );
-                }
-            };
-        }
-
-        Inst::XmmUnaryRmREvex { op, src, dst } => {
-            let (prefix, map, w, opcode) = match op {
-                Avx512Opcode::Vcvtudq2ps => (LegacyPrefixes::_F2, OpcodeMap::_0F, false, 0x7a),
-                Avx512Opcode::Vpabsq => (LegacyPrefixes::_66, OpcodeMap::_0F38, true, 0x1f),
-                Avx512Opcode::Vpopcntb => (LegacyPrefixes::_66, OpcodeMap::_0F38, false, 0x54),
-                _ => unimplemented!("Opcode {:?} not implemented", op),
-            };
-            match src.clone().to_reg_mem() {
-                RegMem::Reg { reg: src } => EvexInstruction::new()
-                    .length(EvexVectorLength::V128)
-                    .prefix(prefix)
-                    .map(map)
-                    .w(w)
-                    .opcode(opcode)
-                    .reg(dst.to_reg().get_hw_encoding())
-                    .rm(src.get_hw_encoding())
-                    .encode(sink),
-                _ => todo!(),
-            };
-        }
-
-        Inst::XmmRmR {
-            op,
-            src1,
-            src2: src_e,
-            dst: reg_g,
-        } => {
-            debug_assert_eq!(*src1, reg_g.to_reg());
-            let rex = RexFlags::clear_w();
-            let (prefix, opcode, length) = match op {
-                SseOpcode::Addps => (LegacyPrefixes::None, 0x0F58, 2),
-                SseOpcode::Addpd => (LegacyPrefixes::_66, 0x0F58, 2),
-                SseOpcode::Addss => (LegacyPrefixes::_F3, 0x0F58, 2),
-                SseOpcode::Addsd => (LegacyPrefixes::_F2, 0x0F58, 2),
-                SseOpcode::Andps => (LegacyPrefixes::None, 0x0F54, 2),
-                SseOpcode::Andpd => (LegacyPrefixes::_66, 0x0F54, 2),
-                SseOpcode::Andnps => (LegacyPrefixes::None, 0x0F55, 2),
-                SseOpcode::Andnpd => (LegacyPrefixes::_66, 0x0F55, 2),
-                SseOpcode::Blendvps => (LegacyPrefixes::_66, 0x0F3814, 3),
-                SseOpcode::Blendvpd => (LegacyPrefixes::_66, 0x0F3815, 3),
-                SseOpcode::Cvttpd2dq => (LegacyPrefixes::_66, 0x0FE6, 2),
-                SseOpcode::Cvttps2dq => (LegacyPrefixes::_F3, 0x0F5B, 2),
-                SseOpcode::Cvtdq2ps => (LegacyPrefixes::None, 0x0F5B, 2),
-                SseOpcode::Divps => (LegacyPrefixes::None, 0x0F5E, 2),
-                SseOpcode::Divpd => (LegacyPrefixes::_66, 0x0F5E, 2),
-                SseOpcode::Divss => (LegacyPrefixes::_F3, 0x0F5E, 2),
-                SseOpcode::Divsd => (LegacyPrefixes::_F2, 0x0F5E, 2),
-                SseOpcode::Maxps => (LegacyPrefixes::None, 0x0F5F, 2),
-                SseOpcode::Maxpd => (LegacyPrefixes::_66, 0x0F5F, 2),
-                SseOpcode::Maxss => (LegacyPrefixes::_F3, 0x0F5F, 2),
-                SseOpcode::Maxsd => (LegacyPrefixes::_F2, 0x0F5F, 2),
-                SseOpcode::Minps => (LegacyPrefixes::None, 0x0F5D, 2),
-                SseOpcode::Minpd => (LegacyPrefixes::_66, 0x0F5D, 2),
-                SseOpcode::Minss => (LegacyPrefixes::_F3, 0x0F5D, 2),
-                SseOpcode::Minsd => (LegacyPrefixes::_F2, 0x0F5D, 2),
-                SseOpcode::Movlhps => (LegacyPrefixes::None, 0x0F16, 2),
-                SseOpcode::Movsd => (LegacyPrefixes::_F2, 0x0F10, 2),
-                SseOpcode::Mulps => (LegacyPrefixes::None, 0x0F59, 2),
-                SseOpcode::Mulpd => (LegacyPrefixes::_66, 0x0F59, 2),
-                SseOpcode::Mulss => (LegacyPrefixes::_F3, 0x0F59, 2),
-                SseOpcode::Mulsd => (LegacyPrefixes::_F2, 0x0F59, 2),
-                SseOpcode::Orpd => (LegacyPrefixes::_66, 0x0F56, 2),
-                SseOpcode::Orps => (LegacyPrefixes::None, 0x0F56, 2),
-                SseOpcode::Packssdw => (LegacyPrefixes::_66, 0x0F6B, 2),
-                SseOpcode::Packsswb => (LegacyPrefixes::_66, 0x0F63, 2),
-                SseOpcode::Packusdw => (LegacyPrefixes::_66, 0x0F382B, 3),
-                SseOpcode::Packuswb => (LegacyPrefixes::_66, 0x0F67, 2),
-                SseOpcode::Paddb => (LegacyPrefixes::_66, 0x0FFC, 2),
-                SseOpcode::Paddd => (LegacyPrefixes::_66, 0x0FFE, 2),
-                SseOpcode::Paddq => (LegacyPrefixes::_66, 0x0FD4, 2),
-                SseOpcode::Paddw => (LegacyPrefixes::_66, 0x0FFD, 2),
-                SseOpcode::Paddsb => (LegacyPrefixes::_66, 0x0FEC, 2),
-                SseOpcode::Paddsw => (LegacyPrefixes::_66, 0x0FED, 2),
-                SseOpcode::Paddusb => (LegacyPrefixes::_66, 0x0FDC, 2),
-                SseOpcode::Paddusw => (LegacyPrefixes::_66, 0x0FDD, 2),
-                SseOpcode::Pmaddubsw => (LegacyPrefixes::_66, 0x0F3804, 3),
-                SseOpcode::Pand => (LegacyPrefixes::_66, 0x0FDB, 2),
-                SseOpcode::Pandn => (LegacyPrefixes::_66, 0x0FDF, 2),
-                SseOpcode::Pavgb => (LegacyPrefixes::_66, 0x0FE0, 2),
-                SseOpcode::Pavgw => (LegacyPrefixes::_66, 0x0FE3, 2),
-                SseOpcode::Pblendvb => (LegacyPrefixes::_66, 0x0F3810, 3),
-                SseOpcode::Pcmpeqb => (LegacyPrefixes::_66, 0x0F74, 2),
-                SseOpcode::Pcmpeqw => (LegacyPrefixes::_66, 0x0F75, 2),
-                SseOpcode::Pcmpeqd => (LegacyPrefixes::_66, 0x0F76, 2),
-                SseOpcode::Pcmpeqq => (LegacyPrefixes::_66, 0x0F3829, 3),
-                SseOpcode::Pcmpgtb => (LegacyPrefixes::_66, 0x0F64, 2),
-                SseOpcode::Pcmpgtw => (LegacyPrefixes::_66, 0x0F65, 2),
-                SseOpcode::Pcmpgtd => (LegacyPrefixes::_66, 0x0F66, 2),
-                SseOpcode::Pcmpgtq => (LegacyPrefixes::_66, 0x0F3837, 3),
-                SseOpcode::Pmaddwd => (LegacyPrefixes::_66, 0x0FF5, 2),
-                SseOpcode::Pmaxsb => (LegacyPrefixes::_66, 0x0F383C, 3),
-                SseOpcode::Pmaxsw => (LegacyPrefixes::_66, 0x0FEE, 2),
-                SseOpcode::Pmaxsd => (LegacyPrefixes::_66, 0x0F383D, 3),
-                SseOpcode::Pmaxub => (LegacyPrefixes::_66, 0x0FDE, 2),
-                SseOpcode::Pmaxuw => (LegacyPrefixes::_66, 0x0F383E, 3),
-                SseOpcode::Pmaxud => (LegacyPrefixes::_66, 0x0F383F, 3),
-                SseOpcode::Pminsb => (LegacyPrefixes::_66, 0x0F3838, 3),
-                SseOpcode::Pminsw => (LegacyPrefixes::_66, 0x0FEA, 2),
-                SseOpcode::Pminsd => (LegacyPrefixes::_66, 0x0F3839, 3),
-                SseOpcode::Pminub => (LegacyPrefixes::_66, 0x0FDA, 2),
-                SseOpcode::Pminuw => (LegacyPrefixes::_66, 0x0F383A, 3),
-                SseOpcode::Pminud => (LegacyPrefixes::_66, 0x0F383B, 3),
-                SseOpcode::Pmuldq => (LegacyPrefixes::_66, 0x0F3828, 3),
-                SseOpcode::Pmulhw => (LegacyPrefixes::_66, 0x0FE5, 2),
-                SseOpcode::Pmulhrsw => (LegacyPrefixes::_66, 0x0F380B, 3),
-                SseOpcode::Pmulhuw => (LegacyPrefixes::_66, 0x0FE4, 2),
-                SseOpcode::Pmulld => (LegacyPrefixes::_66, 0x0F3840, 3),
-                SseOpcode::Pmullw => (LegacyPrefixes::_66, 0x0FD5, 2),
-                SseOpcode::Pmuludq => (LegacyPrefixes::_66, 0x0FF4, 2),
-                SseOpcode::Por => (LegacyPrefixes::_66, 0x0FEB, 2),
-                SseOpcode::Pshufb => (LegacyPrefixes::_66, 0x0F3800, 3),
-                SseOpcode::Psubb => (LegacyPrefixes::_66, 0x0FF8, 2),
-                SseOpcode::Psubd => (LegacyPrefixes::_66, 0x0FFA, 2),
-                SseOpcode::Psubq => (LegacyPrefixes::_66, 0x0FFB, 2),
-                SseOpcode::Psubw => (LegacyPrefixes::_66, 0x0FF9, 2),
-                SseOpcode::Psubsb => (LegacyPrefixes::_66, 0x0FE8, 2),
-                SseOpcode::Psubsw => (LegacyPrefixes::_66, 0x0FE9, 2),
-                SseOpcode::Psubusb => (LegacyPrefixes::_66, 0x0FD8, 2),
-                SseOpcode::Psubusw => (LegacyPrefixes::_66, 0x0FD9, 2),
-                SseOpcode::Punpckhbw => (LegacyPrefixes::_66, 0x0F68, 2),
-                SseOpcode::Punpckhwd => (LegacyPrefixes::_66, 0x0F69, 2),
-                SseOpcode::Punpcklbw => (LegacyPrefixes::_66, 0x0F60, 2),
-                SseOpcode::Punpcklwd => (LegacyPrefixes::_66, 0x0F61, 2),
-                SseOpcode::Pxor => (LegacyPrefixes::_66, 0x0FEF, 2),
-                SseOpcode::Subps => (LegacyPrefixes::None, 0x0F5C, 2),
-                SseOpcode::Subpd => (LegacyPrefixes::_66, 0x0F5C, 2),
-                SseOpcode::Subss => (LegacyPrefixes::_F3, 0x0F5C, 2),
-                SseOpcode::Subsd => (LegacyPrefixes::_F2, 0x0F5C, 2),
-                SseOpcode::Unpcklps => (LegacyPrefixes::None, 0x0F14, 2),
-                SseOpcode::Xorps => (LegacyPrefixes::None, 0x0F57, 2),
-                SseOpcode::Xorpd => (LegacyPrefixes::_66, 0x0F57, 2),
-                _ => unimplemented!("Opcode {:?} not implemented", op),
-            };
-
-            match src_e.clone().to_reg_mem() {
-                RegMem::Reg { reg: reg_e } => {
-                    emit_std_reg_reg(
-                        sink,
-                        prefix,
-                        opcode,
-                        length,
-                        reg_g.to_reg().to_reg(),
-                        reg_e,
-                        rex,
-                    );
-                }
-                RegMem::Mem { addr } => {
-                    let addr = &addr.finalize(state, sink);
-                    emit_std_reg_mem(
-                        sink,
-                        state,
-                        info,
-                        prefix,
-                        opcode,
-                        length,
-                        reg_g.to_reg().to_reg(),
-                        addr,
-                        rex,
-                    );
-                }
-            }
-        }
-
-        Inst::XmmRmREvex {
-            op,
-            src1,
-            src2,
-            dst,
-        } => {
-            let (w, opcode) = match op {
-                Avx512Opcode::Vpermi2b => (false, 0x75),
-                Avx512Opcode::Vpmullq => (true, 0x40),
-                _ => unimplemented!("Opcode {:?} not implemented", op),
-            };
-            match src1.clone().to_reg_mem() {
-                RegMem::Reg { reg: src } => EvexInstruction::new()
-                    .length(EvexVectorLength::V128)
-                    .prefix(LegacyPrefixes::_66)
-                    .map(OpcodeMap::_0F38)
-                    .w(w)
-                    .opcode(opcode)
-                    .reg(dst.to_reg().get_hw_encoding())
-                    .rm(src.get_hw_encoding())
-                    .vvvvv(src2.get_hw_encoding())
-                    .encode(sink),
-                _ => todo!(),
-            };
-        }
-
-        Inst::XmmMinMaxSeq {
-            size,
-            is_min,
-            lhs,
-            rhs,
-            dst,
-        } => {
-            debug_assert_eq!(*rhs, dst.to_reg());
-
-            // Generates the following sequence:
-            // cmpss/cmpsd %lhs, %rhs_dst
-            // jnz do_min_max
-            // jp propagate_nan
-            //
-            // ;; ordered and equal: propagate the sign bit (for -0 vs 0):
-            // {and,or}{ss,sd} %lhs, %rhs_dst
-            // j done
-            //
-            // ;; to get the desired NaN behavior (signalling NaN transformed into a quiet NaN, the
-            // ;; NaN value is returned), we add both inputs.
-            // propagate_nan:
-            // add{ss,sd} %lhs, %rhs_dst
-            // j done
-            //
-            // do_min_max:
-            // {min,max}{ss,sd} %lhs, %rhs_dst
-            //
-            // done:
-            let done = sink.get_label();
-            let propagate_nan = sink.get_label();
-            let do_min_max = sink.get_label();
-
-            let (add_op, cmp_op, and_op, or_op, min_max_op) = match size {
-                OperandSize::Size32 => (
-                    SseOpcode::Addss,
-                    SseOpcode::Ucomiss,
-                    SseOpcode::Andps,
-                    SseOpcode::Orps,
-                    if *is_min {
-                        SseOpcode::Minss
-                    } else {
-                        SseOpcode::Maxss
-                    },
-                ),
-                OperandSize::Size64 => (
-                    SseOpcode::Addsd,
-                    SseOpcode::Ucomisd,
-                    SseOpcode::Andpd,
-                    SseOpcode::Orpd,
-                    if *is_min {
-                        SseOpcode::Minsd
-                    } else {
-                        SseOpcode::Maxsd
-                    },
-                ),
-                _ => unreachable!(),
-            };
-
-            let inst = Inst::xmm_cmp_rm_r(cmp_op, RegMem::reg(lhs.to_reg()), dst.to_reg().to_reg());
-            inst.emit(sink, info, state);
-
-            one_way_jmp(sink, CC::NZ, do_min_max);
-            one_way_jmp(sink, CC::P, propagate_nan);
-
-            // Ordered and equal. The operands are bit-identical unless they are zero
-            // and negative zero. These instructions merge the sign bits in that
-            // case, and are no-ops otherwise.
-            let op = if *is_min { or_op } else { and_op };
-            let inst = Inst::xmm_rm_r(op, RegMem::reg(lhs.to_reg()), dst.to_writable_reg());
-            inst.emit(sink, info, state);
-
-            let inst = Inst::jmp_known(done);
-            inst.emit(sink, info, state);
-
-            // x86's min/max are not symmetric; if either operand is a NaN, they return the
-            // read-only operand: perform an addition between the two operands, which has the
-            // desired NaN propagation effects.
-            sink.bind_label(propagate_nan);
-            let inst = Inst::xmm_rm_r(add_op, RegMem::reg(lhs.to_reg()), dst.to_writable_reg());
-            inst.emit(sink, info, state);
-
-            one_way_jmp(sink, CC::P, done);
-
-            sink.bind_label(do_min_max);
-            let inst = Inst::xmm_rm_r(min_max_op, RegMem::reg(lhs.to_reg()), dst.to_writable_reg());
-            inst.emit(sink, info, state);
-
-            sink.bind_label(done);
-        }
-
-        Inst::XmmRmRImm {
-            op,
-            src1,
-            src2,
-            dst,
-            imm,
-            size,
-        } => {
-            debug_assert_eq!(*src1, dst.to_reg());
-            let (prefix, opcode, len) = match op {
-                SseOpcode::Cmpps => (LegacyPrefixes::None, 0x0FC2, 2),
-                SseOpcode::Cmppd => (LegacyPrefixes::_66, 0x0FC2, 2),
-                SseOpcode::Cmpss => (LegacyPrefixes::_F3, 0x0FC2, 2),
-                SseOpcode::Cmpsd => (LegacyPrefixes::_F2, 0x0FC2, 2),
-                SseOpcode::Insertps => (LegacyPrefixes::_66, 0x0F3A21, 3),
-                SseOpcode::Palignr => (LegacyPrefixes::_66, 0x0F3A0F, 3),
-                SseOpcode::Pinsrb => (LegacyPrefixes::_66, 0x0F3A20, 3),
-                SseOpcode::Pinsrw => (LegacyPrefixes::_66, 0x0FC4, 2),
-                SseOpcode::Pinsrd => (LegacyPrefixes::_66, 0x0F3A22, 3),
-                SseOpcode::Pextrb => (LegacyPrefixes::_66, 0x0F3A14, 3),
-                SseOpcode::Pextrw => (LegacyPrefixes::_66, 0x0FC5, 2),
-                SseOpcode::Pextrd => (LegacyPrefixes::_66, 0x0F3A16, 3),
-                SseOpcode::Pshufd => (LegacyPrefixes::_66, 0x0F70, 2),
-                SseOpcode::Roundps => (LegacyPrefixes::_66, 0x0F3A08, 3),
-                SseOpcode::Roundss => (LegacyPrefixes::_66, 0x0F3A0A, 3),
-                SseOpcode::Roundpd => (LegacyPrefixes::_66, 0x0F3A09, 3),
-                SseOpcode::Roundsd => (LegacyPrefixes::_66, 0x0F3A0B, 3),
-                SseOpcode::Shufps => (LegacyPrefixes::None, 0x0FC6, 2),
-                _ => unimplemented!("Opcode {:?} not implemented", op),
-            };
-            let rex = RexFlags::from(*size);
-            let regs_swapped = match *op {
-                // These opcodes (and not the SSE2 version of PEXTRW) flip the operand
-                // encoding: `dst` in ModRM's r/m, `src` in ModRM's reg field.
-                SseOpcode::Pextrb | SseOpcode::Pextrd => true,
-                // The rest of the opcodes have the customary encoding: `dst` in ModRM's reg,
-                // `src` in ModRM's r/m field.
-                _ => false,
-            };
-            match src2 {
-                RegMem::Reg { reg } => {
-                    if regs_swapped {
-                        emit_std_reg_reg(sink, prefix, opcode, len, *reg, dst.to_reg(), rex);
-                    } else {
-                        emit_std_reg_reg(sink, prefix, opcode, len, dst.to_reg(), *reg, rex);
-                    }
-                }
-                RegMem::Mem { addr } => {
-                    let addr = &addr.finalize(state, sink);
-                    assert!(
-                        !regs_swapped,
-                        "No existing way to encode a mem argument in the ModRM r/m field."
-                    );
-                    emit_std_reg_mem(
-                        sink,
-                        state,
-                        info,
-                        prefix,
-                        opcode,
-                        len,
-                        dst.to_reg(),
-                        addr,
-                        rex,
-                    );
-                }
-            }
-            sink.put1(*imm);
-        }
-
-        Inst::XmmLoadConst { src, dst, ty } => {
-            let load_offset = Amode::rip_relative(sink.get_label_for_constant(*src));
-            let load = Inst::load(*ty, load_offset, *dst, ExtKind::None);
-            load.emit(sink, info, state);
-        }
-
-        Inst::XmmUninitializedValue { .. } => {
-            // This instruction format only exists to declare a register as a `def`; no code is
-            // emitted.
-        }
-
-        Inst::XmmMovRM { op, src, dst } => {
-            let (prefix, opcode) = match op {
-                SseOpcode::Movaps => (LegacyPrefixes::None, 0x0F29),
-                SseOpcode::Movapd => (LegacyPrefixes::_66, 0x0F29),
-                SseOpcode::Movdqu => (LegacyPrefixes::_F3, 0x0F7F),
-                SseOpcode::Movss => (LegacyPrefixes::_F3, 0x0F11),
-                SseOpcode::Movsd => (LegacyPrefixes::_F2, 0x0F11),
-                SseOpcode::Movups => (LegacyPrefixes::None, 0x0F11),
-                SseOpcode::Movupd => (LegacyPrefixes::_66, 0x0F11),
-                _ => unimplemented!("Opcode {:?} not implemented", op),
-            };
-            let dst = &dst.finalize(state, sink);
-            emit_std_reg_mem(
-                sink,
-                state,
-                info,
-                prefix,
-                opcode,
-                2,
-                *src,
-                dst,
-                RexFlags::clear_w(),
-            );
-        }
-
-        Inst::XmmToGpr {
-            op,
-            src,
-            dst,
-            dst_size,
-        } => {
-            let (prefix, opcode, dst_first) = match op {
-                SseOpcode::Cvttss2si => (LegacyPrefixes::_F3, 0x0F2C, true),
-                SseOpcode::Cvttsd2si => (LegacyPrefixes::_F2, 0x0F2C, true),
-                // Movd and movq use the same opcode; the presence of the REX prefix (set below)
-                // actually determines which is used.
-                SseOpcode::Movd | SseOpcode::Movq => (LegacyPrefixes::_66, 0x0F7E, false),
-                SseOpcode::Movmskps => (LegacyPrefixes::None, 0x0F50, true),
-                SseOpcode::Movmskpd => (LegacyPrefixes::_66, 0x0F50, true),
-                SseOpcode::Pmovmskb => (LegacyPrefixes::_66, 0x0FD7, true),
-                _ => panic!("unexpected opcode {:?}", op),
-            };
-            let rex = RexFlags::from(*dst_size);
-            let (src, dst) = if dst_first {
-                (dst.to_reg().to_reg(), src.to_reg())
-            } else {
-                (src.to_reg(), dst.to_reg().to_reg())
-            };
-
-            emit_std_reg_reg(sink, prefix, opcode, 2, src, dst, rex);
-        }
-
-        Inst::GprToXmm {
-            op,
-            src: src_e,
-            dst: reg_g,
-            src_size,
-        } => {
-            let (prefix, opcode) = match op {
-                // Movd and movq use the same opcode; the presence of the REX prefix (set below)
-                // actually determines which is used.
-                SseOpcode::Movd | SseOpcode::Movq => (LegacyPrefixes::_66, 0x0F6E),
-                SseOpcode::Cvtsi2ss => (LegacyPrefixes::_F3, 0x0F2A),
-                SseOpcode::Cvtsi2sd => (LegacyPrefixes::_F2, 0x0F2A),
-                _ => panic!("unexpected opcode {:?}", op),
-            };
-            let rex = RexFlags::from(*src_size);
-            match src_e.clone().to_reg_mem() {
-                RegMem::Reg { reg: reg_e } => {
-                    emit_std_reg_reg(sink, prefix, opcode, 2, reg_g.to_reg().to_reg(), reg_e, rex);
-                }
-                RegMem::Mem { addr } => {
-                    let addr = &addr.finalize(state, sink);
-                    emit_std_reg_mem(
-                        sink,
-                        state,
-                        info,
-                        prefix,
-                        opcode,
-                        2,
-                        reg_g.to_reg().to_reg(),
-                        addr,
-                        rex,
-                    );
-                }
-            }
-        }
-
-        Inst::XmmCmpRmR { op, src, dst } => {
-            let rex = RexFlags::clear_w();
-            let (prefix, opcode, len) = match op {
-                SseOpcode::Ptest => (LegacyPrefixes::_66, 0x0F3817, 3),
-                SseOpcode::Ucomisd => (LegacyPrefixes::_66, 0x0F2E, 2),
-                SseOpcode::Ucomiss => (LegacyPrefixes::None, 0x0F2E, 2),
-                _ => unimplemented!("Emit xmm cmp rm r"),
-            };
-
-            match src.clone().to_reg_mem() {
-                RegMem::Reg { reg } => {
-                    emit_std_reg_reg(sink, prefix, opcode, len, dst.to_reg(), reg, rex);
-                }
-                RegMem::Mem { addr } => {
-                    let addr = &addr.finalize(state, sink);
-                    emit_std_reg_mem(
-                        sink,
-                        state,
-                        info,
-                        prefix,
-                        opcode,
-                        len,
-                        dst.to_reg(),
-                        addr,
-                        rex,
-                    );
-                }
-            }
-        }
-
-        Inst::CvtUint64ToFloatSeq {
-            dst_size,
-            src,
-            dst,
-            tmp_gpr1,
-            tmp_gpr2,
-        } => {
-            // Note: this sequence is specific to 64-bit mode; a 32-bit mode would require a
-            // different sequence.
-            //
-            // Emit the following sequence:
-            //
-            //  cmp 0, %src
-            //  jl handle_negative
-            //
-            //  ;; handle positive, which can't overflow
-            //  cvtsi2sd/cvtsi2ss %src, %dst
-            //  j done
-            //
-            //  ;; handle negative: see below for an explanation of what it's doing.
-            //  handle_negative:
-            //  mov %src, %tmp_gpr1
-            //  shr $1, %tmp_gpr1
-            //  mov %src, %tmp_gpr2
-            //  and $1, %tmp_gpr2
-            //  or %tmp_gpr1, %tmp_gpr2
-            //  cvtsi2sd/cvtsi2ss %tmp_gpr2, %dst
-            //  addsd/addss %dst, %dst
-            //
-            //  done:
-
-            assert_ne!(src, tmp_gpr1);
-            assert_ne!(src, tmp_gpr2);
-            assert_ne!(tmp_gpr1, tmp_gpr2);
-
-            let handle_negative = sink.get_label();
-            let done = sink.get_label();
-
-            // If x seen as a signed int64 is not negative, a signed-conversion will do the right
-            // thing.
-            // TODO use tst src, src here.
-            let inst = Inst::cmp_rmi_r(
-                OperandSize::Size64,
-                RegMemImm::imm(0),
-                src.to_reg().to_reg(),
-            );
-            inst.emit(sink, info, state);
-
-            one_way_jmp(sink, CC::L, handle_negative);
-
-            // Handle a positive int64, which is the "easy" case: a signed conversion will do the
-            // right thing.
-            emit_signed_cvt(
-                sink,
-                info,
-                state,
-                src.to_reg().to_reg(),
-                dst.to_writable_reg(),
-                *dst_size == OperandSize::Size64,
-            );
-
-            let inst = Inst::jmp_known(done);
-            inst.emit(sink, info, state);
-
-            sink.bind_label(handle_negative);
-
-            // Divide x by two to get it in range for the signed conversion, keep the LSB, and
-            // scale it back up on the FP side.
-            let inst = Inst::gen_move(
-                tmp_gpr1.to_writable_reg(),
-                src.to_reg().to_reg(),
-                types::I64,
-            );
-            inst.emit(sink, info, state);
-
-            // tmp_gpr1 := src >> 1
-            let inst = Inst::shift_r(
-                OperandSize::Size64,
-                ShiftKind::ShiftRightLogical,
-                Some(1),
-                tmp_gpr1.to_writable_reg(),
-            );
-            inst.emit(sink, info, state);
-
-            let inst = Inst::gen_move(
-                tmp_gpr2.to_writable_reg(),
-                src.to_reg().to_reg(),
-                types::I64,
-            );
-            inst.emit(sink, info, state);
-
-            let inst = Inst::alu_rmi_r(
-                OperandSize::Size64,
-                AluRmiROpcode::And,
-                RegMemImm::imm(1),
-                tmp_gpr2.to_writable_reg(),
-            );
-            inst.emit(sink, info, state);
-
-            let inst = Inst::alu_rmi_r(
-                OperandSize::Size64,
-                AluRmiROpcode::Or,
-                RegMemImm::reg(tmp_gpr1.to_reg().to_reg()),
-                tmp_gpr2.to_writable_reg(),
-            );
-            inst.emit(sink, info, state);
-
-            emit_signed_cvt(
-                sink,
-                info,
-                state,
-                tmp_gpr2.to_reg().to_reg(),
-                dst.to_writable_reg(),
-                *dst_size == OperandSize::Size64,
-            );
-
-            let add_op = if *dst_size == OperandSize::Size64 {
-                SseOpcode::Addsd
-            } else {
-                SseOpcode::Addss
-            };
-            let inst = Inst::xmm_rm_r(
-                add_op,
-                RegMem::reg(dst.to_reg().to_reg()),
-                dst.to_writable_reg(),
-            );
-            inst.emit(sink, info, state);
-
-            sink.bind_label(done);
-        }
-
-        Inst::CvtFloatToSintSeq {
-            src_size,
-            dst_size,
-            is_saturating,
-            src,
-            dst,
-            tmp_gpr,
-            tmp_xmm,
-        } => {
-            // Emits the following common sequence:
-            //
-            // cvttss2si/cvttsd2si %src, %dst
-            // cmp %dst, 1
-            // jno done
-            //
-            // Then, for saturating conversions:
-            //
-            // ;; check for NaN
-            // cmpss/cmpsd %src, %src
-            // jnp not_nan
-            // xor %dst, %dst
-            //
-            // ;; positive inputs get saturated to INT_MAX; negative ones to INT_MIN, which is
-            // ;; already in %dst.
-            // xorpd %tmp_xmm, %tmp_xmm
-            // cmpss/cmpsd %src, %tmp_xmm
-            // jnb done
-            // mov/movaps $INT_MAX, %dst
-            //
-            // done:
-            //
-            // Then, for non-saturating conversions:
-            //
-            // ;; check for NaN
-            // cmpss/cmpsd %src, %src
-            // jnp not_nan
-            // ud2 trap BadConversionToInteger
-            //
-            // ;; check if INT_MIN was the correct result, against a magic constant:
-            // not_nan:
-            // movaps/mov $magic, %tmp_gpr
-            // movq/movd %tmp_gpr, %tmp_xmm
-            // cmpss/cmpsd %tmp_xmm, %src
-            // jnb/jnbe $check_positive
-            // ud2 trap IntegerOverflow
-            //
-            // ;; if positive, it was a real overflow
-            // check_positive:
-            // xorpd %tmp_xmm, %tmp_xmm
-            // cmpss/cmpsd %src, %tmp_xmm
-            // jnb done
-            // ud2 trap IntegerOverflow
-            //
-            // done:
-
-            let src = src.to_reg();
-
-            let (cast_op, cmp_op, trunc_op) = match src_size {
-                OperandSize::Size64 => (SseOpcode::Movq, SseOpcode::Ucomisd, SseOpcode::Cvttsd2si),
-                OperandSize::Size32 => (SseOpcode::Movd, SseOpcode::Ucomiss, SseOpcode::Cvttss2si),
-                _ => unreachable!(),
-            };
-
-            let done = sink.get_label();
-            let not_nan = sink.get_label();
-
-            // The truncation.
-            let inst = Inst::xmm_to_gpr(trunc_op, src.to_reg(), dst.to_writable_reg(), *dst_size);
-            inst.emit(sink, info, state);
-
-            // Compare against 1, in case of overflow the dst operand was INT_MIN.
-            let inst = Inst::cmp_rmi_r(*dst_size, RegMemImm::imm(1), dst.to_reg().to_reg());
-            inst.emit(sink, info, state);
-
-            one_way_jmp(sink, CC::NO, done); // no overflow => done
-
-            // Check for NaN.
-
-            let inst = Inst::xmm_cmp_rm_r(cmp_op, RegMem::reg(src.to_reg()), src.to_reg());
-            inst.emit(sink, info, state);
-
-            one_way_jmp(sink, CC::NP, not_nan); // go to not_nan if not a NaN
-
-            if *is_saturating {
-                // For NaN, emit 0.
-                let inst = Inst::alu_rmi_r(
-                    *dst_size,
-                    AluRmiROpcode::Xor,
-                    RegMemImm::reg(dst.to_reg().to_reg()),
-                    dst.to_writable_reg(),
-                );
-                inst.emit(sink, info, state);
-
-                let inst = Inst::jmp_known(done);
-                inst.emit(sink, info, state);
-
-                sink.bind_label(not_nan);
-
-                // If the input was positive, saturate to INT_MAX.
-
-                // Zero out tmp_xmm.
-                let inst = Inst::xmm_rm_r(
-                    SseOpcode::Xorpd,
-                    RegMem::reg(tmp_xmm.to_reg().to_reg()),
-                    tmp_xmm.to_writable_reg(),
-                );
-                inst.emit(sink, info, state);
-
-                let inst = Inst::xmm_cmp_rm_r(
-                    cmp_op,
-                    RegMem::reg(src.to_reg()),
-                    tmp_xmm.to_reg().to_reg(),
-                );
-                inst.emit(sink, info, state);
-
-                // Jump if >= to done.
-                one_way_jmp(sink, CC::NB, done);
-
-                // Otherwise, put INT_MAX.
-                if *dst_size == OperandSize::Size64 {
-                    let inst = Inst::imm(
-                        OperandSize::Size64,
-                        0x7fffffffffffffff,
-                        dst.to_writable_reg(),
-                    );
-                    inst.emit(sink, info, state);
-                } else {
-                    let inst = Inst::imm(OperandSize::Size32, 0x7fffffff, dst.to_writable_reg());
-                    inst.emit(sink, info, state);
-                }
-            } else {
-                let check_positive = sink.get_label();
-
-                let inst = Inst::trap(TrapCode::BadConversionToInteger);
-                inst.emit(sink, info, state);
-
-                // Check if INT_MIN was the correct result: determine the smallest floating point
-                // number that would convert to INT_MIN, put it in a temporary register, and compare
-                // against the src register.
-                // If the src register is less (or in some cases, less-or-equal) than the threshold,
-                // trap!
-
-                sink.bind_label(not_nan);
-
-                let mut no_overflow_cc = CC::NB; // >=
-                let output_bits = dst_size.to_bits();
-                match *src_size {
-                    OperandSize::Size32 => {
-                        let cst = Ieee32::pow2(output_bits - 1).neg().bits();
-                        let inst =
-                            Inst::imm(OperandSize::Size32, cst as u64, tmp_gpr.to_writable_reg());
-                        inst.emit(sink, info, state);
-                    }
-                    OperandSize::Size64 => {
-                        // An f64 can represent `i32::min_value() - 1` exactly with precision to spare,
-                        // so there are values less than -2^(N-1) that convert correctly to INT_MIN.
-                        let cst = if output_bits < 64 {
-                            no_overflow_cc = CC::NBE; // >
-                            Ieee64::fcvt_to_sint_negative_overflow(output_bits)
-                        } else {
-                            Ieee64::pow2(output_bits - 1).neg()
-                        };
-                        let inst =
-                            Inst::imm(OperandSize::Size64, cst.bits(), tmp_gpr.to_writable_reg());
-                        inst.emit(sink, info, state);
-                    }
-                    _ => unreachable!(),
-                }
-
-                let inst = Inst::gpr_to_xmm(
-                    cast_op,
-                    RegMem::reg(tmp_gpr.to_reg().to_reg()),
-                    *src_size,
-                    tmp_xmm.to_writable_reg(),
-                );
-                inst.emit(sink, info, state);
-
-                let inst = Inst::xmm_cmp_rm_r(
-                    cmp_op,
-                    RegMem::reg(tmp_xmm.to_reg().to_reg()),
-                    src.to_reg(),
-                );
-                inst.emit(sink, info, state);
-
-                // jump over trap if src >= or > threshold
-                one_way_jmp(sink, no_overflow_cc, check_positive);
-
-                let inst = Inst::trap(TrapCode::IntegerOverflow);
-                inst.emit(sink, info, state);
-
-                // If positive, it was a real overflow.
-
-                sink.bind_label(check_positive);
-
-                // Zero out the tmp_xmm register.
-                let inst = Inst::xmm_rm_r(
-                    SseOpcode::Xorpd,
-                    RegMem::reg(tmp_xmm.to_reg().to_reg()),
-                    tmp_xmm.to_writable_reg(),
-                );
-                inst.emit(sink, info, state);
-
-                let inst = Inst::xmm_cmp_rm_r(
-                    cmp_op,
-                    RegMem::reg(src.to_reg()),
-                    tmp_xmm.to_reg().to_reg(),
-                );
-                inst.emit(sink, info, state);
-
-                one_way_jmp(sink, CC::NB, done); // jump over trap if 0 >= src
-
-                let inst = Inst::trap(TrapCode::IntegerOverflow);
-                inst.emit(sink, info, state);
-            }
-
-            sink.bind_label(done);
-        }
-
-        Inst::CvtFloatToUintSeq {
-            src_size,
-            dst_size,
-            is_saturating,
-            src,
-            dst,
-            tmp_gpr,
-            tmp_xmm,
-        } => {
-            // The only difference in behavior between saturating and non-saturating is how we
-            // handle errors. Emits the following sequence:
-            //
-            // movaps/mov 2**(int_width - 1), %tmp_gpr
-            // movq/movd %tmp_gpr, %tmp_xmm
-            // cmpss/cmpsd %tmp_xmm, %src
-            // jnb is_large
-            //
-            // ;; check for NaN inputs
-            // jnp not_nan
-            // -- non-saturating: ud2 trap BadConversionToInteger
-            // -- saturating: xor %dst, %dst; j done
-            //
-            // not_nan:
-            // cvttss2si/cvttsd2si %src, %dst
-            // cmp 0, %dst
-            // jnl done
-            // -- non-saturating: ud2 trap IntegerOverflow
-            // -- saturating: xor %dst, %dst; j done
-            //
-            // is_large:
-            // subss/subsd %tmp_xmm, %src ; <-- we clobber %src here
-            // cvttss2si/cvttss2sd %tmp_x, %dst
-            // cmp 0, %dst
-            // jnl next_is_large
-            // -- non-saturating: ud2 trap IntegerOverflow
-            // -- saturating: movaps $UINT_MAX, %dst; j done
-            //
-            // next_is_large:
-            // add 2**(int_width -1), %dst ;; 2 instructions for 64-bits integers
-            //
-            // done:
-
-            assert_ne!(tmp_xmm, src, "tmp_xmm clobbers src!");
-
-            let (sub_op, cast_op, cmp_op, trunc_op) = match src_size {
-                OperandSize::Size32 => (
-                    SseOpcode::Subss,
-                    SseOpcode::Movd,
-                    SseOpcode::Ucomiss,
-                    SseOpcode::Cvttss2si,
-                ),
-                OperandSize::Size64 => (
-                    SseOpcode::Subsd,
-                    SseOpcode::Movq,
-                    SseOpcode::Ucomisd,
-                    SseOpcode::Cvttsd2si,
-                ),
-                _ => unreachable!(),
-            };
-
-            let done = sink.get_label();
-
-            let cst = match src_size {
-                OperandSize::Size32 => Ieee32::pow2(dst_size.to_bits() - 1).bits() as u64,
-                OperandSize::Size64 => Ieee64::pow2(dst_size.to_bits() - 1).bits(),
-                _ => unreachable!(),
-            };
-
-            let inst = Inst::imm(*src_size, cst, tmp_gpr.to_writable_reg());
-            inst.emit(sink, info, state);
-
-            let inst = Inst::gpr_to_xmm(
-                cast_op,
-                RegMem::reg(tmp_gpr.to_reg().to_reg()),
-                *src_size,
-                tmp_xmm.to_writable_reg(),
-            );
-            inst.emit(sink, info, state);
-
-            let inst = Inst::xmm_cmp_rm_r(
-                cmp_op,
-                RegMem::reg(tmp_xmm.to_reg().to_reg()),
-                src.to_reg().to_reg(),
-            );
-            inst.emit(sink, info, state);
-
-            let handle_large = sink.get_label();
-            one_way_jmp(sink, CC::NB, handle_large); // jump to handle_large if src >= large_threshold
-
-            let not_nan = sink.get_label();
-            one_way_jmp(sink, CC::NP, not_nan); // jump over trap if not NaN
-
-            if *is_saturating {
-                // Emit 0.
-                let inst = Inst::alu_rmi_r(
-                    *dst_size,
-                    AluRmiROpcode::Xor,
-                    RegMemImm::reg(dst.to_reg().to_reg()),
-                    dst.to_writable_reg(),
-                );
-                inst.emit(sink, info, state);
-
-                let inst = Inst::jmp_known(done);
-                inst.emit(sink, info, state);
-            } else {
-                // Trap.
-                let inst = Inst::trap(TrapCode::BadConversionToInteger);
-                inst.emit(sink, info, state);
-            }
-
-            sink.bind_label(not_nan);
-
-            // Actual truncation for small inputs: if the result is not positive, then we had an
-            // overflow.
-
-            let inst = Inst::xmm_to_gpr(
-                trunc_op,
-                src.to_reg().to_reg(),
-                dst.to_writable_reg(),
-                *dst_size,
-            );
-            inst.emit(sink, info, state);
-
-            let inst = Inst::cmp_rmi_r(*dst_size, RegMemImm::imm(0), dst.to_reg().to_reg());
-            inst.emit(sink, info, state);
-
-            one_way_jmp(sink, CC::NL, done); // if dst >= 0, jump to done
-
-            if *is_saturating {
-                // The input was "small" (< 2**(width -1)), so the only way to get an integer
-                // overflow is because the input was too small: saturate to the min value, i.e. 0.
-                let inst = Inst::alu_rmi_r(
-                    *dst_size,
-                    AluRmiROpcode::Xor,
-                    RegMemImm::reg(dst.to_reg().to_reg()),
-                    dst.to_writable_reg(),
-                );
-                inst.emit(sink, info, state);
-
-                let inst = Inst::jmp_known(done);
-                inst.emit(sink, info, state);
-            } else {
-                // Trap.
-                let inst = Inst::trap(TrapCode::IntegerOverflow);
-                inst.emit(sink, info, state);
-            }
-
-            // Now handle large inputs.
-
-            sink.bind_label(handle_large);
-
-            let inst = Inst::xmm_rm_r(
-                sub_op,
-                RegMem::reg(tmp_xmm.to_reg().to_reg()),
-                src.to_writable_reg(),
-            );
-            inst.emit(sink, info, state);
-
-            let inst = Inst::xmm_to_gpr(
-                trunc_op,
-                src.to_reg().to_reg(),
-                dst.to_writable_reg(),
-                *dst_size,
-            );
-            inst.emit(sink, info, state);
-
-            let inst = Inst::cmp_rmi_r(*dst_size, RegMemImm::imm(0), dst.to_reg().to_reg());
-            inst.emit(sink, info, state);
-
-            let next_is_large = sink.get_label();
-            one_way_jmp(sink, CC::NL, next_is_large); // if dst >= 0, jump to next_is_large
-
-            if *is_saturating {
-                // The input was "large" (>= 2**(width -1)), so the only way to get an integer
-                // overflow is because the input was too large: saturate to the max value.
-                let inst = Inst::imm(
-                    OperandSize::Size64,
-                    if *dst_size == OperandSize::Size64 {
-                        u64::max_value()
-                    } else {
-                        u32::max_value() as u64
-                    },
-                    dst.to_writable_reg(),
-                );
-                inst.emit(sink, info, state);
-
-                let inst = Inst::jmp_known(done);
-                inst.emit(sink, info, state);
-            } else {
-                let inst = Inst::trap(TrapCode::IntegerOverflow);
-                inst.emit(sink, info, state);
-            }
-
-            sink.bind_label(next_is_large);
-
-            if *dst_size == OperandSize::Size64 {
-                let inst = Inst::imm(OperandSize::Size64, 1 << 63, tmp_gpr.to_writable_reg());
-                inst.emit(sink, info, state);
-
-                let inst = Inst::alu_rmi_r(
-                    OperandSize::Size64,
-                    AluRmiROpcode::Add,
-                    RegMemImm::reg(tmp_gpr.to_reg().to_reg()),
-                    dst.to_writable_reg(),
-                );
-                inst.emit(sink, info, state);
-            } else {
-                let inst = Inst::alu_rmi_r(
-                    OperandSize::Size32,
-                    AluRmiROpcode::Add,
-                    RegMemImm::imm(1 << 31),
-                    dst.to_writable_reg(),
-                );
-                inst.emit(sink, info, state);
-            }
-
-            sink.bind_label(done);
-        }
-
-        Inst::LoadExtName { dst, name, offset } => {
-            if info.flags.is_pic() {
-                // Generates: movq symbol@GOTPCREL(%rip), %dst
-                let enc_dst = int_reg_enc(dst.to_reg());
-                sink.put1(0x48 | ((enc_dst >> 3) & 1) << 2);
-                sink.put1(0x8B);
-                sink.put1(0x05 | ((enc_dst & 7) << 3));
-                emit_reloc(sink, state, Reloc::X86GOTPCRel4, name, -4);
-                sink.put4(0);
-                // Offset in the relocation above applies to the address of the *GOT entry*, not
-                // the loaded address; so we emit a separate add or sub instruction if needed.
-                if *offset < 0 {
-                    assert!(*offset >= -i32::MAX as i64);
-                    sink.put1(0x48 | ((enc_dst >> 3) & 1));
-                    sink.put1(0x81);
-                    sink.put1(0xe8 | (enc_dst & 7));
-                    sink.put4((-*offset) as u32);
-                } else if *offset > 0 {
-                    assert!(*offset <= i32::MAX as i64);
-                    sink.put1(0x48 | ((enc_dst >> 3) & 1));
-                    sink.put1(0x81);
-                    sink.put1(0xc0 | (enc_dst & 7));
-                    sink.put4(*offset as u32);
-                }
-            } else {
-                // The full address can be encoded in the register, with a relocation.
-                // Generates: movabsq $name, %dst
-                let enc_dst = int_reg_enc(dst.to_reg());
-                sink.put1(0x48 | ((enc_dst >> 3) & 1));
-                sink.put1(0xB8 | (enc_dst & 7));
-                emit_reloc(sink, state, Reloc::Abs8, name, *offset);
-                if info.flags.emit_all_ones_funcaddrs() {
-                    sink.put8(u64::max_value());
-                } else {
-                    sink.put8(0);
-                }
-            }
-        }
-
-        Inst::LockCmpxchg {
-            ty,
-            replacement,
-            expected,
-            mem,
-            dst_old,
-        } => {
-            debug_assert_eq!(*expected, regs::rax());
-            debug_assert_eq!(dst_old.to_reg(), regs::rax());
-
-            // lock cmpxchg{b,w,l,q} %replacement, (mem)
-            // Note that 0xF0 is the Lock prefix.
-            let (prefix, opcodes) = match *ty {
-                types::I8 => (LegacyPrefixes::_F0, 0x0FB0),
-                types::I16 => (LegacyPrefixes::_66F0, 0x0FB1),
-                types::I32 => (LegacyPrefixes::_F0, 0x0FB1),
-                types::I64 => (LegacyPrefixes::_F0, 0x0FB1),
-                _ => unreachable!(),
-            };
-            let rex = RexFlags::from((OperandSize::from_ty(*ty), *replacement));
-            let amode = mem.finalize(state, sink);
-            emit_std_reg_mem(
-                sink,
-                state,
-                info,
-                prefix,
-                opcodes,
-                2,
-                *replacement,
-                &amode,
-                rex,
-            );
-        }
-
-        Inst::AtomicRmwSeq {
-            ty,
-            op,
-            address,
-            operand,
-            temp,
-            dst_old,
-        } => {
-            debug_assert_eq!(*address, regs::r9());
-            debug_assert_eq!(*operand, regs::r10());
-            debug_assert_eq!(temp.to_reg(), regs::r11());
-            debug_assert_eq!(dst_old.to_reg(), regs::rax());
-
-            // Emit this:
-            //
-            //    mov{zbq,zwq,zlq,q}     (%r9), %rax  // rax = old value
-            //   again:
-            //    movq                   %rax, %r11   // rax = old value, r11 = old value
-            //    `op`q                  %r10, %r11   // rax = old value, r11 = new value
-            //    lock cmpxchg{b,w,l,q}  %r11, (%r9)  // try to store new value
-            //    jnz again // If this is taken, rax will have a "revised" old value
-            //
-            // Operand conventions:
-            //    IN:  %r9 (addr), %r10 (2nd arg for `op`)
-            //    OUT: %rax (old value), %r11 (trashed), %rflags (trashed)
-            //
-            // In the case where the operation is 'xchg', the "`op`q" instruction is instead
-            //   movq                    %r10, %r11
-            // so that we simply write in the destination, the "2nd arg for `op`".
-            let rax = regs::rax();
-            let r9 = regs::r9();
-            let r10 = regs::r10();
-            let r11 = regs::r11();
-            let rax_w = Writable::from_reg(rax);
-            let r11_w = Writable::from_reg(r11);
-            let amode = Amode::imm_reg(0, r9);
-            let again_label = sink.get_label();
-
-            // mov{zbq,zwq,zlq,q} (%r9), %rax
-            // No need to call `add_trap` here, since the `i1` emit will do that.
-            let i1 = Inst::load(*ty, amode.clone(), rax_w, ExtKind::ZeroExtend);
-            i1.emit(sink, info, state);
-
-            // again:
-            sink.bind_label(again_label);
-
-            // movq %rax, %r11
-            let i2 = Inst::mov_r_r(OperandSize::Size64, rax, r11_w);
-            i2.emit(sink, info, state);
-
-            let r10_rmi = RegMemImm::reg(r10);
-            match op {
-                inst_common::AtomicRmwOp::Xchg => {
-                    // movq %r10, %r11
-                    let i3 = Inst::mov_r_r(OperandSize::Size64, r10, r11_w);
-                    i3.emit(sink, info, state);
-                }
-                inst_common::AtomicRmwOp::Nand => {
-                    // andq %r10, %r11
-                    let i3 =
-                        Inst::alu_rmi_r(OperandSize::Size64, AluRmiROpcode::And, r10_rmi, r11_w);
-                    i3.emit(sink, info, state);
-
-                    // notq %r11
-                    let i4 = Inst::not(OperandSize::Size64, r11_w);
-                    i4.emit(sink, info, state);
-                }
-                inst_common::AtomicRmwOp::Umin
-                | inst_common::AtomicRmwOp::Umax
-                | inst_common::AtomicRmwOp::Smin
-                | inst_common::AtomicRmwOp::Smax => {
-                    // cmp %r11, %r10
-                    let i3 = Inst::cmp_rmi_r(OperandSize::from_ty(*ty), RegMemImm::reg(r11), r10);
-                    i3.emit(sink, info, state);
-
-                    // cmovcc %r10, %r11
-                    let cc = match op {
-                        inst_common::AtomicRmwOp::Umin => CC::BE,
-                        inst_common::AtomicRmwOp::Umax => CC::NB,
-                        inst_common::AtomicRmwOp::Smin => CC::LE,
-                        inst_common::AtomicRmwOp::Smax => CC::NL,
-                        _ => unreachable!(),
-                    };
-                    let i4 = Inst::cmove(OperandSize::Size64, cc, RegMem::reg(r10), r11_w);
-                    i4.emit(sink, info, state);
-                }
-                _ => {
-                    // opq %r10, %r11
-                    let alu_op = match op {
-                        inst_common::AtomicRmwOp::Add => AluRmiROpcode::Add,
-                        inst_common::AtomicRmwOp::Sub => AluRmiROpcode::Sub,
-                        inst_common::AtomicRmwOp::And => AluRmiROpcode::And,
-                        inst_common::AtomicRmwOp::Or => AluRmiROpcode::Or,
-                        inst_common::AtomicRmwOp::Xor => AluRmiROpcode::Xor,
-                        inst_common::AtomicRmwOp::Xchg
-                        | inst_common::AtomicRmwOp::Nand
-                        | inst_common::AtomicRmwOp::Umin
-                        | inst_common::AtomicRmwOp::Umax
-                        | inst_common::AtomicRmwOp::Smin
-                        | inst_common::AtomicRmwOp::Smax => unreachable!(),
-                    };
-                    let i3 = Inst::alu_rmi_r(OperandSize::Size64, alu_op, r10_rmi, r11_w);
-                    i3.emit(sink, info, state);
-                }
-            }
-
-            // lock cmpxchg{b,w,l,q} %r11, (%r9)
-            // No need to call `add_trap` here, since the `i4` emit will do that.
-            let i4 = Inst::LockCmpxchg {
-                ty: *ty,
-                replacement: r11,
-                expected: regs::rax(),
-                mem: amode.into(),
-                dst_old: Writable::from_reg(regs::rax()),
-            };
-            i4.emit(sink, info, state);
-
-            // jnz again
-            one_way_jmp(sink, CC::NZ, again_label);
-        }
-
-        Inst::Fence { kind } => {
-            sink.put1(0x0F);
-            sink.put1(0xAE);
-            match kind {
-                FenceKind::MFence => sink.put1(0xF0), // mfence = 0F AE F0
-                FenceKind::LFence => sink.put1(0xE8), // lfence = 0F AE E8
-                FenceKind::SFence => sink.put1(0xF8), // sfence = 0F AE F8
-            }
-        }
-
-        Inst::Hlt => {
-            sink.put1(0xcc);
-        }
-
-        Inst::Ud2 { trap_code } => {
-            let cur_srcloc = state.cur_srcloc();
-            sink.add_trap(cur_srcloc, *trap_code);
-            if let Some(s) = state.take_stack_map() {
-                sink.add_stack_map(StackMapExtent::UpcomingBytes(2), s);
-            }
-            sink.put1(0x0f);
-            sink.put1(0x0b);
-        }
-
-        Inst::VirtualSPOffsetAdj { offset } => {
-            log::trace!(
-                "virtual sp offset adjusted by {} -> {}",
-                offset,
-                state.virtual_sp_offset + offset
-            );
-            state.virtual_sp_offset += offset;
-        }
-
-        Inst::Nop { len } => {
-            // These encodings can all be found in Intel's architecture manual, at the NOP
-            // instruction description.
-            let mut len = *len;
-            while len != 0 {
-                let emitted = u8::min(len, 9);
-                match emitted {
-                    0 => {}
-                    1 => sink.put1(0x90), // NOP
-                    2 => {
-                        // 66 NOP
-                        sink.put1(0x66);
-                        sink.put1(0x90);
-                    }
-                    3 => {
-                        // NOP [EAX]
-                        sink.put1(0x0F);
-                        sink.put1(0x1F);
-                        sink.put1(0x00);
-                    }
-                    4 => {
-                        // NOP 0(EAX), with 0 a 1-byte immediate.
-                        sink.put1(0x0F);
-                        sink.put1(0x1F);
-                        sink.put1(0x40);
-                        sink.put1(0x00);
-                    }
-                    5 => {
-                        // NOP [EAX, EAX, 1]
-                        sink.put1(0x0F);
-                        sink.put1(0x1F);
-                        sink.put1(0x44);
-                        sink.put1(0x00);
-                        sink.put1(0x00);
-                    }
-                    6 => {
-                        // 66 NOP [EAX, EAX, 1]
-                        sink.put1(0x66);
-                        sink.put1(0x0F);
-                        sink.put1(0x1F);
-                        sink.put1(0x44);
-                        sink.put1(0x00);
-                        sink.put1(0x00);
-                    }
-                    7 => {
-                        // NOP 0[EAX], but 0 is a 4 bytes immediate.
-                        sink.put1(0x0F);
-                        sink.put1(0x1F);
-                        sink.put1(0x80);
-                        sink.put1(0x00);
-                        sink.put1(0x00);
-                        sink.put1(0x00);
-                        sink.put1(0x00);
-                    }
-                    8 => {
-                        // NOP 0[EAX, EAX, 1], with 0 a 4 bytes immediate.
-                        sink.put1(0x0F);
-                        sink.put1(0x1F);
-                        sink.put1(0x84);
-                        sink.put1(0x00);
-                        sink.put1(0x00);
-                        sink.put1(0x00);
-                        sink.put1(0x00);
-                        sink.put1(0x00);
-                    }
-                    9 => {
-                        // 66 NOP 0[EAX, EAX, 1], with 0 a 4 bytes immediate.
-                        sink.put1(0x66);
-                        sink.put1(0x0F);
-                        sink.put1(0x1F);
-                        sink.put1(0x84);
-                        sink.put1(0x00);
-                        sink.put1(0x00);
-                        sink.put1(0x00);
-                        sink.put1(0x00);
-                        sink.put1(0x00);
-                    }
-                    _ => unreachable!(),
-                }
-                len -= emitted;
-            }
-        }
-
-        Inst::EpiloguePlaceholder => {
-            // Generate no code.
-        }
-
-        Inst::ElfTlsGetAddr { ref symbol } => {
-            // N.B.: Must be exactly this byte sequence; the linker requires it,
-            // because it must know how to rewrite the bytes.
-
-            // data16 lea gv@tlsgd(%rip),%rdi
-            sink.put1(0x66); // data16
-            sink.put1(0b01001000); // REX.W
-            sink.put1(0x8d); // LEA
-            sink.put1(0x3d); // ModRM byte
-            emit_reloc(sink, state, Reloc::ElfX86_64TlsGd, symbol, -4);
-            sink.put4(0); // offset
-
-            // data16 data16 callq __tls_get_addr-4
-            sink.put1(0x66); // data16
-            sink.put1(0x66); // data16
-            sink.put1(0b01001000); // REX.W
-            sink.put1(0xe8); // CALL
-            emit_reloc(
-                sink,
-                state,
-                Reloc::X86CallPLTRel4,
-                &ExternalName::LibCall(LibCall::ElfTlsGetAddr),
-                -4,
-            );
-            sink.put4(0); // offset
-        }
-
-        Inst::MachOTlsGetAddr { ref symbol } => {
-            // movq gv@tlv(%rip), %rdi
-            sink.put1(0x48); // REX.w
-            sink.put1(0x8b); // MOV
-            sink.put1(0x3d); // ModRM byte
-            emit_reloc(sink, state, Reloc::MachOX86_64Tlv, symbol, -4);
-            sink.put4(0); // offset
-
-            // callq *(%rdi)
-            sink.put1(0xff);
-            sink.put1(0x17);
-        }
-
-        Inst::ValueLabelMarker { .. } => {
-            // Nothing; this is only used to compute debug info.
-        }
-
-        Inst::Unwind { ref inst } => {
-            sink.add_unwind(inst.clone());
-        }
-    }
-
-    state.clear_post_insn();
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/inst/emit_tests.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/inst/emit_tests.rs
deleted file mode 100644
index 154992f0f..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/inst/emit_tests.rs
+++ /dev/null
@@ -1,4747 +0,0 @@
-//! Tests for the emitter
-//!
-//! See comments at the top of `fn x64_emit` for advice on how to create reliable test cases.
-//!
-//! to see stdout: cargo test -- --nocapture
-//!
-//! for this specific case, as of 24 Aug 2020:
-//!
-//! cd to the top of your wasmtime tree, then:
-//!
-//! RUST_BACKTRACE=1 cargo test --features test-programs/test_programs \
-//!   --features experimental_x64 --all --exclude wasmtime-wasi-nn \
-//!   -- isa::x64::inst::emit_tests::test_x64_emit
-
-use super::*;
-use crate::isa::x64;
-use alloc::boxed::Box;
-use alloc::vec::Vec;
-
-impl Inst {
-    fn neg(size: OperandSize, src: Writable<Reg>) -> Inst {
-        debug_assert_eq!(src.to_reg().get_class(), RegClass::I64);
-        Inst::Neg {
-            size,
-            src: Gpr::new(src.to_reg()).unwrap(),
-            dst: WritableGpr::from_writable_reg(src).unwrap(),
-        }
-    }
-}
-
-#[test]
-fn test_x64_emit() {
-    let rax = regs::rax();
-    let rbx = regs::rbx();
-    let rcx = regs::rcx();
-    let rdx = regs::rdx();
-    let rsi = regs::rsi();
-    let rdi = regs::rdi();
-    let rsp = regs::rsp();
-    let rbp = regs::rbp();
-    let r8 = regs::r8();
-    let r9 = regs::r9();
-    let r10 = regs::r10();
-    let r11 = regs::r11();
-    let r12 = regs::r12();
-    let r13 = regs::r13();
-    let r14 = regs::r14();
-    let r15 = regs::r15();
-
-    let xmm0 = regs::xmm0();
-    let xmm1 = regs::xmm1();
-    let xmm2 = regs::xmm2();
-    let xmm3 = regs::xmm3();
-    let xmm4 = regs::xmm4();
-    let xmm5 = regs::xmm5();
-    let xmm6 = regs::xmm6();
-    let xmm7 = regs::xmm7();
-    let xmm8 = regs::xmm8();
-    let xmm9 = regs::xmm9();
-    let xmm10 = regs::xmm10();
-    let xmm11 = regs::xmm11();
-    let xmm12 = regs::xmm12();
-    let xmm13 = regs::xmm13();
-    let xmm14 = regs::xmm14();
-    let xmm15 = regs::xmm15();
-
-    // And Writable<> versions of the same:
-    let w_rax = Writable::<Reg>::from_reg(rax);
-    let w_rbx = Writable::<Reg>::from_reg(rbx);
-    let w_rcx = Writable::<Reg>::from_reg(rcx);
-    let w_rdx = Writable::<Reg>::from_reg(rdx);
-    let w_rsi = Writable::<Reg>::from_reg(rsi);
-    let w_rdi = Writable::<Reg>::from_reg(rdi);
-    let _w_rsp = Writable::<Reg>::from_reg(rsp);
-    let _w_rbp = Writable::<Reg>::from_reg(rbp);
-    let w_r8 = Writable::<Reg>::from_reg(r8);
-    let w_r9 = Writable::<Reg>::from_reg(r9);
-    let _w_r10 = Writable::<Reg>::from_reg(r10);
-    let w_r11 = Writable::<Reg>::from_reg(r11);
-    let w_r12 = Writable::<Reg>::from_reg(r12);
-    let w_r13 = Writable::<Reg>::from_reg(r13);
-    let w_r14 = Writable::<Reg>::from_reg(r14);
-    let w_r15 = Writable::<Reg>::from_reg(r15);
-
-    let w_xmm0 = Writable::<Reg>::from_reg(xmm0);
-    let w_xmm1 = Writable::<Reg>::from_reg(xmm1);
-    let w_xmm2 = Writable::<Reg>::from_reg(xmm2);
-    let w_xmm3 = Writable::<Reg>::from_reg(xmm3);
-    let w_xmm4 = Writable::<Reg>::from_reg(xmm4);
-    let w_xmm5 = Writable::<Reg>::from_reg(xmm5);
-    let w_xmm6 = Writable::<Reg>::from_reg(xmm6);
-    let w_xmm7 = Writable::<Reg>::from_reg(xmm7);
-    let w_xmm8 = Writable::<Reg>::from_reg(xmm8);
-    let w_xmm9 = Writable::<Reg>::from_reg(xmm9);
-    let w_xmm10 = Writable::<Reg>::from_reg(xmm10);
-    let w_xmm11 = Writable::<Reg>::from_reg(xmm11);
-    let w_xmm12 = Writable::<Reg>::from_reg(xmm12);
-    let w_xmm13 = Writable::<Reg>::from_reg(xmm13);
-    let w_xmm14 = Writable::<Reg>::from_reg(xmm14);
-    let w_xmm15 = Writable::<Reg>::from_reg(xmm15);
-
-    let mut insns = Vec::<(Inst, &str, &str)>::new();
-
-    // ========================================================
-    // Cases aimed at checking Addr-esses: IR (Imm + Reg)
-    //
-    // These are just a bunch of loads with all supported (by the emitter)
-    // permutations of address formats.
-    //
-    // Addr_IR, offset zero
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(0, rax), w_rdi),
-        "488B38",
-        "movq    0(%rax), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(0, rbx), w_rdi),
-        "488B3B",
-        "movq    0(%rbx), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(0, rcx), w_rdi),
-        "488B39",
-        "movq    0(%rcx), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(0, rdx), w_rdi),
-        "488B3A",
-        "movq    0(%rdx), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(0, rbp), w_rdi),
-        "488B7D00",
-        "movq    0(%rbp), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(0, rsp), w_rdi),
-        "488B3C24",
-        "movq    0(%rsp), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(0, rsi), w_rdi),
-        "488B3E",
-        "movq    0(%rsi), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(0, rdi), w_rdi),
-        "488B3F",
-        "movq    0(%rdi), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(0, r8), w_rdi),
-        "498B38",
-        "movq    0(%r8), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(0, r9), w_rdi),
-        "498B39",
-        "movq    0(%r9), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(0, r10), w_rdi),
-        "498B3A",
-        "movq    0(%r10), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(0, r11), w_rdi),
-        "498B3B",
-        "movq    0(%r11), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(0, r12), w_rdi),
-        "498B3C24",
-        "movq    0(%r12), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(0, r13), w_rdi),
-        "498B7D00",
-        "movq    0(%r13), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(0, r14), w_rdi),
-        "498B3E",
-        "movq    0(%r14), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(0, r15), w_rdi),
-        "498B3F",
-        "movq    0(%r15), %rdi",
-    ));
-
-    // ========================================================
-    // Addr_IR, offset max simm8
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(127, rax), w_rdi),
-        "488B787F",
-        "movq    127(%rax), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(127, rbx), w_rdi),
-        "488B7B7F",
-        "movq    127(%rbx), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(127, rcx), w_rdi),
-        "488B797F",
-        "movq    127(%rcx), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(127, rdx), w_rdi),
-        "488B7A7F",
-        "movq    127(%rdx), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(127, rbp), w_rdi),
-        "488B7D7F",
-        "movq    127(%rbp), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(127, rsp), w_rdi),
-        "488B7C247F",
-        "movq    127(%rsp), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(127, rsi), w_rdi),
-        "488B7E7F",
-        "movq    127(%rsi), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(127, rdi), w_rdi),
-        "488B7F7F",
-        "movq    127(%rdi), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(127, r8), w_rdi),
-        "498B787F",
-        "movq    127(%r8), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(127, r9), w_rdi),
-        "498B797F",
-        "movq    127(%r9), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(127, r10), w_rdi),
-        "498B7A7F",
-        "movq    127(%r10), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(127, r11), w_rdi),
-        "498B7B7F",
-        "movq    127(%r11), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(127, r12), w_rdi),
-        "498B7C247F",
-        "movq    127(%r12), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(127, r13), w_rdi),
-        "498B7D7F",
-        "movq    127(%r13), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(127, r14), w_rdi),
-        "498B7E7F",
-        "movq    127(%r14), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(127, r15), w_rdi),
-        "498B7F7F",
-        "movq    127(%r15), %rdi",
-    ));
-
-    // ========================================================
-    // Addr_IR, offset min simm8
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, rax), w_rdi),
-        "488B7880",
-        "movq    -128(%rax), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, rbx), w_rdi),
-        "488B7B80",
-        "movq    -128(%rbx), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, rcx), w_rdi),
-        "488B7980",
-        "movq    -128(%rcx), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, rdx), w_rdi),
-        "488B7A80",
-        "movq    -128(%rdx), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, rbp), w_rdi),
-        "488B7D80",
-        "movq    -128(%rbp), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, rsp), w_rdi),
-        "488B7C2480",
-        "movq    -128(%rsp), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, rsi), w_rdi),
-        "488B7E80",
-        "movq    -128(%rsi), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, rdi), w_rdi),
-        "488B7F80",
-        "movq    -128(%rdi), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, r8), w_rdi),
-        "498B7880",
-        "movq    -128(%r8), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, r9), w_rdi),
-        "498B7980",
-        "movq    -128(%r9), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, r10), w_rdi),
-        "498B7A80",
-        "movq    -128(%r10), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, r11), w_rdi),
-        "498B7B80",
-        "movq    -128(%r11), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, r12), w_rdi),
-        "498B7C2480",
-        "movq    -128(%r12), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, r13), w_rdi),
-        "498B7D80",
-        "movq    -128(%r13), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, r14), w_rdi),
-        "498B7E80",
-        "movq    -128(%r14), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-128i32 as u32, r15), w_rdi),
-        "498B7F80",
-        "movq    -128(%r15), %rdi",
-    ));
-
-    // ========================================================
-    // Addr_IR, offset smallest positive simm32
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(128, rax), w_rdi),
-        "488BB880000000",
-        "movq    128(%rax), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(128, rbx), w_rdi),
-        "488BBB80000000",
-        "movq    128(%rbx), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(128, rcx), w_rdi),
-        "488BB980000000",
-        "movq    128(%rcx), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(128, rdx), w_rdi),
-        "488BBA80000000",
-        "movq    128(%rdx), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(128, rbp), w_rdi),
-        "488BBD80000000",
-        "movq    128(%rbp), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(128, rsp), w_rdi),
-        "488BBC2480000000",
-        "movq    128(%rsp), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(128, rsi), w_rdi),
-        "488BBE80000000",
-        "movq    128(%rsi), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(128, rdi), w_rdi),
-        "488BBF80000000",
-        "movq    128(%rdi), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(128, r8), w_rdi),
-        "498BB880000000",
-        "movq    128(%r8), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(128, r9), w_rdi),
-        "498BB980000000",
-        "movq    128(%r9), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(128, r10), w_rdi),
-        "498BBA80000000",
-        "movq    128(%r10), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(128, r11), w_rdi),
-        "498BBB80000000",
-        "movq    128(%r11), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(128, r12), w_rdi),
-        "498BBC2480000000",
-        "movq    128(%r12), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(128, r13), w_rdi),
-        "498BBD80000000",
-        "movq    128(%r13), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(128, r14), w_rdi),
-        "498BBE80000000",
-        "movq    128(%r14), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(128, r15), w_rdi),
-        "498BBF80000000",
-        "movq    128(%r15), %rdi",
-    ));
-
-    // ========================================================
-    // Addr_IR, offset smallest negative simm32
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, rax), w_rdi),
-        "488BB87FFFFFFF",
-        "movq    -129(%rax), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, rbx), w_rdi),
-        "488BBB7FFFFFFF",
-        "movq    -129(%rbx), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, rcx), w_rdi),
-        "488BB97FFFFFFF",
-        "movq    -129(%rcx), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, rdx), w_rdi),
-        "488BBA7FFFFFFF",
-        "movq    -129(%rdx), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, rbp), w_rdi),
-        "488BBD7FFFFFFF",
-        "movq    -129(%rbp), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, rsp), w_rdi),
-        "488BBC247FFFFFFF",
-        "movq    -129(%rsp), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, rsi), w_rdi),
-        "488BBE7FFFFFFF",
-        "movq    -129(%rsi), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, rdi), w_rdi),
-        "488BBF7FFFFFFF",
-        "movq    -129(%rdi), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, r8), w_rdi),
-        "498BB87FFFFFFF",
-        "movq    -129(%r8), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, r9), w_rdi),
-        "498BB97FFFFFFF",
-        "movq    -129(%r9), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, r10), w_rdi),
-        "498BBA7FFFFFFF",
-        "movq    -129(%r10), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, r11), w_rdi),
-        "498BBB7FFFFFFF",
-        "movq    -129(%r11), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, r12), w_rdi),
-        "498BBC247FFFFFFF",
-        "movq    -129(%r12), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, r13), w_rdi),
-        "498BBD7FFFFFFF",
-        "movq    -129(%r13), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, r14), w_rdi),
-        "498BBE7FFFFFFF",
-        "movq    -129(%r14), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-129i32 as u32, r15), w_rdi),
-        "498BBF7FFFFFFF",
-        "movq    -129(%r15), %rdi",
-    ));
-
-    // ========================================================
-    // Addr_IR, offset large positive simm32
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(0x17732077, rax), w_rdi),
-        "488BB877207317",
-        "movq    393420919(%rax), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(0x17732077, rbx), w_rdi),
-        "488BBB77207317",
-        "movq    393420919(%rbx), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(0x17732077, rcx), w_rdi),
-        "488BB977207317",
-        "movq    393420919(%rcx), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(0x17732077, rdx), w_rdi),
-        "488BBA77207317",
-        "movq    393420919(%rdx), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(0x17732077, rbp), w_rdi),
-        "488BBD77207317",
-        "movq    393420919(%rbp), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(0x17732077, rsp), w_rdi),
-        "488BBC2477207317",
-        "movq    393420919(%rsp), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(0x17732077, rsi), w_rdi),
-        "488BBE77207317",
-        "movq    393420919(%rsi), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(0x17732077, rdi), w_rdi),
-        "488BBF77207317",
-        "movq    393420919(%rdi), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(0x17732077, r8), w_rdi),
-        "498BB877207317",
-        "movq    393420919(%r8), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(0x17732077, r9), w_rdi),
-        "498BB977207317",
-        "movq    393420919(%r9), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(0x17732077, r10), w_rdi),
-        "498BBA77207317",
-        "movq    393420919(%r10), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(0x17732077, r11), w_rdi),
-        "498BBB77207317",
-        "movq    393420919(%r11), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(0x17732077, r12), w_rdi),
-        "498BBC2477207317",
-        "movq    393420919(%r12), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(0x17732077, r13), w_rdi),
-        "498BBD77207317",
-        "movq    393420919(%r13), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(0x17732077, r14), w_rdi),
-        "498BBE77207317",
-        "movq    393420919(%r14), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(0x17732077, r15), w_rdi),
-        "498BBF77207317",
-        "movq    393420919(%r15), %rdi",
-    ));
-
-    // ========================================================
-    // Addr_IR, offset large negative simm32
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, rax), w_rdi),
-        "488BB8D9A6BECE",
-        "movq    -826366247(%rax), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, rbx), w_rdi),
-        "488BBBD9A6BECE",
-        "movq    -826366247(%rbx), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, rcx), w_rdi),
-        "488BB9D9A6BECE",
-        "movq    -826366247(%rcx), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, rdx), w_rdi),
-        "488BBAD9A6BECE",
-        "movq    -826366247(%rdx), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, rbp), w_rdi),
-        "488BBDD9A6BECE",
-        "movq    -826366247(%rbp), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, rsp), w_rdi),
-        "488BBC24D9A6BECE",
-        "movq    -826366247(%rsp), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, rsi), w_rdi),
-        "488BBED9A6BECE",
-        "movq    -826366247(%rsi), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, rdi), w_rdi),
-        "488BBFD9A6BECE",
-        "movq    -826366247(%rdi), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, r8), w_rdi),
-        "498BB8D9A6BECE",
-        "movq    -826366247(%r8), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, r9), w_rdi),
-        "498BB9D9A6BECE",
-        "movq    -826366247(%r9), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, r10), w_rdi),
-        "498BBAD9A6BECE",
-        "movq    -826366247(%r10), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, r11), w_rdi),
-        "498BBBD9A6BECE",
-        "movq    -826366247(%r11), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, r12), w_rdi),
-        "498BBC24D9A6BECE",
-        "movq    -826366247(%r12), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, r13), w_rdi),
-        "498BBDD9A6BECE",
-        "movq    -826366247(%r13), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, r14), w_rdi),
-        "498BBED9A6BECE",
-        "movq    -826366247(%r14), %rdi",
-    ));
-    insns.push((
-        Inst::mov64_m_r(Amode::imm_reg(-0x31415927i32 as u32, r15), w_rdi),
-        "498BBFD9A6BECE",
-        "movq    -826366247(%r15), %rdi",
-    ));
-
-    // ========================================================
-    // Cases aimed at checking Addr-esses: IRRS (Imm + Reg + (Reg << Shift))
-    // Note these don't check the case where the index reg is RSP, since we
-    // don't encode any of those.
-    //
-    // Addr_IRRS, offset max simm8
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(127, Gpr::new(rax).unwrap(), Gpr::new(rax).unwrap(), 0),
-            w_r11,
-        ),
-        "4C8B5C007F",
-        "movq    127(%rax,%rax,1), %r11",
-    ));
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(127, Gpr::new(rdi).unwrap(), Gpr::new(rax).unwrap(), 1),
-            w_r11,
-        ),
-        "4C8B5C477F",
-        "movq    127(%rdi,%rax,2), %r11",
-    ));
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(127, Gpr::new(r8).unwrap(), Gpr::new(rax).unwrap(), 2),
-            w_r11,
-        ),
-        "4D8B5C807F",
-        "movq    127(%r8,%rax,4), %r11",
-    ));
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(127, Gpr::new(r15).unwrap(), Gpr::new(rax).unwrap(), 3),
-            w_r11,
-        ),
-        "4D8B5CC77F",
-        "movq    127(%r15,%rax,8), %r11",
-    ));
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(127, Gpr::new(rax).unwrap(), Gpr::new(rdi).unwrap(), 3),
-            w_r11,
-        ),
-        "4C8B5CF87F",
-        "movq    127(%rax,%rdi,8), %r11",
-    ));
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(127, Gpr::new(rdi).unwrap(), Gpr::new(rdi).unwrap(), 2),
-            w_r11,
-        ),
-        "4C8B5CBF7F",
-        "movq    127(%rdi,%rdi,4), %r11",
-    ));
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(127, Gpr::new(r8).unwrap(), Gpr::new(rdi).unwrap(), 1),
-            w_r11,
-        ),
-        "4D8B5C787F",
-        "movq    127(%r8,%rdi,2), %r11",
-    ));
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(127, Gpr::new(r15).unwrap(), Gpr::new(rdi).unwrap(), 0),
-            w_r11,
-        ),
-        "4D8B5C3F7F",
-        "movq    127(%r15,%rdi,1), %r11",
-    ));
-
-    // ========================================================
-    // Addr_IRRS, offset min simm8
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(
-                -128i32 as u32,
-                Gpr::new(rax).unwrap(),
-                Gpr::new(r8).unwrap(),
-                2,
-            ),
-            w_r11,
-        ),
-        "4E8B5C8080",
-        "movq    -128(%rax,%r8,4), %r11",
-    ));
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(
-                -128i32 as u32,
-                Gpr::new(rdi).unwrap(),
-                Gpr::new(r8).unwrap(),
-                3,
-            ),
-            w_r11,
-        ),
-        "4E8B5CC780",
-        "movq    -128(%rdi,%r8,8), %r11",
-    ));
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(
-                -128i32 as u32,
-                Gpr::new(r8).unwrap(),
-                Gpr::new(r8).unwrap(),
-                0,
-            ),
-            w_r11,
-        ),
-        "4F8B5C0080",
-        "movq    -128(%r8,%r8,1), %r11",
-    ));
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(
-                -128i32 as u32,
-                Gpr::new(r15).unwrap(),
-                Gpr::new(r8).unwrap(),
-                1,
-            ),
-            w_r11,
-        ),
-        "4F8B5C4780",
-        "movq    -128(%r15,%r8,2), %r11",
-    ));
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(
-                -128i32 as u32,
-                Gpr::new(rax).unwrap(),
-                Gpr::new(r15).unwrap(),
-                1,
-            ),
-            w_r11,
-        ),
-        "4E8B5C7880",
-        "movq    -128(%rax,%r15,2), %r11",
-    ));
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(
-                -128i32 as u32,
-                Gpr::new(rdi).unwrap(),
-                Gpr::new(r15).unwrap(),
-                0,
-            ),
-            w_r11,
-        ),
-        "4E8B5C3F80",
-        "movq    -128(%rdi,%r15,1), %r11",
-    ));
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(
-                -128i32 as u32,
-                Gpr::new(r8).unwrap(),
-                Gpr::new(r15).unwrap(),
-                3,
-            ),
-            w_r11,
-        ),
-        "4F8B5CF880",
-        "movq    -128(%r8,%r15,8), %r11",
-    ));
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(
-                -128i32 as u32,
-                Gpr::new(r15).unwrap(),
-                Gpr::new(r15).unwrap(),
-                2,
-            ),
-            w_r11,
-        ),
-        "4F8B5CBF80",
-        "movq    -128(%r15,%r15,4), %r11",
-    ));
-
-    // ========================================================
-    // Addr_IRRS, offset large positive simm32
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(
-                0x4f6625be,
-                Gpr::new(rax).unwrap(),
-                Gpr::new(rax).unwrap(),
-                0,
-            ),
-            w_r11,
-        ),
-        "4C8B9C00BE25664F",
-        "movq    1332094398(%rax,%rax,1), %r11",
-    ));
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(
-                0x4f6625be,
-                Gpr::new(rdi).unwrap(),
-                Gpr::new(rax).unwrap(),
-                1,
-            ),
-            w_r11,
-        ),
-        "4C8B9C47BE25664F",
-        "movq    1332094398(%rdi,%rax,2), %r11",
-    ));
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(0x4f6625be, Gpr::new(r8).unwrap(), Gpr::new(rax).unwrap(), 2),
-            w_r11,
-        ),
-        "4D8B9C80BE25664F",
-        "movq    1332094398(%r8,%rax,4), %r11",
-    ));
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(
-                0x4f6625be,
-                Gpr::new(r15).unwrap(),
-                Gpr::new(rax).unwrap(),
-                3,
-            ),
-            w_r11,
-        ),
-        "4D8B9CC7BE25664F",
-        "movq    1332094398(%r15,%rax,8), %r11",
-    ));
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(
-                0x4f6625be,
-                Gpr::new(rax).unwrap(),
-                Gpr::new(rdi).unwrap(),
-                3,
-            ),
-            w_r11,
-        ),
-        "4C8B9CF8BE25664F",
-        "movq    1332094398(%rax,%rdi,8), %r11",
-    ));
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(
-                0x4f6625be,
-                Gpr::new(rdi).unwrap(),
-                Gpr::new(rdi).unwrap(),
-                2,
-            ),
-            w_r11,
-        ),
-        "4C8B9CBFBE25664F",
-        "movq    1332094398(%rdi,%rdi,4), %r11",
-    ));
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(0x4f6625be, Gpr::new(r8).unwrap(), Gpr::new(rdi).unwrap(), 1),
-            w_r11,
-        ),
-        "4D8B9C78BE25664F",
-        "movq    1332094398(%r8,%rdi,2), %r11",
-    ));
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(
-                0x4f6625be,
-                Gpr::new(r15).unwrap(),
-                Gpr::new(rdi).unwrap(),
-                0,
-            ),
-            w_r11,
-        ),
-        "4D8B9C3FBE25664F",
-        "movq    1332094398(%r15,%rdi,1), %r11",
-    ));
-
-    // ========================================================
-    // Addr_IRRS, offset large negative simm32
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(
-                -0x264d1690i32 as u32,
-                Gpr::new(rax).unwrap(),
-                Gpr::new(r8).unwrap(),
-                2,
-            ),
-            w_r11,
-        ),
-        "4E8B9C8070E9B2D9",
-        "movq    -642586256(%rax,%r8,4), %r11",
-    ));
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(
-                -0x264d1690i32 as u32,
-                Gpr::new(rdi).unwrap(),
-                Gpr::new(r8).unwrap(),
-                3,
-            ),
-            w_r11,
-        ),
-        "4E8B9CC770E9B2D9",
-        "movq    -642586256(%rdi,%r8,8), %r11",
-    ));
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(
-                -0x264d1690i32 as u32,
-                Gpr::new(r8).unwrap(),
-                Gpr::new(r8).unwrap(),
-                0,
-            ),
-            w_r11,
-        ),
-        "4F8B9C0070E9B2D9",
-        "movq    -642586256(%r8,%r8,1), %r11",
-    ));
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(
-                -0x264d1690i32 as u32,
-                Gpr::new(r15).unwrap(),
-                Gpr::new(r8).unwrap(),
-                1,
-            ),
-            w_r11,
-        ),
-        "4F8B9C4770E9B2D9",
-        "movq    -642586256(%r15,%r8,2), %r11",
-    ));
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(
-                -0x264d1690i32 as u32,
-                Gpr::new(rax).unwrap(),
-                Gpr::new(r15).unwrap(),
-                1,
-            ),
-            w_r11,
-        ),
-        "4E8B9C7870E9B2D9",
-        "movq    -642586256(%rax,%r15,2), %r11",
-    ));
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(
-                -0x264d1690i32 as u32,
-                Gpr::new(rdi).unwrap(),
-                Gpr::new(r15).unwrap(),
-                0,
-            ),
-            w_r11,
-        ),
-        "4E8B9C3F70E9B2D9",
-        "movq    -642586256(%rdi,%r15,1), %r11",
-    ));
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(
-                -0x264d1690i32 as u32,
-                Gpr::new(r8).unwrap(),
-                Gpr::new(r15).unwrap(),
-                3,
-            ),
-            w_r11,
-        ),
-        "4F8B9CF870E9B2D9",
-        "movq    -642586256(%r8,%r15,8), %r11",
-    ));
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(
-                -0x264d1690i32 as u32,
-                Gpr::new(r15).unwrap(),
-                Gpr::new(r15).unwrap(),
-                2,
-            ),
-            w_r11,
-        ),
-        "4F8B9CBF70E9B2D9",
-        "movq    -642586256(%r15,%r15,4), %r11",
-    ));
-
-    // End of test cases for Addr
-    // ========================================================
-
-    // ========================================================
-    // General tests for each insn.  Don't forget to follow the
-    // guidelines commented just prior to `fn x64_emit`.
-    //
-    // Alu_RMI_R
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size64,
-            AluRmiROpcode::Add,
-            RegMemImm::reg(r15),
-            w_rdx,
-        ),
-        "4C01FA",
-        "addq    %r15, %rdx",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size32,
-            AluRmiROpcode::Add,
-            RegMemImm::reg(rcx),
-            w_r8,
-        ),
-        "4101C8",
-        "addl    %ecx, %r8d",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size32,
-            AluRmiROpcode::Add,
-            RegMemImm::reg(rcx),
-            w_rsi,
-        ),
-        "01CE",
-        "addl    %ecx, %esi",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size64,
-            AluRmiROpcode::Add,
-            RegMemImm::mem(Amode::imm_reg(99, rdi)),
-            w_rdx,
-        ),
-        "48035763",
-        "addq    99(%rdi), %rdx",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size32,
-            AluRmiROpcode::Add,
-            RegMemImm::mem(Amode::imm_reg(99, rdi)),
-            w_r8,
-        ),
-        "44034763",
-        "addl    99(%rdi), %r8d",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size32,
-            AluRmiROpcode::Add,
-            RegMemImm::mem(Amode::imm_reg(99, rdi)),
-            w_rsi,
-        ),
-        "037763",
-        "addl    99(%rdi), %esi",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size64,
-            AluRmiROpcode::Add,
-            RegMemImm::imm(-127i32 as u32),
-            w_rdx,
-        ),
-        "4883C281",
-        "addq    $-127, %rdx",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size64,
-            AluRmiROpcode::Add,
-            RegMemImm::imm(-129i32 as u32),
-            w_rdx,
-        ),
-        "4881C27FFFFFFF",
-        "addq    $-129, %rdx",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size64,
-            AluRmiROpcode::Add,
-            RegMemImm::imm(76543210),
-            w_rdx,
-        ),
-        "4881C2EAF48F04",
-        "addq    $76543210, %rdx",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size32,
-            AluRmiROpcode::Add,
-            RegMemImm::imm(-127i32 as u32),
-            w_r8,
-        ),
-        "4183C081",
-        "addl    $-127, %r8d",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size32,
-            AluRmiROpcode::Add,
-            RegMemImm::imm(-129i32 as u32),
-            w_r8,
-        ),
-        "4181C07FFFFFFF",
-        "addl    $-129, %r8d",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size32,
-            AluRmiROpcode::Add,
-            RegMemImm::imm(-76543210i32 as u32),
-            w_r8,
-        ),
-        "4181C0160B70FB",
-        "addl    $-76543210, %r8d",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size32,
-            AluRmiROpcode::Add,
-            RegMemImm::imm(-127i32 as u32),
-            w_rsi,
-        ),
-        "83C681",
-        "addl    $-127, %esi",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size32,
-            AluRmiROpcode::Add,
-            RegMemImm::imm(-129i32 as u32),
-            w_rsi,
-        ),
-        "81C67FFFFFFF",
-        "addl    $-129, %esi",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size32,
-            AluRmiROpcode::Add,
-            RegMemImm::imm(76543210),
-            w_rsi,
-        ),
-        "81C6EAF48F04",
-        "addl    $76543210, %esi",
-    ));
-    // This is pretty feeble
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size64,
-            AluRmiROpcode::Sub,
-            RegMemImm::reg(r15),
-            w_rdx,
-        ),
-        "4C29FA",
-        "subq    %r15, %rdx",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size64,
-            AluRmiROpcode::And,
-            RegMemImm::reg(r15),
-            w_rdx,
-        ),
-        "4C21FA",
-        "andq    %r15, %rdx",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size64,
-            AluRmiROpcode::Or,
-            RegMemImm::reg(r15),
-            w_rdx,
-        ),
-        "4C09FA",
-        "orq     %r15, %rdx",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size32,
-            AluRmiROpcode::And8,
-            RegMemImm::reg(r15),
-            w_rdx,
-        ),
-        "4420FA",
-        "andb    %r15b, %dl",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size32,
-            AluRmiROpcode::And8,
-            RegMemImm::reg(rax),
-            w_rsi,
-        ),
-        "4020C6",
-        "andb    %al, %sil",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size32,
-            AluRmiROpcode::And8,
-            RegMemImm::reg(rax),
-            w_rbx,
-        ),
-        "20C3",
-        "andb    %al, %bl",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size32,
-            AluRmiROpcode::And8,
-            RegMemImm::mem(Amode::imm_reg(0, rax)),
-            w_rbx,
-        ),
-        "2218",
-        "andb    0(%rax), %bl",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size32,
-            AluRmiROpcode::Or8,
-            RegMemImm::reg(r15),
-            w_rdx,
-        ),
-        "4408FA",
-        "orb     %r15b, %dl",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size32,
-            AluRmiROpcode::Or8,
-            RegMemImm::reg(rax),
-            w_rsi,
-        ),
-        "4008C6",
-        "orb     %al, %sil",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size32,
-            AluRmiROpcode::Or8,
-            RegMemImm::reg(rax),
-            w_rbx,
-        ),
-        "08C3",
-        "orb     %al, %bl",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size32,
-            AluRmiROpcode::Or8,
-            RegMemImm::mem(Amode::imm_reg(0, rax)),
-            w_rbx,
-        ),
-        "0A18",
-        "orb     0(%rax), %bl",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size64,
-            AluRmiROpcode::Xor,
-            RegMemImm::reg(r15),
-            w_rdx,
-        ),
-        "4C31FA",
-        "xorq    %r15, %rdx",
-    ));
-    // Test all mul cases, though
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size64,
-            AluRmiROpcode::Mul,
-            RegMemImm::reg(r15),
-            w_rdx,
-        ),
-        "490FAFD7",
-        "imulq   %r15, %rdx",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size32,
-            AluRmiROpcode::Mul,
-            RegMemImm::reg(rcx),
-            w_r8,
-        ),
-        "440FAFC1",
-        "imull   %ecx, %r8d",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size32,
-            AluRmiROpcode::Mul,
-            RegMemImm::reg(rcx),
-            w_rsi,
-        ),
-        "0FAFF1",
-        "imull   %ecx, %esi",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size64,
-            AluRmiROpcode::Mul,
-            RegMemImm::mem(Amode::imm_reg(99, rdi)),
-            w_rdx,
-        ),
-        "480FAF5763",
-        "imulq   99(%rdi), %rdx",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size32,
-            AluRmiROpcode::Mul,
-            RegMemImm::mem(Amode::imm_reg(99, rdi)),
-            w_r8,
-        ),
-        "440FAF4763",
-        "imull   99(%rdi), %r8d",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size32,
-            AluRmiROpcode::Mul,
-            RegMemImm::mem(Amode::imm_reg(99, rdi)),
-            w_rsi,
-        ),
-        "0FAF7763",
-        "imull   99(%rdi), %esi",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size64,
-            AluRmiROpcode::Mul,
-            RegMemImm::imm(-127i32 as u32),
-            w_rdx,
-        ),
-        "486BD281",
-        "imulq   $-127, %rdx",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size64,
-            AluRmiROpcode::Mul,
-            RegMemImm::imm(-129i32 as u32),
-            w_rdx,
-        ),
-        "4869D27FFFFFFF",
-        "imulq   $-129, %rdx",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size64,
-            AluRmiROpcode::Mul,
-            RegMemImm::imm(76543210),
-            w_rdx,
-        ),
-        "4869D2EAF48F04",
-        "imulq   $76543210, %rdx",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size32,
-            AluRmiROpcode::Mul,
-            RegMemImm::imm(-127i32 as u32),
-            w_r8,
-        ),
-        "456BC081",
-        "imull   $-127, %r8d",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size32,
-            AluRmiROpcode::Mul,
-            RegMemImm::imm(-129i32 as u32),
-            w_r8,
-        ),
-        "4569C07FFFFFFF",
-        "imull   $-129, %r8d",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size32,
-            AluRmiROpcode::Mul,
-            RegMemImm::imm(-76543210i32 as u32),
-            w_r8,
-        ),
-        "4569C0160B70FB",
-        "imull   $-76543210, %r8d",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size32,
-            AluRmiROpcode::Mul,
-            RegMemImm::imm(-127i32 as u32),
-            w_rsi,
-        ),
-        "6BF681",
-        "imull   $-127, %esi",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size32,
-            AluRmiROpcode::Mul,
-            RegMemImm::imm(-129i32 as u32),
-            w_rsi,
-        ),
-        "69F67FFFFFFF",
-        "imull   $-129, %esi",
-    ));
-    insns.push((
-        Inst::alu_rmi_r(
-            OperandSize::Size32,
-            AluRmiROpcode::Mul,
-            RegMemImm::imm(76543210),
-            w_rsi,
-        ),
-        "69F6EAF48F04",
-        "imull   $76543210, %esi",
-    ));
-
-    // ========================================================
-    // UnaryRmR
-
-    insns.push((
-        Inst::unary_rm_r(
-            OperandSize::Size32,
-            UnaryRmROpcode::Bsr,
-            RegMem::reg(rsi),
-            w_rdi,
-        ),
-        "0FBDFE",
-        "bsrl    %esi, %edi",
-    ));
-    insns.push((
-        Inst::unary_rm_r(
-            OperandSize::Size64,
-            UnaryRmROpcode::Bsr,
-            RegMem::reg(r15),
-            w_rax,
-        ),
-        "490FBDC7",
-        "bsrq    %r15, %rax",
-    ));
-
-    // ========================================================
-    // Not
-    insns.push((
-        Inst::not(OperandSize::Size32, Writable::from_reg(regs::rsi())),
-        "F7D6",
-        "notl    %esi",
-    ));
-    insns.push((
-        Inst::not(OperandSize::Size64, Writable::from_reg(regs::r15())),
-        "49F7D7",
-        "notq    %r15",
-    ));
-    insns.push((
-        Inst::not(OperandSize::Size32, Writable::from_reg(regs::r14())),
-        "41F7D6",
-        "notl    %r14d",
-    ));
-    insns.push((
-        Inst::not(OperandSize::Size16, Writable::from_reg(regs::rdi())),
-        "66F7D7",
-        "notw    %di",
-    ));
-    insns.push((
-        Inst::not(OperandSize::Size8, Writable::from_reg(regs::rdi())),
-        "40F6D7",
-        "notb    %dil",
-    ));
-    insns.push((
-        Inst::not(OperandSize::Size8, Writable::from_reg(regs::rax())),
-        "F6D0",
-        "notb    %al",
-    ));
-
-    // ========================================================
-    // Neg
-    insns.push((
-        Inst::neg(OperandSize::Size32, Writable::from_reg(regs::rsi())),
-        "F7DE",
-        "negl    %esi",
-    ));
-    insns.push((
-        Inst::neg(OperandSize::Size64, Writable::from_reg(regs::r15())),
-        "49F7DF",
-        "negq    %r15",
-    ));
-    insns.push((
-        Inst::neg(OperandSize::Size32, Writable::from_reg(regs::r14())),
-        "41F7DE",
-        "negl    %r14d",
-    ));
-    insns.push((
-        Inst::neg(OperandSize::Size16, Writable::from_reg(regs::rdi())),
-        "66F7DF",
-        "negw    %di",
-    ));
-    insns.push((
-        Inst::neg(OperandSize::Size8, Writable::from_reg(regs::rdi())),
-        "40F6DF",
-        "negb    %dil",
-    ));
-    insns.push((
-        Inst::neg(OperandSize::Size8, Writable::from_reg(regs::rax())),
-        "F6D8",
-        "negb    %al",
-    ));
-
-    // ========================================================
-    // Div
-    insns.push((
-        Inst::div(
-            OperandSize::Size32,
-            true, /*signed*/
-            RegMem::reg(regs::rsi()),
-        ),
-        "F7FE",
-        "idiv    %esi",
-    ));
-    insns.push((
-        Inst::div(
-            OperandSize::Size64,
-            true, /*signed*/
-            RegMem::reg(regs::r15()),
-        ),
-        "49F7FF",
-        "idiv    %r15",
-    ));
-    insns.push((
-        Inst::div(
-            OperandSize::Size32,
-            false, /*signed*/
-            RegMem::reg(regs::r14()),
-        ),
-        "41F7F6",
-        "div     %r14d",
-    ));
-    insns.push((
-        Inst::div(
-            OperandSize::Size64,
-            false, /*signed*/
-            RegMem::reg(regs::rdi()),
-        ),
-        "48F7F7",
-        "div     %rdi",
-    ));
-    insns.push((
-        Inst::div(OperandSize::Size8, false, RegMem::reg(regs::rax())),
-        "F6F0",
-        "div     %al",
-    ));
-    insns.push((
-        Inst::div(OperandSize::Size8, false, RegMem::reg(regs::rsi())),
-        "40F6F6",
-        "div     %sil",
-    ));
-
-    // ========================================================
-    // MulHi
-    insns.push((
-        Inst::mul_hi(
-            OperandSize::Size32,
-            true, /*signed*/
-            RegMem::reg(regs::rsi()),
-        ),
-        "F7EE",
-        "imul    %esi",
-    ));
-    insns.push((
-        Inst::mul_hi(
-            OperandSize::Size64,
-            true, /*signed*/
-            RegMem::reg(regs::r15()),
-        ),
-        "49F7EF",
-        "imul    %r15",
-    ));
-    insns.push((
-        Inst::mul_hi(
-            OperandSize::Size32,
-            false, /*signed*/
-            RegMem::reg(regs::r14()),
-        ),
-        "41F7E6",
-        "mul     %r14d",
-    ));
-    insns.push((
-        Inst::mul_hi(
-            OperandSize::Size64,
-            false, /*signed*/
-            RegMem::reg(regs::rdi()),
-        ),
-        "48F7E7",
-        "mul     %rdi",
-    ));
-
-    // ========================================================
-    // cbw
-    insns.push((Inst::sign_extend_data(OperandSize::Size8), "6698", "cbw"));
-
-    // ========================================================
-    // cdq family: SignExtendRaxRdx
-    insns.push((Inst::sign_extend_data(OperandSize::Size16), "6699", "cwd"));
-    insns.push((Inst::sign_extend_data(OperandSize::Size32), "99", "cdq"));
-    insns.push((Inst::sign_extend_data(OperandSize::Size64), "4899", "cqo"));
-
-    // ========================================================
-    // Imm_R
-    //
-    insns.push((
-        Inst::imm(OperandSize::Size32, 1234567, w_r14),
-        "41BE87D61200",
-        "movl    $1234567, %r14d",
-    ));
-    insns.push((
-        Inst::imm(OperandSize::Size32, -126i64 as u64, w_r14),
-        "41BE82FFFFFF",
-        "movl    $-126, %r14d",
-    ));
-    insns.push((
-        Inst::imm(OperandSize::Size64, 1234567898765, w_r14),
-        "49BE8D26FB711F010000",
-        "movabsq $1234567898765, %r14",
-    ));
-    insns.push((
-        Inst::imm(OperandSize::Size64, -126i64 as u64, w_r14),
-        "49C7C682FFFFFF",
-        "movabsq $-126, %r14",
-    ));
-    insns.push((
-        Inst::imm(OperandSize::Size32, 1234567, w_rcx),
-        "B987D61200",
-        "movl    $1234567, %ecx",
-    ));
-    insns.push((
-        Inst::imm(OperandSize::Size32, -126i64 as u64, w_rcx),
-        "B982FFFFFF",
-        "movl    $-126, %ecx",
-    ));
-    insns.push((
-        Inst::imm(OperandSize::Size64, 1234567898765, w_rsi),
-        "48BE8D26FB711F010000",
-        "movabsq $1234567898765, %rsi",
-    ));
-    insns.push((
-        Inst::imm(OperandSize::Size64, -126i64 as u64, w_rbx),
-        "48C7C382FFFFFF",
-        "movabsq $-126, %rbx",
-    ));
-
-    // ========================================================
-    // Mov_R_R
-    insns.push((
-        Inst::mov_r_r(OperandSize::Size32, rbx, w_rsi),
-        "89DE",
-        "movl    %ebx, %esi",
-    ));
-    insns.push((
-        Inst::mov_r_r(OperandSize::Size32, rbx, w_r9),
-        "4189D9",
-        "movl    %ebx, %r9d",
-    ));
-    insns.push((
-        Inst::mov_r_r(OperandSize::Size32, r11, w_rsi),
-        "4489DE",
-        "movl    %r11d, %esi",
-    ));
-    insns.push((
-        Inst::mov_r_r(OperandSize::Size32, r12, w_r9),
-        "4589E1",
-        "movl    %r12d, %r9d",
-    ));
-    insns.push((
-        Inst::mov_r_r(OperandSize::Size64, rbx, w_rsi),
-        "4889DE",
-        "movq    %rbx, %rsi",
-    ));
-    insns.push((
-        Inst::mov_r_r(OperandSize::Size64, rbx, w_r9),
-        "4989D9",
-        "movq    %rbx, %r9",
-    ));
-    insns.push((
-        Inst::mov_r_r(OperandSize::Size64, r11, w_rsi),
-        "4C89DE",
-        "movq    %r11, %rsi",
-    ));
-    insns.push((
-        Inst::mov_r_r(OperandSize::Size64, r12, w_r9),
-        "4D89E1",
-        "movq    %r12, %r9",
-    ));
-
-    // ========================================================
-    // MovZX_RM_R
-    insns.push((
-        Inst::movzx_rm_r(ExtMode::BL, RegMem::reg(rdi), w_rdi),
-        "400FB6FF",
-        "movzbl  %dil, %edi",
-    ));
-    insns.push((
-        Inst::movzx_rm_r(ExtMode::BL, RegMem::reg(rax), w_rsi),
-        "0FB6F0",
-        "movzbl  %al, %esi",
-    ));
-    insns.push((
-        Inst::movzx_rm_r(ExtMode::BL, RegMem::reg(r15), w_rsi),
-        "410FB6F7",
-        "movzbl  %r15b, %esi",
-    ));
-    insns.push((
-        Inst::movzx_rm_r(
-            ExtMode::BL,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, rcx)),
-            w_rsi,
-        ),
-        "0FB671F9",
-        "movzbl  -7(%rcx), %esi",
-    ));
-    insns.push((
-        Inst::movzx_rm_r(
-            ExtMode::BL,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, r8)),
-            w_rbx,
-        ),
-        "410FB658F9",
-        "movzbl  -7(%r8), %ebx",
-    ));
-    insns.push((
-        Inst::movzx_rm_r(
-            ExtMode::BL,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, r10)),
-            w_r9,
-        ),
-        "450FB64AF9",
-        "movzbl  -7(%r10), %r9d",
-    ));
-    insns.push((
-        Inst::movzx_rm_r(
-            ExtMode::BL,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, r11)),
-            w_rdx,
-        ),
-        "410FB653F9",
-        "movzbl  -7(%r11), %edx",
-    ));
-    insns.push((
-        Inst::movzx_rm_r(ExtMode::BQ, RegMem::reg(rax), w_rsi),
-        "480FB6F0",
-        "movzbq  %al, %rsi",
-    ));
-    insns.push((
-        Inst::movzx_rm_r(ExtMode::BQ, RegMem::reg(r10), w_rsi),
-        "490FB6F2",
-        "movzbq  %r10b, %rsi",
-    ));
-    insns.push((
-        Inst::movzx_rm_r(
-            ExtMode::BQ,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, rcx)),
-            w_rsi,
-        ),
-        "480FB671F9",
-        "movzbq  -7(%rcx), %rsi",
-    ));
-    insns.push((
-        Inst::movzx_rm_r(
-            ExtMode::BQ,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, r8)),
-            w_rbx,
-        ),
-        "490FB658F9",
-        "movzbq  -7(%r8), %rbx",
-    ));
-    insns.push((
-        Inst::movzx_rm_r(
-            ExtMode::BQ,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, r10)),
-            w_r9,
-        ),
-        "4D0FB64AF9",
-        "movzbq  -7(%r10), %r9",
-    ));
-    insns.push((
-        Inst::movzx_rm_r(
-            ExtMode::BQ,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, r11)),
-            w_rdx,
-        ),
-        "490FB653F9",
-        "movzbq  -7(%r11), %rdx",
-    ));
-    insns.push((
-        Inst::movzx_rm_r(ExtMode::WL, RegMem::reg(rcx), w_rsi),
-        "0FB7F1",
-        "movzwl  %cx, %esi",
-    ));
-    insns.push((
-        Inst::movzx_rm_r(ExtMode::WL, RegMem::reg(r10), w_rsi),
-        "410FB7F2",
-        "movzwl  %r10w, %esi",
-    ));
-    insns.push((
-        Inst::movzx_rm_r(
-            ExtMode::WL,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, rcx)),
-            w_rsi,
-        ),
-        "0FB771F9",
-        "movzwl  -7(%rcx), %esi",
-    ));
-    insns.push((
-        Inst::movzx_rm_r(
-            ExtMode::WL,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, r8)),
-            w_rbx,
-        ),
-        "410FB758F9",
-        "movzwl  -7(%r8), %ebx",
-    ));
-    insns.push((
-        Inst::movzx_rm_r(
-            ExtMode::WL,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, r10)),
-            w_r9,
-        ),
-        "450FB74AF9",
-        "movzwl  -7(%r10), %r9d",
-    ));
-    insns.push((
-        Inst::movzx_rm_r(
-            ExtMode::WL,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, r11)),
-            w_rdx,
-        ),
-        "410FB753F9",
-        "movzwl  -7(%r11), %edx",
-    ));
-    insns.push((
-        Inst::movzx_rm_r(ExtMode::WQ, RegMem::reg(rcx), w_rsi),
-        "480FB7F1",
-        "movzwq  %cx, %rsi",
-    ));
-    insns.push((
-        Inst::movzx_rm_r(ExtMode::WQ, RegMem::reg(r11), w_rsi),
-        "490FB7F3",
-        "movzwq  %r11w, %rsi",
-    ));
-    insns.push((
-        Inst::movzx_rm_r(
-            ExtMode::WQ,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, rcx)),
-            w_rsi,
-        ),
-        "480FB771F9",
-        "movzwq  -7(%rcx), %rsi",
-    ));
-    insns.push((
-        Inst::movzx_rm_r(
-            ExtMode::WQ,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, r8)),
-            w_rbx,
-        ),
-        "490FB758F9",
-        "movzwq  -7(%r8), %rbx",
-    ));
-    insns.push((
-        Inst::movzx_rm_r(
-            ExtMode::WQ,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, r10)),
-            w_r9,
-        ),
-        "4D0FB74AF9",
-        "movzwq  -7(%r10), %r9",
-    ));
-    insns.push((
-        Inst::movzx_rm_r(
-            ExtMode::WQ,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, r11)),
-            w_rdx,
-        ),
-        "490FB753F9",
-        "movzwq  -7(%r11), %rdx",
-    ));
-    insns.push((
-        Inst::movzx_rm_r(ExtMode::LQ, RegMem::reg(rcx), w_rsi),
-        "8BF1",
-        "movl    %ecx, %esi",
-    ));
-    insns.push((
-        Inst::movzx_rm_r(
-            ExtMode::LQ,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, rcx)),
-            w_rsi,
-        ),
-        "8B71F9",
-        "movl    -7(%rcx), %esi",
-    ));
-    insns.push((
-        Inst::movzx_rm_r(
-            ExtMode::LQ,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, r8)),
-            w_rbx,
-        ),
-        "418B58F9",
-        "movl    -7(%r8), %ebx",
-    ));
-    insns.push((
-        Inst::movzx_rm_r(
-            ExtMode::LQ,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, r10)),
-            w_r9,
-        ),
-        "458B4AF9",
-        "movl    -7(%r10), %r9d",
-    ));
-    insns.push((
-        Inst::movzx_rm_r(
-            ExtMode::LQ,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, r11)),
-            w_rdx,
-        ),
-        "418B53F9",
-        "movl    -7(%r11), %edx",
-    ));
-
-    // ========================================================
-    // Mov64_M_R
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(179, Gpr::new(rax).unwrap(), Gpr::new(rbx).unwrap(), 0),
-            w_rcx,
-        ),
-        "488B8C18B3000000",
-        "movq    179(%rax,%rbx,1), %rcx",
-    ));
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(179, Gpr::new(rax).unwrap(), Gpr::new(rbx).unwrap(), 0),
-            w_r8,
-        ),
-        "4C8B8418B3000000",
-        "movq    179(%rax,%rbx,1), %r8",
-    ));
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(179, Gpr::new(rax).unwrap(), Gpr::new(r9).unwrap(), 0),
-            w_rcx,
-        ),
-        "4A8B8C08B3000000",
-        "movq    179(%rax,%r9,1), %rcx",
-    ));
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(179, Gpr::new(rax).unwrap(), Gpr::new(r9).unwrap(), 0),
-            w_r8,
-        ),
-        "4E8B8408B3000000",
-        "movq    179(%rax,%r9,1), %r8",
-    ));
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(179, Gpr::new(r10).unwrap(), Gpr::new(rbx).unwrap(), 0),
-            w_rcx,
-        ),
-        "498B8C1AB3000000",
-        "movq    179(%r10,%rbx,1), %rcx",
-    ));
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(179, Gpr::new(r10).unwrap(), Gpr::new(rbx).unwrap(), 0),
-            w_r8,
-        ),
-        "4D8B841AB3000000",
-        "movq    179(%r10,%rbx,1), %r8",
-    ));
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(179, Gpr::new(r10).unwrap(), Gpr::new(r9).unwrap(), 0),
-            w_rcx,
-        ),
-        "4B8B8C0AB3000000",
-        "movq    179(%r10,%r9,1), %rcx",
-    ));
-    insns.push((
-        Inst::mov64_m_r(
-            Amode::imm_reg_reg_shift(179, Gpr::new(r10).unwrap(), Gpr::new(r9).unwrap(), 0),
-            w_r8,
-        ),
-        "4F8B840AB3000000",
-        "movq    179(%r10,%r9,1), %r8",
-    ));
-
-    // ========================================================
-    // LoadEffectiveAddress
-    insns.push((
-        Inst::lea(Amode::imm_reg(42, r10), w_r8),
-        "4D8D422A",
-        "lea     42(%r10), %r8",
-    ));
-    insns.push((
-        Inst::lea(Amode::imm_reg(42, r10), w_r15),
-        "4D8D7A2A",
-        "lea     42(%r10), %r15",
-    ));
-    insns.push((
-        Inst::lea(
-            Amode::imm_reg_reg_shift(179, Gpr::new(r10).unwrap(), Gpr::new(r9).unwrap(), 0),
-            w_r8,
-        ),
-        "4F8D840AB3000000",
-        "lea     179(%r10,%r9,1), %r8",
-    ));
-    insns.push((
-        Inst::lea(Amode::rip_relative(MachLabel::from_block(0)), w_rdi),
-        "488D3D00000000",
-        "lea     label0(%rip), %rdi",
-    ));
-
-    // ========================================================
-    // MovSX_RM_R
-    insns.push((
-        Inst::movsx_rm_r(ExtMode::BL, RegMem::reg(rdi), w_rdi),
-        "400FBEFF",
-        "movsbl  %dil, %edi",
-    ));
-    insns.push((
-        Inst::movsx_rm_r(ExtMode::BL, RegMem::reg(rcx), w_rsi),
-        "0FBEF1",
-        "movsbl  %cl, %esi",
-    ));
-    insns.push((
-        Inst::movsx_rm_r(ExtMode::BL, RegMem::reg(r14), w_rsi),
-        "410FBEF6",
-        "movsbl  %r14b, %esi",
-    ));
-    insns.push((
-        Inst::movsx_rm_r(
-            ExtMode::BL,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, rcx)),
-            w_rsi,
-        ),
-        "0FBE71F9",
-        "movsbl  -7(%rcx), %esi",
-    ));
-    insns.push((
-        Inst::movsx_rm_r(
-            ExtMode::BL,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, r8)),
-            w_rbx,
-        ),
-        "410FBE58F9",
-        "movsbl  -7(%r8), %ebx",
-    ));
-    insns.push((
-        Inst::movsx_rm_r(
-            ExtMode::BL,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, r10)),
-            w_r9,
-        ),
-        "450FBE4AF9",
-        "movsbl  -7(%r10), %r9d",
-    ));
-    insns.push((
-        Inst::movsx_rm_r(
-            ExtMode::BL,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, r11)),
-            w_rdx,
-        ),
-        "410FBE53F9",
-        "movsbl  -7(%r11), %edx",
-    ));
-    insns.push((
-        Inst::movsx_rm_r(ExtMode::BQ, RegMem::reg(rcx), w_rsi),
-        "480FBEF1",
-        "movsbq  %cl, %rsi",
-    ));
-    insns.push((
-        Inst::movsx_rm_r(ExtMode::BQ, RegMem::reg(r15), w_rsi),
-        "490FBEF7",
-        "movsbq  %r15b, %rsi",
-    ));
-    insns.push((
-        Inst::movsx_rm_r(
-            ExtMode::BQ,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, rcx)),
-            w_rsi,
-        ),
-        "480FBE71F9",
-        "movsbq  -7(%rcx), %rsi",
-    ));
-    insns.push((
-        Inst::movsx_rm_r(
-            ExtMode::BQ,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, r8)),
-            w_rbx,
-        ),
-        "490FBE58F9",
-        "movsbq  -7(%r8), %rbx",
-    ));
-    insns.push((
-        Inst::movsx_rm_r(
-            ExtMode::BQ,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, r10)),
-            w_r9,
-        ),
-        "4D0FBE4AF9",
-        "movsbq  -7(%r10), %r9",
-    ));
-    insns.push((
-        Inst::movsx_rm_r(
-            ExtMode::BQ,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, r11)),
-            w_rdx,
-        ),
-        "490FBE53F9",
-        "movsbq  -7(%r11), %rdx",
-    ));
-    insns.push((
-        Inst::movsx_rm_r(ExtMode::WL, RegMem::reg(rcx), w_rsi),
-        "0FBFF1",
-        "movswl  %cx, %esi",
-    ));
-    insns.push((
-        Inst::movsx_rm_r(ExtMode::WL, RegMem::reg(r14), w_rsi),
-        "410FBFF6",
-        "movswl  %r14w, %esi",
-    ));
-    insns.push((
-        Inst::movsx_rm_r(
-            ExtMode::WL,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, rcx)),
-            w_rsi,
-        ),
-        "0FBF71F9",
-        "movswl  -7(%rcx), %esi",
-    ));
-    insns.push((
-        Inst::movsx_rm_r(
-            ExtMode::WL,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, r8)),
-            w_rbx,
-        ),
-        "410FBF58F9",
-        "movswl  -7(%r8), %ebx",
-    ));
-    insns.push((
-        Inst::movsx_rm_r(
-            ExtMode::WL,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, r10)),
-            w_r9,
-        ),
-        "450FBF4AF9",
-        "movswl  -7(%r10), %r9d",
-    ));
-    insns.push((
-        Inst::movsx_rm_r(
-            ExtMode::WL,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, r11)),
-            w_rdx,
-        ),
-        "410FBF53F9",
-        "movswl  -7(%r11), %edx",
-    ));
-    insns.push((
-        Inst::movsx_rm_r(ExtMode::WQ, RegMem::reg(rcx), w_rsi),
-        "480FBFF1",
-        "movswq  %cx, %rsi",
-    ));
-    insns.push((
-        Inst::movsx_rm_r(ExtMode::WQ, RegMem::reg(r13), w_rsi),
-        "490FBFF5",
-        "movswq  %r13w, %rsi",
-    ));
-    insns.push((
-        Inst::movsx_rm_r(
-            ExtMode::WQ,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, rcx)),
-            w_rsi,
-        ),
-        "480FBF71F9",
-        "movswq  -7(%rcx), %rsi",
-    ));
-    insns.push((
-        Inst::movsx_rm_r(
-            ExtMode::WQ,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, r8)),
-            w_rbx,
-        ),
-        "490FBF58F9",
-        "movswq  -7(%r8), %rbx",
-    ));
-    insns.push((
-        Inst::movsx_rm_r(
-            ExtMode::WQ,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, r10)),
-            w_r9,
-        ),
-        "4D0FBF4AF9",
-        "movswq  -7(%r10), %r9",
-    ));
-    insns.push((
-        Inst::movsx_rm_r(
-            ExtMode::WQ,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, r11)),
-            w_rdx,
-        ),
-        "490FBF53F9",
-        "movswq  -7(%r11), %rdx",
-    ));
-    insns.push((
-        Inst::movsx_rm_r(ExtMode::LQ, RegMem::reg(rcx), w_rsi),
-        "4863F1",
-        "movslq  %ecx, %rsi",
-    ));
-    insns.push((
-        Inst::movsx_rm_r(ExtMode::LQ, RegMem::reg(r15), w_rsi),
-        "4963F7",
-        "movslq  %r15d, %rsi",
-    ));
-    insns.push((
-        Inst::movsx_rm_r(
-            ExtMode::LQ,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, rcx)),
-            w_rsi,
-        ),
-        "486371F9",
-        "movslq  -7(%rcx), %rsi",
-    ));
-    insns.push((
-        Inst::movsx_rm_r(
-            ExtMode::LQ,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, r8)),
-            w_rbx,
-        ),
-        "496358F9",
-        "movslq  -7(%r8), %rbx",
-    ));
-    insns.push((
-        Inst::movsx_rm_r(
-            ExtMode::LQ,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, r10)),
-            w_r9,
-        ),
-        "4D634AF9",
-        "movslq  -7(%r10), %r9",
-    ));
-    insns.push((
-        Inst::movsx_rm_r(
-            ExtMode::LQ,
-            RegMem::mem(Amode::imm_reg(-7i32 as u32, r11)),
-            w_rdx,
-        ),
-        "496353F9",
-        "movslq  -7(%r11), %rdx",
-    ));
-
-    // ========================================================
-    // Mov_R_M.  Byte stores are tricky.  Check everything carefully.
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size64, rax, Amode::imm_reg(99, rdi)),
-        "48894763",
-        "movq    %rax, 99(%rdi)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size64, rbx, Amode::imm_reg(99, r8)),
-        "49895863",
-        "movq    %rbx, 99(%r8)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size64, rcx, Amode::imm_reg(99, rsi)),
-        "48894E63",
-        "movq    %rcx, 99(%rsi)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size64, rdx, Amode::imm_reg(99, r9)),
-        "49895163",
-        "movq    %rdx, 99(%r9)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size64, rsi, Amode::imm_reg(99, rax)),
-        "48897063",
-        "movq    %rsi, 99(%rax)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size64, rdi, Amode::imm_reg(99, r15)),
-        "49897F63",
-        "movq    %rdi, 99(%r15)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size64, rsp, Amode::imm_reg(99, rcx)),
-        "48896163",
-        "movq    %rsp, 99(%rcx)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size64, rbp, Amode::imm_reg(99, r14)),
-        "49896E63",
-        "movq    %rbp, 99(%r14)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size64, r8, Amode::imm_reg(99, rdi)),
-        "4C894763",
-        "movq    %r8, 99(%rdi)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size64, r9, Amode::imm_reg(99, r8)),
-        "4D894863",
-        "movq    %r9, 99(%r8)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size64, r10, Amode::imm_reg(99, rsi)),
-        "4C895663",
-        "movq    %r10, 99(%rsi)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size64, r11, Amode::imm_reg(99, r9)),
-        "4D895963",
-        "movq    %r11, 99(%r9)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size64, r12, Amode::imm_reg(99, rax)),
-        "4C896063",
-        "movq    %r12, 99(%rax)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size64, r13, Amode::imm_reg(99, r15)),
-        "4D896F63",
-        "movq    %r13, 99(%r15)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size64, r14, Amode::imm_reg(99, rcx)),
-        "4C897163",
-        "movq    %r14, 99(%rcx)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size64, r15, Amode::imm_reg(99, r14)),
-        "4D897E63",
-        "movq    %r15, 99(%r14)",
-    ));
-    //
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size32, rax, Amode::imm_reg(99, rdi)),
-        "894763",
-        "movl    %eax, 99(%rdi)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size32, rbx, Amode::imm_reg(99, r8)),
-        "41895863",
-        "movl    %ebx, 99(%r8)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size32, rcx, Amode::imm_reg(99, rsi)),
-        "894E63",
-        "movl    %ecx, 99(%rsi)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size32, rdx, Amode::imm_reg(99, r9)),
-        "41895163",
-        "movl    %edx, 99(%r9)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size32, rsi, Amode::imm_reg(99, rax)),
-        "897063",
-        "movl    %esi, 99(%rax)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size32, rdi, Amode::imm_reg(99, r15)),
-        "41897F63",
-        "movl    %edi, 99(%r15)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size32, rsp, Amode::imm_reg(99, rcx)),
-        "896163",
-        "movl    %esp, 99(%rcx)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size32, rbp, Amode::imm_reg(99, r14)),
-        "41896E63",
-        "movl    %ebp, 99(%r14)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size32, r8, Amode::imm_reg(99, rdi)),
-        "44894763",
-        "movl    %r8d, 99(%rdi)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size32, r9, Amode::imm_reg(99, r8)),
-        "45894863",
-        "movl    %r9d, 99(%r8)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size32, r10, Amode::imm_reg(99, rsi)),
-        "44895663",
-        "movl    %r10d, 99(%rsi)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size32, r11, Amode::imm_reg(99, r9)),
-        "45895963",
-        "movl    %r11d, 99(%r9)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size32, r12, Amode::imm_reg(99, rax)),
-        "44896063",
-        "movl    %r12d, 99(%rax)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size32, r13, Amode::imm_reg(99, r15)),
-        "45896F63",
-        "movl    %r13d, 99(%r15)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size32, r14, Amode::imm_reg(99, rcx)),
-        "44897163",
-        "movl    %r14d, 99(%rcx)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size32, r15, Amode::imm_reg(99, r14)),
-        "45897E63",
-        "movl    %r15d, 99(%r14)",
-    ));
-    //
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size16, rax, Amode::imm_reg(99, rdi)),
-        "66894763",
-        "movw    %ax, 99(%rdi)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size16, rbx, Amode::imm_reg(99, r8)),
-        "6641895863",
-        "movw    %bx, 99(%r8)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size16, rcx, Amode::imm_reg(99, rsi)),
-        "66894E63",
-        "movw    %cx, 99(%rsi)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size16, rdx, Amode::imm_reg(99, r9)),
-        "6641895163",
-        "movw    %dx, 99(%r9)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size16, rsi, Amode::imm_reg(99, rax)),
-        "66897063",
-        "movw    %si, 99(%rax)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size16, rdi, Amode::imm_reg(99, r15)),
-        "6641897F63",
-        "movw    %di, 99(%r15)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size16, rsp, Amode::imm_reg(99, rcx)),
-        "66896163",
-        "movw    %sp, 99(%rcx)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size16, rbp, Amode::imm_reg(99, r14)),
-        "6641896E63",
-        "movw    %bp, 99(%r14)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size16, r8, Amode::imm_reg(99, rdi)),
-        "6644894763",
-        "movw    %r8w, 99(%rdi)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size16, r9, Amode::imm_reg(99, r8)),
-        "6645894863",
-        "movw    %r9w, 99(%r8)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size16, r10, Amode::imm_reg(99, rsi)),
-        "6644895663",
-        "movw    %r10w, 99(%rsi)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size16, r11, Amode::imm_reg(99, r9)),
-        "6645895963",
-        "movw    %r11w, 99(%r9)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size16, r12, Amode::imm_reg(99, rax)),
-        "6644896063",
-        "movw    %r12w, 99(%rax)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size16, r13, Amode::imm_reg(99, r15)),
-        "6645896F63",
-        "movw    %r13w, 99(%r15)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size16, r14, Amode::imm_reg(99, rcx)),
-        "6644897163",
-        "movw    %r14w, 99(%rcx)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size16, r15, Amode::imm_reg(99, r14)),
-        "6645897E63",
-        "movw    %r15w, 99(%r14)",
-    ));
-    //
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size8, rax, Amode::imm_reg(99, rdi)),
-        "884763",
-        "movb    %al, 99(%rdi)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size8, rbx, Amode::imm_reg(99, r8)),
-        "41885863",
-        "movb    %bl, 99(%r8)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size8, rcx, Amode::imm_reg(99, rsi)),
-        "884E63",
-        "movb    %cl, 99(%rsi)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size8, rdx, Amode::imm_reg(99, r9)),
-        "41885163",
-        "movb    %dl, 99(%r9)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size8, rsi, Amode::imm_reg(99, rax)),
-        "40887063",
-        "movb    %sil, 99(%rax)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size8, rdi, Amode::imm_reg(99, r15)),
-        "41887F63",
-        "movb    %dil, 99(%r15)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size8, rsp, Amode::imm_reg(99, rcx)),
-        "40886163",
-        "movb    %spl, 99(%rcx)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size8, rbp, Amode::imm_reg(99, r14)),
-        "41886E63",
-        "movb    %bpl, 99(%r14)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size8, r8, Amode::imm_reg(99, rdi)),
-        "44884763",
-        "movb    %r8b, 99(%rdi)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size8, r9, Amode::imm_reg(99, r8)),
-        "45884863",
-        "movb    %r9b, 99(%r8)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size8, r10, Amode::imm_reg(99, rsi)),
-        "44885663",
-        "movb    %r10b, 99(%rsi)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size8, r11, Amode::imm_reg(99, r9)),
-        "45885963",
-        "movb    %r11b, 99(%r9)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size8, r12, Amode::imm_reg(99, rax)),
-        "44886063",
-        "movb    %r12b, 99(%rax)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size8, r13, Amode::imm_reg(99, r15)),
-        "45886F63",
-        "movb    %r13b, 99(%r15)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size8, r14, Amode::imm_reg(99, rcx)),
-        "44887163",
-        "movb    %r14b, 99(%rcx)",
-    ));
-    insns.push((
-        Inst::mov_r_m(OperandSize::Size8, r15, Amode::imm_reg(99, r14)),
-        "45887E63",
-        "movb    %r15b, 99(%r14)",
-    ));
-
-    // ========================================================
-    // Shift_R
-    insns.push((
-        Inst::shift_r(OperandSize::Size32, ShiftKind::ShiftLeft, None, w_rdi),
-        "D3E7",
-        "shll    %cl, %edi",
-    ));
-    insns.push((
-        Inst::shift_r(OperandSize::Size32, ShiftKind::ShiftLeft, None, w_r12),
-        "41D3E4",
-        "shll    %cl, %r12d",
-    ));
-    insns.push((
-        Inst::shift_r(OperandSize::Size32, ShiftKind::ShiftLeft, Some(2), w_r8),
-        "41C1E002",
-        "shll    $2, %r8d",
-    ));
-    insns.push((
-        Inst::shift_r(OperandSize::Size32, ShiftKind::ShiftLeft, Some(31), w_r13),
-        "41C1E51F",
-        "shll    $31, %r13d",
-    ));
-    insns.push((
-        Inst::shift_r(OperandSize::Size64, ShiftKind::ShiftLeft, None, w_r13),
-        "49D3E5",
-        "shlq    %cl, %r13",
-    ));
-    insns.push((
-        Inst::shift_r(OperandSize::Size64, ShiftKind::ShiftLeft, None, w_rdi),
-        "48D3E7",
-        "shlq    %cl, %rdi",
-    ));
-    insns.push((
-        Inst::shift_r(OperandSize::Size64, ShiftKind::ShiftLeft, Some(2), w_r8),
-        "49C1E002",
-        "shlq    $2, %r8",
-    ));
-    insns.push((
-        Inst::shift_r(OperandSize::Size64, ShiftKind::ShiftLeft, Some(3), w_rbx),
-        "48C1E303",
-        "shlq    $3, %rbx",
-    ));
-    insns.push((
-        Inst::shift_r(OperandSize::Size64, ShiftKind::ShiftLeft, Some(63), w_r13),
-        "49C1E53F",
-        "shlq    $63, %r13",
-    ));
-    insns.push((
-        Inst::shift_r(
-            OperandSize::Size32,
-            ShiftKind::ShiftRightLogical,
-            None,
-            w_rdi,
-        ),
-        "D3EF",
-        "shrl    %cl, %edi",
-    ));
-    insns.push((
-        Inst::shift_r(
-            OperandSize::Size32,
-            ShiftKind::ShiftRightLogical,
-            Some(2),
-            w_r8,
-        ),
-        "41C1E802",
-        "shrl    $2, %r8d",
-    ));
-    insns.push((
-        Inst::shift_r(
-            OperandSize::Size32,
-            ShiftKind::ShiftRightLogical,
-            Some(31),
-            w_r13,
-        ),
-        "41C1ED1F",
-        "shrl    $31, %r13d",
-    ));
-    insns.push((
-        Inst::shift_r(
-            OperandSize::Size64,
-            ShiftKind::ShiftRightLogical,
-            None,
-            w_rdi,
-        ),
-        "48D3EF",
-        "shrq    %cl, %rdi",
-    ));
-    insns.push((
-        Inst::shift_r(
-            OperandSize::Size64,
-            ShiftKind::ShiftRightLogical,
-            Some(2),
-            w_r8,
-        ),
-        "49C1E802",
-        "shrq    $2, %r8",
-    ));
-    insns.push((
-        Inst::shift_r(
-            OperandSize::Size64,
-            ShiftKind::ShiftRightLogical,
-            Some(63),
-            w_r13,
-        ),
-        "49C1ED3F",
-        "shrq    $63, %r13",
-    ));
-    insns.push((
-        Inst::shift_r(
-            OperandSize::Size32,
-            ShiftKind::ShiftRightArithmetic,
-            None,
-            w_rdi,
-        ),
-        "D3FF",
-        "sarl    %cl, %edi",
-    ));
-    insns.push((
-        Inst::shift_r(
-            OperandSize::Size32,
-            ShiftKind::ShiftRightArithmetic,
-            Some(2),
-            w_r8,
-        ),
-        "41C1F802",
-        "sarl    $2, %r8d",
-    ));
-    insns.push((
-        Inst::shift_r(
-            OperandSize::Size32,
-            ShiftKind::ShiftRightArithmetic,
-            Some(31),
-            w_r13,
-        ),
-        "41C1FD1F",
-        "sarl    $31, %r13d",
-    ));
-    insns.push((
-        Inst::shift_r(
-            OperandSize::Size64,
-            ShiftKind::ShiftRightArithmetic,
-            None,
-            w_rdi,
-        ),
-        "48D3FF",
-        "sarq    %cl, %rdi",
-    ));
-    insns.push((
-        Inst::shift_r(
-            OperandSize::Size64,
-            ShiftKind::ShiftRightArithmetic,
-            Some(2),
-            w_r8,
-        ),
-        "49C1F802",
-        "sarq    $2, %r8",
-    ));
-    insns.push((
-        Inst::shift_r(
-            OperandSize::Size64,
-            ShiftKind::ShiftRightArithmetic,
-            Some(63),
-            w_r13,
-        ),
-        "49C1FD3F",
-        "sarq    $63, %r13",
-    ));
-    insns.push((
-        Inst::shift_r(OperandSize::Size64, ShiftKind::RotateLeft, None, w_r8),
-        "49D3C0",
-        "rolq    %cl, %r8",
-    ));
-    insns.push((
-        Inst::shift_r(OperandSize::Size32, ShiftKind::RotateLeft, Some(3), w_r9),
-        "41C1C103",
-        "roll    $3, %r9d",
-    ));
-    insns.push((
-        Inst::shift_r(OperandSize::Size32, ShiftKind::RotateRight, None, w_rsi),
-        "D3CE",
-        "rorl    %cl, %esi",
-    ));
-    insns.push((
-        Inst::shift_r(OperandSize::Size64, ShiftKind::RotateRight, Some(5), w_r15),
-        "49C1CF05",
-        "rorq    $5, %r15",
-    ));
-    insns.push((
-        Inst::shift_r(OperandSize::Size8, ShiftKind::RotateRight, None, w_rsi),
-        "40D2CE",
-        "rorb    %cl, %sil",
-    ));
-    insns.push((
-        Inst::shift_r(OperandSize::Size8, ShiftKind::RotateRight, None, w_rax),
-        "D2C8",
-        "rorb    %cl, %al",
-    ));
-    insns.push((
-        Inst::shift_r(OperandSize::Size8, ShiftKind::RotateRight, Some(5), w_r15),
-        "41C0CF05",
-        "rorb    $5, %r15b",
-    ));
-    insns.push((
-        Inst::shift_r(OperandSize::Size16, ShiftKind::RotateRight, None, w_rsi),
-        "66D3CE",
-        "rorw    %cl, %si",
-    ));
-    insns.push((
-        Inst::shift_r(OperandSize::Size16, ShiftKind::RotateRight, Some(5), w_r15),
-        "6641C1CF05",
-        "rorw    $5, %r15w",
-    ));
-
-    // ========================================================
-    // CmpRMIR
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size64, RegMemImm::reg(r15), rdx),
-        "4C39FA",
-        "cmpq    %r15, %rdx",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size64, RegMemImm::reg(rcx), r8),
-        "4939C8",
-        "cmpq    %rcx, %r8",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size64, RegMemImm::reg(rcx), rsi),
-        "4839CE",
-        "cmpq    %rcx, %rsi",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(
-            OperandSize::Size64,
-            RegMemImm::mem(Amode::imm_reg(99, rdi)),
-            rdx,
-        ),
-        "483B5763",
-        "cmpq    99(%rdi), %rdx",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(
-            OperandSize::Size64,
-            RegMemImm::mem(Amode::imm_reg(99, rdi)),
-            r8,
-        ),
-        "4C3B4763",
-        "cmpq    99(%rdi), %r8",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(
-            OperandSize::Size64,
-            RegMemImm::mem(Amode::imm_reg(99, rdi)),
-            rsi,
-        ),
-        "483B7763",
-        "cmpq    99(%rdi), %rsi",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size64, RegMemImm::imm(76543210), rdx),
-        "4881FAEAF48F04",
-        "cmpq    $76543210, %rdx",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size64, RegMemImm::imm(-76543210i32 as u32), r8),
-        "4981F8160B70FB",
-        "cmpq    $-76543210, %r8",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size64, RegMemImm::imm(76543210), rsi),
-        "4881FEEAF48F04",
-        "cmpq    $76543210, %rsi",
-    ));
-    //
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size32, RegMemImm::reg(r15), rdx),
-        "4439FA",
-        "cmpl    %r15d, %edx",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size32, RegMemImm::reg(rcx), r8),
-        "4139C8",
-        "cmpl    %ecx, %r8d",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size32, RegMemImm::reg(rcx), rsi),
-        "39CE",
-        "cmpl    %ecx, %esi",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(
-            OperandSize::Size32,
-            RegMemImm::mem(Amode::imm_reg(99, rdi)),
-            rdx,
-        ),
-        "3B5763",
-        "cmpl    99(%rdi), %edx",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(
-            OperandSize::Size32,
-            RegMemImm::mem(Amode::imm_reg(99, rdi)),
-            r8,
-        ),
-        "443B4763",
-        "cmpl    99(%rdi), %r8d",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(
-            OperandSize::Size32,
-            RegMemImm::mem(Amode::imm_reg(99, rdi)),
-            rsi,
-        ),
-        "3B7763",
-        "cmpl    99(%rdi), %esi",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size32, RegMemImm::imm(76543210), rdx),
-        "81FAEAF48F04",
-        "cmpl    $76543210, %edx",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size32, RegMemImm::imm(-76543210i32 as u32), r8),
-        "4181F8160B70FB",
-        "cmpl    $-76543210, %r8d",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size32, RegMemImm::imm(76543210), rsi),
-        "81FEEAF48F04",
-        "cmpl    $76543210, %esi",
-    ));
-    //
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size16, RegMemImm::reg(r15), rdx),
-        "664439FA",
-        "cmpw    %r15w, %dx",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size16, RegMemImm::reg(rcx), r8),
-        "664139C8",
-        "cmpw    %cx, %r8w",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size16, RegMemImm::reg(rcx), rsi),
-        "6639CE",
-        "cmpw    %cx, %si",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(
-            OperandSize::Size16,
-            RegMemImm::mem(Amode::imm_reg(99, rdi)),
-            rdx,
-        ),
-        "663B5763",
-        "cmpw    99(%rdi), %dx",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(
-            OperandSize::Size16,
-            RegMemImm::mem(Amode::imm_reg(99, rdi)),
-            r8,
-        ),
-        "66443B4763",
-        "cmpw    99(%rdi), %r8w",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(
-            OperandSize::Size16,
-            RegMemImm::mem(Amode::imm_reg(99, rdi)),
-            rsi,
-        ),
-        "663B7763",
-        "cmpw    99(%rdi), %si",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size16, RegMemImm::imm(23210), rdx),
-        "6681FAAA5A",
-        "cmpw    $23210, %dx",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size16, RegMemImm::imm(-7654i32 as u32), r8),
-        "664181F81AE2",
-        "cmpw    $-7654, %r8w",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size16, RegMemImm::imm(7654), rsi),
-        "6681FEE61D",
-        "cmpw    $7654, %si",
-    ));
-    //
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size8, RegMemImm::reg(r15), rdx),
-        "4438FA",
-        "cmpb    %r15b, %dl",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size8, RegMemImm::reg(rcx), r8),
-        "4138C8",
-        "cmpb    %cl, %r8b",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size8, RegMemImm::reg(rcx), rsi),
-        "4038CE",
-        "cmpb    %cl, %sil",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(
-            OperandSize::Size8,
-            RegMemImm::mem(Amode::imm_reg(99, rdi)),
-            rdx,
-        ),
-        "3A5763",
-        "cmpb    99(%rdi), %dl",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(
-            OperandSize::Size8,
-            RegMemImm::mem(Amode::imm_reg(99, rdi)),
-            r8,
-        ),
-        "443A4763",
-        "cmpb    99(%rdi), %r8b",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(
-            OperandSize::Size8,
-            RegMemImm::mem(Amode::imm_reg(99, rdi)),
-            rsi,
-        ),
-        "403A7763",
-        "cmpb    99(%rdi), %sil",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size8, RegMemImm::imm(70), rdx),
-        "80FA46",
-        "cmpb    $70, %dl",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size8, RegMemImm::imm(-76i32 as u32), r8),
-        "4180F8B4",
-        "cmpb    $-76, %r8b",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size8, RegMemImm::imm(76), rsi),
-        "4080FE4C",
-        "cmpb    $76, %sil",
-    ));
-    // Extra byte-cases (paranoia!) for cmp_rmi_r for first operand = R
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size8, RegMemImm::reg(rax), rbx),
-        "38C3",
-        "cmpb    %al, %bl",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size8, RegMemImm::reg(rbx), rax),
-        "38D8",
-        "cmpb    %bl, %al",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size8, RegMemImm::reg(rcx), rdx),
-        "38CA",
-        "cmpb    %cl, %dl",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size8, RegMemImm::reg(rcx), rsi),
-        "4038CE",
-        "cmpb    %cl, %sil",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size8, RegMemImm::reg(rcx), r10),
-        "4138CA",
-        "cmpb    %cl, %r10b",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size8, RegMemImm::reg(rcx), r14),
-        "4138CE",
-        "cmpb    %cl, %r14b",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size8, RegMemImm::reg(rbp), rdx),
-        "4038EA",
-        "cmpb    %bpl, %dl",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size8, RegMemImm::reg(rbp), rsi),
-        "4038EE",
-        "cmpb    %bpl, %sil",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size8, RegMemImm::reg(rbp), r10),
-        "4138EA",
-        "cmpb    %bpl, %r10b",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size8, RegMemImm::reg(rbp), r14),
-        "4138EE",
-        "cmpb    %bpl, %r14b",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size8, RegMemImm::reg(r9), rdx),
-        "4438CA",
-        "cmpb    %r9b, %dl",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size8, RegMemImm::reg(r9), rsi),
-        "4438CE",
-        "cmpb    %r9b, %sil",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size8, RegMemImm::reg(r9), r10),
-        "4538CA",
-        "cmpb    %r9b, %r10b",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size8, RegMemImm::reg(r9), r14),
-        "4538CE",
-        "cmpb    %r9b, %r14b",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size8, RegMemImm::reg(r13), rdx),
-        "4438EA",
-        "cmpb    %r13b, %dl",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size8, RegMemImm::reg(r13), rsi),
-        "4438EE",
-        "cmpb    %r13b, %sil",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size8, RegMemImm::reg(r13), r10),
-        "4538EA",
-        "cmpb    %r13b, %r10b",
-    ));
-    insns.push((
-        Inst::cmp_rmi_r(OperandSize::Size8, RegMemImm::reg(r13), r14),
-        "4538EE",
-        "cmpb    %r13b, %r14b",
-    ));
-
-    // ========================================================
-    // TestRmiR
-    insns.push((
-        Inst::test_rmi_r(OperandSize::Size64, RegMemImm::reg(r15), rdx),
-        "4C85FA",
-        "testq   %r15, %rdx",
-    ));
-    insns.push((
-        Inst::test_rmi_r(
-            OperandSize::Size64,
-            RegMemImm::mem(Amode::imm_reg(99, rdi)),
-            rdx,
-        ),
-        "48855763",
-        "testq   99(%rdi), %rdx",
-    ));
-    insns.push((
-        Inst::test_rmi_r(OperandSize::Size64, RegMemImm::imm(127), rdx),
-        "48F7C27F000000",
-        "testq   $127, %rdx",
-    ));
-    insns.push((
-        Inst::test_rmi_r(OperandSize::Size64, RegMemImm::imm(76543210), rdx),
-        "48F7C2EAF48F04",
-        "testq   $76543210, %rdx",
-    ));
-    //
-    insns.push((
-        Inst::test_rmi_r(OperandSize::Size32, RegMemImm::reg(r15), rdx),
-        "4485FA",
-        "testl   %r15d, %edx",
-    ));
-    insns.push((
-        Inst::test_rmi_r(
-            OperandSize::Size32,
-            RegMemImm::mem(Amode::imm_reg(99, rdi)),
-            rdx,
-        ),
-        "855763",
-        "testl   99(%rdi), %edx",
-    ));
-    insns.push((
-        Inst::test_rmi_r(OperandSize::Size32, RegMemImm::imm(76543210), rdx),
-        "F7C2EAF48F04",
-        "testl   $76543210, %edx",
-    ));
-    //
-    insns.push((
-        Inst::test_rmi_r(OperandSize::Size16, RegMemImm::reg(r15), rdx),
-        "664485FA",
-        "testw   %r15w, %dx",
-    ));
-    insns.push((
-        Inst::test_rmi_r(
-            OperandSize::Size16,
-            RegMemImm::mem(Amode::imm_reg(99, rdi)),
-            rdx,
-        ),
-        "66855763",
-        "testw   99(%rdi), %dx",
-    ));
-    insns.push((
-        Inst::test_rmi_r(OperandSize::Size16, RegMemImm::imm(23210), rdx),
-        "66F7C2AA5A",
-        "testw   $23210, %dx",
-    ));
-    //
-    insns.push((
-        Inst::test_rmi_r(OperandSize::Size8, RegMemImm::reg(r15), rdx),
-        "4484FA",
-        "testb   %r15b, %dl",
-    ));
-    insns.push((
-        Inst::test_rmi_r(
-            OperandSize::Size8,
-            RegMemImm::mem(Amode::imm_reg(99, rdi)),
-            rdx,
-        ),
-        "845763",
-        "testb   99(%rdi), %dl",
-    ));
-    insns.push((
-        Inst::test_rmi_r(OperandSize::Size8, RegMemImm::imm(70), rdx),
-        "F6C246",
-        "testb   $70, %dl",
-    ));
-    // Extra byte-cases (paranoia!) for test_rmi_r for first operand = R
-    insns.push((
-        Inst::test_rmi_r(OperandSize::Size8, RegMemImm::reg(rax), rbx),
-        "84C3",
-        "testb   %al, %bl",
-    ));
-    insns.push((
-        Inst::test_rmi_r(OperandSize::Size8, RegMemImm::reg(rcx), rsi),
-        "4084CE",
-        "testb   %cl, %sil",
-    ));
-    insns.push((
-        Inst::test_rmi_r(OperandSize::Size8, RegMemImm::reg(rcx), r10),
-        "4184CA",
-        "testb   %cl, %r10b",
-    ));
-
-    // ========================================================
-    // SetCC
-    insns.push((Inst::setcc(CC::O, w_rsi), "400F90C6", "seto    %sil"));
-    insns.push((Inst::setcc(CC::NLE, w_rsi), "400F9FC6", "setnle  %sil"));
-    insns.push((Inst::setcc(CC::Z, w_r14), "410F94C6", "setz    %r14b"));
-    insns.push((Inst::setcc(CC::LE, w_r14), "410F9EC6", "setle   %r14b"));
-    insns.push((Inst::setcc(CC::P, w_r9), "410F9AC1", "setp    %r9b"));
-    insns.push((Inst::setcc(CC::NP, w_r8), "410F9BC0", "setnp   %r8b"));
-    // ========================================================
-    // Cmove
-    insns.push((
-        Inst::cmove(OperandSize::Size16, CC::O, RegMem::reg(rdi), w_rsi),
-        "660F40F7",
-        "cmovow  %di, %si",
-    ));
-    insns.push((
-        Inst::cmove(
-            OperandSize::Size16,
-            CC::NO,
-            RegMem::mem(Amode::imm_reg_reg_shift(
-                37,
-                Gpr::new(rdi).unwrap(),
-                Gpr::new(rsi).unwrap(),
-                2,
-            )),
-            w_r15,
-        ),
-        "66440F417CB725",
-        "cmovnow 37(%rdi,%rsi,4), %r15w",
-    ));
-    insns.push((
-        Inst::cmove(OperandSize::Size32, CC::LE, RegMem::reg(rdi), w_rsi),
-        "0F4EF7",
-        "cmovlel %edi, %esi",
-    ));
-    insns.push((
-        Inst::cmove(
-            OperandSize::Size32,
-            CC::NLE,
-            RegMem::mem(Amode::imm_reg(0, r15)),
-            w_rsi,
-        ),
-        "410F4F37",
-        "cmovnlel 0(%r15), %esi",
-    ));
-    insns.push((
-        Inst::cmove(OperandSize::Size64, CC::Z, RegMem::reg(rdi), w_r14),
-        "4C0F44F7",
-        "cmovzq  %rdi, %r14",
-    ));
-    insns.push((
-        Inst::cmove(
-            OperandSize::Size64,
-            CC::NZ,
-            RegMem::mem(Amode::imm_reg(13, rdi)),
-            w_r14,
-        ),
-        "4C0F45770D",
-        "cmovnzq 13(%rdi), %r14",
-    ));
-
-    // ========================================================
-    // Push64
-    insns.push((Inst::push64(RegMemImm::reg(rdi)), "57", "pushq   %rdi"));
-    insns.push((Inst::push64(RegMemImm::reg(r8)), "4150", "pushq   %r8"));
-    insns.push((
-        Inst::push64(RegMemImm::mem(Amode::imm_reg_reg_shift(
-            321,
-            Gpr::new(rsi).unwrap(),
-            Gpr::new(rcx).unwrap(),
-            3,
-        ))),
-        "FFB4CE41010000",
-        "pushq   321(%rsi,%rcx,8)",
-    ));
-    insns.push((
-        Inst::push64(RegMemImm::mem(Amode::imm_reg_reg_shift(
-            321,
-            Gpr::new(r9).unwrap(),
-            Gpr::new(rbx).unwrap(),
-            2,
-        ))),
-        "41FFB49941010000",
-        "pushq   321(%r9,%rbx,4)",
-    ));
-    insns.push((Inst::push64(RegMemImm::imm(0)), "6A00", "pushq   $0"));
-    insns.push((Inst::push64(RegMemImm::imm(127)), "6A7F", "pushq   $127"));
-    insns.push((
-        Inst::push64(RegMemImm::imm(128)),
-        "6880000000",
-        "pushq   $128",
-    ));
-    insns.push((
-        Inst::push64(RegMemImm::imm(0x31415927)),
-        "6827594131",
-        "pushq   $826366247",
-    ));
-    insns.push((
-        Inst::push64(RegMemImm::imm(-128i32 as u32)),
-        "6A80",
-        "pushq   $-128",
-    ));
-    insns.push((
-        Inst::push64(RegMemImm::imm(-129i32 as u32)),
-        "687FFFFFFF",
-        "pushq   $-129",
-    ));
-    insns.push((
-        Inst::push64(RegMemImm::imm(-0x75c4e8a1i32 as u32)),
-        "685F173B8A",
-        "pushq   $-1975838881",
-    ));
-
-    // ========================================================
-    // Pop64
-    insns.push((Inst::pop64(w_rax), "58", "popq    %rax"));
-    insns.push((Inst::pop64(w_rdi), "5F", "popq    %rdi"));
-    insns.push((Inst::pop64(w_r8), "4158", "popq    %r8"));
-    insns.push((Inst::pop64(w_r15), "415F", "popq    %r15"));
-
-    // ========================================================
-    // CallKnown
-    insns.push((
-        Inst::call_known(
-            ExternalName::User {
-                namespace: 0,
-                index: 0,
-            },
-            Vec::new(),
-            Vec::new(),
-            Opcode::Call,
-        ),
-        "E800000000",
-        "call    User { namespace: 0, index: 0 }",
-    ));
-
-    // ========================================================
-    // CallUnknown
-    fn call_unknown(rm: RegMem) -> Inst {
-        Inst::call_unknown(rm, Vec::new(), Vec::new(), Opcode::CallIndirect)
-    }
-
-    insns.push((call_unknown(RegMem::reg(rbp)), "FFD5", "call    *%rbp"));
-    insns.push((call_unknown(RegMem::reg(r11)), "41FFD3", "call    *%r11"));
-    insns.push((
-        call_unknown(RegMem::mem(Amode::imm_reg_reg_shift(
-            321,
-            Gpr::new(rsi).unwrap(),
-            Gpr::new(rcx).unwrap(),
-            3,
-        ))),
-        "FF94CE41010000",
-        "call    *321(%rsi,%rcx,8)",
-    ));
-    insns.push((
-        call_unknown(RegMem::mem(Amode::imm_reg_reg_shift(
-            321,
-            Gpr::new(r10).unwrap(),
-            Gpr::new(rdx).unwrap(),
-            2,
-        ))),
-        "41FF949241010000",
-        "call    *321(%r10,%rdx,4)",
-    ));
-
-    // ========================================================
-    // LoadExtName
-    // N.B.: test harness below sets is_pic.
-    insns.push((
-        Inst::LoadExtName {
-            dst: Writable::from_reg(r11),
-            name: Box::new(ExternalName::User {
-                namespace: 0,
-                index: 0,
-            }),
-            offset: 0,
-        },
-        "4C8B1D00000000",
-        "load_ext_name u0:0+0, %r11",
-    ));
-    insns.push((
-        Inst::LoadExtName {
-            dst: Writable::from_reg(r11),
-            name: Box::new(ExternalName::User {
-                namespace: 0,
-                index: 0,
-            }),
-            offset: 0x12345678,
-        },
-        "4C8B1D000000004981C378563412",
-        "load_ext_name u0:0+305419896, %r11",
-    ));
-    insns.push((
-        Inst::LoadExtName {
-            dst: Writable::from_reg(r11),
-            name: Box::new(ExternalName::User {
-                namespace: 0,
-                index: 0,
-            }),
-            offset: -0x12345678,
-        },
-        "4C8B1D000000004981EB78563412",
-        "load_ext_name u0:0+-305419896, %r11",
-    ));
-
-    // ========================================================
-    // Ret
-    insns.push((Inst::ret(), "C3", "ret"));
-
-    // ========================================================
-    // JmpKnown skipped for now
-
-    // ========================================================
-    // JmpCondSymm isn't a real instruction
-
-    // ========================================================
-    // JmpCond skipped for now
-
-    // ========================================================
-    // JmpCondCompound isn't a real instruction
-
-    // ========================================================
-    // JmpUnknown
-    insns.push((Inst::jmp_unknown(RegMem::reg(rbp)), "FFE5", "jmp     *%rbp"));
-    insns.push((
-        Inst::jmp_unknown(RegMem::reg(r11)),
-        "41FFE3",
-        "jmp     *%r11",
-    ));
-    insns.push((
-        Inst::jmp_unknown(RegMem::mem(Amode::imm_reg_reg_shift(
-            321,
-            Gpr::new(rsi).unwrap(),
-            Gpr::new(rcx).unwrap(),
-            3,
-        ))),
-        "FFA4CE41010000",
-        "jmp     *321(%rsi,%rcx,8)",
-    ));
-    insns.push((
-        Inst::jmp_unknown(RegMem::mem(Amode::imm_reg_reg_shift(
-            321,
-            Gpr::new(r10).unwrap(),
-            Gpr::new(rdx).unwrap(),
-            2,
-        ))),
-        "41FFA49241010000",
-        "jmp     *321(%r10,%rdx,4)",
-    ));
-
-    // ========================================================
-    // XMM_CMP_RM_R
-
-    insns.push((
-        Inst::xmm_cmp_rm_r(SseOpcode::Ucomiss, RegMem::reg(xmm1), xmm2),
-        "0F2ED1",
-        "ucomiss %xmm1, %xmm2",
-    ));
-
-    insns.push((
-        Inst::xmm_cmp_rm_r(SseOpcode::Ucomiss, RegMem::reg(xmm0), xmm9),
-        "440F2EC8",
-        "ucomiss %xmm0, %xmm9",
-    ));
-
-    insns.push((
-        Inst::xmm_cmp_rm_r(SseOpcode::Ucomisd, RegMem::reg(xmm13), xmm4),
-        "66410F2EE5",
-        "ucomisd %xmm13, %xmm4",
-    ));
-
-    insns.push((
-        Inst::xmm_cmp_rm_r(SseOpcode::Ucomisd, RegMem::reg(xmm11), xmm12),
-        "66450F2EE3",
-        "ucomisd %xmm11, %xmm12",
-    ));
-
-    // ========================================================
-    // XMM_RM_R: float binary ops
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Addss, RegMem::reg(xmm1), w_xmm0),
-        "F30F58C1",
-        "addss   %xmm1, %xmm0",
-    ));
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Addss, RegMem::reg(xmm11), w_xmm13),
-        "F3450F58EB",
-        "addss   %xmm11, %xmm13",
-    ));
-    insns.push((
-        Inst::xmm_rm_r(
-            SseOpcode::Addss,
-            RegMem::mem(Amode::imm_reg_reg_shift(
-                123,
-                Gpr::new(r10).unwrap(),
-                Gpr::new(rdx).unwrap(),
-                2,
-            )),
-            w_xmm0,
-        ),
-        "F3410F5844927B",
-        "addss   123(%r10,%rdx,4), %xmm0",
-    ));
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Addsd, RegMem::reg(xmm15), w_xmm4),
-        "F2410F58E7",
-        "addsd   %xmm15, %xmm4",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Subss, RegMem::reg(xmm0), w_xmm1),
-        "F30F5CC8",
-        "subss   %xmm0, %xmm1",
-    ));
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Subss, RegMem::reg(xmm12), w_xmm1),
-        "F3410F5CCC",
-        "subss   %xmm12, %xmm1",
-    ));
-    insns.push((
-        Inst::xmm_rm_r(
-            SseOpcode::Subss,
-            RegMem::mem(Amode::imm_reg_reg_shift(
-                321,
-                Gpr::new(r10).unwrap(),
-                Gpr::new(rax).unwrap(),
-                3,
-            )),
-            w_xmm10,
-        ),
-        "F3450F5C94C241010000",
-        "subss   321(%r10,%rax,8), %xmm10",
-    ));
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Subsd, RegMem::reg(xmm5), w_xmm14),
-        "F2440F5CF5",
-        "subsd   %xmm5, %xmm14",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Mulss, RegMem::reg(xmm5), w_xmm4),
-        "F30F59E5",
-        "mulss   %xmm5, %xmm4",
-    ));
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Mulsd, RegMem::reg(xmm5), w_xmm4),
-        "F20F59E5",
-        "mulsd   %xmm5, %xmm4",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Divss, RegMem::reg(xmm8), w_xmm7),
-        "F3410F5EF8",
-        "divss   %xmm8, %xmm7",
-    ));
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Divsd, RegMem::reg(xmm5), w_xmm4),
-        "F20F5EE5",
-        "divsd   %xmm5, %xmm4",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Andps, RegMem::reg(xmm3), w_xmm12),
-        "440F54E3",
-        "andps   %xmm3, %xmm12",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Andnps, RegMem::reg(xmm4), w_xmm11),
-        "440F55DC",
-        "andnps  %xmm4, %xmm11",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Orps, RegMem::reg(xmm1), w_xmm15),
-        "440F56F9",
-        "orps    %xmm1, %xmm15",
-    ));
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Orps, RegMem::reg(xmm5), w_xmm4),
-        "0F56E5",
-        "orps    %xmm5, %xmm4",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Blendvpd, RegMem::reg(xmm15), w_xmm4),
-        "66410F3815E7",
-        "blendvpd %xmm15, %xmm4",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Blendvps, RegMem::reg(xmm2), w_xmm3),
-        "660F3814DA",
-        "blendvps %xmm2, %xmm3",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Pblendvb, RegMem::reg(xmm12), w_xmm13),
-        "66450F3810EC",
-        "pblendvb %xmm12, %xmm13",
-    ));
-
-    // ========================================================
-    // XMM_RM_R: Integer Packed
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Paddb, RegMem::reg(xmm9), w_xmm5),
-        "66410FFCE9",
-        "paddb   %xmm9, %xmm5",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Paddw, RegMem::reg(xmm7), w_xmm6),
-        "660FFDF7",
-        "paddw   %xmm7, %xmm6",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Paddd, RegMem::reg(xmm12), w_xmm13),
-        "66450FFEEC",
-        "paddd   %xmm12, %xmm13",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Paddq, RegMem::reg(xmm1), w_xmm8),
-        "66440FD4C1",
-        "paddq   %xmm1, %xmm8",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Paddsb, RegMem::reg(xmm9), w_xmm5),
-        "66410FECE9",
-        "paddsb  %xmm9, %xmm5",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Paddsw, RegMem::reg(xmm7), w_xmm6),
-        "660FEDF7",
-        "paddsw  %xmm7, %xmm6",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Paddusb, RegMem::reg(xmm12), w_xmm13),
-        "66450FDCEC",
-        "paddusb %xmm12, %xmm13",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Paddusw, RegMem::reg(xmm1), w_xmm8),
-        "66440FDDC1",
-        "paddusw %xmm1, %xmm8",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Psubsb, RegMem::reg(xmm9), w_xmm5),
-        "66410FE8E9",
-        "psubsb  %xmm9, %xmm5",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Psubsw, RegMem::reg(xmm7), w_xmm6),
-        "660FE9F7",
-        "psubsw  %xmm7, %xmm6",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Psubusb, RegMem::reg(xmm12), w_xmm13),
-        "66450FD8EC",
-        "psubusb %xmm12, %xmm13",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Psubusw, RegMem::reg(xmm1), w_xmm8),
-        "66440FD9C1",
-        "psubusw %xmm1, %xmm8",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Pavgb, RegMem::reg(xmm12), w_xmm13),
-        "66450FE0EC",
-        "pavgb   %xmm12, %xmm13",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Pavgw, RegMem::reg(xmm1), w_xmm8),
-        "66440FE3C1",
-        "pavgw   %xmm1, %xmm8",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Psubb, RegMem::reg(xmm5), w_xmm9),
-        "66440FF8CD",
-        "psubb   %xmm5, %xmm9",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Psubw, RegMem::reg(xmm6), w_xmm7),
-        "660FF9FE",
-        "psubw   %xmm6, %xmm7",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Psubd, RegMem::reg(xmm13), w_xmm12),
-        "66450FFAE5",
-        "psubd   %xmm13, %xmm12",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Psubq, RegMem::reg(xmm8), w_xmm1),
-        "66410FFBC8",
-        "psubq   %xmm8, %xmm1",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Pmuldq, RegMem::reg(xmm4), w_xmm15),
-        "66440F3828FC",
-        "pmuldq  %xmm4, %xmm15",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Pmulhw, RegMem::reg(xmm9), w_xmm1),
-        "66410FE5C9",
-        "pmulhw  %xmm9, %xmm1",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Pmulhuw, RegMem::reg(xmm7), w_xmm9),
-        "66440FE4CF",
-        "pmulhuw %xmm7, %xmm9",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Pmulld, RegMem::reg(xmm15), w_xmm6),
-        "66410F3840F7",
-        "pmulld  %xmm15, %xmm6",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Pmullw, RegMem::reg(xmm14), w_xmm1),
-        "66410FD5CE",
-        "pmullw  %xmm14, %xmm1",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r_evex(Avx512Opcode::Vpmullq, RegMem::reg(xmm14), xmm10, w_xmm1),
-        "62D2AD0840CE",
-        "vpmullq %xmm14, %xmm10, %xmm1",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r_evex(Avx512Opcode::Vpermi2b, RegMem::reg(xmm14), xmm10, w_xmm1),
-        "62D22D0875CE",
-        "vpermi2b %xmm14, %xmm10, %xmm1",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r_evex(Avx512Opcode::Vpermi2b, RegMem::reg(xmm1), xmm0, w_xmm2),
-        "62F27D0875D1",
-        "vpermi2b %xmm1, %xmm0, %xmm2",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Pmuludq, RegMem::reg(xmm8), w_xmm9),
-        "66450FF4C8",
-        "pmuludq %xmm8, %xmm9",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Pmaddwd, RegMem::reg(xmm8), w_xmm1),
-        "66410FF5C8",
-        "pmaddwd %xmm8, %xmm1",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Pmaxsb, RegMem::reg(xmm15), w_xmm6),
-        "66410F383CF7",
-        "pmaxsb  %xmm15, %xmm6",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Pmaxsw, RegMem::reg(xmm15), w_xmm6),
-        "66410FEEF7",
-        "pmaxsw  %xmm15, %xmm6",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Pmaxsd, RegMem::reg(xmm15), w_xmm6),
-        "66410F383DF7",
-        "pmaxsd  %xmm15, %xmm6",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Pmaxub, RegMem::reg(xmm14), w_xmm1),
-        "66410FDECE",
-        "pmaxub  %xmm14, %xmm1",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Pmaxuw, RegMem::reg(xmm14), w_xmm1),
-        "66410F383ECE",
-        "pmaxuw  %xmm14, %xmm1",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Pmaxud, RegMem::reg(xmm14), w_xmm1),
-        "66410F383FCE",
-        "pmaxud  %xmm14, %xmm1",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Pminsb, RegMem::reg(xmm8), w_xmm9),
-        "66450F3838C8",
-        "pminsb  %xmm8, %xmm9",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Pminsw, RegMem::reg(xmm8), w_xmm9),
-        "66450FEAC8",
-        "pminsw  %xmm8, %xmm9",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Pminsd, RegMem::reg(xmm8), w_xmm9),
-        "66450F3839C8",
-        "pminsd  %xmm8, %xmm9",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Pminub, RegMem::reg(xmm3), w_xmm2),
-        "660FDAD3",
-        "pminub  %xmm3, %xmm2",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Pminuw, RegMem::reg(xmm3), w_xmm2),
-        "660F383AD3",
-        "pminuw  %xmm3, %xmm2",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Pminud, RegMem::reg(xmm3), w_xmm2),
-        "660F383BD3",
-        "pminud  %xmm3, %xmm2",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Pxor, RegMem::reg(xmm11), w_xmm2),
-        "66410FEFD3",
-        "pxor    %xmm11, %xmm2",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Pshufb, RegMem::reg(xmm11), w_xmm2),
-        "66410F3800D3",
-        "pshufb  %xmm11, %xmm2",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Packssdw, RegMem::reg(xmm11), w_xmm12),
-        "66450F6BE3",
-        "packssdw %xmm11, %xmm12",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Packsswb, RegMem::reg(xmm11), w_xmm2),
-        "66410F63D3",
-        "packsswb %xmm11, %xmm2",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Packusdw, RegMem::reg(xmm13), w_xmm6),
-        "66410F382BF5",
-        "packusdw %xmm13, %xmm6",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Packuswb, RegMem::reg(xmm9), w_xmm4),
-        "66410F67E1",
-        "packuswb %xmm9, %xmm4",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Punpckhbw, RegMem::reg(xmm3), w_xmm2),
-        "660F68D3",
-        "punpckhbw %xmm3, %xmm2",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Punpckhwd, RegMem::reg(xmm13), w_xmm2),
-        "66410F69D5",
-        "punpckhwd %xmm13, %xmm2",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Punpcklbw, RegMem::reg(xmm1), w_xmm8),
-        "66440F60C1",
-        "punpcklbw %xmm1, %xmm8",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Punpcklwd, RegMem::reg(xmm11), w_xmm8),
-        "66450F61C3",
-        "punpcklwd %xmm11, %xmm8",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Unpcklps, RegMem::reg(xmm11), w_xmm2),
-        "410F14D3",
-        "unpcklps %xmm11, %xmm2",
-    ));
-
-    // ========================================================
-    // XMM_RM_R: Integer Conversion
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Cvtdq2ps, RegMem::reg(xmm1), w_xmm8),
-        "440F5BC1",
-        "cvtdq2ps %xmm1, %xmm8",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Cvttpd2dq, RegMem::reg(xmm15), w_xmm7),
-        "66410FE6FF",
-        "cvttpd2dq %xmm15, %xmm7",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r(SseOpcode::Cvttps2dq, RegMem::reg(xmm9), w_xmm8),
-        "F3450F5BC1",
-        "cvttps2dq %xmm9, %xmm8",
-    ));
-
-    // XMM_Mov_R_M: float stores
-    insns.push((
-        Inst::xmm_mov_r_m(SseOpcode::Movss, xmm15, Amode::imm_reg(128, r12)),
-        "F3450F11BC2480000000",
-        "movss   %xmm15, 128(%r12)",
-    ));
-    insns.push((
-        Inst::xmm_mov_r_m(SseOpcode::Movsd, xmm1, Amode::imm_reg(0, rsi)),
-        "F20F110E",
-        "movsd   %xmm1, 0(%rsi)",
-    ));
-
-    // ========================================================
-    // XMM_MOV: Packed Move
-
-    insns.push((
-        Inst::xmm_mov(SseOpcode::Pmovsxbd, RegMem::reg(xmm6), w_xmm8),
-        "66440F3821C6",
-        "pmovsxbd %xmm6, %xmm8",
-    ));
-
-    insns.push((
-        Inst::xmm_mov(SseOpcode::Pmovsxbw, RegMem::reg(xmm9), w_xmm10),
-        "66450F3820D1",
-        "pmovsxbw %xmm9, %xmm10",
-    ));
-
-    insns.push((
-        Inst::xmm_mov(SseOpcode::Pmovsxbq, RegMem::reg(xmm1), w_xmm1),
-        "660F3822C9",
-        "pmovsxbq %xmm1, %xmm1",
-    ));
-
-    insns.push((
-        Inst::xmm_mov(SseOpcode::Pmovsxwd, RegMem::reg(xmm13), w_xmm10),
-        "66450F3823D5",
-        "pmovsxwd %xmm13, %xmm10",
-    ));
-
-    insns.push((
-        Inst::xmm_mov(SseOpcode::Pmovsxwq, RegMem::reg(xmm12), w_xmm12),
-        "66450F3824E4",
-        "pmovsxwq %xmm12, %xmm12",
-    ));
-
-    insns.push((
-        Inst::xmm_mov(SseOpcode::Pmovsxdq, RegMem::reg(xmm10), w_xmm8),
-        "66450F3825C2",
-        "pmovsxdq %xmm10, %xmm8",
-    ));
-
-    insns.push((
-        Inst::xmm_mov(SseOpcode::Pmovzxbd, RegMem::reg(xmm5), w_xmm6),
-        "660F3831F5",
-        "pmovzxbd %xmm5, %xmm6",
-    ));
-
-    insns.push((
-        Inst::xmm_mov(SseOpcode::Pmovzxbw, RegMem::reg(xmm5), w_xmm13),
-        "66440F3830ED",
-        "pmovzxbw %xmm5, %xmm13",
-    ));
-
-    insns.push((
-        Inst::xmm_mov(SseOpcode::Pmovzxbq, RegMem::reg(xmm10), w_xmm11),
-        "66450F3832DA",
-        "pmovzxbq %xmm10, %xmm11",
-    ));
-
-    insns.push((
-        Inst::xmm_mov(SseOpcode::Pmovzxwd, RegMem::reg(xmm2), w_xmm10),
-        "66440F3833D2",
-        "pmovzxwd %xmm2, %xmm10",
-    ));
-
-    insns.push((
-        Inst::xmm_mov(SseOpcode::Pmovzxwq, RegMem::reg(xmm7), w_xmm4),
-        "660F3834E7",
-        "pmovzxwq %xmm7, %xmm4",
-    ));
-
-    insns.push((
-        Inst::xmm_mov(SseOpcode::Pmovzxdq, RegMem::reg(xmm3), w_xmm4),
-        "660F3835E3",
-        "pmovzxdq %xmm3, %xmm4",
-    ));
-
-    // XmmUnary: moves and unary float ops
-    insns.push((
-        Inst::xmm_unary_rm_r(SseOpcode::Movss, RegMem::reg(xmm13), w_xmm2),
-        "F3410F10D5",
-        "movss   %xmm13, %xmm2",
-    ));
-
-    insns.push((
-        Inst::xmm_unary_rm_r(SseOpcode::Movsd, RegMem::reg(xmm0), w_xmm1),
-        "F20F10C8",
-        "movsd   %xmm0, %xmm1",
-    ));
-    insns.push((
-        Inst::xmm_unary_rm_r(
-            SseOpcode::Movsd,
-            RegMem::mem(Amode::imm_reg(0, rsi)),
-            w_xmm2,
-        ),
-        "F20F1016",
-        "movsd   0(%rsi), %xmm2",
-    ));
-    insns.push((
-        Inst::xmm_unary_rm_r(SseOpcode::Movsd, RegMem::reg(xmm14), w_xmm3),
-        "F2410F10DE",
-        "movsd   %xmm14, %xmm3",
-    ));
-
-    insns.push((
-        Inst::xmm_unary_rm_r(SseOpcode::Movaps, RegMem::reg(xmm5), w_xmm14),
-        "440F28F5",
-        "movaps  %xmm5, %xmm14",
-    ));
-
-    insns.push((
-        Inst::xmm_unary_rm_r(SseOpcode::Sqrtss, RegMem::reg(xmm7), w_xmm8),
-        "F3440F51C7",
-        "sqrtss  %xmm7, %xmm8",
-    ));
-    insns.push((
-        Inst::xmm_unary_rm_r(SseOpcode::Sqrtsd, RegMem::reg(xmm1), w_xmm2),
-        "F20F51D1",
-        "sqrtsd  %xmm1, %xmm2",
-    ));
-
-    insns.push((
-        Inst::xmm_unary_rm_r(SseOpcode::Cvtss2sd, RegMem::reg(xmm0), w_xmm1),
-        "F30F5AC8",
-        "cvtss2sd %xmm0, %xmm1",
-    ));
-    insns.push((
-        Inst::xmm_unary_rm_r(SseOpcode::Cvtsd2ss, RegMem::reg(xmm1), w_xmm0),
-        "F20F5AC1",
-        "cvtsd2ss %xmm1, %xmm0",
-    ));
-
-    insns.push((
-        Inst::xmm_unary_rm_r(SseOpcode::Pabsb, RegMem::reg(xmm2), w_xmm1),
-        "660F381CCA",
-        "pabsb   %xmm2, %xmm1",
-    ));
-    insns.push((
-        Inst::xmm_unary_rm_r(SseOpcode::Pabsw, RegMem::reg(xmm0), w_xmm0),
-        "660F381DC0",
-        "pabsw   %xmm0, %xmm0",
-    ));
-    insns.push((
-        Inst::xmm_unary_rm_r(SseOpcode::Pabsd, RegMem::reg(xmm10), w_xmm11),
-        "66450F381EDA",
-        "pabsd   %xmm10, %xmm11",
-    ));
-
-    insns.push((
-        Inst::xmm_unary_rm_r(SseOpcode::Cvtdq2pd, RegMem::reg(xmm2), w_xmm8),
-        "F3440FE6C2",
-        "cvtdq2pd %xmm2, %xmm8",
-    ));
-
-    insns.push((
-        Inst::xmm_unary_rm_r_evex(Avx512Opcode::Vpabsq, RegMem::reg(xmm2), w_xmm8),
-        "6272FD081FC2",
-        "vpabsq  %xmm2, %xmm8",
-    ));
-
-    insns.push((
-        Inst::xmm_unary_rm_r_evex(Avx512Opcode::Vcvtudq2ps, RegMem::reg(xmm2), w_xmm8),
-        "62717F087AC2",
-        "vcvtudq2ps %xmm2, %xmm8",
-    ));
-
-    insns.push((
-        Inst::xmm_unary_rm_r_evex(Avx512Opcode::Vpopcntb, RegMem::reg(xmm2), w_xmm8),
-        "62727D0854C2",
-        "vpopcntb %xmm2, %xmm8",
-    ));
-
-    insns.push((
-        Inst::xmm_unary_rm_r(SseOpcode::Cvtpd2ps, RegMem::reg(xmm7), w_xmm7),
-        "660F5AFF",
-        "cvtpd2ps %xmm7, %xmm7",
-    ));
-
-    insns.push((
-        Inst::xmm_unary_rm_r(SseOpcode::Cvtps2pd, RegMem::reg(xmm11), w_xmm9),
-        "450F5ACB",
-        "cvtps2pd %xmm11, %xmm9",
-    ));
-
-    // Xmm to int conversions, and conversely.
-
-    insns.push((
-        Inst::xmm_to_gpr(SseOpcode::Movd, xmm0, w_rsi, OperandSize::Size32),
-        "660F7EC6",
-        "movd    %xmm0, %esi",
-    ));
-    insns.push((
-        Inst::xmm_to_gpr(SseOpcode::Movq, xmm2, w_rdi, OperandSize::Size64),
-        "66480F7ED7",
-        "movq    %xmm2, %rdi",
-    ));
-    insns.push((
-        Inst::xmm_to_gpr(SseOpcode::Cvttss2si, xmm0, w_rsi, OperandSize::Size32),
-        "F30F2CF0",
-        "cvttss2si %xmm0, %esi",
-    ));
-    insns.push((
-        Inst::xmm_to_gpr(SseOpcode::Cvttss2si, xmm0, w_rdi, OperandSize::Size64),
-        "F3480F2CF8",
-        "cvttss2si %xmm0, %rdi",
-    ));
-    insns.push((
-        Inst::xmm_to_gpr(SseOpcode::Cvttsd2si, xmm0, w_rax, OperandSize::Size32),
-        "F20F2CC0",
-        "cvttsd2si %xmm0, %eax",
-    ));
-    insns.push((
-        Inst::xmm_to_gpr(SseOpcode::Cvttsd2si, xmm0, w_r15, OperandSize::Size64),
-        "F24C0F2CF8",
-        "cvttsd2si %xmm0, %r15",
-    ));
-
-    insns.push((
-        Inst::xmm_to_gpr(SseOpcode::Pmovmskb, xmm10, w_rax, OperandSize::Size32),
-        "66410FD7C2",
-        "pmovmskb %xmm10, %eax",
-    ));
-    insns.push((
-        Inst::xmm_to_gpr(SseOpcode::Movmskps, xmm2, w_rax, OperandSize::Size32),
-        "0F50C2",
-        "movmskps %xmm2, %eax",
-    ));
-    insns.push((
-        Inst::xmm_to_gpr(SseOpcode::Movmskpd, xmm0, w_rcx, OperandSize::Size32),
-        "660F50C8",
-        "movmskpd %xmm0, %ecx",
-    ));
-
-    insns.push((
-        Inst::gpr_to_xmm(
-            SseOpcode::Movd,
-            RegMem::reg(rax),
-            OperandSize::Size32,
-            w_xmm15,
-        ),
-        "66440F6EF8",
-        "movd    %eax, %xmm15",
-    ));
-    insns.push((
-        Inst::gpr_to_xmm(
-            SseOpcode::Movd,
-            RegMem::mem(Amode::imm_reg(2, r10)),
-            OperandSize::Size32,
-            w_xmm9,
-        ),
-        "66450F6E4A02",
-        "movd    2(%r10), %xmm9",
-    ));
-    insns.push((
-        Inst::gpr_to_xmm(
-            SseOpcode::Movd,
-            RegMem::reg(rsi),
-            OperandSize::Size32,
-            w_xmm1,
-        ),
-        "660F6ECE",
-        "movd    %esi, %xmm1",
-    ));
-    insns.push((
-        Inst::gpr_to_xmm(
-            SseOpcode::Movq,
-            RegMem::reg(rdi),
-            OperandSize::Size64,
-            w_xmm15,
-        ),
-        "664C0F6EFF",
-        "movq    %rdi, %xmm15",
-    ));
-    insns.push((
-        Inst::gpr_to_xmm(
-            SseOpcode::Cvtsi2ss,
-            RegMem::reg(rdi),
-            OperandSize::Size32,
-            w_xmm15,
-        ),
-        "F3440F2AFF",
-        "cvtsi2ss %edi, %xmm15",
-    ));
-    insns.push((
-        Inst::gpr_to_xmm(
-            SseOpcode::Cvtsi2sd,
-            RegMem::reg(rsi),
-            OperandSize::Size64,
-            w_xmm1,
-        ),
-        "F2480F2ACE",
-        "cvtsi2sd %rsi, %xmm1",
-    ));
-
-    // ========================================================
-    // XmmRmi
-    insns.push((
-        Inst::xmm_rmi_reg(SseOpcode::Psraw, RegMemImm::reg(xmm10), w_xmm1),
-        "66410FE1CA",
-        "psraw   %xmm10, %xmm1",
-    ));
-    insns.push((
-        Inst::xmm_rmi_reg(SseOpcode::Pslld, RegMemImm::imm(31), w_xmm1),
-        "660F72F11F",
-        "pslld   $31, %xmm1",
-    ));
-    insns.push((
-        Inst::xmm_rmi_reg(SseOpcode::Psrlq, RegMemImm::imm(1), w_xmm3),
-        "660F73D301",
-        "psrlq   $1, %xmm3",
-    ));
-
-    // ========================================================
-    // XmmRmRImm
-    insns.push((
-        Inst::xmm_rm_r_imm(
-            SseOpcode::Cmppd,
-            RegMem::reg(xmm5),
-            w_xmm1,
-            2,
-            OperandSize::Size32,
-        ),
-        "660FC2CD02",
-        "cmppd   $2, %xmm5, %xmm1",
-    ));
-    insns.push((
-        Inst::xmm_rm_r_imm(
-            SseOpcode::Cmpps,
-            RegMem::reg(xmm15),
-            w_xmm7,
-            0,
-            OperandSize::Size32,
-        ),
-        "410FC2FF00",
-        "cmpps   $0, %xmm15, %xmm7",
-    ));
-    insns.push((
-        Inst::xmm_rm_r_imm(
-            SseOpcode::Palignr,
-            RegMem::reg(xmm1),
-            w_xmm9,
-            3,
-            OperandSize::Size32,
-        ),
-        "66440F3A0FC903",
-        "palignr $3, %xmm1, %xmm9",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r_imm(
-            SseOpcode::Shufps,
-            RegMem::reg(xmm1),
-            w_xmm10,
-            136,
-            OperandSize::Size32,
-        ),
-        "440FC6D188",
-        "shufps  $136, %xmm1, %xmm10",
-    ));
-
-    insns.push((
-        Inst::xmm_rm_r_imm(
-            SseOpcode::Roundps,
-            RegMem::reg(xmm7),
-            w_xmm8,
-            3,
-            OperandSize::Size32,
-        ),
-        "66440F3A08C703",
-        "roundps $3, %xmm7, %xmm8",
-    ));
-    insns.push((
-        Inst::xmm_rm_r_imm(
-            SseOpcode::Roundpd,
-            RegMem::reg(xmm10),
-            w_xmm7,
-            2,
-            OperandSize::Size32,
-        ),
-        "66410F3A09FA02",
-        "roundpd $2, %xmm10, %xmm7",
-    ));
-    insns.push((
-        Inst::xmm_rm_r_imm(
-            SseOpcode::Roundps,
-            RegMem::reg(xmm4),
-            w_xmm8,
-            1,
-            OperandSize::Size32,
-        ),
-        "66440F3A08C401",
-        "roundps $1, %xmm4, %xmm8",
-    ));
-    insns.push((
-        Inst::xmm_rm_r_imm(
-            SseOpcode::Roundpd,
-            RegMem::reg(xmm15),
-            w_xmm15,
-            0,
-            OperandSize::Size32,
-        ),
-        "66450F3A09FF00",
-        "roundpd $0, %xmm15, %xmm15",
-    ));
-
-    // ========================================================
-    // Pertaining to atomics.
-    let am1: SyntheticAmode =
-        Amode::imm_reg_reg_shift(321, Gpr::new(r10).unwrap(), Gpr::new(rdx).unwrap(), 2).into();
-    // `am2` doesn't contribute any 1 bits to the rex prefix, so we must use it when testing
-    // for retention of the apparently-redundant rex prefix in the 8-bit case.
-    let am2: SyntheticAmode = Amode::imm_reg_reg_shift(
-        -12345i32 as u32,
-        Gpr::new(rcx).unwrap(),
-        Gpr::new(rsi).unwrap(),
-        3,
-    )
-    .into();
-
-    // A general 8-bit case.
-    insns.push((
-        Inst::LockCmpxchg {
-            ty: types::I8,
-            mem: am1,
-            replacement: rbx,
-            expected: rax,
-            dst_old: w_rax,
-        },
-        "F0410FB09C9241010000",
-        "lock cmpxchgb %bl, 321(%r10,%rdx,4)",
-    ));
-    // Check redundant rex retention in 8-bit cases.
-    insns.push((
-        Inst::LockCmpxchg {
-            ty: types::I8,
-            mem: am2.clone(),
-            replacement: rdx,
-            expected: rax,
-            dst_old: w_rax,
-        },
-        "F00FB094F1C7CFFFFF",
-        "lock cmpxchgb %dl, -12345(%rcx,%rsi,8)",
-    ));
-    insns.push((
-        Inst::LockCmpxchg {
-            ty: types::I8,
-            mem: am2.clone(),
-            replacement: rsi,
-            expected: rax,
-            dst_old: w_rax,
-        },
-        "F0400FB0B4F1C7CFFFFF",
-        "lock cmpxchgb %sil, -12345(%rcx,%rsi,8)",
-    ));
-    insns.push((
-        Inst::LockCmpxchg {
-            ty: types::I8,
-            mem: am2.clone(),
-            replacement: r10,
-            expected: rax,
-            dst_old: w_rax,
-        },
-        "F0440FB094F1C7CFFFFF",
-        "lock cmpxchgb %r10b, -12345(%rcx,%rsi,8)",
-    ));
-    insns.push((
-        Inst::LockCmpxchg {
-            ty: types::I8,
-            mem: am2.clone(),
-            replacement: r15,
-            expected: rax,
-            dst_old: w_rax,
-        },
-        "F0440FB0BCF1C7CFFFFF",
-        "lock cmpxchgb %r15b, -12345(%rcx,%rsi,8)",
-    ));
-    // 16 bit cases
-    insns.push((
-        Inst::LockCmpxchg {
-            ty: types::I16,
-            mem: am2.clone(),
-            replacement: rsi,
-            expected: rax,
-            dst_old: w_rax,
-        },
-        "66F00FB1B4F1C7CFFFFF",
-        "lock cmpxchgw %si, -12345(%rcx,%rsi,8)",
-    ));
-    insns.push((
-        Inst::LockCmpxchg {
-            ty: types::I16,
-            mem: am2.clone(),
-            replacement: r10,
-            expected: rax,
-            dst_old: w_rax,
-        },
-        "66F0440FB194F1C7CFFFFF",
-        "lock cmpxchgw %r10w, -12345(%rcx,%rsi,8)",
-    ));
-    // 32 bit cases
-    insns.push((
-        Inst::LockCmpxchg {
-            ty: types::I32,
-            mem: am2.clone(),
-            replacement: rsi,
-            expected: rax,
-            dst_old: w_rax,
-        },
-        "F00FB1B4F1C7CFFFFF",
-        "lock cmpxchgl %esi, -12345(%rcx,%rsi,8)",
-    ));
-    insns.push((
-        Inst::LockCmpxchg {
-            ty: types::I32,
-            mem: am2.clone(),
-            replacement: r10,
-            expected: rax,
-            dst_old: w_rax,
-        },
-        "F0440FB194F1C7CFFFFF",
-        "lock cmpxchgl %r10d, -12345(%rcx,%rsi,8)",
-    ));
-    // 64 bit cases
-    insns.push((
-        Inst::LockCmpxchg {
-            ty: types::I64,
-            mem: am2.clone(),
-            replacement: rsi,
-            expected: rax,
-            dst_old: w_rax,
-        },
-        "F0480FB1B4F1C7CFFFFF",
-        "lock cmpxchgq %rsi, -12345(%rcx,%rsi,8)",
-    ));
-    insns.push((
-        Inst::LockCmpxchg {
-            ty: types::I64,
-            mem: am2.clone(),
-            replacement: r10,
-            expected: rax,
-            dst_old: w_rax,
-        },
-        "F04C0FB194F1C7CFFFFF",
-        "lock cmpxchgq %r10, -12345(%rcx,%rsi,8)",
-    ));
-
-    // AtomicRmwSeq
-    insns.push((
-        Inst::AtomicRmwSeq {
-            ty: types::I8,
-            op: inst_common::AtomicRmwOp::Or,
-            address: r9,
-            operand: r10,
-            temp: w_r11,
-            dst_old: w_rax
-        },
-        "490FB6014989C34D09D3F0450FB0190F85EFFFFFFF",
-        "atomically { 8_bits_at_[%r9]) Or= %r10; %rax = old_value_at_[%r9]; %r11, %rflags = trash }"
-    ));
-    insns.push((
-        Inst::AtomicRmwSeq {
-            ty: types::I16,
-            op: inst_common::AtomicRmwOp::And,
-            address: r9,
-            operand: r10,
-            temp: w_r11,
-            dst_old: w_rax
-        },
-        "490FB7014989C34D21D366F0450FB1190F85EEFFFFFF",
-        "atomically { 16_bits_at_[%r9]) And= %r10; %rax = old_value_at_[%r9]; %r11, %rflags = trash }"
-    ));
-    insns.push((
-        Inst::AtomicRmwSeq {
-            ty: types::I32,
-            op: inst_common::AtomicRmwOp::Xchg,
-            address: r9,
-            operand: r10,
-            temp: w_r11,
-            dst_old: w_rax
-        },
-        "418B014989C34D89D3F0450FB1190F85EFFFFFFF",
-        "atomically { 32_bits_at_[%r9]) Xchg= %r10; %rax = old_value_at_[%r9]; %r11, %rflags = trash }"
-    ));
-    insns.push((
-        Inst::AtomicRmwSeq {
-            ty: types::I32,
-            op: inst_common::AtomicRmwOp::Umin,
-            address: r9,
-            operand: r10,
-            temp: w_r11,
-            dst_old: w_rax
-        },
-        "418B014989C34539DA4D0F46DAF0450FB1190F85EBFFFFFF",
-        "atomically { 32_bits_at_[%r9]) Umin= %r10; %rax = old_value_at_[%r9]; %r11, %rflags = trash }"
-    ));
-    insns.push((
-        Inst::AtomicRmwSeq {
-            ty: types::I64,
-            op: inst_common::AtomicRmwOp::Add,
-            address: r9,
-            operand: r10,
-            temp: w_r11,
-            dst_old: w_rax
-        },
-        "498B014989C34D01D3F04D0FB1190F85EFFFFFFF",
-        "atomically { 64_bits_at_[%r9]) Add= %r10; %rax = old_value_at_[%r9]; %r11, %rflags = trash }"
-    ));
-
-    // Fence
-    insns.push((
-        Inst::Fence {
-            kind: FenceKind::MFence,
-        },
-        "0FAEF0",
-        "mfence",
-    ));
-    insns.push((
-        Inst::Fence {
-            kind: FenceKind::LFence,
-        },
-        "0FAEE8",
-        "lfence",
-    ));
-    insns.push((
-        Inst::Fence {
-            kind: FenceKind::SFence,
-        },
-        "0FAEF8",
-        "sfence",
-    ));
-
-    // ========================================================
-    // Misc instructions.
-
-    insns.push((Inst::Hlt, "CC", "hlt"));
-
-    let trap_code = TrapCode::UnreachableCodeReached;
-    insns.push((Inst::Ud2 { trap_code }, "0F0B", "ud2 unreachable"));
-
-    insns.push((
-        Inst::ElfTlsGetAddr {
-            symbol: ExternalName::User {
-                namespace: 0,
-                index: 0,
-            },
-        },
-        "66488D3D00000000666648E800000000",
-        "elf_tls_get_addr User { namespace: 0, index: 0 }",
-    ));
-
-    insns.push((
-        Inst::MachOTlsGetAddr {
-            symbol: ExternalName::User {
-                namespace: 0,
-                index: 0,
-            },
-        },
-        "488B3D00000000FF17",
-        "macho_tls_get_addr User { namespace: 0, index: 0 }",
-    ));
-
-    // ========================================================
-    // Actually run the tests!
-    let mut flag_builder = settings::builder();
-    flag_builder.enable("is_pic").unwrap();
-    let flags = settings::Flags::new(flag_builder);
-
-    use crate::settings::Configurable;
-    let mut isa_flag_builder = x64::settings::builder();
-    isa_flag_builder.enable("has_ssse3").unwrap();
-    isa_flag_builder.enable("has_sse41").unwrap();
-    isa_flag_builder.enable("has_avx512bitalg").unwrap();
-    isa_flag_builder.enable("has_avx512dq").unwrap();
-    isa_flag_builder.enable("has_avx512f").unwrap();
-    isa_flag_builder.enable("has_avx512vbmi").unwrap();
-    isa_flag_builder.enable("has_avx512vl").unwrap();
-    let isa_flags = x64::settings::Flags::new(&flags, isa_flag_builder);
-
-    let rru = regs::create_reg_universe_systemv(&flags);
-    let emit_info = EmitInfo::new(flags, isa_flags);
-    for (insn, expected_encoding, expected_printing) in insns {
-        // Check the printed text is as expected.
-        let actual_printing = insn.show_rru(Some(&rru));
-        assert_eq!(expected_printing, actual_printing);
-        let mut buffer = MachBuffer::new();
-
-        insn.emit(&mut buffer, &emit_info, &mut Default::default());
-
-        // Allow one label just after the instruction (so the offset is 0).
-        let label = buffer.get_label();
-        buffer.bind_label(label);
-
-        let buffer = buffer.finish();
-        let actual_encoding = &buffer.stringify_code_bytes();
-        assert_eq!(expected_encoding, actual_encoding, "{}", expected_printing);
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/inst/mod.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/inst/mod.rs
deleted file mode 100644
index 9bf0fe2f0..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/inst/mod.rs
+++ /dev/null
@@ -1,3053 +0,0 @@
-//! This module defines x86_64-specific machine instruction types.
-
-use crate::binemit::{Addend, CodeOffset, Reloc, StackMap};
-use crate::ir::{types, ExternalName, Opcode, SourceLoc, TrapCode, Type, ValueLabel};
-use crate::isa::x64::abi::X64ABIMachineSpec;
-use crate::isa::x64::settings as x64_settings;
-use crate::isa::CallConv;
-use crate::machinst::*;
-use crate::{settings, CodegenError, CodegenResult};
-use alloc::vec::Vec;
-use regalloc::{
-    PrettyPrint, PrettyPrintSized, RealRegUniverse, Reg, RegClass, RegUsageCollector, SpillSlot,
-    VirtualReg, Writable,
-};
-use smallvec::{smallvec, SmallVec};
-use std::fmt;
-use std::string::{String, ToString};
-
-pub mod args;
-mod emit;
-#[cfg(test)]
-mod emit_tests;
-pub mod regs;
-pub mod unwind;
-
-use args::*;
-use regs::show_ireg_sized;
-
-//=============================================================================
-// Instructions (top level): definition
-
-// `Inst` is defined inside ISLE as `MInst`. We publicly re-export it here.
-pub use super::lower::isle::generated_code::MInst as Inst;
-
-pub(crate) fn low32_will_sign_extend_to_64(x: u64) -> bool {
-    let xs = x as i64;
-    xs == ((xs << 32) >> 32)
-}
-
-impl Inst {
-    /// Retrieve a list of ISA feature sets in which the instruction is available. An empty list
-    /// indicates that the instruction is available in the baseline feature set (i.e. SSE2 and
-    /// below); more than one `InstructionSet` in the list indicates that the instruction is present
-    /// *any* of the included ISA feature sets.
-    fn available_in_any_isa(&self) -> SmallVec<[InstructionSet; 2]> {
-        match self {
-            // These instructions are part of SSE2, which is a basic requirement in Cranelift, and
-            // don't have to be checked.
-            Inst::AluRmiR { .. }
-            | Inst::AtomicRmwSeq { .. }
-            | Inst::CallKnown { .. }
-            | Inst::CallUnknown { .. }
-            | Inst::CheckedDivOrRemSeq { .. }
-            | Inst::Cmove { .. }
-            | Inst::CmpRmiR { .. }
-            | Inst::CvtFloatToSintSeq { .. }
-            | Inst::CvtFloatToUintSeq { .. }
-            | Inst::CvtUint64ToFloatSeq { .. }
-            | Inst::Div { .. }
-            | Inst::EpiloguePlaceholder
-            | Inst::Fence { .. }
-            | Inst::Hlt
-            | Inst::Imm { .. }
-            | Inst::JmpCond { .. }
-            | Inst::JmpIf { .. }
-            | Inst::JmpKnown { .. }
-            | Inst::JmpTableSeq { .. }
-            | Inst::JmpUnknown { .. }
-            | Inst::LoadEffectiveAddress { .. }
-            | Inst::LoadExtName { .. }
-            | Inst::LockCmpxchg { .. }
-            | Inst::Mov64MR { .. }
-            | Inst::MovRM { .. }
-            | Inst::MovRR { .. }
-            | Inst::MovsxRmR { .. }
-            | Inst::MovzxRmR { .. }
-            | Inst::MulHi { .. }
-            | Inst::Neg { .. }
-            | Inst::Not { .. }
-            | Inst::Nop { .. }
-            | Inst::Pop64 { .. }
-            | Inst::Push64 { .. }
-            | Inst::Ret
-            | Inst::Setcc { .. }
-            | Inst::ShiftR { .. }
-            | Inst::SignExtendData { .. }
-            | Inst::TrapIf { .. }
-            | Inst::Ud2 { .. }
-            | Inst::VirtualSPOffsetAdj { .. }
-            | Inst::XmmCmove { .. }
-            | Inst::XmmCmpRmR { .. }
-            | Inst::XmmLoadConst { .. }
-            | Inst::XmmMinMaxSeq { .. }
-            | Inst::XmmUninitializedValue { .. }
-            | Inst::ElfTlsGetAddr { .. }
-            | Inst::MachOTlsGetAddr { .. }
-            | Inst::ValueLabelMarker { .. }
-            | Inst::Unwind { .. } => smallvec![],
-
-            Inst::UnaryRmR { op, .. } => op.available_from(),
-
-            // These use dynamic SSE opcodes.
-            Inst::GprToXmm { op, .. }
-            | Inst::XmmMovRM { op, .. }
-            | Inst::XmmRmiReg { opcode: op, .. }
-            | Inst::XmmRmR { op, .. }
-            | Inst::XmmRmRImm { op, .. }
-            | Inst::XmmToGpr { op, .. }
-            | Inst::XmmUnaryRmR { op, .. } => smallvec![op.available_from()],
-
-            Inst::XmmUnaryRmREvex { op, .. } | Inst::XmmRmREvex { op, .. } => op.available_from(),
-        }
-    }
-}
-
-// Handy constructors for Insts.
-
-impl Inst {
-    pub(crate) fn nop(len: u8) -> Self {
-        debug_assert!(len <= 15);
-        Self::Nop { len }
-    }
-
-    pub(crate) fn alu_rmi_r(
-        size: OperandSize,
-        op: AluRmiROpcode,
-        src: RegMemImm,
-        dst: Writable<Reg>,
-    ) -> Self {
-        debug_assert!(size.is_one_of(&[OperandSize::Size32, OperandSize::Size64]));
-        src.assert_regclass_is(RegClass::I64);
-        debug_assert!(dst.to_reg().get_class() == RegClass::I64);
-        Self::AluRmiR {
-            size,
-            op,
-            src1: Gpr::new(dst.to_reg()).unwrap(),
-            src2: GprMemImm::new(src).unwrap(),
-            dst: WritableGpr::from_writable_reg(dst).unwrap(),
-        }
-    }
-
-    #[allow(dead_code)]
-    pub(crate) fn unary_rm_r(
-        size: OperandSize,
-        op: UnaryRmROpcode,
-        src: RegMem,
-        dst: Writable<Reg>,
-    ) -> Self {
-        src.assert_regclass_is(RegClass::I64);
-        debug_assert!(dst.to_reg().get_class() == RegClass::I64);
-        debug_assert!(size.is_one_of(&[
-            OperandSize::Size16,
-            OperandSize::Size32,
-            OperandSize::Size64
-        ]));
-        Self::UnaryRmR {
-            size,
-            op,
-            src: GprMem::new(src).unwrap(),
-            dst: WritableGpr::from_writable_reg(dst).unwrap(),
-        }
-    }
-
-    pub(crate) fn not(size: OperandSize, src: Writable<Reg>) -> Inst {
-        debug_assert_eq!(src.to_reg().get_class(), RegClass::I64);
-        Inst::Not {
-            size,
-            src: Gpr::new(src.to_reg()).unwrap(),
-            dst: WritableGpr::from_writable_reg(src).unwrap(),
-        }
-    }
-
-    pub(crate) fn div(size: OperandSize, signed: bool, divisor: RegMem) -> Inst {
-        divisor.assert_regclass_is(RegClass::I64);
-        Inst::Div {
-            size,
-            signed,
-            divisor: GprMem::new(divisor).unwrap(),
-            dividend: Gpr::new(regs::rax()).unwrap(),
-            dst_quotient: WritableGpr::from_reg(Gpr::new(regs::rax()).unwrap()),
-            dst_remainder: Writable::from_reg(Gpr::new(regs::rdx()).unwrap()),
-        }
-    }
-
-    pub(crate) fn mul_hi(size: OperandSize, signed: bool, rhs: RegMem) -> Inst {
-        debug_assert!(size.is_one_of(&[
-            OperandSize::Size16,
-            OperandSize::Size32,
-            OperandSize::Size64
-        ]));
-        rhs.assert_regclass_is(RegClass::I64);
-        Inst::MulHi {
-            size,
-            signed,
-            src1: Gpr::new(regs::rax()).unwrap(),
-            src2: GprMem::new(rhs).unwrap(),
-            dst_lo: WritableGpr::from_reg(Gpr::new(regs::rax()).unwrap()),
-            dst_hi: WritableGpr::from_reg(Gpr::new(regs::rdx()).unwrap()),
-        }
-    }
-
-    pub(crate) fn checked_div_or_rem_seq(
-        kind: DivOrRemKind,
-        size: OperandSize,
-        divisor: Writable<Reg>,
-        tmp: Option<Writable<Reg>>,
-    ) -> Inst {
-        debug_assert!(divisor.to_reg().get_class() == RegClass::I64);
-        debug_assert!(tmp
-            .map(|tmp| tmp.to_reg().get_class() == RegClass::I64)
-            .unwrap_or(true));
-        Inst::CheckedDivOrRemSeq {
-            kind,
-            size,
-            divisor: WritableGpr::from_writable_reg(divisor).unwrap(),
-            dividend: Gpr::new(regs::rax()).unwrap(),
-            dst_quotient: Writable::from_reg(Gpr::new(regs::rax()).unwrap()),
-            dst_remainder: Writable::from_reg(Gpr::new(regs::rdx()).unwrap()),
-            tmp: tmp.map(|tmp| WritableGpr::from_writable_reg(tmp).unwrap()),
-        }
-    }
-
-    pub(crate) fn sign_extend_data(size: OperandSize) -> Inst {
-        Inst::SignExtendData {
-            size,
-            src: Gpr::new(regs::rax()).unwrap(),
-            dst: Writable::from_reg(Gpr::new(regs::rdx()).unwrap()),
-        }
-    }
-
-    pub(crate) fn imm(dst_size: OperandSize, simm64: u64, dst: Writable<Reg>) -> Inst {
-        debug_assert!(dst_size.is_one_of(&[OperandSize::Size32, OperandSize::Size64]));
-        debug_assert!(dst.to_reg().get_class() == RegClass::I64);
-        // Try to generate a 32-bit immediate when the upper high bits are zeroed (which matches
-        // the semantics of movl).
-        let dst_size = match dst_size {
-            OperandSize::Size64 if simm64 > u32::max_value() as u64 => OperandSize::Size64,
-            _ => OperandSize::Size32,
-        };
-        Inst::Imm {
-            dst_size,
-            simm64,
-            dst: WritableGpr::from_writable_reg(dst).unwrap(),
-        }
-    }
-
-    pub(crate) fn mov_r_r(size: OperandSize, src: Reg, dst: Writable<Reg>) -> Inst {
-        debug_assert!(size.is_one_of(&[OperandSize::Size32, OperandSize::Size64]));
-        debug_assert!(src.get_class() == RegClass::I64);
-        debug_assert!(dst.to_reg().get_class() == RegClass::I64);
-        let src = Gpr::new(src).unwrap();
-        let dst = WritableGpr::from_writable_reg(dst).unwrap();
-        Inst::MovRR { size, src, dst }
-    }
-
-    // TODO Can be replaced by `Inst::move` (high-level) and `Inst::unary_rm_r` (low-level)
-    pub(crate) fn xmm_mov(op: SseOpcode, src: RegMem, dst: Writable<Reg>) -> Inst {
-        src.assert_regclass_is(RegClass::V128);
-        debug_assert!(dst.to_reg().get_class() == RegClass::V128);
-        Inst::XmmUnaryRmR {
-            op,
-            src: XmmMem::new(src).unwrap(),
-            dst: WritableXmm::from_writable_reg(dst).unwrap(),
-        }
-    }
-
-    pub(crate) fn xmm_load_const(src: VCodeConstant, dst: Writable<Reg>, ty: Type) -> Inst {
-        debug_assert!(dst.to_reg().get_class() == RegClass::V128);
-        debug_assert!(ty.is_vector() && ty.bits() == 128);
-        Inst::XmmLoadConst { src, dst, ty }
-    }
-
-    /// Convenient helper for unary float operations.
-    pub(crate) fn xmm_unary_rm_r(op: SseOpcode, src: RegMem, dst: Writable<Reg>) -> Inst {
-        src.assert_regclass_is(RegClass::V128);
-        debug_assert!(dst.to_reg().get_class() == RegClass::V128);
-        Inst::XmmUnaryRmR {
-            op,
-            src: XmmMem::new(src).unwrap(),
-            dst: WritableXmm::from_writable_reg(dst).unwrap(),
-        }
-    }
-
-    pub(crate) fn xmm_unary_rm_r_evex(op: Avx512Opcode, src: RegMem, dst: Writable<Reg>) -> Inst {
-        src.assert_regclass_is(RegClass::V128);
-        debug_assert!(dst.to_reg().get_class() == RegClass::V128);
-        Inst::XmmUnaryRmREvex {
-            op,
-            src: XmmMem::new(src).unwrap(),
-            dst: WritableXmm::from_writable_reg(dst).unwrap(),
-        }
-    }
-
-    pub(crate) fn xmm_rm_r(op: SseOpcode, src: RegMem, dst: Writable<Reg>) -> Self {
-        src.assert_regclass_is(RegClass::V128);
-        debug_assert!(dst.to_reg().get_class() == RegClass::V128);
-        Inst::XmmRmR {
-            op,
-            src1: Xmm::new(dst.to_reg()).unwrap(),
-            src2: XmmMem::new(src).unwrap(),
-            dst: WritableXmm::from_writable_reg(dst).unwrap(),
-        }
-    }
-
-    pub(crate) fn xmm_rm_r_evex(
-        op: Avx512Opcode,
-        src1: RegMem,
-        src2: Reg,
-        dst: Writable<Reg>,
-    ) -> Self {
-        src1.assert_regclass_is(RegClass::V128);
-        debug_assert!(src2.get_class() == RegClass::V128);
-        debug_assert!(dst.to_reg().get_class() == RegClass::V128);
-        Inst::XmmRmREvex {
-            op,
-            src1: XmmMem::new(src1).unwrap(),
-            src2: Xmm::new(src2).unwrap(),
-            dst: WritableXmm::from_writable_reg(dst).unwrap(),
-        }
-    }
-
-    pub(crate) fn xmm_uninit_value(dst: Writable<Reg>) -> Self {
-        debug_assert!(dst.to_reg().get_class() == RegClass::V128);
-        Inst::XmmUninitializedValue {
-            dst: WritableXmm::from_writable_reg(dst).unwrap(),
-        }
-    }
-
-    pub(crate) fn xmm_mov_r_m(op: SseOpcode, src: Reg, dst: impl Into<SyntheticAmode>) -> Inst {
-        debug_assert!(src.get_class() == RegClass::V128);
-        Inst::XmmMovRM {
-            op,
-            src,
-            dst: dst.into(),
-        }
-    }
-
-    pub(crate) fn xmm_to_gpr(
-        op: SseOpcode,
-        src: Reg,
-        dst: Writable<Reg>,
-        dst_size: OperandSize,
-    ) -> Inst {
-        debug_assert!(src.get_class() == RegClass::V128);
-        debug_assert!(dst.to_reg().get_class() == RegClass::I64);
-        debug_assert!(dst_size.is_one_of(&[OperandSize::Size32, OperandSize::Size64]));
-        Inst::XmmToGpr {
-            op,
-            src: Xmm::new(src).unwrap(),
-            dst: WritableGpr::from_writable_reg(dst).unwrap(),
-            dst_size,
-        }
-    }
-
-    pub(crate) fn gpr_to_xmm(
-        op: SseOpcode,
-        src: RegMem,
-        src_size: OperandSize,
-        dst: Writable<Reg>,
-    ) -> Inst {
-        src.assert_regclass_is(RegClass::I64);
-        debug_assert!(src_size.is_one_of(&[OperandSize::Size32, OperandSize::Size64]));
-        debug_assert!(dst.to_reg().get_class() == RegClass::V128);
-        Inst::GprToXmm {
-            op,
-            src: GprMem::new(src).unwrap(),
-            dst: WritableXmm::from_writable_reg(dst).unwrap(),
-            src_size,
-        }
-    }
-
-    pub(crate) fn xmm_cmp_rm_r(op: SseOpcode, src: RegMem, dst: Reg) -> Inst {
-        src.assert_regclass_is(RegClass::V128);
-        debug_assert!(dst.get_class() == RegClass::V128);
-        let src = XmmMem::new(src).unwrap();
-        let dst = Xmm::new(dst).unwrap();
-        Inst::XmmCmpRmR { op, src, dst }
-    }
-
-    pub(crate) fn cvt_u64_to_float_seq(
-        dst_size: OperandSize,
-        src: Writable<Reg>,
-        tmp_gpr1: Writable<Reg>,
-        tmp_gpr2: Writable<Reg>,
-        dst: Writable<Reg>,
-    ) -> Inst {
-        debug_assert!(dst_size.is_one_of(&[OperandSize::Size32, OperandSize::Size64]));
-        debug_assert!(src.to_reg().get_class() == RegClass::I64);
-        debug_assert!(tmp_gpr1.to_reg().get_class() == RegClass::I64);
-        debug_assert!(tmp_gpr2.to_reg().get_class() == RegClass::I64);
-        debug_assert!(dst.to_reg().get_class() == RegClass::V128);
-        Inst::CvtUint64ToFloatSeq {
-            src: WritableGpr::from_writable_reg(src).unwrap(),
-            dst: WritableXmm::from_writable_reg(dst).unwrap(),
-            tmp_gpr1: WritableGpr::from_writable_reg(tmp_gpr1).unwrap(),
-            tmp_gpr2: WritableGpr::from_writable_reg(tmp_gpr2).unwrap(),
-            dst_size,
-        }
-    }
-
-    pub(crate) fn cvt_float_to_sint_seq(
-        src_size: OperandSize,
-        dst_size: OperandSize,
-        is_saturating: bool,
-        src: Writable<Reg>,
-        dst: Writable<Reg>,
-        tmp_gpr: Writable<Reg>,
-        tmp_xmm: Writable<Reg>,
-    ) -> Inst {
-        debug_assert!(src_size.is_one_of(&[OperandSize::Size32, OperandSize::Size64]));
-        debug_assert!(dst_size.is_one_of(&[OperandSize::Size32, OperandSize::Size64]));
-        debug_assert!(src.to_reg().get_class() == RegClass::V128);
-        debug_assert!(tmp_xmm.to_reg().get_class() == RegClass::V128);
-        debug_assert!(tmp_gpr.to_reg().get_class() == RegClass::I64);
-        debug_assert!(dst.to_reg().get_class() == RegClass::I64);
-        Inst::CvtFloatToSintSeq {
-            src_size,
-            dst_size,
-            is_saturating,
-            src: WritableXmm::from_writable_reg(src).unwrap(),
-            dst: WritableGpr::from_writable_reg(dst).unwrap(),
-            tmp_gpr: WritableGpr::from_writable_reg(tmp_gpr).unwrap(),
-            tmp_xmm: WritableXmm::from_writable_reg(tmp_xmm).unwrap(),
-        }
-    }
-
-    pub(crate) fn cvt_float_to_uint_seq(
-        src_size: OperandSize,
-        dst_size: OperandSize,
-        is_saturating: bool,
-        src: Writable<Reg>,
-        dst: Writable<Reg>,
-        tmp_gpr: Writable<Reg>,
-        tmp_xmm: Writable<Reg>,
-    ) -> Inst {
-        debug_assert!(src_size.is_one_of(&[OperandSize::Size32, OperandSize::Size64]));
-        debug_assert!(dst_size.is_one_of(&[OperandSize::Size32, OperandSize::Size64]));
-        debug_assert!(src.to_reg().get_class() == RegClass::V128);
-        debug_assert!(tmp_xmm.to_reg().get_class() == RegClass::V128);
-        debug_assert!(tmp_gpr.to_reg().get_class() == RegClass::I64);
-        debug_assert!(dst.to_reg().get_class() == RegClass::I64);
-        Inst::CvtFloatToUintSeq {
-            src_size,
-            dst_size,
-            is_saturating,
-            src: WritableXmm::from_writable_reg(src).unwrap(),
-            dst: WritableGpr::from_writable_reg(dst).unwrap(),
-            tmp_gpr: WritableGpr::from_writable_reg(tmp_gpr).unwrap(),
-            tmp_xmm: WritableXmm::from_writable_reg(tmp_xmm).unwrap(),
-        }
-    }
-
-    #[allow(dead_code)]
-    pub(crate) fn xmm_min_max_seq(
-        size: OperandSize,
-        is_min: bool,
-        lhs: Reg,
-        rhs: Reg,
-        dst: Writable<Reg>,
-    ) -> Inst {
-        debug_assert!(size.is_one_of(&[OperandSize::Size32, OperandSize::Size64]));
-        debug_assert_eq!(lhs.get_class(), RegClass::V128);
-        debug_assert_eq!(rhs.get_class(), RegClass::V128);
-        debug_assert_eq!(dst.to_reg().get_class(), RegClass::V128);
-        Inst::XmmMinMaxSeq {
-            size,
-            is_min,
-            lhs: Xmm::new(lhs).unwrap(),
-            rhs: Xmm::new(rhs).unwrap(),
-            dst: WritableXmm::from_writable_reg(dst).unwrap(),
-        }
-    }
-
-    pub(crate) fn xmm_rm_r_imm(
-        op: SseOpcode,
-        src: RegMem,
-        dst: Writable<Reg>,
-        imm: u8,
-        size: OperandSize,
-    ) -> Inst {
-        debug_assert!(size.is_one_of(&[OperandSize::Size32, OperandSize::Size64]));
-        Inst::XmmRmRImm {
-            op,
-            src1: dst.to_reg(),
-            src2: src,
-            dst,
-            imm,
-            size,
-        }
-    }
-
-    pub(crate) fn movzx_rm_r(ext_mode: ExtMode, src: RegMem, dst: Writable<Reg>) -> Inst {
-        src.assert_regclass_is(RegClass::I64);
-        debug_assert!(dst.to_reg().get_class() == RegClass::I64);
-        let src = GprMem::new(src).unwrap();
-        let dst = WritableGpr::from_writable_reg(dst).unwrap();
-        Inst::MovzxRmR { ext_mode, src, dst }
-    }
-
-    pub(crate) fn xmm_rmi_reg(opcode: SseOpcode, src: RegMemImm, dst: Writable<Reg>) -> Inst {
-        src.assert_regclass_is(RegClass::V128);
-        debug_assert!(dst.to_reg().get_class() == RegClass::V128);
-        Inst::XmmRmiReg {
-            opcode,
-            src1: Xmm::new(dst.to_reg()).unwrap(),
-            src2: XmmMemImm::new(src).unwrap(),
-            dst: WritableXmm::from_writable_reg(dst).unwrap(),
-        }
-    }
-
-    pub(crate) fn movsx_rm_r(ext_mode: ExtMode, src: RegMem, dst: Writable<Reg>) -> Inst {
-        src.assert_regclass_is(RegClass::I64);
-        debug_assert!(dst.to_reg().get_class() == RegClass::I64);
-        let src = GprMem::new(src).unwrap();
-        let dst = WritableGpr::from_writable_reg(dst).unwrap();
-        Inst::MovsxRmR { ext_mode, src, dst }
-    }
-
-    pub(crate) fn mov64_m_r(src: impl Into<SyntheticAmode>, dst: Writable<Reg>) -> Inst {
-        debug_assert!(dst.to_reg().get_class() == RegClass::I64);
-        Inst::Mov64MR {
-            src: src.into(),
-            dst: WritableGpr::from_writable_reg(dst).unwrap(),
-        }
-    }
-
-    /// A convenience function to be able to use a RegMem as the source of a move.
-    pub(crate) fn mov64_rm_r(src: RegMem, dst: Writable<Reg>) -> Inst {
-        src.assert_regclass_is(RegClass::I64);
-        match src {
-            RegMem::Reg { reg } => Self::mov_r_r(OperandSize::Size64, reg, dst),
-            RegMem::Mem { addr } => Self::mov64_m_r(addr, dst),
-        }
-    }
-
-    pub(crate) fn mov_r_m(size: OperandSize, src: Reg, dst: impl Into<SyntheticAmode>) -> Inst {
-        debug_assert!(src.get_class() == RegClass::I64);
-        Inst::MovRM {
-            size,
-            src: Gpr::new(src).unwrap(),
-            dst: dst.into(),
-        }
-    }
-
-    pub(crate) fn lea(addr: impl Into<SyntheticAmode>, dst: Writable<Reg>) -> Inst {
-        debug_assert!(dst.to_reg().get_class() == RegClass::I64);
-        Inst::LoadEffectiveAddress {
-            addr: addr.into(),
-            dst: WritableGpr::from_writable_reg(dst).unwrap(),
-        }
-    }
-
-    pub(crate) fn shift_r(
-        size: OperandSize,
-        kind: ShiftKind,
-        num_bits: Option<u8>,
-        dst: Writable<Reg>,
-    ) -> Inst {
-        debug_assert!(if let Some(num_bits) = num_bits {
-            num_bits < size.to_bits()
-        } else {
-            true
-        });
-        debug_assert!(dst.to_reg().get_class() == RegClass::I64);
-        Inst::ShiftR {
-            size,
-            kind,
-            src: Gpr::new(dst.to_reg()).unwrap(),
-            num_bits: Imm8Gpr::new(match num_bits {
-                Some(imm) => Imm8Reg::Imm8 { imm },
-                None => Imm8Reg::Reg { reg: regs::rcx() },
-            })
-            .unwrap(),
-            dst: WritableGpr::from_writable_reg(dst).unwrap(),
-        }
-    }
-
-    /// Does a comparison of dst - src for operands of size `size`, as stated by the machine
-    /// instruction semantics. Be careful with the order of parameters!
-    pub(crate) fn cmp_rmi_r(size: OperandSize, src: RegMemImm, dst: Reg) -> Inst {
-        src.assert_regclass_is(RegClass::I64);
-        debug_assert_eq!(dst.get_class(), RegClass::I64);
-        Inst::CmpRmiR {
-            size,
-            src: GprMemImm::new(src).unwrap(),
-            dst: Gpr::new(dst).unwrap(),
-            opcode: CmpOpcode::Cmp,
-        }
-    }
-
-    /// Does a comparison of dst & src for operands of size `size`.
-    pub(crate) fn test_rmi_r(size: OperandSize, src: RegMemImm, dst: Reg) -> Inst {
-        src.assert_regclass_is(RegClass::I64);
-        debug_assert_eq!(dst.get_class(), RegClass::I64);
-        Inst::CmpRmiR {
-            size,
-            src: GprMemImm::new(src).unwrap(),
-            dst: Gpr::new(dst).unwrap(),
-            opcode: CmpOpcode::Test,
-        }
-    }
-
-    pub(crate) fn trap(trap_code: TrapCode) -> Inst {
-        Inst::Ud2 {
-            trap_code: trap_code,
-        }
-    }
-
-    pub(crate) fn setcc(cc: CC, dst: Writable<Reg>) -> Inst {
-        debug_assert!(dst.to_reg().get_class() == RegClass::I64);
-        let dst = WritableGpr::from_writable_reg(dst).unwrap();
-        Inst::Setcc { cc, dst }
-    }
-
-    pub(crate) fn cmove(size: OperandSize, cc: CC, src: RegMem, dst: Writable<Reg>) -> Inst {
-        debug_assert!(size.is_one_of(&[
-            OperandSize::Size16,
-            OperandSize::Size32,
-            OperandSize::Size64
-        ]));
-        debug_assert!(dst.to_reg().get_class() == RegClass::I64);
-        Inst::Cmove {
-            size,
-            cc,
-            consequent: GprMem::new(src).unwrap(),
-            alternative: Gpr::new(dst.to_reg()).unwrap(),
-            dst: WritableGpr::from_writable_reg(dst).unwrap(),
-        }
-    }
-
-    pub(crate) fn xmm_cmove(size: OperandSize, cc: CC, src: RegMem, dst: Writable<Reg>) -> Inst {
-        debug_assert!(size.is_one_of(&[OperandSize::Size32, OperandSize::Size64]));
-        src.assert_regclass_is(RegClass::V128);
-        debug_assert!(dst.to_reg().get_class() == RegClass::V128);
-        let src = XmmMem::new(src).unwrap();
-        let dst = WritableXmm::from_writable_reg(dst).unwrap();
-        Inst::XmmCmove {
-            size,
-            cc,
-            consequent: src,
-            alternative: dst.to_reg(),
-            dst,
-        }
-    }
-
-    pub(crate) fn push64(src: RegMemImm) -> Inst {
-        src.assert_regclass_is(RegClass::I64);
-        let src = GprMemImm::new(src).unwrap();
-        Inst::Push64 { src }
-    }
-
-    pub(crate) fn pop64(dst: Writable<Reg>) -> Inst {
-        debug_assert!(dst.to_reg().get_class() == RegClass::I64);
-        let dst = WritableGpr::from_writable_reg(dst).unwrap();
-        Inst::Pop64 { dst }
-    }
-
-    pub(crate) fn call_known(
-        dest: ExternalName,
-        uses: Vec<Reg>,
-        defs: Vec<Writable<Reg>>,
-        opcode: Opcode,
-    ) -> Inst {
-        Inst::CallKnown {
-            dest,
-            uses,
-            defs,
-            opcode,
-        }
-    }
-
-    pub(crate) fn call_unknown(
-        dest: RegMem,
-        uses: Vec<Reg>,
-        defs: Vec<Writable<Reg>>,
-        opcode: Opcode,
-    ) -> Inst {
-        dest.assert_regclass_is(RegClass::I64);
-        Inst::CallUnknown {
-            dest,
-            uses,
-            defs,
-            opcode,
-        }
-    }
-
-    pub(crate) fn ret() -> Inst {
-        Inst::Ret
-    }
-
-    pub(crate) fn epilogue_placeholder() -> Inst {
-        Inst::EpiloguePlaceholder
-    }
-
-    pub(crate) fn jmp_known(dst: MachLabel) -> Inst {
-        Inst::JmpKnown { dst }
-    }
-
-    pub(crate) fn jmp_if(cc: CC, taken: MachLabel) -> Inst {
-        Inst::JmpIf { cc, taken }
-    }
-
-    pub(crate) fn jmp_cond(cc: CC, taken: MachLabel, not_taken: MachLabel) -> Inst {
-        Inst::JmpCond {
-            cc,
-            taken,
-            not_taken,
-        }
-    }
-
-    pub(crate) fn jmp_unknown(target: RegMem) -> Inst {
-        target.assert_regclass_is(RegClass::I64);
-        Inst::JmpUnknown { target }
-    }
-
-    pub(crate) fn trap_if(cc: CC, trap_code: TrapCode) -> Inst {
-        Inst::TrapIf { cc, trap_code }
-    }
-
-    /// Choose which instruction to use for loading a register value from memory. For loads smaller
-    /// than 64 bits, this method expects a way to extend the value (i.e. [ExtKind::SignExtend],
-    /// [ExtKind::ZeroExtend]); loads with no extension necessary will ignore this.
-    pub(crate) fn load(
-        ty: Type,
-        from_addr: impl Into<SyntheticAmode>,
-        to_reg: Writable<Reg>,
-        ext_kind: ExtKind,
-    ) -> Inst {
-        let rc = to_reg.to_reg().get_class();
-        match rc {
-            RegClass::I64 => {
-                let ext_mode = match ty.bytes() {
-                    1 => Some(ExtMode::BQ),
-                    2 => Some(ExtMode::WQ),
-                    4 => Some(ExtMode::LQ),
-                    8 => None,
-                    _ => unreachable!("the type should never use a scalar load: {}", ty),
-                };
-                if let Some(ext_mode) = ext_mode {
-                    // Values smaller than 64 bits must be extended in some way.
-                    match ext_kind {
-                        ExtKind::SignExtend => {
-                            Inst::movsx_rm_r(ext_mode, RegMem::mem(from_addr), to_reg)
-                        }
-                        ExtKind::ZeroExtend => {
-                            Inst::movzx_rm_r(ext_mode, RegMem::mem(from_addr), to_reg)
-                        }
-                        ExtKind::None => panic!(
-                            "expected an extension kind for extension mode: {:?}",
-                            ext_mode
-                        ),
-                    }
-                } else {
-                    // 64-bit values can be moved directly.
-                    Inst::mov64_m_r(from_addr, to_reg)
-                }
-            }
-            RegClass::V128 => {
-                let opcode = match ty {
-                    types::F32 => SseOpcode::Movss,
-                    types::F64 => SseOpcode::Movsd,
-                    types::F32X4 => SseOpcode::Movups,
-                    types::F64X2 => SseOpcode::Movupd,
-                    _ if ty.is_vector() && ty.bits() == 128 => SseOpcode::Movdqu,
-                    _ => unimplemented!("unable to load type: {}", ty),
-                };
-                Inst::xmm_unary_rm_r(opcode, RegMem::mem(from_addr), to_reg)
-            }
-            _ => panic!("unable to generate load for register class: {:?}", rc),
-        }
-    }
-
-    /// Choose which instruction to use for storing a register value to memory.
-    pub(crate) fn store(ty: Type, from_reg: Reg, to_addr: impl Into<SyntheticAmode>) -> Inst {
-        let rc = from_reg.get_class();
-        match rc {
-            RegClass::I64 => Inst::mov_r_m(OperandSize::from_ty(ty), from_reg, to_addr),
-            RegClass::V128 => {
-                let opcode = match ty {
-                    types::F32 => SseOpcode::Movss,
-                    types::F64 => SseOpcode::Movsd,
-                    types::F32X4 => SseOpcode::Movups,
-                    types::F64X2 => SseOpcode::Movupd,
-                    _ if ty.is_vector() && ty.bits() == 128 => SseOpcode::Movdqu,
-                    _ => unimplemented!("unable to store type: {}", ty),
-                };
-                Inst::xmm_mov_r_m(opcode, from_reg, to_addr)
-            }
-            _ => panic!("unable to generate store for register class: {:?}", rc),
-        }
-    }
-}
-
-// Inst helpers.
-
-impl Inst {
-    /// In certain cases, instructions of this format can act as a definition of an XMM register,
-    /// producing a value that is independent of its initial value.
-    ///
-    /// For example, a vector equality comparison (`cmppd` or `cmpps`) that compares a register to
-    /// itself will generate all ones as a result, regardless of its value. From the register
-    /// allocator's point of view, we should (i) record the first register, which is normally a
-    /// mod, as a def instead; and (ii) not record the second register as a use, because it is the
-    /// same as the first register (already handled).
-    fn produces_const(&self) -> bool {
-        match self {
-            Self::AluRmiR { op, src2, dst, .. } => {
-                src2.clone().to_reg_mem_imm().to_reg() == Some(dst.to_reg().to_reg())
-                    && (*op == AluRmiROpcode::Xor || *op == AluRmiROpcode::Sub)
-            }
-
-            Self::XmmRmR { op, src2, dst, .. } => {
-                src2.clone().to_reg_mem().to_reg() == Some(dst.to_reg().to_reg())
-                    && (*op == SseOpcode::Xorps
-                        || *op == SseOpcode::Xorpd
-                        || *op == SseOpcode::Pxor
-                        || *op == SseOpcode::Pcmpeqb
-                        || *op == SseOpcode::Pcmpeqw
-                        || *op == SseOpcode::Pcmpeqd
-                        || *op == SseOpcode::Pcmpeqq)
-            }
-
-            Self::XmmRmRImm {
-                op, src2, dst, imm, ..
-            } => {
-                src2.to_reg() == Some(dst.to_reg())
-                    && (*op == SseOpcode::Cmppd || *op == SseOpcode::Cmpps)
-                    && *imm == FcmpImm::Equal.encode()
-            }
-
-            _ => false,
-        }
-    }
-
-    /// Translate three-operand instructions into a sequence of two-operand
-    /// instructions.
-    ///
-    /// For example:
-    ///
-    /// ```text
-    /// x = add a, b
-    /// ```
-    ///
-    /// Becomes:
-    ///
-    /// ```text
-    /// mov x, a
-    /// add x, b
-    /// ```
-    ///
-    /// The three-operand form for instructions allows our ISLE DSL code to have
-    /// a value-based, SSA view of the world. This method is responsible for
-    /// undoing that.
-    ///
-    /// Note that register allocation cleans up most of these inserted `mov`s
-    /// with its move coalescing.
-    pub(crate) fn mov_mitosis(mut self) -> impl Iterator<Item = Self> {
-        log::trace!("mov_mitosis({:?})", self);
-
-        let mut insts = SmallVec::<[Self; 4]>::new();
-
-        match &mut self {
-            Inst::AluRmiR { src1, dst, .. } => {
-                if *src1 != dst.to_reg() {
-                    debug_assert!(src1.is_virtual());
-                    insts.push(Self::gen_move(
-                        dst.to_writable_reg(),
-                        src1.to_reg(),
-                        types::I64,
-                    ));
-                    *src1 = dst.to_reg();
-                }
-                insts.push(self);
-            }
-            Inst::XmmRmiReg { src1, dst, .. } => {
-                if *src1 != dst.to_reg() {
-                    debug_assert!(src1.is_virtual());
-                    insts.push(Self::gen_move(
-                        dst.to_writable_reg(),
-                        src1.to_reg(),
-                        types::I8X16,
-                    ));
-                    *src1 = dst.to_reg();
-                }
-                insts.push(self);
-            }
-            Inst::XmmRmR { src1, dst, .. } => {
-                if *src1 != dst.to_reg() {
-                    debug_assert!(src1.is_virtual());
-                    insts.push(Self::gen_move(
-                        dst.to_writable_reg(),
-                        src1.to_reg(),
-                        types::I8X16,
-                    ));
-                    *src1 = dst.to_reg();
-                }
-                insts.push(self);
-            }
-            Inst::XmmRmRImm { src1, dst, .. } => {
-                if *src1 != dst.to_reg() {
-                    debug_assert!(src1.is_virtual());
-                    insts.push(Self::gen_move(*dst, *src1, types::I8X16));
-                    *src1 = dst.to_reg();
-                }
-                insts.push(self);
-            }
-            Inst::XmmMinMaxSeq { rhs, dst, .. } => {
-                if *rhs != dst.to_reg() {
-                    debug_assert!(rhs.is_virtual());
-                    insts.push(Self::gen_move(
-                        dst.to_writable_reg(),
-                        rhs.to_reg(),
-                        types::I8X16,
-                    ));
-                    *rhs = dst.to_reg();
-                }
-                insts.push(self);
-            }
-            Inst::Cmove {
-                size,
-                alternative,
-                dst,
-                ..
-            } => {
-                if *alternative != dst.to_reg() {
-                    debug_assert!(alternative.is_virtual());
-                    insts.push(Self::mov_r_r(
-                        *size,
-                        alternative.to_reg(),
-                        dst.to_writable_reg(),
-                    ));
-                    *alternative = dst.to_reg();
-                }
-                insts.push(self);
-            }
-            Inst::XmmCmove {
-                alternative, dst, ..
-            } => {
-                if *alternative != dst.to_reg() {
-                    debug_assert!(alternative.is_virtual());
-                    insts.push(Self::gen_move(
-                        dst.to_writable_reg(),
-                        alternative.to_reg(),
-                        types::F32X4,
-                    ));
-                    *alternative = dst.to_reg();
-                }
-                insts.push(self);
-            }
-            Inst::Not { src, dst, .. } | Inst::Neg { src, dst, .. } => {
-                if *src != dst.to_reg() {
-                    debug_assert!(src.is_virtual());
-                    insts.push(Self::gen_move(
-                        dst.to_writable_reg(),
-                        src.to_reg(),
-                        types::I64,
-                    ));
-                    *src = dst.to_reg();
-                }
-                insts.push(self);
-            }
-            Inst::Div {
-                dividend,
-                dst_quotient,
-                dst_remainder,
-                ..
-            }
-            | Inst::CheckedDivOrRemSeq {
-                dividend,
-                dst_quotient,
-                dst_remainder,
-                ..
-            } => {
-                if *dividend != regs::rax() {
-                    debug_assert!(dividend.is_virtual());
-                    insts.push(Self::gen_move(
-                        Writable::from_reg(regs::rax()),
-                        dividend.to_reg(),
-                        types::I64,
-                    ));
-                    *dividend = Gpr::new(regs::rax()).unwrap();
-                }
-                let mut quotient_mov = None;
-                if dst_quotient.to_reg() != regs::rax() {
-                    debug_assert!(dst_quotient.to_reg().is_virtual());
-                    quotient_mov = Some(Self::gen_move(
-                        dst_quotient.to_writable_reg(),
-                        regs::rax(),
-                        types::I64,
-                    ));
-                    *dst_quotient = Writable::from_reg(Gpr::new(regs::rax()).unwrap());
-                }
-                let mut remainder_mov = None;
-                if dst_remainder.to_reg() != regs::rdx() {
-                    debug_assert!(dst_remainder.to_reg().is_virtual());
-                    remainder_mov = Some(Self::gen_move(
-                        dst_remainder.to_writable_reg(),
-                        regs::rdx(),
-                        types::I64,
-                    ));
-                    *dst_remainder = Writable::from_reg(Gpr::new(regs::rdx()).unwrap());
-                }
-                insts.push(self);
-                insts.extend(quotient_mov);
-                insts.extend(remainder_mov);
-            }
-            Inst::MulHi {
-                src1,
-                dst_lo,
-                dst_hi,
-                ..
-            } => {
-                if *src1 != regs::rax() {
-                    debug_assert!(src1.is_virtual());
-                    insts.push(Self::gen_move(
-                        Writable::from_reg(regs::rax()),
-                        src1.to_reg(),
-                        types::I64,
-                    ));
-                    *src1 = Gpr::new(regs::rax()).unwrap();
-                }
-                let mut dst_lo_mov = None;
-                if dst_lo.to_reg() != regs::rax() {
-                    debug_assert!(dst_lo.to_reg().is_virtual());
-                    dst_lo_mov = Some(Self::gen_move(
-                        dst_lo.to_writable_reg(),
-                        regs::rax(),
-                        types::I64,
-                    ));
-                    *dst_lo = Writable::from_reg(Gpr::new(regs::rax()).unwrap());
-                }
-                let mut dst_hi_mov = None;
-                if dst_hi.to_reg() != regs::rdx() {
-                    debug_assert!(dst_hi.to_reg().is_virtual());
-                    dst_hi_mov = Some(Self::gen_move(
-                        dst_hi.to_writable_reg(),
-                        regs::rdx(),
-                        types::I64,
-                    ));
-                    *dst_hi = Writable::from_reg(Gpr::new(regs::rdx()).unwrap());
-                }
-                insts.push(self);
-                insts.extend(dst_lo_mov);
-                insts.extend(dst_hi_mov);
-            }
-            Inst::SignExtendData { src, dst, .. } => {
-                if *src != regs::rax() {
-                    debug_assert!(src.is_virtual());
-                    insts.push(Self::gen_move(
-                        Writable::from_reg(regs::rax()),
-                        src.to_reg(),
-                        types::I64,
-                    ));
-                    *src = Gpr::new(regs::rax()).unwrap();
-                }
-                let mut dst_mov = None;
-                if dst.to_reg() != regs::rax() {
-                    debug_assert!(dst.to_reg().is_virtual());
-                    dst_mov = Some(Self::gen_move(
-                        dst.to_writable_reg(),
-                        dst.to_reg().to_reg(),
-                        types::I64,
-                    ));
-                    *dst = Writable::from_reg(Gpr::new(regs::rax()).unwrap());
-                }
-                insts.push(self);
-                insts.extend(dst_mov);
-            }
-            Inst::ShiftR {
-                src, num_bits, dst, ..
-            } => {
-                if *src != dst.to_reg() {
-                    debug_assert!(src.is_virtual());
-                    insts.push(Self::gen_move(
-                        dst.to_writable_reg(),
-                        src.to_reg(),
-                        types::I64,
-                    ));
-                    *src = dst.to_reg();
-                }
-                if let Imm8Reg::Reg { reg } = num_bits.clone().to_imm8_reg() {
-                    if reg != regs::rcx() {
-                        debug_assert!(reg.is_virtual());
-                        insts.push(Self::gen_move(
-                            Writable::from_reg(regs::rcx()),
-                            reg,
-                            types::I64,
-                        ));
-                        *num_bits = Imm8Gpr::new(Imm8Reg::Reg { reg: regs::rcx() }).unwrap();
-                    }
-                }
-                insts.push(self);
-            }
-            Inst::LockCmpxchg {
-                ty,
-                expected,
-                dst_old,
-                ..
-            } => {
-                if *expected != regs::rax() {
-                    debug_assert!(expected.is_virtual());
-                    insts.push(Self::gen_move(
-                        Writable::from_reg(regs::rax()),
-                        *expected,
-                        *ty,
-                    ));
-                }
-                let mut dst_old_mov = None;
-                if dst_old.to_reg() != regs::rax() {
-                    debug_assert!(dst_old.to_reg().is_virtual());
-                    dst_old_mov = Some(Self::gen_move(*dst_old, regs::rax(), *ty));
-                    *dst_old = Writable::from_reg(regs::rax());
-                }
-                insts.push(self);
-                insts.extend(dst_old_mov);
-            }
-            Inst::AtomicRmwSeq {
-                ty,
-                address,
-                operand,
-                dst_old,
-                ..
-            } => {
-                if *address != regs::r9() {
-                    debug_assert!(address.is_virtual());
-                    insts.push(Self::gen_move(
-                        Writable::from_reg(regs::r9()),
-                        *address,
-                        types::I64,
-                    ));
-                    *address = regs::r9();
-                }
-                if *operand != regs::r10() {
-                    debug_assert!(operand.is_virtual());
-                    insts.push(Self::gen_move(
-                        Writable::from_reg(regs::r10()),
-                        *operand,
-                        *ty,
-                    ));
-                    *address = regs::r10();
-                }
-                let mut dst_old_mov = None;
-                if dst_old.to_reg() != regs::rax() {
-                    debug_assert!(dst_old.to_reg().is_virtual());
-                    dst_old_mov = Some(Self::gen_move(*dst_old, regs::rax(), *ty));
-                    *dst_old = Writable::from_reg(regs::rax());
-                }
-                insts.push(self);
-                insts.extend(dst_old_mov);
-            }
-            // No other instruction needs 3-operand to 2-operand legalization.
-            _ => insts.push(self),
-        }
-
-        if log::log_enabled!(log::Level::Trace) {
-            for inst in &insts {
-                log::trace!("  -> {:?}", inst);
-            }
-        }
-
-        insts.into_iter()
-    }
-}
-
-//=============================================================================
-// Instructions: printing
-
-impl PrettyPrint for Inst {
-    fn show_rru(&self, mb_rru: Option<&RealRegUniverse>) -> String {
-        fn ljustify(s: String) -> String {
-            let w = 7;
-            if s.len() >= w {
-                s
-            } else {
-                let need = usize::min(w, w - s.len());
-                s + &format!("{nil: <width$}", nil = "", width = need)
-            }
-        }
-
-        fn ljustify2(s1: String, s2: String) -> String {
-            ljustify(s1 + &s2)
-        }
-
-        fn suffix_lq(size: OperandSize) -> String {
-            match size {
-                OperandSize::Size32 => "l",
-                OperandSize::Size64 => "q",
-                _ => unreachable!(),
-            }
-            .to_string()
-        }
-
-        fn suffix_lqb(size: OperandSize, is_8: bool) -> String {
-            match (size, is_8) {
-                (_, true) => "b",
-                (OperandSize::Size32, false) => "l",
-                (OperandSize::Size64, false) => "q",
-                _ => unreachable!(),
-            }
-            .to_string()
-        }
-
-        fn size_lqb(size: OperandSize, is_8: bool) -> u8 {
-            if is_8 {
-                return 1;
-            }
-            size.to_bytes()
-        }
-
-        fn suffix_bwlq(size: OperandSize) -> String {
-            match size {
-                OperandSize::Size8 => "b".to_string(),
-                OperandSize::Size16 => "w".to_string(),
-                OperandSize::Size32 => "l".to_string(),
-                OperandSize::Size64 => "q".to_string(),
-            }
-        }
-
-        match self {
-            Inst::Nop { len } => format!("{} len={}", ljustify("nop".to_string()), len),
-
-            Inst::AluRmiR {
-                size,
-                op,
-                src1: _,
-                src2,
-                dst,
-            } => format!(
-                "{} {}, {}",
-                ljustify2(op.to_string(), suffix_lqb(*size, op.is_8bit())),
-                src2.show_rru_sized(mb_rru, size_lqb(*size, op.is_8bit())),
-                show_ireg_sized(dst.to_reg().to_reg(), mb_rru, size_lqb(*size, op.is_8bit())),
-            ),
-
-            Inst::UnaryRmR { src, dst, op, size } => format!(
-                "{} {}, {}",
-                ljustify2(op.to_string(), suffix_bwlq(*size)),
-                src.show_rru_sized(mb_rru, size.to_bytes()),
-                show_ireg_sized(dst.to_reg().to_reg(), mb_rru, size.to_bytes()),
-            ),
-
-            Inst::Not { size, src: _, dst } => format!(
-                "{} {}",
-                ljustify2("not".to_string(), suffix_bwlq(*size)),
-                show_ireg_sized(dst.to_reg().to_reg(), mb_rru, size.to_bytes())
-            ),
-
-            Inst::Neg { size, src: _, dst } => format!(
-                "{} {}",
-                ljustify2("neg".to_string(), suffix_bwlq(*size)),
-                show_ireg_sized(dst.to_reg().to_reg(), mb_rru, size.to_bytes())
-            ),
-
-            Inst::Div {
-                size,
-                signed,
-                divisor,
-                ..
-            } => format!(
-                "{} {}",
-                ljustify(if *signed {
-                    "idiv".to_string()
-                } else {
-                    "div".into()
-                }),
-                divisor.show_rru_sized(mb_rru, size.to_bytes())
-            ),
-
-            Inst::MulHi {
-                size, signed, src2, ..
-            } => format!(
-                "{} {}",
-                ljustify(if *signed {
-                    "imul".to_string()
-                } else {
-                    "mul".to_string()
-                }),
-                src2.show_rru_sized(mb_rru, size.to_bytes())
-            ),
-
-            Inst::CheckedDivOrRemSeq {
-                kind,
-                size,
-                divisor,
-                ..
-            } => format!(
-                "{} $rax:$rdx, {}",
-                match kind {
-                    DivOrRemKind::SignedDiv => "sdiv",
-                    DivOrRemKind::UnsignedDiv => "udiv",
-                    DivOrRemKind::SignedRem => "srem",
-                    DivOrRemKind::UnsignedRem => "urem",
-                },
-                show_ireg_sized(divisor.to_reg().to_reg(), mb_rru, size.to_bytes()),
-            ),
-
-            Inst::SignExtendData { size, .. } => match size {
-                OperandSize::Size8 => "cbw",
-                OperandSize::Size16 => "cwd",
-                OperandSize::Size32 => "cdq",
-                OperandSize::Size64 => "cqo",
-            }
-            .into(),
-
-            Inst::XmmUnaryRmR { op, src, dst, .. } => format!(
-                "{} {}, {}",
-                ljustify(op.to_string()),
-                src.show_rru_sized(mb_rru, op.src_size()),
-                show_ireg_sized(dst.to_reg().to_reg(), mb_rru, 8),
-            ),
-
-            Inst::XmmUnaryRmREvex { op, src, dst, .. } => format!(
-                "{} {}, {}",
-                ljustify(op.to_string()),
-                src.show_rru_sized(mb_rru, 8),
-                show_ireg_sized(dst.to_reg().to_reg(), mb_rru, 8),
-            ),
-
-            Inst::XmmMovRM { op, src, dst, .. } => format!(
-                "{} {}, {}",
-                ljustify(op.to_string()),
-                show_ireg_sized(*src, mb_rru, 8),
-                dst.show_rru(mb_rru),
-            ),
-
-            Inst::XmmRmR { op, src2, dst, .. } => format!(
-                "{} {}, {}",
-                ljustify(op.to_string()),
-                src2.show_rru_sized(mb_rru, 8),
-                show_ireg_sized(dst.to_reg().to_reg(), mb_rru, 8),
-            ),
-
-            Inst::XmmRmREvex {
-                op,
-                src1,
-                src2,
-                dst,
-                ..
-            } => format!(
-                "{} {}, {}, {}",
-                ljustify(op.to_string()),
-                src1.show_rru_sized(mb_rru, 8),
-                show_ireg_sized(src2.to_reg(), mb_rru, 8),
-                show_ireg_sized(dst.to_reg().to_reg(), mb_rru, 8),
-            ),
-
-            Inst::XmmMinMaxSeq {
-                lhs,
-                rhs,
-                dst,
-                is_min,
-                size,
-            } => format!(
-                "{} {}, {}, {}",
-                ljustify2(
-                    if *is_min {
-                        "xmm min seq ".to_string()
-                    } else {
-                        "xmm max seq ".to_string()
-                    },
-                    format!("f{}", size.to_bits())
-                ),
-                show_ireg_sized(lhs.to_reg(), mb_rru, 8),
-                show_ireg_sized(rhs.to_reg(), mb_rru, 8),
-                show_ireg_sized(dst.to_reg().to_reg(), mb_rru, 8),
-            ),
-
-            Inst::XmmRmRImm {
-                op,
-                src2,
-                dst,
-                imm,
-                size,
-                ..
-            } => format!(
-                "{} ${}, {}, {}",
-                ljustify(format!(
-                    "{}{}",
-                    op.to_string(),
-                    if *size == OperandSize::Size64 {
-                        ".w"
-                    } else {
-                        ""
-                    }
-                )),
-                imm,
-                src2.show_rru(mb_rru),
-                dst.show_rru(mb_rru),
-            ),
-
-            Inst::XmmUninitializedValue { dst } => {
-                format!("{} {}", ljustify("uninit".into()), dst.show_rru(mb_rru),)
-            }
-
-            Inst::XmmLoadConst { src, dst, .. } => {
-                format!("load_const {:?}, {}", src, dst.show_rru(mb_rru),)
-            }
-
-            Inst::XmmToGpr {
-                op,
-                src,
-                dst,
-                dst_size,
-            } => {
-                let dst_size = dst_size.to_bytes();
-                format!(
-                    "{} {}, {}",
-                    ljustify(op.to_string()),
-                    src.show_rru(mb_rru),
-                    show_ireg_sized(dst.to_reg().to_reg(), mb_rru, dst_size),
-                )
-            }
-
-            Inst::GprToXmm {
-                op,
-                src,
-                src_size,
-                dst,
-            } => format!(
-                "{} {}, {}",
-                ljustify(op.to_string()),
-                src.show_rru_sized(mb_rru, src_size.to_bytes()),
-                dst.show_rru(mb_rru)
-            ),
-
-            Inst::XmmCmpRmR { op, src, dst } => format!(
-                "{} {}, {}",
-                ljustify(op.to_string()),
-                src.show_rru_sized(mb_rru, 8),
-                show_ireg_sized(dst.to_reg(), mb_rru, 8),
-            ),
-
-            Inst::CvtUint64ToFloatSeq {
-                src, dst, dst_size, ..
-            } => format!(
-                "{} {}, {}",
-                ljustify(format!(
-                    "u64_to_{}_seq",
-                    if *dst_size == OperandSize::Size64 {
-                        "f64"
-                    } else {
-                        "f32"
-                    }
-                )),
-                show_ireg_sized(src.to_reg().to_reg(), mb_rru, 8),
-                dst.show_rru(mb_rru),
-            ),
-
-            Inst::CvtFloatToSintSeq {
-                src,
-                dst,
-                src_size,
-                dst_size,
-                ..
-            } => format!(
-                "{} {}, {}",
-                ljustify(format!(
-                    "cvt_float{}_to_sint{}_seq",
-                    src_size.to_bits(),
-                    dst_size.to_bits()
-                )),
-                show_ireg_sized(src.to_reg().to_reg(), mb_rru, 8),
-                show_ireg_sized(dst.to_reg().to_reg(), mb_rru, dst_size.to_bytes()),
-            ),
-
-            Inst::CvtFloatToUintSeq {
-                src,
-                dst,
-                src_size,
-                dst_size,
-                ..
-            } => format!(
-                "{} {}, {}",
-                ljustify(format!(
-                    "cvt_float{}_to_uint{}_seq",
-                    src_size.to_bits(),
-                    dst_size.to_bits()
-                )),
-                show_ireg_sized(src.to_reg().to_reg(), mb_rru, 8),
-                show_ireg_sized(dst.to_reg().to_reg(), mb_rru, dst_size.to_bytes()),
-            ),
-
-            Inst::Imm {
-                dst_size,
-                simm64,
-                dst,
-            } => {
-                if *dst_size == OperandSize::Size64 {
-                    format!(
-                        "{} ${}, {}",
-                        ljustify("movabsq".to_string()),
-                        *simm64 as i64,
-                        show_ireg_sized(dst.to_reg().to_reg(), mb_rru, 8)
-                    )
-                } else {
-                    format!(
-                        "{} ${}, {}",
-                        ljustify("movl".to_string()),
-                        (*simm64 as u32) as i32,
-                        show_ireg_sized(dst.to_reg().to_reg(), mb_rru, 4)
-                    )
-                }
-            }
-
-            Inst::MovRR { size, src, dst } => format!(
-                "{} {}, {}",
-                ljustify2("mov".to_string(), suffix_lq(*size)),
-                show_ireg_sized(src.to_reg(), mb_rru, size.to_bytes()),
-                show_ireg_sized(dst.to_reg().to_reg(), mb_rru, size.to_bytes())
-            ),
-
-            Inst::MovzxRmR {
-                ext_mode, src, dst, ..
-            } => {
-                if *ext_mode == ExtMode::LQ {
-                    format!(
-                        "{} {}, {}",
-                        ljustify("movl".to_string()),
-                        src.show_rru_sized(mb_rru, ext_mode.src_size()),
-                        show_ireg_sized(dst.to_reg().to_reg(), mb_rru, 4)
-                    )
-                } else {
-                    format!(
-                        "{} {}, {}",
-                        ljustify2("movz".to_string(), ext_mode.to_string()),
-                        src.show_rru_sized(mb_rru, ext_mode.src_size()),
-                        show_ireg_sized(dst.to_reg().to_reg(), mb_rru, ext_mode.dst_size())
-                    )
-                }
-            }
-
-            Inst::Mov64MR { src, dst, .. } => format!(
-                "{} {}, {}",
-                ljustify("movq".to_string()),
-                src.show_rru(mb_rru),
-                dst.show_rru(mb_rru)
-            ),
-
-            Inst::LoadEffectiveAddress { addr, dst } => format!(
-                "{} {}, {}",
-                ljustify("lea".to_string()),
-                addr.show_rru(mb_rru),
-                dst.show_rru(mb_rru)
-            ),
-
-            Inst::MovsxRmR {
-                ext_mode, src, dst, ..
-            } => format!(
-                "{} {}, {}",
-                ljustify2("movs".to_string(), ext_mode.to_string()),
-                src.show_rru_sized(mb_rru, ext_mode.src_size()),
-                show_ireg_sized(dst.to_reg().to_reg(), mb_rru, ext_mode.dst_size())
-            ),
-
-            Inst::MovRM { size, src, dst, .. } => format!(
-                "{} {}, {}",
-                ljustify2("mov".to_string(), suffix_bwlq(*size)),
-                show_ireg_sized(src.to_reg(), mb_rru, size.to_bytes()),
-                dst.show_rru(mb_rru)
-            ),
-
-            Inst::ShiftR {
-                size,
-                kind,
-                num_bits,
-                dst,
-                ..
-            } => match num_bits.clone().to_imm8_reg() {
-                Imm8Reg::Reg { reg } => format!(
-                    "{} {}, {}",
-                    ljustify2(kind.to_string(), suffix_bwlq(*size)),
-                    show_ireg_sized(reg, mb_rru, 1),
-                    show_ireg_sized(dst.to_reg().to_reg(), mb_rru, size.to_bytes())
-                ),
-
-                Imm8Reg::Imm8 { imm: num_bits } => format!(
-                    "{} ${}, {}",
-                    ljustify2(kind.to_string(), suffix_bwlq(*size)),
-                    num_bits,
-                    show_ireg_sized(dst.to_reg().to_reg(), mb_rru, size.to_bytes())
-                ),
-            },
-
-            Inst::XmmRmiReg {
-                opcode, src2, dst, ..
-            } => format!(
-                "{} {}, {}",
-                ljustify(opcode.to_string()),
-                src2.show_rru(mb_rru),
-                dst.to_reg().show_rru(mb_rru)
-            ),
-
-            Inst::CmpRmiR {
-                size,
-                src,
-                dst,
-                opcode,
-            } => {
-                let op = match opcode {
-                    CmpOpcode::Cmp => "cmp",
-                    CmpOpcode::Test => "test",
-                };
-                format!(
-                    "{} {}, {}",
-                    ljustify2(op.to_string(), suffix_bwlq(*size)),
-                    src.show_rru_sized(mb_rru, size.to_bytes()),
-                    show_ireg_sized(dst.to_reg(), mb_rru, size.to_bytes())
-                )
-            }
-
-            Inst::Setcc { cc, dst } => format!(
-                "{} {}",
-                ljustify2("set".to_string(), cc.to_string()),
-                show_ireg_sized(dst.to_reg().to_reg(), mb_rru, 1)
-            ),
-
-            Inst::Cmove {
-                size,
-                cc,
-                consequent: src,
-                alternative: _,
-                dst,
-            } => format!(
-                "{} {}, {}",
-                ljustify(format!("cmov{}{}", cc.to_string(), suffix_bwlq(*size))),
-                src.show_rru_sized(mb_rru, size.to_bytes()),
-                show_ireg_sized(dst.to_reg().to_reg(), mb_rru, size.to_bytes())
-            ),
-
-            Inst::XmmCmove {
-                size,
-                cc,
-                consequent: src,
-                dst,
-                ..
-            } => {
-                format!(
-                    "j{} $next; mov{} {}, {}; $next: ",
-                    cc.invert().to_string(),
-                    if *size == OperandSize::Size64 {
-                        "sd"
-                    } else {
-                        "ss"
-                    },
-                    src.show_rru_sized(mb_rru, size.to_bytes()),
-                    show_ireg_sized(dst.to_reg().to_reg(), mb_rru, size.to_bytes())
-                )
-            }
-
-            Inst::Push64 { src } => {
-                format!("{} {}", ljustify("pushq".to_string()), src.show_rru(mb_rru))
-            }
-
-            Inst::Pop64 { dst } => {
-                format!("{} {}", ljustify("popq".to_string()), dst.show_rru(mb_rru))
-            }
-
-            Inst::CallKnown { dest, .. } => format!("{} {:?}", ljustify("call".to_string()), dest),
-
-            Inst::CallUnknown { dest, .. } => format!(
-                "{} *{}",
-                ljustify("call".to_string()),
-                dest.show_rru(mb_rru)
-            ),
-
-            Inst::Ret => "ret".to_string(),
-
-            Inst::EpiloguePlaceholder => "epilogue placeholder".to_string(),
-
-            Inst::JmpKnown { dst } => {
-                format!("{} {}", ljustify("jmp".to_string()), dst.to_string())
-            }
-
-            Inst::JmpIf { cc, taken } => format!(
-                "{} {}",
-                ljustify2("j".to_string(), cc.to_string()),
-                taken.to_string(),
-            ),
-
-            Inst::JmpCond {
-                cc,
-                taken,
-                not_taken,
-            } => format!(
-                "{} {}; j {}",
-                ljustify2("j".to_string(), cc.to_string()),
-                taken.to_string(),
-                not_taken.to_string()
-            ),
-
-            Inst::JmpTableSeq { idx, .. } => {
-                format!("{} {}", ljustify("br_table".into()), idx.show_rru(mb_rru))
-            }
-
-            Inst::JmpUnknown { target } => format!(
-                "{} *{}",
-                ljustify("jmp".to_string()),
-                target.show_rru(mb_rru)
-            ),
-
-            Inst::TrapIf { cc, trap_code, .. } => {
-                format!("j{} ; ud2 {} ;", cc.invert().to_string(), trap_code)
-            }
-
-            Inst::LoadExtName {
-                dst, name, offset, ..
-            } => format!(
-                "{} {}+{}, {}",
-                ljustify("load_ext_name".into()),
-                name,
-                offset,
-                show_ireg_sized(dst.to_reg(), mb_rru, 8),
-            ),
-
-            Inst::LockCmpxchg {
-                ty,
-                replacement,
-                mem,
-                ..
-            } => {
-                let size = ty.bytes() as u8;
-                format!(
-                    "lock cmpxchg{} {}, {}",
-                    suffix_bwlq(OperandSize::from_bytes(size as u32)),
-                    show_ireg_sized(*replacement, mb_rru, size),
-                    mem.show_rru(mb_rru)
-                )
-            }
-
-            Inst::AtomicRmwSeq { ty, op, .. } => {
-                format!(
-                    "atomically {{ {}_bits_at_[%r9]) {:?}= %r10; %rax = old_value_at_[%r9]; %r11, %rflags = trash }}",
-                    ty.bits(), op)
-            }
-
-            Inst::Fence { kind } => match kind {
-                FenceKind::MFence => "mfence".to_string(),
-                FenceKind::LFence => "lfence".to_string(),
-                FenceKind::SFence => "sfence".to_string(),
-            },
-
-            Inst::VirtualSPOffsetAdj { offset } => format!("virtual_sp_offset_adjust {}", offset),
-
-            Inst::Hlt => "hlt".into(),
-
-            Inst::Ud2 { trap_code } => format!("ud2 {}", trap_code),
-
-            Inst::ElfTlsGetAddr { ref symbol } => {
-                format!("elf_tls_get_addr {:?}", symbol)
-            }
-
-            Inst::MachOTlsGetAddr { ref symbol } => {
-                format!("macho_tls_get_addr {:?}", symbol)
-            }
-
-            Inst::ValueLabelMarker { label, reg } => {
-                format!("value_label {:?}, {}", label, reg.show_rru(mb_rru))
-            }
-
-            Inst::Unwind { inst } => {
-                format!("unwind {:?}", inst)
-            }
-        }
-    }
-}
-
-// Temp hook for legacy printing machinery
-impl fmt::Debug for Inst {
-    fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result {
-        // Print the insn without a Universe :-(
-        write!(fmt, "{}", self.show_rru(None))
-    }
-}
-
-fn x64_get_regs(inst: &Inst, collector: &mut RegUsageCollector) {
-    // This is a bit subtle. If some register is in the modified set, then it may not be in either
-    // the use or def sets. However, enforcing that directly is somewhat difficult. Instead,
-    // regalloc.rs will "fix" this for us by removing the modified set from the use and def
-    // sets.
-    match inst {
-        Inst::AluRmiR {
-            src1, src2, dst, ..
-        } => {
-            debug_assert_eq!(*src1, dst.to_reg());
-            if inst.produces_const() {
-                // No need to account for src2, since src2 == dst.
-                collector.add_def(dst.to_writable_reg());
-            } else {
-                src2.get_regs_as_uses(collector);
-                collector.add_mod(dst.to_writable_reg());
-            }
-        }
-        Inst::Not { src, dst, .. } => {
-            debug_assert_eq!(*src, dst.to_reg());
-            collector.add_mod(dst.to_writable_reg());
-        }
-        Inst::Neg { src, dst, .. } => {
-            debug_assert_eq!(*src, dst.to_reg());
-            collector.add_mod(dst.to_writable_reg());
-        }
-        Inst::Div {
-            size,
-            divisor,
-            dividend,
-            dst_quotient,
-            dst_remainder,
-            ..
-        } => {
-            debug_assert_eq!(*dividend, regs::rax());
-            debug_assert_eq!(dst_quotient.to_reg(), regs::rax());
-            collector.add_mod(Writable::from_reg(regs::rax()));
-
-            debug_assert_eq!(dst_remainder.to_reg(), regs::rdx());
-            if *size == OperandSize::Size8 {
-                collector.add_def(Writable::from_reg(regs::rdx()));
-            } else {
-                collector.add_mod(Writable::from_reg(regs::rdx()));
-            }
-
-            divisor.get_regs_as_uses(collector);
-        }
-        Inst::MulHi {
-            src1,
-            src2,
-            dst_lo,
-            dst_hi,
-            ..
-        } => {
-            debug_assert_eq!(*src1, regs::rax());
-            debug_assert_eq!(dst_lo.to_reg(), regs::rax());
-            collector.add_mod(Writable::from_reg(regs::rax()));
-
-            debug_assert_eq!(dst_hi.to_reg(), regs::rdx());
-            collector.add_def(Writable::from_reg(regs::rdx()));
-
-            src2.get_regs_as_uses(collector);
-        }
-        Inst::CheckedDivOrRemSeq {
-            divisor,
-            dividend,
-            dst_quotient,
-            dst_remainder,
-            tmp,
-            ..
-        } => {
-            debug_assert_eq!(*dividend, regs::rax());
-            debug_assert_eq!(dst_quotient.to_reg(), regs::rax());
-            debug_assert_eq!(dst_remainder.to_reg(), regs::rdx());
-            // Mark both fixed registers as mods, to avoid an early clobber problem in codegen
-            // (i.e. the temporary is allocated one of the fixed registers). This requires writing
-            // the rdx register *before* the instruction, which is not too bad.
-            collector.add_mod(Writable::from_reg(regs::rax()));
-            collector.add_mod(Writable::from_reg(regs::rdx()));
-            collector.add_mod(divisor.to_writable_reg());
-            if let Some(tmp) = tmp {
-                collector.add_def(tmp.to_writable_reg());
-            }
-        }
-        Inst::SignExtendData { size, src, dst } => {
-            debug_assert_eq!(*src, regs::rax());
-            debug_assert_eq!(dst.to_reg(), regs::rdx());
-            match size {
-                OperandSize::Size8 => collector.add_mod(Writable::from_reg(regs::rax())),
-                _ => {
-                    collector.add_use(regs::rax());
-                    collector.add_def(Writable::from_reg(regs::rdx()));
-                }
-            }
-        }
-        Inst::UnaryRmR { src, dst, .. } => {
-            src.clone().to_reg_mem().get_regs_as_uses(collector);
-            collector.add_def(dst.to_writable_reg());
-        }
-        Inst::XmmUnaryRmR { src, dst, .. } | Inst::XmmUnaryRmREvex { src, dst, .. } => {
-            src.clone().to_reg_mem().get_regs_as_uses(collector);
-            collector.add_def(dst.to_writable_reg());
-        }
-        Inst::XmmRmR {
-            src1,
-            src2,
-            dst,
-            op,
-            ..
-        } => {
-            debug_assert_eq!(*src1, dst.to_reg());
-            if inst.produces_const() {
-                // No need to account for src, since src == dst.
-                collector.add_def(dst.to_writable_reg());
-            } else {
-                src2.clone().to_reg_mem().get_regs_as_uses(collector);
-                collector.add_mod(dst.to_writable_reg());
-                // Some instructions have an implicit use of XMM0.
-                if *op == SseOpcode::Blendvpd
-                    || *op == SseOpcode::Blendvps
-                    || *op == SseOpcode::Pblendvb
-                {
-                    collector.add_use(regs::xmm0());
-                }
-            }
-        }
-        Inst::XmmRmREvex {
-            op,
-            src1,
-            src2,
-            dst,
-            ..
-        } => {
-            src1.clone().to_reg_mem().get_regs_as_uses(collector);
-            collector.add_use(src2.to_reg());
-            match *op {
-                Avx512Opcode::Vpermi2b => collector.add_mod(dst.to_writable_reg()),
-                _ => collector.add_def(dst.to_writable_reg()),
-            }
-        }
-        Inst::XmmRmRImm {
-            op,
-            src1,
-            src2,
-            dst,
-            ..
-        } => {
-            debug_assert_eq!(*src1, dst.to_reg());
-            if inst.produces_const() {
-                // No need to account for src2, since src2 == dst.
-                debug_assert_eq!(src2.to_reg(), Some(dst.to_reg()));
-                collector.add_def(*dst);
-            } else if *op == SseOpcode::Pextrb
-                || *op == SseOpcode::Pextrw
-                || *op == SseOpcode::Pextrd
-                || *op == SseOpcode::Pshufd
-                || *op == SseOpcode::Roundss
-                || *op == SseOpcode::Roundsd
-                || *op == SseOpcode::Roundps
-                || *op == SseOpcode::Roundpd
-            {
-                src2.get_regs_as_uses(collector);
-                collector.add_def(*dst);
-            } else {
-                src2.get_regs_as_uses(collector);
-                collector.add_mod(*dst);
-            }
-        }
-        Inst::XmmUninitializedValue { dst } => collector.add_def(dst.to_writable_reg()),
-        Inst::XmmLoadConst { dst, .. } => collector.add_def(*dst),
-        Inst::XmmMinMaxSeq { lhs, rhs, dst, .. } => {
-            debug_assert_eq!(*rhs, dst.to_reg());
-            collector.add_use(lhs.to_reg());
-            collector.add_mod(dst.to_writable_reg());
-        }
-        Inst::XmmRmiReg {
-            src1, src2, dst, ..
-        } => {
-            debug_assert_eq!(*src1, dst.to_reg());
-            src2.clone().to_reg_mem_imm().get_regs_as_uses(collector);
-            collector.add_mod(dst.to_writable_reg());
-        }
-        Inst::XmmMovRM { src, dst, .. } => {
-            collector.add_use(*src);
-            dst.get_regs_as_uses(collector);
-        }
-        Inst::XmmCmpRmR { src, dst, .. } => {
-            src.get_regs_as_uses(collector);
-            collector.add_use(dst.to_reg());
-        }
-        Inst::Imm { dst, .. } => {
-            collector.add_def(dst.to_writable_reg());
-        }
-        Inst::MovRR { src, dst, .. } => {
-            collector.add_use(src.to_reg());
-            collector.add_def(dst.to_writable_reg());
-        }
-        Inst::XmmToGpr { src, dst, .. } => {
-            collector.add_use(src.to_reg());
-            collector.add_def(dst.to_writable_reg());
-        }
-        Inst::GprToXmm { src, dst, .. } => {
-            src.get_regs_as_uses(collector);
-            collector.add_def(dst.to_writable_reg());
-        }
-        Inst::CvtUint64ToFloatSeq {
-            src,
-            dst,
-            tmp_gpr1,
-            tmp_gpr2,
-            ..
-        } => {
-            collector.add_mod(src.to_writable_reg());
-            collector.add_def(dst.to_writable_reg());
-            collector.add_def(tmp_gpr1.to_writable_reg());
-            collector.add_def(tmp_gpr2.to_writable_reg());
-        }
-        Inst::CvtFloatToSintSeq {
-            src,
-            dst,
-            tmp_xmm,
-            tmp_gpr,
-            ..
-        }
-        | Inst::CvtFloatToUintSeq {
-            src,
-            dst,
-            tmp_gpr,
-            tmp_xmm,
-            ..
-        } => {
-            collector.add_mod(src.to_writable_reg());
-            collector.add_def(dst.to_writable_reg());
-            collector.add_def(tmp_gpr.to_writable_reg());
-            collector.add_def(tmp_xmm.to_writable_reg());
-        }
-        Inst::MovzxRmR { src, dst, .. } => {
-            src.get_regs_as_uses(collector);
-            collector.add_def(dst.to_writable_reg());
-        }
-        Inst::Mov64MR { src, dst, .. } => {
-            src.get_regs_as_uses(collector);
-            collector.add_def(dst.to_writable_reg())
-        }
-        Inst::LoadEffectiveAddress { addr: src, dst } => {
-            src.get_regs_as_uses(collector);
-            collector.add_def(dst.to_writable_reg())
-        }
-        Inst::MovsxRmR { src, dst, .. } => {
-            src.get_regs_as_uses(collector);
-            collector.add_def(dst.to_writable_reg());
-        }
-        Inst::MovRM { src, dst, .. } => {
-            collector.add_use(src.to_reg());
-            dst.get_regs_as_uses(collector);
-        }
-        Inst::ShiftR { num_bits, dst, .. } => {
-            if let Imm8Reg::Reg { reg } = num_bits.clone().to_imm8_reg() {
-                debug_assert_eq!(reg, regs::rcx());
-                collector.add_use(regs::rcx());
-            }
-            collector.add_mod(dst.to_writable_reg());
-        }
-        Inst::CmpRmiR { src, dst, .. } => {
-            src.get_regs_as_uses(collector);
-            collector.add_use(dst.to_reg()); // yes, really `add_use`
-        }
-        Inst::Setcc { dst, .. } => {
-            collector.add_def(dst.to_writable_reg());
-        }
-        Inst::Cmove {
-            consequent: src,
-            dst,
-            ..
-        } => {
-            src.get_regs_as_uses(collector);
-            collector.add_mod(dst.to_writable_reg());
-        }
-        Inst::XmmCmove {
-            consequent: src,
-            dst,
-            ..
-        } => {
-            src.get_regs_as_uses(collector);
-            collector.add_mod(dst.to_writable_reg());
-        }
-        Inst::Push64 { src } => {
-            src.get_regs_as_uses(collector);
-            collector.add_mod(Writable::from_reg(regs::rsp()));
-        }
-        Inst::Pop64 { dst } => {
-            collector.add_def(dst.to_writable_reg());
-        }
-
-        Inst::CallKnown {
-            ref uses, ref defs, ..
-        } => {
-            collector.add_uses(uses);
-            collector.add_defs(defs);
-        }
-
-        Inst::CallUnknown {
-            ref uses,
-            ref defs,
-            dest,
-            ..
-        } => {
-            collector.add_uses(uses);
-            collector.add_defs(defs);
-            dest.get_regs_as_uses(collector);
-        }
-
-        Inst::JmpTableSeq {
-            ref idx,
-            ref tmp1,
-            ref tmp2,
-            ..
-        } => {
-            collector.add_use(*idx);
-            collector.add_def(*tmp1);
-            collector.add_def(*tmp2);
-        }
-
-        Inst::JmpUnknown { target } => {
-            target.get_regs_as_uses(collector);
-        }
-
-        Inst::LoadExtName { dst, .. } => {
-            collector.add_def(*dst);
-        }
-
-        Inst::LockCmpxchg {
-            replacement,
-            expected,
-            mem,
-            dst_old,
-            ..
-        } => {
-            mem.get_regs_as_uses(collector);
-            collector.add_use(*replacement);
-
-            debug_assert_eq!(*expected, regs::rax());
-            debug_assert_eq!(dst_old.to_reg(), regs::rax());
-            collector.add_mod(Writable::from_reg(regs::rax()));
-        }
-
-        Inst::AtomicRmwSeq { .. } => {
-            collector.add_use(regs::r9());
-            collector.add_use(regs::r10());
-            collector.add_def(Writable::from_reg(regs::r11()));
-            collector.add_def(Writable::from_reg(regs::rax()));
-        }
-
-        Inst::Ret
-        | Inst::EpiloguePlaceholder
-        | Inst::JmpKnown { .. }
-        | Inst::JmpIf { .. }
-        | Inst::JmpCond { .. }
-        | Inst::Nop { .. }
-        | Inst::TrapIf { .. }
-        | Inst::VirtualSPOffsetAdj { .. }
-        | Inst::Hlt
-        | Inst::Ud2 { .. }
-        | Inst::Fence { .. } => {
-            // No registers are used.
-        }
-
-        Inst::ElfTlsGetAddr { .. } | Inst::MachOTlsGetAddr { .. } => {
-            // All caller-saves are clobbered.
-            //
-            // We use the SysV calling convention here because the
-            // pseudoinstruction (and relocation that it emits) is specific to
-            // ELF systems; other x86-64 targets with other conventions (i.e.,
-            // Windows) use different TLS strategies.
-            for reg in X64ABIMachineSpec::get_regs_clobbered_by_call(CallConv::SystemV) {
-                collector.add_def(reg);
-            }
-        }
-
-        Inst::ValueLabelMarker { reg, .. } => {
-            collector.add_use(*reg);
-        }
-
-        Inst::Unwind { .. } => {}
-    }
-}
-
-//=============================================================================
-// Instructions and subcomponents: map_regs
-
-impl Amode {
-    fn map_uses<RM: RegMapper>(&mut self, map: &RM) {
-        match self {
-            Amode::ImmReg { ref mut base, .. } => map.map_use(base),
-            Amode::ImmRegRegShift {
-                ref mut base,
-                ref mut index,
-                ..
-            } => {
-                base.map_use(map);
-                index.map_use(map);
-            }
-            Amode::RipRelative { .. } => {
-                // RIP isn't involved in regalloc.
-            }
-        }
-    }
-
-    /// Offset the amode by a fixed offset.
-    pub(crate) fn offset(&self, offset: u32) -> Self {
-        let mut ret = self.clone();
-        match &mut ret {
-            &mut Amode::ImmReg { ref mut simm32, .. } => *simm32 += offset,
-            &mut Amode::ImmRegRegShift { ref mut simm32, .. } => *simm32 += offset,
-            _ => panic!("Cannot offset amode: {:?}", self),
-        }
-        ret
-    }
-}
-
-impl RegMemImm {
-    fn map_uses<RM: RegMapper>(&mut self, map: &RM) {
-        match self {
-            RegMemImm::Reg { ref mut reg } => map.map_use(reg),
-            RegMemImm::Mem { ref mut addr } => addr.map_uses(map),
-            RegMemImm::Imm { .. } => {}
-        }
-    }
-
-    fn map_as_def<RM: RegMapper>(&mut self, mapper: &RM) {
-        match self {
-            Self::Reg { reg } => {
-                let mut writable_src = Writable::from_reg(*reg);
-                mapper.map_def(&mut writable_src);
-                *self = Self::reg(writable_src.to_reg());
-            }
-            _ => panic!("unexpected RegMemImm kind in map_src_reg_as_def"),
-        }
-    }
-}
-
-impl RegMem {
-    fn map_uses<RM: RegMapper>(&mut self, map: &RM) {
-        match self {
-            RegMem::Reg { ref mut reg } => map.map_use(reg),
-            RegMem::Mem { ref mut addr, .. } => addr.map_uses(map),
-        }
-    }
-
-    fn map_as_def<RM: RegMapper>(&mut self, mapper: &RM) {
-        match self {
-            Self::Reg { reg } => {
-                let mut writable_src = Writable::from_reg(*reg);
-                mapper.map_def(&mut writable_src);
-                *self = Self::reg(writable_src.to_reg());
-            }
-            _ => panic!("unexpected RegMem kind in map_src_reg_as_def"),
-        }
-    }
-}
-
-pub(crate) fn x64_map_regs<RM: RegMapper>(inst: &mut Inst, mapper: &RM) {
-    // Note this must be carefully synchronized with x64_get_regs.
-    let produces_const = inst.produces_const();
-
-    match inst {
-        // ** Nop
-        Inst::AluRmiR {
-            ref mut src1,
-            ref mut src2,
-            ref mut dst,
-            ..
-        } => {
-            debug_assert_eq!(*src1, dst.to_reg());
-            if produces_const {
-                src2.map_as_def(mapper);
-                dst.map_def(mapper);
-                *src1 = dst.to_reg();
-            } else {
-                src2.map_uses(mapper);
-                dst.map_mod(mapper);
-                *src1 = dst.to_reg();
-            }
-        }
-        Inst::Not { src, dst, .. } | Inst::Neg { src, dst, .. } => {
-            debug_assert_eq!(*src, dst.to_reg());
-            dst.map_mod(mapper);
-            *src = dst.to_reg();
-        }
-        Inst::Div { divisor, .. } => divisor.map_uses(mapper),
-        Inst::MulHi { src2, .. } => src2.map_uses(mapper),
-        Inst::CheckedDivOrRemSeq { divisor, tmp, .. } => {
-            divisor.map_mod(mapper);
-            if let Some(tmp) = tmp {
-                tmp.map_def(mapper)
-            }
-        }
-        Inst::SignExtendData { .. } => {}
-        Inst::XmmUnaryRmR {
-            ref mut src,
-            ref mut dst,
-            ..
-        }
-        | Inst::XmmUnaryRmREvex {
-            ref mut src,
-            ref mut dst,
-            ..
-        } => {
-            src.map_uses(mapper);
-            dst.map_def(mapper);
-        }
-        Inst::UnaryRmR {
-            ref mut src,
-            ref mut dst,
-            ..
-        } => {
-            src.map_uses(mapper);
-            dst.map_def(mapper);
-        }
-        Inst::XmmRmRImm {
-            ref op,
-            ref mut src1,
-            ref mut src2,
-            ref mut dst,
-            ..
-        } => {
-            debug_assert_eq!(*src1, dst.to_reg());
-            if produces_const {
-                src2.map_as_def(mapper);
-                mapper.map_def(dst);
-                *src1 = dst.to_reg();
-            } else if *op == SseOpcode::Pextrb
-                || *op == SseOpcode::Pextrw
-                || *op == SseOpcode::Pextrd
-                || *op == SseOpcode::Pshufd
-                || *op == SseOpcode::Roundss
-                || *op == SseOpcode::Roundsd
-                || *op == SseOpcode::Roundps
-                || *op == SseOpcode::Roundpd
-            {
-                src2.map_uses(mapper);
-                mapper.map_def(dst);
-                *src1 = dst.to_reg();
-            } else {
-                src2.map_uses(mapper);
-                mapper.map_mod(dst);
-                *src1 = dst.to_reg();
-            }
-        }
-        Inst::XmmRmR {
-            ref mut src1,
-            ref mut src2,
-            ref mut dst,
-            ..
-        } => {
-            debug_assert_eq!(*src1, dst.to_reg());
-            if produces_const {
-                src2.map_as_def(mapper);
-                dst.map_def(mapper);
-                *src1 = dst.to_reg();
-            } else {
-                src2.map_uses(mapper);
-                dst.map_mod(mapper);
-                *src1 = dst.to_reg();
-            }
-        }
-        Inst::XmmRmREvex {
-            op,
-            ref mut src1,
-            ref mut src2,
-            ref mut dst,
-            ..
-        } => {
-            src1.map_uses(mapper);
-            src2.map_use(mapper);
-            match *op {
-                Avx512Opcode::Vpermi2b => dst.map_mod(mapper),
-                _ => dst.map_def(mapper),
-            }
-        }
-        Inst::XmmRmiReg {
-            ref mut src1,
-            ref mut src2,
-            ref mut dst,
-            ..
-        } => {
-            debug_assert_eq!(*src1, dst.to_reg());
-            src2.map_uses(mapper);
-            dst.map_mod(mapper);
-            *src1 = dst.to_reg();
-        }
-        Inst::XmmUninitializedValue { ref mut dst, .. } => {
-            dst.map_def(mapper);
-        }
-        Inst::XmmLoadConst { ref mut dst, .. } => {
-            mapper.map_def(dst);
-        }
-        Inst::XmmMinMaxSeq {
-            ref mut lhs,
-            ref mut rhs,
-            ref mut dst,
-            ..
-        } => {
-            debug_assert_eq!(*rhs, dst.to_reg());
-            lhs.map_use(mapper);
-            dst.map_mod(mapper);
-            *rhs = dst.to_reg();
-        }
-        Inst::XmmMovRM {
-            ref mut src,
-            ref mut dst,
-            ..
-        } => {
-            mapper.map_use(src);
-            dst.map_uses(mapper);
-        }
-        Inst::XmmCmpRmR {
-            ref mut src,
-            ref mut dst,
-            ..
-        } => {
-            src.map_uses(mapper);
-            dst.map_use(mapper);
-        }
-        Inst::Imm { ref mut dst, .. } => dst.map_def(mapper),
-        Inst::MovRR {
-            ref mut src,
-            ref mut dst,
-            ..
-        } => {
-            src.map_use(mapper);
-            dst.map_def(mapper);
-        }
-        Inst::XmmToGpr {
-            ref mut src,
-            ref mut dst,
-            ..
-        } => {
-            src.map_use(mapper);
-            dst.map_def(mapper);
-        }
-        Inst::GprToXmm {
-            ref mut src,
-            ref mut dst,
-            ..
-        } => {
-            src.map_uses(mapper);
-            dst.map_def(mapper);
-        }
-        Inst::CvtUint64ToFloatSeq {
-            ref mut src,
-            ref mut dst,
-            ref mut tmp_gpr1,
-            ref mut tmp_gpr2,
-            ..
-        } => {
-            src.map_mod(mapper);
-            dst.map_def(mapper);
-            tmp_gpr1.map_def(mapper);
-            tmp_gpr2.map_def(mapper);
-        }
-        Inst::CvtFloatToSintSeq {
-            ref mut src,
-            ref mut dst,
-            ref mut tmp_xmm,
-            ref mut tmp_gpr,
-            ..
-        }
-        | Inst::CvtFloatToUintSeq {
-            ref mut src,
-            ref mut dst,
-            ref mut tmp_gpr,
-            ref mut tmp_xmm,
-            ..
-        } => {
-            src.map_mod(mapper);
-            dst.map_def(mapper);
-            tmp_gpr.map_def(mapper);
-            tmp_xmm.map_def(mapper);
-        }
-        Inst::MovzxRmR {
-            ref mut src,
-            ref mut dst,
-            ..
-        } => {
-            src.map_uses(mapper);
-            dst.map_def(mapper);
-        }
-        Inst::Mov64MR { src, dst, .. } => {
-            src.map_uses(mapper);
-            dst.map_def(mapper);
-        }
-        Inst::LoadEffectiveAddress { addr: src, dst } => {
-            src.map_uses(mapper);
-            dst.map_def(mapper);
-        }
-        Inst::MovsxRmR {
-            ref mut src,
-            ref mut dst,
-            ..
-        } => {
-            src.map_uses(mapper);
-            dst.map_def(mapper);
-        }
-        Inst::MovRM {
-            ref mut src,
-            ref mut dst,
-            ..
-        } => {
-            src.map_use(mapper);
-            dst.map_uses(mapper);
-        }
-        Inst::ShiftR {
-            ref mut src,
-            ref mut dst,
-            ..
-        } => {
-            debug_assert_eq!(*src, dst.to_reg());
-            dst.map_mod(mapper);
-            *src = dst.to_reg();
-        }
-        Inst::CmpRmiR {
-            ref mut src,
-            ref mut dst,
-            ..
-        } => {
-            src.map_uses(mapper);
-            dst.map_use(mapper);
-        }
-        Inst::Setcc { ref mut dst, .. } => dst.map_def(mapper),
-        Inst::Cmove {
-            consequent: ref mut src,
-            ref mut dst,
-            ref mut alternative,
-            ..
-        } => {
-            src.map_uses(mapper);
-            dst.map_mod(mapper);
-            *alternative = dst.to_reg();
-        }
-        Inst::XmmCmove {
-            consequent: ref mut src,
-            ref mut dst,
-            ref mut alternative,
-            ..
-        } => {
-            src.map_uses(mapper);
-            dst.map_mod(mapper);
-            *alternative = dst.to_reg();
-        }
-        Inst::Push64 { ref mut src } => src.map_uses(mapper),
-        Inst::Pop64 { ref mut dst } => {
-            dst.map_def(mapper);
-        }
-
-        Inst::CallKnown {
-            ref mut uses,
-            ref mut defs,
-            ..
-        } => {
-            for r in uses.iter_mut() {
-                mapper.map_use(r);
-            }
-            for r in defs.iter_mut() {
-                mapper.map_def(r);
-            }
-        }
-
-        Inst::CallUnknown {
-            ref mut uses,
-            ref mut defs,
-            ref mut dest,
-            ..
-        } => {
-            for r in uses.iter_mut() {
-                mapper.map_use(r);
-            }
-            for r in defs.iter_mut() {
-                mapper.map_def(r);
-            }
-            dest.map_uses(mapper);
-        }
-
-        Inst::JmpTableSeq {
-            ref mut idx,
-            ref mut tmp1,
-            ref mut tmp2,
-            ..
-        } => {
-            mapper.map_use(idx);
-            mapper.map_def(tmp1);
-            mapper.map_def(tmp2);
-        }
-
-        Inst::JmpUnknown { ref mut target } => target.map_uses(mapper),
-
-        Inst::LoadExtName { ref mut dst, .. } => mapper.map_def(dst),
-
-        Inst::LockCmpxchg {
-            ref mut replacement,
-            ref mut mem,
-            ..
-        } => {
-            mapper.map_use(replacement);
-            mem.map_uses(mapper);
-        }
-
-        Inst::ValueLabelMarker { ref mut reg, .. } => mapper.map_use(reg),
-
-        Inst::Ret
-        | Inst::EpiloguePlaceholder
-        | Inst::JmpKnown { .. }
-        | Inst::JmpCond { .. }
-        | Inst::JmpIf { .. }
-        | Inst::Nop { .. }
-        | Inst::TrapIf { .. }
-        | Inst::VirtualSPOffsetAdj { .. }
-        | Inst::Ud2 { .. }
-        | Inst::Hlt
-        | Inst::AtomicRmwSeq { .. }
-        | Inst::ElfTlsGetAddr { .. }
-        | Inst::MachOTlsGetAddr { .. }
-        | Inst::Fence { .. }
-        | Inst::Unwind { .. } => {
-            // Instruction doesn't explicitly mention any regs, so it can't have any virtual
-            // regs that we'd need to remap.  Hence no action required.
-        }
-    }
-}
-
-//=============================================================================
-// Instructions: misc functions and external interface
-
-impl MachInst for Inst {
-    fn get_regs(&self, collector: &mut RegUsageCollector) {
-        x64_get_regs(&self, collector)
-    }
-
-    fn map_regs<RUM>(&mut self, mapper: &RUM)
-    where
-        RUM: regalloc::RegUsageMapper,
-    {
-        x64_map_regs(self, mapper);
-    }
-
-    fn is_move(&self) -> Option<(Writable<Reg>, Reg)> {
-        match self {
-            // Note (carefully!) that a 32-bit mov *isn't* a no-op since it zeroes
-            // out the upper 32 bits of the destination.  For example, we could
-            // conceivably use `movl %reg, %reg` to zero out the top 32 bits of
-            // %reg.
-            Self::MovRR { size, src, dst, .. } if *size == OperandSize::Size64 => {
-                Some((dst.to_writable_reg(), src.to_reg()))
-            }
-            // Note as well that MOVS[S|D] when used in the `XmmUnaryRmR` context are pure moves of
-            // scalar floating-point values (and annotate `dst` as `def`s to the register allocator)
-            // whereas the same operation in a packed context, e.g. `XMM_RM_R`, is used to merge a
-            // value into the lowest lane of a vector (not a move).
-            Self::XmmUnaryRmR { op, src, dst, .. }
-                if *op == SseOpcode::Movss
-                    || *op == SseOpcode::Movsd
-                    || *op == SseOpcode::Movaps
-                    || *op == SseOpcode::Movapd
-                    || *op == SseOpcode::Movups
-                    || *op == SseOpcode::Movupd
-                    || *op == SseOpcode::Movdqa
-                    || *op == SseOpcode::Movdqu =>
-            {
-                if let RegMem::Reg { reg } = src.clone().to_reg_mem() {
-                    Some((dst.to_writable_reg(), reg))
-                } else {
-                    None
-                }
-            }
-            _ => None,
-        }
-    }
-
-    fn is_epilogue_placeholder(&self) -> bool {
-        if let Self::EpiloguePlaceholder = self {
-            true
-        } else {
-            false
-        }
-    }
-
-    fn is_term<'a>(&'a self) -> MachTerminator<'a> {
-        match self {
-            // Interesting cases.
-            &Self::Ret | &Self::EpiloguePlaceholder => MachTerminator::Ret,
-            &Self::JmpKnown { dst } => MachTerminator::Uncond(dst),
-            &Self::JmpCond {
-                taken, not_taken, ..
-            } => MachTerminator::Cond(taken, not_taken),
-            &Self::JmpTableSeq {
-                ref targets_for_term,
-                ..
-            } => MachTerminator::Indirect(&targets_for_term[..]),
-            // All other cases are boring.
-            _ => MachTerminator::None,
-        }
-    }
-
-    fn stack_op_info(&self) -> Option<MachInstStackOpInfo> {
-        match self {
-            Self::VirtualSPOffsetAdj { offset } => Some(MachInstStackOpInfo::NomSPAdj(*offset)),
-            Self::MovRM {
-                size: OperandSize::Size8,
-                src,
-                dst: SyntheticAmode::NominalSPOffset { simm32 },
-            } => Some(MachInstStackOpInfo::StoreNomSPOff(
-                src.to_reg(),
-                *simm32 as i64,
-            )),
-            Self::Mov64MR {
-                src: SyntheticAmode::NominalSPOffset { simm32 },
-                dst,
-            } => Some(MachInstStackOpInfo::LoadNomSPOff(
-                dst.to_reg().to_reg(),
-                *simm32 as i64,
-            )),
-            _ => None,
-        }
-    }
-
-    fn gen_move(dst_reg: Writable<Reg>, src_reg: Reg, ty: Type) -> Inst {
-        log::trace!(
-            "Inst::gen_move {:?} -> {:?} (type: {:?})",
-            src_reg,
-            dst_reg.to_reg(),
-            ty
-        );
-        let rc_dst = dst_reg.to_reg().get_class();
-        let rc_src = src_reg.get_class();
-        // If this isn't true, we have gone way off the rails.
-        debug_assert!(rc_dst == rc_src);
-        match rc_dst {
-            RegClass::I64 => Inst::mov_r_r(OperandSize::Size64, src_reg, dst_reg),
-            RegClass::V128 => {
-                // The Intel optimization manual, in "3.5.1.13 Zero-Latency MOV Instructions",
-                // doesn't include MOVSS/MOVSD as instructions with zero-latency. Use movaps for
-                // those, which may write more lanes that we need, but are specified to have
-                // zero-latency.
-                let opcode = match ty {
-                    types::F32 | types::F64 | types::F32X4 => SseOpcode::Movaps,
-                    types::F64X2 => SseOpcode::Movapd,
-                    _ if ty.is_vector() && ty.bits() == 128 => SseOpcode::Movdqa,
-                    _ => unimplemented!("unable to move type: {}", ty),
-                };
-                Inst::xmm_unary_rm_r(opcode, RegMem::reg(src_reg), dst_reg)
-            }
-            _ => panic!("gen_move(x64): unhandled regclass {:?}", rc_dst),
-        }
-    }
-
-    fn gen_nop(preferred_size: usize) -> Inst {
-        Inst::nop(std::cmp::min(preferred_size, 15) as u8)
-    }
-
-    fn maybe_direct_reload(&self, _reg: VirtualReg, _slot: SpillSlot) -> Option<Inst> {
-        None
-    }
-
-    fn rc_for_type(ty: Type) -> CodegenResult<(&'static [RegClass], &'static [Type])> {
-        match ty {
-            types::I8 => Ok((&[RegClass::I64], &[types::I8])),
-            types::I16 => Ok((&[RegClass::I64], &[types::I16])),
-            types::I32 => Ok((&[RegClass::I64], &[types::I32])),
-            types::I64 => Ok((&[RegClass::I64], &[types::I64])),
-            types::B1 => Ok((&[RegClass::I64], &[types::B1])),
-            types::B8 => Ok((&[RegClass::I64], &[types::B8])),
-            types::B16 => Ok((&[RegClass::I64], &[types::B16])),
-            types::B32 => Ok((&[RegClass::I64], &[types::B32])),
-            types::B64 => Ok((&[RegClass::I64], &[types::B64])),
-            types::R32 => panic!("32-bit reftype pointer should never be seen on x86-64"),
-            types::R64 => Ok((&[RegClass::I64], &[types::R64])),
-            types::F32 => Ok((&[RegClass::V128], &[types::F32])),
-            types::F64 => Ok((&[RegClass::V128], &[types::F64])),
-            types::I128 => Ok((&[RegClass::I64, RegClass::I64], &[types::I64, types::I64])),
-            types::B128 => Ok((&[RegClass::I64, RegClass::I64], &[types::B64, types::B64])),
-            _ if ty.is_vector() => {
-                assert!(ty.bits() <= 128);
-                Ok((&[RegClass::V128], &[types::I8X16]))
-            }
-            types::IFLAGS | types::FFLAGS => Ok((&[RegClass::I64], &[types::I64])),
-            _ => Err(CodegenError::Unsupported(format!(
-                "Unexpected SSA-value type: {}",
-                ty
-            ))),
-        }
-    }
-
-    fn gen_jump(label: MachLabel) -> Inst {
-        Inst::jmp_known(label)
-    }
-
-    fn gen_constant<F: FnMut(Type) -> Writable<Reg>>(
-        to_regs: ValueRegs<Writable<Reg>>,
-        value: u128,
-        ty: Type,
-        mut alloc_tmp: F,
-    ) -> SmallVec<[Self; 4]> {
-        let mut ret = SmallVec::new();
-        if ty == types::I128 {
-            let lo = value as u64;
-            let hi = (value >> 64) as u64;
-            let lo_reg = to_regs.regs()[0];
-            let hi_reg = to_regs.regs()[1];
-            if lo == 0 {
-                ret.push(Inst::alu_rmi_r(
-                    OperandSize::Size64,
-                    AluRmiROpcode::Xor,
-                    RegMemImm::reg(lo_reg.to_reg()),
-                    lo_reg,
-                ));
-            } else {
-                ret.push(Inst::imm(OperandSize::Size64, lo, lo_reg));
-            }
-            if hi == 0 {
-                ret.push(Inst::alu_rmi_r(
-                    OperandSize::Size64,
-                    AluRmiROpcode::Xor,
-                    RegMemImm::reg(hi_reg.to_reg()),
-                    hi_reg,
-                ));
-            } else {
-                ret.push(Inst::imm(OperandSize::Size64, hi, hi_reg));
-            }
-        } else {
-            let to_reg = to_regs
-                .only_reg()
-                .expect("multi-reg values not supported on x64");
-            if ty == types::F32 {
-                if value == 0 {
-                    ret.push(Inst::xmm_rm_r(
-                        SseOpcode::Xorps,
-                        RegMem::reg(to_reg.to_reg()),
-                        to_reg,
-                    ));
-                } else {
-                    let tmp = alloc_tmp(types::I32);
-                    ret.push(Inst::imm(OperandSize::Size32, value as u64, tmp));
-
-                    ret.push(Inst::gpr_to_xmm(
-                        SseOpcode::Movd,
-                        RegMem::reg(tmp.to_reg()),
-                        OperandSize::Size32,
-                        to_reg,
-                    ));
-                }
-            } else if ty == types::F64 {
-                if value == 0 {
-                    ret.push(Inst::xmm_rm_r(
-                        SseOpcode::Xorpd,
-                        RegMem::reg(to_reg.to_reg()),
-                        to_reg,
-                    ));
-                } else {
-                    let tmp = alloc_tmp(types::I64);
-                    ret.push(Inst::imm(OperandSize::Size64, value as u64, tmp));
-
-                    ret.push(Inst::gpr_to_xmm(
-                        SseOpcode::Movq,
-                        RegMem::reg(tmp.to_reg()),
-                        OperandSize::Size64,
-                        to_reg,
-                    ));
-                }
-            } else {
-                // Must be an integer type.
-                debug_assert!(
-                    ty == types::B1
-                        || ty == types::I8
-                        || ty == types::B8
-                        || ty == types::I16
-                        || ty == types::B16
-                        || ty == types::I32
-                        || ty == types::B32
-                        || ty == types::I64
-                        || ty == types::B64
-                        || ty == types::R32
-                        || ty == types::R64
-                );
-                // Immediates must be 32 or 64 bits.
-                // Smaller types are widened.
-                let size = match OperandSize::from_ty(ty) {
-                    OperandSize::Size64 => OperandSize::Size64,
-                    _ => OperandSize::Size32,
-                };
-                if value == 0 {
-                    ret.push(Inst::alu_rmi_r(
-                        size,
-                        AluRmiROpcode::Xor,
-                        RegMemImm::reg(to_reg.to_reg()),
-                        to_reg,
-                    ));
-                } else {
-                    let value = value as u64;
-                    ret.push(Inst::imm(size, value.into(), to_reg));
-                }
-            }
-        }
-        ret
-    }
-
-    fn worst_case_size() -> CodeOffset {
-        15
-    }
-
-    fn ref_type_regclass(_: &settings::Flags) -> RegClass {
-        RegClass::I64
-    }
-
-    fn gen_value_label_marker(label: ValueLabel, reg: Reg) -> Self {
-        Inst::ValueLabelMarker { label, reg }
-    }
-
-    fn defines_value_label(&self) -> Option<(ValueLabel, Reg)> {
-        match self {
-            Inst::ValueLabelMarker { label, reg } => Some((*label, *reg)),
-            _ => None,
-        }
-    }
-
-    type LabelUse = LabelUse;
-}
-
-/// State carried between emissions of a sequence of instructions.
-#[derive(Default, Clone, Debug)]
-pub struct EmitState {
-    /// Addend to convert nominal-SP offsets to real-SP offsets at the current
-    /// program point.
-    pub(crate) virtual_sp_offset: i64,
-    /// Offset of FP from nominal-SP.
-    pub(crate) nominal_sp_to_fp: i64,
-    /// Safepoint stack map for upcoming instruction, as provided to `pre_safepoint()`.
-    stack_map: Option<StackMap>,
-    /// Current source location.
-    cur_srcloc: SourceLoc,
-}
-
-/// Constant state used during emissions of a sequence of instructions.
-pub struct EmitInfo {
-    pub(super) flags: settings::Flags,
-    isa_flags: x64_settings::Flags,
-}
-
-impl EmitInfo {
-    pub(crate) fn new(flags: settings::Flags, isa_flags: x64_settings::Flags) -> Self {
-        Self { flags, isa_flags }
-    }
-}
-
-impl MachInstEmit for Inst {
-    type State = EmitState;
-    type Info = EmitInfo;
-
-    fn emit(&self, sink: &mut MachBuffer<Inst>, info: &Self::Info, state: &mut Self::State) {
-        emit::emit(self, sink, info, state);
-    }
-
-    fn pretty_print(&self, mb_rru: Option<&RealRegUniverse>, _: &mut Self::State) -> String {
-        self.show_rru(mb_rru)
-    }
-}
-
-impl MachInstEmitState<Inst> for EmitState {
-    fn new(abi: &dyn ABICallee<I = Inst>) -> Self {
-        EmitState {
-            virtual_sp_offset: 0,
-            nominal_sp_to_fp: abi.frame_size() as i64,
-            stack_map: None,
-            cur_srcloc: SourceLoc::default(),
-        }
-    }
-
-    fn pre_safepoint(&mut self, stack_map: StackMap) {
-        self.stack_map = Some(stack_map);
-    }
-
-    fn pre_sourceloc(&mut self, srcloc: SourceLoc) {
-        self.cur_srcloc = srcloc;
-    }
-}
-
-impl EmitState {
-    fn take_stack_map(&mut self) -> Option<StackMap> {
-        self.stack_map.take()
-    }
-
-    fn clear_post_insn(&mut self) {
-        self.stack_map = None;
-    }
-
-    pub(crate) fn cur_srcloc(&self) -> SourceLoc {
-        self.cur_srcloc
-    }
-}
-
-/// A label-use (internal relocation) in generated code.
-#[derive(Clone, Copy, Debug, PartialEq, Eq)]
-pub enum LabelUse {
-    /// A 32-bit offset from location of relocation itself, added to the existing value at that
-    /// location. Used for control flow instructions which consider an offset from the start of the
-    /// next instruction (so the size of the payload -- 4 bytes -- is subtracted from the payload).
-    JmpRel32,
-
-    /// A 32-bit offset from location of relocation itself, added to the existing value at that
-    /// location.
-    PCRel32,
-}
-
-impl MachInstLabelUse for LabelUse {
-    const ALIGN: CodeOffset = 1;
-
-    fn max_pos_range(self) -> CodeOffset {
-        match self {
-            LabelUse::JmpRel32 | LabelUse::PCRel32 => 0x7fff_ffff,
-        }
-    }
-
-    fn max_neg_range(self) -> CodeOffset {
-        match self {
-            LabelUse::JmpRel32 | LabelUse::PCRel32 => 0x8000_0000,
-        }
-    }
-
-    fn patch_size(self) -> CodeOffset {
-        match self {
-            LabelUse::JmpRel32 | LabelUse::PCRel32 => 4,
-        }
-    }
-
-    fn patch(self, buffer: &mut [u8], use_offset: CodeOffset, label_offset: CodeOffset) {
-        let pc_rel = (label_offset as i64) - (use_offset as i64);
-        debug_assert!(pc_rel <= self.max_pos_range() as i64);
-        debug_assert!(pc_rel >= -(self.max_neg_range() as i64));
-        let pc_rel = pc_rel as u32;
-        match self {
-            LabelUse::JmpRel32 => {
-                let addend = u32::from_le_bytes([buffer[0], buffer[1], buffer[2], buffer[3]]);
-                let value = pc_rel.wrapping_add(addend).wrapping_sub(4);
-                buffer.copy_from_slice(&value.to_le_bytes()[..]);
-            }
-            LabelUse::PCRel32 => {
-                let addend = u32::from_le_bytes([buffer[0], buffer[1], buffer[2], buffer[3]]);
-                let value = pc_rel.wrapping_add(addend);
-                buffer.copy_from_slice(&value.to_le_bytes()[..]);
-            }
-        }
-    }
-
-    fn supports_veneer(self) -> bool {
-        match self {
-            LabelUse::JmpRel32 | LabelUse::PCRel32 => false,
-        }
-    }
-
-    fn veneer_size(self) -> CodeOffset {
-        match self {
-            LabelUse::JmpRel32 | LabelUse::PCRel32 => 0,
-        }
-    }
-
-    fn generate_veneer(self, _: &mut [u8], _: CodeOffset) -> (CodeOffset, LabelUse) {
-        match self {
-            LabelUse::JmpRel32 | LabelUse::PCRel32 => {
-                panic!("Veneer not supported for JumpRel32 label-use.");
-            }
-        }
-    }
-
-    fn from_reloc(reloc: Reloc, addend: Addend) -> Option<Self> {
-        match (reloc, addend) {
-            (Reloc::X86CallPCRel4, -4) => Some(LabelUse::JmpRel32),
-            _ => None,
-        }
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/inst/regs.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/inst/regs.rs
deleted file mode 100644
index ddcf3adc2..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/inst/regs.rs
+++ /dev/null
@@ -1,304 +0,0 @@
-//! Registers, the Universe thereof, and printing.
-//!
-//! These are ordered by sequence number, as required in the Universe.
-//!
-//! The caller-saved registers are placed first in order to prefer not to clobber (requiring
-//! saves/restores in prologue/epilogue code) when possible. Note that there is no other heuristic
-//! in the backend that will apply such pressure; the register allocator's cost heuristics are not
-//! aware of the cost of clobber-save/restore code.
-//!
-//! One might worry that this pessimizes code with many callsites, where using caller-saves causes
-//! us to have to save them (as we are the caller) frequently. However, the register allocator
-//! *should be* aware of *this* cost, because it sees that the call instruction modifies all of the
-//! caller-saved (i.e., callee-clobbered) registers.
-//!
-//! Hence, this ordering encodes pressure in one direction (prefer not to clobber registers that we
-//! ourselves have to save) and this is balanaced against the RA's pressure in the other direction
-//! at callsites.
-
-use crate::settings;
-use alloc::vec::Vec;
-use regalloc::{
-    PrettyPrint, RealReg, RealRegUniverse, Reg, RegClass, RegClassInfo, NUM_REG_CLASSES,
-};
-use std::string::String;
-
-// Hardware encodings (note the special rax, rcx, rdx, rbx order).
-
-pub const ENC_RAX: u8 = 0;
-pub const ENC_RCX: u8 = 1;
-pub const ENC_RDX: u8 = 2;
-pub const ENC_RBX: u8 = 3;
-pub const ENC_RSP: u8 = 4;
-pub const ENC_RBP: u8 = 5;
-pub const ENC_RSI: u8 = 6;
-pub const ENC_RDI: u8 = 7;
-pub const ENC_R8: u8 = 8;
-pub const ENC_R9: u8 = 9;
-pub const ENC_R10: u8 = 10;
-pub const ENC_R11: u8 = 11;
-pub const ENC_R12: u8 = 12;
-pub const ENC_R13: u8 = 13;
-pub const ENC_R14: u8 = 14;
-pub const ENC_R15: u8 = 15;
-
-fn gpr(enc: u8, index: u8) -> Reg {
-    Reg::new_real(RegClass::I64, enc, index)
-}
-
-pub(crate) fn rsi() -> Reg {
-    gpr(ENC_RSI, 16)
-}
-pub(crate) fn rdi() -> Reg {
-    gpr(ENC_RDI, 17)
-}
-pub(crate) fn rax() -> Reg {
-    gpr(ENC_RAX, 18)
-}
-pub(crate) fn rcx() -> Reg {
-    gpr(ENC_RCX, 19)
-}
-pub(crate) fn rdx() -> Reg {
-    gpr(ENC_RDX, 20)
-}
-pub(crate) fn r8() -> Reg {
-    gpr(ENC_R8, 21)
-}
-pub(crate) fn r9() -> Reg {
-    gpr(ENC_R9, 22)
-}
-pub(crate) fn r10() -> Reg {
-    gpr(ENC_R10, 23)
-}
-pub(crate) fn r11() -> Reg {
-    gpr(ENC_R11, 24)
-}
-pub(crate) fn r12() -> Reg {
-    gpr(ENC_R12, 25)
-}
-pub(crate) fn r13() -> Reg {
-    gpr(ENC_R13, 26)
-}
-pub(crate) fn r14() -> Reg {
-    gpr(ENC_R14, 27)
-}
-pub(crate) fn rbx() -> Reg {
-    gpr(ENC_RBX, 28)
-}
-
-pub(crate) fn r15() -> Reg {
-    // r15 is put aside since this is the pinned register.
-    gpr(ENC_R15, 29)
-}
-
-/// The pinned register on this architecture.
-/// It must be the same as Spidermonkey's HeapReg, as found in this file.
-/// https://searchfox.org/mozilla-central/source/js/src/jit/x64/Assembler-x64.h#99
-pub(crate) fn pinned_reg() -> Reg {
-    r15()
-}
-
-fn fpr(enc: u8, index: u8) -> Reg {
-    Reg::new_real(RegClass::V128, enc, index)
-}
-
-pub(crate) fn xmm0() -> Reg {
-    fpr(0, 0)
-}
-pub(crate) fn xmm1() -> Reg {
-    fpr(1, 1)
-}
-pub(crate) fn xmm2() -> Reg {
-    fpr(2, 2)
-}
-pub(crate) fn xmm3() -> Reg {
-    fpr(3, 3)
-}
-pub(crate) fn xmm4() -> Reg {
-    fpr(4, 4)
-}
-pub(crate) fn xmm5() -> Reg {
-    fpr(5, 5)
-}
-pub(crate) fn xmm6() -> Reg {
-    fpr(6, 6)
-}
-pub(crate) fn xmm7() -> Reg {
-    fpr(7, 7)
-}
-pub(crate) fn xmm8() -> Reg {
-    fpr(8, 8)
-}
-pub(crate) fn xmm9() -> Reg {
-    fpr(9, 9)
-}
-pub(crate) fn xmm10() -> Reg {
-    fpr(10, 10)
-}
-pub(crate) fn xmm11() -> Reg {
-    fpr(11, 11)
-}
-pub(crate) fn xmm12() -> Reg {
-    fpr(12, 12)
-}
-pub(crate) fn xmm13() -> Reg {
-    fpr(13, 13)
-}
-pub(crate) fn xmm14() -> Reg {
-    fpr(14, 14)
-}
-pub(crate) fn xmm15() -> Reg {
-    fpr(15, 15)
-}
-
-pub(crate) fn rsp() -> Reg {
-    gpr(ENC_RSP, 30)
-}
-pub(crate) fn rbp() -> Reg {
-    gpr(ENC_RBP, 31)
-}
-
-/// Create the register universe for X64.
-///
-/// The ordering of registers matters, as commented in the file doc comment: assumes the
-/// calling-convention is SystemV, at the moment.
-pub(crate) fn create_reg_universe_systemv(flags: &settings::Flags) -> RealRegUniverse {
-    let mut regs = Vec::<(RealReg, String)>::new();
-    let mut allocable_by_class = [None; NUM_REG_CLASSES];
-
-    let use_pinned_reg = flags.enable_pinned_reg();
-
-    // XMM registers
-    let first_fpr = regs.len();
-    regs.push((xmm0().to_real_reg(), "%xmm0".into()));
-    regs.push((xmm1().to_real_reg(), "%xmm1".into()));
-    regs.push((xmm2().to_real_reg(), "%xmm2".into()));
-    regs.push((xmm3().to_real_reg(), "%xmm3".into()));
-    regs.push((xmm4().to_real_reg(), "%xmm4".into()));
-    regs.push((xmm5().to_real_reg(), "%xmm5".into()));
-    regs.push((xmm6().to_real_reg(), "%xmm6".into()));
-    regs.push((xmm7().to_real_reg(), "%xmm7".into()));
-    regs.push((xmm8().to_real_reg(), "%xmm8".into()));
-    regs.push((xmm9().to_real_reg(), "%xmm9".into()));
-    regs.push((xmm10().to_real_reg(), "%xmm10".into()));
-    regs.push((xmm11().to_real_reg(), "%xmm11".into()));
-    regs.push((xmm12().to_real_reg(), "%xmm12".into()));
-    regs.push((xmm13().to_real_reg(), "%xmm13".into()));
-    regs.push((xmm14().to_real_reg(), "%xmm14".into()));
-    regs.push((xmm15().to_real_reg(), "%xmm15".into()));
-    let last_fpr = regs.len() - 1;
-
-    // Integer regs.
-    let first_gpr = regs.len();
-
-    // Caller-saved, in the SystemV x86_64 ABI.
-    regs.push((rsi().to_real_reg(), "%rsi".into()));
-    regs.push((rdi().to_real_reg(), "%rdi".into()));
-    regs.push((rax().to_real_reg(), "%rax".into()));
-    regs.push((rcx().to_real_reg(), "%rcx".into()));
-    regs.push((rdx().to_real_reg(), "%rdx".into()));
-    regs.push((r8().to_real_reg(), "%r8".into()));
-    regs.push((r9().to_real_reg(), "%r9".into()));
-    regs.push((r10().to_real_reg(), "%r10".into()));
-    regs.push((r11().to_real_reg(), "%r11".into()));
-
-    // Callee-saved, in the SystemV x86_64 ABI.
-    regs.push((r12().to_real_reg(), "%r12".into()));
-    regs.push((r13().to_real_reg(), "%r13".into()));
-    regs.push((r14().to_real_reg(), "%r14".into()));
-
-    regs.push((rbx().to_real_reg(), "%rbx".into()));
-
-    // Other regs, not available to the allocator.
-    debug_assert_eq!(r15(), pinned_reg());
-    let allocable = if use_pinned_reg {
-        // The pinned register is not allocatable in this case, so record the length before adding
-        // it.
-        let len = regs.len();
-        regs.push((r15().to_real_reg(), "%r15/pinned".into()));
-        len
-    } else {
-        regs.push((r15().to_real_reg(), "%r15".into()));
-        regs.len()
-    };
-    let last_gpr = allocable - 1;
-
-    regs.push((rsp().to_real_reg(), "%rsp".into()));
-    regs.push((rbp().to_real_reg(), "%rbp".into()));
-
-    allocable_by_class[RegClass::I64.rc_to_usize()] = Some(RegClassInfo {
-        first: first_gpr,
-        last: last_gpr,
-        suggested_scratch: Some(r12().get_index()),
-    });
-    allocable_by_class[RegClass::V128.rc_to_usize()] = Some(RegClassInfo {
-        first: first_fpr,
-        last: last_fpr,
-        suggested_scratch: Some(xmm15().get_index()),
-    });
-
-    // Sanity-check: the index passed to the Reg ctor must match the order in the register list.
-    for (i, reg) in regs.iter().enumerate() {
-        assert_eq!(i, reg.0.get_index());
-    }
-
-    RealRegUniverse {
-        regs,
-        allocable,
-        allocable_by_class,
-    }
-}
-
-/// If `ireg` denotes an I64-classed reg, make a best-effort attempt to show its name at some
-/// smaller size (4, 2 or 1 bytes).
-pub fn show_ireg_sized(reg: Reg, mb_rru: Option<&RealRegUniverse>, size: u8) -> String {
-    let mut s = reg.show_rru(mb_rru);
-
-    if reg.get_class() != RegClass::I64 || size == 8 {
-        // We can't do any better.
-        return s;
-    }
-
-    if reg.is_real() {
-        // Change (eg) "rax" into "eax", "ax" or "al" as appropriate.  This is something one could
-        // describe diplomatically as "a kludge", but it's only debug code.
-        let remapper = match s.as_str() {
-            "%rax" => Some(["%eax", "%ax", "%al"]),
-            "%rbx" => Some(["%ebx", "%bx", "%bl"]),
-            "%rcx" => Some(["%ecx", "%cx", "%cl"]),
-            "%rdx" => Some(["%edx", "%dx", "%dl"]),
-            "%rsi" => Some(["%esi", "%si", "%sil"]),
-            "%rdi" => Some(["%edi", "%di", "%dil"]),
-            "%rbp" => Some(["%ebp", "%bp", "%bpl"]),
-            "%rsp" => Some(["%esp", "%sp", "%spl"]),
-            "%r8" => Some(["%r8d", "%r8w", "%r8b"]),
-            "%r9" => Some(["%r9d", "%r9w", "%r9b"]),
-            "%r10" => Some(["%r10d", "%r10w", "%r10b"]),
-            "%r11" => Some(["%r11d", "%r11w", "%r11b"]),
-            "%r12" => Some(["%r12d", "%r12w", "%r12b"]),
-            "%r13" => Some(["%r13d", "%r13w", "%r13b"]),
-            "%r14" => Some(["%r14d", "%r14w", "%r14b"]),
-            "%r15" => Some(["%r15d", "%r15w", "%r15b"]),
-            _ => None,
-        };
-        if let Some(smaller_names) = remapper {
-            match size {
-                4 => s = smaller_names[0].into(),
-                2 => s = smaller_names[1].into(),
-                1 => s = smaller_names[2].into(),
-                _ => panic!("show_ireg_sized: real"),
-            }
-        }
-    } else {
-        // Add a "l", "w" or "b" suffix to RegClass::I64 vregs used at narrower widths.
-        let suffix = match size {
-            4 => "l",
-            2 => "w",
-            1 => "b",
-            _ => panic!("show_ireg_sized: virtual"),
-        };
-        s = s + suffix;
-    }
-
-    s
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/inst/unwind.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/inst/unwind.rs
deleted file mode 100644
index cb86c3b7c..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/inst/unwind.rs
+++ /dev/null
@@ -1,5 +0,0 @@
-#[cfg(feature = "unwind")]
-pub(crate) mod systemv;
-
-#[cfg(feature = "unwind")]
-pub(crate) mod winx64;
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/inst/unwind/systemv.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/inst/unwind/systemv.rs
deleted file mode 100644
index 68575a18e..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/inst/unwind/systemv.rs
+++ /dev/null
@@ -1,201 +0,0 @@
-//! Unwind information for System V ABI (x86-64).
-
-use crate::isa::unwind::systemv::RegisterMappingError;
-use gimli::{write::CommonInformationEntry, Encoding, Format, Register, X86_64};
-use regalloc::{Reg, RegClass};
-
-/// Creates a new x86-64 common information entry (CIE).
-pub fn create_cie() -> CommonInformationEntry {
-    use gimli::write::CallFrameInstruction;
-
-    let mut entry = CommonInformationEntry::new(
-        Encoding {
-            address_size: 8,
-            format: Format::Dwarf32,
-            version: 1,
-        },
-        1,  // Code alignment factor
-        -8, // Data alignment factor
-        X86_64::RA,
-    );
-
-    // Every frame will start with the call frame address (CFA) at RSP+8
-    // It is +8 to account for the push of the return address by the call instruction
-    entry.add_instruction(CallFrameInstruction::Cfa(X86_64::RSP, 8));
-
-    // Every frame will start with the return address at RSP (CFA-8 = RSP+8-8 = RSP)
-    entry.add_instruction(CallFrameInstruction::Offset(X86_64::RA, -8));
-
-    entry
-}
-
-/// Map Cranelift registers to their corresponding Gimli registers.
-pub fn map_reg(reg: Reg) -> Result<Register, RegisterMappingError> {
-    // Mapping from https://github.com/bytecodealliance/cranelift/pull/902 by @iximeow
-    const X86_GP_REG_MAP: [gimli::Register; 16] = [
-        X86_64::RAX,
-        X86_64::RCX,
-        X86_64::RDX,
-        X86_64::RBX,
-        X86_64::RSP,
-        X86_64::RBP,
-        X86_64::RSI,
-        X86_64::RDI,
-        X86_64::R8,
-        X86_64::R9,
-        X86_64::R10,
-        X86_64::R11,
-        X86_64::R12,
-        X86_64::R13,
-        X86_64::R14,
-        X86_64::R15,
-    ];
-    const X86_XMM_REG_MAP: [gimli::Register; 16] = [
-        X86_64::XMM0,
-        X86_64::XMM1,
-        X86_64::XMM2,
-        X86_64::XMM3,
-        X86_64::XMM4,
-        X86_64::XMM5,
-        X86_64::XMM6,
-        X86_64::XMM7,
-        X86_64::XMM8,
-        X86_64::XMM9,
-        X86_64::XMM10,
-        X86_64::XMM11,
-        X86_64::XMM12,
-        X86_64::XMM13,
-        X86_64::XMM14,
-        X86_64::XMM15,
-    ];
-
-    match reg.get_class() {
-        RegClass::I64 => {
-            // x86 GP registers have a weird mapping to DWARF registers, so we use a
-            // lookup table.
-            Ok(X86_GP_REG_MAP[reg.get_hw_encoding() as usize])
-        }
-        RegClass::V128 => Ok(X86_XMM_REG_MAP[reg.get_hw_encoding() as usize]),
-        _ => Err(RegisterMappingError::UnsupportedRegisterBank("class?")),
-    }
-}
-
-pub(crate) struct RegisterMapper;
-
-impl crate::isa::unwind::systemv::RegisterMapper<Reg> for RegisterMapper {
-    fn map(&self, reg: Reg) -> Result<u16, RegisterMappingError> {
-        Ok(map_reg(reg)?.0)
-    }
-    fn sp(&self) -> u16 {
-        X86_64::RSP.0
-    }
-    fn fp(&self) -> Option<u16> {
-        Some(X86_64::RBP.0)
-    }
-}
-
-#[cfg(test)]
-mod tests {
-    use crate::cursor::{Cursor, FuncCursor};
-    use crate::ir::{
-        types, AbiParam, ExternalName, Function, InstBuilder, Signature, StackSlotData,
-        StackSlotKind,
-    };
-    use crate::isa::{lookup, CallConv};
-    use crate::settings::{builder, Flags};
-    use crate::Context;
-    use gimli::write::Address;
-    use std::str::FromStr;
-    use target_lexicon::triple;
-
-    #[test]
-    fn test_simple_func() {
-        let isa = lookup(triple!("x86_64"))
-            .expect("expect x86 ISA")
-            .finish(Flags::new(builder()))
-            .expect("expect backend creation to succeed");
-
-        let mut context = Context::for_function(create_function(
-            CallConv::SystemV,
-            Some(StackSlotData::new(StackSlotKind::ExplicitSlot, 64)),
-        ));
-
-        context.compile(&*isa).expect("expected compilation");
-
-        let fde = match context
-            .create_unwind_info(isa.as_ref())
-            .expect("can create unwind info")
-        {
-            Some(crate::isa::unwind::UnwindInfo::SystemV(info)) => {
-                info.to_fde(Address::Constant(1234))
-            }
-            _ => panic!("expected unwind information"),
-        };
-
-        assert_eq!(format!("{:?}", fde), "FrameDescriptionEntry { address: Constant(1234), length: 17, lsda: None, instructions: [(1, CfaOffset(16)), (1, Offset(Register(6), -16)), (4, CfaRegister(Register(6)))] }");
-    }
-
-    fn create_function(call_conv: CallConv, stack_slot: Option<StackSlotData>) -> Function {
-        let mut func =
-            Function::with_name_signature(ExternalName::user(0, 0), Signature::new(call_conv));
-
-        let block0 = func.dfg.make_block();
-        let mut pos = FuncCursor::new(&mut func);
-        pos.insert_block(block0);
-        pos.ins().return_(&[]);
-
-        if let Some(stack_slot) = stack_slot {
-            func.stack_slots.push(stack_slot);
-        }
-
-        func
-    }
-
-    #[test]
-    fn test_multi_return_func() {
-        let isa = lookup(triple!("x86_64"))
-            .expect("expect x86 ISA")
-            .finish(Flags::new(builder()))
-            .expect("expect backend creation to succeed");
-
-        let mut context = Context::for_function(create_multi_return_function(CallConv::SystemV));
-
-        context.compile(&*isa).expect("expected compilation");
-
-        let fde = match context
-            .create_unwind_info(isa.as_ref())
-            .expect("can create unwind info")
-        {
-            Some(crate::isa::unwind::UnwindInfo::SystemV(info)) => {
-                info.to_fde(Address::Constant(4321))
-            }
-            _ => panic!("expected unwind information"),
-        };
-
-        assert_eq!(format!("{:?}", fde), "FrameDescriptionEntry { address: Constant(4321), length: 22, lsda: None, instructions: [(1, CfaOffset(16)), (1, Offset(Register(6), -16)), (4, CfaRegister(Register(6)))] }");
-    }
-
-    fn create_multi_return_function(call_conv: CallConv) -> Function {
-        let mut sig = Signature::new(call_conv);
-        sig.params.push(AbiParam::new(types::I32));
-        let mut func = Function::with_name_signature(ExternalName::user(0, 0), sig);
-
-        let block0 = func.dfg.make_block();
-        let v0 = func.dfg.append_block_param(block0, types::I32);
-        let block1 = func.dfg.make_block();
-        let block2 = func.dfg.make_block();
-
-        let mut pos = FuncCursor::new(&mut func);
-        pos.insert_block(block0);
-        pos.ins().brnz(v0, block2, &[]);
-        pos.ins().jump(block1, &[]);
-
-        pos.insert_block(block1);
-        pos.ins().return_(&[]);
-
-        pos.insert_block(block2);
-        pos.ins().return_(&[]);
-
-        func
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/inst/unwind/winx64.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/inst/unwind/winx64.rs
deleted file mode 100644
index ffffc5fef..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/inst/unwind/winx64.rs
+++ /dev/null
@@ -1,16 +0,0 @@
-//! Unwind information for Windows x64 ABI.
-
-use regalloc::{Reg, RegClass};
-
-pub(crate) struct RegisterMapper;
-
-impl crate::isa::unwind::winx64::RegisterMapper<Reg> for RegisterMapper {
-    fn map(reg: Reg) -> crate::isa::unwind::winx64::MappedRegister {
-        use crate::isa::unwind::winx64::MappedRegister;
-        match reg.get_class() {
-            RegClass::I64 => MappedRegister::Int(reg.get_hw_encoding()),
-            RegClass::V128 => MappedRegister::Xmm(reg.get_hw_encoding()),
-            _ => unreachable!(),
-        }
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/lower.isle b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/lower.isle
deleted file mode 100644
index cb7636939..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/lower.isle
+++ /dev/null
@@ -1,2252 +0,0 @@
-;; x86-64 instruction selection and CLIF-to-MachInst lowering.
-
-;; The main lowering constructor term: takes a clif `Inst` and returns the
-;; register(s) within which the lowered instruction's result values live.
-(decl lower (Inst) InstOutput)
-
-;;;; Rules for `iconst` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; `i64` and smaller.
-(rule (lower (has_type (fits_in_64 ty)
-                       (iconst (u64_from_imm64 x))))
-      (imm ty x))
-
-;; `i128`
-(rule (lower (has_type $I128
-                       (iconst (u64_from_imm64 x))))
-      (value_regs (imm $I64 x)
-                  (imm $I64 0)))
-
-;;;; Rules for `bconst` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; `b64` and smaller.
-
-(rule (lower (has_type (fits_in_64 ty)
-                       (bconst $false)))
-      (imm ty 0))
-
-(rule (lower (has_type (fits_in_64 ty)
-                       (bconst $true)))
-      (imm ty 1))
-
-;; `b128`
-
-(rule (lower (has_type $B128
-                       (bconst $false)))
-      (value_regs (imm $B64 0)
-                  (imm $B64 0)))
-
-(rule (lower (has_type $B128
-                       (bconst $true)))
-      (value_regs (imm $B64 1)
-                  (imm $B64 0)))
-
-;;;; Rules for `f32const` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (f32const (u64_from_ieee32 x)))
-      (imm $F32 x))
-
-;;;; Rules for `f64const` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (f64const (u64_from_ieee64 x)))
-      (imm $F64 x))
-
-;;;; Rules for `null` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type ty (null)))
-      (imm ty 0))
-
-;;;; Rules for `iadd` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; `i64` and smaller.
-
-;; Add two registers.
-(rule (lower (has_type (fits_in_64 ty)
-                       (iadd x y)))
-      (add ty x y))
-
-;; Add a register and an immediate.
-
-(rule (lower (has_type (fits_in_64 ty)
-                       (iadd x (simm32_from_value y))))
-      (add ty x y))
-
-(rule (lower (has_type (fits_in_64 ty)
-                       (iadd (simm32_from_value x) y)))
-      (add ty y x))
-
-;; Add a register and memory.
-
-(rule (lower (has_type (fits_in_64 ty)
-                       (iadd x (sinkable_load y))))
-      (add ty
-           x
-           (sink_load_to_gpr_mem_imm y)))
-
-(rule (lower (has_type (fits_in_64 ty)
-                       (iadd (sinkable_load x) y)))
-      (add ty
-           y
-           (sink_load_to_gpr_mem_imm x)))
-
-;; SSE.
-
-(rule (lower (has_type (multi_lane 8 16)
-                       (iadd x y)))
-      (paddb x y))
-
-(rule (lower (has_type (multi_lane 16 8)
-                       (iadd x y)))
-      (paddw x y))
-
-(rule (lower (has_type (multi_lane 32 4)
-                       (iadd x y)))
-      (paddd x y))
-
-(rule (lower (has_type (multi_lane 64 2)
-                       (iadd x y)))
-      (paddq x y))
-
-;; `i128`
-(rule (lower (has_type $I128 (iadd x y)))
-      ;; Get the high/low registers for `x`.
-      (let ((x_regs ValueRegs x)
-            (x_lo Gpr (value_regs_get_gpr x_regs 0))
-            (x_hi Gpr (value_regs_get_gpr x_regs 1)))
-        ;; Get the high/low registers for `y`.
-        (let ((y_regs ValueRegs y)
-              (y_lo Gpr (value_regs_get_gpr y_regs 0))
-              (y_hi Gpr (value_regs_get_gpr y_regs 1)))
-          ;; Do an add followed by an add-with-carry.
-          (with_flags (add_with_flags_paired $I64 x_lo y_lo)
-                      (adc_paired $I64 x_hi y_hi)))))
-
-;;;; Rules for `sadd_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type (multi_lane 8 16)
-                       (sadd_sat x y)))
-      (paddsb x y))
-
-(rule (lower (has_type (multi_lane 16 8)
-                       (sadd_sat x y)))
-      (paddsw x y))
-
-;;;; Rules for `uadd_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type (multi_lane 8 16)
-                       (uadd_sat x y)))
-      (paddusb x y))
-
-(rule (lower (has_type (multi_lane 16 8)
-                       (uadd_sat x y)))
-      (paddusw x y))
-
-;;;; Rules for `iadd_ifcout` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; N.B.: the second output of `iadd_ifcout` is meant to be the
-;; `iflags` value containing the carry result. However, we plan to
-;; replace this with a bool carry flag, and all consumers of `iflags`
-;; remain in the handwritten pattern-matching code and explicitly
-;; match on the flags producer. So we can get away with just
-;; using an invalid second output, and the reg-renaming code does the
-;; right thing, for now. For safety, we assert elsewhere that no one
-;; actually uses the register assigned to the SSA `iflags`-typed
-;; `Value`.
-
-(decl output_ifcout (Reg) InstOutput)
-(rule (output_ifcout reg)
-      (output_pair reg (value_regs_invalid)))
-
-;; Add two registers.
-(rule (lower (has_type (fits_in_64 ty)
-                       (iadd_ifcout x y)))
-      (output_ifcout (add ty x y)))
-
-;; Add a register and an immediate.
-
-(rule (lower (has_type (fits_in_64 ty)
-                       (iadd_ifcout x (simm32_from_value y))))
-      (output_ifcout (add ty x y)))
-
-(rule (lower (has_type (fits_in_64 ty)
-                       (iadd_ifcout (simm32_from_value x) y)))
-      (output_ifcout (add ty y x)))
-
-;; Add a register and memory.
-
-(rule (lower (has_type (fits_in_64 ty)
-                       (iadd_ifcout x (sinkable_load y))))
-      (output_ifcout (add ty x (sink_load_to_gpr_mem_imm y))))
-
-(rule (lower (has_type (fits_in_64 ty)
-                       (iadd_ifcout (sinkable_load x) y)))
-      (output_ifcout (add ty y (sink_load_to_gpr_mem_imm x))))
-
-;; (No `iadd_ifcout` for `i128`.)
-
-;;;; Rules for `iadd_imm` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; `i64` and smaller.
-
-;; When the immediate fits in a `RegMemImm.Imm`, use that.
-(rule (lower (has_type (fits_in_64 ty) (iadd_imm y (simm32_from_imm64 x))))
-      (add ty y x))
-
-;; Otherwise, put the immediate into a register.
-(rule (lower (has_type (fits_in_64 ty) (iadd_imm y (u64_from_imm64 x))))
-      (add ty y (imm ty x)))
-
-;; `i128`
-
-;; When the immediate fits in a `RegMemImm.Imm`, use that.
-(rule (lower (has_type $I128 (iadd_imm y (simm32_from_imm64 x))))
-      (let ((y_regs ValueRegs y)
-            (y_lo Gpr (value_regs_get_gpr y_regs 0))
-            (y_hi Gpr (value_regs_get_gpr y_regs 1)))
-        (with_flags (add_with_flags_paired $I64 y_lo x)
-                    (adc_paired $I64 y_hi (RegMemImm.Imm 0)))))
-
-;; Otherwise, put the immediate into a register.
-(rule (lower (has_type $I128 (iadd_imm y (u64_from_imm64 x))))
-      (let ((y_regs ValueRegs y)
-            (y_lo Gpr (value_regs_get_gpr y_regs 0))
-            (y_hi Gpr (value_regs_get_gpr y_regs 1))
-            (x_lo Gpr (imm $I64 x)))
-        (with_flags (add_with_flags_paired $I64 y_lo x_lo)
-                    (adc_paired $I64 y_hi (RegMemImm.Imm 0)))))
-
-;;;; Rules for `isub` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; `i64` and smaller.
-
-;; Sub two registers.
-(rule (lower (has_type (fits_in_64 ty)
-                       (isub x y)))
-      (sub ty x y))
-
-;; Sub a register and an immediate.
-(rule (lower (has_type (fits_in_64 ty)
-                       (isub x (simm32_from_value y))))
-      (sub ty x y))
-
-;; Sub a register and memory.
-(rule (lower (has_type (fits_in_64 ty)
-                       (isub x (sinkable_load y))))
-      (sub ty x
-           (sink_load_to_gpr_mem_imm y)))
-
-;; SSE.
-
-(rule (lower (has_type (multi_lane 8 16)
-                       (isub x y)))
-      (psubb x y))
-
-(rule (lower (has_type (multi_lane 16 8)
-                       (isub x y)))
-      (psubw x y))
-
-(rule (lower (has_type (multi_lane 32 4)
-                       (isub x y)))
-      (psubd x y))
-
-(rule (lower (has_type (multi_lane 64 2)
-                       (isub x y)))
-      (psubq x y))
-
-;; `i128`
-(rule (lower (has_type $I128 (isub x y)))
-      ;; Get the high/low registers for `x`.
-      (let ((x_regs ValueRegs x)
-            (x_lo Gpr (value_regs_get_gpr x_regs 0))
-            (x_hi Gpr (value_regs_get_gpr x_regs 1)))
-        ;; Get the high/low registers for `y`.
-        (let ((y_regs ValueRegs y)
-              (y_lo Gpr (value_regs_get_gpr y_regs 0))
-              (y_hi Gpr (value_regs_get_gpr y_regs 1)))
-          ;; Do a sub followed by an sub-with-borrow.
-          (with_flags (sub_with_flags_paired $I64 x_lo y_lo)
-                      (sbb_paired $I64 x_hi y_hi)))))
-
-;;;; Rules for `ssub_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type (multi_lane 8 16)
-                       (ssub_sat x y)))
-      (psubsb x y))
-
-(rule (lower (has_type (multi_lane 16 8)
-                       (ssub_sat x y)))
-      (psubsw x y))
-
-;;;; Rules for `usub_sat` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type (multi_lane 8 16)
-                       (usub_sat x y)))
-      (psubusb x y))
-
-(rule (lower (has_type (multi_lane 16 8)
-                       (usub_sat x y)))
-      (psubusw x y))
-
-;;;; Rules for `band` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; `{i,b}64` and smaller.
-
-;; And two registers.
-(rule (lower (has_type (fits_in_64 ty) (band x y)))
-      (x64_and ty x y))
-
-;; And with a memory operand.
-
-(rule (lower (has_type (fits_in_64 ty)
-                       (band x (sinkable_load y))))
-      (x64_and ty x
-               (sink_load_to_gpr_mem_imm y)))
-
-(rule (lower (has_type (fits_in_64 ty)
-                       (band (sinkable_load x) y)))
-      (x64_and ty
-               y
-               (sink_load_to_gpr_mem_imm x)))
-
-;; And with an immediate.
-
-(rule (lower (has_type (fits_in_64 ty)
-                       (band x (simm32_from_value y))))
-      (x64_and ty x y))
-
-(rule (lower (has_type (fits_in_64 ty)
-                       (band (simm32_from_value x) y)))
-      (x64_and ty y x))
-
-;; SSE.
-
-(decl sse_and (Type Xmm XmmMem) Xmm)
-(rule (sse_and $F32X4 x y) (andps x y))
-(rule (sse_and $F64X2 x y) (andpd x y))
-(rule (sse_and (multi_lane _bits _lanes) x y) (pand x y))
-
-(rule (lower (has_type ty @ (multi_lane _bits _lanes)
-                       (band x y)))
-      (sse_and ty x y))
-
-;; `{i,b}128`.
-
-(rule (lower (has_type $I128 (band x y)))
-      (let ((x_regs ValueRegs x)
-            (x_lo Gpr (value_regs_get_gpr x_regs 0))
-            (x_hi Gpr (value_regs_get_gpr x_regs 1))
-            (y_regs ValueRegs y)
-            (y_lo Gpr (value_regs_get_gpr y_regs 0))
-            (y_hi Gpr (value_regs_get_gpr y_regs 1)))
-        (value_gprs (x64_and $I64 x_lo y_lo)
-                    (x64_and $I64 x_hi y_hi))))
-
-(rule (lower (has_type $B128 (band x y)))
-      ;; Booleans are always `0` or `1`, so we only need to do the `and` on the
-      ;; low half. The high half is always zero but, rather than generate a new
-      ;; zero, we just reuse `x`'s high half which is already zero.
-      (let ((x_regs ValueRegs x)
-            (x_lo Gpr (value_regs_get_gpr x_regs 0))
-            (x_hi Gpr (value_regs_get_gpr x_regs 1))
-            (y_lo Gpr (lo_gpr y)))
-        (value_gprs (x64_and $I64 x_lo y_lo)
-                    x_hi)))
-
-;;;; Rules for `bor` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; `{i,b}64` and smaller.
-
-;; Or two registers.
-(rule (lower (has_type (fits_in_64 ty) (bor x y)))
-      (or ty x y))
-
-;; Or with a memory operand.
-
-(rule (lower (has_type (fits_in_64 ty)
-                       (bor x (sinkable_load y))))
-      (or ty x
-          (sink_load_to_gpr_mem_imm y)))
-
-(rule (lower (has_type (fits_in_64 ty)
-                       (bor (sinkable_load x) y)))
-      (or ty y
-          (sink_load_to_gpr_mem_imm x)))
-
-;; Or with an immediate.
-
-(rule (lower (has_type (fits_in_64 ty)
-                       (bor x (simm32_from_value y))))
-      (or ty x y))
-
-(rule (lower (has_type (fits_in_64 ty)
-                       (bor (simm32_from_value x) y)))
-      (or ty y x))
-
-;; SSE.
-
-(decl sse_or (Type Xmm XmmMem) Xmm)
-(rule (sse_or $F32X4 x y) (orps x y))
-(rule (sse_or $F64X2 x y) (orpd x y))
-(rule (sse_or (multi_lane _bits _lanes) x y) (por x y))
-
-(rule (lower (has_type ty @ (multi_lane _bits _lanes)
-                       (bor x y)))
-      (sse_or ty x y))
-
-;; `{i,b}128`.
-
-(decl or_i128 (ValueRegs ValueRegs) ValueRegs)
-(rule (or_i128 x y)
-      (let ((x_lo Gpr (value_regs_get_gpr x 0))
-            (x_hi Gpr (value_regs_get_gpr x 1))
-            (y_lo Gpr (value_regs_get_gpr y 0))
-            (y_hi Gpr (value_regs_get_gpr y 1)))
-        (value_gprs (or $I64 x_lo y_lo)
-                    (or $I64 x_hi y_hi))))
-
-(rule (lower (has_type $I128 (bor x y)))
-      (or_i128 x y))
-
-(rule (lower (has_type $B128 (bor x y)))
-      ;; Booleans are always `0` or `1`, so we only need to do the `or` on the
-      ;; low half. The high half is always zero but, rather than generate a new
-      ;; zero, we just reuse `x`'s high half which is already zero.
-      (let ((x_regs ValueRegs x)
-            (x_lo Gpr (value_regs_get_gpr x_regs 0))
-            (x_hi Gpr (value_regs_get_gpr x_regs 1))
-            (y_lo Gpr (lo_gpr y)))
-        (value_gprs (or $I64 x_lo y_lo)
-                    x_hi)))
-
-;;;; Rules for `bxor` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; `{i,b}64` and smaller.
-
-;; Xor two registers.
-(rule (lower (has_type (fits_in_64 ty) (bxor x y)))
-      (xor ty x y))
-
-;; Xor with a memory operand.
-
-(rule (lower (has_type (fits_in_64 ty)
-                       (bxor x (sinkable_load y))))
-      (xor ty x
-           (sink_load_to_gpr_mem_imm y)))
-
-(rule (lower (has_type (fits_in_64 ty)
-                       (bxor (sinkable_load x) y)))
-      (xor ty y
-           (sink_load_to_gpr_mem_imm x)))
-
-;; Xor with an immediate.
-
-(rule (lower (has_type (fits_in_64 ty)
-                       (bxor x (simm32_from_value y))))
-      (xor ty x y))
-
-(rule (lower (has_type (fits_in_64 ty)
-                       (bxor (simm32_from_value x) y)))
-      (xor ty y x))
-
-;; SSE.
-
-(rule (lower (has_type ty @ (multi_lane _bits _lanes) (bxor x y)))
-      (sse_xor ty x y))
-
-;; `{i,b}128`.
-
-(rule (lower (has_type $I128 (bxor x y)))
-      (let ((x_regs ValueRegs x)
-            (x_lo Gpr (value_regs_get_gpr x_regs 0))
-            (x_hi Gpr (value_regs_get_gpr x_regs 1))
-            (y_regs ValueRegs y)
-            (y_lo Gpr (value_regs_get_gpr y_regs 0))
-            (y_hi Gpr (value_regs_get_gpr y_regs 1)))
-        (value_gprs (xor $I64 x_lo y_lo)
-                    (xor $I64 x_hi y_hi))))
-
-(rule (lower (has_type $B128 (bxor x y)))
-      ;; Booleans are always `0` or `1`, so we only need to do the `xor` on the
-      ;; low half. The high half is always zero but, rather than generate a new
-      ;; zero, we just reuse `x`'s high half which is already zero.
-      (let ((x_regs ValueRegs x)
-            (x_lo Gpr (value_regs_get_gpr x_regs 0))
-            (x_hi Gpr (value_regs_get_gpr x_regs 1))
-            (y_lo Gpr (lo_gpr y)))
-        (value_gprs (xor $I64 x_lo y_lo)
-                    x_hi)))
-
-;;;; Rules for `ishl` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; `i64` and smaller.
-
-(rule (lower (has_type (fits_in_64 ty) (ishl src amt)))
-      (shl ty src (put_masked_in_imm8_gpr amt ty)))
-
-;; `i128`.
-
-(decl shl_i128 (ValueRegs Gpr) ValueRegs)
-(rule (shl_i128 src amt)
-      ;; Unpack the registers that make up the 128-bit value being shifted.
-      (let ((src_lo Gpr (value_regs_get_gpr src 0))
-            (src_hi Gpr (value_regs_get_gpr src 1))
-            ;; Do two 64-bit shifts.
-            (lo_shifted Gpr (shl $I64 src_lo amt))
-            (hi_shifted Gpr (shl $I64 src_hi amt))
-            ;; `src_lo >> (64 - amt)` are the bits to carry over from the lo
-            ;; into the hi.
-            (carry Gpr (shr $I64
-                            src_lo
-                            (sub $I64
-                                 (imm $I64 64)
-                                 amt)))
-            (zero Gpr (imm $I64 0))
-            ;; Nullify the carry if we are shifting in by a multiple of 128.
-            (carry_ Gpr (with_flags_reg (test (OperandSize.Size64)
-                                              (RegMemImm.Imm 127)
-                                              amt)
-                                        (cmove $I64
-                                               (CC.Z)
-                                               zero
-                                               carry)))
-            ;; Add the carry into the high half.
-            (hi_shifted_ Gpr (or $I64 carry_ hi_shifted)))
-        ;; Combine the two shifted halves. However, if we are shifting by >= 64
-        ;; (modulo 128), then the low bits are zero and the high bits are our
-        ;; low bits.
-        (with_flags (test (OperandSize.Size64) (RegMemImm.Imm 64) amt)
-                    (consumes_flags_concat
-                     (cmove $I64 (CC.Z) lo_shifted zero)
-                     (cmove $I64 (CC.Z) hi_shifted_ lo_shifted)))))
-
-(rule (lower (has_type $I128 (ishl src amt)))
-      ;; NB: Only the low bits of `amt` matter since we logically mask the shift
-      ;; amount to the value's bit width.
-      (let ((amt_ Gpr (lo_gpr amt)))
-        (shl_i128 src amt_)))
-
-;; SSE.
-
-;; Since the x86 instruction set does not have any 8x16 shift instructions (even
-;; in higher feature sets like AVX), we lower the `ishl.i8x16` to a sequence of
-;; instructions. The basic idea, whether the amount to shift by is an immediate
-;; or not, is to use a 16x8 shift and then mask off the incorrect bits to 0s.
-(rule (lower (has_type $I8X16 (ishl src amt)))
-      (let (
-            ;; Shift `src` using 16x8. Unfortunately, a 16x8 shift will only be
-            ;; correct for half of the lanes; the others must be fixed up with
-            ;; the mask below.
-            (unmasked Xmm (psllw src (mov_rmi_to_xmm amt)))
-            (mask_addr SyntheticAmode (ishl_i8x16_mask amt))
-            (mask Reg (x64_load $I8X16 mask_addr (ExtKind.None))))
-        (sse_and $I8X16 unmasked (RegMem.Reg mask))))
-
-;; Get the address of the mask to use when fixing up the lanes that weren't
-;; correctly generated by the 16x8 shift.
-(decl ishl_i8x16_mask (RegMemImm) SyntheticAmode)
-
-;; When the shift amount is known, we can statically (i.e. at compile time)
-;; determine the mask to use and only emit that.
-(decl ishl_i8x16_mask_for_const (u32) SyntheticAmode)
-(extern constructor ishl_i8x16_mask_for_const ishl_i8x16_mask_for_const)
-(rule (ishl_i8x16_mask (RegMemImm.Imm amt))
-      (ishl_i8x16_mask_for_const amt))
-
-;; Otherwise, we must emit the entire mask table and dynamically (i.e. at run
-;; time) find the correct mask offset in the table. We use `lea` to find the
-;; base address of the mask table and then complex addressing to offset to the
-;; right mask: `base_address + amt << 4`
-(decl ishl_i8x16_mask_table () SyntheticAmode)
-(extern constructor ishl_i8x16_mask_table ishl_i8x16_mask_table)
-(rule (ishl_i8x16_mask (RegMemImm.Reg amt))
-      (let ((mask_table SyntheticAmode (ishl_i8x16_mask_table))
-            (base_mask_addr Gpr (lea mask_table))
-            (mask_offset Gpr (shl $I64 amt
-                                  (imm8_to_imm8_gpr 4))))
-        (amode_imm_reg_reg_shift 0
-                                 base_mask_addr
-                                 mask_offset
-                                 0)))
-
-(rule (ishl_i8x16_mask (RegMemImm.Mem amt))
-      (ishl_i8x16_mask (RegMemImm.Reg (x64_load $I64 amt (ExtKind.None)))))
-
-;; 16x8, 32x4, and 64x2 shifts can each use a single instruction.
-
-(rule (lower (has_type $I16X8 (ishl src amt)))
-      (psllw src (mov_rmi_to_xmm amt)))
-
-(rule (lower (has_type $I32X4 (ishl src amt)))
-      (pslld src (mov_rmi_to_xmm amt)))
-
-(rule (lower (has_type $I64X2 (ishl src amt)))
-      (psllq src (mov_rmi_to_xmm amt)))
-
-;;;; Rules for `ushr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; `i64` and smaller.
-
-(rule (lower (has_type (fits_in_64 ty) (ushr src amt)))
-      (let ((src_ Gpr (extend_to_gpr src ty (ExtendKind.Zero))))
-        (shr ty src_ (put_masked_in_imm8_gpr amt ty))))
-
-;; `i128`.
-
-(decl shr_i128 (ValueRegs Gpr) ValueRegs)
-(rule (shr_i128 src amt)
-      ;; Unpack the lo/hi halves of `src`.
-      (let ((src_lo Gpr (value_regs_get_gpr src 0))
-            (src_hi Gpr (value_regs_get_gpr src 1))
-            ;; Do a shift on each half.
-            (lo_shifted Gpr (shr $I64 src_lo amt))
-            (hi_shifted Gpr (shr $I64 src_hi amt))
-            ;; `src_hi << (64 - amt)` are the bits to carry over from the hi
-            ;; into the lo.
-            (carry Gpr (shl $I64
-                            src_hi
-                            (sub $I64
-                                 (imm $I64 64)
-                                 amt)))
-            ;; Nullify the carry if we are shifting by a multiple of 128.
-            (carry_ Gpr (with_flags_reg (test (OperandSize.Size64) (RegMemImm.Imm 127) amt)
-                                        (cmove $I64 (CC.Z) (imm $I64 0) carry)))
-            ;; Add the carry bits into the lo.
-            (lo_shifted_ Gpr (or $I64 carry_ lo_shifted)))
-        ;; Combine the two shifted halves. However, if we are shifting by >= 64
-        ;; (modulo 128), then the hi bits are zero and the lo bits are what
-        ;; would otherwise be our hi bits.
-        (with_flags (test (OperandSize.Size64) (RegMemImm.Imm 64) amt)
-                    (consumes_flags_concat
-                     (cmove $I64 (CC.Z) lo_shifted_ hi_shifted)
-                     (cmove $I64 (CC.Z) hi_shifted (imm $I64 0))))))
-
-(rule (lower (has_type $I128 (ushr src amt)))
-      ;; NB: Only the low bits of `amt` matter since we logically mask the shift
-      ;; amount to the value's bit width.
-      (let ((amt_ Gpr (lo_gpr amt)))
-        (shr_i128 src amt_)))
-
-;; SSE.
-
-;; There are no 8x16 shifts in x64. Do the same 16x8-shift-and-mask thing we do
-;; with 8x16 `ishl`.
-(rule (lower (has_type $I8X16 (ushr src amt)))
-      (let (
-            ;; Shift `src` using 16x8. Unfortunately, a 16x8 shift will only be
-            ;; correct for half of the lanes; the others must be fixed up with
-            ;; the mask below.
-            (unmasked Xmm (psrlw src (mov_rmi_to_xmm amt)))
-            (mask_addr SyntheticAmode (ushr_i8x16_mask amt))
-            (mask Reg (x64_load $I8X16 mask_addr (ExtKind.None))))
-        (sse_and $I8X16
-                 unmasked
-                 (RegMem.Reg mask))))
-
-;; Get the address of the mask to use when fixing up the lanes that weren't
-;; correctly generated by the 16x8 shift.
-(decl ushr_i8x16_mask (RegMemImm) SyntheticAmode)
-
-;; When the shift amount is known, we can statically (i.e. at compile time)
-;; determine the mask to use and only emit that.
-(decl ushr_i8x16_mask_for_const (u32) SyntheticAmode)
-(extern constructor ushr_i8x16_mask_for_const ushr_i8x16_mask_for_const)
-(rule (ushr_i8x16_mask (RegMemImm.Imm amt))
-      (ushr_i8x16_mask_for_const amt))
-
-;; Otherwise, we must emit the entire mask table and dynamically (i.e. at run
-;; time) find the correct mask offset in the table. We use `lea` to find the
-;; base address of the mask table and then complex addressing to offset to the
-;; right mask: `base_address + amt << 4`
-(decl ushr_i8x16_mask_table () SyntheticAmode)
-(extern constructor ushr_i8x16_mask_table ushr_i8x16_mask_table)
-(rule (ushr_i8x16_mask (RegMemImm.Reg amt))
-      (let ((mask_table SyntheticAmode (ushr_i8x16_mask_table))
-            (base_mask_addr Gpr (lea mask_table))
-            (mask_offset Gpr (shl $I64
-                                  amt
-                                  (imm8_to_imm8_gpr 4))))
-        (amode_imm_reg_reg_shift 0
-                                 base_mask_addr
-                                 mask_offset
-                                 0)))
-
-(rule (ushr_i8x16_mask (RegMemImm.Mem amt))
-      (ushr_i8x16_mask (RegMemImm.Reg (x64_load $I64 amt (ExtKind.None)))))
-
-;; 16x8, 32x4, and 64x2 shifts can each use a single instruction.
-
-(rule (lower (has_type $I16X8 (ushr src amt)))
-      (psrlw src (mov_rmi_to_xmm amt)))
-
-(rule (lower (has_type $I32X4 (ushr src amt)))
-      (psrld src (mov_rmi_to_xmm amt)))
-
-(rule (lower (has_type $I64X2 (ushr src amt)))
-      (psrlq src (mov_rmi_to_xmm amt)))
-
-;;;; Rules for `sshr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; `i64` and smaller.
-
-(rule (lower (has_type (fits_in_64 ty) (sshr src amt)))
-      (let ((src_ Gpr (extend_to_gpr src ty (ExtendKind.Sign))))
-        (sar ty src_ (put_masked_in_imm8_gpr amt ty))))
-
-;; `i128`.
-
-(decl sar_i128 (ValueRegs Gpr) ValueRegs)
-(rule (sar_i128 src amt)
-      ;; Unpack the low/high halves of `src`.
-      (let ((src_lo Gpr (value_regs_get_gpr src 0))
-            (src_hi Gpr (value_regs_get_gpr src 1))
-            ;; Do a shift of each half. NB: the low half uses an unsigned shift
-            ;; because its MSB is not a sign bit.
-            (lo_shifted Gpr (shr $I64 src_lo amt))
-            (hi_shifted Gpr (sar $I64 src_hi amt))
-            ;; `src_hi << (64 - amt)` are the bits to carry over from the low
-            ;; half to the high half.
-            (carry Gpr (shl $I64
-                            src_hi
-                            (sub $I64
-                                 (imm $I64 64)
-                                 amt)))
-            ;; Nullify the carry if we are shifting by a multiple of 128.
-            (carry_ Gpr (with_flags_reg (test (OperandSize.Size64) (RegMemImm.Imm 127) amt)
-                                        (cmove $I64 (CC.Z) (imm $I64 0) carry)))
-            ;; Add the carry into the low half.
-            (lo_shifted_ Gpr (or $I64 lo_shifted carry_))
-            ;; Get all sign bits.
-            (sign_bits Gpr (sar $I64 src_hi (imm8_to_imm8_gpr 63))))
-        ;; Combine the two shifted halves. However, if we are shifting by >= 64
-        ;; (modulo 128), then the hi bits are all sign bits and the lo bits are
-        ;; what would otherwise be our hi bits.
-        (with_flags (test (OperandSize.Size64) (RegMemImm.Imm 64) amt)
-                    (consumes_flags_concat
-                     (cmove $I64 (CC.Z) lo_shifted_ hi_shifted)
-                     (cmove $I64 (CC.Z) hi_shifted sign_bits)))))
-
-(rule (lower (has_type $I128 (sshr src amt)))
-      ;; NB: Only the low bits of `amt` matter since we logically mask the shift
-      ;; amount to the value's bit width.
-      (let ((amt_ Gpr (lo_gpr amt)))
-        (sar_i128 src amt_)))
-
-;; SSE.
-
-;; Since the x86 instruction set does not have an 8x16 shift instruction and the
-;; approach used for `ishl` and `ushr` cannot be easily used (the masks do not
-;; preserve the sign), we use a different approach here: separate the low and
-;; high lanes, shift them separately, and merge them into the final result.
-;;
-;; Visually, this looks like the following, where `src.i8x16 = [s0, s1, ...,
-;; s15]:
-;;
-;;   lo.i16x8 = [(s0, s0), (s1, s1), ..., (s7, s7)]
-;;   shifted_lo.i16x8 = shift each lane of `low`
-;;   hi.i16x8 = [(s8, s8), (s9, s9), ..., (s15, s15)]
-;;   shifted_hi.i16x8 = shift each lane of `high`
-;;   result = [s0'', s1'', ..., s15'']
-(rule (lower (has_type $I8X16 (sshr src amt @ (value_type amt_ty))))
-      (let ((src_ Xmm (put_in_xmm src))
-            ;; In order for `packsswb` later to only use the high byte of each
-            ;; 16x8 lane, we shift right an extra 8 bits, relying on `psraw` to
-            ;; fill in the upper bits appropriately.
-            (lo Xmm (punpcklbw src_ src_))
-            (hi Xmm (punpckhbw src_ src_))
-            (amt_ XmmMemImm (sshr_i8x16_bigger_shift amt_ty amt))
-            (shifted_lo Xmm (psraw lo amt_))
-            (shifted_hi Xmm (psraw hi amt_)))
-        (packsswb shifted_lo shifted_hi)))
-
-(decl sshr_i8x16_bigger_shift (Type RegMemImm) XmmMemImm)
-(rule (sshr_i8x16_bigger_shift _ty (RegMemImm.Imm i))
-      (xmm_mem_imm_new (RegMemImm.Imm (u32_add i 8))))
-(rule (sshr_i8x16_bigger_shift ty (RegMemImm.Reg r))
-      (mov_rmi_to_xmm (RegMemImm.Reg (add ty
-                                          r
-                                          (RegMemImm.Imm 8)))))
-(rule (sshr_i8x16_bigger_shift ty rmi @ (RegMemImm.Mem _m))
-      (mov_rmi_to_xmm (RegMemImm.Reg (add ty
-                                          (imm ty 8)
-                                          rmi))))
-
-;; `sshr.{i16x8,i32x4}` can be a simple `psra{w,d}`, we just have to make sure
-;; that if the shift amount is in a register, it is in an XMM register.
-
-(rule (lower (has_type $I16X8 (sshr src amt)))
-      (psraw src (mov_rmi_to_xmm amt)))
-
-(rule (lower (has_type $I32X4 (sshr src amt)))
-      (psrad src (mov_rmi_to_xmm amt)))
-
-;; The `sshr.i64x2` CLIF instruction has no single x86 instruction in the older
-;; feature sets. Newer ones like AVX512VL + AVX512F include `vpsraq`, a 128-bit
-;; instruction that would fit here, but this backend does not currently have
-;; support for EVEX encodings. To remedy this, we extract each 64-bit lane to a
-;; GPR, shift each using a scalar instruction, and insert the shifted values
-;; back in the `dst` XMM register.
-;;
-;; (TODO: when EVEX support is available, add an alternate lowering here).
-(rule (lower (has_type $I64X2 (sshr src amt)))
-      (let ((src_ Xmm (put_in_xmm src))
-            (lo Gpr (pextrd $I64 src_ 0))
-            (hi Gpr (pextrd $I64 src_ 1))
-            (amt_ Imm8Gpr (put_masked_in_imm8_gpr amt $I64))
-            (shifted_lo Gpr (sar $I64 lo amt_))
-            (shifted_hi Gpr (sar $I64 hi amt_)))
-        (make_i64x2_from_lanes shifted_lo
-                               shifted_hi)))
-
-;;;; Rules for `rotl` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; `i16` and `i8`: we need to extend the shift amount, or mask the
-;; constant.
-
-(rule (lower (has_type (ty_8_or_16 ty) (rotl src amt)))
-      (let ((amt_ Gpr (extend_to_gpr amt $I32 (ExtendKind.Zero))))
-        (x64_rotl ty src (gpr_to_imm8_gpr amt_))))
-
-(rule (lower (has_type (ty_8_or_16 ty)
-                       (rotl src (u64_from_iconst amt))))
-      (x64_rotl ty src
-                (const_to_type_masked_imm8 amt ty)))
-
-;; `i64` and `i32`: we can rely on x86's rotate-amount masking since
-;;  we operate on the whole register.
-
-(rule (lower (has_type (ty_32_or_64 ty) (rotl src amt)))
-      ;; NB: Only the low bits of `amt` matter since we logically mask the
-      ;; shift amount to the value's bit width.
-      (let ((amt_ Gpr (lo_gpr amt)))
-        (x64_rotl ty src amt_)))
-
-(rule (lower (has_type (ty_32_or_64 ty)
-                       (rotl src (u64_from_iconst amt))))
-      (x64_rotl ty src
-                (const_to_type_masked_imm8 amt ty)))
-
-;; `i128`.
-
-(rule (lower (has_type $I128 (rotl src amt)))
-      (let ((src_ ValueRegs src)
-            ;; NB: Only the low bits of `amt` matter since we logically mask the
-            ;; rotation amount to the value's bit width.
-            (amt_ Gpr (lo_gpr amt)))
-        (or_i128 (shl_i128 src_ amt_)
-                 (shr_i128 src_ (sub $I64
-                                     (imm $I64 128)
-                                     amt_)))))
-
-;;;; Rules for `rotr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; `i16` and `i8`: we need to extend the shift amount, or mask the
-;; constant.
-
-(rule (lower (has_type (ty_8_or_16 ty) (rotr src amt)))
-      (let ((amt_ Gpr (extend_to_gpr amt $I32 (ExtendKind.Zero))))
-        (x64_rotr ty src amt_)))
-
-(rule (lower (has_type (ty_8_or_16 ty)
-                       (rotr src (u64_from_iconst amt))))
-      (x64_rotr ty src
-                (const_to_type_masked_imm8 amt ty)))
-
-;; `i64` and `i32`: we can rely on x86's rotate-amount masking since
-;;  we operate on the whole register.
-
-(rule (lower (has_type (ty_32_or_64 ty) (rotr src amt)))
-      ;; NB: Only the low bits of `amt` matter since we logically mask the
-      ;; shift amount to the value's bit width.
-      (let ((amt_ Gpr (lo_gpr amt)))
-        (x64_rotr ty src amt_)))
-
-(rule (lower (has_type (ty_32_or_64 ty)
-                       (rotr src (u64_from_iconst amt))))
-      (x64_rotr ty src
-                (const_to_type_masked_imm8 amt ty)))
-
-;; `i128`.
-
-(rule (lower (has_type $I128 (rotr src amt)))
-      (let ((src_ ValueRegs src)
-            ;; NB: Only the low bits of `amt` matter since we logically mask the
-            ;; rotation amount to the value's bit width.
-            (amt_ Gpr (lo_gpr amt)))
-        (or_i128 (shr_i128 src_ amt_)
-                 (shl_i128 src_ (sub $I64
-                                     (imm $I64 128)
-                                     amt_)))))
-
-;;;; Rules for `ineg` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; `i64` and smaller.
-
-(rule (lower (has_type (fits_in_64 ty) (ineg x)))
-      (neg ty x))
-
-;; SSE.
-
-(rule (lower (has_type $I8X16 (ineg x)))
-      (psubb (imm $I8X16 0) x))
-
-(rule (lower (has_type $I16X8 (ineg x)))
-      (psubw (imm $I16X8 0) x))
-
-(rule (lower (has_type $I32X4 (ineg x)))
-      (psubd (imm $I32X4 0) x))
-
-(rule (lower (has_type $I64X2 (ineg x)))
-      (psubq (imm $I64X2 0) x))
-
-;;;; Rules for `avg_round` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type (multi_lane 8 16)
-                       (avg_round x y)))
-      (pavgb x y))
-
-(rule (lower (has_type (multi_lane 16 8)
-                       (avg_round x y)))
-      (pavgw x y))
-
-;;;; Rules for `imul` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; `i64` and smaller.
-
-;; Multiply two registers.
-(rule (lower (has_type (fits_in_64 ty) (imul x y)))
-      (mul ty x y))
-
-;; Multiply a register and an immediate.
-
-(rule (lower (has_type (fits_in_64 ty)
-                       (imul x (simm32_from_value y))))
-      (mul ty x y))
-
-(rule (lower (has_type (fits_in_64 ty)
-                       (imul (simm32_from_value x) y)))
-      (mul ty y x))
-
-;; Multiply a register and a memory load.
-
-(rule (lower (has_type (fits_in_64 ty)
-                       (imul x (sinkable_load y))))
-      (mul ty
-           x
-           (sink_load_to_gpr_mem_imm y)))
-
-(rule (lower (has_type (fits_in_64 ty)
-                       (imul (sinkable_load x) y)))
-      (mul ty y
-           (sink_load_to_gpr_mem_imm x)))
-
-;; `i128`.
-
-;; mul:
-;;   dst_lo = lhs_lo * rhs_lo
-;;   dst_hi = umulhi(lhs_lo, rhs_lo) +
-;;            lhs_lo * rhs_hi +
-;;            lhs_hi * rhs_lo
-;;
-;; so we emit:
-;;   lo_hi = mul x_lo, y_hi
-;;   hi_lo = mul x_hi, y_lo
-;;   hilo_hilo = add lo_hi, hi_lo
-;;   dst_lo:hi_lolo = mulhi_u x_lo, y_lo
-;;   dst_hi = add hilo_hilo, hi_lolo
-;;   return (dst_lo, dst_hi)
-(rule (lower (has_type $I128 (imul x y)))
-      ;; Put `x` into registers and unpack its hi/lo halves.
-      (let ((x_regs ValueRegs x)
-            (x_lo Gpr (value_regs_get_gpr x_regs 0))
-            (x_hi Gpr (value_regs_get_gpr x_regs 1))
-            ;; Put `y` into registers and unpack its hi/lo halves.
-            (y_regs ValueRegs y)
-            (y_lo Gpr (value_regs_get_gpr y_regs 0))
-            (y_hi Gpr (value_regs_get_gpr y_regs 1))
-            ;; lo_hi = mul x_lo, y_hi
-            (lo_hi Gpr (mul $I64 x_lo y_hi))
-            ;; hi_lo = mul x_hi, y_lo
-            (hi_lo Gpr (mul $I64 x_hi y_lo))
-            ;; hilo_hilo = add lo_hi, hi_lo
-            (hilo_hilo Gpr (add $I64 lo_hi hi_lo))
-            ;; dst_lo:hi_lolo = mulhi_u x_lo, y_lo
-            (mul_regs ValueRegs (mulhi_u $I64 x_lo y_lo))
-            (dst_lo Gpr (value_regs_get_gpr mul_regs 0))
-            (hi_lolo Gpr (value_regs_get_gpr mul_regs 1))
-            ;; dst_hi = add hilo_hilo, hi_lolo
-            (dst_hi Gpr (add $I64 hilo_hilo hi_lolo)))
-        (value_gprs dst_lo dst_hi)))
-
-;; SSE.
-
-;; (No i8x16 multiply.)
-
-(rule (lower (has_type (multi_lane 16 8) (imul x y)))
-      (pmullw x y))
-
-(rule (lower (has_type (multi_lane 32 4) (imul x y)))
-      (pmulld x y))
-
-;; With AVX-512 we can implement `i64x2` multiplication with a single
-;; instruction.
-(rule (lower (has_type (and (avx512vl_enabled)
-                            (avx512dq_enabled)
-                            (multi_lane 64 2))
-                       (imul x y)))
-      (vpmullq x y))
-
-;; Otherwise, for i64x2 multiplication we describe a lane A as being composed of
-;; a 32-bit upper half "Ah" and a 32-bit lower half "Al". The 32-bit long hand
-;; multiplication can then be written as:
-;;
-;;    Ah Al
-;; *  Bh Bl
-;;    -----
-;;    Al * Bl
-;; + (Ah * Bl) << 32
-;; + (Al * Bh) << 32
-;;
-;; So for each lane we will compute:
-;;
-;;   A * B  = (Al * Bl) + ((Ah * Bl) + (Al * Bh)) << 32
-;;
-;; Note, the algorithm will use `pmuldq` which operates directly on the lower
-;; 32-bit (`Al` or `Bl`) of a lane and writes the result to the full 64-bits of
-;; the lane of the destination. For this reason we don't need shifts to isolate
-;; the lower 32-bits, however, we will need to use shifts to isolate the high
-;; 32-bits when doing calculations, i.e., `Ah == A >> 32`.
-(rule (lower (has_type (multi_lane 64 2)
-                       (imul a b)))
-      (let ((a0 Xmm a)
-            (b0 Xmm b)
-            ;; a_hi = A >> 32
-            (a_hi Xmm (psrlq a0 (RegMemImm.Imm 32)))
-            ;; ah_bl = Ah * Bl
-            (ah_bl Xmm (pmuludq a_hi b0))
-            ;; b_hi = B >> 32
-            (b_hi Xmm (psrlq b0 (RegMemImm.Imm 32)))
-            ;; al_bh = Al * Bh
-            (al_bh Xmm (pmuludq a0 b_hi))
-            ;; aa_bb = ah_bl + al_bh
-            (aa_bb Xmm (paddq ah_bl al_bh))
-            ;; aa_bb_shifted = aa_bb << 32
-            (aa_bb_shifted Xmm (psllq aa_bb (RegMemImm.Imm 32)))
-            ;; al_bl = Al * Bl
-            (al_bl Xmm (pmuludq a0 b0)))
-        ;; al_bl + aa_bb_shifted
-        (paddq al_bl aa_bb_shifted)))
-
-;; Special case for `i16x8.extmul_high_i8x16_s`.
-(rule (lower (has_type (multi_lane 16 8)
-                       (imul (swiden_high (and (value_type (multi_lane 8 16))
-                                               x))
-                             (swiden_high (and (value_type (multi_lane 8 16))
-                                               y)))))
-      (let ((x1 Xmm x)
-            (x2 Xmm (palignr x1 x1 8 (OperandSize.Size32)))
-            (x3 Xmm (pmovsxbw x2))
-            (y1 Xmm y)
-            (y2 Xmm (palignr y1 y1 8 (OperandSize.Size32)))
-            (y3 Xmm (pmovsxbw y2)))
-        (pmullw x3 y3)))
-
-;; Special case for `i32x4.extmul_high_i16x8_s`.
-(rule (lower (has_type (multi_lane 32 4)
-                       (imul (swiden_high (and (value_type (multi_lane 16 8))
-                                               x))
-                             (swiden_high (and (value_type (multi_lane 16 8))
-                                               y)))))
-      (let ((x2 Xmm x)
-            (y2 Xmm y)
-            (lo Xmm (pmullw x2 y2))
-            (hi Xmm (pmulhw x2 y2)))
-        (punpckhwd lo hi)))
-
-;; Special case for `i64x2.extmul_high_i32x4_s`.
-(rule (lower (has_type (multi_lane 64 2)
-                       (imul (swiden_high (and (value_type (multi_lane 32 4))
-                                               x))
-                             (swiden_high (and (value_type (multi_lane 32 4))
-                                               y)))))
-      (let ((x2 Xmm (pshufd x
-                            0xFA
-                            (OperandSize.Size32)))
-            (y2 Xmm (pshufd y
-                            0xFA
-                            (OperandSize.Size32))))
-        (pmuldq x2 y2)))
-
-;; Special case for `i16x8.extmul_low_i8x16_s`.
-(rule (lower (has_type (multi_lane 16 8)
-                       (imul (swiden_low (and (value_type (multi_lane 8 16))
-                                              x))
-                             (swiden_low (and (value_type (multi_lane 8 16))
-                                              y)))))
-      (let ((x2 Xmm (pmovsxbw x))
-            (y2 Xmm (pmovsxbw y)))
-        (pmullw x2 y2)))
-
-;; Special case for `i32x4.extmul_low_i16x8_s`.
-(rule (lower (has_type (multi_lane 32 4)
-                       (imul (swiden_low (and (value_type (multi_lane 16 8))
-                                              x))
-                             (swiden_low (and (value_type (multi_lane 16 8))
-                                              y)))))
-      (let ((x2 Xmm x)
-            (y2 Xmm y)
-            (lo Xmm (pmullw x2 y2))
-            (hi Xmm (pmulhw x2 y2)))
-        (punpcklwd lo hi)))
-
-;; Special case for `i64x2.extmul_low_i32x4_s`.
-(rule (lower (has_type (multi_lane 64 2)
-                       (imul (swiden_low (and (value_type (multi_lane 32 4))
-                                              x))
-                             (swiden_low (and (value_type (multi_lane 32 4))
-                                              y)))))
-      (let ((x2 Xmm (pshufd x
-                            0x50
-                            (OperandSize.Size32)))
-            (y2 Xmm (pshufd y
-                            0x50
-                            (OperandSize.Size32))))
-        (pmuldq x2 y2)))
-
-;; Special case for `i16x8.extmul_high_i8x16_u`.
-(rule (lower (has_type (multi_lane 16 8)
-                       (imul (uwiden_high (and (value_type (multi_lane 8 16))
-                                               x))
-                             (uwiden_high (and (value_type (multi_lane 8 16))
-                                               y)))))
-      (let ((x1 Xmm x)
-            (x2 Xmm (palignr x1 x1 8 (OperandSize.Size32)))
-            (x3 Xmm (pmovzxbw x2))
-            (y1 Xmm y)
-            (y2 Xmm (palignr y1 y1 8 (OperandSize.Size32)))
-            (y3 Xmm (pmovzxbw y2)))
-        (pmullw x3 y3)))
-
-;; Special case for `i32x4.extmul_high_i16x8_u`.
-(rule (lower (has_type (multi_lane 32 4)
-                       (imul (uwiden_high (and (value_type (multi_lane 16 8))
-                                               x))
-                             (uwiden_high (and (value_type (multi_lane 16 8))
-                                               y)))))
-      (let ((x2 Xmm x)
-            (y2 Xmm y)
-            (lo Xmm (pmullw x2 y2))
-            (hi Xmm (pmulhuw x2 y2)))
-        (punpckhwd lo hi)))
-
-;; Special case for `i64x2.extmul_high_i32x4_u`.
-(rule (lower (has_type (multi_lane 64 2)
-                       (imul (uwiden_high (and (value_type (multi_lane 32 4))
-                                               x))
-                             (uwiden_high (and (value_type (multi_lane 32 4))
-                                               y)))))
-      (let ((x2 Xmm (pshufd x
-                            0xFA
-                            (OperandSize.Size32)))
-            (y2 Xmm (pshufd y
-                            0xFA
-                            (OperandSize.Size32))))
-        (pmuludq x2 y2)))
-
-;; Special case for `i16x8.extmul_low_i8x16_u`.
-(rule (lower (has_type (multi_lane 16 8)
-                       (imul (uwiden_low (and (value_type (multi_lane 8 16))
-                                              x))
-                             (uwiden_low (and (value_type (multi_lane 8 16))
-                                              y)))))
-      (let ((x2 Xmm (pmovzxbw x))
-            (y2 Xmm (pmovzxbw y)))
-        (pmullw x2 y2)))
-
-;; Special case for `i32x4.extmul_low_i16x8_u`.
-(rule (lower (has_type (multi_lane 32 4)
-                       (imul (uwiden_low (and (value_type (multi_lane 16 8))
-                                              x))
-                             (uwiden_low (and (value_type (multi_lane 16 8))
-                                              y)))))
-      (let ((x2 Xmm x)
-            (y2 Xmm y)
-            (lo Xmm (pmullw x2 y2))
-            (hi Xmm (pmulhuw x2 y2)))
-        (punpcklwd lo hi)))
-
-;; Special case for `i64x2.extmul_low_i32x4_u`.
-(rule (lower (has_type (multi_lane 64 2)
-                       (imul (uwiden_low (and (value_type (multi_lane 32 4))
-                                              x))
-                             (uwiden_low (and (value_type (multi_lane 32 4))
-                                              y)))))
-      (let ((x2 Xmm (pshufd x
-                            0x50
-                            (OperandSize.Size32)))
-            (y2 Xmm (pshufd y
-                            0x50
-                            (OperandSize.Size32))))
-        (pmuludq x2 y2)))
-
-;;;; Rules for `band_not` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl sse_and_not (Type Xmm XmmMem) Xmm)
-(rule (sse_and_not $F32X4 x y) (andnps x y))
-(rule (sse_and_not $F64X2 x y) (andnpd x y))
-(rule (sse_and_not (multi_lane _bits _lanes) x y) (pandn x y))
-
-;; Note the flipping of operands below. CLIF specifies
-;;
-;;   band_not(x, y) = and(x, not(y))
-;;
-;; while x86 does
-;;
-;;   pandn(x, y) = and(not(x), y)
-(rule (lower (has_type ty (band_not x y)))
-      (sse_and_not ty y x))
-
-;;;; Rules for `iabs` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type $I8X16 (iabs x)))
-      (pabsb x))
-
-(rule (lower (has_type $I16X8 (iabs x)))
-      (pabsw x))
-
-(rule (lower (has_type $I32X4 (iabs x)))
-      (pabsd x))
-
-;; When AVX512 is available, we can use a single `vpabsq` instruction.
-(rule (lower (has_type (and (avx512vl_enabled)
-                            (avx512f_enabled)
-                            $I64X2)
-                       (iabs x)))
-      (vpabsq x))
-
-;; Otherwise, we use a separate register, `neg`, to contain the results of `0 -
-;; x` and then blend in those results with `blendvpd` if the MSB of `neg` was
-;; set to 1 (i.e. if `neg` was negative or, conversely, if `x` was originally
-;; positive).
-(rule (lower (has_type $I64X2 (iabs x)))
-      (let ((rx Xmm x)
-            (neg Xmm (psubq (imm $I64X2 0) rx)))
-        (blendvpd neg rx neg)))
-
-;;;; Rules for `fabs` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Special case for `f32x4.abs`.
-(rule (lower (has_type $F32X4 (fabs x)))
-      (andps x
-             (psrld (vector_all_ones $F32X4)
-                    (RegMemImm.Imm 1))))
-
-;; Special case for `f64x2.abs`.
-(rule (lower (has_type $F64X2 (fabs x)))
-      (andpd x
-             (psrlq (vector_all_ones $F64X2)
-                    (RegMemImm.Imm 1))))
-
-;;;; Rules for `bnot` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; `i64` and smaller.
-
-(rule (lower (has_type (fits_in_64 ty) (bnot x)))
-      (not ty x))
-
-;; `i128`.
-
-(decl i128_not (Value) ValueRegs)
-(rule (i128_not x)
-      (let ((x_regs ValueRegs x)
-            (x_lo Gpr (value_regs_get_gpr x_regs 0))
-            (x_hi Gpr (value_regs_get_gpr x_regs 1)))
-        (value_gprs (not $I64 x_lo)
-                    (not $I64 x_hi))))
-
-(rule (lower (has_type $I128 (bnot x)))
-      (i128_not x))
-
-(rule (lower (has_type $B128 (bnot x)))
-      (i128_not x))
-
-;; Special case for vector-types where bit-negation is an xor against an
-;; all-one value
-(rule (lower (has_type ty @ (multi_lane _bits _lanes) (bnot x)))
-      (sse_xor ty x (vector_all_ones ty)))
-
-;;;; Rules for `bitselect` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type ty @ (multi_lane _bits _lanes)
-                       (bitselect condition
-                                  if_true
-                                  if_false)))
-      ;; a = and if_true, condition
-      ;; b = and_not condition, if_false
-      ;; or b, a
-      (let ((cond_xmm Xmm condition)
-            (a Xmm (sse_and ty if_true cond_xmm))
-            (b Xmm (sse_and_not ty cond_xmm if_false)))
-        (sse_or ty b a)))
-
-;;;; Rules for `vselect` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type ty @ (multi_lane _bits _lanes)
-                       (vselect condition if_true if_false)))
-      (sse_blend ty
-                 condition
-                 if_true
-                 if_false))
-
-;;;; Rules for `insertlane` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (insertlane vec @ (value_type ty) val (u8_from_uimm8 idx)))
-      (vec_insert_lane ty vec val idx))
-
-;; Helper function used below for `insertlane` but also here for other
-;; lowerings.
-;;
-;; Note that the `Type` used here is the type of vector the insertion is
-;; happening into, or the type of the first `Reg` argument.
-(decl vec_insert_lane (Type Xmm RegMem u8) Xmm)
-
-;; i8x16.replace_lane
-(rule (vec_insert_lane $I8X16 vec val idx)
-      (pinsrb vec val idx))
-
-;; i16x8.replace_lane
-(rule (vec_insert_lane $I16X8 vec val idx)
-      (pinsrw vec val idx))
-
-;; i32x4.replace_lane
-(rule (vec_insert_lane $I32X4 vec val idx)
-      (pinsrd vec val idx (OperandSize.Size32)))
-
-;; i64x2.replace_lane
-(rule (vec_insert_lane $I64X2 vec val idx)
-      (pinsrd vec val idx (OperandSize.Size64)))
-
-;; f32x4.replace_lane
-(rule (vec_insert_lane $F32X4 vec val idx)
-      (insertps vec val (sse_insertps_lane_imm idx)))
-
-;; External rust code used to calculate the immediate value to `insertps`.
-(decl sse_insertps_lane_imm (u8) u8)
-(extern constructor sse_insertps_lane_imm sse_insertps_lane_imm)
-
-;; f64x2.replace_lane 0
-;;
-;; Here the `movsd` instruction is used specifically to specialize moving
-;; into the fist lane where unlike above cases we're not using the lane
-;; immediate as an immediate to the instruction itself.
-;;
-;; Note, though, the `movsd` has different behavior with respect to the second
-;; lane of the f64x2 depending on whether the RegMem operand is a register or
-;; memory. When loading from a register `movsd` preserves the upper bits, but
-;; when loading from memory it zeros the upper bits. We specifically want to
-;; preserve the upper bits so if a `RegMem.Mem` is passed in we need to emit
-;; two `movsd` instructions. The first `movsd` (used as `xmm_unary_rm_r`) will
-;; load from memory into a temp register and then the second `movsd` (modeled
-;; internally as `xmm_rm_r` will merge the temp register into our `vec`
-;; register.
-(rule (vec_insert_lane $F64X2 vec (RegMem.Reg val) 0)
-      (movsd vec val))
-(rule (vec_insert_lane $F64X2 vec mem 0)
-      (movsd vec (xmm_unary_rm_r (SseOpcode.Movsd)
-                                 mem)))
-
-;; f64x2.replace_lane 1
-;;
-;; Here the `movlhps` instruction is used specifically to specialize moving
-;; into the second lane where unlike above cases we're not using the lane
-;; immediate as an immediate to the instruction itself.
-(rule (vec_insert_lane $F64X2 vec val 1)
-      (movlhps vec (reg_mem_to_xmm_mem val)))
-
-;;;; Rules for `imin`, `imax`, `umin`, `umax` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; `i64` and smaller.
-
-(decl cmp_and_choose (Type CC Value Value) ValueRegs)
-(rule (cmp_and_choose (fits_in_64 ty) cc x y)
-      (let ((x_reg Gpr x)
-            (y_reg Gpr y)
-            (size OperandSize (raw_operand_size_of_type ty)))
-        (with_flags_reg (cmp size x_reg y_reg)
-                        (cmove ty cc y_reg x_reg))))
-
-(rule (lower (has_type (fits_in_64 ty) (umin x y)))
-      (cmp_and_choose ty (CC.B) x y))
-
-(rule (lower (has_type (fits_in_64 ty) (umax x y)))
-      (cmp_and_choose ty (CC.NB) x y))
-
-(rule (lower (has_type (fits_in_64 ty) (imin x y)))
-      (cmp_and_choose ty (CC.L) x y))
-
-(rule (lower (has_type (fits_in_64 ty) (imax x y)))
-      (cmp_and_choose ty (CC.NL) x y))
-
-;; SSE `imax`.
-
-(rule (lower (has_type $I8X16 (imax x y)))
-      (pmaxsb x y))
-
-(rule (lower (has_type $I16X8 (imax x y)))
-      (pmaxsw x y))
-
-(rule (lower (has_type $I32X4 (imax x y)))
-      (pmaxsd x y))
-
-;; SSE `imin`.
-
-(rule (lower (has_type $I8X16 (imin x y)))
-      (pminsb x y))
-
-(rule (lower (has_type $I16X8 (imin x y)))
-      (pminsw x y))
-
-(rule (lower (has_type $I32X4 (imin x y)))
-      (pminsd x y))
-
-;; SSE `umax`.
-
-(rule (lower (has_type $I8X16 (umax x y)))
-      (pmaxub x y))
-
-(rule (lower (has_type $I16X8 (umax x y)))
-      (pmaxuw x y))
-
-(rule (lower (has_type $I32X4 (umax x y)))
-      (pmaxud x y))
-
-;; SSE `umin`.
-
-(rule (lower (has_type $I8X16 (umin x y)))
-      (pminub x y))
-
-(rule (lower (has_type $I16X8 (umin x y)))
-      (pminuw x y))
-
-(rule (lower (has_type $I32X4 (umin x y)))
-      (pminud x y))
-
-;;;; Rules for `trap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (trap code))
-      (safepoint (ud2 code)))
-
-;;;; Rules for `resumable_trap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (resumable_trap code))
-      (safepoint (ud2 code)))
-
-;;;; Rules for `select` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; CLIF `select` instructions receive a testable argument (i.e. boolean or
-;; integer) that determines which of the other two arguments is selected as
-;; output. Since Cranelift booleans are typically generated by a comparison, the
-;; lowerings in this section "look upwards in the tree" to emit the proper
-;; sequence of "selection" instructions.
-;;
-;; The following rules--for selecting on a floating-point comparison--emit a
-;; `UCOMIS*` instruction and then a conditional move, `cmove`. Note that for
-;; values contained in XMM registers, `cmove` and `cmove_or` may in fact emit a
-;; jump sequence, not `CMOV`. The `cmove` instruction operates on the flags set
-;; by `UCOMIS*`; the key to understanding these is the UCOMIS* documentation
-;; (see Intel's Software Developer's Manual, volume 2, chapter 4):
-;;  - unordered assigns    Z = 1, P = 1, C = 1
-;;  - greater than assigns Z = 0, P = 0, C = 0
-;;  - less than assigns    Z = 0, P = 0, C = 1
-;;  - equal assigns        Z = 1, P = 0, C = 0
-;;
-;; Note that prefixing the flag with `N` means "not," so that `CC.P -> P = 1`
-;; and `CC.NP -> P = 0`. Also, x86 uses mnemonics for certain combinations of
-;; flags; e.g.:
-;;  - `CC.B -> C = 1` (below)
-;;  - `CC.NB -> C = 0` (not below)
-;;  - `CC.BE -> C = 1 OR Z = 1` (below or equal)
-;;  - `CC.NBE -> C = 0 AND Z = 0` (not below or equal)
-
-(rule (lower (has_type ty (select (fcmp (FloatCC.Ordered) a b) x y)))
-      (with_flags (fpcmp b a) (cmove_from_values ty (CC.NP) x y)))
-
-(rule (lower (has_type ty (select (fcmp (FloatCC.Unordered) a b) x y)))
-      (with_flags (fpcmp b a) (cmove_from_values ty (CC.P) x y)))
-
-(rule (lower (has_type ty (select (fcmp (FloatCC.GreaterThan) a b) x y)))
-      (with_flags (fpcmp b a) (cmove_from_values ty (CC.NBE) x y)))
-
-(rule (lower (has_type ty (select (fcmp (FloatCC.GreaterThanOrEqual) a b) x y)))
-      (with_flags (fpcmp b a) (cmove_from_values ty (CC.NB) x y)))
-
-(rule (lower (has_type ty (select (fcmp (FloatCC.UnorderedOrLessThan) a b) x y)))
-      (with_flags (fpcmp b a) (cmove_from_values ty (CC.B) x y)))
-
-(rule (lower (has_type ty (select (fcmp (FloatCC.UnorderedOrLessThanOrEqual) a b) x y)))
-      (with_flags (fpcmp b a) (cmove_from_values ty (CC.BE) x y)))
-
-;; Certain FloatCC variants are implemented by flipping the operands of the
-;; comparison (e.g., "greater than" is lowered the same as "less than" but the
-;; comparison is reversed). This allows us to use a single flag for the `cmove`,
-;; which involves fewer instructions than `cmove_or`.
-;;
-;; But why flip at all, you may ask? Can't we just use `CC.B` (i.e., below) for
-;; `FloatCC.LessThan`? Recall that in these floating-point lowerings, values may
-;; be unordered and we must we want to express that `FloatCC.LessThan` is `LT`,
-;; not `LT | UNO`. By flipping the operands AND inverting the comparison (e.g.,
-;; to `CC.NBE`), we also avoid these unordered cases.
-
-(rule (lower (has_type ty (select (fcmp (FloatCC.LessThan) a b) x y)))
-      (with_flags (fpcmp a b) (cmove_from_values ty (CC.NBE) x y)))
-
-(rule (lower (has_type ty (select (fcmp (FloatCC.LessThanOrEqual) a b) x y)))
-      (with_flags (fpcmp a b) (cmove_from_values ty (CC.NB) x y)))
-
-(rule (lower (has_type ty (select (fcmp (FloatCC.UnorderedOrGreaterThan) a b) x y)))
-      (with_flags (fpcmp a b) (cmove_from_values ty (CC.B) x y)))
-
-(rule (lower (has_type ty (select (fcmp (FloatCC.UnorderedOrGreaterThanOrEqual) a b) x y)))
-      (with_flags (fpcmp a b) (cmove_from_values ty (CC.BE) x y)))
-
-;; `FloatCC.Equal` and `FloatCC.NotEqual` can only be implemented with multiple
-;; flag checks. Recall from the flag assignment chart above that equality, e.g.,
-;; will assign `Z = 1`. But so does an unordered comparison: `Z = 1, P = 1, C =
-;; 1`. In order to avoid semantics like `EQ | UNO` for equality, we must ensure
-;; that the values are actually ordered, checking that `P = 0` (note that the
-;; `C` flag is irrelevant here). Since we cannot find a single instruction that
-;; implements a `Z = 1 AND P = 0` check, we invert the flag checks (i.e., `Z = 1
-;; AND P = 0` becomes `Z = 0 OR P = 1`) and also flip the select operands, `x`
-;; and `y`. The same argument applies to `FloatCC.NotEqual`.
-;;
-;; More details about the CLIF semantics for `fcmp` are available at
-;; https://docs.rs/cranelift-codegen/latest/cranelift_codegen/ir/trait.InstBuilder.html#method.fcmp.
-
-(rule (lower (has_type ty (select (fcmp (FloatCC.Equal) a b) x y)))
-      (with_flags (fpcmp a b) (cmove_or_from_values ty (CC.NZ) (CC.P) y x)))
-
-(rule (lower (has_type ty (select (fcmp (FloatCC.NotEqual) a b) x y)))
-      (with_flags (fpcmp a b) (cmove_or_from_values ty (CC.NZ) (CC.P) x y)))
-
-;; Rules for `clz` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; If available, we can use a plain lzcnt instruction here. Note no
-;; special handling is required for zero inputs, because the machine
-;; instruction does what the CLIF expects for zero, i.e. it returns
-;; zero.
-(rule 1 (lower
-         (has_type (and
-                    (ty_32_or_64 ty)
-                    (use_lzcnt))
-                   (clz src)))
-      (lzcnt ty src))
-
-(rule (lower
-       (has_type (ty_32_or_64 ty)
-                 (clz src)))
-      (do_clz ty ty src))
-
-(rule (lower
-       (has_type (ty_8_or_16 ty)
-                 (clz src)))
-      (do_clz $I32 ty (extend_to_gpr src $I32 (ExtendKind.Zero))))
-
-(rule (lower
-       (has_type $I128
-                 (clz src)))
-      (let ((upper Gpr (do_clz $I64 $I64 (value_regs_get_gpr src 1)))
-            (lower Gpr (add $I64
-                            (do_clz $I64 $I64 (value_regs_get_gpr src 0))
-                            (RegMemImm.Imm 64)))
-            (result_lo Gpr
-              (with_flags_reg
-               (cmp_imm (OperandSize.Size64) 64 upper)
-               (cmove $I64 (CC.NZ) upper lower))))
-        (value_regs result_lo (imm $I64 0))))
-
-;; Implementation helper for clz; operates on 32 or 64-bit units.
-(decl do_clz (Type Type Gpr) Gpr)
-(rule (do_clz ty orig_ty src)
-      (let ((highest_bit_index Reg (bsr_or_else ty src (imm_i64 $I64 -1)))
-            (bits_minus_1 Reg (imm ty (u64_sub (ty_bits_u64 orig_ty) 1))))
-        (sub ty bits_minus_1 highest_bit_index)))
-
-;; Rules for `ctz` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Analogous to `clz` cases above, but using mirror instructions
-;; (tzcnt vs lzcnt, bsf vs bsr).
-
-(rule 1 (lower
-         (has_type (and
-                    (ty_32_or_64 ty)
-                    (use_bmi1))
-                   (ctz src)))
-      (tzcnt ty src))
-
-(rule (lower
-       (has_type (ty_32_or_64 ty)
-                 (ctz src)))
-      (do_ctz ty ty src))
-
-(rule (lower
-       (has_type (ty_8_or_16 ty)
-                 (ctz src)))
-      (do_ctz $I32 ty (extend_to_gpr src $I32 (ExtendKind.Zero))))
-
-(rule (lower
-       (has_type $I128
-                 (ctz src)))
-      (let ((lower Gpr (do_ctz $I64 $I64 (value_regs_get_gpr src 0)))
-            (upper Gpr (add $I64
-                            (do_ctz $I64 $I64 (value_regs_get_gpr src 1))
-                            (RegMemImm.Imm 64)))
-            (result_lo Gpr
-              (with_flags_reg
-               (cmp_imm (OperandSize.Size64) 64 lower)
-               (cmove $I64 (CC.Z) upper lower))))
-        (value_regs result_lo (imm $I64 0))))
-
-(decl do_ctz (Type Type Gpr) Gpr)
-(rule (do_ctz ty orig_ty src)
-      (bsf_or_else ty src (imm $I64 (ty_bits_u64 orig_ty))))
-
-;; Rules for `popcnt` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule 1 (lower
-         (has_type (and
-                    (ty_32_or_64 ty)
-                    (use_popcnt))
-                   (popcnt src)))
-      (x64_popcnt ty src))
-
-(rule 1 (lower
-         (has_type (and
-                    (ty_8_or_16 ty)
-                    (use_popcnt))
-                   (popcnt src)))
-      (x64_popcnt $I32 (extend_to_gpr src $I32 (ExtendKind.Zero))))
-
-(rule 1 (lower
-         (has_type (and
-                    $I128
-                    (use_popcnt))
-                   (popcnt src)))
-      (let ((lo_count Gpr (x64_popcnt $I64 (value_regs_get_gpr src 0)))
-            (hi_count Gpr (x64_popcnt $I64 (value_regs_get_gpr src 1))))
-        (value_regs (add $I64 lo_count hi_count) (imm $I64 0))))
-
-(rule (lower
-       (has_type (ty_32_or_64 ty)
-                 (popcnt src)))
-      (do_popcnt ty src))
-
-(rule (lower
-       (has_type (ty_8_or_16 ty)
-                 (popcnt src)))
-      (do_popcnt $I32 (extend_to_gpr src $I32 (ExtendKind.Zero))))
-
-(rule (lower
-       (has_type $I128
-                 (popcnt src)))
-      (let ((lo_count Gpr (do_popcnt $I64 (value_regs_get_gpr src 0)))
-            (hi_count Gpr (do_popcnt $I64 (value_regs_get_gpr src 1))))
-        (value_regs (add $I64 lo_count hi_count) (imm $I64 0))))
-
-;; Implementation of popcount when we don't nave a native popcount
-;; instruction.
-(decl do_popcnt (Type Gpr) Gpr)
-(rule (do_popcnt $I64 src)
-      (let ((shifted1 Gpr (shr $I64 src (Imm8Reg.Imm8 1)))
-            (sevens Gpr (imm $I64 0x7777777777777777))
-            (masked1 Gpr (x64_and $I64 shifted1 sevens))
-            ;; diff1 := src - ((src >> 1) & 0b0111_0111_0111...)
-            (diff1 Gpr (sub $I64 src masked1))
-            (shifted2 Gpr (shr $I64 masked1 (Imm8Reg.Imm8 1)))
-            (masked2 Gpr (x64_and $I64 shifted2 sevens))
-            ;; diff2 := diff1 - ((diff1 >> 1) & 0b0111_0111_0111...)
-            (diff2 Gpr (sub $I64 diff1 masked2))
-            (shifted3 Gpr (shr $I64 masked2 (Imm8Reg.Imm8 1)))
-            (masked3 Gpr (x64_and $I64 shifted3 sevens))
-            ;; diff3 := diff2 - ((diff2 >> 1) & 0b0111_0111_0111...)
-            ;;
-            ;; At this point, each nibble of diff3 is the popcount of
-            ;; that nibble. This works because at each step above, we
-            ;; are basically subtracting floor(value / 2) from the
-            ;; running value; the leftover remainder is 1 if the LSB
-            ;; was 1. After three steps, we have (nibble / 8) -- 0 or
-            ;; 1 for the MSB of the nibble -- plus three possible
-            ;; additions for the three other bits.
-            (diff3 Gpr (sub $I64 diff2 masked3))
-            ;; Add the two nibbles of each byte together.
-            (sum1 Gpr (add $I64
-                           (shr $I64 diff3 (Imm8Reg.Imm8 4))
-                           diff3))
-            ;; Mask the above sum to have the popcount for each byte
-            ;; in the lower nibble of that byte.
-            (ofof Gpr (imm $I64 0x0f0f0f0f0f0f0f0f))
-            (masked4 Gpr (x64_and $I64 sum1 ofof))
-            (ones Gpr (imm $I64 0x0101010101010101))
-            ;; Use a multiply to sum all of the bytes' popcounts into
-            ;; the top byte. Consider the binomial expansion for the
-            ;; top byte: it is the sum of the bytes (masked4 >> 56) *
-            ;; 0x01 + (masked4 >> 48) * 0x01 + (masked4 >> 40) * 0x01
-            ;; + ... + (masked4 >> 0).
-            (mul Gpr (mul $I64 masked4 ones))
-            ;; Now take that top byte and return it as the popcount.
-            (final Gpr (shr $I64 mul (Imm8Reg.Imm8 56))))
-        final))
-
-;; This is the 32-bit version of the above; the steps for each nibble
-;; are the same, we just use constants half as wide.
-(rule (do_popcnt $I32 src)
-      (let ((shifted1 Gpr (shr $I32 src (Imm8Reg.Imm8 1)))
-            (sevens Gpr (imm $I32 0x77777777))
-            (masked1 Gpr (x64_and $I32 shifted1 sevens))
-            (diff1 Gpr (sub $I32 src masked1))
-            (shifted2 Gpr (shr $I32 masked1 (Imm8Reg.Imm8 1)))
-            (masked2 Gpr (x64_and $I32 shifted2 sevens))
-            (diff2 Gpr (sub $I32 diff1 masked2))
-            (shifted3 Gpr (shr $I32 masked2 (Imm8Reg.Imm8 1)))
-            (masked3 Gpr (x64_and $I32 shifted3 sevens))
-            (diff3 Gpr (sub $I32 diff2 masked3))
-            (sum1 Gpr (add $I32
-                           (shr $I32 diff3 (Imm8Reg.Imm8 4))
-                           diff3))
-            (masked4 Gpr (x64_and $I32 sum1 (RegMemImm.Imm 0x0f0f0f0f)))
-            (mul Gpr (mul $I32 masked4 (RegMemImm.Imm 0x01010101)))
-            (final Gpr (shr $I32 mul (Imm8Reg.Imm8 24))))
-        final))
-                       
-            
-(rule 1 (lower (has_type (and
-                          $I8X16
-                          (avx512vl_enabled)
-                          (avx512bitalg_enabled))
-                         (popcnt src)))
-      (vpopcntb src))
-
-
-      
-;; For SSE 4.2 we use Mula's algorithm (https://arxiv.org/pdf/1611.07612.pdf):
-;;
-;; __m128i count_bytes ( __m128i v) {
-;;     __m128i lookup = _mm_setr_epi8(0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4);
-;;     __m128i low_mask = _mm_set1_epi8 (0x0f);
-;;     __m128i lo = _mm_and_si128 (v, low_mask);
-;;     __m128i hi = _mm_and_si128 (_mm_srli_epi16 (v, 4), low_mask);
-;;     __m128i cnt1 = _mm_shuffle_epi8 (lookup, lo);
-;;     __m128i cnt2 = _mm_shuffle_epi8 (lookup, hi);
-;;     return _mm_add_epi8 (cnt1, cnt2);
-;; }
-;;
-;; Details of the above algorithm can be found in the reference noted above, but the basics
-;; are to create a lookup table that pre populates the popcnt values for each number [0,15].
-;; The algorithm uses shifts to isolate 4 bit sections of the vector, pshufb as part of the
-;; lookup process, and adds together the results.
-;;
-;; __m128i lookup = _mm_setr_epi8(0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4);
-
-(decl popcount_4bit_table () VCodeConstant)  ;; bits-per-nibble table `lookup` above
-(extern constructor popcount_4bit_table popcount_4bit_table)
-
-(decl popcount_low_mask () VCodeConstant)    ;; mask for low nibbles: 0x0f * 16
-(extern constructor popcount_low_mask popcount_low_mask)
-
-(rule (lower (has_type $I8X16
-                       (popcnt src)))
-      (let ((nibble_table_const VCodeConstant (popcount_4bit_table))
-            (low_mask Xmm (xmm_load_const $I8X16 (popcount_low_mask)))
-            (low_nibbles Xmm (sse_and $I8X16 src low_mask))
-            ;; Note that this is a 16x8 shift, but that's OK; we mask
-            ;; off anything that traverses from one byte to the next
-            ;; with the low_mask below.
-            (shifted_src Xmm (psrlw src (RegMemImm.Imm 4)))
-            (high_nibbles Xmm (sse_and $I8X16 shifted_src low_mask))
-            (lookup Xmm (xmm_load_const $I8X16 (popcount_4bit_table)))
-            (bit_counts_low Xmm (pshufb lookup low_nibbles))
-            (bit_counts_high Xmm (pshufb lookup high_nibbles)))
-        (paddb bit_counts_low bit_counts_high)))
-
-;; Rules for `bitrev` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type $I8 (bitrev src)))
-      (do_bitrev8 $I32 src))
-
-(rule (lower (has_type $I16 (bitrev src)))
-      (do_bitrev16 $I32 src))
-
-(rule (lower (has_type $I32 (bitrev src)))
-      (do_bitrev32 $I32 src))
-
-(rule (lower (has_type $I64 (bitrev src)))
-      (do_bitrev64 $I64 src))
-
-(rule (lower (has_type $I128 (bitrev src)))
-      (value_regs
-       (do_bitrev64 $I64 (value_regs_get_gpr src 1))
-       (do_bitrev64 $I64 (value_regs_get_gpr src 0))))
-
-(decl do_bitrev8 (Type Gpr) Gpr)
-(rule (do_bitrev8 ty src)
-      (let ((tymask u64 (ty_mask ty))
-            (mask1 Gpr (imm ty (u64_and tymask 0x5555555555555555)))
-            (lo1 Gpr (x64_and ty src mask1))
-            (hi1 Gpr (x64_and ty (shr ty src (Imm8Reg.Imm8 1)) mask1))
-            (swap1 Gpr (or ty
-                           (shl ty lo1 (Imm8Reg.Imm8 1))
-                           hi1))
-            (mask2 Gpr (imm ty (u64_and tymask 0x3333333333333333)))
-            (lo2 Gpr (x64_and ty swap1 mask2))
-            (hi2 Gpr (x64_and ty (shr ty swap1 (Imm8Reg.Imm8 2)) mask2))
-            (swap2 Gpr (or ty
-                           (shl ty lo2 (Imm8Reg.Imm8 2))
-                           hi2))
-            (mask4 Gpr (imm ty (u64_and tymask 0x0f0f0f0f0f0f0f0f)))
-            (lo4 Gpr (x64_and ty swap2 mask4))
-            (hi4 Gpr (x64_and ty (shr ty swap2 (Imm8Reg.Imm8 4)) mask4))
-            (swap4 Gpr (or ty
-                           (shl ty lo4 (Imm8Reg.Imm8 4))
-                           hi4)))
-        swap4))
-                       
-(decl do_bitrev16 (Type Gpr) Gpr)
-(rule (do_bitrev16 ty src)
-      (let ((src_ Gpr (do_bitrev8 ty src))
-            (tymask u64 (ty_mask ty))
-            (mask8 Gpr (imm ty (u64_and tymask 0x00ff00ff00ff00ff)))
-            (lo8 Gpr (x64_and ty src_ mask8))
-            (hi8 Gpr (x64_and ty (shr ty src_ (Imm8Reg.Imm8 8)) mask8))
-            (swap8 Gpr (or ty
-                           (shl ty lo8 (Imm8Reg.Imm8 8))
-                           hi8)))
-        swap8))
-      
-(decl do_bitrev32 (Type Gpr) Gpr)
-(rule (do_bitrev32 ty src)
-      (let ((src_ Gpr (do_bitrev16 ty src))
-            (tymask u64 (ty_mask ty))
-            (mask16 Gpr (imm ty (u64_and tymask 0x0000ffff0000ffff)))
-            (lo16 Gpr (x64_and ty src_ mask16))
-            (hi16 Gpr (x64_and ty (shr ty src_ (Imm8Reg.Imm8 16)) mask16))
-            (swap16 Gpr (or ty
-                            (shl ty lo16 (Imm8Reg.Imm8 16))
-                            hi16)))
-        swap16))
-
-(decl do_bitrev64 (Type Gpr) Gpr)
-(rule (do_bitrev64 ty @ $I64 src)
-      (let ((src_ Gpr (do_bitrev32 ty src))
-            (mask32 Gpr (imm ty 0xffffffff))
-            (lo32 Gpr (x64_and ty src_ mask32))
-            (hi32 Gpr (shr ty src_ (Imm8Reg.Imm8 32)))
-            (swap32 Gpr (or ty
-                            (shl ty lo32 (Imm8Reg.Imm8 32))
-                            hi32)))
-        swap32))
-
-;; Rules for `is_null` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Null references are represented by the constant value `0`.
-(rule (lower (is_null src @ (value_type $R64)))
-      (with_flags
-       (cmp_imm (OperandSize.Size64) 0 src)
-       (setcc (CC.Z))))
-
-;; Rules for `is_invalid` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Null references are represented by the constant value `-1`.
-(rule (lower (is_invalid src @ (value_type $R64)))
-      (with_flags
-       (cmp_imm (OperandSize.Size64) 0xffffffff src)  ;; simm32 0xffff_ffff is sign-extended to -1.
-       (setcc (CC.Z))))
-
-
-;; Rules for `uextend` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; T -> T is a no-op.
-(rule (lower (has_type ty (uextend src @ (value_type =ty))))
-      src)
-
-;; I64 -> I128.
-(rule (lower (has_type $I128 (uextend src @ (value_type $I64))))
-      (value_regs src (imm $I64 0)))
-
-;; I{8,16,32} -> I128.
-(rule (lower (has_type $I128 (uextend src @ (value_type (fits_in_32 src_ty)))))
-      (value_regs (extend_to_gpr src $I64 (ExtendKind.Zero)) (imm $I64 0)))
-
-;; I{8,16,32} -> I64.
-(rule (lower (has_type $I64 (uextend src @ (value_type (fits_in_32 src_ty)))))
-      (extend_to_gpr src $I64 (ExtendKind.Zero)))
-
-;; I8 -> I{16,32}, I16 -> I32.
-(rule (lower (has_type (fits_in_32 dst_ty) (uextend src @ (value_type (fits_in_32 src_ty)))))
-      (extend_to_gpr src $I32 (ExtendKind.Zero)))
-
-;; I32 -> I64 with op that produces a zero-extended value in a register.
-;;
-;; As a particular x64 extra-pattern matching opportunity, all the ALU
-;; opcodes on 32-bits will zero-extend the upper 32-bits, so we can
-;; even not generate a zero-extended move in this case.
-;;
-;; (Note that we unfortunately can't factor out the
-;; insts-that-zero-upper-32 pattern into a separate extractor until we
-;; can write internal extractors with multiple rules; and we'd rather
-;; keep these here than write an external extractor containing bits of
-;; the instruction pattern.s)
-(rule (lower (has_type $I64
-                       (uextend src @ (has_type $I32 (iadd _ _)))))
-      src)
-(rule (lower (has_type $I64
-                       (uextend src @ (has_type $I32 (iadd_ifcout _ _)))))
-      src)
-(rule (lower (has_type $I64
-                       (uextend src @ (has_type $I32 (isub _ _)))))
-      src)
-(rule (lower (has_type $I64
-                       (uextend src @ (has_type $I32 (imul _ _)))))
-      src)
-(rule (lower (has_type $I64
-                       (uextend src @ (has_type $I32 (band _ _)))))
-      src)
-(rule (lower (has_type $I64
-                       (uextend src @ (has_type $I32 (bor _ _)))))
-      src)
-(rule (lower (has_type $I64
-                       (uextend src @ (has_type $I32 (bxor _ _)))))
-      src)
-(rule (lower (has_type $I64
-                       (uextend src @ (has_type $I32 (ishl _ _)))))
-      src)
-(rule (lower (has_type $I64
-                       (uextend src @ (has_type $I32 (ushr _ _)))))
-      src)
-(rule (lower (has_type $I64
-                       (uextend src @ (has_type $I32 (uload32 _ _ _)))))
-      src)
-
-;; Rules for `sextend` / `bextend` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl generic_sextend (Value Type Type) InstOutput)
-
-;; T -> T is a no-op.
-(rule (generic_sextend src ty =ty)
-      src)
-
-;; Produce upper 64 bits sign-extended from lower 64: shift right by
-;; 63 bits to spread the sign bit across the result.
-(decl spread_sign_bit (Gpr) Gpr)
-(rule (spread_sign_bit src)
-      (sar $I64 src (Imm8Reg.Imm8 63)))
-
-;; I64 -> I128.
-(rule (generic_sextend src (ty_int_bool_64 _) (ty_int_bool_128 _))
-      (value_regs src (spread_sign_bit src)))
-
-;; I{8,16,32} -> I128.
-(rule (generic_sextend src (fits_in_32 src_ty) (ty_int_bool_128 _))
-      (let ((lo Gpr (extend_to_gpr src $I64 (ExtendKind.Sign)))
-            (hi Gpr (spread_sign_bit lo)))
-      (value_regs lo hi)))
-
-;; I{8,16,32} -> I64.
-(rule (generic_sextend src (fits_in_32 src_ty) (ty_int_bool_64 _))
-      (extend_to_gpr src $I64 (ExtendKind.Sign)))
-
-;; I8 -> I{16,32}, I16 -> I32.
-(rule (generic_sextend src (fits_in_32 src_ty) (fits_in_32 dst_ty))
-      (extend_to_gpr src $I32 (ExtendKind.Sign)))
-
-(rule (lower
-       (has_type dst_ty
-                 (sextend src @ (value_type src_ty))))
-      (generic_sextend src src_ty dst_ty))
-
-;; Bools are stored as 0/-1 so extends must sign-extend as well.
-(rule (lower
-       (has_type dst_ty
-                 (bextend src @ (value_type src_ty))))
-      (generic_sextend src src_ty dst_ty))
-
-;; Rules for `ireduce` / `breduce` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; T -> T is always a no-op, even I128 -> I128.
-(rule (lower (has_type ty (ireduce src @ (value_type =ty))))
-      src)
-
-;; T -> I{64,32,16,8}: We can simply pass through the value: values
-;; are always stored with high bits undefined, so we can just leave
-;; them be.
-(rule (lower (has_type (fits_in_64 ty) (ireduce src)))
-      (value_regs_get_gpr src 0))
-
-;; Likewise for breduce.
-
-(rule (lower (has_type ty (breduce src @ (value_type =ty))))
-      src)
-
-(rule (lower (has_type (fits_in_64 ty) (breduce src)))
-      (value_regs_get_gpr src 0))
-
-;; Rules for `bint` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Booleans are stored as all-zeroes (0) or all-ones (-1). We AND out
-;; the LSB to give a 0 / 1-valued integer result.
-
-(rule (lower (has_type (fits_in_64 ty)
-                       (bint src)))
-      (x64_and ty src (RegMemImm.Imm 1)))
-(rule (lower (has_type $I128
-                       (bint src)))
-      (value_regs
-       (x64_and $I64 src (RegMemImm.Imm 1))
-       (imm $I64 0)))
-
-;; Rules for `debugtrap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (debugtrap))
-      (side_effect (hlt)))
-
-;; Rules for `widening_pairwise_dot_product_s` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type $I32X4
-                       (widening_pairwise_dot_product_s x y)))
-      (pmaddwd x y))
-
-;; Rules for `fadd` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; N.B.: there are no load-op merging rules here. We can't guarantee
-;; the RHS (if a load) is 128-bit aligned, so we must avoid merging a
-;; load. Likewise for other ops below.
-
-(rule (lower (has_type $F32 (fadd x y)))
-      (addss x y))
-(rule (lower (has_type $F64 (fadd x y)))
-      (addsd x y))
-(rule (lower (has_type $F32X4 (fadd x y)))
-      (addps x y))
-(rule (lower (has_type $F64X2 (fadd x y)))
-      (addpd x y))
-
-;; Rules for `fsub` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type $F32 (fsub x y)))
-      (subss x y))
-(rule (lower (has_type $F64 (fsub x y)))
-      (subsd x y))
-(rule (lower (has_type $F32X4 (fsub x y)))
-      (subps x y))
-(rule (lower (has_type $F64X2 (fsub x y)))
-      (subpd x y))
-
-;; Rules for `fmul` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type $F32 (fmul x y)))
-      (mulss x y))
-(rule (lower (has_type $F64 (fmul x y)))
-      (mulsd x y))
-(rule (lower (has_type $F32X4 (fmul x y)))
-      (mulps x y))
-(rule (lower (has_type $F64X2 (fmul x y)))
-      (mulpd x y))
-
-;; Rules for `fdiv` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type $F32 (fdiv x y)))
-      (divss x y))
-(rule (lower (has_type $F64 (fdiv x y)))
-      (divsd x y))
-(rule (lower (has_type $F32X4 (fdiv x y)))
-      (divps x y))
-(rule (lower (has_type $F64X2 (fdiv x y)))
-      (divpd x y))
-
-;; Rules for `fmin` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type $F32 (fmin x y)))
-      (xmm_min_max_seq $F32 $true x y))
-(rule (lower (has_type $F64 (fmin x y)))
-      (xmm_min_max_seq $F64 $true x y))
-
-;; Vector-typed version. We don't use single pseudoinstructions as
-;; above, because we don't need to generate a mini-CFG. Instead, we
-;; perform a branchless series of operations.
-;;
-;; We cannot simply use native min instructions (minps, minpd) because
-;; NaN handling is different per CLIF semantics than on
-;; x86. Specifically, if an argument is NaN, or the arguments are both
-;; zero but of opposite signs, then the x86 instruction always
-;; produces the second argument. However, per CLIF semantics, we
-;; require that fmin(NaN, _) = fmin(_, NaN) = NaN, and fmin(+0, -0) =
-;; fmin(-0, +0) = -0.
-
-(rule (lower (has_type $F32X4 (fmin x y)))
-      ;; Compute min(x, y) and min(y, x) with native
-      ;; instructions. These will differ in one of the edge cases
-      ;; above that we have to handle properly. (Conversely, if they
-      ;; don't differ, then the native instruction's answer is the
-      ;; right one per CLIF semantics.)
-      (let ((min1 Xmm (minps x y))
-            (min2 Xmm (minps y x))
-            ;; Compute the OR of the two. Note that NaNs have an
-            ;; exponent field of all-ones (0xFF for F32), so if either
-            ;; result is a NaN, this OR will be. And if either is a
-            ;; zero (which has an exponent of 0 and mantissa of 0),
-            ;; this captures a sign-bit of 1 (negative) if either
-            ;; input is negative.
-            ;;
-            ;; In the case where we don't have a +/-0 mismatch or
-            ;; NaNs, then `min1` and `min2` are equal and `min_or` is
-            ;; the correct minimum.
-            (min_or Xmm (orps min1 min2))
-            ;; "compare unordered" produces a true mask (all ones) in
-            ;; a given lane if the min is a NaN. We use this to
-            ;; generate a mask to ensure quiet NaNs.
-            (is_nan_mask Xmm (cmpps min_or min2 (FcmpImm.Unordered)))
-            ;; OR in the NaN mask.
-            (min_or_2 Xmm (orps min_or is_nan_mask))
-            ;; Shift the NaN mask down so that it covers just the
-            ;; fraction below the NaN signalling bit; we'll use this
-            ;; to mask off non-canonical NaN payloads.
-            ;;
-            ;; All-ones for NaN, shifted down to leave 10 top bits (1
-            ;; sign, 8 exponent, 1 QNaN bit that must remain set)
-            ;; cleared.
-            (nan_fraction_mask Xmm (psrld is_nan_mask (RegMemImm.Imm 10)))
-            ;; Do a NAND, so that we retain every bit not set in
-            ;; `nan_fraction_mask`. This mask will be all zeroes (so
-            ;; we retain every bit) in non-NaN cases, and will have
-            ;; ones (so we clear those bits) in NaN-payload bits
-            ;; otherwise.
-            (final Xmm (andnps nan_fraction_mask min_or_2)))
-        final))
-
-;; Likewise for F64 lanes, except that the right-shift is by 13 bits
-;; (1 sign, 11 exponent, 1 QNaN bit).
-(rule (lower (has_type $F64X2 (fmin x y)))
-      (let ((min1 Xmm (minpd x y))
-            (min2 Xmm (minpd y x))
-            (min_or Xmm (orpd min1 min2))
-            (is_nan_mask Xmm (cmppd min1 min2 (FcmpImm.Unordered)))
-            (min_or_2 Xmm (orpd min_or is_nan_mask))
-            (nan_fraction_mask Xmm (psrlq is_nan_mask (RegMemImm.Imm 13)))
-            (final Xmm (andnpd nan_fraction_mask min_or_2)))
-        final))
-
-;; Rules for `fmax` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type $F32 (fmax x y)))
-      (xmm_min_max_seq $F32 $false x y))
-(rule (lower (has_type $F64 (fmax x y)))
-      (xmm_min_max_seq $F64 $false x y))
-
-;; The vector version of fmax here is a dual to the fmin sequence
-;; above, almost, with a few differences.
-
-(rule (lower (has_type $F32X4 (fmax x y)))
-      ;; Compute max(x, y) and max(y, x) with native
-      ;; instructions. These will differ in one of the edge cases
-      ;; above that we have to handle properly. (Conversely, if they
-      ;; don't differ, then the native instruction's answer is the
-      ;; right one per CLIF semantics.)
-      (let ((max1 Xmm (maxps x y))
-            (max2 Xmm (maxps y x))
-            ;; Compute the XOR of the two maxima. In the case
-            ;; where we don't have a +/-0 mismatch or NaNs, then
-            ;; `min1` and `min2` are equal and this XOR is zero.
-            (max_xor Xmm (xorps max1 max2))
-            ;; OR the XOR into one of the original maxima. If they are
-            ;; equal, this does nothing. If max2 was NaN, its exponent
-            ;; bits were all-ones, so the xor's exponent bits were the
-            ;; complement of max1, and the OR of max1 and max_xor has
-            ;; an all-ones exponent (is a NaN). If max1 was NaN, then
-            ;; its exponent bits were already all-ones, so the OR will
-            ;; be a NaN as well.
-            (max_blended_nan Xmm (orps max1 max_xor))
-            ;; Subtract the XOR. This ensures that if we had +0 and
-            ;; -0, we end up with +0.
-            (max_blended_nan_positive Xmm (subps max_blended_nan max_xor))
-            ;; "compare unordered" produces a true mask (all ones) in
-            ;; a given lane if the min is a NaN. We use this to
-            ;; generate a mask to ensure quiet NaNs.
-            (is_nan_mask Xmm (cmpps max_blended_nan max_blended_nan (FcmpImm.Unordered)))
-            ;; Shift the NaN mask down so that it covers just the
-            ;; fraction below the NaN signalling bit; we'll use this
-            ;; to mask off non-canonical NaN payloads.
-            ;;
-            ;; All-ones for NaN, shifted down to leave 10 top bits (1
-            ;; sign, 8 exponent, 1 QNaN bit that must remain set)
-            ;; cleared.
-            (nan_fraction_mask Xmm (psrld is_nan_mask (RegMemImm.Imm 10)))
-            ;; Do a NAND, so that we retain every bit not set in
-            ;; `nan_fraction_mask`. This mask will be all zeroes (so
-            ;; we retain every bit) in non-NaN cases, and will have
-            ;; ones (so we clear those bits) in NaN-payload bits
-            ;; otherwise.
-            (final Xmm (andnps nan_fraction_mask max_blended_nan_positive)))
-        final))
-
-(rule (lower (has_type $F64X2 (fmax x y)))
-      ;; Compute max(x, y) and max(y, x) with native
-      ;; instructions. These will differ in one of the edge cases
-      ;; above that we have to handle properly. (Conversely, if they
-      ;; don't differ, then the native instruction's answer is the
-      ;; right one per CLIF semantics.)
-      (let ((max1 Xmm (maxpd x y))
-            (max2 Xmm (maxpd y x))
-            ;; Compute the XOR of the two maxima. In the case
-            ;; where we don't have a +/-0 mismatch or NaNs, then
-            ;; `min1` and `min2` are equal and this XOR is zero.
-            (max_xor Xmm (xorpd max1 max2))
-            ;; OR the XOR into one of the original maxima. If they are
-            ;; equal, this does nothing. If max2 was NaN, its exponent
-            ;; bits were all-ones, so the xor's exponent bits were the
-            ;; complement of max1, and the OR of max1 and max_xor has
-            ;; an all-ones exponent (is a NaN). If max1 was NaN, then
-            ;; its exponent bits were already all-ones, so the OR will
-            ;; be a NaN as well.
-            (max_blended_nan Xmm (orpd max1 max_xor))
-            ;; Subtract the XOR. This ensures that if we had +0 and
-            ;; -0, we end up with +0.
-            (max_blended_nan_positive Xmm (subpd max_blended_nan max_xor))
-            ;; `cmpps` with predicate index `3` is `cmpunordps`, or
-            ;; "compare unordered": it produces a true mask (all ones)
-            ;; in a given lane if the min is a NaN. We use this to
-            ;; generate a mask to ensure quiet NaNs.
-            (is_nan_mask Xmm (cmppd max_blended_nan max_blended_nan (FcmpImm.Unordered)))
-            ;; Shift the NaN mask down so that it covers just the
-            ;; fraction below the NaN signalling bit; we'll use this
-            ;; to mask off non-canonical NaN payloads.
-            ;;
-            ;; All-ones for NaN, shifted down to leave 13 top bits (1
-            ;; sign, 11 exponent, 1 QNaN bit that must remain set)
-            ;; cleared.
-            (nan_fraction_mask Xmm (psrlq is_nan_mask (RegMemImm.Imm 13)))
-            ;; Do a NAND, so that we retain every bit not set in
-            ;; `nan_fraction_mask`. This mask will be all zeroes (so
-            ;; we retain every bit) in non-NaN cases, and will have
-            ;; ones (so we clear those bits) in NaN-payload bits
-            ;; otherwise.
-            (final Xmm (andnpd nan_fraction_mask max_blended_nan_positive)))
-        final))
-
-;; Rules for `fmin_pseudo` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type $F32 (fmin_pseudo x y)))
-      (minss y x))
-(rule (lower (has_type $F64 (fmin_pseudo x y)))
-      (minsd y x))
-(rule (lower (has_type $F32X4 (fmin_pseudo x y)))
-      (minps y x))
-(rule (lower (has_type $F64X2 (fmin_pseudo x y)))
-      (minpd y x))
-
-;; Rules for `fmax_pseudo` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(rule (lower (has_type $F32 (fmax_pseudo x y)))
-      (maxss y x))
-(rule (lower (has_type $F64 (fmax_pseudo x y)))
-      (maxsd y x))
-(rule (lower (has_type $F32X4 (fmax_pseudo x y)))
-      (maxps y x))
-(rule (lower (has_type $F64X2 (fmax_pseudo x y)))
-      (maxpd y x))
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/lower.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/lower.rs
deleted file mode 100644
index 39adcf85c..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/lower.rs
+++ /dev/null
@@ -1,4022 +0,0 @@
-//! Lowering rules for X64.
-
-// ISLE integration glue.
-pub(super) mod isle;
-
-use crate::data_value::DataValue;
-use crate::ir::{
-    condcodes::{CondCode, FloatCC, IntCC},
-    types, AbiParam, ArgumentPurpose, ExternalName, Inst as IRInst, InstructionData, LibCall,
-    Opcode, Signature, Type,
-};
-use crate::isa::x64::abi::*;
-use crate::isa::x64::inst::args::*;
-use crate::isa::x64::inst::*;
-use crate::isa::{x64::settings as x64_settings, x64::X64Backend, CallConv};
-use crate::machinst::lower::*;
-use crate::machinst::*;
-use crate::result::CodegenResult;
-use crate::settings::{Flags, TlsModel};
-use alloc::boxed::Box;
-use alloc::vec::Vec;
-use log::trace;
-use regalloc::{Reg, RegClass, Writable};
-use smallvec::SmallVec;
-use std::convert::TryFrom;
-use target_lexicon::Triple;
-
-//=============================================================================
-// Helpers for instruction lowering.
-
-fn is_int_or_ref_ty(ty: Type) -> bool {
-    match ty {
-        types::I8 | types::I16 | types::I32 | types::I64 | types::R64 => true,
-        types::B1 | types::B8 | types::B16 | types::B32 | types::B64 => true,
-        types::R32 => panic!("shouldn't have 32-bits refs on x64"),
-        _ => false,
-    }
-}
-
-fn is_bool_ty(ty: Type) -> bool {
-    match ty {
-        types::B1 | types::B8 | types::B16 | types::B32 | types::B64 => true,
-        types::R32 => panic!("shouldn't have 32-bits refs on x64"),
-        _ => false,
-    }
-}
-
-/// This is target-word-size dependent.  And it excludes booleans and reftypes.
-fn is_valid_atomic_transaction_ty(ty: Type) -> bool {
-    match ty {
-        types::I8 | types::I16 | types::I32 | types::I64 => true,
-        _ => false,
-    }
-}
-
-/// Returns whether the given specified `input` is a result produced by an instruction with Opcode
-/// `op`.
-// TODO investigate failures with checking against the result index.
-fn matches_input<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    input: InsnInput,
-    op: Opcode,
-) -> Option<IRInst> {
-    let inputs = ctx.get_input_as_source_or_const(input.insn, input.input);
-    inputs.inst.and_then(|(src_inst, _)| {
-        let data = ctx.data(src_inst);
-        if data.opcode() == op {
-            return Some(src_inst);
-        }
-        None
-    })
-}
-
-/// Emits instruction(s) to generate the given 64-bit constant value into a newly-allocated
-/// temporary register, returning that register.
-fn generate_constant<C: LowerCtx<I = Inst>>(ctx: &mut C, ty: Type, c: u64) -> ValueRegs<Reg> {
-    let from_bits = ty_bits(ty);
-    let masked = if from_bits < 64 {
-        c & ((1u64 << from_bits) - 1)
-    } else {
-        c
-    };
-
-    let cst_copy = ctx.alloc_tmp(ty);
-    for inst in Inst::gen_constant(cst_copy, masked as u128, ty, |ty| {
-        ctx.alloc_tmp(ty).only_reg().unwrap()
-    })
-    .into_iter()
-    {
-        ctx.emit(inst);
-    }
-    non_writable_value_regs(cst_copy)
-}
-
-/// Put the given input into possibly multiple registers, and mark it as used (side-effect).
-fn put_input_in_regs<C: LowerCtx<I = Inst>>(ctx: &mut C, spec: InsnInput) -> ValueRegs<Reg> {
-    let ty = ctx.input_ty(spec.insn, spec.input);
-    let input = ctx.get_input_as_source_or_const(spec.insn, spec.input);
-
-    if let Some(c) = input.constant {
-        // Generate constants fresh at each use to minimize long-range register pressure.
-        generate_constant(ctx, ty, c)
-    } else {
-        ctx.put_input_in_regs(spec.insn, spec.input)
-    }
-}
-
-/// Put the given input into a register, and mark it as used (side-effect).
-fn put_input_in_reg<C: LowerCtx<I = Inst>>(ctx: &mut C, spec: InsnInput) -> Reg {
-    put_input_in_regs(ctx, spec)
-        .only_reg()
-        .expect("Multi-register value not expected")
-}
-
-/// Determines whether a load operation (indicated by `src_insn`) can be merged
-/// into the current lowering point. If so, returns the address-base source (as
-/// an `InsnInput`) and an offset from that address from which to perform the
-/// load.
-fn is_mergeable_load<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    src_insn: IRInst,
-) -> Option<(InsnInput, i32)> {
-    let insn_data = ctx.data(src_insn);
-    let inputs = ctx.num_inputs(src_insn);
-    if inputs != 1 {
-        return None;
-    }
-
-    let load_ty = ctx.output_ty(src_insn, 0);
-    if ty_bits(load_ty) < 32 {
-        // Narrower values are handled by ALU insts that are at least 32 bits
-        // wide, which is normally OK as we ignore upper buts; but, if we
-        // generate, e.g., a direct-from-memory 32-bit add for a byte value and
-        // the byte is the last byte in a page, the extra data that we load is
-        // incorrectly accessed. So we only allow loads to merge for
-        // 32-bit-and-above widths.
-        return None;
-    }
-
-    // SIMD instructions can only be load-coalesced when the loaded value comes
-    // from an aligned address.
-    if load_ty.is_vector() && !insn_data.memflags().map_or(false, |f| f.aligned()) {
-        return None;
-    }
-
-    // Just testing the opcode is enough, because the width will always match if
-    // the type does (and the type should match if the CLIF is properly
-    // constructed).
-    if insn_data.opcode() == Opcode::Load {
-        let offset = insn_data
-            .load_store_offset()
-            .expect("load should have offset");
-        Some((
-            InsnInput {
-                insn: src_insn,
-                input: 0,
-            },
-            offset,
-        ))
-    } else {
-        None
-    }
-}
-
-/// Put the given input into a register or a memory operand.
-/// Effectful: may mark the given input as used, when returning the register form.
-fn input_to_reg_mem<C: LowerCtx<I = Inst>>(ctx: &mut C, spec: InsnInput) -> RegMem {
-    let inputs = ctx.get_input_as_source_or_const(spec.insn, spec.input);
-
-    if let Some(c) = inputs.constant {
-        // Generate constants fresh at each use to minimize long-range register pressure.
-        let ty = ctx.input_ty(spec.insn, spec.input);
-        return RegMem::reg(generate_constant(ctx, ty, c).only_reg().unwrap());
-    }
-
-    if let Some((src_insn, 0)) = inputs.inst {
-        if let Some((addr_input, offset)) = is_mergeable_load(ctx, src_insn) {
-            ctx.sink_inst(src_insn);
-            let amode = lower_to_amode(ctx, addr_input, offset);
-            return RegMem::mem(amode);
-        }
-    }
-
-    RegMem::reg(
-        ctx.put_input_in_regs(spec.insn, spec.input)
-            .only_reg()
-            .unwrap(),
-    )
-}
-
-/// An extension specification for `extend_input_to_reg`.
-#[derive(Clone, Copy)]
-enum ExtSpec {
-    ZeroExtendTo32,
-    ZeroExtendTo64,
-    SignExtendTo32,
-    #[allow(dead_code)] // not used just yet but may be used in the future!
-    SignExtendTo64,
-}
-
-/// Put the given input into a register, marking it as used, and do a zero- or signed- extension if
-/// required. (This obviously causes side-effects.)
-fn extend_input_to_reg<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    spec: InsnInput,
-    ext_spec: ExtSpec,
-) -> Reg {
-    let requested_size = match ext_spec {
-        ExtSpec::ZeroExtendTo32 | ExtSpec::SignExtendTo32 => 32,
-        ExtSpec::ZeroExtendTo64 | ExtSpec::SignExtendTo64 => 64,
-    };
-    let input_size = ctx.input_ty(spec.insn, spec.input).bits();
-
-    let requested_ty = if requested_size == 32 {
-        types::I32
-    } else {
-        types::I64
-    };
-
-    let ext_mode = match (input_size, requested_size) {
-        (a, b) if a == b => return put_input_in_reg(ctx, spec),
-        (1, 8) => return put_input_in_reg(ctx, spec),
-        (a, b) => ExtMode::new(a, b).unwrap_or_else(|| panic!("invalid extension: {} -> {}", a, b)),
-    };
-
-    let src = input_to_reg_mem(ctx, spec);
-    let dst = ctx.alloc_tmp(requested_ty).only_reg().unwrap();
-    match ext_spec {
-        ExtSpec::ZeroExtendTo32 | ExtSpec::ZeroExtendTo64 => {
-            ctx.emit(Inst::movzx_rm_r(ext_mode, src, dst))
-        }
-        ExtSpec::SignExtendTo32 | ExtSpec::SignExtendTo64 => {
-            ctx.emit(Inst::movsx_rm_r(ext_mode, src, dst))
-        }
-    }
-    dst.to_reg()
-}
-
-/// Returns whether the given input is an immediate that can be properly sign-extended, without any
-/// possible side-effect.
-fn non_reg_input_to_sext_imm(input: NonRegInput, input_ty: Type) -> Option<u32> {
-    input.constant.and_then(|x| {
-        // For i64 instructions (prefixed with REX.W), require that the immediate will sign-extend
-        // to 64 bits. For other sizes, it doesn't matter and we can just use the plain
-        // constant.
-        if input_ty.bytes() != 8 || low32_will_sign_extend_to_64(x) {
-            Some(x as u32)
-        } else {
-            None
-        }
-    })
-}
-
-fn input_to_imm<C: LowerCtx<I = Inst>>(ctx: &mut C, spec: InsnInput) -> Option<u64> {
-    ctx.get_input_as_source_or_const(spec.insn, spec.input)
-        .constant
-}
-
-/// Put the given input into an immediate, a register or a memory operand.
-/// Effectful: may mark the given input as used, when returning the register form.
-fn input_to_reg_mem_imm<C: LowerCtx<I = Inst>>(ctx: &mut C, spec: InsnInput) -> RegMemImm {
-    let input = ctx.get_input_as_source_or_const(spec.insn, spec.input);
-    let input_ty = ctx.input_ty(spec.insn, spec.input);
-    match non_reg_input_to_sext_imm(input, input_ty) {
-        Some(x) => RegMemImm::imm(x),
-        None => match input_to_reg_mem(ctx, spec) {
-            RegMem::Reg { reg } => RegMemImm::reg(reg),
-            RegMem::Mem { addr } => RegMemImm::mem(addr),
-        },
-    }
-}
-
-/// Emit an instruction to insert a value `src` into a lane of `dst`.
-fn emit_insert_lane<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    src: RegMem,
-    dst: Writable<Reg>,
-    lane: u8,
-    ty: Type,
-) {
-    if !ty.is_float() {
-        let (sse_op, size) = match ty.lane_bits() {
-            8 => (SseOpcode::Pinsrb, OperandSize::Size32),
-            16 => (SseOpcode::Pinsrw, OperandSize::Size32),
-            32 => (SseOpcode::Pinsrd, OperandSize::Size32),
-            64 => (SseOpcode::Pinsrd, OperandSize::Size64),
-            _ => panic!("Unable to insertlane for lane size: {}", ty.lane_bits()),
-        };
-        ctx.emit(Inst::xmm_rm_r_imm(sse_op, src, dst, lane, size));
-    } else if ty == types::F32 {
-        let sse_op = SseOpcode::Insertps;
-        // Insert 32-bits from replacement (at index 00, bits 7:8) to vector (lane
-        // shifted into bits 5:6).
-        let lane = 0b00_00_00_00 | lane << 4;
-        ctx.emit(Inst::xmm_rm_r_imm(
-            sse_op,
-            src,
-            dst,
-            lane,
-            OperandSize::Size32,
-        ));
-    } else if ty == types::F64 {
-        let sse_op = match lane {
-            // Move the lowest quadword in replacement to vector without changing
-            // the upper bits.
-            0 => SseOpcode::Movsd,
-            // Move the low 64 bits of replacement vector to the high 64 bits of the
-            // vector.
-            1 => SseOpcode::Movlhps,
-            _ => unreachable!(),
-        };
-        // Here we use the `xmm_rm_r` encoding because it correctly tells the register
-        // allocator how we are using `dst`: we are using `dst` as a `mod` whereas other
-        // encoding formats like `xmm_unary_rm_r` treat it as a `def`.
-        ctx.emit(Inst::xmm_rm_r(sse_op, src, dst));
-    } else {
-        panic!("unable to emit insertlane for type: {}", ty)
-    }
-}
-
-/// Emit an instruction to extract a lane of `src` into `dst`.
-fn emit_extract_lane<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    src: Reg,
-    dst: Writable<Reg>,
-    lane: u8,
-    ty: Type,
-) {
-    if !ty.is_float() {
-        let (sse_op, size) = match ty.lane_bits() {
-            8 => (SseOpcode::Pextrb, OperandSize::Size32),
-            16 => (SseOpcode::Pextrw, OperandSize::Size32),
-            32 => (SseOpcode::Pextrd, OperandSize::Size32),
-            64 => (SseOpcode::Pextrd, OperandSize::Size64),
-            _ => panic!("Unable to extractlane for lane size: {}", ty.lane_bits()),
-        };
-        let src = RegMem::reg(src);
-        ctx.emit(Inst::xmm_rm_r_imm(sse_op, src, dst, lane, size));
-    } else if ty == types::F32 || ty == types::F64 {
-        if lane == 0 {
-            // Remove the extractlane instruction, leaving the float where it is. The upper
-            // bits will remain unchanged; for correctness, this relies on Cranelift type
-            // checking to avoid using those bits.
-            ctx.emit(Inst::gen_move(dst, src, ty));
-        } else {
-            // Otherwise, shuffle the bits in `lane` to the lowest lane.
-            let sse_op = SseOpcode::Pshufd;
-            let mask = match ty {
-                // Move the value at `lane` to lane 0, copying existing value at lane 0 to
-                // other lanes. Again, this relies on Cranelift type checking to avoid
-                // using those bits.
-                types::F32 => {
-                    assert!(lane > 0 && lane < 4);
-                    0b00_00_00_00 | lane
-                }
-                // Move the value at `lane` 1 (we know it must be 1 because of the `if`
-                // statement above) to lane 0 and leave lane 1 unchanged. The Cranelift type
-                // checking assumption also applies here.
-                types::F64 => {
-                    assert!(lane == 1);
-                    0b11_10_11_10
-                }
-                _ => unreachable!(),
-            };
-            let src = RegMem::reg(src);
-            ctx.emit(Inst::xmm_rm_r_imm(
-                sse_op,
-                src,
-                dst,
-                mask,
-                OperandSize::Size32,
-            ));
-        }
-    } else {
-        panic!("unable to emit extractlane for type: {}", ty)
-    }
-}
-
-/// Emits an int comparison instruction.
-///
-/// Note: make sure that there are no instructions modifying the flags between a call to this
-/// function and the use of the flags!
-///
-/// Takes the condition code that will be tested, and returns
-/// the condition code that should be used. This allows us to
-/// synthesize comparisons out of multiple instructions for
-/// special cases (e.g., 128-bit integers).
-fn emit_cmp<C: LowerCtx<I = Inst>>(ctx: &mut C, insn: IRInst, cc: IntCC) -> IntCC {
-    let ty = ctx.input_ty(insn, 0);
-
-    let inputs = [InsnInput { insn, input: 0 }, InsnInput { insn, input: 1 }];
-
-    if ty == types::I128 {
-        // We need to compare both halves and combine the results appropriately.
-        let cmp1 = ctx.alloc_tmp(types::I64).only_reg().unwrap();
-        let cmp2 = ctx.alloc_tmp(types::I64).only_reg().unwrap();
-        let lhs = put_input_in_regs(ctx, inputs[0]);
-        let lhs_lo = lhs.regs()[0];
-        let lhs_hi = lhs.regs()[1];
-        let rhs = put_input_in_regs(ctx, inputs[1]);
-        let rhs_lo = RegMemImm::reg(rhs.regs()[0]);
-        let rhs_hi = RegMemImm::reg(rhs.regs()[1]);
-        match cc {
-            IntCC::Equal => {
-                ctx.emit(Inst::cmp_rmi_r(OperandSize::Size64, rhs_hi, lhs_hi));
-                ctx.emit(Inst::setcc(CC::Z, cmp1));
-                ctx.emit(Inst::cmp_rmi_r(OperandSize::Size64, rhs_lo, lhs_lo));
-                ctx.emit(Inst::setcc(CC::Z, cmp2));
-                ctx.emit(Inst::alu_rmi_r(
-                    OperandSize::Size64,
-                    AluRmiROpcode::And,
-                    RegMemImm::reg(cmp1.to_reg()),
-                    cmp2,
-                ));
-                ctx.emit(Inst::alu_rmi_r(
-                    OperandSize::Size64,
-                    AluRmiROpcode::And,
-                    RegMemImm::imm(1),
-                    cmp2,
-                ));
-                IntCC::NotEqual
-            }
-            IntCC::NotEqual => {
-                ctx.emit(Inst::cmp_rmi_r(OperandSize::Size64, rhs_hi, lhs_hi));
-                ctx.emit(Inst::setcc(CC::NZ, cmp1));
-                ctx.emit(Inst::cmp_rmi_r(OperandSize::Size64, rhs_lo, lhs_lo));
-                ctx.emit(Inst::setcc(CC::NZ, cmp2));
-                ctx.emit(Inst::alu_rmi_r(
-                    OperandSize::Size64,
-                    AluRmiROpcode::Or,
-                    RegMemImm::reg(cmp1.to_reg()),
-                    cmp2,
-                ));
-                ctx.emit(Inst::alu_rmi_r(
-                    OperandSize::Size64,
-                    AluRmiROpcode::And,
-                    RegMemImm::imm(1),
-                    cmp2,
-                ));
-                IntCC::NotEqual
-            }
-            IntCC::SignedLessThan
-            | IntCC::SignedLessThanOrEqual
-            | IntCC::SignedGreaterThan
-            | IntCC::SignedGreaterThanOrEqual
-            | IntCC::UnsignedLessThan
-            | IntCC::UnsignedLessThanOrEqual
-            | IntCC::UnsignedGreaterThan
-            | IntCC::UnsignedGreaterThanOrEqual => {
-                // Result = (lhs_hi <> rhs_hi) ||
-                //          (lhs_hi == rhs_hi && lhs_lo <> rhs_lo)
-                let cmp3 = ctx.alloc_tmp(types::I64).only_reg().unwrap();
-                ctx.emit(Inst::cmp_rmi_r(OperandSize::Size64, rhs_hi, lhs_hi));
-                ctx.emit(Inst::setcc(CC::from_intcc(cc.without_equal()), cmp1));
-                ctx.emit(Inst::setcc(CC::Z, cmp2));
-                ctx.emit(Inst::cmp_rmi_r(OperandSize::Size64, rhs_lo, lhs_lo));
-                ctx.emit(Inst::setcc(CC::from_intcc(cc.unsigned()), cmp3));
-                ctx.emit(Inst::alu_rmi_r(
-                    OperandSize::Size64,
-                    AluRmiROpcode::And,
-                    RegMemImm::reg(cmp2.to_reg()),
-                    cmp3,
-                ));
-                ctx.emit(Inst::alu_rmi_r(
-                    OperandSize::Size64,
-                    AluRmiROpcode::Or,
-                    RegMemImm::reg(cmp1.to_reg()),
-                    cmp3,
-                ));
-                ctx.emit(Inst::alu_rmi_r(
-                    OperandSize::Size64,
-                    AluRmiROpcode::And,
-                    RegMemImm::imm(1),
-                    cmp3,
-                ));
-                IntCC::NotEqual
-            }
-            _ => panic!("Unhandled IntCC in I128 comparison: {:?}", cc),
-        }
-    } else {
-        // TODO Try to commute the operands (and invert the condition) if one is an immediate.
-        let lhs = put_input_in_reg(ctx, inputs[0]);
-        // We force the RHS into a register, and disallow load-op fusion, because we
-        // do not have a transitive guarantee that this cmp-site will be the sole
-        // user of the value. Consider: the icmp might be the only user of a load,
-        // but there may be multiple users of the icmp (e.g.  select or bint
-        // instructions) that each invoke `emit_cmp()`. If we were to allow a load
-        // to sink to the *latest* one, but other sites did not permit sinking, then
-        // we would be missing the load for other cmp-sites.
-        let rhs = put_input_in_reg(ctx, inputs[1]);
-
-        // Cranelift's icmp semantics want to compare lhs - rhs, while Intel gives
-        // us dst - src at the machine instruction level, so invert operands.
-        ctx.emit(Inst::cmp_rmi_r(
-            OperandSize::from_ty(ty),
-            RegMemImm::reg(rhs),
-            lhs,
-        ));
-        cc
-    }
-}
-
-/// A specification for a fcmp emission.
-enum FcmpSpec {
-    /// Normal flow.
-    Normal,
-
-    /// Avoid emitting Equal at all costs by inverting it to NotEqual, and indicate when that
-    /// happens with `InvertedEqualOrConditions`.
-    ///
-    /// This is useful in contexts where it is hard/inefficient to produce a single instruction (or
-    /// sequence of instructions) that check for an "AND" combination of condition codes; see for
-    /// instance lowering of Select.
-    #[allow(dead_code)]
-    InvertEqual,
-}
-
-/// This explains how to interpret the results of an fcmp instruction.
-enum FcmpCondResult {
-    /// The given condition code must be set.
-    Condition(CC),
-
-    /// Both condition codes must be set.
-    AndConditions(CC, CC),
-
-    /// Either of the conditions codes must be set.
-    OrConditions(CC, CC),
-
-    /// The associated spec was set to `FcmpSpec::InvertEqual` and Equal has been inverted. Either
-    /// of the condition codes must be set, and the user must invert meaning of analyzing the
-    /// condition code results. When the spec is set to `FcmpSpec::Normal`, then this case can't be
-    /// reached.
-    InvertedEqualOrConditions(CC, CC),
-}
-
-/// Emits a float comparison instruction.
-///
-/// Note: make sure that there are no instructions modifying the flags between a call to this
-/// function and the use of the flags!
-fn emit_fcmp<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    insn: IRInst,
-    mut cond_code: FloatCC,
-    spec: FcmpSpec,
-) -> FcmpCondResult {
-    let (flip_operands, inverted_equal) = match cond_code {
-        FloatCC::LessThan
-        | FloatCC::LessThanOrEqual
-        | FloatCC::UnorderedOrGreaterThan
-        | FloatCC::UnorderedOrGreaterThanOrEqual => {
-            cond_code = cond_code.reverse();
-            (true, false)
-        }
-        FloatCC::Equal => {
-            let inverted_equal = match spec {
-                FcmpSpec::Normal => false,
-                FcmpSpec::InvertEqual => {
-                    cond_code = FloatCC::NotEqual; // same as .inverse()
-                    true
-                }
-            };
-            (false, inverted_equal)
-        }
-        _ => (false, false),
-    };
-
-    // The only valid CC constructed with `from_floatcc` can be put in the flag
-    // register with a direct float comparison; do this here.
-    let op = match ctx.input_ty(insn, 0) {
-        types::F32 => SseOpcode::Ucomiss,
-        types::F64 => SseOpcode::Ucomisd,
-        _ => panic!("Bad input type to Fcmp"),
-    };
-
-    let inputs = &[InsnInput { insn, input: 0 }, InsnInput { insn, input: 1 }];
-    let (lhs_input, rhs_input) = if flip_operands {
-        (inputs[1], inputs[0])
-    } else {
-        (inputs[0], inputs[1])
-    };
-    let lhs = put_input_in_reg(ctx, lhs_input);
-    // See above in `emit_cmp()`. We must only use the reg/reg form of the
-    // comparison in order to avoid issues with merged loads.
-    let rhs = put_input_in_reg(ctx, rhs_input);
-    ctx.emit(Inst::xmm_cmp_rm_r(op, RegMem::reg(rhs), lhs));
-
-    let cond_result = match cond_code {
-        FloatCC::Equal => FcmpCondResult::AndConditions(CC::NP, CC::Z),
-        FloatCC::NotEqual if inverted_equal => {
-            FcmpCondResult::InvertedEqualOrConditions(CC::P, CC::NZ)
-        }
-        FloatCC::NotEqual if !inverted_equal => FcmpCondResult::OrConditions(CC::P, CC::NZ),
-        _ => FcmpCondResult::Condition(CC::from_floatcc(cond_code)),
-    };
-
-    cond_result
-}
-
-fn make_libcall_sig<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    insn: IRInst,
-    call_conv: CallConv,
-    ptr_ty: Type,
-) -> Signature {
-    let mut sig = Signature::new(call_conv);
-    for i in 0..ctx.num_inputs(insn) {
-        sig.params.push(AbiParam::new(ctx.input_ty(insn, i)));
-    }
-    for i in 0..ctx.num_outputs(insn) {
-        sig.returns.push(AbiParam::new(ctx.output_ty(insn, i)));
-    }
-    if call_conv.extends_baldrdash() {
-        // Adds the special VMContext parameter to the signature.
-        sig.params
-            .push(AbiParam::special(ptr_ty, ArgumentPurpose::VMContext));
-    }
-    sig
-}
-
-fn emit_vm_call<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    flags: &Flags,
-    triple: &Triple,
-    libcall: LibCall,
-    insn: IRInst,
-    inputs: SmallVec<[InsnInput; 4]>,
-    outputs: SmallVec<[InsnOutput; 2]>,
-) -> CodegenResult<()> {
-    let extname = ExternalName::LibCall(libcall);
-
-    let dist = if flags.use_colocated_libcalls() {
-        RelocDistance::Near
-    } else {
-        RelocDistance::Far
-    };
-
-    // TODO avoid recreating signatures for every single Libcall function.
-    let call_conv = CallConv::for_libcall(flags, CallConv::triple_default(triple));
-    let sig = make_libcall_sig(ctx, insn, call_conv, types::I64);
-    let caller_conv = ctx.abi().call_conv();
-
-    let mut abi = X64ABICaller::from_func(&sig, &extname, dist, caller_conv, flags)?;
-
-    abi.emit_stack_pre_adjust(ctx);
-
-    let vm_context = if call_conv.extends_baldrdash() { 1 } else { 0 };
-    assert_eq!(inputs.len() + vm_context, abi.num_args());
-
-    for (i, input) in inputs.iter().enumerate() {
-        let arg_reg = put_input_in_reg(ctx, *input);
-        abi.emit_copy_regs_to_arg(ctx, i, ValueRegs::one(arg_reg));
-    }
-    if call_conv.extends_baldrdash() {
-        let vm_context_vreg = ctx
-            .get_vm_context()
-            .expect("should have a VMContext to pass to libcall funcs");
-        abi.emit_copy_regs_to_arg(ctx, inputs.len(), ValueRegs::one(vm_context_vreg));
-    }
-
-    abi.emit_call(ctx);
-    for (i, output) in outputs.iter().enumerate() {
-        let retval_reg = get_output_reg(ctx, *output).only_reg().unwrap();
-        abi.emit_copy_retval_to_regs(ctx, i, ValueRegs::one(retval_reg));
-    }
-    abi.emit_stack_post_adjust(ctx);
-
-    Ok(())
-}
-
-/// Returns whether the given input is a shift by a constant value less or equal than 3.
-/// The goal is to embed it within an address mode.
-fn matches_small_constant_shift<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    spec: InsnInput,
-) -> Option<(InsnInput, u8)> {
-    matches_input(ctx, spec, Opcode::Ishl).and_then(|shift| {
-        match input_to_imm(
-            ctx,
-            InsnInput {
-                insn: shift,
-                input: 1,
-            },
-        ) {
-            Some(shift_amt) if shift_amt <= 3 => Some((
-                InsnInput {
-                    insn: shift,
-                    input: 0,
-                },
-                shift_amt as u8,
-            )),
-            _ => None,
-        }
-    })
-}
-
-/// Lowers an instruction to one of the x86 addressing modes.
-///
-/// Note: the 32-bit offset in Cranelift has to be sign-extended, which maps x86's behavior.
-fn lower_to_amode<C: LowerCtx<I = Inst>>(ctx: &mut C, spec: InsnInput, offset: i32) -> Amode {
-    let flags = ctx
-        .memflags(spec.insn)
-        .expect("Instruction with amode should have memflags");
-
-    // We now either have an add that we must materialize, or some other input; as well as the
-    // final offset.
-    if let Some(add) = matches_input(ctx, spec, Opcode::Iadd) {
-        debug_assert_eq!(ctx.output_ty(add, 0), types::I64);
-        let add_inputs = &[
-            InsnInput {
-                insn: add,
-                input: 0,
-            },
-            InsnInput {
-                insn: add,
-                input: 1,
-            },
-        ];
-
-        // TODO heap_addr legalization generates a uext64 *after* the shift, so these optimizations
-        // aren't happening in the wasm case. We could do better, given some range analysis.
-        let (base, index, shift) = if let Some((shift_input, shift_amt)) =
-            matches_small_constant_shift(ctx, add_inputs[0])
-        {
-            (
-                put_input_in_reg(ctx, add_inputs[1]),
-                put_input_in_reg(ctx, shift_input),
-                shift_amt,
-            )
-        } else if let Some((shift_input, shift_amt)) =
-            matches_small_constant_shift(ctx, add_inputs[1])
-        {
-            (
-                put_input_in_reg(ctx, add_inputs[0]),
-                put_input_in_reg(ctx, shift_input),
-                shift_amt,
-            )
-        } else {
-            for i in 0..=1 {
-                // Try to pierce through uextend.
-                if let Some(uextend) = matches_input(
-                    ctx,
-                    InsnInput {
-                        insn: add,
-                        input: i,
-                    },
-                    Opcode::Uextend,
-                ) {
-                    if let Some(cst) = ctx.get_input_as_source_or_const(uextend, 0).constant {
-                        // Zero the upper bits.
-                        let input_size = ctx.input_ty(uextend, 0).bits() as u64;
-                        let shift: u64 = 64 - input_size;
-                        let uext_cst: u64 = (cst << shift) >> shift;
-
-                        let final_offset = (offset as i64).wrapping_add(uext_cst as i64);
-                        if low32_will_sign_extend_to_64(final_offset as u64) {
-                            let base = put_input_in_reg(ctx, add_inputs[1 - i]);
-                            return Amode::imm_reg(final_offset as u32, base).with_flags(flags);
-                        }
-                    }
-                }
-
-                // If it's a constant, add it directly!
-                if let Some(cst) = ctx.get_input_as_source_or_const(add, i).constant {
-                    let final_offset = (offset as i64).wrapping_add(cst as i64);
-                    if low32_will_sign_extend_to_64(final_offset as u64) {
-                        let base = put_input_in_reg(ctx, add_inputs[1 - i]);
-                        return Amode::imm_reg(final_offset as u32, base).with_flags(flags);
-                    }
-                }
-            }
-
-            (
-                put_input_in_reg(ctx, add_inputs[0]),
-                put_input_in_reg(ctx, add_inputs[1]),
-                0,
-            )
-        };
-
-        return Amode::imm_reg_reg_shift(
-            offset as u32,
-            Gpr::new(base).unwrap(),
-            Gpr::new(index).unwrap(),
-            shift,
-        )
-        .with_flags(flags);
-    }
-
-    let input = put_input_in_reg(ctx, spec);
-    Amode::imm_reg(offset as u32, input).with_flags(flags)
-}
-
-fn emit_moves<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    dst: ValueRegs<Writable<Reg>>,
-    src: ValueRegs<Reg>,
-    ty: Type,
-) {
-    let (_, tys) = Inst::rc_for_type(ty).unwrap();
-    for ((dst, src), ty) in dst.regs().iter().zip(src.regs().iter()).zip(tys.iter()) {
-        ctx.emit(Inst::gen_move(*dst, *src, *ty));
-    }
-}
-
-fn emit_cmoves<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    size: u8,
-    cc: CC,
-    src: ValueRegs<Reg>,
-    dst: ValueRegs<Writable<Reg>>,
-) {
-    let size = size / src.len() as u8;
-    let size = u8::max(size, 4); // at least 32 bits
-    for (dst, src) in dst.regs().iter().zip(src.regs().iter()) {
-        ctx.emit(Inst::cmove(
-            OperandSize::from_bytes(size.into()),
-            cc,
-            RegMem::reg(*src),
-            *dst,
-        ));
-    }
-}
-
-//=============================================================================
-// Top-level instruction lowering entry point, for one instruction.
-
-/// Actually codegen an instruction's results into registers.
-fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
-    ctx: &mut C,
-    insn: IRInst,
-    flags: &Flags,
-    isa_flags: &x64_settings::Flags,
-    triple: &Triple,
-) -> CodegenResult<()> {
-    let op = ctx.data(insn).opcode();
-
-    let inputs: SmallVec<[InsnInput; 4]> = (0..ctx.num_inputs(insn))
-        .map(|i| InsnInput { insn, input: i })
-        .collect();
-    let outputs: SmallVec<[InsnOutput; 2]> = (0..ctx.num_outputs(insn))
-        .map(|i| InsnOutput { insn, output: i })
-        .collect();
-
-    let ty = if outputs.len() > 0 {
-        Some(ctx.output_ty(insn, 0))
-    } else {
-        None
-    };
-
-    if let Ok(()) = isle::lower(ctx, flags, isa_flags, &outputs, insn) {
-        return Ok(());
-    }
-
-    let implemented_in_isle = |ctx: &mut C| {
-        unreachable!(
-            "implemented in ISLE: inst = `{}`, type = `{:?}`",
-            ctx.dfg().display_inst(insn),
-            ty
-        )
-    };
-
-    match op {
-        Opcode::Iconst
-        | Opcode::Bconst
-        | Opcode::F32const
-        | Opcode::F64const
-        | Opcode::Null
-        | Opcode::Iadd
-        | Opcode::IaddIfcout
-        | Opcode::SaddSat
-        | Opcode::UaddSat
-        | Opcode::Isub
-        | Opcode::SsubSat
-        | Opcode::UsubSat
-        | Opcode::AvgRound
-        | Opcode::Band
-        | Opcode::Bor
-        | Opcode::Bxor
-        | Opcode::Imul
-        | Opcode::BandNot
-        | Opcode::Iabs
-        | Opcode::Imax
-        | Opcode::Umax
-        | Opcode::Imin
-        | Opcode::Umin
-        | Opcode::Bnot
-        | Opcode::Bitselect
-        | Opcode::Vselect
-        | Opcode::Ushr
-        | Opcode::Sshr
-        | Opcode::Ishl
-        | Opcode::Rotl
-        | Opcode::Rotr
-        | Opcode::Ineg
-        | Opcode::Trap
-        | Opcode::ResumableTrap
-        | Opcode::Clz
-        | Opcode::Ctz
-        | Opcode::Popcnt
-        | Opcode::Bitrev
-        | Opcode::IsNull
-        | Opcode::IsInvalid
-        | Opcode::Uextend
-        | Opcode::Sextend
-        | Opcode::Breduce
-        | Opcode::Bextend
-        | Opcode::Ireduce
-        | Opcode::Bint
-        | Opcode::Debugtrap
-        | Opcode::WideningPairwiseDotProductS
-        | Opcode::Fadd
-        | Opcode::Fsub
-        | Opcode::Fmul
-        | Opcode::Fdiv
-        | Opcode::Fmin
-        | Opcode::Fmax
-        | Opcode::FminPseudo
-        | Opcode::FmaxPseudo => implemented_in_isle(ctx),
-
-        Opcode::Icmp => {
-            let condcode = ctx.data(insn).cond_code().unwrap();
-            let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let ty = ctx.input_ty(insn, 0);
-            if !ty.is_vector() {
-                let condcode = emit_cmp(ctx, insn, condcode);
-                let cc = CC::from_intcc(condcode);
-                ctx.emit(Inst::setcc(cc, dst));
-            } else {
-                assert_eq!(ty.bits(), 128);
-                let eq = |ty| match ty {
-                    types::I8X16 => SseOpcode::Pcmpeqb,
-                    types::I16X8 => SseOpcode::Pcmpeqw,
-                    types::I32X4 => SseOpcode::Pcmpeqd,
-                    types::I64X2 => SseOpcode::Pcmpeqq,
-                    _ => panic!(
-                        "Unable to find an instruction for {} for type: {}",
-                        condcode, ty
-                    ),
-                };
-                let gt = |ty| match ty {
-                    types::I8X16 => SseOpcode::Pcmpgtb,
-                    types::I16X8 => SseOpcode::Pcmpgtw,
-                    types::I32X4 => SseOpcode::Pcmpgtd,
-                    types::I64X2 => SseOpcode::Pcmpgtq,
-                    _ => panic!(
-                        "Unable to find an instruction for {} for type: {}",
-                        condcode, ty
-                    ),
-                };
-                let maxu = |ty| match ty {
-                    types::I8X16 => SseOpcode::Pmaxub,
-                    types::I16X8 => SseOpcode::Pmaxuw,
-                    types::I32X4 => SseOpcode::Pmaxud,
-                    _ => panic!(
-                        "Unable to find an instruction for {} for type: {}",
-                        condcode, ty
-                    ),
-                };
-                let mins = |ty| match ty {
-                    types::I8X16 => SseOpcode::Pminsb,
-                    types::I16X8 => SseOpcode::Pminsw,
-                    types::I32X4 => SseOpcode::Pminsd,
-                    _ => panic!(
-                        "Unable to find an instruction for {} for type: {}",
-                        condcode, ty
-                    ),
-                };
-                let minu = |ty| match ty {
-                    types::I8X16 => SseOpcode::Pminub,
-                    types::I16X8 => SseOpcode::Pminuw,
-                    types::I32X4 => SseOpcode::Pminud,
-                    _ => panic!(
-                        "Unable to find an instruction for {} for type: {}",
-                        condcode, ty
-                    ),
-                };
-
-                // Here we decide which operand to use as the read/write `dst` (ModRM reg field) and
-                // which to use as the read `input` (ModRM r/m field). In the normal case we use
-                // Cranelift's first operand, the `lhs`, as `dst` but we flip the operands for the
-                // less-than cases so that we can reuse the greater-than implementation.
-                //
-                // In a surprising twist, the operands for i64x2 `gte`/`sle` must also be flipped
-                // from the normal order because of the special-case lowering for these instructions
-                // (i.e. we use PCMPGTQ with flipped operands and negate the result).
-                let input = match condcode {
-                    IntCC::SignedLessThanOrEqual if ty == types::I64X2 => {
-                        let lhs = put_input_in_reg(ctx, inputs[0]);
-                        let rhs = input_to_reg_mem(ctx, inputs[1]);
-                        ctx.emit(Inst::gen_move(dst, lhs, ty));
-                        rhs
-                    }
-                    IntCC::SignedGreaterThanOrEqual if ty == types::I64X2 => {
-                        let lhs = input_to_reg_mem(ctx, inputs[0]);
-                        let rhs = put_input_in_reg(ctx, inputs[1]);
-                        ctx.emit(Inst::gen_move(dst, rhs, ty));
-                        lhs
-                    }
-                    IntCC::SignedLessThan
-                    | IntCC::SignedLessThanOrEqual
-                    | IntCC::UnsignedLessThan
-                    | IntCC::UnsignedLessThanOrEqual => {
-                        let lhs = input_to_reg_mem(ctx, inputs[0]);
-                        let rhs = put_input_in_reg(ctx, inputs[1]);
-                        ctx.emit(Inst::gen_move(dst, rhs, ty));
-                        lhs
-                    }
-                    _ => {
-                        let lhs = put_input_in_reg(ctx, inputs[0]);
-                        let rhs = input_to_reg_mem(ctx, inputs[1]);
-                        ctx.emit(Inst::gen_move(dst, lhs, ty));
-                        rhs
-                    }
-                };
-
-                match condcode {
-                    IntCC::Equal => ctx.emit(Inst::xmm_rm_r(eq(ty), input, dst)),
-                    IntCC::NotEqual => {
-                        ctx.emit(Inst::xmm_rm_r(eq(ty), input, dst));
-                        // Emit all 1s into the `tmp` register.
-                        let tmp = ctx.alloc_tmp(ty).only_reg().unwrap();
-                        ctx.emit(Inst::xmm_rm_r(eq(ty), RegMem::from(tmp), tmp));
-                        // Invert the result of the `PCMPEQ*`.
-                        ctx.emit(Inst::xmm_rm_r(SseOpcode::Pxor, RegMem::from(tmp), dst));
-                    }
-                    IntCC::SignedGreaterThan | IntCC::SignedLessThan => {
-                        ctx.emit(Inst::xmm_rm_r(gt(ty), input, dst))
-                    }
-                    IntCC::SignedGreaterThanOrEqual | IntCC::SignedLessThanOrEqual
-                        if ty != types::I64X2 =>
-                    {
-                        ctx.emit(Inst::xmm_rm_r(mins(ty), input.clone(), dst));
-                        ctx.emit(Inst::xmm_rm_r(eq(ty), input, dst))
-                    }
-                    IntCC::SignedGreaterThanOrEqual | IntCC::SignedLessThanOrEqual
-                        if ty == types::I64X2 =>
-                    {
-                        // The PMINS* instruction is only available in AVX512VL/F so we must instead
-                        // compare with flipped operands and negate the result (emitting one more
-                        // instruction).
-                        ctx.emit(Inst::xmm_rm_r(gt(ty), input, dst));
-                        // Emit all 1s into the `tmp` register.
-                        let tmp = ctx.alloc_tmp(ty).only_reg().unwrap();
-                        ctx.emit(Inst::xmm_rm_r(eq(ty), RegMem::from(tmp), tmp));
-                        // Invert the result of the `PCMPGT*`.
-                        ctx.emit(Inst::xmm_rm_r(SseOpcode::Pxor, RegMem::from(tmp), dst));
-                    }
-                    IntCC::UnsignedGreaterThan | IntCC::UnsignedLessThan => {
-                        ctx.emit(Inst::xmm_rm_r(maxu(ty), input.clone(), dst));
-                        ctx.emit(Inst::xmm_rm_r(eq(ty), input, dst));
-                        // Emit all 1s into the `tmp` register.
-                        let tmp = ctx.alloc_tmp(ty).only_reg().unwrap();
-                        ctx.emit(Inst::xmm_rm_r(eq(ty), RegMem::from(tmp), tmp));
-                        // Invert the result of the `PCMPEQ*`.
-                        ctx.emit(Inst::xmm_rm_r(SseOpcode::Pxor, RegMem::from(tmp), dst));
-                    }
-                    IntCC::UnsignedGreaterThanOrEqual | IntCC::UnsignedLessThanOrEqual => {
-                        ctx.emit(Inst::xmm_rm_r(minu(ty), input.clone(), dst));
-                        ctx.emit(Inst::xmm_rm_r(eq(ty), input, dst))
-                    }
-                    _ => unimplemented!("Unimplemented comparison code for icmp: {}", condcode),
-                }
-            }
-        }
-
-        Opcode::Fcmp => {
-            let cond_code = ctx.data(insn).fp_cond_code().unwrap();
-            let input_ty = ctx.input_ty(insn, 0);
-            if !input_ty.is_vector() {
-                // Unordered is returned by setting ZF, PF, CF <- 111
-                // Greater than by ZF, PF, CF <- 000
-                // Less than by ZF, PF, CF <- 001
-                // Equal by ZF, PF, CF <- 100
-                //
-                // Checking the result of comiss is somewhat annoying because you don't have setcc
-                // instructions that explicitly check simultaneously for the condition (i.e. eq, le,
-                // gt, etc) *and* orderedness.
-                //
-                // So that might mean we need more than one setcc check and then a logical "and" or
-                // "or" to determine both, in some cases.  However knowing that if the parity bit is
-                // set, then the result was considered unordered and knowing that if the parity bit is
-                // set, then both the ZF and CF flag bits must also be set we can get away with using
-                // one setcc for most condition codes.
-
-                let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-
-                match emit_fcmp(ctx, insn, cond_code, FcmpSpec::Normal) {
-                    FcmpCondResult::Condition(cc) => {
-                        ctx.emit(Inst::setcc(cc, dst));
-                    }
-                    FcmpCondResult::AndConditions(cc1, cc2) => {
-                        let tmp = ctx.alloc_tmp(types::I32).only_reg().unwrap();
-                        ctx.emit(Inst::setcc(cc1, tmp));
-                        ctx.emit(Inst::setcc(cc2, dst));
-                        ctx.emit(Inst::alu_rmi_r(
-                            OperandSize::Size32,
-                            AluRmiROpcode::And,
-                            RegMemImm::reg(tmp.to_reg()),
-                            dst,
-                        ));
-                    }
-                    FcmpCondResult::OrConditions(cc1, cc2) => {
-                        let tmp = ctx.alloc_tmp(types::I32).only_reg().unwrap();
-                        ctx.emit(Inst::setcc(cc1, tmp));
-                        ctx.emit(Inst::setcc(cc2, dst));
-                        ctx.emit(Inst::alu_rmi_r(
-                            OperandSize::Size32,
-                            AluRmiROpcode::Or,
-                            RegMemImm::reg(tmp.to_reg()),
-                            dst,
-                        ));
-                    }
-                    FcmpCondResult::InvertedEqualOrConditions(_, _) => unreachable!(),
-                }
-            } else {
-                let op = match input_ty {
-                    types::F32X4 => SseOpcode::Cmpps,
-                    types::F64X2 => SseOpcode::Cmppd,
-                    _ => panic!("Bad input type to fcmp: {}", input_ty),
-                };
-
-                // Since some packed comparisons are not available, some of the condition codes
-                // must be inverted, with a corresponding `flip` of the operands.
-                let (imm, flip) = match cond_code {
-                    FloatCC::GreaterThan => (FcmpImm::LessThan, true),
-                    FloatCC::GreaterThanOrEqual => (FcmpImm::LessThanOrEqual, true),
-                    FloatCC::UnorderedOrLessThan => (FcmpImm::UnorderedOrGreaterThan, true),
-                    FloatCC::UnorderedOrLessThanOrEqual => {
-                        (FcmpImm::UnorderedOrGreaterThanOrEqual, true)
-                    }
-                    FloatCC::OrderedNotEqual | FloatCC::UnorderedOrEqual => {
-                        panic!("unsupported float condition code: {}", cond_code)
-                    }
-                    _ => (FcmpImm::from(cond_code), false),
-                };
-
-                // Determine the operands of the comparison, possibly by flipping them.
-                let (lhs, rhs) = if flip {
-                    (
-                        put_input_in_reg(ctx, inputs[1]),
-                        input_to_reg_mem(ctx, inputs[0]),
-                    )
-                } else {
-                    (
-                        put_input_in_reg(ctx, inputs[0]),
-                        input_to_reg_mem(ctx, inputs[1]),
-                    )
-                };
-
-                // Move the `lhs` to the same register as `dst`; this may not emit an actual move
-                // but ensures that the registers are the same to match x86's read-write operand
-                // encoding.
-                let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-                ctx.emit(Inst::gen_move(dst, lhs, input_ty));
-
-                // Emit the comparison.
-                ctx.emit(Inst::xmm_rm_r_imm(
-                    op,
-                    rhs,
-                    dst,
-                    imm.encode(),
-                    OperandSize::Size32,
-                ));
-            }
-        }
-
-        Opcode::FallthroughReturn | Opcode::Return => {
-            for i in 0..ctx.num_inputs(insn) {
-                let src_reg = put_input_in_regs(ctx, inputs[i]);
-                let retval_reg = ctx.retval(i);
-                let ty = ctx.input_ty(insn, i);
-                assert!(src_reg.len() == retval_reg.len());
-                let (_, tys) = Inst::rc_for_type(ty)?;
-                for ((&src, &dst), &ty) in src_reg
-                    .regs()
-                    .iter()
-                    .zip(retval_reg.regs().iter())
-                    .zip(tys.iter())
-                {
-                    ctx.emit(Inst::gen_move(dst, src, ty));
-                }
-            }
-            // N.B.: the Ret itself is generated by the ABI.
-        }
-
-        Opcode::Call | Opcode::CallIndirect => {
-            let caller_conv = ctx.abi().call_conv();
-            let (mut abi, inputs) = match op {
-                Opcode::Call => {
-                    let (extname, dist) = ctx.call_target(insn).unwrap();
-                    let sig = ctx.call_sig(insn).unwrap();
-                    assert_eq!(inputs.len(), sig.params.len());
-                    assert_eq!(outputs.len(), sig.returns.len());
-                    (
-                        X64ABICaller::from_func(sig, &extname, dist, caller_conv, flags)?,
-                        &inputs[..],
-                    )
-                }
-
-                Opcode::CallIndirect => {
-                    let ptr = put_input_in_reg(ctx, inputs[0]);
-                    let sig = ctx.call_sig(insn).unwrap();
-                    assert_eq!(inputs.len() - 1, sig.params.len());
-                    assert_eq!(outputs.len(), sig.returns.len());
-                    (
-                        X64ABICaller::from_ptr(sig, ptr, op, caller_conv, flags)?,
-                        &inputs[1..],
-                    )
-                }
-
-                _ => unreachable!(),
-            };
-
-            abi.emit_stack_pre_adjust(ctx);
-            assert_eq!(inputs.len(), abi.num_args());
-            for i in abi.get_copy_to_arg_order() {
-                let input = inputs[i];
-                let arg_regs = put_input_in_regs(ctx, input);
-                abi.emit_copy_regs_to_arg(ctx, i, arg_regs);
-            }
-            abi.emit_call(ctx);
-            for (i, output) in outputs.iter().enumerate() {
-                let retval_regs = get_output_reg(ctx, *output);
-                abi.emit_copy_retval_to_regs(ctx, i, retval_regs);
-            }
-            abi.emit_stack_post_adjust(ctx);
-        }
-
-        Opcode::Trapif | Opcode::Trapff => {
-            let trap_code = ctx.data(insn).trap_code().unwrap();
-
-            if matches_input(ctx, inputs[0], Opcode::IaddIfcout).is_some() {
-                let cond_code = ctx.data(insn).cond_code().unwrap();
-                // The flags must not have been clobbered by any other instruction between the
-                // iadd_ifcout and this instruction, as verified by the CLIF validator; so we can
-                // simply use the flags here.
-                let cc = CC::from_intcc(cond_code);
-
-                ctx.emit_safepoint(Inst::TrapIf { trap_code, cc });
-            } else if op == Opcode::Trapif {
-                let cond_code = ctx.data(insn).cond_code().unwrap();
-
-                // Verification ensures that the input is always a single-def ifcmp.
-                let ifcmp = matches_input(ctx, inputs[0], Opcode::Ifcmp).unwrap();
-                let cond_code = emit_cmp(ctx, ifcmp, cond_code);
-                let cc = CC::from_intcc(cond_code);
-
-                ctx.emit_safepoint(Inst::TrapIf { trap_code, cc });
-            } else {
-                let cond_code = ctx.data(insn).fp_cond_code().unwrap();
-
-                // Verification ensures that the input is always a single-def ffcmp.
-                let ffcmp = matches_input(ctx, inputs[0], Opcode::Ffcmp).unwrap();
-
-                match emit_fcmp(ctx, ffcmp, cond_code, FcmpSpec::Normal) {
-                    FcmpCondResult::Condition(cc) => {
-                        ctx.emit_safepoint(Inst::TrapIf { trap_code, cc })
-                    }
-                    FcmpCondResult::AndConditions(cc1, cc2) => {
-                        // A bit unfortunate, but materialize the flags in their own register, and
-                        // check against this.
-                        let tmp = ctx.alloc_tmp(types::I32).only_reg().unwrap();
-                        let tmp2 = ctx.alloc_tmp(types::I32).only_reg().unwrap();
-                        ctx.emit(Inst::setcc(cc1, tmp));
-                        ctx.emit(Inst::setcc(cc2, tmp2));
-                        ctx.emit(Inst::alu_rmi_r(
-                            OperandSize::Size32,
-                            AluRmiROpcode::And,
-                            RegMemImm::reg(tmp.to_reg()),
-                            tmp2,
-                        ));
-                        ctx.emit_safepoint(Inst::TrapIf {
-                            trap_code,
-                            cc: CC::NZ,
-                        });
-                    }
-                    FcmpCondResult::OrConditions(cc1, cc2) => {
-                        ctx.emit_safepoint(Inst::TrapIf { trap_code, cc: cc1 });
-                        ctx.emit_safepoint(Inst::TrapIf { trap_code, cc: cc2 });
-                    }
-                    FcmpCondResult::InvertedEqualOrConditions(_, _) => unreachable!(),
-                };
-            };
-        }
-
-        Opcode::Sqrt => {
-            // We can't guarantee the RHS (if a load) is 128-bit aligned, so we
-            // must avoid merging a load here.
-            let src = RegMem::reg(put_input_in_reg(ctx, inputs[0]));
-            let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let ty = ty.unwrap();
-
-            let sse_op = match ty {
-                types::F32 => SseOpcode::Sqrtss,
-                types::F64 => SseOpcode::Sqrtsd,
-                types::F32X4 => SseOpcode::Sqrtps,
-                types::F64X2 => SseOpcode::Sqrtpd,
-                _ => panic!(
-                    "invalid type: expected one of [F32, F64, F32X4, F64X2], found {}",
-                    ty
-                ),
-            };
-
-            ctx.emit(Inst::xmm_unary_rm_r(sse_op, src, dst));
-        }
-
-        Opcode::Fpromote => {
-            // We can't guarantee the RHS (if a load) is 128-bit aligned, so we
-            // must avoid merging a load here.
-            let src = RegMem::reg(put_input_in_reg(ctx, inputs[0]));
-            let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            ctx.emit(Inst::xmm_unary_rm_r(SseOpcode::Cvtss2sd, src, dst));
-        }
-
-        Opcode::FvpromoteLow => {
-            let src = RegMem::reg(put_input_in_reg(ctx, inputs[0]));
-            let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            ctx.emit(Inst::xmm_unary_rm_r(
-                SseOpcode::Cvtps2pd,
-                RegMem::from(src),
-                dst,
-            ));
-        }
-
-        Opcode::Fdemote => {
-            // We can't guarantee the RHS (if a load) is 128-bit aligned, so we
-            // must avoid merging a load here.
-            let src = RegMem::reg(put_input_in_reg(ctx, inputs[0]));
-            let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            ctx.emit(Inst::xmm_unary_rm_r(SseOpcode::Cvtsd2ss, src, dst));
-        }
-
-        Opcode::Fvdemote => {
-            let src = RegMem::reg(put_input_in_reg(ctx, inputs[0]));
-            let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            ctx.emit(Inst::xmm_unary_rm_r(
-                SseOpcode::Cvtpd2ps,
-                RegMem::from(src),
-                dst,
-            ));
-        }
-
-        Opcode::FcvtFromSint => {
-            let output_ty = ty.unwrap();
-            if !output_ty.is_vector() {
-                let (ext_spec, src_size) = match ctx.input_ty(insn, 0) {
-                    types::I8 | types::I16 => (Some(ExtSpec::SignExtendTo32), OperandSize::Size32),
-                    types::I32 => (None, OperandSize::Size32),
-                    types::I64 => (None, OperandSize::Size64),
-                    _ => unreachable!(),
-                };
-
-                let src = match ext_spec {
-                    Some(ext_spec) => RegMem::reg(extend_input_to_reg(ctx, inputs[0], ext_spec)),
-                    None => RegMem::reg(put_input_in_reg(ctx, inputs[0])),
-                };
-
-                let opcode = if output_ty == types::F32 {
-                    SseOpcode::Cvtsi2ss
-                } else {
-                    assert_eq!(output_ty, types::F64);
-                    SseOpcode::Cvtsi2sd
-                };
-                let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-                ctx.emit(Inst::gpr_to_xmm(opcode, src, src_size, dst));
-            } else {
-                let ty = ty.unwrap();
-                let src = put_input_in_reg(ctx, inputs[0]);
-                let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-                let opcode = match ctx.input_ty(insn, 0) {
-                    types::I32X4 => SseOpcode::Cvtdq2ps,
-                    _ => {
-                        unimplemented!("unable to use type {} for op {}", ctx.input_ty(insn, 0), op)
-                    }
-                };
-                ctx.emit(Inst::gen_move(dst, src, ty));
-                ctx.emit(Inst::xmm_rm_r(opcode, RegMem::from(dst), dst));
-            }
-        }
-        Opcode::FcvtLowFromSint => {
-            let src = RegMem::reg(put_input_in_reg(ctx, inputs[0]));
-            let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            ctx.emit(Inst::xmm_unary_rm_r(
-                SseOpcode::Cvtdq2pd,
-                RegMem::from(src),
-                dst,
-            ));
-        }
-        Opcode::FcvtFromUint => {
-            let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let ty = ty.unwrap();
-            let input_ty = ctx.input_ty(insn, 0);
-            let output_ty = ctx.output_ty(insn, 0);
-
-            if !ty.is_vector() {
-                match input_ty {
-                    types::I8 | types::I16 | types::I32 => {
-                        // Conversion from an unsigned int smaller than 64-bit is easy: zero-extend +
-                        // do a signed conversion (which won't overflow).
-                        let opcode = if ty == types::F32 {
-                            SseOpcode::Cvtsi2ss
-                        } else {
-                            assert_eq!(ty, types::F64);
-                            SseOpcode::Cvtsi2sd
-                        };
-
-                        let src = RegMem::reg(extend_input_to_reg(
-                            ctx,
-                            inputs[0],
-                            ExtSpec::ZeroExtendTo64,
-                        ));
-                        ctx.emit(Inst::gpr_to_xmm(opcode, src, OperandSize::Size64, dst));
-                    }
-
-                    types::I64 => {
-                        let src = put_input_in_reg(ctx, inputs[0]);
-
-                        let src_copy = ctx.alloc_tmp(types::I64).only_reg().unwrap();
-                        ctx.emit(Inst::gen_move(src_copy, src, types::I64));
-
-                        let tmp_gpr1 = ctx.alloc_tmp(types::I64).only_reg().unwrap();
-                        let tmp_gpr2 = ctx.alloc_tmp(types::I64).only_reg().unwrap();
-                        ctx.emit(Inst::cvt_u64_to_float_seq(
-                            if ty == types::F64 {
-                                OperandSize::Size64
-                            } else {
-                                OperandSize::Size32
-                            },
-                            src_copy,
-                            tmp_gpr1,
-                            tmp_gpr2,
-                            dst,
-                        ));
-                    }
-                    _ => panic!("unexpected input type for FcvtFromUint: {:?}", input_ty),
-                };
-            } else if output_ty == types::F64X2 {
-                if let Some(uwiden) = matches_input(ctx, inputs[0], Opcode::UwidenLow) {
-                    let uwiden_input = InsnInput {
-                        insn: uwiden,
-                        input: 0,
-                    };
-                    let src = put_input_in_reg(ctx, uwiden_input);
-                    let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-                    let input_ty = ctx.input_ty(uwiden, 0);
-
-                    // Matches_input further obfuscates which Wasm instruction this is ultimately
-                    // lowering. Check here that the types are as expected for F64x2ConvertLowI32x4U.
-                    debug_assert!(input_ty == types::I32X4);
-
-                    // Algorithm uses unpcklps to help create a float that is equivalent
-                    // 0x1.0p52 + double(src). 0x1.0p52 is unique because at this exponent
-                    // every value of the mantissa represents a corresponding uint32 number.
-                    // When we subtract 0x1.0p52 we are left with double(src).
-                    let uint_mask = ctx.alloc_tmp(types::I32X4).only_reg().unwrap();
-                    ctx.emit(Inst::gen_move(dst, src, types::I32X4));
-
-                    static UINT_MASK: [u8; 16] = [
-                        0x00, 0x00, 0x30, 0x43, 0x00, 0x00, 0x30, 0x43, 0x00, 0x00, 0x00, 0x00,
-                        0x00, 0x00, 0x00, 0x00,
-                    ];
-
-                    let uint_mask_const =
-                        ctx.use_constant(VCodeConstantData::WellKnown(&UINT_MASK));
-
-                    ctx.emit(Inst::xmm_load_const(
-                        uint_mask_const,
-                        uint_mask,
-                        types::I32X4,
-                    ));
-
-                    // Creates 0x1.0p52 + double(src)
-                    ctx.emit(Inst::xmm_rm_r(
-                        SseOpcode::Unpcklps,
-                        RegMem::from(uint_mask),
-                        dst,
-                    ));
-
-                    static UINT_MASK_HIGH: [u8; 16] = [
-                        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x43, 0x00, 0x00, 0x00, 0x00,
-                        0x00, 0x00, 0x30, 0x43,
-                    ];
-
-                    let uint_mask_high_const =
-                        ctx.use_constant(VCodeConstantData::WellKnown(&UINT_MASK_HIGH));
-                    let uint_mask_high = ctx.alloc_tmp(types::I32X4).only_reg().unwrap();
-                    ctx.emit(Inst::xmm_load_const(
-                        uint_mask_high_const,
-                        uint_mask_high,
-                        types::I32X4,
-                    ));
-
-                    // 0x1.0p52 + double(src) - 0x1.0p52
-                    ctx.emit(Inst::xmm_rm_r(
-                        SseOpcode::Subpd,
-                        RegMem::from(uint_mask_high),
-                        dst,
-                    ));
-                } else {
-                    panic!("Unsupported FcvtFromUint conversion types: {}", ty);
-                }
-            } else {
-                assert_eq!(ctx.input_ty(insn, 0), types::I32X4);
-                let src = put_input_in_reg(ctx, inputs[0]);
-                let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-
-                if isa_flags.use_avx512vl_simd() && isa_flags.use_avx512f_simd() {
-                    // When AVX512VL and AVX512F are available,
-                    // `fcvt_from_uint` can be lowered to a single instruction.
-                    ctx.emit(Inst::xmm_unary_rm_r_evex(
-                        Avx512Opcode::Vcvtudq2ps,
-                        RegMem::reg(src),
-                        dst,
-                    ));
-                } else {
-                    // Converting packed unsigned integers to packed floats
-                    // requires a few steps. There is no single instruction
-                    // lowering for converting unsigned floats but there is for
-                    // converting packed signed integers to float (cvtdq2ps). In
-                    // the steps below we isolate the upper half (16 bits) and
-                    // lower half (16 bits) of each lane and then we convert
-                    // each half separately using cvtdq2ps meant for signed
-                    // integers. In order for this to work for the upper half
-                    // bits we must shift right by 1 (divide by 2) these bits in
-                    // order to ensure the most significant bit is 0 not signed,
-                    // and then after the conversion we double the value.
-                    // Finally we add the converted values where addition will
-                    // correctly round.
-                    //
-                    // Sequence:
-                    // -> A = 0xffffffff
-                    // -> Ah = 0xffff0000
-                    // -> Al = 0x0000ffff
-                    // -> Convert(Al) // Convert int to float
-                    // -> Ah = Ah >> 1 // Shift right 1 to assure Ah conversion isn't treated as signed
-                    // -> Convert(Ah) // Convert .. with no loss of significant digits from previous shift
-                    // -> Ah = Ah + Ah // Double Ah to account for shift right before the conversion.
-                    // -> dst = Ah + Al // Add the two floats together
-
-                    // Create a temporary register
-                    let tmp = ctx.alloc_tmp(types::I32X4).only_reg().unwrap();
-                    ctx.emit(Inst::xmm_unary_rm_r(
-                        SseOpcode::Movapd,
-                        RegMem::reg(src),
-                        tmp,
-                    ));
-                    ctx.emit(Inst::gen_move(dst, src, ty));
-
-                    // Get the low 16 bits
-                    ctx.emit(Inst::xmm_rmi_reg(SseOpcode::Pslld, RegMemImm::imm(16), tmp));
-                    ctx.emit(Inst::xmm_rmi_reg(SseOpcode::Psrld, RegMemImm::imm(16), tmp));
-
-                    // Get the high 16 bits
-                    ctx.emit(Inst::xmm_rm_r(SseOpcode::Psubd, RegMem::from(tmp), dst));
-
-                    // Convert the low 16 bits
-                    ctx.emit(Inst::xmm_rm_r(SseOpcode::Cvtdq2ps, RegMem::from(tmp), tmp));
-
-                    // Shift the high bits by 1, convert, and double to get the correct value.
-                    ctx.emit(Inst::xmm_rmi_reg(SseOpcode::Psrld, RegMemImm::imm(1), dst));
-                    ctx.emit(Inst::xmm_rm_r(SseOpcode::Cvtdq2ps, RegMem::from(dst), dst));
-                    ctx.emit(Inst::xmm_rm_r(
-                        SseOpcode::Addps,
-                        RegMem::reg(dst.to_reg()),
-                        dst,
-                    ));
-
-                    // Add together the two converted values.
-                    ctx.emit(Inst::xmm_rm_r(
-                        SseOpcode::Addps,
-                        RegMem::reg(tmp.to_reg()),
-                        dst,
-                    ));
-                }
-            }
-        }
-
-        Opcode::FcvtToUint | Opcode::FcvtToUintSat | Opcode::FcvtToSint | Opcode::FcvtToSintSat => {
-            let src = put_input_in_reg(ctx, inputs[0]);
-            let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-
-            let input_ty = ctx.input_ty(insn, 0);
-            if !input_ty.is_vector() {
-                let src_size = if input_ty == types::F32 {
-                    OperandSize::Size32
-                } else {
-                    assert_eq!(input_ty, types::F64);
-                    OperandSize::Size64
-                };
-
-                let output_ty = ty.unwrap();
-                let dst_size = if output_ty == types::I32 {
-                    OperandSize::Size32
-                } else {
-                    assert_eq!(output_ty, types::I64);
-                    OperandSize::Size64
-                };
-
-                let to_signed = op == Opcode::FcvtToSint || op == Opcode::FcvtToSintSat;
-                let is_sat = op == Opcode::FcvtToUintSat || op == Opcode::FcvtToSintSat;
-
-                let src_copy = ctx.alloc_tmp(input_ty).only_reg().unwrap();
-                ctx.emit(Inst::gen_move(src_copy, src, input_ty));
-
-                let tmp_xmm = ctx.alloc_tmp(input_ty).only_reg().unwrap();
-                let tmp_gpr = ctx.alloc_tmp(output_ty).only_reg().unwrap();
-
-                if to_signed {
-                    ctx.emit(Inst::cvt_float_to_sint_seq(
-                        src_size, dst_size, is_sat, src_copy, dst, tmp_gpr, tmp_xmm,
-                    ));
-                } else {
-                    ctx.emit(Inst::cvt_float_to_uint_seq(
-                        src_size, dst_size, is_sat, src_copy, dst, tmp_gpr, tmp_xmm,
-                    ));
-                }
-            } else {
-                if op == Opcode::FcvtToSintSat {
-                    // Sets destination to zero if float is NaN
-                    assert_eq!(types::F32X4, ctx.input_ty(insn, 0));
-                    let tmp = ctx.alloc_tmp(types::I32X4).only_reg().unwrap();
-                    ctx.emit(Inst::xmm_unary_rm_r(
-                        SseOpcode::Movapd,
-                        RegMem::reg(src),
-                        tmp,
-                    ));
-                    ctx.emit(Inst::gen_move(dst, src, input_ty));
-                    let cond = FcmpImm::from(FloatCC::Equal);
-                    ctx.emit(Inst::xmm_rm_r_imm(
-                        SseOpcode::Cmpps,
-                        RegMem::reg(tmp.to_reg()),
-                        tmp,
-                        cond.encode(),
-                        OperandSize::Size32,
-                    ));
-                    ctx.emit(Inst::xmm_rm_r(
-                        SseOpcode::Andps,
-                        RegMem::reg(tmp.to_reg()),
-                        dst,
-                    ));
-
-                    // Sets top bit of tmp if float is positive
-                    // Setting up to set top bit on negative float values
-                    ctx.emit(Inst::xmm_rm_r(
-                        SseOpcode::Pxor,
-                        RegMem::reg(dst.to_reg()),
-                        tmp,
-                    ));
-
-                    // Convert the packed float to packed doubleword.
-                    ctx.emit(Inst::xmm_rm_r(
-                        SseOpcode::Cvttps2dq,
-                        RegMem::reg(dst.to_reg()),
-                        dst,
-                    ));
-
-                    // Set top bit only if < 0
-                    // Saturate lane with sign (top) bit.
-                    ctx.emit(Inst::xmm_rm_r(
-                        SseOpcode::Pand,
-                        RegMem::reg(dst.to_reg()),
-                        tmp,
-                    ));
-                    ctx.emit(Inst::xmm_rmi_reg(SseOpcode::Psrad, RegMemImm::imm(31), tmp));
-
-                    // On overflow 0x80000000 is returned to a lane.
-                    // Below sets positive overflow lanes to 0x7FFFFFFF
-                    // Keeps negative overflow lanes as is.
-                    ctx.emit(Inst::xmm_rm_r(
-                        SseOpcode::Pxor,
-                        RegMem::reg(tmp.to_reg()),
-                        dst,
-                    ));
-                } else if op == Opcode::FcvtToUintSat {
-                    // The algorithm for converting floats to unsigned ints is a little tricky. The
-                    // complication arises because we are converting from a signed 64-bit int with a positive
-                    // integer range from 1..INT_MAX (0x1..0x7FFFFFFF) to an unsigned integer with an extended
-                    // range from (INT_MAX+1)..UINT_MAX. It's this range from (INT_MAX+1)..UINT_MAX
-                    // (0x80000000..0xFFFFFFFF) that needs to be accounted for as a special case since our
-                    // conversion instruction (cvttps2dq) only converts as high as INT_MAX (0x7FFFFFFF), but
-                    // which conveniently setting underflows and overflows (smaller than MIN_INT or larger than
-                    // MAX_INT) to be INT_MAX+1 (0x80000000). Nothing that the range (INT_MAX+1)..UINT_MAX includes
-                    // precisely INT_MAX values we can correctly account for and convert every value in this range
-                    // if we simply subtract INT_MAX+1 before doing the cvttps2dq conversion. After the subtraction
-                    // every value originally (INT_MAX+1)..UINT_MAX is now the range (0..INT_MAX).
-                    // After the conversion we add INT_MAX+1 back to this converted value, noting again that
-                    // values we are trying to account for were already set to INT_MAX+1 during the original conversion.
-                    // We simply have to create a mask and make sure we are adding together only the lanes that need
-                    // to be accounted for. Digesting it all the steps then are:
-                    //
-                    // Step 1 - Account for NaN and negative floats by setting these src values to zero.
-                    // Step 2 - Make a copy (tmp1) of the src value since we need to convert twice for
-                    //          reasons described above.
-                    // Step 3 - Convert the original src values. This will convert properly all floats up to INT_MAX
-                    // Step 4 - Subtract INT_MAX from the copy set (tmp1). Note, all zero and negative values are those
-                    //          values that were originally in the range (0..INT_MAX). This will come in handy during
-                    //          step 7 when we zero negative lanes.
-                    // Step 5 - Create a bit mask for tmp1 that will correspond to all lanes originally less than
-                    //          UINT_MAX that are now less than INT_MAX thanks to the subtraction.
-                    // Step 6 - Convert the second set of values (tmp1)
-                    // Step 7 - Prep the converted second set by zeroing out negative lanes (these have already been
-                    //          converted correctly with the first set) and by setting overflow lanes to 0x7FFFFFFF
-                    //          as this will allow us to properly saturate overflow lanes when adding to 0x80000000
-                    // Step 8 - Add the orginal converted src and the converted tmp1 where float values originally less
-                    //          than and equal to INT_MAX will be unchanged, float values originally between INT_MAX+1 and
-                    //          UINT_MAX will add together (INT_MAX) + (SRC - INT_MAX), and float values originally
-                    //          greater than UINT_MAX will be saturated to UINT_MAX (0xFFFFFFFF) after adding (0x8000000 + 0x7FFFFFFF).
-                    //
-                    //
-                    // The table below illustrates the result after each step where it matters for the converted set.
-                    // Note the original value range (original src set) is the final dst in Step 8:
-                    //
-                    // Original src set:
-                    // | Original Value Range |    Step 1    |         Step 3         |          Step 8           |
-                    // |  -FLT_MIN..FLT_MAX   | 0.0..FLT_MAX | 0..INT_MAX(w/overflow) | 0..UINT_MAX(w/saturation) |
-                    //
-                    // Copied src set (tmp1):
-                    // |    Step 2    |                  Step 4                  |
-                    // | 0.0..FLT_MAX | (0.0-(INT_MAX+1))..(FLT_MAX-(INT_MAX+1)) |
-                    //
-                    // |                       Step 6                        |                 Step 7                 |
-                    // | (0-(INT_MAX+1))..(UINT_MAX-(INT_MAX+1))(w/overflow) | ((INT_MAX+1)-(INT_MAX+1))..(INT_MAX+1) |
-
-                    // Create temporaries
-                    assert_eq!(types::F32X4, ctx.input_ty(insn, 0));
-                    let tmp1 = ctx.alloc_tmp(types::I32X4).only_reg().unwrap();
-                    let tmp2 = ctx.alloc_tmp(types::I32X4).only_reg().unwrap();
-
-                    // Converting to unsigned int so if float src is negative or NaN
-                    // will first set to zero.
-                    ctx.emit(Inst::xmm_rm_r(SseOpcode::Pxor, RegMem::from(tmp2), tmp2));
-                    ctx.emit(Inst::gen_move(dst, src, input_ty));
-                    ctx.emit(Inst::xmm_rm_r(SseOpcode::Maxps, RegMem::from(tmp2), dst));
-
-                    // Set tmp2 to INT_MAX+1. It is important to note here that after it looks
-                    // like we are only converting INT_MAX (0x7FFFFFFF) but in fact because
-                    // single precision IEEE-754 floats can only accurately represent contingous
-                    // integers up to 2^23 and outside of this range it rounds to the closest
-                    // integer that it can represent. In the case of INT_MAX, this value gets
-                    // represented as 0x4f000000 which is the integer value (INT_MAX+1).
-
-                    ctx.emit(Inst::xmm_rm_r(SseOpcode::Pcmpeqd, RegMem::from(tmp2), tmp2));
-                    ctx.emit(Inst::xmm_rmi_reg(SseOpcode::Psrld, RegMemImm::imm(1), tmp2));
-                    ctx.emit(Inst::xmm_rm_r(
-                        SseOpcode::Cvtdq2ps,
-                        RegMem::from(tmp2),
-                        tmp2,
-                    ));
-
-                    // Make a copy of these lanes and then do the first conversion.
-                    // Overflow lanes greater than the maximum allowed signed value will
-                    // set to 0x80000000. Negative and NaN lanes will be 0x0
-                    ctx.emit(Inst::xmm_mov(SseOpcode::Movaps, RegMem::from(dst), tmp1));
-                    ctx.emit(Inst::xmm_rm_r(SseOpcode::Cvttps2dq, RegMem::from(dst), dst));
-
-                    // Set lanes to src - max_signed_int
-                    ctx.emit(Inst::xmm_rm_r(SseOpcode::Subps, RegMem::from(tmp2), tmp1));
-
-                    // Create mask for all positive lanes to saturate (i.e. greater than
-                    // or equal to the maxmimum allowable unsigned int).
-                    let cond = FcmpImm::from(FloatCC::LessThanOrEqual);
-                    ctx.emit(Inst::xmm_rm_r_imm(
-                        SseOpcode::Cmpps,
-                        RegMem::from(tmp1),
-                        tmp2,
-                        cond.encode(),
-                        OperandSize::Size32,
-                    ));
-
-                    // Convert those set of lanes that have the max_signed_int factored out.
-                    ctx.emit(Inst::xmm_rm_r(
-                        SseOpcode::Cvttps2dq,
-                        RegMem::from(tmp1),
-                        tmp1,
-                    ));
-
-                    // Prepare converted lanes by zeroing negative lanes and prepping lanes
-                    // that have positive overflow (based on the mask) by setting these lanes
-                    // to 0x7FFFFFFF
-                    ctx.emit(Inst::xmm_rm_r(SseOpcode::Pxor, RegMem::from(tmp2), tmp1));
-                    ctx.emit(Inst::xmm_rm_r(SseOpcode::Pxor, RegMem::from(tmp2), tmp2));
-                    ctx.emit(Inst::xmm_rm_r(SseOpcode::Pmaxsd, RegMem::from(tmp2), tmp1));
-
-                    // Add this second set of converted lanes to the original to properly handle
-                    // values greater than max signed int.
-                    ctx.emit(Inst::xmm_rm_r(SseOpcode::Paddd, RegMem::from(tmp1), dst));
-                } else {
-                    // Since this branch is also guarded by a check for vector types
-                    // neither Opcode::FcvtToUint nor Opcode::FcvtToSint can reach here
-                    // due to vector varients not existing. The first two branches will
-                    // cover all reachable cases.
-                    unreachable!();
-                }
-            }
-        }
-        Opcode::IaddPairwise => {
-            if let (Some(swiden_low), Some(swiden_high)) = (
-                matches_input(ctx, inputs[0], Opcode::SwidenLow),
-                matches_input(ctx, inputs[1], Opcode::SwidenHigh),
-            ) {
-                let swiden_input = &[
-                    InsnInput {
-                        insn: swiden_low,
-                        input: 0,
-                    },
-                    InsnInput {
-                        insn: swiden_high,
-                        input: 0,
-                    },
-                ];
-
-                let input_ty = ctx.input_ty(swiden_low, 0);
-                let output_ty = ctx.output_ty(insn, 0);
-                let src0 = put_input_in_reg(ctx, swiden_input[0]);
-                let src1 = put_input_in_reg(ctx, swiden_input[1]);
-                let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-                if src0 != src1 {
-                    unimplemented!(
-                        "iadd_pairwise not implemented for general case with different inputs"
-                    );
-                }
-                match (input_ty, output_ty) {
-                    (types::I8X16, types::I16X8) => {
-                        static MUL_CONST: [u8; 16] = [0x01; 16];
-                        let mul_const = ctx.use_constant(VCodeConstantData::WellKnown(&MUL_CONST));
-                        let mul_const_reg = ctx.alloc_tmp(types::I8X16).only_reg().unwrap();
-                        ctx.emit(Inst::xmm_load_const(mul_const, mul_const_reg, types::I8X16));
-                        ctx.emit(Inst::xmm_mov(
-                            SseOpcode::Movdqa,
-                            RegMem::reg(mul_const_reg.to_reg()),
-                            dst,
-                        ));
-                        ctx.emit(Inst::xmm_rm_r(SseOpcode::Pmaddubsw, RegMem::reg(src0), dst));
-                    }
-                    (types::I16X8, types::I32X4) => {
-                        static MUL_CONST: [u8; 16] = [
-                            0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00,
-                            0x01, 0x00, 0x01, 0x00,
-                        ];
-                        let mul_const = ctx.use_constant(VCodeConstantData::WellKnown(&MUL_CONST));
-                        let mul_const_reg = ctx.alloc_tmp(types::I16X8).only_reg().unwrap();
-                        ctx.emit(Inst::xmm_load_const(mul_const, mul_const_reg, types::I16X8));
-                        ctx.emit(Inst::xmm_mov(SseOpcode::Movdqa, RegMem::reg(src0), dst));
-                        ctx.emit(Inst::xmm_rm_r(
-                            SseOpcode::Pmaddwd,
-                            RegMem::reg(mul_const_reg.to_reg()),
-                            dst,
-                        ));
-                    }
-                    _ => {
-                        unimplemented!("Type not supported for {:?}", op);
-                    }
-                }
-            } else if let (Some(uwiden_low), Some(uwiden_high)) = (
-                matches_input(ctx, inputs[0], Opcode::UwidenLow),
-                matches_input(ctx, inputs[1], Opcode::UwidenHigh),
-            ) {
-                let uwiden_input = &[
-                    InsnInput {
-                        insn: uwiden_low,
-                        input: 0,
-                    },
-                    InsnInput {
-                        insn: uwiden_high,
-                        input: 0,
-                    },
-                ];
-
-                let input_ty = ctx.input_ty(uwiden_low, 0);
-                let output_ty = ctx.output_ty(insn, 0);
-                let src0 = put_input_in_reg(ctx, uwiden_input[0]);
-                let src1 = put_input_in_reg(ctx, uwiden_input[1]);
-                let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-                if src0 != src1 {
-                    unimplemented!(
-                        "iadd_pairwise not implemented for general case with different inputs"
-                    );
-                }
-                match (input_ty, output_ty) {
-                    (types::I8X16, types::I16X8) => {
-                        static MUL_CONST: [u8; 16] = [0x01; 16];
-                        let mul_const = ctx.use_constant(VCodeConstantData::WellKnown(&MUL_CONST));
-                        let mul_const_reg = ctx.alloc_tmp(types::I8X16).only_reg().unwrap();
-                        ctx.emit(Inst::xmm_load_const(mul_const, mul_const_reg, types::I8X16));
-                        ctx.emit(Inst::xmm_mov(SseOpcode::Movdqa, RegMem::reg(src0), dst));
-                        ctx.emit(Inst::xmm_rm_r(
-                            SseOpcode::Pmaddubsw,
-                            RegMem::reg(mul_const_reg.to_reg()),
-                            dst,
-                        ));
-                    }
-                    (types::I16X8, types::I32X4) => {
-                        static PXOR_CONST: [u8; 16] = [
-                            0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80,
-                            0x00, 0x80, 0x00, 0x80,
-                        ];
-                        let pxor_const =
-                            ctx.use_constant(VCodeConstantData::WellKnown(&PXOR_CONST));
-                        let pxor_const_reg = ctx.alloc_tmp(types::I16X8).only_reg().unwrap();
-                        ctx.emit(Inst::xmm_load_const(
-                            pxor_const,
-                            pxor_const_reg,
-                            types::I16X8,
-                        ));
-                        ctx.emit(Inst::xmm_mov(SseOpcode::Movdqa, RegMem::reg(src0), dst));
-                        ctx.emit(Inst::xmm_rm_r(
-                            SseOpcode::Pxor,
-                            RegMem::reg(pxor_const_reg.to_reg()),
-                            dst,
-                        ));
-
-                        static MADD_CONST: [u8; 16] = [
-                            0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00,
-                            0x01, 0x00, 0x01, 0x00,
-                        ];
-                        let madd_const =
-                            ctx.use_constant(VCodeConstantData::WellKnown(&MADD_CONST));
-                        let madd_const_reg = ctx.alloc_tmp(types::I8X16).only_reg().unwrap();
-                        ctx.emit(Inst::xmm_load_const(
-                            madd_const,
-                            madd_const_reg,
-                            types::I16X8,
-                        ));
-                        ctx.emit(Inst::xmm_rm_r(
-                            SseOpcode::Pmaddwd,
-                            RegMem::reg(madd_const_reg.to_reg()),
-                            dst,
-                        ));
-                        static ADDD_CONST2: [u8; 16] = [
-                            0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00,
-                            0x00, 0x00, 0x01, 0x00,
-                        ];
-                        let addd_const2 =
-                            ctx.use_constant(VCodeConstantData::WellKnown(&ADDD_CONST2));
-                        let addd_const2_reg = ctx.alloc_tmp(types::I8X16).only_reg().unwrap();
-                        ctx.emit(Inst::xmm_load_const(
-                            addd_const2,
-                            addd_const2_reg,
-                            types::I16X8,
-                        ));
-                        ctx.emit(Inst::xmm_rm_r(
-                            SseOpcode::Paddd,
-                            RegMem::reg(addd_const2_reg.to_reg()),
-                            dst,
-                        ));
-                    }
-                    _ => {
-                        unimplemented!("Type not supported for {:?}", op);
-                    }
-                }
-            } else {
-                unimplemented!("Operands not supported for {:?}", op);
-            }
-        }
-        Opcode::UwidenHigh | Opcode::UwidenLow | Opcode::SwidenHigh | Opcode::SwidenLow => {
-            let input_ty = ctx.input_ty(insn, 0);
-            let output_ty = ctx.output_ty(insn, 0);
-            let src = put_input_in_reg(ctx, inputs[0]);
-            let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            if output_ty.is_vector() {
-                match op {
-                    Opcode::SwidenLow => match (input_ty, output_ty) {
-                        (types::I8X16, types::I16X8) => {
-                            ctx.emit(Inst::xmm_mov(SseOpcode::Pmovsxbw, RegMem::reg(src), dst));
-                        }
-                        (types::I16X8, types::I32X4) => {
-                            ctx.emit(Inst::xmm_mov(SseOpcode::Pmovsxwd, RegMem::reg(src), dst));
-                        }
-                        (types::I32X4, types::I64X2) => {
-                            ctx.emit(Inst::xmm_mov(SseOpcode::Pmovsxdq, RegMem::reg(src), dst));
-                        }
-                        _ => unreachable!(),
-                    },
-                    Opcode::SwidenHigh => match (input_ty, output_ty) {
-                        (types::I8X16, types::I16X8) => {
-                            ctx.emit(Inst::gen_move(dst, src, output_ty));
-                            ctx.emit(Inst::xmm_rm_r_imm(
-                                SseOpcode::Palignr,
-                                RegMem::reg(src),
-                                dst,
-                                8,
-                                OperandSize::Size32,
-                            ));
-                            ctx.emit(Inst::xmm_mov(SseOpcode::Pmovsxbw, RegMem::from(dst), dst));
-                        }
-                        (types::I16X8, types::I32X4) => {
-                            ctx.emit(Inst::gen_move(dst, src, output_ty));
-                            ctx.emit(Inst::xmm_rm_r_imm(
-                                SseOpcode::Palignr,
-                                RegMem::reg(src),
-                                dst,
-                                8,
-                                OperandSize::Size32,
-                            ));
-                            ctx.emit(Inst::xmm_mov(SseOpcode::Pmovsxwd, RegMem::from(dst), dst));
-                        }
-                        (types::I32X4, types::I64X2) => {
-                            ctx.emit(Inst::xmm_rm_r_imm(
-                                SseOpcode::Pshufd,
-                                RegMem::reg(src),
-                                dst,
-                                0xEE,
-                                OperandSize::Size32,
-                            ));
-                            ctx.emit(Inst::xmm_mov(SseOpcode::Pmovsxdq, RegMem::from(dst), dst));
-                        }
-                        _ => unreachable!(),
-                    },
-                    Opcode::UwidenLow => match (input_ty, output_ty) {
-                        (types::I8X16, types::I16X8) => {
-                            ctx.emit(Inst::xmm_mov(SseOpcode::Pmovzxbw, RegMem::reg(src), dst));
-                        }
-                        (types::I16X8, types::I32X4) => {
-                            ctx.emit(Inst::xmm_mov(SseOpcode::Pmovzxwd, RegMem::reg(src), dst));
-                        }
-                        (types::I32X4, types::I64X2) => {
-                            ctx.emit(Inst::xmm_mov(SseOpcode::Pmovzxdq, RegMem::reg(src), dst));
-                        }
-                        _ => unreachable!(),
-                    },
-                    Opcode::UwidenHigh => match (input_ty, output_ty) {
-                        (types::I8X16, types::I16X8) => {
-                            ctx.emit(Inst::gen_move(dst, src, output_ty));
-                            ctx.emit(Inst::xmm_rm_r_imm(
-                                SseOpcode::Palignr,
-                                RegMem::reg(src),
-                                dst,
-                                8,
-                                OperandSize::Size32,
-                            ));
-                            ctx.emit(Inst::xmm_mov(SseOpcode::Pmovzxbw, RegMem::from(dst), dst));
-                        }
-                        (types::I16X8, types::I32X4) => {
-                            ctx.emit(Inst::gen_move(dst, src, output_ty));
-                            ctx.emit(Inst::xmm_rm_r_imm(
-                                SseOpcode::Palignr,
-                                RegMem::reg(src),
-                                dst,
-                                8,
-                                OperandSize::Size32,
-                            ));
-                            ctx.emit(Inst::xmm_mov(SseOpcode::Pmovzxwd, RegMem::from(dst), dst));
-                        }
-                        (types::I32X4, types::I64X2) => {
-                            ctx.emit(Inst::xmm_rm_r_imm(
-                                SseOpcode::Pshufd,
-                                RegMem::reg(src),
-                                dst,
-                                0xEE,
-                                OperandSize::Size32,
-                            ));
-                            ctx.emit(Inst::xmm_mov(SseOpcode::Pmovzxdq, RegMem::from(dst), dst));
-                        }
-                        _ => unreachable!(),
-                    },
-                    _ => unreachable!(),
-                }
-            } else {
-                panic!("Unsupported non-vector type for widen instruction {:?}", ty);
-            }
-        }
-        Opcode::Snarrow | Opcode::Unarrow => {
-            let input_ty = ctx.input_ty(insn, 0);
-            let output_ty = ctx.output_ty(insn, 0);
-            let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            if output_ty.is_vector() {
-                match op {
-                    Opcode::Snarrow => match (input_ty, output_ty) {
-                        (types::I16X8, types::I8X16) => {
-                            let src1 = put_input_in_reg(ctx, inputs[0]);
-                            let src2 = put_input_in_reg(ctx, inputs[1]);
-                            ctx.emit(Inst::gen_move(dst, src1, input_ty));
-                            ctx.emit(Inst::xmm_rm_r(SseOpcode::Packsswb, RegMem::reg(src2), dst));
-                        }
-                        (types::I32X4, types::I16X8) => {
-                            let src1 = put_input_in_reg(ctx, inputs[0]);
-                            let src2 = put_input_in_reg(ctx, inputs[1]);
-                            ctx.emit(Inst::gen_move(dst, src1, input_ty));
-                            ctx.emit(Inst::xmm_rm_r(SseOpcode::Packssdw, RegMem::reg(src2), dst));
-                        }
-                        // TODO: The type we are expecting as input as actually an F64X2 but the instruction is only defined
-                        // for integers so here we use I64X2. This is a separate issue that needs to be fixed in instruction.rs.
-                        (types::I64X2, types::I32X4) => {
-                            if let Some(fcvt_inst) =
-                                matches_input(ctx, inputs[0], Opcode::FcvtToSintSat)
-                            {
-                                //y = i32x4.trunc_sat_f64x2_s_zero(x) is lowered to:
-                                //MOVE xmm_tmp, xmm_x
-                                //CMPEQPD xmm_tmp, xmm_x
-                                //MOVE xmm_y, xmm_x
-                                //ANDPS xmm_tmp, [wasm_f64x2_splat(2147483647.0)]
-                                //MINPD xmm_y, xmm_tmp
-                                //CVTTPD2DQ xmm_y, xmm_y
-
-                                let fcvt_input = InsnInput {
-                                    insn: fcvt_inst,
-                                    input: 0,
-                                };
-                                let src = put_input_in_reg(ctx, fcvt_input);
-                                ctx.emit(Inst::gen_move(dst, src, input_ty));
-                                let tmp1 = ctx.alloc_tmp(output_ty).only_reg().unwrap();
-                                ctx.emit(Inst::gen_move(tmp1, src, input_ty));
-                                let cond = FcmpImm::from(FloatCC::Equal);
-                                ctx.emit(Inst::xmm_rm_r_imm(
-                                    SseOpcode::Cmppd,
-                                    RegMem::reg(src),
-                                    tmp1,
-                                    cond.encode(),
-                                    OperandSize::Size32,
-                                ));
-
-                                // 2147483647.0 is equivalent to 0x41DFFFFFFFC00000
-                                static UMAX_MASK: [u8; 16] = [
-                                    0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0xDF, 0x41, 0x00, 0x00,
-                                    0xC0, 0xFF, 0xFF, 0xFF, 0xDF, 0x41,
-                                ];
-                                let umax_const =
-                                    ctx.use_constant(VCodeConstantData::WellKnown(&UMAX_MASK));
-                                let umax_mask = ctx.alloc_tmp(types::F64X2).only_reg().unwrap();
-                                ctx.emit(Inst::xmm_load_const(umax_const, umax_mask, types::F64X2));
-
-                                //ANDPD xmm_y, [wasm_f64x2_splat(2147483647.0)]
-                                ctx.emit(Inst::xmm_rm_r(
-                                    SseOpcode::Andps,
-                                    RegMem::from(umax_mask),
-                                    tmp1,
-                                ));
-                                ctx.emit(Inst::xmm_rm_r(SseOpcode::Minpd, RegMem::from(tmp1), dst));
-                                ctx.emit(Inst::xmm_rm_r(
-                                    SseOpcode::Cvttpd2dq,
-                                    RegMem::from(dst),
-                                    dst,
-                                ));
-                            } else {
-                                unreachable!();
-                            }
-                        }
-                        _ => unreachable!(),
-                    },
-                    Opcode::Unarrow => match (input_ty, output_ty) {
-                        (types::I16X8, types::I8X16) => {
-                            let src1 = put_input_in_reg(ctx, inputs[0]);
-                            let src2 = put_input_in_reg(ctx, inputs[1]);
-                            ctx.emit(Inst::gen_move(dst, src1, input_ty));
-                            ctx.emit(Inst::xmm_rm_r(SseOpcode::Packuswb, RegMem::reg(src2), dst));
-                        }
-                        (types::I32X4, types::I16X8) => {
-                            let src1 = put_input_in_reg(ctx, inputs[0]);
-                            let src2 = put_input_in_reg(ctx, inputs[1]);
-                            ctx.emit(Inst::gen_move(dst, src1, input_ty));
-                            ctx.emit(Inst::xmm_rm_r(SseOpcode::Packusdw, RegMem::reg(src2), dst));
-                        }
-                        _ => unreachable!(),
-                    },
-                    _ => unreachable!(),
-                }
-            } else {
-                panic!("Unsupported non-vector type for widen instruction {:?}", ty);
-            }
-        }
-        Opcode::Bitcast => {
-            let input_ty = ctx.input_ty(insn, 0);
-            let output_ty = ctx.output_ty(insn, 0);
-            match (input_ty, output_ty) {
-                (types::F32, types::I32) => {
-                    let src = put_input_in_reg(ctx, inputs[0]);
-                    let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-                    ctx.emit(Inst::xmm_to_gpr(
-                        SseOpcode::Movd,
-                        src,
-                        dst,
-                        OperandSize::Size32,
-                    ));
-                }
-                (types::I32, types::F32) => {
-                    let src = input_to_reg_mem(ctx, inputs[0]);
-                    let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-                    ctx.emit(Inst::gpr_to_xmm(
-                        SseOpcode::Movd,
-                        src,
-                        OperandSize::Size32,
-                        dst,
-                    ));
-                }
-                (types::F64, types::I64) => {
-                    let src = put_input_in_reg(ctx, inputs[0]);
-                    let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-                    ctx.emit(Inst::xmm_to_gpr(
-                        SseOpcode::Movq,
-                        src,
-                        dst,
-                        OperandSize::Size64,
-                    ));
-                }
-                (types::I64, types::F64) => {
-                    let src = input_to_reg_mem(ctx, inputs[0]);
-                    let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-                    ctx.emit(Inst::gpr_to_xmm(
-                        SseOpcode::Movq,
-                        src,
-                        OperandSize::Size64,
-                        dst,
-                    ));
-                }
-                _ => unreachable!("invalid bitcast from {:?} to {:?}", input_ty, output_ty),
-            }
-        }
-
-        Opcode::Fabs | Opcode::Fneg => {
-            let src = RegMem::reg(put_input_in_reg(ctx, inputs[0]));
-            let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-
-            // In both cases, generate a constant and apply a single binary instruction:
-            // - to compute the absolute value, set all bits to 1 but the MSB to 0, and bit-AND the
-            // src with it.
-            // - to compute the negated value, set all bits to 0 but the MSB to 1, and bit-XOR the
-            // src with it.
-            let output_ty = ty.unwrap();
-            if !output_ty.is_vector() {
-                let (val, opcode): (u64, _) = match output_ty {
-                    types::F32 => match op {
-                        Opcode::Fabs => (0x7fffffff, SseOpcode::Andps),
-                        Opcode::Fneg => (0x80000000, SseOpcode::Xorps),
-                        _ => unreachable!(),
-                    },
-                    types::F64 => match op {
-                        Opcode::Fabs => (0x7fffffffffffffff, SseOpcode::Andpd),
-                        Opcode::Fneg => (0x8000000000000000, SseOpcode::Xorpd),
-                        _ => unreachable!(),
-                    },
-                    _ => panic!("unexpected type {:?} for Fabs", output_ty),
-                };
-
-                for inst in Inst::gen_constant(ValueRegs::one(dst), val as u128, output_ty, |ty| {
-                    ctx.alloc_tmp(ty).only_reg().unwrap()
-                }) {
-                    ctx.emit(inst);
-                }
-
-                ctx.emit(Inst::xmm_rm_r(opcode, src, dst));
-            } else {
-                // Eventually vector constants should be available in `gen_constant` and this block
-                // can be merged with the one above (TODO).
-                if output_ty.bits() == 128 {
-                    // Move the `lhs` to the same register as `dst`; this may not emit an actual move
-                    // but ensures that the registers are the same to match x86's read-write operand
-                    // encoding.
-                    let src = put_input_in_reg(ctx, inputs[0]);
-                    ctx.emit(Inst::gen_move(dst, src, output_ty));
-
-                    // Generate an all 1s constant in an XMM register. This uses CMPPS but could
-                    // have used CMPPD with the same effect. Note, we zero the temp we allocate
-                    // because if not, there is a chance that the register we use could be initialized
-                    // with NaN .. in which case the CMPPS would fail since NaN != NaN.
-                    let tmp = ctx.alloc_tmp(output_ty).only_reg().unwrap();
-                    ctx.emit(Inst::xmm_rm_r(SseOpcode::Xorps, RegMem::from(tmp), tmp));
-                    let cond = FcmpImm::from(FloatCC::Equal);
-                    let cmpps = Inst::xmm_rm_r_imm(
-                        SseOpcode::Cmpps,
-                        RegMem::reg(tmp.to_reg()),
-                        tmp,
-                        cond.encode(),
-                        OperandSize::Size32,
-                    );
-                    ctx.emit(cmpps);
-
-                    // Shift the all 1s constant to generate the mask.
-                    let lane_bits = output_ty.lane_bits();
-                    let (shift_opcode, opcode, shift_by) = match (op, lane_bits) {
-                        (Opcode::Fabs, _) => {
-                            unreachable!(
-                                "implemented in ISLE: inst = `{}`, type = `{:?}`",
-                                ctx.dfg().display_inst(insn),
-                                ty
-                            );
-                        }
-                        (Opcode::Fneg, 32) => (SseOpcode::Pslld, SseOpcode::Xorps, 31),
-                        (Opcode::Fneg, 64) => (SseOpcode::Psllq, SseOpcode::Xorpd, 63),
-                        _ => unreachable!(
-                            "unexpected opcode and lane size: {:?}, {} bits",
-                            op, lane_bits
-                        ),
-                    };
-                    let shift = Inst::xmm_rmi_reg(shift_opcode, RegMemImm::imm(shift_by), tmp);
-                    ctx.emit(shift);
-
-                    // Apply shifted mask (XOR or AND).
-                    let mask = Inst::xmm_rm_r(opcode, RegMem::reg(tmp.to_reg()), dst);
-                    ctx.emit(mask);
-                } else {
-                    panic!("unexpected type {:?} for Fabs", output_ty);
-                }
-            }
-        }
-
-        Opcode::Fcopysign => {
-            let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let lhs = put_input_in_reg(ctx, inputs[0]);
-            let rhs = put_input_in_reg(ctx, inputs[1]);
-
-            let ty = ty.unwrap();
-
-            // We're going to generate the following sequence:
-            //
-            // movabs     $INT_MIN, tmp_gpr1
-            // mov{d,q}   tmp_gpr1, tmp_xmm1
-            // movap{s,d} tmp_xmm1, dst
-            // andnp{s,d} src_1, dst
-            // movap{s,d} src_2, tmp_xmm2
-            // andp{s,d}  tmp_xmm1, tmp_xmm2
-            // orp{s,d}   tmp_xmm2, dst
-
-            let tmp_xmm1 = ctx.alloc_tmp(types::F32).only_reg().unwrap();
-            let tmp_xmm2 = ctx.alloc_tmp(types::F32).only_reg().unwrap();
-
-            let (sign_bit_cst, mov_op, and_not_op, and_op, or_op) = match ty {
-                types::F32 => (
-                    0x8000_0000,
-                    SseOpcode::Movaps,
-                    SseOpcode::Andnps,
-                    SseOpcode::Andps,
-                    SseOpcode::Orps,
-                ),
-                types::F64 => (
-                    0x8000_0000_0000_0000,
-                    SseOpcode::Movapd,
-                    SseOpcode::Andnpd,
-                    SseOpcode::Andpd,
-                    SseOpcode::Orpd,
-                ),
-                _ => {
-                    panic!("unexpected type {:?} for copysign", ty);
-                }
-            };
-
-            for inst in Inst::gen_constant(ValueRegs::one(tmp_xmm1), sign_bit_cst, ty, |ty| {
-                ctx.alloc_tmp(ty).only_reg().unwrap()
-            }) {
-                ctx.emit(inst);
-            }
-            ctx.emit(Inst::xmm_mov(mov_op, RegMem::reg(tmp_xmm1.to_reg()), dst));
-            ctx.emit(Inst::xmm_rm_r(and_not_op, RegMem::reg(lhs), dst));
-            ctx.emit(Inst::xmm_mov(mov_op, RegMem::reg(rhs), tmp_xmm2));
-            ctx.emit(Inst::xmm_rm_r(
-                and_op,
-                RegMem::reg(tmp_xmm1.to_reg()),
-                tmp_xmm2,
-            ));
-            ctx.emit(Inst::xmm_rm_r(or_op, RegMem::reg(tmp_xmm2.to_reg()), dst));
-        }
-
-        Opcode::Ceil | Opcode::Floor | Opcode::Nearest | Opcode::Trunc => {
-            let ty = ty.unwrap();
-            if isa_flags.use_sse41() {
-                let mode = match op {
-                    Opcode::Ceil => RoundImm::RoundUp,
-                    Opcode::Floor => RoundImm::RoundDown,
-                    Opcode::Nearest => RoundImm::RoundNearest,
-                    Opcode::Trunc => RoundImm::RoundZero,
-                    _ => panic!("unexpected opcode {:?} in Ceil/Floor/Nearest/Trunc", op),
-                };
-                let op = match ty {
-                    types::F32 => SseOpcode::Roundss,
-                    types::F64 => SseOpcode::Roundsd,
-                    types::F32X4 => SseOpcode::Roundps,
-                    types::F64X2 => SseOpcode::Roundpd,
-                    _ => panic!("unexpected type {:?} in Ceil/Floor/Nearest/Trunc", ty),
-                };
-                let src = input_to_reg_mem(ctx, inputs[0]);
-                let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-                ctx.emit(Inst::xmm_rm_r_imm(
-                    op,
-                    src,
-                    dst,
-                    mode.encode(),
-                    OperandSize::Size32,
-                ));
-            } else {
-                // Lower to VM calls when there's no access to SSE4.1.
-                // Note, for vector types on platforms that don't support sse41
-                // the execution will panic here.
-                let libcall = match (op, ty) {
-                    (Opcode::Ceil, types::F32) => LibCall::CeilF32,
-                    (Opcode::Ceil, types::F64) => LibCall::CeilF64,
-                    (Opcode::Floor, types::F32) => LibCall::FloorF32,
-                    (Opcode::Floor, types::F64) => LibCall::FloorF64,
-                    (Opcode::Nearest, types::F32) => LibCall::NearestF32,
-                    (Opcode::Nearest, types::F64) => LibCall::NearestF64,
-                    (Opcode::Trunc, types::F32) => LibCall::TruncF32,
-                    (Opcode::Trunc, types::F64) => LibCall::TruncF64,
-                    _ => panic!(
-                        "unexpected type/opcode {:?}/{:?} in Ceil/Floor/Nearest/Trunc",
-                        ty, op
-                    ),
-                };
-                emit_vm_call(ctx, flags, triple, libcall, insn, inputs, outputs)?;
-            }
-        }
-
-        Opcode::Load
-        | Opcode::Uload8
-        | Opcode::Sload8
-        | Opcode::Uload16
-        | Opcode::Sload16
-        | Opcode::Uload32
-        | Opcode::Sload32
-        | Opcode::LoadComplex
-        | Opcode::Uload8Complex
-        | Opcode::Sload8Complex
-        | Opcode::Uload16Complex
-        | Opcode::Sload16Complex
-        | Opcode::Uload32Complex
-        | Opcode::Sload32Complex
-        | Opcode::Sload8x8
-        | Opcode::Uload8x8
-        | Opcode::Sload16x4
-        | Opcode::Uload16x4
-        | Opcode::Sload32x2
-        | Opcode::Uload32x2 => {
-            let offset = ctx.data(insn).load_store_offset().unwrap();
-
-            let elem_ty = match op {
-                Opcode::Sload8 | Opcode::Uload8 | Opcode::Sload8Complex | Opcode::Uload8Complex => {
-                    types::I8
-                }
-                Opcode::Sload16
-                | Opcode::Uload16
-                | Opcode::Sload16Complex
-                | Opcode::Uload16Complex => types::I16,
-                Opcode::Sload32
-                | Opcode::Uload32
-                | Opcode::Sload32Complex
-                | Opcode::Uload32Complex => types::I32,
-                Opcode::Sload8x8
-                | Opcode::Uload8x8
-                | Opcode::Sload8x8Complex
-                | Opcode::Uload8x8Complex => types::I8X8,
-                Opcode::Sload16x4
-                | Opcode::Uload16x4
-                | Opcode::Sload16x4Complex
-                | Opcode::Uload16x4Complex => types::I16X4,
-                Opcode::Sload32x2
-                | Opcode::Uload32x2
-                | Opcode::Sload32x2Complex
-                | Opcode::Uload32x2Complex => types::I32X2,
-                Opcode::Load | Opcode::LoadComplex => ctx.output_ty(insn, 0),
-                _ => unimplemented!(),
-            };
-
-            let ext_mode = ExtMode::new(elem_ty.bits(), 64);
-
-            let sign_extend = match op {
-                Opcode::Sload8
-                | Opcode::Sload8Complex
-                | Opcode::Sload16
-                | Opcode::Sload16Complex
-                | Opcode::Sload32
-                | Opcode::Sload32Complex
-                | Opcode::Sload8x8
-                | Opcode::Sload8x8Complex
-                | Opcode::Sload16x4
-                | Opcode::Sload16x4Complex
-                | Opcode::Sload32x2
-                | Opcode::Sload32x2Complex => true,
-                _ => false,
-            };
-
-            let amode = match op {
-                Opcode::Load
-                | Opcode::Uload8
-                | Opcode::Sload8
-                | Opcode::Uload16
-                | Opcode::Sload16
-                | Opcode::Uload32
-                | Opcode::Sload32
-                | Opcode::Sload8x8
-                | Opcode::Uload8x8
-                | Opcode::Sload16x4
-                | Opcode::Uload16x4
-                | Opcode::Sload32x2
-                | Opcode::Uload32x2 => {
-                    assert_eq!(inputs.len(), 1, "only one input for load operands");
-                    lower_to_amode(ctx, inputs[0], offset)
-                }
-
-                Opcode::LoadComplex
-                | Opcode::Uload8Complex
-                | Opcode::Sload8Complex
-                | Opcode::Uload16Complex
-                | Opcode::Sload16Complex
-                | Opcode::Uload32Complex
-                | Opcode::Sload32Complex
-                | Opcode::Sload8x8Complex
-                | Opcode::Uload8x8Complex
-                | Opcode::Sload16x4Complex
-                | Opcode::Uload16x4Complex
-                | Opcode::Sload32x2Complex
-                | Opcode::Uload32x2Complex => {
-                    assert_eq!(
-                        inputs.len(),
-                        2,
-                        "can't handle more than two inputs in complex load"
-                    );
-                    let base = put_input_in_reg(ctx, inputs[0]);
-                    let index = put_input_in_reg(ctx, inputs[1]);
-                    let shift = 0;
-                    let flags = ctx.memflags(insn).expect("load should have memflags");
-                    Amode::imm_reg_reg_shift(
-                        offset as u32,
-                        Gpr::new(base).unwrap(),
-                        Gpr::new(index).unwrap(),
-                        shift,
-                    )
-                    .with_flags(flags)
-                }
-                _ => unreachable!(),
-            };
-
-            if elem_ty == types::I128 {
-                let dsts = get_output_reg(ctx, outputs[0]);
-                ctx.emit(Inst::mov64_m_r(amode.clone(), dsts.regs()[0]));
-                ctx.emit(Inst::mov64_m_r(amode.offset(8), dsts.regs()[1]));
-            } else {
-                let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-                let is_xmm = elem_ty.is_float() || elem_ty.is_vector();
-                match (sign_extend, is_xmm) {
-                    (true, false) => {
-                        // The load is sign-extended only when the output size is lower than 64 bits,
-                        // so ext-mode is defined in this case.
-                        ctx.emit(Inst::movsx_rm_r(ext_mode.unwrap(), RegMem::mem(amode), dst));
-                    }
-                    (false, false) => {
-                        if elem_ty.bytes() == 8 {
-                            // Use a plain load.
-                            ctx.emit(Inst::mov64_m_r(amode, dst))
-                        } else {
-                            // Use a zero-extended load.
-                            ctx.emit(Inst::movzx_rm_r(ext_mode.unwrap(), RegMem::mem(amode), dst))
-                        }
-                    }
-                    (_, true) => {
-                        ctx.emit(match elem_ty {
-                            types::F32 => Inst::xmm_mov(SseOpcode::Movss, RegMem::mem(amode), dst),
-                            types::F64 => Inst::xmm_mov(SseOpcode::Movsd, RegMem::mem(amode), dst),
-                            types::I8X8 => {
-                                if sign_extend == true {
-                                    Inst::xmm_mov(SseOpcode::Pmovsxbw, RegMem::mem(amode), dst)
-                                } else {
-                                    Inst::xmm_mov(SseOpcode::Pmovzxbw, RegMem::mem(amode), dst)
-                                }
-                            }
-                            types::I16X4 => {
-                                if sign_extend == true {
-                                    Inst::xmm_mov(SseOpcode::Pmovsxwd, RegMem::mem(amode), dst)
-                                } else {
-                                    Inst::xmm_mov(SseOpcode::Pmovzxwd, RegMem::mem(amode), dst)
-                                }
-                            }
-                            types::I32X2 => {
-                                if sign_extend == true {
-                                    Inst::xmm_mov(SseOpcode::Pmovsxdq, RegMem::mem(amode), dst)
-                                } else {
-                                    Inst::xmm_mov(SseOpcode::Pmovzxdq, RegMem::mem(amode), dst)
-                                }
-                            }
-                            _ if elem_ty.is_vector() && elem_ty.bits() == 128 => {
-                                Inst::xmm_mov(SseOpcode::Movups, RegMem::mem(amode), dst)
-                            }
-                            // TODO Specialize for different types: MOVUPD, MOVDQU
-                            _ => unreachable!(
-                                "unexpected type for load: {:?} - {:?}",
-                                elem_ty,
-                                elem_ty.bits()
-                            ),
-                        });
-                    }
-                }
-            }
-        }
-
-        Opcode::Store
-        | Opcode::Istore8
-        | Opcode::Istore16
-        | Opcode::Istore32
-        | Opcode::StoreComplex
-        | Opcode::Istore8Complex
-        | Opcode::Istore16Complex
-        | Opcode::Istore32Complex => {
-            let offset = ctx.data(insn).load_store_offset().unwrap();
-
-            let elem_ty = match op {
-                Opcode::Istore8 | Opcode::Istore8Complex => types::I8,
-                Opcode::Istore16 | Opcode::Istore16Complex => types::I16,
-                Opcode::Istore32 | Opcode::Istore32Complex => types::I32,
-                Opcode::Store | Opcode::StoreComplex => ctx.input_ty(insn, 0),
-                _ => unreachable!(),
-            };
-
-            let addr = match op {
-                Opcode::Store | Opcode::Istore8 | Opcode::Istore16 | Opcode::Istore32 => {
-                    assert_eq!(inputs.len(), 2, "only one input for store memory operands");
-                    lower_to_amode(ctx, inputs[1], offset)
-                }
-
-                Opcode::StoreComplex
-                | Opcode::Istore8Complex
-                | Opcode::Istore16Complex
-                | Opcode::Istore32Complex => {
-                    assert_eq!(
-                        inputs.len(),
-                        3,
-                        "can't handle more than two inputs in complex store"
-                    );
-                    let base = put_input_in_reg(ctx, inputs[1]);
-                    let index = put_input_in_reg(ctx, inputs[2]);
-                    let shift = 0;
-                    let flags = ctx.memflags(insn).expect("store should have memflags");
-                    Amode::imm_reg_reg_shift(
-                        offset as u32,
-                        Gpr::new(base).unwrap(),
-                        Gpr::new(index).unwrap(),
-                        shift,
-                    )
-                    .with_flags(flags)
-                }
-
-                _ => unreachable!(),
-            };
-
-            if elem_ty == types::I128 {
-                let srcs = put_input_in_regs(ctx, inputs[0]);
-                ctx.emit(Inst::store(types::I64, srcs.regs()[0], addr.clone()));
-                ctx.emit(Inst::store(types::I64, srcs.regs()[1], addr.offset(8)));
-            } else {
-                let src = put_input_in_reg(ctx, inputs[0]);
-                ctx.emit(Inst::store(elem_ty, src, addr));
-            }
-        }
-
-        Opcode::AtomicRmw => {
-            // This is a simple, general-case atomic update, based on a loop involving
-            // `cmpxchg`.  Note that we could do much better than this in the case where the old
-            // value at the location (that is to say, the SSA `Value` computed by this CLIF
-            // instruction) is not required.  In that case, we could instead implement this
-            // using a single `lock`-prefixed x64 read-modify-write instruction.  Also, even in
-            // the case where the old value is required, for the `add` and `sub` cases, we can
-            // use the single instruction `lock xadd`.  However, those improvements have been
-            // left for another day.
-            // TODO: filed as https://github.com/bytecodealliance/wasmtime/issues/2153
-            let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let mut addr = put_input_in_reg(ctx, inputs[0]);
-            let mut arg2 = put_input_in_reg(ctx, inputs[1]);
-            let ty_access = ty.unwrap();
-            assert!(is_valid_atomic_transaction_ty(ty_access));
-
-            // Make sure that both args are in virtual regs, since in effect we have to do a
-            // parallel copy to get them safely to the AtomicRmwSeq input regs, and that's not
-            // guaranteed safe if either is in a real reg.
-            addr = ctx.ensure_in_vreg(addr, types::I64);
-            arg2 = ctx.ensure_in_vreg(arg2, types::I64);
-
-            // Move the args to the preordained AtomicRMW input regs.  Note that `AtomicRmwSeq`
-            // operates at whatever width is specified by `ty`, so there's no need to
-            // zero-extend `arg2` in the case of `ty` being I8/I16/I32.
-            ctx.emit(Inst::gen_move(
-                Writable::from_reg(regs::r9()),
-                addr,
-                types::I64,
-            ));
-            ctx.emit(Inst::gen_move(
-                Writable::from_reg(regs::r10()),
-                arg2,
-                types::I64,
-            ));
-
-            // Now the AtomicRmwSeq (pseudo-) instruction itself
-            let op = inst_common::AtomicRmwOp::from(ctx.data(insn).atomic_rmw_op().unwrap());
-            ctx.emit(Inst::AtomicRmwSeq {
-                ty: ty_access,
-                op,
-                address: regs::r9(),
-                operand: regs::r10(),
-                temp: Writable::from_reg(regs::r11()),
-                dst_old: Writable::from_reg(regs::rax()),
-            });
-
-            // And finally, copy the preordained AtomicRmwSeq output reg to its destination.
-            ctx.emit(Inst::gen_move(dst, regs::rax(), types::I64));
-        }
-
-        Opcode::AtomicCas => {
-            // This is very similar to, but not identical to, the `AtomicRmw` case.  As with
-            // `AtomicRmw`, there's no need to zero-extend narrow values here.
-            let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let addr = lower_to_amode(ctx, inputs[0], 0);
-            let expected = put_input_in_reg(ctx, inputs[1]);
-            let replacement = put_input_in_reg(ctx, inputs[2]);
-            let ty_access = ty.unwrap();
-            assert!(is_valid_atomic_transaction_ty(ty_access));
-
-            // Move the expected value into %rax.  Because there's only one fixed register on
-            // the input side, we don't have to use `ensure_in_vreg`, as is necessary in the
-            // `AtomicRmw` case.
-            ctx.emit(Inst::gen_move(
-                Writable::from_reg(regs::rax()),
-                expected,
-                types::I64,
-            ));
-            ctx.emit(Inst::LockCmpxchg {
-                ty: ty_access,
-                mem: addr.into(),
-                replacement,
-                expected: regs::rax(),
-                dst_old: Writable::from_reg(regs::rax()),
-            });
-            // And finally, copy the old value at the location to its destination reg.
-            ctx.emit(Inst::gen_move(dst, regs::rax(), types::I64));
-        }
-
-        Opcode::AtomicLoad => {
-            // This is a normal load.  The x86-TSO memory model provides sufficient sequencing
-            // to satisfy the CLIF synchronisation requirements for `AtomicLoad` without the
-            // need for any fence instructions.
-            let data = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let addr = lower_to_amode(ctx, inputs[0], 0);
-            let ty_access = ty.unwrap();
-            assert!(is_valid_atomic_transaction_ty(ty_access));
-
-            let rm = RegMem::mem(addr);
-            if ty_access == types::I64 {
-                ctx.emit(Inst::mov64_rm_r(rm, data));
-            } else {
-                let ext_mode = ExtMode::new(ty_access.bits(), 64).unwrap_or_else(|| {
-                    panic!(
-                        "invalid extension during AtomicLoad: {} -> {}",
-                        ty_access.bits(),
-                        64
-                    )
-                });
-                ctx.emit(Inst::movzx_rm_r(ext_mode, rm, data));
-            }
-        }
-
-        Opcode::AtomicStore => {
-            // This is a normal store, followed by an `mfence` instruction.
-            let data = put_input_in_reg(ctx, inputs[0]);
-            let addr = lower_to_amode(ctx, inputs[1], 0);
-            let ty_access = ctx.input_ty(insn, 0);
-            assert!(is_valid_atomic_transaction_ty(ty_access));
-
-            ctx.emit(Inst::store(ty_access, data, addr));
-            ctx.emit(Inst::Fence {
-                kind: FenceKind::MFence,
-            });
-        }
-
-        Opcode::Fence => {
-            ctx.emit(Inst::Fence {
-                kind: FenceKind::MFence,
-            });
-        }
-
-        Opcode::FuncAddr => {
-            let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let (extname, _) = ctx.call_target(insn).unwrap();
-            let extname = extname.clone();
-            ctx.emit(Inst::LoadExtName {
-                dst,
-                name: Box::new(extname),
-                offset: 0,
-            });
-        }
-
-        Opcode::SymbolValue => {
-            let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let (extname, _, offset) = ctx.symbol_value(insn).unwrap();
-            let extname = extname.clone();
-            ctx.emit(Inst::LoadExtName {
-                dst,
-                name: Box::new(extname),
-                offset,
-            });
-        }
-
-        Opcode::StackAddr => {
-            let (stack_slot, offset) = match *ctx.data(insn) {
-                InstructionData::StackLoad {
-                    opcode: Opcode::StackAddr,
-                    stack_slot,
-                    offset,
-                } => (stack_slot, offset),
-                _ => unreachable!(),
-            };
-            let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let offset: i32 = offset.into();
-            let inst = ctx
-                .abi()
-                .stackslot_addr(stack_slot, u32::try_from(offset).unwrap(), dst);
-            ctx.emit(inst);
-        }
-
-        Opcode::Select => {
-            let flag_input = inputs[0];
-            if let Some(_) = matches_input(ctx, flag_input, Opcode::Fcmp) {
-                implemented_in_isle(ctx);
-            } else {
-                let ty = ty.unwrap();
-
-                let size = ty.bytes() as u8;
-                let lhs = put_input_in_regs(ctx, inputs[1]);
-                let rhs = put_input_in_regs(ctx, inputs[2]);
-                let dst = get_output_reg(ctx, outputs[0]);
-
-                let cc = if let Some(icmp) = matches_input(ctx, flag_input, Opcode::Icmp) {
-                    let cond_code = ctx.data(icmp).cond_code().unwrap();
-                    let cond_code = emit_cmp(ctx, icmp, cond_code);
-                    CC::from_intcc(cond_code)
-                } else {
-                    let sel_ty = ctx.input_ty(insn, 0);
-                    let size = OperandSize::from_ty(ctx.input_ty(insn, 0));
-                    let test = put_input_in_reg(ctx, flag_input);
-                    let test_input = if sel_ty == types::B1 {
-                        // The input is a boolean value; test the LSB for nonzero with:
-                        //     test reg, 1
-                        RegMemImm::imm(1)
-                    } else {
-                        // The input is an integer; test the whole value for
-                        // nonzero with:
-                        //     test reg, reg
-                        //
-                        // (It doesn't make sense to have a boolean wider than
-                        // one bit here -- which bit would cause us to select an
-                        // input?)
-                        assert!(!is_bool_ty(sel_ty));
-                        RegMemImm::reg(test)
-                    };
-                    ctx.emit(Inst::test_rmi_r(size, test_input, test));
-                    CC::NZ
-                };
-
-                // This doesn't affect the flags.
-                emit_moves(ctx, dst, rhs, ty);
-
-                if is_int_or_ref_ty(ty) || ty == types::I128 {
-                    emit_cmoves(ctx, size, cc, lhs, dst);
-                } else {
-                    debug_assert!(
-                        ty == types::F32
-                            || ty == types::F64
-                            || (ty.is_vector() && ty.bits() == 128)
-                    );
-                    ctx.emit(Inst::xmm_cmove(
-                        if ty == types::F64 {
-                            OperandSize::Size64
-                        } else {
-                            OperandSize::Size32
-                        },
-                        cc,
-                        RegMem::reg(lhs.only_reg().unwrap()),
-                        dst.only_reg().unwrap(),
-                    ));
-                }
-            }
-        }
-
-        Opcode::Selectif | Opcode::SelectifSpectreGuard => {
-            let lhs = put_input_in_regs(ctx, inputs[1]);
-            let rhs = put_input_in_regs(ctx, inputs[2]);
-            let dst = get_output_reg(ctx, outputs[0]);
-            let ty = ctx.output_ty(insn, 0);
-
-            // Verification ensures that the input is always a single-def ifcmp.
-            let cmp_insn = ctx
-                .get_input_as_source_or_const(inputs[0].insn, inputs[0].input)
-                .inst
-                .unwrap()
-                .0;
-            debug_assert_eq!(ctx.data(cmp_insn).opcode(), Opcode::Ifcmp);
-            let cond_code = ctx.data(insn).cond_code().unwrap();
-            let cond_code = emit_cmp(ctx, cmp_insn, cond_code);
-
-            let cc = CC::from_intcc(cond_code);
-
-            if is_int_or_ref_ty(ty) || ty == types::I128 {
-                let size = ty.bytes() as u8;
-                emit_moves(ctx, dst, rhs, ty);
-                emit_cmoves(ctx, size, cc, lhs, dst);
-            } else {
-                debug_assert!(ty == types::F32 || ty == types::F64);
-                emit_moves(ctx, dst, rhs, ty);
-                ctx.emit(Inst::xmm_cmove(
-                    if ty == types::F64 {
-                        OperandSize::Size64
-                    } else {
-                        OperandSize::Size32
-                    },
-                    cc,
-                    RegMem::reg(lhs.only_reg().unwrap()),
-                    dst.only_reg().unwrap(),
-                ));
-            }
-        }
-
-        Opcode::Udiv | Opcode::Urem | Opcode::Sdiv | Opcode::Srem => {
-            let kind = match op {
-                Opcode::Udiv => DivOrRemKind::UnsignedDiv,
-                Opcode::Sdiv => DivOrRemKind::SignedDiv,
-                Opcode::Urem => DivOrRemKind::UnsignedRem,
-                Opcode::Srem => DivOrRemKind::SignedRem,
-                _ => unreachable!(),
-            };
-            let is_div = kind.is_div();
-
-            let input_ty = ctx.input_ty(insn, 0);
-            let size = OperandSize::from_ty(input_ty);
-
-            let dividend = put_input_in_reg(ctx, inputs[0]);
-            let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-
-            ctx.emit(Inst::gen_move(
-                Writable::from_reg(regs::rax()),
-                dividend,
-                input_ty,
-            ));
-
-            // Always do explicit checks for `srem`: otherwise, INT_MIN % -1 is not handled properly.
-            if flags.avoid_div_traps() || op == Opcode::Srem {
-                // A vcode meta-instruction is used to lower the inline checks, since they embed
-                // pc-relative offsets that must not change, thus requiring regalloc to not
-                // interfere by introducing spills and reloads.
-                //
-                // Note it keeps the result in $rax (for divide) or $rdx (for rem), so that
-                // regalloc is aware of the coalescing opportunity between rax/rdx and the
-                // destination register.
-                let divisor = put_input_in_reg(ctx, inputs[1]);
-
-                let divisor_copy = ctx.alloc_tmp(types::I64).only_reg().unwrap();
-                ctx.emit(Inst::gen_move(divisor_copy, divisor, types::I64));
-
-                let tmp = if op == Opcode::Sdiv && size == OperandSize::Size64 {
-                    Some(ctx.alloc_tmp(types::I64).only_reg().unwrap())
-                } else {
-                    None
-                };
-                // TODO use xor
-                ctx.emit(Inst::imm(
-                    OperandSize::Size32,
-                    0,
-                    Writable::from_reg(regs::rdx()),
-                ));
-                ctx.emit(Inst::checked_div_or_rem_seq(kind, size, divisor_copy, tmp));
-            } else {
-                // We don't want more than one trap record for a single instruction,
-                // so let's not allow the "mem" case (load-op merging) here; force
-                // divisor into a register instead.
-                let divisor = RegMem::reg(put_input_in_reg(ctx, inputs[1]));
-
-                // Fill in the high parts:
-                if kind.is_signed() {
-                    // sign-extend the sign-bit of al into ah for size 1, or rax into rdx, for
-                    // signed opcodes.
-                    ctx.emit(Inst::sign_extend_data(size));
-                } else if input_ty == types::I8 {
-                    ctx.emit(Inst::movzx_rm_r(
-                        ExtMode::BL,
-                        RegMem::reg(regs::rax()),
-                        Writable::from_reg(regs::rax()),
-                    ));
-                } else {
-                    // zero for unsigned opcodes.
-                    ctx.emit(Inst::imm(
-                        OperandSize::Size64,
-                        0,
-                        Writable::from_reg(regs::rdx()),
-                    ));
-                }
-
-                // Emit the actual idiv.
-                ctx.emit(Inst::div(size, kind.is_signed(), divisor));
-            }
-
-            // Move the result back into the destination reg.
-            if is_div {
-                // The quotient is in rax.
-                ctx.emit(Inst::gen_move(dst, regs::rax(), input_ty));
-            } else {
-                if size == OperandSize::Size8 {
-                    // The remainder is in AH. Right-shift by 8 bits then move from rax.
-                    ctx.emit(Inst::shift_r(
-                        OperandSize::Size64,
-                        ShiftKind::ShiftRightLogical,
-                        Some(8),
-                        Writable::from_reg(regs::rax()),
-                    ));
-                    ctx.emit(Inst::gen_move(dst, regs::rax(), input_ty));
-                } else {
-                    // The remainder is in rdx.
-                    ctx.emit(Inst::gen_move(dst, regs::rdx(), input_ty));
-                }
-            }
-        }
-
-        Opcode::Umulhi | Opcode::Smulhi => {
-            let input_ty = ctx.input_ty(insn, 0);
-
-            let lhs = put_input_in_reg(ctx, inputs[0]);
-            let rhs = input_to_reg_mem(ctx, inputs[1]);
-            let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-
-            // Move lhs in %rax.
-            ctx.emit(Inst::gen_move(
-                Writable::from_reg(regs::rax()),
-                lhs,
-                input_ty,
-            ));
-
-            // Emit the actual mul or imul.
-            let signed = op == Opcode::Smulhi;
-            ctx.emit(Inst::mul_hi(OperandSize::from_ty(input_ty), signed, rhs));
-
-            // Read the result from the high part (stored in %rdx).
-            ctx.emit(Inst::gen_move(dst, regs::rdx(), input_ty));
-        }
-
-        Opcode::GetPinnedReg => {
-            let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            ctx.emit(Inst::gen_move(dst, regs::pinned_reg(), types::I64));
-        }
-
-        Opcode::SetPinnedReg => {
-            let src = put_input_in_reg(ctx, inputs[0]);
-            ctx.emit(Inst::gen_move(
-                Writable::from_reg(regs::pinned_reg()),
-                src,
-                types::I64,
-            ));
-        }
-
-        Opcode::Vconst => {
-            let used_constant = if let &InstructionData::UnaryConst {
-                constant_handle, ..
-            } = ctx.data(insn)
-            {
-                ctx.use_constant(VCodeConstantData::Pool(
-                    constant_handle,
-                    ctx.get_constant_data(constant_handle).clone(),
-                ))
-            } else {
-                unreachable!("vconst should always have unary_const format")
-            };
-            // TODO use Inst::gen_constant() instead.
-            let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let ty = ty.unwrap();
-            ctx.emit(Inst::xmm_load_const(used_constant, dst, ty));
-        }
-
-        Opcode::RawBitcast => {
-            // A raw_bitcast is just a mechanism for correcting the type of V128 values (see
-            // https://github.com/bytecodealliance/wasmtime/issues/1147). As such, this IR
-            // instruction should emit no machine code but a move is necessary to give the register
-            // allocator a definition for the output virtual register.
-            let src = put_input_in_reg(ctx, inputs[0]);
-            let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let ty = ty.unwrap();
-            ctx.emit(Inst::gen_move(dst, src, ty));
-        }
-
-        Opcode::Shuffle => {
-            let ty = ty.unwrap();
-            let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let lhs_ty = ctx.input_ty(insn, 0);
-            let lhs = put_input_in_reg(ctx, inputs[0]);
-            let rhs = put_input_in_reg(ctx, inputs[1]);
-            let mask = match ctx.get_immediate(insn) {
-                Some(DataValue::V128(bytes)) => bytes.to_vec(),
-                _ => unreachable!("shuffle should always have a 16-byte immediate"),
-            };
-
-            // A mask-building helper: in 128-bit SIMD, 0-15 indicate which lane to read from and a
-            // 1 in the most significant position zeroes the lane.
-            let zero_unknown_lane_index = |b: u8| if b > 15 { 0b10000000 } else { b };
-
-            ctx.emit(Inst::gen_move(dst, rhs, ty));
-            if rhs == lhs {
-                // If `lhs` and `rhs` are the same we can use a single PSHUFB to shuffle the XMM
-                // register. We statically build `constructed_mask` to zero out any unknown lane
-                // indices (may not be completely necessary: verification could fail incorrect mask
-                // values) and fix the indexes to all point to the `dst` vector.
-                let constructed_mask = mask
-                    .iter()
-                    // If the mask is greater than 15 it still may be referring to a lane in b.
-                    .map(|&b| if b > 15 { b.wrapping_sub(16) } else { b })
-                    .map(zero_unknown_lane_index)
-                    .collect();
-                let constant = ctx.use_constant(VCodeConstantData::Generated(constructed_mask));
-                let tmp = ctx.alloc_tmp(types::I8X16).only_reg().unwrap();
-                ctx.emit(Inst::xmm_load_const(constant, tmp, ty));
-                // After loading the constructed mask in a temporary register, we use this to
-                // shuffle the `dst` register (remember that, in this case, it is the same as
-                // `src` so we disregard this register).
-                ctx.emit(Inst::xmm_rm_r(SseOpcode::Pshufb, RegMem::from(tmp), dst));
-            } else {
-                if isa_flags.use_avx512vl_simd() && isa_flags.use_avx512vbmi_simd() {
-                    assert!(
-                        mask.iter().all(|b| *b < 32),
-                        "shuffle mask values must be between 0 and 31"
-                    );
-
-                    // Load the mask into the destination register.
-                    let constant = ctx.use_constant(VCodeConstantData::Generated(mask.into()));
-                    ctx.emit(Inst::xmm_load_const(constant, dst, ty));
-
-                    // VPERMI2B has the exact semantics of Wasm's shuffle:
-                    // permute the bytes in `src1` and `src2` using byte indexes
-                    // in `dst` and store the byte results in `dst`.
-                    ctx.emit(Inst::xmm_rm_r_evex(
-                        Avx512Opcode::Vpermi2b,
-                        RegMem::reg(rhs),
-                        lhs,
-                        dst,
-                    ));
-                } else {
-                    // If `lhs` and `rhs` are different, we must shuffle each separately and then OR
-                    // them together. This is necessary due to PSHUFB semantics. As in the case above,
-                    // we build the `constructed_mask` for each case statically.
-
-                    // PSHUFB the `lhs` argument into `tmp0`, placing zeroes for unused lanes.
-                    let tmp0 = ctx.alloc_tmp(lhs_ty).only_reg().unwrap();
-                    ctx.emit(Inst::gen_move(tmp0, lhs, lhs_ty));
-                    let constructed_mask =
-                        mask.iter().cloned().map(zero_unknown_lane_index).collect();
-                    let constant = ctx.use_constant(VCodeConstantData::Generated(constructed_mask));
-                    let tmp1 = ctx.alloc_tmp(types::I8X16).only_reg().unwrap();
-                    ctx.emit(Inst::xmm_load_const(constant, tmp1, ty));
-                    ctx.emit(Inst::xmm_rm_r(SseOpcode::Pshufb, RegMem::from(tmp1), tmp0));
-
-                    // PSHUFB the second argument, placing zeroes for unused lanes.
-                    let constructed_mask = mask
-                        .iter()
-                        .map(|b| b.wrapping_sub(16))
-                        .map(zero_unknown_lane_index)
-                        .collect();
-                    let constant = ctx.use_constant(VCodeConstantData::Generated(constructed_mask));
-                    let tmp2 = ctx.alloc_tmp(types::I8X16).only_reg().unwrap();
-                    ctx.emit(Inst::xmm_load_const(constant, tmp2, ty));
-                    ctx.emit(Inst::xmm_rm_r(SseOpcode::Pshufb, RegMem::from(tmp2), dst));
-
-                    // OR the shuffled registers (the mechanism and lane-size for OR-ing the registers
-                    // is not important).
-                    ctx.emit(Inst::xmm_rm_r(SseOpcode::Orps, RegMem::from(tmp0), dst));
-                }
-            }
-        }
-
-        Opcode::Swizzle => {
-            // SIMD swizzle; the following inefficient implementation is due to the Wasm SIMD spec
-            // requiring mask indexes greater than 15 to have the same semantics as a 0 index. For
-            // the spec discussion, see https://github.com/WebAssembly/simd/issues/93. The CLIF
-            // semantics match the Wasm SIMD semantics for this instruction.
-            // The instruction format maps to variables like: %dst = swizzle %src, %mask
-            let ty = ty.unwrap();
-            let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let src = put_input_in_reg(ctx, inputs[0]);
-            let swizzle_mask = put_input_in_reg(ctx, inputs[1]);
-
-            // Inform the register allocator that `src` and `dst` should be in the same register.
-            ctx.emit(Inst::gen_move(dst, src, ty));
-
-            // Create a mask for zeroing out-of-bounds lanes of the swizzle mask.
-            let zero_mask = ctx.alloc_tmp(types::I8X16).only_reg().unwrap();
-            static ZERO_MASK_VALUE: [u8; 16] = [
-                0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70,
-                0x70, 0x70,
-            ];
-            let constant = ctx.use_constant(VCodeConstantData::WellKnown(&ZERO_MASK_VALUE));
-            ctx.emit(Inst::xmm_load_const(constant, zero_mask, ty));
-
-            // Use the `zero_mask` on a writable `swizzle_mask`.
-            let swizzle_mask = Writable::from_reg(swizzle_mask);
-            ctx.emit(Inst::xmm_rm_r(
-                SseOpcode::Paddusb,
-                RegMem::from(zero_mask),
-                swizzle_mask,
-            ));
-
-            // Shuffle `dst` using the fixed-up `swizzle_mask`.
-            ctx.emit(Inst::xmm_rm_r(
-                SseOpcode::Pshufb,
-                RegMem::from(swizzle_mask),
-                dst,
-            ));
-        }
-
-        Opcode::Insertlane => {
-            unreachable!(
-                "implemented in ISLE: inst = `{}`, type = `{:?}`",
-                ctx.dfg().display_inst(insn),
-                ty
-            );
-        }
-
-        Opcode::Extractlane => {
-            // The instruction format maps to variables like: %dst = extractlane %src, %lane
-            let ty = ty.unwrap();
-            let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let src_ty = ctx.input_ty(insn, 0);
-            assert_eq!(src_ty.bits(), 128);
-            let src = put_input_in_reg(ctx, inputs[0]);
-            let lane = if let InstructionData::BinaryImm8 { imm, .. } = ctx.data(insn) {
-                *imm
-            } else {
-                unreachable!();
-            };
-            debug_assert!(lane < src_ty.lane_count() as u8);
-
-            emit_extract_lane(ctx, src, dst, lane, ty);
-        }
-
-        Opcode::ScalarToVector => {
-            // When moving a scalar value to a vector register, we must be handle several
-            // situations:
-            //  1. a scalar float is already in an XMM register, so we simply move it
-            //  2. a scalar of any other type resides in a GPR register: MOVD moves the bits to an
-            //     XMM register and zeroes the upper bits
-            //  3. a scalar (float or otherwise) that has previously been loaded from memory (e.g.
-            //     the default lowering of Wasm's `load[32|64]_zero`) can be lowered to a single
-            //     MOVSS/MOVSD instruction; to do this, we rely on `input_to_reg_mem` to sink the
-            //     unused load.
-            let src = input_to_reg_mem(ctx, inputs[0]);
-            let src_ty = ctx.input_ty(insn, 0);
-            let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let dst_ty = ty.unwrap();
-            assert!(src_ty == dst_ty.lane_type() && dst_ty.bits() == 128);
-            match src {
-                RegMem::Reg { reg } => {
-                    if src_ty.is_float() {
-                        // Case 1: when moving a scalar float, we simply move from one XMM register
-                        // to another, expecting the register allocator to elide this. Here we
-                        // assume that the upper bits of a scalar float have not been munged with
-                        // (the same assumption the old backend makes).
-                        ctx.emit(Inst::gen_move(dst, reg, dst_ty));
-                    } else {
-                        // Case 2: when moving a scalar value of any other type, use MOVD to zero
-                        // the upper lanes.
-                        let src_size = match src_ty.bits() {
-                            32 => OperandSize::Size32,
-                            64 => OperandSize::Size64,
-                            _ => unimplemented!("invalid source size for type: {}", src_ty),
-                        };
-                        ctx.emit(Inst::gpr_to_xmm(SseOpcode::Movd, src, src_size, dst));
-                    }
-                }
-                RegMem::Mem { .. } => {
-                    // Case 3: when presented with `load + scalar_to_vector`, coalesce into a single
-                    // MOVSS/MOVSD instruction.
-                    let opcode = match src_ty.bits() {
-                        32 => SseOpcode::Movss,
-                        64 => SseOpcode::Movsd,
-                        _ => unimplemented!("unable to move scalar to vector for type: {}", src_ty),
-                    };
-                    ctx.emit(Inst::xmm_mov(opcode, src, dst));
-                }
-            }
-        }
-
-        Opcode::Splat => {
-            let ty = ty.unwrap();
-            assert_eq!(ty.bits(), 128);
-            let src_ty = ctx.input_ty(insn, 0);
-            assert!(src_ty.bits() < 128);
-
-            let src = input_to_reg_mem(ctx, inputs[0]);
-            let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-
-            // We know that splat will overwrite all of the lanes of `dst` but it takes several
-            // instructions to do so. Because of the multiple instructions, there is no good way to
-            // declare `dst` a `def` except with the following pseudo-instruction.
-            ctx.emit(Inst::xmm_uninit_value(dst));
-
-            // TODO: eventually many of these sequences could be optimized with AVX's VBROADCAST*
-            // and VPBROADCAST*.
-            match ty.lane_bits() {
-                8 => {
-                    emit_insert_lane(ctx, src, dst, 0, ty.lane_type());
-                    // Initialize a register with all 0s.
-                    let tmp = ctx.alloc_tmp(ty).only_reg().unwrap();
-                    ctx.emit(Inst::xmm_rm_r(SseOpcode::Pxor, RegMem::from(tmp), tmp));
-                    // Shuffle the lowest byte lane to all other lanes.
-                    ctx.emit(Inst::xmm_rm_r(SseOpcode::Pshufb, RegMem::from(tmp), dst))
-                }
-                16 => {
-                    emit_insert_lane(ctx, src.clone(), dst, 0, ty.lane_type());
-                    emit_insert_lane(ctx, src, dst, 1, ty.lane_type());
-                    // Shuffle the lowest two lanes to all other lanes.
-                    ctx.emit(Inst::xmm_rm_r_imm(
-                        SseOpcode::Pshufd,
-                        RegMem::from(dst),
-                        dst,
-                        0,
-                        OperandSize::Size32,
-                    ))
-                }
-                32 => {
-                    emit_insert_lane(ctx, src, dst, 0, ty.lane_type());
-                    // Shuffle the lowest lane to all other lanes.
-                    ctx.emit(Inst::xmm_rm_r_imm(
-                        SseOpcode::Pshufd,
-                        RegMem::from(dst),
-                        dst,
-                        0,
-                        OperandSize::Size32,
-                    ))
-                }
-                64 => {
-                    emit_insert_lane(ctx, src.clone(), dst, 0, ty.lane_type());
-                    emit_insert_lane(ctx, src, dst, 1, ty.lane_type());
-                }
-                _ => panic!("Invalid type to splat: {}", ty),
-            }
-        }
-
-        Opcode::VanyTrue => {
-            let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let src_ty = ctx.input_ty(insn, 0);
-            assert_eq!(src_ty.bits(), 128);
-            let src = put_input_in_reg(ctx, inputs[0]);
-            // Set the ZF if the result is all zeroes.
-            ctx.emit(Inst::xmm_cmp_rm_r(SseOpcode::Ptest, RegMem::reg(src), src));
-            // If the ZF is not set, place a 1 in `dst`.
-            ctx.emit(Inst::setcc(CC::NZ, dst));
-        }
-
-        Opcode::VallTrue => {
-            let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let src_ty = ctx.input_ty(insn, 0);
-            assert_eq!(src_ty.bits(), 128);
-            let src = input_to_reg_mem(ctx, inputs[0]);
-
-            let eq = |ty: Type| match ty.lane_bits() {
-                8 => SseOpcode::Pcmpeqb,
-                16 => SseOpcode::Pcmpeqw,
-                32 => SseOpcode::Pcmpeqd,
-                64 => SseOpcode::Pcmpeqq,
-                _ => panic!("Unable to find an instruction for {} for type: {}", op, ty),
-            };
-
-            // Initialize a register with all 0s.
-            let tmp = ctx.alloc_tmp(src_ty).only_reg().unwrap();
-            ctx.emit(Inst::xmm_rm_r(SseOpcode::Pxor, RegMem::from(tmp), tmp));
-            // Compare to see what lanes are filled with all 1s.
-            ctx.emit(Inst::xmm_rm_r(eq(src_ty), src, tmp));
-            // Set the ZF if the result is all zeroes.
-            ctx.emit(Inst::xmm_cmp_rm_r(
-                SseOpcode::Ptest,
-                RegMem::from(tmp),
-                tmp.to_reg(),
-            ));
-            // If the ZF is set, place a 1 in `dst`.
-            ctx.emit(Inst::setcc(CC::Z, dst));
-        }
-
-        Opcode::VhighBits => {
-            let src = put_input_in_reg(ctx, inputs[0]);
-            let src_ty = ctx.input_ty(insn, 0);
-            debug_assert!(src_ty.is_vector() && src_ty.bits() == 128);
-            let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            debug_assert!(dst.to_reg().get_class() == RegClass::I64);
-
-            // The Intel specification allows using both 32-bit and 64-bit GPRs as destination for
-            // the "move mask" instructions. This is controlled by the REX.R bit: "In 64-bit mode,
-            // the instruction can access additional registers when used with a REX.R prefix. The
-            // default operand size is 64-bit in 64-bit mode" (PMOVMSKB in IA Software Development
-            // Manual, vol. 2). This being the case, we will always clear REX.W since its use is
-            // unnecessary (`OperandSize` is used for setting/clearing REX.W).
-            let size = OperandSize::Size32;
-
-            match src_ty {
-                types::I8X16 | types::B8X16 => {
-                    ctx.emit(Inst::xmm_to_gpr(SseOpcode::Pmovmskb, src, dst, size))
-                }
-                types::I32X4 | types::B32X4 | types::F32X4 => {
-                    ctx.emit(Inst::xmm_to_gpr(SseOpcode::Movmskps, src, dst, size))
-                }
-                types::I64X2 | types::B64X2 | types::F64X2 => {
-                    ctx.emit(Inst::xmm_to_gpr(SseOpcode::Movmskpd, src, dst, size))
-                }
-                types::I16X8 | types::B16X8 => {
-                    // There is no x86 instruction for extracting the high bit of 16-bit lanes so
-                    // here we:
-                    // - duplicate the 16-bit lanes of `src` into 8-bit lanes:
-                    //     PACKSSWB([x1, x2, ...], [x1, x2, ...]) = [x1', x2', ..., x1', x2', ...]
-                    // - use PMOVMSKB to gather the high bits; now we have duplicates, though
-                    // - shift away the bottom 8 high bits to remove the duplicates.
-                    let tmp = ctx.alloc_tmp(src_ty).only_reg().unwrap();
-                    ctx.emit(Inst::gen_move(tmp, src, src_ty));
-                    ctx.emit(Inst::xmm_rm_r(SseOpcode::Packsswb, RegMem::reg(src), tmp));
-                    ctx.emit(Inst::xmm_to_gpr(
-                        SseOpcode::Pmovmskb,
-                        tmp.to_reg(),
-                        dst,
-                        size,
-                    ));
-                    ctx.emit(Inst::shift_r(
-                        OperandSize::Size64,
-                        ShiftKind::ShiftRightLogical,
-                        Some(8),
-                        dst,
-                    ));
-                }
-                _ => unimplemented!("unknown input type {} for {}", src_ty, op),
-            }
-        }
-
-        Opcode::Iconcat => {
-            let ty = ctx.output_ty(insn, 0);
-            assert_eq!(
-                ty,
-                types::I128,
-                "Iconcat not expected to be used for non-128-bit type"
-            );
-            assert_eq!(ctx.input_ty(insn, 0), types::I64);
-            assert_eq!(ctx.input_ty(insn, 1), types::I64);
-            let lo = put_input_in_reg(ctx, inputs[0]);
-            let hi = put_input_in_reg(ctx, inputs[1]);
-            let dst = get_output_reg(ctx, outputs[0]);
-            ctx.emit(Inst::gen_move(dst.regs()[0], lo, types::I64));
-            ctx.emit(Inst::gen_move(dst.regs()[1], hi, types::I64));
-        }
-
-        Opcode::Isplit => {
-            let ty = ctx.input_ty(insn, 0);
-            assert_eq!(
-                ty,
-                types::I128,
-                "Iconcat not expected to be used for non-128-bit type"
-            );
-            assert_eq!(ctx.output_ty(insn, 0), types::I64);
-            assert_eq!(ctx.output_ty(insn, 1), types::I64);
-            let src = put_input_in_regs(ctx, inputs[0]);
-            let dst_lo = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-            let dst_hi = get_output_reg(ctx, outputs[1]).only_reg().unwrap();
-            ctx.emit(Inst::gen_move(dst_lo, src.regs()[0], types::I64));
-            ctx.emit(Inst::gen_move(dst_hi, src.regs()[1], types::I64));
-        }
-
-        Opcode::TlsValue => match flags.tls_model() {
-            TlsModel::ElfGd => {
-                let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-                let (name, _, _) = ctx.symbol_value(insn).unwrap();
-                let symbol = name.clone();
-                ctx.emit(Inst::ElfTlsGetAddr { symbol });
-                ctx.emit(Inst::gen_move(dst, regs::rax(), types::I64));
-            }
-            TlsModel::Macho => {
-                let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-                let (name, _, _) = ctx.symbol_value(insn).unwrap();
-                let symbol = name.clone();
-                ctx.emit(Inst::MachOTlsGetAddr { symbol });
-                ctx.emit(Inst::gen_move(dst, regs::rax(), types::I64));
-            }
-            _ => {
-                todo!(
-                    "Unimplemented TLS model in x64 backend: {:?}",
-                    flags.tls_model()
-                );
-            }
-        },
-
-        Opcode::SqmulRoundSat => {
-            // Lane-wise saturating rounding multiplication in Q15 format
-            // Optimal lowering taken from instruction proposal https://github.com/WebAssembly/simd/pull/365
-            // y = i16x8.q15mulr_sat_s(a, b) is lowered to:
-            //MOVDQA xmm_y, xmm_a
-            //MOVDQA xmm_tmp, wasm_i16x8_splat(0x8000)
-            //PMULHRSW xmm_y, xmm_b
-            //PCMPEQW xmm_tmp, xmm_y
-            //PXOR xmm_y, xmm_tmp
-            let input_ty = ctx.input_ty(insn, 0);
-            let src1 = put_input_in_reg(ctx, inputs[0]);
-            let src2 = put_input_in_reg(ctx, inputs[1]);
-            let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-
-            ctx.emit(Inst::gen_move(dst, src1, input_ty));
-            static SAT_MASK: [u8; 16] = [
-                0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80,
-                0x00, 0x80,
-            ];
-            let mask_const = ctx.use_constant(VCodeConstantData::WellKnown(&SAT_MASK));
-            let mask = ctx.alloc_tmp(types::I16X8).only_reg().unwrap();
-            ctx.emit(Inst::xmm_load_const(mask_const, mask, types::I16X8));
-
-            ctx.emit(Inst::xmm_rm_r(SseOpcode::Pmulhrsw, RegMem::reg(src2), dst));
-            ctx.emit(Inst::xmm_rm_r(
-                SseOpcode::Pcmpeqw,
-                RegMem::reg(dst.to_reg()),
-                mask,
-            ));
-            ctx.emit(Inst::xmm_rm_r(
-                SseOpcode::Pxor,
-                RegMem::reg(mask.to_reg()),
-                dst,
-            ));
-        }
-
-        Opcode::Uunarrow => {
-            if let Some(fcvt_inst) = matches_input(ctx, inputs[0], Opcode::FcvtToUintSat) {
-                //y = i32x4.trunc_sat_f64x2_u_zero(x) is lowered to:
-                //MOVAPD xmm_y, xmm_x
-                //XORPD xmm_tmp, xmm_tmp
-                //MAXPD xmm_y, xmm_tmp
-                //MINPD xmm_y, [wasm_f64x2_splat(4294967295.0)]
-                //ROUNDPD xmm_y, xmm_y, 0x0B
-                //ADDPD xmm_y, [wasm_f64x2_splat(0x1.0p+52)]
-                //SHUFPS xmm_y, xmm_xmp, 0x88
-
-                let fcvt_input = InsnInput {
-                    insn: fcvt_inst,
-                    input: 0,
-                };
-                let input_ty = ctx.input_ty(fcvt_inst, 0);
-                let output_ty = ctx.output_ty(insn, 0);
-                let src = put_input_in_reg(ctx, fcvt_input);
-                let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
-
-                ctx.emit(Inst::gen_move(dst, src, input_ty));
-                let tmp1 = ctx.alloc_tmp(output_ty).only_reg().unwrap();
-                ctx.emit(Inst::xmm_rm_r(SseOpcode::Xorpd, RegMem::from(tmp1), tmp1));
-                ctx.emit(Inst::xmm_rm_r(SseOpcode::Maxpd, RegMem::from(tmp1), dst));
-
-                // 4294967295.0 is equivalent to 0x41EFFFFFFFE00000
-                static UMAX_MASK: [u8; 16] = [
-                    0x00, 0x00, 0xE0, 0xFF, 0xFF, 0xFF, 0xEF, 0x41, 0x00, 0x00, 0xE0, 0xFF, 0xFF,
-                    0xFF, 0xEF, 0x41,
-                ];
-                let umax_const = ctx.use_constant(VCodeConstantData::WellKnown(&UMAX_MASK));
-                let umax_mask = ctx.alloc_tmp(types::F64X2).only_reg().unwrap();
-                ctx.emit(Inst::xmm_load_const(umax_const, umax_mask, types::F64X2));
-
-                //MINPD xmm_y, [wasm_f64x2_splat(4294967295.0)]
-                ctx.emit(Inst::xmm_rm_r(
-                    SseOpcode::Minpd,
-                    RegMem::from(umax_mask),
-                    dst,
-                ));
-                //ROUNDPD xmm_y, xmm_y, 0x0B
-                ctx.emit(Inst::xmm_rm_r_imm(
-                    SseOpcode::Roundpd,
-                    RegMem::reg(dst.to_reg()),
-                    dst,
-                    RoundImm::RoundZero.encode(),
-                    OperandSize::Size32,
-                ));
-                //ADDPD xmm_y, [wasm_f64x2_splat(0x1.0p+52)]
-                static UINT_MASK: [u8; 16] = [
-                    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00,
-                    0x00, 0x30, 0x43,
-                ];
-                let uint_mask_const = ctx.use_constant(VCodeConstantData::WellKnown(&UINT_MASK));
-                let uint_mask = ctx.alloc_tmp(types::F64X2).only_reg().unwrap();
-                ctx.emit(Inst::xmm_load_const(
-                    uint_mask_const,
-                    uint_mask,
-                    types::F64X2,
-                ));
-                ctx.emit(Inst::xmm_rm_r(
-                    SseOpcode::Addpd,
-                    RegMem::from(uint_mask),
-                    dst,
-                ));
-
-                //SHUFPS xmm_y, xmm_xmp, 0x88
-                ctx.emit(Inst::xmm_rm_r_imm(
-                    SseOpcode::Shufps,
-                    RegMem::reg(tmp1.to_reg()),
-                    dst,
-                    0x88,
-                    OperandSize::Size32,
-                ));
-            } else {
-                println!("Did not match fcvt input!");
-            }
-        }
-
-        // Unimplemented opcodes below. These are not currently used by Wasm
-        // lowering or other known embeddings, but should be either supported or
-        // removed eventually.
-        Opcode::Uload8x8Complex
-        | Opcode::Sload8x8Complex
-        | Opcode::Uload16x4Complex
-        | Opcode::Sload16x4Complex
-        | Opcode::Uload32x2Complex
-        | Opcode::Sload32x2Complex => {
-            unimplemented!("Vector load {:?} not implemented", op);
-        }
-
-        Opcode::Cls => unimplemented!("Cls not supported"),
-
-        Opcode::Fma => unimplemented!("Fma not supported"),
-
-        Opcode::BorNot | Opcode::BxorNot => {
-            unimplemented!("or-not / xor-not opcodes not implemented");
-        }
-
-        Opcode::Bmask => unimplemented!("Bmask not implemented"),
-
-        Opcode::Trueif | Opcode::Trueff => unimplemented!("trueif / trueff not implemented"),
-
-        Opcode::ConstAddr => unimplemented!("ConstAddr not implemented"),
-
-        Opcode::Vsplit | Opcode::Vconcat => {
-            unimplemented!("Vector split/concat ops not implemented.");
-        }
-
-        // Opcodes that should be removed by legalization. These should
-        // eventually be removed if/when we replace in-situ legalization with
-        // something better.
-        Opcode::Ifcmp | Opcode::Ffcmp => {
-            panic!("Should never reach ifcmp/ffcmp as isel root!");
-        }
-
-        Opcode::IaddImm
-        | Opcode::ImulImm
-        | Opcode::UdivImm
-        | Opcode::SdivImm
-        | Opcode::UremImm
-        | Opcode::SremImm
-        | Opcode::IrsubImm
-        | Opcode::IaddCin
-        | Opcode::IaddIfcin
-        | Opcode::IaddCout
-        | Opcode::IaddCarry
-        | Opcode::IaddIfcarry
-        | Opcode::IsubBin
-        | Opcode::IsubIfbin
-        | Opcode::IsubBout
-        | Opcode::IsubIfbout
-        | Opcode::IsubBorrow
-        | Opcode::IsubIfborrow
-        | Opcode::BandImm
-        | Opcode::BorImm
-        | Opcode::BxorImm
-        | Opcode::RotlImm
-        | Opcode::RotrImm
-        | Opcode::IshlImm
-        | Opcode::UshrImm
-        | Opcode::SshrImm
-        | Opcode::IcmpImm
-        | Opcode::IfcmpImm => {
-            panic!("ALU+imm and ALU+carry ops should not appear here!");
-        }
-
-        Opcode::StackLoad | Opcode::StackStore => {
-            panic!("Direct stack memory access not supported; should have been legalized");
-        }
-
-        Opcode::GlobalValue => {
-            panic!("global_value should have been removed by legalization!");
-        }
-
-        Opcode::HeapAddr => {
-            panic!("heap_addr should have been removed by legalization!");
-        }
-
-        Opcode::TableAddr => {
-            panic!("table_addr should have been removed by legalization!");
-        }
-
-        Opcode::IfcmpSp | Opcode::Copy => {
-            panic!("Unused opcode should not be encountered.");
-        }
-
-        Opcode::Trapz | Opcode::Trapnz | Opcode::ResumableTrapnz => {
-            panic!("trapz / trapnz / resumable_trapnz should have been removed by legalization!");
-        }
-
-        Opcode::Jump
-        | Opcode::Brz
-        | Opcode::Brnz
-        | Opcode::BrIcmp
-        | Opcode::Brif
-        | Opcode::Brff
-        | Opcode::BrTable => {
-            panic!("Branch opcode reached non-branch lowering logic!");
-        }
-
-        Opcode::Nop => {
-            // Nothing.
-        }
-    }
-
-    Ok(())
-}
-
-//=============================================================================
-// Lowering-backend trait implementation.
-
-impl LowerBackend for X64Backend {
-    type MInst = Inst;
-
-    fn lower<C: LowerCtx<I = Inst>>(&self, ctx: &mut C, ir_inst: IRInst) -> CodegenResult<()> {
-        lower_insn_to_regs(ctx, ir_inst, &self.flags, &self.x64_flags, &self.triple)
-    }
-
-    fn lower_branch_group<C: LowerCtx<I = Inst>>(
-        &self,
-        ctx: &mut C,
-        branches: &[IRInst],
-        targets: &[MachLabel],
-    ) -> CodegenResult<()> {
-        // A block should end with at most two branches. The first may be a
-        // conditional branch; a conditional branch can be followed only by an
-        // unconditional branch or fallthrough. Otherwise, if only one branch,
-        // it may be an unconditional branch, a fallthrough, a return, or a
-        // trap. These conditions are verified by `is_ebb_basic()` during the
-        // verifier pass.
-        assert!(branches.len() <= 2);
-
-        if branches.len() == 2 {
-            // Must be a conditional branch followed by an unconditional branch.
-            let op0 = ctx.data(branches[0]).opcode();
-            let op1 = ctx.data(branches[1]).opcode();
-
-            trace!(
-                "lowering two-branch group: opcodes are {:?} and {:?}",
-                op0,
-                op1
-            );
-            assert!(op1 == Opcode::Jump);
-
-            let taken = targets[0];
-            // not_taken target is the target of the second branch.
-            let not_taken = targets[1];
-
-            match op0 {
-                Opcode::Brz | Opcode::Brnz => {
-                    let flag_input = InsnInput {
-                        insn: branches[0],
-                        input: 0,
-                    };
-
-                    let src_ty = ctx.input_ty(branches[0], 0);
-
-                    if let Some(icmp) = matches_input(ctx, flag_input, Opcode::Icmp) {
-                        let cond_code = ctx.data(icmp).cond_code().unwrap();
-                        let cond_code = emit_cmp(ctx, icmp, cond_code);
-
-                        let cond_code = if op0 == Opcode::Brz {
-                            cond_code.inverse()
-                        } else {
-                            cond_code
-                        };
-
-                        let cc = CC::from_intcc(cond_code);
-                        ctx.emit(Inst::jmp_cond(cc, taken, not_taken));
-                    } else if let Some(fcmp) = matches_input(ctx, flag_input, Opcode::Fcmp) {
-                        let cond_code = ctx.data(fcmp).fp_cond_code().unwrap();
-                        let cond_code = if op0 == Opcode::Brz {
-                            cond_code.inverse()
-                        } else {
-                            cond_code
-                        };
-                        match emit_fcmp(ctx, fcmp, cond_code, FcmpSpec::Normal) {
-                            FcmpCondResult::Condition(cc) => {
-                                ctx.emit(Inst::jmp_cond(cc, taken, not_taken));
-                            }
-                            FcmpCondResult::AndConditions(cc1, cc2) => {
-                                ctx.emit(Inst::jmp_if(cc1.invert(), not_taken));
-                                ctx.emit(Inst::jmp_cond(cc2.invert(), not_taken, taken));
-                            }
-                            FcmpCondResult::OrConditions(cc1, cc2) => {
-                                ctx.emit(Inst::jmp_if(cc1, taken));
-                                ctx.emit(Inst::jmp_cond(cc2, taken, not_taken));
-                            }
-                            FcmpCondResult::InvertedEqualOrConditions(_, _) => unreachable!(),
-                        }
-                    } else if src_ty == types::I128 {
-                        let src = put_input_in_regs(
-                            ctx,
-                            InsnInput {
-                                insn: branches[0],
-                                input: 0,
-                            },
-                        );
-                        let (half_cc, comb_op) = match op0 {
-                            Opcode::Brz => (CC::Z, AluRmiROpcode::And8),
-                            Opcode::Brnz => (CC::NZ, AluRmiROpcode::Or8),
-                            _ => unreachable!(),
-                        };
-                        let tmp1 = ctx.alloc_tmp(types::I64).only_reg().unwrap();
-                        let tmp2 = ctx.alloc_tmp(types::I64).only_reg().unwrap();
-                        ctx.emit(Inst::cmp_rmi_r(
-                            OperandSize::Size64,
-                            RegMemImm::imm(0),
-                            src.regs()[0],
-                        ));
-                        ctx.emit(Inst::setcc(half_cc, tmp1));
-                        ctx.emit(Inst::cmp_rmi_r(
-                            OperandSize::Size64,
-                            RegMemImm::imm(0),
-                            src.regs()[1],
-                        ));
-                        ctx.emit(Inst::setcc(half_cc, tmp2));
-                        ctx.emit(Inst::alu_rmi_r(
-                            OperandSize::Size32,
-                            comb_op,
-                            RegMemImm::reg(tmp1.to_reg()),
-                            tmp2,
-                        ));
-                        ctx.emit(Inst::jmp_cond(CC::NZ, taken, not_taken));
-                    } else if is_int_or_ref_ty(src_ty) || is_bool_ty(src_ty) {
-                        let src = put_input_in_reg(
-                            ctx,
-                            InsnInput {
-                                insn: branches[0],
-                                input: 0,
-                            },
-                        );
-                        let cc = match op0 {
-                            Opcode::Brz => CC::Z,
-                            Opcode::Brnz => CC::NZ,
-                            _ => unreachable!(),
-                        };
-                        // See case for `Opcode::Select` above re: testing the
-                        // boolean input.
-                        let test_input = if src_ty == types::B1 {
-                            // test src, 1
-                            RegMemImm::imm(1)
-                        } else {
-                            assert!(!is_bool_ty(src_ty));
-                            // test src, src
-                            RegMemImm::reg(src)
-                        };
-
-                        ctx.emit(Inst::test_rmi_r(
-                            OperandSize::from_ty(src_ty),
-                            test_input,
-                            src,
-                        ));
-                        ctx.emit(Inst::jmp_cond(cc, taken, not_taken));
-                    } else {
-                        unimplemented!("brz/brnz with non-int type {:?}", src_ty);
-                    }
-                }
-
-                Opcode::BrIcmp => {
-                    let src_ty = ctx.input_ty(branches[0], 0);
-                    if is_int_or_ref_ty(src_ty) || is_bool_ty(src_ty) {
-                        let lhs = put_input_in_reg(
-                            ctx,
-                            InsnInput {
-                                insn: branches[0],
-                                input: 0,
-                            },
-                        );
-                        let rhs = input_to_reg_mem_imm(
-                            ctx,
-                            InsnInput {
-                                insn: branches[0],
-                                input: 1,
-                            },
-                        );
-                        let cc = CC::from_intcc(ctx.data(branches[0]).cond_code().unwrap());
-                        // Cranelift's icmp semantics want to compare lhs - rhs, while Intel gives
-                        // us dst - src at the machine instruction level, so invert operands.
-                        ctx.emit(Inst::cmp_rmi_r(OperandSize::from_ty(src_ty), rhs, lhs));
-                        ctx.emit(Inst::jmp_cond(cc, taken, not_taken));
-                    } else {
-                        unimplemented!("bricmp with non-int type {:?}", src_ty);
-                    }
-                }
-
-                Opcode::Brif => {
-                    let flag_input = InsnInput {
-                        insn: branches[0],
-                        input: 0,
-                    };
-
-                    if let Some(ifcmp) = matches_input(ctx, flag_input, Opcode::Ifcmp) {
-                        let cond_code = ctx.data(branches[0]).cond_code().unwrap();
-                        let cond_code = emit_cmp(ctx, ifcmp, cond_code);
-                        let cc = CC::from_intcc(cond_code);
-                        ctx.emit(Inst::jmp_cond(cc, taken, not_taken));
-                    } else if let Some(ifcmp_sp) = matches_input(ctx, flag_input, Opcode::IfcmpSp) {
-                        let operand = put_input_in_reg(
-                            ctx,
-                            InsnInput {
-                                insn: ifcmp_sp,
-                                input: 0,
-                            },
-                        );
-                        let ty = ctx.input_ty(ifcmp_sp, 0);
-                        ctx.emit(Inst::cmp_rmi_r(
-                            OperandSize::from_ty(ty),
-                            RegMemImm::reg(regs::rsp()),
-                            operand,
-                        ));
-                        let cond_code = ctx.data(branches[0]).cond_code().unwrap();
-                        let cc = CC::from_intcc(cond_code);
-                        ctx.emit(Inst::jmp_cond(cc, taken, not_taken));
-                    } else {
-                        // Should be disallowed by flags checks in verifier.
-                        unimplemented!("Brif with non-ifcmp input");
-                    }
-                }
-                Opcode::Brff => {
-                    let flag_input = InsnInput {
-                        insn: branches[0],
-                        input: 0,
-                    };
-
-                    if let Some(ffcmp) = matches_input(ctx, flag_input, Opcode::Ffcmp) {
-                        let cond_code = ctx.data(branches[0]).fp_cond_code().unwrap();
-                        match emit_fcmp(ctx, ffcmp, cond_code, FcmpSpec::Normal) {
-                            FcmpCondResult::Condition(cc) => {
-                                ctx.emit(Inst::jmp_cond(cc, taken, not_taken));
-                            }
-                            FcmpCondResult::AndConditions(cc1, cc2) => {
-                                ctx.emit(Inst::jmp_if(cc1.invert(), not_taken));
-                                ctx.emit(Inst::jmp_cond(cc2.invert(), not_taken, taken));
-                            }
-                            FcmpCondResult::OrConditions(cc1, cc2) => {
-                                ctx.emit(Inst::jmp_if(cc1, taken));
-                                ctx.emit(Inst::jmp_cond(cc2, taken, not_taken));
-                            }
-                            FcmpCondResult::InvertedEqualOrConditions(_, _) => unreachable!(),
-                        }
-                    } else {
-                        // Should be disallowed by flags checks in verifier.
-                        unimplemented!("Brff with input not from ffcmp");
-                    }
-                }
-
-                _ => panic!("unexpected branch opcode: {:?}", op0),
-            }
-        } else {
-            assert_eq!(branches.len(), 1);
-
-            // Must be an unconditional branch or trap.
-            let op = ctx.data(branches[0]).opcode();
-            match op {
-                Opcode::Jump => {
-                    ctx.emit(Inst::jmp_known(targets[0]));
-                }
-
-                Opcode::BrTable => {
-                    let jt_size = targets.len() - 1;
-                    assert!(jt_size <= u32::MAX as usize);
-                    let jt_size = jt_size as u32;
-
-                    let ty = ctx.input_ty(branches[0], 0);
-                    let ext_spec = match ty {
-                        types::I128 => panic!("BrTable unimplemented for I128"),
-                        types::I64 => ExtSpec::ZeroExtendTo64,
-                        _ => ExtSpec::ZeroExtendTo32,
-                    };
-
-                    let idx = extend_input_to_reg(
-                        ctx,
-                        InsnInput {
-                            insn: branches[0],
-                            input: 0,
-                        },
-                        ext_spec,
-                    );
-
-                    // Bounds-check (compute flags from idx - jt_size) and branch to default.
-                    // We only support u32::MAX entries, but we compare the full 64 bit register
-                    // when doing the bounds check.
-                    let cmp_size = if ty == types::I64 {
-                        OperandSize::Size64
-                    } else {
-                        OperandSize::Size32
-                    };
-                    ctx.emit(Inst::cmp_rmi_r(cmp_size, RegMemImm::imm(jt_size), idx));
-
-                    // Emit the compound instruction that does:
-                    //
-                    // lea $jt, %rA
-                    // movsbl [%rA, %rIndex, 2], %rB
-                    // add %rB, %rA
-                    // j *%rA
-                    // [jt entries]
-                    //
-                    // This must be *one* instruction in the vcode because we cannot allow regalloc
-                    // to insert any spills/fills in the middle of the sequence; otherwise, the
-                    // lea PC-rel offset to the jumptable would be incorrect.  (The alternative
-                    // is to introduce a relocation pass for inlined jumptables, which is much
-                    // worse.)
-
-                    // This temporary is used as a signed integer of 64-bits (to hold addresses).
-                    let tmp1 = ctx.alloc_tmp(types::I64).only_reg().unwrap();
-                    // This temporary is used as a signed integer of 32-bits (for the wasm-table
-                    // index) and then 64-bits (address addend). The small lie about the I64 type
-                    // is benign, since the temporary is dead after this instruction (and its
-                    // Cranelift type is thus unused).
-                    let tmp2 = ctx.alloc_tmp(types::I64).only_reg().unwrap();
-
-                    let targets_for_term: Vec<MachLabel> = targets.to_vec();
-                    let default_target = targets[0];
-
-                    let jt_targets: Vec<MachLabel> = targets.iter().skip(1).cloned().collect();
-
-                    ctx.emit(Inst::JmpTableSeq {
-                        idx,
-                        tmp1,
-                        tmp2,
-                        default_target,
-                        targets: jt_targets,
-                        targets_for_term,
-                    });
-                }
-
-                _ => panic!("Unknown branch type {:?}", op),
-            }
-        }
-
-        Ok(())
-    }
-
-    fn maybe_pinned_reg(&self) -> Option<Reg> {
-        Some(regs::pinned_reg())
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/lower/isle.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/lower/isle.rs
deleted file mode 100644
index c20bf3b1e..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/lower/isle.rs
+++ /dev/null
@@ -1,572 +0,0 @@
-//! ISLE integration glue code for x64 lowering.
-
-// Pull in the ISLE generated code.
-pub(crate) mod generated_code;
-use generated_code::MInst;
-use regalloc::Writable;
-
-// Types that the generated ISLE code uses via `use super::*`.
-use super::{is_int_or_ref_ty, is_mergeable_load, lower_to_amode, Reg};
-use crate::{
-    ir::{
-        condcodes::FloatCC, immediates::*, types::*, Inst, InstructionData, Opcode, TrapCode,
-        Value, ValueLabel, ValueList,
-    },
-    isa::{
-        settings::Flags,
-        unwind::UnwindInst,
-        x64::{
-            inst::{args::*, regs, x64_map_regs},
-            settings::Flags as IsaFlags,
-        },
-    },
-    machinst::{
-        isle::*, AtomicRmwOp, InsnInput, InsnOutput, LowerCtx, VCodeConstant, VCodeConstantData,
-    },
-};
-use std::convert::TryFrom;
-
-pub struct SinkableLoad {
-    inst: Inst,
-    addr_input: InsnInput,
-    offset: i32,
-}
-
-/// The main entry point for lowering with ISLE.
-pub(crate) fn lower<C>(
-    lower_ctx: &mut C,
-    flags: &Flags,
-    isa_flags: &IsaFlags,
-    outputs: &[InsnOutput],
-    inst: Inst,
-) -> Result<(), ()>
-where
-    C: LowerCtx<I = MInst>,
-{
-    lower_common(
-        lower_ctx,
-        flags,
-        isa_flags,
-        outputs,
-        inst,
-        |cx, insn| generated_code::constructor_lower(cx, insn),
-        x64_map_regs,
-    )
-}
-
-impl<C> generated_code::Context for IsleContext<'_, C, Flags, IsaFlags, 6>
-where
-    C: LowerCtx<I = MInst>,
-{
-    isle_prelude_methods!();
-
-    #[inline]
-    fn operand_size_of_type_32_64(&mut self, ty: Type) -> OperandSize {
-        if ty.bits() == 64 {
-            OperandSize::Size64
-        } else {
-            OperandSize::Size32
-        }
-    }
-
-    #[inline]
-    fn raw_operand_size_of_type(&mut self, ty: Type) -> OperandSize {
-        OperandSize::from_ty(ty)
-    }
-
-    fn put_in_reg_mem_imm(&mut self, val: Value) -> RegMemImm {
-        let inputs = self.lower_ctx.get_value_as_source_or_const(val);
-
-        if let Some(c) = inputs.constant {
-            if let Some(imm) = to_simm32(c as i64) {
-                return imm.to_reg_mem_imm();
-            }
-
-            // Generate constants fresh at each use to minimize long-range
-            // register pressure.
-            let ty = self.value_type(val);
-            return RegMemImm::reg(generated_code::constructor_imm(self, ty, c).unwrap());
-        }
-
-        if let Some((src_insn, 0)) = inputs.inst {
-            if let Some((addr_input, offset)) = is_mergeable_load(self.lower_ctx, src_insn) {
-                self.lower_ctx.sink_inst(src_insn);
-                let amode = lower_to_amode(self.lower_ctx, addr_input, offset);
-                return RegMemImm::mem(amode);
-            }
-        }
-
-        RegMemImm::reg(self.put_in_reg(val))
-    }
-
-    fn put_in_reg_mem(&mut self, val: Value) -> RegMem {
-        let inputs = self.lower_ctx.get_value_as_source_or_const(val);
-
-        if let Some(c) = inputs.constant {
-            // Generate constants fresh at each use to minimize long-range
-            // register pressure.
-            let ty = self.value_type(val);
-            return RegMem::reg(generated_code::constructor_imm(self, ty, c).unwrap());
-        }
-
-        if let Some((src_insn, 0)) = inputs.inst {
-            if let Some((addr_input, offset)) = is_mergeable_load(self.lower_ctx, src_insn) {
-                self.lower_ctx.sink_inst(src_insn);
-                let amode = lower_to_amode(self.lower_ctx, addr_input, offset);
-                return RegMem::mem(amode);
-            }
-        }
-
-        RegMem::reg(self.put_in_reg(val))
-    }
-
-    fn put_masked_in_imm8_gpr(&mut self, val: Value, ty: Type) -> Imm8Gpr {
-        let inputs = self.lower_ctx.get_value_as_source_or_const(val);
-
-        if let Some(c) = inputs.constant {
-            let mask = 1_u64
-                .checked_shl(ty.bits() as u32)
-                .map_or(u64::MAX, |x| x - 1);
-            return Imm8Gpr::new(Imm8Reg::Imm8 {
-                imm: (c & mask) as u8,
-            })
-            .unwrap();
-        }
-
-        Imm8Gpr::new(Imm8Reg::Reg {
-            reg: self.put_in_regs(val).regs()[0],
-        })
-        .unwrap()
-    }
-
-    #[inline]
-    fn encode_fcmp_imm(&mut self, imm: &FcmpImm) -> u8 {
-        imm.encode()
-    }
-
-    #[inline]
-    fn avx512vl_enabled(&mut self, _: Type) -> Option<()> {
-        if self.isa_flags.use_avx512vl_simd() {
-            Some(())
-        } else {
-            None
-        }
-    }
-
-    #[inline]
-    fn avx512dq_enabled(&mut self, _: Type) -> Option<()> {
-        if self.isa_flags.use_avx512dq_simd() {
-            Some(())
-        } else {
-            None
-        }
-    }
-
-    #[inline]
-    fn avx512f_enabled(&mut self, _: Type) -> Option<()> {
-        if self.isa_flags.use_avx512f_simd() {
-            Some(())
-        } else {
-            None
-        }
-    }
-
-    #[inline]
-    fn avx512bitalg_enabled(&mut self, _: Type) -> Option<()> {
-        if self.isa_flags.use_avx512bitalg_simd() {
-            Some(())
-        } else {
-            None
-        }
-    }
-
-    #[inline]
-    fn use_lzcnt(&mut self, _: Type) -> Option<()> {
-        if self.isa_flags.use_lzcnt() {
-            Some(())
-        } else {
-            None
-        }
-    }
-
-    #[inline]
-    fn use_bmi1(&mut self, _: Type) -> Option<()> {
-        if self.isa_flags.use_bmi1() {
-            Some(())
-        } else {
-            None
-        }
-    }
-
-    #[inline]
-    fn use_popcnt(&mut self, _: Type) -> Option<()> {
-        if self.isa_flags.use_popcnt() {
-            Some(())
-        } else {
-            None
-        }
-    }
-
-    #[inline]
-    fn imm8_from_value(&mut self, val: Value) -> Option<Imm8Reg> {
-        let inst = self.lower_ctx.dfg().value_def(val).inst()?;
-        let constant = self.lower_ctx.get_constant(inst)?;
-        let imm = u8::try_from(constant).ok()?;
-        Some(Imm8Reg::Imm8 { imm })
-    }
-
-    #[inline]
-    fn const_to_type_masked_imm8(&mut self, c: u64, ty: Type) -> Imm8Gpr {
-        let mask = 1_u64
-            .checked_shl(ty.bits() as u32)
-            .map_or(u64::MAX, |x| x - 1);
-        Imm8Gpr::new(Imm8Reg::Imm8 {
-            imm: (c & mask) as u8,
-        })
-        .unwrap()
-    }
-
-    #[inline]
-    fn simm32_from_value(&mut self, val: Value) -> Option<GprMemImm> {
-        let inst = self.lower_ctx.dfg().value_def(val).inst()?;
-        let constant: u64 = self.lower_ctx.get_constant(inst)?;
-        let constant = constant as i64;
-        to_simm32(constant)
-    }
-
-    #[inline]
-    fn simm32_from_imm64(&mut self, imm: Imm64) -> Option<GprMemImm> {
-        to_simm32(imm.bits())
-    }
-
-    fn sinkable_load(&mut self, val: Value) -> Option<SinkableLoad> {
-        let input = self.lower_ctx.get_value_as_source_or_const(val);
-        if let Some((inst, 0)) = input.inst {
-            if let Some((addr_input, offset)) = is_mergeable_load(self.lower_ctx, inst) {
-                return Some(SinkableLoad {
-                    inst,
-                    addr_input,
-                    offset,
-                });
-            }
-        }
-        None
-    }
-
-    fn sink_load(&mut self, load: &SinkableLoad) -> RegMemImm {
-        self.lower_ctx.sink_inst(load.inst);
-        let addr = lower_to_amode(self.lower_ctx, load.addr_input, load.offset);
-        RegMemImm::Mem {
-            addr: SyntheticAmode::Real(addr),
-        }
-    }
-
-    #[inline]
-    fn ext_mode(&mut self, from_bits: u16, to_bits: u16) -> ExtMode {
-        ExtMode::new(from_bits, to_bits).unwrap()
-    }
-
-    fn emit(&mut self, inst: &MInst) -> Unit {
-        for inst in inst.clone().mov_mitosis() {
-            self.emitted_insts.push((inst, false));
-        }
-    }
-
-    fn emit_safepoint(&mut self, inst: &MInst) -> Unit {
-        use crate::machinst::MachInst;
-        for inst in inst.clone().mov_mitosis() {
-            let is_safepoint = !inst.is_move().is_some();
-            self.emitted_insts.push((inst, is_safepoint));
-        }
-    }
-
-    #[inline]
-    fn nonzero_u64_fits_in_u32(&mut self, x: u64) -> Option<u64> {
-        if x != 0 && x < u64::from(u32::MAX) {
-            Some(x)
-        } else {
-            None
-        }
-    }
-
-    #[inline]
-    fn sse_insertps_lane_imm(&mut self, lane: u8) -> u8 {
-        // Insert 32-bits from replacement (at index 00, bits 7:8) to vector (lane
-        // shifted into bits 5:6).
-        0b00_00_00_00 | lane << 4
-    }
-
-    #[inline]
-    fn xmm0(&mut self) -> WritableXmm {
-        WritableXmm::from_reg(Xmm::new(regs::xmm0()).unwrap())
-    }
-
-    #[inline]
-    fn synthetic_amode_to_reg_mem(&mut self, addr: &SyntheticAmode) -> RegMem {
-        RegMem::mem(addr.clone())
-    }
-
-    #[inline]
-    fn amode_imm_reg_reg_shift(&mut self, simm32: u32, base: Gpr, index: Gpr, shift: u8) -> Amode {
-        Amode::imm_reg_reg_shift(simm32, base, index, shift)
-    }
-
-    #[inline]
-    fn amode_to_synthetic_amode(&mut self, amode: &Amode) -> SyntheticAmode {
-        amode.clone().into()
-    }
-
-    #[inline]
-    fn writable_gpr_to_reg(&mut self, r: WritableGpr) -> WritableReg {
-        r.to_writable_reg()
-    }
-
-    #[inline]
-    fn writable_xmm_to_reg(&mut self, r: WritableXmm) -> WritableReg {
-        r.to_writable_reg()
-    }
-
-    fn ishl_i8x16_mask_for_const(&mut self, amt: u32) -> SyntheticAmode {
-        // When the shift amount is known, we can statically (i.e. at compile
-        // time) determine the mask to use and only emit that.
-        debug_assert!(amt < 8);
-        let mask_offset = amt as usize * 16;
-        let mask_constant = self.lower_ctx.use_constant(VCodeConstantData::WellKnown(
-            &I8X16_ISHL_MASKS[mask_offset..mask_offset + 16],
-        ));
-        SyntheticAmode::ConstantOffset(mask_constant)
-    }
-
-    fn ishl_i8x16_mask_table(&mut self) -> SyntheticAmode {
-        let mask_table = self
-            .lower_ctx
-            .use_constant(VCodeConstantData::WellKnown(&I8X16_ISHL_MASKS));
-        SyntheticAmode::ConstantOffset(mask_table)
-    }
-
-    fn ushr_i8x16_mask_for_const(&mut self, amt: u32) -> SyntheticAmode {
-        // When the shift amount is known, we can statically (i.e. at compile
-        // time) determine the mask to use and only emit that.
-        debug_assert!(amt < 8);
-        let mask_offset = amt as usize * 16;
-        let mask_constant = self.lower_ctx.use_constant(VCodeConstantData::WellKnown(
-            &I8X16_USHR_MASKS[mask_offset..mask_offset + 16],
-        ));
-        SyntheticAmode::ConstantOffset(mask_constant)
-    }
-
-    fn ushr_i8x16_mask_table(&mut self) -> SyntheticAmode {
-        let mask_table = self
-            .lower_ctx
-            .use_constant(VCodeConstantData::WellKnown(&I8X16_USHR_MASKS));
-        SyntheticAmode::ConstantOffset(mask_table)
-    }
-
-    fn popcount_4bit_table(&mut self) -> VCodeConstant {
-        self.lower_ctx
-            .use_constant(VCodeConstantData::WellKnown(&POPCOUNT_4BIT_TABLE))
-    }
-
-    fn popcount_low_mask(&mut self) -> VCodeConstant {
-        self.lower_ctx
-            .use_constant(VCodeConstantData::WellKnown(&POPCOUNT_LOW_MASK))
-    }
-
-    #[inline]
-    fn writable_reg_to_xmm(&mut self, r: WritableReg) -> WritableXmm {
-        Writable::from_reg(Xmm::new(r.to_reg()).unwrap())
-    }
-
-    #[inline]
-    fn writable_xmm_to_xmm(&mut self, r: WritableXmm) -> Xmm {
-        r.to_reg()
-    }
-
-    #[inline]
-    fn writable_gpr_to_gpr(&mut self, r: WritableGpr) -> Gpr {
-        r.to_reg()
-    }
-
-    #[inline]
-    fn gpr_to_reg(&mut self, r: Gpr) -> Reg {
-        r.into()
-    }
-
-    #[inline]
-    fn xmm_to_reg(&mut self, r: Xmm) -> Reg {
-        r.into()
-    }
-
-    #[inline]
-    fn xmm_to_xmm_mem_imm(&mut self, r: Xmm) -> XmmMemImm {
-        r.into()
-    }
-
-    #[inline]
-    fn temp_writable_gpr(&mut self) -> WritableGpr {
-        Writable::from_reg(Gpr::new(self.temp_writable_reg(I64).to_reg()).unwrap())
-    }
-
-    #[inline]
-    fn temp_writable_xmm(&mut self) -> WritableXmm {
-        Writable::from_reg(Xmm::new(self.temp_writable_reg(I8X16).to_reg()).unwrap())
-    }
-
-    #[inline]
-    fn reg_mem_to_xmm_mem(&mut self, rm: &RegMem) -> XmmMem {
-        XmmMem::new(rm.clone()).unwrap()
-    }
-
-    #[inline]
-    fn gpr_mem_imm_new(&mut self, rmi: &RegMemImm) -> GprMemImm {
-        GprMemImm::new(rmi.clone()).unwrap()
-    }
-
-    #[inline]
-    fn xmm_mem_imm_new(&mut self, rmi: &RegMemImm) -> XmmMemImm {
-        XmmMemImm::new(rmi.clone()).unwrap()
-    }
-
-    #[inline]
-    fn xmm_to_xmm_mem(&mut self, r: Xmm) -> XmmMem {
-        r.into()
-    }
-
-    #[inline]
-    fn xmm_mem_to_reg_mem(&mut self, xm: &XmmMem) -> RegMem {
-        xm.clone().into()
-    }
-
-    #[inline]
-    fn gpr_mem_to_reg_mem(&mut self, gm: &GprMem) -> RegMem {
-        gm.clone().into()
-    }
-
-    #[inline]
-    fn xmm_new(&mut self, r: Reg) -> Xmm {
-        Xmm::new(r).unwrap()
-    }
-
-    #[inline]
-    fn gpr_new(&mut self, r: Reg) -> Gpr {
-        Gpr::new(r).unwrap()
-    }
-
-    #[inline]
-    fn reg_mem_to_gpr_mem(&mut self, rm: &RegMem) -> GprMem {
-        GprMem::new(rm.clone()).unwrap()
-    }
-
-    #[inline]
-    fn reg_to_gpr_mem(&mut self, r: Reg) -> GprMem {
-        GprMem::new(RegMem::reg(r)).unwrap()
-    }
-
-    #[inline]
-    fn imm8_reg_to_imm8_gpr(&mut self, ir: &Imm8Reg) -> Imm8Gpr {
-        Imm8Gpr::new(ir.clone()).unwrap()
-    }
-
-    #[inline]
-    fn gpr_to_gpr_mem(&mut self, gpr: Gpr) -> GprMem {
-        GprMem::from(gpr)
-    }
-
-    #[inline]
-    fn gpr_to_gpr_mem_imm(&mut self, gpr: Gpr) -> GprMemImm {
-        GprMemImm::from(gpr)
-    }
-
-    #[inline]
-    fn gpr_to_imm8_gpr(&mut self, gpr: Gpr) -> Imm8Gpr {
-        Imm8Gpr::from(gpr)
-    }
-
-    #[inline]
-    fn imm8_to_imm8_gpr(&mut self, imm: u8) -> Imm8Gpr {
-        Imm8Gpr::new(Imm8Reg::Imm8 { imm }).unwrap()
-    }
-
-    fn is_gpr_type(&mut self, ty: Type) -> Option<Type> {
-        if is_int_or_ref_ty(ty) || ty == I128 || ty == B128 {
-            Some(ty)
-        } else {
-            None
-        }
-    }
-
-    #[inline]
-    fn is_xmm_type(&mut self, ty: Type) -> Option<Type> {
-        if ty == F32 || ty == F64 || (ty.is_vector() && ty.bits() == 128) {
-            Some(ty)
-        } else {
-            None
-        }
-    }
-
-    #[inline]
-    fn is_single_register_type(&mut self, ty: Type) -> Option<Type> {
-        if ty != I128 {
-            Some(ty)
-        } else {
-            None
-        }
-    }
-}
-
-// Since x64 doesn't have 8x16 shifts and we must use a 16x8 shift instead, we
-// need to fix up the bits that migrate from one half of the lane to the
-// other. Each 16-byte mask is indexed by the shift amount: e.g. if we shift
-// right by 0 (no movement), we want to retain all the bits so we mask with
-// `0xff`; if we shift right by 1, we want to retain all bits except the MSB so
-// we mask with `0x7f`; etc.
-
-#[rustfmt::skip] // Preserve 16 bytes (i.e. one mask) per row.
-const I8X16_ISHL_MASKS: [u8; 128] = [
-    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-    0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe,
-    0xfc, 0xfc, 0xfc, 0xfc, 0xfc, 0xfc, 0xfc, 0xfc, 0xfc, 0xfc, 0xfc, 0xfc, 0xfc, 0xfc, 0xfc, 0xfc,
-    0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8,
-    0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0,
-    0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0, 0xe0,
-    0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0,
-    0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-];
-
-#[rustfmt::skip] // Preserve 16 bytes (i.e. one mask) per row.
-const I8X16_USHR_MASKS: [u8; 128] = [
-    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-    0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
-    0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f,
-    0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f,
-    0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f,
-    0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
-    0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
-    0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
-];
-
-/// Number of bits set in a given nibble (4-bit value). Used in the
-/// vector implementation of popcount.
-#[rustfmt::skip] // Preserve 4x4 layout.
-const POPCOUNT_4BIT_TABLE: [u8; 16] = [
-    0x00, 0x01, 0x01, 0x02,
-    0x01, 0x02, 0x02, 0x03,
-    0x01, 0x02, 0x02, 0x03,
-    0x02, 0x03, 0x03, 0x04,
-];
-
-const POPCOUNT_LOW_MASK: [u8; 16] = [0x0f; 16];
-
-#[inline]
-fn to_simm32(constant: i64) -> Option<GprMemImm> {
-    if constant == ((constant << 32) >> 32) {
-        Some(
-            GprMemImm::new(RegMemImm::Imm {
-                simm32: constant as u32,
-            })
-            .unwrap(),
-        )
-    } else {
-        None
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/lower/isle/generated_code.manifest b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/lower/isle/generated_code.manifest
deleted file mode 100644
index ebb1176c9..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/lower/isle/generated_code.manifest
+++ /dev/null
@@ -1,4 +0,0 @@
-src/clif.isle 9ea75a6f790b5c03
-src/prelude.isle b2bc986bcbbbb77
-src/isa/x64/inst.isle 40f495d3ca5ae547
-src/isa/x64/lower.isle c049f7d36db0e0fb
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/lower/isle/generated_code.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/lower/isle/generated_code.rs
deleted file mode 100644
index ab52c9cad..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/lower/isle/generated_code.rs
+++ /dev/null
@@ -1,9338 +0,0 @@
-// GENERATED BY ISLE. DO NOT EDIT!
-//
-// Generated automatically from the instruction-selection DSL code in:
-// - src/clif.isle
-// - src/prelude.isle
-// - src/isa/x64/inst.isle
-// - src/isa/x64/lower.isle
-
-#![allow(dead_code, unreachable_code, unreachable_patterns)]
-#![allow(unused_imports, unused_variables, non_snake_case)]
-#![allow(irrefutable_let_patterns)]
-
-use super::*; // Pulls in all external types.
-
-/// Context during lowering: an implementation of this trait
-/// must be provided with all external constructors and extractors.
-/// A mutable borrow is passed along through all lowering logic.
-pub trait Context {
-    fn unpack_value_array_2(&mut self, arg0: &ValueArray2) -> (Value, Value);
-    fn pack_value_array_2(&mut self, arg0: Value, arg1: Value) -> ValueArray2;
-    fn unpack_value_array_3(&mut self, arg0: &ValueArray3) -> (Value, Value, Value);
-    fn pack_value_array_3(&mut self, arg0: Value, arg1: Value, arg2: Value) -> ValueArray3;
-    fn u32_add(&mut self, arg0: u32, arg1: u32) -> u32;
-    fn u8_and(&mut self, arg0: u8, arg1: u8) -> u8;
-    fn value_reg(&mut self, arg0: Reg) -> ValueRegs;
-    fn value_regs(&mut self, arg0: Reg, arg1: Reg) -> ValueRegs;
-    fn value_regs_invalid(&mut self) -> ValueRegs;
-    fn output_none(&mut self) -> InstOutput;
-    fn output(&mut self, arg0: ValueRegs) -> InstOutput;
-    fn output_pair(&mut self, arg0: ValueRegs, arg1: ValueRegs) -> InstOutput;
-    fn output_builder_new(&mut self) -> InstOutputBuilder;
-    fn output_builder_push(&mut self, arg0: &InstOutputBuilder, arg1: ValueRegs) -> Unit;
-    fn output_builder_finish(&mut self, arg0: &InstOutputBuilder) -> InstOutput;
-    fn temp_writable_reg(&mut self, arg0: Type) -> WritableReg;
-    fn invalid_reg(&mut self) -> Reg;
-    fn put_in_reg(&mut self, arg0: Value) -> Reg;
-    fn put_in_regs(&mut self, arg0: Value) -> ValueRegs;
-    fn value_regs_get(&mut self, arg0: ValueRegs, arg1: usize) -> Reg;
-    fn u8_as_u64(&mut self, arg0: u8) -> u64;
-    fn u16_as_u64(&mut self, arg0: u16) -> u64;
-    fn u32_as_u64(&mut self, arg0: u32) -> u64;
-    fn i64_as_u64(&mut self, arg0: i64) -> u64;
-    fn u64_add(&mut self, arg0: u64, arg1: u64) -> u64;
-    fn u64_sub(&mut self, arg0: u64, arg1: u64) -> u64;
-    fn u64_and(&mut self, arg0: u64, arg1: u64) -> u64;
-    fn ty_bits(&mut self, arg0: Type) -> u8;
-    fn ty_bits_u16(&mut self, arg0: Type) -> u16;
-    fn ty_bits_u64(&mut self, arg0: Type) -> u64;
-    fn ty_mask(&mut self, arg0: Type) -> u64;
-    fn ty_bytes(&mut self, arg0: Type) -> u16;
-    fn lane_type(&mut self, arg0: Type) -> Type;
-    fn fits_in_16(&mut self, arg0: Type) -> Option<Type>;
-    fn fits_in_32(&mut self, arg0: Type) -> Option<Type>;
-    fn fits_in_64(&mut self, arg0: Type) -> Option<Type>;
-    fn ty_32_or_64(&mut self, arg0: Type) -> Option<Type>;
-    fn ty_8_or_16(&mut self, arg0: Type) -> Option<Type>;
-    fn ty_int_bool_64(&mut self, arg0: Type) -> Option<Type>;
-    fn ty_int_bool_128(&mut self, arg0: Type) -> Option<Type>;
-    fn vec128(&mut self, arg0: Type) -> Option<Type>;
-    fn not_i64x2(&mut self, arg0: Type) -> Option<()>;
-    fn value_list_slice(&mut self, arg0: ValueList) -> ValueSlice;
-    fn value_slice_empty(&mut self, arg0: ValueSlice) -> Option<()>;
-    fn value_slice_unwrap(&mut self, arg0: ValueSlice) -> Option<(Value, ValueSlice)>;
-    fn value_slice_len(&mut self, arg0: ValueSlice) -> usize;
-    fn value_slice_get(&mut self, arg0: ValueSlice, arg1: usize) -> Value;
-    fn writable_reg_to_reg(&mut self, arg0: WritableReg) -> Reg;
-    fn u8_from_uimm8(&mut self, arg0: Uimm8) -> u8;
-    fn u64_from_imm64(&mut self, arg0: Imm64) -> u64;
-    fn nonzero_u64_from_imm64(&mut self, arg0: Imm64) -> Option<u64>;
-    fn u64_from_ieee32(&mut self, arg0: Ieee32) -> u64;
-    fn u64_from_ieee64(&mut self, arg0: Ieee64) -> u64;
-    fn inst_results(&mut self, arg0: Inst) -> ValueSlice;
-    fn first_result(&mut self, arg0: Inst) -> Option<Value>;
-    fn inst_data(&mut self, arg0: Inst) -> InstructionData;
-    fn value_type(&mut self, arg0: Value) -> Type;
-    fn multi_lane(&mut self, arg0: Type) -> Option<(u8, u16)>;
-    fn def_inst(&mut self, arg0: Value) -> Option<Inst>;
-    fn emit(&mut self, arg0: &MInst) -> Unit;
-    fn emit_safepoint(&mut self, arg0: &MInst) -> Unit;
-    fn trap_code_division_by_zero(&mut self) -> TrapCode;
-    fn trap_code_integer_overflow(&mut self) -> TrapCode;
-    fn trap_code_bad_conversion_to_integer(&mut self) -> TrapCode;
-    fn avoid_div_traps(&mut self, arg0: Type) -> Option<()>;
-    fn func_ref_data(&mut self, arg0: FuncRef) -> (SigRef, ExternalName, RelocDistance);
-    fn symbol_value_data(
-        &mut self,
-        arg0: GlobalValue,
-    ) -> Option<(ExternalName, RelocDistance, i64)>;
-    fn reloc_distance_near(&mut self, arg0: RelocDistance) -> Option<()>;
-    fn operand_size_of_type_32_64(&mut self, arg0: Type) -> OperandSize;
-    fn raw_operand_size_of_type(&mut self, arg0: Type) -> OperandSize;
-    fn put_in_reg_mem_imm(&mut self, arg0: Value) -> RegMemImm;
-    fn put_in_reg_mem(&mut self, arg0: Value) -> RegMem;
-    fn synthetic_amode_to_reg_mem(&mut self, arg0: &SyntheticAmode) -> RegMem;
-    fn amode_imm_reg_reg_shift(&mut self, arg0: u32, arg1: Gpr, arg2: Gpr, arg3: u8) -> Amode;
-    fn amode_to_synthetic_amode(&mut self, arg0: &Amode) -> SyntheticAmode;
-    fn put_masked_in_imm8_gpr(&mut self, arg0: Value, arg1: Type) -> Imm8Gpr;
-    fn encode_fcmp_imm(&mut self, arg0: &FcmpImm) -> u8;
-    fn imm8_reg_to_imm8_gpr(&mut self, arg0: &Imm8Reg) -> Imm8Gpr;
-    fn writable_gpr_to_reg(&mut self, arg0: WritableGpr) -> WritableReg;
-    fn writable_xmm_to_reg(&mut self, arg0: WritableXmm) -> WritableReg;
-    fn writable_reg_to_xmm(&mut self, arg0: WritableReg) -> WritableXmm;
-    fn writable_xmm_to_xmm(&mut self, arg0: WritableXmm) -> Xmm;
-    fn writable_gpr_to_gpr(&mut self, arg0: WritableGpr) -> Gpr;
-    fn gpr_to_reg(&mut self, arg0: Gpr) -> Reg;
-    fn gpr_to_gpr_mem(&mut self, arg0: Gpr) -> GprMem;
-    fn gpr_to_gpr_mem_imm(&mut self, arg0: Gpr) -> GprMemImm;
-    fn xmm_to_reg(&mut self, arg0: Xmm) -> Reg;
-    fn xmm_to_xmm_mem_imm(&mut self, arg0: Xmm) -> XmmMemImm;
-    fn temp_writable_gpr(&mut self) -> WritableGpr;
-    fn temp_writable_xmm(&mut self) -> WritableXmm;
-    fn reg_mem_to_xmm_mem(&mut self, arg0: &RegMem) -> XmmMem;
-    fn gpr_mem_imm_new(&mut self, arg0: &RegMemImm) -> GprMemImm;
-    fn xmm_mem_imm_new(&mut self, arg0: &RegMemImm) -> XmmMemImm;
-    fn xmm_to_xmm_mem(&mut self, arg0: Xmm) -> XmmMem;
-    fn xmm_mem_to_reg_mem(&mut self, arg0: &XmmMem) -> RegMem;
-    fn gpr_mem_to_reg_mem(&mut self, arg0: &GprMem) -> RegMem;
-    fn xmm_new(&mut self, arg0: Reg) -> Xmm;
-    fn gpr_new(&mut self, arg0: Reg) -> Gpr;
-    fn reg_mem_to_gpr_mem(&mut self, arg0: &RegMem) -> GprMem;
-    fn reg_to_gpr_mem(&mut self, arg0: Reg) -> GprMem;
-    fn gpr_to_imm8_gpr(&mut self, arg0: Gpr) -> Imm8Gpr;
-    fn imm8_to_imm8_gpr(&mut self, arg0: u8) -> Imm8Gpr;
-    fn xmm0(&mut self) -> WritableXmm;
-    fn is_xmm_type(&mut self, arg0: Type) -> Option<Type>;
-    fn is_gpr_type(&mut self, arg0: Type) -> Option<Type>;
-    fn is_single_register_type(&mut self, arg0: Type) -> Option<Type>;
-    fn avx512vl_enabled(&mut self, arg0: Type) -> Option<()>;
-    fn avx512dq_enabled(&mut self, arg0: Type) -> Option<()>;
-    fn avx512f_enabled(&mut self, arg0: Type) -> Option<()>;
-    fn avx512bitalg_enabled(&mut self, arg0: Type) -> Option<()>;
-    fn use_lzcnt(&mut self, arg0: Type) -> Option<()>;
-    fn use_bmi1(&mut self, arg0: Type) -> Option<()>;
-    fn use_popcnt(&mut self, arg0: Type) -> Option<()>;
-    fn imm8_from_value(&mut self, arg0: Value) -> Option<Imm8Reg>;
-    fn const_to_type_masked_imm8(&mut self, arg0: u64, arg1: Type) -> Imm8Gpr;
-    fn simm32_from_value(&mut self, arg0: Value) -> Option<GprMemImm>;
-    fn simm32_from_imm64(&mut self, arg0: Imm64) -> Option<GprMemImm>;
-    fn sinkable_load(&mut self, arg0: Value) -> Option<SinkableLoad>;
-    fn sink_load(&mut self, arg0: &SinkableLoad) -> RegMemImm;
-    fn ext_mode(&mut self, arg0: u16, arg1: u16) -> ExtMode;
-    fn nonzero_u64_fits_in_u32(&mut self, arg0: u64) -> Option<u64>;
-    fn ishl_i8x16_mask_for_const(&mut self, arg0: u32) -> SyntheticAmode;
-    fn ishl_i8x16_mask_table(&mut self) -> SyntheticAmode;
-    fn ushr_i8x16_mask_for_const(&mut self, arg0: u32) -> SyntheticAmode;
-    fn ushr_i8x16_mask_table(&mut self) -> SyntheticAmode;
-    fn sse_insertps_lane_imm(&mut self, arg0: u8) -> u8;
-    fn popcount_4bit_table(&mut self) -> VCodeConstant;
-    fn popcount_low_mask(&mut self) -> VCodeConstant;
-}
-
-/// Internal type SideEffectNoResult: defined at src/prelude.isle line 393.
-#[derive(Clone, Debug)]
-pub enum SideEffectNoResult {
-    Inst { inst: MInst },
-}
-
-/// Internal type ProducesFlags: defined at src/prelude.isle line 415.
-#[derive(Clone, Debug)]
-pub enum ProducesFlags {
-    ProducesFlagsSideEffect { inst: MInst },
-    ProducesFlagsReturnsReg { inst: MInst, result: Reg },
-    ProducesFlagsReturnsResultWithConsumer { inst: MInst, result: Reg },
-}
-
-/// Internal type ConsumesFlags: defined at src/prelude.isle line 426.
-#[derive(Clone, Debug)]
-pub enum ConsumesFlags {
-    ConsumesFlagsReturnsResultWithProducer {
-        inst: MInst,
-        result: Reg,
-    },
-    ConsumesFlagsReturnsReg {
-        inst: MInst,
-        result: Reg,
-    },
-    ConsumesFlagsTwiceReturnsValueRegs {
-        inst1: MInst,
-        inst2: MInst,
-        result: ValueRegs,
-    },
-    ConsumesFlagsFourTimesReturnsValueRegs {
-        inst1: MInst,
-        inst2: MInst,
-        inst3: MInst,
-        inst4: MInst,
-        result: ValueRegs,
-    },
-}
-
-/// Internal type MInst: defined at src/isa/x64/inst.isle line 8.
-#[derive(Clone)]
-pub enum MInst {
-    Nop {
-        len: u8,
-    },
-    AluRmiR {
-        size: OperandSize,
-        op: AluRmiROpcode,
-        src1: Gpr,
-        src2: GprMemImm,
-        dst: WritableGpr,
-    },
-    UnaryRmR {
-        size: OperandSize,
-        op: UnaryRmROpcode,
-        src: GprMem,
-        dst: WritableGpr,
-    },
-    Not {
-        size: OperandSize,
-        src: Gpr,
-        dst: WritableGpr,
-    },
-    Neg {
-        size: OperandSize,
-        src: Gpr,
-        dst: WritableGpr,
-    },
-    Div {
-        size: OperandSize,
-        signed: bool,
-        divisor: GprMem,
-        dividend: Gpr,
-        dst_quotient: WritableGpr,
-        dst_remainder: WritableGpr,
-    },
-    MulHi {
-        size: OperandSize,
-        signed: bool,
-        src1: Gpr,
-        src2: GprMem,
-        dst_lo: WritableGpr,
-        dst_hi: WritableGpr,
-    },
-    CheckedDivOrRemSeq {
-        kind: DivOrRemKind,
-        size: OperandSize,
-        dividend: Gpr,
-        divisor: WritableGpr,
-        dst_quotient: WritableGpr,
-        dst_remainder: WritableGpr,
-        tmp: OptionWritableGpr,
-    },
-    SignExtendData {
-        size: OperandSize,
-        src: Gpr,
-        dst: WritableGpr,
-    },
-    Imm {
-        dst_size: OperandSize,
-        simm64: u64,
-        dst: WritableGpr,
-    },
-    MovRR {
-        size: OperandSize,
-        src: Gpr,
-        dst: WritableGpr,
-    },
-    MovzxRmR {
-        ext_mode: ExtMode,
-        src: GprMem,
-        dst: WritableGpr,
-    },
-    Mov64MR {
-        src: SyntheticAmode,
-        dst: WritableGpr,
-    },
-    LoadEffectiveAddress {
-        addr: SyntheticAmode,
-        dst: WritableGpr,
-    },
-    MovsxRmR {
-        ext_mode: ExtMode,
-        src: GprMem,
-        dst: WritableGpr,
-    },
-    MovRM {
-        size: OperandSize,
-        src: Gpr,
-        dst: SyntheticAmode,
-    },
-    ShiftR {
-        size: OperandSize,
-        kind: ShiftKind,
-        src: Gpr,
-        num_bits: Imm8Gpr,
-        dst: WritableGpr,
-    },
-    XmmRmiReg {
-        opcode: SseOpcode,
-        src1: Xmm,
-        src2: XmmMemImm,
-        dst: WritableXmm,
-    },
-    CmpRmiR {
-        size: OperandSize,
-        opcode: CmpOpcode,
-        src: GprMemImm,
-        dst: Gpr,
-    },
-    Setcc {
-        cc: CC,
-        dst: WritableGpr,
-    },
-    Cmove {
-        size: OperandSize,
-        cc: CC,
-        consequent: GprMem,
-        alternative: Gpr,
-        dst: WritableGpr,
-    },
-    XmmCmove {
-        size: OperandSize,
-        cc: CC,
-        consequent: XmmMem,
-        alternative: Xmm,
-        dst: WritableXmm,
-    },
-    Push64 {
-        src: GprMemImm,
-    },
-    Pop64 {
-        dst: WritableGpr,
-    },
-    XmmRmR {
-        op: SseOpcode,
-        src1: Xmm,
-        src2: XmmMem,
-        dst: WritableXmm,
-    },
-    XmmRmREvex {
-        op: Avx512Opcode,
-        src1: XmmMem,
-        src2: Xmm,
-        dst: WritableXmm,
-    },
-    XmmUnaryRmR {
-        op: SseOpcode,
-        src: XmmMem,
-        dst: WritableXmm,
-    },
-    XmmUnaryRmREvex {
-        op: Avx512Opcode,
-        src: XmmMem,
-        dst: WritableXmm,
-    },
-    XmmMovRM {
-        op: SseOpcode,
-        src: Reg,
-        dst: SyntheticAmode,
-    },
-    XmmLoadConst {
-        src: VCodeConstant,
-        dst: WritableReg,
-        ty: Type,
-    },
-    XmmToGpr {
-        op: SseOpcode,
-        src: Xmm,
-        dst: WritableGpr,
-        dst_size: OperandSize,
-    },
-    GprToXmm {
-        op: SseOpcode,
-        src: GprMem,
-        dst: WritableXmm,
-        src_size: OperandSize,
-    },
-    CvtUint64ToFloatSeq {
-        dst_size: OperandSize,
-        src: WritableGpr,
-        dst: WritableXmm,
-        tmp_gpr1: WritableGpr,
-        tmp_gpr2: WritableGpr,
-    },
-    CvtFloatToSintSeq {
-        dst_size: OperandSize,
-        src_size: OperandSize,
-        is_saturating: bool,
-        src: WritableXmm,
-        dst: WritableGpr,
-        tmp_gpr: WritableGpr,
-        tmp_xmm: WritableXmm,
-    },
-    CvtFloatToUintSeq {
-        dst_size: OperandSize,
-        src_size: OperandSize,
-        is_saturating: bool,
-        src: WritableXmm,
-        dst: WritableGpr,
-        tmp_gpr: WritableGpr,
-        tmp_xmm: WritableXmm,
-    },
-    XmmMinMaxSeq {
-        size: OperandSize,
-        is_min: bool,
-        lhs: Xmm,
-        rhs: Xmm,
-        dst: WritableXmm,
-    },
-    XmmCmpRmR {
-        op: SseOpcode,
-        src: XmmMem,
-        dst: Xmm,
-    },
-    XmmRmRImm {
-        op: SseOpcode,
-        src1: Reg,
-        src2: RegMem,
-        dst: WritableReg,
-        imm: u8,
-        size: OperandSize,
-    },
-    CallKnown {
-        dest: ExternalName,
-        uses: VecReg,
-        defs: VecWritableReg,
-        opcode: Opcode,
-    },
-    CallUnknown {
-        dest: RegMem,
-        uses: VecReg,
-        defs: VecWritableReg,
-        opcode: Opcode,
-    },
-    Ret,
-    EpiloguePlaceholder,
-    JmpKnown {
-        dst: MachLabel,
-    },
-    JmpIf {
-        cc: CC,
-        taken: MachLabel,
-    },
-    JmpCond {
-        cc: CC,
-        taken: MachLabel,
-        not_taken: MachLabel,
-    },
-    JmpTableSeq {
-        idx: Reg,
-        tmp1: WritableReg,
-        tmp2: WritableReg,
-        default_target: MachLabel,
-        targets: VecMachLabel,
-        targets_for_term: VecMachLabel,
-    },
-    JmpUnknown {
-        target: RegMem,
-    },
-    TrapIf {
-        cc: CC,
-        trap_code: TrapCode,
-    },
-    Hlt,
-    Ud2 {
-        trap_code: TrapCode,
-    },
-    LoadExtName {
-        dst: WritableReg,
-        name: BoxExternalName,
-        offset: i64,
-    },
-    LockCmpxchg {
-        ty: Type,
-        replacement: Reg,
-        expected: Reg,
-        mem: SyntheticAmode,
-        dst_old: WritableReg,
-    },
-    AtomicRmwSeq {
-        ty: Type,
-        op: AtomicRmwOp,
-        address: Reg,
-        operand: Reg,
-        temp: WritableReg,
-        dst_old: WritableReg,
-    },
-    Fence {
-        kind: FenceKind,
-    },
-    VirtualSPOffsetAdj {
-        offset: i64,
-    },
-    XmmUninitializedValue {
-        dst: WritableXmm,
-    },
-    ElfTlsGetAddr {
-        symbol: ExternalName,
-    },
-    MachOTlsGetAddr {
-        symbol: ExternalName,
-    },
-    ValueLabelMarker {
-        reg: Reg,
-        label: ValueLabel,
-    },
-    Unwind {
-        inst: UnwindInst,
-    },
-}
-
-/// Internal type ExtendKind: defined at src/isa/x64/inst.isle line 1120.
-#[derive(Copy, Clone, PartialEq, Eq, Debug)]
-pub enum ExtendKind {
-    Sign,
-    Zero,
-}
-
-// Generated as internal constructor for term output_reg.
-pub fn constructor_output_reg<C: Context>(ctx: &mut C, arg0: Reg) -> Option<InstOutput> {
-    let pattern0_0 = arg0;
-    // Rule at src/prelude.isle line 86.
-    let expr0_0 = C::value_reg(ctx, pattern0_0);
-    let expr1_0 = C::output(ctx, expr0_0);
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term output_value.
-pub fn constructor_output_value<C: Context>(ctx: &mut C, arg0: Value) -> Option<InstOutput> {
-    let pattern0_0 = arg0;
-    // Rule at src/prelude.isle line 90.
-    let expr0_0 = C::put_in_regs(ctx, pattern0_0);
-    let expr1_0 = C::output(ctx, expr0_0);
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term temp_reg.
-pub fn constructor_temp_reg<C: Context>(ctx: &mut C, arg0: Type) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    // Rule at src/prelude.isle line 110.
-    let expr0_0 = C::temp_writable_reg(ctx, pattern0_0);
-    let expr1_0 = C::writable_reg_to_reg(ctx, expr0_0);
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term lo_reg.
-pub fn constructor_lo_reg<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    // Rule at src/prelude.isle line 145.
-    let expr0_0 = C::put_in_regs(ctx, pattern0_0);
-    let expr1_0: usize = 0;
-    let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term side_effect.
-pub fn constructor_side_effect<C: Context>(
-    ctx: &mut C,
-    arg0: &SideEffectNoResult,
-) -> Option<InstOutput> {
-    let pattern0_0 = arg0;
-    if let &SideEffectNoResult::Inst {
-        inst: ref pattern1_0,
-    } = pattern0_0
-    {
-        // Rule at src/prelude.isle line 398.
-        let expr0_0 = C::emit(ctx, pattern1_0);
-        let expr1_0 = C::output_none(ctx);
-        return Some(expr1_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term safepoint.
-pub fn constructor_safepoint<C: Context>(
-    ctx: &mut C,
-    arg0: &SideEffectNoResult,
-) -> Option<InstOutput> {
-    let pattern0_0 = arg0;
-    if let &SideEffectNoResult::Inst {
-        inst: ref pattern1_0,
-    } = pattern0_0
-    {
-        // Rule at src/prelude.isle line 404.
-        let expr0_0 = C::emit_safepoint(ctx, pattern1_0);
-        let expr1_0 = C::output_none(ctx);
-        return Some(expr1_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term produces_flags_get_reg.
-pub fn constructor_produces_flags_get_reg<C: Context>(
-    ctx: &mut C,
-    arg0: &ProducesFlags,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    if let &ProducesFlags::ProducesFlagsReturnsReg {
-        inst: ref pattern1_0,
-        result: pattern1_1,
-    } = pattern0_0
-    {
-        // Rule at src/prelude.isle line 442.
-        return Some(pattern1_1);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term produces_flags_ignore.
-pub fn constructor_produces_flags_ignore<C: Context>(
-    ctx: &mut C,
-    arg0: &ProducesFlags,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    match pattern0_0 {
-        &ProducesFlags::ProducesFlagsReturnsReg {
-            inst: ref pattern1_0,
-            result: pattern1_1,
-        } => {
-            // Rule at src/prelude.isle line 447.
-            let expr0_0 = ProducesFlags::ProducesFlagsSideEffect {
-                inst: pattern1_0.clone(),
-            };
-            return Some(expr0_0);
-        }
-        &ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
-            inst: ref pattern1_0,
-            result: pattern1_1,
-        } => {
-            // Rule at src/prelude.isle line 449.
-            let expr0_0 = ProducesFlags::ProducesFlagsSideEffect {
-                inst: pattern1_0.clone(),
-            };
-            return Some(expr0_0);
-        }
-        _ => {}
-    }
-    return None;
-}
-
-// Generated as internal constructor for term consumes_flags_concat.
-pub fn constructor_consumes_flags_concat<C: Context>(
-    ctx: &mut C,
-    arg0: &ConsumesFlags,
-    arg1: &ConsumesFlags,
-) -> Option<ConsumesFlags> {
-    let pattern0_0 = arg0;
-    if let &ConsumesFlags::ConsumesFlagsReturnsReg {
-        inst: ref pattern1_0,
-        result: pattern1_1,
-    } = pattern0_0
-    {
-        let pattern2_0 = arg1;
-        if let &ConsumesFlags::ConsumesFlagsReturnsReg {
-            inst: ref pattern3_0,
-            result: pattern3_1,
-        } = pattern2_0
-        {
-            // Rule at src/prelude.isle line 456.
-            let expr0_0 = C::value_regs(ctx, pattern1_1, pattern3_1);
-            let expr1_0 = ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs {
-                inst1: pattern1_0.clone(),
-                inst2: pattern3_0.clone(),
-                result: expr0_0,
-            };
-            return Some(expr1_0);
-        }
-    }
-    return None;
-}
-
-// Generated as internal constructor for term with_flags.
-pub fn constructor_with_flags<C: Context>(
-    ctx: &mut C,
-    arg0: &ProducesFlags,
-    arg1: &ConsumesFlags,
-) -> Option<ValueRegs> {
-    let pattern0_0 = arg0;
-    match pattern0_0 {
-        &ProducesFlags::ProducesFlagsSideEffect {
-            inst: ref pattern1_0,
-        } => {
-            let pattern2_0 = arg1;
-            match pattern2_0 {
-                &ConsumesFlags::ConsumesFlagsReturnsReg {
-                    inst: ref pattern3_0,
-                    result: pattern3_1,
-                } => {
-                    // Rule at src/prelude.isle line 481.
-                    let expr0_0 = C::emit(ctx, pattern1_0);
-                    let expr1_0 = C::emit(ctx, pattern3_0);
-                    let expr2_0 = C::value_reg(ctx, pattern3_1);
-                    return Some(expr2_0);
-                }
-                &ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs {
-                    inst1: ref pattern3_0,
-                    inst2: ref pattern3_1,
-                    result: pattern3_2,
-                } => {
-                    // Rule at src/prelude.isle line 487.
-                    let expr0_0 = C::emit(ctx, pattern1_0);
-                    let expr1_0 = C::emit(ctx, pattern3_0);
-                    let expr2_0 = C::emit(ctx, pattern3_1);
-                    return Some(pattern3_2);
-                }
-                &ConsumesFlags::ConsumesFlagsFourTimesReturnsValueRegs {
-                    inst1: ref pattern3_0,
-                    inst2: ref pattern3_1,
-                    inst3: ref pattern3_2,
-                    inst4: ref pattern3_3,
-                    result: pattern3_4,
-                } => {
-                    // Rule at src/prelude.isle line 499.
-                    let expr0_0 = C::emit(ctx, pattern1_0);
-                    let expr1_0 = C::emit(ctx, pattern3_0);
-                    let expr2_0 = C::emit(ctx, pattern3_1);
-                    let expr3_0 = C::emit(ctx, pattern3_2);
-                    let expr4_0 = C::emit(ctx, pattern3_3);
-                    return Some(pattern3_4);
-                }
-                _ => {}
-            }
-        }
-        &ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
-            inst: ref pattern1_0,
-            result: pattern1_1,
-        } => {
-            let pattern2_0 = arg1;
-            if let &ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
-                inst: ref pattern3_0,
-                result: pattern3_1,
-            } = pattern2_0
-            {
-                // Rule at src/prelude.isle line 475.
-                let expr0_0 = C::emit(ctx, pattern1_0);
-                let expr1_0 = C::emit(ctx, pattern3_0);
-                let expr2_0 = C::value_regs(ctx, pattern1_1, pattern3_1);
-                return Some(expr2_0);
-            }
-        }
-        _ => {}
-    }
-    return None;
-}
-
-// Generated as internal constructor for term with_flags_reg.
-pub fn constructor_with_flags_reg<C: Context>(
-    ctx: &mut C,
-    arg0: &ProducesFlags,
-    arg1: &ConsumesFlags,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/prelude.isle line 516.
-    let expr0_0 = constructor_with_flags(ctx, pattern0_0, pattern1_0)?;
-    let expr1_0: usize = 0;
-    let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term operand_size_bits.
-pub fn constructor_operand_size_bits<C: Context>(ctx: &mut C, arg0: &OperandSize) -> Option<u16> {
-    let pattern0_0 = arg0;
-    match pattern0_0 {
-        &OperandSize::Size8 => {
-            // Rule at src/isa/x64/inst.isle line 510.
-            let expr0_0: u16 = 8;
-            return Some(expr0_0);
-        }
-        &OperandSize::Size16 => {
-            // Rule at src/isa/x64/inst.isle line 511.
-            let expr0_0: u16 = 16;
-            return Some(expr0_0);
-        }
-        &OperandSize::Size32 => {
-            // Rule at src/isa/x64/inst.isle line 512.
-            let expr0_0: u16 = 32;
-            return Some(expr0_0);
-        }
-        &OperandSize::Size64 => {
-            // Rule at src/isa/x64/inst.isle line 513.
-            let expr0_0: u16 = 64;
-            return Some(expr0_0);
-        }
-        _ => {}
-    }
-    return None;
-}
-
-// Generated as internal constructor for term reg_to_gpr_mem_imm.
-pub fn constructor_reg_to_gpr_mem_imm<C: Context>(ctx: &mut C, arg0: Reg) -> Option<GprMemImm> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/x64/inst.isle line 950.
-    let expr0_0 = C::gpr_new(ctx, pattern0_0);
-    let expr1_0 = C::gpr_to_gpr_mem_imm(ctx, expr0_0);
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term put_in_gpr.
-pub fn constructor_put_in_gpr<C: Context>(ctx: &mut C, arg0: Value) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/x64/inst.isle line 957.
-    let expr0_0 = C::put_in_reg(ctx, pattern0_0);
-    let expr1_0 = C::gpr_new(ctx, expr0_0);
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term put_in_gpr_mem.
-pub fn constructor_put_in_gpr_mem<C: Context>(ctx: &mut C, arg0: Value) -> Option<GprMem> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/x64/inst.isle line 964.
-    let expr0_0 = C::put_in_reg_mem(ctx, pattern0_0);
-    let expr1_0 = C::reg_mem_to_gpr_mem(ctx, &expr0_0);
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term put_in_gpr_mem_imm.
-pub fn constructor_put_in_gpr_mem_imm<C: Context>(ctx: &mut C, arg0: Value) -> Option<GprMemImm> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/x64/inst.isle line 971.
-    let expr0_0 = C::put_in_reg_mem_imm(ctx, pattern0_0);
-    let expr1_0 = C::gpr_mem_imm_new(ctx, &expr0_0);
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term put_in_xmm.
-pub fn constructor_put_in_xmm<C: Context>(ctx: &mut C, arg0: Value) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/x64/inst.isle line 978.
-    let expr0_0 = C::put_in_reg(ctx, pattern0_0);
-    let expr1_0 = C::xmm_new(ctx, expr0_0);
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term put_in_xmm_mem.
-pub fn constructor_put_in_xmm_mem<C: Context>(ctx: &mut C, arg0: Value) -> Option<XmmMem> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/x64/inst.isle line 985.
-    let expr0_0 = C::put_in_reg_mem(ctx, pattern0_0);
-    let expr1_0 = C::reg_mem_to_xmm_mem(ctx, &expr0_0);
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term put_in_xmm_mem_imm.
-pub fn constructor_put_in_xmm_mem_imm<C: Context>(ctx: &mut C, arg0: Value) -> Option<XmmMemImm> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/x64/inst.isle line 992.
-    let expr0_0 = C::put_in_reg_mem_imm(ctx, pattern0_0);
-    let expr1_0 = C::xmm_mem_imm_new(ctx, &expr0_0);
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term output_gpr.
-pub fn constructor_output_gpr<C: Context>(ctx: &mut C, arg0: Gpr) -> Option<InstOutput> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/x64/inst.isle line 997.
-    let expr0_0 = C::gpr_to_reg(ctx, pattern0_0);
-    let expr1_0 = constructor_output_reg(ctx, expr0_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term value_gprs.
-pub fn constructor_value_gprs<C: Context>(ctx: &mut C, arg0: Gpr, arg1: Gpr) -> Option<ValueRegs> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1002.
-    let expr0_0 = C::gpr_to_reg(ctx, pattern0_0);
-    let expr1_0 = C::gpr_to_reg(ctx, pattern1_0);
-    let expr2_0 = C::value_regs(ctx, expr0_0, expr1_0);
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term output_xmm.
-pub fn constructor_output_xmm<C: Context>(ctx: &mut C, arg0: Xmm) -> Option<InstOutput> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/x64/inst.isle line 1007.
-    let expr0_0 = C::xmm_to_reg(ctx, pattern0_0);
-    let expr1_0 = constructor_output_reg(ctx, expr0_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term value_regs_get_gpr.
-pub fn constructor_value_regs_get_gpr<C: Context>(
-    ctx: &mut C,
-    arg0: ValueRegs,
-    arg1: usize,
-) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1014.
-    let expr0_0 = C::value_regs_get(ctx, pattern0_0, pattern1_0);
-    let expr1_0 = C::gpr_new(ctx, expr0_0);
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term lo_gpr.
-pub fn constructor_lo_gpr<C: Context>(ctx: &mut C, arg0: Value) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/x64/inst.isle line 1027.
-    let expr0_0 = constructor_lo_reg(ctx, pattern0_0)?;
-    let expr1_0 = C::gpr_new(ctx, expr0_0);
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term sink_load_to_gpr_mem_imm.
-pub fn constructor_sink_load_to_gpr_mem_imm<C: Context>(
-    ctx: &mut C,
-    arg0: &SinkableLoad,
-) -> Option<GprMemImm> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/x64/inst.isle line 1110.
-    let expr0_0 = C::sink_load(ctx, pattern0_0);
-    let expr1_0 = C::gpr_mem_imm_new(ctx, &expr0_0);
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term extend_to_gpr.
-pub fn constructor_extend_to_gpr<C: Context>(
-    ctx: &mut C,
-    arg0: Value,
-    arg1: Type,
-    arg2: &ExtendKind,
-) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = C::value_type(ctx, pattern0_0);
-    let pattern2_0 = arg1;
-    if pattern2_0 == pattern1_0 {
-        let pattern4_0 = arg2;
-        // Rule at src/isa/x64/inst.isle line 1132.
-        let expr0_0 = constructor_put_in_gpr(ctx, pattern0_0)?;
-        return Some(expr0_0);
-    }
-    let pattern3_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 1135.
-    let expr0_0 = C::ty_bits_u16(ctx, pattern1_0);
-    let expr1_0 = C::operand_size_of_type_32_64(ctx, pattern2_0);
-    let expr2_0 = constructor_operand_size_bits(ctx, &expr1_0)?;
-    let expr3_0 = C::ext_mode(ctx, expr0_0, expr2_0);
-    let expr4_0 = constructor_put_in_gpr_mem(ctx, pattern0_0)?;
-    let expr5_0 = constructor_extend(ctx, pattern3_0, pattern2_0, &expr3_0, &expr4_0)?;
-    return Some(expr5_0);
-}
-
-// Generated as internal constructor for term extend.
-pub fn constructor_extend<C: Context>(
-    ctx: &mut C,
-    arg0: &ExtendKind,
-    arg1: Type,
-    arg2: &ExtMode,
-    arg3: &GprMem,
-) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    match pattern0_0 {
-        &ExtendKind::Sign => {
-            let pattern2_0 = arg1;
-            let pattern3_0 = arg2;
-            let pattern4_0 = arg3;
-            // Rule at src/isa/x64/inst.isle line 1155.
-            let expr0_0 = constructor_movsx(ctx, pattern2_0, pattern3_0, pattern4_0)?;
-            return Some(expr0_0);
-        }
-        &ExtendKind::Zero => {
-            let pattern2_0 = arg1;
-            let pattern3_0 = arg2;
-            let pattern4_0 = arg3;
-            // Rule at src/isa/x64/inst.isle line 1151.
-            let expr0_0 = constructor_movzx(ctx, pattern2_0, pattern3_0, pattern4_0)?;
-            return Some(expr0_0);
-        }
-        _ => {}
-    }
-    return None;
-}
-
-// Generated as internal constructor for term sse_xor_op.
-pub fn constructor_sse_xor_op<C: Context>(ctx: &mut C, arg0: Type) -> Option<SseOpcode> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == F32X4 {
-        // Rule at src/isa/x64/inst.isle line 1162.
-        let expr0_0 = SseOpcode::Xorps;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == F64X2 {
-        // Rule at src/isa/x64/inst.isle line 1163.
-        let expr0_0 = SseOpcode::Xorpd;
-        return Some(expr0_0);
-    }
-    if let Some((pattern1_0, pattern1_1)) = C::multi_lane(ctx, pattern0_0) {
-        // Rule at src/isa/x64/inst.isle line 1164.
-        let expr0_0 = SseOpcode::Pxor;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term sse_xor.
-pub fn constructor_sse_xor<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Xmm,
-    arg2: &XmmMem,
-) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 1168.
-    let expr0_0 = constructor_sse_xor_op(ctx, pattern0_0)?;
-    let expr1_0 = constructor_xmm_rm_r(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term sse_cmp_op.
-pub fn constructor_sse_cmp_op<C: Context>(ctx: &mut C, arg0: Type) -> Option<SseOpcode> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == F32X4 {
-        // Rule at src/isa/x64/inst.isle line 1177.
-        let expr0_0 = SseOpcode::Cmpps;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == F64X2 {
-        // Rule at src/isa/x64/inst.isle line 1178.
-        let expr0_0 = SseOpcode::Cmppd;
-        return Some(expr0_0);
-    }
-    if let Some((pattern1_0, pattern1_1)) = C::multi_lane(ctx, pattern0_0) {
-        if pattern1_0 == 8 {
-            if pattern1_1 == 16 {
-                // Rule at src/isa/x64/inst.isle line 1173.
-                let expr0_0 = SseOpcode::Pcmpeqb;
-                return Some(expr0_0);
-            }
-        }
-        if pattern1_0 == 16 {
-            if pattern1_1 == 8 {
-                // Rule at src/isa/x64/inst.isle line 1174.
-                let expr0_0 = SseOpcode::Pcmpeqw;
-                return Some(expr0_0);
-            }
-        }
-        if pattern1_0 == 32 {
-            if pattern1_1 == 4 {
-                // Rule at src/isa/x64/inst.isle line 1175.
-                let expr0_0 = SseOpcode::Pcmpeqd;
-                return Some(expr0_0);
-            }
-        }
-        if pattern1_0 == 64 {
-            if pattern1_1 == 2 {
-                // Rule at src/isa/x64/inst.isle line 1176.
-                let expr0_0 = SseOpcode::Pcmpeqq;
-                return Some(expr0_0);
-            }
-        }
-    }
-    return None;
-}
-
-// Generated as internal constructor for term vector_all_ones.
-pub fn constructor_vector_all_ones<C: Context>(ctx: &mut C, arg0: Type) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/x64/inst.isle line 1192.
-    let expr0_0 = C::temp_writable_xmm(ctx);
-    let expr1_0: Type = I32X4;
-    let expr2_0 = constructor_sse_cmp_op(ctx, expr1_0)?;
-    let expr3_0 = C::writable_xmm_to_xmm(ctx, expr0_0);
-    let expr4_0 = constructor_writable_xmm_to_xmm_mem(ctx, expr0_0)?;
-    let expr5_0 = MInst::XmmRmR {
-        op: expr2_0,
-        src1: expr3_0,
-        src2: expr4_0,
-        dst: expr0_0,
-    };
-    let expr6_0 = C::emit(ctx, &expr5_0);
-    let expr7_0 = C::writable_xmm_to_xmm(ctx, expr0_0);
-    return Some(expr7_0);
-}
-
-// Generated as internal constructor for term make_i64x2_from_lanes.
-pub fn constructor_make_i64x2_from_lanes<C: Context>(
-    ctx: &mut C,
-    arg0: &GprMem,
-    arg1: &GprMem,
-) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1202.
-    let expr0_0 = C::temp_writable_xmm(ctx);
-    let expr1_0 = C::writable_xmm_to_reg(ctx, expr0_0);
-    let expr2_0 = MInst::XmmUninitializedValue { dst: expr0_0 };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = SseOpcode::Pinsrd;
-    let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    let expr6_0 = C::gpr_mem_to_reg_mem(ctx, pattern0_0);
-    let expr7_0: u8 = 0;
-    let expr8_0 = OperandSize::Size64;
-    let expr9_0 = MInst::XmmRmRImm {
-        op: expr4_0,
-        src1: expr5_0,
-        src2: expr6_0,
-        dst: expr1_0,
-        imm: expr7_0,
-        size: expr8_0,
-    };
-    let expr10_0 = C::emit(ctx, &expr9_0);
-    let expr11_0 = SseOpcode::Pinsrd;
-    let expr12_0 = C::writable_reg_to_reg(ctx, expr1_0);
-    let expr13_0 = C::gpr_mem_to_reg_mem(ctx, pattern1_0);
-    let expr14_0: u8 = 1;
-    let expr15_0 = OperandSize::Size64;
-    let expr16_0 = MInst::XmmRmRImm {
-        op: expr11_0,
-        src1: expr12_0,
-        src2: expr13_0,
-        dst: expr1_0,
-        imm: expr14_0,
-        size: expr15_0,
-    };
-    let expr17_0 = C::emit(ctx, &expr16_0);
-    let expr18_0 = C::writable_xmm_to_xmm(ctx, expr0_0);
-    return Some(expr18_0);
-}
-
-// Generated as internal constructor for term mov_rmi_to_xmm.
-pub fn constructor_mov_rmi_to_xmm<C: Context>(ctx: &mut C, arg0: &RegMemImm) -> Option<XmmMemImm> {
-    let pattern0_0 = arg0;
-    match pattern0_0 {
-        &RegMemImm::Imm { simm32: pattern1_0 } => {
-            // Rule at src/isa/x64/inst.isle line 1223.
-            let expr0_0 = C::xmm_mem_imm_new(ctx, pattern0_0);
-            return Some(expr0_0);
-        }
-        &RegMemImm::Reg { reg: pattern1_0 } => {
-            // Rule at src/isa/x64/inst.isle line 1224.
-            let expr0_0 = SseOpcode::Movd;
-            let expr1_0 = C::reg_to_gpr_mem(ctx, pattern1_0);
-            let expr2_0 = OperandSize::Size32;
-            let expr3_0 = constructor_gpr_to_xmm(ctx, &expr0_0, &expr1_0, &expr2_0)?;
-            let expr4_0 = C::xmm_to_xmm_mem_imm(ctx, expr3_0);
-            return Some(expr4_0);
-        }
-        &RegMemImm::Mem {
-            addr: ref pattern1_0,
-        } => {
-            // Rule at src/isa/x64/inst.isle line 1222.
-            let expr0_0 = C::xmm_mem_imm_new(ctx, pattern0_0);
-            return Some(expr0_0);
-        }
-        _ => {}
-    }
-    return None;
-}
-
-// Generated as internal constructor for term x64_load.
-pub fn constructor_x64_load<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &SyntheticAmode,
-    arg2: &ExtKind,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I64 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/x64/inst.isle line 1239.
-        let expr0_0 = C::temp_writable_gpr(ctx);
-        let expr1_0 = MInst::Mov64MR {
-            src: pattern2_0.clone(),
-            dst: expr0_0,
-        };
-        let expr2_0 = C::emit(ctx, &expr1_0);
-        let expr3_0 = constructor_writable_gpr_to_r_reg(ctx, expr0_0)?;
-        return Some(expr3_0);
-    }
-    if pattern0_0 == F32 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/x64/inst.isle line 1244.
-        let expr0_0 = SseOpcode::Movss;
-        let expr1_0 = constructor_synthetic_amode_to_xmm_mem(ctx, pattern2_0)?;
-        let expr2_0 = constructor_xmm_unary_rm_r(ctx, &expr0_0, &expr1_0)?;
-        let expr3_0 = C::xmm_to_reg(ctx, expr2_0);
-        return Some(expr3_0);
-    }
-    if pattern0_0 == F64 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/x64/inst.isle line 1248.
-        let expr0_0 = SseOpcode::Movsd;
-        let expr1_0 = constructor_synthetic_amode_to_xmm_mem(ctx, pattern2_0)?;
-        let expr2_0 = constructor_xmm_unary_rm_r(ctx, &expr0_0, &expr1_0)?;
-        let expr3_0 = C::xmm_to_reg(ctx, expr2_0);
-        return Some(expr3_0);
-    }
-    if pattern0_0 == F32X4 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/x64/inst.isle line 1252.
-        let expr0_0 = SseOpcode::Movups;
-        let expr1_0 = constructor_synthetic_amode_to_xmm_mem(ctx, pattern2_0)?;
-        let expr2_0 = constructor_xmm_unary_rm_r(ctx, &expr0_0, &expr1_0)?;
-        let expr3_0 = C::xmm_to_reg(ctx, expr2_0);
-        return Some(expr3_0);
-    }
-    if pattern0_0 == F64X2 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/x64/inst.isle line 1256.
-        let expr0_0 = SseOpcode::Movupd;
-        let expr1_0 = constructor_synthetic_amode_to_xmm_mem(ctx, pattern2_0)?;
-        let expr2_0 = constructor_xmm_unary_rm_r(ctx, &expr0_0, &expr1_0)?;
-        let expr3_0 = C::xmm_to_reg(ctx, expr2_0);
-        return Some(expr3_0);
-    }
-    if let Some((pattern1_0, pattern1_1)) = C::multi_lane(ctx, pattern0_0) {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/x64/inst.isle line 1260.
-        let expr0_0 = SseOpcode::Movdqu;
-        let expr1_0 = constructor_synthetic_amode_to_xmm_mem(ctx, pattern2_0)?;
-        let expr2_0 = constructor_xmm_unary_rm_r(ctx, &expr0_0, &expr1_0)?;
-        let expr3_0 = C::xmm_to_reg(ctx, expr2_0);
-        return Some(expr3_0);
-    }
-    if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        if let &ExtKind::SignExtend = pattern3_0 {
-            // Rule at src/isa/x64/inst.isle line 1234.
-            let expr0_0 = C::ty_bytes(ctx, pattern1_0);
-            let expr1_0: u16 = 8;
-            let expr2_0 = C::ext_mode(ctx, expr0_0, expr1_0);
-            let expr3_0 = constructor_synthetic_amode_to_gpr_mem(ctx, pattern2_0)?;
-            let expr4_0 = constructor_movsx(ctx, pattern1_0, &expr2_0, &expr3_0)?;
-            let expr5_0 = C::gpr_to_reg(ctx, expr4_0);
-            return Some(expr5_0);
-        }
-    }
-    return None;
-}
-
-// Generated as internal constructor for term xmm_load_const.
-pub fn constructor_xmm_load_const<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: VCodeConstant,
-) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1266.
-    let expr0_0 = C::temp_writable_xmm(ctx);
-    let expr1_0 = C::writable_xmm_to_reg(ctx, expr0_0);
-    let expr2_0 = MInst::XmmLoadConst {
-        src: pattern1_0,
-        dst: expr1_0,
-        ty: pattern0_0,
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_xmm_to_xmm(ctx, expr0_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term alu_rmi_r.
-pub fn constructor_alu_rmi_r<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &AluRmiROpcode,
-    arg2: Gpr,
-    arg3: &GprMemImm,
-) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/x64/inst.isle line 1279.
-    let expr0_0 = C::temp_writable_gpr(ctx);
-    let expr1_0 = C::operand_size_of_type_32_64(ctx, pattern0_0);
-    let expr2_0 = MInst::AluRmiR {
-        size: expr1_0,
-        op: pattern1_0.clone(),
-        src1: pattern2_0,
-        src2: pattern3_0.clone(),
-        dst: expr0_0,
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_gpr_to_gpr(ctx, expr0_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term add.
-pub fn constructor_add<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Gpr,
-    arg2: &GprMemImm,
-) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 1287.
-    let expr0_0 = AluRmiROpcode::Add;
-    let expr1_0 = constructor_alu_rmi_r(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term add_with_flags_paired.
-pub fn constructor_add_with_flags_paired<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Gpr,
-    arg2: &GprMemImm,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 1295.
-    let expr0_0 = C::temp_writable_gpr(ctx);
-    let expr1_0 = C::operand_size_of_type_32_64(ctx, pattern0_0);
-    let expr2_0 = AluRmiROpcode::Add;
-    let expr3_0 = MInst::AluRmiR {
-        size: expr1_0,
-        op: expr2_0,
-        src1: pattern1_0,
-        src2: pattern2_0.clone(),
-        dst: expr0_0,
-    };
-    let expr4_0 = constructor_writable_gpr_to_r_reg(ctx, expr0_0)?;
-    let expr5_0 = ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
-        inst: expr3_0,
-        result: expr4_0,
-    };
-    return Some(expr5_0);
-}
-
-// Generated as internal constructor for term adc_paired.
-pub fn constructor_adc_paired<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Gpr,
-    arg2: &GprMemImm,
-) -> Option<ConsumesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 1307.
-    let expr0_0 = C::temp_writable_gpr(ctx);
-    let expr1_0 = C::operand_size_of_type_32_64(ctx, pattern0_0);
-    let expr2_0 = AluRmiROpcode::Adc;
-    let expr3_0 = MInst::AluRmiR {
-        size: expr1_0,
-        op: expr2_0,
-        src1: pattern1_0,
-        src2: pattern2_0.clone(),
-        dst: expr0_0,
-    };
-    let expr4_0 = constructor_writable_gpr_to_r_reg(ctx, expr0_0)?;
-    let expr5_0 = ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
-        inst: expr3_0,
-        result: expr4_0,
-    };
-    return Some(expr5_0);
-}
-
-// Generated as internal constructor for term sub.
-pub fn constructor_sub<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Gpr,
-    arg2: &GprMemImm,
-) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 1319.
-    let expr0_0 = AluRmiROpcode::Sub;
-    let expr1_0 = constructor_alu_rmi_r(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term sub_with_flags_paired.
-pub fn constructor_sub_with_flags_paired<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Gpr,
-    arg2: &GprMemImm,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 1327.
-    let expr0_0 = C::temp_writable_gpr(ctx);
-    let expr1_0 = C::operand_size_of_type_32_64(ctx, pattern0_0);
-    let expr2_0 = AluRmiROpcode::Sub;
-    let expr3_0 = MInst::AluRmiR {
-        size: expr1_0,
-        op: expr2_0,
-        src1: pattern1_0,
-        src2: pattern2_0.clone(),
-        dst: expr0_0,
-    };
-    let expr4_0 = constructor_writable_gpr_to_r_reg(ctx, expr0_0)?;
-    let expr5_0 = ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
-        inst: expr3_0,
-        result: expr4_0,
-    };
-    return Some(expr5_0);
-}
-
-// Generated as internal constructor for term sbb_paired.
-pub fn constructor_sbb_paired<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Gpr,
-    arg2: &GprMemImm,
-) -> Option<ConsumesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 1339.
-    let expr0_0 = C::temp_writable_gpr(ctx);
-    let expr1_0 = C::operand_size_of_type_32_64(ctx, pattern0_0);
-    let expr2_0 = AluRmiROpcode::Sbb;
-    let expr3_0 = MInst::AluRmiR {
-        size: expr1_0,
-        op: expr2_0,
-        src1: pattern1_0,
-        src2: pattern2_0.clone(),
-        dst: expr0_0,
-    };
-    let expr4_0 = constructor_writable_gpr_to_r_reg(ctx, expr0_0)?;
-    let expr5_0 = ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
-        inst: expr3_0,
-        result: expr4_0,
-    };
-    return Some(expr5_0);
-}
-
-// Generated as internal constructor for term mul.
-pub fn constructor_mul<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Gpr,
-    arg2: &GprMemImm,
-) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 1351.
-    let expr0_0 = AluRmiROpcode::Mul;
-    let expr1_0 = constructor_alu_rmi_r(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term x64_and.
-pub fn constructor_x64_and<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Gpr,
-    arg2: &GprMemImm,
-) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 1359.
-    let expr0_0 = AluRmiROpcode::And;
-    let expr1_0 = constructor_alu_rmi_r(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term or.
-pub fn constructor_or<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Gpr,
-    arg2: &GprMemImm,
-) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 1367.
-    let expr0_0 = AluRmiROpcode::Or;
-    let expr1_0 = constructor_alu_rmi_r(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term xor.
-pub fn constructor_xor<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Gpr,
-    arg2: &GprMemImm,
-) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 1375.
-    let expr0_0 = AluRmiROpcode::Xor;
-    let expr1_0 = constructor_alu_rmi_r(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term imm.
-pub fn constructor_imm<C: Context>(ctx: &mut C, arg0: Type, arg1: u64) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I64 {
-        let pattern2_0 = arg1;
-        if let Some(pattern3_0) = C::nonzero_u64_fits_in_u32(ctx, pattern2_0) {
-            // Rule at src/isa/x64/inst.isle line 1415.
-            let expr0_0 = C::temp_writable_gpr(ctx);
-            let expr1_0 = OperandSize::Size32;
-            let expr2_0 = MInst::Imm {
-                dst_size: expr1_0,
-                simm64: pattern3_0,
-                dst: expr0_0,
-            };
-            let expr3_0 = C::emit(ctx, &expr2_0);
-            let expr4_0 = constructor_writable_gpr_to_r_reg(ctx, expr0_0)?;
-            return Some(expr4_0);
-        }
-    }
-    if pattern0_0 == F32 {
-        let pattern2_0 = arg1;
-        if pattern2_0 == 0 {
-            // Rule at src/isa/x64/inst.isle line 1444.
-            let expr0_0 = C::temp_writable_xmm(ctx);
-            let expr1_0 = C::writable_xmm_to_xmm(ctx, expr0_0);
-            let expr2_0 = SseOpcode::Xorps;
-            let expr3_0 = C::xmm_to_xmm_mem(ctx, expr1_0);
-            let expr4_0 = MInst::XmmRmR {
-                op: expr2_0,
-                src1: expr1_0,
-                src2: expr3_0,
-                dst: expr0_0,
-            };
-            let expr5_0 = C::emit(ctx, &expr4_0);
-            let expr6_0 = C::xmm_to_reg(ctx, expr1_0);
-            return Some(expr6_0);
-        }
-        // Rule at src/isa/x64/inst.isle line 1392.
-        let expr0_0 = SseOpcode::Movd;
-        let expr1_0: Type = I32;
-        let expr2_0 = constructor_imm(ctx, expr1_0, pattern2_0)?;
-        let expr3_0 = C::reg_to_gpr_mem(ctx, expr2_0);
-        let expr4_0 = OperandSize::Size32;
-        let expr5_0 = constructor_gpr_to_xmm(ctx, &expr0_0, &expr3_0, &expr4_0)?;
-        let expr6_0 = C::xmm_to_reg(ctx, expr5_0);
-        return Some(expr6_0);
-    }
-    if pattern0_0 == F64 {
-        let pattern2_0 = arg1;
-        if pattern2_0 == 0 {
-            // Rule at src/isa/x64/inst.isle line 1456.
-            let expr0_0 = C::temp_writable_xmm(ctx);
-            let expr1_0 = C::writable_xmm_to_xmm(ctx, expr0_0);
-            let expr2_0 = SseOpcode::Xorpd;
-            let expr3_0 = C::xmm_to_xmm_mem(ctx, expr1_0);
-            let expr4_0 = MInst::XmmRmR {
-                op: expr2_0,
-                src1: expr1_0,
-                src2: expr3_0,
-                dst: expr0_0,
-            };
-            let expr5_0 = C::emit(ctx, &expr4_0);
-            let expr6_0 = C::xmm_to_reg(ctx, expr1_0);
-            return Some(expr6_0);
-        }
-        // Rule at src/isa/x64/inst.isle line 1398.
-        let expr0_0 = SseOpcode::Movq;
-        let expr1_0: Type = I64;
-        let expr2_0 = constructor_imm(ctx, expr1_0, pattern2_0)?;
-        let expr3_0 = C::reg_to_gpr_mem(ctx, expr2_0);
-        let expr4_0 = OperandSize::Size64;
-        let expr5_0 = constructor_gpr_to_xmm(ctx, &expr0_0, &expr3_0, &expr4_0)?;
-        let expr6_0 = C::xmm_to_reg(ctx, expr5_0);
-        return Some(expr6_0);
-    }
-    if let Some((pattern1_0, pattern1_1)) = C::multi_lane(ctx, pattern0_0) {
-        let pattern2_0 = arg1;
-        if pattern2_0 == 0 {
-            // Rule at src/isa/x64/inst.isle line 1434.
-            let expr0_0 = C::temp_writable_xmm(ctx);
-            let expr1_0 = C::writable_xmm_to_xmm(ctx, expr0_0);
-            let expr2_0 = constructor_sse_xor_op(ctx, pattern0_0)?;
-            let expr3_0 = C::xmm_to_xmm_mem(ctx, expr1_0);
-            let expr4_0 = MInst::XmmRmR {
-                op: expr2_0,
-                src1: expr1_0,
-                src2: expr3_0,
-                dst: expr0_0,
-            };
-            let expr5_0 = C::emit(ctx, &expr4_0);
-            let expr6_0 = C::xmm_to_reg(ctx, expr1_0);
-            return Some(expr6_0);
-        }
-    }
-    if let Some(pattern1_0) = C::fits_in_64(ctx, pattern0_0) {
-        let pattern2_0 = arg1;
-        if pattern2_0 == 0 {
-            // Rule at src/isa/x64/inst.isle line 1421.
-            let expr0_0 = C::temp_writable_gpr(ctx);
-            let expr1_0 = C::writable_gpr_to_gpr(ctx, expr0_0);
-            let expr2_0 = C::operand_size_of_type_32_64(ctx, pattern1_0);
-            let expr3_0 = AluRmiROpcode::Xor;
-            let expr4_0 = C::gpr_to_gpr_mem_imm(ctx, expr1_0);
-            let expr5_0 = MInst::AluRmiR {
-                size: expr2_0,
-                op: expr3_0,
-                src1: expr1_0,
-                src2: expr4_0,
-                dst: expr0_0,
-            };
-            let expr6_0 = C::emit(ctx, &expr5_0);
-            let expr7_0 = C::gpr_to_reg(ctx, expr1_0);
-            return Some(expr7_0);
-        }
-        // Rule at src/isa/x64/inst.isle line 1385.
-        let expr0_0 = C::temp_writable_gpr(ctx);
-        let expr1_0 = C::operand_size_of_type_32_64(ctx, pattern1_0);
-        let expr2_0 = MInst::Imm {
-            dst_size: expr1_0,
-            simm64: pattern2_0,
-            dst: expr0_0,
-        };
-        let expr3_0 = C::emit(ctx, &expr2_0);
-        let expr4_0 = constructor_writable_gpr_to_r_reg(ctx, expr0_0)?;
-        return Some(expr4_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term imm_i64.
-pub fn constructor_imm_i64<C: Context>(ctx: &mut C, arg0: Type, arg1: i64) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1407.
-    let expr0_0 = C::i64_as_u64(ctx, pattern1_0);
-    let expr1_0 = constructor_imm(ctx, pattern0_0, expr0_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term shift_r.
-pub fn constructor_shift_r<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &ShiftKind,
-    arg2: Gpr,
-    arg3: &Imm8Gpr,
-) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/x64/inst.isle line 1469.
-    let expr0_0 = C::temp_writable_gpr(ctx);
-    let expr1_0 = C::raw_operand_size_of_type(ctx, pattern0_0);
-    let expr2_0 = MInst::ShiftR {
-        size: expr1_0,
-        kind: pattern1_0.clone(),
-        src: pattern2_0,
-        num_bits: pattern3_0.clone(),
-        dst: expr0_0,
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_gpr_to_gpr(ctx, expr0_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term x64_rotl.
-pub fn constructor_x64_rotl<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Gpr,
-    arg2: &Imm8Gpr,
-) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 1479.
-    let expr0_0 = ShiftKind::RotateLeft;
-    let expr1_0 = constructor_shift_r(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term x64_rotr.
-pub fn constructor_x64_rotr<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Gpr,
-    arg2: &Imm8Gpr,
-) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 1484.
-    let expr0_0 = ShiftKind::RotateRight;
-    let expr1_0 = constructor_shift_r(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term shl.
-pub fn constructor_shl<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Gpr,
-    arg2: &Imm8Gpr,
-) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 1489.
-    let expr0_0 = ShiftKind::ShiftLeft;
-    let expr1_0 = constructor_shift_r(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term shr.
-pub fn constructor_shr<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Gpr,
-    arg2: &Imm8Gpr,
-) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 1494.
-    let expr0_0 = ShiftKind::ShiftRightLogical;
-    let expr1_0 = constructor_shift_r(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term sar.
-pub fn constructor_sar<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Gpr,
-    arg2: &Imm8Gpr,
-) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 1499.
-    let expr0_0 = ShiftKind::ShiftRightArithmetic;
-    let expr1_0 = constructor_shift_r(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term cmp_rmi_r.
-pub fn constructor_cmp_rmi_r<C: Context>(
-    ctx: &mut C,
-    arg0: &OperandSize,
-    arg1: &CmpOpcode,
-    arg2: &GprMemImm,
-    arg3: Gpr,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/x64/inst.isle line 1504.
-    let expr0_0 = MInst::CmpRmiR {
-        size: pattern0_0.clone(),
-        opcode: pattern1_0.clone(),
-        src: pattern2_0.clone(),
-        dst: pattern3_0,
-    };
-    let expr1_0 = ProducesFlags::ProducesFlagsSideEffect { inst: expr0_0 };
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term cmp.
-pub fn constructor_cmp<C: Context>(
-    ctx: &mut C,
-    arg0: &OperandSize,
-    arg1: &GprMemImm,
-    arg2: Gpr,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 1513.
-    let expr0_0 = CmpOpcode::Cmp;
-    let expr1_0 = constructor_cmp_rmi_r(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term cmp_imm.
-pub fn constructor_cmp_imm<C: Context>(
-    ctx: &mut C,
-    arg0: &OperandSize,
-    arg1: u32,
-    arg2: Gpr,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 1518.
-    let expr0_0 = CmpOpcode::Cmp;
-    let expr1_0 = RegMemImm::Imm { simm32: pattern1_0 };
-    let expr2_0 = C::gpr_mem_imm_new(ctx, &expr1_0);
-    let expr3_0 = constructor_cmp_rmi_r(ctx, pattern0_0, &expr0_0, &expr2_0, pattern2_0)?;
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term xmm_cmp_rm_r.
-pub fn constructor_xmm_cmp_rm_r<C: Context>(
-    ctx: &mut C,
-    arg0: &SseOpcode,
-    arg1: &XmmMem,
-    arg2: Xmm,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 1523.
-    let expr0_0 = MInst::XmmCmpRmR {
-        op: pattern0_0.clone(),
-        src: pattern1_0.clone(),
-        dst: pattern2_0,
-    };
-    let expr1_0 = ProducesFlags::ProducesFlagsSideEffect { inst: expr0_0 };
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term fpcmp.
-pub fn constructor_fpcmp<C: Context>(
-    ctx: &mut C,
-    arg0: Value,
-    arg1: Value,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = C::value_type(ctx, pattern0_0);
-    if pattern1_0 == F32 {
-        let pattern3_0 = arg1;
-        // Rule at src/isa/x64/inst.isle line 1530.
-        let expr0_0 = SseOpcode::Ucomiss;
-        let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern0_0)?;
-        let expr2_0 = constructor_put_in_xmm(ctx, pattern3_0)?;
-        let expr3_0 = constructor_xmm_cmp_rm_r(ctx, &expr0_0, &expr1_0, expr2_0)?;
-        return Some(expr3_0);
-    }
-    if pattern1_0 == F64 {
-        let pattern3_0 = arg1;
-        // Rule at src/isa/x64/inst.isle line 1532.
-        let expr0_0 = SseOpcode::Ucomisd;
-        let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern0_0)?;
-        let expr2_0 = constructor_put_in_xmm(ctx, pattern3_0)?;
-        let expr3_0 = constructor_xmm_cmp_rm_r(ctx, &expr0_0, &expr1_0, expr2_0)?;
-        return Some(expr3_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term test.
-pub fn constructor_test<C: Context>(
-    ctx: &mut C,
-    arg0: &OperandSize,
-    arg1: &GprMemImm,
-    arg2: Gpr,
-) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 1537.
-    let expr0_0 = CmpOpcode::Test;
-    let expr1_0 = constructor_cmp_rmi_r(ctx, pattern0_0, &expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term cmove.
-pub fn constructor_cmove<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &CC,
-    arg2: &GprMem,
-    arg3: Gpr,
-) -> Option<ConsumesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/x64/inst.isle line 1544.
-    let expr0_0 = C::temp_writable_gpr(ctx);
-    let expr1_0 = C::operand_size_of_type_32_64(ctx, pattern0_0);
-    let expr2_0 = MInst::Cmove {
-        size: expr1_0,
-        cc: pattern1_0.clone(),
-        consequent: pattern2_0.clone(),
-        alternative: pattern3_0,
-        dst: expr0_0,
-    };
-    let expr3_0 = constructor_writable_gpr_to_r_reg(ctx, expr0_0)?;
-    let expr4_0 = ConsumesFlags::ConsumesFlagsReturnsReg {
-        inst: expr2_0,
-        result: expr3_0,
-    };
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term cmove_xmm.
-pub fn constructor_cmove_xmm<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &CC,
-    arg2: &XmmMem,
-    arg3: Xmm,
-) -> Option<ConsumesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/x64/inst.isle line 1552.
-    let expr0_0 = C::temp_writable_xmm(ctx);
-    let expr1_0 = C::operand_size_of_type_32_64(ctx, pattern0_0);
-    let expr2_0 = MInst::XmmCmove {
-        size: expr1_0,
-        cc: pattern1_0.clone(),
-        consequent: pattern2_0.clone(),
-        alternative: pattern3_0,
-        dst: expr0_0,
-    };
-    let expr3_0 = constructor_writable_xmm_to_r_reg(ctx, expr0_0)?;
-    let expr4_0 = ConsumesFlags::ConsumesFlagsReturnsReg {
-        inst: expr2_0,
-        result: expr3_0,
-    };
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term cmove_from_values.
-pub fn constructor_cmove_from_values<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &CC,
-    arg2: Value,
-    arg3: Value,
-) -> Option<ConsumesFlags> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I128 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/x64/inst.isle line 1563.
-        let expr0_0 = C::put_in_regs(ctx, pattern3_0);
-        let expr1_0 = C::put_in_regs(ctx, pattern4_0);
-        let expr2_0 = C::temp_writable_gpr(ctx);
-        let expr3_0 = C::temp_writable_gpr(ctx);
-        let expr4_0 = OperandSize::Size64;
-        let expr5_0: usize = 0;
-        let expr6_0 = constructor_value_regs_get_gpr(ctx, expr0_0, expr5_0)?;
-        let expr7_0 = C::gpr_to_gpr_mem(ctx, expr6_0);
-        let expr8_0: usize = 0;
-        let expr9_0 = constructor_value_regs_get_gpr(ctx, expr1_0, expr8_0)?;
-        let expr10_0 = MInst::Cmove {
-            size: expr4_0,
-            cc: pattern2_0.clone(),
-            consequent: expr7_0,
-            alternative: expr9_0,
-            dst: expr2_0,
-        };
-        let expr11_0: usize = 1;
-        let expr12_0 = constructor_value_regs_get_gpr(ctx, expr0_0, expr11_0)?;
-        let expr13_0 = C::gpr_to_gpr_mem(ctx, expr12_0);
-        let expr14_0: usize = 1;
-        let expr15_0 = constructor_value_regs_get_gpr(ctx, expr1_0, expr14_0)?;
-        let expr16_0 = MInst::Cmove {
-            size: expr4_0,
-            cc: pattern2_0.clone(),
-            consequent: expr13_0,
-            alternative: expr15_0,
-            dst: expr3_0,
-        };
-        let expr17_0 = constructor_writable_gpr_to_r_reg(ctx, expr2_0)?;
-        let expr18_0 = constructor_writable_gpr_to_r_reg(ctx, expr3_0)?;
-        let expr19_0 = C::value_regs(ctx, expr17_0, expr18_0);
-        let expr20_0 = ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs {
-            inst1: expr10_0,
-            inst2: expr16_0,
-            result: expr19_0,
-        };
-        return Some(expr20_0);
-    }
-    if let Some(pattern1_0) = C::is_xmm_type(ctx, pattern0_0) {
-        if let Some(pattern2_0) = C::is_single_register_type(ctx, pattern1_0) {
-            let pattern3_0 = arg1;
-            let pattern4_0 = arg2;
-            let pattern5_0 = arg3;
-            // Rule at src/isa/x64/inst.isle line 1587.
-            let expr0_0 = constructor_put_in_xmm_mem(ctx, pattern4_0)?;
-            let expr1_0 = constructor_put_in_xmm(ctx, pattern5_0)?;
-            let expr2_0 = constructor_cmove_xmm(ctx, pattern2_0, pattern3_0, &expr0_0, expr1_0)?;
-            return Some(expr2_0);
-        }
-    }
-    if let Some(pattern1_0) = C::is_gpr_type(ctx, pattern0_0) {
-        if let Some(pattern2_0) = C::is_single_register_type(ctx, pattern1_0) {
-            let pattern3_0 = arg1;
-            let pattern4_0 = arg2;
-            let pattern5_0 = arg3;
-            // Rule at src/isa/x64/inst.isle line 1584.
-            let expr0_0 = constructor_put_in_gpr_mem(ctx, pattern4_0)?;
-            let expr1_0 = constructor_put_in_gpr(ctx, pattern5_0)?;
-            let expr2_0 = constructor_cmove(ctx, pattern2_0, pattern3_0, &expr0_0, expr1_0)?;
-            return Some(expr2_0);
-        }
-    }
-    return None;
-}
-
-// Generated as internal constructor for term cmove_or.
-pub fn constructor_cmove_or<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &CC,
-    arg2: &CC,
-    arg3: &GprMem,
-    arg4: Gpr,
-) -> Option<ConsumesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    let pattern4_0 = arg4;
-    // Rule at src/isa/x64/inst.isle line 1594.
-    let expr0_0 = C::temp_writable_gpr(ctx);
-    let expr1_0 = C::temp_writable_gpr(ctx);
-    let expr2_0 = C::operand_size_of_type_32_64(ctx, pattern0_0);
-    let expr3_0 = MInst::Cmove {
-        size: expr2_0,
-        cc: pattern1_0.clone(),
-        consequent: pattern3_0.clone(),
-        alternative: pattern4_0,
-        dst: expr1_0,
-    };
-    let expr4_0 = C::writable_gpr_to_gpr(ctx, expr1_0);
-    let expr5_0 = MInst::Cmove {
-        size: expr2_0,
-        cc: pattern2_0.clone(),
-        consequent: pattern3_0.clone(),
-        alternative: expr4_0,
-        dst: expr0_0,
-    };
-    let expr6_0 = constructor_writable_gpr_to_value_regs(ctx, expr0_0)?;
-    let expr7_0 = ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs {
-        inst1: expr3_0,
-        inst2: expr5_0,
-        result: expr6_0,
-    };
-    return Some(expr7_0);
-}
-
-// Generated as internal constructor for term cmove_or_xmm.
-pub fn constructor_cmove_or_xmm<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &CC,
-    arg2: &CC,
-    arg3: &XmmMem,
-    arg4: Xmm,
-) -> Option<ConsumesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    let pattern4_0 = arg4;
-    // Rule at src/isa/x64/inst.isle line 1606.
-    let expr0_0 = C::temp_writable_xmm(ctx);
-    let expr1_0 = C::temp_writable_xmm(ctx);
-    let expr2_0 = C::operand_size_of_type_32_64(ctx, pattern0_0);
-    let expr3_0 = MInst::XmmCmove {
-        size: expr2_0,
-        cc: pattern1_0.clone(),
-        consequent: pattern3_0.clone(),
-        alternative: pattern4_0,
-        dst: expr1_0,
-    };
-    let expr4_0 = C::writable_xmm_to_xmm(ctx, expr1_0);
-    let expr5_0 = MInst::XmmCmove {
-        size: expr2_0,
-        cc: pattern2_0.clone(),
-        consequent: pattern3_0.clone(),
-        alternative: expr4_0,
-        dst: expr0_0,
-    };
-    let expr6_0 = constructor_writable_xmm_to_value_regs(ctx, expr0_0)?;
-    let expr7_0 = ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs {
-        inst1: expr3_0,
-        inst2: expr5_0,
-        result: expr6_0,
-    };
-    return Some(expr7_0);
-}
-
-// Generated as internal constructor for term cmove_or_from_values.
-pub fn constructor_cmove_or_from_values<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &CC,
-    arg2: &CC,
-    arg3: Value,
-    arg4: Value,
-) -> Option<ConsumesFlags> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I128 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        let pattern5_0 = arg4;
-        // Rule at src/isa/x64/inst.isle line 1621.
-        let expr0_0 = C::put_in_regs(ctx, pattern4_0);
-        let expr1_0 = C::put_in_regs(ctx, pattern5_0);
-        let expr2_0 = C::temp_writable_gpr(ctx);
-        let expr3_0 = C::temp_writable_gpr(ctx);
-        let expr4_0 = C::temp_writable_gpr(ctx);
-        let expr5_0 = C::temp_writable_gpr(ctx);
-        let expr6_0 = OperandSize::Size64;
-        let expr7_0: usize = 0;
-        let expr8_0 = constructor_value_regs_get_gpr(ctx, expr0_0, expr7_0)?;
-        let expr9_0 = C::gpr_to_gpr_mem(ctx, expr8_0);
-        let expr10_0: usize = 0;
-        let expr11_0 = constructor_value_regs_get_gpr(ctx, expr1_0, expr10_0)?;
-        let expr12_0 = MInst::Cmove {
-            size: expr6_0,
-            cc: pattern2_0.clone(),
-            consequent: expr9_0,
-            alternative: expr11_0,
-            dst: expr4_0,
-        };
-        let expr13_0: usize = 0;
-        let expr14_0 = constructor_value_regs_get_gpr(ctx, expr0_0, expr13_0)?;
-        let expr15_0 = C::gpr_to_gpr_mem(ctx, expr14_0);
-        let expr16_0 = C::writable_gpr_to_gpr(ctx, expr4_0);
-        let expr17_0 = MInst::Cmove {
-            size: expr6_0,
-            cc: pattern2_0.clone(),
-            consequent: expr15_0,
-            alternative: expr16_0,
-            dst: expr2_0,
-        };
-        let expr18_0: usize = 1;
-        let expr19_0 = constructor_value_regs_get_gpr(ctx, expr0_0, expr18_0)?;
-        let expr20_0 = C::gpr_to_gpr_mem(ctx, expr19_0);
-        let expr21_0: usize = 1;
-        let expr22_0 = constructor_value_regs_get_gpr(ctx, expr1_0, expr21_0)?;
-        let expr23_0 = MInst::Cmove {
-            size: expr6_0,
-            cc: pattern2_0.clone(),
-            consequent: expr20_0,
-            alternative: expr22_0,
-            dst: expr5_0,
-        };
-        let expr24_0: usize = 1;
-        let expr25_0 = constructor_value_regs_get_gpr(ctx, expr0_0, expr24_0)?;
-        let expr26_0 = C::gpr_to_gpr_mem(ctx, expr25_0);
-        let expr27_0 = C::writable_gpr_to_gpr(ctx, expr5_0);
-        let expr28_0 = MInst::Cmove {
-            size: expr6_0,
-            cc: pattern2_0.clone(),
-            consequent: expr26_0,
-            alternative: expr27_0,
-            dst: expr3_0,
-        };
-        let expr29_0 = constructor_writable_gpr_to_r_reg(ctx, expr2_0)?;
-        let expr30_0 = constructor_writable_gpr_to_r_reg(ctx, expr3_0)?;
-        let expr31_0 = C::value_regs(ctx, expr29_0, expr30_0);
-        let expr32_0 = ConsumesFlags::ConsumesFlagsFourTimesReturnsValueRegs {
-            inst1: expr12_0,
-            inst2: expr17_0,
-            inst3: expr23_0,
-            inst4: expr28_0,
-            result: expr31_0,
-        };
-        return Some(expr32_0);
-    }
-    if let Some(pattern1_0) = C::is_xmm_type(ctx, pattern0_0) {
-        if let Some(pattern2_0) = C::is_single_register_type(ctx, pattern1_0) {
-            let pattern3_0 = arg1;
-            let pattern4_0 = arg2;
-            let pattern5_0 = arg3;
-            let pattern6_0 = arg4;
-            // Rule at src/isa/x64/inst.isle line 1643.
-            let expr0_0 = constructor_put_in_xmm_mem(ctx, pattern5_0)?;
-            let expr1_0 = constructor_put_in_xmm(ctx, pattern6_0)?;
-            let expr2_0 = constructor_cmove_or_xmm(
-                ctx, pattern2_0, pattern3_0, pattern4_0, &expr0_0, expr1_0,
-            )?;
-            return Some(expr2_0);
-        }
-    }
-    if let Some(pattern1_0) = C::is_gpr_type(ctx, pattern0_0) {
-        if let Some(pattern2_0) = C::is_single_register_type(ctx, pattern1_0) {
-            let pattern3_0 = arg1;
-            let pattern4_0 = arg2;
-            let pattern5_0 = arg3;
-            let pattern6_0 = arg4;
-            // Rule at src/isa/x64/inst.isle line 1640.
-            let expr0_0 = constructor_put_in_gpr_mem(ctx, pattern5_0)?;
-            let expr1_0 = constructor_put_in_gpr(ctx, pattern6_0)?;
-            let expr2_0 =
-                constructor_cmove_or(ctx, pattern2_0, pattern3_0, pattern4_0, &expr0_0, expr1_0)?;
-            return Some(expr2_0);
-        }
-    }
-    return None;
-}
-
-// Generated as internal constructor for term setcc.
-pub fn constructor_setcc<C: Context>(ctx: &mut C, arg0: &CC) -> Option<ConsumesFlags> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/x64/inst.isle line 1648.
-    let expr0_0 = C::temp_writable_gpr(ctx);
-    let expr1_0 = MInst::Setcc {
-        cc: pattern0_0.clone(),
-        dst: expr0_0,
-    };
-    let expr2_0 = constructor_writable_gpr_to_r_reg(ctx, expr0_0)?;
-    let expr3_0 = ConsumesFlags::ConsumesFlagsReturnsReg {
-        inst: expr1_0,
-        result: expr2_0,
-    };
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term movzx.
-pub fn constructor_movzx<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &ExtMode,
-    arg2: &GprMem,
-) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 1656.
-    let expr0_0 = C::temp_writable_gpr(ctx);
-    let expr1_0 = MInst::MovzxRmR {
-        ext_mode: pattern1_0.clone(),
-        src: pattern2_0.clone(),
-        dst: expr0_0,
-    };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = C::writable_gpr_to_gpr(ctx, expr0_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term movsx.
-pub fn constructor_movsx<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &ExtMode,
-    arg2: &GprMem,
-) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 1663.
-    let expr0_0 = C::temp_writable_gpr(ctx);
-    let expr1_0 = MInst::MovsxRmR {
-        ext_mode: pattern1_0.clone(),
-        src: pattern2_0.clone(),
-        dst: expr0_0,
-    };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = C::writable_gpr_to_gpr(ctx, expr0_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term xmm_rm_r.
-pub fn constructor_xmm_rm_r<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &SseOpcode,
-    arg2: Xmm,
-    arg3: &XmmMem,
-) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/x64/inst.isle line 1670.
-    let expr0_0 = C::temp_writable_xmm(ctx);
-    let expr1_0 = MInst::XmmRmR {
-        op: pattern1_0.clone(),
-        src1: pattern2_0,
-        src2: pattern3_0.clone(),
-        dst: expr0_0,
-    };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = C::writable_xmm_to_xmm(ctx, expr0_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term paddb.
-pub fn constructor_paddb<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1677.
-    let expr0_0: Type = I8X16;
-    let expr1_0 = SseOpcode::Paddb;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term paddw.
-pub fn constructor_paddw<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1682.
-    let expr0_0: Type = I16X8;
-    let expr1_0 = SseOpcode::Paddw;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term paddd.
-pub fn constructor_paddd<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1687.
-    let expr0_0: Type = I32X4;
-    let expr1_0 = SseOpcode::Paddd;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term paddq.
-pub fn constructor_paddq<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1692.
-    let expr0_0: Type = I64X2;
-    let expr1_0 = SseOpcode::Paddq;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term paddsb.
-pub fn constructor_paddsb<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1697.
-    let expr0_0: Type = I8X16;
-    let expr1_0 = SseOpcode::Paddsb;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term paddsw.
-pub fn constructor_paddsw<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1702.
-    let expr0_0: Type = I16X8;
-    let expr1_0 = SseOpcode::Paddsw;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term paddusb.
-pub fn constructor_paddusb<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1707.
-    let expr0_0: Type = I8X16;
-    let expr1_0 = SseOpcode::Paddusb;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term paddusw.
-pub fn constructor_paddusw<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1712.
-    let expr0_0: Type = I16X8;
-    let expr1_0 = SseOpcode::Paddusw;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term psubb.
-pub fn constructor_psubb<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1717.
-    let expr0_0: Type = I8X16;
-    let expr1_0 = SseOpcode::Psubb;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term psubw.
-pub fn constructor_psubw<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1722.
-    let expr0_0: Type = I16X8;
-    let expr1_0 = SseOpcode::Psubw;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term psubd.
-pub fn constructor_psubd<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1727.
-    let expr0_0: Type = I32X4;
-    let expr1_0 = SseOpcode::Psubd;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term psubq.
-pub fn constructor_psubq<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1732.
-    let expr0_0: Type = I64X2;
-    let expr1_0 = SseOpcode::Psubq;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term psubsb.
-pub fn constructor_psubsb<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1737.
-    let expr0_0: Type = I8X16;
-    let expr1_0 = SseOpcode::Psubsb;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term psubsw.
-pub fn constructor_psubsw<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1742.
-    let expr0_0: Type = I16X8;
-    let expr1_0 = SseOpcode::Psubsw;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term psubusb.
-pub fn constructor_psubusb<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1747.
-    let expr0_0: Type = I8X16;
-    let expr1_0 = SseOpcode::Psubusb;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term psubusw.
-pub fn constructor_psubusw<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1752.
-    let expr0_0: Type = I16X8;
-    let expr1_0 = SseOpcode::Psubusw;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term pavgb.
-pub fn constructor_pavgb<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1757.
-    let expr0_0: Type = I8X16;
-    let expr1_0 = SseOpcode::Pavgb;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term pavgw.
-pub fn constructor_pavgw<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1762.
-    let expr0_0: Type = I16X8;
-    let expr1_0 = SseOpcode::Pavgw;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term pand.
-pub fn constructor_pand<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1767.
-    let expr0_0: Type = F32X4;
-    let expr1_0 = SseOpcode::Pand;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term andps.
-pub fn constructor_andps<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1772.
-    let expr0_0: Type = F32X4;
-    let expr1_0 = SseOpcode::Andps;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term andpd.
-pub fn constructor_andpd<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1777.
-    let expr0_0: Type = F64X2;
-    let expr1_0 = SseOpcode::Andpd;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term por.
-pub fn constructor_por<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1782.
-    let expr0_0: Type = F32X4;
-    let expr1_0 = SseOpcode::Por;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term orps.
-pub fn constructor_orps<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1787.
-    let expr0_0: Type = F32X4;
-    let expr1_0 = SseOpcode::Orps;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term orpd.
-pub fn constructor_orpd<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1792.
-    let expr0_0: Type = F64X2;
-    let expr1_0 = SseOpcode::Orpd;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term pxor.
-pub fn constructor_pxor<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1797.
-    let expr0_0: Type = I8X16;
-    let expr1_0 = SseOpcode::Pxor;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term xorps.
-pub fn constructor_xorps<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1802.
-    let expr0_0: Type = F32X4;
-    let expr1_0 = SseOpcode::Xorps;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term xorpd.
-pub fn constructor_xorpd<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1807.
-    let expr0_0: Type = F64X2;
-    let expr1_0 = SseOpcode::Xorpd;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term pmullw.
-pub fn constructor_pmullw<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1812.
-    let expr0_0: Type = I16X8;
-    let expr1_0 = SseOpcode::Pmullw;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term pmulld.
-pub fn constructor_pmulld<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1817.
-    let expr0_0: Type = I16X8;
-    let expr1_0 = SseOpcode::Pmulld;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term pmulhw.
-pub fn constructor_pmulhw<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1822.
-    let expr0_0: Type = I16X8;
-    let expr1_0 = SseOpcode::Pmulhw;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term pmulhuw.
-pub fn constructor_pmulhuw<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1827.
-    let expr0_0: Type = I16X8;
-    let expr1_0 = SseOpcode::Pmulhuw;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term pmuldq.
-pub fn constructor_pmuldq<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1832.
-    let expr0_0: Type = I16X8;
-    let expr1_0 = SseOpcode::Pmuldq;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term pmuludq.
-pub fn constructor_pmuludq<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1837.
-    let expr0_0: Type = I64X2;
-    let expr1_0 = SseOpcode::Pmuludq;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term punpckhwd.
-pub fn constructor_punpckhwd<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1842.
-    let expr0_0: Type = I16X8;
-    let expr1_0 = SseOpcode::Punpckhwd;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term punpcklwd.
-pub fn constructor_punpcklwd<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1847.
-    let expr0_0: Type = I16X8;
-    let expr1_0 = SseOpcode::Punpcklwd;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term andnps.
-pub fn constructor_andnps<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1852.
-    let expr0_0: Type = F32X4;
-    let expr1_0 = SseOpcode::Andnps;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term andnpd.
-pub fn constructor_andnpd<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1857.
-    let expr0_0: Type = F64X2;
-    let expr1_0 = SseOpcode::Andnpd;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term pandn.
-pub fn constructor_pandn<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1862.
-    let expr0_0: Type = F64X2;
-    let expr1_0 = SseOpcode::Pandn;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term addss.
-pub fn constructor_addss<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1867.
-    let expr0_0: Type = F32;
-    let expr1_0 = SseOpcode::Addss;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term addsd.
-pub fn constructor_addsd<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1872.
-    let expr0_0: Type = F64;
-    let expr1_0 = SseOpcode::Addsd;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term addps.
-pub fn constructor_addps<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1877.
-    let expr0_0: Type = F32;
-    let expr1_0 = SseOpcode::Addps;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term addpd.
-pub fn constructor_addpd<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1882.
-    let expr0_0: Type = F32;
-    let expr1_0 = SseOpcode::Addpd;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term subss.
-pub fn constructor_subss<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1887.
-    let expr0_0: Type = F32;
-    let expr1_0 = SseOpcode::Subss;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term subsd.
-pub fn constructor_subsd<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1892.
-    let expr0_0: Type = F64;
-    let expr1_0 = SseOpcode::Subsd;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term subps.
-pub fn constructor_subps<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1897.
-    let expr0_0: Type = F32;
-    let expr1_0 = SseOpcode::Subps;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term subpd.
-pub fn constructor_subpd<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1902.
-    let expr0_0: Type = F32;
-    let expr1_0 = SseOpcode::Subpd;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term mulss.
-pub fn constructor_mulss<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1907.
-    let expr0_0: Type = F32;
-    let expr1_0 = SseOpcode::Mulss;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term mulsd.
-pub fn constructor_mulsd<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1912.
-    let expr0_0: Type = F64;
-    let expr1_0 = SseOpcode::Mulsd;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term mulps.
-pub fn constructor_mulps<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1917.
-    let expr0_0: Type = F32;
-    let expr1_0 = SseOpcode::Mulps;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term mulpd.
-pub fn constructor_mulpd<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1922.
-    let expr0_0: Type = F32;
-    let expr1_0 = SseOpcode::Mulpd;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term divss.
-pub fn constructor_divss<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1927.
-    let expr0_0: Type = F32;
-    let expr1_0 = SseOpcode::Divss;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term divsd.
-pub fn constructor_divsd<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1932.
-    let expr0_0: Type = F64;
-    let expr1_0 = SseOpcode::Divsd;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term divps.
-pub fn constructor_divps<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1937.
-    let expr0_0: Type = F32;
-    let expr1_0 = SseOpcode::Divps;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term divpd.
-pub fn constructor_divpd<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1942.
-    let expr0_0: Type = F32;
-    let expr1_0 = SseOpcode::Divpd;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term sse_blend_op.
-pub fn constructor_sse_blend_op<C: Context>(ctx: &mut C, arg0: Type) -> Option<SseOpcode> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == F32X4 {
-        // Rule at src/isa/x64/inst.isle line 1946.
-        let expr0_0 = SseOpcode::Blendvps;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == F64X2 {
-        // Rule at src/isa/x64/inst.isle line 1947.
-        let expr0_0 = SseOpcode::Blendvpd;
-        return Some(expr0_0);
-    }
-    if let Some((pattern1_0, pattern1_1)) = C::multi_lane(ctx, pattern0_0) {
-        // Rule at src/isa/x64/inst.isle line 1948.
-        let expr0_0 = SseOpcode::Pblendvb;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term sse_mov_op.
-pub fn constructor_sse_mov_op<C: Context>(ctx: &mut C, arg0: Type) -> Option<SseOpcode> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == F32X4 {
-        // Rule at src/isa/x64/inst.isle line 1951.
-        let expr0_0 = SseOpcode::Movaps;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == F64X2 {
-        // Rule at src/isa/x64/inst.isle line 1952.
-        let expr0_0 = SseOpcode::Movapd;
-        return Some(expr0_0);
-    }
-    if let Some((pattern1_0, pattern1_1)) = C::multi_lane(ctx, pattern0_0) {
-        // Rule at src/isa/x64/inst.isle line 1953.
-        let expr0_0 = SseOpcode::Movdqa;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term sse_blend.
-pub fn constructor_sse_blend<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &XmmMem,
-    arg2: &XmmMem,
-    arg3: Xmm,
-) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/x64/inst.isle line 1957.
-    let expr0_0 = C::xmm0(ctx);
-    let expr1_0 = constructor_sse_mov_op(ctx, pattern0_0)?;
-    let expr2_0 = MInst::XmmUnaryRmR {
-        op: expr1_0,
-        src: pattern1_0.clone(),
-        dst: expr0_0,
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = constructor_sse_blend_op(ctx, pattern0_0)?;
-    let expr5_0 = constructor_xmm_rm_r(ctx, pattern0_0, &expr4_0, pattern3_0, pattern2_0)?;
-    return Some(expr5_0);
-}
-
-// Generated as internal constructor for term blendvpd.
-pub fn constructor_blendvpd<C: Context>(
-    ctx: &mut C,
-    arg0: Xmm,
-    arg1: &XmmMem,
-    arg2: Xmm,
-) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 1971.
-    let expr0_0 = C::xmm0(ctx);
-    let expr1_0 = SseOpcode::Movapd;
-    let expr2_0 = C::xmm_to_xmm_mem(ctx, pattern2_0);
-    let expr3_0 = MInst::XmmUnaryRmR {
-        op: expr1_0,
-        src: expr2_0,
-        dst: expr0_0,
-    };
-    let expr4_0 = C::emit(ctx, &expr3_0);
-    let expr5_0: Type = F64X2;
-    let expr6_0 = SseOpcode::Blendvpd;
-    let expr7_0 = constructor_xmm_rm_r(ctx, expr5_0, &expr6_0, pattern0_0, pattern1_0)?;
-    return Some(expr7_0);
-}
-
-// Generated as internal constructor for term movsd.
-pub fn constructor_movsd<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1985.
-    let expr0_0: Type = I8X16;
-    let expr1_0 = SseOpcode::Movsd;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term movlhps.
-pub fn constructor_movlhps<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1990.
-    let expr0_0: Type = I8X16;
-    let expr1_0 = SseOpcode::Movlhps;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term pmaxsb.
-pub fn constructor_pmaxsb<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 1995.
-    let expr0_0: Type = I8X16;
-    let expr1_0 = SseOpcode::Pmaxsb;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term pmaxsw.
-pub fn constructor_pmaxsw<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2000.
-    let expr0_0: Type = I8X16;
-    let expr1_0 = SseOpcode::Pmaxsw;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term pmaxsd.
-pub fn constructor_pmaxsd<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2005.
-    let expr0_0: Type = I8X16;
-    let expr1_0 = SseOpcode::Pmaxsd;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term pminsb.
-pub fn constructor_pminsb<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2010.
-    let expr0_0: Type = I8X16;
-    let expr1_0 = SseOpcode::Pminsb;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term pminsw.
-pub fn constructor_pminsw<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2015.
-    let expr0_0: Type = I8X16;
-    let expr1_0 = SseOpcode::Pminsw;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term pminsd.
-pub fn constructor_pminsd<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2020.
-    let expr0_0: Type = I8X16;
-    let expr1_0 = SseOpcode::Pminsd;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term pmaxub.
-pub fn constructor_pmaxub<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2025.
-    let expr0_0: Type = I8X16;
-    let expr1_0 = SseOpcode::Pmaxub;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term pmaxuw.
-pub fn constructor_pmaxuw<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2030.
-    let expr0_0: Type = I8X16;
-    let expr1_0 = SseOpcode::Pmaxuw;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term pmaxud.
-pub fn constructor_pmaxud<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2035.
-    let expr0_0: Type = I8X16;
-    let expr1_0 = SseOpcode::Pmaxud;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term pminub.
-pub fn constructor_pminub<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2040.
-    let expr0_0: Type = I8X16;
-    let expr1_0 = SseOpcode::Pminub;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term pminuw.
-pub fn constructor_pminuw<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2045.
-    let expr0_0: Type = I8X16;
-    let expr1_0 = SseOpcode::Pminuw;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term pminud.
-pub fn constructor_pminud<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2050.
-    let expr0_0: Type = I8X16;
-    let expr1_0 = SseOpcode::Pminud;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term punpcklbw.
-pub fn constructor_punpcklbw<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2055.
-    let expr0_0: Type = I8X16;
-    let expr1_0 = SseOpcode::Punpcklbw;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term punpckhbw.
-pub fn constructor_punpckhbw<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2060.
-    let expr0_0: Type = I8X16;
-    let expr1_0 = SseOpcode::Punpckhbw;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term packsswb.
-pub fn constructor_packsswb<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2065.
-    let expr0_0: Type = I8X16;
-    let expr1_0 = SseOpcode::Packsswb;
-    let expr2_0 = constructor_xmm_rm_r(ctx, expr0_0, &expr1_0, pattern0_0, pattern1_0)?;
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term xmm_rm_r_imm.
-pub fn constructor_xmm_rm_r_imm<C: Context>(
-    ctx: &mut C,
-    arg0: &SseOpcode,
-    arg1: Reg,
-    arg2: &RegMem,
-    arg3: u8,
-    arg4: &OperandSize,
-) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    let pattern4_0 = arg4;
-    // Rule at src/isa/x64/inst.isle line 2070.
-    let expr0_0 = C::temp_writable_xmm(ctx);
-    let expr1_0 = C::writable_xmm_to_reg(ctx, expr0_0);
-    let expr2_0 = MInst::XmmRmRImm {
-        op: pattern0_0.clone(),
-        src1: pattern1_0,
-        src2: pattern2_0.clone(),
-        dst: expr1_0,
-        imm: pattern3_0,
-        size: pattern4_0.clone(),
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_xmm_to_xmm(ctx, expr0_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term palignr.
-pub fn constructor_palignr<C: Context>(
-    ctx: &mut C,
-    arg0: Xmm,
-    arg1: &XmmMem,
-    arg2: u8,
-    arg3: &OperandSize,
-) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/x64/inst.isle line 2082.
-    let expr0_0 = SseOpcode::Palignr;
-    let expr1_0 = C::xmm_to_reg(ctx, pattern0_0);
-    let expr2_0 = C::xmm_mem_to_reg_mem(ctx, pattern1_0);
-    let expr3_0 =
-        constructor_xmm_rm_r_imm(ctx, &expr0_0, expr1_0, &expr2_0, pattern2_0, pattern3_0)?;
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term cmpps.
-pub fn constructor_cmpps<C: Context>(
-    ctx: &mut C,
-    arg0: Xmm,
-    arg1: &XmmMem,
-    arg2: &FcmpImm,
-) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 2091.
-    let expr0_0 = SseOpcode::Cmpps;
-    let expr1_0 = C::xmm_to_reg(ctx, pattern0_0);
-    let expr2_0 = C::xmm_mem_to_reg_mem(ctx, pattern1_0);
-    let expr3_0 = C::encode_fcmp_imm(ctx, pattern2_0);
-    let expr4_0 = OperandSize::Size32;
-    let expr5_0 = constructor_xmm_rm_r_imm(ctx, &expr0_0, expr1_0, &expr2_0, expr3_0, &expr4_0)?;
-    return Some(expr5_0);
-}
-
-// Generated as internal constructor for term pinsrb.
-pub fn constructor_pinsrb<C: Context>(
-    ctx: &mut C,
-    arg0: Xmm,
-    arg1: &GprMem,
-    arg2: u8,
-) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 2100.
-    let expr0_0 = SseOpcode::Pinsrb;
-    let expr1_0 = C::xmm_to_reg(ctx, pattern0_0);
-    let expr2_0 = C::gpr_mem_to_reg_mem(ctx, pattern1_0);
-    let expr3_0 = OperandSize::Size32;
-    let expr4_0 = constructor_xmm_rm_r_imm(ctx, &expr0_0, expr1_0, &expr2_0, pattern2_0, &expr3_0)?;
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term pinsrw.
-pub fn constructor_pinsrw<C: Context>(
-    ctx: &mut C,
-    arg0: Xmm,
-    arg1: &GprMem,
-    arg2: u8,
-) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 2109.
-    let expr0_0 = SseOpcode::Pinsrw;
-    let expr1_0 = C::xmm_to_reg(ctx, pattern0_0);
-    let expr2_0 = C::gpr_mem_to_reg_mem(ctx, pattern1_0);
-    let expr3_0 = OperandSize::Size32;
-    let expr4_0 = constructor_xmm_rm_r_imm(ctx, &expr0_0, expr1_0, &expr2_0, pattern2_0, &expr3_0)?;
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term pinsrd.
-pub fn constructor_pinsrd<C: Context>(
-    ctx: &mut C,
-    arg0: Xmm,
-    arg1: &GprMem,
-    arg2: u8,
-    arg3: &OperandSize,
-) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/x64/inst.isle line 2118.
-    let expr0_0 = SseOpcode::Pinsrd;
-    let expr1_0 = C::xmm_to_reg(ctx, pattern0_0);
-    let expr2_0 = C::gpr_mem_to_reg_mem(ctx, pattern1_0);
-    let expr3_0 =
-        constructor_xmm_rm_r_imm(ctx, &expr0_0, expr1_0, &expr2_0, pattern2_0, pattern3_0)?;
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term pmaddwd.
-pub fn constructor_pmaddwd<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2127.
-    let expr0_0 = C::temp_writable_xmm(ctx);
-    let expr1_0 = SseOpcode::Pmaddwd;
-    let expr2_0 = MInst::XmmRmR {
-        op: expr1_0,
-        src1: pattern0_0,
-        src2: pattern1_0.clone(),
-        dst: expr0_0,
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_xmm_to_xmm(ctx, expr0_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term insertps.
-pub fn constructor_insertps<C: Context>(
-    ctx: &mut C,
-    arg0: Xmm,
-    arg1: &XmmMem,
-    arg2: u8,
-) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 2137.
-    let expr0_0 = SseOpcode::Insertps;
-    let expr1_0 = C::xmm_to_reg(ctx, pattern0_0);
-    let expr2_0 = C::xmm_mem_to_reg_mem(ctx, pattern1_0);
-    let expr3_0 = OperandSize::Size32;
-    let expr4_0 = constructor_xmm_rm_r_imm(ctx, &expr0_0, expr1_0, &expr2_0, pattern2_0, &expr3_0)?;
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term pshufd.
-pub fn constructor_pshufd<C: Context>(
-    ctx: &mut C,
-    arg0: &XmmMem,
-    arg1: u8,
-    arg2: &OperandSize,
-) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 2146.
-    let expr0_0 = C::temp_writable_xmm(ctx);
-    let expr1_0 = SseOpcode::Pshufd;
-    let expr2_0 = constructor_writable_xmm_to_r_reg(ctx, expr0_0)?;
-    let expr3_0 = C::xmm_mem_to_reg_mem(ctx, pattern0_0);
-    let expr4_0 = C::writable_xmm_to_reg(ctx, expr0_0);
-    let expr5_0 = MInst::XmmRmRImm {
-        op: expr1_0,
-        src1: expr2_0,
-        src2: expr3_0,
-        dst: expr4_0,
-        imm: pattern1_0,
-        size: pattern2_0.clone(),
-    };
-    let expr6_0 = C::emit(ctx, &expr5_0);
-    let expr7_0 = C::writable_xmm_to_xmm(ctx, expr0_0);
-    return Some(expr7_0);
-}
-
-// Generated as internal constructor for term pshufb.
-pub fn constructor_pshufb<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2158.
-    let expr0_0 = C::temp_writable_xmm(ctx);
-    let expr1_0 = SseOpcode::Pshufb;
-    let expr2_0 = MInst::XmmRmR {
-        op: expr1_0,
-        src1: pattern0_0,
-        src2: pattern1_0.clone(),
-        dst: expr0_0,
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_xmm_to_xmm(ctx, expr0_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term xmm_unary_rm_r.
-pub fn constructor_xmm_unary_rm_r<C: Context>(
-    ctx: &mut C,
-    arg0: &SseOpcode,
-    arg1: &XmmMem,
-) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2168.
-    let expr0_0 = C::temp_writable_xmm(ctx);
-    let expr1_0 = MInst::XmmUnaryRmR {
-        op: pattern0_0.clone(),
-        src: pattern1_0.clone(),
-        dst: expr0_0,
-    };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = C::writable_xmm_to_xmm(ctx, expr0_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term pmovsxbw.
-pub fn constructor_pmovsxbw<C: Context>(ctx: &mut C, arg0: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/x64/inst.isle line 2175.
-    let expr0_0 = SseOpcode::Pmovsxbw;
-    let expr1_0 = constructor_xmm_unary_rm_r(ctx, &expr0_0, pattern0_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term pmovzxbw.
-pub fn constructor_pmovzxbw<C: Context>(ctx: &mut C, arg0: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/x64/inst.isle line 2180.
-    let expr0_0 = SseOpcode::Pmovzxbw;
-    let expr1_0 = constructor_xmm_unary_rm_r(ctx, &expr0_0, pattern0_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term pabsb.
-pub fn constructor_pabsb<C: Context>(ctx: &mut C, arg0: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/x64/inst.isle line 2185.
-    let expr0_0 = SseOpcode::Pabsb;
-    let expr1_0 = constructor_xmm_unary_rm_r(ctx, &expr0_0, pattern0_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term pabsw.
-pub fn constructor_pabsw<C: Context>(ctx: &mut C, arg0: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/x64/inst.isle line 2190.
-    let expr0_0 = SseOpcode::Pabsw;
-    let expr1_0 = constructor_xmm_unary_rm_r(ctx, &expr0_0, pattern0_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term pabsd.
-pub fn constructor_pabsd<C: Context>(ctx: &mut C, arg0: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/x64/inst.isle line 2195.
-    let expr0_0 = SseOpcode::Pabsd;
-    let expr1_0 = constructor_xmm_unary_rm_r(ctx, &expr0_0, pattern0_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term xmm_unary_rm_r_evex.
-pub fn constructor_xmm_unary_rm_r_evex<C: Context>(
-    ctx: &mut C,
-    arg0: &Avx512Opcode,
-    arg1: &XmmMem,
-) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2200.
-    let expr0_0 = C::temp_writable_xmm(ctx);
-    let expr1_0 = MInst::XmmUnaryRmREvex {
-        op: pattern0_0.clone(),
-        src: pattern1_0.clone(),
-        dst: expr0_0,
-    };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = C::writable_xmm_to_xmm(ctx, expr0_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term vpabsq.
-pub fn constructor_vpabsq<C: Context>(ctx: &mut C, arg0: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/x64/inst.isle line 2207.
-    let expr0_0 = Avx512Opcode::Vpabsq;
-    let expr1_0 = constructor_xmm_unary_rm_r_evex(ctx, &expr0_0, pattern0_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term vpopcntb.
-pub fn constructor_vpopcntb<C: Context>(ctx: &mut C, arg0: &XmmMem) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/x64/inst.isle line 2212.
-    let expr0_0 = Avx512Opcode::Vpopcntb;
-    let expr1_0 = constructor_xmm_unary_rm_r_evex(ctx, &expr0_0, pattern0_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term xmm_rm_r_evex.
-pub fn constructor_xmm_rm_r_evex<C: Context>(
-    ctx: &mut C,
-    arg0: &Avx512Opcode,
-    arg1: &XmmMem,
-    arg2: Xmm,
-) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 2217.
-    let expr0_0 = C::temp_writable_xmm(ctx);
-    let expr1_0 = MInst::XmmRmREvex {
-        op: pattern0_0.clone(),
-        src1: pattern1_0.clone(),
-        src2: pattern2_0,
-        dst: expr0_0,
-    };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = C::writable_xmm_to_xmm(ctx, expr0_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term vpmullq.
-pub fn constructor_vpmullq<C: Context>(ctx: &mut C, arg0: &XmmMem, arg1: Xmm) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2229.
-    let expr0_0 = Avx512Opcode::Vpmullq;
-    let expr1_0 = constructor_xmm_rm_r_evex(ctx, &expr0_0, pattern0_0, pattern1_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term mul_hi.
-pub fn constructor_mul_hi<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: bool,
-    arg2: Gpr,
-    arg3: &GprMem,
-) -> Option<ValueRegs> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/x64/inst.isle line 2238.
-    let expr0_0 = C::temp_writable_gpr(ctx);
-    let expr1_0 = C::temp_writable_gpr(ctx);
-    let expr2_0 = C::operand_size_of_type_32_64(ctx, pattern0_0);
-    let expr3_0 = MInst::MulHi {
-        size: expr2_0,
-        signed: pattern1_0,
-        src1: pattern2_0,
-        src2: pattern3_0.clone(),
-        dst_lo: expr0_0,
-        dst_hi: expr1_0,
-    };
-    let expr4_0 = C::emit(ctx, &expr3_0);
-    let expr5_0 = C::writable_gpr_to_gpr(ctx, expr0_0);
-    let expr6_0 = C::writable_gpr_to_gpr(ctx, expr1_0);
-    let expr7_0 = constructor_value_gprs(ctx, expr5_0, expr6_0)?;
-    return Some(expr7_0);
-}
-
-// Generated as internal constructor for term mulhi_u.
-pub fn constructor_mulhi_u<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Gpr,
-    arg2: &GprMem,
-) -> Option<ValueRegs> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 2253.
-    let expr0_0: bool = false;
-    let expr1_0 = constructor_mul_hi(ctx, pattern0_0, expr0_0, pattern1_0, pattern2_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term xmm_rmi_xmm.
-pub fn constructor_xmm_rmi_xmm<C: Context>(
-    ctx: &mut C,
-    arg0: &SseOpcode,
-    arg1: Xmm,
-    arg2: &XmmMemImm,
-) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 2258.
-    let expr0_0 = C::temp_writable_xmm(ctx);
-    let expr1_0 = MInst::XmmRmiReg {
-        opcode: pattern0_0.clone(),
-        src1: pattern1_0,
-        src2: pattern2_0.clone(),
-        dst: expr0_0,
-    };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = C::writable_xmm_to_xmm(ctx, expr0_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term psllw.
-pub fn constructor_psllw<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMemImm) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2268.
-    let expr0_0 = SseOpcode::Psllw;
-    let expr1_0 = constructor_xmm_rmi_xmm(ctx, &expr0_0, pattern0_0, pattern1_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term pslld.
-pub fn constructor_pslld<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMemImm) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2273.
-    let expr0_0 = SseOpcode::Pslld;
-    let expr1_0 = constructor_xmm_rmi_xmm(ctx, &expr0_0, pattern0_0, pattern1_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term psllq.
-pub fn constructor_psllq<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMemImm) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2278.
-    let expr0_0 = SseOpcode::Psllq;
-    let expr1_0 = constructor_xmm_rmi_xmm(ctx, &expr0_0, pattern0_0, pattern1_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term psrlw.
-pub fn constructor_psrlw<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMemImm) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2283.
-    let expr0_0 = SseOpcode::Psrlw;
-    let expr1_0 = constructor_xmm_rmi_xmm(ctx, &expr0_0, pattern0_0, pattern1_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term psrld.
-pub fn constructor_psrld<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMemImm) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2288.
-    let expr0_0 = SseOpcode::Psrld;
-    let expr1_0 = constructor_xmm_rmi_xmm(ctx, &expr0_0, pattern0_0, pattern1_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term psrlq.
-pub fn constructor_psrlq<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMemImm) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2293.
-    let expr0_0 = SseOpcode::Psrlq;
-    let expr1_0 = constructor_xmm_rmi_xmm(ctx, &expr0_0, pattern0_0, pattern1_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term psraw.
-pub fn constructor_psraw<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMemImm) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2298.
-    let expr0_0 = SseOpcode::Psraw;
-    let expr1_0 = constructor_xmm_rmi_xmm(ctx, &expr0_0, pattern0_0, pattern1_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term psrad.
-pub fn constructor_psrad<C: Context>(ctx: &mut C, arg0: Xmm, arg1: &XmmMemImm) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2303.
-    let expr0_0 = SseOpcode::Psrad;
-    let expr1_0 = constructor_xmm_rmi_xmm(ctx, &expr0_0, pattern0_0, pattern1_0)?;
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term pextrd.
-pub fn constructor_pextrd<C: Context>(ctx: &mut C, arg0: Type, arg1: Xmm, arg2: u8) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 2308.
-    let expr0_0 = C::temp_writable_gpr(ctx);
-    let expr1_0 = SseOpcode::Pextrd;
-    let expr2_0 = constructor_writable_gpr_to_r_reg(ctx, expr0_0)?;
-    let expr3_0 = C::xmm_to_reg(ctx, pattern1_0);
-    let expr4_0 = constructor_xmm_to_reg_mem(ctx, expr3_0)?;
-    let expr5_0 = C::xmm_mem_to_reg_mem(ctx, &expr4_0);
-    let expr6_0 = C::writable_gpr_to_reg(ctx, expr0_0);
-    let expr7_0 = C::lane_type(ctx, pattern0_0);
-    let expr8_0 = C::operand_size_of_type_32_64(ctx, expr7_0);
-    let expr9_0 = MInst::XmmRmRImm {
-        op: expr1_0,
-        src1: expr2_0,
-        src2: expr5_0,
-        dst: expr6_0,
-        imm: pattern2_0,
-        size: expr8_0,
-    };
-    let expr10_0 = C::emit(ctx, &expr9_0);
-    let expr11_0 = C::writable_gpr_to_gpr(ctx, expr0_0);
-    return Some(expr11_0);
-}
-
-// Generated as internal constructor for term cmppd.
-pub fn constructor_cmppd<C: Context>(
-    ctx: &mut C,
-    arg0: Xmm,
-    arg1: &XmmMem,
-    arg2: &FcmpImm,
-) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 2324.
-    let expr0_0 = SseOpcode::Cmppd;
-    let expr1_0 = C::xmm_to_reg(ctx, pattern0_0);
-    let expr2_0 = C::xmm_mem_to_reg_mem(ctx, pattern1_0);
-    let expr3_0 = C::encode_fcmp_imm(ctx, pattern2_0);
-    let expr4_0 = OperandSize::Size32;
-    let expr5_0 = constructor_xmm_rm_r_imm(ctx, &expr0_0, expr1_0, &expr2_0, expr3_0, &expr4_0)?;
-    return Some(expr5_0);
-}
-
-// Generated as internal constructor for term gpr_to_xmm.
-pub fn constructor_gpr_to_xmm<C: Context>(
-    ctx: &mut C,
-    arg0: &SseOpcode,
-    arg1: &GprMem,
-    arg2: &OperandSize,
-) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 2333.
-    let expr0_0 = C::temp_writable_xmm(ctx);
-    let expr1_0 = MInst::GprToXmm {
-        op: pattern0_0.clone(),
-        src: pattern1_0.clone(),
-        dst: expr0_0,
-        src_size: pattern2_0.clone(),
-    };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = C::writable_xmm_to_xmm(ctx, expr0_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term not.
-pub fn constructor_not<C: Context>(ctx: &mut C, arg0: Type, arg1: Gpr) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2340.
-    let expr0_0 = C::temp_writable_gpr(ctx);
-    let expr1_0 = C::operand_size_of_type_32_64(ctx, pattern0_0);
-    let expr2_0 = MInst::Not {
-        size: expr1_0,
-        src: pattern1_0,
-        dst: expr0_0,
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_gpr_to_gpr(ctx, expr0_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term neg.
-pub fn constructor_neg<C: Context>(ctx: &mut C, arg0: Type, arg1: Gpr) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2348.
-    let expr0_0 = C::temp_writable_gpr(ctx);
-    let expr1_0 = C::operand_size_of_type_32_64(ctx, pattern0_0);
-    let expr2_0 = MInst::Neg {
-        size: expr1_0,
-        src: pattern1_0,
-        dst: expr0_0,
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_gpr_to_gpr(ctx, expr0_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term lea.
-pub fn constructor_lea<C: Context>(ctx: &mut C, arg0: &SyntheticAmode) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/x64/inst.isle line 2355.
-    let expr0_0 = C::temp_writable_gpr(ctx);
-    let expr1_0 = MInst::LoadEffectiveAddress {
-        addr: pattern0_0.clone(),
-        dst: expr0_0,
-    };
-    let expr2_0 = C::emit(ctx, &expr1_0);
-    let expr3_0 = C::writable_gpr_to_gpr(ctx, expr0_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term ud2.
-pub fn constructor_ud2<C: Context>(ctx: &mut C, arg0: &TrapCode) -> Option<SideEffectNoResult> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/x64/inst.isle line 2362.
-    let expr0_0 = MInst::Ud2 {
-        trap_code: pattern0_0.clone(),
-    };
-    let expr1_0 = SideEffectNoResult::Inst { inst: expr0_0 };
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term hlt.
-pub fn constructor_hlt<C: Context>(ctx: &mut C) -> Option<SideEffectNoResult> {
-    // Rule at src/isa/x64/inst.isle line 2367.
-    let expr0_0 = MInst::Hlt;
-    let expr1_0 = SideEffectNoResult::Inst { inst: expr0_0 };
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term lzcnt.
-pub fn constructor_lzcnt<C: Context>(ctx: &mut C, arg0: Type, arg1: Gpr) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2372.
-    let expr0_0 = C::temp_writable_gpr(ctx);
-    let expr1_0 = C::operand_size_of_type_32_64(ctx, pattern0_0);
-    let expr2_0 = UnaryRmROpcode::Lzcnt;
-    let expr3_0 = C::gpr_to_gpr_mem(ctx, pattern1_0);
-    let expr4_0 = MInst::UnaryRmR {
-        size: expr1_0,
-        op: expr2_0,
-        src: expr3_0,
-        dst: expr0_0,
-    };
-    let expr5_0 = C::emit(ctx, &expr4_0);
-    let expr6_0 = C::writable_gpr_to_gpr(ctx, expr0_0);
-    return Some(expr6_0);
-}
-
-// Generated as internal constructor for term tzcnt.
-pub fn constructor_tzcnt<C: Context>(ctx: &mut C, arg0: Type, arg1: Gpr) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2380.
-    let expr0_0 = C::temp_writable_gpr(ctx);
-    let expr1_0 = C::operand_size_of_type_32_64(ctx, pattern0_0);
-    let expr2_0 = UnaryRmROpcode::Tzcnt;
-    let expr3_0 = C::gpr_to_gpr_mem(ctx, pattern1_0);
-    let expr4_0 = MInst::UnaryRmR {
-        size: expr1_0,
-        op: expr2_0,
-        src: expr3_0,
-        dst: expr0_0,
-    };
-    let expr5_0 = C::emit(ctx, &expr4_0);
-    let expr6_0 = C::writable_gpr_to_gpr(ctx, expr0_0);
-    return Some(expr6_0);
-}
-
-// Generated as internal constructor for term bsr.
-pub fn constructor_bsr<C: Context>(ctx: &mut C, arg0: Type, arg1: Gpr) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2388.
-    let expr0_0 = C::temp_writable_gpr(ctx);
-    let expr1_0 = C::operand_size_of_type_32_64(ctx, pattern0_0);
-    let expr2_0 = UnaryRmROpcode::Bsr;
-    let expr3_0 = C::gpr_to_gpr_mem(ctx, pattern1_0);
-    let expr4_0 = MInst::UnaryRmR {
-        size: expr1_0,
-        op: expr2_0,
-        src: expr3_0,
-        dst: expr0_0,
-    };
-    let expr5_0 = constructor_writable_gpr_to_r_reg(ctx, expr0_0)?;
-    let expr6_0 = ProducesFlags::ProducesFlagsReturnsReg {
-        inst: expr4_0,
-        result: expr5_0,
-    };
-    return Some(expr6_0);
-}
-
-// Generated as internal constructor for term bsr_or_else.
-pub fn constructor_bsr_or_else<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Gpr,
-    arg2: Gpr,
-) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 2397.
-    let expr0_0 = constructor_bsr(ctx, pattern0_0, pattern1_0)?;
-    let expr1_0 = constructor_produces_flags_get_reg(ctx, &expr0_0)?;
-    let expr2_0 = C::gpr_new(ctx, expr1_0);
-    let expr3_0 = CC::Z;
-    let expr4_0 = C::gpr_to_gpr_mem(ctx, pattern2_0);
-    let expr5_0 = constructor_cmove(ctx, pattern0_0, &expr3_0, &expr4_0, expr2_0)?;
-    let expr6_0 = constructor_produces_flags_ignore(ctx, &expr0_0)?;
-    let expr7_0 = constructor_with_flags_reg(ctx, &expr6_0, &expr5_0)?;
-    let expr8_0 = C::gpr_new(ctx, expr7_0);
-    return Some(expr8_0);
-}
-
-// Generated as internal constructor for term bsf.
-pub fn constructor_bsf<C: Context>(ctx: &mut C, arg0: Type, arg1: Gpr) -> Option<ProducesFlags> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2408.
-    let expr0_0 = C::temp_writable_gpr(ctx);
-    let expr1_0 = C::operand_size_of_type_32_64(ctx, pattern0_0);
-    let expr2_0 = UnaryRmROpcode::Bsf;
-    let expr3_0 = C::gpr_to_gpr_mem(ctx, pattern1_0);
-    let expr4_0 = MInst::UnaryRmR {
-        size: expr1_0,
-        op: expr2_0,
-        src: expr3_0,
-        dst: expr0_0,
-    };
-    let expr5_0 = constructor_writable_gpr_to_r_reg(ctx, expr0_0)?;
-    let expr6_0 = ProducesFlags::ProducesFlagsReturnsReg {
-        inst: expr4_0,
-        result: expr5_0,
-    };
-    return Some(expr6_0);
-}
-
-// Generated as internal constructor for term bsf_or_else.
-pub fn constructor_bsf_or_else<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Gpr,
-    arg2: Gpr,
-) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/inst.isle line 2417.
-    let expr0_0 = constructor_bsf(ctx, pattern0_0, pattern1_0)?;
-    let expr1_0 = constructor_produces_flags_get_reg(ctx, &expr0_0)?;
-    let expr2_0 = C::gpr_new(ctx, expr1_0);
-    let expr3_0 = CC::Z;
-    let expr4_0 = C::gpr_to_gpr_mem(ctx, pattern2_0);
-    let expr5_0 = constructor_cmove(ctx, pattern0_0, &expr3_0, &expr4_0, expr2_0)?;
-    let expr6_0 = constructor_produces_flags_ignore(ctx, &expr0_0)?;
-    let expr7_0 = constructor_with_flags_reg(ctx, &expr6_0, &expr5_0)?;
-    let expr8_0 = C::gpr_new(ctx, expr7_0);
-    return Some(expr8_0);
-}
-
-// Generated as internal constructor for term x64_popcnt.
-pub fn constructor_x64_popcnt<C: Context>(ctx: &mut C, arg0: Type, arg1: Gpr) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2428.
-    let expr0_0 = C::temp_writable_gpr(ctx);
-    let expr1_0 = C::operand_size_of_type_32_64(ctx, pattern0_0);
-    let expr2_0 = UnaryRmROpcode::Popcnt;
-    let expr3_0 = C::gpr_to_gpr_mem(ctx, pattern1_0);
-    let expr4_0 = MInst::UnaryRmR {
-        size: expr1_0,
-        op: expr2_0,
-        src: expr3_0,
-        dst: expr0_0,
-    };
-    let expr5_0 = C::emit(ctx, &expr4_0);
-    let expr6_0 = C::writable_gpr_to_gpr(ctx, expr0_0);
-    return Some(expr6_0);
-}
-
-// Generated as internal constructor for term xmm_min_max_seq.
-pub fn constructor_xmm_min_max_seq<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: bool,
-    arg2: Xmm,
-    arg3: Xmm,
-) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    let pattern3_0 = arg3;
-    // Rule at src/isa/x64/inst.isle line 2436.
-    let expr0_0 = C::temp_writable_xmm(ctx);
-    let expr1_0 = C::operand_size_of_type_32_64(ctx, pattern0_0);
-    let expr2_0 = MInst::XmmMinMaxSeq {
-        size: expr1_0,
-        is_min: pattern1_0,
-        lhs: pattern2_0,
-        rhs: pattern3_0,
-        dst: expr0_0,
-    };
-    let expr3_0 = C::emit(ctx, &expr2_0);
-    let expr4_0 = C::writable_xmm_to_xmm(ctx, expr0_0);
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term minss.
-pub fn constructor_minss<C: Context>(ctx: &mut C, arg0: Xmm, arg1: Xmm) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2444.
-    let expr0_0 = C::temp_writable_xmm(ctx);
-    let expr1_0 = SseOpcode::Minss;
-    let expr2_0 = C::xmm_to_xmm_mem(ctx, pattern1_0);
-    let expr3_0 = MInst::XmmRmR {
-        op: expr1_0,
-        src1: pattern0_0,
-        src2: expr2_0,
-        dst: expr0_0,
-    };
-    let expr4_0 = C::emit(ctx, &expr3_0);
-    let expr5_0 = C::writable_xmm_to_xmm(ctx, expr0_0);
-    return Some(expr5_0);
-}
-
-// Generated as internal constructor for term minsd.
-pub fn constructor_minsd<C: Context>(ctx: &mut C, arg0: Xmm, arg1: Xmm) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2451.
-    let expr0_0 = C::temp_writable_xmm(ctx);
-    let expr1_0 = SseOpcode::Minsd;
-    let expr2_0 = C::xmm_to_xmm_mem(ctx, pattern1_0);
-    let expr3_0 = MInst::XmmRmR {
-        op: expr1_0,
-        src1: pattern0_0,
-        src2: expr2_0,
-        dst: expr0_0,
-    };
-    let expr4_0 = C::emit(ctx, &expr3_0);
-    let expr5_0 = C::writable_xmm_to_xmm(ctx, expr0_0);
-    return Some(expr5_0);
-}
-
-// Generated as internal constructor for term minps.
-pub fn constructor_minps<C: Context>(ctx: &mut C, arg0: Xmm, arg1: Xmm) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2459.
-    let expr0_0 = C::temp_writable_xmm(ctx);
-    let expr1_0 = SseOpcode::Minps;
-    let expr2_0 = C::xmm_to_xmm_mem(ctx, pattern1_0);
-    let expr3_0 = MInst::XmmRmR {
-        op: expr1_0,
-        src1: pattern0_0,
-        src2: expr2_0,
-        dst: expr0_0,
-    };
-    let expr4_0 = C::emit(ctx, &expr3_0);
-    let expr5_0 = C::writable_xmm_to_xmm(ctx, expr0_0);
-    return Some(expr5_0);
-}
-
-// Generated as internal constructor for term minpd.
-pub fn constructor_minpd<C: Context>(ctx: &mut C, arg0: Xmm, arg1: Xmm) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2466.
-    let expr0_0 = C::temp_writable_xmm(ctx);
-    let expr1_0 = SseOpcode::Minpd;
-    let expr2_0 = C::xmm_to_xmm_mem(ctx, pattern1_0);
-    let expr3_0 = MInst::XmmRmR {
-        op: expr1_0,
-        src1: pattern0_0,
-        src2: expr2_0,
-        dst: expr0_0,
-    };
-    let expr4_0 = C::emit(ctx, &expr3_0);
-    let expr5_0 = C::writable_xmm_to_xmm(ctx, expr0_0);
-    return Some(expr5_0);
-}
-
-// Generated as internal constructor for term maxss.
-pub fn constructor_maxss<C: Context>(ctx: &mut C, arg0: Xmm, arg1: Xmm) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2473.
-    let expr0_0 = C::temp_writable_xmm(ctx);
-    let expr1_0 = SseOpcode::Maxss;
-    let expr2_0 = C::xmm_to_xmm_mem(ctx, pattern1_0);
-    let expr3_0 = MInst::XmmRmR {
-        op: expr1_0,
-        src1: pattern0_0,
-        src2: expr2_0,
-        dst: expr0_0,
-    };
-    let expr4_0 = C::emit(ctx, &expr3_0);
-    let expr5_0 = C::writable_xmm_to_xmm(ctx, expr0_0);
-    return Some(expr5_0);
-}
-
-// Generated as internal constructor for term maxsd.
-pub fn constructor_maxsd<C: Context>(ctx: &mut C, arg0: Xmm, arg1: Xmm) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2480.
-    let expr0_0 = C::temp_writable_xmm(ctx);
-    let expr1_0 = SseOpcode::Maxsd;
-    let expr2_0 = C::xmm_to_xmm_mem(ctx, pattern1_0);
-    let expr3_0 = MInst::XmmRmR {
-        op: expr1_0,
-        src1: pattern0_0,
-        src2: expr2_0,
-        dst: expr0_0,
-    };
-    let expr4_0 = C::emit(ctx, &expr3_0);
-    let expr5_0 = C::writable_xmm_to_xmm(ctx, expr0_0);
-    return Some(expr5_0);
-}
-
-// Generated as internal constructor for term maxps.
-pub fn constructor_maxps<C: Context>(ctx: &mut C, arg0: Xmm, arg1: Xmm) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2487.
-    let expr0_0 = C::temp_writable_xmm(ctx);
-    let expr1_0 = SseOpcode::Maxps;
-    let expr2_0 = C::xmm_to_xmm_mem(ctx, pattern1_0);
-    let expr3_0 = MInst::XmmRmR {
-        op: expr1_0,
-        src1: pattern0_0,
-        src2: expr2_0,
-        dst: expr0_0,
-    };
-    let expr4_0 = C::emit(ctx, &expr3_0);
-    let expr5_0 = C::writable_xmm_to_xmm(ctx, expr0_0);
-    return Some(expr5_0);
-}
-
-// Generated as internal constructor for term maxpd.
-pub fn constructor_maxpd<C: Context>(ctx: &mut C, arg0: Xmm, arg1: Xmm) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/inst.isle line 2494.
-    let expr0_0 = C::temp_writable_xmm(ctx);
-    let expr1_0 = SseOpcode::Maxpd;
-    let expr2_0 = C::xmm_to_xmm_mem(ctx, pattern1_0);
-    let expr3_0 = MInst::XmmRmR {
-        op: expr1_0,
-        src1: pattern0_0,
-        src2: expr2_0,
-        dst: expr0_0,
-    };
-    let expr4_0 = C::emit(ctx, &expr3_0);
-    let expr5_0 = C::writable_xmm_to_xmm(ctx, expr0_0);
-    return Some(expr5_0);
-}
-
-// Generated as internal constructor for term reg_to_xmm_mem.
-pub fn constructor_reg_to_xmm_mem<C: Context>(ctx: &mut C, arg0: Reg) -> Option<XmmMem> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/x64/inst.isle line 2549.
-    let expr0_0 = C::xmm_new(ctx, pattern0_0);
-    let expr1_0 = C::xmm_to_xmm_mem(ctx, expr0_0);
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term xmm_to_reg_mem.
-pub fn constructor_xmm_to_reg_mem<C: Context>(ctx: &mut C, arg0: Reg) -> Option<XmmMem> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/x64/inst.isle line 2552.
-    let expr0_0 = C::xmm_new(ctx, pattern0_0);
-    let expr1_0 = C::xmm_to_reg(ctx, expr0_0);
-    let expr2_0 = RegMem::Reg { reg: expr1_0 };
-    let expr3_0 = C::reg_mem_to_xmm_mem(ctx, &expr2_0);
-    return Some(expr3_0);
-}
-
-// Generated as internal constructor for term writable_gpr_to_r_reg.
-pub fn constructor_writable_gpr_to_r_reg<C: Context>(
-    ctx: &mut C,
-    arg0: WritableGpr,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/x64/inst.isle line 2556.
-    let expr0_0 = C::writable_gpr_to_reg(ctx, pattern0_0);
-    let expr1_0 = C::writable_reg_to_reg(ctx, expr0_0);
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term writable_gpr_to_gpr_mem.
-pub fn constructor_writable_gpr_to_gpr_mem<C: Context>(
-    ctx: &mut C,
-    arg0: WritableGpr,
-) -> Option<GprMem> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/x64/inst.isle line 2559.
-    let expr0_0 = C::writable_gpr_to_gpr(ctx, pattern0_0);
-    let expr1_0 = C::gpr_to_gpr_mem(ctx, expr0_0);
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term writable_gpr_to_value_regs.
-pub fn constructor_writable_gpr_to_value_regs<C: Context>(
-    ctx: &mut C,
-    arg0: WritableGpr,
-) -> Option<ValueRegs> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/x64/inst.isle line 2562.
-    let expr0_0 = constructor_writable_gpr_to_r_reg(ctx, pattern0_0)?;
-    let expr1_0 = C::value_reg(ctx, expr0_0);
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term writable_xmm_to_r_reg.
-pub fn constructor_writable_xmm_to_r_reg<C: Context>(
-    ctx: &mut C,
-    arg0: WritableXmm,
-) -> Option<Reg> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/x64/inst.isle line 2565.
-    let expr0_0 = C::writable_xmm_to_reg(ctx, pattern0_0);
-    let expr1_0 = C::writable_reg_to_reg(ctx, expr0_0);
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term writable_xmm_to_xmm_mem.
-pub fn constructor_writable_xmm_to_xmm_mem<C: Context>(
-    ctx: &mut C,
-    arg0: WritableXmm,
-) -> Option<XmmMem> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/x64/inst.isle line 2568.
-    let expr0_0 = C::writable_xmm_to_xmm(ctx, pattern0_0);
-    let expr1_0 = C::xmm_to_xmm_mem(ctx, expr0_0);
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term writable_xmm_to_value_regs.
-pub fn constructor_writable_xmm_to_value_regs<C: Context>(
-    ctx: &mut C,
-    arg0: WritableXmm,
-) -> Option<ValueRegs> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/x64/inst.isle line 2571.
-    let expr0_0 = constructor_writable_xmm_to_r_reg(ctx, pattern0_0)?;
-    let expr1_0 = C::value_reg(ctx, expr0_0);
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term synthetic_amode_to_gpr_mem.
-pub fn constructor_synthetic_amode_to_gpr_mem<C: Context>(
-    ctx: &mut C,
-    arg0: &SyntheticAmode,
-) -> Option<GprMem> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/x64/inst.isle line 2575.
-    let expr0_0 = C::synthetic_amode_to_reg_mem(ctx, pattern0_0);
-    let expr1_0 = C::reg_mem_to_gpr_mem(ctx, &expr0_0);
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term synthetic_amode_to_xmm_mem.
-pub fn constructor_synthetic_amode_to_xmm_mem<C: Context>(
-    ctx: &mut C,
-    arg0: &SyntheticAmode,
-) -> Option<XmmMem> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/x64/inst.isle line 2578.
-    let expr0_0 = C::synthetic_amode_to_reg_mem(ctx, pattern0_0);
-    let expr1_0 = C::reg_mem_to_xmm_mem(ctx, &expr0_0);
-    return Some(expr1_0);
-}
-
-// Generated as internal constructor for term lower.
-pub fn constructor_lower<C: Context>(ctx: &mut C, arg0: Inst) -> Option<InstOutput> {
-    let pattern0_0 = arg0;
-    if let Some(pattern1_0) = C::first_result(ctx, pattern0_0) {
-        let pattern2_0 = C::value_type(ctx, pattern1_0);
-        if pattern2_0 == I128 {
-            if let Some(()) = C::use_popcnt(ctx, pattern2_0) {
-                let pattern5_0 = C::inst_data(ctx, pattern0_0);
-                if let &InstructionData::Unary {
-                    opcode: ref pattern6_0,
-                    arg: pattern6_1,
-                } = &pattern5_0
-                {
-                    if let &Opcode::Popcnt = pattern6_0 {
-                        // Rule at src/isa/x64/lower.isle line 1628.
-                        let expr0_0: Type = I64;
-                        let expr1_0 = C::put_in_regs(ctx, pattern6_1);
-                        let expr2_0: usize = 0;
-                        let expr3_0 = constructor_value_regs_get_gpr(ctx, expr1_0, expr2_0)?;
-                        let expr4_0 = constructor_x64_popcnt(ctx, expr0_0, expr3_0)?;
-                        let expr5_0: Type = I64;
-                        let expr6_0 = C::put_in_regs(ctx, pattern6_1);
-                        let expr7_0: usize = 1;
-                        let expr8_0 = constructor_value_regs_get_gpr(ctx, expr6_0, expr7_0)?;
-                        let expr9_0 = constructor_x64_popcnt(ctx, expr5_0, expr8_0)?;
-                        let expr10_0: Type = I64;
-                        let expr11_0 = C::gpr_to_gpr_mem_imm(ctx, expr9_0);
-                        let expr12_0 = constructor_add(ctx, expr10_0, expr4_0, &expr11_0)?;
-                        let expr13_0 = C::gpr_to_reg(ctx, expr12_0);
-                        let expr14_0: Type = I64;
-                        let expr15_0: u64 = 0;
-                        let expr16_0 = constructor_imm(ctx, expr14_0, expr15_0)?;
-                        let expr17_0 = C::value_regs(ctx, expr13_0, expr16_0);
-                        let expr18_0 = C::output(ctx, expr17_0);
-                        return Some(expr18_0);
-                    }
-                }
-            }
-        }
-        if pattern2_0 == I8X16 {
-            if let Some(()) = C::avx512vl_enabled(ctx, pattern2_0) {
-                if let Some(()) = C::avx512bitalg_enabled(ctx, pattern2_0) {
-                    let pattern6_0 = C::inst_data(ctx, pattern0_0);
-                    if let &InstructionData::Unary {
-                        opcode: ref pattern7_0,
-                        arg: pattern7_1,
-                    } = &pattern6_0
-                    {
-                        if let &Opcode::Popcnt = pattern7_0 {
-                            // Rule at src/isa/x64/lower.isle line 1720.
-                            let expr0_0 = constructor_put_in_xmm_mem(ctx, pattern7_1)?;
-                            let expr1_0 = constructor_vpopcntb(ctx, &expr0_0)?;
-                            let expr2_0 = constructor_output_xmm(ctx, expr1_0)?;
-                            return Some(expr2_0);
-                        }
-                    }
-                }
-            }
-        }
-        if let Some(pattern3_0) = C::ty_32_or_64(ctx, pattern2_0) {
-            if let Some(()) = C::use_lzcnt(ctx, pattern2_0) {
-                let pattern5_0 = C::inst_data(ctx, pattern0_0);
-                if let &InstructionData::Unary {
-                    opcode: ref pattern6_0,
-                    arg: pattern6_1,
-                } = &pattern5_0
-                {
-                    if let &Opcode::Clz = pattern6_0 {
-                        // Rule at src/isa/x64/lower.isle line 1536.
-                        let expr0_0 = constructor_put_in_gpr(ctx, pattern6_1)?;
-                        let expr1_0 = constructor_lzcnt(ctx, pattern3_0, expr0_0)?;
-                        let expr2_0 = constructor_output_gpr(ctx, expr1_0)?;
-                        return Some(expr2_0);
-                    }
-                }
-            }
-            if let Some(()) = C::use_bmi1(ctx, pattern2_0) {
-                let pattern5_0 = C::inst_data(ctx, pattern0_0);
-                if let &InstructionData::Unary {
-                    opcode: ref pattern6_0,
-                    arg: pattern6_1,
-                } = &pattern5_0
-                {
-                    if let &Opcode::Ctz = pattern6_0 {
-                        // Rule at src/isa/x64/lower.isle line 1578.
-                        let expr0_0 = constructor_put_in_gpr(ctx, pattern6_1)?;
-                        let expr1_0 = constructor_tzcnt(ctx, pattern3_0, expr0_0)?;
-                        let expr2_0 = constructor_output_gpr(ctx, expr1_0)?;
-                        return Some(expr2_0);
-                    }
-                }
-            }
-            if let Some(()) = C::use_popcnt(ctx, pattern2_0) {
-                let pattern5_0 = C::inst_data(ctx, pattern0_0);
-                if let &InstructionData::Unary {
-                    opcode: ref pattern6_0,
-                    arg: pattern6_1,
-                } = &pattern5_0
-                {
-                    if let &Opcode::Popcnt = pattern6_0 {
-                        // Rule at src/isa/x64/lower.isle line 1614.
-                        let expr0_0 = constructor_put_in_gpr(ctx, pattern6_1)?;
-                        let expr1_0 = constructor_x64_popcnt(ctx, pattern3_0, expr0_0)?;
-                        let expr2_0 = constructor_output_gpr(ctx, expr1_0)?;
-                        return Some(expr2_0);
-                    }
-                }
-            }
-        }
-        if let Some(pattern3_0) = C::ty_8_or_16(ctx, pattern2_0) {
-            if let Some(()) = C::use_popcnt(ctx, pattern2_0) {
-                let pattern5_0 = C::inst_data(ctx, pattern0_0);
-                if let &InstructionData::Unary {
-                    opcode: ref pattern6_0,
-                    arg: pattern6_1,
-                } = &pattern5_0
-                {
-                    if let &Opcode::Popcnt = pattern6_0 {
-                        // Rule at src/isa/x64/lower.isle line 1621.
-                        let expr0_0: Type = I32;
-                        let expr1_0: Type = I32;
-                        let expr2_0 = ExtendKind::Zero;
-                        let expr3_0 =
-                            constructor_extend_to_gpr(ctx, pattern6_1, expr1_0, &expr2_0)?;
-                        let expr4_0 = constructor_x64_popcnt(ctx, expr0_0, expr3_0)?;
-                        let expr5_0 = constructor_output_gpr(ctx, expr4_0)?;
-                        return Some(expr5_0);
-                    }
-                }
-            }
-        }
-    }
-    let pattern0_0 = arg0;
-    let pattern1_0 = C::inst_data(ctx, pattern0_0);
-    match &pattern1_0 {
-        &InstructionData::NullAry {
-            opcode: ref pattern2_0,
-        } => {
-            if let &Opcode::Debugtrap = pattern2_0 {
-                // Rule at src/isa/x64/lower.isle line 2006.
-                let expr0_0 = constructor_hlt(ctx)?;
-                let expr1_0 = constructor_side_effect(ctx, &expr0_0)?;
-                return Some(expr1_0);
-            }
-        }
-        &InstructionData::UnaryIeee32 {
-            opcode: ref pattern2_0,
-            imm: pattern2_1,
-        } => {
-            if let &Opcode::F32const = pattern2_0 {
-                let pattern4_0 = C::u64_from_ieee32(ctx, pattern2_1);
-                // Rule at src/isa/x64/lower.isle line 46.
-                let expr0_0: Type = F32;
-                let expr1_0 = constructor_imm(ctx, expr0_0, pattern4_0)?;
-                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                return Some(expr2_0);
-            }
-        }
-        &InstructionData::UnaryIeee64 {
-            opcode: ref pattern2_0,
-            imm: pattern2_1,
-        } => {
-            if let &Opcode::F64const = pattern2_0 {
-                let pattern4_0 = C::u64_from_ieee64(ctx, pattern2_1);
-                // Rule at src/isa/x64/lower.isle line 51.
-                let expr0_0: Type = F64;
-                let expr1_0 = constructor_imm(ctx, expr0_0, pattern4_0)?;
-                let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                return Some(expr2_0);
-            }
-        }
-        &InstructionData::Trap {
-            opcode: ref pattern2_0,
-            code: ref pattern2_1,
-        } => {
-            match pattern2_0 {
-                &Opcode::Trap => {
-                    // Rule at src/isa/x64/lower.isle line 1435.
-                    let expr0_0 = constructor_ud2(ctx, pattern2_1)?;
-                    let expr1_0 = constructor_safepoint(ctx, &expr0_0)?;
-                    return Some(expr1_0);
-                }
-                &Opcode::ResumableTrap => {
-                    // Rule at src/isa/x64/lower.isle line 1440.
-                    let expr0_0 = constructor_ud2(ctx, pattern2_1)?;
-                    let expr1_0 = constructor_safepoint(ctx, &expr0_0)?;
-                    return Some(expr1_0);
-                }
-                _ => {}
-            }
-        }
-        &InstructionData::TernaryImm8 {
-            opcode: ref pattern2_0,
-            args: ref pattern2_1,
-            imm: pattern2_2,
-        } => {
-            if let &Opcode::Insertlane = pattern2_0 {
-                let (pattern4_0, pattern4_1) = C::unpack_value_array_2(ctx, pattern2_1);
-                let pattern5_0 = C::value_type(ctx, pattern4_0);
-                let pattern6_0 = C::u8_from_uimm8(ctx, pattern2_2);
-                // Rule at src/isa/x64/lower.isle line 1302.
-                let expr0_0 = constructor_put_in_xmm(ctx, pattern4_0)?;
-                let expr1_0 = C::put_in_reg_mem(ctx, pattern4_1);
-                let expr2_0 =
-                    constructor_vec_insert_lane(ctx, pattern5_0, expr0_0, &expr1_0, pattern6_0)?;
-                let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                return Some(expr3_0);
-            }
-        }
-        &InstructionData::Unary {
-            opcode: ref pattern2_0,
-            arg: pattern2_1,
-        } => {
-            match pattern2_0 {
-                &Opcode::IsNull => {
-                    let pattern4_0 = C::value_type(ctx, pattern2_1);
-                    if pattern4_0 == R64 {
-                        // Rule at src/isa/x64/lower.isle line 1849.
-                        let expr0_0 = OperandSize::Size64;
-                        let expr1_0: u32 = 0;
-                        let expr2_0 = constructor_put_in_gpr(ctx, pattern2_1)?;
-                        let expr3_0 = constructor_cmp_imm(ctx, &expr0_0, expr1_0, expr2_0)?;
-                        let expr4_0 = CC::Z;
-                        let expr5_0 = constructor_setcc(ctx, &expr4_0)?;
-                        let expr6_0 = constructor_with_flags(ctx, &expr3_0, &expr5_0)?;
-                        let expr7_0 = C::output(ctx, expr6_0);
-                        return Some(expr7_0);
-                    }
-                }
-                &Opcode::IsInvalid => {
-                    let pattern4_0 = C::value_type(ctx, pattern2_1);
-                    if pattern4_0 == R64 {
-                        // Rule at src/isa/x64/lower.isle line 1857.
-                        let expr0_0 = OperandSize::Size64;
-                        let expr1_0: u32 = 4294967295;
-                        let expr2_0 = constructor_put_in_gpr(ctx, pattern2_1)?;
-                        let expr3_0 = constructor_cmp_imm(ctx, &expr0_0, expr1_0, expr2_0)?;
-                        let expr4_0 = CC::Z;
-                        let expr5_0 = constructor_setcc(ctx, &expr4_0)?;
-                        let expr6_0 = constructor_with_flags(ctx, &expr3_0, &expr5_0)?;
-                        let expr7_0 = C::output(ctx, expr6_0);
-                        return Some(expr7_0);
-                    }
-                }
-                _ => {}
-            }
-        }
-        _ => {}
-    }
-    if let Some(pattern1_0) = C::first_result(ctx, pattern0_0) {
-        let pattern2_0 = C::value_type(ctx, pattern1_0);
-        if pattern2_0 == B128 {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            match &pattern4_0 {
-                &InstructionData::UnaryBool {
-                    opcode: ref pattern5_0,
-                    imm: pattern5_1,
-                } => {
-                    if let &Opcode::Bconst = pattern5_0 {
-                        if pattern5_1 == true {
-                            // Rule at src/isa/x64/lower.isle line 39.
-                            let expr0_0: Type = B64;
-                            let expr1_0: u64 = 1;
-                            let expr2_0 = constructor_imm(ctx, expr0_0, expr1_0)?;
-                            let expr3_0: Type = B64;
-                            let expr4_0: u64 = 0;
-                            let expr5_0 = constructor_imm(ctx, expr3_0, expr4_0)?;
-                            let expr6_0 = C::value_regs(ctx, expr2_0, expr5_0);
-                            let expr7_0 = C::output(ctx, expr6_0);
-                            return Some(expr7_0);
-                        }
-                        if pattern5_1 == false {
-                            // Rule at src/isa/x64/lower.isle line 34.
-                            let expr0_0: Type = B64;
-                            let expr1_0: u64 = 0;
-                            let expr2_0 = constructor_imm(ctx, expr0_0, expr1_0)?;
-                            let expr3_0: Type = B64;
-                            let expr4_0: u64 = 0;
-                            let expr5_0 = constructor_imm(ctx, expr3_0, expr4_0)?;
-                            let expr6_0 = C::value_regs(ctx, expr2_0, expr5_0);
-                            let expr7_0 = C::output(ctx, expr6_0);
-                            return Some(expr7_0);
-                        }
-                    }
-                }
-                &InstructionData::Binary {
-                    opcode: ref pattern5_0,
-                    args: ref pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Band => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 344.
-                            let expr0_0 = C::put_in_regs(ctx, pattern7_0);
-                            let expr1_0: usize = 0;
-                            let expr2_0 = constructor_value_regs_get_gpr(ctx, expr0_0, expr1_0)?;
-                            let expr3_0: usize = 1;
-                            let expr4_0 = constructor_value_regs_get_gpr(ctx, expr0_0, expr3_0)?;
-                            let expr5_0 = constructor_lo_gpr(ctx, pattern7_1)?;
-                            let expr6_0: Type = I64;
-                            let expr7_0 = C::gpr_to_gpr_mem_imm(ctx, expr5_0);
-                            let expr8_0 = constructor_x64_and(ctx, expr6_0, expr2_0, &expr7_0)?;
-                            let expr9_0 = constructor_value_gprs(ctx, expr8_0, expr4_0)?;
-                            let expr10_0 = C::output(ctx, expr9_0);
-                            return Some(expr10_0);
-                        }
-                        &Opcode::Bor => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 410.
-                            let expr0_0 = C::put_in_regs(ctx, pattern7_0);
-                            let expr1_0: usize = 0;
-                            let expr2_0 = constructor_value_regs_get_gpr(ctx, expr0_0, expr1_0)?;
-                            let expr3_0: usize = 1;
-                            let expr4_0 = constructor_value_regs_get_gpr(ctx, expr0_0, expr3_0)?;
-                            let expr5_0 = constructor_lo_gpr(ctx, pattern7_1)?;
-                            let expr6_0: Type = I64;
-                            let expr7_0 = C::gpr_to_gpr_mem_imm(ctx, expr5_0);
-                            let expr8_0 = constructor_or(ctx, expr6_0, expr2_0, &expr7_0)?;
-                            let expr9_0 = constructor_value_gprs(ctx, expr8_0, expr4_0)?;
-                            let expr10_0 = C::output(ctx, expr9_0);
-                            return Some(expr10_0);
-                        }
-                        &Opcode::Bxor => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 468.
-                            let expr0_0 = C::put_in_regs(ctx, pattern7_0);
-                            let expr1_0: usize = 0;
-                            let expr2_0 = constructor_value_regs_get_gpr(ctx, expr0_0, expr1_0)?;
-                            let expr3_0: usize = 1;
-                            let expr4_0 = constructor_value_regs_get_gpr(ctx, expr0_0, expr3_0)?;
-                            let expr5_0 = constructor_lo_gpr(ctx, pattern7_1)?;
-                            let expr6_0: Type = I64;
-                            let expr7_0 = C::gpr_to_gpr_mem_imm(ctx, expr5_0);
-                            let expr8_0 = constructor_xor(ctx, expr6_0, expr2_0, &expr7_0)?;
-                            let expr9_0 = constructor_value_gprs(ctx, expr8_0, expr4_0)?;
-                            let expr10_0 = C::output(ctx, expr9_0);
-                            return Some(expr10_0);
-                        }
-                        _ => {}
-                    }
-                }
-                &InstructionData::Unary {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                } => {
-                    if let &Opcode::Bnot = pattern5_0 {
-                        // Rule at src/isa/x64/lower.isle line 1269.
-                        let expr0_0 = constructor_i128_not(ctx, pattern5_1)?;
-                        let expr1_0 = C::output(ctx, expr0_0);
-                        return Some(expr1_0);
-                    }
-                }
-                _ => {}
-            }
-        }
-        if pattern2_0 == I8 {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            if let &InstructionData::Unary {
-                opcode: ref pattern5_0,
-                arg: pattern5_1,
-            } = &pattern4_0
-            {
-                if let &Opcode::Bitrev = pattern5_0 {
-                    // Rule at src/isa/x64/lower.isle line 1771.
-                    let expr0_0: Type = I32;
-                    let expr1_0 = constructor_put_in_gpr(ctx, pattern5_1)?;
-                    let expr2_0 = constructor_do_bitrev8(ctx, expr0_0, expr1_0)?;
-                    let expr3_0 = constructor_output_gpr(ctx, expr2_0)?;
-                    return Some(expr3_0);
-                }
-            }
-        }
-        if pattern2_0 == I16 {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            if let &InstructionData::Unary {
-                opcode: ref pattern5_0,
-                arg: pattern5_1,
-            } = &pattern4_0
-            {
-                if let &Opcode::Bitrev = pattern5_0 {
-                    // Rule at src/isa/x64/lower.isle line 1774.
-                    let expr0_0: Type = I32;
-                    let expr1_0 = constructor_put_in_gpr(ctx, pattern5_1)?;
-                    let expr2_0 = constructor_do_bitrev16(ctx, expr0_0, expr1_0)?;
-                    let expr3_0 = constructor_output_gpr(ctx, expr2_0)?;
-                    return Some(expr3_0);
-                }
-            }
-        }
-        if pattern2_0 == I32 {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            if let &InstructionData::Unary {
-                opcode: ref pattern5_0,
-                arg: pattern5_1,
-            } = &pattern4_0
-            {
-                if let &Opcode::Bitrev = pattern5_0 {
-                    // Rule at src/isa/x64/lower.isle line 1777.
-                    let expr0_0: Type = I32;
-                    let expr1_0 = constructor_put_in_gpr(ctx, pattern5_1)?;
-                    let expr2_0 = constructor_do_bitrev32(ctx, expr0_0, expr1_0)?;
-                    let expr3_0 = constructor_output_gpr(ctx, expr2_0)?;
-                    return Some(expr3_0);
-                }
-            }
-        }
-        if pattern2_0 == I64 {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            if let &InstructionData::Unary {
-                opcode: ref pattern5_0,
-                arg: pattern5_1,
-            } = &pattern4_0
-            {
-                match pattern5_0 {
-                    &Opcode::Bitrev => {
-                        // Rule at src/isa/x64/lower.isle line 1780.
-                        let expr0_0: Type = I64;
-                        let expr1_0 = constructor_put_in_gpr(ctx, pattern5_1)?;
-                        let expr2_0 = constructor_do_bitrev64(ctx, expr0_0, expr1_0)?;
-                        let expr3_0 = constructor_output_gpr(ctx, expr2_0)?;
-                        return Some(expr3_0);
-                    }
-                    &Opcode::Uextend => {
-                        if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
-                            if let Some(pattern8_0) = C::first_result(ctx, pattern7_0) {
-                                let pattern9_0 = C::value_type(ctx, pattern8_0);
-                                if pattern9_0 == I32 {
-                                    let pattern11_0 = C::inst_data(ctx, pattern7_0);
-                                    match &pattern11_0 {
-                                        &InstructionData::Binary {
-                                            opcode: ref pattern12_0,
-                                            args: ref pattern12_1,
-                                        } => {
-                                            match pattern12_0 {
-                                                &Opcode::Iadd => {
-                                                    let (pattern14_0, pattern14_1) =
-                                                        C::unpack_value_array_2(ctx, pattern12_1);
-                                                    // Rule at src/isa/x64/lower.isle line 1896.
-                                                    let expr0_0 =
-                                                        constructor_output_value(ctx, pattern5_1)?;
-                                                    return Some(expr0_0);
-                                                }
-                                                &Opcode::Isub => {
-                                                    let (pattern14_0, pattern14_1) =
-                                                        C::unpack_value_array_2(ctx, pattern12_1);
-                                                    // Rule at src/isa/x64/lower.isle line 1902.
-                                                    let expr0_0 =
-                                                        constructor_output_value(ctx, pattern5_1)?;
-                                                    return Some(expr0_0);
-                                                }
-                                                &Opcode::Imul => {
-                                                    let (pattern14_0, pattern14_1) =
-                                                        C::unpack_value_array_2(ctx, pattern12_1);
-                                                    // Rule at src/isa/x64/lower.isle line 1905.
-                                                    let expr0_0 =
-                                                        constructor_output_value(ctx, pattern5_1)?;
-                                                    return Some(expr0_0);
-                                                }
-                                                &Opcode::IaddIfcout => {
-                                                    let (pattern14_0, pattern14_1) =
-                                                        C::unpack_value_array_2(ctx, pattern12_1);
-                                                    // Rule at src/isa/x64/lower.isle line 1899.
-                                                    let expr0_0 =
-                                                        constructor_output_value(ctx, pattern5_1)?;
-                                                    return Some(expr0_0);
-                                                }
-                                                &Opcode::Band => {
-                                                    let (pattern14_0, pattern14_1) =
-                                                        C::unpack_value_array_2(ctx, pattern12_1);
-                                                    // Rule at src/isa/x64/lower.isle line 1908.
-                                                    let expr0_0 =
-                                                        constructor_output_value(ctx, pattern5_1)?;
-                                                    return Some(expr0_0);
-                                                }
-                                                &Opcode::Bor => {
-                                                    let (pattern14_0, pattern14_1) =
-                                                        C::unpack_value_array_2(ctx, pattern12_1);
-                                                    // Rule at src/isa/x64/lower.isle line 1911.
-                                                    let expr0_0 =
-                                                        constructor_output_value(ctx, pattern5_1)?;
-                                                    return Some(expr0_0);
-                                                }
-                                                &Opcode::Bxor => {
-                                                    let (pattern14_0, pattern14_1) =
-                                                        C::unpack_value_array_2(ctx, pattern12_1);
-                                                    // Rule at src/isa/x64/lower.isle line 1914.
-                                                    let expr0_0 =
-                                                        constructor_output_value(ctx, pattern5_1)?;
-                                                    return Some(expr0_0);
-                                                }
-                                                &Opcode::Ishl => {
-                                                    let (pattern14_0, pattern14_1) =
-                                                        C::unpack_value_array_2(ctx, pattern12_1);
-                                                    // Rule at src/isa/x64/lower.isle line 1917.
-                                                    let expr0_0 =
-                                                        constructor_output_value(ctx, pattern5_1)?;
-                                                    return Some(expr0_0);
-                                                }
-                                                &Opcode::Ushr => {
-                                                    let (pattern14_0, pattern14_1) =
-                                                        C::unpack_value_array_2(ctx, pattern12_1);
-                                                    // Rule at src/isa/x64/lower.isle line 1920.
-                                                    let expr0_0 =
-                                                        constructor_output_value(ctx, pattern5_1)?;
-                                                    return Some(expr0_0);
-                                                }
-                                                _ => {}
-                                            }
-                                        }
-                                        &InstructionData::Load {
-                                            opcode: ref pattern12_0,
-                                            arg: pattern12_1,
-                                            flags: pattern12_2,
-                                            offset: pattern12_3,
-                                        } => {
-                                            if let &Opcode::Uload32 = pattern12_0 {
-                                                // Rule at src/isa/x64/lower.isle line 1923.
-                                                let expr0_0 =
-                                                    constructor_output_value(ctx, pattern5_1)?;
-                                                return Some(expr0_0);
-                                            }
-                                        }
-                                        _ => {}
-                                    }
-                                }
-                            }
-                        }
-                        let pattern7_0 = C::value_type(ctx, pattern5_1);
-                        if let Some(pattern8_0) = C::fits_in_32(ctx, pattern7_0) {
-                            // Rule at src/isa/x64/lower.isle line 1878.
-                            let expr0_0: Type = I64;
-                            let expr1_0 = ExtendKind::Zero;
-                            let expr2_0 =
-                                constructor_extend_to_gpr(ctx, pattern5_1, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_gpr(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                    }
-                    _ => {}
-                }
-            }
-        }
-        if pattern2_0 == I128 {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            match &pattern4_0 {
-                &InstructionData::UnaryImm {
-                    opcode: ref pattern5_0,
-                    imm: pattern5_1,
-                } => {
-                    if let &Opcode::Iconst = pattern5_0 {
-                        let pattern7_0 = C::u64_from_imm64(ctx, pattern5_1);
-                        // Rule at src/isa/x64/lower.isle line 15.
-                        let expr0_0: Type = I64;
-                        let expr1_0 = constructor_imm(ctx, expr0_0, pattern7_0)?;
-                        let expr2_0: Type = I64;
-                        let expr3_0: u64 = 0;
-                        let expr4_0 = constructor_imm(ctx, expr2_0, expr3_0)?;
-                        let expr5_0 = C::value_regs(ctx, expr1_0, expr4_0);
-                        let expr6_0 = C::output(ctx, expr5_0);
-                        return Some(expr6_0);
-                    }
-                }
-                &InstructionData::Binary {
-                    opcode: ref pattern5_0,
-                    args: ref pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Iadd => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 111.
-                            let expr0_0 = C::put_in_regs(ctx, pattern7_0);
-                            let expr1_0: usize = 0;
-                            let expr2_0 = constructor_value_regs_get_gpr(ctx, expr0_0, expr1_0)?;
-                            let expr3_0: usize = 1;
-                            let expr4_0 = constructor_value_regs_get_gpr(ctx, expr0_0, expr3_0)?;
-                            let expr5_0 = C::put_in_regs(ctx, pattern7_1);
-                            let expr6_0: usize = 0;
-                            let expr7_0 = constructor_value_regs_get_gpr(ctx, expr5_0, expr6_0)?;
-                            let expr8_0: usize = 1;
-                            let expr9_0 = constructor_value_regs_get_gpr(ctx, expr5_0, expr8_0)?;
-                            let expr10_0: Type = I64;
-                            let expr11_0 = C::gpr_to_gpr_mem_imm(ctx, expr7_0);
-                            let expr12_0 = constructor_add_with_flags_paired(
-                                ctx, expr10_0, expr2_0, &expr11_0,
-                            )?;
-                            let expr13_0: Type = I64;
-                            let expr14_0 = C::gpr_to_gpr_mem_imm(ctx, expr9_0);
-                            let expr15_0 =
-                                constructor_adc_paired(ctx, expr13_0, expr4_0, &expr14_0)?;
-                            let expr16_0 = constructor_with_flags(ctx, &expr12_0, &expr15_0)?;
-                            let expr17_0 = C::output(ctx, expr16_0);
-                            return Some(expr17_0);
-                        }
-                        &Opcode::Isub => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 257.
-                            let expr0_0 = C::put_in_regs(ctx, pattern7_0);
-                            let expr1_0: usize = 0;
-                            let expr2_0 = constructor_value_regs_get_gpr(ctx, expr0_0, expr1_0)?;
-                            let expr3_0: usize = 1;
-                            let expr4_0 = constructor_value_regs_get_gpr(ctx, expr0_0, expr3_0)?;
-                            let expr5_0 = C::put_in_regs(ctx, pattern7_1);
-                            let expr6_0: usize = 0;
-                            let expr7_0 = constructor_value_regs_get_gpr(ctx, expr5_0, expr6_0)?;
-                            let expr8_0: usize = 1;
-                            let expr9_0 = constructor_value_regs_get_gpr(ctx, expr5_0, expr8_0)?;
-                            let expr10_0: Type = I64;
-                            let expr11_0 = C::gpr_to_gpr_mem_imm(ctx, expr7_0);
-                            let expr12_0 = constructor_sub_with_flags_paired(
-                                ctx, expr10_0, expr2_0, &expr11_0,
-                            )?;
-                            let expr13_0: Type = I64;
-                            let expr14_0 = C::gpr_to_gpr_mem_imm(ctx, expr9_0);
-                            let expr15_0 =
-                                constructor_sbb_paired(ctx, expr13_0, expr4_0, &expr14_0)?;
-                            let expr16_0 = constructor_with_flags(ctx, &expr12_0, &expr15_0)?;
-                            let expr17_0 = C::output(ctx, expr16_0);
-                            return Some(expr17_0);
-                        }
-                        &Opcode::Imul => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 957.
-                            let expr0_0 = C::put_in_regs(ctx, pattern7_0);
-                            let expr1_0: usize = 0;
-                            let expr2_0 = constructor_value_regs_get_gpr(ctx, expr0_0, expr1_0)?;
-                            let expr3_0: usize = 1;
-                            let expr4_0 = constructor_value_regs_get_gpr(ctx, expr0_0, expr3_0)?;
-                            let expr5_0 = C::put_in_regs(ctx, pattern7_1);
-                            let expr6_0: usize = 0;
-                            let expr7_0 = constructor_value_regs_get_gpr(ctx, expr5_0, expr6_0)?;
-                            let expr8_0: usize = 1;
-                            let expr9_0 = constructor_value_regs_get_gpr(ctx, expr5_0, expr8_0)?;
-                            let expr10_0: Type = I64;
-                            let expr11_0 = C::gpr_to_gpr_mem_imm(ctx, expr9_0);
-                            let expr12_0 = constructor_mul(ctx, expr10_0, expr2_0, &expr11_0)?;
-                            let expr13_0: Type = I64;
-                            let expr14_0 = C::gpr_to_gpr_mem_imm(ctx, expr7_0);
-                            let expr15_0 = constructor_mul(ctx, expr13_0, expr4_0, &expr14_0)?;
-                            let expr16_0: Type = I64;
-                            let expr17_0 = C::gpr_to_gpr_mem_imm(ctx, expr15_0);
-                            let expr18_0 = constructor_add(ctx, expr16_0, expr12_0, &expr17_0)?;
-                            let expr19_0: Type = I64;
-                            let expr20_0 = C::gpr_to_gpr_mem(ctx, expr7_0);
-                            let expr21_0 = constructor_mulhi_u(ctx, expr19_0, expr2_0, &expr20_0)?;
-                            let expr22_0: usize = 0;
-                            let expr23_0 = constructor_value_regs_get_gpr(ctx, expr21_0, expr22_0)?;
-                            let expr24_0: usize = 1;
-                            let expr25_0 = constructor_value_regs_get_gpr(ctx, expr21_0, expr24_0)?;
-                            let expr26_0: Type = I64;
-                            let expr27_0 = C::gpr_to_gpr_mem_imm(ctx, expr25_0);
-                            let expr28_0 = constructor_add(ctx, expr26_0, expr18_0, &expr27_0)?;
-                            let expr29_0 = constructor_value_gprs(ctx, expr23_0, expr28_0)?;
-                            let expr30_0 = C::output(ctx, expr29_0);
-                            return Some(expr30_0);
-                        }
-                        &Opcode::Band => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 334.
-                            let expr0_0 = C::put_in_regs(ctx, pattern7_0);
-                            let expr1_0: usize = 0;
-                            let expr2_0 = constructor_value_regs_get_gpr(ctx, expr0_0, expr1_0)?;
-                            let expr3_0: usize = 1;
-                            let expr4_0 = constructor_value_regs_get_gpr(ctx, expr0_0, expr3_0)?;
-                            let expr5_0 = C::put_in_regs(ctx, pattern7_1);
-                            let expr6_0: usize = 0;
-                            let expr7_0 = constructor_value_regs_get_gpr(ctx, expr5_0, expr6_0)?;
-                            let expr8_0: usize = 1;
-                            let expr9_0 = constructor_value_regs_get_gpr(ctx, expr5_0, expr8_0)?;
-                            let expr10_0: Type = I64;
-                            let expr11_0 = C::gpr_to_gpr_mem_imm(ctx, expr7_0);
-                            let expr12_0 = constructor_x64_and(ctx, expr10_0, expr2_0, &expr11_0)?;
-                            let expr13_0: Type = I64;
-                            let expr14_0 = C::gpr_to_gpr_mem_imm(ctx, expr9_0);
-                            let expr15_0 = constructor_x64_and(ctx, expr13_0, expr4_0, &expr14_0)?;
-                            let expr16_0 = constructor_value_gprs(ctx, expr12_0, expr15_0)?;
-                            let expr17_0 = C::output(ctx, expr16_0);
-                            return Some(expr17_0);
-                        }
-                        &Opcode::Bor => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 407.
-                            let expr0_0 = C::put_in_regs(ctx, pattern7_0);
-                            let expr1_0 = C::put_in_regs(ctx, pattern7_1);
-                            let expr2_0 = constructor_or_i128(ctx, expr0_0, expr1_0)?;
-                            let expr3_0 = C::output(ctx, expr2_0);
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Bxor => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 458.
-                            let expr0_0 = C::put_in_regs(ctx, pattern7_0);
-                            let expr1_0: usize = 0;
-                            let expr2_0 = constructor_value_regs_get_gpr(ctx, expr0_0, expr1_0)?;
-                            let expr3_0: usize = 1;
-                            let expr4_0 = constructor_value_regs_get_gpr(ctx, expr0_0, expr3_0)?;
-                            let expr5_0 = C::put_in_regs(ctx, pattern7_1);
-                            let expr6_0: usize = 0;
-                            let expr7_0 = constructor_value_regs_get_gpr(ctx, expr5_0, expr6_0)?;
-                            let expr8_0: usize = 1;
-                            let expr9_0 = constructor_value_regs_get_gpr(ctx, expr5_0, expr8_0)?;
-                            let expr10_0: Type = I64;
-                            let expr11_0 = C::gpr_to_gpr_mem_imm(ctx, expr7_0);
-                            let expr12_0 = constructor_xor(ctx, expr10_0, expr2_0, &expr11_0)?;
-                            let expr13_0: Type = I64;
-                            let expr14_0 = C::gpr_to_gpr_mem_imm(ctx, expr9_0);
-                            let expr15_0 = constructor_xor(ctx, expr13_0, expr4_0, &expr14_0)?;
-                            let expr16_0 = constructor_value_gprs(ctx, expr12_0, expr15_0)?;
-                            let expr17_0 = C::output(ctx, expr16_0);
-                            return Some(expr17_0);
-                        }
-                        &Opcode::Rotl => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 830.
-                            let expr0_0 = C::put_in_regs(ctx, pattern7_0);
-                            let expr1_0 = constructor_lo_gpr(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_shl_i128(ctx, expr0_0, expr1_0)?;
-                            let expr3_0: Type = I64;
-                            let expr4_0: Type = I64;
-                            let expr5_0: u64 = 128;
-                            let expr6_0 = constructor_imm(ctx, expr4_0, expr5_0)?;
-                            let expr7_0 = C::gpr_new(ctx, expr6_0);
-                            let expr8_0 = C::gpr_to_gpr_mem_imm(ctx, expr1_0);
-                            let expr9_0 = constructor_sub(ctx, expr3_0, expr7_0, &expr8_0)?;
-                            let expr10_0 = constructor_shr_i128(ctx, expr0_0, expr9_0)?;
-                            let expr11_0 = constructor_or_i128(ctx, expr2_0, expr10_0)?;
-                            let expr12_0 = C::output(ctx, expr11_0);
-                            return Some(expr12_0);
-                        }
-                        &Opcode::Rotr => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 870.
-                            let expr0_0 = C::put_in_regs(ctx, pattern7_0);
-                            let expr1_0 = constructor_lo_gpr(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_shr_i128(ctx, expr0_0, expr1_0)?;
-                            let expr3_0: Type = I64;
-                            let expr4_0: Type = I64;
-                            let expr5_0: u64 = 128;
-                            let expr6_0 = constructor_imm(ctx, expr4_0, expr5_0)?;
-                            let expr7_0 = C::gpr_new(ctx, expr6_0);
-                            let expr8_0 = C::gpr_to_gpr_mem_imm(ctx, expr1_0);
-                            let expr9_0 = constructor_sub(ctx, expr3_0, expr7_0, &expr8_0)?;
-                            let expr10_0 = constructor_shl_i128(ctx, expr0_0, expr9_0)?;
-                            let expr11_0 = constructor_or_i128(ctx, expr2_0, expr10_0)?;
-                            let expr12_0 = C::output(ctx, expr11_0);
-                            return Some(expr12_0);
-                        }
-                        &Opcode::Ishl => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 522.
-                            let expr0_0 = constructor_lo_gpr(ctx, pattern7_1)?;
-                            let expr1_0 = C::put_in_regs(ctx, pattern7_0);
-                            let expr2_0 = constructor_shl_i128(ctx, expr1_0, expr0_0)?;
-                            let expr3_0 = C::output(ctx, expr2_0);
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Ushr => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 623.
-                            let expr0_0 = constructor_lo_gpr(ctx, pattern7_1)?;
-                            let expr1_0 = C::put_in_regs(ctx, pattern7_0);
-                            let expr2_0 = constructor_shr_i128(ctx, expr1_0, expr0_0)?;
-                            let expr3_0 = C::output(ctx, expr2_0);
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Sshr => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 728.
-                            let expr0_0 = constructor_lo_gpr(ctx, pattern7_1)?;
-                            let expr1_0 = C::put_in_regs(ctx, pattern7_0);
-                            let expr2_0 = constructor_sar_i128(ctx, expr1_0, expr0_0)?;
-                            let expr3_0 = C::output(ctx, expr2_0);
-                            return Some(expr3_0);
-                        }
-                        _ => {}
-                    }
-                }
-                &InstructionData::Unary {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Bnot => {
-                            // Rule at src/isa/x64/lower.isle line 1266.
-                            let expr0_0 = constructor_i128_not(ctx, pattern5_1)?;
-                            let expr1_0 = C::output(ctx, expr0_0);
-                            return Some(expr1_0);
-                        }
-                        &Opcode::Bitrev => {
-                            // Rule at src/isa/x64/lower.isle line 1783.
-                            let expr0_0: Type = I64;
-                            let expr1_0 = C::put_in_regs(ctx, pattern5_1);
-                            let expr2_0: usize = 1;
-                            let expr3_0 = constructor_value_regs_get_gpr(ctx, expr1_0, expr2_0)?;
-                            let expr4_0 = constructor_do_bitrev64(ctx, expr0_0, expr3_0)?;
-                            let expr5_0 = C::gpr_to_reg(ctx, expr4_0);
-                            let expr6_0: Type = I64;
-                            let expr7_0 = C::put_in_regs(ctx, pattern5_1);
-                            let expr8_0: usize = 0;
-                            let expr9_0 = constructor_value_regs_get_gpr(ctx, expr7_0, expr8_0)?;
-                            let expr10_0 = constructor_do_bitrev64(ctx, expr6_0, expr9_0)?;
-                            let expr11_0 = C::gpr_to_reg(ctx, expr10_0);
-                            let expr12_0 = C::value_regs(ctx, expr5_0, expr11_0);
-                            let expr13_0 = C::output(ctx, expr12_0);
-                            return Some(expr13_0);
-                        }
-                        &Opcode::Clz => {
-                            // Rule at src/isa/x64/lower.isle line 1553.
-                            let expr0_0: Type = I64;
-                            let expr1_0: Type = I64;
-                            let expr2_0 = C::put_in_regs(ctx, pattern5_1);
-                            let expr3_0: usize = 1;
-                            let expr4_0 = constructor_value_regs_get_gpr(ctx, expr2_0, expr3_0)?;
-                            let expr5_0 = constructor_do_clz(ctx, expr0_0, expr1_0, expr4_0)?;
-                            let expr6_0: Type = I64;
-                            let expr7_0: Type = I64;
-                            let expr8_0: Type = I64;
-                            let expr9_0 = C::put_in_regs(ctx, pattern5_1);
-                            let expr10_0: usize = 0;
-                            let expr11_0 = constructor_value_regs_get_gpr(ctx, expr9_0, expr10_0)?;
-                            let expr12_0 = constructor_do_clz(ctx, expr7_0, expr8_0, expr11_0)?;
-                            let expr13_0: u32 = 64;
-                            let expr14_0 = RegMemImm::Imm { simm32: expr13_0 };
-                            let expr15_0 = C::gpr_mem_imm_new(ctx, &expr14_0);
-                            let expr16_0 = constructor_add(ctx, expr6_0, expr12_0, &expr15_0)?;
-                            let expr17_0 = OperandSize::Size64;
-                            let expr18_0: u32 = 64;
-                            let expr19_0 = constructor_cmp_imm(ctx, &expr17_0, expr18_0, expr5_0)?;
-                            let expr20_0: Type = I64;
-                            let expr21_0 = CC::NZ;
-                            let expr22_0 = C::gpr_to_gpr_mem(ctx, expr5_0);
-                            let expr23_0 =
-                                constructor_cmove(ctx, expr20_0, &expr21_0, &expr22_0, expr16_0)?;
-                            let expr24_0 = constructor_with_flags_reg(ctx, &expr19_0, &expr23_0)?;
-                            let expr25_0 = C::gpr_new(ctx, expr24_0);
-                            let expr26_0 = C::gpr_to_reg(ctx, expr25_0);
-                            let expr27_0: Type = I64;
-                            let expr28_0: u64 = 0;
-                            let expr29_0 = constructor_imm(ctx, expr27_0, expr28_0)?;
-                            let expr30_0 = C::value_regs(ctx, expr26_0, expr29_0);
-                            let expr31_0 = C::output(ctx, expr30_0);
-                            return Some(expr31_0);
-                        }
-                        &Opcode::Ctz => {
-                            // Rule at src/isa/x64/lower.isle line 1595.
-                            let expr0_0: Type = I64;
-                            let expr1_0: Type = I64;
-                            let expr2_0 = C::put_in_regs(ctx, pattern5_1);
-                            let expr3_0: usize = 0;
-                            let expr4_0 = constructor_value_regs_get_gpr(ctx, expr2_0, expr3_0)?;
-                            let expr5_0 = constructor_do_ctz(ctx, expr0_0, expr1_0, expr4_0)?;
-                            let expr6_0: Type = I64;
-                            let expr7_0: Type = I64;
-                            let expr8_0: Type = I64;
-                            let expr9_0 = C::put_in_regs(ctx, pattern5_1);
-                            let expr10_0: usize = 1;
-                            let expr11_0 = constructor_value_regs_get_gpr(ctx, expr9_0, expr10_0)?;
-                            let expr12_0 = constructor_do_ctz(ctx, expr7_0, expr8_0, expr11_0)?;
-                            let expr13_0: u32 = 64;
-                            let expr14_0 = RegMemImm::Imm { simm32: expr13_0 };
-                            let expr15_0 = C::gpr_mem_imm_new(ctx, &expr14_0);
-                            let expr16_0 = constructor_add(ctx, expr6_0, expr12_0, &expr15_0)?;
-                            let expr17_0 = OperandSize::Size64;
-                            let expr18_0: u32 = 64;
-                            let expr19_0 = constructor_cmp_imm(ctx, &expr17_0, expr18_0, expr5_0)?;
-                            let expr20_0: Type = I64;
-                            let expr21_0 = CC::Z;
-                            let expr22_0 = C::gpr_to_gpr_mem(ctx, expr16_0);
-                            let expr23_0 =
-                                constructor_cmove(ctx, expr20_0, &expr21_0, &expr22_0, expr5_0)?;
-                            let expr24_0 = constructor_with_flags_reg(ctx, &expr19_0, &expr23_0)?;
-                            let expr25_0 = C::gpr_new(ctx, expr24_0);
-                            let expr26_0 = C::gpr_to_reg(ctx, expr25_0);
-                            let expr27_0: Type = I64;
-                            let expr28_0: u64 = 0;
-                            let expr29_0 = constructor_imm(ctx, expr27_0, expr28_0)?;
-                            let expr30_0 = C::value_regs(ctx, expr26_0, expr29_0);
-                            let expr31_0 = C::output(ctx, expr30_0);
-                            return Some(expr31_0);
-                        }
-                        &Opcode::Popcnt => {
-                            // Rule at src/isa/x64/lower.isle line 1647.
-                            let expr0_0: Type = I64;
-                            let expr1_0 = C::put_in_regs(ctx, pattern5_1);
-                            let expr2_0: usize = 0;
-                            let expr3_0 = constructor_value_regs_get_gpr(ctx, expr1_0, expr2_0)?;
-                            let expr4_0 = constructor_do_popcnt(ctx, expr0_0, expr3_0)?;
-                            let expr5_0: Type = I64;
-                            let expr6_0 = C::put_in_regs(ctx, pattern5_1);
-                            let expr7_0: usize = 1;
-                            let expr8_0 = constructor_value_regs_get_gpr(ctx, expr6_0, expr7_0)?;
-                            let expr9_0 = constructor_do_popcnt(ctx, expr5_0, expr8_0)?;
-                            let expr10_0: Type = I64;
-                            let expr11_0 = C::gpr_to_gpr_mem_imm(ctx, expr9_0);
-                            let expr12_0 = constructor_add(ctx, expr10_0, expr4_0, &expr11_0)?;
-                            let expr13_0 = C::gpr_to_reg(ctx, expr12_0);
-                            let expr14_0: Type = I64;
-                            let expr15_0: u64 = 0;
-                            let expr16_0 = constructor_imm(ctx, expr14_0, expr15_0)?;
-                            let expr17_0 = C::value_regs(ctx, expr13_0, expr16_0);
-                            let expr18_0 = C::output(ctx, expr17_0);
-                            return Some(expr18_0);
-                        }
-                        &Opcode::Bint => {
-                            // Rule at src/isa/x64/lower.isle line 1998.
-                            let expr0_0: Type = I64;
-                            let expr1_0 = constructor_put_in_gpr(ctx, pattern5_1)?;
-                            let expr2_0: u32 = 1;
-                            let expr3_0 = RegMemImm::Imm { simm32: expr2_0 };
-                            let expr4_0 = C::gpr_mem_imm_new(ctx, &expr3_0);
-                            let expr5_0 = constructor_x64_and(ctx, expr0_0, expr1_0, &expr4_0)?;
-                            let expr6_0 = C::gpr_to_reg(ctx, expr5_0);
-                            let expr7_0: Type = I64;
-                            let expr8_0: u64 = 0;
-                            let expr9_0 = constructor_imm(ctx, expr7_0, expr8_0)?;
-                            let expr10_0 = C::value_regs(ctx, expr6_0, expr9_0);
-                            let expr11_0 = C::output(ctx, expr10_0);
-                            return Some(expr11_0);
-                        }
-                        &Opcode::Uextend => {
-                            let pattern7_0 = C::value_type(ctx, pattern5_1);
-                            if pattern7_0 == I64 {
-                                // Rule at src/isa/x64/lower.isle line 1870.
-                                let expr0_0 = C::put_in_reg(ctx, pattern5_1);
-                                let expr1_0: Type = I64;
-                                let expr2_0: u64 = 0;
-                                let expr3_0 = constructor_imm(ctx, expr1_0, expr2_0)?;
-                                let expr4_0 = C::value_regs(ctx, expr0_0, expr3_0);
-                                let expr5_0 = C::output(ctx, expr4_0);
-                                return Some(expr5_0);
-                            }
-                            if let Some(pattern8_0) = C::fits_in_32(ctx, pattern7_0) {
-                                // Rule at src/isa/x64/lower.isle line 1874.
-                                let expr0_0: Type = I64;
-                                let expr1_0 = ExtendKind::Zero;
-                                let expr2_0 =
-                                    constructor_extend_to_gpr(ctx, pattern5_1, expr0_0, &expr1_0)?;
-                                let expr3_0 = C::gpr_to_reg(ctx, expr2_0);
-                                let expr4_0: Type = I64;
-                                let expr5_0: u64 = 0;
-                                let expr6_0 = constructor_imm(ctx, expr4_0, expr5_0)?;
-                                let expr7_0 = C::value_regs(ctx, expr3_0, expr6_0);
-                                let expr8_0 = C::output(ctx, expr7_0);
-                                return Some(expr8_0);
-                            }
-                        }
-                        _ => {}
-                    }
-                }
-                &InstructionData::BinaryImm64 {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                    imm: pattern5_2,
-                } => {
-                    if let &Opcode::IaddImm = pattern5_0 {
-                        let pattern7_0 = C::u64_from_imm64(ctx, pattern5_2);
-                        // Rule at src/isa/x64/lower.isle line 210.
-                        let expr0_0 = C::put_in_regs(ctx, pattern5_1);
-                        let expr1_0: usize = 0;
-                        let expr2_0 = constructor_value_regs_get_gpr(ctx, expr0_0, expr1_0)?;
-                        let expr3_0: usize = 1;
-                        let expr4_0 = constructor_value_regs_get_gpr(ctx, expr0_0, expr3_0)?;
-                        let expr5_0: Type = I64;
-                        let expr6_0 = constructor_imm(ctx, expr5_0, pattern7_0)?;
-                        let expr7_0 = C::gpr_new(ctx, expr6_0);
-                        let expr8_0: Type = I64;
-                        let expr9_0 = C::gpr_to_gpr_mem_imm(ctx, expr7_0);
-                        let expr10_0 =
-                            constructor_add_with_flags_paired(ctx, expr8_0, expr2_0, &expr9_0)?;
-                        let expr11_0: Type = I64;
-                        let expr12_0: u32 = 0;
-                        let expr13_0 = RegMemImm::Imm { simm32: expr12_0 };
-                        let expr14_0 = C::gpr_mem_imm_new(ctx, &expr13_0);
-                        let expr15_0 = constructor_adc_paired(ctx, expr11_0, expr4_0, &expr14_0)?;
-                        let expr16_0 = constructor_with_flags(ctx, &expr10_0, &expr15_0)?;
-                        let expr17_0 = C::output(ctx, expr16_0);
-                        return Some(expr17_0);
-                    }
-                }
-                _ => {}
-            }
-        }
-        if pattern2_0 == F32 {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            if let &InstructionData::Binary {
-                opcode: ref pattern5_0,
-                args: ref pattern5_1,
-            } = &pattern4_0
-            {
-                match pattern5_0 {
-                    &Opcode::Fadd => {
-                        let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                        // Rule at src/isa/x64/lower.isle line 2021.
-                        let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                        let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern7_1)?;
-                        let expr2_0 = constructor_addss(ctx, expr0_0, &expr1_0)?;
-                        let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                        return Some(expr3_0);
-                    }
-                    &Opcode::Fsub => {
-                        let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                        // Rule at src/isa/x64/lower.isle line 2032.
-                        let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                        let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern7_1)?;
-                        let expr2_0 = constructor_subss(ctx, expr0_0, &expr1_0)?;
-                        let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                        return Some(expr3_0);
-                    }
-                    &Opcode::Fmul => {
-                        let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                        // Rule at src/isa/x64/lower.isle line 2043.
-                        let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                        let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern7_1)?;
-                        let expr2_0 = constructor_mulss(ctx, expr0_0, &expr1_0)?;
-                        let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                        return Some(expr3_0);
-                    }
-                    &Opcode::Fdiv => {
-                        let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                        // Rule at src/isa/x64/lower.isle line 2054.
-                        let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                        let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern7_1)?;
-                        let expr2_0 = constructor_divss(ctx, expr0_0, &expr1_0)?;
-                        let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                        return Some(expr3_0);
-                    }
-                    &Opcode::Fmin => {
-                        let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                        // Rule at src/isa/x64/lower.isle line 2065.
-                        let expr0_0: Type = F32;
-                        let expr1_0: bool = true;
-                        let expr2_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                        let expr3_0 = constructor_put_in_xmm(ctx, pattern7_1)?;
-                        let expr4_0 =
-                            constructor_xmm_min_max_seq(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
-                        let expr5_0 = constructor_output_xmm(ctx, expr4_0)?;
-                        return Some(expr5_0);
-                    }
-                    &Opcode::FminPseudo => {
-                        let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                        // Rule at src/isa/x64/lower.isle line 2234.
-                        let expr0_0 = constructor_put_in_xmm(ctx, pattern7_1)?;
-                        let expr1_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                        let expr2_0 = constructor_minss(ctx, expr0_0, expr1_0)?;
-                        let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                        return Some(expr3_0);
-                    }
-                    &Opcode::Fmax => {
-                        let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                        // Rule at src/isa/x64/lower.isle line 2137.
-                        let expr0_0: Type = F32;
-                        let expr1_0: bool = false;
-                        let expr2_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                        let expr3_0 = constructor_put_in_xmm(ctx, pattern7_1)?;
-                        let expr4_0 =
-                            constructor_xmm_min_max_seq(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
-                        let expr5_0 = constructor_output_xmm(ctx, expr4_0)?;
-                        return Some(expr5_0);
-                    }
-                    &Opcode::FmaxPseudo => {
-                        let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                        // Rule at src/isa/x64/lower.isle line 2245.
-                        let expr0_0 = constructor_put_in_xmm(ctx, pattern7_1)?;
-                        let expr1_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                        let expr2_0 = constructor_maxss(ctx, expr0_0, expr1_0)?;
-                        let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                        return Some(expr3_0);
-                    }
-                    _ => {}
-                }
-            }
-        }
-        if pattern2_0 == F64 {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            if let &InstructionData::Binary {
-                opcode: ref pattern5_0,
-                args: ref pattern5_1,
-            } = &pattern4_0
-            {
-                match pattern5_0 {
-                    &Opcode::Fadd => {
-                        let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                        // Rule at src/isa/x64/lower.isle line 2023.
-                        let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                        let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern7_1)?;
-                        let expr2_0 = constructor_addsd(ctx, expr0_0, &expr1_0)?;
-                        let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                        return Some(expr3_0);
-                    }
-                    &Opcode::Fsub => {
-                        let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                        // Rule at src/isa/x64/lower.isle line 2034.
-                        let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                        let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern7_1)?;
-                        let expr2_0 = constructor_subsd(ctx, expr0_0, &expr1_0)?;
-                        let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                        return Some(expr3_0);
-                    }
-                    &Opcode::Fmul => {
-                        let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                        // Rule at src/isa/x64/lower.isle line 2045.
-                        let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                        let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern7_1)?;
-                        let expr2_0 = constructor_mulsd(ctx, expr0_0, &expr1_0)?;
-                        let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                        return Some(expr3_0);
-                    }
-                    &Opcode::Fdiv => {
-                        let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                        // Rule at src/isa/x64/lower.isle line 2056.
-                        let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                        let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern7_1)?;
-                        let expr2_0 = constructor_divsd(ctx, expr0_0, &expr1_0)?;
-                        let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                        return Some(expr3_0);
-                    }
-                    &Opcode::Fmin => {
-                        let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                        // Rule at src/isa/x64/lower.isle line 2067.
-                        let expr0_0: Type = F64;
-                        let expr1_0: bool = true;
-                        let expr2_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                        let expr3_0 = constructor_put_in_xmm(ctx, pattern7_1)?;
-                        let expr4_0 =
-                            constructor_xmm_min_max_seq(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
-                        let expr5_0 = constructor_output_xmm(ctx, expr4_0)?;
-                        return Some(expr5_0);
-                    }
-                    &Opcode::FminPseudo => {
-                        let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                        // Rule at src/isa/x64/lower.isle line 2236.
-                        let expr0_0 = constructor_put_in_xmm(ctx, pattern7_1)?;
-                        let expr1_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                        let expr2_0 = constructor_minsd(ctx, expr0_0, expr1_0)?;
-                        let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                        return Some(expr3_0);
-                    }
-                    &Opcode::Fmax => {
-                        let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                        // Rule at src/isa/x64/lower.isle line 2139.
-                        let expr0_0: Type = F64;
-                        let expr1_0: bool = false;
-                        let expr2_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                        let expr3_0 = constructor_put_in_xmm(ctx, pattern7_1)?;
-                        let expr4_0 =
-                            constructor_xmm_min_max_seq(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
-                        let expr5_0 = constructor_output_xmm(ctx, expr4_0)?;
-                        return Some(expr5_0);
-                    }
-                    &Opcode::FmaxPseudo => {
-                        let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                        // Rule at src/isa/x64/lower.isle line 2247.
-                        let expr0_0 = constructor_put_in_xmm(ctx, pattern7_1)?;
-                        let expr1_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                        let expr2_0 = constructor_maxsd(ctx, expr0_0, expr1_0)?;
-                        let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                        return Some(expr3_0);
-                    }
-                    _ => {}
-                }
-            }
-        }
-        if pattern2_0 == I8X16 {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            match &pattern4_0 {
-                &InstructionData::Binary {
-                    opcode: ref pattern5_0,
-                    args: ref pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Imin => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 1402.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_pminsb(ctx, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Umin => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 1424.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_pminub(ctx, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Imax => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 1391.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_pmaxsb(ctx, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Umax => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 1413.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_pmaxub(ctx, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Ishl => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 534.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = C::put_in_reg_mem_imm(ctx, pattern7_1);
-                            let expr2_0 = constructor_mov_rmi_to_xmm(ctx, &expr1_0)?;
-                            let expr3_0 = constructor_psllw(ctx, expr0_0, &expr2_0)?;
-                            let expr4_0 = C::put_in_reg_mem_imm(ctx, pattern7_1);
-                            let expr5_0 = constructor_ishl_i8x16_mask(ctx, &expr4_0)?;
-                            let expr6_0: Type = I8X16;
-                            let expr7_0 = ExtKind::None;
-                            let expr8_0 = constructor_x64_load(ctx, expr6_0, &expr5_0, &expr7_0)?;
-                            let expr9_0: Type = I8X16;
-                            let expr10_0 = RegMem::Reg { reg: expr8_0 };
-                            let expr11_0 = C::reg_mem_to_xmm_mem(ctx, &expr10_0);
-                            let expr12_0 = constructor_sse_and(ctx, expr9_0, expr3_0, &expr11_0)?;
-                            let expr13_0 = constructor_output_xmm(ctx, expr12_0)?;
-                            return Some(expr13_0);
-                        }
-                        &Opcode::Ushr => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 633.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = C::put_in_reg_mem_imm(ctx, pattern7_1);
-                            let expr2_0 = constructor_mov_rmi_to_xmm(ctx, &expr1_0)?;
-                            let expr3_0 = constructor_psrlw(ctx, expr0_0, &expr2_0)?;
-                            let expr4_0 = C::put_in_reg_mem_imm(ctx, pattern7_1);
-                            let expr5_0 = constructor_ushr_i8x16_mask(ctx, &expr4_0)?;
-                            let expr6_0: Type = I8X16;
-                            let expr7_0 = ExtKind::None;
-                            let expr8_0 = constructor_x64_load(ctx, expr6_0, &expr5_0, &expr7_0)?;
-                            let expr9_0: Type = I8X16;
-                            let expr10_0 = RegMem::Reg { reg: expr8_0 };
-                            let expr11_0 = C::reg_mem_to_xmm_mem(ctx, &expr10_0);
-                            let expr12_0 = constructor_sse_and(ctx, expr9_0, expr3_0, &expr11_0)?;
-                            let expr13_0 = constructor_output_xmm(ctx, expr12_0)?;
-                            return Some(expr13_0);
-                        }
-                        &Opcode::Sshr => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            let pattern8_0 = C::value_type(ctx, pattern7_1);
-                            // Rule at src/isa/x64/lower.isle line 749.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = C::xmm_to_xmm_mem(ctx, expr0_0);
-                            let expr2_0 = constructor_punpcklbw(ctx, expr0_0, &expr1_0)?;
-                            let expr3_0 = C::xmm_to_xmm_mem(ctx, expr0_0);
-                            let expr4_0 = constructor_punpckhbw(ctx, expr0_0, &expr3_0)?;
-                            let expr5_0 = C::put_in_reg_mem_imm(ctx, pattern7_1);
-                            let expr6_0 =
-                                constructor_sshr_i8x16_bigger_shift(ctx, pattern8_0, &expr5_0)?;
-                            let expr7_0 = constructor_psraw(ctx, expr2_0, &expr6_0)?;
-                            let expr8_0 = constructor_psraw(ctx, expr4_0, &expr6_0)?;
-                            let expr9_0 = C::xmm_to_xmm_mem(ctx, expr8_0);
-                            let expr10_0 = constructor_packsswb(ctx, expr7_0, &expr9_0)?;
-                            let expr11_0 = constructor_output_xmm(ctx, expr10_0)?;
-                            return Some(expr11_0);
-                        }
-                        _ => {}
-                    }
-                }
-                &InstructionData::Unary {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Ineg => {
-                            // Rule at src/isa/x64/lower.isle line 889.
-                            let expr0_0: Type = I8X16;
-                            let expr1_0: u64 = 0;
-                            let expr2_0 = constructor_imm(ctx, expr0_0, expr1_0)?;
-                            let expr3_0 = C::xmm_new(ctx, expr2_0);
-                            let expr4_0 = constructor_put_in_xmm_mem(ctx, pattern5_1)?;
-                            let expr5_0 = constructor_psubb(ctx, expr3_0, &expr4_0)?;
-                            let expr6_0 = constructor_output_xmm(ctx, expr5_0)?;
-                            return Some(expr6_0);
-                        }
-                        &Opcode::Iabs => {
-                            // Rule at src/isa/x64/lower.isle line 1210.
-                            let expr0_0 = constructor_put_in_xmm_mem(ctx, pattern5_1)?;
-                            let expr1_0 = constructor_pabsb(ctx, &expr0_0)?;
-                            let expr2_0 = constructor_output_xmm(ctx, expr1_0)?;
-                            return Some(expr2_0);
-                        }
-                        &Opcode::Popcnt => {
-                            // Rule at src/isa/x64/lower.isle line 1754.
-                            let expr0_0 = C::popcount_4bit_table(ctx);
-                            let expr1_0: Type = I8X16;
-                            let expr2_0 = C::popcount_low_mask(ctx);
-                            let expr3_0 = constructor_xmm_load_const(ctx, expr1_0, expr2_0)?;
-                            let expr4_0: Type = I8X16;
-                            let expr5_0 = constructor_put_in_xmm(ctx, pattern5_1)?;
-                            let expr6_0 = C::xmm_to_xmm_mem(ctx, expr3_0);
-                            let expr7_0 = constructor_sse_and(ctx, expr4_0, expr5_0, &expr6_0)?;
-                            let expr8_0 = constructor_put_in_xmm(ctx, pattern5_1)?;
-                            let expr9_0: u32 = 4;
-                            let expr10_0 = RegMemImm::Imm { simm32: expr9_0 };
-                            let expr11_0 = constructor_mov_rmi_to_xmm(ctx, &expr10_0)?;
-                            let expr12_0 = constructor_psrlw(ctx, expr8_0, &expr11_0)?;
-                            let expr13_0: Type = I8X16;
-                            let expr14_0 = C::xmm_to_xmm_mem(ctx, expr3_0);
-                            let expr15_0 = constructor_sse_and(ctx, expr13_0, expr12_0, &expr14_0)?;
-                            let expr16_0: Type = I8X16;
-                            let expr17_0 = C::popcount_4bit_table(ctx);
-                            let expr18_0 = constructor_xmm_load_const(ctx, expr16_0, expr17_0)?;
-                            let expr19_0 = C::xmm_to_xmm_mem(ctx, expr7_0);
-                            let expr20_0 = constructor_pshufb(ctx, expr18_0, &expr19_0)?;
-                            let expr21_0 = C::xmm_to_xmm_mem(ctx, expr15_0);
-                            let expr22_0 = constructor_pshufb(ctx, expr18_0, &expr21_0)?;
-                            let expr23_0 = C::xmm_to_xmm_mem(ctx, expr22_0);
-                            let expr24_0 = constructor_paddb(ctx, expr20_0, &expr23_0)?;
-                            let expr25_0 = constructor_output_xmm(ctx, expr24_0)?;
-                            return Some(expr25_0);
-                        }
-                        _ => {}
-                    }
-                }
-                _ => {}
-            }
-        }
-        if pattern2_0 == I16X8 {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            match &pattern4_0 {
-                &InstructionData::Binary {
-                    opcode: ref pattern5_0,
-                    args: ref pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Imin => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 1405.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_pminsw(ctx, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Umin => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 1427.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_pminuw(ctx, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Imax => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 1394.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_pmaxsw(ctx, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Umax => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 1416.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_pmaxuw(ctx, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Ishl => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 576.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = C::put_in_reg_mem_imm(ctx, pattern7_1);
-                            let expr2_0 = constructor_mov_rmi_to_xmm(ctx, &expr1_0)?;
-                            let expr3_0 = constructor_psllw(ctx, expr0_0, &expr2_0)?;
-                            let expr4_0 = constructor_output_xmm(ctx, expr3_0)?;
-                            return Some(expr4_0);
-                        }
-                        &Opcode::Ushr => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 678.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = C::put_in_reg_mem_imm(ctx, pattern7_1);
-                            let expr2_0 = constructor_mov_rmi_to_xmm(ctx, &expr1_0)?;
-                            let expr3_0 = constructor_psrlw(ctx, expr0_0, &expr2_0)?;
-                            let expr4_0 = constructor_output_xmm(ctx, expr3_0)?;
-                            return Some(expr4_0);
-                        }
-                        &Opcode::Sshr => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 776.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = C::put_in_reg_mem_imm(ctx, pattern7_1);
-                            let expr2_0 = constructor_mov_rmi_to_xmm(ctx, &expr1_0)?;
-                            let expr3_0 = constructor_psraw(ctx, expr0_0, &expr2_0)?;
-                            let expr4_0 = constructor_output_xmm(ctx, expr3_0)?;
-                            return Some(expr4_0);
-                        }
-                        _ => {}
-                    }
-                }
-                &InstructionData::Unary {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Ineg => {
-                            // Rule at src/isa/x64/lower.isle line 892.
-                            let expr0_0: Type = I16X8;
-                            let expr1_0: u64 = 0;
-                            let expr2_0 = constructor_imm(ctx, expr0_0, expr1_0)?;
-                            let expr3_0 = C::xmm_new(ctx, expr2_0);
-                            let expr4_0 = constructor_put_in_xmm_mem(ctx, pattern5_1)?;
-                            let expr5_0 = constructor_psubw(ctx, expr3_0, &expr4_0)?;
-                            let expr6_0 = constructor_output_xmm(ctx, expr5_0)?;
-                            return Some(expr6_0);
-                        }
-                        &Opcode::Iabs => {
-                            // Rule at src/isa/x64/lower.isle line 1213.
-                            let expr0_0 = constructor_put_in_xmm_mem(ctx, pattern5_1)?;
-                            let expr1_0 = constructor_pabsw(ctx, &expr0_0)?;
-                            let expr2_0 = constructor_output_xmm(ctx, expr1_0)?;
-                            return Some(expr2_0);
-                        }
-                        _ => {}
-                    }
-                }
-                _ => {}
-            }
-        }
-        if pattern2_0 == I32X4 {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            match &pattern4_0 {
-                &InstructionData::Binary {
-                    opcode: ref pattern5_0,
-                    args: ref pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Imin => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 1408.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_pminsd(ctx, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Umin => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 1430.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_pminud(ctx, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Imax => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 1397.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_pmaxsd(ctx, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Umax => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 1419.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_pmaxud(ctx, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Ishl => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 579.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = C::put_in_reg_mem_imm(ctx, pattern7_1);
-                            let expr2_0 = constructor_mov_rmi_to_xmm(ctx, &expr1_0)?;
-                            let expr3_0 = constructor_pslld(ctx, expr0_0, &expr2_0)?;
-                            let expr4_0 = constructor_output_xmm(ctx, expr3_0)?;
-                            return Some(expr4_0);
-                        }
-                        &Opcode::Ushr => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 681.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = C::put_in_reg_mem_imm(ctx, pattern7_1);
-                            let expr2_0 = constructor_mov_rmi_to_xmm(ctx, &expr1_0)?;
-                            let expr3_0 = constructor_psrld(ctx, expr0_0, &expr2_0)?;
-                            let expr4_0 = constructor_output_xmm(ctx, expr3_0)?;
-                            return Some(expr4_0);
-                        }
-                        &Opcode::Sshr => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 779.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = C::put_in_reg_mem_imm(ctx, pattern7_1);
-                            let expr2_0 = constructor_mov_rmi_to_xmm(ctx, &expr1_0)?;
-                            let expr3_0 = constructor_psrad(ctx, expr0_0, &expr2_0)?;
-                            let expr4_0 = constructor_output_xmm(ctx, expr3_0)?;
-                            return Some(expr4_0);
-                        }
-                        &Opcode::WideningPairwiseDotProductS => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 2011.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_pmaddwd(ctx, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        _ => {}
-                    }
-                }
-                &InstructionData::Unary {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Ineg => {
-                            // Rule at src/isa/x64/lower.isle line 895.
-                            let expr0_0: Type = I32X4;
-                            let expr1_0: u64 = 0;
-                            let expr2_0 = constructor_imm(ctx, expr0_0, expr1_0)?;
-                            let expr3_0 = C::xmm_new(ctx, expr2_0);
-                            let expr4_0 = constructor_put_in_xmm_mem(ctx, pattern5_1)?;
-                            let expr5_0 = constructor_psubd(ctx, expr3_0, &expr4_0)?;
-                            let expr6_0 = constructor_output_xmm(ctx, expr5_0)?;
-                            return Some(expr6_0);
-                        }
-                        &Opcode::Iabs => {
-                            // Rule at src/isa/x64/lower.isle line 1216.
-                            let expr0_0 = constructor_put_in_xmm_mem(ctx, pattern5_1)?;
-                            let expr1_0 = constructor_pabsd(ctx, &expr0_0)?;
-                            let expr2_0 = constructor_output_xmm(ctx, expr1_0)?;
-                            return Some(expr2_0);
-                        }
-                        _ => {}
-                    }
-                }
-                _ => {}
-            }
-        }
-        if pattern2_0 == I64X2 {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            match &pattern4_0 {
-                &InstructionData::Binary {
-                    opcode: ref pattern5_0,
-                    args: ref pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Ishl => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 582.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = C::put_in_reg_mem_imm(ctx, pattern7_1);
-                            let expr2_0 = constructor_mov_rmi_to_xmm(ctx, &expr1_0)?;
-                            let expr3_0 = constructor_psllq(ctx, expr0_0, &expr2_0)?;
-                            let expr4_0 = constructor_output_xmm(ctx, expr3_0)?;
-                            return Some(expr4_0);
-                        }
-                        &Opcode::Ushr => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 684.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = C::put_in_reg_mem_imm(ctx, pattern7_1);
-                            let expr2_0 = constructor_mov_rmi_to_xmm(ctx, &expr1_0)?;
-                            let expr3_0 = constructor_psrlq(ctx, expr0_0, &expr2_0)?;
-                            let expr4_0 = constructor_output_xmm(ctx, expr3_0)?;
-                            return Some(expr4_0);
-                        }
-                        &Opcode::Sshr => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 790.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0: Type = I64;
-                            let expr2_0: u8 = 0;
-                            let expr3_0 = constructor_pextrd(ctx, expr1_0, expr0_0, expr2_0)?;
-                            let expr4_0: Type = I64;
-                            let expr5_0: u8 = 1;
-                            let expr6_0 = constructor_pextrd(ctx, expr4_0, expr0_0, expr5_0)?;
-                            let expr7_0: Type = I64;
-                            let expr8_0 = C::put_masked_in_imm8_gpr(ctx, pattern7_1, expr7_0);
-                            let expr9_0: Type = I64;
-                            let expr10_0 = constructor_sar(ctx, expr9_0, expr3_0, &expr8_0)?;
-                            let expr11_0: Type = I64;
-                            let expr12_0 = constructor_sar(ctx, expr11_0, expr6_0, &expr8_0)?;
-                            let expr13_0 = C::gpr_to_gpr_mem(ctx, expr10_0);
-                            let expr14_0 = C::gpr_to_gpr_mem(ctx, expr12_0);
-                            let expr15_0 =
-                                constructor_make_i64x2_from_lanes(ctx, &expr13_0, &expr14_0)?;
-                            let expr16_0 = constructor_output_xmm(ctx, expr15_0)?;
-                            return Some(expr16_0);
-                        }
-                        _ => {}
-                    }
-                }
-                &InstructionData::Unary {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Ineg => {
-                            // Rule at src/isa/x64/lower.isle line 898.
-                            let expr0_0: Type = I64X2;
-                            let expr1_0: u64 = 0;
-                            let expr2_0 = constructor_imm(ctx, expr0_0, expr1_0)?;
-                            let expr3_0 = C::xmm_new(ctx, expr2_0);
-                            let expr4_0 = constructor_put_in_xmm_mem(ctx, pattern5_1)?;
-                            let expr5_0 = constructor_psubq(ctx, expr3_0, &expr4_0)?;
-                            let expr6_0 = constructor_output_xmm(ctx, expr5_0)?;
-                            return Some(expr6_0);
-                        }
-                        &Opcode::Iabs => {
-                            // Rule at src/isa/x64/lower.isle line 1230.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern5_1)?;
-                            let expr1_0: Type = I64X2;
-                            let expr2_0: u64 = 0;
-                            let expr3_0 = constructor_imm(ctx, expr1_0, expr2_0)?;
-                            let expr4_0 = C::xmm_new(ctx, expr3_0);
-                            let expr5_0 = C::xmm_to_xmm_mem(ctx, expr0_0);
-                            let expr6_0 = constructor_psubq(ctx, expr4_0, &expr5_0)?;
-                            let expr7_0 = C::xmm_to_xmm_mem(ctx, expr0_0);
-                            let expr8_0 = constructor_blendvpd(ctx, expr6_0, &expr7_0, expr6_0)?;
-                            let expr9_0 = constructor_output_xmm(ctx, expr8_0)?;
-                            return Some(expr9_0);
-                        }
-                        _ => {}
-                    }
-                }
-                _ => {}
-            }
-        }
-        if pattern2_0 == F32X4 {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            match &pattern4_0 {
-                &InstructionData::Binary {
-                    opcode: ref pattern5_0,
-                    args: ref pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Fadd => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 2025.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_addps(ctx, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Fsub => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 2036.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_subps(ctx, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Fmul => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 2047.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_mulps(ctx, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Fdiv => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 2058.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_divps(ctx, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Fmin => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 2082.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_xmm(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_minps(ctx, expr0_0, expr1_0)?;
-                            let expr3_0 = constructor_put_in_xmm(ctx, pattern7_1)?;
-                            let expr4_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr5_0 = constructor_minps(ctx, expr3_0, expr4_0)?;
-                            let expr6_0 = C::xmm_to_xmm_mem(ctx, expr5_0);
-                            let expr7_0 = constructor_orps(ctx, expr2_0, &expr6_0)?;
-                            let expr8_0 = C::xmm_to_xmm_mem(ctx, expr5_0);
-                            let expr9_0 = FcmpImm::Unordered;
-                            let expr10_0 = constructor_cmpps(ctx, expr7_0, &expr8_0, &expr9_0)?;
-                            let expr11_0 = C::xmm_to_xmm_mem(ctx, expr10_0);
-                            let expr12_0 = constructor_orps(ctx, expr7_0, &expr11_0)?;
-                            let expr13_0: u32 = 10;
-                            let expr14_0 = RegMemImm::Imm { simm32: expr13_0 };
-                            let expr15_0 = constructor_mov_rmi_to_xmm(ctx, &expr14_0)?;
-                            let expr16_0 = constructor_psrld(ctx, expr10_0, &expr15_0)?;
-                            let expr17_0 = C::xmm_to_xmm_mem(ctx, expr12_0);
-                            let expr18_0 = constructor_andnps(ctx, expr16_0, &expr17_0)?;
-                            let expr19_0 = constructor_output_xmm(ctx, expr18_0)?;
-                            return Some(expr19_0);
-                        }
-                        &Opcode::FminPseudo => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 2238.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_1)?;
-                            let expr1_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr2_0 = constructor_minps(ctx, expr0_0, expr1_0)?;
-                            let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Fmax => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 2145.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_xmm(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_maxps(ctx, expr0_0, expr1_0)?;
-                            let expr3_0 = constructor_put_in_xmm(ctx, pattern7_1)?;
-                            let expr4_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr5_0 = constructor_maxps(ctx, expr3_0, expr4_0)?;
-                            let expr6_0 = C::xmm_to_xmm_mem(ctx, expr5_0);
-                            let expr7_0 = constructor_xorps(ctx, expr2_0, &expr6_0)?;
-                            let expr8_0 = C::xmm_to_xmm_mem(ctx, expr7_0);
-                            let expr9_0 = constructor_orps(ctx, expr2_0, &expr8_0)?;
-                            let expr10_0 = C::xmm_to_xmm_mem(ctx, expr7_0);
-                            let expr11_0 = constructor_subps(ctx, expr9_0, &expr10_0)?;
-                            let expr12_0 = C::xmm_to_xmm_mem(ctx, expr9_0);
-                            let expr13_0 = FcmpImm::Unordered;
-                            let expr14_0 = constructor_cmpps(ctx, expr9_0, &expr12_0, &expr13_0)?;
-                            let expr15_0: u32 = 10;
-                            let expr16_0 = RegMemImm::Imm { simm32: expr15_0 };
-                            let expr17_0 = constructor_mov_rmi_to_xmm(ctx, &expr16_0)?;
-                            let expr18_0 = constructor_psrld(ctx, expr14_0, &expr17_0)?;
-                            let expr19_0 = C::xmm_to_xmm_mem(ctx, expr11_0);
-                            let expr20_0 = constructor_andnps(ctx, expr18_0, &expr19_0)?;
-                            let expr21_0 = constructor_output_xmm(ctx, expr20_0)?;
-                            return Some(expr21_0);
-                        }
-                        &Opcode::FmaxPseudo => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 2249.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_1)?;
-                            let expr1_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr2_0 = constructor_maxps(ctx, expr0_0, expr1_0)?;
-                            let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        _ => {}
-                    }
-                }
-                &InstructionData::Unary {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                } => {
-                    if let &Opcode::Fabs = pattern5_0 {
-                        // Rule at src/isa/x64/lower.isle line 1238.
-                        let expr0_0 = constructor_put_in_xmm(ctx, pattern5_1)?;
-                        let expr1_0: Type = F32X4;
-                        let expr2_0 = constructor_vector_all_ones(ctx, expr1_0)?;
-                        let expr3_0: u32 = 1;
-                        let expr4_0 = RegMemImm::Imm { simm32: expr3_0 };
-                        let expr5_0 = constructor_mov_rmi_to_xmm(ctx, &expr4_0)?;
-                        let expr6_0 = constructor_psrld(ctx, expr2_0, &expr5_0)?;
-                        let expr7_0 = C::xmm_to_xmm_mem(ctx, expr6_0);
-                        let expr8_0 = constructor_andps(ctx, expr0_0, &expr7_0)?;
-                        let expr9_0 = constructor_output_xmm(ctx, expr8_0)?;
-                        return Some(expr9_0);
-                    }
-                }
-                _ => {}
-            }
-        }
-        if pattern2_0 == F64X2 {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            match &pattern4_0 {
-                &InstructionData::Binary {
-                    opcode: ref pattern5_0,
-                    args: ref pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Fadd => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 2027.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_addpd(ctx, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Fsub => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 2038.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_subpd(ctx, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Fmul => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 2049.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_mulpd(ctx, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Fdiv => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 2060.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_divpd(ctx, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Fmin => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 2125.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_xmm(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_minpd(ctx, expr0_0, expr1_0)?;
-                            let expr3_0 = constructor_put_in_xmm(ctx, pattern7_1)?;
-                            let expr4_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr5_0 = constructor_minpd(ctx, expr3_0, expr4_0)?;
-                            let expr6_0 = C::xmm_to_xmm_mem(ctx, expr5_0);
-                            let expr7_0 = constructor_orpd(ctx, expr2_0, &expr6_0)?;
-                            let expr8_0 = C::xmm_to_xmm_mem(ctx, expr5_0);
-                            let expr9_0 = FcmpImm::Unordered;
-                            let expr10_0 = constructor_cmppd(ctx, expr2_0, &expr8_0, &expr9_0)?;
-                            let expr11_0 = C::xmm_to_xmm_mem(ctx, expr10_0);
-                            let expr12_0 = constructor_orpd(ctx, expr7_0, &expr11_0)?;
-                            let expr13_0: u32 = 13;
-                            let expr14_0 = RegMemImm::Imm { simm32: expr13_0 };
-                            let expr15_0 = constructor_mov_rmi_to_xmm(ctx, &expr14_0)?;
-                            let expr16_0 = constructor_psrlq(ctx, expr10_0, &expr15_0)?;
-                            let expr17_0 = C::xmm_to_xmm_mem(ctx, expr12_0);
-                            let expr18_0 = constructor_andnpd(ctx, expr16_0, &expr17_0)?;
-                            let expr19_0 = constructor_output_xmm(ctx, expr18_0)?;
-                            return Some(expr19_0);
-                        }
-                        &Opcode::FminPseudo => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 2240.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_1)?;
-                            let expr1_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr2_0 = constructor_minpd(ctx, expr0_0, expr1_0)?;
-                            let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Fmax => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 2188.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_xmm(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_maxpd(ctx, expr0_0, expr1_0)?;
-                            let expr3_0 = constructor_put_in_xmm(ctx, pattern7_1)?;
-                            let expr4_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr5_0 = constructor_maxpd(ctx, expr3_0, expr4_0)?;
-                            let expr6_0 = C::xmm_to_xmm_mem(ctx, expr5_0);
-                            let expr7_0 = constructor_xorpd(ctx, expr2_0, &expr6_0)?;
-                            let expr8_0 = C::xmm_to_xmm_mem(ctx, expr7_0);
-                            let expr9_0 = constructor_orpd(ctx, expr2_0, &expr8_0)?;
-                            let expr10_0 = C::xmm_to_xmm_mem(ctx, expr7_0);
-                            let expr11_0 = constructor_subpd(ctx, expr9_0, &expr10_0)?;
-                            let expr12_0 = C::xmm_to_xmm_mem(ctx, expr9_0);
-                            let expr13_0 = FcmpImm::Unordered;
-                            let expr14_0 = constructor_cmppd(ctx, expr9_0, &expr12_0, &expr13_0)?;
-                            let expr15_0: u32 = 13;
-                            let expr16_0 = RegMemImm::Imm { simm32: expr15_0 };
-                            let expr17_0 = constructor_mov_rmi_to_xmm(ctx, &expr16_0)?;
-                            let expr18_0 = constructor_psrlq(ctx, expr14_0, &expr17_0)?;
-                            let expr19_0 = C::xmm_to_xmm_mem(ctx, expr11_0);
-                            let expr20_0 = constructor_andnpd(ctx, expr18_0, &expr19_0)?;
-                            let expr21_0 = constructor_output_xmm(ctx, expr20_0)?;
-                            return Some(expr21_0);
-                        }
-                        &Opcode::FmaxPseudo => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 2251.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_1)?;
-                            let expr1_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr2_0 = constructor_maxpd(ctx, expr0_0, expr1_0)?;
-                            let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        _ => {}
-                    }
-                }
-                &InstructionData::Unary {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                } => {
-                    if let &Opcode::Fabs = pattern5_0 {
-                        // Rule at src/isa/x64/lower.isle line 1244.
-                        let expr0_0 = constructor_put_in_xmm(ctx, pattern5_1)?;
-                        let expr1_0: Type = F64X2;
-                        let expr2_0 = constructor_vector_all_ones(ctx, expr1_0)?;
-                        let expr3_0: u32 = 1;
-                        let expr4_0 = RegMemImm::Imm { simm32: expr3_0 };
-                        let expr5_0 = constructor_mov_rmi_to_xmm(ctx, &expr4_0)?;
-                        let expr6_0 = constructor_psrlq(ctx, expr2_0, &expr5_0)?;
-                        let expr7_0 = C::xmm_to_xmm_mem(ctx, expr6_0);
-                        let expr8_0 = constructor_andpd(ctx, expr0_0, &expr7_0)?;
-                        let expr9_0 = constructor_output_xmm(ctx, expr8_0)?;
-                        return Some(expr9_0);
-                    }
-                }
-                _ => {}
-            }
-        }
-        let pattern3_0 = C::inst_data(ctx, pattern0_0);
-        match &pattern3_0 {
-            &InstructionData::NullAry {
-                opcode: ref pattern4_0,
-            } => {
-                if let &Opcode::Null = pattern4_0 {
-                    // Rule at src/isa/x64/lower.isle line 56.
-                    let expr0_0: u64 = 0;
-                    let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
-                    let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                    return Some(expr2_0);
-                }
-            }
-            &InstructionData::Binary {
-                opcode: ref pattern4_0,
-                args: ref pattern4_1,
-            } => {
-                if let &Opcode::BandNot = pattern4_0 {
-                    let (pattern6_0, pattern6_1) = C::unpack_value_array_2(ctx, pattern4_1);
-                    // Rule at src/isa/x64/lower.isle line 1205.
-                    let expr0_0 = constructor_put_in_xmm(ctx, pattern6_1)?;
-                    let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern6_0)?;
-                    let expr2_0 = constructor_sse_and_not(ctx, pattern2_0, expr0_0, &expr1_0)?;
-                    let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                    return Some(expr3_0);
-                }
-            }
-            &InstructionData::Ternary {
-                opcode: ref pattern4_0,
-                args: ref pattern4_1,
-            } => {
-                if let &Opcode::Select = pattern4_0 {
-                    let (pattern6_0, pattern6_1, pattern6_2) =
-                        C::unpack_value_array_3(ctx, pattern4_1);
-                    if let Some(pattern7_0) = C::def_inst(ctx, pattern6_0) {
-                        let pattern8_0 = C::inst_data(ctx, pattern7_0);
-                        if let &InstructionData::FloatCompare {
-                            opcode: ref pattern9_0,
-                            args: ref pattern9_1,
-                            cond: ref pattern9_2,
-                        } = &pattern8_0
-                        {
-                            if let &Opcode::Fcmp = pattern9_0 {
-                                let (pattern11_0, pattern11_1) =
-                                    C::unpack_value_array_2(ctx, pattern9_1);
-                                match pattern9_2 {
-                                    &FloatCC::Equal => {
-                                        // Rule at src/isa/x64/lower.isle line 1524.
-                                        let expr0_0 =
-                                            constructor_fpcmp(ctx, pattern11_0, pattern11_1)?;
-                                        let expr1_0 = CC::NZ;
-                                        let expr2_0 = CC::P;
-                                        let expr3_0 = constructor_cmove_or_from_values(
-                                            ctx, pattern2_0, &expr1_0, &expr2_0, pattern6_2,
-                                            pattern6_1,
-                                        )?;
-                                        let expr4_0 =
-                                            constructor_with_flags(ctx, &expr0_0, &expr3_0)?;
-                                        let expr5_0 = C::output(ctx, expr4_0);
-                                        return Some(expr5_0);
-                                    }
-                                    &FloatCC::GreaterThan => {
-                                        // Rule at src/isa/x64/lower.isle line 1476.
-                                        let expr0_0 =
-                                            constructor_fpcmp(ctx, pattern11_1, pattern11_0)?;
-                                        let expr1_0 = CC::NBE;
-                                        let expr2_0 = constructor_cmove_from_values(
-                                            ctx, pattern2_0, &expr1_0, pattern6_1, pattern6_2,
-                                        )?;
-                                        let expr3_0 =
-                                            constructor_with_flags(ctx, &expr0_0, &expr2_0)?;
-                                        let expr4_0 = C::output(ctx, expr3_0);
-                                        return Some(expr4_0);
-                                    }
-                                    &FloatCC::GreaterThanOrEqual => {
-                                        // Rule at src/isa/x64/lower.isle line 1479.
-                                        let expr0_0 =
-                                            constructor_fpcmp(ctx, pattern11_1, pattern11_0)?;
-                                        let expr1_0 = CC::NB;
-                                        let expr2_0 = constructor_cmove_from_values(
-                                            ctx, pattern2_0, &expr1_0, pattern6_1, pattern6_2,
-                                        )?;
-                                        let expr3_0 =
-                                            constructor_with_flags(ctx, &expr0_0, &expr2_0)?;
-                                        let expr4_0 = C::output(ctx, expr3_0);
-                                        return Some(expr4_0);
-                                    }
-                                    &FloatCC::LessThan => {
-                                        // Rule at src/isa/x64/lower.isle line 1499.
-                                        let expr0_0 =
-                                            constructor_fpcmp(ctx, pattern11_0, pattern11_1)?;
-                                        let expr1_0 = CC::NBE;
-                                        let expr2_0 = constructor_cmove_from_values(
-                                            ctx, pattern2_0, &expr1_0, pattern6_1, pattern6_2,
-                                        )?;
-                                        let expr3_0 =
-                                            constructor_with_flags(ctx, &expr0_0, &expr2_0)?;
-                                        let expr4_0 = C::output(ctx, expr3_0);
-                                        return Some(expr4_0);
-                                    }
-                                    &FloatCC::LessThanOrEqual => {
-                                        // Rule at src/isa/x64/lower.isle line 1502.
-                                        let expr0_0 =
-                                            constructor_fpcmp(ctx, pattern11_0, pattern11_1)?;
-                                        let expr1_0 = CC::NB;
-                                        let expr2_0 = constructor_cmove_from_values(
-                                            ctx, pattern2_0, &expr1_0, pattern6_1, pattern6_2,
-                                        )?;
-                                        let expr3_0 =
-                                            constructor_with_flags(ctx, &expr0_0, &expr2_0)?;
-                                        let expr4_0 = C::output(ctx, expr3_0);
-                                        return Some(expr4_0);
-                                    }
-                                    &FloatCC::NotEqual => {
-                                        // Rule at src/isa/x64/lower.isle line 1527.
-                                        let expr0_0 =
-                                            constructor_fpcmp(ctx, pattern11_0, pattern11_1)?;
-                                        let expr1_0 = CC::NZ;
-                                        let expr2_0 = CC::P;
-                                        let expr3_0 = constructor_cmove_or_from_values(
-                                            ctx, pattern2_0, &expr1_0, &expr2_0, pattern6_1,
-                                            pattern6_2,
-                                        )?;
-                                        let expr4_0 =
-                                            constructor_with_flags(ctx, &expr0_0, &expr3_0)?;
-                                        let expr5_0 = C::output(ctx, expr4_0);
-                                        return Some(expr5_0);
-                                    }
-                                    &FloatCC::Ordered => {
-                                        // Rule at src/isa/x64/lower.isle line 1470.
-                                        let expr0_0 =
-                                            constructor_fpcmp(ctx, pattern11_1, pattern11_0)?;
-                                        let expr1_0 = CC::NP;
-                                        let expr2_0 = constructor_cmove_from_values(
-                                            ctx, pattern2_0, &expr1_0, pattern6_1, pattern6_2,
-                                        )?;
-                                        let expr3_0 =
-                                            constructor_with_flags(ctx, &expr0_0, &expr2_0)?;
-                                        let expr4_0 = C::output(ctx, expr3_0);
-                                        return Some(expr4_0);
-                                    }
-                                    &FloatCC::Unordered => {
-                                        // Rule at src/isa/x64/lower.isle line 1473.
-                                        let expr0_0 =
-                                            constructor_fpcmp(ctx, pattern11_1, pattern11_0)?;
-                                        let expr1_0 = CC::P;
-                                        let expr2_0 = constructor_cmove_from_values(
-                                            ctx, pattern2_0, &expr1_0, pattern6_1, pattern6_2,
-                                        )?;
-                                        let expr3_0 =
-                                            constructor_with_flags(ctx, &expr0_0, &expr2_0)?;
-                                        let expr4_0 = C::output(ctx, expr3_0);
-                                        return Some(expr4_0);
-                                    }
-                                    &FloatCC::UnorderedOrGreaterThan => {
-                                        // Rule at src/isa/x64/lower.isle line 1505.
-                                        let expr0_0 =
-                                            constructor_fpcmp(ctx, pattern11_0, pattern11_1)?;
-                                        let expr1_0 = CC::B;
-                                        let expr2_0 = constructor_cmove_from_values(
-                                            ctx, pattern2_0, &expr1_0, pattern6_1, pattern6_2,
-                                        )?;
-                                        let expr3_0 =
-                                            constructor_with_flags(ctx, &expr0_0, &expr2_0)?;
-                                        let expr4_0 = C::output(ctx, expr3_0);
-                                        return Some(expr4_0);
-                                    }
-                                    &FloatCC::UnorderedOrGreaterThanOrEqual => {
-                                        // Rule at src/isa/x64/lower.isle line 1508.
-                                        let expr0_0 =
-                                            constructor_fpcmp(ctx, pattern11_0, pattern11_1)?;
-                                        let expr1_0 = CC::BE;
-                                        let expr2_0 = constructor_cmove_from_values(
-                                            ctx, pattern2_0, &expr1_0, pattern6_1, pattern6_2,
-                                        )?;
-                                        let expr3_0 =
-                                            constructor_with_flags(ctx, &expr0_0, &expr2_0)?;
-                                        let expr4_0 = C::output(ctx, expr3_0);
-                                        return Some(expr4_0);
-                                    }
-                                    &FloatCC::UnorderedOrLessThan => {
-                                        // Rule at src/isa/x64/lower.isle line 1482.
-                                        let expr0_0 =
-                                            constructor_fpcmp(ctx, pattern11_1, pattern11_0)?;
-                                        let expr1_0 = CC::B;
-                                        let expr2_0 = constructor_cmove_from_values(
-                                            ctx, pattern2_0, &expr1_0, pattern6_1, pattern6_2,
-                                        )?;
-                                        let expr3_0 =
-                                            constructor_with_flags(ctx, &expr0_0, &expr2_0)?;
-                                        let expr4_0 = C::output(ctx, expr3_0);
-                                        return Some(expr4_0);
-                                    }
-                                    &FloatCC::UnorderedOrLessThanOrEqual => {
-                                        // Rule at src/isa/x64/lower.isle line 1485.
-                                        let expr0_0 =
-                                            constructor_fpcmp(ctx, pattern11_1, pattern11_0)?;
-                                        let expr1_0 = CC::BE;
-                                        let expr2_0 = constructor_cmove_from_values(
-                                            ctx, pattern2_0, &expr1_0, pattern6_1, pattern6_2,
-                                        )?;
-                                        let expr3_0 =
-                                            constructor_with_flags(ctx, &expr0_0, &expr2_0)?;
-                                        let expr4_0 = C::output(ctx, expr3_0);
-                                        return Some(expr4_0);
-                                    }
-                                    _ => {}
-                                }
-                            }
-                        }
-                    }
-                }
-            }
-            &InstructionData::Unary {
-                opcode: ref pattern4_0,
-                arg: pattern4_1,
-            } => {
-                match pattern4_0 {
-                    &Opcode::Breduce => {
-                        let pattern6_0 = C::value_type(ctx, pattern4_1);
-                        if pattern6_0 == pattern2_0 {
-                            // Rule at src/isa/x64/lower.isle line 1984.
-                            let expr0_0 = constructor_output_value(ctx, pattern4_1)?;
-                            return Some(expr0_0);
-                        }
-                    }
-                    &Opcode::Bextend => {
-                        let pattern6_0 = C::value_type(ctx, pattern4_1);
-                        // Rule at src/isa/x64/lower.isle line 1965.
-                        let expr0_0 =
-                            constructor_generic_sextend(ctx, pattern4_1, pattern6_0, pattern2_0)?;
-                        return Some(expr0_0);
-                    }
-                    &Opcode::Ireduce => {
-                        let pattern6_0 = C::value_type(ctx, pattern4_1);
-                        if pattern6_0 == pattern2_0 {
-                            // Rule at src/isa/x64/lower.isle line 1973.
-                            let expr0_0 = constructor_output_value(ctx, pattern4_1)?;
-                            return Some(expr0_0);
-                        }
-                    }
-                    &Opcode::Uextend => {
-                        let pattern6_0 = C::value_type(ctx, pattern4_1);
-                        if pattern6_0 == pattern2_0 {
-                            // Rule at src/isa/x64/lower.isle line 1866.
-                            let expr0_0 = constructor_output_value(ctx, pattern4_1)?;
-                            return Some(expr0_0);
-                        }
-                    }
-                    &Opcode::Sextend => {
-                        let pattern6_0 = C::value_type(ctx, pattern4_1);
-                        // Rule at src/isa/x64/lower.isle line 1959.
-                        let expr0_0 =
-                            constructor_generic_sextend(ctx, pattern4_1, pattern6_0, pattern2_0)?;
-                        return Some(expr0_0);
-                    }
-                    _ => {}
-                }
-            }
-            _ => {}
-        }
-        if let Some(()) = C::avx512vl_enabled(ctx, pattern2_0) {
-            if let Some(()) = C::avx512dq_enabled(ctx, pattern2_0) {
-                if let Some((pattern5_0, pattern5_1)) = C::multi_lane(ctx, pattern2_0) {
-                    if pattern5_0 == 64 {
-                        if pattern5_1 == 2 {
-                            let pattern8_0 = C::inst_data(ctx, pattern0_0);
-                            if let &InstructionData::Binary {
-                                opcode: ref pattern9_0,
-                                args: ref pattern9_1,
-                            } = &pattern8_0
-                            {
-                                if let &Opcode::Imul = pattern9_0 {
-                                    let (pattern11_0, pattern11_1) =
-                                        C::unpack_value_array_2(ctx, pattern9_1);
-                                    // Rule at src/isa/x64/lower.isle line 992.
-                                    let expr0_0 = constructor_put_in_xmm_mem(ctx, pattern11_0)?;
-                                    let expr1_0 = constructor_put_in_xmm(ctx, pattern11_1)?;
-                                    let expr2_0 = constructor_vpmullq(ctx, &expr0_0, expr1_0)?;
-                                    let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                                    return Some(expr3_0);
-                                }
-                            }
-                        }
-                    }
-                }
-            }
-            if let Some(()) = C::avx512f_enabled(ctx, pattern2_0) {
-                if pattern2_0 == I64X2 {
-                    let pattern6_0 = C::inst_data(ctx, pattern0_0);
-                    if let &InstructionData::Unary {
-                        opcode: ref pattern7_0,
-                        arg: pattern7_1,
-                    } = &pattern6_0
-                    {
-                        if let &Opcode::Iabs = pattern7_0 {
-                            // Rule at src/isa/x64/lower.isle line 1220.
-                            let expr0_0 = constructor_put_in_xmm_mem(ctx, pattern7_1)?;
-                            let expr1_0 = constructor_vpabsq(ctx, &expr0_0)?;
-                            let expr2_0 = constructor_output_xmm(ctx, expr1_0)?;
-                            return Some(expr2_0);
-                        }
-                    }
-                }
-            }
-        }
-        if let Some((pattern3_0, pattern3_1)) = C::multi_lane(ctx, pattern2_0) {
-            if pattern3_0 == 8 {
-                if pattern3_1 == 16 {
-                    let pattern6_0 = C::inst_data(ctx, pattern0_0);
-                    if let &InstructionData::Binary {
-                        opcode: ref pattern7_0,
-                        args: ref pattern7_1,
-                    } = &pattern6_0
-                    {
-                        match pattern7_0 {
-                            &Opcode::AvgRound => {
-                                let (pattern9_0, pattern9_1) =
-                                    C::unpack_value_array_2(ctx, pattern7_1);
-                                // Rule at src/isa/x64/lower.isle line 903.
-                                let expr0_0 = constructor_put_in_xmm(ctx, pattern9_0)?;
-                                let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern9_1)?;
-                                let expr2_0 = constructor_pavgb(ctx, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            &Opcode::UaddSat => {
-                                let (pattern9_0, pattern9_1) =
-                                    C::unpack_value_array_2(ctx, pattern7_1);
-                                // Rule at src/isa/x64/lower.isle line 136.
-                                let expr0_0 = constructor_put_in_xmm(ctx, pattern9_0)?;
-                                let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern9_1)?;
-                                let expr2_0 = constructor_paddusb(ctx, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            &Opcode::SaddSat => {
-                                let (pattern9_0, pattern9_1) =
-                                    C::unpack_value_array_2(ctx, pattern7_1);
-                                // Rule at src/isa/x64/lower.isle line 126.
-                                let expr0_0 = constructor_put_in_xmm(ctx, pattern9_0)?;
-                                let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern9_1)?;
-                                let expr2_0 = constructor_paddsb(ctx, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            &Opcode::UsubSat => {
-                                let (pattern9_0, pattern9_1) =
-                                    C::unpack_value_array_2(ctx, pattern7_1);
-                                // Rule at src/isa/x64/lower.isle line 282.
-                                let expr0_0 = constructor_put_in_xmm(ctx, pattern9_0)?;
-                                let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern9_1)?;
-                                let expr2_0 = constructor_psubusb(ctx, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            &Opcode::SsubSat => {
-                                let (pattern9_0, pattern9_1) =
-                                    C::unpack_value_array_2(ctx, pattern7_1);
-                                // Rule at src/isa/x64/lower.isle line 272.
-                                let expr0_0 = constructor_put_in_xmm(ctx, pattern9_0)?;
-                                let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern9_1)?;
-                                let expr2_0 = constructor_psubsb(ctx, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            &Opcode::Iadd => {
-                                let (pattern9_0, pattern9_1) =
-                                    C::unpack_value_array_2(ctx, pattern7_1);
-                                // Rule at src/isa/x64/lower.isle line 94.
-                                let expr0_0 = constructor_put_in_xmm(ctx, pattern9_0)?;
-                                let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern9_1)?;
-                                let expr2_0 = constructor_paddb(ctx, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            &Opcode::Isub => {
-                                let (pattern9_0, pattern9_1) =
-                                    C::unpack_value_array_2(ctx, pattern7_1);
-                                // Rule at src/isa/x64/lower.isle line 240.
-                                let expr0_0 = constructor_put_in_xmm(ctx, pattern9_0)?;
-                                let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern9_1)?;
-                                let expr2_0 = constructor_psubb(ctx, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            _ => {}
-                        }
-                    }
-                }
-            }
-            if pattern3_0 == 16 {
-                if pattern3_1 == 8 {
-                    let pattern6_0 = C::inst_data(ctx, pattern0_0);
-                    if let &InstructionData::Binary {
-                        opcode: ref pattern7_0,
-                        args: ref pattern7_1,
-                    } = &pattern6_0
-                    {
-                        match pattern7_0 {
-                            &Opcode::AvgRound => {
-                                let (pattern9_0, pattern9_1) =
-                                    C::unpack_value_array_2(ctx, pattern7_1);
-                                // Rule at src/isa/x64/lower.isle line 907.
-                                let expr0_0 = constructor_put_in_xmm(ctx, pattern9_0)?;
-                                let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern9_1)?;
-                                let expr2_0 = constructor_pavgw(ctx, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            &Opcode::UaddSat => {
-                                let (pattern9_0, pattern9_1) =
-                                    C::unpack_value_array_2(ctx, pattern7_1);
-                                // Rule at src/isa/x64/lower.isle line 140.
-                                let expr0_0 = constructor_put_in_xmm(ctx, pattern9_0)?;
-                                let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern9_1)?;
-                                let expr2_0 = constructor_paddusw(ctx, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            &Opcode::SaddSat => {
-                                let (pattern9_0, pattern9_1) =
-                                    C::unpack_value_array_2(ctx, pattern7_1);
-                                // Rule at src/isa/x64/lower.isle line 130.
-                                let expr0_0 = constructor_put_in_xmm(ctx, pattern9_0)?;
-                                let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern9_1)?;
-                                let expr2_0 = constructor_paddsw(ctx, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            &Opcode::UsubSat => {
-                                let (pattern9_0, pattern9_1) =
-                                    C::unpack_value_array_2(ctx, pattern7_1);
-                                // Rule at src/isa/x64/lower.isle line 286.
-                                let expr0_0 = constructor_put_in_xmm(ctx, pattern9_0)?;
-                                let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern9_1)?;
-                                let expr2_0 = constructor_psubusw(ctx, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            &Opcode::SsubSat => {
-                                let (pattern9_0, pattern9_1) =
-                                    C::unpack_value_array_2(ctx, pattern7_1);
-                                // Rule at src/isa/x64/lower.isle line 276.
-                                let expr0_0 = constructor_put_in_xmm(ctx, pattern9_0)?;
-                                let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern9_1)?;
-                                let expr2_0 = constructor_psubsw(ctx, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            &Opcode::Iadd => {
-                                let (pattern9_0, pattern9_1) =
-                                    C::unpack_value_array_2(ctx, pattern7_1);
-                                // Rule at src/isa/x64/lower.isle line 98.
-                                let expr0_0 = constructor_put_in_xmm(ctx, pattern9_0)?;
-                                let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern9_1)?;
-                                let expr2_0 = constructor_paddw(ctx, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            &Opcode::Isub => {
-                                let (pattern9_0, pattern9_1) =
-                                    C::unpack_value_array_2(ctx, pattern7_1);
-                                // Rule at src/isa/x64/lower.isle line 244.
-                                let expr0_0 = constructor_put_in_xmm(ctx, pattern9_0)?;
-                                let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern9_1)?;
-                                let expr2_0 = constructor_psubw(ctx, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            &Opcode::Imul => {
-                                let (pattern9_0, pattern9_1) =
-                                    C::unpack_value_array_2(ctx, pattern7_1);
-                                if let Some(pattern10_0) = C::def_inst(ctx, pattern9_0) {
-                                    let pattern11_0 = C::inst_data(ctx, pattern10_0);
-                                    if let &InstructionData::Unary {
-                                        opcode: ref pattern12_0,
-                                        arg: pattern12_1,
-                                    } = &pattern11_0
-                                    {
-                                        match pattern12_0 {
-                                            &Opcode::SwidenLow => {
-                                                let pattern14_0 = C::value_type(ctx, pattern12_1);
-                                                if let Some((pattern15_0, pattern15_1)) =
-                                                    C::multi_lane(ctx, pattern14_0)
-                                                {
-                                                    if pattern15_0 == 8 {
-                                                        if pattern15_1 == 16 {
-                                                            if let Some(pattern18_0) =
-                                                                C::def_inst(ctx, pattern9_1)
-                                                            {
-                                                                let pattern19_0 =
-                                                                    C::inst_data(ctx, pattern18_0);
-                                                                if let &InstructionData::Unary {
-                                                                    opcode: ref pattern20_0,
-                                                                    arg: pattern20_1,
-                                                                } = &pattern19_0
-                                                                {
-                                                                    if let &Opcode::SwidenLow =
-                                                                        pattern20_0
-                                                                    {
-                                                                        let pattern22_0 =
-                                                                            C::value_type(
-                                                                                ctx,
-                                                                                pattern20_1,
-                                                                            );
-                                                                        if let Some((
-                                                                            pattern23_0,
-                                                                            pattern23_1,
-                                                                        )) = C::multi_lane(
-                                                                            ctx,
-                                                                            pattern22_0,
-                                                                        ) {
-                                                                            if pattern23_0 == 8 {
-                                                                                if pattern23_1 == 16
-                                                                                {
-                                                                                    // Rule at src/isa/x64/lower.isle line 1080.
-                                                                                    let expr0_0 = constructor_put_in_xmm_mem(ctx, pattern12_1)?;
-                                                                                    let expr1_0 = constructor_pmovsxbw(ctx, &expr0_0)?;
-                                                                                    let expr2_0 = constructor_put_in_xmm_mem(ctx, pattern20_1)?;
-                                                                                    let expr3_0 = constructor_pmovsxbw(ctx, &expr2_0)?;
-                                                                                    let expr4_0 = C::xmm_to_xmm_mem(ctx, expr3_0);
-                                                                                    let expr5_0 = constructor_pmullw(ctx, expr1_0, &expr4_0)?;
-                                                                                    let expr6_0 = constructor_output_xmm(ctx, expr5_0)?;
-                                                                                    return Some(
-                                                                                        expr6_0,
-                                                                                    );
-                                                                                }
-                                                                            }
-                                                                        }
-                                                                    }
-                                                                }
-                                                            }
-                                                        }
-                                                    }
-                                                }
-                                            }
-                                            &Opcode::SwidenHigh => {
-                                                let pattern14_0 = C::value_type(ctx, pattern12_1);
-                                                if let Some((pattern15_0, pattern15_1)) =
-                                                    C::multi_lane(ctx, pattern14_0)
-                                                {
-                                                    if pattern15_0 == 8 {
-                                                        if pattern15_1 == 16 {
-                                                            if let Some(pattern18_0) =
-                                                                C::def_inst(ctx, pattern9_1)
-                                                            {
-                                                                let pattern19_0 =
-                                                                    C::inst_data(ctx, pattern18_0);
-                                                                if let &InstructionData::Unary {
-                                                                    opcode: ref pattern20_0,
-                                                                    arg: pattern20_1,
-                                                                } = &pattern19_0
-                                                                {
-                                                                    if let &Opcode::SwidenHigh =
-                                                                        pattern20_0
-                                                                    {
-                                                                        let pattern22_0 =
-                                                                            C::value_type(
-                                                                                ctx,
-                                                                                pattern20_1,
-                                                                            );
-                                                                        if let Some((
-                                                                            pattern23_0,
-                                                                            pattern23_1,
-                                                                        )) = C::multi_lane(
-                                                                            ctx,
-                                                                            pattern22_0,
-                                                                        ) {
-                                                                            if pattern23_0 == 8 {
-                                                                                if pattern23_1 == 16
-                                                                                {
-                                                                                    // Rule at src/isa/x64/lower.isle line 1040.
-                                                                                    let expr0_0 = constructor_put_in_xmm(ctx, pattern12_1)?;
-                                                                                    let expr1_0 = C::xmm_to_xmm_mem(ctx, expr0_0);
-                                                                                    let expr2_0: u8 = 8;
-                                                                                    let expr3_0 = OperandSize::Size32;
-                                                                                    let expr4_0 = constructor_palignr(ctx, expr0_0, &expr1_0, expr2_0, &expr3_0)?;
-                                                                                    let expr5_0 = C::xmm_to_xmm_mem(ctx, expr4_0);
-                                                                                    let expr6_0 = constructor_pmovsxbw(ctx, &expr5_0)?;
-                                                                                    let expr7_0 = constructor_put_in_xmm(ctx, pattern20_1)?;
-                                                                                    let expr8_0 = C::xmm_to_xmm_mem(ctx, expr7_0);
-                                                                                    let expr9_0: u8 = 8;
-                                                                                    let expr10_0 = OperandSize::Size32;
-                                                                                    let expr11_0 = constructor_palignr(ctx, expr7_0, &expr8_0, expr9_0, &expr10_0)?;
-                                                                                    let expr12_0 = C::xmm_to_xmm_mem(ctx, expr11_0);
-                                                                                    let expr13_0 = constructor_pmovsxbw(ctx, &expr12_0)?;
-                                                                                    let expr14_0 = C::xmm_to_xmm_mem(ctx, expr13_0);
-                                                                                    let expr15_0 = constructor_pmullw(ctx, expr6_0, &expr14_0)?;
-                                                                                    let expr16_0 = constructor_output_xmm(ctx, expr15_0)?;
-                                                                                    return Some(
-                                                                                        expr16_0,
-                                                                                    );
-                                                                                }
-                                                                            }
-                                                                        }
-                                                                    }
-                                                                }
-                                                            }
-                                                        }
-                                                    }
-                                                }
-                                            }
-                                            &Opcode::UwidenLow => {
-                                                let pattern14_0 = C::value_type(ctx, pattern12_1);
-                                                if let Some((pattern15_0, pattern15_1)) =
-                                                    C::multi_lane(ctx, pattern14_0)
-                                                {
-                                                    if pattern15_0 == 8 {
-                                                        if pattern15_1 == 16 {
-                                                            if let Some(pattern18_0) =
-                                                                C::def_inst(ctx, pattern9_1)
-                                                            {
-                                                                let pattern19_0 =
-                                                                    C::inst_data(ctx, pattern18_0);
-                                                                if let &InstructionData::Unary {
-                                                                    opcode: ref pattern20_0,
-                                                                    arg: pattern20_1,
-                                                                } = &pattern19_0
-                                                                {
-                                                                    if let &Opcode::UwidenLow =
-                                                                        pattern20_0
-                                                                    {
-                                                                        let pattern22_0 =
-                                                                            C::value_type(
-                                                                                ctx,
-                                                                                pattern20_1,
-                                                                            );
-                                                                        if let Some((
-                                                                            pattern23_0,
-                                                                            pattern23_1,
-                                                                        )) = C::multi_lane(
-                                                                            ctx,
-                                                                            pattern22_0,
-                                                                        ) {
-                                                                            if pattern23_0 == 8 {
-                                                                                if pattern23_1 == 16
-                                                                                {
-                                                                                    // Rule at src/isa/x64/lower.isle line 1156.
-                                                                                    let expr0_0 = constructor_put_in_xmm_mem(ctx, pattern12_1)?;
-                                                                                    let expr1_0 = constructor_pmovzxbw(ctx, &expr0_0)?;
-                                                                                    let expr2_0 = constructor_put_in_xmm_mem(ctx, pattern20_1)?;
-                                                                                    let expr3_0 = constructor_pmovzxbw(ctx, &expr2_0)?;
-                                                                                    let expr4_0 = C::xmm_to_xmm_mem(ctx, expr3_0);
-                                                                                    let expr5_0 = constructor_pmullw(ctx, expr1_0, &expr4_0)?;
-                                                                                    let expr6_0 = constructor_output_xmm(ctx, expr5_0)?;
-                                                                                    return Some(
-                                                                                        expr6_0,
-                                                                                    );
-                                                                                }
-                                                                            }
-                                                                        }
-                                                                    }
-                                                                }
-                                                            }
-                                                        }
-                                                    }
-                                                }
-                                            }
-                                            &Opcode::UwidenHigh => {
-                                                let pattern14_0 = C::value_type(ctx, pattern12_1);
-                                                if let Some((pattern15_0, pattern15_1)) =
-                                                    C::multi_lane(ctx, pattern14_0)
-                                                {
-                                                    if pattern15_0 == 8 {
-                                                        if pattern15_1 == 16 {
-                                                            if let Some(pattern18_0) =
-                                                                C::def_inst(ctx, pattern9_1)
-                                                            {
-                                                                let pattern19_0 =
-                                                                    C::inst_data(ctx, pattern18_0);
-                                                                if let &InstructionData::Unary {
-                                                                    opcode: ref pattern20_0,
-                                                                    arg: pattern20_1,
-                                                                } = &pattern19_0
-                                                                {
-                                                                    if let &Opcode::UwidenHigh =
-                                                                        pattern20_0
-                                                                    {
-                                                                        let pattern22_0 =
-                                                                            C::value_type(
-                                                                                ctx,
-                                                                                pattern20_1,
-                                                                            );
-                                                                        if let Some((
-                                                                            pattern23_0,
-                                                                            pattern23_1,
-                                                                        )) = C::multi_lane(
-                                                                            ctx,
-                                                                            pattern22_0,
-                                                                        ) {
-                                                                            if pattern23_0 == 8 {
-                                                                                if pattern23_1 == 16
-                                                                                {
-                                                                                    // Rule at src/isa/x64/lower.isle line 1116.
-                                                                                    let expr0_0 = constructor_put_in_xmm(ctx, pattern12_1)?;
-                                                                                    let expr1_0 = C::xmm_to_xmm_mem(ctx, expr0_0);
-                                                                                    let expr2_0: u8 = 8;
-                                                                                    let expr3_0 = OperandSize::Size32;
-                                                                                    let expr4_0 = constructor_palignr(ctx, expr0_0, &expr1_0, expr2_0, &expr3_0)?;
-                                                                                    let expr5_0 = C::xmm_to_xmm_mem(ctx, expr4_0);
-                                                                                    let expr6_0 = constructor_pmovzxbw(ctx, &expr5_0)?;
-                                                                                    let expr7_0 = constructor_put_in_xmm(ctx, pattern20_1)?;
-                                                                                    let expr8_0 = C::xmm_to_xmm_mem(ctx, expr7_0);
-                                                                                    let expr9_0: u8 = 8;
-                                                                                    let expr10_0 = OperandSize::Size32;
-                                                                                    let expr11_0 = constructor_palignr(ctx, expr7_0, &expr8_0, expr9_0, &expr10_0)?;
-                                                                                    let expr12_0 = C::xmm_to_xmm_mem(ctx, expr11_0);
-                                                                                    let expr13_0 = constructor_pmovzxbw(ctx, &expr12_0)?;
-                                                                                    let expr14_0 = C::xmm_to_xmm_mem(ctx, expr13_0);
-                                                                                    let expr15_0 = constructor_pmullw(ctx, expr6_0, &expr14_0)?;
-                                                                                    let expr16_0 = constructor_output_xmm(ctx, expr15_0)?;
-                                                                                    return Some(
-                                                                                        expr16_0,
-                                                                                    );
-                                                                                }
-                                                                            }
-                                                                        }
-                                                                    }
-                                                                }
-                                                            }
-                                                        }
-                                                    }
-                                                }
-                                            }
-                                            _ => {}
-                                        }
-                                    }
-                                }
-                                // Rule at src/isa/x64/lower.isle line 984.
-                                let expr0_0 = constructor_put_in_xmm(ctx, pattern9_0)?;
-                                let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern9_1)?;
-                                let expr2_0 = constructor_pmullw(ctx, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            _ => {}
-                        }
-                    }
-                }
-            }
-            if pattern3_0 == 32 {
-                if pattern3_1 == 4 {
-                    let pattern6_0 = C::inst_data(ctx, pattern0_0);
-                    if let &InstructionData::Binary {
-                        opcode: ref pattern7_0,
-                        args: ref pattern7_1,
-                    } = &pattern6_0
-                    {
-                        match pattern7_0 {
-                            &Opcode::Iadd => {
-                                let (pattern9_0, pattern9_1) =
-                                    C::unpack_value_array_2(ctx, pattern7_1);
-                                // Rule at src/isa/x64/lower.isle line 102.
-                                let expr0_0 = constructor_put_in_xmm(ctx, pattern9_0)?;
-                                let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern9_1)?;
-                                let expr2_0 = constructor_paddd(ctx, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            &Opcode::Isub => {
-                                let (pattern9_0, pattern9_1) =
-                                    C::unpack_value_array_2(ctx, pattern7_1);
-                                // Rule at src/isa/x64/lower.isle line 248.
-                                let expr0_0 = constructor_put_in_xmm(ctx, pattern9_0)?;
-                                let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern9_1)?;
-                                let expr2_0 = constructor_psubd(ctx, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            &Opcode::Imul => {
-                                let (pattern9_0, pattern9_1) =
-                                    C::unpack_value_array_2(ctx, pattern7_1);
-                                if let Some(pattern10_0) = C::def_inst(ctx, pattern9_0) {
-                                    let pattern11_0 = C::inst_data(ctx, pattern10_0);
-                                    if let &InstructionData::Unary {
-                                        opcode: ref pattern12_0,
-                                        arg: pattern12_1,
-                                    } = &pattern11_0
-                                    {
-                                        match pattern12_0 {
-                                            &Opcode::SwidenLow => {
-                                                let pattern14_0 = C::value_type(ctx, pattern12_1);
-                                                if let Some((pattern15_0, pattern15_1)) =
-                                                    C::multi_lane(ctx, pattern14_0)
-                                                {
-                                                    if pattern15_0 == 16 {
-                                                        if pattern15_1 == 8 {
-                                                            if let Some(pattern18_0) =
-                                                                C::def_inst(ctx, pattern9_1)
-                                                            {
-                                                                let pattern19_0 =
-                                                                    C::inst_data(ctx, pattern18_0);
-                                                                if let &InstructionData::Unary {
-                                                                    opcode: ref pattern20_0,
-                                                                    arg: pattern20_1,
-                                                                } = &pattern19_0
-                                                                {
-                                                                    if let &Opcode::SwidenLow =
-                                                                        pattern20_0
-                                                                    {
-                                                                        let pattern22_0 =
-                                                                            C::value_type(
-                                                                                ctx,
-                                                                                pattern20_1,
-                                                                            );
-                                                                        if let Some((
-                                                                            pattern23_0,
-                                                                            pattern23_1,
-                                                                        )) = C::multi_lane(
-                                                                            ctx,
-                                                                            pattern22_0,
-                                                                        ) {
-                                                                            if pattern23_0 == 16 {
-                                                                                if pattern23_1 == 8
-                                                                                {
-                                                                                    // Rule at src/isa/x64/lower.isle line 1090.
-                                                                                    let expr0_0 = constructor_put_in_xmm(ctx, pattern12_1)?;
-                                                                                    let expr1_0 = constructor_put_in_xmm(ctx, pattern20_1)?;
-                                                                                    let expr2_0 = C::xmm_to_xmm_mem(ctx, expr1_0);
-                                                                                    let expr3_0 = constructor_pmullw(ctx, expr0_0, &expr2_0)?;
-                                                                                    let expr4_0 = C::xmm_to_xmm_mem(ctx, expr1_0);
-                                                                                    let expr5_0 = constructor_pmulhw(ctx, expr0_0, &expr4_0)?;
-                                                                                    let expr6_0 = C::xmm_to_xmm_mem(ctx, expr5_0);
-                                                                                    let expr7_0 = constructor_punpcklwd(ctx, expr3_0, &expr6_0)?;
-                                                                                    let expr8_0 = constructor_output_xmm(ctx, expr7_0)?;
-                                                                                    return Some(
-                                                                                        expr8_0,
-                                                                                    );
-                                                                                }
-                                                                            }
-                                                                        }
-                                                                    }
-                                                                }
-                                                            }
-                                                        }
-                                                    }
-                                                }
-                                            }
-                                            &Opcode::SwidenHigh => {
-                                                let pattern14_0 = C::value_type(ctx, pattern12_1);
-                                                if let Some((pattern15_0, pattern15_1)) =
-                                                    C::multi_lane(ctx, pattern14_0)
-                                                {
-                                                    if pattern15_0 == 16 {
-                                                        if pattern15_1 == 8 {
-                                                            if let Some(pattern18_0) =
-                                                                C::def_inst(ctx, pattern9_1)
-                                                            {
-                                                                let pattern19_0 =
-                                                                    C::inst_data(ctx, pattern18_0);
-                                                                if let &InstructionData::Unary {
-                                                                    opcode: ref pattern20_0,
-                                                                    arg: pattern20_1,
-                                                                } = &pattern19_0
-                                                                {
-                                                                    if let &Opcode::SwidenHigh =
-                                                                        pattern20_0
-                                                                    {
-                                                                        let pattern22_0 =
-                                                                            C::value_type(
-                                                                                ctx,
-                                                                                pattern20_1,
-                                                                            );
-                                                                        if let Some((
-                                                                            pattern23_0,
-                                                                            pattern23_1,
-                                                                        )) = C::multi_lane(
-                                                                            ctx,
-                                                                            pattern22_0,
-                                                                        ) {
-                                                                            if pattern23_0 == 16 {
-                                                                                if pattern23_1 == 8
-                                                                                {
-                                                                                    // Rule at src/isa/x64/lower.isle line 1054.
-                                                                                    let expr0_0 = constructor_put_in_xmm(ctx, pattern12_1)?;
-                                                                                    let expr1_0 = constructor_put_in_xmm(ctx, pattern20_1)?;
-                                                                                    let expr2_0 = C::xmm_to_xmm_mem(ctx, expr1_0);
-                                                                                    let expr3_0 = constructor_pmullw(ctx, expr0_0, &expr2_0)?;
-                                                                                    let expr4_0 = C::xmm_to_xmm_mem(ctx, expr1_0);
-                                                                                    let expr5_0 = constructor_pmulhw(ctx, expr0_0, &expr4_0)?;
-                                                                                    let expr6_0 = C::xmm_to_xmm_mem(ctx, expr5_0);
-                                                                                    let expr7_0 = constructor_punpckhwd(ctx, expr3_0, &expr6_0)?;
-                                                                                    let expr8_0 = constructor_output_xmm(ctx, expr7_0)?;
-                                                                                    return Some(
-                                                                                        expr8_0,
-                                                                                    );
-                                                                                }
-                                                                            }
-                                                                        }
-                                                                    }
-                                                                }
-                                                            }
-                                                        }
-                                                    }
-                                                }
-                                            }
-                                            &Opcode::UwidenLow => {
-                                                let pattern14_0 = C::value_type(ctx, pattern12_1);
-                                                if let Some((pattern15_0, pattern15_1)) =
-                                                    C::multi_lane(ctx, pattern14_0)
-                                                {
-                                                    if pattern15_0 == 16 {
-                                                        if pattern15_1 == 8 {
-                                                            if let Some(pattern18_0) =
-                                                                C::def_inst(ctx, pattern9_1)
-                                                            {
-                                                                let pattern19_0 =
-                                                                    C::inst_data(ctx, pattern18_0);
-                                                                if let &InstructionData::Unary {
-                                                                    opcode: ref pattern20_0,
-                                                                    arg: pattern20_1,
-                                                                } = &pattern19_0
-                                                                {
-                                                                    if let &Opcode::UwidenLow =
-                                                                        pattern20_0
-                                                                    {
-                                                                        let pattern22_0 =
-                                                                            C::value_type(
-                                                                                ctx,
-                                                                                pattern20_1,
-                                                                            );
-                                                                        if let Some((
-                                                                            pattern23_0,
-                                                                            pattern23_1,
-                                                                        )) = C::multi_lane(
-                                                                            ctx,
-                                                                            pattern22_0,
-                                                                        ) {
-                                                                            if pattern23_0 == 16 {
-                                                                                if pattern23_1 == 8
-                                                                                {
-                                                                                    // Rule at src/isa/x64/lower.isle line 1166.
-                                                                                    let expr0_0 = constructor_put_in_xmm(ctx, pattern12_1)?;
-                                                                                    let expr1_0 = constructor_put_in_xmm(ctx, pattern20_1)?;
-                                                                                    let expr2_0 = C::xmm_to_xmm_mem(ctx, expr1_0);
-                                                                                    let expr3_0 = constructor_pmullw(ctx, expr0_0, &expr2_0)?;
-                                                                                    let expr4_0 = C::xmm_to_xmm_mem(ctx, expr1_0);
-                                                                                    let expr5_0 = constructor_pmulhuw(ctx, expr0_0, &expr4_0)?;
-                                                                                    let expr6_0 = C::xmm_to_xmm_mem(ctx, expr5_0);
-                                                                                    let expr7_0 = constructor_punpcklwd(ctx, expr3_0, &expr6_0)?;
-                                                                                    let expr8_0 = constructor_output_xmm(ctx, expr7_0)?;
-                                                                                    return Some(
-                                                                                        expr8_0,
-                                                                                    );
-                                                                                }
-                                                                            }
-                                                                        }
-                                                                    }
-                                                                }
-                                                            }
-                                                        }
-                                                    }
-                                                }
-                                            }
-                                            &Opcode::UwidenHigh => {
-                                                let pattern14_0 = C::value_type(ctx, pattern12_1);
-                                                if let Some((pattern15_0, pattern15_1)) =
-                                                    C::multi_lane(ctx, pattern14_0)
-                                                {
-                                                    if pattern15_0 == 16 {
-                                                        if pattern15_1 == 8 {
-                                                            if let Some(pattern18_0) =
-                                                                C::def_inst(ctx, pattern9_1)
-                                                            {
-                                                                let pattern19_0 =
-                                                                    C::inst_data(ctx, pattern18_0);
-                                                                if let &InstructionData::Unary {
-                                                                    opcode: ref pattern20_0,
-                                                                    arg: pattern20_1,
-                                                                } = &pattern19_0
-                                                                {
-                                                                    if let &Opcode::UwidenHigh =
-                                                                        pattern20_0
-                                                                    {
-                                                                        let pattern22_0 =
-                                                                            C::value_type(
-                                                                                ctx,
-                                                                                pattern20_1,
-                                                                            );
-                                                                        if let Some((
-                                                                            pattern23_0,
-                                                                            pattern23_1,
-                                                                        )) = C::multi_lane(
-                                                                            ctx,
-                                                                            pattern22_0,
-                                                                        ) {
-                                                                            if pattern23_0 == 16 {
-                                                                                if pattern23_1 == 8
-                                                                                {
-                                                                                    // Rule at src/isa/x64/lower.isle line 1130.
-                                                                                    let expr0_0 = constructor_put_in_xmm(ctx, pattern12_1)?;
-                                                                                    let expr1_0 = constructor_put_in_xmm(ctx, pattern20_1)?;
-                                                                                    let expr2_0 = C::xmm_to_xmm_mem(ctx, expr1_0);
-                                                                                    let expr3_0 = constructor_pmullw(ctx, expr0_0, &expr2_0)?;
-                                                                                    let expr4_0 = C::xmm_to_xmm_mem(ctx, expr1_0);
-                                                                                    let expr5_0 = constructor_pmulhuw(ctx, expr0_0, &expr4_0)?;
-                                                                                    let expr6_0 = C::xmm_to_xmm_mem(ctx, expr5_0);
-                                                                                    let expr7_0 = constructor_punpckhwd(ctx, expr3_0, &expr6_0)?;
-                                                                                    let expr8_0 = constructor_output_xmm(ctx, expr7_0)?;
-                                                                                    return Some(
-                                                                                        expr8_0,
-                                                                                    );
-                                                                                }
-                                                                            }
-                                                                        }
-                                                                    }
-                                                                }
-                                                            }
-                                                        }
-                                                    }
-                                                }
-                                            }
-                                            _ => {}
-                                        }
-                                    }
-                                }
-                                // Rule at src/isa/x64/lower.isle line 987.
-                                let expr0_0 = constructor_put_in_xmm(ctx, pattern9_0)?;
-                                let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern9_1)?;
-                                let expr2_0 = constructor_pmulld(ctx, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            _ => {}
-                        }
-                    }
-                }
-            }
-            if pattern3_0 == 64 {
-                if pattern3_1 == 2 {
-                    let pattern6_0 = C::inst_data(ctx, pattern0_0);
-                    if let &InstructionData::Binary {
-                        opcode: ref pattern7_0,
-                        args: ref pattern7_1,
-                    } = &pattern6_0
-                    {
-                        match pattern7_0 {
-                            &Opcode::Iadd => {
-                                let (pattern9_0, pattern9_1) =
-                                    C::unpack_value_array_2(ctx, pattern7_1);
-                                // Rule at src/isa/x64/lower.isle line 106.
-                                let expr0_0 = constructor_put_in_xmm(ctx, pattern9_0)?;
-                                let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern9_1)?;
-                                let expr2_0 = constructor_paddq(ctx, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            &Opcode::Isub => {
-                                let (pattern9_0, pattern9_1) =
-                                    C::unpack_value_array_2(ctx, pattern7_1);
-                                // Rule at src/isa/x64/lower.isle line 252.
-                                let expr0_0 = constructor_put_in_xmm(ctx, pattern9_0)?;
-                                let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern9_1)?;
-                                let expr2_0 = constructor_psubq(ctx, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            &Opcode::Imul => {
-                                let (pattern9_0, pattern9_1) =
-                                    C::unpack_value_array_2(ctx, pattern7_1);
-                                if let Some(pattern10_0) = C::def_inst(ctx, pattern9_0) {
-                                    let pattern11_0 = C::inst_data(ctx, pattern10_0);
-                                    if let &InstructionData::Unary {
-                                        opcode: ref pattern12_0,
-                                        arg: pattern12_1,
-                                    } = &pattern11_0
-                                    {
-                                        match pattern12_0 {
-                                            &Opcode::SwidenLow => {
-                                                let pattern14_0 = C::value_type(ctx, pattern12_1);
-                                                if let Some((pattern15_0, pattern15_1)) =
-                                                    C::multi_lane(ctx, pattern14_0)
-                                                {
-                                                    if pattern15_0 == 32 {
-                                                        if pattern15_1 == 4 {
-                                                            if let Some(pattern18_0) =
-                                                                C::def_inst(ctx, pattern9_1)
-                                                            {
-                                                                let pattern19_0 =
-                                                                    C::inst_data(ctx, pattern18_0);
-                                                                if let &InstructionData::Unary {
-                                                                    opcode: ref pattern20_0,
-                                                                    arg: pattern20_1,
-                                                                } = &pattern19_0
-                                                                {
-                                                                    if let &Opcode::SwidenLow =
-                                                                        pattern20_0
-                                                                    {
-                                                                        let pattern22_0 =
-                                                                            C::value_type(
-                                                                                ctx,
-                                                                                pattern20_1,
-                                                                            );
-                                                                        if let Some((
-                                                                            pattern23_0,
-                                                                            pattern23_1,
-                                                                        )) = C::multi_lane(
-                                                                            ctx,
-                                                                            pattern22_0,
-                                                                        ) {
-                                                                            if pattern23_0 == 32 {
-                                                                                if pattern23_1 == 4
-                                                                                {
-                                                                                    // Rule at src/isa/x64/lower.isle line 1102.
-                                                                                    let expr0_0 = constructor_put_in_xmm_mem(ctx, pattern12_1)?;
-                                                                                    let expr1_0: u8 = 80;
-                                                                                    let expr2_0 = OperandSize::Size32;
-                                                                                    let expr3_0 = constructor_pshufd(ctx, &expr0_0, expr1_0, &expr2_0)?;
-                                                                                    let expr4_0 = constructor_put_in_xmm_mem(ctx, pattern20_1)?;
-                                                                                    let expr5_0: u8 = 80;
-                                                                                    let expr6_0 = OperandSize::Size32;
-                                                                                    let expr7_0 = constructor_pshufd(ctx, &expr4_0, expr5_0, &expr6_0)?;
-                                                                                    let expr8_0 = C::xmm_to_xmm_mem(ctx, expr7_0);
-                                                                                    let expr9_0 = constructor_pmuldq(ctx, expr3_0, &expr8_0)?;
-                                                                                    let expr10_0 = constructor_output_xmm(ctx, expr9_0)?;
-                                                                                    return Some(
-                                                                                        expr10_0,
-                                                                                    );
-                                                                                }
-                                                                            }
-                                                                        }
-                                                                    }
-                                                                }
-                                                            }
-                                                        }
-                                                    }
-                                                }
-                                            }
-                                            &Opcode::SwidenHigh => {
-                                                let pattern14_0 = C::value_type(ctx, pattern12_1);
-                                                if let Some((pattern15_0, pattern15_1)) =
-                                                    C::multi_lane(ctx, pattern14_0)
-                                                {
-                                                    if pattern15_0 == 32 {
-                                                        if pattern15_1 == 4 {
-                                                            if let Some(pattern18_0) =
-                                                                C::def_inst(ctx, pattern9_1)
-                                                            {
-                                                                let pattern19_0 =
-                                                                    C::inst_data(ctx, pattern18_0);
-                                                                if let &InstructionData::Unary {
-                                                                    opcode: ref pattern20_0,
-                                                                    arg: pattern20_1,
-                                                                } = &pattern19_0
-                                                                {
-                                                                    if let &Opcode::SwidenHigh =
-                                                                        pattern20_0
-                                                                    {
-                                                                        let pattern22_0 =
-                                                                            C::value_type(
-                                                                                ctx,
-                                                                                pattern20_1,
-                                                                            );
-                                                                        if let Some((
-                                                                            pattern23_0,
-                                                                            pattern23_1,
-                                                                        )) = C::multi_lane(
-                                                                            ctx,
-                                                                            pattern22_0,
-                                                                        ) {
-                                                                            if pattern23_0 == 32 {
-                                                                                if pattern23_1 == 4
-                                                                                {
-                                                                                    // Rule at src/isa/x64/lower.isle line 1066.
-                                                                                    let expr0_0 = constructor_put_in_xmm_mem(ctx, pattern12_1)?;
-                                                                                    let expr1_0: u8 = 250;
-                                                                                    let expr2_0 = OperandSize::Size32;
-                                                                                    let expr3_0 = constructor_pshufd(ctx, &expr0_0, expr1_0, &expr2_0)?;
-                                                                                    let expr4_0 = constructor_put_in_xmm_mem(ctx, pattern20_1)?;
-                                                                                    let expr5_0: u8 = 250;
-                                                                                    let expr6_0 = OperandSize::Size32;
-                                                                                    let expr7_0 = constructor_pshufd(ctx, &expr4_0, expr5_0, &expr6_0)?;
-                                                                                    let expr8_0 = C::xmm_to_xmm_mem(ctx, expr7_0);
-                                                                                    let expr9_0 = constructor_pmuldq(ctx, expr3_0, &expr8_0)?;
-                                                                                    let expr10_0 = constructor_output_xmm(ctx, expr9_0)?;
-                                                                                    return Some(
-                                                                                        expr10_0,
-                                                                                    );
-                                                                                }
-                                                                            }
-                                                                        }
-                                                                    }
-                                                                }
-                                                            }
-                                                        }
-                                                    }
-                                                }
-                                            }
-                                            &Opcode::UwidenLow => {
-                                                let pattern14_0 = C::value_type(ctx, pattern12_1);
-                                                if let Some((pattern15_0, pattern15_1)) =
-                                                    C::multi_lane(ctx, pattern14_0)
-                                                {
-                                                    if pattern15_0 == 32 {
-                                                        if pattern15_1 == 4 {
-                                                            if let Some(pattern18_0) =
-                                                                C::def_inst(ctx, pattern9_1)
-                                                            {
-                                                                let pattern19_0 =
-                                                                    C::inst_data(ctx, pattern18_0);
-                                                                if let &InstructionData::Unary {
-                                                                    opcode: ref pattern20_0,
-                                                                    arg: pattern20_1,
-                                                                } = &pattern19_0
-                                                                {
-                                                                    if let &Opcode::UwidenLow =
-                                                                        pattern20_0
-                                                                    {
-                                                                        let pattern22_0 =
-                                                                            C::value_type(
-                                                                                ctx,
-                                                                                pattern20_1,
-                                                                            );
-                                                                        if let Some((
-                                                                            pattern23_0,
-                                                                            pattern23_1,
-                                                                        )) = C::multi_lane(
-                                                                            ctx,
-                                                                            pattern22_0,
-                                                                        ) {
-                                                                            if pattern23_0 == 32 {
-                                                                                if pattern23_1 == 4
-                                                                                {
-                                                                                    // Rule at src/isa/x64/lower.isle line 1178.
-                                                                                    let expr0_0 = constructor_put_in_xmm_mem(ctx, pattern12_1)?;
-                                                                                    let expr1_0: u8 = 80;
-                                                                                    let expr2_0 = OperandSize::Size32;
-                                                                                    let expr3_0 = constructor_pshufd(ctx, &expr0_0, expr1_0, &expr2_0)?;
-                                                                                    let expr4_0 = constructor_put_in_xmm_mem(ctx, pattern20_1)?;
-                                                                                    let expr5_0: u8 = 80;
-                                                                                    let expr6_0 = OperandSize::Size32;
-                                                                                    let expr7_0 = constructor_pshufd(ctx, &expr4_0, expr5_0, &expr6_0)?;
-                                                                                    let expr8_0 = C::xmm_to_xmm_mem(ctx, expr7_0);
-                                                                                    let expr9_0 = constructor_pmuludq(ctx, expr3_0, &expr8_0)?;
-                                                                                    let expr10_0 = constructor_output_xmm(ctx, expr9_0)?;
-                                                                                    return Some(
-                                                                                        expr10_0,
-                                                                                    );
-                                                                                }
-                                                                            }
-                                                                        }
-                                                                    }
-                                                                }
-                                                            }
-                                                        }
-                                                    }
-                                                }
-                                            }
-                                            &Opcode::UwidenHigh => {
-                                                let pattern14_0 = C::value_type(ctx, pattern12_1);
-                                                if let Some((pattern15_0, pattern15_1)) =
-                                                    C::multi_lane(ctx, pattern14_0)
-                                                {
-                                                    if pattern15_0 == 32 {
-                                                        if pattern15_1 == 4 {
-                                                            if let Some(pattern18_0) =
-                                                                C::def_inst(ctx, pattern9_1)
-                                                            {
-                                                                let pattern19_0 =
-                                                                    C::inst_data(ctx, pattern18_0);
-                                                                if let &InstructionData::Unary {
-                                                                    opcode: ref pattern20_0,
-                                                                    arg: pattern20_1,
-                                                                } = &pattern19_0
-                                                                {
-                                                                    if let &Opcode::UwidenHigh =
-                                                                        pattern20_0
-                                                                    {
-                                                                        let pattern22_0 =
-                                                                            C::value_type(
-                                                                                ctx,
-                                                                                pattern20_1,
-                                                                            );
-                                                                        if let Some((
-                                                                            pattern23_0,
-                                                                            pattern23_1,
-                                                                        )) = C::multi_lane(
-                                                                            ctx,
-                                                                            pattern22_0,
-                                                                        ) {
-                                                                            if pattern23_0 == 32 {
-                                                                                if pattern23_1 == 4
-                                                                                {
-                                                                                    // Rule at src/isa/x64/lower.isle line 1142.
-                                                                                    let expr0_0 = constructor_put_in_xmm_mem(ctx, pattern12_1)?;
-                                                                                    let expr1_0: u8 = 250;
-                                                                                    let expr2_0 = OperandSize::Size32;
-                                                                                    let expr3_0 = constructor_pshufd(ctx, &expr0_0, expr1_0, &expr2_0)?;
-                                                                                    let expr4_0 = constructor_put_in_xmm_mem(ctx, pattern20_1)?;
-                                                                                    let expr5_0: u8 = 250;
-                                                                                    let expr6_0 = OperandSize::Size32;
-                                                                                    let expr7_0 = constructor_pshufd(ctx, &expr4_0, expr5_0, &expr6_0)?;
-                                                                                    let expr8_0 = C::xmm_to_xmm_mem(ctx, expr7_0);
-                                                                                    let expr9_0 = constructor_pmuludq(ctx, expr3_0, &expr8_0)?;
-                                                                                    let expr10_0 = constructor_output_xmm(ctx, expr9_0)?;
-                                                                                    return Some(
-                                                                                        expr10_0,
-                                                                                    );
-                                                                                }
-                                                                            }
-                                                                        }
-                                                                    }
-                                                                }
-                                                            }
-                                                        }
-                                                    }
-                                                }
-                                            }
-                                            _ => {}
-                                        }
-                                    }
-                                }
-                                // Rule at src/isa/x64/lower.isle line 1018.
-                                let expr0_0 = constructor_put_in_xmm(ctx, pattern9_0)?;
-                                let expr1_0 = constructor_put_in_xmm(ctx, pattern9_1)?;
-                                let expr2_0: u32 = 32;
-                                let expr3_0 = RegMemImm::Imm { simm32: expr2_0 };
-                                let expr4_0 = constructor_mov_rmi_to_xmm(ctx, &expr3_0)?;
-                                let expr5_0 = constructor_psrlq(ctx, expr0_0, &expr4_0)?;
-                                let expr6_0 = C::xmm_to_xmm_mem(ctx, expr1_0);
-                                let expr7_0 = constructor_pmuludq(ctx, expr5_0, &expr6_0)?;
-                                let expr8_0: u32 = 32;
-                                let expr9_0 = RegMemImm::Imm { simm32: expr8_0 };
-                                let expr10_0 = constructor_mov_rmi_to_xmm(ctx, &expr9_0)?;
-                                let expr11_0 = constructor_psrlq(ctx, expr1_0, &expr10_0)?;
-                                let expr12_0 = C::xmm_to_xmm_mem(ctx, expr11_0);
-                                let expr13_0 = constructor_pmuludq(ctx, expr0_0, &expr12_0)?;
-                                let expr14_0 = C::xmm_to_xmm_mem(ctx, expr13_0);
-                                let expr15_0 = constructor_paddq(ctx, expr7_0, &expr14_0)?;
-                                let expr16_0: u32 = 32;
-                                let expr17_0 = RegMemImm::Imm { simm32: expr16_0 };
-                                let expr18_0 = constructor_mov_rmi_to_xmm(ctx, &expr17_0)?;
-                                let expr19_0 = constructor_psllq(ctx, expr15_0, &expr18_0)?;
-                                let expr20_0 = C::xmm_to_xmm_mem(ctx, expr1_0);
-                                let expr21_0 = constructor_pmuludq(ctx, expr0_0, &expr20_0)?;
-                                let expr22_0 = C::xmm_to_xmm_mem(ctx, expr19_0);
-                                let expr23_0 = constructor_paddq(ctx, expr21_0, &expr22_0)?;
-                                let expr24_0 = constructor_output_xmm(ctx, expr23_0)?;
-                                return Some(expr24_0);
-                            }
-                            _ => {}
-                        }
-                    }
-                }
-            }
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            match &pattern4_0 {
-                &InstructionData::Binary {
-                    opcode: ref pattern5_0,
-                    args: ref pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Band => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 328.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_sse_and(ctx, pattern2_0, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Bor => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 392.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_sse_or(ctx, pattern2_0, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Bxor => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 453.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_sse_xor(ctx, pattern2_0, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_xmm(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        _ => {}
-                    }
-                }
-                &InstructionData::Ternary {
-                    opcode: ref pattern5_0,
-                    args: ref pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Bitselect => {
-                            let (pattern7_0, pattern7_1, pattern7_2) =
-                                C::unpack_value_array_3(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 1279.
-                            let expr0_0 = constructor_put_in_xmm(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_xmm(ctx, pattern7_1)?;
-                            let expr2_0 = C::xmm_to_xmm_mem(ctx, expr0_0);
-                            let expr3_0 = constructor_sse_and(ctx, pattern2_0, expr1_0, &expr2_0)?;
-                            let expr4_0 = constructor_put_in_xmm_mem(ctx, pattern7_2)?;
-                            let expr5_0 =
-                                constructor_sse_and_not(ctx, pattern2_0, expr0_0, &expr4_0)?;
-                            let expr6_0 = C::xmm_to_xmm_mem(ctx, expr3_0);
-                            let expr7_0 = constructor_sse_or(ctx, pattern2_0, expr5_0, &expr6_0)?;
-                            let expr8_0 = constructor_output_xmm(ctx, expr7_0)?;
-                            return Some(expr8_0);
-                        }
-                        &Opcode::Vselect => {
-                            let (pattern7_0, pattern7_1, pattern7_2) =
-                                C::unpack_value_array_3(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 1293.
-                            let expr0_0 = constructor_put_in_xmm_mem(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_xmm_mem(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_put_in_xmm(ctx, pattern7_2)?;
-                            let expr3_0 = constructor_sse_blend(
-                                ctx, pattern2_0, &expr0_0, &expr1_0, expr2_0,
-                            )?;
-                            let expr4_0 = constructor_output_xmm(ctx, expr3_0)?;
-                            return Some(expr4_0);
-                        }
-                        _ => {}
-                    }
-                }
-                &InstructionData::Unary {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                } => {
-                    if let &Opcode::Bnot = pattern5_0 {
-                        // Rule at src/isa/x64/lower.isle line 1274.
-                        let expr0_0 = constructor_put_in_xmm(ctx, pattern5_1)?;
-                        let expr1_0 = constructor_vector_all_ones(ctx, pattern2_0)?;
-                        let expr2_0 = C::xmm_to_xmm_mem(ctx, expr1_0);
-                        let expr3_0 = constructor_sse_xor(ctx, pattern2_0, expr0_0, &expr2_0)?;
-                        let expr4_0 = constructor_output_xmm(ctx, expr3_0)?;
-                        return Some(expr4_0);
-                    }
-                }
-                _ => {}
-            }
-        }
-        if let Some(pattern3_0) = C::fits_in_32(ctx, pattern2_0) {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            if let &InstructionData::Unary {
-                opcode: ref pattern5_0,
-                arg: pattern5_1,
-            } = &pattern4_0
-            {
-                if let &Opcode::Uextend = pattern5_0 {
-                    let pattern7_0 = C::value_type(ctx, pattern5_1);
-                    if let Some(pattern8_0) = C::fits_in_32(ctx, pattern7_0) {
-                        // Rule at src/isa/x64/lower.isle line 1882.
-                        let expr0_0: Type = I32;
-                        let expr1_0 = ExtendKind::Zero;
-                        let expr2_0 =
-                            constructor_extend_to_gpr(ctx, pattern5_1, expr0_0, &expr1_0)?;
-                        let expr3_0 = constructor_output_gpr(ctx, expr2_0)?;
-                        return Some(expr3_0);
-                    }
-                }
-            }
-        }
-        if let Some(pattern3_0) = C::fits_in_64(ctx, pattern2_0) {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            match &pattern4_0 {
-                &InstructionData::UnaryImm {
-                    opcode: ref pattern5_0,
-                    imm: pattern5_1,
-                } => {
-                    if let &Opcode::Iconst = pattern5_0 {
-                        let pattern7_0 = C::u64_from_imm64(ctx, pattern5_1);
-                        // Rule at src/isa/x64/lower.isle line 10.
-                        let expr0_0 = constructor_imm(ctx, pattern3_0, pattern7_0)?;
-                        let expr1_0 = constructor_output_reg(ctx, expr0_0)?;
-                        return Some(expr1_0);
-                    }
-                }
-                &InstructionData::UnaryBool {
-                    opcode: ref pattern5_0,
-                    imm: pattern5_1,
-                } => {
-                    if let &Opcode::Bconst = pattern5_0 {
-                        if pattern5_1 == true {
-                            // Rule at src/isa/x64/lower.isle line 28.
-                            let expr0_0: u64 = 1;
-                            let expr1_0 = constructor_imm(ctx, pattern3_0, expr0_0)?;
-                            let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                            return Some(expr2_0);
-                        }
-                        if pattern5_1 == false {
-                            // Rule at src/isa/x64/lower.isle line 24.
-                            let expr0_0: u64 = 0;
-                            let expr1_0 = constructor_imm(ctx, pattern3_0, expr0_0)?;
-                            let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
-                            return Some(expr2_0);
-                        }
-                    }
-                }
-                &InstructionData::Binary {
-                    opcode: ref pattern5_0,
-                    args: ref pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Imin => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 1383.
-                            let expr0_0 = CC::L;
-                            let expr1_0 = constructor_cmp_and_choose(
-                                ctx, pattern3_0, &expr0_0, pattern7_0, pattern7_1,
-                            )?;
-                            let expr2_0 = C::output(ctx, expr1_0);
-                            return Some(expr2_0);
-                        }
-                        &Opcode::Umin => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 1377.
-                            let expr0_0 = CC::B;
-                            let expr1_0 = constructor_cmp_and_choose(
-                                ctx, pattern3_0, &expr0_0, pattern7_0, pattern7_1,
-                            )?;
-                            let expr2_0 = C::output(ctx, expr1_0);
-                            return Some(expr2_0);
-                        }
-                        &Opcode::Imax => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 1386.
-                            let expr0_0 = CC::NL;
-                            let expr1_0 = constructor_cmp_and_choose(
-                                ctx, pattern3_0, &expr0_0, pattern7_0, pattern7_1,
-                            )?;
-                            let expr2_0 = C::output(ctx, expr1_0);
-                            return Some(expr2_0);
-                        }
-                        &Opcode::Umax => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 1380.
-                            let expr0_0 = CC::NB;
-                            let expr1_0 = constructor_cmp_and_choose(
-                                ctx, pattern3_0, &expr0_0, pattern7_0, pattern7_1,
-                            )?;
-                            let expr2_0 = C::output(ctx, expr1_0);
-                            return Some(expr2_0);
-                        }
-                        &Opcode::Iadd => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            if let Some(pattern8_0) = C::simm32_from_value(ctx, pattern7_0) {
-                                // Rule at src/isa/x64/lower.isle line 74.
-                                let expr0_0 = constructor_put_in_gpr(ctx, pattern7_1)?;
-                                let expr1_0 =
-                                    constructor_add(ctx, pattern3_0, expr0_0, &pattern8_0)?;
-                                let expr2_0 = constructor_output_gpr(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            if let Some(pattern8_0) = C::sinkable_load(ctx, pattern7_0) {
-                                // Rule at src/isa/x64/lower.isle line 86.
-                                let expr0_0 = constructor_put_in_gpr(ctx, pattern7_1)?;
-                                let expr1_0 =
-                                    constructor_sink_load_to_gpr_mem_imm(ctx, &pattern8_0)?;
-                                let expr2_0 = constructor_add(ctx, pattern3_0, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_gpr(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            if let Some(pattern8_0) = C::simm32_from_value(ctx, pattern7_1) {
-                                // Rule at src/isa/x64/lower.isle line 70.
-                                let expr0_0 = constructor_put_in_gpr(ctx, pattern7_0)?;
-                                let expr1_0 =
-                                    constructor_add(ctx, pattern3_0, expr0_0, &pattern8_0)?;
-                                let expr2_0 = constructor_output_gpr(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            if let Some(pattern8_0) = C::sinkable_load(ctx, pattern7_1) {
-                                // Rule at src/isa/x64/lower.isle line 80.
-                                let expr0_0 = constructor_put_in_gpr(ctx, pattern7_0)?;
-                                let expr1_0 =
-                                    constructor_sink_load_to_gpr_mem_imm(ctx, &pattern8_0)?;
-                                let expr2_0 = constructor_add(ctx, pattern3_0, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_gpr(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            // Rule at src/isa/x64/lower.isle line 64.
-                            let expr0_0 = constructor_put_in_gpr(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_gpr_mem_imm(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_add(ctx, pattern3_0, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_gpr(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Isub => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            if let Some(pattern8_0) = C::simm32_from_value(ctx, pattern7_1) {
-                                // Rule at src/isa/x64/lower.isle line 228.
-                                let expr0_0 = constructor_put_in_gpr(ctx, pattern7_0)?;
-                                let expr1_0 =
-                                    constructor_sub(ctx, pattern3_0, expr0_0, &pattern8_0)?;
-                                let expr2_0 = constructor_output_gpr(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            if let Some(pattern8_0) = C::sinkable_load(ctx, pattern7_1) {
-                                // Rule at src/isa/x64/lower.isle line 233.
-                                let expr0_0 = constructor_put_in_gpr(ctx, pattern7_0)?;
-                                let expr1_0 =
-                                    constructor_sink_load_to_gpr_mem_imm(ctx, &pattern8_0)?;
-                                let expr2_0 = constructor_sub(ctx, pattern3_0, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_gpr(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            // Rule at src/isa/x64/lower.isle line 223.
-                            let expr0_0 = constructor_put_in_gpr(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_gpr_mem_imm(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_sub(ctx, pattern3_0, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_gpr(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Imul => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            if let Some(pattern8_0) = C::simm32_from_value(ctx, pattern7_0) {
-                                // Rule at src/isa/x64/lower.isle line 925.
-                                let expr0_0 = constructor_put_in_gpr(ctx, pattern7_1)?;
-                                let expr1_0 =
-                                    constructor_mul(ctx, pattern3_0, expr0_0, &pattern8_0)?;
-                                let expr2_0 = constructor_output_gpr(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            if let Some(pattern8_0) = C::sinkable_load(ctx, pattern7_0) {
-                                // Rule at src/isa/x64/lower.isle line 937.
-                                let expr0_0 = constructor_put_in_gpr(ctx, pattern7_1)?;
-                                let expr1_0 =
-                                    constructor_sink_load_to_gpr_mem_imm(ctx, &pattern8_0)?;
-                                let expr2_0 = constructor_mul(ctx, pattern3_0, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_gpr(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            if let Some(pattern8_0) = C::simm32_from_value(ctx, pattern7_1) {
-                                // Rule at src/isa/x64/lower.isle line 921.
-                                let expr0_0 = constructor_put_in_gpr(ctx, pattern7_0)?;
-                                let expr1_0 =
-                                    constructor_mul(ctx, pattern3_0, expr0_0, &pattern8_0)?;
-                                let expr2_0 = constructor_output_gpr(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            if let Some(pattern8_0) = C::sinkable_load(ctx, pattern7_1) {
-                                // Rule at src/isa/x64/lower.isle line 931.
-                                let expr0_0 = constructor_put_in_gpr(ctx, pattern7_0)?;
-                                let expr1_0 =
-                                    constructor_sink_load_to_gpr_mem_imm(ctx, &pattern8_0)?;
-                                let expr2_0 = constructor_mul(ctx, pattern3_0, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_gpr(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            // Rule at src/isa/x64/lower.isle line 916.
-                            let expr0_0 = constructor_put_in_gpr(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_gpr_mem_imm(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_mul(ctx, pattern3_0, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_gpr(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::IaddIfcout => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            if let Some(pattern8_0) = C::simm32_from_value(ctx, pattern7_0) {
-                                // Rule at src/isa/x64/lower.isle line 171.
-                                let expr0_0 = constructor_put_in_gpr(ctx, pattern7_1)?;
-                                let expr1_0 =
-                                    constructor_add(ctx, pattern3_0, expr0_0, &pattern8_0)?;
-                                let expr2_0 = C::gpr_to_reg(ctx, expr1_0);
-                                let expr3_0 = constructor_output_ifcout(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            if let Some(pattern8_0) = C::sinkable_load(ctx, pattern7_0) {
-                                // Rule at src/isa/x64/lower.isle line 181.
-                                let expr0_0 = constructor_put_in_gpr(ctx, pattern7_1)?;
-                                let expr1_0 =
-                                    constructor_sink_load_to_gpr_mem_imm(ctx, &pattern8_0)?;
-                                let expr2_0 = constructor_add(ctx, pattern3_0, expr0_0, &expr1_0)?;
-                                let expr3_0 = C::gpr_to_reg(ctx, expr2_0);
-                                let expr4_0 = constructor_output_ifcout(ctx, expr3_0)?;
-                                return Some(expr4_0);
-                            }
-                            if let Some(pattern8_0) = C::simm32_from_value(ctx, pattern7_1) {
-                                // Rule at src/isa/x64/lower.isle line 167.
-                                let expr0_0 = constructor_put_in_gpr(ctx, pattern7_0)?;
-                                let expr1_0 =
-                                    constructor_add(ctx, pattern3_0, expr0_0, &pattern8_0)?;
-                                let expr2_0 = C::gpr_to_reg(ctx, expr1_0);
-                                let expr3_0 = constructor_output_ifcout(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            if let Some(pattern8_0) = C::sinkable_load(ctx, pattern7_1) {
-                                // Rule at src/isa/x64/lower.isle line 177.
-                                let expr0_0 = constructor_put_in_gpr(ctx, pattern7_0)?;
-                                let expr1_0 =
-                                    constructor_sink_load_to_gpr_mem_imm(ctx, &pattern8_0)?;
-                                let expr2_0 = constructor_add(ctx, pattern3_0, expr0_0, &expr1_0)?;
-                                let expr3_0 = C::gpr_to_reg(ctx, expr2_0);
-                                let expr4_0 = constructor_output_ifcout(ctx, expr3_0)?;
-                                return Some(expr4_0);
-                            }
-                            // Rule at src/isa/x64/lower.isle line 161.
-                            let expr0_0 = constructor_put_in_gpr(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_gpr_mem_imm(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_add(ctx, pattern3_0, expr0_0, &expr1_0)?;
-                            let expr3_0 = C::gpr_to_reg(ctx, expr2_0);
-                            let expr4_0 = constructor_output_ifcout(ctx, expr3_0)?;
-                            return Some(expr4_0);
-                        }
-                        &Opcode::Band => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            if let Some(pattern8_0) = C::simm32_from_value(ctx, pattern7_0) {
-                                // Rule at src/isa/x64/lower.isle line 317.
-                                let expr0_0 = constructor_put_in_gpr(ctx, pattern7_1)?;
-                                let expr1_0 =
-                                    constructor_x64_and(ctx, pattern3_0, expr0_0, &pattern8_0)?;
-                                let expr2_0 = constructor_output_gpr(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            if let Some(pattern8_0) = C::sinkable_load(ctx, pattern7_0) {
-                                // Rule at src/isa/x64/lower.isle line 305.
-                                let expr0_0 = constructor_put_in_gpr(ctx, pattern7_1)?;
-                                let expr1_0 =
-                                    constructor_sink_load_to_gpr_mem_imm(ctx, &pattern8_0)?;
-                                let expr2_0 =
-                                    constructor_x64_and(ctx, pattern3_0, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_gpr(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            if let Some(pattern8_0) = C::simm32_from_value(ctx, pattern7_1) {
-                                // Rule at src/isa/x64/lower.isle line 313.
-                                let expr0_0 = constructor_put_in_gpr(ctx, pattern7_0)?;
-                                let expr1_0 =
-                                    constructor_x64_and(ctx, pattern3_0, expr0_0, &pattern8_0)?;
-                                let expr2_0 = constructor_output_gpr(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            if let Some(pattern8_0) = C::sinkable_load(ctx, pattern7_1) {
-                                // Rule at src/isa/x64/lower.isle line 300.
-                                let expr0_0 = constructor_put_in_gpr(ctx, pattern7_0)?;
-                                let expr1_0 =
-                                    constructor_sink_load_to_gpr_mem_imm(ctx, &pattern8_0)?;
-                                let expr2_0 =
-                                    constructor_x64_and(ctx, pattern3_0, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_gpr(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            // Rule at src/isa/x64/lower.isle line 295.
-                            let expr0_0 = constructor_put_in_gpr(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_gpr_mem_imm(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_x64_and(ctx, pattern3_0, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_gpr(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Bor => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            if let Some(pattern8_0) = C::simm32_from_value(ctx, pattern7_0) {
-                                // Rule at src/isa/x64/lower.isle line 381.
-                                let expr0_0 = constructor_put_in_gpr(ctx, pattern7_1)?;
-                                let expr1_0 =
-                                    constructor_or(ctx, pattern3_0, expr0_0, &pattern8_0)?;
-                                let expr2_0 = constructor_output_gpr(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            if let Some(pattern8_0) = C::sinkable_load(ctx, pattern7_0) {
-                                // Rule at src/isa/x64/lower.isle line 370.
-                                let expr0_0 = constructor_put_in_gpr(ctx, pattern7_1)?;
-                                let expr1_0 =
-                                    constructor_sink_load_to_gpr_mem_imm(ctx, &pattern8_0)?;
-                                let expr2_0 = constructor_or(ctx, pattern3_0, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_gpr(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            if let Some(pattern8_0) = C::simm32_from_value(ctx, pattern7_1) {
-                                // Rule at src/isa/x64/lower.isle line 377.
-                                let expr0_0 = constructor_put_in_gpr(ctx, pattern7_0)?;
-                                let expr1_0 =
-                                    constructor_or(ctx, pattern3_0, expr0_0, &pattern8_0)?;
-                                let expr2_0 = constructor_output_gpr(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            if let Some(pattern8_0) = C::sinkable_load(ctx, pattern7_1) {
-                                // Rule at src/isa/x64/lower.isle line 365.
-                                let expr0_0 = constructor_put_in_gpr(ctx, pattern7_0)?;
-                                let expr1_0 =
-                                    constructor_sink_load_to_gpr_mem_imm(ctx, &pattern8_0)?;
-                                let expr2_0 = constructor_or(ctx, pattern3_0, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_gpr(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            // Rule at src/isa/x64/lower.isle line 360.
-                            let expr0_0 = constructor_put_in_gpr(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_gpr_mem_imm(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_or(ctx, pattern3_0, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_gpr(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Bxor => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            if let Some(pattern8_0) = C::simm32_from_value(ctx, pattern7_0) {
-                                // Rule at src/isa/x64/lower.isle line 447.
-                                let expr0_0 = constructor_put_in_gpr(ctx, pattern7_1)?;
-                                let expr1_0 =
-                                    constructor_xor(ctx, pattern3_0, expr0_0, &pattern8_0)?;
-                                let expr2_0 = constructor_output_gpr(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            if let Some(pattern8_0) = C::sinkable_load(ctx, pattern7_0) {
-                                // Rule at src/isa/x64/lower.isle line 436.
-                                let expr0_0 = constructor_put_in_gpr(ctx, pattern7_1)?;
-                                let expr1_0 =
-                                    constructor_sink_load_to_gpr_mem_imm(ctx, &pattern8_0)?;
-                                let expr2_0 = constructor_xor(ctx, pattern3_0, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_gpr(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            if let Some(pattern8_0) = C::simm32_from_value(ctx, pattern7_1) {
-                                // Rule at src/isa/x64/lower.isle line 443.
-                                let expr0_0 = constructor_put_in_gpr(ctx, pattern7_0)?;
-                                let expr1_0 =
-                                    constructor_xor(ctx, pattern3_0, expr0_0, &pattern8_0)?;
-                                let expr2_0 = constructor_output_gpr(ctx, expr1_0)?;
-                                return Some(expr2_0);
-                            }
-                            if let Some(pattern8_0) = C::sinkable_load(ctx, pattern7_1) {
-                                // Rule at src/isa/x64/lower.isle line 431.
-                                let expr0_0 = constructor_put_in_gpr(ctx, pattern7_0)?;
-                                let expr1_0 =
-                                    constructor_sink_load_to_gpr_mem_imm(ctx, &pattern8_0)?;
-                                let expr2_0 = constructor_xor(ctx, pattern3_0, expr0_0, &expr1_0)?;
-                                let expr3_0 = constructor_output_gpr(ctx, expr2_0)?;
-                                return Some(expr3_0);
-                            }
-                            // Rule at src/isa/x64/lower.isle line 426.
-                            let expr0_0 = constructor_put_in_gpr(ctx, pattern7_0)?;
-                            let expr1_0 = constructor_put_in_gpr_mem_imm(ctx, pattern7_1)?;
-                            let expr2_0 = constructor_xor(ctx, pattern3_0, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_gpr(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Ishl => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 483.
-                            let expr0_0 = constructor_put_in_gpr(ctx, pattern7_0)?;
-                            let expr1_0 = C::put_masked_in_imm8_gpr(ctx, pattern7_1, pattern3_0);
-                            let expr2_0 = constructor_shl(ctx, pattern3_0, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_output_gpr(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Ushr => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 589.
-                            let expr0_0 = ExtendKind::Zero;
-                            let expr1_0 =
-                                constructor_extend_to_gpr(ctx, pattern7_0, pattern3_0, &expr0_0)?;
-                            let expr2_0 = C::put_masked_in_imm8_gpr(ctx, pattern7_1, pattern3_0);
-                            let expr3_0 = constructor_shr(ctx, pattern3_0, expr1_0, &expr2_0)?;
-                            let expr4_0 = constructor_output_gpr(ctx, expr3_0)?;
-                            return Some(expr4_0);
-                        }
-                        &Opcode::Sshr => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            // Rule at src/isa/x64/lower.isle line 691.
-                            let expr0_0 = ExtendKind::Sign;
-                            let expr1_0 =
-                                constructor_extend_to_gpr(ctx, pattern7_0, pattern3_0, &expr0_0)?;
-                            let expr2_0 = C::put_masked_in_imm8_gpr(ctx, pattern7_1, pattern3_0);
-                            let expr3_0 = constructor_sar(ctx, pattern3_0, expr1_0, &expr2_0)?;
-                            let expr4_0 = constructor_output_gpr(ctx, expr3_0)?;
-                            return Some(expr4_0);
-                        }
-                        _ => {}
-                    }
-                }
-                &InstructionData::Unary {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Ineg => {
-                            // Rule at src/isa/x64/lower.isle line 884.
-                            let expr0_0 = constructor_put_in_gpr(ctx, pattern5_1)?;
-                            let expr1_0 = constructor_neg(ctx, pattern3_0, expr0_0)?;
-                            let expr2_0 = constructor_output_gpr(ctx, expr1_0)?;
-                            return Some(expr2_0);
-                        }
-                        &Opcode::Bnot => {
-                            // Rule at src/isa/x64/lower.isle line 1253.
-                            let expr0_0 = constructor_put_in_gpr(ctx, pattern5_1)?;
-                            let expr1_0 = constructor_not(ctx, pattern3_0, expr0_0)?;
-                            let expr2_0 = constructor_output_gpr(ctx, expr1_0)?;
-                            return Some(expr2_0);
-                        }
-                        &Opcode::Breduce => {
-                            // Rule at src/isa/x64/lower.isle line 1987.
-                            let expr0_0 = C::put_in_regs(ctx, pattern5_1);
-                            let expr1_0: usize = 0;
-                            let expr2_0 = constructor_value_regs_get_gpr(ctx, expr0_0, expr1_0)?;
-                            let expr3_0 = constructor_output_gpr(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        &Opcode::Bint => {
-                            // Rule at src/isa/x64/lower.isle line 1995.
-                            let expr0_0 = constructor_put_in_gpr(ctx, pattern5_1)?;
-                            let expr1_0: u32 = 1;
-                            let expr2_0 = RegMemImm::Imm { simm32: expr1_0 };
-                            let expr3_0 = C::gpr_mem_imm_new(ctx, &expr2_0);
-                            let expr4_0 = constructor_x64_and(ctx, pattern3_0, expr0_0, &expr3_0)?;
-                            let expr5_0 = constructor_output_gpr(ctx, expr4_0)?;
-                            return Some(expr5_0);
-                        }
-                        &Opcode::Ireduce => {
-                            // Rule at src/isa/x64/lower.isle line 1979.
-                            let expr0_0 = C::put_in_regs(ctx, pattern5_1);
-                            let expr1_0: usize = 0;
-                            let expr2_0 = constructor_value_regs_get_gpr(ctx, expr0_0, expr1_0)?;
-                            let expr3_0 = constructor_output_gpr(ctx, expr2_0)?;
-                            return Some(expr3_0);
-                        }
-                        _ => {}
-                    }
-                }
-                &InstructionData::BinaryImm64 {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                    imm: pattern5_2,
-                } => {
-                    if let &Opcode::IaddImm = pattern5_0 {
-                        let pattern7_0 = C::u64_from_imm64(ctx, pattern5_2);
-                        // Rule at src/isa/x64/lower.isle line 196.
-                        let expr0_0 = constructor_put_in_gpr(ctx, pattern5_1)?;
-                        let expr1_0 = constructor_imm(ctx, pattern3_0, pattern7_0)?;
-                        let expr2_0 = constructor_reg_to_gpr_mem_imm(ctx, expr1_0)?;
-                        let expr3_0 = constructor_add(ctx, pattern3_0, expr0_0, &expr2_0)?;
-                        let expr4_0 = constructor_output_gpr(ctx, expr3_0)?;
-                        return Some(expr4_0);
-                    }
-                }
-                _ => {}
-            }
-        }
-        if let Some(pattern3_0) = C::ty_32_or_64(ctx, pattern2_0) {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            match &pattern4_0 {
-                &InstructionData::Binary {
-                    opcode: ref pattern5_0,
-                    args: ref pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Rotl => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
-                                let pattern9_0 = C::inst_data(ctx, pattern8_0);
-                                if let &InstructionData::UnaryImm {
-                                    opcode: ref pattern10_0,
-                                    imm: pattern10_1,
-                                } = &pattern9_0
-                                {
-                                    if let &Opcode::Iconst = pattern10_0 {
-                                        let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
-                                        // Rule at src/isa/x64/lower.isle line 823.
-                                        let expr0_0 = constructor_put_in_gpr(ctx, pattern7_0)?;
-                                        let expr1_0 = C::const_to_type_masked_imm8(
-                                            ctx,
-                                            pattern12_0,
-                                            pattern3_0,
-                                        );
-                                        let expr2_0 = constructor_x64_rotl(
-                                            ctx, pattern3_0, expr0_0, &expr1_0,
-                                        )?;
-                                        let expr3_0 = constructor_output_gpr(ctx, expr2_0)?;
-                                        return Some(expr3_0);
-                                    }
-                                }
-                            }
-                            // Rule at src/isa/x64/lower.isle line 817.
-                            let expr0_0 = constructor_lo_gpr(ctx, pattern7_1)?;
-                            let expr1_0 = constructor_put_in_gpr(ctx, pattern7_0)?;
-                            let expr2_0 = C::gpr_to_imm8_gpr(ctx, expr0_0);
-                            let expr3_0 = constructor_x64_rotl(ctx, pattern3_0, expr1_0, &expr2_0)?;
-                            let expr4_0 = constructor_output_gpr(ctx, expr3_0)?;
-                            return Some(expr4_0);
-                        }
-                        &Opcode::Rotr => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
-                                let pattern9_0 = C::inst_data(ctx, pattern8_0);
-                                if let &InstructionData::UnaryImm {
-                                    opcode: ref pattern10_0,
-                                    imm: pattern10_1,
-                                } = &pattern9_0
-                                {
-                                    if let &Opcode::Iconst = pattern10_0 {
-                                        let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
-                                        // Rule at src/isa/x64/lower.isle line 863.
-                                        let expr0_0 = constructor_put_in_gpr(ctx, pattern7_0)?;
-                                        let expr1_0 = C::const_to_type_masked_imm8(
-                                            ctx,
-                                            pattern12_0,
-                                            pattern3_0,
-                                        );
-                                        let expr2_0 = constructor_x64_rotr(
-                                            ctx, pattern3_0, expr0_0, &expr1_0,
-                                        )?;
-                                        let expr3_0 = constructor_output_gpr(ctx, expr2_0)?;
-                                        return Some(expr3_0);
-                                    }
-                                }
-                            }
-                            // Rule at src/isa/x64/lower.isle line 857.
-                            let expr0_0 = constructor_lo_gpr(ctx, pattern7_1)?;
-                            let expr1_0 = constructor_put_in_gpr(ctx, pattern7_0)?;
-                            let expr2_0 = C::gpr_to_imm8_gpr(ctx, expr0_0);
-                            let expr3_0 = constructor_x64_rotr(ctx, pattern3_0, expr1_0, &expr2_0)?;
-                            let expr4_0 = constructor_output_gpr(ctx, expr3_0)?;
-                            return Some(expr4_0);
-                        }
-                        _ => {}
-                    }
-                }
-                &InstructionData::Unary {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Clz => {
-                            // Rule at src/isa/x64/lower.isle line 1543.
-                            let expr0_0 = constructor_put_in_gpr(ctx, pattern5_1)?;
-                            let expr1_0 = constructor_do_clz(ctx, pattern3_0, pattern3_0, expr0_0)?;
-                            let expr2_0 = constructor_output_gpr(ctx, expr1_0)?;
-                            return Some(expr2_0);
-                        }
-                        &Opcode::Ctz => {
-                            // Rule at src/isa/x64/lower.isle line 1585.
-                            let expr0_0 = constructor_put_in_gpr(ctx, pattern5_1)?;
-                            let expr1_0 = constructor_do_ctz(ctx, pattern3_0, pattern3_0, expr0_0)?;
-                            let expr2_0 = constructor_output_gpr(ctx, expr1_0)?;
-                            return Some(expr2_0);
-                        }
-                        &Opcode::Popcnt => {
-                            // Rule at src/isa/x64/lower.isle line 1637.
-                            let expr0_0 = constructor_put_in_gpr(ctx, pattern5_1)?;
-                            let expr1_0 = constructor_do_popcnt(ctx, pattern3_0, expr0_0)?;
-                            let expr2_0 = constructor_output_gpr(ctx, expr1_0)?;
-                            return Some(expr2_0);
-                        }
-                        _ => {}
-                    }
-                }
-                _ => {}
-            }
-        }
-        if let Some(pattern3_0) = C::ty_8_or_16(ctx, pattern2_0) {
-            let pattern4_0 = C::inst_data(ctx, pattern0_0);
-            match &pattern4_0 {
-                &InstructionData::Binary {
-                    opcode: ref pattern5_0,
-                    args: ref pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Rotl => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
-                                let pattern9_0 = C::inst_data(ctx, pattern8_0);
-                                if let &InstructionData::UnaryImm {
-                                    opcode: ref pattern10_0,
-                                    imm: pattern10_1,
-                                } = &pattern9_0
-                                {
-                                    if let &Opcode::Iconst = pattern10_0 {
-                                        let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
-                                        // Rule at src/isa/x64/lower.isle line 809.
-                                        let expr0_0 = constructor_put_in_gpr(ctx, pattern7_0)?;
-                                        let expr1_0 = C::const_to_type_masked_imm8(
-                                            ctx,
-                                            pattern12_0,
-                                            pattern3_0,
-                                        );
-                                        let expr2_0 = constructor_x64_rotl(
-                                            ctx, pattern3_0, expr0_0, &expr1_0,
-                                        )?;
-                                        let expr3_0 = constructor_output_gpr(ctx, expr2_0)?;
-                                        return Some(expr3_0);
-                                    }
-                                }
-                            }
-                            // Rule at src/isa/x64/lower.isle line 805.
-                            let expr0_0: Type = I32;
-                            let expr1_0 = ExtendKind::Zero;
-                            let expr2_0 =
-                                constructor_extend_to_gpr(ctx, pattern7_1, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_put_in_gpr(ctx, pattern7_0)?;
-                            let expr4_0 = C::gpr_to_imm8_gpr(ctx, expr2_0);
-                            let expr5_0 = constructor_x64_rotl(ctx, pattern3_0, expr3_0, &expr4_0)?;
-                            let expr6_0 = constructor_output_gpr(ctx, expr5_0)?;
-                            return Some(expr6_0);
-                        }
-                        &Opcode::Rotr => {
-                            let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
-                            if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
-                                let pattern9_0 = C::inst_data(ctx, pattern8_0);
-                                if let &InstructionData::UnaryImm {
-                                    opcode: ref pattern10_0,
-                                    imm: pattern10_1,
-                                } = &pattern9_0
-                                {
-                                    if let &Opcode::Iconst = pattern10_0 {
-                                        let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
-                                        // Rule at src/isa/x64/lower.isle line 849.
-                                        let expr0_0 = constructor_put_in_gpr(ctx, pattern7_0)?;
-                                        let expr1_0 = C::const_to_type_masked_imm8(
-                                            ctx,
-                                            pattern12_0,
-                                            pattern3_0,
-                                        );
-                                        let expr2_0 = constructor_x64_rotr(
-                                            ctx, pattern3_0, expr0_0, &expr1_0,
-                                        )?;
-                                        let expr3_0 = constructor_output_gpr(ctx, expr2_0)?;
-                                        return Some(expr3_0);
-                                    }
-                                }
-                            }
-                            // Rule at src/isa/x64/lower.isle line 845.
-                            let expr0_0: Type = I32;
-                            let expr1_0 = ExtendKind::Zero;
-                            let expr2_0 =
-                                constructor_extend_to_gpr(ctx, pattern7_1, expr0_0, &expr1_0)?;
-                            let expr3_0 = constructor_put_in_gpr(ctx, pattern7_0)?;
-                            let expr4_0 = C::gpr_to_imm8_gpr(ctx, expr2_0);
-                            let expr5_0 = constructor_x64_rotr(ctx, pattern3_0, expr3_0, &expr4_0)?;
-                            let expr6_0 = constructor_output_gpr(ctx, expr5_0)?;
-                            return Some(expr6_0);
-                        }
-                        _ => {}
-                    }
-                }
-                &InstructionData::Unary {
-                    opcode: ref pattern5_0,
-                    arg: pattern5_1,
-                } => {
-                    match pattern5_0 {
-                        &Opcode::Clz => {
-                            // Rule at src/isa/x64/lower.isle line 1548.
-                            let expr0_0: Type = I32;
-                            let expr1_0: Type = I32;
-                            let expr2_0 = ExtendKind::Zero;
-                            let expr3_0 =
-                                constructor_extend_to_gpr(ctx, pattern5_1, expr1_0, &expr2_0)?;
-                            let expr4_0 = constructor_do_clz(ctx, expr0_0, pattern3_0, expr3_0)?;
-                            let expr5_0 = constructor_output_gpr(ctx, expr4_0)?;
-                            return Some(expr5_0);
-                        }
-                        &Opcode::Ctz => {
-                            // Rule at src/isa/x64/lower.isle line 1590.
-                            let expr0_0: Type = I32;
-                            let expr1_0: Type = I32;
-                            let expr2_0 = ExtendKind::Zero;
-                            let expr3_0 =
-                                constructor_extend_to_gpr(ctx, pattern5_1, expr1_0, &expr2_0)?;
-                            let expr4_0 = constructor_do_ctz(ctx, expr0_0, pattern3_0, expr3_0)?;
-                            let expr5_0 = constructor_output_gpr(ctx, expr4_0)?;
-                            return Some(expr5_0);
-                        }
-                        &Opcode::Popcnt => {
-                            // Rule at src/isa/x64/lower.isle line 1642.
-                            let expr0_0: Type = I32;
-                            let expr1_0: Type = I32;
-                            let expr2_0 = ExtendKind::Zero;
-                            let expr3_0 =
-                                constructor_extend_to_gpr(ctx, pattern5_1, expr1_0, &expr2_0)?;
-                            let expr4_0 = constructor_do_popcnt(ctx, expr0_0, expr3_0)?;
-                            let expr5_0 = constructor_output_gpr(ctx, expr4_0)?;
-                            return Some(expr5_0);
-                        }
-                        _ => {}
-                    }
-                }
-                _ => {}
-            }
-        }
-    }
-    return None;
-}
-
-// Generated as internal constructor for term output_ifcout.
-pub fn constructor_output_ifcout<C: Context>(ctx: &mut C, arg0: Reg) -> Option<InstOutput> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/x64/lower.isle line 157.
-    let expr0_0 = C::value_reg(ctx, pattern0_0);
-    let expr1_0 = C::value_regs_invalid(ctx);
-    let expr2_0 = C::output_pair(ctx, expr0_0, expr1_0);
-    return Some(expr2_0);
-}
-
-// Generated as internal constructor for term sse_and.
-pub fn constructor_sse_and<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Xmm,
-    arg2: &XmmMem,
-) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == F32X4 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/x64/lower.isle line 324.
-        let expr0_0 = constructor_andps(ctx, pattern2_0, pattern3_0)?;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == F64X2 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/x64/lower.isle line 325.
-        let expr0_0 = constructor_andpd(ctx, pattern2_0, pattern3_0)?;
-        return Some(expr0_0);
-    }
-    if let Some((pattern1_0, pattern1_1)) = C::multi_lane(ctx, pattern0_0) {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/x64/lower.isle line 326.
-        let expr0_0 = constructor_pand(ctx, pattern2_0, pattern3_0)?;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term sse_or.
-pub fn constructor_sse_or<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Xmm,
-    arg2: &XmmMem,
-) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == F32X4 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/x64/lower.isle line 388.
-        let expr0_0 = constructor_orps(ctx, pattern2_0, pattern3_0)?;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == F64X2 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/x64/lower.isle line 389.
-        let expr0_0 = constructor_orpd(ctx, pattern2_0, pattern3_0)?;
-        return Some(expr0_0);
-    }
-    if let Some((pattern1_0, pattern1_1)) = C::multi_lane(ctx, pattern0_0) {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/x64/lower.isle line 390.
-        let expr0_0 = constructor_por(ctx, pattern2_0, pattern3_0)?;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term or_i128.
-pub fn constructor_or_i128<C: Context>(
-    ctx: &mut C,
-    arg0: ValueRegs,
-    arg1: ValueRegs,
-) -> Option<ValueRegs> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/lower.isle line 399.
-    let expr0_0: usize = 0;
-    let expr1_0 = constructor_value_regs_get_gpr(ctx, pattern0_0, expr0_0)?;
-    let expr2_0: usize = 1;
-    let expr3_0 = constructor_value_regs_get_gpr(ctx, pattern0_0, expr2_0)?;
-    let expr4_0: usize = 0;
-    let expr5_0 = constructor_value_regs_get_gpr(ctx, pattern1_0, expr4_0)?;
-    let expr6_0: usize = 1;
-    let expr7_0 = constructor_value_regs_get_gpr(ctx, pattern1_0, expr6_0)?;
-    let expr8_0: Type = I64;
-    let expr9_0 = C::gpr_to_gpr_mem_imm(ctx, expr5_0);
-    let expr10_0 = constructor_or(ctx, expr8_0, expr1_0, &expr9_0)?;
-    let expr11_0: Type = I64;
-    let expr12_0 = C::gpr_to_gpr_mem_imm(ctx, expr7_0);
-    let expr13_0 = constructor_or(ctx, expr11_0, expr3_0, &expr12_0)?;
-    let expr14_0 = constructor_value_gprs(ctx, expr10_0, expr13_0)?;
-    return Some(expr14_0);
-}
-
-// Generated as internal constructor for term shl_i128.
-pub fn constructor_shl_i128<C: Context>(
-    ctx: &mut C,
-    arg0: ValueRegs,
-    arg1: Gpr,
-) -> Option<ValueRegs> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/lower.isle line 489.
-    let expr0_0: usize = 0;
-    let expr1_0 = constructor_value_regs_get_gpr(ctx, pattern0_0, expr0_0)?;
-    let expr2_0: usize = 1;
-    let expr3_0 = constructor_value_regs_get_gpr(ctx, pattern0_0, expr2_0)?;
-    let expr4_0: Type = I64;
-    let expr5_0 = C::gpr_to_imm8_gpr(ctx, pattern1_0);
-    let expr6_0 = constructor_shl(ctx, expr4_0, expr1_0, &expr5_0)?;
-    let expr7_0: Type = I64;
-    let expr8_0 = C::gpr_to_imm8_gpr(ctx, pattern1_0);
-    let expr9_0 = constructor_shl(ctx, expr7_0, expr3_0, &expr8_0)?;
-    let expr10_0: Type = I64;
-    let expr11_0: Type = I64;
-    let expr12_0: Type = I64;
-    let expr13_0: u64 = 64;
-    let expr14_0 = constructor_imm(ctx, expr12_0, expr13_0)?;
-    let expr15_0 = C::gpr_new(ctx, expr14_0);
-    let expr16_0 = C::gpr_to_gpr_mem_imm(ctx, pattern1_0);
-    let expr17_0 = constructor_sub(ctx, expr11_0, expr15_0, &expr16_0)?;
-    let expr18_0 = C::gpr_to_imm8_gpr(ctx, expr17_0);
-    let expr19_0 = constructor_shr(ctx, expr10_0, expr1_0, &expr18_0)?;
-    let expr20_0: Type = I64;
-    let expr21_0: u64 = 0;
-    let expr22_0 = constructor_imm(ctx, expr20_0, expr21_0)?;
-    let expr23_0 = C::gpr_new(ctx, expr22_0);
-    let expr24_0 = OperandSize::Size64;
-    let expr25_0: u32 = 127;
-    let expr26_0 = RegMemImm::Imm { simm32: expr25_0 };
-    let expr27_0 = C::gpr_mem_imm_new(ctx, &expr26_0);
-    let expr28_0 = constructor_test(ctx, &expr24_0, &expr27_0, pattern1_0)?;
-    let expr29_0: Type = I64;
-    let expr30_0 = CC::Z;
-    let expr31_0 = C::gpr_to_gpr_mem(ctx, expr23_0);
-    let expr32_0 = constructor_cmove(ctx, expr29_0, &expr30_0, &expr31_0, expr19_0)?;
-    let expr33_0 = constructor_with_flags_reg(ctx, &expr28_0, &expr32_0)?;
-    let expr34_0 = C::gpr_new(ctx, expr33_0);
-    let expr35_0: Type = I64;
-    let expr36_0 = C::gpr_to_gpr_mem_imm(ctx, expr9_0);
-    let expr37_0 = constructor_or(ctx, expr35_0, expr34_0, &expr36_0)?;
-    let expr38_0 = OperandSize::Size64;
-    let expr39_0: u32 = 64;
-    let expr40_0 = RegMemImm::Imm { simm32: expr39_0 };
-    let expr41_0 = C::gpr_mem_imm_new(ctx, &expr40_0);
-    let expr42_0 = constructor_test(ctx, &expr38_0, &expr41_0, pattern1_0)?;
-    let expr43_0: Type = I64;
-    let expr44_0 = CC::Z;
-    let expr45_0 = C::gpr_to_gpr_mem(ctx, expr6_0);
-    let expr46_0 = constructor_cmove(ctx, expr43_0, &expr44_0, &expr45_0, expr23_0)?;
-    let expr47_0: Type = I64;
-    let expr48_0 = CC::Z;
-    let expr49_0 = C::gpr_to_gpr_mem(ctx, expr37_0);
-    let expr50_0 = constructor_cmove(ctx, expr47_0, &expr48_0, &expr49_0, expr6_0)?;
-    let expr51_0 = constructor_consumes_flags_concat(ctx, &expr46_0, &expr50_0)?;
-    let expr52_0 = constructor_with_flags(ctx, &expr42_0, &expr51_0)?;
-    return Some(expr52_0);
-}
-
-// Generated as internal constructor for term ishl_i8x16_mask.
-pub fn constructor_ishl_i8x16_mask<C: Context>(
-    ctx: &mut C,
-    arg0: &RegMemImm,
-) -> Option<SyntheticAmode> {
-    let pattern0_0 = arg0;
-    match pattern0_0 {
-        &RegMemImm::Imm { simm32: pattern1_0 } => {
-            // Rule at src/isa/x64/lower.isle line 552.
-            let expr0_0 = C::ishl_i8x16_mask_for_const(ctx, pattern1_0);
-            return Some(expr0_0);
-        }
-        &RegMemImm::Reg { reg: pattern1_0 } => {
-            // Rule at src/isa/x64/lower.isle line 561.
-            let expr0_0 = C::ishl_i8x16_mask_table(ctx);
-            let expr1_0 = constructor_lea(ctx, &expr0_0)?;
-            let expr2_0: Type = I64;
-            let expr3_0 = C::gpr_new(ctx, pattern1_0);
-            let expr4_0: u8 = 4;
-            let expr5_0 = C::imm8_to_imm8_gpr(ctx, expr4_0);
-            let expr6_0 = constructor_shl(ctx, expr2_0, expr3_0, &expr5_0)?;
-            let expr7_0: u32 = 0;
-            let expr8_0: u8 = 0;
-            let expr9_0 = C::amode_imm_reg_reg_shift(ctx, expr7_0, expr1_0, expr6_0, expr8_0);
-            let expr10_0 = C::amode_to_synthetic_amode(ctx, &expr9_0);
-            return Some(expr10_0);
-        }
-        &RegMemImm::Mem {
-            addr: ref pattern1_0,
-        } => {
-            // Rule at src/isa/x64/lower.isle line 571.
-            let expr0_0: Type = I64;
-            let expr1_0 = ExtKind::None;
-            let expr2_0 = constructor_x64_load(ctx, expr0_0, pattern1_0, &expr1_0)?;
-            let expr3_0 = RegMemImm::Reg { reg: expr2_0 };
-            let expr4_0 = constructor_ishl_i8x16_mask(ctx, &expr3_0)?;
-            return Some(expr4_0);
-        }
-        _ => {}
-    }
-    return None;
-}
-
-// Generated as internal constructor for term shr_i128.
-pub fn constructor_shr_i128<C: Context>(
-    ctx: &mut C,
-    arg0: ValueRegs,
-    arg1: Gpr,
-) -> Option<ValueRegs> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/lower.isle line 596.
-    let expr0_0: usize = 0;
-    let expr1_0 = constructor_value_regs_get_gpr(ctx, pattern0_0, expr0_0)?;
-    let expr2_0: usize = 1;
-    let expr3_0 = constructor_value_regs_get_gpr(ctx, pattern0_0, expr2_0)?;
-    let expr4_0: Type = I64;
-    let expr5_0 = C::gpr_to_imm8_gpr(ctx, pattern1_0);
-    let expr6_0 = constructor_shr(ctx, expr4_0, expr1_0, &expr5_0)?;
-    let expr7_0: Type = I64;
-    let expr8_0 = C::gpr_to_imm8_gpr(ctx, pattern1_0);
-    let expr9_0 = constructor_shr(ctx, expr7_0, expr3_0, &expr8_0)?;
-    let expr10_0: Type = I64;
-    let expr11_0: Type = I64;
-    let expr12_0: Type = I64;
-    let expr13_0: u64 = 64;
-    let expr14_0 = constructor_imm(ctx, expr12_0, expr13_0)?;
-    let expr15_0 = C::gpr_new(ctx, expr14_0);
-    let expr16_0 = C::gpr_to_gpr_mem_imm(ctx, pattern1_0);
-    let expr17_0 = constructor_sub(ctx, expr11_0, expr15_0, &expr16_0)?;
-    let expr18_0 = C::gpr_to_imm8_gpr(ctx, expr17_0);
-    let expr19_0 = constructor_shl(ctx, expr10_0, expr3_0, &expr18_0)?;
-    let expr20_0 = OperandSize::Size64;
-    let expr21_0: u32 = 127;
-    let expr22_0 = RegMemImm::Imm { simm32: expr21_0 };
-    let expr23_0 = C::gpr_mem_imm_new(ctx, &expr22_0);
-    let expr24_0 = constructor_test(ctx, &expr20_0, &expr23_0, pattern1_0)?;
-    let expr25_0: Type = I64;
-    let expr26_0 = CC::Z;
-    let expr27_0: Type = I64;
-    let expr28_0: u64 = 0;
-    let expr29_0 = constructor_imm(ctx, expr27_0, expr28_0)?;
-    let expr30_0 = C::reg_to_gpr_mem(ctx, expr29_0);
-    let expr31_0 = constructor_cmove(ctx, expr25_0, &expr26_0, &expr30_0, expr19_0)?;
-    let expr32_0 = constructor_with_flags_reg(ctx, &expr24_0, &expr31_0)?;
-    let expr33_0 = C::gpr_new(ctx, expr32_0);
-    let expr34_0: Type = I64;
-    let expr35_0 = C::gpr_to_gpr_mem_imm(ctx, expr6_0);
-    let expr36_0 = constructor_or(ctx, expr34_0, expr33_0, &expr35_0)?;
-    let expr37_0 = OperandSize::Size64;
-    let expr38_0: u32 = 64;
-    let expr39_0 = RegMemImm::Imm { simm32: expr38_0 };
-    let expr40_0 = C::gpr_mem_imm_new(ctx, &expr39_0);
-    let expr41_0 = constructor_test(ctx, &expr37_0, &expr40_0, pattern1_0)?;
-    let expr42_0: Type = I64;
-    let expr43_0 = CC::Z;
-    let expr44_0 = C::gpr_to_gpr_mem(ctx, expr36_0);
-    let expr45_0 = constructor_cmove(ctx, expr42_0, &expr43_0, &expr44_0, expr9_0)?;
-    let expr46_0: Type = I64;
-    let expr47_0 = CC::Z;
-    let expr48_0 = C::gpr_to_gpr_mem(ctx, expr9_0);
-    let expr49_0: Type = I64;
-    let expr50_0: u64 = 0;
-    let expr51_0 = constructor_imm(ctx, expr49_0, expr50_0)?;
-    let expr52_0 = C::gpr_new(ctx, expr51_0);
-    let expr53_0 = constructor_cmove(ctx, expr46_0, &expr47_0, &expr48_0, expr52_0)?;
-    let expr54_0 = constructor_consumes_flags_concat(ctx, &expr45_0, &expr53_0)?;
-    let expr55_0 = constructor_with_flags(ctx, &expr41_0, &expr54_0)?;
-    return Some(expr55_0);
-}
-
-// Generated as internal constructor for term ushr_i8x16_mask.
-pub fn constructor_ushr_i8x16_mask<C: Context>(
-    ctx: &mut C,
-    arg0: &RegMemImm,
-) -> Option<SyntheticAmode> {
-    let pattern0_0 = arg0;
-    match pattern0_0 {
-        &RegMemImm::Imm { simm32: pattern1_0 } => {
-            // Rule at src/isa/x64/lower.isle line 653.
-            let expr0_0 = C::ushr_i8x16_mask_for_const(ctx, pattern1_0);
-            return Some(expr0_0);
-        }
-        &RegMemImm::Reg { reg: pattern1_0 } => {
-            // Rule at src/isa/x64/lower.isle line 662.
-            let expr0_0 = C::ushr_i8x16_mask_table(ctx);
-            let expr1_0 = constructor_lea(ctx, &expr0_0)?;
-            let expr2_0: Type = I64;
-            let expr3_0 = C::gpr_new(ctx, pattern1_0);
-            let expr4_0: u8 = 4;
-            let expr5_0 = C::imm8_to_imm8_gpr(ctx, expr4_0);
-            let expr6_0 = constructor_shl(ctx, expr2_0, expr3_0, &expr5_0)?;
-            let expr7_0: u32 = 0;
-            let expr8_0: u8 = 0;
-            let expr9_0 = C::amode_imm_reg_reg_shift(ctx, expr7_0, expr1_0, expr6_0, expr8_0);
-            let expr10_0 = C::amode_to_synthetic_amode(ctx, &expr9_0);
-            return Some(expr10_0);
-        }
-        &RegMemImm::Mem {
-            addr: ref pattern1_0,
-        } => {
-            // Rule at src/isa/x64/lower.isle line 673.
-            let expr0_0: Type = I64;
-            let expr1_0 = ExtKind::None;
-            let expr2_0 = constructor_x64_load(ctx, expr0_0, pattern1_0, &expr1_0)?;
-            let expr3_0 = RegMemImm::Reg { reg: expr2_0 };
-            let expr4_0 = constructor_ushr_i8x16_mask(ctx, &expr3_0)?;
-            return Some(expr4_0);
-        }
-        _ => {}
-    }
-    return None;
-}
-
-// Generated as internal constructor for term sar_i128.
-pub fn constructor_sar_i128<C: Context>(
-    ctx: &mut C,
-    arg0: ValueRegs,
-    arg1: Gpr,
-) -> Option<ValueRegs> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/lower.isle line 698.
-    let expr0_0: usize = 0;
-    let expr1_0 = constructor_value_regs_get_gpr(ctx, pattern0_0, expr0_0)?;
-    let expr2_0: usize = 1;
-    let expr3_0 = constructor_value_regs_get_gpr(ctx, pattern0_0, expr2_0)?;
-    let expr4_0: Type = I64;
-    let expr5_0 = C::gpr_to_imm8_gpr(ctx, pattern1_0);
-    let expr6_0 = constructor_shr(ctx, expr4_0, expr1_0, &expr5_0)?;
-    let expr7_0: Type = I64;
-    let expr8_0 = C::gpr_to_imm8_gpr(ctx, pattern1_0);
-    let expr9_0 = constructor_sar(ctx, expr7_0, expr3_0, &expr8_0)?;
-    let expr10_0: Type = I64;
-    let expr11_0: Type = I64;
-    let expr12_0: Type = I64;
-    let expr13_0: u64 = 64;
-    let expr14_0 = constructor_imm(ctx, expr12_0, expr13_0)?;
-    let expr15_0 = C::gpr_new(ctx, expr14_0);
-    let expr16_0 = C::gpr_to_gpr_mem_imm(ctx, pattern1_0);
-    let expr17_0 = constructor_sub(ctx, expr11_0, expr15_0, &expr16_0)?;
-    let expr18_0 = C::gpr_to_imm8_gpr(ctx, expr17_0);
-    let expr19_0 = constructor_shl(ctx, expr10_0, expr3_0, &expr18_0)?;
-    let expr20_0 = OperandSize::Size64;
-    let expr21_0: u32 = 127;
-    let expr22_0 = RegMemImm::Imm { simm32: expr21_0 };
-    let expr23_0 = C::gpr_mem_imm_new(ctx, &expr22_0);
-    let expr24_0 = constructor_test(ctx, &expr20_0, &expr23_0, pattern1_0)?;
-    let expr25_0: Type = I64;
-    let expr26_0 = CC::Z;
-    let expr27_0: Type = I64;
-    let expr28_0: u64 = 0;
-    let expr29_0 = constructor_imm(ctx, expr27_0, expr28_0)?;
-    let expr30_0 = C::reg_to_gpr_mem(ctx, expr29_0);
-    let expr31_0 = constructor_cmove(ctx, expr25_0, &expr26_0, &expr30_0, expr19_0)?;
-    let expr32_0 = constructor_with_flags_reg(ctx, &expr24_0, &expr31_0)?;
-    let expr33_0 = C::gpr_new(ctx, expr32_0);
-    let expr34_0: Type = I64;
-    let expr35_0 = C::gpr_to_gpr_mem_imm(ctx, expr33_0);
-    let expr36_0 = constructor_or(ctx, expr34_0, expr6_0, &expr35_0)?;
-    let expr37_0: Type = I64;
-    let expr38_0: u8 = 63;
-    let expr39_0 = C::imm8_to_imm8_gpr(ctx, expr38_0);
-    let expr40_0 = constructor_sar(ctx, expr37_0, expr3_0, &expr39_0)?;
-    let expr41_0 = OperandSize::Size64;
-    let expr42_0: u32 = 64;
-    let expr43_0 = RegMemImm::Imm { simm32: expr42_0 };
-    let expr44_0 = C::gpr_mem_imm_new(ctx, &expr43_0);
-    let expr45_0 = constructor_test(ctx, &expr41_0, &expr44_0, pattern1_0)?;
-    let expr46_0: Type = I64;
-    let expr47_0 = CC::Z;
-    let expr48_0 = C::gpr_to_gpr_mem(ctx, expr36_0);
-    let expr49_0 = constructor_cmove(ctx, expr46_0, &expr47_0, &expr48_0, expr9_0)?;
-    let expr50_0: Type = I64;
-    let expr51_0 = CC::Z;
-    let expr52_0 = C::gpr_to_gpr_mem(ctx, expr9_0);
-    let expr53_0 = constructor_cmove(ctx, expr50_0, &expr51_0, &expr52_0, expr40_0)?;
-    let expr54_0 = constructor_consumes_flags_concat(ctx, &expr49_0, &expr53_0)?;
-    let expr55_0 = constructor_with_flags(ctx, &expr45_0, &expr54_0)?;
-    return Some(expr55_0);
-}
-
-// Generated as internal constructor for term sshr_i8x16_bigger_shift.
-pub fn constructor_sshr_i8x16_bigger_shift<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &RegMemImm,
-) -> Option<XmmMemImm> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    match pattern1_0 {
-        &RegMemImm::Imm { simm32: pattern2_0 } => {
-            // Rule at src/isa/x64/lower.isle line 762.
-            let expr0_0: u32 = 8;
-            let expr1_0 = C::u32_add(ctx, pattern2_0, expr0_0);
-            let expr2_0 = RegMemImm::Imm { simm32: expr1_0 };
-            let expr3_0 = C::xmm_mem_imm_new(ctx, &expr2_0);
-            return Some(expr3_0);
-        }
-        &RegMemImm::Reg { reg: pattern2_0 } => {
-            // Rule at src/isa/x64/lower.isle line 764.
-            let expr0_0 = C::gpr_new(ctx, pattern2_0);
-            let expr1_0: u32 = 8;
-            let expr2_0 = RegMemImm::Imm { simm32: expr1_0 };
-            let expr3_0 = C::gpr_mem_imm_new(ctx, &expr2_0);
-            let expr4_0 = constructor_add(ctx, pattern0_0, expr0_0, &expr3_0)?;
-            let expr5_0 = C::gpr_to_reg(ctx, expr4_0);
-            let expr6_0 = RegMemImm::Reg { reg: expr5_0 };
-            let expr7_0 = constructor_mov_rmi_to_xmm(ctx, &expr6_0)?;
-            return Some(expr7_0);
-        }
-        &RegMemImm::Mem {
-            addr: ref pattern2_0,
-        } => {
-            // Rule at src/isa/x64/lower.isle line 768.
-            let expr0_0: u64 = 8;
-            let expr1_0 = constructor_imm(ctx, pattern0_0, expr0_0)?;
-            let expr2_0 = C::gpr_new(ctx, expr1_0);
-            let expr3_0 = C::gpr_mem_imm_new(ctx, pattern1_0);
-            let expr4_0 = constructor_add(ctx, pattern0_0, expr2_0, &expr3_0)?;
-            let expr5_0 = C::gpr_to_reg(ctx, expr4_0);
-            let expr6_0 = RegMemImm::Reg { reg: expr5_0 };
-            let expr7_0 = constructor_mov_rmi_to_xmm(ctx, &expr6_0)?;
-            return Some(expr7_0);
-        }
-        _ => {}
-    }
-    return None;
-}
-
-// Generated as internal constructor for term sse_and_not.
-pub fn constructor_sse_and_not<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Xmm,
-    arg2: &XmmMem,
-) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == F32X4 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/x64/lower.isle line 1194.
-        let expr0_0 = constructor_andnps(ctx, pattern2_0, pattern3_0)?;
-        return Some(expr0_0);
-    }
-    if pattern0_0 == F64X2 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/x64/lower.isle line 1195.
-        let expr0_0 = constructor_andnpd(ctx, pattern2_0, pattern3_0)?;
-        return Some(expr0_0);
-    }
-    if let Some((pattern1_0, pattern1_1)) = C::multi_lane(ctx, pattern0_0) {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        // Rule at src/isa/x64/lower.isle line 1196.
-        let expr0_0 = constructor_pandn(ctx, pattern2_0, pattern3_0)?;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term i128_not.
-pub fn constructor_i128_not<C: Context>(ctx: &mut C, arg0: Value) -> Option<ValueRegs> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/x64/lower.isle line 1259.
-    let expr0_0 = C::put_in_regs(ctx, pattern0_0);
-    let expr1_0: usize = 0;
-    let expr2_0 = constructor_value_regs_get_gpr(ctx, expr0_0, expr1_0)?;
-    let expr3_0: usize = 1;
-    let expr4_0 = constructor_value_regs_get_gpr(ctx, expr0_0, expr3_0)?;
-    let expr5_0: Type = I64;
-    let expr6_0 = constructor_not(ctx, expr5_0, expr2_0)?;
-    let expr7_0: Type = I64;
-    let expr8_0 = constructor_not(ctx, expr7_0, expr4_0)?;
-    let expr9_0 = constructor_value_gprs(ctx, expr6_0, expr8_0)?;
-    return Some(expr9_0);
-}
-
-// Generated as internal constructor for term vec_insert_lane.
-pub fn constructor_vec_insert_lane<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Xmm,
-    arg2: &RegMem,
-    arg3: u8,
-) -> Option<Xmm> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I8X16 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/x64/lower.isle line 1313.
-        let expr0_0 = C::reg_mem_to_gpr_mem(ctx, pattern3_0);
-        let expr1_0 = constructor_pinsrb(ctx, pattern2_0, &expr0_0, pattern4_0)?;
-        return Some(expr1_0);
-    }
-    if pattern0_0 == I16X8 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/x64/lower.isle line 1317.
-        let expr0_0 = C::reg_mem_to_gpr_mem(ctx, pattern3_0);
-        let expr1_0 = constructor_pinsrw(ctx, pattern2_0, &expr0_0, pattern4_0)?;
-        return Some(expr1_0);
-    }
-    if pattern0_0 == I32X4 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/x64/lower.isle line 1321.
-        let expr0_0 = C::reg_mem_to_gpr_mem(ctx, pattern3_0);
-        let expr1_0 = OperandSize::Size32;
-        let expr2_0 = constructor_pinsrd(ctx, pattern2_0, &expr0_0, pattern4_0, &expr1_0)?;
-        return Some(expr2_0);
-    }
-    if pattern0_0 == I64X2 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/x64/lower.isle line 1325.
-        let expr0_0 = C::reg_mem_to_gpr_mem(ctx, pattern3_0);
-        let expr1_0 = OperandSize::Size64;
-        let expr2_0 = constructor_pinsrd(ctx, pattern2_0, &expr0_0, pattern4_0, &expr1_0)?;
-        return Some(expr2_0);
-    }
-    if pattern0_0 == F32X4 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/x64/lower.isle line 1329.
-        let expr0_0 = C::reg_mem_to_xmm_mem(ctx, pattern3_0);
-        let expr1_0 = C::sse_insertps_lane_imm(ctx, pattern4_0);
-        let expr2_0 = constructor_insertps(ctx, pattern2_0, &expr0_0, expr1_0)?;
-        return Some(expr2_0);
-    }
-    if pattern0_0 == F64X2 {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        if let &RegMem::Reg { reg: pattern4_0 } = pattern3_0 {
-            let pattern5_0 = arg3;
-            if pattern5_0 == 0 {
-                // Rule at src/isa/x64/lower.isle line 1351.
-                let expr0_0 = constructor_reg_to_xmm_mem(ctx, pattern4_0)?;
-                let expr1_0 = constructor_movsd(ctx, pattern2_0, &expr0_0)?;
-                return Some(expr1_0);
-            }
-        }
-        let pattern4_0 = arg3;
-        if pattern4_0 == 0 {
-            // Rule at src/isa/x64/lower.isle line 1353.
-            let expr0_0 = SseOpcode::Movsd;
-            let expr1_0 = C::reg_mem_to_xmm_mem(ctx, pattern3_0);
-            let expr2_0 = constructor_xmm_unary_rm_r(ctx, &expr0_0, &expr1_0)?;
-            let expr3_0 = C::xmm_to_xmm_mem(ctx, expr2_0);
-            let expr4_0 = constructor_movsd(ctx, pattern2_0, &expr3_0)?;
-            return Some(expr4_0);
-        }
-        if pattern4_0 == 1 {
-            // Rule at src/isa/x64/lower.isle line 1362.
-            let expr0_0 = C::reg_mem_to_xmm_mem(ctx, pattern3_0);
-            let expr1_0 = constructor_movlhps(ctx, pattern2_0, &expr0_0)?;
-            return Some(expr1_0);
-        }
-    }
-    return None;
-}
-
-// Generated as internal constructor for term cmp_and_choose.
-pub fn constructor_cmp_and_choose<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: &CC,
-    arg2: Value,
-    arg3: Value,
-) -> Option<ValueRegs> {
-    let pattern0_0 = arg0;
-    if let Some(pattern1_0) = C::fits_in_64(ctx, pattern0_0) {
-        let pattern2_0 = arg1;
-        let pattern3_0 = arg2;
-        let pattern4_0 = arg3;
-        // Rule at src/isa/x64/lower.isle line 1370.
-        let expr0_0 = constructor_put_in_gpr(ctx, pattern3_0)?;
-        let expr1_0 = constructor_put_in_gpr(ctx, pattern4_0)?;
-        let expr2_0 = C::raw_operand_size_of_type(ctx, pattern1_0);
-        let expr3_0 = C::gpr_to_gpr_mem_imm(ctx, expr0_0);
-        let expr4_0 = constructor_cmp(ctx, &expr2_0, &expr3_0, expr1_0)?;
-        let expr5_0 = C::gpr_to_gpr_mem(ctx, expr1_0);
-        let expr6_0 = constructor_cmove(ctx, pattern1_0, pattern2_0, &expr5_0, expr0_0)?;
-        let expr7_0 = constructor_with_flags_reg(ctx, &expr4_0, &expr6_0)?;
-        let expr8_0 = C::value_reg(ctx, expr7_0);
-        return Some(expr8_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term do_clz.
-pub fn constructor_do_clz<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Type,
-    arg2: Gpr,
-) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/lower.isle line 1568.
-    let expr0_0: Type = I64;
-    let expr1_0: i64 = -1;
-    let expr2_0 = constructor_imm_i64(ctx, expr0_0, expr1_0)?;
-    let expr3_0 = C::gpr_new(ctx, expr2_0);
-    let expr4_0 = constructor_bsr_or_else(ctx, pattern0_0, pattern2_0, expr3_0)?;
-    let expr5_0 = C::gpr_to_reg(ctx, expr4_0);
-    let expr6_0 = C::ty_bits_u64(ctx, pattern1_0);
-    let expr7_0: u64 = 1;
-    let expr8_0 = C::u64_sub(ctx, expr6_0, expr7_0);
-    let expr9_0 = constructor_imm(ctx, pattern0_0, expr8_0)?;
-    let expr10_0 = C::gpr_new(ctx, expr9_0);
-    let expr11_0 = constructor_reg_to_gpr_mem_imm(ctx, expr5_0)?;
-    let expr12_0 = constructor_sub(ctx, pattern0_0, expr10_0, &expr11_0)?;
-    return Some(expr12_0);
-}
-
-// Generated as internal constructor for term do_ctz.
-pub fn constructor_do_ctz<C: Context>(
-    ctx: &mut C,
-    arg0: Type,
-    arg1: Type,
-    arg2: Gpr,
-) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    let pattern2_0 = arg2;
-    // Rule at src/isa/x64/lower.isle line 1609.
-    let expr0_0: Type = I64;
-    let expr1_0 = C::ty_bits_u64(ctx, pattern1_0);
-    let expr2_0 = constructor_imm(ctx, expr0_0, expr1_0)?;
-    let expr3_0 = C::gpr_new(ctx, expr2_0);
-    let expr4_0 = constructor_bsf_or_else(ctx, pattern0_0, pattern2_0, expr3_0)?;
-    return Some(expr4_0);
-}
-
-// Generated as internal constructor for term do_popcnt.
-pub fn constructor_do_popcnt<C: Context>(ctx: &mut C, arg0: Type, arg1: Gpr) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I32 {
-        let pattern2_0 = arg1;
-        // Rule at src/isa/x64/lower.isle line 1700.
-        let expr0_0: Type = I32;
-        let expr1_0: u8 = 1;
-        let expr2_0 = Imm8Reg::Imm8 { imm: expr1_0 };
-        let expr3_0 = C::imm8_reg_to_imm8_gpr(ctx, &expr2_0);
-        let expr4_0 = constructor_shr(ctx, expr0_0, pattern2_0, &expr3_0)?;
-        let expr5_0: Type = I32;
-        let expr6_0: u64 = 2004318071;
-        let expr7_0 = constructor_imm(ctx, expr5_0, expr6_0)?;
-        let expr8_0 = C::gpr_new(ctx, expr7_0);
-        let expr9_0: Type = I32;
-        let expr10_0 = C::gpr_to_gpr_mem_imm(ctx, expr8_0);
-        let expr11_0 = constructor_x64_and(ctx, expr9_0, expr4_0, &expr10_0)?;
-        let expr12_0: Type = I32;
-        let expr13_0 = C::gpr_to_gpr_mem_imm(ctx, expr11_0);
-        let expr14_0 = constructor_sub(ctx, expr12_0, pattern2_0, &expr13_0)?;
-        let expr15_0: Type = I32;
-        let expr16_0: u8 = 1;
-        let expr17_0 = Imm8Reg::Imm8 { imm: expr16_0 };
-        let expr18_0 = C::imm8_reg_to_imm8_gpr(ctx, &expr17_0);
-        let expr19_0 = constructor_shr(ctx, expr15_0, expr11_0, &expr18_0)?;
-        let expr20_0: Type = I32;
-        let expr21_0 = C::gpr_to_gpr_mem_imm(ctx, expr8_0);
-        let expr22_0 = constructor_x64_and(ctx, expr20_0, expr19_0, &expr21_0)?;
-        let expr23_0: Type = I32;
-        let expr24_0 = C::gpr_to_gpr_mem_imm(ctx, expr22_0);
-        let expr25_0 = constructor_sub(ctx, expr23_0, expr14_0, &expr24_0)?;
-        let expr26_0: Type = I32;
-        let expr27_0: u8 = 1;
-        let expr28_0 = Imm8Reg::Imm8 { imm: expr27_0 };
-        let expr29_0 = C::imm8_reg_to_imm8_gpr(ctx, &expr28_0);
-        let expr30_0 = constructor_shr(ctx, expr26_0, expr22_0, &expr29_0)?;
-        let expr31_0: Type = I32;
-        let expr32_0 = C::gpr_to_gpr_mem_imm(ctx, expr8_0);
-        let expr33_0 = constructor_x64_and(ctx, expr31_0, expr30_0, &expr32_0)?;
-        let expr34_0: Type = I32;
-        let expr35_0 = C::gpr_to_gpr_mem_imm(ctx, expr33_0);
-        let expr36_0 = constructor_sub(ctx, expr34_0, expr25_0, &expr35_0)?;
-        let expr37_0: Type = I32;
-        let expr38_0: Type = I32;
-        let expr39_0: u8 = 4;
-        let expr40_0 = Imm8Reg::Imm8 { imm: expr39_0 };
-        let expr41_0 = C::imm8_reg_to_imm8_gpr(ctx, &expr40_0);
-        let expr42_0 = constructor_shr(ctx, expr38_0, expr36_0, &expr41_0)?;
-        let expr43_0 = C::gpr_to_gpr_mem_imm(ctx, expr36_0);
-        let expr44_0 = constructor_add(ctx, expr37_0, expr42_0, &expr43_0)?;
-        let expr45_0: Type = I32;
-        let expr46_0: u32 = 252645135;
-        let expr47_0 = RegMemImm::Imm { simm32: expr46_0 };
-        let expr48_0 = C::gpr_mem_imm_new(ctx, &expr47_0);
-        let expr49_0 = constructor_x64_and(ctx, expr45_0, expr44_0, &expr48_0)?;
-        let expr50_0: Type = I32;
-        let expr51_0: u32 = 16843009;
-        let expr52_0 = RegMemImm::Imm { simm32: expr51_0 };
-        let expr53_0 = C::gpr_mem_imm_new(ctx, &expr52_0);
-        let expr54_0 = constructor_mul(ctx, expr50_0, expr49_0, &expr53_0)?;
-        let expr55_0: Type = I32;
-        let expr56_0: u8 = 24;
-        let expr57_0 = Imm8Reg::Imm8 { imm: expr56_0 };
-        let expr58_0 = C::imm8_reg_to_imm8_gpr(ctx, &expr57_0);
-        let expr59_0 = constructor_shr(ctx, expr55_0, expr54_0, &expr58_0)?;
-        return Some(expr59_0);
-    }
-    if pattern0_0 == I64 {
-        let pattern2_0 = arg1;
-        // Rule at src/isa/x64/lower.isle line 1657.
-        let expr0_0: Type = I64;
-        let expr1_0: u8 = 1;
-        let expr2_0 = Imm8Reg::Imm8 { imm: expr1_0 };
-        let expr3_0 = C::imm8_reg_to_imm8_gpr(ctx, &expr2_0);
-        let expr4_0 = constructor_shr(ctx, expr0_0, pattern2_0, &expr3_0)?;
-        let expr5_0: Type = I64;
-        let expr6_0: u64 = 8608480567731124087;
-        let expr7_0 = constructor_imm(ctx, expr5_0, expr6_0)?;
-        let expr8_0 = C::gpr_new(ctx, expr7_0);
-        let expr9_0: Type = I64;
-        let expr10_0 = C::gpr_to_gpr_mem_imm(ctx, expr8_0);
-        let expr11_0 = constructor_x64_and(ctx, expr9_0, expr4_0, &expr10_0)?;
-        let expr12_0: Type = I64;
-        let expr13_0 = C::gpr_to_gpr_mem_imm(ctx, expr11_0);
-        let expr14_0 = constructor_sub(ctx, expr12_0, pattern2_0, &expr13_0)?;
-        let expr15_0: Type = I64;
-        let expr16_0: u8 = 1;
-        let expr17_0 = Imm8Reg::Imm8 { imm: expr16_0 };
-        let expr18_0 = C::imm8_reg_to_imm8_gpr(ctx, &expr17_0);
-        let expr19_0 = constructor_shr(ctx, expr15_0, expr11_0, &expr18_0)?;
-        let expr20_0: Type = I64;
-        let expr21_0 = C::gpr_to_gpr_mem_imm(ctx, expr8_0);
-        let expr22_0 = constructor_x64_and(ctx, expr20_0, expr19_0, &expr21_0)?;
-        let expr23_0: Type = I64;
-        let expr24_0 = C::gpr_to_gpr_mem_imm(ctx, expr22_0);
-        let expr25_0 = constructor_sub(ctx, expr23_0, expr14_0, &expr24_0)?;
-        let expr26_0: Type = I64;
-        let expr27_0: u8 = 1;
-        let expr28_0 = Imm8Reg::Imm8 { imm: expr27_0 };
-        let expr29_0 = C::imm8_reg_to_imm8_gpr(ctx, &expr28_0);
-        let expr30_0 = constructor_shr(ctx, expr26_0, expr22_0, &expr29_0)?;
-        let expr31_0: Type = I64;
-        let expr32_0 = C::gpr_to_gpr_mem_imm(ctx, expr8_0);
-        let expr33_0 = constructor_x64_and(ctx, expr31_0, expr30_0, &expr32_0)?;
-        let expr34_0: Type = I64;
-        let expr35_0 = C::gpr_to_gpr_mem_imm(ctx, expr33_0);
-        let expr36_0 = constructor_sub(ctx, expr34_0, expr25_0, &expr35_0)?;
-        let expr37_0: Type = I64;
-        let expr38_0: Type = I64;
-        let expr39_0: u8 = 4;
-        let expr40_0 = Imm8Reg::Imm8 { imm: expr39_0 };
-        let expr41_0 = C::imm8_reg_to_imm8_gpr(ctx, &expr40_0);
-        let expr42_0 = constructor_shr(ctx, expr38_0, expr36_0, &expr41_0)?;
-        let expr43_0 = C::gpr_to_gpr_mem_imm(ctx, expr36_0);
-        let expr44_0 = constructor_add(ctx, expr37_0, expr42_0, &expr43_0)?;
-        let expr45_0: Type = I64;
-        let expr46_0: u64 = 1085102592571150095;
-        let expr47_0 = constructor_imm(ctx, expr45_0, expr46_0)?;
-        let expr48_0 = C::gpr_new(ctx, expr47_0);
-        let expr49_0: Type = I64;
-        let expr50_0 = C::gpr_to_gpr_mem_imm(ctx, expr48_0);
-        let expr51_0 = constructor_x64_and(ctx, expr49_0, expr44_0, &expr50_0)?;
-        let expr52_0: Type = I64;
-        let expr53_0: u64 = 72340172838076673;
-        let expr54_0 = constructor_imm(ctx, expr52_0, expr53_0)?;
-        let expr55_0 = C::gpr_new(ctx, expr54_0);
-        let expr56_0: Type = I64;
-        let expr57_0 = C::gpr_to_gpr_mem_imm(ctx, expr55_0);
-        let expr58_0 = constructor_mul(ctx, expr56_0, expr51_0, &expr57_0)?;
-        let expr59_0: Type = I64;
-        let expr60_0: u8 = 56;
-        let expr61_0 = Imm8Reg::Imm8 { imm: expr60_0 };
-        let expr62_0 = C::imm8_reg_to_imm8_gpr(ctx, &expr61_0);
-        let expr63_0 = constructor_shr(ctx, expr59_0, expr58_0, &expr62_0)?;
-        return Some(expr63_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term do_bitrev8.
-pub fn constructor_do_bitrev8<C: Context>(ctx: &mut C, arg0: Type, arg1: Gpr) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/lower.isle line 1789.
-    let expr0_0 = C::ty_mask(ctx, pattern0_0);
-    let expr1_0: u64 = 6148914691236517205;
-    let expr2_0 = C::u64_and(ctx, expr0_0, expr1_0);
-    let expr3_0 = constructor_imm(ctx, pattern0_0, expr2_0)?;
-    let expr4_0 = C::gpr_new(ctx, expr3_0);
-    let expr5_0 = C::gpr_to_gpr_mem_imm(ctx, expr4_0);
-    let expr6_0 = constructor_x64_and(ctx, pattern0_0, pattern1_0, &expr5_0)?;
-    let expr7_0: u8 = 1;
-    let expr8_0 = Imm8Reg::Imm8 { imm: expr7_0 };
-    let expr9_0 = C::imm8_reg_to_imm8_gpr(ctx, &expr8_0);
-    let expr10_0 = constructor_shr(ctx, pattern0_0, pattern1_0, &expr9_0)?;
-    let expr11_0 = C::gpr_to_gpr_mem_imm(ctx, expr4_0);
-    let expr12_0 = constructor_x64_and(ctx, pattern0_0, expr10_0, &expr11_0)?;
-    let expr13_0: u8 = 1;
-    let expr14_0 = Imm8Reg::Imm8 { imm: expr13_0 };
-    let expr15_0 = C::imm8_reg_to_imm8_gpr(ctx, &expr14_0);
-    let expr16_0 = constructor_shl(ctx, pattern0_0, expr6_0, &expr15_0)?;
-    let expr17_0 = C::gpr_to_gpr_mem_imm(ctx, expr12_0);
-    let expr18_0 = constructor_or(ctx, pattern0_0, expr16_0, &expr17_0)?;
-    let expr19_0: u64 = 3689348814741910323;
-    let expr20_0 = C::u64_and(ctx, expr0_0, expr19_0);
-    let expr21_0 = constructor_imm(ctx, pattern0_0, expr20_0)?;
-    let expr22_0 = C::gpr_new(ctx, expr21_0);
-    let expr23_0 = C::gpr_to_gpr_mem_imm(ctx, expr22_0);
-    let expr24_0 = constructor_x64_and(ctx, pattern0_0, expr18_0, &expr23_0)?;
-    let expr25_0: u8 = 2;
-    let expr26_0 = Imm8Reg::Imm8 { imm: expr25_0 };
-    let expr27_0 = C::imm8_reg_to_imm8_gpr(ctx, &expr26_0);
-    let expr28_0 = constructor_shr(ctx, pattern0_0, expr18_0, &expr27_0)?;
-    let expr29_0 = C::gpr_to_gpr_mem_imm(ctx, expr22_0);
-    let expr30_0 = constructor_x64_and(ctx, pattern0_0, expr28_0, &expr29_0)?;
-    let expr31_0: u8 = 2;
-    let expr32_0 = Imm8Reg::Imm8 { imm: expr31_0 };
-    let expr33_0 = C::imm8_reg_to_imm8_gpr(ctx, &expr32_0);
-    let expr34_0 = constructor_shl(ctx, pattern0_0, expr24_0, &expr33_0)?;
-    let expr35_0 = C::gpr_to_gpr_mem_imm(ctx, expr30_0);
-    let expr36_0 = constructor_or(ctx, pattern0_0, expr34_0, &expr35_0)?;
-    let expr37_0: u64 = 1085102592571150095;
-    let expr38_0 = C::u64_and(ctx, expr0_0, expr37_0);
-    let expr39_0 = constructor_imm(ctx, pattern0_0, expr38_0)?;
-    let expr40_0 = C::gpr_new(ctx, expr39_0);
-    let expr41_0 = C::gpr_to_gpr_mem_imm(ctx, expr40_0);
-    let expr42_0 = constructor_x64_and(ctx, pattern0_0, expr36_0, &expr41_0)?;
-    let expr43_0: u8 = 4;
-    let expr44_0 = Imm8Reg::Imm8 { imm: expr43_0 };
-    let expr45_0 = C::imm8_reg_to_imm8_gpr(ctx, &expr44_0);
-    let expr46_0 = constructor_shr(ctx, pattern0_0, expr36_0, &expr45_0)?;
-    let expr47_0 = C::gpr_to_gpr_mem_imm(ctx, expr40_0);
-    let expr48_0 = constructor_x64_and(ctx, pattern0_0, expr46_0, &expr47_0)?;
-    let expr49_0: u8 = 4;
-    let expr50_0 = Imm8Reg::Imm8 { imm: expr49_0 };
-    let expr51_0 = C::imm8_reg_to_imm8_gpr(ctx, &expr50_0);
-    let expr52_0 = constructor_shl(ctx, pattern0_0, expr42_0, &expr51_0)?;
-    let expr53_0 = C::gpr_to_gpr_mem_imm(ctx, expr48_0);
-    let expr54_0 = constructor_or(ctx, pattern0_0, expr52_0, &expr53_0)?;
-    return Some(expr54_0);
-}
-
-// Generated as internal constructor for term do_bitrev16.
-pub fn constructor_do_bitrev16<C: Context>(ctx: &mut C, arg0: Type, arg1: Gpr) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/lower.isle line 1812.
-    let expr0_0 = constructor_do_bitrev8(ctx, pattern0_0, pattern1_0)?;
-    let expr1_0 = C::ty_mask(ctx, pattern0_0);
-    let expr2_0: u64 = 71777214294589695;
-    let expr3_0 = C::u64_and(ctx, expr1_0, expr2_0);
-    let expr4_0 = constructor_imm(ctx, pattern0_0, expr3_0)?;
-    let expr5_0 = C::gpr_new(ctx, expr4_0);
-    let expr6_0 = C::gpr_to_gpr_mem_imm(ctx, expr5_0);
-    let expr7_0 = constructor_x64_and(ctx, pattern0_0, expr0_0, &expr6_0)?;
-    let expr8_0: u8 = 8;
-    let expr9_0 = Imm8Reg::Imm8 { imm: expr8_0 };
-    let expr10_0 = C::imm8_reg_to_imm8_gpr(ctx, &expr9_0);
-    let expr11_0 = constructor_shr(ctx, pattern0_0, expr0_0, &expr10_0)?;
-    let expr12_0 = C::gpr_to_gpr_mem_imm(ctx, expr5_0);
-    let expr13_0 = constructor_x64_and(ctx, pattern0_0, expr11_0, &expr12_0)?;
-    let expr14_0: u8 = 8;
-    let expr15_0 = Imm8Reg::Imm8 { imm: expr14_0 };
-    let expr16_0 = C::imm8_reg_to_imm8_gpr(ctx, &expr15_0);
-    let expr17_0 = constructor_shl(ctx, pattern0_0, expr7_0, &expr16_0)?;
-    let expr18_0 = C::gpr_to_gpr_mem_imm(ctx, expr13_0);
-    let expr19_0 = constructor_or(ctx, pattern0_0, expr17_0, &expr18_0)?;
-    return Some(expr19_0);
-}
-
-// Generated as internal constructor for term do_bitrev32.
-pub fn constructor_do_bitrev32<C: Context>(ctx: &mut C, arg0: Type, arg1: Gpr) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    // Rule at src/isa/x64/lower.isle line 1824.
-    let expr0_0 = constructor_do_bitrev16(ctx, pattern0_0, pattern1_0)?;
-    let expr1_0 = C::ty_mask(ctx, pattern0_0);
-    let expr2_0: u64 = 281470681808895;
-    let expr3_0 = C::u64_and(ctx, expr1_0, expr2_0);
-    let expr4_0 = constructor_imm(ctx, pattern0_0, expr3_0)?;
-    let expr5_0 = C::gpr_new(ctx, expr4_0);
-    let expr6_0 = C::gpr_to_gpr_mem_imm(ctx, expr5_0);
-    let expr7_0 = constructor_x64_and(ctx, pattern0_0, expr0_0, &expr6_0)?;
-    let expr8_0: u8 = 16;
-    let expr9_0 = Imm8Reg::Imm8 { imm: expr8_0 };
-    let expr10_0 = C::imm8_reg_to_imm8_gpr(ctx, &expr9_0);
-    let expr11_0 = constructor_shr(ctx, pattern0_0, expr0_0, &expr10_0)?;
-    let expr12_0 = C::gpr_to_gpr_mem_imm(ctx, expr5_0);
-    let expr13_0 = constructor_x64_and(ctx, pattern0_0, expr11_0, &expr12_0)?;
-    let expr14_0: u8 = 16;
-    let expr15_0 = Imm8Reg::Imm8 { imm: expr14_0 };
-    let expr16_0 = C::imm8_reg_to_imm8_gpr(ctx, &expr15_0);
-    let expr17_0 = constructor_shl(ctx, pattern0_0, expr7_0, &expr16_0)?;
-    let expr18_0 = C::gpr_to_gpr_mem_imm(ctx, expr13_0);
-    let expr19_0 = constructor_or(ctx, pattern0_0, expr17_0, &expr18_0)?;
-    return Some(expr19_0);
-}
-
-// Generated as internal constructor for term do_bitrev64.
-pub fn constructor_do_bitrev64<C: Context>(ctx: &mut C, arg0: Type, arg1: Gpr) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    if pattern0_0 == I64 {
-        let pattern2_0 = arg1;
-        // Rule at src/isa/x64/lower.isle line 1836.
-        let expr0_0 = constructor_do_bitrev32(ctx, pattern0_0, pattern2_0)?;
-        let expr1_0: u64 = 4294967295;
-        let expr2_0 = constructor_imm(ctx, pattern0_0, expr1_0)?;
-        let expr3_0 = C::gpr_new(ctx, expr2_0);
-        let expr4_0 = C::gpr_to_gpr_mem_imm(ctx, expr3_0);
-        let expr5_0 = constructor_x64_and(ctx, pattern0_0, expr0_0, &expr4_0)?;
-        let expr6_0: u8 = 32;
-        let expr7_0 = Imm8Reg::Imm8 { imm: expr6_0 };
-        let expr8_0 = C::imm8_reg_to_imm8_gpr(ctx, &expr7_0);
-        let expr9_0 = constructor_shr(ctx, pattern0_0, expr0_0, &expr8_0)?;
-        let expr10_0: u8 = 32;
-        let expr11_0 = Imm8Reg::Imm8 { imm: expr10_0 };
-        let expr12_0 = C::imm8_reg_to_imm8_gpr(ctx, &expr11_0);
-        let expr13_0 = constructor_shl(ctx, pattern0_0, expr5_0, &expr12_0)?;
-        let expr14_0 = C::gpr_to_gpr_mem_imm(ctx, expr9_0);
-        let expr15_0 = constructor_or(ctx, pattern0_0, expr13_0, &expr14_0)?;
-        return Some(expr15_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term generic_sextend.
-pub fn constructor_generic_sextend<C: Context>(
-    ctx: &mut C,
-    arg0: Value,
-    arg1: Type,
-    arg2: Type,
-) -> Option<InstOutput> {
-    let pattern0_0 = arg0;
-    let pattern1_0 = arg1;
-    if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
-        let pattern3_0 = arg2;
-        if let Some(pattern4_0) = C::fits_in_32(ctx, pattern3_0) {
-            // Rule at src/isa/x64/lower.isle line 1956.
-            let expr0_0: Type = I32;
-            let expr1_0 = ExtendKind::Sign;
-            let expr2_0 = constructor_extend_to_gpr(ctx, pattern0_0, expr0_0, &expr1_0)?;
-            let expr3_0 = constructor_output_gpr(ctx, expr2_0)?;
-            return Some(expr3_0);
-        }
-        if let Some(pattern4_0) = C::ty_int_bool_64(ctx, pattern3_0) {
-            // Rule at src/isa/x64/lower.isle line 1952.
-            let expr0_0: Type = I64;
-            let expr1_0 = ExtendKind::Sign;
-            let expr2_0 = constructor_extend_to_gpr(ctx, pattern0_0, expr0_0, &expr1_0)?;
-            let expr3_0 = constructor_output_gpr(ctx, expr2_0)?;
-            return Some(expr3_0);
-        }
-        if let Some(pattern4_0) = C::ty_int_bool_128(ctx, pattern3_0) {
-            // Rule at src/isa/x64/lower.isle line 1946.
-            let expr0_0: Type = I64;
-            let expr1_0 = ExtendKind::Sign;
-            let expr2_0 = constructor_extend_to_gpr(ctx, pattern0_0, expr0_0, &expr1_0)?;
-            let expr3_0 = constructor_spread_sign_bit(ctx, expr2_0)?;
-            let expr4_0 = C::gpr_to_reg(ctx, expr2_0);
-            let expr5_0 = C::gpr_to_reg(ctx, expr3_0);
-            let expr6_0 = C::value_regs(ctx, expr4_0, expr5_0);
-            let expr7_0 = C::output(ctx, expr6_0);
-            return Some(expr7_0);
-        }
-    }
-    if let Some(pattern2_0) = C::ty_int_bool_64(ctx, pattern1_0) {
-        let pattern3_0 = arg2;
-        if let Some(pattern4_0) = C::ty_int_bool_128(ctx, pattern3_0) {
-            // Rule at src/isa/x64/lower.isle line 1942.
-            let expr0_0 = C::put_in_reg(ctx, pattern0_0);
-            let expr1_0 = constructor_put_in_gpr(ctx, pattern0_0)?;
-            let expr2_0 = constructor_spread_sign_bit(ctx, expr1_0)?;
-            let expr3_0 = C::gpr_to_reg(ctx, expr2_0);
-            let expr4_0 = C::value_regs(ctx, expr0_0, expr3_0);
-            let expr5_0 = C::output(ctx, expr4_0);
-            return Some(expr5_0);
-        }
-    }
-    let pattern2_0 = arg2;
-    if pattern2_0 == pattern1_0 {
-        // Rule at src/isa/x64/lower.isle line 1932.
-        let expr0_0 = constructor_output_value(ctx, pattern0_0)?;
-        return Some(expr0_0);
-    }
-    return None;
-}
-
-// Generated as internal constructor for term spread_sign_bit.
-pub fn constructor_spread_sign_bit<C: Context>(ctx: &mut C, arg0: Gpr) -> Option<Gpr> {
-    let pattern0_0 = arg0;
-    // Rule at src/isa/x64/lower.isle line 1938.
-    let expr0_0: Type = I64;
-    let expr1_0: u8 = 63;
-    let expr2_0 = Imm8Reg::Imm8 { imm: expr1_0 };
-    let expr3_0 = C::imm8_reg_to_imm8_gpr(ctx, &expr2_0);
-    let expr4_0 = constructor_sar(ctx, expr0_0, pattern0_0, &expr3_0)?;
-    return Some(expr4_0);
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/mod.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/mod.rs
deleted file mode 100644
index a86ffc34f..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/mod.rs
+++ /dev/null
@@ -1,367 +0,0 @@
-//! X86_64-bit Instruction Set Architecture.
-
-use self::inst::EmitInfo;
-
-use super::TargetIsa;
-use crate::ir::{condcodes::IntCC, Function};
-#[cfg(feature = "unwind")]
-use crate::isa::unwind::systemv;
-use crate::isa::x64::{inst::regs::create_reg_universe_systemv, settings as x64_settings};
-use crate::isa::Builder as IsaBuilder;
-use crate::machinst::{
-    compile, MachCompileResult, MachTextSectionBuilder, TextSectionBuilder, VCode,
-};
-use crate::result::{CodegenError, CodegenResult};
-use crate::settings::{self as shared_settings, Flags};
-use alloc::{boxed::Box, vec::Vec};
-use core::fmt;
-
-use regalloc::{PrettyPrint, RealRegUniverse, Reg};
-use target_lexicon::Triple;
-
-mod abi;
-pub mod encoding;
-mod inst;
-mod lower;
-mod settings;
-
-/// An X64 backend.
-pub(crate) struct X64Backend {
-    triple: Triple,
-    flags: Flags,
-    x64_flags: x64_settings::Flags,
-    reg_universe: RealRegUniverse,
-}
-
-impl X64Backend {
-    /// Create a new X64 backend with the given (shared) flags.
-    fn new_with_flags(triple: Triple, flags: Flags, x64_flags: x64_settings::Flags) -> Self {
-        let reg_universe = create_reg_universe_systemv(&flags);
-        Self {
-            triple,
-            flags,
-            x64_flags,
-            reg_universe,
-        }
-    }
-
-    fn compile_vcode(&self, func: &Function, flags: Flags) -> CodegenResult<VCode<inst::Inst>> {
-        // This performs lowering to VCode, register-allocates the code, computes
-        // block layout and finalizes branches. The result is ready for binary emission.
-        let emit_info = EmitInfo::new(flags.clone(), self.x64_flags.clone());
-        let abi = Box::new(abi::X64ABICallee::new(&func, flags, self.isa_flags())?);
-        compile::compile::<Self>(&func, self, abi, &self.reg_universe, emit_info)
-    }
-}
-
-impl TargetIsa for X64Backend {
-    fn compile_function(
-        &self,
-        func: &Function,
-        want_disasm: bool,
-    ) -> CodegenResult<MachCompileResult> {
-        let flags = self.flags();
-        let vcode = self.compile_vcode(func, flags.clone())?;
-
-        let (buffer, bb_starts, bb_edges) = vcode.emit();
-        let buffer = buffer.finish();
-        let frame_size = vcode.frame_size();
-        let value_labels_ranges = vcode.value_labels_ranges();
-        let stackslot_offsets = vcode.stackslot_offsets().clone();
-
-        let disasm = if want_disasm {
-            Some(vcode.show_rru(Some(&create_reg_universe_systemv(flags))))
-        } else {
-            None
-        };
-
-        Ok(MachCompileResult {
-            buffer,
-            frame_size,
-            disasm,
-            value_labels_ranges,
-            stackslot_offsets,
-            bb_starts,
-            bb_edges,
-        })
-    }
-
-    fn flags(&self) -> &Flags {
-        &self.flags
-    }
-
-    fn isa_flags(&self) -> Vec<shared_settings::Value> {
-        self.x64_flags.iter().collect()
-    }
-
-    fn name(&self) -> &'static str {
-        "x64"
-    }
-
-    fn triple(&self) -> &Triple {
-        &self.triple
-    }
-
-    fn unsigned_add_overflow_condition(&self) -> IntCC {
-        // Unsigned `<`; this corresponds to the carry flag set on x86, which
-        // indicates an add has overflowed.
-        IntCC::UnsignedLessThan
-    }
-
-    #[cfg(feature = "unwind")]
-    fn emit_unwind_info(
-        &self,
-        result: &MachCompileResult,
-        kind: crate::machinst::UnwindInfoKind,
-    ) -> CodegenResult<Option<crate::isa::unwind::UnwindInfo>> {
-        use crate::isa::unwind::UnwindInfo;
-        use crate::machinst::UnwindInfoKind;
-        Ok(match kind {
-            UnwindInfoKind::SystemV => {
-                let mapper = self::inst::unwind::systemv::RegisterMapper;
-                Some(UnwindInfo::SystemV(
-                    crate::isa::unwind::systemv::create_unwind_info_from_insts(
-                        &result.buffer.unwind_info[..],
-                        result.buffer.data().len(),
-                        &mapper,
-                    )?,
-                ))
-            }
-            UnwindInfoKind::Windows => Some(UnwindInfo::WindowsX64(
-                crate::isa::unwind::winx64::create_unwind_info_from_insts::<
-                    self::inst::unwind::winx64::RegisterMapper,
-                >(&result.buffer.unwind_info[..])?,
-            )),
-            _ => None,
-        })
-    }
-
-    #[cfg(feature = "unwind")]
-    fn create_systemv_cie(&self) -> Option<gimli::write::CommonInformationEntry> {
-        Some(inst::unwind::systemv::create_cie())
-    }
-
-    #[cfg(feature = "unwind")]
-    fn map_regalloc_reg_to_dwarf(&self, reg: Reg) -> Result<u16, systemv::RegisterMappingError> {
-        inst::unwind::systemv::map_reg(reg).map(|reg| reg.0)
-    }
-
-    fn text_section_builder(&self, num_funcs: u32) -> Box<dyn TextSectionBuilder> {
-        Box::new(MachTextSectionBuilder::<inst::Inst>::new(num_funcs))
-    }
-}
-
-impl fmt::Display for X64Backend {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        f.debug_struct("MachBackend")
-            .field("name", &self.name())
-            .field("triple", &self.triple())
-            .field("flags", &format!("{}", self.flags()))
-            .finish()
-    }
-}
-
-/// Create a new `isa::Builder`.
-pub(crate) fn isa_builder(triple: Triple) -> IsaBuilder {
-    IsaBuilder {
-        triple,
-        setup: x64_settings::builder(),
-        constructor: isa_constructor,
-    }
-}
-
-fn isa_constructor(
-    triple: Triple,
-    shared_flags: Flags,
-    builder: shared_settings::Builder,
-) -> CodegenResult<Box<dyn TargetIsa>> {
-    let isa_flags = x64_settings::Flags::new(&shared_flags, builder);
-
-    // Check for compatibility between flags and ISA level
-    // requested. In particular, SIMD support requires SSE4.2.
-    if shared_flags.enable_simd() {
-        if !isa_flags.has_sse3()
-            || !isa_flags.has_ssse3()
-            || !isa_flags.has_sse41()
-            || !isa_flags.has_sse42()
-        {
-            return Err(CodegenError::Unsupported(
-                "SIMD support requires SSE3, SSSE3, SSE4.1, and SSE4.2 on x86_64.".into(),
-            ));
-        }
-    }
-
-    let backend = X64Backend::new_with_flags(triple, shared_flags, isa_flags);
-    Ok(Box::new(backend))
-}
-
-#[cfg(test)]
-mod test {
-    use super::*;
-    use crate::cursor::{Cursor, FuncCursor};
-    use crate::ir::{types::*, SourceLoc, ValueLabel, ValueLabelStart};
-    use crate::ir::{AbiParam, ExternalName, Function, InstBuilder, Signature};
-    use crate::isa::CallConv;
-    use crate::settings;
-    use crate::settings::Configurable;
-    use core::str::FromStr;
-    use cranelift_entity::EntityRef;
-    use target_lexicon::Triple;
-
-    /// We have to test cold blocks by observing final machine code,
-    /// rather than VCode, because the VCode orders blocks in lowering
-    /// order, not emission order. (The exact difference between the
-    /// two is that cold blocks are sunk in the latter.) We might as
-    /// well do the test here, where we have a backend to use.
-    #[test]
-    fn test_cold_blocks() {
-        let name = ExternalName::testcase("test0");
-        let mut sig = Signature::new(CallConv::SystemV);
-        sig.params.push(AbiParam::new(I32));
-        sig.returns.push(AbiParam::new(I32));
-        let mut func = Function::with_name_signature(name, sig);
-        // Add debug info: this tests the debug machinery wrt cold
-        // blocks as well.
-        func.dfg.collect_debug_info();
-
-        let bb0 = func.dfg.make_block();
-        let arg0 = func.dfg.append_block_param(bb0, I32);
-        let bb1 = func.dfg.make_block();
-        let bb2 = func.dfg.make_block();
-        let bb3 = func.dfg.make_block();
-        let bb1_param = func.dfg.append_block_param(bb1, I32);
-        let bb3_param = func.dfg.append_block_param(bb3, I32);
-
-        let mut pos = FuncCursor::new(&mut func);
-
-        pos.insert_block(bb0);
-        pos.set_srcloc(SourceLoc::new(1));
-        let v0 = pos.ins().iconst(I32, 0x1234);
-        pos.set_srcloc(SourceLoc::new(2));
-        let v1 = pos.ins().iadd(arg0, v0);
-        pos.ins().brnz(v1, bb1, &[v1]);
-        pos.ins().jump(bb2, &[]);
-
-        pos.insert_block(bb1);
-        pos.set_srcloc(SourceLoc::new(3));
-        let v2 = pos.ins().isub(v1, v0);
-        pos.set_srcloc(SourceLoc::new(4));
-        let v3 = pos.ins().iadd(v2, bb1_param);
-        pos.ins().brnz(v1, bb2, &[]);
-        pos.ins().jump(bb3, &[v3]);
-
-        pos.func.layout.set_cold(bb2);
-        pos.insert_block(bb2);
-        pos.set_srcloc(SourceLoc::new(5));
-        let v4 = pos.ins().iadd(v1, v0);
-        pos.ins().brnz(v4, bb2, &[]);
-        pos.ins().jump(bb1, &[v4]);
-
-        pos.insert_block(bb3);
-        pos.set_srcloc(SourceLoc::new(6));
-        pos.ins().return_(&[bb3_param]);
-
-        // Create some debug info. Make one label that follows all the
-        // values around. Note that this is usually done via an API on
-        // the FunctionBuilder, but that's in cranelift_frontend
-        // (i.e., a higher level of the crate DAG) so we have to build
-        // it manually here.
-        pos.func.dfg.values_labels.as_mut().unwrap().insert(
-            v0,
-            crate::ir::ValueLabelAssignments::Starts(vec![ValueLabelStart {
-                from: SourceLoc::new(1),
-                label: ValueLabel::new(1),
-            }]),
-        );
-        pos.func.dfg.values_labels.as_mut().unwrap().insert(
-            v1,
-            crate::ir::ValueLabelAssignments::Starts(vec![ValueLabelStart {
-                from: SourceLoc::new(2),
-                label: ValueLabel::new(1),
-            }]),
-        );
-        pos.func.dfg.values_labels.as_mut().unwrap().insert(
-            v2,
-            crate::ir::ValueLabelAssignments::Starts(vec![ValueLabelStart {
-                from: SourceLoc::new(3),
-                label: ValueLabel::new(1),
-            }]),
-        );
-        pos.func.dfg.values_labels.as_mut().unwrap().insert(
-            v3,
-            crate::ir::ValueLabelAssignments::Starts(vec![ValueLabelStart {
-                from: SourceLoc::new(4),
-                label: ValueLabel::new(1),
-            }]),
-        );
-        pos.func.dfg.values_labels.as_mut().unwrap().insert(
-            v4,
-            crate::ir::ValueLabelAssignments::Starts(vec![ValueLabelStart {
-                from: SourceLoc::new(5),
-                label: ValueLabel::new(1),
-            }]),
-        );
-
-        let mut shared_flags_builder = settings::builder();
-        shared_flags_builder.set("opt_level", "none").unwrap();
-        shared_flags_builder.set("enable_verifier", "true").unwrap();
-        let shared_flags = settings::Flags::new(shared_flags_builder);
-        let isa_flags = x64_settings::Flags::new(&shared_flags, x64_settings::builder());
-        let backend = X64Backend::new_with_flags(
-            Triple::from_str("x86_64").unwrap(),
-            shared_flags,
-            isa_flags,
-        );
-        let result = backend
-            .compile_function(&mut func, /* want_disasm = */ false)
-            .unwrap();
-        let code = result.buffer.data();
-
-        // 00000000  55                push rbp
-        // 00000001  4889E5            mov rbp,rsp
-        // 00000004  4889FE            mov rsi,rdi
-        // 00000007  81C634120000      add esi,0x1234
-        // 0000000D  85F6              test esi,esi
-        // 0000000F  0F841B000000      jz near 0x30
-        // 00000015  4889F7            mov rdi,rsi
-        // 00000018  4889F0            mov rax,rsi
-        // 0000001B  81E834120000      sub eax,0x1234
-        // 00000021  01F8              add eax,edi
-        // 00000023  85F6              test esi,esi
-        // 00000025  0F8505000000      jnz near 0x30
-        // 0000002B  4889EC            mov rsp,rbp
-        // 0000002E  5D                pop rbp
-        // 0000002F  C3                ret
-        // 00000030  4889F7            mov rdi,rsi    <--- cold block
-        // 00000033  81C734120000      add edi,0x1234
-        // 00000039  85FF              test edi,edi
-        // 0000003B  0F85EFFFFFFF      jnz near 0x30
-        // 00000041  E9D2FFFFFF        jmp 0x18
-
-        let golden = vec![
-            85, 72, 137, 229, 72, 137, 254, 129, 198, 52, 18, 0, 0, 133, 246, 15, 132, 27, 0, 0, 0,
-            72, 137, 247, 72, 137, 240, 129, 232, 52, 18, 0, 0, 1, 248, 133, 246, 15, 133, 5, 0, 0,
-            0, 72, 137, 236, 93, 195, 72, 137, 247, 129, 199, 52, 18, 0, 0, 133, 255, 15, 133, 239,
-            255, 255, 255, 233, 210, 255, 255, 255,
-        ];
-
-        assert_eq!(code, &golden[..]);
-    }
-
-    // Check that feature tests for SIMD work correctly.
-    #[test]
-    fn simd_required_features() {
-        let mut shared_flags_builder = settings::builder();
-        shared_flags_builder.set("enable_simd", "true").unwrap();
-        let shared_flags = settings::Flags::new(shared_flags_builder);
-        let mut isa_builder = crate::isa::lookup_by_name("x86_64").unwrap();
-        isa_builder.set("has_sse3", "false").unwrap();
-        isa_builder.set("has_ssse3", "false").unwrap();
-        isa_builder.set("has_sse41", "false").unwrap();
-        isa_builder.set("has_sse42", "false").unwrap();
-        assert!(matches!(
-            isa_builder.finish(shared_flags),
-            Err(CodegenError::Unsupported(_)),
-        ));
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/settings.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/settings.rs
deleted file mode 100644
index 501e153b4..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/isa/x64/settings.rs
+++ /dev/null
@@ -1,9 +0,0 @@
-//! x86 Settings.
-
-use crate::settings::{self, detail, Builder, Value};
-use core::fmt;
-
-// Include code generated by `cranelift-codegen/meta/src/gen_settings.rs:`. This file contains a
-// public `Flags` struct with an impl for all of the settings defined in
-// `cranelift-codegen/meta/src/isa/x86/settings.rs`.
-include!(concat!(env!("OUT_DIR"), "/settings-x86.rs"));
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/iterators.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/iterators.rs
deleted file mode 100644
index ca9c4ab26..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/iterators.rs
+++ /dev/null
@@ -1,93 +0,0 @@
-//! Iterator utilities.
-
-/// Extra methods for iterators.
-pub trait IteratorExtras: Iterator {
-    /// Create an iterator that produces adjacent pairs of elements from the iterator.
-    fn adjacent_pairs(mut self) -> AdjacentPairs<Self>
-    where
-        Self: Sized,
-        Self::Item: Clone,
-    {
-        let elem = self.next();
-        AdjacentPairs { iter: self, elem }
-    }
-}
-
-impl<T> IteratorExtras for T where T: Iterator {}
-
-/// Adjacent pairs iterator returned by `adjacent_pairs()`.
-///
-/// This wraps another iterator and produces a sequence of adjacent pairs of elements.
-pub struct AdjacentPairs<I>
-where
-    I: Iterator,
-    I::Item: Clone,
-{
-    iter: I,
-    elem: Option<I::Item>,
-}
-
-impl<I> Iterator for AdjacentPairs<I>
-where
-    I: Iterator,
-    I::Item: Clone,
-{
-    type Item = (I::Item, I::Item);
-
-    fn next(&mut self) -> Option<Self::Item> {
-        self.elem.take().and_then(|e| {
-            self.elem = self.iter.next();
-            self.elem.clone().map(|n| (e, n))
-        })
-    }
-}
-
-#[cfg(test)]
-mod tests {
-    use alloc::vec::Vec;
-
-    #[test]
-    fn adjpairs() {
-        use super::IteratorExtras;
-
-        assert_eq!(
-            [1, 2, 3, 4]
-                .iter()
-                .cloned()
-                .adjacent_pairs()
-                .collect::<Vec<_>>(),
-            vec![(1, 2), (2, 3), (3, 4)]
-        );
-        assert_eq!(
-            [2, 3, 4]
-                .iter()
-                .cloned()
-                .adjacent_pairs()
-                .collect::<Vec<_>>(),
-            vec![(2, 3), (3, 4)]
-        );
-        assert_eq!(
-            [2, 3, 4]
-                .iter()
-                .cloned()
-                .adjacent_pairs()
-                .collect::<Vec<_>>(),
-            vec![(2, 3), (3, 4)]
-        );
-        assert_eq!(
-            [3, 4].iter().cloned().adjacent_pairs().collect::<Vec<_>>(),
-            vec![(3, 4)]
-        );
-        assert_eq!(
-            [4].iter().cloned().adjacent_pairs().collect::<Vec<_>>(),
-            vec![]
-        );
-        assert_eq!(
-            [].iter()
-                .cloned()
-                .adjacent_pairs()
-                .collect::<Vec<(i32, i32)>>(),
-            vec![]
-        );
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/legalizer/globalvalue.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/legalizer/globalvalue.rs
deleted file mode 100644
index 50974a1d8..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/legalizer/globalvalue.rs
+++ /dev/null
@@ -1,127 +0,0 @@
-//! Legalization of global values.
-//!
-//! This module exports the `expand_global_value` function which transforms a `global_value`
-//! instruction into code that depends on the kind of global value referenced.
-
-use crate::cursor::{Cursor, FuncCursor};
-use crate::ir::{self, InstBuilder};
-use crate::isa::TargetIsa;
-
-/// Expand a `global_value` instruction according to the definition of the global value.
-pub fn expand_global_value(
-    inst: ir::Inst,
-    func: &mut ir::Function,
-    isa: &dyn TargetIsa,
-    global_value: ir::GlobalValue,
-) {
-    match func.global_values[global_value] {
-        ir::GlobalValueData::VMContext => vmctx_addr(inst, func),
-        ir::GlobalValueData::IAddImm {
-            base,
-            offset,
-            global_type,
-        } => iadd_imm_addr(inst, func, base, offset.into(), global_type),
-        ir::GlobalValueData::Load {
-            base,
-            offset,
-            global_type,
-            readonly,
-        } => load_addr(inst, func, base, offset, global_type, readonly, isa),
-        ir::GlobalValueData::Symbol { tls, .. } => symbol(inst, func, global_value, isa, tls),
-    }
-}
-
-/// Expand a `global_value` instruction for a vmctx global.
-fn vmctx_addr(inst: ir::Inst, func: &mut ir::Function) {
-    // Get the value representing the `vmctx` argument.
-    let vmctx = func
-        .special_param(ir::ArgumentPurpose::VMContext)
-        .expect("Missing vmctx parameter");
-
-    // Replace the `global_value` instruction's value with an alias to the vmctx arg.
-    let result = func.dfg.first_result(inst);
-    func.dfg.clear_results(inst);
-    func.dfg.change_to_alias(result, vmctx);
-    func.layout.remove_inst(inst);
-}
-
-/// Expand a `global_value` instruction for an iadd_imm global.
-fn iadd_imm_addr(
-    inst: ir::Inst,
-    func: &mut ir::Function,
-    base: ir::GlobalValue,
-    offset: i64,
-    global_type: ir::Type,
-) {
-    let mut pos = FuncCursor::new(func).at_inst(inst);
-
-    // Get the value for the lhs. For tidiness, expand VMContext here so that we avoid
-    // `vmctx_addr` which creates an otherwise unneeded value alias.
-    let lhs = if let ir::GlobalValueData::VMContext = pos.func.global_values[base] {
-        pos.func
-            .special_param(ir::ArgumentPurpose::VMContext)
-            .expect("Missing vmctx parameter")
-    } else {
-        pos.ins().global_value(global_type, base)
-    };
-
-    // Simply replace the `global_value` instruction with an `iadd_imm`, reusing the result value.
-    pos.func.dfg.replace(inst).iadd_imm(lhs, offset);
-}
-
-/// Expand a `global_value` instruction for a load global.
-fn load_addr(
-    inst: ir::Inst,
-    func: &mut ir::Function,
-    base: ir::GlobalValue,
-    offset: ir::immediates::Offset32,
-    global_type: ir::Type,
-    readonly: bool,
-    isa: &dyn TargetIsa,
-) {
-    // We need to load a pointer from the `base` global value, so insert a new `global_value`
-    // instruction. This depends on the iterative legalization loop. Note that the IR verifier
-    // detects any cycles in the `load` globals.
-    let ptr_ty = isa.pointer_type();
-    let mut pos = FuncCursor::new(func).at_inst(inst);
-    pos.use_srcloc(inst);
-
-    // Get the value for the base. For tidiness, expand VMContext here so that we avoid
-    // `vmctx_addr` which creates an otherwise unneeded value alias.
-    let base_addr = if let ir::GlobalValueData::VMContext = pos.func.global_values[base] {
-        pos.func
-            .special_param(ir::ArgumentPurpose::VMContext)
-            .expect("Missing vmctx parameter")
-    } else {
-        pos.ins().global_value(ptr_ty, base)
-    };
-
-    // Global-value loads are always notrap and aligned. They may be readonly.
-    let mut mflags = ir::MemFlags::trusted();
-    if readonly {
-        mflags.set_readonly();
-    }
-
-    // Perform the load.
-    pos.func
-        .dfg
-        .replace(inst)
-        .load(global_type, mflags, base_addr, offset);
-}
-
-/// Expand a `global_value` instruction for a symbolic name global.
-fn symbol(
-    inst: ir::Inst,
-    func: &mut ir::Function,
-    gv: ir::GlobalValue,
-    isa: &dyn TargetIsa,
-    tls: bool,
-) {
-    let ptr_ty = isa.pointer_type();
-
-    if tls {
-        func.dfg.replace(inst).tls_value(ptr_ty, gv);
-    } else {
-        func.dfg.replace(inst).symbol_value(ptr_ty, gv);
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/legalizer/heap.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/legalizer/heap.rs
deleted file mode 100644
index 91ae3da3c..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/legalizer/heap.rs
+++ /dev/null
@@ -1,259 +0,0 @@
-//! Legalization of heaps.
-//!
-//! This module exports the `expand_heap_addr` function which transforms a `heap_addr`
-//! instruction into code that depends on the kind of heap referenced.
-
-use crate::cursor::{Cursor, FuncCursor};
-use crate::flowgraph::ControlFlowGraph;
-use crate::ir::condcodes::IntCC;
-use crate::ir::immediates::Uimm32;
-use crate::ir::{self, InstBuilder};
-use crate::isa::TargetIsa;
-
-/// Expand a `heap_addr` instruction according to the definition of the heap.
-pub fn expand_heap_addr(
-    inst: ir::Inst,
-    func: &mut ir::Function,
-    cfg: &mut ControlFlowGraph,
-    isa: &dyn TargetIsa,
-    heap: ir::Heap,
-    offset: ir::Value,
-    access_size: Uimm32,
-) {
-    match func.heaps[heap].style {
-        ir::HeapStyle::Dynamic { bound_gv } => dynamic_addr(
-            isa,
-            inst,
-            heap,
-            offset,
-            u64::from(access_size),
-            bound_gv,
-            func,
-        ),
-        ir::HeapStyle::Static { bound } => static_addr(
-            isa,
-            inst,
-            heap,
-            offset,
-            u64::from(access_size),
-            bound.into(),
-            func,
-            cfg,
-        ),
-    }
-}
-
-/// Expand a `heap_addr` for a dynamic heap.
-fn dynamic_addr(
-    isa: &dyn TargetIsa,
-    inst: ir::Inst,
-    heap: ir::Heap,
-    offset: ir::Value,
-    access_size: u64,
-    bound_gv: ir::GlobalValue,
-    func: &mut ir::Function,
-) {
-    let offset_ty = func.dfg.value_type(offset);
-    let addr_ty = func.dfg.value_type(func.dfg.first_result(inst));
-    let min_size = func.heaps[heap].min_size.into();
-    let mut pos = FuncCursor::new(func).at_inst(inst);
-    pos.use_srcloc(inst);
-
-    let offset = cast_offset_to_pointer_ty(offset, offset_ty, addr_ty, &mut pos);
-
-    // Start with the bounds check. Trap if `offset + access_size > bound`.
-    let bound = pos.ins().global_value(addr_ty, bound_gv);
-    let (cc, lhs, bound) = if access_size == 1 {
-        // `offset > bound - 1` is the same as `offset >= bound`.
-        (IntCC::UnsignedGreaterThanOrEqual, offset, bound)
-    } else if access_size <= min_size {
-        // We know that bound >= min_size, so here we can compare `offset > bound - access_size`
-        // without wrapping.
-        let adj_bound = pos.ins().iadd_imm(bound, -(access_size as i64));
-        (IntCC::UnsignedGreaterThan, offset, adj_bound)
-    } else {
-        // We need an overflow check for the adjusted offset.
-        let access_size_val = pos.ins().iconst(addr_ty, access_size as i64);
-        let (adj_offset, overflow) = pos.ins().iadd_ifcout(offset, access_size_val);
-        pos.ins().trapif(
-            isa.unsigned_add_overflow_condition(),
-            overflow,
-            ir::TrapCode::HeapOutOfBounds,
-        );
-        (IntCC::UnsignedGreaterThan, adj_offset, bound)
-    };
-    let oob = pos.ins().icmp(cc, lhs, bound);
-    pos.ins().trapnz(oob, ir::TrapCode::HeapOutOfBounds);
-
-    let spectre_oob_comparison = if isa.flags().enable_heap_access_spectre_mitigation() {
-        Some((cc, lhs, bound))
-    } else {
-        None
-    };
-
-    compute_addr(
-        isa,
-        inst,
-        heap,
-        addr_ty,
-        offset,
-        pos.func,
-        spectre_oob_comparison,
-    );
-}
-
-/// Expand a `heap_addr` for a static heap.
-fn static_addr(
-    isa: &dyn TargetIsa,
-    inst: ir::Inst,
-    heap: ir::Heap,
-    mut offset: ir::Value,
-    access_size: u64,
-    bound: u64,
-    func: &mut ir::Function,
-    cfg: &mut ControlFlowGraph,
-) {
-    let offset_ty = func.dfg.value_type(offset);
-    let addr_ty = func.dfg.value_type(func.dfg.first_result(inst));
-    let mut pos = FuncCursor::new(func).at_inst(inst);
-    pos.use_srcloc(inst);
-
-    // The goal here is to trap if `offset + access_size > bound`.
-    //
-    // This first case is a trivial case where we can easily trap.
-    if access_size > bound {
-        // This will simply always trap since `offset >= 0`.
-        pos.ins().trap(ir::TrapCode::HeapOutOfBounds);
-        pos.func.dfg.replace(inst).iconst(addr_ty, 0);
-
-        // Split Block, as the trap is a terminator instruction.
-        let curr_block = pos.current_block().expect("Cursor is not in a block");
-        let new_block = pos.func.dfg.make_block();
-        pos.insert_block(new_block);
-        cfg.recompute_block(pos.func, curr_block);
-        cfg.recompute_block(pos.func, new_block);
-        return;
-    }
-
-    // After the trivial case is done we're now mostly interested in trapping
-    // if `offset > bound - access_size`. We know `bound - access_size` here is
-    // non-negative from the above comparison.
-    //
-    // If we can know `bound - access_size >= 4GB` then with a 32-bit offset
-    // we're guaranteed:
-    //
-    //      bound - access_size >= 4GB > offset
-    //
-    // or, in other words, `offset < bound - access_size`, meaning we can't trap
-    // for any value of `offset`.
-    //
-    // With that we have an optimization here where with 32-bit offsets and
-    // `bound - access_size >= 4GB` we can omit a bounds check.
-    let limit = bound - access_size;
-    let mut spectre_oob_comparison = None;
-    offset = cast_offset_to_pointer_ty(offset, offset_ty, addr_ty, &mut pos);
-    if offset_ty != ir::types::I32 || limit < 0xffff_ffff {
-        // Here we want to test the condition `offset > limit` and if that's
-        // true then this is an out-of-bounds access and needs to trap. For ARM
-        // and other RISC architectures it's easier to test against an immediate
-        // that's even instead of odd, so if `limit` is odd then we instead test
-        // for `offset >= limit + 1`.
-        //
-        // The thinking behind this is that:
-        //
-        //      A >= B + 1  =>  A - 1 >= B  =>  A > B
-        //
-        // where the last step here is true because A/B are integers, which
-        // should mean that `A >= B + 1` is an equivalent check for `A > B`
-        let (cc, lhs, limit_imm) = if limit & 1 == 1 {
-            let limit = limit as i64 + 1;
-            (IntCC::UnsignedGreaterThanOrEqual, offset, limit)
-        } else {
-            let limit = limit as i64;
-            (IntCC::UnsignedGreaterThan, offset, limit)
-        };
-        let oob = pos.ins().icmp_imm(cc, lhs, limit_imm);
-        pos.ins().trapnz(oob, ir::TrapCode::HeapOutOfBounds);
-        if isa.flags().enable_heap_access_spectre_mitigation() {
-            let limit = pos.ins().iconst(addr_ty, limit_imm);
-            spectre_oob_comparison = Some((cc, lhs, limit));
-        }
-    }
-
-    compute_addr(
-        isa,
-        inst,
-        heap,
-        addr_ty,
-        offset,
-        pos.func,
-        spectre_oob_comparison,
-    );
-}
-
-fn cast_offset_to_pointer_ty(
-    offset: ir::Value,
-    offset_ty: ir::Type,
-    addr_ty: ir::Type,
-    pos: &mut FuncCursor,
-) -> ir::Value {
-    if offset_ty == addr_ty {
-        return offset;
-    }
-    // Note that using 64-bit heaps on a 32-bit host is not currently supported,
-    // would require at least a bounds check here to ensure that the truncation
-    // from 64-to-32 bits doesn't lose any upper bits. For now though we're
-    // mostly interested in the 32-bit-heaps-on-64-bit-hosts cast.
-    assert!(offset_ty.bits() < addr_ty.bits());
-
-    // Convert `offset` to `addr_ty`.
-    let extended_offset = pos.ins().uextend(addr_ty, offset);
-
-    // Add debug value-label alias so that debuginfo can name the extended
-    // value as the address
-    let loc = pos.srcloc();
-    pos.func
-        .dfg
-        .add_value_label_alias(extended_offset, loc, offset);
-
-    extended_offset
-}
-
-/// Emit code for the base address computation of a `heap_addr` instruction.
-fn compute_addr(
-    isa: &dyn TargetIsa,
-    inst: ir::Inst,
-    heap: ir::Heap,
-    addr_ty: ir::Type,
-    offset: ir::Value,
-    func: &mut ir::Function,
-    // If we are performing Spectre mitigation with conditional selects, the
-    // values to compare and the condition code that indicates an out-of bounds
-    // condition; on this condition, the conditional move will choose a
-    // speculatively safe address (a zero / null pointer) instead.
-    spectre_oob_comparison: Option<(IntCC, ir::Value, ir::Value)>,
-) {
-    debug_assert_eq!(func.dfg.value_type(offset), addr_ty);
-    let mut pos = FuncCursor::new(func).at_inst(inst);
-    pos.use_srcloc(inst);
-
-    // Add the heap base address base
-    let base = if isa.flags().enable_pinned_reg() && isa.flags().use_pinned_reg_as_heap_base() {
-        pos.ins().get_pinned_reg(isa.pointer_type())
-    } else {
-        let base_gv = pos.func.heaps[heap].base;
-        pos.ins().global_value(addr_ty, base_gv)
-    };
-
-    if let Some((cc, a, b)) = spectre_oob_comparison {
-        let final_addr = pos.ins().iadd(base, offset);
-        let zero = pos.ins().iconst(addr_ty, 0);
-        let flags = pos.ins().ifcmp(a, b);
-        pos.func
-            .dfg
-            .replace(inst)
-            .selectif_spectre_guard(addr_ty, cc, flags, zero, final_addr);
-    } else {
-        pos.func.dfg.replace(inst).iadd(base, offset);
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/legalizer/mod.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/legalizer/mod.rs
deleted file mode 100644
index d0f39d360..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/legalizer/mod.rs
+++ /dev/null
@@ -1,363 +0,0 @@
-//! Legalize instructions.
-//!
-//! A legal instruction is one that can be mapped directly to a machine code instruction for the
-//! target ISA. The `legalize_function()` function takes as input any function and transforms it
-//! into an equivalent function using only legal instructions.
-//!
-//! The characteristics of legal instructions depend on the target ISA, so any given instruction
-//! can be legal for one ISA and illegal for another.
-//!
-//! Besides transforming instructions, the legalizer also fills out the `function.encodings` map
-//! which provides a legal encoding recipe for every instruction.
-//!
-//! The legalizer does not deal with register allocation constraints. These constraints are derived
-//! from the encoding recipes, and solved later by the register allocator.
-
-use crate::cursor::{Cursor, FuncCursor};
-use crate::flowgraph::ControlFlowGraph;
-use crate::ir::types::I32;
-use crate::ir::{self, InstBuilder, InstructionData, MemFlags};
-use crate::isa::TargetIsa;
-
-mod globalvalue;
-mod heap;
-mod table;
-
-use self::globalvalue::expand_global_value;
-use self::heap::expand_heap_addr;
-use self::table::expand_table_addr;
-
-/// Perform a simple legalization by expansion of the function, without
-/// platform-specific transforms.
-pub fn simple_legalize(func: &mut ir::Function, cfg: &mut ControlFlowGraph, isa: &dyn TargetIsa) {
-    let mut pos = FuncCursor::new(func);
-    let func_begin = pos.position();
-    pos.set_position(func_begin);
-    while let Some(_block) = pos.next_block() {
-        let mut prev_pos = pos.position();
-        while let Some(inst) = pos.next_inst() {
-            match pos.func.dfg[inst] {
-                // control flow
-                InstructionData::BranchIcmp {
-                    opcode: ir::Opcode::BrIcmp,
-                    cond,
-                    destination,
-                    ref args,
-                } => {
-                    let a = args.get(0, &pos.func.dfg.value_lists).unwrap();
-                    let b = args.get(1, &pos.func.dfg.value_lists).unwrap();
-                    let block_args = args.as_slice(&pos.func.dfg.value_lists)[2..].to_vec();
-
-                    let old_block = pos.func.layout.pp_block(inst);
-                    pos.func.dfg.clear_results(inst);
-
-                    let icmp_res = pos.func.dfg.replace(inst).icmp(cond, a, b);
-                    let mut pos = FuncCursor::new(pos.func).after_inst(inst);
-                    pos.use_srcloc(inst);
-                    pos.ins().brnz(icmp_res, destination, &block_args);
-
-                    cfg.recompute_block(pos.func, destination);
-                    cfg.recompute_block(pos.func, old_block);
-                }
-                InstructionData::CondTrap {
-                    opcode:
-                        opcode @ (ir::Opcode::Trapnz | ir::Opcode::Trapz | ir::Opcode::ResumableTrapnz),
-                    arg,
-                    code,
-                } => {
-                    expand_cond_trap(inst, &mut pos.func, cfg, opcode, arg, code);
-                }
-
-                // memory and constants
-                InstructionData::UnaryGlobalValue {
-                    opcode: ir::Opcode::GlobalValue,
-                    global_value,
-                } => expand_global_value(inst, &mut pos.func, isa, global_value),
-                InstructionData::HeapAddr {
-                    opcode: ir::Opcode::HeapAddr,
-                    heap,
-                    arg,
-                    imm,
-                } => expand_heap_addr(inst, &mut pos.func, cfg, isa, heap, arg, imm),
-                InstructionData::StackLoad {
-                    opcode: ir::Opcode::StackLoad,
-                    stack_slot,
-                    offset,
-                } => {
-                    let ty = pos.func.dfg.value_type(pos.func.dfg.first_result(inst));
-                    let addr_ty = isa.pointer_type();
-
-                    let mut pos = FuncCursor::new(pos.func).at_inst(inst);
-                    pos.use_srcloc(inst);
-
-                    let addr = pos.ins().stack_addr(addr_ty, stack_slot, offset);
-
-                    // Stack slots are required to be accessible and aligned.
-                    let mflags = MemFlags::trusted();
-                    pos.func.dfg.replace(inst).load(ty, mflags, addr, 0);
-                }
-                InstructionData::StackStore {
-                    opcode: ir::Opcode::StackStore,
-                    arg,
-                    stack_slot,
-                    offset,
-                } => {
-                    let addr_ty = isa.pointer_type();
-
-                    let mut pos = FuncCursor::new(pos.func).at_inst(inst);
-                    pos.use_srcloc(inst);
-
-                    let addr = pos.ins().stack_addr(addr_ty, stack_slot, offset);
-
-                    let mut mflags = MemFlags::new();
-                    // Stack slots are required to be accessible and aligned.
-                    mflags.set_notrap();
-                    mflags.set_aligned();
-                    pos.func.dfg.replace(inst).store(mflags, arg, addr, 0);
-                }
-                InstructionData::TableAddr {
-                    opcode: ir::Opcode::TableAddr,
-                    table,
-                    arg,
-                    offset,
-                } => expand_table_addr(inst, &mut pos.func, table, arg, offset),
-
-                // bitops
-                InstructionData::BinaryImm64 {
-                    opcode: ir::Opcode::BandImm,
-                    arg,
-                    imm,
-                } => {
-                    let ty = pos.func.dfg.value_type(arg);
-                    let imm = pos.ins().iconst(ty, imm);
-                    pos.func.dfg.replace(inst).band(arg, imm);
-                }
-                InstructionData::BinaryImm64 {
-                    opcode: ir::Opcode::BorImm,
-                    arg,
-                    imm,
-                } => {
-                    let ty = pos.func.dfg.value_type(arg);
-                    let imm = pos.ins().iconst(ty, imm);
-                    pos.func.dfg.replace(inst).bor(arg, imm);
-                }
-                InstructionData::BinaryImm64 {
-                    opcode: ir::Opcode::BxorImm,
-                    arg,
-                    imm,
-                } => {
-                    let ty = pos.func.dfg.value_type(arg);
-                    let imm = pos.ins().iconst(ty, imm);
-                    pos.func.dfg.replace(inst).bxor(arg, imm);
-                }
-                InstructionData::BinaryImm64 {
-                    opcode: ir::Opcode::IaddImm,
-                    arg,
-                    imm,
-                } => {
-                    let ty = pos.func.dfg.value_type(arg);
-                    let imm = pos.ins().iconst(ty, imm);
-                    pos.func.dfg.replace(inst).iadd(arg, imm);
-                }
-
-                // bitshifting
-                InstructionData::BinaryImm64 {
-                    opcode: ir::Opcode::IshlImm,
-                    arg,
-                    imm,
-                } => {
-                    let imm = pos.ins().iconst(I32, imm);
-                    pos.func.dfg.replace(inst).ishl(arg, imm);
-                }
-                InstructionData::BinaryImm64 {
-                    opcode: ir::Opcode::RotlImm,
-                    arg,
-                    imm,
-                } => {
-                    let imm = pos.ins().iconst(I32, imm);
-                    pos.func.dfg.replace(inst).rotl(arg, imm);
-                }
-                InstructionData::BinaryImm64 {
-                    opcode: ir::Opcode::RotrImm,
-                    arg,
-                    imm,
-                } => {
-                    let imm = pos.ins().iconst(I32, imm);
-                    pos.func.dfg.replace(inst).rotr(arg, imm);
-                }
-                InstructionData::BinaryImm64 {
-                    opcode: ir::Opcode::SshrImm,
-                    arg,
-                    imm,
-                } => {
-                    let imm = pos.ins().iconst(I32, imm);
-                    pos.func.dfg.replace(inst).sshr(arg, imm);
-                }
-                InstructionData::BinaryImm64 {
-                    opcode: ir::Opcode::UshrImm,
-                    arg,
-                    imm,
-                } => {
-                    let imm = pos.ins().iconst(I32, imm);
-                    pos.func.dfg.replace(inst).ushr(arg, imm);
-                }
-
-                // math
-                InstructionData::BinaryImm64 {
-                    opcode: ir::Opcode::IrsubImm,
-                    arg,
-                    imm,
-                } => {
-                    let ty = pos.func.dfg.value_type(arg);
-                    let imm = pos.ins().iconst(ty, imm);
-                    pos.func.dfg.replace(inst).isub(imm, arg); // note: arg order reversed
-                }
-                InstructionData::BinaryImm64 {
-                    opcode: ir::Opcode::ImulImm,
-                    arg,
-                    imm,
-                } => {
-                    let ty = pos.func.dfg.value_type(arg);
-                    let imm = pos.ins().iconst(ty, imm);
-                    pos.func.dfg.replace(inst).imul(arg, imm);
-                }
-                InstructionData::BinaryImm64 {
-                    opcode: ir::Opcode::SdivImm,
-                    arg,
-                    imm,
-                } => {
-                    let ty = pos.func.dfg.value_type(arg);
-                    let imm = pos.ins().iconst(ty, imm);
-                    pos.func.dfg.replace(inst).sdiv(arg, imm);
-                }
-                InstructionData::BinaryImm64 {
-                    opcode: ir::Opcode::SremImm,
-                    arg,
-                    imm,
-                } => {
-                    let ty = pos.func.dfg.value_type(arg);
-                    let imm = pos.ins().iconst(ty, imm);
-                    pos.func.dfg.replace(inst).srem(arg, imm);
-                }
-                InstructionData::BinaryImm64 {
-                    opcode: ir::Opcode::UdivImm,
-                    arg,
-                    imm,
-                } => {
-                    let ty = pos.func.dfg.value_type(arg);
-                    let imm = pos.ins().iconst(ty, imm);
-                    pos.func.dfg.replace(inst).udiv(arg, imm);
-                }
-                InstructionData::BinaryImm64 {
-                    opcode: ir::Opcode::UremImm,
-                    arg,
-                    imm,
-                } => {
-                    let ty = pos.func.dfg.value_type(arg);
-                    let imm = pos.ins().iconst(ty, imm);
-                    pos.func.dfg.replace(inst).urem(arg, imm);
-                }
-
-                // comparisons
-                InstructionData::BinaryImm64 {
-                    opcode: ir::Opcode::IfcmpImm,
-                    arg,
-                    imm,
-                } => {
-                    let ty = pos.func.dfg.value_type(arg);
-                    let imm = pos.ins().iconst(ty, imm);
-                    pos.func.dfg.replace(inst).ifcmp(arg, imm);
-                }
-                InstructionData::IntCompareImm {
-                    opcode: ir::Opcode::IcmpImm,
-                    cond,
-                    arg,
-                    imm,
-                } => {
-                    let ty = pos.func.dfg.value_type(arg);
-                    let imm = pos.ins().iconst(ty, imm);
-                    pos.func.dfg.replace(inst).icmp(cond, arg, imm);
-                }
-
-                _ => {
-                    prev_pos = pos.position();
-                    continue;
-                }
-            }
-
-            // Legalization implementations require fixpoint loop here.
-            // TODO: fix this.
-            pos.set_position(prev_pos);
-        }
-    }
-}
-
-/// Custom expansion for conditional trap instructions.
-fn expand_cond_trap(
-    inst: ir::Inst,
-    func: &mut ir::Function,
-    cfg: &mut ControlFlowGraph,
-    opcode: ir::Opcode,
-    arg: ir::Value,
-    code: ir::TrapCode,
-) {
-    // Parse the instruction.
-    let trapz = match opcode {
-        ir::Opcode::Trapz => true,
-        ir::Opcode::Trapnz | ir::Opcode::ResumableTrapnz => false,
-        _ => panic!("Expected cond trap: {}", func.dfg.display_inst(inst)),
-    };
-
-    // Split the block after `inst`:
-    //
-    //     trapnz arg
-    //     ..
-    //
-    // Becomes:
-    //
-    //     brz arg, new_block_resume
-    //     jump new_block_trap
-    //
-    //   new_block_trap:
-    //     trap
-    //
-    //   new_block_resume:
-    //     ..
-    let old_block = func.layout.pp_block(inst);
-    let new_block_trap = func.dfg.make_block();
-    let new_block_resume = func.dfg.make_block();
-
-    // Replace trap instruction by the inverted condition.
-    if trapz {
-        func.dfg.replace(inst).brnz(arg, new_block_resume, &[]);
-    } else {
-        func.dfg.replace(inst).brz(arg, new_block_resume, &[]);
-    }
-
-    // Add jump instruction after the inverted branch.
-    let mut pos = FuncCursor::new(func).after_inst(inst);
-    pos.use_srcloc(inst);
-    pos.ins().jump(new_block_trap, &[]);
-
-    // Insert the new label and the unconditional trap terminator.
-    pos.insert_block(new_block_trap);
-
-    match opcode {
-        ir::Opcode::Trapz | ir::Opcode::Trapnz => {
-            pos.ins().trap(code);
-        }
-        ir::Opcode::ResumableTrapnz => {
-            pos.ins().resumable_trap(code);
-            pos.ins().jump(new_block_resume, &[]);
-        }
-        _ => unreachable!(),
-    }
-
-    // Insert the new label and resume the execution when the trap fails.
-    pos.insert_block(new_block_resume);
-
-    // Finally update the CFG.
-    cfg.recompute_block(pos.func, old_block);
-    cfg.recompute_block(pos.func, new_block_resume);
-    cfg.recompute_block(pos.func, new_block_trap);
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/legalizer/table.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/legalizer/table.rs
deleted file mode 100644
index 2cefb91f2..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/legalizer/table.rs
+++ /dev/null
@@ -1,87 +0,0 @@
-//! Legalization of tables.
-//!
-//! This module exports the `expand_table_addr` function which transforms a `table_addr`
-//! instruction into code that depends on the kind of table referenced.
-
-use crate::cursor::{Cursor, FuncCursor};
-use crate::ir::condcodes::IntCC;
-use crate::ir::immediates::Offset32;
-use crate::ir::{self, InstBuilder};
-
-/// Expand a `table_addr` instruction according to the definition of the table.
-pub fn expand_table_addr(
-    inst: ir::Inst,
-    func: &mut ir::Function,
-    table: ir::Table,
-    index: ir::Value,
-    element_offset: Offset32,
-) {
-    let bound_gv = func.tables[table].bound_gv;
-    let index_ty = func.dfg.value_type(index);
-    let addr_ty = func.dfg.value_type(func.dfg.first_result(inst));
-    let mut pos = FuncCursor::new(func).at_inst(inst);
-    pos.use_srcloc(inst);
-
-    // Start with the bounds check. Trap if `index + 1 > bound`.
-    let bound = pos.ins().global_value(index_ty, bound_gv);
-
-    // `index > bound - 1` is the same as `index >= bound`.
-    let oob = pos
-        .ins()
-        .icmp(IntCC::UnsignedGreaterThanOrEqual, index, bound);
-    pos.ins().trapnz(oob, ir::TrapCode::TableOutOfBounds);
-
-    compute_addr(
-        inst,
-        table,
-        addr_ty,
-        index,
-        index_ty,
-        element_offset,
-        pos.func,
-    );
-}
-
-/// Emit code for the base address computation of a `table_addr` instruction.
-fn compute_addr(
-    inst: ir::Inst,
-    table: ir::Table,
-    addr_ty: ir::Type,
-    mut index: ir::Value,
-    index_ty: ir::Type,
-    element_offset: Offset32,
-    func: &mut ir::Function,
-) {
-    let mut pos = FuncCursor::new(func).at_inst(inst);
-    pos.use_srcloc(inst);
-
-    // Convert `index` to `addr_ty`.
-    if index_ty != addr_ty {
-        index = pos.ins().uextend(addr_ty, index);
-    }
-
-    // Add the table base address base
-    let base_gv = pos.func.tables[table].base_gv;
-    let base = pos.ins().global_value(addr_ty, base_gv);
-
-    let element_size = pos.func.tables[table].element_size;
-    let mut offset;
-    let element_size: u64 = element_size.into();
-    if element_size == 1 {
-        offset = index;
-    } else if element_size.is_power_of_two() {
-        offset = pos
-            .ins()
-            .ishl_imm(index, i64::from(element_size.trailing_zeros()));
-    } else {
-        offset = pos.ins().imul_imm(index, element_size as i64);
-    }
-
-    if element_offset == Offset32::new(0) {
-        pos.func.dfg.replace(inst).iadd(base, offset);
-    } else {
-        let imm: i64 = element_offset.into();
-        offset = pos.ins().iadd(base, offset);
-        pos.func.dfg.replace(inst).iadd_imm(offset, imm);
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/lib.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/lib.rs
deleted file mode 100644
index 3d5ca2003..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/lib.rs
+++ /dev/null
@@ -1,119 +0,0 @@
-//! Cranelift code generation library.
-#![deny(missing_docs, trivial_numeric_casts, unused_extern_crates)]
-#![warn(unused_import_braces)]
-#![cfg_attr(feature = "std", deny(unstable_features))]
-#![cfg_attr(feature = "clippy", plugin(clippy(conf_file = "../../clippy.toml")))]
-#![cfg_attr(feature="cargo-clippy", allow(
-// Produces only a false positive:
-                clippy::while_let_loop,
-// Produces many false positives, but did produce some valid lints, now fixed:
-                clippy::needless_lifetimes,
-// Generated code makes some style transgressions, but readability doesn't suffer much:
-                clippy::many_single_char_names,
-                clippy::identity_op,
-                clippy::needless_borrow,
-                clippy::cast_lossless,
-                clippy::unreadable_literal,
-                clippy::assign_op_pattern,
-                clippy::empty_line_after_outer_attr,
-// Hard to avoid in generated code:
-                clippy::cognitive_complexity,
-                clippy::too_many_arguments,
-// Code generator doesn't have a way to collapse identical arms:
-                clippy::match_same_arms,
-// These are relatively minor style issues, but would be easy to fix:
-                clippy::new_without_default,
-                clippy::should_implement_trait,
-                clippy::len_without_is_empty))]
-#![cfg_attr(
-    feature = "cargo-clippy",
-    warn(
-        clippy::float_arithmetic,
-        clippy::mut_mut,
-        clippy::nonminimal_bool,
-        clippy::map_unwrap_or,
-        clippy::unicode_not_nfc,
-        clippy::use_self
-    )
-)]
-#![no_std]
-// Various bits and pieces of this crate might only be used for one platform or
-// another, but it's not really too useful to learn about that all the time. On
-// CI we build at least one version of this crate with `--features all-arch`
-// which means we'll always detect truly dead code, otherwise if this is only
-// built for one platform we don't have to worry too much about trimming
-// everything down.
-#![cfg_attr(not(feature = "all-arch"), allow(dead_code))]
-
-#[allow(unused_imports)] // #[macro_use] is required for no_std
-#[macro_use]
-extern crate alloc;
-
-#[cfg(feature = "std")]
-#[macro_use]
-extern crate std;
-
-#[cfg(not(feature = "std"))]
-use hashbrown::{hash_map, HashMap, HashSet};
-#[cfg(feature = "std")]
-use std::collections::{hash_map, HashMap, HashSet};
-
-pub use crate::context::Context;
-pub use crate::value_label::{ValueLabelsRanges, ValueLocRange};
-pub use crate::verifier::verify_function;
-pub use crate::write::write_function;
-
-pub use cranelift_bforest as bforest;
-pub use cranelift_entity as entity;
-#[cfg(feature = "unwind")]
-pub use gimli;
-
-#[macro_use]
-mod machinst;
-
-pub mod binemit;
-pub mod cfg_printer;
-pub mod cursor;
-pub mod data_value;
-pub mod dbg;
-pub mod dominator_tree;
-pub mod flowgraph;
-pub mod ir;
-pub mod isa;
-pub mod loop_analysis;
-pub mod print_errors;
-pub mod settings;
-pub mod timing;
-pub mod verifier;
-pub mod write;
-
-pub use crate::entity::packed_option;
-pub use crate::machinst::buffer::{MachCallSite, MachReloc, MachSrcLoc, MachStackMap, MachTrap};
-pub use crate::machinst::TextSectionBuilder;
-
-mod bitset;
-mod constant_hash;
-mod context;
-mod dce;
-mod divconst_magic_numbers;
-mod fx;
-mod inst_predicates;
-mod iterators;
-mod legalizer;
-mod licm;
-mod log;
-mod nan_canonicalization;
-mod remove_constant_phis;
-mod result;
-mod scoped_hash_map;
-mod simple_gvn;
-mod simple_preopt;
-mod unreachable_code;
-mod value_label;
-
-#[cfg(feature = "souper-harvest")]
-mod souper_harvest;
-
-pub use crate::result::{CodegenError, CodegenResult};
-
-include!(concat!(env!("OUT_DIR"), "/version.rs"));
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/licm.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/licm.rs
deleted file mode 100644
index 3375a49a3..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/licm.rs
+++ /dev/null
@@ -1,245 +0,0 @@
-//! A Loop Invariant Code Motion optimization pass
-
-use crate::cursor::{Cursor, FuncCursor};
-use crate::dominator_tree::DominatorTree;
-use crate::entity::{EntityList, ListPool};
-use crate::flowgraph::{BlockPredecessor, ControlFlowGraph};
-use crate::fx::FxHashSet;
-use crate::ir::{
-    Block, DataFlowGraph, Function, Inst, InstBuilder, InstructionData, Layout, Opcode, Type, Value,
-};
-use crate::loop_analysis::{Loop, LoopAnalysis};
-use crate::timing;
-use alloc::vec::Vec;
-
-/// Performs the LICM pass by detecting loops within the CFG and moving
-/// loop-invariant instructions out of them.
-/// Changes the CFG and domtree in-place during the operation.
-pub fn do_licm(
-    func: &mut Function,
-    cfg: &mut ControlFlowGraph,
-    domtree: &mut DominatorTree,
-    loop_analysis: &mut LoopAnalysis,
-) {
-    let _tt = timing::licm();
-    debug_assert!(cfg.is_valid());
-    debug_assert!(domtree.is_valid());
-    debug_assert!(loop_analysis.is_valid());
-
-    for lp in loop_analysis.loops() {
-        // For each loop that we want to optimize we determine the set of loop-invariant
-        // instructions
-        let invariant_insts = remove_loop_invariant_instructions(lp, func, cfg, loop_analysis);
-        // Then we create the loop's pre-header and fill it with the invariant instructions
-        // Then we remove the invariant instructions from the loop body
-        if !invariant_insts.is_empty() {
-            // If the loop has a natural pre-header we use it, otherwise we create it.
-            let mut pos;
-            match has_pre_header(&func.layout, cfg, domtree, loop_analysis.loop_header(lp)) {
-                None => {
-                    let pre_header =
-                        create_pre_header(loop_analysis.loop_header(lp), func, cfg, domtree);
-                    pos = FuncCursor::new(func).at_last_inst(pre_header);
-                }
-                // If there is a natural pre-header we insert new instructions just before the
-                // related jumping instruction (which is not necessarily at the end).
-                Some((_, last_inst)) => {
-                    pos = FuncCursor::new(func).at_inst(last_inst);
-                }
-            };
-            // The last instruction of the pre-header is the termination instruction (usually
-            // a jump) so we need to insert just before this.
-            for inst in invariant_insts {
-                pos.insert_inst(inst);
-            }
-        }
-    }
-    // We have to recompute the domtree to account for the changes
-    cfg.compute(func);
-    domtree.compute(func, cfg);
-}
-
-/// Insert a pre-header before the header, modifying the function layout and CFG to reflect it.
-/// A jump instruction to the header is placed at the end of the pre-header.
-fn create_pre_header(
-    header: Block,
-    func: &mut Function,
-    cfg: &mut ControlFlowGraph,
-    domtree: &DominatorTree,
-) -> Block {
-    let pool = &mut ListPool::<Value>::new();
-    let header_args_values = func.dfg.block_params(header).to_vec();
-    let header_args_types: Vec<Type> = header_args_values
-        .into_iter()
-        .map(|val| func.dfg.value_type(val))
-        .collect();
-    let pre_header = func.dfg.make_block();
-    let mut pre_header_args_value: EntityList<Value> = EntityList::new();
-    for typ in header_args_types {
-        pre_header_args_value.push(func.dfg.append_block_param(pre_header, typ), pool);
-    }
-
-    for BlockPredecessor {
-        inst: last_inst, ..
-    } in cfg.pred_iter(header)
-    {
-        // We only follow normal edges (not the back edges)
-        if !domtree.dominates(header, last_inst, &func.layout) {
-            func.rewrite_branch_destination(last_inst, header, pre_header);
-        }
-    }
-
-    // Inserts the pre-header at the right place in the layout.
-    let mut pos = FuncCursor::new(func).at_top(header);
-    pos.insert_block(pre_header);
-    pos.next_inst();
-    pos.ins().jump(header, pre_header_args_value.as_slice(pool));
-
-    pre_header
-}
-
-/// Detects if a loop header has a natural pre-header.
-///
-/// A loop header has a pre-header if there is only one predecessor that the header doesn't
-/// dominate.
-/// Returns the pre-header Block and the instruction jumping to the header.
-fn has_pre_header(
-    layout: &Layout,
-    cfg: &ControlFlowGraph,
-    domtree: &DominatorTree,
-    header: Block,
-) -> Option<(Block, Inst)> {
-    let mut result = None;
-    for BlockPredecessor {
-        block: pred_block,
-        inst: branch_inst,
-    } in cfg.pred_iter(header)
-    {
-        // We only count normal edges (not the back edges)
-        if !domtree.dominates(header, branch_inst, layout) {
-            if result.is_some() {
-                // We have already found one, there are more than one
-                return None;
-            }
-            if branch_inst != layout.last_inst(pred_block).unwrap()
-                || cfg.succ_iter(pred_block).nth(1).is_some()
-            {
-                // It's along a critical edge, so don't use it.
-                return None;
-            }
-            result = Some((pred_block, branch_inst));
-        }
-    }
-    result
-}
-
-/// Test whether the given opcode is unsafe to even consider for LICM.
-fn trivially_unsafe_for_licm(opcode: Opcode) -> bool {
-    opcode.can_store()
-        || opcode.is_call()
-        || opcode.is_branch()
-        || opcode.is_terminator()
-        || opcode.is_return()
-        || opcode.can_trap()
-        || opcode.other_side_effects()
-        || opcode.writes_cpu_flags()
-}
-
-fn is_unsafe_load(inst_data: &InstructionData) -> bool {
-    match *inst_data {
-        InstructionData::Load { flags, .. } | InstructionData::LoadComplex { flags, .. } => {
-            !flags.readonly() || !flags.notrap()
-        }
-        _ => inst_data.opcode().can_load(),
-    }
-}
-
-/// Test whether the given instruction is loop-invariant.
-fn is_loop_invariant(inst: Inst, dfg: &DataFlowGraph, loop_values: &FxHashSet<Value>) -> bool {
-    if trivially_unsafe_for_licm(dfg[inst].opcode()) {
-        return false;
-    }
-
-    if is_unsafe_load(&dfg[inst]) {
-        return false;
-    }
-
-    let inst_args = dfg.inst_args(inst);
-    for arg in inst_args {
-        let arg = dfg.resolve_aliases(*arg);
-        if loop_values.contains(&arg) {
-            return false;
-        }
-    }
-    true
-}
-
-/// Traverses a loop in reverse post-order from a header block and identify loop-invariant
-/// instructions. These loop-invariant instructions are then removed from the code and returned
-/// (in reverse post-order) for later use.
-fn remove_loop_invariant_instructions(
-    lp: Loop,
-    func: &mut Function,
-    cfg: &ControlFlowGraph,
-    loop_analysis: &LoopAnalysis,
-) -> Vec<Inst> {
-    let mut loop_values: FxHashSet<Value> = FxHashSet();
-    let mut invariant_insts: Vec<Inst> = Vec::new();
-    let mut pos = FuncCursor::new(func);
-    // We traverse the loop block in reverse post-order.
-    for block in postorder_blocks_loop(loop_analysis, cfg, lp).iter().rev() {
-        // Arguments of the block are loop values
-        for val in pos.func.dfg.block_params(*block) {
-            loop_values.insert(*val);
-        }
-        pos.goto_top(*block);
-        #[cfg_attr(feature = "cargo-clippy", allow(clippy::block_in_if_condition_stmt))]
-        while let Some(inst) = pos.next_inst() {
-            if is_loop_invariant(inst, &pos.func.dfg, &loop_values) {
-                // If all the instruction's argument are defined outside the loop
-                // then this instruction is loop-invariant
-                invariant_insts.push(inst);
-                // We remove it from the loop
-                pos.remove_inst_and_step_back();
-            } else {
-                // If the instruction is not loop-invariant we push its results in the set of
-                // loop values
-                for out in pos.func.dfg.inst_results(inst) {
-                    loop_values.insert(*out);
-                }
-            }
-        }
-    }
-    invariant_insts
-}
-
-/// Return blocks from a loop in post-order, starting from an entry point in the block.
-fn postorder_blocks_loop(
-    loop_analysis: &LoopAnalysis,
-    cfg: &ControlFlowGraph,
-    lp: Loop,
-) -> Vec<Block> {
-    let mut grey = FxHashSet();
-    let mut black = FxHashSet();
-    let mut stack = vec![loop_analysis.loop_header(lp)];
-    let mut postorder = Vec::new();
-
-    while !stack.is_empty() {
-        let node = stack.pop().unwrap();
-        if !grey.contains(&node) {
-            // This is a white node. Mark it as gray.
-            grey.insert(node);
-            stack.push(node);
-            // Get any children we've never seen before.
-            for child in cfg.succ_iter(node) {
-                if loop_analysis.is_in_loop(child, lp) && !grey.contains(&child) {
-                    stack.push(child);
-                }
-            }
-        } else if !black.contains(&node) {
-            postorder.push(node);
-            black.insert(node);
-        }
-    }
-    postorder
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/log.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/log.rs
deleted file mode 100644
index c5bd59aa5..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/log.rs
+++ /dev/null
@@ -1,39 +0,0 @@
-//! This module implements deferred display helpers.
-//!
-//! These are particularly useful in logging contexts, where the maximum logging level filter might
-//! be enabled, but we don't want the arguments to be evaluated early:
-//!
-//! ```
-//! log::set_max_level(log::LevelFilter::max());
-//! fn expensive_calculation() -> String {
-//!   "a string that is very slow to generate".into()
-//! }
-//! log::debug!("{}", expensive_calculation());
-//! ```
-//!
-//! If the associated log implementation filters out log debug entries, the expensive calculation
-//! would have been spurious. In this case, we can wrap the expensive computation within an
-//! `DeferredDisplay`, so that the computation only happens when the actual `fmt` function is
-//! called.
-
-use core::fmt;
-
-pub(crate) struct DeferredDisplay<F>(F);
-
-impl<F: Fn() -> T, T: fmt::Display> DeferredDisplay<F> {
-    pub(crate) fn new(f: F) -> Self {
-        Self(f)
-    }
-}
-
-impl<F: Fn() -> T, T: fmt::Display> fmt::Display for DeferredDisplay<F> {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        self.0().fmt(f)
-    }
-}
-
-impl<F: Fn() -> T, T: fmt::Debug> fmt::Debug for DeferredDisplay<F> {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        self.0().fmt(f)
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/loop_analysis.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/loop_analysis.rs
deleted file mode 100644
index 0e8715ae9..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/loop_analysis.rs
+++ /dev/null
@@ -1,349 +0,0 @@
-//! A loop analysis represented as mappings of loops to their header Block
-//! and parent in the loop tree.
-
-use crate::dominator_tree::DominatorTree;
-use crate::entity::entity_impl;
-use crate::entity::SecondaryMap;
-use crate::entity::{Keys, PrimaryMap};
-use crate::flowgraph::{BlockPredecessor, ControlFlowGraph};
-use crate::ir::{Block, Function, Layout};
-use crate::packed_option::PackedOption;
-use crate::timing;
-use alloc::vec::Vec;
-
-/// A opaque reference to a code loop.
-#[derive(Copy, Clone, PartialEq, Eq, Hash)]
-pub struct Loop(u32);
-entity_impl!(Loop, "loop");
-
-/// Loop tree information for a single function.
-///
-/// Loops are referenced by the Loop object, and for each loop you can access its header block,
-/// its eventual parent in the loop tree and all the block belonging to the loop.
-pub struct LoopAnalysis {
-    loops: PrimaryMap<Loop, LoopData>,
-    block_loop_map: SecondaryMap<Block, PackedOption<Loop>>,
-    valid: bool,
-}
-
-struct LoopData {
-    header: Block,
-    parent: PackedOption<Loop>,
-}
-
-impl LoopData {
-    /// Creates a `LoopData` object with the loop header and its eventual parent in the loop tree.
-    pub fn new(header: Block, parent: Option<Loop>) -> Self {
-        Self {
-            header,
-            parent: parent.into(),
-        }
-    }
-}
-
-/// Methods for querying the loop analysis.
-impl LoopAnalysis {
-    /// Allocate a new blank loop analysis struct. Use `compute` to compute the loop analysis for
-    /// a function.
-    pub fn new() -> Self {
-        Self {
-            valid: false,
-            loops: PrimaryMap::new(),
-            block_loop_map: SecondaryMap::new(),
-        }
-    }
-
-    /// Returns all the loops contained in a function.
-    pub fn loops(&self) -> Keys<Loop> {
-        self.loops.keys()
-    }
-
-    /// Returns the header block of a particular loop.
-    ///
-    /// The characteristic property of a loop header block is that it dominates some of its
-    /// predecessors.
-    pub fn loop_header(&self, lp: Loop) -> Block {
-        self.loops[lp].header
-    }
-
-    /// Return the eventual parent of a loop in the loop tree.
-    pub fn loop_parent(&self, lp: Loop) -> Option<Loop> {
-        self.loops[lp].parent.expand()
-    }
-
-    /// Determine if a Block belongs to a loop by running a finger along the loop tree.
-    ///
-    /// Returns `true` if `block` is in loop `lp`.
-    pub fn is_in_loop(&self, block: Block, lp: Loop) -> bool {
-        let block_loop = self.block_loop_map[block];
-        match block_loop.expand() {
-            None => false,
-            Some(block_loop) => self.is_child_loop(block_loop, lp),
-        }
-    }
-
-    /// Determines if a loop is contained in another loop.
-    ///
-    /// `is_child_loop(child,parent)` returns `true` if and only if `child` is a child loop of
-    /// `parent` (or `child == parent`).
-    pub fn is_child_loop(&self, child: Loop, parent: Loop) -> bool {
-        let mut finger = Some(child);
-        while let Some(finger_loop) = finger {
-            if finger_loop == parent {
-                return true;
-            }
-            finger = self.loop_parent(finger_loop);
-        }
-        false
-    }
-}
-
-impl LoopAnalysis {
-    /// Detects the loops in a function. Needs the control flow graph and the dominator tree.
-    pub fn compute(&mut self, func: &Function, cfg: &ControlFlowGraph, domtree: &DominatorTree) {
-        let _tt = timing::loop_analysis();
-        self.loops.clear();
-        self.block_loop_map.clear();
-        self.block_loop_map.resize(func.dfg.num_blocks());
-        self.find_loop_headers(cfg, domtree, &func.layout);
-        self.discover_loop_blocks(cfg, domtree, &func.layout);
-        self.valid = true;
-    }
-
-    /// Check if the loop analysis is in a valid state.
-    ///
-    /// Note that this doesn't perform any kind of validity checks. It simply checks if the
-    /// `compute()` method has been called since the last `clear()`. It does not check that the
-    /// loop analysis is consistent with the CFG.
-    pub fn is_valid(&self) -> bool {
-        self.valid
-    }
-
-    /// Clear all the data structures contained in the loop analysis. This will leave the
-    /// analysis in a similar state to a context returned by `new()` except that allocated
-    /// memory be retained.
-    pub fn clear(&mut self) {
-        self.loops.clear();
-        self.block_loop_map.clear();
-        self.valid = false;
-    }
-
-    // Traverses the CFG in reverse postorder and create a loop object for every block having a
-    // back edge.
-    fn find_loop_headers(
-        &mut self,
-        cfg: &ControlFlowGraph,
-        domtree: &DominatorTree,
-        layout: &Layout,
-    ) {
-        // We traverse the CFG in reverse postorder
-        for &block in domtree.cfg_postorder().iter().rev() {
-            for BlockPredecessor {
-                inst: pred_inst, ..
-            } in cfg.pred_iter(block)
-            {
-                // If the block dominates one of its predecessors it is a back edge
-                if domtree.dominates(block, pred_inst, layout) {
-                    // This block is a loop header, so we create its associated loop
-                    let lp = self.loops.push(LoopData::new(block, None));
-                    self.block_loop_map[block] = lp.into();
-                    break;
-                    // We break because we only need one back edge to identify a loop header.
-                }
-            }
-        }
-    }
-
-    // Intended to be called after `find_loop_headers`. For each detected loop header,
-    // discovers all the block belonging to the loop and its inner loops. After a call to this
-    // function, the loop tree is fully constructed.
-    fn discover_loop_blocks(
-        &mut self,
-        cfg: &ControlFlowGraph,
-        domtree: &DominatorTree,
-        layout: &Layout,
-    ) {
-        let mut stack: Vec<Block> = Vec::new();
-        // We handle each loop header in reverse order, corresponding to a pseudo postorder
-        // traversal of the graph.
-        for lp in self.loops().rev() {
-            for BlockPredecessor {
-                block: pred,
-                inst: pred_inst,
-            } in cfg.pred_iter(self.loops[lp].header)
-            {
-                // We follow the back edges
-                if domtree.dominates(self.loops[lp].header, pred_inst, layout) {
-                    stack.push(pred);
-                }
-            }
-            while let Some(node) = stack.pop() {
-                let continue_dfs: Option<Block>;
-                match self.block_loop_map[node].expand() {
-                    None => {
-                        // The node hasn't been visited yet, we tag it as part of the loop
-                        self.block_loop_map[node] = PackedOption::from(lp);
-                        continue_dfs = Some(node);
-                    }
-                    Some(node_loop) => {
-                        // We copy the node_loop into a mutable reference passed along the while
-                        let mut node_loop = node_loop;
-                        // The node is part of a loop, which can be lp or an inner loop
-                        let mut node_loop_parent_option = self.loops[node_loop].parent;
-                        while let Some(node_loop_parent) = node_loop_parent_option.expand() {
-                            if node_loop_parent == lp {
-                                // We have encountered lp so we stop (already visited)
-                                break;
-                            } else {
-                                //
-                                node_loop = node_loop_parent;
-                                // We lookup the parent loop
-                                node_loop_parent_option = self.loops[node_loop].parent;
-                            }
-                        }
-                        // Now node_loop_parent is either:
-                        // - None and node_loop is an new inner loop of lp
-                        // - Some(...) and the initial node_loop was a known inner loop of lp
-                        match node_loop_parent_option.expand() {
-                            Some(_) => continue_dfs = None,
-                            None => {
-                                if node_loop != lp {
-                                    self.loops[node_loop].parent = lp.into();
-                                    continue_dfs = Some(self.loops[node_loop].header)
-                                } else {
-                                    // If lp is a one-block loop then we make sure we stop
-                                    continue_dfs = None
-                                }
-                            }
-                        }
-                    }
-                }
-                // Now we have handled the popped node and need to continue the DFS by adding the
-                // predecessors of that node
-                if let Some(continue_dfs) = continue_dfs {
-                    for BlockPredecessor { block: pred, .. } in cfg.pred_iter(continue_dfs) {
-                        stack.push(pred)
-                    }
-                }
-            }
-        }
-    }
-}
-
-#[cfg(test)]
-mod tests {
-    use crate::cursor::{Cursor, FuncCursor};
-    use crate::dominator_tree::DominatorTree;
-    use crate::flowgraph::ControlFlowGraph;
-    use crate::ir::{types, Function, InstBuilder};
-    use crate::loop_analysis::{Loop, LoopAnalysis};
-    use alloc::vec::Vec;
-
-    #[test]
-    fn nested_loops_detection() {
-        let mut func = Function::new();
-        let block0 = func.dfg.make_block();
-        let block1 = func.dfg.make_block();
-        let block2 = func.dfg.make_block();
-        let block3 = func.dfg.make_block();
-        let cond = func.dfg.append_block_param(block0, types::I32);
-
-        {
-            let mut cur = FuncCursor::new(&mut func);
-
-            cur.insert_block(block0);
-            cur.ins().jump(block1, &[]);
-
-            cur.insert_block(block1);
-            cur.ins().jump(block2, &[]);
-
-            cur.insert_block(block2);
-            cur.ins().brnz(cond, block1, &[]);
-            cur.ins().jump(block3, &[]);
-
-            cur.insert_block(block3);
-            cur.ins().brnz(cond, block0, &[]);
-        }
-
-        let mut loop_analysis = LoopAnalysis::new();
-        let mut cfg = ControlFlowGraph::new();
-        let mut domtree = DominatorTree::new();
-        cfg.compute(&func);
-        domtree.compute(&func, &cfg);
-        loop_analysis.compute(&func, &cfg, &domtree);
-
-        let loops = loop_analysis.loops().collect::<Vec<Loop>>();
-        assert_eq!(loops.len(), 2);
-        assert_eq!(loop_analysis.loop_header(loops[0]), block0);
-        assert_eq!(loop_analysis.loop_header(loops[1]), block1);
-        assert_eq!(loop_analysis.loop_parent(loops[1]), Some(loops[0]));
-        assert_eq!(loop_analysis.loop_parent(loops[0]), None);
-        assert_eq!(loop_analysis.is_in_loop(block0, loops[0]), true);
-        assert_eq!(loop_analysis.is_in_loop(block0, loops[1]), false);
-        assert_eq!(loop_analysis.is_in_loop(block1, loops[1]), true);
-        assert_eq!(loop_analysis.is_in_loop(block1, loops[0]), true);
-        assert_eq!(loop_analysis.is_in_loop(block2, loops[1]), true);
-        assert_eq!(loop_analysis.is_in_loop(block2, loops[0]), true);
-        assert_eq!(loop_analysis.is_in_loop(block3, loops[0]), true);
-        assert_eq!(loop_analysis.is_in_loop(block0, loops[1]), false);
-    }
-
-    #[test]
-    fn complex_loop_detection() {
-        let mut func = Function::new();
-        let block0 = func.dfg.make_block();
-        let block1 = func.dfg.make_block();
-        let block2 = func.dfg.make_block();
-        let block3 = func.dfg.make_block();
-        let block4 = func.dfg.make_block();
-        let block5 = func.dfg.make_block();
-        let cond = func.dfg.append_block_param(block0, types::I32);
-
-        {
-            let mut cur = FuncCursor::new(&mut func);
-
-            cur.insert_block(block0);
-            cur.ins().brnz(cond, block1, &[]);
-            cur.ins().jump(block3, &[]);
-
-            cur.insert_block(block1);
-            cur.ins().jump(block2, &[]);
-
-            cur.insert_block(block2);
-            cur.ins().brnz(cond, block1, &[]);
-            cur.ins().jump(block5, &[]);
-
-            cur.insert_block(block3);
-            cur.ins().jump(block4, &[]);
-
-            cur.insert_block(block4);
-            cur.ins().brnz(cond, block3, &[]);
-            cur.ins().jump(block5, &[]);
-
-            cur.insert_block(block5);
-            cur.ins().brnz(cond, block0, &[]);
-        }
-
-        let mut loop_analysis = LoopAnalysis::new();
-        let mut cfg = ControlFlowGraph::new();
-        let mut domtree = DominatorTree::new();
-        cfg.compute(&func);
-        domtree.compute(&func, &cfg);
-        loop_analysis.compute(&func, &cfg, &domtree);
-
-        let loops = loop_analysis.loops().collect::<Vec<Loop>>();
-        assert_eq!(loops.len(), 3);
-        assert_eq!(loop_analysis.loop_header(loops[0]), block0);
-        assert_eq!(loop_analysis.loop_header(loops[1]), block1);
-        assert_eq!(loop_analysis.loop_header(loops[2]), block3);
-        assert_eq!(loop_analysis.loop_parent(loops[1]), Some(loops[0]));
-        assert_eq!(loop_analysis.loop_parent(loops[2]), Some(loops[0]));
-        assert_eq!(loop_analysis.loop_parent(loops[0]), None);
-        assert_eq!(loop_analysis.is_in_loop(block0, loops[0]), true);
-        assert_eq!(loop_analysis.is_in_loop(block1, loops[1]), true);
-        assert_eq!(loop_analysis.is_in_loop(block2, loops[1]), true);
-        assert_eq!(loop_analysis.is_in_loop(block3, loops[2]), true);
-        assert_eq!(loop_analysis.is_in_loop(block4, loops[2]), true);
-        assert_eq!(loop_analysis.is_in_loop(block5, loops[0]), true);
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/abi.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/abi.rs
deleted file mode 100644
index d32993d1c..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/abi.rs
+++ /dev/null
@@ -1,245 +0,0 @@
-//! ABI definitions.
-
-use crate::binemit::StackMap;
-use crate::ir::{Signature, StackSlot};
-use crate::isa::CallConv;
-use crate::machinst::*;
-use crate::settings;
-use regalloc::{Reg, Set, SpillSlot, Writable};
-use smallvec::SmallVec;
-
-/// A small vector of instructions (with some reasonable size); appropriate for
-/// a small fixed sequence implementing one operation.
-pub type SmallInstVec<I> = SmallVec<[I; 4]>;
-
-/// Trait implemented by an object that tracks ABI-related state (e.g., stack
-/// layout) and can generate code while emitting the *body* of a function.
-pub trait ABICallee {
-    /// The instruction type for the ISA associated with this ABI.
-    type I: VCodeInst;
-
-    /// Does the ABI-body code need a temp reg (and if so, of what type)? One
-    /// will be provided to `init()` as the `maybe_tmp` arg if so.
-    fn temp_needed(&self) -> Option<Type>;
-
-    /// Initialize. This is called after the ABICallee is constructed because it
-    /// may be provided with a temp vreg, which can only be allocated once the
-    /// lowering context exists.
-    fn init(&mut self, maybe_tmp: Option<Writable<Reg>>);
-
-    /// Access the (possibly legalized) signature.
-    fn signature(&self) -> &Signature;
-
-    /// Accumulate outgoing arguments.  This ensures that at least SIZE bytes
-    /// are allocated in the prologue to be available for use in function calls
-    /// to hold arguments and/or return values.  If this function is called
-    /// multiple times, the maximum of all SIZE values will be available.
-    fn accumulate_outgoing_args_size(&mut self, size: u32);
-
-    /// Get the settings controlling this function's compilation.
-    fn flags(&self) -> &settings::Flags;
-
-    /// Get the calling convention implemented by this ABI object.
-    fn call_conv(&self) -> CallConv;
-
-    /// Get the liveins of the function.
-    fn liveins(&self) -> Set<RealReg>;
-
-    /// Get the liveouts of the function.
-    fn liveouts(&self) -> Set<RealReg>;
-
-    /// Number of arguments.
-    fn num_args(&self) -> usize;
-
-    /// Number of return values.
-    fn num_retvals(&self) -> usize;
-
-    /// Number of stack slots (not spill slots).
-    fn num_stackslots(&self) -> usize;
-
-    /// The offsets of all stack slots (not spill slots) for debuginfo purposes.
-    fn stackslot_offsets(&self) -> &PrimaryMap<StackSlot, u32>;
-
-    /// Generate an instruction which copies an argument to a destination
-    /// register.
-    fn gen_copy_arg_to_regs(
-        &self,
-        idx: usize,
-        into_reg: ValueRegs<Writable<Reg>>,
-    ) -> SmallInstVec<Self::I>;
-
-    /// Is the given argument needed in the body (as opposed to, e.g., serving
-    /// only as a special ABI-specific placeholder)? This controls whether
-    /// lowering will copy it to a virtual reg use by CLIF instructions.
-    fn arg_is_needed_in_body(&self, idx: usize) -> bool;
-
-    /// Generate any setup instruction needed to save values to the
-    /// return-value area. This is usually used when were are multiple return
-    /// values or an otherwise large return value that must be passed on the
-    /// stack; typically the ABI specifies an extra hidden argument that is a
-    /// pointer to that memory.
-    fn gen_retval_area_setup(&self) -> Option<Self::I>;
-
-    /// Generate an instruction which copies a source register to a return value slot.
-    fn gen_copy_regs_to_retval(
-        &self,
-        idx: usize,
-        from_reg: ValueRegs<Writable<Reg>>,
-    ) -> SmallInstVec<Self::I>;
-
-    /// Generate a return instruction.
-    fn gen_ret(&self) -> Self::I;
-
-    /// Generate an epilogue placeholder. The returned instruction should return `true` from
-    /// `is_epilogue_placeholder()`; this is used to indicate to the lowering driver when
-    /// the epilogue should be inserted.
-    fn gen_epilogue_placeholder(&self) -> Self::I;
-
-    // -----------------------------------------------------------------
-    // Every function above this line may only be called pre-regalloc.
-    // Every function below this line may only be called post-regalloc.
-    // `spillslots()` must be called before any other post-regalloc
-    // function.
-    // ----------------------------------------------------------------
-
-    /// Update with the number of spillslots, post-regalloc.
-    fn set_num_spillslots(&mut self, slots: usize);
-
-    /// Update with the clobbered registers, post-regalloc.
-    fn set_clobbered(&mut self, clobbered: Set<Writable<RealReg>>);
-
-    /// Get the address of a stackslot.
-    fn stackslot_addr(&self, slot: StackSlot, offset: u32, into_reg: Writable<Reg>) -> Self::I;
-
-    /// Load from a spillslot.
-    fn load_spillslot(
-        &self,
-        slot: SpillSlot,
-        ty: Type,
-        into_reg: ValueRegs<Writable<Reg>>,
-    ) -> SmallInstVec<Self::I>;
-
-    /// Store to a spillslot.
-    fn store_spillslot(
-        &self,
-        slot: SpillSlot,
-        ty: Type,
-        from_reg: ValueRegs<Reg>,
-    ) -> SmallInstVec<Self::I>;
-
-    /// Generate a stack map, given a list of spillslots and the emission state
-    /// at a given program point (prior to emission fo the safepointing
-    /// instruction).
-    fn spillslots_to_stack_map(
-        &self,
-        slots: &[SpillSlot],
-        state: &<Self::I as MachInstEmit>::State,
-    ) -> StackMap;
-
-    /// Generate a prologue, post-regalloc. This should include any stack
-    /// frame or other setup necessary to use the other methods (`load_arg`,
-    /// `store_retval`, and spillslot accesses.)  `self` is mutable so that we
-    /// can store information in it which will be useful when creating the
-    /// epilogue.
-    fn gen_prologue(&mut self) -> SmallInstVec<Self::I>;
-
-    /// Generate an epilogue, post-regalloc. Note that this must generate the
-    /// actual return instruction (rather than emitting this in the lowering
-    /// logic), because the epilogue code comes before the return and the two are
-    /// likely closely related.
-    fn gen_epilogue(&self) -> SmallInstVec<Self::I>;
-
-    /// Returns the full frame size for the given function, after prologue
-    /// emission has run. This comprises the spill slots and stack-storage slots
-    /// (but not storage for clobbered callee-save registers, arguments pushed
-    /// at callsites within this function, or other ephemeral pushes).  This is
-    /// used for ABI variants where the client generates prologue/epilogue code,
-    /// as in Baldrdash (SpiderMonkey integration).
-    fn frame_size(&self) -> u32;
-
-    /// Returns the size of arguments expected on the stack.
-    fn stack_args_size(&self) -> u32;
-
-    /// Get the spill-slot size.
-    fn get_spillslot_size(&self, rc: RegClass) -> u32;
-
-    /// Generate a spill.
-    fn gen_spill(&self, to_slot: SpillSlot, from_reg: RealReg) -> Self::I;
-
-    /// Generate a reload (fill).
-    fn gen_reload(&self, to_reg: Writable<RealReg>, from_slot: SpillSlot) -> Self::I;
-}
-
-/// Trait implemented by an object that tracks ABI-related state and can
-/// generate code while emitting a *call* to a function.
-///
-/// An instance of this trait returns information for a *particular*
-/// callsite. It will usually be computed from the called function's
-/// signature.
-///
-/// Unlike `ABICallee` above, methods on this trait are not invoked directly
-/// by the machine-independent code. Rather, the machine-specific lowering
-/// code will typically create an `ABICaller` when creating machine instructions
-/// for an IR call instruction inside `lower()`, directly emit the arg and
-/// and retval copies, and attach the register use/def info to the call.
-///
-/// This trait is thus provided for convenience to the backends.
-pub trait ABICaller {
-    /// The instruction type for the ISA associated with this ABI.
-    type I: VCodeInst;
-
-    /// Get the number of arguments expected.
-    fn num_args(&self) -> usize;
-
-    /// Access the (possibly legalized) signature.
-    fn signature(&self) -> &Signature;
-
-    /// Emit a copy of an argument value from a source register, prior to the call.
-    fn emit_copy_regs_to_arg<C: LowerCtx<I = Self::I>>(
-        &self,
-        ctx: &mut C,
-        idx: usize,
-        from_reg: ValueRegs<Reg>,
-    );
-
-    /// Specific order for copying into arguments at callsites. We must be
-    /// careful to copy into StructArgs first, because we need to be able
-    /// to invoke memcpy() before we've loaded other arg regs (see above).
-    fn get_copy_to_arg_order(&self) -> SmallVec<[usize; 8]>;
-
-    /// Emit a copy a return value into a destination register, after the call returns.
-    fn emit_copy_retval_to_regs<C: LowerCtx<I = Self::I>>(
-        &self,
-        ctx: &mut C,
-        idx: usize,
-        into_reg: ValueRegs<Writable<Reg>>,
-    );
-
-    /// Emit code to pre-adjust the stack, prior to argument copies and call.
-    fn emit_stack_pre_adjust<C: LowerCtx<I = Self::I>>(&self, ctx: &mut C);
-
-    /// Emit code to post-adjust the satck, after call return and return-value copies.
-    fn emit_stack_post_adjust<C: LowerCtx<I = Self::I>>(&self, ctx: &mut C);
-
-    /// Accumulate outgoing arguments.  This ensures that the caller (as
-    /// identified via the CTX argument) allocates enough space in the
-    /// prologue to hold all arguments and return values for this call.
-    /// There is no code emitted at the call site, everything is done
-    /// in the caller's function prologue.
-    fn accumulate_outgoing_args_size<C: LowerCtx<I = Self::I>>(&self, ctx: &mut C);
-
-    /// Emit the call itself.
-    ///
-    /// The returned instruction should have proper use- and def-sets according
-    /// to the argument registers, return-value registers, and clobbered
-    /// registers for this function signature in this ABI.
-    ///
-    /// (Arg registers are uses, and retval registers are defs. Clobbered
-    /// registers are also logically defs, but should never be read; their
-    /// values are "defined" (to the regalloc) but "undefined" in every other
-    /// sense.)
-    ///
-    /// This function should only be called once, as it is allowed to re-use
-    /// parts of the ABICaller object in emitting instructions.
-    fn emit_call<C: LowerCtx<I = Self::I>>(&mut self, ctx: &mut C);
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/abi_impl.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/abi_impl.rs
deleted file mode 100644
index 065ee7074..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/abi_impl.rs
+++ /dev/null
@@ -1,1736 +0,0 @@
-//! Implementation of a vanilla ABI, shared between several machines. The
-//! implementation here assumes that arguments will be passed in registers
-//! first, then additional args on the stack; that the stack grows downward,
-//! contains a standard frame (return address and frame pointer), and the
-//! compiler is otherwise free to allocate space below that with its choice of
-//! layout; and that the machine has some notion of caller- and callee-save
-//! registers. Most modern machines, e.g. x86-64 and AArch64, should fit this
-//! mold and thus both of these backends use this shared implementation.
-//!
-//! See the documentation in specific machine backends for the "instantiation"
-//! of this generic ABI, i.e., which registers are caller/callee-save, arguments
-//! and return values, and any other special requirements.
-//!
-//! For now the implementation here assumes a 64-bit machine, but we intend to
-//! make this 32/64-bit-generic shortly.
-//!
-//! # Vanilla ABI
-//!
-//! First, arguments and return values are passed in registers up to a certain
-//! fixed count, after which they overflow onto the stack. Multiple return
-//! values either fit in registers, or are returned in a separate return-value
-//! area on the stack, given by a hidden extra parameter.
-//!
-//! Note that the exact stack layout is up to us. We settled on the
-//! below design based on several requirements. In particular, we need
-//! to be able to generate instructions (or instruction sequences) to
-//! access arguments, stack slots, and spill slots before we know how
-//! many spill slots or clobber-saves there will be, because of our
-//! pass structure. We also prefer positive offsets to negative
-//! offsets because of an asymmetry in some machines' addressing modes
-//! (e.g., on AArch64, positive offsets have a larger possible range
-//! without a long-form sequence to synthesize an arbitrary
-//! offset). We also need clobber-save registers to be "near" the
-//! frame pointer: Windows unwind information requires it to be within
-//! 240 bytes of RBP. Finally, it is not allowed to access memory
-//! below the current SP value.
-//!
-//! We assume that a prologue first pushes the frame pointer (and
-//! return address above that, if the machine does not do that in
-//! hardware). We set FP to point to this two-word frame record. We
-//! store all other frame slots below this two-word frame record, with
-//! the stack pointer remaining at or below this fixed frame storage
-//! for the rest of the function. We can then access frame storage
-//! slots using positive offsets from SP. In order to allow codegen
-//! for the latter before knowing how SP might be adjusted around
-//! callsites, we implement a "nominal SP" tracking feature by which a
-//! fixup (distance between actual SP and a "nominal" SP) is known at
-//! each instruction.
-//!
-//! Note that if we ever support dynamic stack-space allocation (for
-//! `alloca`), we will need a way to reference spill slots and stack
-//! slots without "nominal SP", because we will no longer be able to
-//! know a static offset from SP to the slots at any particular
-//! program point. Probably the best solution at that point will be to
-//! revert to using the frame pointer as the reference for all slots,
-//! and creating a "nominal FP" synthetic addressing mode (analogous
-//! to "nominal SP" today) to allow generating spill/reload and
-//! stackslot accesses before we know how large the clobber-saves will
-//! be.
-//!
-//! # Stack Layout
-//!
-//! The stack looks like:
-//!
-//! ```plain
-//!   (high address)
-//!
-//!                              +---------------------------+
-//!                              |          ...              |
-//!                              | stack args                |
-//!                              | (accessed via FP)         |
-//!                              +---------------------------+
-//! SP at function entry ----->  | return address            |
-//!                              +---------------------------+
-//! FP after prologue -------->  | FP (pushed by prologue)   |
-//!                              +---------------------------+
-//!                              |          ...              |
-//!                              | clobbered callee-saves    |
-//! unwind-frame base     ---->  | (pushed by prologue)      |
-//!                              +---------------------------+
-//!                              |          ...              |
-//!                              | spill slots               |
-//!                              | (accessed via nominal SP) |
-//!                              |          ...              |
-//!                              | stack slots               |
-//!                              | (accessed via nominal SP) |
-//! nominal SP --------------->  | (alloc'd by prologue)     |
-//! (SP at end of prologue)      +---------------------------+
-//!                              | [alignment as needed]     |
-//!                              |          ...              |
-//!                              | args for call             |
-//! SP before making a call -->  | (pushed at callsite)      |
-//!                              +---------------------------+
-//!
-//!   (low address)
-//! ```
-//!
-//! # Multi-value Returns
-//!
-//! Note that we support multi-value returns in two ways. First, we allow for
-//! multiple return-value registers. Second, if teh appropriate flag is set, we
-//! support the SpiderMonkey Wasm ABI.  For details of the multi-value return
-//! ABI, see:
-//!
-//! <https://searchfox.org/mozilla-central/rev/bc3600def806859c31b2c7ac06e3d69271052a89/js/src/wasm/WasmStubs.h#134>
-//!
-//! In brief:
-//! - Return values are processed in *reverse* order.
-//! - The first return value in this order (so the last return) goes into the
-//!   ordinary return register.
-//! - Any further returns go in a struct-return area, allocated upwards (in
-//!   address order) during the reverse traversal.
-//! - This struct-return area is provided by the caller, and a pointer to its
-//!   start is passed as an invisible last (extra) argument. Normally the caller
-//!   will allocate this area on the stack. When we generate calls, we place it
-//!   just above the on-stack argument area.
-//! - So, for example, a function returning 4 i64's (v0, v1, v2, v3), with no
-//!   formal arguments, would:
-//!   - Accept a pointer `P` to the struct return area as a hidden argument in the
-//!     first argument register on entry.
-//!   - Return v3 in the one and only return-value register.
-//!   - Return v2 in memory at `[P]`.
-//!   - Return v1 in memory at `[P+8]`.
-//!   - Return v0 in memory at `[P+16]`.
-
-use super::abi::*;
-use crate::binemit::StackMap;
-use crate::ir::types::*;
-use crate::ir::{ArgumentExtension, ArgumentPurpose, StackSlot};
-use crate::machinst::*;
-use crate::settings;
-use crate::CodegenResult;
-use crate::{ir, isa};
-use alloc::vec::Vec;
-use regalloc::{RealReg, Reg, RegClass, Set, SpillSlot, Writable};
-use smallvec::{smallvec, SmallVec};
-use std::convert::TryFrom;
-use std::marker::PhantomData;
-use std::mem;
-
-/// A location for (part of) an argument or return value. These "storage slots"
-/// are specified for each register-sized part of an argument.
-#[derive(Clone, Copy, Debug, PartialEq, Eq)]
-pub enum ABIArgSlot {
-    /// In a real register.
-    Reg {
-        /// Register that holds this arg.
-        reg: RealReg,
-        /// Value type of this arg.
-        ty: ir::Type,
-        /// Should this arg be zero- or sign-extended?
-        extension: ir::ArgumentExtension,
-    },
-    /// Arguments only: on stack, at given offset from SP at entry.
-    Stack {
-        /// Offset of this arg relative to the base of stack args.
-        offset: i64,
-        /// Value type of this arg.
-        ty: ir::Type,
-        /// Should this arg be zero- or sign-extended?
-        extension: ir::ArgumentExtension,
-    },
-}
-
-/// An ABIArg is composed of one or more parts. This allows for a CLIF-level
-/// Value to be passed with its parts in more than one location at the ABI
-/// level. For example, a 128-bit integer may be passed in two 64-bit registers,
-/// or even a 64-bit register and a 64-bit stack slot, on a 64-bit machine. The
-/// number of "parts" should correspond to the number of registers used to store
-/// this type according to the machine backend.
-///
-/// As an invariant, the `purpose` for every part must match. As a further
-/// invariant, a `StructArg` part cannot appear with any other part.
-#[derive(Clone, Debug)]
-pub enum ABIArg {
-    /// Storage slots (registers or stack locations) for each part of the
-    /// argument value. The number of slots must equal the number of register
-    /// parts used to store a value of this type.
-    Slots {
-        /// Slots, one per register part.
-        slots: Vec<ABIArgSlot>,
-        /// Purpose of this arg.
-        purpose: ir::ArgumentPurpose,
-    },
-    /// Structure argument. We reserve stack space for it, but the CLIF-level
-    /// semantics are a little weird: the value passed to the call instruction,
-    /// and received in the corresponding block param, is a *pointer*. On the
-    /// caller side, we memcpy the data from the passed-in pointer to the stack
-    /// area; on the callee side, we compute a pointer to this stack area and
-    /// provide that as the argument's value.
-    StructArg {
-        /// Offset of this arg relative to base of stack args.
-        offset: i64,
-        /// Size of this arg on the stack.
-        size: u64,
-        /// Purpose of this arg.
-        purpose: ir::ArgumentPurpose,
-    },
-}
-
-impl ABIArg {
-    /// Get the purpose of this arg.
-    fn get_purpose(&self) -> ir::ArgumentPurpose {
-        match self {
-            &ABIArg::Slots { purpose, .. } => purpose,
-            &ABIArg::StructArg { purpose, .. } => purpose,
-        }
-    }
-
-    /// Is this a StructArg?
-    fn is_struct_arg(&self) -> bool {
-        match self {
-            &ABIArg::StructArg { .. } => true,
-            _ => false,
-        }
-    }
-
-    /// Create an ABIArg from one register.
-    pub fn reg(
-        reg: RealReg,
-        ty: ir::Type,
-        extension: ir::ArgumentExtension,
-        purpose: ir::ArgumentPurpose,
-    ) -> ABIArg {
-        ABIArg::Slots {
-            slots: vec![ABIArgSlot::Reg { reg, ty, extension }],
-            purpose,
-        }
-    }
-
-    /// Create an ABIArg from one stack slot.
-    pub fn stack(
-        offset: i64,
-        ty: ir::Type,
-        extension: ir::ArgumentExtension,
-        purpose: ir::ArgumentPurpose,
-    ) -> ABIArg {
-        ABIArg::Slots {
-            slots: vec![ABIArgSlot::Stack {
-                offset,
-                ty,
-                extension,
-            }],
-            purpose,
-        }
-    }
-}
-
-/// Are we computing information about arguments or return values? Much of the
-/// handling is factored out into common routines; this enum allows us to
-/// distinguish which case we're handling.
-#[derive(Clone, Copy, Debug, PartialEq, Eq)]
-pub enum ArgsOrRets {
-    /// Arguments.
-    Args,
-    /// Return values.
-    Rets,
-}
-
-/// Is an instruction returned by an ABI machine-specific backend a safepoint,
-/// or not?
-#[derive(Clone, Copy, Debug, PartialEq, Eq)]
-pub enum InstIsSafepoint {
-    /// The instruction is a safepoint.
-    Yes,
-    /// The instruction is not a safepoint.
-    No,
-}
-
-/// Abstract location for a machine-specific ABI impl to translate into the
-/// appropriate addressing mode.
-#[derive(Clone, Copy, Debug)]
-pub enum StackAMode {
-    /// Offset from the frame pointer, possibly making use of a specific type
-    /// for a scaled indexing operation.
-    FPOffset(i64, ir::Type),
-    /// Offset from the nominal stack pointer, possibly making use of a specific
-    /// type for a scaled indexing operation.
-    NominalSPOffset(i64, ir::Type),
-    /// Offset from the real stack pointer, possibly making use of a specific
-    /// type for a scaled indexing operation.
-    SPOffset(i64, ir::Type),
-}
-
-impl StackAMode {
-    /// Offset by an addend.
-    pub fn offset(self, addend: i64) -> Self {
-        match self {
-            StackAMode::FPOffset(off, ty) => StackAMode::FPOffset(off + addend, ty),
-            StackAMode::NominalSPOffset(off, ty) => StackAMode::NominalSPOffset(off + addend, ty),
-            StackAMode::SPOffset(off, ty) => StackAMode::SPOffset(off + addend, ty),
-        }
-    }
-}
-
-/// Trait implemented by machine-specific backend to provide information about
-/// register assignments and to allow generating the specific instructions for
-/// stack loads/saves, prologues/epilogues, etc.
-pub trait ABIMachineSpec {
-    /// The instruction type.
-    type I: VCodeInst;
-
-    /// Returns the number of bits in a word, that is 32/64 for 32/64-bit architecture.
-    fn word_bits() -> u32;
-
-    /// Returns the number of bytes in a word.
-    fn word_bytes() -> u32 {
-        return Self::word_bits() / 8;
-    }
-
-    /// Returns word-size integer type.
-    fn word_type() -> Type {
-        match Self::word_bits() {
-            32 => I32,
-            64 => I64,
-            _ => unreachable!(),
-        }
-    }
-
-    /// Returns word register class.
-    fn word_reg_class() -> RegClass {
-        match Self::word_bits() {
-            32 => RegClass::I32,
-            64 => RegClass::I64,
-            _ => unreachable!(),
-        }
-    }
-
-    /// Returns required stack alignment in bytes.
-    fn stack_align(call_conv: isa::CallConv) -> u32;
-
-    /// Process a list of parameters or return values and allocate them to registers
-    /// and stack slots.
-    ///
-    /// Returns the list of argument locations, the stack-space used (rounded up
-    /// to as alignment requires), and if `add_ret_area_ptr` was passed, the
-    /// index of the extra synthetic arg that was added.
-    fn compute_arg_locs(
-        call_conv: isa::CallConv,
-        flags: &settings::Flags,
-        params: &[ir::AbiParam],
-        args_or_rets: ArgsOrRets,
-        add_ret_area_ptr: bool,
-    ) -> CodegenResult<(Vec<ABIArg>, i64, Option<usize>)>;
-
-    /// Returns the offset from FP to the argument area, i.e., jumping over the saved FP, return
-    /// address, and maybe other standard elements depending on ABI (e.g. Wasm TLS reg).
-    fn fp_to_arg_offset(call_conv: isa::CallConv, flags: &settings::Flags) -> i64;
-
-    /// Generate a load from the stack.
-    fn gen_load_stack(mem: StackAMode, into_reg: Writable<Reg>, ty: Type) -> Self::I;
-
-    /// Generate a store to the stack.
-    fn gen_store_stack(mem: StackAMode, from_reg: Reg, ty: Type) -> Self::I;
-
-    /// Generate a move.
-    fn gen_move(to_reg: Writable<Reg>, from_reg: Reg, ty: Type) -> Self::I;
-
-    /// Generate an integer-extend operation.
-    fn gen_extend(
-        to_reg: Writable<Reg>,
-        from_reg: Reg,
-        is_signed: bool,
-        from_bits: u8,
-        to_bits: u8,
-    ) -> Self::I;
-
-    /// Generate a return instruction.
-    fn gen_ret() -> Self::I;
-
-    /// Generate an "epilogue placeholder" instruction, recognized by lowering
-    /// when using the Baldrdash ABI.
-    fn gen_epilogue_placeholder() -> Self::I;
-
-    /// Generate an add-with-immediate. Note that even if this uses a scratch
-    /// register, it must satisfy two requirements:
-    ///
-    /// - The add-imm sequence must only clobber caller-save registers, because
-    ///   it will be placed in the prologue before the clobbered callee-save
-    ///   registers are saved.
-    ///
-    /// - The add-imm sequence must work correctly when `from_reg` and/or
-    ///   `into_reg` are the register returned by `get_stacklimit_reg()`.
-    fn gen_add_imm(into_reg: Writable<Reg>, from_reg: Reg, imm: u32) -> SmallInstVec<Self::I>;
-
-    /// Generate a sequence that traps with a `TrapCode::StackOverflow` code if
-    /// the stack pointer is less than the given limit register (assuming the
-    /// stack grows downward).
-    fn gen_stack_lower_bound_trap(limit_reg: Reg) -> SmallInstVec<Self::I>;
-
-    /// Generate an instruction to compute an address of a stack slot (FP- or
-    /// SP-based offset).
-    fn gen_get_stack_addr(mem: StackAMode, into_reg: Writable<Reg>, ty: Type) -> Self::I;
-
-    /// Get a fixed register to use to compute a stack limit. This is needed for
-    /// certain sequences generated after the register allocator has already
-    /// run. This must satisfy two requirements:
-    ///
-    /// - It must be a caller-save register, because it will be clobbered in the
-    ///   prologue before the clobbered callee-save registers are saved.
-    ///
-    /// - It must be safe to pass as an argument and/or destination to
-    ///   `gen_add_imm()`. This is relevant when an addition with a large
-    ///   immediate needs its own temporary; it cannot use the same fixed
-    ///   temporary as this one.
-    fn get_stacklimit_reg() -> Reg;
-
-    /// Generate a store to the given [base+offset] address.
-    fn gen_load_base_offset(into_reg: Writable<Reg>, base: Reg, offset: i32, ty: Type) -> Self::I;
-
-    /// Generate a load from the given [base+offset] address.
-    fn gen_store_base_offset(base: Reg, offset: i32, from_reg: Reg, ty: Type) -> Self::I;
-
-    /// Adjust the stack pointer up or down.
-    fn gen_sp_reg_adjust(amount: i32) -> SmallInstVec<Self::I>;
-
-    /// Generate a meta-instruction that adjusts the nominal SP offset.
-    fn gen_nominal_sp_adj(amount: i32) -> Self::I;
-
-    /// Generates extra unwind instructions for a new frame  for this
-    /// architecture, whether the frame has a prologue sequence or not.
-    fn gen_debug_frame_info(
-        _flags: &settings::Flags,
-        _isa_flags: &Vec<settings::Value>,
-    ) -> SmallInstVec<Self::I> {
-        // By default, generates nothing.
-        smallvec![]
-    }
-
-    /// Generate the usual frame-setup sequence for this architecture: e.g.,
-    /// `push rbp / mov rbp, rsp` on x86-64, or `stp fp, lr, [sp, #-16]!` on
-    /// AArch64.
-    fn gen_prologue_frame_setup(flags: &settings::Flags) -> SmallInstVec<Self::I>;
-
-    /// Generate the usual frame-restore sequence for this architecture.
-    fn gen_epilogue_frame_restore(flags: &settings::Flags) -> SmallInstVec<Self::I>;
-
-    /// Generate a probestack call.
-    fn gen_probestack(_frame_size: u32) -> SmallInstVec<Self::I>;
-
-    /// Get all clobbered registers that are callee-saved according to the ABI; the result
-    /// contains the registers in a sorted order.
-    fn get_clobbered_callee_saves(
-        call_conv: isa::CallConv,
-        regs: &Set<Writable<RealReg>>,
-    ) -> Vec<Writable<RealReg>>;
-
-    /// Determine whether it is necessary to generate the usual frame-setup
-    /// sequence (refer to gen_prologue_frame_setup()).
-    fn is_frame_setup_needed(
-        is_leaf: bool,
-        stack_args_size: u32,
-        num_clobbered_callee_saves: usize,
-        fixed_frame_storage_size: u32,
-    ) -> bool;
-
-    /// Generate a clobber-save sequence. The implementation here should return
-    /// a sequence of instructions that "push" or otherwise save to the stack all
-    /// registers written/modified by the function body that are callee-saved.
-    /// The sequence of instructions should adjust the stack pointer downward,
-    /// and should align as necessary according to ABI requirements.
-    ///
-    /// Returns stack bytes used as well as instructions. Does not adjust
-    /// nominal SP offset; caller will do that.
-    fn gen_clobber_save(
-        call_conv: isa::CallConv,
-        setup_frame: bool,
-        flags: &settings::Flags,
-        clobbered_callee_saves: &Vec<Writable<RealReg>>,
-        fixed_frame_storage_size: u32,
-        outgoing_args_size: u32,
-    ) -> (u64, SmallVec<[Self::I; 16]>);
-
-    /// Generate a clobber-restore sequence. This sequence should perform the
-    /// opposite of the clobber-save sequence generated above, assuming that SP
-    /// going into the sequence is at the same point that it was left when the
-    /// clobber-save sequence finished.
-    fn gen_clobber_restore(
-        call_conv: isa::CallConv,
-        flags: &settings::Flags,
-        clobbers: &Set<Writable<RealReg>>,
-        fixed_frame_storage_size: u32,
-        outgoing_args_size: u32,
-    ) -> SmallVec<[Self::I; 16]>;
-
-    /// Generate a call instruction/sequence. This method is provided one
-    /// temporary register to use to synthesize the called address, if needed.
-    fn gen_call(
-        dest: &CallDest,
-        uses: Vec<Reg>,
-        defs: Vec<Writable<Reg>>,
-        opcode: ir::Opcode,
-        tmp: Writable<Reg>,
-        callee_conv: isa::CallConv,
-        callee_conv: isa::CallConv,
-    ) -> SmallVec<[(InstIsSafepoint, Self::I); 2]>;
-
-    /// Generate a memcpy invocation. Used to set up struct args. May clobber
-    /// caller-save registers; we only memcpy before we start to set up args for
-    /// a call.
-    fn gen_memcpy(
-        call_conv: isa::CallConv,
-        dst: Reg,
-        src: Reg,
-        size: usize,
-    ) -> SmallVec<[Self::I; 8]>;
-
-    /// Get the number of spillslots required for the given register-class.
-    fn get_number_of_spillslots_for_value(rc: RegClass) -> u32;
-
-    /// Get the current virtual-SP offset from an instruction-emission state.
-    fn get_virtual_sp_offset_from_state(s: &<Self::I as MachInstEmit>::State) -> i64;
-
-    /// Get the "nominal SP to FP" offset from an instruction-emission state.
-    fn get_nominal_sp_to_fp(s: &<Self::I as MachInstEmit>::State) -> i64;
-
-    /// Get all caller-save registers, that is, registers that we expect
-    /// not to be saved across a call to a callee with the given ABI.
-    fn get_regs_clobbered_by_call(call_conv_of_callee: isa::CallConv) -> Vec<Writable<Reg>>;
-
-    /// Get the needed extension mode, given the mode attached to the argument
-    /// in the signature and the calling convention. The input (the attribute in
-    /// the signature) specifies what extension type should be done *if* the ABI
-    /// requires extension to the full register; this method's return value
-    /// indicates whether the extension actually *will* be done.
-    fn get_ext_mode(
-        call_conv: isa::CallConv,
-        specified: ir::ArgumentExtension,
-    ) -> ir::ArgumentExtension;
-}
-
-/// ABI information shared between body (callee) and caller.
-struct ABISig {
-    /// Argument locations (regs or stack slots). Stack offsets are relative to
-    /// SP on entry to function.
-    args: Vec<ABIArg>,
-    /// Return-value locations. Stack offsets are relative to the return-area
-    /// pointer.
-    rets: Vec<ABIArg>,
-    /// Space on stack used to store arguments.
-    stack_arg_space: i64,
-    /// Space on stack used to store return values.
-    stack_ret_space: i64,
-    /// Index in `args` of the stack-return-value-area argument.
-    stack_ret_arg: Option<usize>,
-    /// Calling convention used.
-    call_conv: isa::CallConv,
-}
-
-impl ABISig {
-    fn from_func_sig<M: ABIMachineSpec>(
-        sig: &ir::Signature,
-        flags: &settings::Flags,
-    ) -> CodegenResult<ABISig> {
-        // Compute args and retvals from signature. Handle retvals first,
-        // because we may need to add a return-area arg to the args.
-        let (rets, stack_ret_space, _) = M::compute_arg_locs(
-            sig.call_conv,
-            flags,
-            &sig.returns,
-            ArgsOrRets::Rets,
-            /* extra ret-area ptr = */ false,
-        )?;
-        let need_stack_return_area = stack_ret_space > 0;
-        let (args, stack_arg_space, stack_ret_arg) = M::compute_arg_locs(
-            sig.call_conv,
-            flags,
-            &sig.params,
-            ArgsOrRets::Args,
-            need_stack_return_area,
-        )?;
-
-        log::trace!(
-            "ABISig: sig {:?} => args = {:?} rets = {:?} arg stack = {} ret stack = {} stack_ret_arg = {:?}",
-            sig,
-            args,
-            rets,
-            stack_arg_space,
-            stack_ret_space,
-            stack_ret_arg
-        );
-
-        Ok(ABISig {
-            args,
-            rets,
-            stack_arg_space,
-            stack_ret_space,
-            stack_ret_arg,
-            call_conv: sig.call_conv,
-        })
-    }
-}
-
-/// ABI object for a function body.
-pub struct ABICalleeImpl<M: ABIMachineSpec> {
-    /// CLIF-level signature, possibly normalized.
-    ir_sig: ir::Signature,
-    /// Signature: arg and retval regs.
-    sig: ABISig,
-    /// Offsets to each stackslot.
-    stackslots: PrimaryMap<StackSlot, u32>,
-    /// Total stack size of all stackslots.
-    stackslots_size: u32,
-    /// Stack size to be reserved for outgoing arguments.
-    outgoing_args_size: u32,
-    /// Clobbered registers, from regalloc.
-    clobbered: Set<Writable<RealReg>>,
-    /// Total number of spillslots, from regalloc.
-    spillslots: Option<usize>,
-    /// Storage allocated for the fixed part of the stack frame.  This is
-    /// usually the same as the total frame size below, except in the case
-    /// of the baldrdash calling convention.
-    fixed_frame_storage_size: u32,
-    /// "Total frame size", as defined by "distance between FP and nominal SP".
-    /// Some items are pushed below nominal SP, so the function may actually use
-    /// more stack than this would otherwise imply. It is simply the initial
-    /// frame/allocation size needed for stackslots and spillslots.
-    total_frame_size: Option<u32>,
-    /// The register holding the return-area pointer, if needed.
-    ret_area_ptr: Option<Writable<Reg>>,
-    /// Calling convention this function expects.
-    call_conv: isa::CallConv,
-    /// The settings controlling this function's compilation.
-    flags: settings::Flags,
-    /// The ISA-specific flag values controlling this function's compilation.
-    isa_flags: Vec<settings::Value>,
-    /// Whether or not this function is a "leaf", meaning it calls no other
-    /// functions
-    is_leaf: bool,
-    /// If this function has a stack limit specified, then `Reg` is where the
-    /// stack limit will be located after the instructions specified have been
-    /// executed.
-    ///
-    /// Note that this is intended for insertion into the prologue, if
-    /// present. Also note that because the instructions here execute in the
-    /// prologue this happens after legalization/register allocation/etc so we
-    /// need to be extremely careful with each instruction. The instructions are
-    /// manually register-allocated and carefully only use caller-saved
-    /// registers and keep nothing live after this sequence of instructions.
-    stack_limit: Option<(Reg, SmallInstVec<M::I>)>,
-    /// Are we to invoke the probestack function in the prologue? If so,
-    /// what is the minimum size at which we must invoke it?
-    probestack_min_frame: Option<u32>,
-    /// Whether it is necessary to generate the usual frame-setup sequence.
-    setup_frame: bool,
-
-    _mach: PhantomData<M>,
-}
-
-fn get_special_purpose_param_register(
-    f: &ir::Function,
-    abi: &ABISig,
-    purpose: ir::ArgumentPurpose,
-) -> Option<Reg> {
-    let idx = f.signature.special_param_index(purpose)?;
-    match &abi.args[idx] {
-        &ABIArg::Slots { ref slots, .. } => match &slots[0] {
-            &ABIArgSlot::Reg { reg, .. } => Some(reg.to_reg()),
-            _ => None,
-        },
-        _ => None,
-    }
-}
-
-fn ty_from_class(class: RegClass) -> Type {
-    match class {
-        RegClass::I32 => I32,
-        RegClass::I64 => I64,
-        RegClass::F32 => F32,
-        RegClass::F64 => F64,
-        RegClass::V128 => I8X16,
-        _ => panic!("Unknown regclass: {:?}", class),
-    }
-}
-
-impl<M: ABIMachineSpec> ABICalleeImpl<M> {
-    /// Create a new body ABI instance.
-    pub fn new(
-        f: &ir::Function,
-        flags: settings::Flags,
-        isa_flags: Vec<settings::Value>,
-    ) -> CodegenResult<Self> {
-        log::trace!("ABI: func signature {:?}", f.signature);
-
-        let ir_sig = ensure_struct_return_ptr_is_returned(&f.signature);
-        let sig = ABISig::from_func_sig::<M>(&ir_sig, &flags)?;
-
-        let call_conv = f.signature.call_conv;
-        // Only these calling conventions are supported.
-        debug_assert!(
-            call_conv == isa::CallConv::SystemV
-                || call_conv == isa::CallConv::Fast
-                || call_conv == isa::CallConv::Cold
-                || call_conv.extends_baldrdash()
-                || call_conv.extends_windows_fastcall()
-                || call_conv == isa::CallConv::AppleAarch64
-                || call_conv == isa::CallConv::WasmtimeSystemV
-                || call_conv == isa::CallConv::WasmtimeAppleAarch64,
-            "Unsupported calling convention: {:?}",
-            call_conv
-        );
-
-        // Compute stackslot locations and total stackslot size.
-        let mut stack_offset: u32 = 0;
-        let mut stackslots = PrimaryMap::new();
-        for (stackslot, data) in f.stack_slots.iter() {
-            let off = stack_offset;
-            stack_offset += data.size;
-            let mask = M::word_bytes() - 1;
-            stack_offset = (stack_offset + mask) & !mask;
-            debug_assert_eq!(stackslot.as_u32() as usize, stackslots.len());
-            stackslots.push(off);
-        }
-
-        // Figure out what instructions, if any, will be needed to check the
-        // stack limit. This can either be specified as a special-purpose
-        // argument or as a global value which often calculates the stack limit
-        // from the arguments.
-        let stack_limit =
-            get_special_purpose_param_register(f, &sig, ir::ArgumentPurpose::StackLimit)
-                .map(|reg| (reg, smallvec![]))
-                .or_else(|| f.stack_limit.map(|gv| gen_stack_limit::<M>(f, &sig, gv)));
-
-        // Determine whether a probestack call is required for large enough
-        // frames (and the minimum frame size if so).
-        let probestack_min_frame = if flags.enable_probestack() {
-            assert!(
-                !flags.probestack_func_adjusts_sp(),
-                "SP-adjusting probestack not supported in new backends"
-            );
-            Some(1 << flags.probestack_size_log2())
-        } else {
-            None
-        };
-
-        Ok(Self {
-            ir_sig,
-            sig,
-            stackslots,
-            stackslots_size: stack_offset,
-            outgoing_args_size: 0,
-            clobbered: Set::empty(),
-            spillslots: None,
-            fixed_frame_storage_size: 0,
-            total_frame_size: None,
-            ret_area_ptr: None,
-            call_conv,
-            flags,
-            isa_flags,
-            is_leaf: f.is_leaf(),
-            stack_limit,
-            probestack_min_frame,
-            setup_frame: true,
-            _mach: PhantomData,
-        })
-    }
-
-    /// Inserts instructions necessary for checking the stack limit into the
-    /// prologue.
-    ///
-    /// This function will generate instructions necessary for perform a stack
-    /// check at the header of a function. The stack check is intended to trap
-    /// if the stack pointer goes below a particular threshold, preventing stack
-    /// overflow in wasm or other code. The `stack_limit` argument here is the
-    /// register which holds the threshold below which we're supposed to trap.
-    /// This function is known to allocate `stack_size` bytes and we'll push
-    /// instructions onto `insts`.
-    ///
-    /// Note that the instructions generated here are special because this is
-    /// happening so late in the pipeline (e.g. after register allocation). This
-    /// means that we need to do manual register allocation here and also be
-    /// careful to not clobber any callee-saved or argument registers. For now
-    /// this routine makes do with the `spilltmp_reg` as one temporary
-    /// register, and a second register of `tmp2` which is caller-saved. This
-    /// should be fine for us since no spills should happen in this sequence of
-    /// instructions, so our register won't get accidentally clobbered.
-    ///
-    /// No values can be live after the prologue, but in this case that's ok
-    /// because we just need to perform a stack check before progressing with
-    /// the rest of the function.
-    fn insert_stack_check(
-        &self,
-        stack_limit: Reg,
-        stack_size: u32,
-        insts: &mut SmallInstVec<M::I>,
-    ) {
-        // With no explicit stack allocated we can just emit the simple check of
-        // the stack registers against the stack limit register, and trap if
-        // it's out of bounds.
-        if stack_size == 0 {
-            insts.extend(M::gen_stack_lower_bound_trap(stack_limit));
-            return;
-        }
-
-        // Note that the 32k stack size here is pretty special. See the
-        // documentation in x86/abi.rs for why this is here. The general idea is
-        // that we're protecting against overflow in the addition that happens
-        // below.
-        if stack_size >= 32 * 1024 {
-            insts.extend(M::gen_stack_lower_bound_trap(stack_limit));
-        }
-
-        // Add the `stack_size` to `stack_limit`, placing the result in
-        // `scratch`.
-        //
-        // Note though that `stack_limit`'s register may be the same as
-        // `scratch`. If our stack size doesn't fit into an immediate this
-        // means we need a second scratch register for loading the stack size
-        // into a register.
-        let scratch = Writable::from_reg(M::get_stacklimit_reg());
-        insts.extend(M::gen_add_imm(scratch, stack_limit, stack_size).into_iter());
-        insts.extend(M::gen_stack_lower_bound_trap(scratch.to_reg()));
-    }
-}
-
-/// Generates the instructions necessary for the `gv` to be materialized into a
-/// register.
-///
-/// This function will return a register that will contain the result of
-/// evaluating `gv`. It will also return any instructions necessary to calculate
-/// the value of the register.
-///
-/// Note that global values are typically lowered to instructions via the
-/// standard legalization pass. Unfortunately though prologue generation happens
-/// so late in the pipeline that we can't use these legalization passes to
-/// generate the instructions for `gv`. As a result we duplicate some lowering
-/// of `gv` here and support only some global values. This is similar to what
-/// the x86 backend does for now, and hopefully this can be somewhat cleaned up
-/// in the future too!
-///
-/// Also note that this function will make use of `writable_spilltmp_reg()` as a
-/// temporary register to store values in if necessary. Currently after we write
-/// to this register there's guaranteed to be no spilled values between where
-/// it's used, because we're not participating in register allocation anyway!
-fn gen_stack_limit<M: ABIMachineSpec>(
-    f: &ir::Function,
-    abi: &ABISig,
-    gv: ir::GlobalValue,
-) -> (Reg, SmallInstVec<M::I>) {
-    let mut insts = smallvec![];
-    let reg = generate_gv::<M>(f, abi, gv, &mut insts);
-    return (reg, insts);
-}
-
-fn generate_gv<M: ABIMachineSpec>(
-    f: &ir::Function,
-    abi: &ABISig,
-    gv: ir::GlobalValue,
-    insts: &mut SmallInstVec<M::I>,
-) -> Reg {
-    match f.global_values[gv] {
-        // Return the direct register the vmcontext is in
-        ir::GlobalValueData::VMContext => {
-            get_special_purpose_param_register(f, abi, ir::ArgumentPurpose::VMContext)
-                .expect("no vmcontext parameter found")
-        }
-        // Load our base value into a register, then load from that register
-        // in to a temporary register.
-        ir::GlobalValueData::Load {
-            base,
-            offset,
-            global_type: _,
-            readonly: _,
-        } => {
-            let base = generate_gv::<M>(f, abi, base, insts);
-            let into_reg = Writable::from_reg(M::get_stacklimit_reg());
-            insts.push(M::gen_load_base_offset(
-                into_reg,
-                base,
-                offset.into(),
-                M::word_type(),
-            ));
-            return into_reg.to_reg();
-        }
-        ref other => panic!("global value for stack limit not supported: {}", other),
-    }
-}
-
-fn gen_load_stack_multi<M: ABIMachineSpec>(
-    from: StackAMode,
-    dst: ValueRegs<Writable<Reg>>,
-    ty: Type,
-) -> SmallInstVec<M::I> {
-    let mut ret = smallvec![];
-    let (_, tys) = M::I::rc_for_type(ty).unwrap();
-    let mut offset = 0;
-    // N.B.: registers are given in the `ValueRegs` in target endian order.
-    for (&dst, &ty) in dst.regs().iter().zip(tys.iter()) {
-        ret.push(M::gen_load_stack(from.offset(offset), dst, ty));
-        offset += ty.bytes() as i64;
-    }
-    ret
-}
-
-fn gen_store_stack_multi<M: ABIMachineSpec>(
-    from: StackAMode,
-    src: ValueRegs<Reg>,
-    ty: Type,
-) -> SmallInstVec<M::I> {
-    let mut ret = smallvec![];
-    let (_, tys) = M::I::rc_for_type(ty).unwrap();
-    let mut offset = 0;
-    // N.B.: registers are given in the `ValueRegs` in target endian order.
-    for (&src, &ty) in src.regs().iter().zip(tys.iter()) {
-        ret.push(M::gen_store_stack(from.offset(offset), src, ty));
-        offset += ty.bytes() as i64;
-    }
-    ret
-}
-
-fn ensure_struct_return_ptr_is_returned(sig: &ir::Signature) -> ir::Signature {
-    let params_structret = sig
-        .params
-        .iter()
-        .find(|p| p.purpose == ArgumentPurpose::StructReturn);
-    let rets_have_structret = sig.returns.len() > 0
-        && sig
-            .returns
-            .iter()
-            .any(|arg| arg.purpose == ArgumentPurpose::StructReturn);
-    let mut sig = sig.clone();
-    if params_structret.is_some() && !rets_have_structret {
-        sig.returns.insert(0, params_structret.unwrap().clone());
-    }
-    sig
-}
-
-impl<M: ABIMachineSpec> ABICallee for ABICalleeImpl<M> {
-    type I = M::I;
-
-    fn signature(&self) -> &ir::Signature {
-        &self.ir_sig
-    }
-
-    fn temp_needed(&self) -> Option<Type> {
-        if self.sig.stack_ret_arg.is_some() {
-            Some(M::word_type())
-        } else {
-            None
-        }
-    }
-
-    fn init(&mut self, maybe_tmp: Option<Writable<Reg>>) {
-        if self.sig.stack_ret_arg.is_some() {
-            assert!(maybe_tmp.is_some());
-            self.ret_area_ptr = maybe_tmp;
-        }
-    }
-
-    fn accumulate_outgoing_args_size(&mut self, size: u32) {
-        if size > self.outgoing_args_size {
-            self.outgoing_args_size = size;
-        }
-    }
-
-    fn flags(&self) -> &settings::Flags {
-        &self.flags
-    }
-
-    fn call_conv(&self) -> isa::CallConv {
-        self.sig.call_conv
-    }
-
-    fn liveins(&self) -> Set<RealReg> {
-        let mut set: Set<RealReg> = Set::empty();
-        for arg in &self.sig.args {
-            if let &ABIArg::Slots { ref slots, .. } = arg {
-                for slot in slots {
-                    if let ABIArgSlot::Reg { reg, .. } = slot {
-                        set.insert(*reg);
-                    }
-                }
-            }
-        }
-        set
-    }
-
-    fn liveouts(&self) -> Set<RealReg> {
-        let mut set: Set<RealReg> = Set::empty();
-        for ret in &self.sig.rets {
-            if let &ABIArg::Slots { ref slots, .. } = ret {
-                for slot in slots {
-                    if let ABIArgSlot::Reg { reg, .. } = slot {
-                        set.insert(*reg);
-                    }
-                }
-            }
-        }
-        set
-    }
-
-    fn num_args(&self) -> usize {
-        self.sig.args.len()
-    }
-
-    fn num_retvals(&self) -> usize {
-        self.sig.rets.len()
-    }
-
-    fn num_stackslots(&self) -> usize {
-        self.stackslots.len()
-    }
-
-    fn stackslot_offsets(&self) -> &PrimaryMap<StackSlot, u32> {
-        &self.stackslots
-    }
-
-    fn gen_copy_arg_to_regs(
-        &self,
-        idx: usize,
-        into_regs: ValueRegs<Writable<Reg>>,
-    ) -> SmallInstVec<Self::I> {
-        let mut insts = smallvec![];
-        match &self.sig.args[idx] {
-            &ABIArg::Slots { ref slots, .. } => {
-                assert_eq!(into_regs.len(), slots.len());
-                for (slot, into_reg) in slots.iter().zip(into_regs.regs().iter()) {
-                    match slot {
-                        // Extension mode doesn't matter (we're copying out, not in; we
-                        // ignore high bits by convention).
-                        &ABIArgSlot::Reg { reg, ty, .. } => {
-                            insts.push(M::gen_move(*into_reg, reg.to_reg(), ty));
-                        }
-                        &ABIArgSlot::Stack { offset, ty, .. } => {
-                            insts.push(M::gen_load_stack(
-                                StackAMode::FPOffset(
-                                    M::fp_to_arg_offset(self.call_conv, &self.flags) + offset,
-                                    ty,
-                                ),
-                                *into_reg,
-                                ty,
-                            ));
-                        }
-                    }
-                }
-            }
-            &ABIArg::StructArg { offset, .. } => {
-                let into_reg = into_regs.only_reg().unwrap();
-                insts.push(M::gen_get_stack_addr(
-                    StackAMode::FPOffset(
-                        M::fp_to_arg_offset(self.call_conv, &self.flags) + offset,
-                        I8,
-                    ),
-                    into_reg,
-                    I8,
-                ));
-            }
-        }
-        insts
-    }
-
-    fn arg_is_needed_in_body(&self, idx: usize) -> bool {
-        match self.sig.args[idx].get_purpose() {
-            // Special Baldrdash-specific pseudo-args that are present only to
-            // fill stack slots.  Won't ever be used as ordinary values in the
-            // body.
-            ir::ArgumentPurpose::CalleeTLS | ir::ArgumentPurpose::CallerTLS => false,
-            _ => true,
-        }
-    }
-
-    fn gen_copy_regs_to_retval(
-        &self,
-        idx: usize,
-        from_regs: ValueRegs<Writable<Reg>>,
-    ) -> SmallInstVec<Self::I> {
-        let mut ret = smallvec![];
-        let word_bits = M::word_bits() as u8;
-        match &self.sig.rets[idx] {
-            &ABIArg::Slots { ref slots, .. } => {
-                assert_eq!(from_regs.len(), slots.len());
-                for (slot, from_reg) in slots.iter().zip(from_regs.regs().iter()) {
-                    match slot {
-                        &ABIArgSlot::Reg {
-                            reg, ty, extension, ..
-                        } => {
-                            let from_bits = ty_bits(ty) as u8;
-                            let ext = M::get_ext_mode(self.sig.call_conv, extension);
-                            match (ext, from_bits) {
-                                (ArgumentExtension::Uext, n) | (ArgumentExtension::Sext, n)
-                                    if n < word_bits =>
-                                {
-                                    let signed = ext == ArgumentExtension::Sext;
-                                    ret.push(M::gen_extend(
-                                        Writable::from_reg(reg.to_reg()),
-                                        from_reg.to_reg(),
-                                        signed,
-                                        from_bits,
-                                        /* to_bits = */ word_bits,
-                                    ));
-                                }
-                                _ => {
-                                    ret.push(M::gen_move(
-                                        Writable::from_reg(reg.to_reg()),
-                                        from_reg.to_reg(),
-                                        ty,
-                                    ));
-                                }
-                            };
-                        }
-                        &ABIArgSlot::Stack {
-                            offset,
-                            ty,
-                            extension,
-                            ..
-                        } => {
-                            let mut ty = ty;
-                            let from_bits = ty_bits(ty) as u8;
-                            // A machine ABI implementation should ensure that stack frames
-                            // have "reasonable" size. All current ABIs for machinst
-                            // backends (aarch64 and x64) enforce a 128MB limit.
-                            let off = i32::try_from(offset).expect(
-                                "Argument stack offset greater than 2GB; should hit impl limit first",
-                                );
-                            let ext = M::get_ext_mode(self.sig.call_conv, extension);
-                            // Trash the from_reg; it should be its last use.
-                            match (ext, from_bits) {
-                                (ArgumentExtension::Uext, n) | (ArgumentExtension::Sext, n)
-                                    if n < word_bits =>
-                                {
-                                    assert_eq!(M::word_reg_class(), from_reg.to_reg().get_class());
-                                    let signed = ext == ArgumentExtension::Sext;
-                                    ret.push(M::gen_extend(
-                                        Writable::from_reg(from_reg.to_reg()),
-                                        from_reg.to_reg(),
-                                        signed,
-                                        from_bits,
-                                        /* to_bits = */ word_bits,
-                                    ));
-                                    // Store the extended version.
-                                    ty = M::word_type();
-                                }
-                                _ => {}
-                            };
-                            ret.push(M::gen_store_base_offset(
-                                self.ret_area_ptr.unwrap().to_reg(),
-                                off,
-                                from_reg.to_reg(),
-                                ty,
-                            ));
-                        }
-                    }
-                }
-            }
-            &ABIArg::StructArg { .. } => {
-                panic!("StructArg in return position is unsupported");
-            }
-        }
-        ret
-    }
-
-    fn gen_retval_area_setup(&self) -> Option<Self::I> {
-        if let Some(i) = self.sig.stack_ret_arg {
-            let insts = self.gen_copy_arg_to_regs(i, ValueRegs::one(self.ret_area_ptr.unwrap()));
-            let inst = insts.into_iter().next().unwrap();
-            log::trace!(
-                "gen_retval_area_setup: inst {:?}; ptr reg is {:?}",
-                inst,
-                self.ret_area_ptr.unwrap().to_reg()
-            );
-            Some(inst)
-        } else {
-            log::trace!("gen_retval_area_setup: not needed");
-            None
-        }
-    }
-
-    fn gen_ret(&self) -> Self::I {
-        M::gen_ret()
-    }
-
-    fn gen_epilogue_placeholder(&self) -> Self::I {
-        M::gen_epilogue_placeholder()
-    }
-
-    fn set_num_spillslots(&mut self, slots: usize) {
-        self.spillslots = Some(slots);
-    }
-
-    fn set_clobbered(&mut self, clobbered: Set<Writable<RealReg>>) {
-        self.clobbered = clobbered;
-    }
-
-    /// Produce an instruction that computes a stackslot address.
-    fn stackslot_addr(&self, slot: StackSlot, offset: u32, into_reg: Writable<Reg>) -> Self::I {
-        // Offset from beginning of stackslot area, which is at nominal SP (see
-        // [MemArg::NominalSPOffset] for more details on nominal SP tracking).
-        let stack_off = self.stackslots[slot] as i64;
-        let sp_off: i64 = stack_off + (offset as i64);
-        M::gen_get_stack_addr(StackAMode::NominalSPOffset(sp_off, I8), into_reg, I8)
-    }
-
-    /// Load from a spillslot.
-    fn load_spillslot(
-        &self,
-        slot: SpillSlot,
-        ty: Type,
-        into_regs: ValueRegs<Writable<Reg>>,
-    ) -> SmallInstVec<Self::I> {
-        // Offset from beginning of spillslot area, which is at nominal SP + stackslots_size.
-        let islot = slot.get() as i64;
-        let spill_off = islot * M::word_bytes() as i64;
-        let sp_off = self.stackslots_size as i64 + spill_off;
-        log::trace!("load_spillslot: slot {:?} -> sp_off {}", slot, sp_off);
-
-        gen_load_stack_multi::<M>(StackAMode::NominalSPOffset(sp_off, ty), into_regs, ty)
-    }
-
-    /// Store to a spillslot.
-    fn store_spillslot(
-        &self,
-        slot: SpillSlot,
-        ty: Type,
-        from_regs: ValueRegs<Reg>,
-    ) -> SmallInstVec<Self::I> {
-        // Offset from beginning of spillslot area, which is at nominal SP + stackslots_size.
-        let islot = slot.get() as i64;
-        let spill_off = islot * M::word_bytes() as i64;
-        let sp_off = self.stackslots_size as i64 + spill_off;
-        log::trace!("store_spillslot: slot {:?} -> sp_off {}", slot, sp_off);
-
-        gen_store_stack_multi::<M>(StackAMode::NominalSPOffset(sp_off, ty), from_regs, ty)
-    }
-
-    fn spillslots_to_stack_map(
-        &self,
-        slots: &[SpillSlot],
-        state: &<Self::I as MachInstEmit>::State,
-    ) -> StackMap {
-        let virtual_sp_offset = M::get_virtual_sp_offset_from_state(state);
-        let nominal_sp_to_fp = M::get_nominal_sp_to_fp(state);
-        assert!(virtual_sp_offset >= 0);
-        log::trace!(
-            "spillslots_to_stackmap: slots = {:?}, state = {:?}",
-            slots,
-            state
-        );
-        let map_size = (virtual_sp_offset + nominal_sp_to_fp) as u32;
-        let bytes = M::word_bytes();
-        let map_words = (map_size + bytes - 1) / bytes;
-        let mut bits = std::iter::repeat(false)
-            .take(map_words as usize)
-            .collect::<Vec<bool>>();
-
-        let first_spillslot_word =
-            ((self.stackslots_size + virtual_sp_offset as u32) / bytes) as usize;
-        for &slot in slots {
-            let slot = slot.get() as usize;
-            bits[first_spillslot_word + slot] = true;
-        }
-
-        StackMap::from_slice(&bits[..])
-    }
-
-    fn gen_prologue(&mut self) -> SmallInstVec<Self::I> {
-        let bytes = M::word_bytes();
-        let mut total_stacksize = self.stackslots_size + bytes * self.spillslots.unwrap() as u32;
-        if self.call_conv.extends_baldrdash() {
-            debug_assert!(
-                !self.flags.enable_probestack(),
-                "baldrdash does not expect cranelift to emit stack probes"
-            );
-            total_stacksize += self.flags.baldrdash_prologue_words() as u32 * bytes;
-        }
-        let mask = M::stack_align(self.call_conv) - 1;
-        let total_stacksize = (total_stacksize + mask) & !mask; // 16-align the stack.
-        let clobbered_callee_saves = M::get_clobbered_callee_saves(self.call_conv, &self.clobbered);
-        let mut insts = smallvec![];
-
-        if !self.call_conv.extends_baldrdash() {
-            self.fixed_frame_storage_size += total_stacksize;
-            self.setup_frame = M::is_frame_setup_needed(
-                self.is_leaf,
-                self.stack_args_size(),
-                clobbered_callee_saves.len(),
-                self.fixed_frame_storage_size,
-            );
-
-            insts.extend(M::gen_debug_frame_info(&self.flags, &self.isa_flags).into_iter());
-
-            if self.setup_frame {
-                // set up frame
-                insts.extend(M::gen_prologue_frame_setup(&self.flags).into_iter());
-            }
-
-            // Leaf functions with zero stack don't need a stack check if one's
-            // specified, otherwise always insert the stack check.
-            if total_stacksize > 0 || !self.is_leaf {
-                if let Some((reg, stack_limit_load)) = &self.stack_limit {
-                    insts.extend(stack_limit_load.clone());
-                    self.insert_stack_check(*reg, total_stacksize, &mut insts);
-                }
-                if let Some(min_frame) = &self.probestack_min_frame {
-                    if total_stacksize >= *min_frame {
-                        insts.extend(M::gen_probestack(total_stacksize));
-                    }
-                }
-            }
-        }
-
-        // Save clobbered registers.
-        let (clobber_size, clobber_insts) = M::gen_clobber_save(
-            self.call_conv,
-            self.setup_frame,
-            &self.flags,
-            &clobbered_callee_saves,
-            self.fixed_frame_storage_size,
-            self.outgoing_args_size,
-        );
-        insts.extend(clobber_insts);
-
-        // N.B.: "nominal SP", which we use to refer to stackslots and
-        // spillslots, is defined to be equal to the stack pointer at this point
-        // in the prologue.
-        //
-        // If we push any further data onto the stack in the function
-        // body, we emit a virtual-SP adjustment meta-instruction so
-        // that the nominal SP references behave as if SP were still
-        // at this point. See documentation for
-        // [crate::machinst::abi_impl](this module) for more details
-        // on stackframe layout and nominal SP maintenance.
-
-        self.total_frame_size = Some(total_stacksize + clobber_size as u32);
-        insts
-    }
-
-    fn gen_epilogue(&self) -> SmallInstVec<M::I> {
-        let mut insts = smallvec![];
-
-        // Restore clobbered registers.
-        insts.extend(M::gen_clobber_restore(
-            self.call_conv,
-            &self.flags,
-            &self.clobbered,
-            self.fixed_frame_storage_size,
-            self.outgoing_args_size,
-        ));
-
-        // N.B.: we do *not* emit a nominal SP adjustment here, because (i) there will be no
-        // references to nominal SP offsets before the return below, and (ii) the instruction
-        // emission tracks running SP offset linearly (in straight-line order), not according to
-        // the CFG, so early returns in the middle of function bodies would cause an incorrect
-        // offset for the rest of the body.
-
-        if !self.call_conv.extends_baldrdash() {
-            if self.setup_frame {
-                insts.extend(M::gen_epilogue_frame_restore(&self.flags));
-            }
-
-            insts.push(M::gen_ret());
-        }
-
-        log::trace!("Epilogue: {:?}", insts);
-        insts
-    }
-
-    fn frame_size(&self) -> u32 {
-        self.total_frame_size
-            .expect("frame size not computed before prologue generation")
-    }
-
-    fn stack_args_size(&self) -> u32 {
-        self.sig.stack_arg_space as u32
-    }
-
-    fn get_spillslot_size(&self, rc: RegClass) -> u32 {
-        M::get_number_of_spillslots_for_value(rc)
-    }
-
-    fn gen_spill(&self, to_slot: SpillSlot, from_reg: RealReg) -> Self::I {
-        let ty = ty_from_class(from_reg.to_reg().get_class());
-        self.store_spillslot(to_slot, ty, ValueRegs::one(from_reg.to_reg()))
-            .into_iter()
-            .next()
-            .unwrap()
-    }
-
-    fn gen_reload(&self, to_reg: Writable<RealReg>, from_slot: SpillSlot) -> Self::I {
-        let ty = ty_from_class(to_reg.to_reg().get_class());
-        self.load_spillslot(
-            from_slot,
-            ty,
-            writable_value_regs(ValueRegs::one(to_reg.to_reg().to_reg())),
-        )
-        .into_iter()
-        .next()
-        .unwrap()
-    }
-}
-
-fn abisig_to_uses_and_defs<M: ABIMachineSpec>(sig: &ABISig) -> (Vec<Reg>, Vec<Writable<Reg>>) {
-    // Compute uses: all arg regs.
-    let mut uses = Vec::new();
-    for arg in &sig.args {
-        if let &ABIArg::Slots { ref slots, .. } = arg {
-            for slot in slots {
-                match slot {
-                    &ABIArgSlot::Reg { reg, .. } => {
-                        uses.push(reg.to_reg());
-                    }
-                    _ => {}
-                }
-            }
-        }
-    }
-
-    // Compute defs: all retval regs, and all caller-save (clobbered) regs.
-    let mut defs = M::get_regs_clobbered_by_call(sig.call_conv);
-    for ret in &sig.rets {
-        if let &ABIArg::Slots { ref slots, .. } = ret {
-            for slot in slots {
-                match slot {
-                    &ABIArgSlot::Reg { reg, .. } => {
-                        defs.push(Writable::from_reg(reg.to_reg()));
-                    }
-                    _ => {}
-                }
-            }
-        }
-    }
-
-    (uses, defs)
-}
-
-/// ABI object for a callsite.
-pub struct ABICallerImpl<M: ABIMachineSpec> {
-    /// CLIF-level signature, possibly normalized.
-    ir_sig: ir::Signature,
-    /// The called function's signature.
-    sig: ABISig,
-    /// All uses for the callsite, i.e., function args.
-    uses: Vec<Reg>,
-    /// All defs for the callsite, i.e., return values and caller-saves.
-    defs: Vec<Writable<Reg>>,
-    /// Call destination.
-    dest: CallDest,
-    /// Actual call opcode; used to distinguish various types of calls.
-    opcode: ir::Opcode,
-    /// Caller's calling convention.
-    caller_conv: isa::CallConv,
-    /// The settings controlling this compilation.
-    flags: settings::Flags,
-
-    _mach: PhantomData<M>,
-}
-
-/// Destination for a call.
-#[derive(Debug, Clone)]
-pub enum CallDest {
-    /// Call to an ExtName (named function symbol).
-    ExtName(ir::ExternalName, RelocDistance),
-    /// Indirect call to a function pointer in a register.
-    Reg(Reg),
-}
-
-impl<M: ABIMachineSpec> ABICallerImpl<M> {
-    /// Create a callsite ABI object for a call directly to the specified function.
-    pub fn from_func(
-        sig: &ir::Signature,
-        extname: &ir::ExternalName,
-        dist: RelocDistance,
-        caller_conv: isa::CallConv,
-        flags: &settings::Flags,
-    ) -> CodegenResult<ABICallerImpl<M>> {
-        let ir_sig = ensure_struct_return_ptr_is_returned(sig);
-        let sig = ABISig::from_func_sig::<M>(&ir_sig, flags)?;
-        let (uses, defs) = abisig_to_uses_and_defs::<M>(&sig);
-        Ok(ABICallerImpl {
-            ir_sig,
-            sig,
-            uses,
-            defs,
-            dest: CallDest::ExtName(extname.clone(), dist),
-            opcode: ir::Opcode::Call,
-            caller_conv,
-            flags: flags.clone(),
-            _mach: PhantomData,
-        })
-    }
-
-    /// Create a callsite ABI object for a call to a function pointer with the
-    /// given signature.
-    pub fn from_ptr(
-        sig: &ir::Signature,
-        ptr: Reg,
-        opcode: ir::Opcode,
-        caller_conv: isa::CallConv,
-        flags: &settings::Flags,
-    ) -> CodegenResult<ABICallerImpl<M>> {
-        let ir_sig = ensure_struct_return_ptr_is_returned(sig);
-        let sig = ABISig::from_func_sig::<M>(&ir_sig, flags)?;
-        let (uses, defs) = abisig_to_uses_and_defs::<M>(&sig);
-        Ok(ABICallerImpl {
-            ir_sig,
-            sig,
-            uses,
-            defs,
-            dest: CallDest::Reg(ptr),
-            opcode,
-            caller_conv,
-            flags: flags.clone(),
-            _mach: PhantomData,
-        })
-    }
-}
-
-fn adjust_stack_and_nominal_sp<M: ABIMachineSpec, C: LowerCtx<I = M::I>>(
-    ctx: &mut C,
-    off: i32,
-    is_sub: bool,
-) {
-    if off == 0 {
-        return;
-    }
-    let amt = if is_sub { -off } else { off };
-    for inst in M::gen_sp_reg_adjust(amt) {
-        ctx.emit(inst);
-    }
-    ctx.emit(M::gen_nominal_sp_adj(-amt));
-}
-
-impl<M: ABIMachineSpec> ABICaller for ABICallerImpl<M> {
-    type I = M::I;
-
-    fn signature(&self) -> &ir::Signature {
-        &self.ir_sig
-    }
-
-    fn num_args(&self) -> usize {
-        if self.sig.stack_ret_arg.is_some() {
-            self.sig.args.len() - 1
-        } else {
-            self.sig.args.len()
-        }
-    }
-
-    fn accumulate_outgoing_args_size<C: LowerCtx<I = Self::I>>(&self, ctx: &mut C) {
-        let off = self.sig.stack_arg_space + self.sig.stack_ret_space;
-        ctx.abi().accumulate_outgoing_args_size(off as u32);
-    }
-
-    fn emit_stack_pre_adjust<C: LowerCtx<I = Self::I>>(&self, ctx: &mut C) {
-        let off = self.sig.stack_arg_space + self.sig.stack_ret_space;
-        adjust_stack_and_nominal_sp::<M, C>(ctx, off as i32, /* is_sub = */ true)
-    }
-
-    fn emit_stack_post_adjust<C: LowerCtx<I = Self::I>>(&self, ctx: &mut C) {
-        let off = self.sig.stack_arg_space + self.sig.stack_ret_space;
-        adjust_stack_and_nominal_sp::<M, C>(ctx, off as i32, /* is_sub = */ false)
-    }
-
-    fn emit_copy_regs_to_arg<C: LowerCtx<I = Self::I>>(
-        &self,
-        ctx: &mut C,
-        idx: usize,
-        from_regs: ValueRegs<Reg>,
-    ) {
-        let word_rc = M::word_reg_class();
-        let word_bits = M::word_bits() as usize;
-        match &self.sig.args[idx] {
-            &ABIArg::Slots { ref slots, .. } => {
-                assert_eq!(from_regs.len(), slots.len());
-                for (slot, from_reg) in slots.iter().zip(from_regs.regs().iter()) {
-                    match slot {
-                        &ABIArgSlot::Reg {
-                            reg, ty, extension, ..
-                        } => {
-                            let ext = M::get_ext_mode(self.sig.call_conv, extension);
-                            if ext != ir::ArgumentExtension::None && ty_bits(ty) < word_bits {
-                                assert_eq!(word_rc, reg.get_class());
-                                let signed = match ext {
-                                    ir::ArgumentExtension::Uext => false,
-                                    ir::ArgumentExtension::Sext => true,
-                                    _ => unreachable!(),
-                                };
-                                ctx.emit(M::gen_extend(
-                                    Writable::from_reg(reg.to_reg()),
-                                    *from_reg,
-                                    signed,
-                                    ty_bits(ty) as u8,
-                                    word_bits as u8,
-                                ));
-                            } else {
-                                ctx.emit(M::gen_move(
-                                    Writable::from_reg(reg.to_reg()),
-                                    *from_reg,
-                                    ty,
-                                ));
-                            }
-                        }
-                        &ABIArgSlot::Stack {
-                            offset,
-                            ty,
-                            extension,
-                            ..
-                        } => {
-                            let mut ty = ty;
-                            let ext = M::get_ext_mode(self.sig.call_conv, extension);
-                            if ext != ir::ArgumentExtension::None && ty_bits(ty) < word_bits {
-                                assert_eq!(word_rc, from_reg.get_class());
-                                let signed = match ext {
-                                    ir::ArgumentExtension::Uext => false,
-                                    ir::ArgumentExtension::Sext => true,
-                                    _ => unreachable!(),
-                                };
-                                // Extend in place in the source register. Our convention is to
-                                // treat high bits as undefined for values in registers, so this
-                                // is safe, even for an argument that is nominally read-only.
-                                ctx.emit(M::gen_extend(
-                                    Writable::from_reg(*from_reg),
-                                    *from_reg,
-                                    signed,
-                                    ty_bits(ty) as u8,
-                                    word_bits as u8,
-                                ));
-                                // Store the extended version.
-                                ty = M::word_type();
-                            }
-                            ctx.emit(M::gen_store_stack(
-                                StackAMode::SPOffset(offset, ty),
-                                *from_reg,
-                                ty,
-                            ));
-                        }
-                    }
-                }
-            }
-            &ABIArg::StructArg { offset, size, .. } => {
-                let src_ptr = from_regs.only_reg().unwrap();
-                let dst_ptr = ctx.alloc_tmp(M::word_type()).only_reg().unwrap();
-                ctx.emit(M::gen_get_stack_addr(
-                    StackAMode::SPOffset(offset, I8),
-                    dst_ptr,
-                    I8,
-                ));
-                // Emit a memcpy from `src_ptr` to `dst_ptr` of `size` bytes.
-                // N.B.: because we process StructArg params *first*, this is
-                // safe w.r.t. clobbers: we have not yet filled in any other
-                // arg regs.
-                let memcpy_call_conv = isa::CallConv::for_libcall(&self.flags, self.sig.call_conv);
-                for insn in
-                    M::gen_memcpy(memcpy_call_conv, dst_ptr.to_reg(), src_ptr, size as usize)
-                        .into_iter()
-                {
-                    ctx.emit(insn);
-                }
-            }
-        }
-    }
-
-    fn get_copy_to_arg_order(&self) -> SmallVec<[usize; 8]> {
-        let mut ret = SmallVec::new();
-        for (i, arg) in self.sig.args.iter().enumerate() {
-            // Struct args.
-            if arg.is_struct_arg() {
-                ret.push(i);
-            }
-        }
-        for (i, arg) in self.sig.args.iter().enumerate() {
-            // Non-struct args. Skip an appended return-area arg for multivalue
-            // returns, if any.
-            if !arg.is_struct_arg() && i < self.ir_sig.params.len() {
-                ret.push(i);
-            }
-        }
-        ret
-    }
-
-    fn emit_copy_retval_to_regs<C: LowerCtx<I = Self::I>>(
-        &self,
-        ctx: &mut C,
-        idx: usize,
-        into_regs: ValueRegs<Writable<Reg>>,
-    ) {
-        match &self.sig.rets[idx] {
-            &ABIArg::Slots { ref slots, .. } => {
-                assert_eq!(into_regs.len(), slots.len());
-                for (slot, into_reg) in slots.iter().zip(into_regs.regs().iter()) {
-                    match slot {
-                        // Extension mode doesn't matter because we're copying out, not in,
-                        // and we ignore high bits in our own registers by convention.
-                        &ABIArgSlot::Reg { reg, ty, .. } => {
-                            ctx.emit(M::gen_move(*into_reg, reg.to_reg(), ty));
-                        }
-                        &ABIArgSlot::Stack { offset, ty, .. } => {
-                            let ret_area_base = self.sig.stack_arg_space;
-                            ctx.emit(M::gen_load_stack(
-                                StackAMode::SPOffset(offset + ret_area_base, ty),
-                                *into_reg,
-                                ty,
-                            ));
-                        }
-                    }
-                }
-            }
-            &ABIArg::StructArg { .. } => {
-                panic!("StructArg not supported in return position");
-            }
-        }
-    }
-
-    fn emit_call<C: LowerCtx<I = Self::I>>(&mut self, ctx: &mut C) {
-        let (uses, defs) = (
-            mem::replace(&mut self.uses, Default::default()),
-            mem::replace(&mut self.defs, Default::default()),
-        );
-        let word_type = M::word_type();
-        if let Some(i) = self.sig.stack_ret_arg {
-            let rd = ctx.alloc_tmp(word_type).only_reg().unwrap();
-            let ret_area_base = self.sig.stack_arg_space;
-            ctx.emit(M::gen_get_stack_addr(
-                StackAMode::SPOffset(ret_area_base, I8),
-                rd,
-                I8,
-            ));
-            self.emit_copy_regs_to_arg(ctx, i, ValueRegs::one(rd.to_reg()));
-        }
-        let tmp = ctx.alloc_tmp(word_type).only_reg().unwrap();
-        for (is_safepoint, inst) in M::gen_call(
-            &self.dest,
-            uses,
-            defs,
-            self.opcode,
-            tmp,
-            self.sig.call_conv,
-            self.caller_conv,
-        )
-        .into_iter()
-        {
-            match is_safepoint {
-                InstIsSafepoint::Yes => ctx.emit_safepoint(inst),
-                InstIsSafepoint::No => ctx.emit(inst),
-            }
-        }
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/blockorder.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/blockorder.rs
deleted file mode 100644
index 5c805c402..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/blockorder.rs
+++ /dev/null
@@ -1,634 +0,0 @@
-//! Computation of basic block order in emitted code.
-//!
-//! This module handles the translation from CLIF BBs to VCode BBs.
-//!
-//! The basic idea is that we compute a sequence of "lowered blocks" that
-//! correspond to one or more blocks in the graph: (CLIF CFG) `union` (implicit
-//! block on *every* edge). Conceptually, the lowering pipeline wants to insert
-//! moves for phi-nodes on every block-to-block transfer; these blocks always
-//! conceptually exist, but may be merged with an "original" CLIF block (and
-//! hence not actually exist; this is equivalent to inserting the blocks only on
-//! critical edges).
-//!
-//! In other words, starting from a CFG like this (where each "CLIF block" and
-//! "(edge N->M)" is a separate basic block):
-//!
-//! ```plain
-//!
-//!              CLIF block 0
-//!               /           \
-//!       (edge 0->1)         (edge 0->2)
-//!              |                |
-//!       CLIF block 1         CLIF block 2
-//!              \                /
-//!           (edge 1->3)   (edge 2->3)
-//!                   \      /
-//!                 CLIF block 3
-//! ```
-//!
-//! We can produce a CFG of lowered blocks like so:
-//!
-//! ```plain
-//!            +--------------+
-//!            | CLIF block 0 |
-//!            +--------------+
-//!               /           \
-//!     +--------------+     +--------------+
-//!     | (edge 0->1)  |     |(edge 0->2)   |
-//!     | CLIF block 1 |     | CLIF block 2 |
-//!     +--------------+     +--------------+
-//!              \                /
-//!          +-----------+ +-----------+
-//!          |(edge 1->3)| |(edge 2->3)|
-//!          +-----------+ +-----------+
-//!                   \      /
-//!                +------------+
-//!                |CLIF block 3|
-//!                +------------+
-//! ```
-//!
-//! (note that the edges into CLIF blocks 1 and 2 could be merged with those
-//! blocks' original bodies, but the out-edges could not because for simplicity
-//! in the successor-function definition, we only ever merge an edge onto one
-//! side of an original CLIF block.)
-//!
-//! Each `LoweredBlock` names just an original CLIF block, an original CLIF
-//! block prepended or appended with an edge block (never both, though), or just
-//! an edge block.
-//!
-//! To compute this lowering, we do a DFS over the CLIF-plus-edge-block graph
-//! (never actually materialized, just defined by a "successors" function), and
-//! compute the reverse postorder.
-//!
-//! This algorithm isn't perfect w.r.t. generated code quality: we don't, for
-//! example, consider any information about whether edge blocks will actually
-//! have content, because this computation happens as part of lowering *before*
-//! regalloc, and regalloc may or may not insert moves/spills/reloads on any
-//! particular edge. But it works relatively well and is conceptually simple.
-//! Furthermore, the [MachBuffer] machine-code sink performs final peephole-like
-//! branch editing that in practice elides empty blocks and simplifies some of
-//! the other redundancies that this scheme produces.
-
-use crate::entity::SecondaryMap;
-use crate::fx::{FxHashMap, FxHashSet};
-use crate::ir::{Block, Function, Inst, Opcode};
-use crate::machinst::lower::visit_block_succs;
-use crate::machinst::*;
-
-use smallvec::SmallVec;
-
-/// Mapping from CLIF BBs to VCode BBs.
-#[derive(Debug)]
-pub struct BlockLoweringOrder {
-    /// Lowered blocks, in BlockIndex order. Each block is some combination of
-    /// (i) a CLIF block, and (ii) inserted crit-edge blocks before or after;
-    /// see [LoweredBlock] for details.
-    lowered_order: Vec<LoweredBlock>,
-    /// Successors for all lowered blocks, in one serialized vector. Indexed by
-    /// the ranges in `lowered_succ_ranges`.
-    #[allow(dead_code)]
-    lowered_succs: Vec<(Inst, LoweredBlock)>,
-    /// BlockIndex values for successors for all lowered blocks, in the same
-    /// order as `lowered_succs`.
-    lowered_succ_indices: Vec<(Inst, BlockIndex)>,
-    /// Ranges in `lowered_succs` giving the successor lists for each lowered
-    /// block. Indexed by lowering-order index (`BlockIndex`).
-    lowered_succ_ranges: Vec<(usize, usize)>,
-    /// Mapping from CLIF BB to BlockIndex (index in lowered order). Note that
-    /// some CLIF BBs may not be lowered; in particular, we skip unreachable
-    /// blocks.
-    #[allow(dead_code)]
-    orig_map: SecondaryMap<Block, Option<BlockIndex>>,
-    /// Cold blocks. These blocks are not reordered in the
-    /// `lowered_order` above; the lowered order must respect RPO
-    /// (uses after defs) in order for lowering to be
-    /// correct. Instead, this set is used to provide `is_cold()`,
-    /// which is used by VCode emission to sink the blocks at the last
-    /// moment (when we actually emit bytes into the MachBuffer).
-    cold_blocks: FxHashSet<BlockIndex>,
-}
-
-/// The origin of a block in the lowered block-order: either an original CLIF
-/// block, or an inserted edge-block, or a combination of the two if an edge is
-/// non-critical.
-#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
-pub enum LoweredBlock {
-    /// Block in original CLIF, with no merged edge-blocks.
-    Orig {
-        /// Original CLIF block.
-        block: Block,
-    },
-    /// Block in the original CLIF, plus edge-block to one succ (which is the
-    /// one successor of the original block).
-    OrigAndEdge {
-        /// The original CLIF block contained in this lowered block.
-        block: Block,
-        /// The edge (jump) instruction transitioning from this block
-        /// to the next, i.e., corresponding to the included edge-block. This
-        /// will be an instruction in `block`.
-        edge_inst: Inst,
-        /// The successor CLIF block.
-        succ: Block,
-    },
-    /// Block in the original CLIF, preceded by edge-block from one pred (which
-    /// is the one pred of the original block).
-    EdgeAndOrig {
-        /// The previous CLIF block, i.e., the edge block's predecessor.
-        pred: Block,
-        /// The edge (jump) instruction corresponding to the included
-        /// edge-block. This will be an instruction in `pred`.
-        edge_inst: Inst,
-        /// The original CLIF block included in this lowered block.
-        block: Block,
-    },
-    /// Split critical edge between two CLIF blocks. This lowered block does not
-    /// correspond to any original CLIF blocks; it only serves as an insertion
-    /// point for work to happen on the transition from `pred` to `succ`.
-    Edge {
-        /// The predecessor CLIF block.
-        pred: Block,
-        /// The edge (jump) instruction corresponding to this edge's transition.
-        /// This will be an instruction in `pred`.
-        edge_inst: Inst,
-        /// The successor CLIF block.
-        succ: Block,
-    },
-}
-
-impl LoweredBlock {
-    /// The associated original (CLIF) block included in this lowered block, if
-    /// any.
-    pub fn orig_block(self) -> Option<Block> {
-        match self {
-            LoweredBlock::Orig { block, .. }
-            | LoweredBlock::OrigAndEdge { block, .. }
-            | LoweredBlock::EdgeAndOrig { block, .. } => Some(block),
-            LoweredBlock::Edge { .. } => None,
-        }
-    }
-
-    /// The associated in-edge, if any.
-    pub fn in_edge(self) -> Option<(Block, Inst, Block)> {
-        match self {
-            LoweredBlock::EdgeAndOrig {
-                pred,
-                edge_inst,
-                block,
-            } => Some((pred, edge_inst, block)),
-            _ => None,
-        }
-    }
-
-    /// the associated out-edge, if any. Also includes edge-only blocks.
-    pub fn out_edge(self) -> Option<(Block, Inst, Block)> {
-        match self {
-            LoweredBlock::OrigAndEdge {
-                block,
-                edge_inst,
-                succ,
-            } => Some((block, edge_inst, succ)),
-            LoweredBlock::Edge {
-                pred,
-                edge_inst,
-                succ,
-            } => Some((pred, edge_inst, succ)),
-            _ => None,
-        }
-    }
-}
-
-impl BlockLoweringOrder {
-    /// Compute and return a lowered block order for `f`.
-    pub fn new(f: &Function) -> BlockLoweringOrder {
-        log::trace!("BlockLoweringOrder: function body {:?}", f);
-
-        // Step 1: compute the in-edge and out-edge count of every block.
-        let mut block_in_count = SecondaryMap::with_default(0);
-        let mut block_out_count = SecondaryMap::with_default(0);
-
-        // Cache the block successors to avoid re-examining branches below.
-        let mut block_succs: SmallVec<[(Inst, Block); 128]> = SmallVec::new();
-        let mut block_succ_range = SecondaryMap::with_default((0, 0));
-        let mut fallthrough_return_block = None;
-        for block in f.layout.blocks() {
-            let block_succ_start = block_succs.len();
-            visit_block_succs(f, block, |inst, succ| {
-                block_out_count[block] += 1;
-                block_in_count[succ] += 1;
-                block_succs.push((inst, succ));
-            });
-            let block_succ_end = block_succs.len();
-            block_succ_range[block] = (block_succ_start, block_succ_end);
-
-            for inst in f.layout.block_likely_branches(block) {
-                if f.dfg[inst].opcode() == Opcode::Return {
-                    // Implicit output edge for any return.
-                    block_out_count[block] += 1;
-                }
-                if f.dfg[inst].opcode() == Opcode::FallthroughReturn {
-                    // Fallthrough return block must come last.
-                    debug_assert!(fallthrough_return_block == None);
-                    fallthrough_return_block = Some(block);
-                }
-            }
-        }
-        // Implicit input edge for entry block.
-        if let Some(entry) = f.layout.entry_block() {
-            block_in_count[entry] += 1;
-        }
-
-        // Here we define the implicit CLIF-plus-edges graph. There are
-        // conceptually two such graphs: the original, with every edge explicit,
-        // and the merged one, with blocks (represented by `LoweredBlock`
-        // values) that contain original CLIF blocks, edges, or both. This
-        // function returns a lowered block's successors as per the latter, with
-        // consideration to edge-block merging.
-        //
-        // Note that there is a property of the block-merging rules below
-        // that is very important to ensure we don't miss any lowered blocks:
-        // any block in the implicit CLIF-plus-edges graph will *only* be
-        // included in one block in the merged graph.
-        //
-        // This, combined with the property that every edge block is reachable
-        // only from one predecessor (and hence cannot be reached by a DFS
-        // backedge), means that it is sufficient in our DFS below to track
-        // visited-bits per original CLIF block only, not per edge. This greatly
-        // simplifies the data structures (no need to keep a sparse hash-set of
-        // (block, block) tuples).
-        let compute_lowered_succs = |ret: &mut Vec<(Inst, LoweredBlock)>, block: LoweredBlock| {
-            let start_idx = ret.len();
-            match block {
-                LoweredBlock::Orig { block } | LoweredBlock::EdgeAndOrig { block, .. } => {
-                    // At an orig block; successors are always edge blocks,
-                    // possibly with orig blocks following.
-                    let range = block_succ_range[block];
-                    for &(edge_inst, succ) in &block_succs[range.0..range.1] {
-                        if block_in_count[succ] == 1 {
-                            ret.push((
-                                edge_inst,
-                                LoweredBlock::EdgeAndOrig {
-                                    pred: block,
-                                    edge_inst,
-                                    block: succ,
-                                },
-                            ));
-                        } else {
-                            ret.push((
-                                edge_inst,
-                                LoweredBlock::Edge {
-                                    pred: block,
-                                    edge_inst,
-                                    succ,
-                                },
-                            ));
-                        }
-                    }
-                }
-                LoweredBlock::Edge {
-                    succ, edge_inst, ..
-                }
-                | LoweredBlock::OrigAndEdge {
-                    succ, edge_inst, ..
-                } => {
-                    // At an edge block; successors are always orig blocks,
-                    // possibly with edge blocks following.
-                    if block_out_count[succ] == 1 {
-                        let range = block_succ_range[succ];
-                        // check if the one succ is a real CFG edge (vs.
-                        // implicit return succ).
-                        if range.1 - range.0 > 0 {
-                            debug_assert!(range.1 - range.0 == 1);
-                            let (succ_edge_inst, succ_succ) = block_succs[range.0];
-                            ret.push((
-                                edge_inst,
-                                LoweredBlock::OrigAndEdge {
-                                    block: succ,
-                                    edge_inst: succ_edge_inst,
-                                    succ: succ_succ,
-                                },
-                            ));
-                        } else {
-                            ret.push((edge_inst, LoweredBlock::Orig { block: succ }));
-                        }
-                    } else {
-                        ret.push((edge_inst, LoweredBlock::Orig { block: succ }));
-                    }
-                }
-            }
-            let end_idx = ret.len();
-            (start_idx, end_idx)
-        };
-
-        // Build the explicit LoweredBlock-to-LoweredBlock successors list.
-        let mut lowered_succs = vec![];
-        let mut lowered_succ_indices = vec![];
-
-        // Step 2: Compute RPO traversal of the implicit CLIF-plus-edge-block graph. Use an
-        // explicit stack so we don't overflow the real stack with a deep DFS.
-        #[derive(Debug)]
-        struct StackEntry {
-            this: LoweredBlock,
-            succs: (usize, usize), // range in lowered_succs
-            cur_succ: usize,       // index in lowered_succs
-        }
-
-        let mut stack: SmallVec<[StackEntry; 16]> = SmallVec::new();
-        let mut visited = FxHashSet::default();
-        let mut postorder = vec![];
-        if let Some(entry) = f.layout.entry_block() {
-            // FIXME(cfallin): we might be able to use OrigAndEdge. Find a way
-            // to not special-case the entry block here.
-            let block = LoweredBlock::Orig { block: entry };
-            visited.insert(block);
-            let range = compute_lowered_succs(&mut lowered_succs, block);
-            lowered_succ_indices.resize(lowered_succs.len(), 0);
-            stack.push(StackEntry {
-                this: block,
-                succs: range,
-                cur_succ: range.1,
-            });
-        }
-
-        let mut deferred_last = None;
-        while !stack.is_empty() {
-            let stack_entry = stack.last_mut().unwrap();
-            let range = stack_entry.succs;
-            if stack_entry.cur_succ == range.0 {
-                let orig_block = stack_entry.this.orig_block();
-                if orig_block.is_some() && orig_block == fallthrough_return_block {
-                    deferred_last = Some((stack_entry.this, range));
-                } else {
-                    postorder.push((stack_entry.this, range));
-                }
-                stack.pop();
-            } else {
-                // Heuristic: chase the children in reverse. This puts the first
-                // successor block first in RPO, all other things being equal,
-                // which tends to prioritize loop backedges over out-edges,
-                // putting the edge-block closer to the loop body and minimizing
-                // live-ranges in linear instruction space.
-                let next = lowered_succs[stack_entry.cur_succ - 1].1;
-                stack_entry.cur_succ -= 1;
-                if visited.contains(&next) {
-                    continue;
-                }
-                visited.insert(next);
-                let range = compute_lowered_succs(&mut lowered_succs, next);
-                lowered_succ_indices.resize(lowered_succs.len(), 0);
-                stack.push(StackEntry {
-                    this: next,
-                    succs: range,
-                    cur_succ: range.1,
-                });
-            }
-        }
-
-        postorder.reverse();
-        let mut rpo = postorder;
-        if let Some(d) = deferred_last {
-            rpo.push(d);
-        }
-
-        // Step 3: now that we have RPO, build the BlockIndex/BB fwd/rev maps.
-        let mut lowered_order = vec![];
-        let mut cold_blocks = FxHashSet::default();
-        let mut lowered_succ_ranges = vec![];
-        let mut lb_to_bindex = FxHashMap::default();
-        for (block, succ_range) in rpo.into_iter() {
-            let index = lowered_order.len() as BlockIndex;
-            lb_to_bindex.insert(block, index);
-            lowered_order.push(block);
-            lowered_succ_ranges.push(succ_range);
-
-            if block
-                .orig_block()
-                .map(|b| f.layout.is_cold(b))
-                .unwrap_or(false)
-            {
-                cold_blocks.insert(index);
-            }
-        }
-
-        let lowered_succ_indices = lowered_succs
-            .iter()
-            .map(|&(inst, succ)| (inst, lb_to_bindex.get(&succ).cloned().unwrap()))
-            .collect();
-
-        let mut orig_map = SecondaryMap::with_default(None);
-        for (i, lb) in lowered_order.iter().enumerate() {
-            let i = i as BlockIndex;
-            if let Some(b) = lb.orig_block() {
-                orig_map[b] = Some(i);
-            }
-        }
-
-        let result = BlockLoweringOrder {
-            lowered_order,
-            lowered_succs,
-            lowered_succ_indices,
-            lowered_succ_ranges,
-            orig_map,
-            cold_blocks,
-        };
-        log::trace!("BlockLoweringOrder: {:?}", result);
-        result
-    }
-
-    /// Get the lowered order of blocks.
-    pub fn lowered_order(&self) -> &[LoweredBlock] {
-        &self.lowered_order[..]
-    }
-
-    /// Get the successor indices for a lowered block.
-    pub fn succ_indices(&self, block: BlockIndex) -> &[(Inst, BlockIndex)] {
-        let range = self.lowered_succ_ranges[block as usize];
-        &self.lowered_succ_indices[range.0..range.1]
-    }
-
-    /// Determine whether the given lowered-block index is cold.
-    pub fn is_cold(&self, block: BlockIndex) -> bool {
-        self.cold_blocks.contains(&block)
-    }
-}
-
-#[cfg(test)]
-mod test {
-    use super::*;
-    use crate::cursor::{Cursor, FuncCursor};
-    use crate::ir::types::*;
-    use crate::ir::{AbiParam, ExternalName, Function, InstBuilder, Signature};
-    use crate::isa::CallConv;
-
-    fn build_test_func(n_blocks: usize, edges: &[(usize, usize)]) -> Function {
-        assert!(n_blocks > 0);
-
-        let name = ExternalName::testcase("test0");
-        let mut sig = Signature::new(CallConv::SystemV);
-        sig.params.push(AbiParam::new(I32));
-        let mut func = Function::with_name_signature(name, sig);
-        let blocks = (0..n_blocks)
-            .map(|i| {
-                let bb = func.dfg.make_block();
-                assert!(bb.as_u32() == i as u32);
-                bb
-            })
-            .collect::<Vec<_>>();
-
-        let arg0 = func.dfg.append_block_param(blocks[0], I32);
-
-        let mut pos = FuncCursor::new(&mut func);
-
-        let mut edge = 0;
-        for i in 0..n_blocks {
-            pos.insert_block(blocks[i]);
-            let mut succs = vec![];
-            while edge < edges.len() && edges[edge].0 == i {
-                succs.push(edges[edge].1);
-                edge += 1;
-            }
-            if succs.len() == 0 {
-                pos.ins().return_(&[arg0]);
-            } else if succs.len() == 1 {
-                pos.ins().jump(blocks[succs[0]], &[]);
-            } else if succs.len() == 2 {
-                pos.ins().brnz(arg0, blocks[succs[0]], &[]);
-                pos.ins().jump(blocks[succs[1]], &[]);
-            } else {
-                panic!("Too many successors");
-            }
-        }
-
-        func
-    }
-
-    #[test]
-    fn test_blockorder_diamond() {
-        let func = build_test_func(4, &[(0, 1), (0, 2), (1, 3), (2, 3)]);
-        let order = BlockLoweringOrder::new(&func);
-
-        assert_eq!(order.lowered_order.len(), 6);
-
-        assert!(order.lowered_order[0].orig_block().unwrap().as_u32() == 0);
-        assert!(order.lowered_order[0].in_edge().is_none());
-        assert!(order.lowered_order[0].out_edge().is_none());
-
-        assert!(order.lowered_order[1].orig_block().unwrap().as_u32() == 1);
-        assert!(order.lowered_order[1].in_edge().unwrap().0.as_u32() == 0);
-        assert!(order.lowered_order[1].in_edge().unwrap().2.as_u32() == 1);
-
-        assert!(order.lowered_order[2].orig_block().is_none());
-        assert!(order.lowered_order[2].in_edge().is_none());
-        assert!(order.lowered_order[2].out_edge().unwrap().0.as_u32() == 1);
-        assert!(order.lowered_order[2].out_edge().unwrap().2.as_u32() == 3);
-
-        assert!(order.lowered_order[3].orig_block().unwrap().as_u32() == 2);
-        assert!(order.lowered_order[3].in_edge().unwrap().0.as_u32() == 0);
-        assert!(order.lowered_order[3].in_edge().unwrap().2.as_u32() == 2);
-        assert!(order.lowered_order[3].out_edge().is_none());
-
-        assert!(order.lowered_order[4].orig_block().is_none());
-        assert!(order.lowered_order[4].in_edge().is_none());
-        assert!(order.lowered_order[4].out_edge().unwrap().0.as_u32() == 2);
-        assert!(order.lowered_order[4].out_edge().unwrap().2.as_u32() == 3);
-
-        assert!(order.lowered_order[5].orig_block().unwrap().as_u32() == 3);
-        assert!(order.lowered_order[5].in_edge().is_none());
-        assert!(order.lowered_order[5].out_edge().is_none());
-    }
-
-    #[test]
-    fn test_blockorder_critedge() {
-        //            0
-        //          /   \
-        //         1     2
-        //        /  \     \
-        //       3    4    |
-        //       |\  _|____|
-        //       | \/ |
-        //       | /\ |
-        //       5    6
-        //
-        // (3 -> 5, 3 -> 6, 4 -> 6 are critical edges and must be split)
-        //
-        let func = build_test_func(
-            7,
-            &[
-                (0, 1),
-                (0, 2),
-                (1, 3),
-                (1, 4),
-                (2, 5),
-                (3, 5),
-                (3, 6),
-                (4, 6),
-            ],
-        );
-        let order = BlockLoweringOrder::new(&func);
-
-        assert_eq!(order.lowered_order.len(), 11);
-        println!("ordered = {:?}", order.lowered_order);
-
-        // block 0
-        assert!(order.lowered_order[0].orig_block().unwrap().as_u32() == 0);
-        assert!(order.lowered_order[0].in_edge().is_none());
-        assert!(order.lowered_order[0].out_edge().is_none());
-
-        // edge 0->1 + block 1
-        assert!(order.lowered_order[1].orig_block().unwrap().as_u32() == 1);
-        assert!(order.lowered_order[1].in_edge().unwrap().0.as_u32() == 0);
-        assert!(order.lowered_order[1].in_edge().unwrap().2.as_u32() == 1);
-        assert!(order.lowered_order[1].out_edge().is_none());
-
-        // edge 1->3 + block 3
-        assert!(order.lowered_order[2].orig_block().unwrap().as_u32() == 3);
-        assert!(order.lowered_order[2].in_edge().unwrap().0.as_u32() == 1);
-        assert!(order.lowered_order[2].in_edge().unwrap().2.as_u32() == 3);
-        assert!(order.lowered_order[2].out_edge().is_none());
-
-        // edge 3->5
-        assert!(order.lowered_order[3].orig_block().is_none());
-        assert!(order.lowered_order[3].in_edge().is_none());
-        assert!(order.lowered_order[3].out_edge().unwrap().0.as_u32() == 3);
-        assert!(order.lowered_order[3].out_edge().unwrap().2.as_u32() == 5);
-
-        // edge 3->6
-        assert!(order.lowered_order[4].orig_block().is_none());
-        assert!(order.lowered_order[4].in_edge().is_none());
-        assert!(order.lowered_order[4].out_edge().unwrap().0.as_u32() == 3);
-        assert!(order.lowered_order[4].out_edge().unwrap().2.as_u32() == 6);
-
-        // edge 1->4 + block 4
-        assert!(order.lowered_order[5].orig_block().unwrap().as_u32() == 4);
-        assert!(order.lowered_order[5].in_edge().unwrap().0.as_u32() == 1);
-        assert!(order.lowered_order[5].in_edge().unwrap().2.as_u32() == 4);
-        assert!(order.lowered_order[5].out_edge().is_none());
-
-        // edge 4->6
-        assert!(order.lowered_order[6].orig_block().is_none());
-        assert!(order.lowered_order[6].in_edge().is_none());
-        assert!(order.lowered_order[6].out_edge().unwrap().0.as_u32() == 4);
-        assert!(order.lowered_order[6].out_edge().unwrap().2.as_u32() == 6);
-
-        // block 6
-        assert!(order.lowered_order[7].orig_block().unwrap().as_u32() == 6);
-        assert!(order.lowered_order[7].in_edge().is_none());
-        assert!(order.lowered_order[7].out_edge().is_none());
-
-        // edge 0->2 + block 2
-        assert!(order.lowered_order[8].orig_block().unwrap().as_u32() == 2);
-        assert!(order.lowered_order[8].in_edge().unwrap().0.as_u32() == 0);
-        assert!(order.lowered_order[8].in_edge().unwrap().2.as_u32() == 2);
-        assert!(order.lowered_order[8].out_edge().is_none());
-
-        // edge 2->5
-        assert!(order.lowered_order[9].orig_block().is_none());
-        assert!(order.lowered_order[9].in_edge().is_none());
-        assert!(order.lowered_order[9].out_edge().unwrap().0.as_u32() == 2);
-        assert!(order.lowered_order[9].out_edge().unwrap().2.as_u32() == 5);
-
-        // block 5
-        assert!(order.lowered_order[10].orig_block().unwrap().as_u32() == 5);
-        assert!(order.lowered_order[10].in_edge().is_none());
-        assert!(order.lowered_order[10].out_edge().is_none());
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/buffer.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/buffer.rs
deleted file mode 100644
index 7091d880d..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/buffer.rs
+++ /dev/null
@@ -1,2096 +0,0 @@
-//! In-memory representation of compiled machine code, with labels and fixups to
-//! refer to those labels. Handles constant-pool island insertion and also
-//! veneer insertion for out-of-range jumps.
-//!
-//! This code exists to solve three problems:
-//!
-//! - Branch targets for forward branches are not known until later, when we
-//!   emit code in a single pass through the instruction structs.
-//!
-//! - On many architectures, address references or offsets have limited range.
-//!   For example, on AArch64, conditional branches can only target code +/- 1MB
-//!   from the branch itself.
-//!
-//! - The lowering of control flow from the CFG-with-edges produced by
-//!   [BlockLoweringOrder](super::BlockLoweringOrder), combined with many empty
-//!   edge blocks when the register allocator does not need to insert any
-//!   spills/reloads/moves in edge blocks, results in many suboptimal branch
-//!   patterns. The lowering also pays no attention to block order, and so
-//!   two-target conditional forms (cond-br followed by uncond-br) can often by
-//!   avoided because one of the targets is the fallthrough. There are several
-//!   cases here where we can simplify to use fewer branches.
-//!
-//! This "buffer" implements a single-pass code emission strategy (with a later
-//! "fixup" pass, but only through recorded fixups, not all instructions). The
-//! basic idea is:
-//!
-//! - Emit branches as they are, including two-target (cond/uncond) compound
-//!   forms, but with zero offsets and optimistically assuming the target will be
-//!   in range. Record the "fixup" for later. Targets are denoted instead by
-//!   symbolic "labels" that are then bound to certain offsets in the buffer as
-//!   we emit code. (Nominally, there is a label at the start of every basic
-//!   block.)
-//!
-//! - As we do this, track the offset in the buffer at which the first label
-//!   reference "goes out of range". We call this the "deadline". If we reach the
-//!   deadline and we still have not bound the label to which an unresolved branch
-//!   refers, we have a problem!
-//!
-//! - To solve this problem, we emit "islands" full of "veneers". An island is
-//!   simply a chunk of code inserted in the middle of the code actually produced
-//!   by the emitter (e.g., vcode iterating over instruction structs). The emitter
-//!   has some awareness of this: it either asks for an island between blocks, so
-//!   it is not accidentally executed, or else it emits a branch around the island
-//!   when all other options fail (see `Inst::EmitIsland` meta-instruction).
-//!
-//! - A "veneer" is an instruction (or sequence of instructions) in an "island"
-//!   that implements a longer-range reference to a label. The idea is that, for
-//!   example, a branch with a limited range can branch to a "veneer" instead,
-//!   which is simply a branch in a form that can use a longer-range reference. On
-//!   AArch64, for example, conditionals have a +/- 1 MB range, but a conditional
-//!   can branch to an unconditional branch which has a +/- 128 MB range. Hence, a
-//!   conditional branch's label reference can be fixed up with a "veneer" to
-//!   achieve a longer range.
-//!
-//! - To implement all of this, we require the backend to provide a `LabelUse`
-//!   type that implements a trait. This is nominally an enum that records one of
-//!   several kinds of references to an offset in code -- basically, a relocation
-//!   type -- and will usually correspond to different instruction formats. The
-//!   `LabelUse` implementation specifies the maximum range, how to patch in the
-//!   actual label location when known, and how to generate a veneer to extend the
-//!   range.
-//!
-//! That satisfies label references, but we still may have suboptimal branch
-//! patterns. To clean up the branches, we do a simple "peephole"-style
-//! optimization on the fly. To do so, the emitter (e.g., `Inst::emit()`)
-//! informs the buffer of branches in the code and, in the case of conditionals,
-//! the code that would have been emitted to invert this branch's condition. We
-//! track the "latest branches": these are branches that are contiguous up to
-//! the current offset. (If any code is emitted after a branch, that branch or
-//! run of contiguous branches is no longer "latest".) The latest branches are
-//! those that we can edit by simply truncating the buffer and doing something
-//! else instead.
-//!
-//! To optimize branches, we implement several simple rules, and try to apply
-//! them to the "latest branches" when possible:
-//!
-//! - A branch with a label target, when that label is bound to the ending
-//!   offset of the branch (the fallthrough location), can be removed altogether,
-//!   because the branch would have no effect).
-//!
-//! - An unconditional branch that starts at a label location, and branches to
-//!   another label, results in a "label alias": all references to the label bound
-//!   *to* this branch instruction are instead resolved to the *target* of the
-//!   branch instruction. This effectively removes empty blocks that just
-//!   unconditionally branch to the next block. We call this "branch threading".
-//!
-//! - A conditional followed by an unconditional, when the conditional branches
-//!   to the unconditional's fallthrough, results in (i) the truncation of the
-//!   unconditional, (ii) the inversion of the condition's condition, and (iii)
-//!   replacement of the conditional's target (using the original target of the
-//!   unconditional). This is a fancy way of saying "we can flip a two-target
-//!   conditional branch's taken/not-taken targets if it works better with our
-//!   fallthrough". To make this work, the emitter actually gives the buffer
-//!   *both* forms of every conditional branch: the true form is emitted into the
-//!   buffer, and the "inverted" machine-code bytes are provided as part of the
-//!   branch-fixup metadata.
-//!
-//! - An unconditional B preceded by another unconditional P, when B's label(s) have
-//!   been redirected to target(B), can be removed entirely. This is an extension
-//!   of the branch-threading optimization, and is valid because if we know there
-//!   will be no fallthrough into this branch instruction (the prior instruction
-//!   is an unconditional jump), and if we know we have successfully redirected
-//!   all labels, then this branch instruction is unreachable. Note that this
-//!   works because the redirection happens before the label is ever resolved
-//!   (fixups happen at island emission time, at which point latest-branches are
-//!   cleared, or at the end of emission), so we are sure to catch and redirect
-//!   all possible paths to this instruction.
-//!
-//! # Branch-optimization Correctness
-//!
-//! The branch-optimization mechanism depends on a few data structures with
-//! invariants, which are always held outside the scope of top-level public
-//! methods:
-//!
-//! - The latest-branches list. Each entry describes a span of the buffer
-//!   (start/end offsets), the label target, the corresponding fixup-list entry
-//!   index, and the bytes (must be the same length) for the inverted form, if
-//!   conditional. The list of labels that are bound to the start-offset of this
-//!   branch is *complete* (if any label has a resolved offset equal to `start`
-//!   and is not an alias, it must appear in this list) and *precise* (no label
-//!   in this list can be bound to another offset). No label in this list should
-//!   be an alias.  No two branch ranges can overlap, and branches are in
-//!   ascending-offset order.
-//!
-//! - The labels-at-tail list. This contains all MachLabels that have been bound
-//!   to (whose resolved offsets are equal to) the tail offset of the buffer.
-//!   No label in this list should be an alias.
-//!
-//! - The label_offsets array, containing the bound offset of a label or
-//!   UNKNOWN. No label can be bound at an offset greater than the current
-//!   buffer tail.
-//!
-//! - The label_aliases array, containing another label to which a label is
-//!   bound or UNKNOWN. A label's resolved offset is the resolved offset
-//!   of the label it is aliased to, if this is set.
-//!
-//! We argue below, at each method, how the invariants in these data structures
-//! are maintained (grep for "Post-invariant").
-//!
-//! Given these invariants, we argue why each optimization preserves execution
-//! semantics below (grep for "Preserves execution semantics").
-
-use crate::binemit::{Addend, CodeOffset, Reloc, StackMap};
-use crate::ir::{ExternalName, Opcode, SourceLoc, TrapCode};
-use crate::isa::unwind::UnwindInst;
-use crate::machinst::{
-    BlockIndex, MachInstLabelUse, TextSectionBuilder, VCodeConstant, VCodeConstants, VCodeInst,
-};
-use crate::timing;
-use cranelift_entity::{entity_impl, SecondaryMap};
-use log::trace;
-use smallvec::SmallVec;
-use std::convert::TryFrom;
-use std::mem;
-use std::string::String;
-use std::vec::Vec;
-
-/// A buffer of output to be produced, fixed up, and then emitted to a CodeSink
-/// in bulk.
-///
-/// This struct uses `SmallVec`s to support small-ish function bodies without
-/// any heap allocation. As such, it will be several kilobytes large. This is
-/// likely fine as long as it is stack-allocated for function emission then
-/// thrown away; but beware if many buffer objects are retained persistently.
-pub struct MachBuffer<I: VCodeInst> {
-    /// The buffer contents, as raw bytes.
-    data: SmallVec<[u8; 1024]>,
-    /// Any relocations referring to this code. Note that only *external*
-    /// relocations are tracked here; references to labels within the buffer are
-    /// resolved before emission.
-    relocs: SmallVec<[MachReloc; 16]>,
-    /// Any trap records referring to this code.
-    traps: SmallVec<[MachTrap; 16]>,
-    /// Any call site records referring to this code.
-    call_sites: SmallVec<[MachCallSite; 16]>,
-    /// Any source location mappings referring to this code.
-    srclocs: SmallVec<[MachSrcLoc; 64]>,
-    /// Any stack maps referring to this code.
-    stack_maps: SmallVec<[MachStackMap; 8]>,
-    /// Any unwind info at a given location.
-    unwind_info: SmallVec<[(CodeOffset, UnwindInst); 8]>,
-    /// The current source location in progress (after `start_srcloc()` and
-    /// before `end_srcloc()`).  This is a (start_offset, src_loc) tuple.
-    cur_srcloc: Option<(CodeOffset, SourceLoc)>,
-    /// Known label offsets; `UNKNOWN_LABEL_OFFSET` if unknown.
-    label_offsets: SmallVec<[CodeOffset; 16]>,
-    /// Label aliases: when one label points to an unconditional jump, and that
-    /// jump points to another label, we can redirect references to the first
-    /// label immediately to the second.
-    ///
-    /// Invariant: we don't have label-alias cycles. We ensure this by,
-    /// before setting label A to alias label B, resolving B's alias
-    /// target (iteratively until a non-aliased label); if B is already
-    /// aliased to A, then we cannot alias A back to B.
-    label_aliases: SmallVec<[MachLabel; 16]>,
-    /// Constants that must be emitted at some point.
-    pending_constants: SmallVec<[MachLabelConstant; 16]>,
-    /// Fixups that must be performed after all code is emitted.
-    fixup_records: SmallVec<[MachLabelFixup<I>; 16]>,
-    /// Current deadline at which all constants are flushed and all code labels
-    /// are extended by emitting long-range jumps in an island. This flush
-    /// should be rare (e.g., on AArch64, the shortest-range PC-rel references
-    /// are +/- 1MB for conditional jumps and load-literal instructions), so
-    /// it's acceptable to track a minimum and flush-all rather than doing more
-    /// detailed "current minimum" / sort-by-deadline trickery.
-    island_deadline: CodeOffset,
-    /// How many bytes are needed in the worst case for an island, given all
-    /// pending constants and fixups.
-    island_worst_case_size: CodeOffset,
-    /// Latest branches, to facilitate in-place editing for better fallthrough
-    /// behavior and empty-block removal.
-    latest_branches: SmallVec<[MachBranch; 4]>,
-    /// All labels at the current offset (emission tail). This is lazily
-    /// cleared: it is actually accurate as long as the current offset is
-    /// `labels_at_tail_off`, but if `cur_offset()` has grown larger, it should
-    /// be considered as empty.
-    ///
-    /// For correctness, this *must* be complete (i.e., the vector must contain
-    /// all labels whose offsets are resolved to the current tail), because we
-    /// rely on it to update labels when we truncate branches.
-    labels_at_tail: SmallVec<[MachLabel; 4]>,
-    /// The last offset at which `labels_at_tail` is valid. It is conceptually
-    /// always describing the tail of the buffer, but we do not clear
-    /// `labels_at_tail` eagerly when the tail grows, rather we lazily clear it
-    /// when the offset has grown past this (`labels_at_tail_off`) point.
-    /// Always <= `cur_offset()`.
-    labels_at_tail_off: CodeOffset,
-    /// Map used constants to their [MachLabel].
-    constant_labels: SecondaryMap<VCodeConstant, MachLabel>,
-}
-
-/// A `MachBuffer` once emission is completed: holds generated code and records,
-/// without fixups. This allows the type to be independent of the backend.
-pub struct MachBufferFinalized {
-    /// The buffer contents, as raw bytes.
-    data: SmallVec<[u8; 1024]>,
-    /// Any relocations referring to this code. Note that only *external*
-    /// relocations are tracked here; references to labels within the buffer are
-    /// resolved before emission.
-    relocs: SmallVec<[MachReloc; 16]>,
-    /// Any trap records referring to this code.
-    traps: SmallVec<[MachTrap; 16]>,
-    /// Any call site records referring to this code.
-    call_sites: SmallVec<[MachCallSite; 16]>,
-    /// Any source location mappings referring to this code.
-    srclocs: SmallVec<[MachSrcLoc; 64]>,
-    /// Any stack maps referring to this code.
-    stack_maps: SmallVec<[MachStackMap; 8]>,
-    /// Any unwind info at a given location.
-    pub unwind_info: SmallVec<[(CodeOffset, UnwindInst); 8]>,
-}
-
-const UNKNOWN_LABEL_OFFSET: CodeOffset = 0xffff_ffff;
-const UNKNOWN_LABEL: MachLabel = MachLabel(0xffff_ffff);
-
-/// Threshold on max length of `labels_at_this_branch` list to avoid
-/// unbounded quadratic behavior (see comment below at use-site).
-const LABEL_LIST_THRESHOLD: usize = 100;
-
-/// A label refers to some offset in a `MachBuffer`. It may not be resolved at
-/// the point at which it is used by emitted code; the buffer records "fixups"
-/// for references to the label, and will come back and patch the code
-/// appropriately when the label's location is eventually known.
-#[derive(Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
-pub struct MachLabel(u32);
-entity_impl!(MachLabel);
-
-impl MachLabel {
-    /// Get a label for a block. (The first N MachLabels are always reseved for
-    /// the N blocks in the vcode.)
-    pub fn from_block(bindex: BlockIndex) -> MachLabel {
-        MachLabel(bindex)
-    }
-
-    /// Get the numeric label index.
-    pub fn get(self) -> u32 {
-        self.0
-    }
-
-    /// Creates a string representing this label, for convenience.
-    pub fn to_string(&self) -> String {
-        format!("label{}", self.0)
-    }
-}
-
-impl Default for MachLabel {
-    fn default() -> Self {
-        UNKNOWN_LABEL
-    }
-}
-
-/// A stack map extent, when creating a stack map.
-pub enum StackMapExtent {
-    /// The stack map starts at this instruction, and ends after the number of upcoming bytes
-    /// (note: this is a code offset diff).
-    UpcomingBytes(CodeOffset),
-
-    /// The stack map started at the given offset and ends at the current one. This helps
-    /// architectures where the instruction size has not a fixed length.
-    StartedAtOffset(CodeOffset),
-}
-
-impl<I: VCodeInst> MachBuffer<I> {
-    /// Create a new section, known to start at `start_offset` and with a size limited to
-    /// `length_limit`.
-    pub fn new() -> MachBuffer<I> {
-        MachBuffer {
-            data: SmallVec::new(),
-            relocs: SmallVec::new(),
-            traps: SmallVec::new(),
-            call_sites: SmallVec::new(),
-            srclocs: SmallVec::new(),
-            stack_maps: SmallVec::new(),
-            unwind_info: SmallVec::new(),
-            cur_srcloc: None,
-            label_offsets: SmallVec::new(),
-            label_aliases: SmallVec::new(),
-            pending_constants: SmallVec::new(),
-            fixup_records: SmallVec::new(),
-            island_deadline: UNKNOWN_LABEL_OFFSET,
-            island_worst_case_size: 0,
-            latest_branches: SmallVec::new(),
-            labels_at_tail: SmallVec::new(),
-            labels_at_tail_off: 0,
-            constant_labels: SecondaryMap::new(),
-        }
-    }
-
-    /// Debug-only: check invariants of labels and branch-records described
-    /// under "Branch-optimization Correctness" above.
-    ///
-    /// These invariants are checked at branch-simplification
-    /// time. Note that they may be temporarily violated at other
-    /// times, e.g. after calling `add_{cond,uncond}_branch()` and
-    /// before emitting branch bytes.
-    fn check_label_branch_invariants(&self) {
-        if !cfg!(debug_assertions) || cfg!(fuzzing) {
-            return;
-        }
-        let cur_off = self.cur_offset();
-        // Check that every entry in latest_branches has *correct*
-        // labels_at_this_branch lists. We do not check completeness because
-        // that would require building a reverse index, which is too slow even
-        // for a debug invariant check.
-        let mut last_end = 0;
-        for b in &self.latest_branches {
-            debug_assert!(b.start < b.end);
-            debug_assert!(b.end <= cur_off);
-            debug_assert!(b.start >= last_end);
-            last_end = b.end;
-            for &l in &b.labels_at_this_branch {
-                debug_assert_eq!(self.resolve_label_offset(l), b.start);
-                debug_assert_eq!(self.label_aliases[l.0 as usize], UNKNOWN_LABEL);
-            }
-        }
-
-        // Check that every label is unresolved, or resolved at or
-        // before cur_offset. If at cur_offset, must be in
-        // `labels_at_tail`. We skip labels that are aliased to
-        // others already.
-        for (i, &off) in self.label_offsets.iter().enumerate() {
-            let label = MachLabel(i as u32);
-            if self.label_aliases[i] != UNKNOWN_LABEL {
-                continue;
-            }
-            debug_assert!(off == UNKNOWN_LABEL_OFFSET || off <= cur_off);
-            if off == cur_off {
-                debug_assert!(
-                    self.labels_at_tail_off == cur_off && self.labels_at_tail.contains(&label)
-                );
-            }
-        }
-
-        // Check that every label in `labels_at_tail_off` is precise, i.e.,
-        // resolves to the cur offset.
-        debug_assert!(self.labels_at_tail_off <= cur_off);
-        if self.labels_at_tail_off == cur_off {
-            for &l in &self.labels_at_tail {
-                debug_assert_eq!(self.resolve_label_offset(l), cur_off);
-                debug_assert_eq!(self.label_aliases[l.0 as usize], UNKNOWN_LABEL);
-            }
-        }
-    }
-
-    /// Current offset from start of buffer.
-    pub fn cur_offset(&self) -> CodeOffset {
-        self.data.len() as CodeOffset
-    }
-
-    /// Add a byte.
-    pub fn put1(&mut self, value: u8) {
-        trace!("MachBuffer: put byte @ {}: {:x}", self.cur_offset(), value);
-        self.data.push(value);
-
-        // Post-invariant: conceptual-labels_at_tail contains a complete and
-        // precise list of labels bound at `cur_offset()`. We have advanced
-        // `cur_offset()`, hence if it had been equal to `labels_at_tail_off`
-        // before, it is not anymore (and it cannot become equal, because
-        // `labels_at_tail_off` is always <= `cur_offset()`). Thus the list is
-        // conceptually empty (even though it is only lazily cleared). No labels
-        // can be bound at this new offset (by invariant on `label_offsets`).
-        // Hence the invariant holds.
-    }
-
-    /// Add 2 bytes.
-    pub fn put2(&mut self, value: u16) {
-        trace!(
-            "MachBuffer: put 16-bit word @ {}: {:x}",
-            self.cur_offset(),
-            value
-        );
-        let bytes = value.to_le_bytes();
-        self.data.extend_from_slice(&bytes[..]);
-
-        // Post-invariant: as for `put1()`.
-    }
-
-    /// Add 4 bytes.
-    pub fn put4(&mut self, value: u32) {
-        trace!(
-            "MachBuffer: put 32-bit word @ {}: {:x}",
-            self.cur_offset(),
-            value
-        );
-        let bytes = value.to_le_bytes();
-        self.data.extend_from_slice(&bytes[..]);
-
-        // Post-invariant: as for `put1()`.
-    }
-
-    /// Add 8 bytes.
-    pub fn put8(&mut self, value: u64) {
-        trace!(
-            "MachBuffer: put 64-bit word @ {}: {:x}",
-            self.cur_offset(),
-            value
-        );
-        let bytes = value.to_le_bytes();
-        self.data.extend_from_slice(&bytes[..]);
-
-        // Post-invariant: as for `put1()`.
-    }
-
-    /// Add a slice of bytes.
-    pub fn put_data(&mut self, data: &[u8]) {
-        trace!(
-            "MachBuffer: put data @ {}: len {}",
-            self.cur_offset(),
-            data.len()
-        );
-        self.data.extend_from_slice(data);
-
-        // Post-invariant: as for `put1()`.
-    }
-
-    /// Reserve appended space and return a mutable slice referring to it.
-    pub fn get_appended_space(&mut self, len: usize) -> &mut [u8] {
-        trace!("MachBuffer: put data @ {}: len {}", self.cur_offset(), len);
-        let off = self.data.len();
-        let new_len = self.data.len() + len;
-        self.data.resize(new_len, 0);
-        &mut self.data[off..]
-
-        // Post-invariant: as for `put1()`.
-    }
-
-    /// Align up to the given alignment.
-    pub fn align_to(&mut self, align_to: CodeOffset) {
-        trace!("MachBuffer: align to {}", align_to);
-        assert!(align_to.is_power_of_two());
-        while self.cur_offset() & (align_to - 1) != 0 {
-            self.put1(0);
-        }
-
-        // Post-invariant: as for `put1()`.
-    }
-
-    /// Allocate a `Label` to refer to some offset. May not be bound to a fixed
-    /// offset yet.
-    pub fn get_label(&mut self) -> MachLabel {
-        let l = self.label_offsets.len() as u32;
-        self.label_offsets.push(UNKNOWN_LABEL_OFFSET);
-        self.label_aliases.push(UNKNOWN_LABEL);
-        trace!("MachBuffer: new label -> {:?}", MachLabel(l));
-        MachLabel(l)
-
-        // Post-invariant: the only mutation is to add a new label; it has no
-        // bound offset yet, so it trivially satisfies all invariants.
-    }
-
-    /// Reserve the first N MachLabels for blocks.
-    pub fn reserve_labels_for_blocks(&mut self, blocks: BlockIndex) {
-        trace!("MachBuffer: first {} labels are for blocks", blocks);
-        debug_assert!(self.label_offsets.is_empty());
-        self.label_offsets
-            .resize(blocks as usize, UNKNOWN_LABEL_OFFSET);
-        self.label_aliases.resize(blocks as usize, UNKNOWN_LABEL);
-
-        // Post-invariant: as for `get_label()`.
-    }
-
-    /// Reserve the next N MachLabels for constants.
-    pub fn reserve_labels_for_constants(&mut self, constants: &VCodeConstants) {
-        trace!(
-            "MachBuffer: next {} labels are for constants",
-            constants.len()
-        );
-        for c in constants.keys() {
-            self.constant_labels[c] = self.get_label();
-        }
-
-        // Post-invariant: as for `get_label()`.
-    }
-
-    /// Retrieve the reserved label for a constant.
-    pub fn get_label_for_constant(&self, constant: VCodeConstant) -> MachLabel {
-        self.constant_labels[constant]
-    }
-
-    /// Bind a label to the current offset. A label can only be bound once.
-    pub fn bind_label(&mut self, label: MachLabel) {
-        trace!(
-            "MachBuffer: bind label {:?} at offset {}",
-            label,
-            self.cur_offset()
-        );
-        debug_assert_eq!(self.label_offsets[label.0 as usize], UNKNOWN_LABEL_OFFSET);
-        debug_assert_eq!(self.label_aliases[label.0 as usize], UNKNOWN_LABEL);
-        let offset = self.cur_offset();
-        self.label_offsets[label.0 as usize] = offset;
-        self.lazily_clear_labels_at_tail();
-        self.labels_at_tail.push(label);
-
-        // Invariants hold: bound offset of label is <= cur_offset (in fact it
-        // is equal). If the `labels_at_tail` list was complete and precise
-        // before, it is still, because we have bound this label to the current
-        // offset and added it to the list (which contains all labels at the
-        // current offset).
-
-        self.check_label_branch_invariants();
-        self.optimize_branches();
-
-        // Post-invariant: by `optimize_branches()` (see argument there).
-    }
-
-    /// Lazily clear `labels_at_tail` if the tail offset has moved beyond the
-    /// offset that it applies to.
-    fn lazily_clear_labels_at_tail(&mut self) {
-        let offset = self.cur_offset();
-        if offset > self.labels_at_tail_off {
-            self.labels_at_tail_off = offset;
-            self.labels_at_tail.clear();
-        }
-
-        // Post-invariant: either labels_at_tail_off was at cur_offset, and
-        // state is untouched, or was less than cur_offset, in which case the
-        // labels_at_tail list was conceptually empty, and is now actually
-        // empty.
-    }
-
-    /// Resolve a label to an offset, if known. May return `UNKNOWN_LABEL_OFFSET`.
-    pub(crate) fn resolve_label_offset(&self, mut label: MachLabel) -> CodeOffset {
-        let mut iters = 0;
-        while self.label_aliases[label.0 as usize] != UNKNOWN_LABEL {
-            label = self.label_aliases[label.0 as usize];
-            // To protect against an infinite loop (despite our assurances to
-            // ourselves that the invariants make this impossible), assert out
-            // after 1M iterations. The number of basic blocks is limited
-            // in most contexts anyway so this should be impossible to hit with
-            // a legitimate input.
-            iters += 1;
-            assert!(iters < 1_000_000, "Unexpected cycle in label aliases");
-        }
-        self.label_offsets[label.0 as usize]
-
-        // Post-invariant: no mutations.
-    }
-
-    /// Emit a reference to the given label with the given reference type (i.e.,
-    /// branch-instruction format) at the current offset.  This is like a
-    /// relocation, but handled internally.
-    ///
-    /// This can be called before the branch is actually emitted; fixups will
-    /// not happen until an island is emitted or the buffer is finished.
-    pub fn use_label_at_offset(&mut self, offset: CodeOffset, label: MachLabel, kind: I::LabelUse) {
-        trace!(
-            "MachBuffer: use_label_at_offset: offset {} label {:?} kind {:?}",
-            offset,
-            label,
-            kind
-        );
-
-        // Add the fixup, and update the worst-case island size based on a
-        // veneer for this label use.
-        self.fixup_records.push(MachLabelFixup {
-            label,
-            offset,
-            kind,
-        });
-        if kind.supports_veneer() {
-            self.island_worst_case_size += kind.veneer_size();
-            self.island_worst_case_size &= !(I::LabelUse::ALIGN - 1);
-        }
-        let deadline = offset.saturating_add(kind.max_pos_range());
-        if deadline < self.island_deadline {
-            self.island_deadline = deadline;
-        }
-
-        // Post-invariant: no mutations to branches/labels data structures.
-    }
-
-    /// Inform the buffer of an unconditional branch at the given offset,
-    /// targetting the given label. May be used to optimize branches.
-    /// The last added label-use must correspond to this branch.
-    /// This must be called when the current offset is equal to `start`; i.e.,
-    /// before actually emitting the branch. This implies that for a branch that
-    /// uses a label and is eligible for optimizations by the MachBuffer, the
-    /// proper sequence is:
-    ///
-    /// - Call `use_label_at_offset()` to emit the fixup record.
-    /// - Call `add_uncond_branch()` to make note of the branch.
-    /// - Emit the bytes for the branch's machine code.
-    ///
-    /// Additional requirement: no labels may be bound between `start` and `end`
-    /// (exclusive on both ends).
-    pub fn add_uncond_branch(&mut self, start: CodeOffset, end: CodeOffset, target: MachLabel) {
-        assert!(self.cur_offset() == start);
-        debug_assert!(end > start);
-        assert!(!self.fixup_records.is_empty());
-        let fixup = self.fixup_records.len() - 1;
-        self.lazily_clear_labels_at_tail();
-        self.latest_branches.push(MachBranch {
-            start,
-            end,
-            target,
-            fixup,
-            inverted: None,
-            labels_at_this_branch: self.labels_at_tail.clone(),
-        });
-
-        // Post-invariant: we asserted branch start is current tail; the list of
-        // labels at branch is cloned from list of labels at current tail.
-    }
-
-    /// Inform the buffer of a conditional branch at the given offset,
-    /// targetting the given label. May be used to optimize branches.
-    /// The last added label-use must correspond to this branch.
-    ///
-    /// Additional requirement: no labels may be bound between `start` and `end`
-    /// (exclusive on both ends).
-    pub fn add_cond_branch(
-        &mut self,
-        start: CodeOffset,
-        end: CodeOffset,
-        target: MachLabel,
-        inverted: &[u8],
-    ) {
-        assert!(self.cur_offset() == start);
-        debug_assert!(end > start);
-        assert!(!self.fixup_records.is_empty());
-        debug_assert!(inverted.len() == (end - start) as usize);
-        let fixup = self.fixup_records.len() - 1;
-        let inverted = Some(SmallVec::from(inverted));
-        self.lazily_clear_labels_at_tail();
-        self.latest_branches.push(MachBranch {
-            start,
-            end,
-            target,
-            fixup,
-            inverted,
-            labels_at_this_branch: self.labels_at_tail.clone(),
-        });
-
-        // Post-invariant: we asserted branch start is current tail; labels at
-        // branch list is cloned from list of labels at current tail.
-    }
-
-    fn truncate_last_branch(&mut self) {
-        self.lazily_clear_labels_at_tail();
-        // Invariants hold at this point.
-
-        let b = self.latest_branches.pop().unwrap();
-        assert!(b.end == self.cur_offset());
-
-        // State:
-        //    [PRE CODE]
-        //  Offset b.start, b.labels_at_this_branch:
-        //    [BRANCH CODE]
-        //  cur_off, self.labels_at_tail -->
-        //    (end of buffer)
-        self.data.truncate(b.start as usize);
-        self.fixup_records.truncate(b.fixup);
-        while let Some(mut last_srcloc) = self.srclocs.last_mut() {
-            if last_srcloc.end <= b.start {
-                break;
-            }
-            if last_srcloc.start < b.start {
-                last_srcloc.end = b.start;
-                break;
-            }
-            self.srclocs.pop();
-        }
-        // State:
-        //    [PRE CODE]
-        //  cur_off, Offset b.start, b.labels_at_this_branch:
-        //    (end of buffer)
-        //
-        //  self.labels_at_tail -->  (past end of buffer)
-        let cur_off = self.cur_offset();
-        self.labels_at_tail_off = cur_off;
-        // State:
-        //    [PRE CODE]
-        //  cur_off, Offset b.start, b.labels_at_this_branch,
-        //  self.labels_at_tail:
-        //    (end of buffer)
-        //
-        // resolve_label_offset(l) for l in labels_at_tail:
-        //    (past end of buffer)
-
-        trace!(
-            "truncate_last_branch: truncated {:?}; off now {}",
-            b,
-            cur_off
-        );
-
-        // Fix up resolved label offsets for labels at tail.
-        for &l in &self.labels_at_tail {
-            self.label_offsets[l.0 as usize] = cur_off;
-        }
-        // Old labels_at_this_branch are now at cur_off.
-        self.labels_at_tail
-            .extend(b.labels_at_this_branch.into_iter());
-
-        // Post-invariant: this operation is defined to truncate the buffer,
-        // which moves cur_off backward, and to move labels at the end of the
-        // buffer back to the start-of-branch offset.
-        //
-        // latest_branches satisfies all invariants:
-        // - it has no branches past the end of the buffer (branches are in
-        //   order, we removed the last one, and we truncated the buffer to just
-        //   before the start of that branch)
-        // - no labels were moved to lower offsets than the (new) cur_off, so
-        //   the labels_at_this_branch list for any other branch need not change.
-        //
-        // labels_at_tail satisfies all invariants:
-        // - all labels that were at the tail after the truncated branch are
-        //   moved backward to just before the branch, which becomes the new tail;
-        //   thus every element in the list should remain (ensured by `.extend()`
-        //   above).
-        // - all labels that refer to the new tail, which is the start-offset of
-        //   the truncated branch, must be present. The `labels_at_this_branch`
-        //   list in the truncated branch's record is a complete and precise list
-        //   of exactly these labels; we append these to labels_at_tail.
-        // - labels_at_tail_off is at cur_off after truncation occurs, so the
-        //   list is valid (not to be lazily cleared).
-        //
-        // The stated operation was performed:
-        // - For each label at the end of the buffer prior to this method, it
-        //   now resolves to the new (truncated) end of the buffer: it must have
-        //   been in `labels_at_tail` (this list is precise and complete, and
-        //   the tail was at the end of the truncated branch on entry), and we
-        //   iterate over this list and set `label_offsets` to the new tail.
-        //   None of these labels could have been an alias (by invariant), so
-        //   `label_offsets` is authoritative for each.
-        // - No other labels will be past the end of the buffer, because of the
-        //   requirement that no labels be bound to the middle of branch ranges
-        //   (see comments to `add_{cond,uncond}_branch()`).
-        // - The buffer is truncated to just before the last branch, and the
-        //   fixup record referring to that last branch is removed.
-    }
-
-    fn optimize_branches(&mut self) {
-        self.lazily_clear_labels_at_tail();
-        // Invariants valid at this point.
-
-        trace!(
-            "enter optimize_branches:\n b = {:?}\n l = {:?}\n f = {:?}",
-            self.latest_branches,
-            self.labels_at_tail,
-            self.fixup_records
-        );
-
-        // We continue to munch on branches at the tail of the buffer until no
-        // more rules apply. Note that the loop only continues if a branch is
-        // actually truncated (or if labels are redirected away from a branch),
-        // so this always makes progress.
-        while let Some(b) = self.latest_branches.last() {
-            let cur_off = self.cur_offset();
-            trace!("optimize_branches: last branch {:?} at off {}", b, cur_off);
-            // If there has been any code emission since the end of the last branch or
-            // label definition, then there's nothing we can edit (because we
-            // don't move code once placed, only back up and overwrite), so
-            // clear the records and finish.
-            if b.end < cur_off {
-                break;
-            }
-
-            // If the "labels at this branch" list on this branch is
-            // longer than a threshold, don't do any simplification,
-            // and let the branch remain to separate those labels from
-            // the current tail. This avoids quadratic behavior (see
-            // #3468): otherwise, if a long string of "goto next;
-            // next:" patterns are emitted, all of the labels will
-            // coalesce into a long list of aliases for the current
-            // buffer tail. We must track all aliases of the current
-            // tail for correctness, but we are also allowed to skip
-            // optimization (removal) of any branch, so we take the
-            // escape hatch here and let it stand. In effect this
-            // "spreads" the many thousands of labels in the
-            // pathological case among an actual (harmless but
-            // suboptimal) instruction once per N labels.
-            if b.labels_at_this_branch.len() > LABEL_LIST_THRESHOLD {
-                break;
-            }
-
-            // Invariant: we are looking at a branch that ends at the tail of
-            // the buffer.
-
-            // For any branch, conditional or unconditional:
-            // - If the target is a label at the current offset, then remove
-            //   the conditional branch, and reset all labels that targetted
-            //   the current offset (end of branch) to the truncated
-            //   end-of-code.
-            //
-            // Preserves execution semantics: a branch to its own fallthrough
-            // address is equivalent to a no-op; in both cases, nextPC is the
-            // fallthrough.
-            if self.resolve_label_offset(b.target) == cur_off {
-                trace!("branch with target == cur off; truncating");
-                self.truncate_last_branch();
-                continue;
-            }
-
-            // If latest is an unconditional branch:
-            //
-            // - If the branch's target is not its own start address, then for
-            //   each label at the start of branch, make the label an alias of the
-            //   branch target, and remove the label from the "labels at this
-            //   branch" list.
-            //
-            //   - Preserves execution semantics: an unconditional branch's
-            //     only effect is to set PC to a new PC; this change simply
-            //     collapses one step in the step-semantics.
-            //
-            //   - Post-invariant: the labels that were bound to the start of
-            //     this branch become aliases, so they must not be present in any
-            //     labels-at-this-branch list or the labels-at-tail list. The
-            //     labels are removed form the latest-branch record's
-            //     labels-at-this-branch list, and are never placed in the
-            //     labels-at-tail list. Furthermore, it is correct that they are
-            //     not in either list, because they are now aliases, and labels
-            //     that are aliases remain aliases forever.
-            //
-            // - If there is a prior unconditional branch that ends just before
-            //   this one begins, and this branch has no labels bound to its
-            //   start, then we can truncate this branch, because it is entirely
-            //   unreachable (we have redirected all labels that make it
-            //   reachable otherwise). Do so and continue around the loop.
-            //
-            //   - Preserves execution semantics: the branch is unreachable,
-            //     because execution can only flow into an instruction from the
-            //     prior instruction's fallthrough or from a branch bound to that
-            //     instruction's start offset. Unconditional branches have no
-            //     fallthrough, so if the prior instruction is an unconditional
-            //     branch, no fallthrough entry can happen. The
-            //     labels-at-this-branch list is complete (by invariant), so if it
-            //     is empty, then the instruction is entirely unreachable. Thus,
-            //     it can be removed.
-            //
-            //   - Post-invariant: ensured by truncate_last_branch().
-            //
-            // - If there is a prior conditional branch whose target label
-            //   resolves to the current offset (branches around the
-            //   unconditional branch), then remove the unconditional branch,
-            //   and make the target of the unconditional the target of the
-            //   conditional instead.
-            //
-            //   - Preserves execution semantics: previously we had:
-            //
-            //         L1:
-            //            cond_br L2
-            //            br L3
-            //         L2:
-            //            (end of buffer)
-            //
-            //     by removing the last branch, we have:
-            //
-            //         L1:
-            //            cond_br L2
-            //         L2:
-            //            (end of buffer)
-            //
-            //     we then fix up the records for the conditional branch to
-            //     have:
-            //
-            //         L1:
-            //           cond_br.inverted L3
-            //         L2:
-            //
-            //     In the original code, control flow reaches L2 when the
-            //     conditional branch's predicate is true, and L3 otherwise. In
-            //     the optimized code, the same is true.
-            //
-            //   - Post-invariant: all edits to latest_branches and
-            //     labels_at_tail are performed by `truncate_last_branch()`,
-            //     which maintains the invariants at each step.
-
-            if b.is_uncond() {
-                // Set any label equal to current branch's start as an alias of
-                // the branch's target, if the target is not the branch itself
-                // (i.e., an infinite loop).
-                //
-                // We cannot perform this aliasing if the target of this branch
-                // ultimately aliases back here; if so, we need to keep this
-                // branch, so break out of this loop entirely (and clear the
-                // latest-branches list below).
-                //
-                // Note that this check is what prevents cycles from forming in
-                // `self.label_aliases`. To see why, consider an arbitrary start
-                // state:
-                //
-                // label_aliases[L1] = L2, label_aliases[L2] = L3, ..., up to
-                // Ln, which is not aliased.
-                //
-                // We would create a cycle if we assigned label_aliases[Ln]
-                // = L1.  Note that the below assignment is the only write
-                // to label_aliases.
-                //
-                // By our other invariants, we have that Ln (`l` below)
-                // resolves to the offset `b.start`, because it is in the
-                // set `b.labels_at_this_branch`.
-                //
-                // If L1 were already aliased, through some arbitrarily deep
-                // chain, to Ln, then it must also resolve to this offset
-                // `b.start`.
-                //
-                // By checking the resolution of `L1` against this offset,
-                // and aborting this branch-simplification if they are
-                // equal, we prevent the below assignment from ever creating
-                // a cycle.
-                if self.resolve_label_offset(b.target) != b.start {
-                    let redirected = b.labels_at_this_branch.len();
-                    for &l in &b.labels_at_this_branch {
-                        trace!(
-                            " -> label at start of branch {:?} redirected to target {:?}",
-                            l,
-                            b.target
-                        );
-                        self.label_aliases[l.0 as usize] = b.target;
-                        // NOTE: we continue to ensure the invariant that labels
-                        // pointing to tail of buffer are in `labels_at_tail`
-                        // because we already ensured above that the last branch
-                        // cannot have a target of `cur_off`; so we never have
-                        // to put the label into `labels_at_tail` when moving it
-                        // here.
-                    }
-                    // Maintain invariant: all branches have been redirected
-                    // and are no longer pointing at the start of this branch.
-                    let mut_b = self.latest_branches.last_mut().unwrap();
-                    mut_b.labels_at_this_branch.clear();
-
-                    if redirected > 0 {
-                        trace!(" -> after label redirects, restarting loop");
-                        continue;
-                    }
-                } else {
-                    break;
-                }
-
-                let b = self.latest_branches.last().unwrap();
-
-                // Examine any immediately preceding branch.
-                if self.latest_branches.len() > 1 {
-                    let prev_b = &self.latest_branches[self.latest_branches.len() - 2];
-                    trace!(" -> more than one branch; prev_b = {:?}", prev_b);
-                    // This uncond is immediately after another uncond; we
-                    // should have already redirected labels to this uncond away
-                    // (but check to be sure); so we can truncate this uncond.
-                    if prev_b.is_uncond()
-                        && prev_b.end == b.start
-                        && b.labels_at_this_branch.is_empty()
-                    {
-                        trace!(" -> uncond follows another uncond; truncating");
-                        self.truncate_last_branch();
-                        continue;
-                    }
-
-                    // This uncond is immediately after a conditional, and the
-                    // conditional's target is the end of this uncond, and we've
-                    // already redirected labels to this uncond away; so we can
-                    // truncate this uncond, flip the sense of the conditional, and
-                    // set the conditional's target (in `latest_branches` and in
-                    // `fixup_records`) to the uncond's target.
-                    if prev_b.is_cond()
-                        && prev_b.end == b.start
-                        && self.resolve_label_offset(prev_b.target) == cur_off
-                    {
-                        trace!(" -> uncond follows a conditional, and conditional's target resolves to current offset");
-                        // Save the target of the uncond (this becomes the
-                        // target of the cond), and truncate the uncond.
-                        let target = b.target;
-                        let data = prev_b.inverted.clone().unwrap();
-                        self.truncate_last_branch();
-
-                        // Mutate the code and cond branch.
-                        let off_before_edit = self.cur_offset();
-                        let prev_b = self.latest_branches.last_mut().unwrap();
-                        let not_inverted = SmallVec::from(
-                            &self.data[(prev_b.start as usize)..(prev_b.end as usize)],
-                        );
-
-                        // Low-level edit: replaces bytes of branch with
-                        // inverted form. cur_off remains the same afterward, so
-                        // we do not need to modify label data structures.
-                        self.data.truncate(prev_b.start as usize);
-                        self.data.extend_from_slice(&data[..]);
-
-                        // Save the original code as the inversion of the
-                        // inverted branch, in case we later edit this branch
-                        // again.
-                        prev_b.inverted = Some(not_inverted);
-                        self.fixup_records[prev_b.fixup].label = target;
-                        trace!(" -> reassigning target of condbr to {:?}", target);
-                        prev_b.target = target;
-                        debug_assert_eq!(off_before_edit, self.cur_offset());
-                        continue;
-                    }
-                }
-            }
-
-            // If we couldn't do anything with the last branch, then break.
-            break;
-        }
-
-        self.purge_latest_branches();
-
-        trace!(
-            "leave optimize_branches:\n b = {:?}\n l = {:?}\n f = {:?}",
-            self.latest_branches,
-            self.labels_at_tail,
-            self.fixup_records
-        );
-    }
-
-    fn purge_latest_branches(&mut self) {
-        // All of our branch simplification rules work only if a branch ends at
-        // the tail of the buffer, with no following code; and branches are in
-        // order in latest_branches; so if the last entry ends prior to
-        // cur_offset, then clear all entries.
-        let cur_off = self.cur_offset();
-        if let Some(l) = self.latest_branches.last() {
-            if l.end < cur_off {
-                trace!("purge_latest_branches: removing branch {:?}", l);
-                self.latest_branches.clear();
-            }
-        }
-
-        // Post-invariant: no invariant requires any branch to appear in
-        // `latest_branches`; it is always optional. The list-clear above thus
-        // preserves all semantics.
-    }
-
-    /// Emit a constant at some point in the future, binding the given label to
-    /// its offset. The constant will be placed at most `max_distance` from the
-    /// current offset.
-    pub fn defer_constant(
-        &mut self,
-        label: MachLabel,
-        align: CodeOffset,
-        data: &[u8],
-        max_distance: CodeOffset,
-    ) {
-        trace!(
-            "defer_constant: eventually emit {} bytes aligned to {} at label {:?}",
-            data.len(),
-            align,
-            label
-        );
-        let deadline = self.cur_offset().saturating_add(max_distance);
-        self.island_worst_case_size += data.len() as CodeOffset;
-        self.island_worst_case_size =
-            (self.island_worst_case_size + I::LabelUse::ALIGN - 1) & !(I::LabelUse::ALIGN - 1);
-        self.pending_constants.push(MachLabelConstant {
-            label,
-            align,
-            data: SmallVec::from(data),
-        });
-        if deadline < self.island_deadline {
-            self.island_deadline = deadline;
-        }
-    }
-
-    /// Is an island needed within the next N bytes?
-    pub fn island_needed(&self, distance: CodeOffset) -> bool {
-        self.worst_case_end_of_island(distance) > self.island_deadline
-    }
-
-    /// Returns the maximal offset that islands can reach if `distance` more
-    /// bytes are appended.
-    ///
-    /// This is used to determine if veneers need insertions since jumps that
-    /// can't reach past this point must get a veneer of some form.
-    fn worst_case_end_of_island(&self, distance: CodeOffset) -> CodeOffset {
-        self.cur_offset()
-            .saturating_add(distance)
-            .saturating_add(self.island_worst_case_size)
-    }
-
-    /// Emit all pending constants and required pending veneers.
-    ///
-    /// Should only be called if `island_needed()` returns true, i.e., if we
-    /// actually reach a deadline. It's not necessarily a problem to do so
-    /// otherwise but it may result in unnecessary work during emission.
-    pub fn emit_island(&mut self, distance: CodeOffset) {
-        self.emit_island_maybe_forced(false, distance);
-    }
-
-    /// Same as `emit_island`, but an internal API with a `force_veneers`
-    /// argument to force all veneers to always get emitted for debugging.
-    fn emit_island_maybe_forced(&mut self, force_veneers: bool, distance: CodeOffset) {
-        // We're going to purge fixups, so no latest-branch editing can happen
-        // anymore.
-        self.latest_branches.clear();
-
-        // Reset internal calculations about islands since we're going to
-        // change the calculus as we apply fixups. The `forced_threshold` is
-        // used here to determine whether jumps to unknown labels will require
-        // a veneer or not.
-        let forced_threshold = self.worst_case_end_of_island(distance);
-        self.island_deadline = UNKNOWN_LABEL_OFFSET;
-        self.island_worst_case_size = 0;
-
-        // First flush out all constants so we have more labels in case fixups
-        // are applied against these labels.
-        for MachLabelConstant { label, align, data } in mem::take(&mut self.pending_constants) {
-            self.align_to(align);
-            self.bind_label(label);
-            self.put_data(&data[..]);
-        }
-
-        for fixup in mem::take(&mut self.fixup_records) {
-            trace!("emit_island: fixup {:?}", fixup);
-            let MachLabelFixup {
-                label,
-                offset,
-                kind,
-            } = fixup;
-            let label_offset = self.resolve_label_offset(label);
-            let start = offset as usize;
-            let end = (offset + kind.patch_size()) as usize;
-
-            if label_offset != UNKNOWN_LABEL_OFFSET {
-                // If the offset of the label for this fixup is known then
-                // we're going to do something here-and-now. We're either going
-                // to patch the original offset because it's an in-bounds jump,
-                // or we're going to generate a veneer, patch the fixup to jump
-                // to the veneer, and then keep going.
-                //
-                // If the label comes after the original fixup, then we should
-                // be guaranteed that the jump is in-bounds. Otherwise there's
-                // a bug somewhere because this method wasn't called soon
-                // enough. All forward-jumps are tracked and should get veneers
-                // before their deadline comes and they're unable to jump
-                // further.
-                //
-                // Otherwise if the label is before the fixup, then that's a
-                // backwards jump. If it's past the maximum negative range
-                // then we'll emit a veneer that to jump forward to which can
-                // then jump backwards.
-                let veneer_required = if label_offset >= offset {
-                    assert!((label_offset - offset) <= kind.max_pos_range());
-                    false
-                } else {
-                    (offset - label_offset) > kind.max_neg_range()
-                };
-                trace!(
-                    " -> label_offset = {}, known, required = {} (pos {} neg {})",
-                    label_offset,
-                    veneer_required,
-                    kind.max_pos_range(),
-                    kind.max_neg_range()
-                );
-
-                if (force_veneers && kind.supports_veneer()) || veneer_required {
-                    self.emit_veneer(label, offset, kind);
-                } else {
-                    let slice = &mut self.data[start..end];
-                    trace!("patching in-range!");
-                    kind.patch(slice, offset, label_offset);
-                }
-            } else {
-                // If the offset of this label is not known at this time then
-                // there's one of two possibilities:
-                //
-                // * First we may be about to exceed the maximum jump range of
-                //   this fixup. In that case a veneer is inserted to buy some
-                //   more budget for the forward-jump. It's guaranteed that the
-                //   label will eventually come after where we're at, so we know
-                //   that the forward jump is necessary.
-                //
-                // * Otherwise we're still within range of the forward jump but
-                //   the precise target isn't known yet. In that case we
-                //   enqueue the fixup to get processed later.
-                if forced_threshold - offset > kind.max_pos_range() {
-                    self.emit_veneer(label, offset, kind);
-                } else {
-                    self.use_label_at_offset(offset, label, kind);
-                }
-            }
-        }
-    }
-
-    /// Emits a "veneer" the `kind` code at `offset` to jump to `label`.
-    ///
-    /// This will generate extra machine code, using `kind`, to get a
-    /// larger-jump-kind than `kind` allows. The code at `offset` is then
-    /// patched to jump to our new code, and then the new code is enqueued for
-    /// a fixup to get processed at some later time.
-    fn emit_veneer(&mut self, label: MachLabel, offset: CodeOffset, kind: I::LabelUse) {
-        // If this `kind` doesn't support a veneer then that's a bug in the
-        // backend because we need to implement support for such a veneer.
-        assert!(
-            kind.supports_veneer(),
-            "jump beyond the range of {:?} but a veneer isn't supported",
-            kind,
-        );
-
-        // Allocate space for a veneer in the island.
-        self.align_to(I::LabelUse::ALIGN);
-        let veneer_offset = self.cur_offset();
-        trace!("making a veneer at {}", veneer_offset);
-        let start = offset as usize;
-        let end = (offset + kind.patch_size()) as usize;
-        let slice = &mut self.data[start..end];
-        // Patch the original label use to refer to the veneer.
-        trace!(
-            "patching original at offset {} to veneer offset {}",
-            offset,
-            veneer_offset
-        );
-        kind.patch(slice, offset, veneer_offset);
-        // Generate the veneer.
-        let veneer_slice = self.get_appended_space(kind.veneer_size() as usize);
-        let (veneer_fixup_off, veneer_label_use) =
-            kind.generate_veneer(veneer_slice, veneer_offset);
-        trace!(
-            "generated veneer; fixup offset {}, label_use {:?}",
-            veneer_fixup_off,
-            veneer_label_use
-        );
-        // Register a new use of `label` with our new veneer fixup and offset.
-        // This'll recalculate deadlines accordingly and enqueue this fixup to
-        // get processed at some later time.
-        self.use_label_at_offset(veneer_fixup_off, label, veneer_label_use);
-    }
-
-    fn finish_emission_maybe_forcing_veneers(&mut self, force_veneers: bool) {
-        while !self.pending_constants.is_empty() || !self.fixup_records.is_empty() {
-            // `emit_island()` will emit any pending veneers and constants, and
-            // as a side-effect, will also take care of any fixups with resolved
-            // labels eagerly.
-            self.emit_island_maybe_forced(force_veneers, u32::MAX);
-        }
-
-        // Ensure that all labels have been fixed up after the last island is emitted. This is a
-        // full (release-mode) assert because an unresolved label means the emitted code is
-        // incorrect.
-        assert!(self.fixup_records.is_empty());
-    }
-
-    /// Finish any deferred emissions and/or fixups.
-    pub fn finish(mut self) -> MachBufferFinalized {
-        let _tt = timing::vcode_emit_finish();
-
-        self.finish_emission_maybe_forcing_veneers(false);
-
-        let mut srclocs = self.srclocs;
-        srclocs.sort_by_key(|entry| entry.start);
-
-        MachBufferFinalized {
-            data: self.data,
-            relocs: self.relocs,
-            traps: self.traps,
-            call_sites: self.call_sites,
-            srclocs,
-            stack_maps: self.stack_maps,
-            unwind_info: self.unwind_info,
-        }
-    }
-
-    /// Add an external relocation at the current offset.
-    pub fn add_reloc(
-        &mut self,
-        srcloc: SourceLoc,
-        kind: Reloc,
-        name: &ExternalName,
-        addend: Addend,
-    ) {
-        let name = name.clone();
-        // FIXME(#3277): This should use `I::LabelUse::from_reloc` to optionally
-        // generate a label-use statement to track whether an island is possibly
-        // needed to escape this function to actually get to the external name.
-        // This is most likely to come up on AArch64 where calls between
-        // functions use a 26-bit signed offset which gives +/- 64MB. This means
-        // that if a function is 128MB in size and there's a call in the middle
-        // it's impossible to reach the actual target. Also, while it's
-        // technically possible to jump to the start of a function and then jump
-        // further, island insertion below always inserts islands after
-        // previously appended code so for Cranelift's own implementation this
-        // is also a problem for 64MB functions on AArch64 which start with a
-        // call instruction, those won't be able to escape.
-        //
-        // Ideally what needs to happen here is that a `LabelUse` is
-        // transparently generated (or call-sites of this function are audited
-        // to generate a `LabelUse` instead) and tracked internally. The actual
-        // relocation would then change over time if and when a veneer is
-        // inserted, where the relocation here would be patched by this
-        // `MachBuffer` to jump to the veneer. The problem, though, is that all
-        // this still needs to end up, in the case of a singular function,
-        // generating a final relocation pointing either to this particular
-        // relocation or to the veneer inserted. Additionally
-        // `MachBuffer` needs the concept of a label which will never be
-        // resolved, so `emit_island` doesn't trip over not actually ever
-        // knowning what some labels are. Currently the loop in
-        // `finish_emission_maybe_forcing_veneers` would otherwise infinitely
-        // loop.
-        //
-        // For now this means that because relocs aren't tracked at all that
-        // AArch64 functions have a rough size limits of 64MB. For now that's
-        // somewhat reasonable and the failure mode is a panic in `MachBuffer`
-        // when a relocation can't otherwise be resolved later, so it shouldn't
-        // actually result in any memory unsafety or anything like that.
-        self.relocs.push(MachReloc {
-            offset: self.data.len() as CodeOffset,
-            srcloc,
-            kind,
-            name,
-            addend,
-        });
-    }
-
-    /// Add a trap record at the current offset.
-    pub fn add_trap(&mut self, srcloc: SourceLoc, code: TrapCode) {
-        self.traps.push(MachTrap {
-            offset: self.data.len() as CodeOffset,
-            srcloc,
-            code,
-        });
-    }
-
-    /// Add a call-site record at the current offset.
-    pub fn add_call_site(&mut self, srcloc: SourceLoc, opcode: Opcode) {
-        debug_assert!(
-            opcode.is_call(),
-            "adding call site info for a non-call instruction."
-        );
-        self.call_sites.push(MachCallSite {
-            ret_addr: self.data.len() as CodeOffset,
-            srcloc,
-            opcode,
-        });
-    }
-
-    /// Add an unwind record at the current offset.
-    pub fn add_unwind(&mut self, unwind: UnwindInst) {
-        self.unwind_info.push((self.cur_offset(), unwind));
-    }
-
-    /// Set the `SourceLoc` for code from this offset until the offset at the
-    /// next call to `end_srcloc()`.
-    pub fn start_srcloc(&mut self, loc: SourceLoc) {
-        self.cur_srcloc = Some((self.cur_offset(), loc));
-    }
-
-    /// Mark the end of the `SourceLoc` segment started at the last
-    /// `start_srcloc()` call.
-    pub fn end_srcloc(&mut self) {
-        let (start, loc) = self
-            .cur_srcloc
-            .take()
-            .expect("end_srcloc() called without start_srcloc()");
-        let end = self.cur_offset();
-        // Skip zero-length extends.
-        debug_assert!(end >= start);
-        if end > start {
-            self.srclocs.push(MachSrcLoc { start, end, loc });
-        }
-    }
-
-    /// Add stack map metadata for this program point: a set of stack offsets
-    /// (from SP upward) that contain live references.
-    ///
-    /// The `offset_to_fp` value is the offset from the nominal SP (at which the `stack_offsets`
-    /// are based) and the FP value. By subtracting `offset_to_fp` from each `stack_offsets`
-    /// element, one can obtain live-reference offsets from FP instead.
-    pub fn add_stack_map(&mut self, extent: StackMapExtent, stack_map: StackMap) {
-        let (start, end) = match extent {
-            StackMapExtent::UpcomingBytes(insn_len) => {
-                let start_offset = self.cur_offset();
-                (start_offset, start_offset + insn_len)
-            }
-            StackMapExtent::StartedAtOffset(start_offset) => {
-                let end_offset = self.cur_offset();
-                debug_assert!(end_offset >= start_offset);
-                (start_offset, end_offset)
-            }
-        };
-        self.stack_maps.push(MachStackMap {
-            offset: start,
-            offset_end: end,
-            stack_map,
-        });
-    }
-}
-
-impl MachBufferFinalized {
-    /// Get a list of source location mapping tuples in sorted-by-start-offset order.
-    pub fn get_srclocs_sorted(&self) -> &[MachSrcLoc] {
-        &self.srclocs[..]
-    }
-
-    /// Get the total required size for the code.
-    pub fn total_size(&self) -> CodeOffset {
-        self.data.len() as CodeOffset
-    }
-
-    /// Return the code in this mach buffer as a hex string for testing purposes.
-    pub fn stringify_code_bytes(&self) -> String {
-        // This is pretty lame, but whatever ..
-        use std::fmt::Write;
-        let mut s = String::with_capacity(self.data.len() * 2);
-        for b in &self.data {
-            write!(&mut s, "{:02X}", b).unwrap();
-        }
-        s
-    }
-
-    /// Get the code bytes.
-    pub fn data(&self) -> &[u8] {
-        // N.B.: we emit every section into the .text section as far as
-        // the `CodeSink` is concerned; we do not bother to segregate
-        // the contents into the actual program text, the jumptable and the
-        // rodata (constant pool). This allows us to generate code assuming
-        // that these will not be relocated relative to each other, and avoids
-        // having to designate each section as belonging in one of the three
-        // fixed categories defined by `CodeSink`. If this becomes a problem
-        // later (e.g. because of memory permissions or similar), we can
-        // add this designation and segregate the output; take care, however,
-        // to add the appropriate relocations in this case.
-
-        &self.data[..]
-    }
-
-    /// Get the list of external relocations for this code.
-    pub fn relocs(&self) -> &[MachReloc] {
-        &self.relocs[..]
-    }
-
-    /// Get the list of trap records for this code.
-    pub fn traps(&self) -> &[MachTrap] {
-        &self.traps[..]
-    }
-
-    /// Get the stack map metadata for this code.
-    pub fn stack_maps(&self) -> &[MachStackMap] {
-        &self.stack_maps[..]
-    }
-
-    /// Get the list of call sites for this code.
-    pub fn call_sites(&self) -> &[MachCallSite] {
-        &self.call_sites[..]
-    }
-}
-
-/// A constant that is deferred to the next constant-pool opportunity.
-struct MachLabelConstant {
-    /// This label will refer to the constant's offset.
-    label: MachLabel,
-    /// Required alignment.
-    align: CodeOffset,
-    /// This data will be emitted when able.
-    data: SmallVec<[u8; 16]>,
-}
-
-/// A fixup to perform on the buffer once code is emitted. Fixups always refer
-/// to labels and patch the code based on label offsets. Hence, they are like
-/// relocations, but internal to one buffer.
-#[derive(Debug)]
-struct MachLabelFixup<I: VCodeInst> {
-    /// The label whose offset controls this fixup.
-    label: MachLabel,
-    /// The offset to fix up / patch to refer to this label.
-    offset: CodeOffset,
-    /// The kind of fixup. This is architecture-specific; each architecture may have,
-    /// e.g., several types of branch instructions, each with differently-sized
-    /// offset fields and different places within the instruction to place the
-    /// bits.
-    kind: I::LabelUse,
-}
-
-/// A relocation resulting from a compilation.
-#[derive(Clone, Debug)]
-pub struct MachReloc {
-    /// The offset at which the relocation applies, *relative to the
-    /// containing section*.
-    pub offset: CodeOffset,
-    /// The original source location.
-    pub srcloc: SourceLoc,
-    /// The kind of relocation.
-    pub kind: Reloc,
-    /// The external symbol / name to which this relocation refers.
-    pub name: ExternalName,
-    /// The addend to add to the symbol value.
-    pub addend: i64,
-}
-
-/// A trap record resulting from a compilation.
-#[derive(Clone, Debug)]
-pub struct MachTrap {
-    /// The offset at which the trap instruction occurs, *relative to the
-    /// containing section*.
-    pub offset: CodeOffset,
-    /// The original source location.
-    pub srcloc: SourceLoc,
-    /// The trap code.
-    pub code: TrapCode,
-}
-
-/// A call site record resulting from a compilation.
-#[derive(Clone, Debug)]
-pub struct MachCallSite {
-    /// The offset of the call's return address, *relative to the containing section*.
-    pub ret_addr: CodeOffset,
-    /// The original source location.
-    pub srcloc: SourceLoc,
-    /// The call's opcode.
-    pub opcode: Opcode,
-}
-
-/// A source-location mapping resulting from a compilation.
-#[derive(Clone, Debug)]
-pub struct MachSrcLoc {
-    /// The start of the region of code corresponding to a source location.
-    /// This is relative to the start of the function, not to the start of the
-    /// section.
-    pub start: CodeOffset,
-    /// The end of the region of code corresponding to a source location.
-    /// This is relative to the start of the section, not to the start of the
-    /// section.
-    pub end: CodeOffset,
-    /// The source location.
-    pub loc: SourceLoc,
-}
-
-/// Record of stack map metadata: stack offsets containing references.
-#[derive(Clone, Debug)]
-pub struct MachStackMap {
-    /// The code offset at which this stack map applies.
-    pub offset: CodeOffset,
-    /// The code offset just past the "end" of the instruction: that is, the
-    /// offset of the first byte of the following instruction, or equivalently,
-    /// the start offset plus the instruction length.
-    pub offset_end: CodeOffset,
-    /// The stack map itself.
-    pub stack_map: StackMap,
-}
-
-/// Record of branch instruction in the buffer, to facilitate editing.
-#[derive(Clone, Debug)]
-struct MachBranch {
-    start: CodeOffset,
-    end: CodeOffset,
-    target: MachLabel,
-    fixup: usize,
-    inverted: Option<SmallVec<[u8; 8]>>,
-    /// All labels pointing to the start of this branch. For correctness, this
-    /// *must* be complete (i.e., must contain all labels whose resolved offsets
-    /// are at the start of this branch): we rely on being able to redirect all
-    /// labels that could jump to this branch before removing it, if it is
-    /// otherwise unreachable.
-    labels_at_this_branch: SmallVec<[MachLabel; 4]>,
-}
-
-impl MachBranch {
-    fn is_cond(&self) -> bool {
-        self.inverted.is_some()
-    }
-    fn is_uncond(&self) -> bool {
-        self.inverted.is_none()
-    }
-}
-
-/// Implementation of the `TextSectionBuilder` trait backed by `MachBuffer`.
-///
-/// Note that `MachBuffer` was primarily written for intra-function references
-/// of jumps between basic blocks, but it's also quite usable for entire text
-/// sections and resolving references between functions themselves. This
-/// builder interprets "blocks" as labeled functions for the purposes of
-/// resolving labels internally in the buffer.
-pub struct MachTextSectionBuilder<I: VCodeInst> {
-    buf: MachBuffer<I>,
-    next_func: u32,
-    force_veneers: bool,
-}
-
-impl<I: VCodeInst> MachTextSectionBuilder<I> {
-    pub fn new(num_funcs: u32) -> MachTextSectionBuilder<I> {
-        let mut buf = MachBuffer::new();
-        buf.reserve_labels_for_blocks(num_funcs);
-        MachTextSectionBuilder {
-            buf,
-            next_func: 0,
-            force_veneers: false,
-        }
-    }
-}
-
-impl<I: VCodeInst> TextSectionBuilder for MachTextSectionBuilder<I> {
-    fn append(&mut self, named: bool, func: &[u8], align: u32) -> u64 {
-        // Conditionally emit an island if it's necessary to resolve jumps
-        // between functions which are too far away.
-        let size = func.len() as u32;
-        if self.force_veneers || self.buf.island_needed(size) {
-            self.buf.emit_island_maybe_forced(self.force_veneers, size);
-        }
-
-        self.buf.align_to(align);
-        let pos = self.buf.cur_offset();
-        if named {
-            self.buf.bind_label(MachLabel::from_block(self.next_func));
-            self.next_func += 1;
-        }
-        self.buf.put_data(func);
-        u64::from(pos)
-    }
-
-    fn resolve_reloc(&mut self, offset: u64, reloc: Reloc, addend: Addend, target: u32) -> bool {
-        let label = MachLabel::from_block(target);
-        let offset = u32::try_from(offset).unwrap();
-        match I::LabelUse::from_reloc(reloc, addend) {
-            Some(label_use) => {
-                self.buf.use_label_at_offset(offset, label, label_use);
-                true
-            }
-            None => false,
-        }
-    }
-
-    fn force_veneers(&mut self) {
-        self.force_veneers = true;
-    }
-
-    fn finish(&mut self) -> Vec<u8> {
-        // Double-check all functions were pushed.
-        assert_eq!(self.next_func, self.buf.label_offsets.len() as u32);
-
-        // Finish up any veneers, if necessary.
-        self.buf
-            .finish_emission_maybe_forcing_veneers(self.force_veneers);
-
-        // We don't need the data any more, so return it to the caller.
-        mem::take(&mut self.buf.data).into_vec()
-    }
-}
-
-// We use an actual instruction definition to do tests, so we depend on the `arm64` feature here.
-#[cfg(all(test, feature = "arm64"))]
-mod test {
-    use super::*;
-    use crate::isa::aarch64::inst::xreg;
-    use crate::isa::aarch64::inst::{BranchTarget, CondBrKind, EmitInfo, Inst};
-    use crate::machinst::MachInstEmit;
-    use crate::settings;
-    use std::default::Default;
-    use std::vec::Vec;
-
-    fn label(n: u32) -> MachLabel {
-        MachLabel::from_block(n)
-    }
-    fn target(n: u32) -> BranchTarget {
-        BranchTarget::Label(label(n))
-    }
-
-    #[test]
-    fn test_elide_jump_to_next() {
-        let info = EmitInfo::new(settings::Flags::new(settings::builder()));
-        let mut buf = MachBuffer::new();
-        let mut state = Default::default();
-
-        buf.reserve_labels_for_blocks(2);
-        buf.bind_label(label(0));
-        let inst = Inst::Jump { dest: target(1) };
-        inst.emit(&mut buf, &info, &mut state);
-        buf.bind_label(label(1));
-        let buf = buf.finish();
-        assert_eq!(0, buf.total_size());
-    }
-
-    #[test]
-    fn test_elide_trivial_jump_blocks() {
-        let info = EmitInfo::new(settings::Flags::new(settings::builder()));
-        let mut buf = MachBuffer::new();
-        let mut state = Default::default();
-
-        buf.reserve_labels_for_blocks(4);
-
-        buf.bind_label(label(0));
-        let inst = Inst::CondBr {
-            kind: CondBrKind::NotZero(xreg(0)),
-            taken: target(1),
-            not_taken: target(2),
-        };
-        inst.emit(&mut buf, &info, &mut state);
-
-        buf.bind_label(label(1));
-        let inst = Inst::Jump { dest: target(3) };
-        inst.emit(&mut buf, &info, &mut state);
-
-        buf.bind_label(label(2));
-        let inst = Inst::Jump { dest: target(3) };
-        inst.emit(&mut buf, &info, &mut state);
-
-        buf.bind_label(label(3));
-
-        let buf = buf.finish();
-        assert_eq!(0, buf.total_size());
-    }
-
-    #[test]
-    fn test_flip_cond() {
-        let info = EmitInfo::new(settings::Flags::new(settings::builder()));
-        let mut buf = MachBuffer::new();
-        let mut state = Default::default();
-
-        buf.reserve_labels_for_blocks(4);
-
-        buf.bind_label(label(0));
-        let inst = Inst::CondBr {
-            kind: CondBrKind::NotZero(xreg(0)),
-            taken: target(1),
-            not_taken: target(2),
-        };
-        inst.emit(&mut buf, &info, &mut state);
-
-        buf.bind_label(label(1));
-        let inst = Inst::Udf {
-            trap_code: TrapCode::Interrupt,
-        };
-        inst.emit(&mut buf, &info, &mut state);
-
-        buf.bind_label(label(2));
-        let inst = Inst::Nop4;
-        inst.emit(&mut buf, &info, &mut state);
-
-        buf.bind_label(label(3));
-
-        let buf = buf.finish();
-
-        let mut buf2 = MachBuffer::new();
-        let mut state = Default::default();
-        let inst = Inst::TrapIf {
-            kind: CondBrKind::NotZero(xreg(0)),
-            trap_code: TrapCode::Interrupt,
-        };
-        inst.emit(&mut buf2, &info, &mut state);
-        let inst = Inst::Nop4;
-        inst.emit(&mut buf2, &info, &mut state);
-
-        let buf2 = buf2.finish();
-
-        assert_eq!(buf.data, buf2.data);
-    }
-
-    #[test]
-    fn test_island() {
-        let info = EmitInfo::new(settings::Flags::new(settings::builder()));
-        let mut buf = MachBuffer::new();
-        let mut state = Default::default();
-
-        buf.reserve_labels_for_blocks(4);
-
-        buf.bind_label(label(0));
-        let inst = Inst::CondBr {
-            kind: CondBrKind::NotZero(xreg(0)),
-            taken: target(2),
-            not_taken: target(3),
-        };
-        inst.emit(&mut buf, &info, &mut state);
-
-        buf.bind_label(label(1));
-        while buf.cur_offset() < 2000000 {
-            if buf.island_needed(0) {
-                buf.emit_island(0);
-            }
-            let inst = Inst::Nop4;
-            inst.emit(&mut buf, &info, &mut state);
-        }
-
-        buf.bind_label(label(2));
-        let inst = Inst::Nop4;
-        inst.emit(&mut buf, &info, &mut state);
-
-        buf.bind_label(label(3));
-        let inst = Inst::Nop4;
-        inst.emit(&mut buf, &info, &mut state);
-
-        let buf = buf.finish();
-
-        assert_eq!(2000000 + 8, buf.total_size());
-
-        let mut buf2 = MachBuffer::new();
-        let mut state = Default::default();
-        let inst = Inst::CondBr {
-            kind: CondBrKind::NotZero(xreg(0)),
-
-            // This conditionally taken branch has a 19-bit constant, shifted
-            // to the left by two, giving us a 21-bit range in total. Half of
-            // this range positive so the we should be around 1 << 20 bytes
-            // away for our jump target.
-            //
-            // There are two pending fixups by the time we reach this point,
-            // one for this 19-bit jump and one for the unconditional 26-bit
-            // jump below. A 19-bit veneer is 4 bytes large and the 26-bit
-            // veneer is 20 bytes large, which means that pessimistically
-            // assuming we'll need two veneers we need 24 bytes of extra
-            // space, meaning that the actual island should come 24-bytes
-            // before the deadline.
-            taken: BranchTarget::ResolvedOffset((1 << 20) - 4 - 20),
-
-            // This branch is in-range so no veneers should be needed, it should
-            // go directly to the target.
-            not_taken: BranchTarget::ResolvedOffset(2000000 + 4 - 4),
-        };
-        inst.emit(&mut buf2, &info, &mut state);
-
-        let buf2 = buf2.finish();
-
-        assert_eq!(&buf.data[0..8], &buf2.data[..]);
-    }
-
-    #[test]
-    fn test_island_backward() {
-        let info = EmitInfo::new(settings::Flags::new(settings::builder()));
-        let mut buf = MachBuffer::new();
-        let mut state = Default::default();
-
-        buf.reserve_labels_for_blocks(4);
-
-        buf.bind_label(label(0));
-        let inst = Inst::Nop4;
-        inst.emit(&mut buf, &info, &mut state);
-
-        buf.bind_label(label(1));
-        let inst = Inst::Nop4;
-        inst.emit(&mut buf, &info, &mut state);
-
-        buf.bind_label(label(2));
-        while buf.cur_offset() < 2000000 {
-            let inst = Inst::Nop4;
-            inst.emit(&mut buf, &info, &mut state);
-        }
-
-        buf.bind_label(label(3));
-        let inst = Inst::CondBr {
-            kind: CondBrKind::NotZero(xreg(0)),
-            taken: target(0),
-            not_taken: target(1),
-        };
-        inst.emit(&mut buf, &info, &mut state);
-
-        let buf = buf.finish();
-
-        assert_eq!(2000000 + 12, buf.total_size());
-
-        let mut buf2 = MachBuffer::new();
-        let mut state = Default::default();
-        let inst = Inst::CondBr {
-            kind: CondBrKind::NotZero(xreg(0)),
-            taken: BranchTarget::ResolvedOffset(8),
-            not_taken: BranchTarget::ResolvedOffset(4 - (2000000 + 4)),
-        };
-        inst.emit(&mut buf2, &info, &mut state);
-        let inst = Inst::Jump {
-            dest: BranchTarget::ResolvedOffset(-(2000000 + 8)),
-        };
-        inst.emit(&mut buf2, &info, &mut state);
-
-        let buf2 = buf2.finish();
-
-        assert_eq!(&buf.data[2000000..], &buf2.data[..]);
-    }
-
-    #[test]
-    fn test_multiple_redirect() {
-        // label0:
-        //   cbz x0, label1
-        //   b label2
-        // label1:
-        //   b label3
-        // label2:
-        //   nop
-        //   nop
-        //   b label0
-        // label3:
-        //   b label4
-        // label4:
-        //   b label5
-        // label5:
-        //   b label7
-        // label6:
-        //   nop
-        // label7:
-        //   ret
-        //
-        // -- should become:
-        //
-        // label0:
-        //   cbz x0, label7
-        // label2:
-        //   nop
-        //   nop
-        //   b label0
-        // label6:
-        //   nop
-        // label7:
-        //   ret
-
-        let info = EmitInfo::new(settings::Flags::new(settings::builder()));
-        let mut buf = MachBuffer::new();
-        let mut state = Default::default();
-
-        buf.reserve_labels_for_blocks(8);
-
-        buf.bind_label(label(0));
-        let inst = Inst::CondBr {
-            kind: CondBrKind::Zero(xreg(0)),
-            taken: target(1),
-            not_taken: target(2),
-        };
-        inst.emit(&mut buf, &info, &mut state);
-
-        buf.bind_label(label(1));
-        let inst = Inst::Jump { dest: target(3) };
-        inst.emit(&mut buf, &info, &mut state);
-
-        buf.bind_label(label(2));
-        let inst = Inst::Nop4;
-        inst.emit(&mut buf, &info, &mut state);
-        inst.emit(&mut buf, &info, &mut state);
-        let inst = Inst::Jump { dest: target(0) };
-        inst.emit(&mut buf, &info, &mut state);
-
-        buf.bind_label(label(3));
-        let inst = Inst::Jump { dest: target(4) };
-        inst.emit(&mut buf, &info, &mut state);
-
-        buf.bind_label(label(4));
-        let inst = Inst::Jump { dest: target(5) };
-        inst.emit(&mut buf, &info, &mut state);
-
-        buf.bind_label(label(5));
-        let inst = Inst::Jump { dest: target(7) };
-        inst.emit(&mut buf, &info, &mut state);
-
-        buf.bind_label(label(6));
-        let inst = Inst::Nop4;
-        inst.emit(&mut buf, &info, &mut state);
-
-        buf.bind_label(label(7));
-        let inst = Inst::Ret;
-        inst.emit(&mut buf, &info, &mut state);
-
-        let buf = buf.finish();
-
-        let golden_data = vec![
-            0xa0, 0x00, 0x00, 0xb4, // cbz x0, 0x14
-            0x1f, 0x20, 0x03, 0xd5, // nop
-            0x1f, 0x20, 0x03, 0xd5, // nop
-            0xfd, 0xff, 0xff, 0x17, // b 0
-            0x1f, 0x20, 0x03, 0xd5, // nop
-            0xc0, 0x03, 0x5f, 0xd6, // ret
-        ];
-
-        assert_eq!(&golden_data[..], &buf.data[..]);
-    }
-
-    #[test]
-    fn test_handle_branch_cycle() {
-        // label0:
-        //   b label1
-        // label1:
-        //   b label2
-        // label2:
-        //   b label3
-        // label3:
-        //   b label4
-        // label4:
-        //   b label1  // note: not label0 (to make it interesting).
-        //
-        // -- should become:
-        //
-        // label0, label1, ..., label4:
-        //   b label0
-        let info = EmitInfo::new(settings::Flags::new(settings::builder()));
-        let mut buf = MachBuffer::new();
-        let mut state = Default::default();
-
-        buf.reserve_labels_for_blocks(5);
-
-        buf.bind_label(label(0));
-        let inst = Inst::Jump { dest: target(1) };
-        inst.emit(&mut buf, &info, &mut state);
-
-        buf.bind_label(label(1));
-        let inst = Inst::Jump { dest: target(2) };
-        inst.emit(&mut buf, &info, &mut state);
-
-        buf.bind_label(label(2));
-        let inst = Inst::Jump { dest: target(3) };
-        inst.emit(&mut buf, &info, &mut state);
-
-        buf.bind_label(label(3));
-        let inst = Inst::Jump { dest: target(4) };
-        inst.emit(&mut buf, &info, &mut state);
-
-        buf.bind_label(label(4));
-        let inst = Inst::Jump { dest: target(1) };
-        inst.emit(&mut buf, &info, &mut state);
-
-        let buf = buf.finish();
-
-        let golden_data = vec![
-            0x00, 0x00, 0x00, 0x14, // b 0
-        ];
-
-        assert_eq!(&golden_data[..], &buf.data[..]);
-    }
-
-    #[test]
-    fn metadata_records() {
-        let mut buf = MachBuffer::<Inst>::new();
-
-        buf.reserve_labels_for_blocks(1);
-
-        buf.bind_label(label(0));
-        buf.put1(1);
-        buf.add_trap(SourceLoc::default(), TrapCode::HeapOutOfBounds);
-        buf.put1(2);
-        buf.add_trap(SourceLoc::default(), TrapCode::IntegerOverflow);
-        buf.add_trap(SourceLoc::default(), TrapCode::IntegerDivisionByZero);
-        buf.add_call_site(SourceLoc::default(), Opcode::Call);
-        buf.add_reloc(
-            SourceLoc::default(),
-            Reloc::Abs4,
-            &ExternalName::user(0, 0),
-            0,
-        );
-        buf.put1(3);
-        buf.add_reloc(
-            SourceLoc::default(),
-            Reloc::Abs8,
-            &ExternalName::user(1, 1),
-            1,
-        );
-        buf.put1(4);
-
-        let buf = buf.finish();
-
-        assert_eq!(buf.data(), &[1, 2, 3, 4]);
-        assert_eq!(
-            buf.traps()
-                .iter()
-                .map(|trap| (trap.offset, trap.code))
-                .collect::<Vec<_>>(),
-            vec![
-                (1, TrapCode::HeapOutOfBounds),
-                (2, TrapCode::IntegerOverflow),
-                (2, TrapCode::IntegerDivisionByZero)
-            ]
-        );
-        assert_eq!(
-            buf.call_sites()
-                .iter()
-                .map(|call_site| (call_site.ret_addr, call_site.opcode))
-                .collect::<Vec<_>>(),
-            vec![(2, Opcode::Call)]
-        );
-        assert_eq!(
-            buf.relocs()
-                .iter()
-                .map(|reloc| (reloc.offset, reloc.kind))
-                .collect::<Vec<_>>(),
-            vec![(2, Reloc::Abs4), (3, Reloc::Abs8)]
-        );
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/compile.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/compile.rs
deleted file mode 100644
index 67593d940..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/compile.rs
+++ /dev/null
@@ -1,114 +0,0 @@
-//! Compilation backend pipeline: optimized IR to VCode / binemit.
-
-use crate::ir::Function;
-use crate::isa::TargetIsa;
-use crate::log::DeferredDisplay;
-use crate::machinst::*;
-use crate::settings;
-use crate::timing;
-
-use regalloc::{allocate_registers_with_opts, Algorithm, Options, PrettyPrint};
-
-/// Compile the given function down to VCode with allocated registers, ready
-/// for binary emission.
-pub fn compile<B: LowerBackend + TargetIsa>(
-    f: &Function,
-    b: &B,
-    abi: Box<dyn ABICallee<I = B::MInst>>,
-    reg_universe: &RealRegUniverse,
-    emit_info: <B::MInst as MachInstEmit>::Info,
-) -> CodegenResult<VCode<B::MInst>>
-where
-    B::MInst: PrettyPrint,
-{
-    // Compute lowered block order.
-    let block_order = BlockLoweringOrder::new(f);
-    // Build the lowering context.
-    let lower = Lower::new(f, abi, emit_info, block_order)?;
-    // Lower the IR.
-    let (mut vcode, stack_map_request_info) = {
-        let _tt = timing::vcode_lower();
-        lower.lower(b)?
-    };
-
-    // Creating the vcode string representation may be costly for large functions, so defer its
-    // rendering.
-    log::trace!(
-        "vcode from lowering: \n{}",
-        DeferredDisplay::new(|| vcode.show_rru(Some(reg_universe)))
-    );
-
-    // Perform register allocation.
-    let (run_checker, algorithm) = match vcode.flags().regalloc() {
-        settings::Regalloc::Backtracking => (false, Algorithm::Backtracking(Default::default())),
-        settings::Regalloc::BacktrackingChecked => {
-            (true, Algorithm::Backtracking(Default::default()))
-        }
-        settings::Regalloc::ExperimentalLinearScan => {
-            (false, Algorithm::LinearScan(Default::default()))
-        }
-        settings::Regalloc::ExperimentalLinearScanChecked => {
-            (true, Algorithm::LinearScan(Default::default()))
-        }
-    };
-
-    #[cfg(feature = "regalloc-snapshot")]
-    {
-        use std::fs;
-        use std::path::Path;
-        if let Some(path) = std::env::var("SERIALIZE_REGALLOC").ok() {
-            let snapshot = regalloc::IRSnapshot::from_function(&vcode, reg_universe);
-            let serialized = bincode::serialize(&snapshot).expect("couldn't serialize snapshot");
-
-            let file_path = Path::new(&path).join(Path::new(&format!("ir{}.bin", f.name)));
-            fs::write(file_path, &serialized).expect("couldn't write IR snapshot file");
-        }
-    }
-
-    // If either there are no reference-typed values, or else there are
-    // but there are no safepoints at which we need to know about them,
-    // then we don't need stack maps.
-    let sri = if stack_map_request_info.reftyped_vregs.len() > 0
-        && stack_map_request_info.safepoint_insns.len() > 0
-    {
-        Some(&stack_map_request_info)
-    } else {
-        None
-    };
-
-    let result = {
-        let _tt = timing::regalloc();
-        allocate_registers_with_opts(
-            &mut vcode,
-            reg_universe,
-            sri,
-            Options {
-                run_checker,
-                algorithm,
-            },
-        )
-        .map_err(|err| {
-            log::error!(
-                "Register allocation error for vcode\n{}\nError: {:?}",
-                vcode.show_rru(Some(reg_universe)),
-                err
-            );
-            err
-        })
-        .expect("register allocation")
-    };
-
-    // Reorder vcode into final order and copy out final instruction sequence
-    // all at once. This also inserts prologues/epilogues.
-    {
-        let _tt = timing::vcode_post_ra();
-        vcode.replace_insns_from_regalloc(result);
-    }
-
-    log::trace!(
-        "vcode after regalloc: final version:\n{}",
-        DeferredDisplay::new(|| vcode.show_rru(Some(reg_universe)))
-    );
-
-    Ok(vcode)
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/debug.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/debug.rs
deleted file mode 100644
index e2eafe50b..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/debug.rs
+++ /dev/null
@@ -1,525 +0,0 @@
-//! Debug info analysis: computes value-label ranges from value-label markers in
-//! generated VCode.
-//!
-//! We "reverse-engineer" debug info like this because it is far more reliable
-//! than generating it while emitting code and keeping it in sync.
-//!
-//! This works by (i) observing "value-label marker" instructions, which are
-//! semantically just an assignment from a register to a "value label" (which
-//! one can think of as another register; they represent, e.g., Wasm locals) at
-//! a certain point in the code, and (ii) observing loads and stores to the
-//! stack and register moves.
-//!
-//! We track, at every program point, the correspondence between each value
-//! label and *all* locations in which it resides. E.g., if it is stored to the
-//! stack, we remember that it is in both a register and the stack slot; but if
-//! the register is later overwritten, then we have it just in the stack slot.
-//! This allows us to avoid false-positives observing loads/stores that we think
-//! are spillslots but really aren't.
-//!
-//! We do a standard forward dataflow analysis to compute this info.
-
-use crate::ir::ValueLabel;
-use crate::machinst::*;
-use crate::value_label::{LabelValueLoc, ValueLabelsRanges, ValueLocRange};
-use log::trace;
-use regalloc::{Reg, RegUsageCollector};
-use std::collections::{HashMap, HashSet};
-use std::hash::Hash;
-
-/// Location of a labeled value: in a register or in a stack slot. Note that a
-/// value may live in more than one location; `AnalysisInfo` maps each
-/// value-label to multiple `ValueLoc`s.
-#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
-enum ValueLoc {
-    Reg(Reg),
-    /// Nominal-SP offset.
-    Stack(i64),
-}
-
-impl From<ValueLoc> for LabelValueLoc {
-    fn from(v: ValueLoc) -> Self {
-        match v {
-            ValueLoc::Reg(r) => LabelValueLoc::Reg(r),
-            ValueLoc::Stack(off) => LabelValueLoc::SPOffset(off),
-        }
-    }
-}
-
-impl ValueLoc {
-    fn is_reg(self) -> bool {
-        match self {
-            ValueLoc::Reg(_) => true,
-            _ => false,
-        }
-    }
-    fn is_stack(self) -> bool {
-        match self {
-            ValueLoc::Stack(_) => true,
-            _ => false,
-        }
-    }
-}
-
-/// Mappings at one program point.
-#[derive(Clone, Debug)]
-struct AnalysisInfo {
-    /// Nominal SP relative to real SP. If `None`, then the offset is
-    /// indeterminate (i.e., we merged to the lattice 'bottom' element). This
-    /// should not happen in well-formed code.
-    nominal_sp_offset: Option<i64>,
-    /// Forward map from labeled values to sets of locations.
-    label_to_locs: HashMap<ValueLabel, HashSet<ValueLoc>>,
-    /// Reverse map for each register indicating the value it holds, if any.
-    reg_to_label: HashMap<Reg, ValueLabel>,
-    /// Reverse map for each stack offset indicating the value it holds, if any.
-    stack_to_label: HashMap<i64, ValueLabel>,
-}
-
-/// Get the registers written (mod'd or def'd) by a machine instruction.
-fn get_inst_writes<M: MachInst>(m: &M) -> Vec<Reg> {
-    // TODO: expose this part of regalloc.rs's interface publicly.
-    let mut vecs = RegUsageCollector::get_empty_reg_vecs_test_framework_only(false);
-    let mut coll = RegUsageCollector::new(&mut vecs);
-    m.get_regs(&mut coll);
-    vecs.defs.extend(vecs.mods.into_iter());
-    vecs.defs
-}
-
-impl AnalysisInfo {
-    /// Create a new analysis state. This is the "top" lattice element at which
-    /// the fixpoint dataflow analysis starts.
-    fn new() -> Self {
-        AnalysisInfo {
-            nominal_sp_offset: Some(0),
-            label_to_locs: HashMap::new(),
-            reg_to_label: HashMap::new(),
-            stack_to_label: HashMap::new(),
-        }
-    }
-
-    /// Remove all locations for a given labeled value. Used when the labeled
-    /// value is redefined (so old values become stale).
-    fn clear_label(&mut self, label: ValueLabel) {
-        if let Some(locs) = self.label_to_locs.remove(&label) {
-            for loc in locs {
-                match loc {
-                    ValueLoc::Reg(r) => {
-                        self.reg_to_label.remove(&r);
-                    }
-                    ValueLoc::Stack(off) => {
-                        self.stack_to_label.remove(&off);
-                    }
-                }
-            }
-        }
-    }
-
-    /// Remove a label from a register, if any. Used, e.g., if the register is
-    /// overwritten.
-    fn clear_reg(&mut self, reg: Reg) {
-        if let Some(label) = self.reg_to_label.remove(&reg) {
-            if let Some(locs) = self.label_to_locs.get_mut(&label) {
-                locs.remove(&ValueLoc::Reg(reg));
-            }
-        }
-    }
-
-    /// Remove a label from a stack offset, if any. Used, e.g., when the stack
-    /// slot is overwritten.
-    fn clear_stack_off(&mut self, off: i64) {
-        if let Some(label) = self.stack_to_label.remove(&off) {
-            if let Some(locs) = self.label_to_locs.get_mut(&label) {
-                locs.remove(&ValueLoc::Stack(off));
-            }
-        }
-    }
-
-    /// Indicate that a labeled value is newly defined and its new value is in
-    /// `reg`.
-    fn def_label_at_reg(&mut self, label: ValueLabel, reg: Reg) {
-        self.clear_label(label);
-        self.label_to_locs
-            .entry(label)
-            .or_insert_with(|| HashSet::new())
-            .insert(ValueLoc::Reg(reg));
-        self.reg_to_label.insert(reg, label);
-    }
-
-    /// Process a store from a register to a stack slot (offset).
-    fn store_reg(&mut self, reg: Reg, off: i64) {
-        self.clear_stack_off(off);
-        if let Some(label) = self.reg_to_label.get(&reg) {
-            if let Some(locs) = self.label_to_locs.get_mut(label) {
-                locs.insert(ValueLoc::Stack(off));
-            }
-            self.stack_to_label.insert(off, *label);
-        }
-    }
-
-    /// Process a load from a stack slot (offset) to a register.
-    fn load_reg(&mut self, reg: Reg, off: i64) {
-        self.clear_reg(reg);
-        if let Some(&label) = self.stack_to_label.get(&off) {
-            if let Some(locs) = self.label_to_locs.get_mut(&label) {
-                locs.insert(ValueLoc::Reg(reg));
-            }
-            self.reg_to_label.insert(reg, label);
-        }
-    }
-
-    /// Process a move from one register to another.
-    fn move_reg(&mut self, to: Reg, from: Reg) {
-        self.clear_reg(to);
-        if let Some(&label) = self.reg_to_label.get(&from) {
-            if let Some(locs) = self.label_to_locs.get_mut(&label) {
-                locs.insert(ValueLoc::Reg(to));
-            }
-            self.reg_to_label.insert(to, label);
-        }
-    }
-
-    /// Update the analysis state w.r.t. an instruction's effects. Given the
-    /// state just before `inst`, this method updates `self` to be the state
-    /// just after `inst`.
-    fn step<M: MachInst>(&mut self, inst: &M) {
-        for write in get_inst_writes(inst) {
-            self.clear_reg(write);
-        }
-        if let Some((label, reg)) = inst.defines_value_label() {
-            self.def_label_at_reg(label, reg);
-        }
-        match inst.stack_op_info() {
-            Some(MachInstStackOpInfo::LoadNomSPOff(reg, offset)) => {
-                self.load_reg(reg, offset + self.nominal_sp_offset.unwrap());
-            }
-            Some(MachInstStackOpInfo::StoreNomSPOff(reg, offset)) => {
-                self.store_reg(reg, offset + self.nominal_sp_offset.unwrap());
-            }
-            Some(MachInstStackOpInfo::NomSPAdj(offset)) => {
-                if self.nominal_sp_offset.is_some() {
-                    self.nominal_sp_offset = Some(self.nominal_sp_offset.unwrap() + offset);
-                }
-            }
-            _ => {}
-        }
-        if let Some((to, from)) = inst.is_move() {
-            let to = to.to_reg();
-            self.move_reg(to, from);
-        }
-    }
-}
-
-/// Trait used to implement the dataflow analysis' meet (intersect) function
-/// onthe `AnalysisInfo` components. For efficiency, this is implemented as a
-/// mutation on the LHS, rather than a pure functional operation.
-trait IntersectFrom {
-    fn intersect_from(&mut self, other: &Self) -> IntersectResult;
-}
-
-/// Result of an intersection operation. Indicates whether the mutated LHS
-/// (which becomes the intersection result) differs from the original LHS. Also
-/// indicates if the value has become "empty" and should be removed from a
-/// parent container, if any.
-struct IntersectResult {
-    /// Did the intersection change the LHS input (the one that was mutated into
-    /// the result)? This is needed to drive the fixpoint loop; when no more
-    /// changes occur, then we have converted.
-    changed: bool,
-    /// Is the resulting value "empty"? This can be used when a container, such
-    /// as a map, holds values of this (intersection result) type; when
-    /// `is_empty` is true for the merge of the values at a particular key, we
-    /// can remove that key from the merged (intersected) result. This is not
-    /// necessary for analysis correctness but reduces the memory and runtime
-    /// cost of the fixpoint loop.
-    is_empty: bool,
-}
-
-impl IntersectFrom for AnalysisInfo {
-    fn intersect_from(&mut self, other: &Self) -> IntersectResult {
-        let mut changed = false;
-        changed |= self
-            .nominal_sp_offset
-            .intersect_from(&other.nominal_sp_offset)
-            .changed;
-        changed |= self
-            .label_to_locs
-            .intersect_from(&other.label_to_locs)
-            .changed;
-        changed |= self
-            .reg_to_label
-            .intersect_from(&other.reg_to_label)
-            .changed;
-        changed |= self
-            .stack_to_label
-            .intersect_from(&other.stack_to_label)
-            .changed;
-        IntersectResult {
-            changed,
-            is_empty: false,
-        }
-    }
-}
-
-impl<K, V> IntersectFrom for HashMap<K, V>
-where
-    K: Copy + Eq + Hash,
-    V: IntersectFrom,
-{
-    /// Intersection for hashmap: remove keys that are not in both inputs;
-    /// recursively intersect values for keys in common.
-    fn intersect_from(&mut self, other: &Self) -> IntersectResult {
-        let mut changed = false;
-        let mut remove_keys = vec![];
-        for k in self.keys() {
-            if !other.contains_key(k) {
-                remove_keys.push(*k);
-            }
-        }
-        for k in &remove_keys {
-            changed = true;
-            self.remove(k);
-        }
-
-        remove_keys.clear();
-        for k in other.keys() {
-            if let Some(v) = self.get_mut(k) {
-                let result = v.intersect_from(other.get(k).unwrap());
-                changed |= result.changed;
-                if result.is_empty {
-                    remove_keys.push(*k);
-                }
-            }
-        }
-        for k in &remove_keys {
-            changed = true;
-            self.remove(k);
-        }
-
-        IntersectResult {
-            changed,
-            is_empty: self.len() == 0,
-        }
-    }
-}
-impl<T> IntersectFrom for HashSet<T>
-where
-    T: Copy + Eq + Hash,
-{
-    /// Intersection for hashset: just take the set intersection.
-    fn intersect_from(&mut self, other: &Self) -> IntersectResult {
-        let mut changed = false;
-        let mut remove = vec![];
-        for val in self.iter() {
-            if !other.contains(val) {
-                remove.push(*val);
-            }
-        }
-        for val in remove {
-            changed = true;
-            self.remove(&val);
-        }
-
-        IntersectResult {
-            changed,
-            is_empty: self.len() == 0,
-        }
-    }
-}
-impl IntersectFrom for ValueLabel {
-    // Intersection for labeled value: remove if not equal. This is equivalent
-    // to a three-level lattice with top, bottom, and unordered set of
-    // individual labels in between.
-    fn intersect_from(&mut self, other: &Self) -> IntersectResult {
-        IntersectResult {
-            changed: false,
-            is_empty: *self != *other,
-        }
-    }
-}
-impl<T> IntersectFrom for Option<T>
-where
-    T: Copy + Eq,
-{
-    /// Intersectino for Option<T>: recursively intersect if both `Some`, else
-    /// `None`.
-    fn intersect_from(&mut self, other: &Self) -> IntersectResult {
-        let mut changed = false;
-        if !(self.is_some() && other.is_some() && self == other) {
-            changed = true;
-            *self = None;
-        }
-        IntersectResult {
-            changed,
-            is_empty: self.is_none(),
-        }
-    }
-}
-
-/// Compute the value-label ranges (locations for program-point ranges for
-/// labeled values) from a given `VCode` compilation result.
-///
-/// In order to compute this information, we perform a dataflow analysis on the
-/// machine code. To do so, and translate the results into a form usable by the
-/// debug-info consumers, we need to know two additional things:
-///
-/// - The machine-code layout (code offsets) of the instructions. DWARF is
-///   encoded in terms of instruction *ends* (and we reason about value
-///   locations at program points *after* instructions, to match this), so we
-///   take an array `inst_ends`, giving us code offsets for each instruction's
-///   end-point. (Note that this is one *past* the last byte; so a 4-byte
-///   instruction at offset 0 has an end offset of 4.)
-///
-/// - The locations of the labels to which branches will jump. Branches can tell
-///   us about their targets in terms of `MachLabel`s, but we don't know where
-///   those `MachLabel`s will be placed in the linear array of instructions.  We
-///   take the array `label_insn_index` to provide this info: for a label with
-///   index `l`, `label_insn_index[l]` is the index of the instruction before
-///   which that label is bound.
-pub(crate) fn compute<I: VCodeInst>(
-    insts: &[I],
-    layout_info: &InstsLayoutInfo,
-) -> ValueLabelsRanges {
-    let inst_start = |idx: usize| {
-        if idx == 0 {
-            0
-        } else {
-            layout_info.inst_end_offsets[idx - 1]
-        }
-    };
-
-    trace!("compute: insts =");
-    for i in 0..insts.len() {
-        trace!(
-            " #{} end: {} -> {:?}",
-            i,
-            layout_info.inst_end_offsets[i],
-            insts[i]
-        );
-    }
-    trace!("label_insn_index: {:?}", layout_info.label_inst_indices);
-
-    // Info at each block head, indexed by label.
-    let mut block_starts: HashMap<u32, AnalysisInfo> = HashMap::new();
-
-    // Initialize state at entry.
-    block_starts.insert(0, AnalysisInfo::new());
-
-    // Worklist: label indices for basic blocks.
-    let mut worklist = Vec::new();
-    let mut worklist_set = HashSet::new();
-    worklist.push(0);
-    worklist_set.insert(0);
-
-    while !worklist.is_empty() {
-        let block = worklist.pop().unwrap();
-        worklist_set.remove(&block);
-
-        let mut state = block_starts.get(&block).unwrap().clone();
-        trace!("at block {} -> state: {:?}", block, state);
-        // Iterate for each instruction in the block (we break at the first
-        // terminator we see).
-        let mut index = layout_info.label_inst_indices[block as usize];
-        while index < insts.len() as u32 {
-            state.step(&insts[index as usize]);
-            trace!(" -> inst #{}: {:?}", index, insts[index as usize]);
-            trace!("    --> state: {:?}", state);
-
-            let term = insts[index as usize].is_term();
-            if term.is_term() {
-                for succ in term.get_succs() {
-                    trace!("    SUCCESSOR block {}", succ.get());
-                    if let Some(succ_state) = block_starts.get_mut(&succ.get()) {
-                        trace!("       orig state: {:?}", succ_state);
-                        if succ_state.intersect_from(&state).changed {
-                            if worklist_set.insert(succ.get()) {
-                                worklist.push(succ.get());
-                            }
-                            trace!("        (changed)");
-                        }
-                        trace!("       new state: {:?}", succ_state);
-                    } else {
-                        // First time seeing this block
-                        block_starts.insert(succ.get(), state.clone());
-                        worklist.push(succ.get());
-                        worklist_set.insert(succ.get());
-                    }
-                }
-                break;
-            }
-
-            index += 1;
-        }
-    }
-
-    // Now iterate over blocks one last time, collecting
-    // value-label locations.
-
-    let mut value_labels_ranges: ValueLabelsRanges = HashMap::new();
-    for block in 0..layout_info.label_inst_indices.len() {
-        let start_index = layout_info.label_inst_indices[block];
-        let end_index = if block == layout_info.label_inst_indices.len() - 1 {
-            insts.len() as u32
-        } else {
-            layout_info.label_inst_indices[block + 1]
-        };
-        let block = block as u32;
-        let mut state = block_starts.get(&block).unwrap().clone();
-        for index in start_index..end_index {
-            let offset = inst_start(index as usize);
-            let end = layout_info.inst_end_offsets[index as usize];
-
-            // Cold blocks cause instructions to occur out-of-order wrt
-            // others. We rely on the monotonic mapping from instruction
-            // index to offset in machine code for this analysis to work,
-            // so we just skip debuginfo for cold blocks. This should be
-            // generally fine, as cold blocks generally constitute
-            // slowpaths for expansions of particular ops, rather than
-            // user-written code.
-            if layout_info.start_of_cold_code.is_some()
-                && offset >= layout_info.start_of_cold_code.unwrap()
-            {
-                continue;
-            }
-
-            assert!(offset <= end);
-            state.step(&insts[index as usize]);
-
-            for (label, locs) in &state.label_to_locs {
-                trace!("   inst {} has label {:?} -> locs {:?}", index, label, locs);
-                // Find an appropriate loc: a register if possible, otherwise pick the first stack
-                // loc.
-                let reg = locs.iter().cloned().find(|l| l.is_reg());
-                let loc = reg.or_else(|| locs.iter().cloned().find(|l| l.is_stack()));
-                if let Some(loc) = loc {
-                    let loc = LabelValueLoc::from(loc);
-                    let list = value_labels_ranges.entry(*label).or_insert_with(|| vec![]);
-                    // If the existing location list for this value-label is
-                    // either empty, or has an end location that does not extend
-                    // to the current offset, then we have to append a new
-                    // entry. Otherwise, we can extend the current entry.
-                    //
-                    // Note that `end` is one past the end of the instruction;
-                    // it appears that `end` is exclusive, so a mapping valid at
-                    // offset 5 will have start = 5, end = 6.
-                    if list
-                        .last()
-                        .map(|last| last.end <= offset || last.loc != loc)
-                        .unwrap_or(true)
-                    {
-                        list.push(ValueLocRange {
-                            loc,
-                            start: end,
-                            end: end + 1,
-                        });
-                    } else {
-                        list.last_mut().unwrap().end = end + 1;
-                    }
-                }
-            }
-        }
-    }
-
-    trace!("ret: {:?}", value_labels_ranges);
-    value_labels_ranges
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/helpers.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/helpers.rs
deleted file mode 100644
index 40139d61e..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/helpers.rs
+++ /dev/null
@@ -1,43 +0,0 @@
-//! Miscellaneous helpers for machine backends.
-
-use super::{InsnOutput, LowerCtx, VCodeInst, ValueRegs};
-use crate::ir::Type;
-use regalloc::{Reg, Writable};
-use std::ops::{Add, BitAnd, Not, Sub};
-
-/// Returns the size (in bits) of a given type.
-pub fn ty_bits(ty: Type) -> usize {
-    usize::from(ty.bits())
-}
-
-/// Is the type represented by an integer (not float) at the machine level?
-pub(crate) fn ty_has_int_representation(ty: Type) -> bool {
-    ty.is_int() || ty.is_bool() || ty.is_ref()
-}
-
-/// Is the type represented by a float or vector value at the machine level?
-pub(crate) fn ty_has_float_or_vec_representation(ty: Type) -> bool {
-    ty.is_vector() || ty.is_float()
-}
-
-/// Allocate a register for an instruction output and return it.
-pub(crate) fn get_output_reg<I: VCodeInst, C: LowerCtx<I = I>>(
-    ctx: &mut C,
-    spec: InsnOutput,
-) -> ValueRegs<Writable<Reg>> {
-    ctx.get_output(spec.insn, spec.output)
-}
-
-/// Align a size up to a power-of-two alignment.
-pub(crate) fn align_to<N>(x: N, alignment: N) -> N
-where
-    N: Not<Output = N>
-        + BitAnd<N, Output = N>
-        + Add<N, Output = N>
-        + Sub<N, Output = N>
-        + From<u8>
-        + Copy,
-{
-    let alignment_mask = alignment - 1.into();
-    (x + alignment_mask) & !alignment_mask
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/inst_common.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/inst_common.rs
deleted file mode 100644
index a4fb41ec7..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/inst_common.rs
+++ /dev/null
@@ -1,94 +0,0 @@
-//! A place to park MachInst::Inst fragments which are common across multiple architectures.
-
-use super::{LowerCtx, VCodeInst};
-use crate::ir::{self, Inst as IRInst};
-use smallvec::SmallVec;
-
-//============================================================================
-// Instruction input "slots".
-//
-// We use these types to refer to operand numbers, and result numbers, together
-// with the associated instruction, in a type-safe way.
-
-/// Identifier for a particular input of an instruction.
-#[derive(Clone, Copy, Debug, PartialEq, Eq)]
-pub(crate) struct InsnInput {
-    pub(crate) insn: IRInst,
-    pub(crate) input: usize,
-}
-
-/// Identifier for a particular output of an instruction.
-#[derive(Clone, Copy, Debug, PartialEq, Eq)]
-pub(crate) struct InsnOutput {
-    pub(crate) insn: IRInst,
-    pub(crate) output: usize,
-}
-
-pub(crate) fn insn_inputs<I: VCodeInst, C: LowerCtx<I = I>>(
-    ctx: &C,
-    insn: IRInst,
-) -> SmallVec<[InsnInput; 4]> {
-    (0..ctx.num_inputs(insn))
-        .map(|i| InsnInput { insn, input: i })
-        .collect()
-}
-
-pub(crate) fn insn_outputs<I: VCodeInst, C: LowerCtx<I = I>>(
-    ctx: &C,
-    insn: IRInst,
-) -> SmallVec<[InsnOutput; 4]> {
-    (0..ctx.num_outputs(insn))
-        .map(|i| InsnOutput { insn, output: i })
-        .collect()
-}
-
-//============================================================================
-// Atomic instructions.
-
-/// Atomic memory update operations.  As of 21 Aug 2020 these are used for the aarch64 and x64
-/// targets.
-#[derive(Clone, Copy, Debug, PartialEq, Eq)]
-#[repr(u8)]
-pub enum AtomicRmwOp {
-    /// Add
-    Add,
-    /// Sub
-    Sub,
-    /// And
-    And,
-    /// Nand
-    Nand,
-    /// Or
-    Or,
-    /// Exclusive Or
-    Xor,
-    /// Exchange (swap operands)
-    Xchg,
-    /// Unsigned min
-    Umin,
-    /// Unsigned max
-    Umax,
-    /// Signed min
-    Smin,
-    /// Signed max
-    Smax,
-}
-
-impl AtomicRmwOp {
-    /// Converts an `ir::AtomicRmwOp` to the corresponding `inst_common::AtomicRmwOp`.
-    pub fn from(ir_op: ir::AtomicRmwOp) -> Self {
-        match ir_op {
-            ir::AtomicRmwOp::Add => AtomicRmwOp::Add,
-            ir::AtomicRmwOp::Sub => AtomicRmwOp::Sub,
-            ir::AtomicRmwOp::And => AtomicRmwOp::And,
-            ir::AtomicRmwOp::Nand => AtomicRmwOp::Nand,
-            ir::AtomicRmwOp::Or => AtomicRmwOp::Or,
-            ir::AtomicRmwOp::Xor => AtomicRmwOp::Xor,
-            ir::AtomicRmwOp::Xchg => AtomicRmwOp::Xchg,
-            ir::AtomicRmwOp::Umin => AtomicRmwOp::Umin,
-            ir::AtomicRmwOp::Umax => AtomicRmwOp::Umax,
-            ir::AtomicRmwOp::Smin => AtomicRmwOp::Smin,
-            ir::AtomicRmwOp::Smax => AtomicRmwOp::Smax,
-        }
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/isle.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/isle.rs
deleted file mode 100644
index 3afb02f8a..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/isle.rs
+++ /dev/null
@@ -1,545 +0,0 @@
-use crate::ir::{types, Inst, Value, ValueList};
-use crate::machinst::{get_output_reg, InsnOutput, LowerCtx, MachInst, RegRenamer};
-use alloc::boxed::Box;
-use alloc::vec::Vec;
-use regalloc::{Reg, Writable};
-use smallvec::SmallVec;
-use std::cell::Cell;
-
-pub use super::MachLabel;
-pub use crate::ir::{ExternalName, FuncRef, GlobalValue, SigRef};
-pub use crate::isa::unwind::UnwindInst;
-pub use crate::machinst::RelocDistance;
-
-pub type Unit = ();
-pub type ValueSlice = (ValueList, usize);
-pub type ValueArray2 = [Value; 2];
-pub type ValueArray3 = [Value; 3];
-pub type WritableReg = Writable<Reg>;
-pub type VecReg = Vec<Reg>;
-pub type VecWritableReg = Vec<WritableReg>;
-pub type ValueRegs = crate::machinst::ValueRegs<Reg>;
-pub type InstOutput = SmallVec<[ValueRegs; 2]>;
-pub type InstOutputBuilder = Cell<InstOutput>;
-pub type VecMachLabel = Vec<MachLabel>;
-pub type BoxExternalName = Box<ExternalName>;
-
-/// Helper macro to define methods in `prelude.isle` within `impl Context for
-/// ...` for each backend. These methods are shared amongst all backends.
-#[macro_export]
-#[doc(hidden)]
-macro_rules! isle_prelude_methods {
-    () => {
-        #[inline]
-        fn unpack_value_array_2(&mut self, arr: &ValueArray2) -> (Value, Value) {
-            let [a, b] = *arr;
-            (a, b)
-        }
-
-        #[inline]
-        fn pack_value_array_2(&mut self, a: Value, b: Value) -> ValueArray2 {
-            [a, b]
-        }
-
-        #[inline]
-        fn unpack_value_array_3(&mut self, arr: &ValueArray3) -> (Value, Value, Value) {
-            let [a, b, c] = *arr;
-            (a, b, c)
-        }
-
-        #[inline]
-        fn pack_value_array_3(&mut self, a: Value, b: Value, c: Value) -> ValueArray3 {
-            [a, b, c]
-        }
-
-        #[inline]
-        fn value_reg(&mut self, reg: Reg) -> ValueRegs {
-            ValueRegs::one(reg)
-        }
-
-        #[inline]
-        fn value_regs(&mut self, r1: Reg, r2: Reg) -> ValueRegs {
-            ValueRegs::two(r1, r2)
-        }
-
-        #[inline]
-        fn value_regs_invalid(&mut self) -> ValueRegs {
-            ValueRegs::invalid()
-        }
-
-        #[inline]
-        fn output_none(&mut self) -> InstOutput {
-            smallvec::smallvec![]
-        }
-
-        #[inline]
-        fn output(&mut self, regs: ValueRegs) -> InstOutput {
-            smallvec::smallvec![regs]
-        }
-
-        #[inline]
-        fn output_pair(&mut self, r1: ValueRegs, r2: ValueRegs) -> InstOutput {
-            smallvec::smallvec![r1, r2]
-        }
-
-        #[inline]
-        fn output_builder_new(&mut self) -> InstOutputBuilder {
-            std::cell::Cell::new(InstOutput::new())
-        }
-
-        #[inline]
-        fn output_builder_push(&mut self, builder: &InstOutputBuilder, regs: ValueRegs) -> Unit {
-            let mut vec = builder.take();
-            vec.push(regs);
-            builder.set(vec);
-        }
-
-        #[inline]
-        fn output_builder_finish(&mut self, builder: &InstOutputBuilder) -> InstOutput {
-            builder.take()
-        }
-
-        #[inline]
-        fn temp_writable_reg(&mut self, ty: Type) -> WritableReg {
-            let value_regs = self.lower_ctx.alloc_tmp(ty);
-            value_regs.only_reg().unwrap()
-        }
-
-        #[inline]
-        fn invalid_reg(&mut self) -> Reg {
-            Reg::invalid()
-        }
-
-        #[inline]
-        fn put_in_reg(&mut self, val: Value) -> Reg {
-            self.lower_ctx.put_value_in_regs(val).only_reg().unwrap()
-        }
-
-        #[inline]
-        fn put_in_regs(&mut self, val: Value) -> ValueRegs {
-            self.lower_ctx.put_value_in_regs(val)
-        }
-
-        #[inline]
-        fn value_regs_get(&mut self, regs: ValueRegs, i: usize) -> Reg {
-            regs.regs()[i]
-        }
-
-        #[inline]
-        fn u8_as_u64(&mut self, x: u8) -> u64 {
-            x.into()
-        }
-
-        #[inline]
-        fn u16_as_u64(&mut self, x: u16) -> u64 {
-            x.into()
-        }
-
-        #[inline]
-        fn u32_as_u64(&mut self, x: u32) -> u64 {
-            x.into()
-        }
-
-        #[inline]
-        fn i64_as_u64(&mut self, x: i64) -> u64 {
-            x as u64
-        }
-
-        #[inline]
-        fn u64_add(&mut self, x: u64, y: u64) -> u64 {
-            x.wrapping_add(y)
-        }
-
-        #[inline]
-        fn u64_sub(&mut self, x: u64, y: u64) -> u64 {
-            x.wrapping_sub(y)
-        }
-
-        #[inline]
-        fn u64_and(&mut self, x: u64, y: u64) -> u64 {
-            x & y
-        }
-
-        #[inline]
-        fn ty_bits(&mut self, ty: Type) -> u8 {
-            use std::convert::TryInto;
-            ty.bits().try_into().unwrap()
-        }
-
-        #[inline]
-        fn ty_bits_u16(&mut self, ty: Type) -> u16 {
-            ty.bits()
-        }
-
-        #[inline]
-        fn ty_bits_u64(&mut self, ty: Type) -> u64 {
-            ty.bits() as u64
-        }
-
-        #[inline]
-        fn ty_bytes(&mut self, ty: Type) -> u16 {
-            u16::try_from(ty.bytes()).unwrap()
-        }
-
-        #[inline]
-        fn ty_mask(&mut self, ty: Type) -> u64 {
-            match ty.bits() {
-                1 => 1,
-                8 => 0xff,
-                16 => 0xffff,
-                32 => 0xffff_ffff,
-                64 => 0xffff_ffff_ffff_ffff,
-                _ => unimplemented!(),
-            }
-        }
-
-        fn fits_in_16(&mut self, ty: Type) -> Option<Type> {
-            if ty.bits() <= 16 {
-                Some(ty)
-            } else {
-                None
-            }
-        }
-
-        #[inline]
-        fn fits_in_32(&mut self, ty: Type) -> Option<Type> {
-            if ty.bits() <= 32 {
-                Some(ty)
-            } else {
-                None
-            }
-        }
-
-        #[inline]
-        fn fits_in_64(&mut self, ty: Type) -> Option<Type> {
-            if ty.bits() <= 64 {
-                Some(ty)
-            } else {
-                None
-            }
-        }
-
-        #[inline]
-        fn ty_32_or_64(&mut self, ty: Type) -> Option<Type> {
-            if ty.bits() == 32 || ty.bits() == 64 {
-                Some(ty)
-            } else {
-                None
-            }
-        }
-
-        #[inline]
-        fn ty_8_or_16(&mut self, ty: Type) -> Option<Type> {
-            if ty.bits() == 8 || ty.bits() == 16 {
-                Some(ty)
-            } else {
-                None
-            }
-        }
-
-        #[inline]
-        fn ty_int_bool_64(&mut self, ty: Type) -> Option<Type> {
-            match ty {
-                I64 | B64 => Some(ty),
-                _ => None,
-            }
-        }
-
-        #[inline]
-        fn ty_int_bool_128(&mut self, ty: Type) -> Option<Type> {
-            match ty {
-                I128 | B128 => Some(ty),
-                _ => None,
-            }
-        }
-
-        fn vec128(&mut self, ty: Type) -> Option<Type> {
-            if ty.is_vector() && ty.bits() == 128 {
-                Some(ty)
-            } else {
-                None
-            }
-        }
-
-        #[inline]
-        fn value_list_slice(&mut self, list: ValueList) -> ValueSlice {
-            (list, 0)
-        }
-
-        #[inline]
-        fn value_slice_empty(&mut self, slice: ValueSlice) -> Option<()> {
-            let (list, off) = slice;
-            if off >= list.len(&self.lower_ctx.dfg().value_lists) {
-                Some(())
-            } else {
-                None
-            }
-        }
-
-        #[inline]
-        fn value_slice_unwrap(&mut self, slice: ValueSlice) -> Option<(Value, ValueSlice)> {
-            let (list, off) = slice;
-            if let Some(val) = list.get(off, &self.lower_ctx.dfg().value_lists) {
-                Some((val, (list, off + 1)))
-            } else {
-                None
-            }
-        }
-
-        #[inline]
-        fn value_slice_len(&mut self, slice: ValueSlice) -> usize {
-            let (list, off) = slice;
-            list.len(&self.lower_ctx.dfg().value_lists) - off
-        }
-
-        #[inline]
-        fn value_slice_get(&mut self, slice: ValueSlice, idx: usize) -> Value {
-            let (list, off) = slice;
-            list.get(off + idx, &self.lower_ctx.dfg().value_lists)
-                .unwrap()
-        }
-
-        #[inline]
-        fn writable_reg_to_reg(&mut self, r: WritableReg) -> Reg {
-            r.to_reg()
-        }
-
-        #[inline]
-        fn u64_from_imm64(&mut self, imm: Imm64) -> u64 {
-            imm.bits() as u64
-        }
-
-        #[inline]
-        fn inst_results(&mut self, inst: Inst) -> ValueSlice {
-            (self.lower_ctx.dfg().inst_results_list(inst), 0)
-        }
-
-        #[inline]
-        fn first_result(&mut self, inst: Inst) -> Option<Value> {
-            self.lower_ctx.dfg().inst_results(inst).first().copied()
-        }
-
-        #[inline]
-        fn inst_data(&mut self, inst: Inst) -> InstructionData {
-            self.lower_ctx.dfg()[inst].clone()
-        }
-
-        #[inline]
-        fn value_type(&mut self, val: Value) -> Type {
-            self.lower_ctx.dfg().value_type(val)
-        }
-
-        #[inline]
-        fn multi_lane(&mut self, ty: Type) -> Option<(u8, u16)> {
-            if ty.lane_count() > 1 {
-                Some((ty.lane_bits(), ty.lane_count()))
-            } else {
-                None
-            }
-        }
-
-        #[inline]
-        fn def_inst(&mut self, val: Value) -> Option<Inst> {
-            self.lower_ctx.dfg().value_def(val).inst()
-        }
-
-        fn u64_from_ieee32(&mut self, val: Ieee32) -> u64 {
-            val.bits().into()
-        }
-
-        fn u64_from_ieee64(&mut self, val: Ieee64) -> u64 {
-            val.bits()
-        }
-
-        fn u8_from_uimm8(&mut self, val: Uimm8) -> u8 {
-            val
-        }
-
-        fn not_i64x2(&mut self, ty: Type) -> Option<()> {
-            if ty == I64X2 {
-                None
-            } else {
-                Some(())
-            }
-        }
-
-        fn trap_code_division_by_zero(&mut self) -> TrapCode {
-            TrapCode::IntegerDivisionByZero
-        }
-
-        fn trap_code_integer_overflow(&mut self) -> TrapCode {
-            TrapCode::IntegerOverflow
-        }
-
-        fn trap_code_bad_conversion_to_integer(&mut self) -> TrapCode {
-            TrapCode::BadConversionToInteger
-        }
-
-        fn avoid_div_traps(&mut self, _: Type) -> Option<()> {
-            if self.flags.avoid_div_traps() {
-                Some(())
-            } else {
-                None
-            }
-        }
-
-        #[inline]
-        fn func_ref_data(&mut self, func_ref: FuncRef) -> (SigRef, ExternalName, RelocDistance) {
-            let funcdata = &self.lower_ctx.dfg().ext_funcs[func_ref];
-            (
-                funcdata.signature,
-                funcdata.name.clone(),
-                funcdata.reloc_distance(),
-            )
-        }
-
-        #[inline]
-        fn symbol_value_data(
-            &mut self,
-            global_value: GlobalValue,
-        ) -> Option<(ExternalName, RelocDistance, i64)> {
-            let (name, reloc, offset) = self.lower_ctx.symbol_value_data(global_value)?;
-            Some((name.clone(), reloc, offset))
-        }
-
-        #[inline]
-        fn reloc_distance_near(&mut self, dist: RelocDistance) -> Option<()> {
-            if dist == RelocDistance::Near {
-                Some(())
-            } else {
-                None
-            }
-        }
-
-        fn nonzero_u64_from_imm64(&mut self, val: Imm64) -> Option<u64> {
-            match val.bits() {
-                0 => None,
-                n => Some(n as u64),
-            }
-        }
-
-        #[inline]
-        fn u32_add(&mut self, a: u32, b: u32) -> u32 {
-            a.wrapping_add(b)
-        }
-
-        #[inline]
-        fn u8_and(&mut self, a: u8, b: u8) -> u8 {
-            a & b
-        }
-
-        #[inline]
-        fn lane_type(&mut self, ty: Type) -> Type {
-            ty.lane_type()
-        }
-    };
-}
-
-/// This structure is used to implement the ISLE-generated `Context` trait and
-/// internally has a temporary reference to a machinst `LowerCtx`.
-pub(crate) struct IsleContext<'a, C: LowerCtx, F, I, const N: usize>
-where
-    [(C::I, bool); N]: smallvec::Array,
-{
-    pub lower_ctx: &'a mut C,
-    pub flags: &'a F,
-    pub isa_flags: &'a I,
-    pub emitted_insts: SmallVec<[(C::I, bool); N]>,
-}
-
-/// Shared lowering code amongst all backends for doing ISLE-based lowering.
-///
-/// The `isle_lower` argument here is an ISLE-generated function for `lower` and
-/// then this function otherwise handles register mapping and such around the
-/// lowering.
-pub(crate) fn lower_common<C, F, I, IF, const N: usize>(
-    lower_ctx: &mut C,
-    flags: &F,
-    isa_flags: &I,
-    outputs: &[InsnOutput],
-    inst: Inst,
-    isle_lower: IF,
-    map_regs: fn(&mut C::I, &RegRenamer),
-) -> Result<(), ()>
-where
-    C: LowerCtx,
-    [(C::I, bool); N]: smallvec::Array<Item = (C::I, bool)>,
-    IF: Fn(&mut IsleContext<'_, C, F, I, N>, Inst) -> Option<InstOutput>,
-{
-    // TODO: reuse the ISLE context across lowerings so we can reuse its
-    // internal heap allocations.
-    let mut isle_ctx = IsleContext {
-        lower_ctx,
-        flags,
-        isa_flags,
-        emitted_insts: SmallVec::new(),
-    };
-
-    let temp_regs = isle_lower(&mut isle_ctx, inst).ok_or(())?;
-
-    #[cfg(debug_assertions)]
-    {
-        debug_assert_eq!(
-            temp_regs.len(),
-            outputs.len(),
-            "the number of temporary values and destination values do \
-         not match ({} != {}); ensure the correct registers are being \
-         returned.",
-            temp_regs.len(),
-            outputs.len(),
-        );
-    }
-
-    // The ISLE generated code emits its own registers to define the
-    // instruction's lowered values in. We rename those registers to the
-    // registers they were assigned when their value was used as an operand in
-    // earlier lowerings.
-    let mut renamer = RegRenamer::default();
-    for i in 0..outputs.len() {
-        let regs = temp_regs[i];
-        let dsts = get_output_reg(isle_ctx.lower_ctx, outputs[i]);
-        let ty = isle_ctx
-            .lower_ctx
-            .output_ty(outputs[i].insn, outputs[i].output);
-        if ty == types::IFLAGS || ty == types::FFLAGS {
-            // Flags values do not occupy any registers.
-            assert!(regs.len() == 0);
-        } else {
-            let (_, tys) = <C::I>::rc_for_type(ty).unwrap();
-            assert!(regs.len() == tys.len());
-            assert!(regs.len() == dsts.len());
-            for ((dst, temp), ty) in dsts.regs().iter().zip(regs.regs().iter()).zip(tys) {
-                renamer.add_rename(*temp, dst.to_reg(), *ty);
-            }
-        }
-    }
-    for (inst, _) in isle_ctx.emitted_insts.iter_mut() {
-        map_regs(inst, &renamer);
-    }
-
-    // If any renamed register wasn't actually defined in the ISLE-generated
-    // instructions then what we're actually doing is "renaming" an input to a
-    // new name which requires manually inserting a `mov` instruction. Note that
-    // this typically doesn't happen and is only here for cases where the input
-    // is sometimes passed through unmodified to the output, such as
-    // zero-extending a 64-bit input to a 128-bit output which doesn't actually
-    // change the input and simply produces another zero'd register.
-    for (old, new, ty) in renamer.unmapped_defs() {
-        isle_ctx
-            .lower_ctx
-            .emit(<C::I>::gen_move(Writable::from_reg(new), old, ty));
-    }
-
-    // Once everything is remapped we forward all emitted instructions to the
-    // `lower_ctx`. Note that this happens after the synthetic mov's above in
-    // case any of these instruction use those movs.
-    for (inst, is_safepoint) in isle_ctx.emitted_insts {
-        if is_safepoint {
-            lower_ctx.emit_safepoint(inst);
-        } else {
-            lower_ctx.emit(inst);
-        }
-    }
-
-    Ok(())
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/lower.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/lower.rs
deleted file mode 100644
index cd28dfea0..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/lower.rs
+++ /dev/null
@@ -1,1375 +0,0 @@
-//! This module implements lowering (instruction selection) from Cranelift IR
-//! to machine instructions with virtual registers. This is *almost* the final
-//! machine code, except for register allocation.
-
-// TODO: separate the IR-query core of `LowerCtx` from the lowering logic built
-// on top of it, e.g. the side-effect/coloring analysis and the scan support.
-
-use crate::data_value::DataValue;
-use crate::entity::SecondaryMap;
-use crate::fx::{FxHashMap, FxHashSet};
-use crate::inst_predicates::{has_lowering_side_effect, is_constant_64bit};
-use crate::ir::instructions::BranchInfo;
-use crate::ir::{
-    types::{FFLAGS, IFLAGS},
-    ArgumentPurpose, Block, Constant, ConstantData, DataFlowGraph, ExternalName, Function,
-    GlobalValue, GlobalValueData, Inst, InstructionData, MemFlags, Opcode, Signature, SourceLoc,
-    Type, Value, ValueDef, ValueLabelAssignments, ValueLabelStart,
-};
-use crate::machinst::{
-    non_writable_value_regs, writable_value_regs, ABICallee, BlockIndex, BlockLoweringOrder,
-    LoweredBlock, MachLabel, VCode, VCodeBuilder, VCodeConstant, VCodeConstantData, VCodeConstants,
-    VCodeInst, ValueRegs,
-};
-use crate::CodegenResult;
-use alloc::boxed::Box;
-use alloc::vec::Vec;
-use core::convert::TryInto;
-use regalloc::{Reg, StackmapRequestInfo, Writable};
-use smallvec::{smallvec, SmallVec};
-use std::fmt::Debug;
-
-/// An "instruction color" partitions CLIF instructions by side-effecting ops.
-/// All instructions with the same "color" are guaranteed not to be separated by
-/// any side-effecting op (for this purpose, loads are also considered
-/// side-effecting, to avoid subtle questions w.r.t. the memory model), and
-/// furthermore, it is guaranteed that for any two instructions A and B such
-/// that color(A) == color(B), either A dominates B and B postdominates A, or
-/// vice-versa. (For now, in practice, only ops in the same basic block can ever
-/// have the same color, trivially providing the second condition.) Intuitively,
-/// this means that the ops of the same color must always execute "together", as
-/// part of one atomic contiguous section of the dynamic execution trace, and
-/// they can be freely permuted (modulo true dataflow dependencies) without
-/// affecting program behavior.
-#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
-struct InstColor(u32);
-impl InstColor {
-    fn new(n: u32) -> InstColor {
-        InstColor(n)
-    }
-
-    /// Get an arbitrary index representing this color. The index is unique
-    /// *within a single function compilation*, but indices may be reused across
-    /// functions.
-    pub fn get(self) -> u32 {
-        self.0
-    }
-}
-
-/// A context that machine-specific lowering code can use to emit lowered
-/// instructions. This is the view of the machine-independent per-function
-/// lowering context that is seen by the machine backend.
-pub trait LowerCtx {
-    /// The instruction type for which this lowering framework is instantiated.
-    type I: VCodeInst;
-
-    fn dfg(&self) -> &DataFlowGraph;
-
-    // Function-level queries:
-
-    /// Get the `ABICallee`.
-    fn abi(&mut self) -> &mut dyn ABICallee<I = Self::I>;
-    /// Get the (virtual) register that receives the return value. A return
-    /// instruction should lower into a sequence that fills this register. (Why
-    /// not allow the backend to specify its own result register for the return?
-    /// Because there may be multiple return points.)
-    fn retval(&self, idx: usize) -> ValueRegs<Writable<Reg>>;
-    /// Returns the vreg containing the VmContext parameter, if there's one.
-    fn get_vm_context(&self) -> Option<Reg>;
-
-    // General instruction queries:
-
-    /// Get the instdata for a given IR instruction.
-    fn data(&self, ir_inst: Inst) -> &InstructionData;
-    /// Get the controlling type for a polymorphic IR instruction.
-    fn ty(&self, ir_inst: Inst) -> Type;
-    /// Get the target for a call instruction, as an `ExternalName`. Returns a tuple
-    /// providing this name and the "relocation distance", i.e., whether the backend
-    /// can assume the target will be "nearby" (within some small offset) or an
-    /// arbitrary address. (This comes from the `colocated` bit in the CLIF.)
-    fn call_target<'b>(&'b self, ir_inst: Inst) -> Option<(&'b ExternalName, RelocDistance)>;
-    /// Get the signature for a call or call-indirect instruction.
-    fn call_sig<'b>(&'b self, ir_inst: Inst) -> Option<&'b Signature>;
-    /// Get the symbol name, relocation distance estimate, and offset for a
-    /// symbol_value instruction.
-    fn symbol_value<'b>(&'b self, ir_inst: Inst) -> Option<(&'b ExternalName, RelocDistance, i64)>;
-    /// Likewise, but starting with a GlobalValue identifier.
-    fn symbol_value_data<'b>(
-        &'b self,
-        global_value: GlobalValue,
-    ) -> Option<(&'b ExternalName, RelocDistance, i64)>;
-    /// Returns the memory flags of a given memory access.
-    fn memflags(&self, ir_inst: Inst) -> Option<MemFlags>;
-    /// Get the source location for a given instruction.
-    fn srcloc(&self, ir_inst: Inst) -> SourceLoc;
-
-    // Instruction input/output queries:
-
-    /// Get the number of inputs to the given IR instruction.
-    fn num_inputs(&self, ir_inst: Inst) -> usize;
-    /// Get the number of outputs to the given IR instruction.
-    fn num_outputs(&self, ir_inst: Inst) -> usize;
-    /// Get the type for an instruction's input.
-    fn input_ty(&self, ir_inst: Inst, idx: usize) -> Type;
-    /// Get the type for a value.
-    fn value_ty(&self, val: Value) -> Type;
-    /// Get the type for an instruction's output.
-    fn output_ty(&self, ir_inst: Inst, idx: usize) -> Type;
-    /// Get the value of a constant instruction (`iconst`, etc.) as a 64-bit
-    /// value, if possible.
-    fn get_constant(&self, ir_inst: Inst) -> Option<u64>;
-    /// Get the input as one of two options other than a direct register:
-    ///
-    /// - An instruction, given that it is effect-free or able to sink its
-    ///   effect to the current instruction being lowered, and given it has only
-    ///   one output, and if effect-ful, given that this is the only use;
-    /// - A constant, if the value is a constant.
-    ///
-    /// The instruction input may be available in either of these forms.  It may
-    /// be available in neither form, if the conditions are not met; if so, use
-    /// `put_input_in_regs()` instead to get it in a register.
-    ///
-    /// If the backend merges the effect of a side-effecting instruction, it
-    /// must call `sink_inst()`. When this is called, it indicates that the
-    /// effect has been sunk to the current scan location. The sunk
-    /// instruction's result(s) must have *no* uses remaining, because it will
-    /// not be codegen'd (it has been integrated into the current instruction).
-    fn get_input_as_source_or_const(&self, ir_inst: Inst, idx: usize) -> NonRegInput;
-    /// Like `get_input_as_source_or_const` but with a `Value`.
-    fn get_value_as_source_or_const(&self, value: Value) -> NonRegInput;
-    /// Resolves a particular input of an instruction to the `Value` that it is
-    /// represented with.
-    fn input_as_value(&self, ir_inst: Inst, idx: usize) -> Value;
-    /// Put the `idx`th input into register(s) and return the assigned register.
-    fn put_input_in_regs(&mut self, ir_inst: Inst, idx: usize) -> ValueRegs<Reg>;
-    /// Put the given value into register(s) and return the assigned register.
-    fn put_value_in_regs(&mut self, value: Value) -> ValueRegs<Reg>;
-    /// Get the `idx`th output register(s) of the given IR instruction. When
-    /// `backend.lower_inst_to_regs(ctx, inst)` is called, it is expected that
-    /// the backend will write results to these output register(s).  This
-    /// register will always be "fresh"; it is guaranteed not to overlap with
-    /// any of the inputs, and can be freely used as a scratch register within
-    /// the lowered instruction sequence, as long as its final value is the
-    /// result of the computation.
-    fn get_output(&self, ir_inst: Inst, idx: usize) -> ValueRegs<Writable<Reg>>;
-
-    // Codegen primitives: allocate temps, emit instructions, set result registers,
-    // ask for an input to be gen'd into a register.
-
-    /// Get a new temp.
-    fn alloc_tmp(&mut self, ty: Type) -> ValueRegs<Writable<Reg>>;
-    /// Emit a machine instruction.
-    fn emit(&mut self, mach_inst: Self::I);
-    /// Emit a machine instruction that is a safepoint.
-    fn emit_safepoint(&mut self, mach_inst: Self::I);
-    /// Indicate that the side-effect of an instruction has been sunk to the
-    /// current scan location. This should only be done with the instruction's
-    /// original results are not used (i.e., `put_input_in_regs` is not invoked
-    /// for the input produced by the sunk instruction), otherwise the
-    /// side-effect will occur twice.
-    fn sink_inst(&mut self, ir_inst: Inst);
-    /// Retrieve constant data given a handle.
-    fn get_constant_data(&self, constant_handle: Constant) -> &ConstantData;
-    /// Indicate that a constant should be emitted.
-    fn use_constant(&mut self, constant: VCodeConstantData) -> VCodeConstant;
-    /// Retrieve the value immediate from an instruction. This will perform necessary lookups on the
-    /// `DataFlowGraph` to retrieve even large immediates.
-    fn get_immediate(&self, ir_inst: Inst) -> Option<DataValue>;
-    /// Cause the value in `reg` to be in a virtual reg, by copying it into a new virtual reg
-    /// if `reg` is a real reg.  `ty` describes the type of the value in `reg`.
-    fn ensure_in_vreg(&mut self, reg: Reg, ty: Type) -> Reg;
-}
-
-/// A representation of all of the ways in which a value is available, aside
-/// from as a direct register.
-///
-/// - An instruction, if it would be allowed to occur at the current location
-///   instead (see [LowerCtx::get_input_as_source_or_const()] for more
-///   details).
-///
-/// - A constant, if the value is known to be a constant.
-#[derive(Clone, Copy, Debug)]
-pub struct NonRegInput {
-    /// An instruction produces this value (as the given output), and its
-    /// computation (and side-effect if applicable) could occur at the
-    /// current instruction's location instead.
-    ///
-    /// If this instruction's operation is merged into the current instruction,
-    /// the backend must call [LowerCtx::sink_inst()].
-    pub inst: Option<(Inst, usize)>,
-    /// The value is a known constant.
-    pub constant: Option<u64>,
-}
-
-/// A machine backend.
-pub trait LowerBackend {
-    /// The machine instruction type.
-    type MInst: VCodeInst;
-
-    /// Lower a single instruction.
-    ///
-    /// For a branch, this function should not generate the actual branch
-    /// instruction. However, it must force any values it needs for the branch
-    /// edge (block-param actuals) into registers, because the actual branch
-    /// generation (`lower_branch_group()`) happens *after* any possible merged
-    /// out-edge.
-    fn lower<C: LowerCtx<I = Self::MInst>>(&self, ctx: &mut C, inst: Inst) -> CodegenResult<()>;
-
-    /// Lower a block-terminating group of branches (which together can be seen
-    /// as one N-way branch), given a vcode MachLabel for each target.
-    fn lower_branch_group<C: LowerCtx<I = Self::MInst>>(
-        &self,
-        ctx: &mut C,
-        insts: &[Inst],
-        targets: &[MachLabel],
-    ) -> CodegenResult<()>;
-
-    /// A bit of a hack: give a fixed register that always holds the result of a
-    /// `get_pinned_reg` instruction, if known.  This allows elision of moves
-    /// into the associated vreg, instead using the real reg directly.
-    fn maybe_pinned_reg(&self) -> Option<Reg> {
-        None
-    }
-}
-
-/// A pending instruction to insert and auxiliary information about it: its source location and
-/// whether it is a safepoint.
-struct InstTuple<I: VCodeInst> {
-    loc: SourceLoc,
-    is_safepoint: bool,
-    inst: I,
-}
-
-/// Machine-independent lowering driver / machine-instruction container. Maintains a correspondence
-/// from original Inst to MachInsts.
-pub struct Lower<'func, I: VCodeInst> {
-    /// The function to lower.
-    f: &'func Function,
-
-    /// Lowered machine instructions.
-    vcode: VCodeBuilder<I>,
-
-    /// Mapping from `Value` (SSA value in IR) to virtual register.
-    value_regs: SecondaryMap<Value, ValueRegs<Reg>>,
-
-    /// Return-value vregs.
-    retval_regs: Vec<ValueRegs<Reg>>,
-
-    /// Instruction colors at block exits. From this map, we can recover all
-    /// instruction colors by scanning backward from the block end and
-    /// decrementing on any color-changing (side-effecting) instruction.
-    block_end_colors: SecondaryMap<Block, InstColor>,
-
-    /// Instruction colors at side-effecting ops. This is the *entry* color,
-    /// i.e., the version of global state that exists before an instruction
-    /// executes.  For each side-effecting instruction, the *exit* color is its
-    /// entry color plus one.
-    side_effect_inst_entry_colors: FxHashMap<Inst, InstColor>,
-
-    /// Current color as we scan during lowering. While we are lowering an
-    /// instruction, this is equal to the color *at entry to* the instruction.
-    cur_scan_entry_color: Option<InstColor>,
-
-    /// Current instruction as we scan during lowering.
-    cur_inst: Option<Inst>,
-
-    /// Instruction constant values, if known.
-    inst_constants: FxHashMap<Inst, u64>,
-
-    /// Use-counts per SSA value, as counted in the input IR.
-    value_uses: SecondaryMap<Value, u32>,
-
-    /// Actual uses of each SSA value so far, incremented while lowering.
-    value_lowered_uses: SecondaryMap<Value, u32>,
-
-    /// Effectful instructions that have been sunk; they are not codegen'd at
-    /// their original locations.
-    inst_sunk: FxHashSet<Inst>,
-
-    /// Next virtual register number to allocate.
-    next_vreg: u32,
-
-    /// Insts in reverse block order, before final copy to vcode.
-    block_insts: Vec<InstTuple<I>>,
-
-    /// Ranges in `block_insts` constituting BBs.
-    block_ranges: Vec<(usize, usize)>,
-
-    /// Instructions collected for the BB in progress, in reverse order, with
-    /// source-locs attached.
-    bb_insts: Vec<InstTuple<I>>,
-
-    /// Instructions collected for the CLIF inst in progress, in forward order.
-    ir_insts: Vec<InstTuple<I>>,
-
-    /// The register to use for GetPinnedReg, if any, on this architecture.
-    pinned_reg: Option<Reg>,
-
-    /// The vreg containing the special VmContext parameter, if it is present in the current
-    /// function's signature.
-    vm_context: Option<Reg>,
-}
-
-/// Notion of "relocation distance". This gives an estimate of how far away a symbol will be from a
-/// reference.
-#[derive(Clone, Copy, Debug, PartialEq, Eq)]
-pub enum RelocDistance {
-    /// Target of relocation is "nearby". The threshold for this is fuzzy but should be interpreted
-    /// as approximately "within the compiled output of one module"; e.g., within AArch64's +/-
-    /// 128MB offset. If unsure, use `Far` instead.
-    Near,
-    /// Target of relocation could be anywhere in the address space.
-    Far,
-}
-
-fn alloc_vregs<I: VCodeInst>(
-    ty: Type,
-    next_vreg: &mut u32,
-    vcode: &mut VCodeBuilder<I>,
-) -> CodegenResult<ValueRegs<Reg>> {
-    let v = *next_vreg;
-    let (regclasses, tys) = I::rc_for_type(ty)?;
-    *next_vreg += regclasses.len() as u32;
-    let regs = match regclasses {
-        &[rc0] => ValueRegs::one(Reg::new_virtual(rc0, v)),
-        &[rc0, rc1] => ValueRegs::two(Reg::new_virtual(rc0, v), Reg::new_virtual(rc1, v + 1)),
-        // We can extend this if/when we support 32-bit targets; e.g.,
-        // an i128 on a 32-bit machine will need up to four machine regs
-        // for a `Value`.
-        _ => panic!("Value must reside in 1 or 2 registers"),
-    };
-    for (&reg_ty, &reg) in tys.iter().zip(regs.regs().iter()) {
-        vcode.set_vreg_type(reg.to_virtual_reg(), reg_ty);
-    }
-    Ok(regs)
-}
-
-enum GenerateReturn {
-    Yes,
-    No,
-}
-
-impl<'func, I: VCodeInst> Lower<'func, I> {
-    /// Prepare a new lowering context for the given IR function.
-    pub fn new(
-        f: &'func Function,
-        abi: Box<dyn ABICallee<I = I>>,
-        emit_info: I::Info,
-        block_order: BlockLoweringOrder,
-    ) -> CodegenResult<Lower<'func, I>> {
-        let constants = VCodeConstants::with_capacity(f.dfg.constants.len());
-        let mut vcode = VCodeBuilder::new(abi, emit_info, block_order, constants);
-
-        let mut next_vreg: u32 = 0;
-
-        let mut value_regs = SecondaryMap::with_default(ValueRegs::invalid());
-
-        // Assign a vreg to each block param and each inst result.
-        for bb in f.layout.blocks() {
-            for &param in f.dfg.block_params(bb) {
-                let ty = f.dfg.value_type(param);
-                if value_regs[param].is_invalid() {
-                    let regs = alloc_vregs(ty, &mut next_vreg, &mut vcode)?;
-                    value_regs[param] = regs;
-                    log::trace!("bb {} param {}: regs {:?}", bb, param, regs);
-                }
-            }
-            for inst in f.layout.block_insts(bb) {
-                for &result in f.dfg.inst_results(inst) {
-                    let ty = f.dfg.value_type(result);
-                    if value_regs[result].is_invalid() {
-                        let regs = alloc_vregs(ty, &mut next_vreg, &mut vcode)?;
-                        value_regs[result] = regs;
-                        log::trace!(
-                            "bb {} inst {} ({:?}): result regs {:?}",
-                            bb,
-                            inst,
-                            f.dfg[inst],
-                            regs,
-                        );
-                    }
-                }
-            }
-        }
-
-        let vm_context = vcode
-            .abi()
-            .signature()
-            .special_param_index(ArgumentPurpose::VMContext)
-            .map(|vm_context_index| {
-                let entry_block = f.layout.entry_block().unwrap();
-                let param = f.dfg.block_params(entry_block)[vm_context_index];
-                value_regs[param].only_reg().unwrap()
-            });
-
-        // Assign vreg(s) to each return value.
-        let mut retval_regs = vec![];
-        for ret in &vcode.abi().signature().returns.clone() {
-            let regs = alloc_vregs(ret.value_type, &mut next_vreg, &mut vcode)?;
-            retval_regs.push(regs);
-            log::trace!("retval gets regs {:?}", regs);
-        }
-
-        // Compute instruction colors, find constant instructions, and find instructions with
-        // side-effects, in one combined pass.
-        let mut cur_color = 0;
-        let mut block_end_colors = SecondaryMap::with_default(InstColor::new(0));
-        let mut side_effect_inst_entry_colors = FxHashMap::default();
-        let mut inst_constants = FxHashMap::default();
-        let mut value_uses = SecondaryMap::with_default(0);
-        for bb in f.layout.blocks() {
-            cur_color += 1;
-            for inst in f.layout.block_insts(bb) {
-                let side_effect = has_lowering_side_effect(f, inst);
-
-                log::trace!("bb {} inst {} has color {}", bb, inst, cur_color);
-                if side_effect {
-                    side_effect_inst_entry_colors.insert(inst, InstColor::new(cur_color));
-                    log::trace!(" -> side-effecting; incrementing color for next inst");
-                    cur_color += 1;
-                }
-
-                // Determine if this is a constant; if so, add to the table.
-                if let Some(c) = is_constant_64bit(f, inst) {
-                    log::trace!(" -> constant: {}", c);
-                    inst_constants.insert(inst, c);
-                }
-
-                // Count uses of all arguments.
-                for arg in f.dfg.inst_args(inst) {
-                    let arg = f.dfg.resolve_aliases(*arg);
-                    value_uses[arg] += 1;
-                }
-            }
-
-            block_end_colors[bb] = InstColor::new(cur_color);
-        }
-
-        Ok(Lower {
-            f,
-            vcode,
-            value_regs,
-            retval_regs,
-            block_end_colors,
-            side_effect_inst_entry_colors,
-            inst_constants,
-            next_vreg,
-            value_uses,
-            value_lowered_uses: SecondaryMap::default(),
-            inst_sunk: FxHashSet::default(),
-            cur_scan_entry_color: None,
-            cur_inst: None,
-            block_insts: vec![],
-            block_ranges: vec![],
-            bb_insts: vec![],
-            ir_insts: vec![],
-            pinned_reg: None,
-            vm_context,
-        })
-    }
-
-    fn gen_arg_setup(&mut self) {
-        if let Some(entry_bb) = self.f.layout.entry_block() {
-            log::trace!(
-                "gen_arg_setup: entry BB {} args are:\n{:?}",
-                entry_bb,
-                self.f.dfg.block_params(entry_bb)
-            );
-            for (i, param) in self.f.dfg.block_params(entry_bb).iter().enumerate() {
-                if !self.vcode.abi().arg_is_needed_in_body(i) {
-                    continue;
-                }
-                let regs = writable_value_regs(self.value_regs[*param]);
-                for insn in self.vcode.abi().gen_copy_arg_to_regs(i, regs).into_iter() {
-                    self.emit(insn);
-                }
-                if self.abi().signature().params[i].purpose == ArgumentPurpose::StructReturn {
-                    assert!(regs.len() == 1);
-                    let ty = self.abi().signature().params[i].value_type;
-                    // The ABI implementation must have ensured that a StructReturn
-                    // arg is present in the return values.
-                    let struct_ret_idx = self
-                        .abi()
-                        .signature()
-                        .returns
-                        .iter()
-                        .position(|ret| ret.purpose == ArgumentPurpose::StructReturn)
-                        .expect("StructReturn return value not present!");
-                    self.emit(I::gen_move(
-                        Writable::from_reg(self.retval_regs[struct_ret_idx].regs()[0]),
-                        regs.regs()[0].to_reg(),
-                        ty,
-                    ));
-                }
-            }
-            if let Some(insn) = self.vcode.abi().gen_retval_area_setup() {
-                self.emit(insn);
-            }
-        }
-    }
-
-    fn gen_retval_setup(&mut self, gen_ret_inst: GenerateReturn) {
-        // Hack: to keep `vmctx` alive, if it exists, we emit a value label here
-        // for it if debug info is requested. This ensures that it exists either
-        // in a register or spillslot throughout the entire function body, and
-        // allows for a better debugging experience.
-        if let Some(vmctx_val) = self.f.special_param(ArgumentPurpose::VMContext) {
-            self.emit_value_label_marks_for_value(vmctx_val);
-        }
-
-        let retval_regs = self.retval_regs.clone();
-        for (i, regs) in retval_regs.into_iter().enumerate() {
-            let regs = writable_value_regs(regs);
-            for insn in self
-                .vcode
-                .abi()
-                .gen_copy_regs_to_retval(i, regs)
-                .into_iter()
-            {
-                self.emit(insn);
-            }
-        }
-        let inst = match gen_ret_inst {
-            GenerateReturn::Yes => self.vcode.abi().gen_ret(),
-            GenerateReturn::No => self.vcode.abi().gen_epilogue_placeholder(),
-        };
-        self.emit(inst);
-    }
-
-    fn lower_edge(&mut self, pred: Block, inst: Inst, succ: Block) -> CodegenResult<()> {
-        log::trace!("lower_edge: pred {} succ {}", pred, succ);
-
-        let num_args = self.f.dfg.block_params(succ).len();
-        debug_assert!(num_args == self.f.dfg.inst_variable_args(inst).len());
-
-        // Most blocks have no params, so skip all the hoop-jumping below and make an early exit.
-        if num_args == 0 {
-            return Ok(());
-        }
-
-        self.cur_inst = Some(inst);
-
-        // Make up two vectors of info:
-        //
-        // * one for dsts which are to be assigned constants.  We'll deal with those second, so
-        //   as to minimise live ranges.
-        //
-        // * one for dsts whose sources are non-constants.
-
-        let mut const_bundles: SmallVec<[_; 16]> = SmallVec::new();
-        let mut var_bundles: SmallVec<[_; 16]> = SmallVec::new();
-
-        let mut i = 0;
-        for (dst_val, src_val) in self
-            .f
-            .dfg
-            .block_params(succ)
-            .iter()
-            .zip(self.f.dfg.inst_variable_args(inst).iter())
-        {
-            let src_val = self.f.dfg.resolve_aliases(*src_val);
-            let ty = self.f.dfg.value_type(src_val);
-
-            debug_assert!(ty == self.f.dfg.value_type(*dst_val));
-            let dst_regs = self.value_regs[*dst_val];
-
-            let input = self.get_value_as_source_or_const(src_val);
-            log::trace!("jump arg {} is {}", i, src_val);
-            i += 1;
-
-            if let Some(c) = input.constant {
-                log::trace!(" -> constant {}", c);
-                const_bundles.push((ty, writable_value_regs(dst_regs), c));
-            } else {
-                let src_regs = self.put_value_in_regs(src_val);
-                log::trace!(" -> reg {:?}", src_regs);
-                // Skip self-assignments.  Not only are they pointless, they falsely trigger the
-                // overlap-check below and hence can cause a lot of unnecessary copying through
-                // temporaries.
-                if dst_regs != src_regs {
-                    var_bundles.push((ty, writable_value_regs(dst_regs), src_regs));
-                }
-            }
-        }
-
-        // Deal first with the moves whose sources are variables.
-
-        // FIXME: use regalloc.rs' SparseSetU here.  This would avoid all heap allocation
-        // for cases of up to circa 16 args.  Currently not possible because regalloc.rs
-        // does not export it.
-        let mut src_reg_set = FxHashSet::<Reg>::default();
-        for (_, _, src_regs) in &var_bundles {
-            for &reg in src_regs.regs() {
-                src_reg_set.insert(reg);
-            }
-        }
-        let mut overlaps = false;
-        'outer: for (_, dst_regs, _) in &var_bundles {
-            for &reg in dst_regs.regs() {
-                if src_reg_set.contains(&reg.to_reg()) {
-                    overlaps = true;
-                    break 'outer;
-                }
-            }
-        }
-
-        // If, as is mostly the case, the source and destination register sets are non
-        // overlapping, then we can copy directly, so as to save the register allocator work.
-        if !overlaps {
-            for (ty, dst_regs, src_regs) in &var_bundles {
-                let (_, reg_tys) = I::rc_for_type(*ty)?;
-                for ((dst, src), reg_ty) in dst_regs
-                    .regs()
-                    .iter()
-                    .zip(src_regs.regs().iter())
-                    .zip(reg_tys.iter())
-                {
-                    self.emit(I::gen_move(*dst, *src, *reg_ty));
-                }
-            }
-        } else {
-            // There's some overlap, so play safe and copy via temps.
-            let mut tmp_regs = SmallVec::<[ValueRegs<Writable<Reg>>; 16]>::new();
-            for (ty, _, _) in &var_bundles {
-                tmp_regs.push(self.alloc_tmp(*ty));
-            }
-            for ((ty, _, src_reg), tmp_reg) in var_bundles.iter().zip(tmp_regs.iter()) {
-                let (_, reg_tys) = I::rc_for_type(*ty)?;
-                for ((tmp, src), reg_ty) in tmp_reg
-                    .regs()
-                    .iter()
-                    .zip(src_reg.regs().iter())
-                    .zip(reg_tys.iter())
-                {
-                    self.emit(I::gen_move(*tmp, *src, *reg_ty));
-                }
-            }
-            for ((ty, dst_reg, _), tmp_reg) in var_bundles.iter().zip(tmp_regs.iter()) {
-                let (_, reg_tys) = I::rc_for_type(*ty)?;
-                for ((dst, tmp), reg_ty) in dst_reg
-                    .regs()
-                    .iter()
-                    .zip(tmp_reg.regs().iter())
-                    .zip(reg_tys.iter())
-                {
-                    self.emit(I::gen_move(*dst, tmp.to_reg(), *reg_ty));
-                }
-            }
-        }
-
-        // Now, finally, deal with the moves whose sources are constants.
-        for (ty, dst_reg, const_val) in &const_bundles {
-            for inst in I::gen_constant(*dst_reg, *const_val as u128, *ty, |ty| {
-                self.alloc_tmp(ty).only_reg().unwrap()
-            })
-            .into_iter()
-            {
-                self.emit(inst);
-            }
-        }
-
-        Ok(())
-    }
-
-    /// Has this instruction been sunk to a use-site (i.e., away from its
-    /// original location)?
-    fn is_inst_sunk(&self, inst: Inst) -> bool {
-        self.inst_sunk.contains(&inst)
-    }
-
-    // Is any result of this instruction needed?
-    fn is_any_inst_result_needed(&self, inst: Inst) -> bool {
-        self.f
-            .dfg
-            .inst_results(inst)
-            .iter()
-            .any(|&result| self.value_lowered_uses[result] > 0)
-    }
-
-    fn lower_clif_block<B: LowerBackend<MInst = I>>(
-        &mut self,
-        backend: &B,
-        block: Block,
-    ) -> CodegenResult<()> {
-        self.cur_scan_entry_color = Some(self.block_end_colors[block]);
-        // Lowering loop:
-        // - For each non-branch instruction, in reverse order:
-        //   - If side-effecting (load, store, branch/call/return, possible trap), or if
-        //     used outside of this block, or if demanded by another inst, then lower.
-        //
-        // That's it! Lowering of side-effecting ops will force all *needed*
-        // (live) non-side-effecting ops to be lowered at the right places, via
-        // the `use_input_reg()` callback on the `LowerCtx` (that's us). That's
-        // because `use_input_reg()` sets the eager/demand bit for any insts
-        // whose result registers are used.
-        //
-        // We build up the BB in reverse instruction order in `bb_insts`.
-        // Because the machine backend calls `ctx.emit()` in forward order, we
-        // collect per-IR-inst lowered instructions in `ir_insts`, then reverse
-        // these and append to `bb_insts` as we go backward through the block.
-        // `bb_insts` are then reversed again and appended to the VCode at the
-        // end of the BB (in the toplevel driver `lower()`).
-        for inst in self.f.layout.block_insts(block).rev() {
-            let data = &self.f.dfg[inst];
-            let has_side_effect = has_lowering_side_effect(self.f, inst);
-            // If  inst has been sunk to another location, skip it.
-            if self.is_inst_sunk(inst) {
-                continue;
-            }
-            // Are any outputs used at least once?
-            let value_needed = self.is_any_inst_result_needed(inst);
-            log::trace!(
-                "lower_clif_block: block {} inst {} ({:?}) is_branch {} side_effect {} value_needed {}",
-                block,
-                inst,
-                data,
-                data.opcode().is_branch(),
-                has_side_effect,
-                value_needed,
-            );
-
-            // Update scan state to color prior to this inst (as we are scanning
-            // backward).
-            self.cur_inst = Some(inst);
-            if has_side_effect {
-                let entry_color = *self
-                    .side_effect_inst_entry_colors
-                    .get(&inst)
-                    .expect("every side-effecting inst should have a color-map entry");
-                self.cur_scan_entry_color = Some(entry_color);
-            }
-
-            // Skip lowering branches; these are handled separately
-            // (see `lower_clif_branches()` below).
-            if self.f.dfg[inst].opcode().is_branch() {
-                continue;
-            }
-
-            // Normal instruction: codegen if the instruction is side-effecting
-            // or any of its outputs its used.
-            if has_side_effect || value_needed {
-                log::trace!("lowering: inst {}: {:?}", inst, self.f.dfg[inst]);
-                backend.lower(self, inst)?;
-                // Emit value-label markers if needed, to later recover debug
-                // mappings.
-                self.emit_value_label_markers_for_inst(inst);
-            }
-            if data.opcode().is_return() {
-                // Return: handle specially, using ABI-appropriate sequence.
-                let gen_ret = if data.opcode() == Opcode::Return {
-                    GenerateReturn::Yes
-                } else {
-                    debug_assert!(data.opcode() == Opcode::FallthroughReturn);
-                    GenerateReturn::No
-                };
-                self.gen_retval_setup(gen_ret);
-            }
-
-            let loc = self.srcloc(inst);
-            self.finish_ir_inst(loc);
-        }
-        self.cur_scan_entry_color = None;
-        Ok(())
-    }
-
-    fn get_value_labels<'a>(&'a self, val: Value, depth: usize) -> Option<&'a [ValueLabelStart]> {
-        if let Some(ref values_labels) = self.f.dfg.values_labels {
-            log::trace!(
-                "get_value_labels: val {} -> {} -> {:?}",
-                val,
-                self.f.dfg.resolve_aliases(val),
-                values_labels.get(&self.f.dfg.resolve_aliases(val))
-            );
-            let val = self.f.dfg.resolve_aliases(val);
-            match values_labels.get(&val) {
-                Some(&ValueLabelAssignments::Starts(ref list)) => Some(&list[..]),
-                Some(&ValueLabelAssignments::Alias { value, .. }) if depth < 10 => {
-                    self.get_value_labels(value, depth + 1)
-                }
-                _ => None,
-            }
-        } else {
-            None
-        }
-    }
-
-    fn emit_value_label_marks_for_value(&mut self, val: Value) {
-        let mut markers: SmallVec<[I; 4]> = smallvec![];
-        let regs = self.value_regs[val];
-        if regs.len() > 1 {
-            return;
-        }
-        let reg = regs.only_reg().unwrap();
-
-        if let Some(label_starts) = self.get_value_labels(val, 0) {
-            let labels = label_starts
-                .iter()
-                .map(|&ValueLabelStart { label, .. }| label)
-                .collect::<FxHashSet<_>>();
-            for label in labels {
-                log::trace!(
-                    "value labeling: defines val {:?} -> reg {:?} -> label {:?}",
-                    val,
-                    reg,
-                    label,
-                );
-                markers.push(I::gen_value_label_marker(label, reg));
-            }
-        }
-        for marker in markers {
-            self.emit(marker);
-        }
-    }
-
-    fn emit_value_label_markers_for_inst(&mut self, inst: Inst) {
-        if self.f.dfg.values_labels.is_none() {
-            return;
-        }
-
-        log::trace!(
-            "value labeling: srcloc {}: inst {}",
-            self.srcloc(inst),
-            inst
-        );
-        for &val in self.f.dfg.inst_results(inst) {
-            self.emit_value_label_marks_for_value(val);
-        }
-    }
-
-    fn emit_value_label_markers_for_block_args(&mut self, block: Block) {
-        if self.f.dfg.values_labels.is_none() {
-            return;
-        }
-
-        log::trace!("value labeling: block {}", block);
-        for &arg in self.f.dfg.block_params(block) {
-            self.emit_value_label_marks_for_value(arg);
-        }
-        self.finish_ir_inst(SourceLoc::default());
-    }
-
-    fn finish_ir_inst(&mut self, loc: SourceLoc) {
-        // `bb_insts` is kept in reverse order, so emit the instructions in
-        // reverse order.
-        for mut tuple in self.ir_insts.drain(..).rev() {
-            tuple.loc = loc;
-            self.bb_insts.push(tuple);
-        }
-    }
-
-    fn finish_bb(&mut self) {
-        let start = self.block_insts.len();
-        for tuple in self.bb_insts.drain(..).rev() {
-            self.block_insts.push(tuple);
-        }
-        let end = self.block_insts.len();
-        self.block_ranges.push((start, end));
-    }
-
-    fn copy_bbs_to_vcode(&mut self) {
-        for &(start, end) in self.block_ranges.iter().rev() {
-            for &InstTuple {
-                loc,
-                is_safepoint,
-                ref inst,
-            } in &self.block_insts[start..end]
-            {
-                self.vcode.set_srcloc(loc);
-                self.vcode.push(inst.clone(), is_safepoint);
-            }
-            self.vcode.end_bb();
-        }
-    }
-
-    fn lower_clif_branches<B: LowerBackend<MInst = I>>(
-        &mut self,
-        backend: &B,
-        block: Block,
-        branches: &SmallVec<[Inst; 2]>,
-        targets: &SmallVec<[MachLabel; 2]>,
-    ) -> CodegenResult<()> {
-        log::trace!(
-            "lower_clif_branches: block {} branches {:?} targets {:?}",
-            block,
-            branches,
-            targets,
-        );
-        // When considering code-motion opportunities, consider the current
-        // program point to be the first branch.
-        self.cur_inst = Some(branches[0]);
-        backend.lower_branch_group(self, branches, targets)?;
-        let loc = self.srcloc(branches[0]);
-        self.finish_ir_inst(loc);
-        Ok(())
-    }
-
-    fn collect_branches_and_targets(
-        &self,
-        bindex: BlockIndex,
-        _bb: Block,
-        branches: &mut SmallVec<[Inst; 2]>,
-        targets: &mut SmallVec<[MachLabel; 2]>,
-    ) {
-        branches.clear();
-        targets.clear();
-        let mut last_inst = None;
-        for &(inst, succ) in self.vcode.block_order().succ_indices(bindex) {
-            // Avoid duplicates: this ensures a br_table is only inserted once.
-            if last_inst != Some(inst) {
-                branches.push(inst);
-            } else {
-                debug_assert!(self.f.dfg[inst].opcode() == Opcode::BrTable);
-                debug_assert!(branches.len() == 1);
-            }
-            last_inst = Some(inst);
-            targets.push(MachLabel::from_block(succ));
-        }
-    }
-
-    /// Lower the function.
-    pub fn lower<B: LowerBackend<MInst = I>>(
-        mut self,
-        backend: &B,
-    ) -> CodegenResult<(VCode<I>, StackmapRequestInfo)> {
-        log::trace!("about to lower function: {:?}", self.f);
-
-        // Initialize the ABI object, giving it a temp if requested.
-        let maybe_tmp = if let Some(temp_ty) = self.vcode.abi().temp_needed() {
-            Some(self.alloc_tmp(temp_ty).only_reg().unwrap())
-        } else {
-            None
-        };
-        self.vcode.abi().init(maybe_tmp);
-
-        // Get the pinned reg here (we only parameterize this function on `B`,
-        // not the whole `Lower` impl).
-        self.pinned_reg = backend.maybe_pinned_reg();
-
-        self.vcode.set_entry(0);
-
-        // Reused vectors for branch lowering.
-        let mut branches: SmallVec<[Inst; 2]> = SmallVec::new();
-        let mut targets: SmallVec<[MachLabel; 2]> = SmallVec::new();
-
-        // get a copy of the lowered order; we hold this separately because we
-        // need a mut ref to the vcode to mutate it below.
-        let lowered_order: SmallVec<[LoweredBlock; 64]> = self
-            .vcode
-            .block_order()
-            .lowered_order()
-            .iter()
-            .cloned()
-            .collect();
-
-        // Main lowering loop over lowered blocks.
-        for (bindex, lb) in lowered_order.iter().enumerate().rev() {
-            let bindex = bindex as BlockIndex;
-
-            // Lower the block body in reverse order (see comment in
-            // `lower_clif_block()` for rationale).
-
-            // End branches.
-            if let Some(bb) = lb.orig_block() {
-                self.collect_branches_and_targets(bindex, bb, &mut branches, &mut targets);
-                if branches.len() > 0 {
-                    self.lower_clif_branches(backend, bb, &branches, &targets)?;
-                    self.finish_ir_inst(self.srcloc(branches[0]));
-                }
-            } else {
-                // If no orig block, this must be a pure edge block; get the successor and
-                // emit a jump.
-                let (_, succ) = self.vcode.block_order().succ_indices(bindex)[0];
-                self.emit(I::gen_jump(MachLabel::from_block(succ)));
-                self.finish_ir_inst(SourceLoc::default());
-            }
-
-            // Out-edge phi moves.
-            if let Some((pred, inst, succ)) = lb.out_edge() {
-                self.lower_edge(pred, inst, succ)?;
-                self.finish_ir_inst(SourceLoc::default());
-            }
-            // Original block body.
-            if let Some(bb) = lb.orig_block() {
-                self.lower_clif_block(backend, bb)?;
-                self.emit_value_label_markers_for_block_args(bb);
-            }
-            // In-edge phi moves.
-            if let Some((pred, inst, succ)) = lb.in_edge() {
-                self.lower_edge(pred, inst, succ)?;
-                self.finish_ir_inst(SourceLoc::default());
-            }
-
-            if bindex == 0 {
-                // Set up the function with arg vreg inits.
-                self.gen_arg_setup();
-                self.finish_ir_inst(SourceLoc::default());
-            }
-
-            self.finish_bb();
-        }
-
-        self.copy_bbs_to_vcode();
-
-        // Now that we've emitted all instructions into the VCodeBuilder, let's build the VCode.
-        let (vcode, stack_map_info) = self.vcode.build();
-        log::trace!("built vcode: {:?}", vcode);
-
-        Ok((vcode, stack_map_info))
-    }
-}
-
-impl<'func, I: VCodeInst> LowerCtx for Lower<'func, I> {
-    type I = I;
-
-    fn dfg(&self) -> &DataFlowGraph {
-        &self.f.dfg
-    }
-
-    fn abi(&mut self) -> &mut dyn ABICallee<I = I> {
-        self.vcode.abi()
-    }
-
-    fn retval(&self, idx: usize) -> ValueRegs<Writable<Reg>> {
-        writable_value_regs(self.retval_regs[idx])
-    }
-
-    fn get_vm_context(&self) -> Option<Reg> {
-        self.vm_context
-    }
-
-    fn data(&self, ir_inst: Inst) -> &InstructionData {
-        &self.f.dfg[ir_inst]
-    }
-
-    fn ty(&self, ir_inst: Inst) -> Type {
-        self.f.dfg.ctrl_typevar(ir_inst)
-    }
-
-    fn call_target<'b>(&'b self, ir_inst: Inst) -> Option<(&'b ExternalName, RelocDistance)> {
-        match &self.f.dfg[ir_inst] {
-            &InstructionData::Call { func_ref, .. }
-            | &InstructionData::FuncAddr { func_ref, .. } => {
-                let funcdata = &self.f.dfg.ext_funcs[func_ref];
-                let dist = funcdata.reloc_distance();
-                Some((&funcdata.name, dist))
-            }
-            _ => None,
-        }
-    }
-
-    fn call_sig<'b>(&'b self, ir_inst: Inst) -> Option<&'b Signature> {
-        match &self.f.dfg[ir_inst] {
-            &InstructionData::Call { func_ref, .. } => {
-                let funcdata = &self.f.dfg.ext_funcs[func_ref];
-                Some(&self.f.dfg.signatures[funcdata.signature])
-            }
-            &InstructionData::CallIndirect { sig_ref, .. } => Some(&self.f.dfg.signatures[sig_ref]),
-            _ => None,
-        }
-    }
-
-    fn symbol_value<'b>(&'b self, ir_inst: Inst) -> Option<(&'b ExternalName, RelocDistance, i64)> {
-        match &self.f.dfg[ir_inst] {
-            &InstructionData::UnaryGlobalValue { global_value, .. } => {
-                self.symbol_value_data(global_value)
-            }
-            _ => None,
-        }
-    }
-
-    fn symbol_value_data<'b>(
-        &'b self,
-        global_value: GlobalValue,
-    ) -> Option<(&'b ExternalName, RelocDistance, i64)> {
-        let gvdata = &self.f.global_values[global_value];
-        match gvdata {
-            &GlobalValueData::Symbol {
-                ref name,
-                ref offset,
-                ..
-            } => {
-                let offset = offset.bits();
-                let dist = gvdata.maybe_reloc_distance().unwrap();
-                Some((name, dist, offset))
-            }
-            _ => None,
-        }
-    }
-
-    fn memflags(&self, ir_inst: Inst) -> Option<MemFlags> {
-        match &self.f.dfg[ir_inst] {
-            &InstructionData::AtomicCas { flags, .. } => Some(flags),
-            &InstructionData::AtomicRmw { flags, .. } => Some(flags),
-            &InstructionData::Load { flags, .. }
-            | &InstructionData::LoadComplex { flags, .. }
-            | &InstructionData::LoadNoOffset { flags, .. }
-            | &InstructionData::Store { flags, .. }
-            | &InstructionData::StoreComplex { flags, .. } => Some(flags),
-            &InstructionData::StoreNoOffset { flags, .. } => Some(flags),
-            _ => None,
-        }
-    }
-
-    fn srcloc(&self, ir_inst: Inst) -> SourceLoc {
-        self.f.srclocs[ir_inst]
-    }
-
-    fn num_inputs(&self, ir_inst: Inst) -> usize {
-        self.f.dfg.inst_args(ir_inst).len()
-    }
-
-    fn num_outputs(&self, ir_inst: Inst) -> usize {
-        self.f.dfg.inst_results(ir_inst).len()
-    }
-
-    fn input_ty(&self, ir_inst: Inst, idx: usize) -> Type {
-        self.value_ty(self.input_as_value(ir_inst, idx))
-    }
-
-    fn value_ty(&self, val: Value) -> Type {
-        self.f.dfg.value_type(val)
-    }
-
-    fn output_ty(&self, ir_inst: Inst, idx: usize) -> Type {
-        self.f.dfg.value_type(self.f.dfg.inst_results(ir_inst)[idx])
-    }
-
-    fn get_constant(&self, ir_inst: Inst) -> Option<u64> {
-        self.inst_constants.get(&ir_inst).cloned()
-    }
-
-    fn input_as_value(&self, ir_inst: Inst, idx: usize) -> Value {
-        let val = self.f.dfg.inst_args(ir_inst)[idx];
-        self.f.dfg.resolve_aliases(val)
-    }
-
-    fn get_input_as_source_or_const(&self, ir_inst: Inst, idx: usize) -> NonRegInput {
-        let val = self.input_as_value(ir_inst, idx);
-        self.get_value_as_source_or_const(val)
-    }
-
-    fn get_value_as_source_or_const(&self, val: Value) -> NonRegInput {
-        log::trace!(
-            "get_input_for_val: val {} at cur_inst {:?} cur_scan_entry_color {:?}",
-            val,
-            self.cur_inst,
-            self.cur_scan_entry_color,
-        );
-        let inst = match self.f.dfg.value_def(val) {
-            // OK to merge source instruction if (i) we have a source
-            // instruction, and:
-            // - It has no side-effects, OR
-            // - It has a side-effect, has one output value, that one output has
-            //   only one use (this one), and the instruction's color is *one less
-            //   than* the current scan color.
-            //
-            //   This latter set of conditions is testing whether a
-            //   side-effecting instruction can sink to the current scan
-            //   location; this is possible if the in-color of this inst is
-            //   equal to the out-color of the producing inst, so no other
-            //   side-effecting ops occur between them (which will only be true
-            //   if they are in the same BB, because color increments at each BB
-            //   start).
-            //
-            //   If it is actually sunk, then in `merge_inst()`, we update the
-            //   scan color so that as we scan over the range past which the
-            //   instruction was sunk, we allow other instructions (that came
-            //   prior to the sunk instruction) to sink.
-            ValueDef::Result(src_inst, result_idx) => {
-                let src_side_effect = has_lowering_side_effect(self.f, src_inst);
-                log::trace!(" -> src inst {}", src_inst);
-                log::trace!(" -> has lowering side effect: {}", src_side_effect);
-                if !src_side_effect {
-                    // Pure instruction: always possible to sink.
-                    Some((src_inst, result_idx))
-                } else {
-                    // Side-effect: test whether this is the only use of the
-                    // only result of the instruction, and whether colors allow
-                    // the code-motion.
-                    if self.cur_scan_entry_color.is_some()
-                        && self.value_uses[val] == 1
-                        && self.value_lowered_uses[val] == 0
-                        && self.num_outputs(src_inst) == 1
-                        && self
-                            .side_effect_inst_entry_colors
-                            .get(&src_inst)
-                            .unwrap()
-                            .get()
-                            + 1
-                            == self.cur_scan_entry_color.unwrap().get()
-                    {
-                        Some((src_inst, 0))
-                    } else {
-                        None
-                    }
-                }
-            }
-            _ => None,
-        };
-        let constant = inst.and_then(|(inst, _)| self.get_constant(inst));
-
-        NonRegInput { inst, constant }
-    }
-
-    fn put_input_in_regs(&mut self, ir_inst: Inst, idx: usize) -> ValueRegs<Reg> {
-        let val = self.f.dfg.inst_args(ir_inst)[idx];
-        self.put_value_in_regs(val)
-    }
-
-    fn put_value_in_regs(&mut self, val: Value) -> ValueRegs<Reg> {
-        let val = self.f.dfg.resolve_aliases(val);
-        log::trace!("put_value_in_regs: val {}", val);
-
-        // Assert that the value is not `iflags`/`fflags`-typed; these
-        // cannot be reified into normal registers. TODO(#3249)
-        // eventually remove the `iflags` type altogether!
-        let ty = self.f.dfg.value_type(val);
-        assert!(ty != IFLAGS && ty != FFLAGS);
-
-        // If the value is a constant, then (re)materialize it at each use. This
-        // lowers register pressure.
-        if let Some(c) = self
-            .f
-            .dfg
-            .value_def(val)
-            .inst()
-            .and_then(|inst| self.get_constant(inst))
-        {
-            let regs = self.alloc_tmp(ty);
-            log::trace!(" -> regs {:?}", regs);
-            assert!(regs.is_valid());
-
-            let insts = I::gen_constant(regs, c.into(), ty, |ty| {
-                self.alloc_tmp(ty).only_reg().unwrap()
-            });
-            for inst in insts {
-                self.emit(inst);
-            }
-            return non_writable_value_regs(regs);
-        }
-
-        let mut regs = self.value_regs[val];
-        log::trace!(" -> regs {:?}", regs);
-        assert!(regs.is_valid());
-
-        self.value_lowered_uses[val] += 1;
-
-        // Pinned-reg hack: if backend specifies a fixed pinned register, use it
-        // directly when we encounter a GetPinnedReg op, rather than lowering
-        // the actual op, and do not return the source inst to the caller; the
-        // value comes "out of the ether" and we will not force generation of
-        // the superfluous move.
-        if let ValueDef::Result(i, 0) = self.f.dfg.value_def(val) {
-            if self.f.dfg[i].opcode() == Opcode::GetPinnedReg {
-                if let Some(pr) = self.pinned_reg {
-                    regs = ValueRegs::one(pr);
-                }
-            }
-        }
-
-        regs
-    }
-
-    fn get_output(&self, ir_inst: Inst, idx: usize) -> ValueRegs<Writable<Reg>> {
-        let val = self.f.dfg.inst_results(ir_inst)[idx];
-        writable_value_regs(self.value_regs[val])
-    }
-
-    fn alloc_tmp(&mut self, ty: Type) -> ValueRegs<Writable<Reg>> {
-        writable_value_regs(alloc_vregs(ty, &mut self.next_vreg, &mut self.vcode).unwrap())
-    }
-
-    fn emit(&mut self, mach_inst: I) {
-        self.ir_insts.push(InstTuple {
-            loc: SourceLoc::default(),
-            is_safepoint: false,
-            inst: mach_inst,
-        });
-    }
-
-    fn emit_safepoint(&mut self, mach_inst: I) {
-        self.ir_insts.push(InstTuple {
-            loc: SourceLoc::default(),
-            is_safepoint: true,
-            inst: mach_inst,
-        });
-    }
-
-    fn sink_inst(&mut self, ir_inst: Inst) {
-        assert!(has_lowering_side_effect(self.f, ir_inst));
-        assert!(self.cur_scan_entry_color.is_some());
-
-        let sunk_inst_entry_color = self
-            .side_effect_inst_entry_colors
-            .get(&ir_inst)
-            .cloned()
-            .unwrap();
-        let sunk_inst_exit_color = InstColor::new(sunk_inst_entry_color.get() + 1);
-        assert!(sunk_inst_exit_color == self.cur_scan_entry_color.unwrap());
-        self.cur_scan_entry_color = Some(sunk_inst_entry_color);
-        self.inst_sunk.insert(ir_inst);
-    }
-
-    fn get_constant_data(&self, constant_handle: Constant) -> &ConstantData {
-        self.f.dfg.constants.get(constant_handle)
-    }
-
-    fn use_constant(&mut self, constant: VCodeConstantData) -> VCodeConstant {
-        self.vcode.constants().insert(constant)
-    }
-
-    fn get_immediate(&self, ir_inst: Inst) -> Option<DataValue> {
-        let inst_data = self.data(ir_inst);
-        match inst_data {
-            InstructionData::Shuffle { imm, .. } => {
-                let buffer = self.f.dfg.immediates.get(imm.clone()).unwrap().as_slice();
-                let value = DataValue::V128(buffer.try_into().expect("a 16-byte data buffer"));
-                Some(value)
-            }
-            InstructionData::UnaryConst {
-                constant_handle, ..
-            } => {
-                let buffer = self.f.dfg.constants.get(constant_handle.clone()).as_slice();
-                let value = DataValue::V128(buffer.try_into().expect("a 16-byte data buffer"));
-                Some(value)
-            }
-            _ => inst_data.imm_value(),
-        }
-    }
-
-    fn ensure_in_vreg(&mut self, reg: Reg, ty: Type) -> Reg {
-        if reg.is_virtual() {
-            reg
-        } else {
-            let new_reg = self.alloc_tmp(ty).only_reg().unwrap();
-            self.emit(I::gen_move(new_reg, reg, ty));
-            new_reg.to_reg()
-        }
-    }
-}
-
-/// Visit all successors of a block with a given visitor closure.
-pub(crate) fn visit_block_succs<F: FnMut(Inst, Block)>(f: &Function, block: Block, mut visit: F) {
-    for inst in f.layout.block_likely_branches(block) {
-        if f.dfg[inst].opcode().is_branch() {
-            visit_branch_targets(f, inst, &mut visit);
-        }
-    }
-}
-
-fn visit_branch_targets<F: FnMut(Inst, Block)>(f: &Function, inst: Inst, visit: &mut F) {
-    match f.dfg[inst].analyze_branch(&f.dfg.value_lists) {
-        BranchInfo::NotABranch => {}
-        BranchInfo::SingleDest(dest, _) => {
-            visit(inst, dest);
-        }
-        BranchInfo::Table(table, maybe_dest) => {
-            if let Some(dest) = maybe_dest {
-                visit(inst, dest);
-            }
-            for &dest in f.jump_tables[table].as_slice() {
-                visit(inst, dest);
-            }
-        }
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/mod.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/mod.rs
deleted file mode 100644
index e16dcce9a..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/mod.rs
+++ /dev/null
@@ -1,423 +0,0 @@
-//! This module exposes the machine-specific backend definition pieces.
-//!
-//! The MachInst infrastructure is the compiler backend, from CLIF
-//! (ir::Function) to machine code. The purpose of this infrastructure is, at a
-//! high level, to do instruction selection/lowering (to machine instructions),
-//! register allocation, and then perform all the fixups to branches, constant
-//! data references, etc., needed to actually generate machine code.
-//!
-//! The container for machine instructions, at various stages of construction,
-//! is the `VCode` struct. We refer to a sequence of machine instructions organized
-//! into basic blocks as "vcode". This is short for "virtual-register code", though
-//! it's a bit of a misnomer because near the end of the pipeline, vcode has all
-//! real registers. Nevertheless, the name is catchy and we like it.
-//!
-//! The compilation pipeline, from an `ir::Function` (already optimized as much as
-//! you like by machine-independent optimization passes) onward, is as follows.
-//! (N.B.: though we show the VCode separately at each stage, the passes
-//! mutate the VCode in place; these are not separate copies of the code.)
-//!
-//! ```plain
-//!
-//!     ir::Function                (SSA IR, machine-independent opcodes)
-//!         |
-//!         |  [lower]
-//!         |
-//!     VCode<arch_backend::Inst>   (machine instructions:
-//!         |                        - mostly virtual registers.
-//!         |                        - cond branches in two-target form.
-//!         |                        - branch targets are block indices.
-//!         |                        - in-memory constants held by insns,
-//!         |                          with unknown offsets.
-//!         |                        - critical edges (actually all edges)
-//!         |                          are split.)
-//!         | [regalloc]
-//!         |
-//!     VCode<arch_backend::Inst>   (machine instructions:
-//!         |                        - all real registers.
-//!         |                        - new instruction sequence returned
-//!         |                          out-of-band in RegAllocResult.
-//!         |                        - instruction sequence has spills,
-//!         |                          reloads, and moves inserted.
-//!         |                        - other invariants same as above.)
-//!         |
-//!         | [preamble/postamble]
-//!         |
-//!     VCode<arch_backend::Inst>   (machine instructions:
-//!         |                        - stack-frame size known.
-//!         |                        - out-of-band instruction sequence
-//!         |                          has preamble prepended to entry
-//!         |                          block, and postamble injected before
-//!         |                          every return instruction.
-//!         |                        - all symbolic stack references to
-//!         |                          stackslots and spillslots are resolved
-//!         |                          to concrete FP-offset mem addresses.)
-//!         |
-//!         | [binary emission via MachBuffer
-//!         |  with streaming branch resolution/simplification]
-//!         |
-//!     Vec<u8>                     (machine code!)
-//!
-//! ```
-
-use crate::binemit::{Addend, CodeInfo, CodeOffset, Reloc, StackMap};
-use crate::ir::{SourceLoc, StackSlot, Type, ValueLabel};
-use crate::result::CodegenResult;
-use crate::settings::Flags;
-use crate::value_label::ValueLabelsRanges;
-use alloc::boxed::Box;
-use alloc::vec::Vec;
-use core::fmt::Debug;
-use cranelift_entity::PrimaryMap;
-use regalloc::RegUsageCollector;
-use regalloc::{
-    RealReg, RealRegUniverse, Reg, RegClass, RegUsageMapper, SpillSlot, VirtualReg, Writable,
-};
-use smallvec::{smallvec, SmallVec};
-use std::string::String;
-
-#[macro_use]
-pub mod isle;
-
-pub mod lower;
-pub use lower::*;
-pub mod vcode;
-pub use vcode::*;
-pub mod compile;
-pub use compile::*;
-pub mod blockorder;
-pub use blockorder::*;
-pub mod abi;
-pub use abi::*;
-pub mod abi_impl;
-pub use abi_impl::*;
-pub mod buffer;
-pub use buffer::*;
-pub mod helpers;
-pub use helpers::*;
-pub mod inst_common;
-pub use inst_common::*;
-pub mod valueregs;
-pub use valueregs::*;
-pub mod debug;
-pub use regmapping::*;
-pub mod regmapping;
-
-/// A machine instruction.
-pub trait MachInst: Clone + Debug {
-    /// Return the registers referenced by this machine instruction along with
-    /// the modes of reference (use, def, modify).
-    fn get_regs(&self, collector: &mut RegUsageCollector);
-
-    /// Map virtual registers to physical registers using the given virt->phys
-    /// maps corresponding to the program points prior to, and after, this instruction.
-    fn map_regs<RUM: RegUsageMapper>(&mut self, maps: &RUM);
-
-    /// If this is a simple move, return the (source, destination) tuple of registers.
-    fn is_move(&self) -> Option<(Writable<Reg>, Reg)>;
-
-    /// Is this a terminator (branch or ret)? If so, return its type
-    /// (ret/uncond/cond) and target if applicable.
-    fn is_term<'a>(&'a self) -> MachTerminator<'a>;
-
-    /// Returns true if the instruction is an epilogue placeholder.
-    fn is_epilogue_placeholder(&self) -> bool;
-
-    /// Should this instruction be included in the clobber-set?
-    fn is_included_in_clobbers(&self) -> bool {
-        true
-    }
-
-    /// If this is a load or store to the stack, return that info.
-    fn stack_op_info(&self) -> Option<MachInstStackOpInfo> {
-        None
-    }
-
-    /// Generate a move.
-    fn gen_move(to_reg: Writable<Reg>, from_reg: Reg, ty: Type) -> Self;
-
-    /// Generate a constant into a reg.
-    fn gen_constant<F: FnMut(Type) -> Writable<Reg>>(
-        to_regs: ValueRegs<Writable<Reg>>,
-        value: u128,
-        ty: Type,
-        alloc_tmp: F,
-    ) -> SmallVec<[Self; 4]>;
-
-    /// Possibly operate on a value directly in a spill-slot rather than a
-    /// register. Useful if the machine has register-memory instruction forms
-    /// (e.g., add directly from or directly to memory), like x86.
-    fn maybe_direct_reload(&self, reg: VirtualReg, slot: SpillSlot) -> Option<Self>;
-
-    /// Determine register class(es) to store the given Cranelift type, and the
-    /// Cranelift type actually stored in the underlying register(s).  May return
-    /// an error if the type isn't supported by this backend.
-    ///
-    /// If the type requires multiple registers, then the list of registers is
-    /// returned in little-endian order.
-    ///
-    /// Note that the type actually stored in the register(s) may differ in the
-    /// case that a value is split across registers: for example, on a 32-bit
-    /// target, an I64 may be stored in two registers, each of which holds an
-    /// I32. The actually-stored types are used only to inform the backend when
-    /// generating spills and reloads for individual registers.
-    fn rc_for_type(ty: Type) -> CodegenResult<(&'static [RegClass], &'static [Type])>;
-
-    /// Generate a jump to another target. Used during lowering of
-    /// control flow.
-    fn gen_jump(target: MachLabel) -> Self;
-
-    /// Generate a NOP. The `preferred_size` parameter allows the caller to
-    /// request a NOP of that size, or as close to it as possible. The machine
-    /// backend may return a NOP whose binary encoding is smaller than the
-    /// preferred size, but must not return a NOP that is larger. However,
-    /// the instruction must have a nonzero size if preferred_size is nonzero.
-    fn gen_nop(preferred_size: usize) -> Self;
-
-    /// Align a basic block offset (from start of function).  By default, no
-    /// alignment occurs.
-    fn align_basic_block(offset: CodeOffset) -> CodeOffset {
-        offset
-    }
-
-    /// What is the worst-case instruction size emitted by this instruction type?
-    fn worst_case_size() -> CodeOffset;
-
-    /// What is the register class used for reference types (GC-observable pointers)? Can
-    /// be dependent on compilation flags.
-    fn ref_type_regclass(_flags: &Flags) -> RegClass;
-
-    /// Does this instruction define a ValueLabel? Returns the `Reg` whose value
-    /// becomes the new value of the `ValueLabel` after this instruction.
-    fn defines_value_label(&self) -> Option<(ValueLabel, Reg)> {
-        None
-    }
-
-    /// Create a marker instruction that defines a value label.
-    fn gen_value_label_marker(_label: ValueLabel, _reg: Reg) -> Self {
-        Self::gen_nop(0)
-    }
-
-    /// A label-use kind: a type that describes the types of label references that
-    /// can occur in an instruction.
-    type LabelUse: MachInstLabelUse;
-}
-
-/// A descriptor of a label reference (use) in an instruction set.
-pub trait MachInstLabelUse: Clone + Copy + Debug + Eq {
-    /// Required alignment for any veneer. Usually the required instruction
-    /// alignment (e.g., 4 for a RISC with 32-bit instructions, or 1 for x86).
-    const ALIGN: CodeOffset;
-
-    /// What is the maximum PC-relative range (positive)? E.g., if `1024`, a
-    /// label-reference fixup at offset `x` is valid if the label resolves to `x
-    /// + 1024`.
-    fn max_pos_range(self) -> CodeOffset;
-    /// What is the maximum PC-relative range (negative)? This is the absolute
-    /// value; i.e., if `1024`, then a label-reference fixup at offset `x` is
-    /// valid if the label resolves to `x - 1024`.
-    fn max_neg_range(self) -> CodeOffset;
-    /// What is the size of code-buffer slice this label-use needs to patch in
-    /// the label's value?
-    fn patch_size(self) -> CodeOffset;
-    /// Perform a code-patch, given the offset into the buffer of this label use
-    /// and the offset into the buffer of the label's definition.
-    /// It is guaranteed that, given `delta = offset - label_offset`, we will
-    /// have `offset >= -self.max_neg_range()` and `offset <=
-    /// self.max_pos_range()`.
-    fn patch(self, buffer: &mut [u8], use_offset: CodeOffset, label_offset: CodeOffset);
-    /// Can the label-use be patched to a veneer that supports a longer range?
-    /// Usually valid for jumps (a short-range jump can jump to a longer-range
-    /// jump), but not for e.g. constant pool references, because the constant
-    /// load would require different code (one more level of indirection).
-    fn supports_veneer(self) -> bool;
-    /// How many bytes are needed for a veneer?
-    fn veneer_size(self) -> CodeOffset;
-    /// Generate a veneer. The given code-buffer slice is `self.veneer_size()`
-    /// bytes long at offset `veneer_offset` in the buffer. The original
-    /// label-use will be patched to refer to this veneer's offset.  A new
-    /// (offset, LabelUse) is returned that allows the veneer to use the actual
-    /// label. For veneers to work properly, it is expected that the new veneer
-    /// has a larger range; on most platforms this probably means either a
-    /// "long-range jump" (e.g., on ARM, the 26-bit form), or if already at that
-    /// stage, a jump that supports a full 32-bit range, for example.
-    fn generate_veneer(self, buffer: &mut [u8], veneer_offset: CodeOffset) -> (CodeOffset, Self);
-
-    /// Returns the corresponding label-use for the relocation specified.
-    ///
-    /// This returns `None` if the relocation doesn't have a corresponding
-    /// representation for the target architecture.
-    fn from_reloc(reloc: Reloc, addend: Addend) -> Option<Self>;
-}
-
-/// Describes a block terminator (not call) in the vcode, when its branches
-/// have not yet been finalized (so a branch may have two targets).
-#[derive(Clone, Debug, PartialEq, Eq)]
-pub enum MachTerminator<'a> {
-    /// Not a terminator.
-    None,
-    /// A return instruction.
-    Ret,
-    /// An unconditional branch to another block.
-    Uncond(MachLabel),
-    /// A conditional branch to one of two other blocks.
-    Cond(MachLabel, MachLabel),
-    /// An indirect branch with known possible targets.
-    Indirect(&'a [MachLabel]),
-}
-
-impl<'a> MachTerminator<'a> {
-    /// Get the successor labels named in a `MachTerminator`.
-    pub fn get_succs(&self) -> SmallVec<[MachLabel; 2]> {
-        let mut ret = smallvec![];
-        match self {
-            &MachTerminator::Uncond(l) => {
-                ret.push(l);
-            }
-            &MachTerminator::Cond(l1, l2) => {
-                ret.push(l1);
-                ret.push(l2);
-            }
-            &MachTerminator::Indirect(ls) => {
-                ret.extend(ls.iter().cloned());
-            }
-            _ => {}
-        }
-        ret
-    }
-
-    /// Is this a terminator?
-    pub fn is_term(&self) -> bool {
-        match self {
-            MachTerminator::None => false,
-            _ => true,
-        }
-    }
-}
-
-/// A trait describing the ability to encode a MachInst into binary machine code.
-pub trait MachInstEmit: MachInst {
-    /// Persistent state carried across `emit` invocations.
-    type State: MachInstEmitState<Self>;
-    /// Constant information used in `emit` invocations.
-    type Info;
-    /// Emit the instruction.
-    fn emit(&self, code: &mut MachBuffer<Self>, info: &Self::Info, state: &mut Self::State);
-    /// Pretty-print the instruction.
-    fn pretty_print(&self, mb_rru: Option<&RealRegUniverse>, state: &mut Self::State) -> String;
-}
-
-/// A trait describing the emission state carried between MachInsts when
-/// emitting a function body.
-pub trait MachInstEmitState<I: MachInst>: Default + Clone + Debug {
-    /// Create a new emission state given the ABI object.
-    fn new(abi: &dyn ABICallee<I = I>) -> Self;
-    /// Update the emission state before emitting an instruction that is a
-    /// safepoint.
-    fn pre_safepoint(&mut self, _stack_map: StackMap) {}
-    /// Update the emission state to indicate instructions are associated with a
-    /// particular SourceLoc.
-    fn pre_sourceloc(&mut self, _srcloc: SourceLoc) {}
-}
-
-/// The result of a `MachBackend::compile_function()` call. Contains machine
-/// code (as bytes) and a disassembly, if requested.
-pub struct MachCompileResult {
-    /// Machine code.
-    pub buffer: MachBufferFinalized,
-    /// Size of stack frame, in bytes.
-    pub frame_size: u32,
-    /// Disassembly, if requested.
-    pub disasm: Option<String>,
-    /// Debug info: value labels to registers/stackslots at code offsets.
-    pub value_labels_ranges: ValueLabelsRanges,
-    /// Debug info: stackslots to stack pointer offsets.
-    pub stackslot_offsets: PrimaryMap<StackSlot, u32>,
-    /// Basic-block layout info: block start offsets.
-    ///
-    /// This info is generated only if the `machine_code_cfg_info`
-    /// flag is set.
-    pub bb_starts: Vec<CodeOffset>,
-    /// Basic-block layout info: block edges. Each edge is `(from,
-    /// to)`, where `from` and `to` are basic-block start offsets of
-    /// the respective blocks.
-    ///
-    /// This info is generated only if the `machine_code_cfg_info`
-    /// flag is set.
-    pub bb_edges: Vec<(CodeOffset, CodeOffset)>,
-}
-
-impl MachCompileResult {
-    /// Get a `CodeInfo` describing section sizes from this compilation result.
-    pub fn code_info(&self) -> CodeInfo {
-        CodeInfo {
-            total_size: self.buffer.total_size(),
-        }
-    }
-}
-
-/// An object that can be used to create the text section of an executable.
-///
-/// This primarily handles resolving relative relocations at
-/// text-section-assembly time rather than at load/link time. This
-/// architecture-specific logic is sort of like a linker, but only for one
-/// object file at a time.
-pub trait TextSectionBuilder {
-    /// Appends `data` to the text section with the `align` specified.
-    ///
-    /// If `labeled` is `true` then the offset of the final data is used to
-    /// resolve relocations in `resolve_reloc` in the future.
-    ///
-    /// This function returns the offset at which the data was placed in the
-    /// text section.
-    fn append(&mut self, labeled: bool, data: &[u8], align: u32) -> u64;
-
-    /// Attempts to resolve a relocation for this function.
-    ///
-    /// The `offset` is the offset of the relocation, within the text section.
-    /// The `reloc` is the kind of relocation.
-    /// The `addend` is the value to add to the relocation.
-    /// The `target` is the labeled function that is the target of this
-    /// relocation.
-    ///
-    /// Labeled functions are created with the `append` function above by
-    /// setting the `labeled` parameter to `true`.
-    ///
-    /// If this builder does not know how to handle `reloc` then this function
-    /// will return `false`. Otherwise this function will return `true` and this
-    /// relocation will be resolved in the final bytes returned by `finish`.
-    fn resolve_reloc(&mut self, offset: u64, reloc: Reloc, addend: Addend, target: u32) -> bool;
-
-    /// A debug-only option which is used to for
-    fn force_veneers(&mut self);
-
-    /// Completes this text section, filling out any final details, and returns
-    /// the bytes of the text section.
-    fn finish(&mut self) -> Vec<u8>;
-}
-
-/// Expected unwind info type.
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-#[non_exhaustive]
-pub enum UnwindInfoKind {
-    /// No unwind info.
-    None,
-    /// SystemV CIE/FDE unwind info.
-    #[cfg(feature = "unwind")]
-    SystemV,
-    /// Windows X64 Unwind info
-    #[cfg(feature = "unwind")]
-    Windows,
-}
-
-/// Info about an operation that loads or stores from/to the stack.
-#[derive(Clone, Copy, Debug)]
-pub enum MachInstStackOpInfo {
-    /// Load from an offset from the nominal stack pointer into the given reg.
-    LoadNomSPOff(Reg, i64),
-    /// Store to an offset from the nominal stack pointer from the given reg.
-    StoreNomSPOff(Reg, i64),
-    /// Adjustment of nominal-SP up or down. This value is added to subsequent
-    /// offsets in loads/stores above to produce real-SP offsets.
-    NomSPAdj(i64),
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/regmapping.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/regmapping.rs
deleted file mode 100644
index 4b51c426b..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/regmapping.rs
+++ /dev/null
@@ -1,108 +0,0 @@
-use crate::ir::Type;
-use regalloc::{Reg, RegUsageMapper, Writable};
-use smallvec::SmallVec;
-use std::cell::Cell;
-
-// Define our own register-mapping trait so we can do arbitrary register
-// renaming that are more free form than what `regalloc` constrains us to with
-// its `RegUsageMapper` trait definition.
-pub trait RegMapper {
-    fn get_use(&self, reg: Reg) -> Option<Reg>;
-    fn get_def(&self, reg: Reg) -> Option<Reg>;
-    fn get_mod(&self, reg: Reg) -> Option<Reg>;
-
-    fn map_use(&self, r: &mut Reg) {
-        if let Some(new) = self.get_use(*r) {
-            *r = new;
-        }
-    }
-
-    fn map_def(&self, r: &mut Writable<Reg>) {
-        if let Some(new) = self.get_def(r.to_reg()) {
-            *r = Writable::from_reg(new);
-        }
-    }
-
-    fn map_mod(&self, r: &mut Writable<Reg>) {
-        if let Some(new) = self.get_mod(r.to_reg()) {
-            *r = Writable::from_reg(new);
-        }
-    }
-}
-
-impl<T> RegMapper for T
-where
-    T: RegUsageMapper,
-{
-    fn get_use(&self, reg: Reg) -> Option<Reg> {
-        let v = reg.as_virtual_reg()?;
-        self.get_use(v).map(|r| r.to_reg())
-    }
-
-    fn get_def(&self, reg: Reg) -> Option<Reg> {
-        let v = reg.as_virtual_reg()?;
-        self.get_def(v).map(|r| r.to_reg())
-    }
-
-    fn get_mod(&self, reg: Reg) -> Option<Reg> {
-        let v = reg.as_virtual_reg()?;
-        self.get_mod(v).map(|r| r.to_reg())
-    }
-}
-
-#[derive(Debug, Default)]
-pub struct RegRenamer {
-    // Map of `(old, new, used, ty)` register names. Use a `SmallVec` because
-    // we typically only have one or two renamings.
-    //
-    // The `used` flag indicates whether the mapping has been used for
-    // `get_def`, later used afterwards during `unmapped_defs` to know what
-    // moves need to be generated.
-    renames: SmallVec<[(Reg, Reg, Cell<bool>, Type); 2]>,
-}
-
-impl RegRenamer {
-    /// Adds a new mapping which means that `old` reg should now be called
-    /// `new`. The type of `old` is `ty` as specified.
-    pub fn add_rename(&mut self, old: Reg, new: Reg, ty: Type) {
-        self.renames.push((old, new, Cell::new(false), ty));
-    }
-
-    fn get_rename(&self, reg: Reg, set_used_def: bool) -> Option<Reg> {
-        let (_, new, used_def, _) = self.renames.iter().find(|(old, _, _, _)| reg == *old)?;
-        used_def.set(used_def.get() || set_used_def);
-        Some(*new)
-    }
-
-    /// Returns the list of register mappings, with their type, which were not
-    /// actually mapped.
-    ///
-    /// This list is used because it means that the `old` name for the register
-    /// was never actually defined, so to correctly rename this register the
-    /// caller needs to move `old` into `new`.
-    ///
-    /// This yields tuples of `(old, new, ty)`.
-    pub fn unmapped_defs(&self) -> impl Iterator<Item = (Reg, Reg, Type)> + '_ {
-        self.renames.iter().filter_map(|(old, new, used_def, ty)| {
-            if used_def.get() {
-                None
-            } else {
-                Some((*old, *new, *ty))
-            }
-        })
-    }
-}
-
-impl RegMapper for RegRenamer {
-    fn get_use(&self, reg: Reg) -> Option<Reg> {
-        self.get_rename(reg, false)
-    }
-
-    fn get_def(&self, reg: Reg) -> Option<Reg> {
-        self.get_rename(reg, true)
-    }
-
-    fn get_mod(&self, reg: Reg) -> Option<Reg> {
-        self.get_rename(reg, false)
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/valueregs.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/valueregs.rs
deleted file mode 100644
index df18202cc..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/valueregs.rs
+++ /dev/null
@@ -1,130 +0,0 @@
-//! Data structure for tracking the (possibly multiple) registers that hold one
-//! SSA `Value`.
-
-use regalloc::{RealReg, Reg, VirtualReg, Writable};
-use std::fmt::Debug;
-
-const VALUE_REGS_PARTS: usize = 2;
-
-/// Location at which a `Value` is stored in register(s): the value is located
-/// in one or more registers, depending on its width. A value may be stored in
-/// more than one register if the machine has no registers wide enough
-/// otherwise: for example, on a 32-bit architecture, we may store `I64` values
-/// in two registers, and `I128` values in four.
-///
-/// By convention, the register parts are kept in machine-endian order here.
-///
-/// N.B.: we cap the capacity of this at four (when any 32-bit target is
-/// enabled) or two (otherwise), and we use special in-band sentinal `Reg`
-/// values (`Reg::invalid()`) to avoid the need to carry a separate length. This
-/// allows the struct to be `Copy` (no heap or drop overhead) and be only 16 or
-/// 8 bytes, which is important for compiler performance.
-#[derive(Clone, Copy, Debug, PartialEq, Eq)]
-pub struct ValueRegs<R: Clone + Copy + Debug + PartialEq + Eq + InvalidSentinel> {
-    parts: [R; VALUE_REGS_PARTS],
-}
-
-/// A type with an "invalid" sentinel value.
-pub trait InvalidSentinel: Copy + Eq {
-    /// The invalid sentinel value.
-    fn invalid_sentinel() -> Self;
-    /// Is this the invalid sentinel?
-    fn is_invalid_sentinel(self) -> bool {
-        self == Self::invalid_sentinel()
-    }
-}
-impl InvalidSentinel for Reg {
-    fn invalid_sentinel() -> Self {
-        Reg::invalid()
-    }
-}
-impl InvalidSentinel for VirtualReg {
-    fn invalid_sentinel() -> Self {
-        VirtualReg::invalid()
-    }
-}
-impl InvalidSentinel for RealReg {
-    fn invalid_sentinel() -> Self {
-        RealReg::invalid()
-    }
-}
-impl InvalidSentinel for Writable<Reg> {
-    fn invalid_sentinel() -> Self {
-        Writable::from_reg(Reg::invalid_sentinel())
-    }
-}
-
-impl<R: Clone + Copy + Debug + PartialEq + Eq + InvalidSentinel> ValueRegs<R> {
-    /// Create an invalid Value-in-Reg.
-    pub fn invalid() -> Self {
-        ValueRegs {
-            parts: [R::invalid_sentinel(); VALUE_REGS_PARTS],
-        }
-    }
-
-    /// Is this Value-to-Reg mapping valid?
-    pub fn is_valid(self) -> bool {
-        !self.parts[0].is_invalid_sentinel()
-    }
-    /// Is this Value-to-Reg mapping invalid?
-    pub fn is_invalid(self) -> bool {
-        self.parts[0].is_invalid_sentinel()
-    }
-
-    /// Return the single register used for this value, if any.
-    pub fn only_reg(self) -> Option<R> {
-        if self.len() == 1 {
-            Some(self.parts[0])
-        } else {
-            None
-        }
-    }
-
-    /// Return an iterator over the registers storing this value.
-    pub fn regs(&self) -> &[R] {
-        &self.parts[0..self.len()]
-    }
-}
-
-impl<R: Clone + Copy + Debug + PartialEq + Eq + InvalidSentinel> ValueRegs<R> {
-    /// Create a Value-in-R location for a value stored in one register.
-    pub fn one(reg: R) -> Self {
-        ValueRegs {
-            parts: [reg, R::invalid_sentinel()],
-        }
-    }
-    /// Create a Value-in-R location for a value stored in two registers.
-    pub fn two(r1: R, r2: R) -> Self {
-        ValueRegs { parts: [r1, r2] }
-    }
-
-    /// Return the number of registers used.
-    pub fn len(self) -> usize {
-        // If rustc/LLVM is smart enough, this might even be vectorized...
-        (self.parts[0] != R::invalid_sentinel()) as usize
-            + (self.parts[1] != R::invalid_sentinel()) as usize
-    }
-
-    /// Map individual registers via a map function.
-    pub fn map<NewR, F>(self, f: F) -> ValueRegs<NewR>
-    where
-        NewR: Clone + Copy + Debug + PartialEq + Eq + InvalidSentinel,
-        F: Fn(R) -> NewR,
-    {
-        ValueRegs {
-            parts: [f(self.parts[0]), f(self.parts[1])],
-        }
-    }
-}
-
-/// Create a writable ValueRegs.
-#[allow(dead_code)]
-pub(crate) fn writable_value_regs(regs: ValueRegs<Reg>) -> ValueRegs<Writable<Reg>> {
-    regs.map(|r| Writable::from_reg(r))
-}
-
-/// Strip a writable ValueRegs down to a readonly ValueRegs.
-#[allow(dead_code)]
-pub(crate) fn non_writable_value_regs(regs: ValueRegs<Writable<Reg>>) -> ValueRegs<Reg> {
-    regs.map(|r| r.to_reg())
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/vcode.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/vcode.rs
deleted file mode 100644
index e31c1d8ec..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/machinst/vcode.rs
+++ /dev/null
@@ -1,962 +0,0 @@
-//! This implements the VCode container: a CFG of Insts that have been lowered.
-//!
-//! VCode is virtual-register code. An instruction in VCode is almost a machine
-//! instruction; however, its register slots can refer to virtual registers in
-//! addition to real machine registers.
-//!
-//! VCode is structured with traditional basic blocks, and
-//! each block must be terminated by an unconditional branch (one target), a
-//! conditional branch (two targets), or a return (no targets). Note that this
-//! slightly differs from the machine code of most ISAs: in most ISAs, a
-//! conditional branch has one target (and the not-taken case falls through).
-//! However, we expect that machine backends will elide branches to the following
-//! block (i.e., zero-offset jumps), and will be able to codegen a branch-cond /
-//! branch-uncond pair if *both* targets are not fallthrough. This allows us to
-//! play with layout prior to final binary emission, as well, if we want.
-//!
-//! See the main module comment in `mod.rs` for more details on the VCode-based
-//! backend pipeline.
-
-use crate::ir::{self, types, Constant, ConstantData, SourceLoc};
-use crate::machinst::*;
-use crate::settings;
-use crate::timing;
-use regalloc::Function as RegallocFunction;
-use regalloc::Set as RegallocSet;
-use regalloc::{
-    BlockIx, InstIx, PrettyPrint, Range, RegAllocResult, RegClass, RegUsageCollector,
-    RegUsageMapper, SpillSlot, StackmapRequestInfo,
-};
-
-use alloc::boxed::Box;
-use alloc::{borrow::Cow, vec::Vec};
-use cranelift_entity::{entity_impl, Keys, PrimaryMap};
-use std::cell::RefCell;
-use std::collections::HashMap;
-use std::fmt;
-use std::iter;
-use std::string::String;
-
-/// Index referring to an instruction in VCode.
-pub type InsnIndex = u32;
-/// Index referring to a basic block in VCode.
-pub type BlockIndex = u32;
-
-/// VCodeInst wraps all requirements for a MachInst to be in VCode: it must be
-/// a `MachInst` and it must be able to emit itself at least to a `SizeCodeSink`.
-pub trait VCodeInst: MachInst + MachInstEmit {}
-impl<I: MachInst + MachInstEmit> VCodeInst for I {}
-
-/// A function in "VCode" (virtualized-register code) form, after lowering.
-/// This is essentially a standard CFG of basic blocks, where each basic block
-/// consists of lowered instructions produced by the machine-specific backend.
-pub struct VCode<I: VCodeInst> {
-    /// Function liveins.
-    liveins: RegallocSet<RealReg>,
-
-    /// Function liveouts.
-    liveouts: RegallocSet<RealReg>,
-
-    /// VReg IR-level types.
-    vreg_types: Vec<Type>,
-
-    /// Do we have any ref values among our vregs?
-    have_ref_values: bool,
-
-    /// Lowered machine instructions in order corresponding to the original IR.
-    insts: Vec<I>,
-
-    /// Source locations for each instruction. (`SourceLoc` is a `u32`, so it is
-    /// reasonable to keep one of these per instruction.)
-    srclocs: Vec<SourceLoc>,
-
-    /// Entry block.
-    entry: BlockIndex,
-
-    /// Block instruction indices.
-    block_ranges: Vec<(InsnIndex, InsnIndex)>,
-
-    /// Block successors: index range in the successor-list below.
-    block_succ_range: Vec<(usize, usize)>,
-
-    /// Block successor lists, concatenated into one Vec. The `block_succ_range`
-    /// list of tuples above gives (start, end) ranges within this list that
-    /// correspond to each basic block's successors.
-    block_succs: Vec<BlockIx>,
-
-    /// Block-order information.
-    block_order: BlockLoweringOrder,
-
-    /// ABI object.
-    abi: Box<dyn ABICallee<I = I>>,
-
-    /// Constant information used during code emission. This should be
-    /// immutable across function compilations within the same module.
-    emit_info: I::Info,
-
-    /// Safepoint instruction indices. Filled in post-regalloc. (Prior to
-    /// regalloc, the safepoint instructions are listed in the separate
-    /// `StackmapRequestInfo` held separate from the `VCode`.)
-    safepoint_insns: Vec<InsnIndex>,
-
-    /// For each safepoint entry in `safepoint_insns`, a list of `SpillSlot`s.
-    /// These are used to generate actual stack maps at emission. Filled in
-    /// post-regalloc.
-    safepoint_slots: Vec<Vec<SpillSlot>>,
-
-    /// Do we generate debug info?
-    generate_debug_info: bool,
-
-    /// Instruction end offsets, instruction indices at each label,
-    /// total buffer size, and start of cold code.  Only present if
-    /// `generate_debug_info` is set.
-    insts_layout: RefCell<InstsLayoutInfo>,
-
-    /// Constants.
-    constants: VCodeConstants,
-
-    /// Are any debug value-labels present? If not, we can skip the
-    /// post-emission analysis.
-    has_value_labels: bool,
-}
-
-#[derive(Debug, Default)]
-pub(crate) struct InstsLayoutInfo {
-    pub(crate) inst_end_offsets: Vec<CodeOffset>,
-    pub(crate) label_inst_indices: Vec<CodeOffset>,
-    pub(crate) start_of_cold_code: Option<CodeOffset>,
-}
-
-/// A builder for a VCode function body. This builder is designed for the
-/// lowering approach that we take: we traverse basic blocks in forward
-/// (original IR) order, but within each basic block, we generate code from
-/// bottom to top; and within each IR instruction that we visit in this reverse
-/// order, we emit machine instructions in *forward* order again.
-///
-/// Hence, to produce the final instructions in proper order, we perform two
-/// swaps.  First, the machine instructions (`I` instances) are produced in
-/// forward order for an individual IR instruction. Then these are *reversed*
-/// and concatenated to `bb_insns` at the end of the IR instruction lowering.
-/// The `bb_insns` vec will thus contain all machine instructions for a basic
-/// block, in reverse order. Finally, when we're done with a basic block, we
-/// reverse the whole block's vec of instructions again, and concatenate onto
-/// the VCode's insts.
-pub struct VCodeBuilder<I: VCodeInst> {
-    /// In-progress VCode.
-    vcode: VCode<I>,
-
-    /// In-progress stack map-request info.
-    stack_map_info: StackmapRequestInfo,
-
-    /// Index of the last block-start in the vcode.
-    block_start: InsnIndex,
-
-    /// Start of succs for the current block in the concatenated succs list.
-    succ_start: usize,
-
-    /// Current source location.
-    cur_srcloc: SourceLoc,
-}
-
-impl<I: VCodeInst> VCodeBuilder<I> {
-    /// Create a new VCodeBuilder.
-    pub fn new(
-        abi: Box<dyn ABICallee<I = I>>,
-        emit_info: I::Info,
-        block_order: BlockLoweringOrder,
-        constants: VCodeConstants,
-    ) -> VCodeBuilder<I> {
-        let reftype_class = I::ref_type_regclass(abi.flags());
-        let vcode = VCode::new(
-            abi,
-            emit_info,
-            block_order,
-            constants,
-            /* generate_debug_info = */ true,
-        );
-        let stack_map_info = StackmapRequestInfo {
-            reftype_class,
-            reftyped_vregs: vec![],
-            safepoint_insns: vec![],
-        };
-
-        VCodeBuilder {
-            vcode,
-            stack_map_info,
-            block_start: 0,
-            succ_start: 0,
-            cur_srcloc: SourceLoc::default(),
-        }
-    }
-
-    /// Access the ABI object.
-    pub fn abi(&mut self) -> &mut dyn ABICallee<I = I> {
-        &mut *self.vcode.abi
-    }
-
-    /// Access to the BlockLoweringOrder object.
-    pub fn block_order(&self) -> &BlockLoweringOrder {
-        &self.vcode.block_order
-    }
-
-    /// Set the type of a VReg.
-    pub fn set_vreg_type(&mut self, vreg: VirtualReg, ty: Type) {
-        if self.vcode.vreg_types.len() <= vreg.get_index() {
-            self.vcode
-                .vreg_types
-                .resize(vreg.get_index() + 1, ir::types::I8);
-        }
-        self.vcode.vreg_types[vreg.get_index()] = ty;
-        if is_reftype(ty) {
-            self.stack_map_info.reftyped_vregs.push(vreg);
-            self.vcode.have_ref_values = true;
-        }
-    }
-
-    /// Set the current block as the entry block.
-    pub fn set_entry(&mut self, block: BlockIndex) {
-        self.vcode.entry = block;
-    }
-
-    /// End the current basic block. Must be called after emitting vcode insts
-    /// for IR insts and prior to ending the function (building the VCode).
-    pub fn end_bb(&mut self) {
-        let start_idx = self.block_start;
-        let end_idx = self.vcode.insts.len() as InsnIndex;
-        self.block_start = end_idx;
-        // Add the instruction index range to the list of blocks.
-        self.vcode.block_ranges.push((start_idx, end_idx));
-        // End the successors list.
-        let succ_end = self.vcode.block_succs.len();
-        self.vcode
-            .block_succ_range
-            .push((self.succ_start, succ_end));
-        self.succ_start = succ_end;
-    }
-
-    /// Push an instruction for the current BB and current IR inst within the BB.
-    pub fn push(&mut self, insn: I, is_safepoint: bool) {
-        match insn.is_term() {
-            MachTerminator::None | MachTerminator::Ret => {}
-            MachTerminator::Uncond(target) => {
-                self.vcode.block_succs.push(BlockIx::new(target.get()));
-            }
-            MachTerminator::Cond(true_branch, false_branch) => {
-                self.vcode.block_succs.push(BlockIx::new(true_branch.get()));
-                self.vcode
-                    .block_succs
-                    .push(BlockIx::new(false_branch.get()));
-            }
-            MachTerminator::Indirect(targets) => {
-                for target in targets {
-                    self.vcode.block_succs.push(BlockIx::new(target.get()));
-                }
-            }
-        }
-        if insn.defines_value_label().is_some() {
-            self.vcode.has_value_labels = true;
-        }
-        self.vcode.insts.push(insn);
-        self.vcode.srclocs.push(self.cur_srcloc);
-        if is_safepoint {
-            self.stack_map_info
-                .safepoint_insns
-                .push(InstIx::new((self.vcode.insts.len() - 1) as u32));
-        }
-    }
-
-    /// Set the current source location.
-    pub fn set_srcloc(&mut self, srcloc: SourceLoc) {
-        self.cur_srcloc = srcloc;
-    }
-
-    /// Access the constants.
-    pub fn constants(&mut self) -> &mut VCodeConstants {
-        &mut self.vcode.constants
-    }
-
-    /// Build the final VCode, returning the vcode itself as well as auxiliary
-    /// information, such as the stack map request information.
-    pub fn build(self) -> (VCode<I>, StackmapRequestInfo) {
-        // TODO: come up with an abstraction for "vcode and auxiliary data". The
-        // auxiliary data needs to be separate from the vcode so that it can be
-        // referenced as the vcode is mutated (e.g. by the register allocator).
-        (self.vcode, self.stack_map_info)
-    }
-}
-
-fn is_redundant_move<I: VCodeInst>(insn: &I) -> bool {
-    if let Some((to, from)) = insn.is_move() {
-        to.to_reg() == from
-    } else {
-        false
-    }
-}
-
-/// Is this type a reference type?
-fn is_reftype(ty: Type) -> bool {
-    ty == types::R64 || ty == types::R32
-}
-
-impl<I: VCodeInst> VCode<I> {
-    /// New empty VCode.
-    fn new(
-        abi: Box<dyn ABICallee<I = I>>,
-        emit_info: I::Info,
-        block_order: BlockLoweringOrder,
-        constants: VCodeConstants,
-        generate_debug_info: bool,
-    ) -> VCode<I> {
-        VCode {
-            liveins: abi.liveins(),
-            liveouts: abi.liveouts(),
-            vreg_types: vec![],
-            have_ref_values: false,
-            insts: vec![],
-            srclocs: vec![],
-            entry: 0,
-            block_ranges: vec![],
-            block_succ_range: vec![],
-            block_succs: vec![],
-            block_order,
-            abi,
-            emit_info,
-            safepoint_insns: vec![],
-            safepoint_slots: vec![],
-            generate_debug_info,
-            insts_layout: RefCell::new(Default::default()),
-            constants,
-            has_value_labels: false,
-        }
-    }
-
-    /// Returns the flags controlling this function's compilation.
-    pub fn flags(&self) -> &settings::Flags {
-        self.abi.flags()
-    }
-
-    /// Get the IR-level type of a VReg.
-    pub fn vreg_type(&self, vreg: VirtualReg) -> Type {
-        self.vreg_types[vreg.get_index()]
-    }
-
-    /// Get the number of blocks. Block indices will be in the range `0 ..
-    /// (self.num_blocks() - 1)`.
-    pub fn num_blocks(&self) -> usize {
-        self.block_ranges.len()
-    }
-
-    /// Stack frame size for the full function's body.
-    pub fn frame_size(&self) -> u32 {
-        self.abi.frame_size()
-    }
-
-    /// Get the successors for a block.
-    pub fn succs(&self, block: BlockIndex) -> &[BlockIx] {
-        let (start, end) = self.block_succ_range[block as usize];
-        &self.block_succs[start..end]
-    }
-
-    /// Take the results of register allocation, with a sequence of
-    /// instructions including spliced fill/reload/move instructions, and replace
-    /// the VCode with them.
-    pub fn replace_insns_from_regalloc(&mut self, result: RegAllocResult<Self>) {
-        // Record the spillslot count and clobbered registers for the ABI/stack
-        // setup code.
-        self.abi.set_num_spillslots(result.num_spill_slots as usize);
-        self.abi
-            .set_clobbered(result.clobbered_registers.map(|r| Writable::from_reg(*r)));
-
-        let mut final_insns = vec![];
-        let mut final_block_ranges = vec![(0, 0); self.num_blocks()];
-        let mut final_srclocs = vec![];
-        let mut final_safepoint_insns = vec![];
-        let mut safept_idx = 0;
-
-        assert!(result.target_map.elems().len() == self.num_blocks());
-        for block in 0..self.num_blocks() {
-            let start = result.target_map.elems()[block].get() as usize;
-            let end = if block == self.num_blocks() - 1 {
-                result.insns.len()
-            } else {
-                result.target_map.elems()[block + 1].get() as usize
-            };
-            let block = block as BlockIndex;
-            let final_start = final_insns.len() as InsnIndex;
-
-            if block == self.entry {
-                // Start with the prologue.
-                let prologue = self.abi.gen_prologue();
-                let len = prologue.len();
-                final_insns.extend(prologue.into_iter());
-                final_srclocs.extend(iter::repeat(SourceLoc::default()).take(len));
-            }
-
-            for i in start..end {
-                let insn = &result.insns[i];
-
-                // Elide redundant moves at this point (we only know what is
-                // redundant once registers are allocated).
-                if is_redundant_move(insn) {
-                    continue;
-                }
-
-                // Is there a srcloc associated with this insn? Look it up based on original
-                // instruction index (if new insn corresponds to some original insn, i.e., is not
-                // an inserted load/spill/move).
-                let orig_iix = result.orig_insn_map[InstIx::new(i as u32)];
-                let srcloc = if orig_iix.is_invalid() {
-                    SourceLoc::default()
-                } else {
-                    self.srclocs[orig_iix.get() as usize]
-                };
-
-                // Whenever encountering a return instruction, replace it
-                // with the epilogue.
-                let is_ret = insn.is_term() == MachTerminator::Ret;
-                if is_ret {
-                    let epilogue = self.abi.gen_epilogue();
-                    let len = epilogue.len();
-                    final_insns.extend(epilogue.into_iter());
-                    final_srclocs.extend(iter::repeat(srcloc).take(len));
-                } else {
-                    final_insns.push(insn.clone());
-                    final_srclocs.push(srcloc);
-                }
-
-                // Was this instruction a safepoint instruction? Add its final
-                // index to the safepoint insn-index list if so.
-                if safept_idx < result.new_safepoint_insns.len()
-                    && (result.new_safepoint_insns[safept_idx].get() as usize) == i
-                {
-                    let idx = final_insns.len() - 1;
-                    final_safepoint_insns.push(idx as InsnIndex);
-                    safept_idx += 1;
-                }
-            }
-
-            let final_end = final_insns.len() as InsnIndex;
-            final_block_ranges[block as usize] = (final_start, final_end);
-        }
-
-        debug_assert!(final_insns.len() == final_srclocs.len());
-
-        self.insts = final_insns;
-        self.srclocs = final_srclocs;
-        self.block_ranges = final_block_ranges;
-        self.safepoint_insns = final_safepoint_insns;
-
-        // Save safepoint slot-lists. These will be passed to the `EmitState`
-        // for the machine backend during emission so that it can do
-        // target-specific translations of slot numbers to stack offsets.
-        self.safepoint_slots = result.stackmaps;
-    }
-
-    /// Emit the instructions to a `MachBuffer`, containing fixed-up code and external
-    /// reloc/trap/etc. records ready for use.
-    pub fn emit(
-        &self,
-    ) -> (
-        MachBuffer<I>,
-        Vec<CodeOffset>,
-        Vec<(CodeOffset, CodeOffset)>,
-    )
-    where
-        I: MachInstEmit,
-    {
-        let _tt = timing::vcode_emit();
-        let mut buffer = MachBuffer::new();
-        let mut state = I::State::new(&*self.abi);
-        let cfg_metadata = self.flags().machine_code_cfg_info();
-        let mut bb_starts: Vec<Option<CodeOffset>> = vec![];
-
-        // The first M MachLabels are reserved for block indices, the next N MachLabels for
-        // constants.
-        buffer.reserve_labels_for_blocks(self.num_blocks() as BlockIndex);
-        buffer.reserve_labels_for_constants(&self.constants);
-
-        let mut inst_end_offsets = vec![0; self.insts.len()];
-        let mut label_inst_indices = vec![0; self.num_blocks()];
-
-        // Construct the final order we emit code in: cold blocks at the end.
-        let mut final_order: SmallVec<[BlockIndex; 16]> = smallvec![];
-        let mut cold_blocks: SmallVec<[BlockIndex; 16]> = smallvec![];
-        for block in 0..self.num_blocks() {
-            let block = block as BlockIndex;
-            if self.block_order.is_cold(block) {
-                cold_blocks.push(block);
-            } else {
-                final_order.push(block);
-            }
-        }
-        let first_cold_block = cold_blocks.first().cloned();
-        final_order.extend(cold_blocks.clone());
-
-        // Emit blocks.
-        let mut safepoint_idx = 0;
-        let mut cur_srcloc = None;
-        let mut last_offset = None;
-        let mut start_of_cold_code = None;
-        for block in final_order {
-            let new_offset = I::align_basic_block(buffer.cur_offset());
-            while new_offset > buffer.cur_offset() {
-                // Pad with NOPs up to the aligned block offset.
-                let nop = I::gen_nop((new_offset - buffer.cur_offset()) as usize);
-                nop.emit(&mut buffer, &self.emit_info, &mut Default::default());
-            }
-            assert_eq!(buffer.cur_offset(), new_offset);
-
-            if Some(block) == first_cold_block {
-                start_of_cold_code = Some(buffer.cur_offset());
-            }
-
-            let (start, end) = self.block_ranges[block as usize];
-            buffer.bind_label(MachLabel::from_block(block));
-            label_inst_indices[block as usize] = start;
-
-            if cfg_metadata {
-                // Track BB starts. If we have backed up due to MachBuffer
-                // branch opts, note that the removed blocks were removed.
-                let cur_offset = buffer.cur_offset();
-                if last_offset.is_some() && cur_offset <= last_offset.unwrap() {
-                    for i in (0..bb_starts.len()).rev() {
-                        if bb_starts[i].is_some() && cur_offset > bb_starts[i].unwrap() {
-                            break;
-                        }
-                        bb_starts[i] = None;
-                    }
-                }
-                bb_starts.push(Some(cur_offset));
-                last_offset = Some(cur_offset);
-            }
-
-            for iix in start..end {
-                let srcloc = self.srclocs[iix as usize];
-                if cur_srcloc != Some(srcloc) {
-                    if cur_srcloc.is_some() {
-                        buffer.end_srcloc();
-                    }
-                    buffer.start_srcloc(srcloc);
-                    cur_srcloc = Some(srcloc);
-                }
-                state.pre_sourceloc(cur_srcloc.unwrap_or(SourceLoc::default()));
-
-                if safepoint_idx < self.safepoint_insns.len()
-                    && self.safepoint_insns[safepoint_idx] == iix
-                {
-                    if self.safepoint_slots[safepoint_idx].len() > 0 {
-                        let stack_map = self.abi.spillslots_to_stack_map(
-                            &self.safepoint_slots[safepoint_idx][..],
-                            &state,
-                        );
-                        state.pre_safepoint(stack_map);
-                    }
-                    safepoint_idx += 1;
-                }
-
-                self.insts[iix as usize].emit(&mut buffer, &self.emit_info, &mut state);
-
-                if self.generate_debug_info {
-                    // Buffer truncation may have happened since last inst append; trim inst-end
-                    // layout info as appropriate.
-                    let l = &mut inst_end_offsets[0..iix as usize];
-                    for end in l.iter_mut().rev() {
-                        if *end > buffer.cur_offset() {
-                            *end = buffer.cur_offset();
-                        } else {
-                            break;
-                        }
-                    }
-                    inst_end_offsets[iix as usize] = buffer.cur_offset();
-                }
-            }
-
-            if cur_srcloc.is_some() {
-                buffer.end_srcloc();
-                cur_srcloc = None;
-            }
-
-            // Do we need an island? Get the worst-case size of the next BB and see if, having
-            // emitted that many bytes, we will be beyond the deadline.
-            if block < (self.num_blocks() - 1) as BlockIndex {
-                let next_block = block + 1;
-                let next_block_range = self.block_ranges[next_block as usize];
-                let next_block_size = next_block_range.1 - next_block_range.0;
-                let worst_case_next_bb = I::worst_case_size() * next_block_size;
-                if buffer.island_needed(worst_case_next_bb) {
-                    buffer.emit_island(worst_case_next_bb);
-                }
-            }
-        }
-
-        // Emit the constants used by the function.
-        for (constant, data) in self.constants.iter() {
-            let label = buffer.get_label_for_constant(constant);
-            buffer.defer_constant(label, data.alignment(), data.as_slice(), u32::max_value());
-        }
-
-        if self.generate_debug_info {
-            for end in inst_end_offsets.iter_mut().rev() {
-                if *end > buffer.cur_offset() {
-                    *end = buffer.cur_offset();
-                } else {
-                    break;
-                }
-            }
-            *self.insts_layout.borrow_mut() = InstsLayoutInfo {
-                inst_end_offsets,
-                label_inst_indices,
-                start_of_cold_code,
-            };
-        }
-
-        // Create `bb_edges` and final (filtered) `bb_starts`.
-        let mut final_bb_starts = vec![];
-        let mut bb_edges = vec![];
-        if cfg_metadata {
-            for block in 0..self.num_blocks() {
-                if bb_starts[block].is_none() {
-                    // Block was deleted by MachBuffer; skip.
-                    continue;
-                }
-                let from = bb_starts[block].unwrap();
-
-                final_bb_starts.push(from);
-                // Resolve each `succ` label and add edges.
-                let succs = self.block_succs(BlockIx::new(block as u32));
-                for succ in succs.iter() {
-                    let to = buffer.resolve_label_offset(MachLabel::from_block(succ.get()));
-                    bb_edges.push((from, to));
-                }
-            }
-        }
-
-        (buffer, final_bb_starts, bb_edges)
-    }
-
-    /// Generates value-label ranges.
-    pub fn value_labels_ranges(&self) -> ValueLabelsRanges {
-        if !self.has_value_labels {
-            return ValueLabelsRanges::default();
-        }
-
-        let layout_info = &self.insts_layout.borrow();
-        debug::compute(&self.insts, &*layout_info)
-    }
-
-    /// Get the offsets of stackslots.
-    pub fn stackslot_offsets(&self) -> &PrimaryMap<StackSlot, u32> {
-        self.abi.stackslot_offsets()
-    }
-
-    /// Get the IR block for a BlockIndex, if one exists.
-    pub fn bindex_to_bb(&self, block: BlockIndex) -> Option<ir::Block> {
-        self.block_order.lowered_order()[block as usize].orig_block()
-    }
-}
-
-impl<I: VCodeInst> RegallocFunction for VCode<I> {
-    type Inst = I;
-
-    fn insns(&self) -> &[I] {
-        &self.insts[..]
-    }
-
-    fn insns_mut(&mut self) -> &mut [I] {
-        &mut self.insts[..]
-    }
-
-    fn get_insn(&self, insn: InstIx) -> &I {
-        &self.insts[insn.get() as usize]
-    }
-
-    fn get_insn_mut(&mut self, insn: InstIx) -> &mut I {
-        &mut self.insts[insn.get() as usize]
-    }
-
-    fn blocks(&self) -> Range<BlockIx> {
-        Range::new(BlockIx::new(0), self.block_ranges.len())
-    }
-
-    fn entry_block(&self) -> BlockIx {
-        BlockIx::new(self.entry)
-    }
-
-    fn block_insns(&self, block: BlockIx) -> Range<InstIx> {
-        let (start, end) = self.block_ranges[block.get() as usize];
-        Range::new(InstIx::new(start), (end - start) as usize)
-    }
-
-    fn block_succs(&self, block: BlockIx) -> Cow<[BlockIx]> {
-        let (start, end) = self.block_succ_range[block.get() as usize];
-        Cow::Borrowed(&self.block_succs[start..end])
-    }
-
-    fn is_ret(&self, insn: InstIx) -> bool {
-        match self.insts[insn.get() as usize].is_term() {
-            MachTerminator::Ret => true,
-            _ => false,
-        }
-    }
-
-    fn is_included_in_clobbers(&self, insn: &I) -> bool {
-        insn.is_included_in_clobbers()
-    }
-
-    fn get_regs(insn: &I, collector: &mut RegUsageCollector) {
-        insn.get_regs(collector)
-    }
-
-    fn map_regs<RUM: RegUsageMapper>(insn: &mut I, mapper: &RUM) {
-        insn.map_regs(mapper);
-    }
-
-    fn is_move(&self, insn: &I) -> Option<(Writable<Reg>, Reg)> {
-        insn.is_move()
-    }
-
-    fn get_num_vregs(&self) -> usize {
-        self.vreg_types.len()
-    }
-
-    fn get_spillslot_size(&self, regclass: RegClass, _: VirtualReg) -> u32 {
-        self.abi.get_spillslot_size(regclass)
-    }
-
-    fn gen_spill(&self, to_slot: SpillSlot, from_reg: RealReg, _: Option<VirtualReg>) -> I {
-        self.abi.gen_spill(to_slot, from_reg)
-    }
-
-    fn gen_reload(
-        &self,
-        to_reg: Writable<RealReg>,
-        from_slot: SpillSlot,
-        _: Option<VirtualReg>,
-    ) -> I {
-        self.abi.gen_reload(to_reg, from_slot)
-    }
-
-    fn gen_move(&self, to_reg: Writable<RealReg>, from_reg: RealReg, vreg: VirtualReg) -> I {
-        let ty = self.vreg_type(vreg);
-        I::gen_move(to_reg.map(|r| r.to_reg()), from_reg.to_reg(), ty)
-    }
-
-    fn gen_zero_len_nop(&self) -> I {
-        I::gen_nop(0)
-    }
-
-    fn maybe_direct_reload(&self, insn: &I, reg: VirtualReg, slot: SpillSlot) -> Option<I> {
-        insn.maybe_direct_reload(reg, slot)
-    }
-
-    fn func_liveins(&self) -> RegallocSet<RealReg> {
-        self.liveins.clone()
-    }
-
-    fn func_liveouts(&self) -> RegallocSet<RealReg> {
-        self.liveouts.clone()
-    }
-}
-
-impl<I: VCodeInst> fmt::Debug for VCode<I> {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        writeln!(f, "VCode_Debug {{")?;
-        writeln!(f, "  Entry block: {}", self.entry)?;
-
-        for block in 0..self.num_blocks() {
-            writeln!(f, "Block {}:", block,)?;
-            for succ in self.succs(block as BlockIndex) {
-                writeln!(f, "  (successor: Block {})", succ.get())?;
-            }
-            let (start, end) = self.block_ranges[block];
-            writeln!(f, "  (instruction range: {} .. {})", start, end)?;
-            for inst in start..end {
-                writeln!(f, "  Inst {}: {:?}", inst, self.insts[inst as usize])?;
-            }
-        }
-
-        writeln!(f, "}}")?;
-        Ok(())
-    }
-}
-
-/// Pretty-printing with `RealRegUniverse` context.
-impl<I: VCodeInst> PrettyPrint for VCode<I> {
-    fn show_rru(&self, mb_rru: Option<&RealRegUniverse>) -> String {
-        use std::fmt::Write;
-
-        let mut s = String::new();
-        write!(&mut s, "VCode_ShowWithRRU {{{{\n").unwrap();
-        write!(&mut s, "  Entry block: {}\n", self.entry).unwrap();
-
-        let mut state = Default::default();
-        let mut safepoint_idx = 0;
-        for i in 0..self.num_blocks() {
-            let block = i as BlockIndex;
-
-            write!(&mut s, "Block {}:\n", block).unwrap();
-            if let Some(bb) = self.bindex_to_bb(block) {
-                write!(&mut s, "  (original IR block: {})\n", bb).unwrap();
-            }
-            for succ in self.succs(block) {
-                write!(&mut s, "  (successor: Block {})\n", succ.get()).unwrap();
-            }
-            let (start, end) = self.block_ranges[block as usize];
-            write!(&mut s, "  (instruction range: {} .. {})\n", start, end).unwrap();
-            for inst in start..end {
-                if safepoint_idx < self.safepoint_insns.len()
-                    && self.safepoint_insns[safepoint_idx] == inst
-                {
-                    write!(
-                        &mut s,
-                        "      (safepoint: slots {:?} with EmitState {:?})\n",
-                        self.safepoint_slots[safepoint_idx], state,
-                    )
-                    .unwrap();
-                    safepoint_idx += 1;
-                }
-                write!(
-                    &mut s,
-                    "  Inst {}:   {}\n",
-                    inst,
-                    self.insts[inst as usize].pretty_print(mb_rru, &mut state)
-                )
-                .unwrap();
-            }
-        }
-
-        write!(&mut s, "}}}}\n").unwrap();
-
-        s
-    }
-}
-
-/// This structure tracks the large constants used in VCode that will be emitted separately by the
-/// [MachBuffer].
-///
-/// First, during the lowering phase, constants are inserted using
-/// [VCodeConstants.insert]; an intermediate handle, [VCodeConstant], tracks what constants are
-/// used in this phase. Some deduplication is performed, when possible, as constant
-/// values are inserted.
-///
-/// Secondly, during the emission phase, the [MachBuffer] assigns [MachLabel]s for each of the
-/// constants so that instructions can refer to the value's memory location. The [MachBuffer]
-/// then writes the constant values to the buffer.
-#[derive(Default)]
-pub struct VCodeConstants {
-    constants: PrimaryMap<VCodeConstant, VCodeConstantData>,
-    pool_uses: HashMap<Constant, VCodeConstant>,
-    well_known_uses: HashMap<*const [u8], VCodeConstant>,
-}
-impl VCodeConstants {
-    /// Initialize the structure with the expected number of constants.
-    pub fn with_capacity(expected_num_constants: usize) -> Self {
-        Self {
-            constants: PrimaryMap::with_capacity(expected_num_constants),
-            pool_uses: HashMap::with_capacity(expected_num_constants),
-            well_known_uses: HashMap::new(),
-        }
-    }
-
-    /// Insert a constant; using this method indicates that a constant value will be used and thus
-    /// will be emitted to the `MachBuffer`. The current implementation can deduplicate constants
-    /// that are [VCodeConstantData::Pool] or [VCodeConstantData::WellKnown] but not
-    /// [VCodeConstantData::Generated].
-    pub fn insert(&mut self, data: VCodeConstantData) -> VCodeConstant {
-        match data {
-            VCodeConstantData::Generated(_) => self.constants.push(data),
-            VCodeConstantData::Pool(constant, _) => match self.pool_uses.get(&constant) {
-                None => {
-                    let vcode_constant = self.constants.push(data);
-                    self.pool_uses.insert(constant, vcode_constant);
-                    vcode_constant
-                }
-                Some(&vcode_constant) => vcode_constant,
-            },
-            VCodeConstantData::WellKnown(data_ref) => {
-                match self.well_known_uses.get(&(data_ref as *const [u8])) {
-                    None => {
-                        let vcode_constant = self.constants.push(data);
-                        self.well_known_uses
-                            .insert(data_ref as *const [u8], vcode_constant);
-                        vcode_constant
-                    }
-                    Some(&vcode_constant) => vcode_constant,
-                }
-            }
-        }
-    }
-
-    /// Return the number of constants inserted.
-    pub fn len(&self) -> usize {
-        self.constants.len()
-    }
-
-    /// Iterate over the [VCodeConstant] keys inserted in this structure.
-    pub fn keys(&self) -> Keys<VCodeConstant> {
-        self.constants.keys()
-    }
-
-    /// Iterate over the [VCodeConstant] keys and the data (as a byte slice) inserted in this
-    /// structure.
-    pub fn iter(&self) -> impl Iterator<Item = (VCodeConstant, &VCodeConstantData)> {
-        self.constants.iter()
-    }
-}
-
-/// A use of a constant by one or more VCode instructions; see [VCodeConstants].
-#[derive(Clone, Copy, Debug, PartialEq, Eq)]
-pub struct VCodeConstant(u32);
-entity_impl!(VCodeConstant);
-
-/// Identify the different types of constant that can be inserted into [VCodeConstants]. Tracking
-/// these separately instead of as raw byte buffers allows us to avoid some duplication.
-pub enum VCodeConstantData {
-    /// A constant already present in the Cranelift IR
-    /// [ConstantPool](crate::ir::constant::ConstantPool).
-    Pool(Constant, ConstantData),
-    /// A reference to a well-known constant value that is statically encoded within the compiler.
-    WellKnown(&'static [u8]),
-    /// A constant value generated during lowering; the value may depend on the instruction context
-    /// which makes it difficult to de-duplicate--if possible, use other variants.
-    Generated(ConstantData),
-}
-impl VCodeConstantData {
-    /// Retrieve the constant data as a byte slice.
-    pub fn as_slice(&self) -> &[u8] {
-        match self {
-            VCodeConstantData::Pool(_, d) | VCodeConstantData::Generated(d) => d.as_slice(),
-            VCodeConstantData::WellKnown(d) => d,
-        }
-    }
-
-    /// Calculate the alignment of the constant data.
-    pub fn alignment(&self) -> u32 {
-        if self.as_slice().len() <= 8 {
-            8
-        } else {
-            16
-        }
-    }
-}
-
-#[cfg(test)]
-mod test {
-    use super::*;
-    use std::mem::size_of;
-
-    #[test]
-    fn size_of_constant_structs() {
-        assert_eq!(size_of::<Constant>(), 4);
-        assert_eq!(size_of::<VCodeConstant>(), 4);
-        assert_eq!(size_of::<ConstantData>(), 24);
-        assert_eq!(size_of::<VCodeConstantData>(), 32);
-        assert_eq!(
-            size_of::<PrimaryMap<VCodeConstant, VCodeConstantData>>(),
-            24
-        );
-        // TODO The VCodeConstants structure's memory size could be further optimized.
-        // With certain versions of Rust, each `HashMap` in `VCodeConstants` occupied at
-        // least 48 bytes, making an empty `VCodeConstants` cost 120 bytes.
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/nan_canonicalization.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/nan_canonicalization.rs
deleted file mode 100644
index 107985e27..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/nan_canonicalization.rs
+++ /dev/null
@@ -1,106 +0,0 @@
-//! A NaN-canonicalizing rewriting pass. Patch floating point arithmetic
-//! instructions that may return a NaN result with a sequence of operations
-//! that will replace nondeterministic NaN's with a single canonical NaN value.
-
-use crate::cursor::{Cursor, FuncCursor};
-use crate::ir::condcodes::FloatCC;
-use crate::ir::immediates::{Ieee32, Ieee64};
-use crate::ir::types;
-use crate::ir::{Function, Inst, InstBuilder, InstructionData, Opcode, Value};
-use crate::timing;
-
-// Canonical 32-bit and 64-bit NaN values.
-static CANON_32BIT_NAN: u32 = 0b01111111110000000000000000000000;
-static CANON_64BIT_NAN: u64 = 0b0111111111111000000000000000000000000000000000000000000000000000;
-
-/// Perform the NaN canonicalization pass.
-pub fn do_nan_canonicalization(func: &mut Function) {
-    let _tt = timing::canonicalize_nans();
-    let mut pos = FuncCursor::new(func);
-    while let Some(_block) = pos.next_block() {
-        while let Some(inst) = pos.next_inst() {
-            if is_fp_arith(&mut pos, inst) {
-                add_nan_canon_seq(&mut pos, inst);
-            }
-        }
-    }
-}
-
-/// Returns true/false based on whether the instruction is a floating-point
-/// arithmetic operation. This ignores operations like `fneg`, `fabs`, or
-/// `fcopysign` that only operate on the sign bit of a floating point value.
-fn is_fp_arith(pos: &mut FuncCursor, inst: Inst) -> bool {
-    match pos.func.dfg[inst] {
-        InstructionData::Unary { opcode, .. } => {
-            opcode == Opcode::Ceil
-                || opcode == Opcode::Floor
-                || opcode == Opcode::Nearest
-                || opcode == Opcode::Sqrt
-                || opcode == Opcode::Trunc
-        }
-        InstructionData::Binary { opcode, .. } => {
-            opcode == Opcode::Fadd
-                || opcode == Opcode::Fdiv
-                || opcode == Opcode::Fmax
-                || opcode == Opcode::Fmin
-                || opcode == Opcode::Fmul
-                || opcode == Opcode::Fsub
-        }
-        InstructionData::Ternary { opcode, .. } => opcode == Opcode::Fma,
-        _ => false,
-    }
-}
-
-/// Append a sequence of canonicalizing instructions after the given instruction.
-fn add_nan_canon_seq(pos: &mut FuncCursor, inst: Inst) {
-    // Select the instruction result, result type. Replace the instruction
-    // result and step forward before inserting the canonicalization sequence.
-    let val = pos.func.dfg.first_result(inst);
-    let val_type = pos.func.dfg.value_type(val);
-    let new_res = pos.func.dfg.replace_result(val, val_type);
-    let _next_inst = pos.next_inst().expect("block missing terminator!");
-
-    // Insert a comparison instruction, to check if `inst_res` is NaN. Select
-    // the canonical NaN value if `val` is NaN, assign the result to `inst`.
-    let is_nan = pos.ins().fcmp(FloatCC::NotEqual, new_res, new_res);
-
-    let scalar_select = |pos: &mut FuncCursor, canon_nan: Value| {
-        pos.ins()
-            .with_result(val)
-            .select(is_nan, canon_nan, new_res);
-    };
-    let vector_select = |pos: &mut FuncCursor, canon_nan: Value| {
-        let cond = pos.ins().raw_bitcast(types::I8X16, is_nan);
-        let canon_nan = pos.ins().raw_bitcast(types::I8X16, canon_nan);
-        let result = pos.ins().raw_bitcast(types::I8X16, new_res);
-        let bitmask = pos.ins().bitselect(cond, canon_nan, result);
-        pos.ins().with_result(val).raw_bitcast(val_type, bitmask);
-    };
-
-    match val_type {
-        types::F32 => {
-            let canon_nan = pos.ins().f32const(Ieee32::with_bits(CANON_32BIT_NAN));
-            scalar_select(pos, canon_nan);
-        }
-        types::F64 => {
-            let canon_nan = pos.ins().f64const(Ieee64::with_bits(CANON_64BIT_NAN));
-            scalar_select(pos, canon_nan);
-        }
-        types::F32X4 => {
-            let canon_nan = pos.ins().iconst(types::I32, i64::from(CANON_32BIT_NAN));
-            let canon_nan = pos.ins().splat(types::I32X4, canon_nan);
-            vector_select(pos, canon_nan);
-        }
-        types::F64X2 => {
-            let canon_nan = pos.ins().iconst(types::I64, CANON_64BIT_NAN as i64);
-            let canon_nan = pos.ins().splat(types::I64X2, canon_nan);
-            vector_select(pos, canon_nan);
-        }
-        _ => {
-            // Panic if the type given was not an IEEE floating point type.
-            panic!("Could not canonicalize NaN: Unexpected result type found.");
-        }
-    }
-
-    pos.prev_inst(); // Step backwards so the pass does not skip instructions.
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/prelude.isle b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/prelude.isle
deleted file mode 100644
index 397c5b0b8..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/prelude.isle
+++ /dev/null
@@ -1,562 +0,0 @@
-;; This is a prelude of standard definitions for ISLE, the instruction-selector
-;; DSL, as we use it bound to our interfaces.
-;;
-;; Note that all `extern` functions here are typically defined in the
-;; `isle_prelude_methods` macro defined in `src/isa/isle.rs`
-
-;;;; Primitive and External Types ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; `()`
-(type Unit (primitive Unit))
-
-;; `bool` is declared in `clif.isle`.
-(extern const $true bool)
-(extern const $false bool)
-
-(type u8 (primitive u8))
-(type u16 (primitive u16))
-(type u32 (primitive u32))
-(type u64 (primitive u64))
-(type u128 (primitive u128))
-(type usize (primitive usize))
-
-(type i8 (primitive i8))
-(type i16 (primitive i16))
-(type i32 (primitive i32))
-(type i64 (primitive i64))
-(type i128 (primitive i128))
-(type isize (primitive isize))
-
-;; `cranelift-entity`-based identifiers.
-(type Inst (primitive Inst))
-(type Type (primitive Type))
-(type Value (primitive Value))
-
-;; ISLE representation of `&[Value]`.
-(type ValueSlice (primitive ValueSlice))
-
-(type ValueList (primitive ValueList))
-(type ValueRegs (primitive ValueRegs))
-
-;; Instruction lowering result: a vector of `ValueRegs`.
-(type InstOutput (primitive InstOutput))
-;; (Mutable) builder to incrementally construct an `InstOutput`.
-(type InstOutputBuilder extern (enum))
-
-(decl u32_add (u32 u32) u32)
-(extern constructor u32_add u32_add)
-
-(decl u8_and (u8 u8) u8)
-(extern constructor u8_and u8_and)
-
-;;;; Registers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(type Reg (primitive Reg))
-(type WritableReg (primitive WritableReg))
-(type OptionWritableReg (primitive OptionWritableReg))
-(type VecReg extern (enum))
-(type VecWritableReg extern (enum))
-
-;; Construct a `ValueRegs` of one register.
-(decl value_reg (Reg) ValueRegs)
-(extern constructor value_reg value_reg)
-
-;; Construct a `ValueRegs` of two registers.
-(decl value_regs (Reg Reg) ValueRegs)
-(extern constructor value_regs value_regs)
-
-;; Construct an empty `ValueRegs` containing only invalid register sentinels.
-(decl value_regs_invalid () ValueRegs)
-(extern constructor value_regs_invalid value_regs_invalid)
-
-;; Construct an empty `InstOutput`.
-(decl output_none () InstOutput)
-(extern constructor output_none output_none)
-
-;; Construct a single-element `InstOutput`.
-(decl output (ValueRegs) InstOutput)
-(extern constructor output output)
-
-;; Construct a two-element `InstOutput`.
-(decl output_pair (ValueRegs ValueRegs) InstOutput)
-(extern constructor output_pair output_pair)
-
-;; Construct a single-element `InstOutput` from a single register.
-(decl output_reg (Reg) InstOutput)
-(rule (output_reg reg) (output (value_reg reg)))
-
-;; Construct a single-element `InstOutput` from a value.
-(decl output_value (Value) InstOutput)
-(rule (output_value val) (output (put_in_regs val)))
-
-;; Initially empty `InstOutput` builder.
-(decl output_builder_new () InstOutputBuilder)
-(extern constructor output_builder_new output_builder_new)
-
-;; Append a `ValueRegs` to an `InstOutput` under construction.
-(decl output_builder_push (InstOutputBuilder ValueRegs) Unit)
-(extern constructor output_builder_push output_builder_push)
-
-;; Finish building an `InstOutput` incrementally.
-(decl output_builder_finish (InstOutputBuilder) InstOutput)
-(extern constructor output_builder_finish output_builder_finish)
-
-;; Get a temporary register for writing.
-(decl temp_writable_reg (Type) WritableReg)
-(extern constructor temp_writable_reg temp_writable_reg)
-
-;; Get a temporary register for reading.
-(decl temp_reg (Type) Reg)
-(rule (temp_reg ty)
-      (writable_reg_to_reg (temp_writable_reg ty)))
-
-;; Get the invalid register.
-(decl invalid_reg () Reg)
-(extern constructor invalid_reg invalid_reg)
-
-;; Put the given value into a register.
-;;
-;; Asserts that the value fits into a single register, and doesn't require
-;; multiple registers for its representation (like `i128` on x64 for example).
-;;
-;; As a side effect, this marks the value as used.
-(decl put_in_reg (Value) Reg)
-(extern constructor put_in_reg put_in_reg)
-
-;; Put the given value into one or more registers.
-;;
-;; As a side effect, this marks the value as used.
-(decl put_in_regs (Value) ValueRegs)
-(extern constructor put_in_regs put_in_regs)
-
-;; Get the `n`th register inside a `ValueRegs`.
-(decl value_regs_get (ValueRegs usize) Reg)
-(extern constructor value_regs_get value_regs_get)
-
-;; Put the value into one or more registers and return the first register.
-;;
-;; Unlike `put_in_reg`, this does not assert that the value fits in a single
-;; register. This is useful for things like a `i128` shift amount, where we mask
-;; the shift amount to the bit width of the value being shifted, and so the high
-;; half of the `i128` won't ever be used.
-;;
-;; As a side efect, this marks that value as used.
-(decl lo_reg (Value) Reg)
-(rule (lo_reg val)
-      (let ((regs ValueRegs (put_in_regs val)))
-        (value_regs_get regs 0)))
-
-;;;; Common Mach Types ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(type MachLabel (primitive MachLabel))
-(type VecMachLabel extern (enum))
-(type ValueLabel (primitive ValueLabel))
-(type UnwindInst (primitive UnwindInst))
-(type ExternalName (primitive ExternalName))
-(type BoxExternalName (primitive BoxExternalName))
-(type RelocDistance (primitive RelocDistance))
-
-;;;; Primitive Type Conversions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl u8_as_u64 (u8) u64)
-(extern constructor u8_as_u64 u8_as_u64)
-
-(decl u16_as_u64 (u16) u64)
-(extern constructor u16_as_u64 u16_as_u64)
-
-(decl u32_as_u64 (u32) u64)
-(extern constructor u32_as_u64 u32_as_u64)
-
-(decl i64_as_u64 (i64) u64)
-(extern constructor i64_as_u64 i64_as_u64)
-
-;;;; Primitive Arithmetic ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl u64_add (u64 u64) u64)
-(extern constructor u64_add u64_add)
-
-(decl u64_sub (u64 u64) u64)
-(extern constructor u64_sub u64_sub)
-
-(decl u64_and (u64 u64) u64)
-(extern constructor u64_and u64_and)
-
-;;;; `cranelift_codegen::ir::Type` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(extern const $B1 Type)
-(extern const $B8 Type)
-(extern const $B16 Type)
-(extern const $B32 Type)
-(extern const $B64 Type)
-(extern const $B128 Type)
-
-(extern const $I8 Type)
-(extern const $I16 Type)
-(extern const $I32 Type)
-(extern const $I64 Type)
-(extern const $I128 Type)
-
-(extern const $R32 Type)
-(extern const $R64 Type)
-
-(extern const $F32 Type)
-(extern const $F64 Type)
-
-(extern const $B8X16 Type)
-(extern const $B16X8 Type)
-(extern const $B32X4 Type)
-(extern const $B64X2 Type)
-
-(extern const $I8X16 Type)
-(extern const $I16X8 Type)
-(extern const $I32X4 Type)
-(extern const $I64X2 Type)
-
-(extern const $F32X4 Type)
-(extern const $F64X2 Type)
-
-;; Get the bit width of a given type.
-(decl ty_bits (Type) u8)
-(extern constructor ty_bits ty_bits)
-
-;; Get the bit width of a given type.
-(decl ty_bits_u16 (Type) u16)
-(extern constructor ty_bits_u16 ty_bits_u16)
-
-;; Get the bit width of a given type.
-(decl ty_bits_u64 (Type) u64)
-(extern constructor ty_bits_u64 ty_bits_u64)
-
-;; Get a mask for the width of a given type.
-(decl ty_mask (Type) u64)
-(extern constructor ty_mask ty_mask)
-
-;; Get the byte width of a given type.
-(decl ty_bytes (Type) u16)
-(extern constructor ty_bytes ty_bytes)
-
-;; Get the type of each lane in the given type.
-(decl lane_type (Type) Type)
-(extern constructor lane_type lane_type)
-
-;;;; Helper Clif Extractors ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; An extractor that only matches types that can fit in 16 bits.
-(decl fits_in_16 (Type) Type)
-(extern extractor fits_in_16 fits_in_16)
-
-;; An extractor that only matches types that can fit in 32 bits.
-(decl fits_in_32 (Type) Type)
-(extern extractor fits_in_32 fits_in_32)
-
-;; An extractor that only matches types that can fit in 64 bits.
-(decl fits_in_64 (Type) Type)
-(extern extractor fits_in_64 fits_in_64)
-
-;; An extractor that matches 32- and 64-bit types only.
-(decl ty_32_or_64 (Type) Type)
-(extern extractor ty_32_or_64 ty_32_or_64)
-
-;; An extractor that matches 8- and 16-bit types only.
-(decl ty_8_or_16 (Type) Type)
-(extern extractor ty_8_or_16 ty_8_or_16)
-
-;; An extractor that matches I64 or B64.
-(decl ty_int_bool_64 (Type) Type)
-(extern extractor ty_int_bool_64 ty_int_bool_64)
-
-;; An extractor that matches I128 or B128.
-(decl ty_int_bool_128 (Type) Type)
-(extern extractor ty_int_bool_128 ty_int_bool_128)
-
-;; An extractor that only matches 128-bit vector types.
-(decl vec128 (Type) Type)
-(extern extractor vec128 vec128)
-
-;; An extractor that matches everything except i64x2
-(decl not_i64x2 () Type)
-(extern extractor not_i64x2 not_i64x2)
-
-;; Extractor to get a `ValueSlice` out of a `ValueList`.
-(decl value_list_slice (ValueSlice) ValueList)
-(extern extractor infallible value_list_slice value_list_slice)
-
-;; Extractor to test whether a `ValueSlice` is empty.
-(decl value_slice_empty () ValueSlice)
-(extern extractor value_slice_empty value_slice_empty)
-
-;; Extractor to split a `ValueSlice` into its first element plus a tail.
-(decl value_slice_unwrap (Value ValueSlice) ValueSlice)
-(extern extractor value_slice_unwrap value_slice_unwrap)
-
-;; Return the length of a `ValueSlice`.
-(decl value_slice_len (ValueSlice) usize)
-(extern constructor value_slice_len value_slice_len)
-
-;; Return any element of a `ValueSlice`.
-(decl value_slice_get (ValueSlice usize) Value)
-(extern constructor value_slice_get value_slice_get)
-
-;; Extractor to get the first element from a value list, along with its tail as
-;; a `ValueSlice`.
-(decl unwrap_head_value_list_1 (Value ValueSlice) ValueList)
-(extractor (unwrap_head_value_list_1 head tail)
-           (value_list_slice (value_slice_unwrap head tail)))
-
-;; Extractor to get the first two elements from a value list, along with its
-;; tail as a `ValueSlice`.
-(decl unwrap_head_value_list_2 (Value Value ValueSlice) ValueList)
-(extractor (unwrap_head_value_list_2 head1 head2 tail)
-           (value_list_slice (value_slice_unwrap head1 (value_slice_unwrap head2 tail))))
-
-;; Turn a `Writable<Reg>` into a `Reg` via `Writable::to_reg`.
-(decl writable_reg_to_reg (WritableReg) Reg)
-(extern constructor writable_reg_to_reg writable_reg_to_reg)
-
-;; Extract a `u8` from an `Uimm8`.
-(decl u8_from_uimm8 (u8) Uimm8)
-(extern extractor infallible u8_from_uimm8 u8_from_uimm8)
-
-;; Extract a `u64` from an `Imm64`.
-(decl u64_from_imm64 (u64) Imm64)
-(extern extractor infallible u64_from_imm64 u64_from_imm64)
-
-;; Extract a `u64` from an `Imm64` which is not zero.
-(decl nonzero_u64_from_imm64 (u64) Imm64)
-(extern extractor nonzero_u64_from_imm64 nonzero_u64_from_imm64)
-
-;; Extract a `u64` from an `Ieee32`.
-(decl u64_from_ieee32 (u64) Ieee32)
-(extern extractor infallible u64_from_ieee32 u64_from_ieee32)
-
-;; Extract a `u64` from an `Ieee64`.
-(decl u64_from_ieee64 (u64) Ieee64)
-(extern extractor infallible u64_from_ieee64 u64_from_ieee64)
-
-;; Extract the result values for the given instruction.
-(decl inst_results (ValueSlice) Inst)
-(extern extractor infallible inst_results inst_results)
-
-;; Extract the first result value of the given instruction.
-(decl first_result (Value) Inst)
-(extern extractor first_result first_result)
-
-;; Extract the `InstructionData` for an `Inst`.
-(decl inst_data (InstructionData) Inst)
-(extern extractor infallible inst_data inst_data)
-
-;; Extract the type of a `Value`.
-(decl value_type (Type) Value)
-(extern extractor infallible value_type value_type)
-
-;; Extract the type of the instruction's first result.
-(decl result_type (Type) Inst)
-(extractor (result_type ty)
-           (first_result (value_type ty)))
-
-;; Extract the type of the instruction's first result and pass along the
-;; instruction as well.
-(decl has_type (Type Inst) Inst)
-(extractor (has_type ty inst)
-           (and (result_type ty)
-                inst))
-
-;; Match a multi-lane type, extracting (# bits per lane, # lanes) from the given
-;; type. Will only match when there is more than one lane.
-(decl multi_lane (u8 u16) Type)
-(extern extractor multi_lane multi_lane)
-
-;; Match the instruction that defines the given value, if any.
-(decl def_inst (Inst) Value)
-(extern extractor def_inst def_inst)
-
-;; Extract a constant `u64` from a value defined by an `iconst`.
-(decl u64_from_iconst (u64) Value)
-(extractor (u64_from_iconst x)
-           (def_inst (iconst (u64_from_imm64 x))))
-
-;; Instruction creation helpers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Emit an instruction.
-;;
-;; This is low-level and side-effectful; it should only be used as an
-;; implementation detail by helpers that preserve the SSA facade themselves.
-
-(decl emit (MInst) Unit)
-(extern constructor emit emit)
-
-(decl emit_safepoint (MInst) Unit)
-(extern constructor emit_safepoint emit_safepoint)
-
-;;;; Helpers for Side-Effectful Instructions Without Results ;;;;;;;;;;;;;;;;;;;
-
-(type SideEffectNoResult (enum (Inst (inst MInst))))
-
-;; Create an empty `InstOutput`, but do emit the given side-effectful
-;; instruction.
-(decl side_effect (SideEffectNoResult) InstOutput)
-(rule (side_effect (SideEffectNoResult.Inst inst))
-      (let ((_ Unit (emit inst)))
-        (output_none)))
-
-;; Similarly, but emit the side-effectful instruction as a safepoint.
-(decl safepoint (SideEffectNoResult) InstOutput)
-(rule (safepoint (SideEffectNoResult.Inst inst))
-      (let ((_ Unit (emit_safepoint inst)))
-        (output_none)))
-
-;;;; Helpers for Working with Flags ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Newtype wrapper around `MInst` for instructions that are used for their
-;; effect on flags.
-;;
-;; Variant determines how result is given when combined with a
-;; ConsumesFlags. See `with_flags` below for more.
-(type ProducesFlags (enum
-                     (ProducesFlagsSideEffect (inst MInst))
-                     ;; Not directly combinable with a ConsumesFlags;
-                     ;; used in s390x and unwrapped directly by `trapif`.
-                     (ProducesFlagsReturnsReg (inst MInst) (result Reg))
-                     (ProducesFlagsReturnsResultWithConsumer (inst MInst) (result Reg))))
-
-;; Newtype wrapper around `MInst` for instructions that consume flags.
-;;
-;; Variant determines how result is given when combined with a
-;; ProducesFlags. See `with_flags` below for more.
-(type ConsumesFlags (enum
-                     (ConsumesFlagsReturnsResultWithProducer (inst MInst) (result Reg))
-                     (ConsumesFlagsReturnsReg (inst MInst) (result Reg))
-                     (ConsumesFlagsTwiceReturnsValueRegs (inst1 MInst)
-                                                         (inst2 MInst)
-                                                         (result ValueRegs))
-                     (ConsumesFlagsFourTimesReturnsValueRegs (inst1 MInst)
-                                                             (inst2 MInst)
-                                                             (inst3 MInst)
-                                                             (inst4 MInst)
-                                                             (result ValueRegs))))
-
-
-
-;; Get the produced register out of a ProducesFlags.
-(decl produces_flags_get_reg (ProducesFlags) Reg)
-(rule (produces_flags_get_reg (ProducesFlags.ProducesFlagsReturnsReg _ reg)) reg)
-
-;; Modify a ProducesFlags to use it only for its side-effect, ignoring
-;; its result.
-(decl produces_flags_ignore (ProducesFlags) ProducesFlags)
-(rule (produces_flags_ignore (ProducesFlags.ProducesFlagsReturnsReg inst _))
-                             (ProducesFlags.ProducesFlagsSideEffect inst))
-(rule (produces_flags_ignore (ProducesFlags.ProducesFlagsReturnsResultWithConsumer inst _))
-                             (ProducesFlags.ProducesFlagsSideEffect inst))
-
-;; Helper for combining two flags-consumer instructions that return a
-;; single Reg, giving a ConsumesFlags that returns both values in a
-;; ValueRegs.
-(decl consumes_flags_concat (ConsumesFlags ConsumesFlags) ConsumesFlags)
-(rule (consumes_flags_concat (ConsumesFlags.ConsumesFlagsReturnsReg inst1 reg1)
-                             (ConsumesFlags.ConsumesFlagsReturnsReg inst2 reg2))
-      (ConsumesFlags.ConsumesFlagsTwiceReturnsValueRegs
-       inst1
-       inst2
-       (value_regs reg1 reg2)))
-
-;; Combine flags-producing and -consuming instructions together, ensuring that
-;; they are emitted back-to-back and no other instructions can be emitted
-;; between them and potentially clobber the flags.
-;;
-;; Returns a `ValueRegs` according to the specific combination of ProducesFlags and ConsumesFlags modes:
-;; - SideEffect + ReturnsReg --> ValueReg with one Reg from consumer
-;; - SideEffect + ReturnsValueRegs --> ValueReg as given from consumer
-;; - ReturnsResultWithProducer + ReturnsResultWithConsumer --> ValueReg with low part from producer, high part from consumer
-;;
-;; See `with_flags_reg` below for a variant that extracts out just the lower Reg.
-(decl with_flags (ProducesFlags ConsumesFlags) ValueRegs)
-
-(rule (with_flags (ProducesFlags.ProducesFlagsReturnsResultWithConsumer producer_inst producer_result)
-                  (ConsumesFlags.ConsumesFlagsReturnsResultWithProducer consumer_inst consumer_result))
-      (let ((_x Unit (emit producer_inst))
-            (_y Unit (emit consumer_inst)))
-        (value_regs producer_result consumer_result)))
-
-(rule (with_flags (ProducesFlags.ProducesFlagsSideEffect producer_inst)
-                  (ConsumesFlags.ConsumesFlagsReturnsReg consumer_inst consumer_result))
-      (let ((_x Unit (emit producer_inst))
-            (_y Unit (emit consumer_inst)))
-        (value_reg consumer_result)))
-
-(rule (with_flags (ProducesFlags.ProducesFlagsSideEffect producer_inst)
-                  (ConsumesFlags.ConsumesFlagsTwiceReturnsValueRegs consumer_inst_1
-                                                                    consumer_inst_2
-                                                                    consumer_result))
-      ;; We must emit these instructions in order as the creator of
-      ;; the ConsumesFlags may be relying on dataflow dependencies
-      ;; amongst them.
-      (let ((_x Unit (emit producer_inst))
-            (_y Unit (emit consumer_inst_1))
-            (_z Unit (emit consumer_inst_2)))
-        consumer_result))
-
-(rule (with_flags (ProducesFlags.ProducesFlagsSideEffect producer_inst)
-                  (ConsumesFlags.ConsumesFlagsFourTimesReturnsValueRegs consumer_inst_1
-                                                                        consumer_inst_2
-                                                                        consumer_inst_3
-                                                                        consumer_inst_4
-                                                                        consumer_result))
-      ;; We must emit these instructions in order as the creator of
-      ;; the ConsumesFlags may be relying on dataflow dependencies
-      ;; amongst them.
-      (let ((_x Unit (emit producer_inst))
-            (_y Unit (emit consumer_inst_1))
-            (_z Unit (emit consumer_inst_2))
-            (_w Unit (emit consumer_inst_3))
-            (_v Unit (emit consumer_inst_4)))
-        consumer_result))
-
-(decl with_flags_reg (ProducesFlags ConsumesFlags) Reg)
-(rule (with_flags_reg p c)
-      (let ((v ValueRegs (with_flags p c)))
-        (value_regs_get v 0)))
-
-;;;; Helpers for Working with TrapCode ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl trap_code_division_by_zero () TrapCode)
-(extern constructor trap_code_division_by_zero trap_code_division_by_zero)
-
-(decl trap_code_integer_overflow () TrapCode)
-(extern constructor trap_code_integer_overflow trap_code_integer_overflow)
-
-(decl trap_code_bad_conversion_to_integer () TrapCode)
-(extern constructor trap_code_bad_conversion_to_integer trap_code_bad_conversion_to_integer)
-
-;;;; Helpers for accessing compilation flags ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(decl avoid_div_traps () Type)
-(extern extractor avoid_div_traps avoid_div_traps)
-
-;;;; Helpers for accessing instruction data ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Accessor for `FuncRef`.
-
-(decl func_ref_data (SigRef ExternalName RelocDistance) FuncRef)
-(extern extractor infallible func_ref_data func_ref_data)
-
-;; Accessor for `GobalValue`.
-
-(decl symbol_value_data (ExternalName RelocDistance i64) GlobalValue)
-(extern extractor symbol_value_data symbol_value_data)
-
-;; Accessor for `RelocDistance`.
-
-(decl reloc_distance_near () RelocDistance)
-(extern extractor reloc_distance_near reloc_distance_near)
-
-;;;; Automatic conversions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-(convert Inst Value def_inst)
-(convert Reg ValueRegs value_reg)
-(convert Value Reg put_in_reg)
-(convert Value ValueRegs put_in_regs)
-(convert WritableReg Reg writable_reg_to_reg)
-(convert ValueRegs InstOutput output)
-(convert Reg InstOutput output_reg)
-(convert Value InstOutput output_value)
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/preopt.peepmatic b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/preopt.peepmatic
deleted file mode 100644
index b03208949..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/preopt.peepmatic
+++ /dev/null
@@ -1,196 +0,0 @@
-;; Apply basic simplifications.
-;;
-;; This folds constants with arithmetic to form `_imm` instructions, and other
-;; minor simplifications.
-;;
-;; Doesn't apply some simplifications if the native word width (in bytes) is
-;; smaller than the controlling type's width of the instruction. This would
-;; result in an illegal instruction that would likely be expanded back into an
-;; instruction on smaller types with the same initial opcode, creating
-;; unnecessary churn.
-
-;; Binary instructions whose second argument is constant.
-(=> (when (iadd $x $C)
-      (fits-in-native-word $C))
-    (iadd_imm $C $x))
-(=> (when (imul $x $C)
-      (fits-in-native-word $C))
-    (imul_imm $C $x))
-(=> (when (sdiv $x $C)
-      (fits-in-native-word $C))
-    (sdiv_imm $C $x))
-(=> (when (udiv $x $C)
-      (fits-in-native-word $C))
-    (udiv_imm $C $x))
-(=> (when (srem $x $C)
-      (fits-in-native-word $C))
-    (srem_imm $C $x))
-(=> (when (urem $x $C)
-      (fits-in-native-word $C))
-    (urem_imm $C $x))
-(=> (when (band $x $C)
-      (fits-in-native-word $C))
-    (band_imm $C $x))
-(=> (when (bor $x $C)
-      (fits-in-native-word $C))
-    (bor_imm $C $x))
-(=> (when (bxor $x $C)
-      (fits-in-native-word $C))
-    (bxor_imm $C $x))
-(=> (when (rotl $x $C)
-      (fits-in-native-word $C))
-    (rotl_imm $C $x))
-(=> (when (rotr $x $C)
-      (fits-in-native-word $C))
-    (rotr_imm $C $x))
-(=> (when (ishl $x $C)
-      (fits-in-native-word $C))
-    (ishl_imm $C $x))
-(=> (when (ushr $x $C)
-      (fits-in-native-word $C))
-    (ushr_imm $C $x))
-(=> (when (sshr $x $C)
-      (fits-in-native-word $C))
-    (sshr_imm $C $x))
-(=> (when (isub $x $C)
-      (fits-in-native-word $C))
-    (iadd_imm $(neg $C) $x))
-(=> (when (ifcmp $x $C)
-      (fits-in-native-word $C))
-    (ifcmp_imm $C $x))
-(=> (when (icmp $cond $x $C)
-      (fits-in-native-word $C))
-    (icmp_imm $cond $C $x))
-
-;; Binary instructions whose first operand is constant.
-(=> (when (iadd $C $x)
-      (fits-in-native-word $C))
-    (iadd_imm $C $x))
-(=> (when (imul $C $x)
-      (fits-in-native-word $C))
-    (imul_imm $C $x))
-(=> (when (band $C $x)
-      (fits-in-native-word $C))
-    (band_imm $C $x))
-(=> (when (bor $C $x)
-      (fits-in-native-word $C))
-    (bor_imm $C $x))
-(=> (when (bxor $C $x)
-      (fits-in-native-word $C))
-    (bxor_imm $C $x))
-(=> (when (isub $C $x)
-      (fits-in-native-word $C))
-    (irsub_imm $C $x))
-
-;; Fold `(binop_imm $C1 (binop_imm $C2 $x))` into `(binop_imm $(binop $C2 $C1) $x)`.
-(=> (iadd_imm $C1 (iadd_imm $C2 $x)) (iadd_imm $(iadd $C1 $C2) $x))
-(=> (imul_imm $C1 (imul_imm $C2 $x)) (imul_imm $(imul $C1 $C2) $x))
-(=> (bor_imm $C1 (bor_imm $C2 $x)) (bor_imm $(bor $C1 $C2) $x))
-(=> (band_imm $C1 (band_imm $C2 $x)) (band_imm $(band $C1 $C2) $x))
-(=> (bxor_imm $C1 (bxor_imm $C2 $x)) (bxor_imm $(bxor $C1 $C2) $x))
-
-;; Remove operations that are no-ops.
-(=> (iadd_imm 0 $x) $x)
-(=> (imul_imm 1 $x) $x)
-(=> (sdiv_imm 1 $x) $x)
-(=> (udiv_imm 1 $x) $x)
-(=> (bor_imm 0 $x) $x)
-(=> (band_imm -1 $x) $x)
-(=> (bxor_imm 0 $x) $x)
-(=> (rotl_imm 0 $x) $x)
-(=> (rotr_imm 0 $x) $x)
-(=> (ishl_imm 0 $x) $x)
-(=> (ushr_imm 0 $x) $x)
-(=> (sshr_imm 0 $x) $x)
-
-;; Replace with zero.
-(=> (imul_imm 0 $x) 0)
-(=> (band_imm 0 $x) 0)
-
-;; Replace with negative 1.
-(=> (bor_imm -1 $x) -1)
-
-;; Transform `[(x << N) >> N]` into a (un)signed-extending move.
-;;
-;; i16 -> i8 -> i16
-(=> (when (ushr_imm 8 (ishl_imm 8 $x))
-      (bit-width $x 16))
-    (uextend{i16} (ireduce{i8} $x)))
-(=> (when (sshr_imm 8 (ishl_imm 8 $x))
-      (bit-width $x 16))
-    (sextend{i16} (ireduce{i8} $x)))
-;; i32 -> i8 -> i32
-(=> (when (ushr_imm 24 (ishl_imm 24 $x))
-      (bit-width $x 32))
-    (uextend{i32} (ireduce{i8} $x)))
-(=> (when (sshr_imm 24 (ishl_imm 24 $x))
-      (bit-width $x 32))
-    (sextend{i32} (ireduce{i8} $x)))
-;; i32 -> i16 -> i32
-(=> (when (ushr_imm 16 (ishl_imm 16 $x))
-      (bit-width $x 32))
-    (uextend{i32} (ireduce{i16} $x)))
-(=> (when (sshr_imm 16 (ishl_imm 16 $x))
-      (bit-width $x 32))
-    (sextend{i32} (ireduce{i16} $x)))
-;; i64 -> i8 -> i64
-(=> (when (ushr_imm 56 (ishl_imm 56 $x))
-      (bit-width $x 64))
-    (uextend{i64} (ireduce{i8} $x)))
-(=> (when (sshr_imm 56 (ishl_imm 56 $x))
-      (bit-width $x 64))
-    (sextend{i64} (ireduce{i8} $x)))
-;; i64 -> i16 -> i64
-(=> (when (ushr_imm 48 (ishl_imm 48 $x))
-      (bit-width $x 64))
-    (uextend{i64} (ireduce{i16} $x)))
-(=> (when (sshr_imm 48 (ishl_imm 48 $x))
-      (bit-width $x 64))
-    (sextend{i64} (ireduce{i16} $x)))
-;; i64 -> i32 -> i64
-(=> (when (ushr_imm 32 (ishl_imm 32 $x))
-      (bit-width $x 64))
-    (uextend{i64} (ireduce{i32} $x)))
-(=> (when (sshr_imm 32 (ishl_imm 32 $x))
-      (bit-width $x 64))
-    (sextend{i64} (ireduce{i32} $x)))
-
-;; Fold away redundant `bint` instructions that accept both integer and boolean
-;; arguments.
-(=> (select (bint $x) $y $z) (select $x $y $z))
-(=> (brz (bint $x)) (brz $x))
-(=> (brnz (bint $x)) (brnz $x))
-(=> (trapz (bint $x)) (trapz $x))
-(=> (trapnz (bint $x)) (trapnz $x))
-
-;; Fold comparisons into branch operations when possible.
-;;
-;; This matches against operations which compare against zero, then use the
-;; result in a `brz` or `brnz` branch. It folds those two operations into a
-;; single `brz` or `brnz`.
-(=> (brnz (icmp_imm ne 0 $x)) (brnz $x))
-(=> (brz (icmp_imm ne 0 $x)) (brz $x))
-(=> (brnz (icmp_imm eq 0 $x)) (brz $x))
-(=> (brz (icmp_imm eq 0 $x)) (brnz $x))
-
-;; Division and remainder by constants.
-;;
-;; TODO: this section is incomplete, and a bunch of related optimizations are
-;; still hand-coded in `simple_preopt.rs`.
-
-;; (Division by one is handled above.)
-
-;; Remainder by one is zero.
-(=> (urem_imm 1 $x) 0)
-(=> (srem_imm 1 $x) 0)
-
-;; Division by a power of two -> shift right.
-(=> (when (udiv_imm $C $x)
-          (is-power-of-two $C))
-    (ushr_imm $(log2 $C) $x))
-
-;; Remainder by a power of two -> bitwise and with decreased by one constant.
-(=> (when (urem_imm $C $x)
-          (is-power-of-two $C)
-          (fits-in-native-word $C))
-    (band_imm $(isub $C 1) $x))
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/print_errors.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/print_errors.rs
deleted file mode 100644
index e3fe73661..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/print_errors.rs
+++ /dev/null
@@ -1,220 +0,0 @@
-//! Utility routines for pretty-printing error messages.
-
-use crate::entity::SecondaryMap;
-use crate::ir;
-use crate::ir::entities::{AnyEntity, Block, Inst, Value};
-use crate::ir::function::Function;
-use crate::result::CodegenError;
-use crate::verifier::{VerifierError, VerifierErrors};
-use crate::write::{decorate_function, FuncWriter, PlainWriter};
-use alloc::boxed::Box;
-use alloc::string::{String, ToString};
-use alloc::vec::Vec;
-use core::fmt;
-use core::fmt::Write;
-
-/// Pretty-print a verifier error.
-pub fn pretty_verifier_error<'a>(
-    func: &ir::Function,
-    func_w: Option<Box<dyn FuncWriter + 'a>>,
-    errors: VerifierErrors,
-) -> String {
-    let mut errors = errors.0;
-    let mut w = String::new();
-    let num_errors = errors.len();
-
-    decorate_function(
-        &mut PrettyVerifierError(func_w.unwrap_or_else(|| Box::new(PlainWriter)), &mut errors),
-        &mut w,
-        func,
-    )
-    .unwrap();
-
-    writeln!(
-        w,
-        "\n; {} verifier error{} detected (see above). Compilation aborted.",
-        num_errors,
-        if num_errors == 1 { "" } else { "s" }
-    )
-    .unwrap();
-
-    w
-}
-
-struct PrettyVerifierError<'a>(Box<dyn FuncWriter + 'a>, &'a mut Vec<VerifierError>);
-
-impl<'a> FuncWriter for PrettyVerifierError<'a> {
-    fn write_block_header(
-        &mut self,
-        w: &mut dyn Write,
-        func: &Function,
-        block: Block,
-        indent: usize,
-    ) -> fmt::Result {
-        pretty_block_header_error(w, func, block, indent, &mut *self.0, self.1)
-    }
-
-    fn write_instruction(
-        &mut self,
-        w: &mut dyn Write,
-        func: &Function,
-        aliases: &SecondaryMap<Value, Vec<Value>>,
-        inst: Inst,
-        indent: usize,
-    ) -> fmt::Result {
-        pretty_instruction_error(w, func, aliases, inst, indent, &mut *self.0, self.1)
-    }
-
-    fn write_entity_definition(
-        &mut self,
-        w: &mut dyn Write,
-        func: &Function,
-        entity: AnyEntity,
-        value: &dyn fmt::Display,
-    ) -> fmt::Result {
-        pretty_preamble_error(w, func, entity, value, &mut *self.0, self.1)
-    }
-}
-
-/// Pretty-print a function verifier error for a given block.
-fn pretty_block_header_error(
-    w: &mut dyn Write,
-    func: &Function,
-    cur_block: Block,
-    indent: usize,
-    func_w: &mut dyn FuncWriter,
-    errors: &mut Vec<VerifierError>,
-) -> fmt::Result {
-    let mut s = String::new();
-    func_w.write_block_header(&mut s, func, cur_block, indent)?;
-    write!(w, "{}", s)?;
-
-    // TODO: Use drain_filter here when it gets stabilized
-    let mut i = 0;
-    let mut printed_error = false;
-    while i != errors.len() {
-        match errors[i].location {
-            ir::entities::AnyEntity::Block(block) if block == cur_block => {
-                if !printed_error {
-                    print_arrow(w, &s)?;
-                    printed_error = true;
-                }
-                let err = errors.remove(i);
-                print_error(w, err)?;
-            }
-            _ => i += 1,
-        }
-    }
-
-    if printed_error {
-        w.write_char('\n')?;
-    }
-
-    Ok(())
-}
-
-/// Pretty-print a function verifier error for a given instruction.
-fn pretty_instruction_error(
-    w: &mut dyn Write,
-    func: &Function,
-    aliases: &SecondaryMap<Value, Vec<Value>>,
-    cur_inst: Inst,
-    indent: usize,
-    func_w: &mut dyn FuncWriter,
-    errors: &mut Vec<VerifierError>,
-) -> fmt::Result {
-    let mut s = String::new();
-    func_w.write_instruction(&mut s, func, aliases, cur_inst, indent)?;
-    write!(w, "{}", s)?;
-
-    // TODO: Use drain_filter here when it gets stabilized
-    let mut i = 0;
-    let mut printed_error = false;
-    while i != errors.len() {
-        match errors[i].location {
-            ir::entities::AnyEntity::Inst(inst) if inst == cur_inst => {
-                if !printed_error {
-                    print_arrow(w, &s)?;
-                    printed_error = true;
-                }
-                let err = errors.remove(i);
-                print_error(w, err)?;
-            }
-            _ => i += 1,
-        }
-    }
-
-    if printed_error {
-        w.write_char('\n')?;
-    }
-
-    Ok(())
-}
-
-fn pretty_preamble_error(
-    w: &mut dyn Write,
-    func: &Function,
-    entity: AnyEntity,
-    value: &dyn fmt::Display,
-    func_w: &mut dyn FuncWriter,
-    errors: &mut Vec<VerifierError>,
-) -> fmt::Result {
-    let mut s = String::new();
-    func_w.write_entity_definition(&mut s, func, entity, value)?;
-    write!(w, "{}", s)?;
-
-    // TODO: Use drain_filter here when it gets stabilized
-    let mut i = 0;
-    let mut printed_error = false;
-    while i != errors.len() {
-        if entity == errors[i].location {
-            if !printed_error {
-                print_arrow(w, &s)?;
-                printed_error = true;
-            }
-            let err = errors.remove(i);
-            print_error(w, err)?;
-        } else {
-            i += 1
-        }
-    }
-
-    if printed_error {
-        w.write_char('\n')?;
-    }
-
-    Ok(())
-}
-
-/// Prints:
-///    ;   ^~~~~~
-fn print_arrow(w: &mut dyn Write, entity: &str) -> fmt::Result {
-    write!(w, ";")?;
-
-    let indent = entity.len() - entity.trim_start().len();
-    if indent != 0 {
-        write!(w, "{1:0$}^", indent - 1, "")?;
-    }
-
-    for _ in 0..entity.trim().len() - 1 {
-        write!(w, "~")?;
-    }
-
-    writeln!(w)
-}
-
-/// Prints:
-///    ; error: [ERROR BODY]
-fn print_error(w: &mut dyn Write, err: VerifierError) -> fmt::Result {
-    writeln!(w, "; error: {}", err.to_string())?;
-    Ok(())
-}
-
-/// Pretty-print a Cranelift error.
-pub fn pretty_error(func: &ir::Function, err: CodegenError) -> String {
-    if let CodegenError::Verifier(e) = err {
-        pretty_verifier_error(func, None, e)
-    } else {
-        err.to_string()
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/remove_constant_phis.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/remove_constant_phis.rs
deleted file mode 100644
index 234d89c26..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/remove_constant_phis.rs
+++ /dev/null
@@ -1,391 +0,0 @@
-//! A Constant-Phi-Node removal pass.
-
-use crate::dominator_tree::DominatorTree;
-use crate::entity::EntityList;
-use crate::fx::FxHashMap;
-use crate::fx::FxHashSet;
-use crate::ir::instructions::BranchInfo;
-use crate::ir::Function;
-use crate::ir::{Block, Inst, Value};
-use crate::timing;
-
-use smallvec::{smallvec, SmallVec};
-use std::vec::Vec;
-
-// A note on notation.  For the sake of clarity, this file uses the phrase
-// "formal parameters" to mean the `Value`s listed in the block head, and
-// "actual parameters" to mean the `Value`s passed in a branch or a jump:
-//
-// block4(v16: i32, v18: i32):    <-- formal parameters
-//   ...
-//   brnz v27, block7(v22, v24)   <-- actual parameters
-//   jump block6
-
-// This transformation pass (conceptually) partitions all values in the
-// function into two groups:
-//
-// * Group A: values defined by block formal parameters, except for the entry block.
-//
-// * Group B: All other values: that is, values defined by instructions,
-//   and the formals of the entry block.
-//
-// For each value in Group A, it attempts to establish whether it will have
-// the value of exactly one member of Group B.  If so, the formal parameter is
-// deleted, all corresponding actual parameters (in jumps/branches to the
-// defining block) are deleted, and a rename is inserted.
-//
-// The entry block is special-cased because (1) we don't know what values flow
-// to its formals and (2) in any case we can't change its formals.
-//
-// Work proceeds in three phases.
-//
-// * Phase 1: examine all instructions.  For each block, make up a useful
-//   grab-bag of information, `BlockSummary`, that summarises the block's
-//   formals and jump/branch instruction.  This is used by Phases 2 and 3.
-//
-// * Phase 2: for each value in Group A, try to find a single Group B value
-//   that flows to it.  This is done using a classical iterative forward
-//   dataflow analysis over a simple constant-propagation style lattice.  It
-//   converges quickly in practice -- I have seen at most 4 iterations.  This
-//   is relatively cheap because the iteration is done over the
-//   `BlockSummary`s, and does not visit each instruction.  The resulting
-//   fixed point is stored in a `SolverState`.
-//
-// * Phase 3: using the `SolverState` and `BlockSummary`, edit the function to
-//   remove redundant formals and actuals, and to insert suitable renames.
-//
-// Note that the effectiveness of the analysis depends on on the fact that
-// there are no copy instructions in Cranelift's IR.  If there were, the
-// computation of `actual_absval` in Phase 2 would have to be extended to
-// chase through such copies.
-//
-// For large functions, the analysis cost using the new AArch64 backend is about
-// 0.6% of the non-optimising compile time, as measured by instruction counts.
-// This transformation usually pays for itself several times over, though, by
-// reducing the isel/regalloc cost downstream.  Gains of up to 7% have been
-// seen for large functions.
-
-// The `Value`s (Group B) that can flow to a formal parameter (Group A).
-#[derive(Clone, Copy, Debug, PartialEq)]
-enum AbstractValue {
-    // Two or more values flow to this formal.
-    Many,
-    // Exactly one value, as stated, flows to this formal.  The `Value`s that
-    // can appear here are exactly: `Value`s defined by `Inst`s, plus the
-    // `Value`s defined by the formals of the entry block.  Note that this is
-    // exactly the set of `Value`s that are *not* tracked in the solver below
-    // (see `SolverState`).
-    One(Value /*Group B*/),
-    // No value flows to this formal.
-    None,
-}
-
-impl AbstractValue {
-    fn join(self, other: AbstractValue) -> AbstractValue {
-        match (self, other) {
-            // Joining with `None` has no effect
-            (AbstractValue::None, p2) => p2,
-            (p1, AbstractValue::None) => p1,
-            // Joining with `Many` produces `Many`
-            (AbstractValue::Many, _p2) => AbstractValue::Many,
-            (_p1, AbstractValue::Many) => AbstractValue::Many,
-            // The only interesting case
-            (AbstractValue::One(v1), AbstractValue::One(v2)) => {
-                if v1 == v2 {
-                    AbstractValue::One(v1)
-                } else {
-                    AbstractValue::Many
-                }
-            }
-        }
-    }
-    fn is_one(self) -> bool {
-        if let AbstractValue::One(_) = self {
-            true
-        } else {
-            false
-        }
-    }
-}
-
-// For some block, a useful bundle of info.  The `Block` itself is not stored
-// here since it will be the key in the associated `FxHashMap` -- see
-// `summaries` below.  For the `SmallVec` tuning params: most blocks have
-// few parameters, hence `4`.  And almost all blocks have either one or two
-// successors, hence `2`.
-#[derive(Debug)]
-struct BlockSummary {
-    // Formal parameters for this `Block`
-    formals: SmallVec<[Value; 4] /*Group A*/>,
-    // For each `Inst` in this block that transfers to another block: the
-    // `Inst` itself, the destination `Block`, and the actual parameters
-    // passed.  We don't bother to include transfers that pass zero parameters
-    // since that makes more work for the solver for no purpose.
-    dests: SmallVec<[(Inst, Block, SmallVec<[Value; 4] /*both Groups A and B*/>); 2]>,
-}
-impl BlockSummary {
-    fn new(formals: SmallVec<[Value; 4]>) -> Self {
-        Self {
-            formals,
-            dests: smallvec![],
-        }
-    }
-}
-
-// Solver state.  This holds a AbstractValue for each formal parameter, except
-// for those from the entry block.
-struct SolverState {
-    absvals: FxHashMap<Value /*Group A*/, AbstractValue>,
-}
-impl SolverState {
-    fn new() -> Self {
-        Self {
-            absvals: FxHashMap::default(),
-        }
-    }
-    fn get(&self, actual: Value) -> AbstractValue {
-        match self.absvals.get(&actual) {
-            Some(lp) => *lp,
-            None => panic!("SolverState::get: formal param {:?} is untracked?!", actual),
-        }
-    }
-    fn maybe_get(&self, actual: Value) -> Option<&AbstractValue> {
-        self.absvals.get(&actual)
-    }
-    fn set(&mut self, actual: Value, lp: AbstractValue) {
-        match self.absvals.insert(actual, lp) {
-            Some(_old_lp) => {}
-            None => panic!("SolverState::set: formal param {:?} is untracked?!", actual),
-        }
-    }
-}
-
-/// Detect phis in `func` that will only ever produce one value, using a
-/// classic forward dataflow analysis.  Then remove them.
-#[inline(never)]
-pub fn do_remove_constant_phis(func: &mut Function, domtree: &mut DominatorTree) {
-    let _tt = timing::remove_constant_phis();
-    debug_assert!(domtree.is_valid());
-
-    // Get the blocks, in reverse postorder
-    let mut blocks_reverse_postorder = Vec::<Block>::new();
-    for block in domtree.cfg_postorder() {
-        blocks_reverse_postorder.push(*block);
-    }
-    blocks_reverse_postorder.reverse();
-
-    // Phase 1 of 3: for each block, make a summary containing all relevant
-    // info.  The solver will iterate over the summaries, rather than having
-    // to inspect each instruction in each block.
-    let mut summaries = FxHashMap::<Block, BlockSummary>::default();
-
-    for b in &blocks_reverse_postorder {
-        let formals = func.dfg.block_params(*b);
-        let mut summary = BlockSummary::new(SmallVec::from(formals));
-
-        for inst in func.layout.block_insts(*b) {
-            let idetails = &func.dfg[inst];
-            // Note that multi-dest transfers (i.e., branch tables) don't
-            // carry parameters in our IR, so we only have to care about
-            // `SingleDest` here.
-            if let BranchInfo::SingleDest(dest, _) = idetails.analyze_branch(&func.dfg.value_lists)
-            {
-                let inst_var_args = func.dfg.inst_variable_args(inst);
-                // Skip branches/jumps that carry no params.
-                if inst_var_args.len() > 0 {
-                    let mut actuals = SmallVec::<[Value; 4]>::new();
-                    for arg in inst_var_args {
-                        let arg = func.dfg.resolve_aliases(*arg);
-                        actuals.push(arg);
-                    }
-                    summary.dests.push((inst, dest, actuals));
-                }
-            }
-        }
-
-        // Ensure the invariant that all blocks (except for the entry) appear
-        // in the summary, *unless* they have neither formals nor any
-        // param-carrying branches/jumps.
-        if formals.len() > 0 || summary.dests.len() > 0 {
-            summaries.insert(*b, summary);
-        }
-    }
-
-    // Phase 2 of 3: iterate over the summaries in reverse postorder,
-    // computing new `AbstractValue`s for each tracked `Value`.  The set of
-    // tracked `Value`s is exactly Group A as described above.
-
-    let entry_block = func
-        .layout
-        .entry_block()
-        .expect("remove_constant_phis: entry block unknown");
-
-    // Set up initial solver state
-    let mut state = SolverState::new();
-
-    for b in &blocks_reverse_postorder {
-        // For each block, get the formals
-        if *b == entry_block {
-            continue;
-        }
-        let formals: &[Value] = func.dfg.block_params(*b);
-        for formal in formals {
-            let mb_old_absval = state.absvals.insert(*formal, AbstractValue::None);
-            assert!(mb_old_absval.is_none());
-        }
-    }
-
-    // Solve: repeatedly traverse the blocks in reverse postorder, until there
-    // are no changes.
-    let mut iter_no = 0;
-    loop {
-        iter_no += 1;
-        let mut changed = false;
-
-        for src in &blocks_reverse_postorder {
-            let mb_src_summary = summaries.get(src);
-            // The src block might have no summary.  This means it has no
-            // branches/jumps that carry parameters *and* it doesn't take any
-            // parameters itself.  Phase 1 ensures this.  So we can ignore it.
-            if mb_src_summary.is_none() {
-                continue;
-            }
-            let src_summary = mb_src_summary.unwrap();
-            for (_inst, dst, src_actuals) in &src_summary.dests {
-                assert!(*dst != entry_block);
-                // By contrast, the dst block must have a summary.  Phase 1
-                // will have only included an entry in `src_summary.dests` if
-                // that branch/jump carried at least one parameter.  So the
-                // dst block does take parameters, so it must have a summary.
-                let dst_summary = summaries
-                    .get(dst)
-                    .expect("remove_constant_phis: dst block has no summary");
-                let dst_formals = &dst_summary.formals;
-                assert!(src_actuals.len() == dst_formals.len());
-                for (formal, actual) in dst_formals.iter().zip(src_actuals.iter()) {
-                    // Find the abstract value for `actual`.  If it is a block
-                    // formal parameter then the most recent abstract value is
-                    // to be found in the solver state.  If not, then it's a
-                    // real value defining point (not a phi), in which case
-                    // return it itself.
-                    let actual_absval = match state.maybe_get(*actual) {
-                        Some(pt) => *pt,
-                        None => AbstractValue::One(*actual),
-                    };
-
-                    // And `join` the new value with the old.
-                    let formal_absval_old = state.get(*formal);
-                    let formal_absval_new = formal_absval_old.join(actual_absval);
-                    if formal_absval_new != formal_absval_old {
-                        changed = true;
-                        state.set(*formal, formal_absval_new);
-                    }
-                }
-            }
-        }
-
-        if !changed {
-            break;
-        }
-    }
-    let mut n_consts = 0;
-    for absval in state.absvals.values() {
-        if absval.is_one() {
-            n_consts += 1;
-        }
-    }
-
-    // Phase 3 of 3: edit the function to remove constant formals, using the
-    // summaries and the final solver state as a guide.
-
-    // Make up a set of blocks that need editing.
-    let mut need_editing = FxHashSet::<Block>::default();
-    for (block, summary) in &summaries {
-        if *block == entry_block {
-            continue;
-        }
-        for formal in &summary.formals {
-            let formal_absval = state.get(*formal);
-            if formal_absval.is_one() {
-                need_editing.insert(*block);
-                break;
-            }
-        }
-    }
-
-    // Firstly, deal with the formals.  For each formal which is redundant,
-    // remove it, and also add a reroute from it to the constant value which
-    // it we know it to be.
-    for b in &need_editing {
-        let mut del_these = SmallVec::<[(Value, Value); 32]>::new();
-        let formals: &[Value] = func.dfg.block_params(*b);
-        for formal in formals {
-            // The state must give an absval for `formal`.
-            if let AbstractValue::One(replacement_val) = state.get(*formal) {
-                del_these.push((*formal, replacement_val));
-            }
-        }
-        // We can delete the formals in any order.  However,
-        // `remove_block_param` works by sliding backwards all arguments to
-        // the right of the it is asked to delete.  Hence when removing more
-        // than one formal, it is significantly more efficient to ask it to
-        // remove the rightmost formal first, and hence this `reverse`.
-        del_these.reverse();
-        for (redundant_formal, replacement_val) in del_these {
-            func.dfg.remove_block_param(redundant_formal);
-            func.dfg.change_to_alias(redundant_formal, replacement_val);
-        }
-    }
-
-    // Secondly, visit all branch insns.  If the destination has had its
-    // formals changed, change the actuals accordingly.  Don't scan all insns,
-    // rather just visit those as listed in the summaries we prepared earlier.
-    for (_src_block, summary) in &summaries {
-        for (inst, dst_block, _src_actuals) in &summary.dests {
-            if !need_editing.contains(dst_block) {
-                continue;
-            }
-
-            let old_actuals = func.dfg[*inst].take_value_list().unwrap();
-            let num_old_actuals = old_actuals.len(&func.dfg.value_lists);
-            let num_fixed_actuals = func.dfg[*inst]
-                .opcode()
-                .constraints()
-                .num_fixed_value_arguments();
-            let dst_summary = summaries.get(&dst_block).unwrap();
-
-            // Check that the numbers of arguments make sense.
-            assert!(num_fixed_actuals <= num_old_actuals);
-            assert!(num_fixed_actuals + dst_summary.formals.len() == num_old_actuals);
-
-            // Create a new value list.
-            let mut new_actuals = EntityList::<Value>::new();
-            // Copy the fixed args to the new list
-            for i in 0..num_fixed_actuals {
-                let val = old_actuals.get(i, &func.dfg.value_lists).unwrap();
-                new_actuals.push(val, &mut func.dfg.value_lists);
-            }
-
-            // Copy the variable args (the actual block params) to the new
-            // list, filtering out redundant ones.
-            for i in 0..dst_summary.formals.len() {
-                let actual_i = old_actuals
-                    .get(num_fixed_actuals + i, &func.dfg.value_lists)
-                    .unwrap();
-                let formal_i = dst_summary.formals[i];
-                let is_redundant = state.get(formal_i).is_one();
-                if !is_redundant {
-                    new_actuals.push(actual_i, &mut func.dfg.value_lists);
-                }
-            }
-            func.dfg[*inst].put_value_list(new_actuals);
-        }
-    }
-
-    log::debug!(
-        "do_remove_constant_phis: done, {} iters.   {} formals, of which {} const.",
-        iter_no,
-        state.absvals.len(),
-        n_consts
-    );
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/result.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/result.rs
deleted file mode 100644
index 3178cd5ba..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/result.rs
+++ /dev/null
@@ -1,76 +0,0 @@
-//! Result and error types representing the outcome of compiling a function.
-
-use crate::verifier::VerifierErrors;
-use std::string::String;
-
-/// A compilation error.
-///
-/// When Cranelift fails to compile a function, it will return one of these error codes.
-#[derive(Debug, PartialEq, Eq)]
-pub enum CodegenError {
-    /// A list of IR verifier errors.
-    ///
-    /// This always represents a bug, either in the code that generated IR for Cranelift, or a bug
-    /// in Cranelift itself.
-    Verifier(VerifierErrors),
-
-    /// An implementation limit was exceeded.
-    ///
-    /// Cranelift can compile very large and complicated functions, but the [implementation has
-    /// limits][limits] that cause compilation to fail when they are exceeded.
-    ///
-    /// [limits]: https://github.com/bytecodealliance/wasmtime/blob/main/cranelift/docs/ir.md#implementation-limits
-    ImplLimitExceeded,
-
-    /// The code size for the function is too large.
-    ///
-    /// Different target ISAs may impose a limit on the size of a compiled function. If that limit
-    /// is exceeded, compilation fails.
-    CodeTooLarge,
-
-    /// Something is not supported by the code generator. This might be an indication that a
-    /// feature is used without explicitly enabling it, or that something is temporarily
-    /// unsupported by a given target backend.
-    Unsupported(String),
-
-    /// A failure to map Cranelift register representation to a DWARF register representation.
-    #[cfg(feature = "unwind")]
-    RegisterMappingError(crate::isa::unwind::systemv::RegisterMappingError),
-}
-
-/// A convenient alias for a `Result` that uses `CodegenError` as the error type.
-pub type CodegenResult<T> = Result<T, CodegenError>;
-
-// This is manually implementing Error and Display instead of using thiserror to reduce the amount
-// of dependencies used by Cranelift.
-impl std::error::Error for CodegenError {
-    fn source(&self) -> Option<&(dyn std::error::Error + 'static)> {
-        match self {
-            CodegenError::Verifier(source) => Some(source),
-            CodegenError::ImplLimitExceeded { .. }
-            | CodegenError::CodeTooLarge { .. }
-            | CodegenError::Unsupported { .. } => None,
-            #[cfg(feature = "unwind")]
-            CodegenError::RegisterMappingError { .. } => None,
-        }
-    }
-}
-
-impl std::fmt::Display for CodegenError {
-    fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result {
-        match self {
-            CodegenError::Verifier(_) => write!(f, "Verifier errors"),
-            CodegenError::ImplLimitExceeded => write!(f, "Implementation limit exceeded"),
-            CodegenError::CodeTooLarge => write!(f, "Code for function is too large"),
-            CodegenError::Unsupported(feature) => write!(f, "Unsupported feature: {}", feature),
-            #[cfg(feature = "unwind")]
-            CodegenError::RegisterMappingError(_0) => write!(f, "Register mapping error"),
-        }
-    }
-}
-
-impl From<VerifierErrors> for CodegenError {
-    fn from(source: VerifierErrors) -> Self {
-        CodegenError::Verifier { 0: source }
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/scoped_hash_map.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/scoped_hash_map.rs
deleted file mode 100644
index 809d22132..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/scoped_hash_map.rs
+++ /dev/null
@@ -1,233 +0,0 @@
-//! `ScopedHashMap`
-//!
-//! This module defines a struct `ScopedHashMap<K, V>` which defines a `FxHashMap`-like
-//! container that has a concept of scopes that can be entered and exited, such that
-//! values inserted while inside a scope aren't visible outside the scope.
-
-use crate::fx::FxHashMap;
-use core::hash::Hash;
-use core::mem;
-
-#[cfg(not(feature = "std"))]
-use crate::fx::FxHasher;
-#[cfg(not(feature = "std"))]
-type Hasher = core::hash::BuildHasherDefault<FxHasher>;
-
-struct Val<K, V> {
-    value: V,
-    next_key: Option<K>,
-    depth: usize,
-}
-
-/// A view into an occupied entry in a `ScopedHashMap`. It is part of the `Entry` enum.
-pub struct OccupiedEntry<'a, K: 'a, V: 'a> {
-    #[cfg(feature = "std")]
-    entry: super::hash_map::OccupiedEntry<'a, K, Val<K, V>>,
-    #[cfg(not(feature = "std"))]
-    entry: super::hash_map::OccupiedEntry<'a, K, Val<K, V>, Hasher>,
-}
-
-impl<'a, K, V> OccupiedEntry<'a, K, V> {
-    /// Gets a reference to the value in the entry.
-    pub fn get(&self) -> &V {
-        &self.entry.get().value
-    }
-}
-
-/// A view into a vacant entry in a `ScopedHashMap`. It is part of the `Entry` enum.
-pub struct VacantEntry<'a, K: 'a, V: 'a> {
-    #[cfg(feature = "std")]
-    entry: super::hash_map::VacantEntry<'a, K, Val<K, V>>,
-    #[cfg(not(feature = "std"))]
-    entry: super::hash_map::VacantEntry<'a, K, Val<K, V>, Hasher>,
-    next_key: Option<K>,
-    depth: usize,
-}
-
-impl<'a, K: Hash, V> VacantEntry<'a, K, V> {
-    /// Sets the value of the entry with the `VacantEntry`'s key.
-    pub fn insert(self, value: V) {
-        self.entry.insert(Val {
-            value,
-            next_key: self.next_key,
-            depth: self.depth,
-        });
-    }
-}
-
-/// A view into a single entry in a map, which may either be vacant or occupied.
-///
-/// This enum is constructed from the `entry` method on `ScopedHashMap`.
-pub enum Entry<'a, K: 'a, V: 'a> {
-    Occupied(OccupiedEntry<'a, K, V>),
-    Vacant(VacantEntry<'a, K, V>),
-}
-
-/// A wrapper around a `FxHashMap` which adds the concept of scopes. Items inserted
-/// within a scope are removed when the scope is exited.
-///
-/// Shadowing, where one scope has entries with the same keys as a containing scope,
-/// is not supported in this implementation.
-pub struct ScopedHashMap<K, V> {
-    map: FxHashMap<K, Val<K, V>>,
-    last_insert: Option<K>,
-    current_depth: usize,
-}
-
-impl<K, V> ScopedHashMap<K, V>
-where
-    K: PartialEq + Eq + Hash + Clone,
-{
-    /// Creates an empty `ScopedHashMap`.
-    pub fn new() -> Self {
-        Self {
-            map: FxHashMap(),
-            last_insert: None,
-            current_depth: 0,
-        }
-    }
-
-    /// Similar to `FxHashMap::entry`, gets the given key's corresponding entry in the map for
-    /// in-place manipulation.
-    pub fn entry(&mut self, key: K) -> Entry<K, V> {
-        use super::hash_map::Entry::*;
-        match self.map.entry(key) {
-            Occupied(entry) => Entry::Occupied(OccupiedEntry { entry }),
-            Vacant(entry) => {
-                let clone_key = entry.key().clone();
-                Entry::Vacant(VacantEntry {
-                    entry,
-                    next_key: mem::replace(&mut self.last_insert, Some(clone_key)),
-                    depth: self.current_depth,
-                })
-            }
-        }
-    }
-
-    /// Enter a new scope.
-    pub fn increment_depth(&mut self) {
-        // Increment the depth.
-        self.current_depth = self.current_depth.checked_add(1).unwrap();
-    }
-
-    /// Exit the current scope.
-    pub fn decrement_depth(&mut self) {
-        // Remove all elements inserted at the current depth.
-        while let Some(key) = self.last_insert.clone() {
-            use crate::hash_map::Entry::*;
-            match self.map.entry(key) {
-                Occupied(entry) => {
-                    if entry.get().depth != self.current_depth {
-                        break;
-                    }
-                    self.last_insert = entry.remove_entry().1.next_key;
-                }
-                Vacant(_) => panic!(),
-            }
-        }
-
-        // Decrement the depth.
-        self.current_depth = self.current_depth.checked_sub(1).unwrap();
-    }
-}
-
-#[cfg(test)]
-mod tests {
-    use super::*;
-
-    #[test]
-    fn basic() {
-        let mut map: ScopedHashMap<i32, i32> = ScopedHashMap::new();
-
-        match map.entry(0) {
-            Entry::Occupied(_entry) => panic!(),
-            Entry::Vacant(entry) => entry.insert(1),
-        }
-        match map.entry(2) {
-            Entry::Occupied(_entry) => panic!(),
-            Entry::Vacant(entry) => entry.insert(8),
-        }
-        match map.entry(2) {
-            Entry::Occupied(entry) => assert!(*entry.get() == 8),
-            Entry::Vacant(_entry) => panic!(),
-        }
-        map.increment_depth();
-        match map.entry(2) {
-            Entry::Occupied(entry) => assert!(*entry.get() == 8),
-            Entry::Vacant(_entry) => panic!(),
-        }
-        match map.entry(1) {
-            Entry::Occupied(_entry) => panic!(),
-            Entry::Vacant(entry) => entry.insert(3),
-        }
-        match map.entry(1) {
-            Entry::Occupied(entry) => assert!(*entry.get() == 3),
-            Entry::Vacant(_entry) => panic!(),
-        }
-        match map.entry(0) {
-            Entry::Occupied(entry) => assert!(*entry.get() == 1),
-            Entry::Vacant(_entry) => panic!(),
-        }
-        match map.entry(2) {
-            Entry::Occupied(entry) => assert!(*entry.get() == 8),
-            Entry::Vacant(_entry) => panic!(),
-        }
-        map.decrement_depth();
-        match map.entry(0) {
-            Entry::Occupied(entry) => assert!(*entry.get() == 1),
-            Entry::Vacant(_entry) => panic!(),
-        }
-        match map.entry(2) {
-            Entry::Occupied(entry) => assert!(*entry.get() == 8),
-            Entry::Vacant(_entry) => panic!(),
-        }
-        map.increment_depth();
-        match map.entry(2) {
-            Entry::Occupied(entry) => assert!(*entry.get() == 8),
-            Entry::Vacant(_entry) => panic!(),
-        }
-        match map.entry(1) {
-            Entry::Occupied(_entry) => panic!(),
-            Entry::Vacant(entry) => entry.insert(4),
-        }
-        match map.entry(1) {
-            Entry::Occupied(entry) => assert!(*entry.get() == 4),
-            Entry::Vacant(_entry) => panic!(),
-        }
-        match map.entry(2) {
-            Entry::Occupied(entry) => assert!(*entry.get() == 8),
-            Entry::Vacant(_entry) => panic!(),
-        }
-        map.decrement_depth();
-        map.increment_depth();
-        map.increment_depth();
-        map.increment_depth();
-        match map.entry(2) {
-            Entry::Occupied(entry) => assert!(*entry.get() == 8),
-            Entry::Vacant(_entry) => panic!(),
-        }
-        match map.entry(1) {
-            Entry::Occupied(_entry) => panic!(),
-            Entry::Vacant(entry) => entry.insert(5),
-        }
-        match map.entry(1) {
-            Entry::Occupied(entry) => assert!(*entry.get() == 5),
-            Entry::Vacant(_entry) => panic!(),
-        }
-        match map.entry(2) {
-            Entry::Occupied(entry) => assert!(*entry.get() == 8),
-            Entry::Vacant(_entry) => panic!(),
-        }
-        map.decrement_depth();
-        map.decrement_depth();
-        map.decrement_depth();
-        match map.entry(2) {
-            Entry::Occupied(entry) => assert!(*entry.get() == 8),
-            Entry::Vacant(_entry) => panic!(),
-        }
-        match map.entry(1) {
-            Entry::Occupied(_entry) => panic!(),
-            Entry::Vacant(entry) => entry.insert(3),
-        }
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/settings.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/settings.rs
deleted file mode 100644
index 1842e543f..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/settings.rs
+++ /dev/null
@@ -1,581 +0,0 @@
-//! Shared settings module.
-//!
-//! This module defines data structures to access the settings defined in the meta language.
-//!
-//! Each settings group is translated to a `Flags` struct either in this module or in its
-//! ISA-specific `settings` module. The struct provides individual getter methods for all of the
-//! settings as well as computed predicate flags.
-//!
-//! The `Flags` struct is immutable once it has been created. A `Builder` instance is used to
-//! create it.
-//!
-//! # Example
-//! ```
-//! use cranelift_codegen::settings::{self, Configurable};
-//!
-//! let mut b = settings::builder();
-//! b.set("opt_level", "speed_and_size");
-//!
-//! let f = settings::Flags::new(b);
-//! assert_eq!(f.opt_level(), settings::OptLevel::SpeedAndSize);
-//! ```
-
-use crate::constant_hash::{probe, simple_hash};
-use crate::isa::TargetIsa;
-use alloc::boxed::Box;
-use alloc::string::{String, ToString};
-use core::fmt;
-use core::str;
-
-/// A string-based configurator for settings groups.
-///
-/// The `Configurable` protocol allows settings to be modified by name before a finished `Flags`
-/// struct is created.
-pub trait Configurable {
-    /// Set the string value of any setting by name.
-    ///
-    /// This can set any type of setting whether it is numeric, boolean, or enumerated.
-    fn set(&mut self, name: &str, value: &str) -> SetResult<()>;
-
-    /// Enable a boolean setting or apply a preset.
-    ///
-    /// If the identified setting isn't a boolean or a preset, a `BadType` error is returned.
-    fn enable(&mut self, name: &str) -> SetResult<()>;
-}
-
-/// Represents the kind of setting.
-#[derive(Clone, Copy, Debug, Eq, PartialEq)]
-pub enum SettingKind {
-    /// The setting is an enumeration.
-    Enum,
-    /// The setting is a number.
-    Num,
-    /// The setting is a boolean.
-    Bool,
-    /// The setting is a preset.
-    Preset,
-}
-
-/// Represents an available builder setting.
-///
-/// This is used for iterating settings in a builder.
-#[derive(Clone, Copy, Debug)]
-pub struct Setting {
-    /// The name of the setting.
-    pub name: &'static str,
-    /// The description of the setting.
-    pub description: &'static str,
-    /// The kind of the setting.
-    pub kind: SettingKind,
-    /// The supported values of the setting (for enum values).
-    pub values: Option<&'static [&'static str]>,
-}
-
-/// Represents a setting value.
-///
-/// This is used for iterating values in `Flags`.
-pub struct Value {
-    /// The name of the setting associated with this value.
-    pub name: &'static str,
-    pub(crate) detail: detail::Detail,
-    pub(crate) values: Option<&'static [&'static str]>,
-    pub(crate) value: u8,
-}
-
-impl Value {
-    /// Gets the kind of setting.
-    pub fn kind(&self) -> SettingKind {
-        match &self.detail {
-            detail::Detail::Enum { .. } => SettingKind::Enum,
-            detail::Detail::Num => SettingKind::Num,
-            detail::Detail::Bool { .. } => SettingKind::Bool,
-            detail::Detail::Preset => unreachable!(),
-        }
-    }
-
-    /// Gets the enum value if the value is from an enum setting.
-    pub fn as_enum(&self) -> Option<&'static str> {
-        self.values.map(|v| v[self.value as usize])
-    }
-
-    /// Gets the numerical value if the value is from a num setting.
-    pub fn as_num(&self) -> Option<u8> {
-        match &self.detail {
-            detail::Detail::Num => Some(self.value),
-            _ => None,
-        }
-    }
-
-    /// Gets the boolean value if the value is from a boolean setting.
-    pub fn as_bool(&self) -> Option<bool> {
-        match &self.detail {
-            detail::Detail::Bool { bit } => Some(self.value & (1 << bit) != 0),
-            _ => None,
-        }
-    }
-}
-
-impl fmt::Display for Value {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        if let Some(enum_variant) = self.as_enum() {
-            write!(f, "{}={}", self.name, enum_variant)
-        } else if let Some(num) = self.as_num() {
-            write!(f, "{}={}", self.name, num)
-        } else if let Some(b) = self.as_bool() {
-            if b {
-                write!(f, "{}=1", self.name)
-            } else {
-                write!(f, "{}=0", self.name)
-            }
-        } else {
-            unreachable!()
-        }
-    }
-}
-
-/// Collect settings values based on a template.
-#[derive(Clone, Hash)]
-pub struct Builder {
-    template: &'static detail::Template,
-    bytes: Box<[u8]>,
-}
-
-impl Builder {
-    /// Create a new builder with defaults and names from the given template.
-    pub fn new(tmpl: &'static detail::Template) -> Self {
-        Self {
-            template: tmpl,
-            bytes: tmpl.defaults.into(),
-        }
-    }
-
-    /// Extract contents of builder once everything is configured.
-    pub fn state_for(self, name: &str) -> Box<[u8]> {
-        assert_eq!(name, self.template.name);
-        self.bytes
-    }
-
-    /// Iterates the available settings in the builder.
-    pub fn iter(&self) -> impl Iterator<Item = Setting> {
-        let template = self.template;
-
-        template.descriptors.iter().map(move |d| {
-            let (kind, values) = match d.detail {
-                detail::Detail::Enum { last, enumerators } => {
-                    let values = template.enums(last, enumerators);
-                    (SettingKind::Enum, Some(values))
-                }
-                detail::Detail::Num => (SettingKind::Num, None),
-                detail::Detail::Bool { .. } => (SettingKind::Bool, None),
-                detail::Detail::Preset => (SettingKind::Preset, None),
-            };
-
-            Setting {
-                name: d.name,
-                description: d.description,
-                kind,
-                values,
-            }
-        })
-    }
-
-    /// Set the value of a single bit.
-    fn set_bit(&mut self, offset: usize, bit: u8, value: bool) {
-        let byte = &mut self.bytes[offset];
-        let mask = 1 << bit;
-        if value {
-            *byte |= mask;
-        } else {
-            *byte &= !mask;
-        }
-    }
-
-    /// Apply a preset. The argument is a slice of (mask, value) bytes.
-    fn apply_preset(&mut self, values: &[(u8, u8)]) {
-        for (byte, &(mask, value)) in self.bytes.iter_mut().zip(values) {
-            *byte = (*byte & !mask) | value;
-        }
-    }
-
-    /// Look up a descriptor by name.
-    fn lookup(&self, name: &str) -> SetResult<(usize, detail::Detail)> {
-        match probe(self.template, name, simple_hash(name)) {
-            Err(_) => Err(SetError::BadName(name.to_string())),
-            Ok(entry) => {
-                let d = &self.template.descriptors[self.template.hash_table[entry] as usize];
-                Ok((d.offset as usize, d.detail))
-            }
-        }
-    }
-}
-
-fn parse_bool_value(value: &str) -> SetResult<bool> {
-    match value {
-        "true" | "on" | "yes" | "1" => Ok(true),
-        "false" | "off" | "no" | "0" => Ok(false),
-        _ => Err(SetError::BadValue("bool".to_string())),
-    }
-}
-
-fn parse_enum_value(value: &str, choices: &[&str]) -> SetResult<u8> {
-    match choices.iter().position(|&tag| tag == value) {
-        Some(idx) => Ok(idx as u8),
-        None => {
-            // TODO: Use `join` instead of this code, once
-            // https://github.com/rust-lang/rust/issues/27747 is resolved.
-            let mut all_choices = String::new();
-            let mut first = true;
-            for choice in choices {
-                if first {
-                    first = false
-                } else {
-                    all_choices += ", ";
-                }
-                all_choices += choice;
-            }
-            Err(SetError::BadValue(format!("any among {}", all_choices)))
-        }
-    }
-}
-
-impl Configurable for Builder {
-    fn enable(&mut self, name: &str) -> SetResult<()> {
-        use self::detail::Detail;
-        let (offset, detail) = self.lookup(name)?;
-        match detail {
-            Detail::Bool { bit } => {
-                self.set_bit(offset, bit, true);
-                Ok(())
-            }
-            Detail::Preset => {
-                self.apply_preset(&self.template.presets[offset..]);
-                Ok(())
-            }
-            _ => Err(SetError::BadType),
-        }
-    }
-
-    fn set(&mut self, name: &str, value: &str) -> SetResult<()> {
-        use self::detail::Detail;
-        let (offset, detail) = self.lookup(name)?;
-        match detail {
-            Detail::Bool { bit } => {
-                self.set_bit(offset, bit, parse_bool_value(value)?);
-            }
-            Detail::Num => {
-                self.bytes[offset] = value
-                    .parse()
-                    .map_err(|_| SetError::BadValue("number".to_string()))?;
-            }
-            Detail::Enum { last, enumerators } => {
-                self.bytes[offset] =
-                    parse_enum_value(value, self.template.enums(last, enumerators))?;
-            }
-            Detail::Preset => return Err(SetError::BadName(name.to_string())),
-        }
-        Ok(())
-    }
-}
-
-/// An error produced when changing a setting.
-#[derive(Debug, PartialEq, Eq)]
-pub enum SetError {
-    /// No setting by this name exists.
-    BadName(String),
-
-    /// Type mismatch for setting (e.g., setting an enum setting as a bool).
-    BadType,
-
-    /// This is not a valid value for this setting.
-    BadValue(String),
-}
-
-impl std::error::Error for SetError {}
-
-impl fmt::Display for SetError {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        match self {
-            SetError::BadName(name) => write!(f, "No existing setting named '{}'", name),
-            SetError::BadType => {
-                write!(f, "Trying to set a setting with the wrong type")
-            }
-            SetError::BadValue(value) => {
-                write!(f, "Unexpected value for a setting, expected {}", value)
-            }
-        }
-    }
-}
-
-/// A result returned when changing a setting.
-pub type SetResult<T> = Result<T, SetError>;
-
-/// A reference to just the boolean predicates of a settings object.
-///
-/// The settings objects themselves are generated and appear in the `isa/*/settings.rs` modules.
-/// Each settings object provides a `predicate_view()` method that makes it possible to query
-/// ISA predicates by number.
-#[derive(Clone, Copy, Hash)]
-pub struct PredicateView<'a>(&'a [u8]);
-
-impl<'a> PredicateView<'a> {
-    /// Create a new view of a precomputed predicate vector.
-    ///
-    /// See the `predicate_view()` method on the various `Flags` types defined for each ISA.
-    pub fn new(bits: &'a [u8]) -> Self {
-        PredicateView(bits)
-    }
-
-    /// Check a numbered predicate.
-    pub fn test(self, p: usize) -> bool {
-        self.0[p / 8] & (1 << (p % 8)) != 0
-    }
-}
-
-/// Implementation details for generated code.
-///
-/// This module holds definitions that need to be public so the can be instantiated by generated
-/// code in other modules.
-pub mod detail {
-    use crate::constant_hash;
-    use core::fmt;
-    use core::hash::Hash;
-
-    /// An instruction group template.
-    #[derive(Hash)]
-    pub struct Template {
-        /// Name of the instruction group.
-        pub name: &'static str,
-        /// List of setting descriptors.
-        pub descriptors: &'static [Descriptor],
-        /// Union of all enumerators.
-        pub enumerators: &'static [&'static str],
-        /// Hash table of settings.
-        pub hash_table: &'static [u16],
-        /// Default values.
-        pub defaults: &'static [u8],
-        /// Pairs of (mask, value) for presets.
-        pub presets: &'static [(u8, u8)],
-    }
-
-    impl Template {
-        /// Get enumerators corresponding to a `Details::Enum`.
-        pub fn enums(&self, last: u8, enumerators: u16) -> &[&'static str] {
-            let from = enumerators as usize;
-            let len = usize::from(last) + 1;
-            &self.enumerators[from..from + len]
-        }
-
-        /// Format a setting value as a TOML string. This is mostly for use by the generated
-        /// `Display` implementation.
-        pub fn format_toml_value(
-            &self,
-            detail: Detail,
-            byte: u8,
-            f: &mut fmt::Formatter,
-        ) -> fmt::Result {
-            match detail {
-                Detail::Bool { bit } => write!(f, "{}", (byte & (1 << bit)) != 0),
-                Detail::Num => write!(f, "{}", byte),
-                Detail::Enum { last, enumerators } => {
-                    if byte <= last {
-                        let tags = self.enums(last, enumerators);
-                        write!(f, "\"{}\"", tags[usize::from(byte)])
-                    } else {
-                        write!(f, "{}", byte)
-                    }
-                }
-                // Presets aren't printed. They are reflected in the other settings.
-                Detail::Preset { .. } => Ok(()),
-            }
-        }
-    }
-
-    /// The template contains a hash table for by-name lookup.
-    impl<'a> constant_hash::Table<&'a str> for Template {
-        fn len(&self) -> usize {
-            self.hash_table.len()
-        }
-
-        fn key(&self, idx: usize) -> Option<&'a str> {
-            let e = self.hash_table[idx] as usize;
-            if e < self.descriptors.len() {
-                Some(self.descriptors[e].name)
-            } else {
-                None
-            }
-        }
-    }
-
-    /// A setting descriptor holds the information needed to generically set and print a setting.
-    ///
-    /// Each settings group will be represented as a constant DESCRIPTORS array.
-    #[derive(Hash)]
-    pub struct Descriptor {
-        /// Lower snake-case name of setting as defined in meta.
-        pub name: &'static str,
-
-        /// The description of the setting.
-        pub description: &'static str,
-
-        /// Offset of byte containing this setting.
-        pub offset: u32,
-
-        /// Additional details, depending on the kind of setting.
-        pub detail: Detail,
-    }
-
-    /// The different kind of settings along with descriptor bits that depend on the kind.
-    #[derive(Clone, Copy, Hash)]
-    pub enum Detail {
-        /// A boolean setting only uses one bit, numbered from LSB.
-        Bool {
-            /// 0-7.
-            bit: u8,
-        },
-
-        /// A numerical setting uses the whole byte.
-        Num,
-
-        /// An Enum setting uses a range of enumerators.
-        Enum {
-            /// Numerical value of last enumerator, allowing for 1-256 enumerators.
-            last: u8,
-
-            /// First enumerator in the ENUMERATORS table.
-            enumerators: u16,
-        },
-
-        /// A preset is not an individual setting, it is a collection of settings applied at once.
-        ///
-        /// The `Descriptor::offset` field refers to the `PRESETS` table.
-        Preset,
-    }
-
-    impl Detail {
-        /// Check if a detail is a Detail::Preset. Useful because the Descriptor
-        /// offset field has a different meaning when the detail is a preset.
-        pub fn is_preset(self) -> bool {
-            match self {
-                Self::Preset => true,
-                _ => false,
-            }
-        }
-    }
-}
-
-// Include code generated by `meta/gen_settings.rs`. This file contains a public `Flags` struct
-// with an implementation for all of the settings defined in
-// `cranelift-codegen/meta/src/shared/settings.rs`.
-include!(concat!(env!("OUT_DIR"), "/settings.rs"));
-
-/// Wrapper containing flags and optionally a `TargetIsa` trait object.
-///
-/// A few passes need to access the flags but only optionally a target ISA. The `FlagsOrIsa`
-/// wrapper can be used to pass either, and extract the flags so they are always accessible.
-#[derive(Clone, Copy)]
-pub struct FlagsOrIsa<'a> {
-    /// Flags are always present.
-    pub flags: &'a Flags,
-
-    /// The ISA may not be present.
-    pub isa: Option<&'a dyn TargetIsa>,
-}
-
-impl<'a> From<&'a Flags> for FlagsOrIsa<'a> {
-    fn from(flags: &'a Flags) -> FlagsOrIsa {
-        FlagsOrIsa { flags, isa: None }
-    }
-}
-
-impl<'a> From<&'a dyn TargetIsa> for FlagsOrIsa<'a> {
-    fn from(isa: &'a dyn TargetIsa) -> FlagsOrIsa {
-        FlagsOrIsa {
-            flags: isa.flags(),
-            isa: Some(isa),
-        }
-    }
-}
-
-#[cfg(test)]
-mod tests {
-    use super::Configurable;
-    use super::SetError::*;
-    use super::{builder, Flags};
-    use alloc::string::ToString;
-
-    #[test]
-    fn display_default() {
-        let b = builder();
-        let f = Flags::new(b);
-        assert_eq!(
-            f.to_string(),
-            r#"[shared]
-regalloc = "backtracking"
-opt_level = "none"
-tls_model = "none"
-libcall_call_conv = "isa_default"
-baldrdash_prologue_words = 0
-probestack_size_log2 = 12
-enable_verifier = true
-is_pic = false
-use_colocated_libcalls = false
-avoid_div_traps = false
-enable_float = true
-enable_nan_canonicalization = false
-enable_pinned_reg = false
-use_pinned_reg_as_heap_base = false
-enable_simd = false
-enable_atomics = true
-enable_safepoints = false
-enable_llvm_abi_extensions = false
-unwind_info = true
-machine_code_cfg_info = false
-emit_all_ones_funcaddrs = false
-enable_probestack = true
-probestack_func_adjusts_sp = false
-enable_jump_tables = true
-enable_heap_access_spectre_mitigation = true
-"#
-        );
-        assert_eq!(f.opt_level(), super::OptLevel::None);
-        assert_eq!(f.enable_simd(), false);
-        assert_eq!(f.baldrdash_prologue_words(), 0);
-    }
-
-    #[test]
-    fn modify_bool() {
-        let mut b = builder();
-        assert_eq!(b.enable("not_there"), Err(BadName("not_there".to_string())));
-        assert_eq!(b.enable("enable_simd"), Ok(()));
-        assert_eq!(b.set("enable_simd", "false"), Ok(()));
-
-        let f = Flags::new(b);
-        assert_eq!(f.enable_simd(), false);
-    }
-
-    #[test]
-    fn modify_string() {
-        let mut b = builder();
-        assert_eq!(
-            b.set("not_there", "true"),
-            Err(BadName("not_there".to_string()))
-        );
-        assert_eq!(b.set("enable_simd", ""), Err(BadValue("bool".to_string())));
-        assert_eq!(
-            b.set("enable_simd", "best"),
-            Err(BadValue("bool".to_string()))
-        );
-        assert_eq!(
-            b.set("opt_level", "true"),
-            Err(BadValue(
-                "any among none, speed, speed_and_size".to_string()
-            ))
-        );
-        assert_eq!(b.set("opt_level", "speed"), Ok(()));
-        assert_eq!(b.set("enable_simd", "0"), Ok(()));
-
-        let f = Flags::new(b);
-        assert_eq!(f.enable_simd(), false);
-        assert_eq!(f.opt_level(), super::OptLevel::Speed);
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/simple_gvn.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/simple_gvn.rs
deleted file mode 100644
index 5351aced4..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/simple_gvn.rs
+++ /dev/null
@@ -1,152 +0,0 @@
-//! A simple GVN pass.
-
-use crate::cursor::{Cursor, FuncCursor};
-use crate::dominator_tree::DominatorTree;
-use crate::ir::{Function, Inst, InstructionData, Opcode, Type};
-use crate::scoped_hash_map::ScopedHashMap;
-use crate::timing;
-use alloc::vec::Vec;
-use core::cell::{Ref, RefCell};
-use core::hash::{Hash, Hasher};
-
-/// Test whether the given opcode is unsafe to even consider for GVN.
-fn trivially_unsafe_for_gvn(opcode: Opcode) -> bool {
-    opcode.is_call()
-        || opcode.is_branch()
-        || opcode.is_terminator()
-        || opcode.is_return()
-        || opcode.can_trap()
-        || opcode.other_side_effects()
-        || opcode.can_store()
-        || opcode.writes_cpu_flags()
-}
-
-/// Test that, if the specified instruction is a load, it doesn't have the `readonly` memflag.
-fn is_load_and_not_readonly(inst_data: &InstructionData) -> bool {
-    match *inst_data {
-        InstructionData::Load { flags, .. } | InstructionData::LoadComplex { flags, .. } => {
-            !flags.readonly()
-        }
-        _ => inst_data.opcode().can_load(),
-    }
-}
-
-/// Wrapper around `InstructionData` which implements `Eq` and `Hash`
-#[derive(Clone)]
-struct HashKey<'a, 'f: 'a> {
-    inst: InstructionData,
-    ty: Type,
-    pos: &'a RefCell<FuncCursor<'f>>,
-}
-impl<'a, 'f: 'a> Hash for HashKey<'a, 'f> {
-    fn hash<H: Hasher>(&self, state: &mut H) {
-        let pool = &self.pos.borrow().func.dfg.value_lists;
-        self.inst.hash(state, pool);
-        self.ty.hash(state);
-    }
-}
-impl<'a, 'f: 'a> PartialEq for HashKey<'a, 'f> {
-    fn eq(&self, other: &Self) -> bool {
-        let pool = &self.pos.borrow().func.dfg.value_lists;
-        self.inst.eq(&other.inst, pool) && self.ty == other.ty
-    }
-}
-impl<'a, 'f: 'a> Eq for HashKey<'a, 'f> {}
-
-/// Perform simple GVN on `func`.
-///
-pub fn do_simple_gvn(func: &mut Function, domtree: &mut DominatorTree) {
-    let _tt = timing::gvn();
-    debug_assert!(domtree.is_valid());
-
-    // Visit blocks in a reverse post-order.
-    //
-    // The RefCell here is a bit ugly since the HashKeys in the ScopedHashMap
-    // need a reference to the function.
-    let pos = RefCell::new(FuncCursor::new(func));
-
-    let mut visible_values: ScopedHashMap<HashKey, Inst> = ScopedHashMap::new();
-    let mut scope_stack: Vec<Inst> = Vec::new();
-
-    for &block in domtree.cfg_postorder().iter().rev() {
-        {
-            // Pop any scopes that we just exited.
-            let layout = &pos.borrow().func.layout;
-            loop {
-                if let Some(current) = scope_stack.last() {
-                    if domtree.dominates(*current, block, layout) {
-                        break;
-                    }
-                } else {
-                    break;
-                }
-                scope_stack.pop();
-                visible_values.decrement_depth();
-            }
-
-            // Push a scope for the current block.
-            scope_stack.push(layout.first_inst(block).unwrap());
-            visible_values.increment_depth();
-        }
-
-        pos.borrow_mut().goto_top(block);
-        while let Some(inst) = {
-            let mut pos = pos.borrow_mut();
-            pos.next_inst()
-        } {
-            // Resolve aliases, particularly aliases we created earlier.
-            pos.borrow_mut().func.dfg.resolve_aliases_in_arguments(inst);
-
-            let func = Ref::map(pos.borrow(), |pos| &pos.func);
-
-            let opcode = func.dfg[inst].opcode();
-
-            if opcode.is_branch() && !opcode.is_terminator() {
-                scope_stack.push(func.layout.next_inst(inst).unwrap());
-                visible_values.increment_depth();
-            }
-
-            if trivially_unsafe_for_gvn(opcode) {
-                continue;
-            }
-
-            // These are split up to separate concerns.
-            if is_load_and_not_readonly(&func.dfg[inst]) {
-                continue;
-            }
-
-            let ctrl_typevar = func.dfg.ctrl_typevar(inst);
-            let key = HashKey {
-                inst: func.dfg[inst].clone(),
-                ty: ctrl_typevar,
-                pos: &pos,
-            };
-            use crate::scoped_hash_map::Entry::*;
-            match visible_values.entry(key) {
-                Occupied(entry) => {
-                    #[allow(clippy::debug_assert_with_mut_call)]
-                    {
-                        // Clippy incorrectly believes `&func.layout` should not be used here:
-                        // https://github.com/rust-lang/rust-clippy/issues/4737
-                        debug_assert!(domtree.dominates(*entry.get(), inst, &func.layout));
-                    }
-
-                    // If the redundant instruction is representing the current
-                    // scope, pick a new representative.
-                    let old = scope_stack.last_mut().unwrap();
-                    if *old == inst {
-                        *old = func.layout.next_inst(inst).unwrap();
-                    }
-                    // Replace the redundant instruction and remove it.
-                    drop(func);
-                    let mut pos = pos.borrow_mut();
-                    pos.func.dfg.replace_with_aliases(inst, *entry.get());
-                    pos.remove_inst_and_step_back();
-                }
-                Vacant(entry) => {
-                    entry.insert(inst);
-                }
-            }
-        }
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/simple_preopt.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/simple_preopt.rs
deleted file mode 100644
index 276ff13c6..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/simple_preopt.rs
+++ /dev/null
@@ -1,1054 +0,0 @@
-//! A pre-legalization rewriting pass.
-//!
-//! This module provides early-stage optimizations. The optimizations found
-//! should be useful for already well-optimized code. More general purpose
-//! early-stage optimizations can be found in the preopt crate.
-
-use crate::cursor::{Cursor, FuncCursor};
-use crate::divconst_magic_numbers::{magic_s32, magic_s64, magic_u32, magic_u64};
-use crate::divconst_magic_numbers::{MS32, MS64, MU32, MU64};
-use crate::flowgraph::ControlFlowGraph;
-use crate::ir::{
-    condcodes::{CondCode, IntCC},
-    instructions::Opcode,
-    types::{I32, I64},
-    Block, DataFlowGraph, Function, Inst, InstBuilder, InstructionData, Type, Value,
-};
-use crate::isa::TargetIsa;
-use crate::timing;
-
-#[inline]
-/// Replaces the unique result of the instruction inst to an alias of the given value, and
-/// replaces the instruction with a nop. Can be used only on instructions producing one unique
-/// result, otherwise will assert.
-fn replace_single_result_with_alias(dfg: &mut DataFlowGraph, inst: Inst, value: Value) {
-    // Replace the result value by an alias.
-    let results = dfg.detach_results(inst);
-    debug_assert!(results.len(&dfg.value_lists) == 1);
-    let result = results.get(0, &dfg.value_lists).unwrap();
-    dfg.change_to_alias(result, value);
-
-    // Replace instruction by a nop.
-    dfg.replace(inst).nop();
-}
-
-//----------------------------------------------------------------------
-//
-// Pattern-match helpers and transformation for div and rem by constants.
-
-// Simple math helpers
-
-/// if `x` is a power of two, or the negation thereof, return the power along
-/// with a boolean that indicates whether `x` is negative. Else return None.
-#[inline]
-fn i32_is_power_of_two(x: i32) -> Option<(bool, u32)> {
-    // We have to special-case this because abs(x) isn't representable.
-    if x == -0x8000_0000 {
-        return Some((true, 31));
-    }
-    let abs_x = i32::wrapping_abs(x) as u32;
-    if abs_x.is_power_of_two() {
-        return Some((x < 0, abs_x.trailing_zeros()));
-    }
-    None
-}
-
-/// Same comments as for i32_is_power_of_two apply.
-#[inline]
-fn i64_is_power_of_two(x: i64) -> Option<(bool, u32)> {
-    // We have to special-case this because abs(x) isn't representable.
-    if x == -0x8000_0000_0000_0000 {
-        return Some((true, 63));
-    }
-    let abs_x = i64::wrapping_abs(x) as u64;
-    if abs_x.is_power_of_two() {
-        return Some((x < 0, abs_x.trailing_zeros()));
-    }
-    None
-}
-
-/// Representation of an instruction that can be replaced by a single division/remainder operation
-/// between a left Value operand and a right immediate operand.
-#[derive(Debug)]
-enum DivRemByConstInfo {
-    DivU32(Value, u32),
-    DivU64(Value, u64),
-    DivS32(Value, i32),
-    DivS64(Value, i64),
-    RemU32(Value, u32),
-    RemU64(Value, u64),
-    RemS32(Value, i32),
-    RemS64(Value, i64),
-}
-
-/// Possibly create a DivRemByConstInfo from the given components, by figuring out which, if any,
-/// of the 8 cases apply, and also taking care to sanity-check the immediate.
-fn package_up_divrem_info(
-    value: Value,
-    value_type: Type,
-    imm_i64: i64,
-    is_signed: bool,
-    is_rem: bool,
-) -> Option<DivRemByConstInfo> {
-    let imm_u64 = imm_i64 as u64;
-
-    match (is_signed, value_type) {
-        (false, I32) => {
-            if imm_u64 < 0x1_0000_0000 {
-                if is_rem {
-                    Some(DivRemByConstInfo::RemU32(value, imm_u64 as u32))
-                } else {
-                    Some(DivRemByConstInfo::DivU32(value, imm_u64 as u32))
-                }
-            } else {
-                None
-            }
-        }
-
-        (false, I64) => {
-            // unsigned 64, no range constraint.
-            if is_rem {
-                Some(DivRemByConstInfo::RemU64(value, imm_u64))
-            } else {
-                Some(DivRemByConstInfo::DivU64(value, imm_u64))
-            }
-        }
-
-        (true, I32) => {
-            if imm_u64 <= 0x7fff_ffff || imm_u64 >= 0xffff_ffff_8000_0000 {
-                if is_rem {
-                    Some(DivRemByConstInfo::RemS32(value, imm_u64 as i32))
-                } else {
-                    Some(DivRemByConstInfo::DivS32(value, imm_u64 as i32))
-                }
-            } else {
-                None
-            }
-        }
-
-        (true, I64) => {
-            // signed 64, no range constraint.
-            if is_rem {
-                Some(DivRemByConstInfo::RemS64(value, imm_u64 as i64))
-            } else {
-                Some(DivRemByConstInfo::DivS64(value, imm_u64 as i64))
-            }
-        }
-
-        _ => None,
-    }
-}
-
-/// Examine `inst` to see if it is a div or rem by a constant, and if so return the operands,
-/// signedness, operation size and div-vs-rem-ness in a handy bundle.
-fn get_div_info(inst: Inst, dfg: &DataFlowGraph) -> Option<DivRemByConstInfo> {
-    if let InstructionData::BinaryImm64 { opcode, arg, imm } = dfg[inst] {
-        let (is_signed, is_rem) = match opcode {
-            Opcode::UdivImm => (false, false),
-            Opcode::UremImm => (false, true),
-            Opcode::SdivImm => (true, false),
-            Opcode::SremImm => (true, true),
-            _ => return None,
-        };
-        return package_up_divrem_info(arg, dfg.value_type(arg), imm.into(), is_signed, is_rem);
-    }
-
-    None
-}
-
-/// Actually do the transformation given a bundle containing the relevant information.
-/// `divrem_info` describes a div or rem by a constant, that `pos` currently points at, and `inst`
-/// is the associated instruction.  `inst` is replaced by a sequence of other operations that
-/// calculate the same result. Note that there are various `divrem_info` cases where we cannot do
-/// any transformation, in which case `inst` is left unchanged.
-fn do_divrem_transformation(divrem_info: &DivRemByConstInfo, pos: &mut FuncCursor, inst: Inst) {
-    let is_rem = match *divrem_info {
-        DivRemByConstInfo::DivU32(_, _)
-        | DivRemByConstInfo::DivU64(_, _)
-        | DivRemByConstInfo::DivS32(_, _)
-        | DivRemByConstInfo::DivS64(_, _) => false,
-        DivRemByConstInfo::RemU32(_, _)
-        | DivRemByConstInfo::RemU64(_, _)
-        | DivRemByConstInfo::RemS32(_, _)
-        | DivRemByConstInfo::RemS64(_, _) => true,
-    };
-
-    match *divrem_info {
-        // -------------------- U32 --------------------
-
-        // U32 div, rem by zero: ignore
-        DivRemByConstInfo::DivU32(_n1, 0) | DivRemByConstInfo::RemU32(_n1, 0) => {}
-
-        // U32 div by 1: identity
-        // U32 rem by 1: zero
-        DivRemByConstInfo::DivU32(n1, 1) | DivRemByConstInfo::RemU32(n1, 1) => {
-            if is_rem {
-                pos.func.dfg.replace(inst).iconst(I32, 0);
-            } else {
-                replace_single_result_with_alias(&mut pos.func.dfg, inst, n1);
-            }
-        }
-
-        // U32 div, rem by a power-of-2
-        DivRemByConstInfo::DivU32(n1, d) | DivRemByConstInfo::RemU32(n1, d)
-            if d.is_power_of_two() =>
-        {
-            debug_assert!(d >= 2);
-            // compute k where d == 2^k
-            let k = d.trailing_zeros();
-            debug_assert!(k >= 1 && k <= 31);
-            if is_rem {
-                let mask = (1u64 << k) - 1;
-                pos.func.dfg.replace(inst).band_imm(n1, mask as i64);
-            } else {
-                pos.func.dfg.replace(inst).ushr_imm(n1, k as i64);
-            }
-        }
-
-        // U32 div, rem by non-power-of-2
-        DivRemByConstInfo::DivU32(n1, d) | DivRemByConstInfo::RemU32(n1, d) => {
-            debug_assert!(d >= 3);
-            let MU32 {
-                mul_by,
-                do_add,
-                shift_by,
-            } = magic_u32(d);
-            let qf; // final quotient
-            let q0 = pos.ins().iconst(I32, mul_by as i64);
-            let q1 = pos.ins().umulhi(n1, q0);
-            if do_add {
-                debug_assert!(shift_by >= 1 && shift_by <= 32);
-                let t1 = pos.ins().isub(n1, q1);
-                let t2 = pos.ins().ushr_imm(t1, 1);
-                let t3 = pos.ins().iadd(t2, q1);
-                // I never found any case where shift_by == 1 here.
-                // So there's no attempt to fold out a zero shift.
-                debug_assert_ne!(shift_by, 1);
-                qf = pos.ins().ushr_imm(t3, (shift_by - 1) as i64);
-            } else {
-                debug_assert!(shift_by >= 0 && shift_by <= 31);
-                // Whereas there are known cases here for shift_by == 0.
-                if shift_by > 0 {
-                    qf = pos.ins().ushr_imm(q1, shift_by as i64);
-                } else {
-                    qf = q1;
-                }
-            }
-            // Now qf holds the final quotient. If necessary calculate the
-            // remainder instead.
-            if is_rem {
-                let tt = pos.ins().imul_imm(qf, d as i64);
-                pos.func.dfg.replace(inst).isub(n1, tt);
-            } else {
-                replace_single_result_with_alias(&mut pos.func.dfg, inst, qf);
-            }
-        }
-
-        // -------------------- U64 --------------------
-
-        // U64 div, rem by zero: ignore
-        DivRemByConstInfo::DivU64(_n1, 0) | DivRemByConstInfo::RemU64(_n1, 0) => {}
-
-        // U64 div by 1: identity
-        // U64 rem by 1: zero
-        DivRemByConstInfo::DivU64(n1, 1) | DivRemByConstInfo::RemU64(n1, 1) => {
-            if is_rem {
-                pos.func.dfg.replace(inst).iconst(I64, 0);
-            } else {
-                replace_single_result_with_alias(&mut pos.func.dfg, inst, n1);
-            }
-        }
-
-        // U64 div, rem by a power-of-2
-        DivRemByConstInfo::DivU64(n1, d) | DivRemByConstInfo::RemU64(n1, d)
-            if d.is_power_of_two() =>
-        {
-            debug_assert!(d >= 2);
-            // compute k where d == 2^k
-            let k = d.trailing_zeros();
-            debug_assert!(k >= 1 && k <= 63);
-            if is_rem {
-                let mask = (1u64 << k) - 1;
-                pos.func.dfg.replace(inst).band_imm(n1, mask as i64);
-            } else {
-                pos.func.dfg.replace(inst).ushr_imm(n1, k as i64);
-            }
-        }
-
-        // U64 div, rem by non-power-of-2
-        DivRemByConstInfo::DivU64(n1, d) | DivRemByConstInfo::RemU64(n1, d) => {
-            debug_assert!(d >= 3);
-            let MU64 {
-                mul_by,
-                do_add,
-                shift_by,
-            } = magic_u64(d);
-            let qf; // final quotient
-            let q0 = pos.ins().iconst(I64, mul_by as i64);
-            let q1 = pos.ins().umulhi(n1, q0);
-            if do_add {
-                debug_assert!(shift_by >= 1 && shift_by <= 64);
-                let t1 = pos.ins().isub(n1, q1);
-                let t2 = pos.ins().ushr_imm(t1, 1);
-                let t3 = pos.ins().iadd(t2, q1);
-                // I never found any case where shift_by == 1 here.
-                // So there's no attempt to fold out a zero shift.
-                debug_assert_ne!(shift_by, 1);
-                qf = pos.ins().ushr_imm(t3, (shift_by - 1) as i64);
-            } else {
-                debug_assert!(shift_by >= 0 && shift_by <= 63);
-                // Whereas there are known cases here for shift_by == 0.
-                if shift_by > 0 {
-                    qf = pos.ins().ushr_imm(q1, shift_by as i64);
-                } else {
-                    qf = q1;
-                }
-            }
-            // Now qf holds the final quotient. If necessary calculate the
-            // remainder instead.
-            if is_rem {
-                let tt = pos.ins().imul_imm(qf, d as i64);
-                pos.func.dfg.replace(inst).isub(n1, tt);
-            } else {
-                replace_single_result_with_alias(&mut pos.func.dfg, inst, qf);
-            }
-        }
-
-        // -------------------- S32 --------------------
-
-        // S32 div, rem by zero or -1: ignore
-        DivRemByConstInfo::DivS32(_n1, -1)
-        | DivRemByConstInfo::RemS32(_n1, -1)
-        | DivRemByConstInfo::DivS32(_n1, 0)
-        | DivRemByConstInfo::RemS32(_n1, 0) => {}
-
-        // S32 div by 1: identity
-        // S32 rem by 1: zero
-        DivRemByConstInfo::DivS32(n1, 1) | DivRemByConstInfo::RemS32(n1, 1) => {
-            if is_rem {
-                pos.func.dfg.replace(inst).iconst(I32, 0);
-            } else {
-                replace_single_result_with_alias(&mut pos.func.dfg, inst, n1);
-            }
-        }
-
-        DivRemByConstInfo::DivS32(n1, d) | DivRemByConstInfo::RemS32(n1, d) => {
-            if let Some((is_negative, k)) = i32_is_power_of_two(d) {
-                // k can be 31 only in the case that d is -2^31.
-                debug_assert!(k >= 1 && k <= 31);
-                let t1 = if k - 1 == 0 {
-                    n1
-                } else {
-                    pos.ins().sshr_imm(n1, (k - 1) as i64)
-                };
-                let t2 = pos.ins().ushr_imm(t1, (32 - k) as i64);
-                let t3 = pos.ins().iadd(n1, t2);
-                if is_rem {
-                    // S32 rem by a power-of-2
-                    let t4 = pos.ins().band_imm(t3, i32::wrapping_neg(1 << k) as i64);
-                    // Curiously, we don't care here what the sign of d is.
-                    pos.func.dfg.replace(inst).isub(n1, t4);
-                } else {
-                    // S32 div by a power-of-2
-                    let t4 = pos.ins().sshr_imm(t3, k as i64);
-                    if is_negative {
-                        pos.func.dfg.replace(inst).irsub_imm(t4, 0);
-                    } else {
-                        replace_single_result_with_alias(&mut pos.func.dfg, inst, t4);
-                    }
-                }
-            } else {
-                // S32 div, rem by a non-power-of-2
-                debug_assert!(d < -2 || d > 2);
-                let MS32 { mul_by, shift_by } = magic_s32(d);
-                let q0 = pos.ins().iconst(I32, mul_by as i64);
-                let q1 = pos.ins().smulhi(n1, q0);
-                let q2 = if d > 0 && mul_by < 0 {
-                    pos.ins().iadd(q1, n1)
-                } else if d < 0 && mul_by > 0 {
-                    pos.ins().isub(q1, n1)
-                } else {
-                    q1
-                };
-                debug_assert!(shift_by >= 0 && shift_by <= 31);
-                let q3 = if shift_by == 0 {
-                    q2
-                } else {
-                    pos.ins().sshr_imm(q2, shift_by as i64)
-                };
-                let t1 = pos.ins().ushr_imm(q3, 31);
-                let qf = pos.ins().iadd(q3, t1);
-                // Now qf holds the final quotient. If necessary calculate
-                // the remainder instead.
-                if is_rem {
-                    let tt = pos.ins().imul_imm(qf, d as i64);
-                    pos.func.dfg.replace(inst).isub(n1, tt);
-                } else {
-                    replace_single_result_with_alias(&mut pos.func.dfg, inst, qf);
-                }
-            }
-        }
-
-        // -------------------- S64 --------------------
-
-        // S64 div, rem by zero or -1: ignore
-        DivRemByConstInfo::DivS64(_n1, -1)
-        | DivRemByConstInfo::RemS64(_n1, -1)
-        | DivRemByConstInfo::DivS64(_n1, 0)
-        | DivRemByConstInfo::RemS64(_n1, 0) => {}
-
-        // S64 div by 1: identity
-        // S64 rem by 1: zero
-        DivRemByConstInfo::DivS64(n1, 1) | DivRemByConstInfo::RemS64(n1, 1) => {
-            if is_rem {
-                pos.func.dfg.replace(inst).iconst(I64, 0);
-            } else {
-                replace_single_result_with_alias(&mut pos.func.dfg, inst, n1);
-            }
-        }
-
-        DivRemByConstInfo::DivS64(n1, d) | DivRemByConstInfo::RemS64(n1, d) => {
-            if let Some((is_negative, k)) = i64_is_power_of_two(d) {
-                // k can be 63 only in the case that d is -2^63.
-                debug_assert!(k >= 1 && k <= 63);
-                let t1 = if k - 1 == 0 {
-                    n1
-                } else {
-                    pos.ins().sshr_imm(n1, (k - 1) as i64)
-                };
-                let t2 = pos.ins().ushr_imm(t1, (64 - k) as i64);
-                let t3 = pos.ins().iadd(n1, t2);
-                if is_rem {
-                    // S64 rem by a power-of-2
-                    let t4 = pos.ins().band_imm(t3, i64::wrapping_neg(1 << k));
-                    // Curiously, we don't care here what the sign of d is.
-                    pos.func.dfg.replace(inst).isub(n1, t4);
-                } else {
-                    // S64 div by a power-of-2
-                    let t4 = pos.ins().sshr_imm(t3, k as i64);
-                    if is_negative {
-                        pos.func.dfg.replace(inst).irsub_imm(t4, 0);
-                    } else {
-                        replace_single_result_with_alias(&mut pos.func.dfg, inst, t4);
-                    }
-                }
-            } else {
-                // S64 div, rem by a non-power-of-2
-                debug_assert!(d < -2 || d > 2);
-                let MS64 { mul_by, shift_by } = magic_s64(d);
-                let q0 = pos.ins().iconst(I64, mul_by);
-                let q1 = pos.ins().smulhi(n1, q0);
-                let q2 = if d > 0 && mul_by < 0 {
-                    pos.ins().iadd(q1, n1)
-                } else if d < 0 && mul_by > 0 {
-                    pos.ins().isub(q1, n1)
-                } else {
-                    q1
-                };
-                debug_assert!(shift_by >= 0 && shift_by <= 63);
-                let q3 = if shift_by == 0 {
-                    q2
-                } else {
-                    pos.ins().sshr_imm(q2, shift_by as i64)
-                };
-                let t1 = pos.ins().ushr_imm(q3, 63);
-                let qf = pos.ins().iadd(q3, t1);
-                // Now qf holds the final quotient. If necessary calculate
-                // the remainder instead.
-                if is_rem {
-                    let tt = pos.ins().imul_imm(qf, d);
-                    pos.func.dfg.replace(inst).isub(n1, tt);
-                } else {
-                    replace_single_result_with_alias(&mut pos.func.dfg, inst, qf);
-                }
-            }
-        }
-    }
-}
-
-enum BranchOrderKind {
-    BrzToBrnz(Value),
-    BrnzToBrz(Value),
-    InvertIcmpCond(IntCC, Value, Value),
-}
-
-/// Reorder branches to encourage fallthroughs.
-///
-/// When a block ends with a conditional branch followed by an unconditional
-/// branch, this will reorder them if one of them is branching to the next Block
-/// layout-wise. The unconditional jump can then become a fallthrough.
-fn branch_order(pos: &mut FuncCursor, cfg: &mut ControlFlowGraph, block: Block, inst: Inst) {
-    let (term_inst, term_inst_args, term_dest, cond_inst, cond_inst_args, cond_dest, kind) =
-        match pos.func.dfg[inst] {
-            InstructionData::Jump {
-                opcode: Opcode::Jump,
-                destination,
-                ref args,
-            } => {
-                let next_block = if let Some(next_block) = pos.func.layout.next_block(block) {
-                    next_block
-                } else {
-                    return;
-                };
-
-                if destination == next_block {
-                    return;
-                }
-
-                let prev_inst = if let Some(prev_inst) = pos.func.layout.prev_inst(inst) {
-                    prev_inst
-                } else {
-                    return;
-                };
-
-                let prev_inst_data = &pos.func.dfg[prev_inst];
-
-                if let Some(prev_dest) = prev_inst_data.branch_destination() {
-                    if prev_dest != next_block {
-                        return;
-                    }
-                } else {
-                    return;
-                }
-
-                match prev_inst_data {
-                    InstructionData::Branch {
-                        opcode,
-                        args: ref prev_args,
-                        destination: cond_dest,
-                    } => {
-                        let cond_arg = {
-                            let args = pos.func.dfg.inst_args(prev_inst);
-                            args[0]
-                        };
-
-                        let kind = match opcode {
-                            Opcode::Brz => BranchOrderKind::BrzToBrnz(cond_arg),
-                            Opcode::Brnz => BranchOrderKind::BrnzToBrz(cond_arg),
-                            _ => panic!("unexpected opcode"),
-                        };
-
-                        (
-                            inst,
-                            args.clone(),
-                            destination,
-                            prev_inst,
-                            prev_args.clone(),
-                            *cond_dest,
-                            kind,
-                        )
-                    }
-                    InstructionData::BranchIcmp {
-                        opcode: Opcode::BrIcmp,
-                        cond,
-                        destination: cond_dest,
-                        args: ref prev_args,
-                    } => {
-                        let (x_arg, y_arg) = {
-                            let args = pos.func.dfg.inst_args(prev_inst);
-                            (args[0], args[1])
-                        };
-
-                        (
-                            inst,
-                            args.clone(),
-                            destination,
-                            prev_inst,
-                            prev_args.clone(),
-                            *cond_dest,
-                            BranchOrderKind::InvertIcmpCond(*cond, x_arg, y_arg),
-                        )
-                    }
-                    _ => return,
-                }
-            }
-
-            _ => return,
-        };
-
-    let cond_args = cond_inst_args.as_slice(&pos.func.dfg.value_lists).to_vec();
-    let term_args = term_inst_args.as_slice(&pos.func.dfg.value_lists).to_vec();
-
-    match kind {
-        BranchOrderKind::BrnzToBrz(cond_arg) => {
-            pos.func
-                .dfg
-                .replace(term_inst)
-                .jump(cond_dest, &cond_args[1..]);
-            pos.func
-                .dfg
-                .replace(cond_inst)
-                .brz(cond_arg, term_dest, &term_args);
-        }
-        BranchOrderKind::BrzToBrnz(cond_arg) => {
-            pos.func
-                .dfg
-                .replace(term_inst)
-                .jump(cond_dest, &cond_args[1..]);
-            pos.func
-                .dfg
-                .replace(cond_inst)
-                .brnz(cond_arg, term_dest, &term_args);
-        }
-        BranchOrderKind::InvertIcmpCond(cond, x_arg, y_arg) => {
-            pos.func
-                .dfg
-                .replace(term_inst)
-                .jump(cond_dest, &cond_args[2..]);
-            pos.func.dfg.replace(cond_inst).br_icmp(
-                cond.inverse(),
-                x_arg,
-                y_arg,
-                term_dest,
-                &term_args,
-            );
-        }
-    }
-
-    cfg.recompute_block(pos.func, block);
-}
-
-mod simplify {
-    use super::*;
-    use crate::ir::{
-        dfg::ValueDef,
-        immediates,
-        instructions::{Opcode, ValueList},
-        types::{B8, I16, I32, I8},
-    };
-    use std::marker::PhantomData;
-
-    pub struct PeepholeOptimizer<'a, 'b> {
-        phantom: PhantomData<(&'a (), &'b ())>,
-    }
-
-    pub fn peephole_optimizer<'a, 'b>(_: &dyn TargetIsa) -> PeepholeOptimizer<'a, 'b> {
-        PeepholeOptimizer {
-            phantom: PhantomData,
-        }
-    }
-
-    pub fn apply_all<'a, 'b>(
-        _optimizer: &mut PeepholeOptimizer<'a, 'b>,
-        pos: &mut FuncCursor<'a>,
-        inst: Inst,
-        native_word_width: u32,
-    ) {
-        simplify(pos, inst, native_word_width);
-        branch_opt(pos, inst);
-    }
-
-    #[inline]
-    fn resolve_imm64_value(dfg: &DataFlowGraph, value: Value) -> Option<immediates::Imm64> {
-        if let ValueDef::Result(candidate_inst, _) = dfg.value_def(value) {
-            if let InstructionData::UnaryImm {
-                opcode: Opcode::Iconst,
-                imm,
-            } = dfg[candidate_inst]
-            {
-                return Some(imm);
-            }
-        }
-        None
-    }
-
-    /// Try to transform [(x << N) >> N] into a (un)signed-extending move.
-    /// Returns true if the final instruction has been converted to such a move.
-    fn try_fold_extended_move(
-        pos: &mut FuncCursor,
-        inst: Inst,
-        opcode: Opcode,
-        arg: Value,
-        imm: immediates::Imm64,
-    ) -> bool {
-        if let ValueDef::Result(arg_inst, _) = pos.func.dfg.value_def(arg) {
-            if let InstructionData::BinaryImm64 {
-                opcode: Opcode::IshlImm,
-                arg: prev_arg,
-                imm: prev_imm,
-            } = &pos.func.dfg[arg_inst]
-            {
-                if imm != *prev_imm {
-                    return false;
-                }
-
-                let dest_ty = pos.func.dfg.ctrl_typevar(inst);
-                if dest_ty != pos.func.dfg.ctrl_typevar(arg_inst) || !dest_ty.is_int() {
-                    return false;
-                }
-
-                let imm_bits: i64 = imm.into();
-                let ireduce_ty = match (dest_ty.lane_bits() as i64).wrapping_sub(imm_bits) {
-                    8 => I8,
-                    16 => I16,
-                    32 => I32,
-                    _ => return false,
-                };
-                let ireduce_ty = ireduce_ty.by(dest_ty.lane_count()).unwrap();
-
-                // This becomes a no-op, since ireduce_ty has a smaller lane width than
-                // the argument type (also the destination type).
-                let arg = *prev_arg;
-                let narrower_arg = pos.ins().ireduce(ireduce_ty, arg);
-
-                if opcode == Opcode::UshrImm {
-                    pos.func.dfg.replace(inst).uextend(dest_ty, narrower_arg);
-                } else {
-                    pos.func.dfg.replace(inst).sextend(dest_ty, narrower_arg);
-                }
-                return true;
-            }
-        }
-        false
-    }
-
-    /// Apply basic simplifications.
-    ///
-    /// This folds constants with arithmetic to form `_imm` instructions, and other minor
-    /// simplifications.
-    ///
-    /// Doesn't apply some simplifications if the native word width (in bytes) is smaller than the
-    /// controlling type's width of the instruction. This would result in an illegal instruction that
-    /// would likely be expanded back into an instruction on smaller types with the same initial
-    /// opcode, creating unnecessary churn.
-    fn simplify(pos: &mut FuncCursor, inst: Inst, native_word_width: u32) {
-        match pos.func.dfg[inst] {
-            InstructionData::Binary { opcode, args } => {
-                if let Some(mut imm) = resolve_imm64_value(&pos.func.dfg, args[1]) {
-                    let new_opcode = match opcode {
-                        Opcode::Iadd => Opcode::IaddImm,
-                        Opcode::Imul => Opcode::ImulImm,
-                        Opcode::Sdiv => Opcode::SdivImm,
-                        Opcode::Udiv => Opcode::UdivImm,
-                        Opcode::Srem => Opcode::SremImm,
-                        Opcode::Urem => Opcode::UremImm,
-                        Opcode::Band => Opcode::BandImm,
-                        Opcode::Bor => Opcode::BorImm,
-                        Opcode::Bxor => Opcode::BxorImm,
-                        Opcode::Rotl => Opcode::RotlImm,
-                        Opcode::Rotr => Opcode::RotrImm,
-                        Opcode::Ishl => Opcode::IshlImm,
-                        Opcode::Ushr => Opcode::UshrImm,
-                        Opcode::Sshr => Opcode::SshrImm,
-                        Opcode::Isub => {
-                            imm = imm.wrapping_neg();
-                            Opcode::IaddImm
-                        }
-                        Opcode::Ifcmp => Opcode::IfcmpImm,
-                        _ => return,
-                    };
-                    let ty = pos.func.dfg.ctrl_typevar(inst);
-                    if ty.bytes() <= native_word_width {
-                        pos.func
-                            .dfg
-                            .replace(inst)
-                            .BinaryImm64(new_opcode, ty, imm, args[0]);
-
-                        // Repeat for BinaryImm simplification.
-                        simplify(pos, inst, native_word_width);
-                    }
-                } else if let Some(imm) = resolve_imm64_value(&pos.func.dfg, args[0]) {
-                    let new_opcode = match opcode {
-                        Opcode::Iadd => Opcode::IaddImm,
-                        Opcode::Imul => Opcode::ImulImm,
-                        Opcode::Band => Opcode::BandImm,
-                        Opcode::Bor => Opcode::BorImm,
-                        Opcode::Bxor => Opcode::BxorImm,
-                        Opcode::Isub => Opcode::IrsubImm,
-                        _ => return,
-                    };
-                    let ty = pos.func.dfg.ctrl_typevar(inst);
-                    if ty.bytes() <= native_word_width {
-                        pos.func
-                            .dfg
-                            .replace(inst)
-                            .BinaryImm64(new_opcode, ty, imm, args[1]);
-                    }
-                }
-            }
-
-            InstructionData::BinaryImm64 { opcode, arg, imm } => {
-                let ty = pos.func.dfg.ctrl_typevar(inst);
-
-                let mut arg = arg;
-                let mut imm = imm;
-                match opcode {
-                    Opcode::IaddImm
-                    | Opcode::ImulImm
-                    | Opcode::BorImm
-                    | Opcode::BandImm
-                    | Opcode::BxorImm => {
-                        // Fold binary_op(C2, binary_op(C1, x)) into binary_op(binary_op(C1, C2), x)
-                        if let ValueDef::Result(arg_inst, _) = pos.func.dfg.value_def(arg) {
-                            if let InstructionData::BinaryImm64 {
-                                opcode: prev_opcode,
-                                arg: prev_arg,
-                                imm: prev_imm,
-                            } = &pos.func.dfg[arg_inst]
-                            {
-                                if opcode == *prev_opcode
-                                    && ty == pos.func.dfg.ctrl_typevar(arg_inst)
-                                {
-                                    let lhs: i64 = imm.into();
-                                    let rhs: i64 = (*prev_imm).into();
-                                    let new_imm = match opcode {
-                                        Opcode::BorImm => lhs | rhs,
-                                        Opcode::BandImm => lhs & rhs,
-                                        Opcode::BxorImm => lhs ^ rhs,
-                                        Opcode::IaddImm => lhs.wrapping_add(rhs),
-                                        Opcode::ImulImm => lhs.wrapping_mul(rhs),
-                                        _ => panic!("can't happen"),
-                                    };
-                                    let new_imm = immediates::Imm64::from(new_imm);
-                                    let new_arg = *prev_arg;
-                                    pos.func
-                                        .dfg
-                                        .replace(inst)
-                                        .BinaryImm64(opcode, ty, new_imm, new_arg);
-                                    imm = new_imm;
-                                    arg = new_arg;
-                                }
-                            }
-                        }
-                    }
-
-                    Opcode::UshrImm | Opcode::SshrImm => {
-                        if pos.func.dfg.ctrl_typevar(inst).bytes() <= native_word_width
-                            && try_fold_extended_move(pos, inst, opcode, arg, imm)
-                        {
-                            return;
-                        }
-                    }
-
-                    _ => {}
-                };
-
-                // Replace operations that are no-ops.
-                match (opcode, imm.into()) {
-                    (Opcode::IaddImm, 0)
-                    | (Opcode::ImulImm, 1)
-                    | (Opcode::SdivImm, 1)
-                    | (Opcode::UdivImm, 1)
-                    | (Opcode::BorImm, 0)
-                    | (Opcode::BandImm, -1)
-                    | (Opcode::BxorImm, 0)
-                    | (Opcode::RotlImm, 0)
-                    | (Opcode::RotrImm, 0)
-                    | (Opcode::IshlImm, 0)
-                    | (Opcode::UshrImm, 0)
-                    | (Opcode::SshrImm, 0) => {
-                        // Alias the result value with the original argument.
-                        replace_single_result_with_alias(&mut pos.func.dfg, inst, arg);
-                    }
-                    (Opcode::ImulImm, 0) | (Opcode::BandImm, 0) => {
-                        // Replace by zero.
-                        pos.func.dfg.replace(inst).iconst(ty, 0);
-                    }
-                    (Opcode::BorImm, -1) => {
-                        // Replace by minus one.
-                        pos.func.dfg.replace(inst).iconst(ty, -1);
-                    }
-                    _ => {}
-                }
-            }
-
-            InstructionData::IntCompare { opcode, cond, args } => {
-                debug_assert_eq!(opcode, Opcode::Icmp);
-                if let Some(imm) = resolve_imm64_value(&pos.func.dfg, args[1]) {
-                    if pos.func.dfg.ctrl_typevar(inst).bytes() <= native_word_width {
-                        pos.func.dfg.replace(inst).icmp_imm(cond, args[0], imm);
-                    }
-                }
-            }
-
-            InstructionData::CondTrap { .. }
-            | InstructionData::Branch { .. }
-            | InstructionData::Ternary {
-                opcode: Opcode::Select,
-                ..
-            } => {
-                // Fold away a redundant `bint`.
-                let condition_def = {
-                    let args = pos.func.dfg.inst_args(inst);
-                    pos.func.dfg.value_def(args[0])
-                };
-                if let ValueDef::Result(def_inst, _) = condition_def {
-                    if let InstructionData::Unary {
-                        opcode: Opcode::Bint,
-                        arg: bool_val,
-                    } = pos.func.dfg[def_inst]
-                    {
-                        let args = pos.func.dfg.inst_args_mut(inst);
-                        args[0] = bool_val;
-                    }
-                }
-            }
-
-            InstructionData::Ternary {
-                opcode: Opcode::Bitselect,
-                args,
-            } => {
-                let old_cond_type = pos.func.dfg.value_type(args[0]);
-                if !old_cond_type.is_vector() {
-                    return;
-                }
-
-                // Replace bitselect with vselect if each lane of controlling mask is either
-                // all ones or all zeroes; on x86 bitselect is encoded using 3 instructions,
-                // while vselect can be encoded using single BLEND instruction.
-                if let ValueDef::Result(def_inst, _) = pos.func.dfg.value_def(args[0]) {
-                    let (cond_val, cond_type) = match pos.func.dfg[def_inst] {
-                        InstructionData::Unary {
-                            opcode: Opcode::RawBitcast,
-                            arg,
-                        } => {
-                            // If controlling mask is raw-bitcasted boolean vector then
-                            // we know each lane is either all zeroes or ones,
-                            // so we can use vselect instruction instead.
-                            let arg_type = pos.func.dfg.value_type(arg);
-                            if !arg_type.is_vector() || !arg_type.lane_type().is_bool() {
-                                return;
-                            }
-                            (arg, arg_type)
-                        }
-                        InstructionData::UnaryConst {
-                            opcode: Opcode::Vconst,
-                            constant_handle,
-                        } => {
-                            // If each byte of controlling mask is 0x00 or 0xFF then
-                            // we will always bitcast our way to vselect(B8x16, I8x16, I8x16).
-                            // Bitselect operates at bit level, so the lane types don't matter.
-                            let const_data = pos.func.dfg.constants.get(constant_handle);
-                            if !const_data.iter().all(|&b| b == 0 || b == 0xFF) {
-                                return;
-                            }
-                            let new_type = B8.by(old_cond_type.bytes() as u16).unwrap();
-                            (pos.ins().raw_bitcast(new_type, args[0]), new_type)
-                        }
-                        _ => return,
-                    };
-
-                    let lane_type = Type::int(cond_type.lane_bits() as u16).unwrap();
-                    let arg_type = lane_type.by(cond_type.lane_count()).unwrap();
-                    let old_arg_type = pos.func.dfg.value_type(args[1]);
-
-                    if arg_type != old_arg_type {
-                        // Operands types must match, we need to add bitcasts.
-                        let arg1 = pos.ins().raw_bitcast(arg_type, args[1]);
-                        let arg2 = pos.ins().raw_bitcast(arg_type, args[2]);
-                        let ret = pos.ins().vselect(cond_val, arg1, arg2);
-                        pos.func.dfg.replace(inst).raw_bitcast(old_arg_type, ret);
-                    } else {
-                        pos.func
-                            .dfg
-                            .replace(inst)
-                            .vselect(cond_val, args[1], args[2]);
-                    }
-                }
-            }
-
-            _ => {}
-        }
-    }
-
-    struct BranchOptInfo {
-        br_inst: Inst,
-        cmp_arg: Value,
-        args: ValueList,
-        new_opcode: Opcode,
-    }
-
-    /// Fold comparisons into branch operations when possible.
-    ///
-    /// This matches against operations which compare against zero, then use the
-    /// result in a `brz` or `brnz` branch. It folds those two operations into a
-    /// single `brz` or `brnz`.
-    fn branch_opt(pos: &mut FuncCursor, inst: Inst) {
-        let mut info = if let InstructionData::Branch {
-            opcode: br_opcode,
-            args: ref br_args,
-            ..
-        } = pos.func.dfg[inst]
-        {
-            let first_arg = {
-                let args = pos.func.dfg.inst_args(inst);
-                args[0]
-            };
-
-            let icmp_inst =
-                if let ValueDef::Result(icmp_inst, _) = pos.func.dfg.value_def(first_arg) {
-                    icmp_inst
-                } else {
-                    return;
-                };
-
-            if let InstructionData::IntCompareImm {
-                opcode: Opcode::IcmpImm,
-                arg: cmp_arg,
-                cond: cmp_cond,
-                imm: cmp_imm,
-            } = pos.func.dfg[icmp_inst]
-            {
-                let cmp_imm: i64 = cmp_imm.into();
-                if cmp_imm != 0 {
-                    return;
-                }
-
-                // icmp_imm returns non-zero when the comparison is true. So, if
-                // we're branching on zero, we need to invert the condition.
-                let cond = match br_opcode {
-                    Opcode::Brz => cmp_cond.inverse(),
-                    Opcode::Brnz => cmp_cond,
-                    _ => return,
-                };
-
-                let new_opcode = match cond {
-                    IntCC::Equal => Opcode::Brz,
-                    IntCC::NotEqual => Opcode::Brnz,
-                    _ => return,
-                };
-
-                BranchOptInfo {
-                    br_inst: inst,
-                    cmp_arg,
-                    args: br_args.clone(),
-                    new_opcode,
-                }
-            } else {
-                return;
-            }
-        } else {
-            return;
-        };
-
-        info.args.as_mut_slice(&mut pos.func.dfg.value_lists)[0] = info.cmp_arg;
-        if let InstructionData::Branch { ref mut opcode, .. } = pos.func.dfg[info.br_inst] {
-            *opcode = info.new_opcode;
-        } else {
-            panic!();
-        }
-    }
-}
-
-/// The main pre-opt pass.
-pub fn do_preopt(func: &mut Function, cfg: &mut ControlFlowGraph, isa: &dyn TargetIsa) {
-    let _tt = timing::preopt();
-
-    let mut pos = FuncCursor::new(func);
-    let native_word_width = isa.pointer_bytes() as u32;
-    let mut optimizer = simplify::peephole_optimizer(isa);
-
-    while let Some(block) = pos.next_block() {
-        while let Some(inst) = pos.next_inst() {
-            simplify::apply_all(&mut optimizer, &mut pos, inst, native_word_width);
-
-            // Try to transform divide-by-constant into simpler operations.
-            if let Some(divrem_info) = get_div_info(inst, &pos.func.dfg) {
-                do_divrem_transformation(&divrem_info, &mut pos, inst);
-                continue;
-            }
-
-            branch_order(&mut pos, cfg, block, inst);
-        }
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/souper_harvest.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/souper_harvest.rs
deleted file mode 100644
index 4884ae500..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/souper_harvest.rs
+++ /dev/null
@@ -1,581 +0,0 @@
-//! Harvest left-hand side superoptimization candidates.
-//!
-//! Given a clif function, harvest all its integer subexpressions, so that they
-//! can be fed into [Souper](https://github.com/google/souper) as candidates for
-//! superoptimization. For some of these candidates, Souper will successfully
-//! synthesize a right-hand side that is equivalent but has lower cost than the
-//! left-hand side. Then, we can combine these left- and right-hand sides into a
-//! complete optimization, and add it to our peephole passes.
-//!
-//! To harvest the expression that produced a given value `x`, we do a
-//! post-order traversal of the dataflow graph starting from `x`. As we do this
-//! traversal, we maintain a map from clif values to their translated Souper
-//! values. We stop traversing when we reach anything that can't be translated
-//! into Souper IR: a memory load, a float-to-int conversion, a block parameter,
-//! etc. For values produced by these instructions, we create a Souper `var`,
-//! which is an input variable to the optimization. For instructions that have a
-//! direct mapping into Souper IR, we get the Souper version of each of its
-//! operands and then create the Souper version of the instruction itself. It
-//! should now be clear why we do a post-order traversal: we need an
-//! instruction's translated operands in order to translate the instruction
-//! itself. Once this instruction is translated, we update the clif-to-souper
-//! map with this new translation so that any other instruction that uses this
-//! result as an operand has access to the translated value. When the traversal
-//! is complete we return the translation of `x` as the root of left-hand side
-//! candidate.
-
-use crate::ir;
-use souper_ir::ast;
-use std::collections::{HashMap, HashSet};
-use std::string::String;
-use std::sync::mpsc;
-use std::vec::Vec;
-
-/// Harvest Souper left-hand side candidates from the given function.
-///
-/// Candidates are reported through the given MPSC sender.
-pub fn do_souper_harvest(func: &ir::Function, out: &mut mpsc::Sender<String>) {
-    let mut allocs = Allocs::default();
-
-    // Iterate over each instruction in each block and try and harvest a
-    // left-hand side from its result.
-    for block in func.layout.blocks() {
-        let mut option_inst = func.layout.first_inst(block);
-        while let Some(inst) = option_inst {
-            let results = func.dfg.inst_results(inst);
-            if results.len() == 1 {
-                let val = results[0];
-                let ty = func.dfg.value_type(val);
-                if ty.is_int() && ty.lane_count() == 1 {
-                    harvest_candidate_lhs(&mut allocs, func, val, out);
-                }
-            }
-            option_inst = func.layout.next_inst(inst);
-        }
-    }
-}
-
-/// Allocations that we reuse across many LHS candidate harvests.
-#[derive(Default)]
-struct Allocs {
-    /// A map from cranelift IR to souper IR for values that we've already
-    /// translated into souper IR.
-    ir_to_souper_val: HashMap<ir::Value, ast::ValueId>,
-
-    /// Stack of to-visit and to-trace values for the post-order DFS.
-    dfs_stack: Vec<StackEntry>,
-
-    /// Set of values we've already seen in our post-order DFS.
-    dfs_seen: HashSet<ir::Value>,
-}
-
-impl Allocs {
-    /// Reset the collections to their empty state (without deallocating their
-    /// backing data).
-    fn reset(&mut self) {
-        self.ir_to_souper_val.clear();
-        self.dfs_stack.clear();
-        self.dfs_seen.clear();
-    }
-}
-
-/// Harvest a candidate LHS for `val` from the dataflow graph.
-fn harvest_candidate_lhs(
-    allocs: &mut Allocs,
-    func: &ir::Function,
-    val: ir::Value,
-    out: &mut mpsc::Sender<String>,
-) {
-    allocs.reset();
-    let mut lhs = ast::LeftHandSideBuilder::default();
-    let mut non_var_count = 0;
-
-    // Should we keep tracing through the given `val`? Only if it is defined
-    // by an instruction that we can translate to Souper IR.
-    let should_trace = |val| match func.dfg.value_def(val) {
-        ir::ValueDef::Result(inst, 0) => match func.dfg[inst].opcode() {
-                ir::Opcode::Iadd
-                | ir::Opcode::IaddImm
-                | ir::Opcode::IrsubImm
-                | ir::Opcode::Imul
-                | ir::Opcode::ImulImm
-                | ir::Opcode::Udiv
-                | ir::Opcode::UdivImm
-                | ir::Opcode::Sdiv
-                | ir::Opcode::SdivImm
-                | ir::Opcode::Urem
-                | ir::Opcode::UremImm
-                | ir::Opcode::Srem
-                | ir::Opcode::SremImm
-                | ir::Opcode::Band
-                | ir::Opcode::BandImm
-                | ir::Opcode::Bor
-                | ir::Opcode::BorImm
-                | ir::Opcode::Bxor
-                | ir::Opcode::BxorImm
-                | ir::Opcode::Ishl
-                | ir::Opcode::IshlImm
-                | ir::Opcode::Sshr
-                | ir::Opcode::SshrImm
-                | ir::Opcode::Ushr
-                | ir::Opcode::UshrImm
-                | ir::Opcode::Select
-                | ir::Opcode::Uextend
-                | ir::Opcode::Sextend
-                | ir::Opcode::Trunc
-                | ir::Opcode::Icmp
-                | ir::Opcode::Popcnt
-                | ir::Opcode::Bitrev
-                | ir::Opcode::Clz
-                | ir::Opcode::Ctz
-                // TODO: ir::Opcode::IaddCarry
-                // TODO: ir::Opcode::IaddCout
-                | ir::Opcode::SaddSat
-                | ir::Opcode::SsubSat
-                | ir::Opcode::UsubSat => true,
-                _ => false,
-            },
-        _ => false,
-    };
-
-    post_order_dfs(allocs, &func.dfg, val, should_trace, |allocs, val| {
-        let souper_assignment_rhs = match func.dfg.value_def(val) {
-            ir::ValueDef::Result(inst, 0) => {
-                let args = func.dfg.inst_args(inst);
-
-                // Get the n^th argument as a souper operand.
-                let arg = |allocs: &mut Allocs, n| {
-                    let arg = args[n];
-                    if let Some(a) = allocs.ir_to_souper_val.get(&arg).copied() {
-                        a.into()
-                    } else {
-                        // The only arguments we get that we haven't already
-                        // converted into a souper instruction are `iconst`s and
-                        // `bconst`s. This is because souper only allows
-                        // constants as operands, and it doesn't allow assigning
-                        // constants to a variable name. So we lazily convert
-                        // `iconst`s and `bconst`s into souper operands here,
-                        // when they are actually used.
-                        match func.dfg.value_def(arg) {
-                            ir::ValueDef::Result(inst, 0) => match func.dfg[inst] {
-                                ir::InstructionData::UnaryImm { opcode, imm } => {
-                                    debug_assert_eq!(opcode, ir::Opcode::Iconst);
-                                    let imm: i64 = imm.into();
-                                    ast::Operand::Constant(ast::Constant {
-                                        value: imm.into(),
-                                        r#type: souper_type_of(&func.dfg, arg),
-                                    })
-                                }
-                                ir::InstructionData::UnaryBool { opcode, imm } => {
-                                    debug_assert_eq!(opcode, ir::Opcode::Iconst);
-                                    ast::Operand::Constant(ast::Constant {
-                                        value: imm.into(),
-                                        r#type: souper_type_of(&func.dfg, arg),
-                                    })
-                                }
-                                _ => unreachable!(
-                                    "only iconst and bconst instructions \
-                                     aren't in `ir_to_souper_val`"
-                                ),
-                            },
-                            _ => unreachable!(
-                                "only iconst and bconst instructions \
-                                 aren't in `ir_to_souper_val`"
-                            ),
-                        }
-                    }
-                };
-
-                match (func.dfg[inst].opcode(), &func.dfg[inst]) {
-                    (ir::Opcode::Iadd, _) => {
-                        let a = arg(allocs, 0);
-                        let b = arg(allocs, 1);
-                        ast::Instruction::Add { a, b }.into()
-                    }
-                    (ir::Opcode::IaddImm, ir::InstructionData::BinaryImm64 { imm, .. }) => {
-                        let a = arg(allocs, 0);
-                        let value: i64 = (*imm).into();
-                        let value: i128 = value.into();
-                        let b = ast::Constant {
-                            value,
-                            r#type: souper_type_of(&func.dfg, val),
-                        }
-                        .into();
-                        ast::Instruction::Add { a, b }.into()
-                    }
-                    (ir::Opcode::IrsubImm, ir::InstructionData::BinaryImm64 { imm, .. }) => {
-                        let b = arg(allocs, 0);
-                        let value: i64 = (*imm).into();
-                        let value: i128 = value.into();
-                        let a = ast::Constant {
-                            value,
-                            r#type: souper_type_of(&func.dfg, val),
-                        }
-                        .into();
-                        ast::Instruction::Sub { a, b }.into()
-                    }
-                    (ir::Opcode::Imul, _) => {
-                        let a = arg(allocs, 0);
-                        let b = arg(allocs, 1);
-                        ast::Instruction::Mul { a, b }.into()
-                    }
-                    (ir::Opcode::ImulImm, ir::InstructionData::BinaryImm64 { imm, .. }) => {
-                        let a = arg(allocs, 0);
-                        let value: i64 = (*imm).into();
-                        let value: i128 = value.into();
-                        let b = ast::Constant {
-                            value,
-                            r#type: souper_type_of(&func.dfg, val),
-                        }
-                        .into();
-                        ast::Instruction::Mul { a, b }.into()
-                    }
-                    (ir::Opcode::Udiv, _) => {
-                        let a = arg(allocs, 0);
-                        let b = arg(allocs, 1);
-                        ast::Instruction::Udiv { a, b }.into()
-                    }
-                    (ir::Opcode::UdivImm, ir::InstructionData::BinaryImm64 { imm, .. }) => {
-                        let a = arg(allocs, 0);
-                        let value: i64 = (*imm).into();
-                        let value: i128 = value.into();
-                        let b = ast::Constant {
-                            value,
-                            r#type: souper_type_of(&func.dfg, val),
-                        }
-                        .into();
-                        ast::Instruction::Udiv { a, b }.into()
-                    }
-                    (ir::Opcode::Sdiv, _) => {
-                        let a = arg(allocs, 0);
-                        let b = arg(allocs, 1);
-                        ast::Instruction::Sdiv { a, b }.into()
-                    }
-                    (ir::Opcode::SdivImm, ir::InstructionData::BinaryImm64 { imm, .. }) => {
-                        let a = arg(allocs, 0);
-                        let value: i64 = (*imm).into();
-                        let value: i128 = value.into();
-                        let b = ast::Constant {
-                            value,
-                            r#type: souper_type_of(&func.dfg, val),
-                        }
-                        .into();
-                        ast::Instruction::Sdiv { a, b }.into()
-                    }
-                    (ir::Opcode::Urem, _) => {
-                        let a = arg(allocs, 0);
-                        let b = arg(allocs, 1);
-                        ast::Instruction::Urem { a, b }.into()
-                    }
-                    (ir::Opcode::UremImm, ir::InstructionData::BinaryImm64 { imm, .. }) => {
-                        let a = arg(allocs, 0);
-                        let value: i64 = (*imm).into();
-                        let value: i128 = value.into();
-                        let b = ast::Constant {
-                            value,
-                            r#type: souper_type_of(&func.dfg, val),
-                        }
-                        .into();
-                        ast::Instruction::Urem { a, b }.into()
-                    }
-                    (ir::Opcode::Srem, _) => {
-                        let a = arg(allocs, 0);
-                        let b = arg(allocs, 1);
-                        ast::Instruction::Srem { a, b }.into()
-                    }
-                    (ir::Opcode::SremImm, ir::InstructionData::BinaryImm64 { imm, .. }) => {
-                        let a = arg(allocs, 0);
-                        let value: i64 = (*imm).into();
-                        let value: i128 = value.into();
-                        let b = ast::Constant {
-                            value,
-                            r#type: souper_type_of(&func.dfg, val),
-                        }
-                        .into();
-                        ast::Instruction::Srem { a, b }.into()
-                    }
-                    (ir::Opcode::Band, _) => {
-                        let a = arg(allocs, 0);
-                        let b = arg(allocs, 1);
-                        ast::Instruction::And { a, b }.into()
-                    }
-                    (ir::Opcode::BandImm, ir::InstructionData::BinaryImm64 { imm, .. }) => {
-                        let a = arg(allocs, 0);
-                        let value: i64 = (*imm).into();
-                        let value: i128 = value.into();
-                        let b = ast::Constant {
-                            value,
-                            r#type: souper_type_of(&func.dfg, val),
-                        }
-                        .into();
-                        ast::Instruction::And { a, b }.into()
-                    }
-                    (ir::Opcode::Bor, _) => {
-                        let a = arg(allocs, 0);
-                        let b = arg(allocs, 1);
-                        ast::Instruction::Or { a, b }.into()
-                    }
-                    (ir::Opcode::BorImm, ir::InstructionData::BinaryImm64 { imm, .. }) => {
-                        let a = arg(allocs, 0);
-                        let value: i64 = (*imm).into();
-                        let value: i128 = value.into();
-                        let b = ast::Constant {
-                            value,
-                            r#type: souper_type_of(&func.dfg, val),
-                        }
-                        .into();
-                        ast::Instruction::Or { a, b }.into()
-                    }
-                    (ir::Opcode::Bxor, _) => {
-                        let a = arg(allocs, 0);
-                        let b = arg(allocs, 1);
-                        ast::Instruction::Xor { a, b }.into()
-                    }
-                    (ir::Opcode::BxorImm, ir::InstructionData::BinaryImm64 { imm, .. }) => {
-                        let a = arg(allocs, 0);
-                        let value: i64 = (*imm).into();
-                        let value: i128 = value.into();
-                        let b = ast::Constant {
-                            value,
-                            r#type: souper_type_of(&func.dfg, val),
-                        }
-                        .into();
-                        ast::Instruction::Xor { a, b }.into()
-                    }
-                    (ir::Opcode::Ishl, _) => {
-                        let a = arg(allocs, 0);
-                        let b = arg(allocs, 1);
-                        ast::Instruction::Shl { a, b }.into()
-                    }
-                    (ir::Opcode::IshlImm, ir::InstructionData::BinaryImm64 { imm, .. }) => {
-                        let a = arg(allocs, 0);
-                        let value: i64 = (*imm).into();
-                        let value: i128 = value.into();
-                        let b = ast::Constant {
-                            value,
-                            r#type: souper_type_of(&func.dfg, val),
-                        }
-                        .into();
-                        ast::Instruction::Shl { a, b }.into()
-                    }
-                    (ir::Opcode::Sshr, _) => {
-                        let a = arg(allocs, 0);
-                        let b = arg(allocs, 1);
-                        ast::Instruction::Ashr { a, b }.into()
-                    }
-                    (ir::Opcode::SshrImm, ir::InstructionData::BinaryImm64 { imm, .. }) => {
-                        let a = arg(allocs, 0);
-                        let value: i64 = (*imm).into();
-                        let value: i128 = value.into();
-                        let b = ast::Constant {
-                            value,
-                            r#type: souper_type_of(&func.dfg, val),
-                        }
-                        .into();
-                        ast::Instruction::Ashr { a, b }.into()
-                    }
-                    (ir::Opcode::Ushr, _) => {
-                        let a = arg(allocs, 0);
-                        let b = arg(allocs, 1);
-                        ast::Instruction::Lshr { a, b }.into()
-                    }
-                    (ir::Opcode::UshrImm, ir::InstructionData::BinaryImm64 { imm, .. }) => {
-                        let a = arg(allocs, 0);
-                        let value: i64 = (*imm).into();
-                        let value: i128 = value.into();
-                        let b = ast::Constant {
-                            value,
-                            r#type: souper_type_of(&func.dfg, val),
-                        }
-                        .into();
-                        ast::Instruction::Lshr { a, b }.into()
-                    }
-                    (ir::Opcode::Select, _) => {
-                        let a = arg(allocs, 0);
-
-                        // While Cranelift allows any width condition for
-                        // `select`, Souper requires an `i1`.
-                        let a = match a {
-                            ast::Operand::Value(id) => match lhs.get_value(id).r#type {
-                                Some(ast::Type { width: 1 }) => a,
-                                _ => lhs
-                                    .assignment(
-                                        None,
-                                        Some(ast::Type { width: 1 }),
-                                        ast::Instruction::Trunc { a },
-                                        vec![],
-                                    )
-                                    .into(),
-                            },
-                            ast::Operand::Constant(ast::Constant { value, .. }) => ast::Constant {
-                                value: (value != 0) as _,
-                                r#type: Some(ast::Type { width: 1 }),
-                            }
-                            .into(),
-                        };
-
-                        let b = arg(allocs, 1);
-                        let c = arg(allocs, 2);
-                        ast::Instruction::Select { a, b, c }.into()
-                    }
-                    (ir::Opcode::Uextend, _) => {
-                        let a = arg(allocs, 0);
-                        ast::Instruction::Zext { a }.into()
-                    }
-                    (ir::Opcode::Sextend, _) => {
-                        let a = arg(allocs, 0);
-                        ast::Instruction::Sext { a }.into()
-                    }
-                    (ir::Opcode::Trunc, _) => {
-                        let a = arg(allocs, 0);
-                        ast::Instruction::Trunc { a }.into()
-                    }
-                    (ir::Opcode::Icmp, ir::InstructionData::IntCompare { cond, .. })
-                    | (ir::Opcode::IcmpImm, ir::InstructionData::IntCompare { cond, .. }) => {
-                        let a = arg(allocs, 0);
-                        let b = arg(allocs, 1);
-                        match cond {
-                            ir::condcodes::IntCC::Equal => ast::Instruction::Eq { a, b }.into(),
-                            ir::condcodes::IntCC::NotEqual => ast::Instruction::Ne { a, b }.into(),
-                            ir::condcodes::IntCC::UnsignedLessThan => {
-                                ast::Instruction::Ult { a, b }.into()
-                            }
-                            ir::condcodes::IntCC::SignedLessThan => {
-                                ast::Instruction::Slt { a, b }.into()
-                            }
-                            ir::condcodes::IntCC::UnsignedLessThanOrEqual => {
-                                ast::Instruction::Sle { a, b }.into()
-                            }
-                            ir::condcodes::IntCC::SignedLessThanOrEqual => {
-                                ast::Instruction::Sle { a, b }.into()
-                            }
-                            _ => ast::AssignmentRhs::Var,
-                        }
-                    }
-                    (ir::Opcode::Popcnt, _) => {
-                        let a = arg(allocs, 0);
-                        ast::Instruction::Ctpop { a }.into()
-                    }
-                    (ir::Opcode::Bitrev, _) => {
-                        let a = arg(allocs, 0);
-                        ast::Instruction::BitReverse { a }.into()
-                    }
-                    (ir::Opcode::Clz, _) => {
-                        let a = arg(allocs, 0);
-                        ast::Instruction::Ctlz { a }.into()
-                    }
-                    (ir::Opcode::Ctz, _) => {
-                        let a = arg(allocs, 0);
-                        ast::Instruction::Cttz { a }.into()
-                    }
-                    // TODO: ir::Opcode::IaddCarry
-                    // TODO: ir::Opcode::IaddCout
-                    (ir::Opcode::SaddSat, _) => {
-                        let a = arg(allocs, 0);
-                        let b = arg(allocs, 1);
-                        ast::Instruction::SaddSat { a, b }.into()
-                    }
-                    (ir::Opcode::SsubSat, _) => {
-                        let a = arg(allocs, 0);
-                        let b = arg(allocs, 1);
-                        ast::Instruction::SsubSat { a, b }.into()
-                    }
-                    (ir::Opcode::UsubSat, _) => {
-                        let a = arg(allocs, 0);
-                        let b = arg(allocs, 1);
-                        ast::Instruction::UsubSat { a, b }.into()
-                    }
-                    // Because Souper doesn't allow constants to be on the right
-                    // hand side of an assignment (i.e. `%0:i32 = 1234` is
-                    // disallowed) we have to ignore `iconst` and `bconst`
-                    // instructions until we process them as operands for some
-                    // other instruction. See the `arg` closure above for
-                    // details.
-                    (ir::Opcode::Iconst, _) | (ir::Opcode::Bconst, _) => return,
-                    _ => ast::AssignmentRhs::Var,
-                }
-            }
-            _ => ast::AssignmentRhs::Var,
-        };
-
-        non_var_count += match souper_assignment_rhs {
-            ast::AssignmentRhs::Var => 0,
-            _ => 1,
-        };
-        let souper_ty = souper_type_of(&func.dfg, val);
-        let souper_val = lhs.assignment(None, souper_ty, souper_assignment_rhs, vec![]);
-        let old_value = allocs.ir_to_souper_val.insert(val, souper_val);
-        assert!(old_value.is_none());
-    });
-
-    // We end up harvesting a lot of candidates like:
-    //
-    //     %0:i32 = var
-    //     infer %0
-    //
-    // and
-    //
-    //     %0:i32 = var
-    //     %1:i32 = var
-    //     %2:i32 = add %0, %1
-    //
-    // Both of these are useless. Only actually harvest the candidate if there
-    // are at least two actual operations.
-    if non_var_count >= 2 {
-        let lhs = lhs.finish(allocs.ir_to_souper_val[&val], None);
-        out.send(format!(
-            ";; Harvested from `{}` in `{}`\n{}\n",
-            val, func.name, lhs
-        ))
-        .unwrap();
-    }
-}
-
-fn souper_type_of(dfg: &ir::DataFlowGraph, val: ir::Value) -> Option<ast::Type> {
-    let ty = dfg.value_type(val);
-    assert!(ty.is_int() || ty.is_bool());
-    assert_eq!(ty.lane_count(), 1);
-    Some(ast::Type { width: ty.bits() })
-}
-
-#[derive(Debug)]
-enum StackEntry {
-    Visit(ir::Value),
-    Trace(ir::Value),
-}
-
-fn post_order_dfs(
-    allocs: &mut Allocs,
-    dfg: &ir::DataFlowGraph,
-    val: ir::Value,
-    should_trace: impl Fn(ir::Value) -> bool,
-    mut visit: impl FnMut(&mut Allocs, ir::Value),
-) {
-    allocs.dfs_stack.push(StackEntry::Trace(val));
-
-    while let Some(entry) = allocs.dfs_stack.pop() {
-        match entry {
-            StackEntry::Visit(val) => {
-                let is_new = allocs.dfs_seen.insert(val);
-                if is_new {
-                    visit(allocs, val);
-                }
-            }
-            StackEntry::Trace(val) => {
-                if allocs.dfs_seen.contains(&val) {
-                    continue;
-                }
-
-                allocs.dfs_stack.push(StackEntry::Visit(val));
-                if should_trace(val) {
-                    if let ir::ValueDef::Result(inst, 0) = dfg.value_def(val) {
-                        let args = dfg.inst_args(inst);
-                        for v in args.iter().rev().copied() {
-                            allocs.dfs_stack.push(StackEntry::Trace(v));
-                        }
-                    }
-                }
-            }
-        }
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/timing.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/timing.rs
deleted file mode 100644
index 1613abb9f..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/timing.rs
+++ /dev/null
@@ -1,260 +0,0 @@
-//! Pass timing.
-//!
-//! This modules provides facilities for timing the execution of individual compilation passes.
-
-use core::fmt;
-
-pub use self::details::{add_to_current, take_current, PassTimes, TimingToken};
-
-// Each pass that can be timed is predefined with the `define_passes!` macro. Each pass has a
-// snake_case name and a plain text description used when printing out the timing report.
-//
-// This macro defines:
-//
-// - A C-style enum containing all the pass names and a `None` variant.
-// - A usize constant with the number of defined passes.
-// - A const array of pass descriptions.
-// - A public function per pass used to start the timing of that pass.
-macro_rules! define_passes {
-    { $enum:ident, $num_passes:ident, $descriptions:ident;
-      $($pass:ident: $desc:expr,)+
-    } => {
-        #[allow(non_camel_case_types)]
-        #[derive(Clone, Copy, Debug, PartialEq, Eq)]
-        enum $enum { $($pass,)+ None}
-
-        const $num_passes: usize = $enum::None as usize;
-
-        const $descriptions: [&str; $num_passes] = [ $($desc),+ ];
-
-        $(
-            #[doc=$desc]
-            pub fn $pass() -> TimingToken {
-                details::start_pass($enum::$pass)
-            }
-        )+
-    }
-}
-
-// Pass definitions.
-define_passes! {
-    Pass, NUM_PASSES, DESCRIPTIONS;
-
-    process_file: "Processing test file",
-    parse_text: "Parsing textual Cranelift IR",
-    wasm_translate_module: "Translate WASM module",
-    wasm_translate_function: "Translate WASM function",
-
-    verifier: "Verify Cranelift IR",
-    verify_flags: "Verify CPU flags",
-
-    compile: "Compilation passes",
-    flowgraph: "Control flow graph",
-    domtree: "Dominator tree",
-    loop_analysis: "Loop analysis",
-    preopt: "Pre-legalization rewriting",
-    dce: "Dead code elimination",
-    gvn: "Global value numbering",
-    licm: "Loop invariant code motion",
-    unreachable_code: "Remove unreachable blocks",
-    remove_constant_phis: "Remove constant phi-nodes",
-
-    vcode_lower: "VCode lowering",
-    vcode_post_ra: "VCode post-register allocation finalization",
-    vcode_emit: "VCode emission",
-    vcode_emit_finish: "VCode emission finalization",
-
-    regalloc: "Register allocation",
-    binemit: "Binary machine code emission",
-    layout_renumber: "Layout full renumbering",
-
-    canonicalize_nans: "Canonicalization of NaNs",
-}
-
-impl Pass {
-    pub fn idx(self) -> usize {
-        self as usize
-    }
-}
-
-impl fmt::Display for Pass {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        match DESCRIPTIONS.get(self.idx()) {
-            Some(s) => f.write_str(s),
-            None => f.write_str("<no pass>"),
-        }
-    }
-}
-
-/// Implementation details.
-///
-/// This whole module can be gated on a `cfg` feature to provide a dummy implementation for
-/// performance-sensitive builds or restricted environments. The dummy implementation must provide
-/// `TimingToken` and `PassTimes` types and `take_current`, `add_to_current`, and `start_pass` funcs
-#[cfg(feature = "std")]
-mod details {
-    use super::{Pass, DESCRIPTIONS, NUM_PASSES};
-    use std::cell::{Cell, RefCell};
-    use std::fmt;
-    use std::mem;
-    use std::time::{Duration, Instant};
-
-    /// A timing token is responsible for timing the currently running pass. Timing starts when it
-    /// is created and ends when it is dropped.
-    ///
-    /// Multiple passes can be active at the same time, but they must be started and stopped in a
-    /// LIFO fashion.
-    pub struct TimingToken {
-        /// Start time for this pass.
-        start: Instant,
-
-        // Pass being timed by this token.
-        pass: Pass,
-
-        // The previously active pass which will be restored when this token is dropped.
-        prev: Pass,
-    }
-
-    /// Accumulated timing information for a single pass.
-    #[derive(Default, Copy, Clone)]
-    struct PassTime {
-        /// Total time spent running this pass including children.
-        total: Duration,
-
-        /// Time spent running in child passes.
-        child: Duration,
-    }
-
-    /// Accumulated timing for all passes.
-    pub struct PassTimes {
-        pass: [PassTime; NUM_PASSES],
-    }
-
-    impl PassTimes {
-        /// Returns the total amount of time taken by all the passes measured.
-        pub fn total(&self) -> Duration {
-            self.pass.iter().map(|p| p.total - p.child).sum()
-        }
-    }
-
-    impl Default for PassTimes {
-        fn default() -> Self {
-            Self {
-                pass: [Default::default(); NUM_PASSES],
-            }
-        }
-    }
-
-    impl fmt::Display for PassTimes {
-        fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-            writeln!(f, "======== ========  ==================================")?;
-            writeln!(f, "   Total     Self  Pass")?;
-            writeln!(f, "-------- --------  ----------------------------------")?;
-            for (time, desc) in self.pass.iter().zip(&DESCRIPTIONS[..]) {
-                // Omit passes that haven't run.
-                if time.total == Duration::default() {
-                    continue;
-                }
-
-                // Write a duration as secs.millis, trailing space.
-                fn fmtdur(mut dur: Duration, f: &mut fmt::Formatter) -> fmt::Result {
-                    // Round to nearest ms by adding 500us.
-                    dur += Duration::new(0, 500_000);
-                    let ms = dur.subsec_millis();
-                    write!(f, "{:4}.{:03} ", dur.as_secs(), ms)
-                }
-
-                fmtdur(time.total, f)?;
-                if let Some(s) = time.total.checked_sub(time.child) {
-                    fmtdur(s, f)?;
-                }
-                writeln!(f, " {}", desc)?;
-            }
-            writeln!(f, "======== ========  ==================================")
-        }
-    }
-
-    // Information about passes in a single thread.
-    thread_local! {
-        static CURRENT_PASS: Cell<Pass> = Cell::new(Pass::None);
-        static PASS_TIME: RefCell<PassTimes> = RefCell::new(Default::default());
-    }
-
-    /// Start timing `pass` as a child of the currently running pass, if any.
-    ///
-    /// This function is called by the publicly exposed pass functions.
-    pub(super) fn start_pass(pass: Pass) -> TimingToken {
-        let prev = CURRENT_PASS.with(|p| p.replace(pass));
-        log::debug!("timing: Starting {}, (during {})", pass, prev);
-        TimingToken {
-            start: Instant::now(),
-            pass,
-            prev,
-        }
-    }
-
-    /// Dropping a timing token indicated the end of the pass.
-    impl Drop for TimingToken {
-        fn drop(&mut self) {
-            let duration = self.start.elapsed();
-            log::debug!("timing: Ending {}", self.pass);
-            let old_cur = CURRENT_PASS.with(|p| p.replace(self.prev));
-            debug_assert_eq!(self.pass, old_cur, "Timing tokens dropped out of order");
-            PASS_TIME.with(|rc| {
-                let mut table = rc.borrow_mut();
-                table.pass[self.pass.idx()].total += duration;
-                if let Some(parent) = table.pass.get_mut(self.prev.idx()) {
-                    parent.child += duration;
-                }
-            })
-        }
-    }
-
-    /// Take the current accumulated pass timings and reset the timings for the current thread.
-    pub fn take_current() -> PassTimes {
-        PASS_TIME.with(|rc| mem::replace(&mut *rc.borrow_mut(), Default::default()))
-    }
-
-    /// Add `timings` to the accumulated timings for the current thread.
-    pub fn add_to_current(times: &PassTimes) {
-        PASS_TIME.with(|rc| {
-            for (a, b) in rc.borrow_mut().pass.iter_mut().zip(&times.pass[..]) {
-                a.total += b.total;
-                a.child += b.child;
-            }
-        })
-    }
-}
-
-/// Dummy `debug` implementation
-#[cfg(not(feature = "std"))]
-mod details {
-    use super::Pass;
-    /// Dummy `TimingToken`
-    pub struct TimingToken;
-    /// Dummy `PassTimes`
-    pub struct PassTimes;
-    /// Returns dummy `PassTimes`
-    pub fn take_current() -> PassTimes {
-        PassTimes
-    }
-    /// does nothing
-    pub fn add_to_current(_times: PassTimes) {}
-
-    /// does nothing
-    pub(super) fn start_pass(_pass: Pass) -> TimingToken {
-        TimingToken
-    }
-}
-
-#[cfg(test)]
-mod tests {
-    use super::*;
-    use alloc::string::ToString;
-
-    #[test]
-    fn display() {
-        assert_eq!(Pass::None.to_string(), "<no pass>");
-        assert_eq!(Pass::regalloc.to_string(), "Register allocation");
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/unreachable_code.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/unreachable_code.rs
deleted file mode 100644
index de1af1ac9..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/unreachable_code.rs
+++ /dev/null
@@ -1,58 +0,0 @@
-//! Unreachable code elimination.
-
-use crate::cursor::{Cursor, FuncCursor};
-use crate::dominator_tree::DominatorTree;
-use crate::flowgraph::ControlFlowGraph;
-use crate::ir;
-use crate::timing;
-
-/// Eliminate unreachable code.
-///
-/// This pass deletes whole blocks that can't be reached from the entry block. It does not delete
-/// individual instructions whose results are unused.
-///
-/// The reachability analysis is performed by the dominator tree analysis.
-pub fn eliminate_unreachable_code(
-    func: &mut ir::Function,
-    cfg: &mut ControlFlowGraph,
-    domtree: &DominatorTree,
-) {
-    let _tt = timing::unreachable_code();
-    let mut pos = FuncCursor::new(func);
-    while let Some(block) = pos.next_block() {
-        if domtree.is_reachable(block) {
-            continue;
-        }
-
-        log::trace!("Eliminating unreachable {}", block);
-        // Move the cursor out of the way and make sure the next lop iteration goes to the right
-        // block.
-        pos.prev_block();
-
-        // Remove all instructions from `block`.
-        while let Some(inst) = pos.func.layout.first_inst(block) {
-            log::trace!(" - {}", pos.func.dfg.display_inst(inst));
-            pos.func.layout.remove_inst(inst);
-        }
-
-        // Once the block is completely empty, we can update the CFG which removes it from any
-        // predecessor lists.
-        cfg.recompute_block(pos.func, block);
-
-        // Finally, remove the block from the layout.
-        pos.func.layout.remove_block(block);
-    }
-
-    // Remove all jumptable block-list contents that refer to unreachable
-    // blocks; the jumptable itself must have been unused (or used only in an
-    // unreachable block) if so. Note that we are not necessarily removing *all*
-    // unused jumptables, because that would require computing their
-    // reachability as well; we are just removing enough to clean up references
-    // to deleted blocks.
-    for jt_data in func.jump_tables.values_mut() {
-        let invalid_ref = jt_data.iter().any(|block| !domtree.is_reachable(*block));
-        if invalid_ref {
-            jt_data.clear();
-        }
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/value_label.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/value_label.rs
deleted file mode 100644
index 459fa62d7..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/value_label.rs
+++ /dev/null
@@ -1,69 +0,0 @@
-use crate::ir::{SourceLoc, ValueLabel};
-use crate::HashMap;
-use alloc::vec::Vec;
-use core::cmp::Ordering;
-use core::convert::From;
-use core::ops::Deref;
-use regalloc::Reg;
-
-#[cfg(feature = "enable-serde")]
-use serde::{Deserialize, Serialize};
-
-/// Value location range.
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub struct ValueLocRange {
-    /// The ValueLoc containing a ValueLabel during this range.
-    pub loc: LabelValueLoc,
-    /// The start of the range. It is an offset in the generated code.
-    pub start: u32,
-    /// The end of the range. It is an offset in the generated code.
-    pub end: u32,
-}
-
-/// The particular location for a value.
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
-pub enum LabelValueLoc {
-    /// New-backend Reg.
-    Reg(Reg),
-    /// New-backend offset from stack pointer.
-    SPOffset(i64),
-}
-
-/// Resulting map of Value labels and their ranges/locations.
-pub type ValueLabelsRanges = HashMap<ValueLabel, Vec<ValueLocRange>>;
-
-#[derive(Eq, Clone, Copy)]
-pub struct ComparableSourceLoc(SourceLoc);
-
-impl From<SourceLoc> for ComparableSourceLoc {
-    fn from(s: SourceLoc) -> Self {
-        Self(s)
-    }
-}
-
-impl Deref for ComparableSourceLoc {
-    type Target = SourceLoc;
-    fn deref(&self) -> &SourceLoc {
-        &self.0
-    }
-}
-
-impl PartialOrd for ComparableSourceLoc {
-    fn partial_cmp(&self, other: &Self) -> Option<Ordering> {
-        Some(self.cmp(other))
-    }
-}
-
-impl Ord for ComparableSourceLoc {
-    fn cmp(&self, other: &Self) -> Ordering {
-        self.0.bits().cmp(&other.0.bits())
-    }
-}
-
-impl PartialEq for ComparableSourceLoc {
-    fn eq(&self, other: &Self) -> bool {
-        self.0 == other.0
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/verifier/flags.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/verifier/flags.rs
deleted file mode 100644
index 5e67e3ae7..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/verifier/flags.rs
+++ /dev/null
@@ -1,161 +0,0 @@
-//! Verify CPU flags values.
-
-use crate::entity::{EntitySet, SecondaryMap};
-use crate::flowgraph::{BlockPredecessor, ControlFlowGraph};
-use crate::ir;
-use crate::ir::instructions::BranchInfo;
-use crate::packed_option::PackedOption;
-use crate::timing;
-use crate::verifier::{VerifierErrors, VerifierStepResult};
-
-/// Verify that CPU flags are used correctly.
-///
-/// The value types `iflags` and `fflags` represent CPU flags which usually live in a
-/// special-purpose register, so they can't be used as freely as other value types that can live in
-/// any register.
-///
-/// We verify the following conditions:
-///
-/// - At most one flags value can be live at a time.
-/// - A flags value can not be live across an instruction that clobbers the flags.
-///
-///
-pub fn verify_flags(
-    func: &ir::Function,
-    cfg: &ControlFlowGraph,
-    errors: &mut VerifierErrors,
-) -> VerifierStepResult<()> {
-    let _tt = timing::verify_flags();
-    let mut verifier = FlagsVerifier {
-        func,
-        cfg,
-        livein: SecondaryMap::new(),
-    };
-    verifier.check(errors)
-}
-
-struct FlagsVerifier<'a> {
-    func: &'a ir::Function,
-    cfg: &'a ControlFlowGraph,
-
-    /// The single live-in flags value (if any) for each block.
-    livein: SecondaryMap<ir::Block, PackedOption<ir::Value>>,
-}
-
-impl<'a> FlagsVerifier<'a> {
-    fn check(&mut self, errors: &mut VerifierErrors) -> VerifierStepResult<()> {
-        // List of blocks that need to be processed. blocks may be re-added to this list when we detect
-        // that one of their successor blocks needs a live-in flags value.
-        let mut worklist = EntitySet::with_capacity(self.func.layout.block_capacity());
-        for block in self.func.layout.blocks() {
-            worklist.insert(block);
-        }
-
-        while let Some(block) = worklist.pop() {
-            if let Some(value) = self.visit_block(block, errors)? {
-                // The block has live-in flags. Check if the value changed.
-                match self.livein[block].expand() {
-                    // Revisit any predecessor blocks the first time we see a live-in for `block`.
-                    None => {
-                        self.livein[block] = value.into();
-                        for BlockPredecessor { block: pred, .. } in self.cfg.pred_iter(block) {
-                            worklist.insert(pred);
-                        }
-                    }
-                    Some(old) if old != value => {
-                        return errors.fatal((
-                            block,
-                            format!("conflicting live-in CPU flags: {} and {}", old, value),
-                        ));
-                    }
-                    x => assert_eq!(x, Some(value)),
-                }
-            } else {
-                // Existing live-in flags should never be able to disappear.
-                assert_eq!(self.livein[block].expand(), None);
-            }
-        }
-
-        Ok(())
-    }
-
-    /// Check flags usage in `block` and return the live-in flags value, if any.
-    fn visit_block(
-        &self,
-        block: ir::Block,
-        errors: &mut VerifierErrors,
-    ) -> VerifierStepResult<Option<ir::Value>> {
-        // The single currently live flags value.
-        let mut live_val = None;
-
-        // Visit instructions backwards so we can track liveness accurately.
-        for inst in self.func.layout.block_insts(block).rev() {
-            // Check if `inst` interferes with existing live flags.
-            if let Some(live) = live_val {
-                for &res in self.func.dfg.inst_results(inst) {
-                    if res == live {
-                        // We've reached the def of `live_flags`, so it is no longer live above.
-                        live_val = None;
-                    } else if self.func.dfg.value_type(res).is_flags() {
-                        errors
-                            .report((inst, format!("{} clobbers live CPU flags in {}", res, live)));
-                        return Err(());
-                    }
-                }
-            }
-
-            // Now look for live ranges of CPU flags that end here.
-            for &arg in self.func.dfg.inst_args(inst) {
-                if self.func.dfg.value_type(arg).is_flags() {
-                    merge(&mut live_val, arg, inst, errors)?;
-                }
-            }
-
-            // Include live-in flags to successor blocks.
-            match self.func.dfg.analyze_branch(inst) {
-                BranchInfo::NotABranch => {}
-                BranchInfo::SingleDest(dest, _) => {
-                    if let Some(val) = self.livein[dest].expand() {
-                        merge(&mut live_val, val, inst, errors)?;
-                    }
-                }
-                BranchInfo::Table(jt, dest) => {
-                    if let Some(dest) = dest {
-                        if let Some(val) = self.livein[dest].expand() {
-                            merge(&mut live_val, val, inst, errors)?;
-                        }
-                    }
-                    for dest in self.func.jump_tables[jt].iter() {
-                        if let Some(val) = self.livein[*dest].expand() {
-                            merge(&mut live_val, val, inst, errors)?;
-                        }
-                    }
-                }
-            }
-        }
-
-        // Return the required live-in flags value.
-        Ok(live_val)
-    }
-}
-
-// Merge live flags values, or return an error on conflicting values.
-fn merge(
-    a: &mut Option<ir::Value>,
-    b: ir::Value,
-    inst: ir::Inst,
-    errors: &mut VerifierErrors,
-) -> VerifierStepResult<()> {
-    if let Some(va) = *a {
-        if b != va {
-            return errors.fatal((
-                inst,
-                format!("conflicting live CPU flags: {} and {}", va, b),
-            ));
-        }
-    } else {
-        *a = Some(b);
-    }
-
-    Ok(())
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/verifier/mod.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/verifier/mod.rs
deleted file mode 100644
index f63c45b92..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/verifier/mod.rs
+++ /dev/null
@@ -1,1885 +0,0 @@
-//! A verifier for ensuring that functions are well formed.
-//! It verifies:
-//!
-//! block integrity
-//!
-//! - All instructions reached from the `block_insts` iterator must belong to
-//!   the block as reported by `inst_block()`.
-//! - Every block must end in a terminator instruction, and no other instruction
-//!   can be a terminator.
-//! - Every value in the `block_params` iterator belongs to the block as reported by `value_block`.
-//!
-//! Instruction integrity
-//!
-//! - The instruction format must match the opcode.
-//! - All result values must be created for multi-valued instructions.
-//! - All referenced entities must exist. (Values, blocks, stack slots, ...)
-//! - Instructions must not reference (eg. branch to) the entry block.
-//!
-//! SSA form
-//!
-//! - Values must be defined by an instruction that exists and that is inserted in
-//!   a block, or be an argument of an existing block.
-//! - Values used by an instruction must dominate the instruction.
-//!
-//! Control flow graph and dominator tree integrity:
-//!
-//! - All predecessors in the CFG must be branches to the block.
-//! - All branches to a block must be present in the CFG.
-//! - A recomputed dominator tree is identical to the existing one.
-//!
-//! Type checking
-//!
-//! - Compare input and output values against the opcode's type constraints.
-//!   For polymorphic opcodes, determine the controlling type variable first.
-//! - Branches and jumps must pass arguments to destination blocks that match the
-//!   expected types exactly. The number of arguments must match.
-//! - All blocks in a jump table must take no arguments.
-//! - Function calls are type checked against their signature.
-//! - The entry block must take arguments that match the signature of the current
-//!   function.
-//! - All return instructions must have return value operands matching the current
-//!   function signature.
-//!
-//! Global values
-//!
-//! - Detect cycles in global values.
-//! - Detect use of 'vmctx' global value when no corresponding parameter is defined.
-//!
-//! TODO:
-//! Ad hoc checking
-//!
-//! - Stack slot loads and stores must be in-bounds.
-//! - Immediate constraints for certain opcodes, like `udiv_imm v3, 0`.
-//! - `Insertlane` and `extractlane` instructions have immediate lane numbers that must be in
-//!   range for their polymorphic type.
-//! - Swizzle and shuffle instructions take a variable number of lane arguments. The number
-//!   of arguments must match the destination type, and the lane indexes must be in range.
-
-use self::flags::verify_flags;
-use crate::dbg::DisplayList;
-use crate::dominator_tree::DominatorTree;
-use crate::entity::SparseSet;
-use crate::flowgraph::{BlockPredecessor, ControlFlowGraph};
-use crate::ir;
-use crate::ir::entities::AnyEntity;
-use crate::ir::instructions::{BranchInfo, CallInfo, InstructionFormat, ResolvedConstraint};
-use crate::ir::{
-    types, ArgumentPurpose, Block, Constant, FuncRef, Function, GlobalValue, Inst, JumpTable,
-    Opcode, SigRef, StackSlot, Type, Value, ValueDef, ValueList,
-};
-use crate::isa::TargetIsa;
-use crate::iterators::IteratorExtras;
-use crate::print_errors::pretty_verifier_error;
-use crate::settings::FlagsOrIsa;
-use crate::timing;
-use alloc::collections::BTreeSet;
-use alloc::string::{String, ToString};
-use alloc::vec::Vec;
-use core::cmp::Ordering;
-use core::fmt::{self, Display, Formatter};
-
-mod flags;
-
-/// A verifier error.
-#[derive(Debug, PartialEq, Eq, Clone)]
-pub struct VerifierError {
-    /// The entity causing the verifier error.
-    pub location: AnyEntity,
-    /// Optionally provide some context for the given location; e.g., for `inst42` provide
-    /// `Some("v3 = iconst.i32 0")` for more comprehensible errors.
-    pub context: Option<String>,
-    /// The error message.
-    pub message: String,
-}
-
-// This is manually implementing Error and Display instead of using thiserror to reduce the amount
-// of dependencies used by Cranelift.
-impl std::error::Error for VerifierError {}
-
-impl Display for VerifierError {
-    fn fmt(&self, f: &mut Formatter) -> fmt::Result {
-        match &self.context {
-            None => write!(f, "{}: {}", self.location, self.message),
-            Some(context) => write!(f, "{} ({}): {}", self.location, context, self.message),
-        }
-    }
-}
-
-/// Convenience converter for making error-reporting less verbose.
-///
-/// Converts a tuple of `(location, context, message)` to a `VerifierError`.
-/// ```
-/// use cranelift_codegen::verifier::VerifierErrors;
-/// use cranelift_codegen::ir::Inst;
-/// let mut errors = VerifierErrors::new();
-/// errors.report((Inst::from_u32(42), "v3 = iadd v1, v2", "iadd cannot be used with values of this type"));
-/// // note the double parenthenses to use this syntax
-/// ```
-impl<L, C, M> From<(L, C, M)> for VerifierError
-where
-    L: Into<AnyEntity>,
-    C: Into<String>,
-    M: Into<String>,
-{
-    fn from(items: (L, C, M)) -> Self {
-        let (location, context, message) = items;
-        Self {
-            location: location.into(),
-            context: Some(context.into()),
-            message: message.into(),
-        }
-    }
-}
-
-/// Convenience converter for making error-reporting less verbose.
-///
-/// Same as above but without `context`.
-impl<L, M> From<(L, M)> for VerifierError
-where
-    L: Into<AnyEntity>,
-    M: Into<String>,
-{
-    fn from(items: (L, M)) -> Self {
-        let (location, message) = items;
-        Self {
-            location: location.into(),
-            context: None,
-            message: message.into(),
-        }
-    }
-}
-
-/// Result of a step in the verification process.
-///
-/// Functions that return `VerifierStepResult<()>` should also take a
-/// mutable reference to `VerifierErrors` as argument in order to report
-/// errors.
-///
-/// Here, `Ok` represents a step that **did not lead to a fatal error**,
-/// meaning that the verification process may continue. However, other (non-fatal)
-/// errors might have been reported through the previously mentioned `VerifierErrors`
-/// argument.
-pub type VerifierStepResult<T> = Result<T, ()>;
-
-/// Result of a verification operation.
-///
-/// Unlike `VerifierStepResult<()>` which may be `Ok` while still having reported
-/// errors, this type always returns `Err` if an error (fatal or not) was reported.
-pub type VerifierResult<T> = Result<T, VerifierErrors>;
-
-/// List of verifier errors.
-#[derive(Debug, Default, PartialEq, Eq, Clone)]
-pub struct VerifierErrors(pub Vec<VerifierError>);
-
-// This is manually implementing Error and Display instead of using thiserror to reduce the amount
-// of dependencies used by Cranelift.
-impl std::error::Error for VerifierErrors {}
-
-impl VerifierErrors {
-    /// Return a new `VerifierErrors` struct.
-    #[inline]
-    pub fn new() -> Self {
-        Self(Vec::new())
-    }
-
-    /// Return whether no errors were reported.
-    #[inline]
-    pub fn is_empty(&self) -> bool {
-        self.0.is_empty()
-    }
-
-    /// Return whether one or more errors were reported.
-    #[inline]
-    pub fn has_error(&self) -> bool {
-        !self.0.is_empty()
-    }
-
-    /// Return a `VerifierStepResult` that is fatal if at least one error was reported,
-    /// and non-fatal otherwise.
-    #[inline]
-    pub fn as_result(&self) -> VerifierStepResult<()> {
-        if self.is_empty() {
-            Ok(())
-        } else {
-            Err(())
-        }
-    }
-
-    /// Report an error, adding it to the list of errors.
-    pub fn report(&mut self, error: impl Into<VerifierError>) {
-        self.0.push(error.into());
-    }
-
-    /// Report a fatal error and return `Err`.
-    pub fn fatal(&mut self, error: impl Into<VerifierError>) -> VerifierStepResult<()> {
-        self.report(error);
-        Err(())
-    }
-
-    /// Report a non-fatal error and return `Ok`.
-    pub fn nonfatal(&mut self, error: impl Into<VerifierError>) -> VerifierStepResult<()> {
-        self.report(error);
-        Ok(())
-    }
-}
-
-impl From<Vec<VerifierError>> for VerifierErrors {
-    fn from(v: Vec<VerifierError>) -> Self {
-        Self(v)
-    }
-}
-
-impl Into<Vec<VerifierError>> for VerifierErrors {
-    fn into(self) -> Vec<VerifierError> {
-        self.0
-    }
-}
-
-impl Into<VerifierResult<()>> for VerifierErrors {
-    fn into(self) -> VerifierResult<()> {
-        if self.is_empty() {
-            Ok(())
-        } else {
-            Err(self)
-        }
-    }
-}
-
-impl Display for VerifierErrors {
-    fn fmt(&self, f: &mut Formatter) -> fmt::Result {
-        for err in &self.0 {
-            writeln!(f, "- {}", err)?;
-        }
-        Ok(())
-    }
-}
-
-/// Verify `func`.
-pub fn verify_function<'a, FOI: Into<FlagsOrIsa<'a>>>(
-    func: &Function,
-    fisa: FOI,
-) -> VerifierResult<()> {
-    let _tt = timing::verifier();
-    let mut errors = VerifierErrors::default();
-    let verifier = Verifier::new(func, fisa.into());
-    let result = verifier.run(&mut errors);
-    if errors.is_empty() {
-        result.unwrap();
-        Ok(())
-    } else {
-        Err(errors)
-    }
-}
-
-/// Verify `func` after checking the integrity of associated context data structures `cfg` and
-/// `domtree`.
-pub fn verify_context<'a, FOI: Into<FlagsOrIsa<'a>>>(
-    func: &Function,
-    cfg: &ControlFlowGraph,
-    domtree: &DominatorTree,
-    fisa: FOI,
-    errors: &mut VerifierErrors,
-) -> VerifierStepResult<()> {
-    let _tt = timing::verifier();
-    let verifier = Verifier::new(func, fisa.into());
-    if cfg.is_valid() {
-        verifier.cfg_integrity(cfg, errors)?;
-    }
-    if domtree.is_valid() {
-        verifier.domtree_integrity(domtree, errors)?;
-    }
-    verifier.run(errors)
-}
-
-struct Verifier<'a> {
-    func: &'a Function,
-    expected_cfg: ControlFlowGraph,
-    expected_domtree: DominatorTree,
-    isa: Option<&'a dyn TargetIsa>,
-}
-
-impl<'a> Verifier<'a> {
-    pub fn new(func: &'a Function, fisa: FlagsOrIsa<'a>) -> Self {
-        let expected_cfg = ControlFlowGraph::with_function(func);
-        let expected_domtree = DominatorTree::with_function(func, &expected_cfg);
-        Self {
-            func,
-            expected_cfg,
-            expected_domtree,
-            isa: fisa.isa,
-        }
-    }
-
-    /// Determine a contextual error string for an instruction.
-    #[inline]
-    fn context(&self, inst: Inst) -> String {
-        self.func.dfg.display_inst(inst).to_string()
-    }
-
-    // Check for:
-    //  - cycles in the global value declarations.
-    //  - use of 'vmctx' when no special parameter declares it.
-    fn verify_global_values(&self, errors: &mut VerifierErrors) -> VerifierStepResult<()> {
-        let mut cycle_seen = false;
-        let mut seen = SparseSet::new();
-
-        'gvs: for gv in self.func.global_values.keys() {
-            seen.clear();
-            seen.insert(gv);
-
-            let mut cur = gv;
-            loop {
-                match self.func.global_values[cur] {
-                    ir::GlobalValueData::Load { base, .. }
-                    | ir::GlobalValueData::IAddImm { base, .. } => {
-                        if seen.insert(base).is_some() {
-                            if !cycle_seen {
-                                errors.report((
-                                    gv,
-                                    format!("global value cycle: {}", DisplayList(seen.as_slice())),
-                                ));
-                                // ensures we don't report the cycle multiple times
-                                cycle_seen = true;
-                            }
-                            continue 'gvs;
-                        }
-
-                        cur = base;
-                    }
-                    _ => break,
-                }
-            }
-
-            match self.func.global_values[gv] {
-                ir::GlobalValueData::VMContext { .. } => {
-                    if self
-                        .func
-                        .special_param(ir::ArgumentPurpose::VMContext)
-                        .is_none()
-                    {
-                        errors.report((gv, format!("undeclared vmctx reference {}", gv)));
-                    }
-                }
-                ir::GlobalValueData::IAddImm {
-                    base, global_type, ..
-                } => {
-                    if !global_type.is_int() {
-                        errors.report((
-                            gv,
-                            format!("iadd_imm global value with non-int type {}", global_type),
-                        ));
-                    } else if let Some(isa) = self.isa {
-                        let base_type = self.func.global_values[base].global_type(isa);
-                        if global_type != base_type {
-                            errors.report((
-                                gv,
-                                format!(
-                                    "iadd_imm type {} differs from operand type {}",
-                                    global_type, base_type
-                                ),
-                            ));
-                        }
-                    }
-                }
-                ir::GlobalValueData::Load { base, .. } => {
-                    if let Some(isa) = self.isa {
-                        let base_type = self.func.global_values[base].global_type(isa);
-                        let pointer_type = isa.pointer_type();
-                        if base_type != pointer_type {
-                            errors.report((
-                                gv,
-                                format!(
-                                    "base {} has type {}, which is not the pointer type {}",
-                                    base, base_type, pointer_type
-                                ),
-                            ));
-                        }
-                    }
-                }
-                _ => {}
-            }
-        }
-
-        // Invalid global values shouldn't stop us from verifying the rest of the function
-        Ok(())
-    }
-
-    fn verify_heaps(&self, errors: &mut VerifierErrors) -> VerifierStepResult<()> {
-        if let Some(isa) = self.isa {
-            for (heap, heap_data) in &self.func.heaps {
-                let base = heap_data.base;
-                if !self.func.global_values.is_valid(base) {
-                    return errors.nonfatal((heap, format!("invalid base global value {}", base)));
-                }
-
-                let pointer_type = isa.pointer_type();
-                let base_type = self.func.global_values[base].global_type(isa);
-                if base_type != pointer_type {
-                    errors.report((
-                        heap,
-                        format!(
-                            "heap base has type {}, which is not the pointer type {}",
-                            base_type, pointer_type
-                        ),
-                    ));
-                }
-
-                if let ir::HeapStyle::Dynamic { bound_gv, .. } = heap_data.style {
-                    if !self.func.global_values.is_valid(bound_gv) {
-                        return errors
-                            .nonfatal((heap, format!("invalid bound global value {}", bound_gv)));
-                    }
-
-                    let bound_type = self.func.global_values[bound_gv].global_type(isa);
-                    if pointer_type != bound_type {
-                        errors.report((
-                            heap,
-                            format!(
-                                "heap pointer type {} differs from the type of its bound, {}",
-                                pointer_type, bound_type
-                            ),
-                        ));
-                    }
-                }
-            }
-        }
-
-        Ok(())
-    }
-
-    fn verify_tables(&self, errors: &mut VerifierErrors) -> VerifierStepResult<()> {
-        if let Some(isa) = self.isa {
-            for (table, table_data) in &self.func.tables {
-                let base = table_data.base_gv;
-                if !self.func.global_values.is_valid(base) {
-                    return errors.nonfatal((table, format!("invalid base global value {}", base)));
-                }
-
-                let pointer_type = isa.pointer_type();
-                let base_type = self.func.global_values[base].global_type(isa);
-                if base_type != pointer_type {
-                    errors.report((
-                        table,
-                        format!(
-                            "table base has type {}, which is not the pointer type {}",
-                            base_type, pointer_type
-                        ),
-                    ));
-                }
-
-                let bound_gv = table_data.bound_gv;
-                if !self.func.global_values.is_valid(bound_gv) {
-                    return errors
-                        .nonfatal((table, format!("invalid bound global value {}", bound_gv)));
-                }
-
-                let index_type = table_data.index_type;
-                let bound_type = self.func.global_values[bound_gv].global_type(isa);
-                if index_type != bound_type {
-                    errors.report((
-                        table,
-                        format!(
-                            "table index type {} differs from the type of its bound, {}",
-                            index_type, bound_type
-                        ),
-                    ));
-                }
-            }
-        }
-
-        Ok(())
-    }
-
-    fn verify_jump_tables(&self, errors: &mut VerifierErrors) -> VerifierStepResult<()> {
-        for (jt, jt_data) in &self.func.jump_tables {
-            for &block in jt_data.iter() {
-                self.verify_block(jt, block, errors)?;
-            }
-        }
-        Ok(())
-    }
-
-    /// Check that the given block can be encoded as a BB, by checking that only
-    /// branching instructions are ending the block.
-    fn encodable_as_bb(&self, block: Block, errors: &mut VerifierErrors) -> VerifierStepResult<()> {
-        match self.func.is_block_basic(block) {
-            Ok(()) => Ok(()),
-            Err((inst, message)) => errors.fatal((inst, self.context(inst), message)),
-        }
-    }
-
-    fn block_integrity(
-        &self,
-        block: Block,
-        inst: Inst,
-        errors: &mut VerifierErrors,
-    ) -> VerifierStepResult<()> {
-        let is_terminator = self.func.dfg[inst].opcode().is_terminator();
-        let is_last_inst = self.func.layout.last_inst(block) == Some(inst);
-
-        if is_terminator && !is_last_inst {
-            // Terminating instructions only occur at the end of blocks.
-            return errors.fatal((
-                inst,
-                self.context(inst),
-                format!(
-                    "a terminator instruction was encountered before the end of {}",
-                    block
-                ),
-            ));
-        }
-        if is_last_inst && !is_terminator {
-            return errors.fatal((block, "block does not end in a terminator instruction"));
-        }
-
-        // Instructions belong to the correct block.
-        let inst_block = self.func.layout.inst_block(inst);
-        if inst_block != Some(block) {
-            return errors.fatal((
-                inst,
-                self.context(inst),
-                format!("should belong to {} not {:?}", block, inst_block),
-            ));
-        }
-
-        // Parameters belong to the correct block.
-        for &arg in self.func.dfg.block_params(block) {
-            match self.func.dfg.value_def(arg) {
-                ValueDef::Param(arg_block, _) => {
-                    if block != arg_block {
-                        return errors.fatal((arg, format!("does not belong to {}", block)));
-                    }
-                }
-                _ => {
-                    return errors.fatal((arg, "expected an argument, found a result"));
-                }
-            }
-        }
-
-        Ok(())
-    }
-
-    fn instruction_integrity(
-        &self,
-        inst: Inst,
-        errors: &mut VerifierErrors,
-    ) -> VerifierStepResult<()> {
-        let inst_data = &self.func.dfg[inst];
-        let dfg = &self.func.dfg;
-
-        // The instruction format matches the opcode
-        if inst_data.opcode().format() != InstructionFormat::from(inst_data) {
-            return errors.fatal((
-                inst,
-                self.context(inst),
-                "instruction opcode doesn't match instruction format",
-            ));
-        }
-
-        let num_fixed_results = inst_data.opcode().constraints().num_fixed_results();
-        // var_results is 0 if we aren't a call instruction
-        let var_results = dfg
-            .call_signature(inst)
-            .map_or(0, |sig| dfg.signatures[sig].returns.len());
-        let total_results = num_fixed_results + var_results;
-
-        // All result values for multi-valued instructions are created
-        let got_results = dfg.inst_results(inst).len();
-        if got_results != total_results {
-            return errors.fatal((
-                inst,
-                self.context(inst),
-                format!(
-                    "expected {} result values, found {}",
-                    total_results, got_results,
-                ),
-            ));
-        }
-
-        self.verify_entity_references(inst, errors)
-    }
-
-    fn verify_entity_references(
-        &self,
-        inst: Inst,
-        errors: &mut VerifierErrors,
-    ) -> VerifierStepResult<()> {
-        use crate::ir::instructions::InstructionData::*;
-
-        for &arg in self.func.dfg.inst_args(inst) {
-            self.verify_inst_arg(inst, arg, errors)?;
-
-            // All used values must be attached to something.
-            let original = self.func.dfg.resolve_aliases(arg);
-            if !self.func.dfg.value_is_attached(original) {
-                errors.report((
-                    inst,
-                    self.context(inst),
-                    format!("argument {} -> {} is not attached", arg, original),
-                ));
-            }
-        }
-
-        for &res in self.func.dfg.inst_results(inst) {
-            self.verify_inst_result(inst, res, errors)?;
-        }
-
-        match self.func.dfg[inst] {
-            MultiAry { ref args, .. } => {
-                self.verify_value_list(inst, args, errors)?;
-            }
-            Jump {
-                destination,
-                ref args,
-                ..
-            }
-            | Branch {
-                destination,
-                ref args,
-                ..
-            }
-            | BranchInt {
-                destination,
-                ref args,
-                ..
-            }
-            | BranchFloat {
-                destination,
-                ref args,
-                ..
-            }
-            | BranchIcmp {
-                destination,
-                ref args,
-                ..
-            } => {
-                self.verify_block(inst, destination, errors)?;
-                self.verify_value_list(inst, args, errors)?;
-            }
-            BranchTable {
-                table, destination, ..
-            } => {
-                self.verify_block(inst, destination, errors)?;
-                self.verify_jump_table(inst, table, errors)?;
-            }
-            Call {
-                func_ref, ref args, ..
-            } => {
-                self.verify_func_ref(inst, func_ref, errors)?;
-                self.verify_value_list(inst, args, errors)?;
-            }
-            CallIndirect {
-                sig_ref, ref args, ..
-            } => {
-                self.verify_sig_ref(inst, sig_ref, errors)?;
-                self.verify_value_list(inst, args, errors)?;
-            }
-            FuncAddr { func_ref, .. } => {
-                self.verify_func_ref(inst, func_ref, errors)?;
-            }
-            StackLoad { stack_slot, .. } | StackStore { stack_slot, .. } => {
-                self.verify_stack_slot(inst, stack_slot, errors)?;
-            }
-            UnaryGlobalValue { global_value, .. } => {
-                self.verify_global_value(inst, global_value, errors)?;
-            }
-            HeapAddr { heap, .. } => {
-                self.verify_heap(inst, heap, errors)?;
-            }
-            TableAddr { table, .. } => {
-                self.verify_table(inst, table, errors)?;
-            }
-            LoadComplex { ref args, .. } => {
-                self.verify_value_list(inst, args, errors)?;
-            }
-            StoreComplex { ref args, .. } => {
-                self.verify_value_list(inst, args, errors)?;
-            }
-
-            NullAry {
-                opcode: Opcode::GetPinnedReg,
-            }
-            | Unary {
-                opcode: Opcode::SetPinnedReg,
-                ..
-            } => {
-                if let Some(isa) = &self.isa {
-                    if !isa.flags().enable_pinned_reg() {
-                        return errors.fatal((
-                            inst,
-                            self.context(inst),
-                            "GetPinnedReg/SetPinnedReg cannot be used without enable_pinned_reg",
-                        ));
-                    }
-                } else {
-                    return errors.fatal((
-                        inst,
-                        self.context(inst),
-                        "GetPinnedReg/SetPinnedReg need an ISA!",
-                    ));
-                }
-            }
-            Unary {
-                opcode: Opcode::Bitcast,
-                arg,
-            } => {
-                self.verify_bitcast(inst, arg, errors)?;
-            }
-            UnaryConst {
-                opcode: Opcode::Vconst,
-                constant_handle,
-                ..
-            } => {
-                self.verify_constant_size(inst, constant_handle, errors)?;
-            }
-
-            // Exhaustive list so we can't forget to add new formats
-            AtomicCas { .. }
-            | AtomicRmw { .. }
-            | LoadNoOffset { .. }
-            | StoreNoOffset { .. }
-            | Unary { .. }
-            | UnaryConst { .. }
-            | UnaryImm { .. }
-            | UnaryIeee32 { .. }
-            | UnaryIeee64 { .. }
-            | UnaryBool { .. }
-            | Binary { .. }
-            | BinaryImm8 { .. }
-            | BinaryImm64 { .. }
-            | Ternary { .. }
-            | TernaryImm8 { .. }
-            | Shuffle { .. }
-            | IntCompare { .. }
-            | IntCompareImm { .. }
-            | IntCond { .. }
-            | FloatCompare { .. }
-            | FloatCond { .. }
-            | IntSelect { .. }
-            | Load { .. }
-            | Store { .. }
-            | Trap { .. }
-            | CondTrap { .. }
-            | IntCondTrap { .. }
-            | FloatCondTrap { .. }
-            | NullAry { .. } => {}
-        }
-
-        Ok(())
-    }
-
-    fn verify_block(
-        &self,
-        loc: impl Into<AnyEntity>,
-        e: Block,
-        errors: &mut VerifierErrors,
-    ) -> VerifierStepResult<()> {
-        if !self.func.dfg.block_is_valid(e) || !self.func.layout.is_block_inserted(e) {
-            return errors.fatal((loc, format!("invalid block reference {}", e)));
-        }
-        if let Some(entry_block) = self.func.layout.entry_block() {
-            if e == entry_block {
-                return errors.fatal((loc, format!("invalid reference to entry block {}", e)));
-            }
-        }
-        Ok(())
-    }
-
-    fn verify_sig_ref(
-        &self,
-        inst: Inst,
-        s: SigRef,
-        errors: &mut VerifierErrors,
-    ) -> VerifierStepResult<()> {
-        if !self.func.dfg.signatures.is_valid(s) {
-            errors.fatal((
-                inst,
-                self.context(inst),
-                format!("invalid signature reference {}", s),
-            ))
-        } else {
-            Ok(())
-        }
-    }
-
-    fn verify_func_ref(
-        &self,
-        inst: Inst,
-        f: FuncRef,
-        errors: &mut VerifierErrors,
-    ) -> VerifierStepResult<()> {
-        if !self.func.dfg.ext_funcs.is_valid(f) {
-            errors.nonfatal((
-                inst,
-                self.context(inst),
-                format!("invalid function reference {}", f),
-            ))
-        } else {
-            Ok(())
-        }
-    }
-
-    fn verify_stack_slot(
-        &self,
-        inst: Inst,
-        ss: StackSlot,
-        errors: &mut VerifierErrors,
-    ) -> VerifierStepResult<()> {
-        if !self.func.stack_slots.is_valid(ss) {
-            errors.nonfatal((
-                inst,
-                self.context(inst),
-                format!("invalid stack slot {}", ss),
-            ))
-        } else {
-            Ok(())
-        }
-    }
-
-    fn verify_global_value(
-        &self,
-        inst: Inst,
-        gv: GlobalValue,
-        errors: &mut VerifierErrors,
-    ) -> VerifierStepResult<()> {
-        if !self.func.global_values.is_valid(gv) {
-            errors.nonfatal((
-                inst,
-                self.context(inst),
-                format!("invalid global value {}", gv),
-            ))
-        } else {
-            Ok(())
-        }
-    }
-
-    fn verify_heap(
-        &self,
-        inst: Inst,
-        heap: ir::Heap,
-        errors: &mut VerifierErrors,
-    ) -> VerifierStepResult<()> {
-        if !self.func.heaps.is_valid(heap) {
-            errors.nonfatal((inst, self.context(inst), format!("invalid heap {}", heap)))
-        } else {
-            Ok(())
-        }
-    }
-
-    fn verify_table(
-        &self,
-        inst: Inst,
-        table: ir::Table,
-        errors: &mut VerifierErrors,
-    ) -> VerifierStepResult<()> {
-        if !self.func.tables.is_valid(table) {
-            errors.nonfatal((inst, self.context(inst), format!("invalid table {}", table)))
-        } else {
-            Ok(())
-        }
-    }
-
-    fn verify_value_list(
-        &self,
-        inst: Inst,
-        l: &ValueList,
-        errors: &mut VerifierErrors,
-    ) -> VerifierStepResult<()> {
-        if !l.is_valid(&self.func.dfg.value_lists) {
-            errors.nonfatal((
-                inst,
-                self.context(inst),
-                format!("invalid value list reference {:?}", l),
-            ))
-        } else {
-            Ok(())
-        }
-    }
-
-    fn verify_jump_table(
-        &self,
-        inst: Inst,
-        j: JumpTable,
-        errors: &mut VerifierErrors,
-    ) -> VerifierStepResult<()> {
-        if !self.func.jump_tables.is_valid(j) {
-            errors.nonfatal((
-                inst,
-                self.context(inst),
-                format!("invalid jump table reference {}", j),
-            ))
-        } else {
-            Ok(())
-        }
-    }
-
-    fn verify_value(
-        &self,
-        loc_inst: Inst,
-        v: Value,
-        errors: &mut VerifierErrors,
-    ) -> VerifierStepResult<()> {
-        let dfg = &self.func.dfg;
-        if !dfg.value_is_valid(v) {
-            errors.nonfatal((
-                loc_inst,
-                self.context(loc_inst),
-                format!("invalid value reference {}", v),
-            ))
-        } else {
-            Ok(())
-        }
-    }
-
-    fn verify_inst_arg(
-        &self,
-        loc_inst: Inst,
-        v: Value,
-        errors: &mut VerifierErrors,
-    ) -> VerifierStepResult<()> {
-        self.verify_value(loc_inst, v, errors)?;
-
-        let dfg = &self.func.dfg;
-        let loc_block = self.func.layout.pp_block(loc_inst);
-        let is_reachable = self.expected_domtree.is_reachable(loc_block);
-
-        // SSA form
-        match dfg.value_def(v) {
-            ValueDef::Result(def_inst, _) => {
-                // Value is defined by an instruction that exists.
-                if !dfg.inst_is_valid(def_inst) {
-                    return errors.fatal((
-                        loc_inst,
-                        self.context(loc_inst),
-                        format!("{} is defined by invalid instruction {}", v, def_inst),
-                    ));
-                }
-                // Defining instruction is inserted in a block.
-                if self.func.layout.inst_block(def_inst) == None {
-                    return errors.fatal((
-                        loc_inst,
-                        self.context(loc_inst),
-                        format!("{} is defined by {} which has no block", v, def_inst),
-                    ));
-                }
-                // Defining instruction dominates the instruction that uses the value.
-                if is_reachable {
-                    if !self
-                        .expected_domtree
-                        .dominates(def_inst, loc_inst, &self.func.layout)
-                    {
-                        return errors.fatal((
-                            loc_inst,
-                            self.context(loc_inst),
-                            format!("uses value {} from non-dominating {}", v, def_inst),
-                        ));
-                    }
-                    if def_inst == loc_inst {
-                        return errors.fatal((
-                            loc_inst,
-                            self.context(loc_inst),
-                            format!("uses value {} from itself", v),
-                        ));
-                    }
-                }
-            }
-            ValueDef::Param(block, _) => {
-                // Value is defined by an existing block.
-                if !dfg.block_is_valid(block) {
-                    return errors.fatal((
-                        loc_inst,
-                        self.context(loc_inst),
-                        format!("{} is defined by invalid block {}", v, block),
-                    ));
-                }
-                // Defining block is inserted in the layout
-                if !self.func.layout.is_block_inserted(block) {
-                    return errors.fatal((
-                        loc_inst,
-                        self.context(loc_inst),
-                        format!("{} is defined by {} which is not in the layout", v, block),
-                    ));
-                }
-                // The defining block dominates the instruction using this value.
-                if is_reachable
-                    && !self
-                        .expected_domtree
-                        .dominates(block, loc_inst, &self.func.layout)
-                {
-                    return errors.fatal((
-                        loc_inst,
-                        self.context(loc_inst),
-                        format!("uses value arg from non-dominating {}", block),
-                    ));
-                }
-            }
-        }
-        Ok(())
-    }
-
-    fn verify_inst_result(
-        &self,
-        loc_inst: Inst,
-        v: Value,
-        errors: &mut VerifierErrors,
-    ) -> VerifierStepResult<()> {
-        self.verify_value(loc_inst, v, errors)?;
-
-        match self.func.dfg.value_def(v) {
-            ValueDef::Result(def_inst, _) => {
-                if def_inst != loc_inst {
-                    errors.fatal((
-                        loc_inst,
-                        self.context(loc_inst),
-                        format!("instruction result {} is not defined by the instruction", v),
-                    ))
-                } else {
-                    Ok(())
-                }
-            }
-            ValueDef::Param(_, _) => errors.fatal((
-                loc_inst,
-                self.context(loc_inst),
-                format!("instruction result {} is not defined by the instruction", v),
-            )),
-        }
-    }
-
-    fn verify_bitcast(
-        &self,
-        inst: Inst,
-        arg: Value,
-        errors: &mut VerifierErrors,
-    ) -> VerifierStepResult<()> {
-        let typ = self.func.dfg.ctrl_typevar(inst);
-        let value_type = self.func.dfg.value_type(arg);
-
-        if typ.lane_bits() < value_type.lane_bits() {
-            errors.fatal((
-                inst,
-                format!(
-                    "The bitcast argument {} doesn't fit in a type of {} bits",
-                    arg,
-                    typ.lane_bits()
-                ),
-            ))
-        } else {
-            Ok(())
-        }
-    }
-
-    fn verify_constant_size(
-        &self,
-        inst: Inst,
-        constant: Constant,
-        errors: &mut VerifierErrors,
-    ) -> VerifierStepResult<()> {
-        let type_size = self.func.dfg.ctrl_typevar(inst).bytes() as usize;
-        let constant_size = self.func.dfg.constants.get(constant).len();
-        if type_size != constant_size {
-            errors.fatal((
-                inst,
-                format!(
-                    "The instruction expects {} to have a size of {} bytes but it has {}",
-                    constant, type_size, constant_size
-                ),
-            ))
-        } else {
-            Ok(())
-        }
-    }
-
-    fn domtree_integrity(
-        &self,
-        domtree: &DominatorTree,
-        errors: &mut VerifierErrors,
-    ) -> VerifierStepResult<()> {
-        // We consider two `DominatorTree`s to be equal if they return the same immediate
-        // dominator for each block. Therefore the current domtree is valid if it matches the freshly
-        // computed one.
-        for block in self.func.layout.blocks() {
-            let expected = self.expected_domtree.idom(block);
-            let got = domtree.idom(block);
-            if got != expected {
-                return errors.fatal((
-                    block,
-                    format!(
-                        "invalid domtree, expected idom({}) = {:?}, got {:?}",
-                        block, expected, got
-                    ),
-                ));
-            }
-        }
-        // We also verify if the postorder defined by `DominatorTree` is sane
-        if domtree.cfg_postorder().len() != self.expected_domtree.cfg_postorder().len() {
-            return errors.fatal((
-                AnyEntity::Function,
-                "incorrect number of Blocks in postorder traversal",
-            ));
-        }
-        for (index, (&test_block, &true_block)) in domtree
-            .cfg_postorder()
-            .iter()
-            .zip(self.expected_domtree.cfg_postorder().iter())
-            .enumerate()
-        {
-            if test_block != true_block {
-                return errors.fatal((
-                    test_block,
-                    format!(
-                        "invalid domtree, postorder block number {} should be {}, got {}",
-                        index, true_block, test_block
-                    ),
-                ));
-            }
-        }
-        // We verify rpo_cmp on pairs of adjacent blocks in the postorder
-        for (&prev_block, &next_block) in domtree.cfg_postorder().iter().adjacent_pairs() {
-            if self
-                .expected_domtree
-                .rpo_cmp(prev_block, next_block, &self.func.layout)
-                != Ordering::Greater
-            {
-                return errors.fatal((
-                    next_block,
-                    format!(
-                        "invalid domtree, rpo_cmp does not says {} is greater than {}",
-                        prev_block, next_block
-                    ),
-                ));
-            }
-        }
-        Ok(())
-    }
-
-    fn typecheck_entry_block_params(&self, errors: &mut VerifierErrors) -> VerifierStepResult<()> {
-        if let Some(block) = self.func.layout.entry_block() {
-            let expected_types = &self.func.signature.params;
-            let block_param_count = self.func.dfg.num_block_params(block);
-
-            if block_param_count != expected_types.len() {
-                return errors.fatal((
-                    block,
-                    format!(
-                        "entry block parameters ({}) must match function signature ({})",
-                        block_param_count,
-                        expected_types.len()
-                    ),
-                ));
-            }
-
-            for (i, &arg) in self.func.dfg.block_params(block).iter().enumerate() {
-                let arg_type = self.func.dfg.value_type(arg);
-                if arg_type != expected_types[i].value_type {
-                    errors.report((
-                        block,
-                        format!(
-                            "entry block parameter {} expected to have type {}, got {}",
-                            i, expected_types[i], arg_type
-                        ),
-                    ));
-                }
-            }
-        }
-
-        errors.as_result()
-    }
-
-    fn typecheck(&self, inst: Inst, errors: &mut VerifierErrors) -> VerifierStepResult<()> {
-        let inst_data = &self.func.dfg[inst];
-        let constraints = inst_data.opcode().constraints();
-
-        let ctrl_type = if let Some(value_typeset) = constraints.ctrl_typeset() {
-            // For polymorphic opcodes, determine the controlling type variable first.
-            let ctrl_type = self.func.dfg.ctrl_typevar(inst);
-
-            if !value_typeset.contains(ctrl_type) {
-                errors.report((
-                    inst,
-                    self.context(inst),
-                    format!("has an invalid controlling type {}", ctrl_type),
-                ));
-            }
-
-            ctrl_type
-        } else {
-            // Non-polymorphic instructions don't check the controlling type variable, so `Option`
-            // is unnecessary and we can just make it `INVALID`.
-            types::INVALID
-        };
-
-        // Typechecking instructions is never fatal
-        let _ = self.typecheck_results(inst, ctrl_type, errors);
-        let _ = self.typecheck_fixed_args(inst, ctrl_type, errors);
-        let _ = self.typecheck_variable_args(inst, errors);
-        let _ = self.typecheck_return(inst, errors);
-        let _ = self.typecheck_special(inst, ctrl_type, errors);
-
-        Ok(())
-    }
-
-    fn typecheck_results(
-        &self,
-        inst: Inst,
-        ctrl_type: Type,
-        errors: &mut VerifierErrors,
-    ) -> VerifierStepResult<()> {
-        let mut i = 0;
-        for &result in self.func.dfg.inst_results(inst) {
-            let result_type = self.func.dfg.value_type(result);
-            let expected_type = self.func.dfg.compute_result_type(inst, i, ctrl_type);
-            if let Some(expected_type) = expected_type {
-                if result_type != expected_type {
-                    errors.report((
-                        inst,
-                        self.context(inst),
-                        format!(
-                            "expected result {} ({}) to have type {}, found {}",
-                            i, result, expected_type, result_type
-                        ),
-                    ));
-                }
-            } else {
-                return errors.nonfatal((
-                    inst,
-                    self.context(inst),
-                    "has more result values than expected",
-                ));
-            }
-            i += 1;
-        }
-
-        // There aren't any more result types left.
-        if self.func.dfg.compute_result_type(inst, i, ctrl_type) != None {
-            return errors.nonfatal((
-                inst,
-                self.context(inst),
-                "has fewer result values than expected",
-            ));
-        }
-        Ok(())
-    }
-
-    fn typecheck_fixed_args(
-        &self,
-        inst: Inst,
-        ctrl_type: Type,
-        errors: &mut VerifierErrors,
-    ) -> VerifierStepResult<()> {
-        let constraints = self.func.dfg[inst].opcode().constraints();
-
-        for (i, &arg) in self.func.dfg.inst_fixed_args(inst).iter().enumerate() {
-            let arg_type = self.func.dfg.value_type(arg);
-            match constraints.value_argument_constraint(i, ctrl_type) {
-                ResolvedConstraint::Bound(expected_type) => {
-                    if arg_type != expected_type {
-                        errors.report((
-                            inst,
-                            self.context(inst),
-                            format!(
-                                "arg {} ({}) has type {}, expected {}",
-                                i, arg, arg_type, expected_type
-                            ),
-                        ));
-                    }
-                }
-                ResolvedConstraint::Free(type_set) => {
-                    if !type_set.contains(arg_type) {
-                        errors.report((
-                            inst,
-                            self.context(inst),
-                            format!(
-                                "arg {} ({}) with type {} failed to satisfy type set {:?}",
-                                i, arg, arg_type, type_set
-                            ),
-                        ));
-                    }
-                }
-            }
-        }
-        Ok(())
-    }
-
-    fn typecheck_variable_args(
-        &self,
-        inst: Inst,
-        errors: &mut VerifierErrors,
-    ) -> VerifierStepResult<()> {
-        match self.func.dfg.analyze_branch(inst) {
-            BranchInfo::SingleDest(block, _) => {
-                let iter = self
-                    .func
-                    .dfg
-                    .block_params(block)
-                    .iter()
-                    .map(|&v| self.func.dfg.value_type(v));
-                self.typecheck_variable_args_iterator(inst, iter, errors)?;
-            }
-            BranchInfo::Table(table, block) => {
-                if let Some(block) = block {
-                    let arg_count = self.func.dfg.num_block_params(block);
-                    if arg_count != 0 {
-                        return errors.nonfatal((
-                            inst,
-                            self.context(inst),
-                            format!(
-                                "takes no arguments, but had target {} with {} arguments",
-                                block, arg_count,
-                            ),
-                        ));
-                    }
-                }
-                for block in self.func.jump_tables[table].iter() {
-                    let arg_count = self.func.dfg.num_block_params(*block);
-                    if arg_count != 0 {
-                        return errors.nonfatal((
-                            inst,
-                            self.context(inst),
-                            format!(
-                                "takes no arguments, but had target {} with {} arguments",
-                                block, arg_count,
-                            ),
-                        ));
-                    }
-                }
-            }
-            BranchInfo::NotABranch => {}
-        }
-
-        match self.func.dfg[inst].analyze_call(&self.func.dfg.value_lists) {
-            CallInfo::Direct(func_ref, _) => {
-                let sig_ref = self.func.dfg.ext_funcs[func_ref].signature;
-                let arg_types = self.func.dfg.signatures[sig_ref]
-                    .params
-                    .iter()
-                    .map(|a| a.value_type);
-                self.typecheck_variable_args_iterator(inst, arg_types, errors)?;
-            }
-            CallInfo::Indirect(sig_ref, _) => {
-                let arg_types = self.func.dfg.signatures[sig_ref]
-                    .params
-                    .iter()
-                    .map(|a| a.value_type);
-                self.typecheck_variable_args_iterator(inst, arg_types, errors)?;
-            }
-            CallInfo::NotACall => {}
-        }
-        Ok(())
-    }
-
-    fn typecheck_variable_args_iterator<I: Iterator<Item = Type>>(
-        &self,
-        inst: Inst,
-        iter: I,
-        errors: &mut VerifierErrors,
-    ) -> VerifierStepResult<()> {
-        let variable_args = self.func.dfg.inst_variable_args(inst);
-        let mut i = 0;
-
-        for expected_type in iter {
-            if i >= variable_args.len() {
-                // Result count mismatch handled below, we want the full argument count first though
-                i += 1;
-                continue;
-            }
-            let arg = variable_args[i];
-            let arg_type = self.func.dfg.value_type(arg);
-            if expected_type != arg_type {
-                errors.report((
-                    inst,
-                    self.context(inst),
-                    format!(
-                        "arg {} ({}) has type {}, expected {}",
-                        i, variable_args[i], arg_type, expected_type
-                    ),
-                ));
-            }
-            i += 1;
-        }
-        if i != variable_args.len() {
-            return errors.nonfatal((
-                inst,
-                self.context(inst),
-                format!(
-                    "mismatched argument count for `{}`: got {}, expected {}",
-                    self.func.dfg.display_inst(inst),
-                    variable_args.len(),
-                    i,
-                ),
-            ));
-        }
-        Ok(())
-    }
-
-    fn typecheck_return(&self, inst: Inst, errors: &mut VerifierErrors) -> VerifierStepResult<()> {
-        if self.func.dfg[inst].opcode().is_return() {
-            let args = self.func.dfg.inst_variable_args(inst);
-            let expected_types = &self.func.signature.returns;
-            if args.len() != expected_types.len() {
-                return errors.nonfatal((
-                    inst,
-                    self.context(inst),
-                    "arguments of return must match function signature",
-                ));
-            }
-            for (i, (&arg, &expected_type)) in args.iter().zip(expected_types).enumerate() {
-                let arg_type = self.func.dfg.value_type(arg);
-                if arg_type != expected_type.value_type {
-                    errors.report((
-                        inst,
-                        self.context(inst),
-                        format!(
-                            "arg {} ({}) has type {}, must match function signature of {}",
-                            i, arg, arg_type, expected_type
-                        ),
-                    ));
-                }
-            }
-        }
-        Ok(())
-    }
-
-    // Check special-purpose type constraints that can't be expressed in the normal opcode
-    // constraints.
-    fn typecheck_special(
-        &self,
-        inst: Inst,
-        ctrl_type: Type,
-        errors: &mut VerifierErrors,
-    ) -> VerifierStepResult<()> {
-        match self.func.dfg[inst] {
-            ir::InstructionData::Unary { opcode, arg } => {
-                let arg_type = self.func.dfg.value_type(arg);
-                match opcode {
-                    Opcode::Bextend | Opcode::Uextend | Opcode::Sextend | Opcode::Fpromote => {
-                        if arg_type.lane_count() != ctrl_type.lane_count() {
-                            return errors.nonfatal((
-                                inst,
-                                self.context(inst),
-                                format!(
-                                    "input {} and output {} must have same number of lanes",
-                                    arg_type, ctrl_type,
-                                ),
-                            ));
-                        }
-                        if arg_type.lane_bits() >= ctrl_type.lane_bits() {
-                            return errors.nonfatal((
-                                inst,
-                                self.context(inst),
-                                format!(
-                                    "input {} must be smaller than output {}",
-                                    arg_type, ctrl_type,
-                                ),
-                            ));
-                        }
-                    }
-                    Opcode::Breduce | Opcode::Ireduce | Opcode::Fdemote => {
-                        if arg_type.lane_count() != ctrl_type.lane_count() {
-                            return errors.nonfatal((
-                                inst,
-                                self.context(inst),
-                                format!(
-                                    "input {} and output {} must have same number of lanes",
-                                    arg_type, ctrl_type,
-                                ),
-                            ));
-                        }
-                        if arg_type.lane_bits() <= ctrl_type.lane_bits() {
-                            return errors.nonfatal((
-                                inst,
-                                self.context(inst),
-                                format!(
-                                    "input {} must be larger than output {}",
-                                    arg_type, ctrl_type,
-                                ),
-                            ));
-                        }
-                    }
-                    _ => {}
-                }
-            }
-            ir::InstructionData::HeapAddr { heap, arg, .. } => {
-                let index_type = self.func.dfg.value_type(arg);
-                let heap_index_type = self.func.heaps[heap].index_type;
-                if index_type != heap_index_type {
-                    return errors.nonfatal((
-                        inst,
-                        self.context(inst),
-                        format!(
-                            "index type {} differs from heap index type {}",
-                            index_type, heap_index_type,
-                        ),
-                    ));
-                }
-            }
-            ir::InstructionData::TableAddr { table, arg, .. } => {
-                let index_type = self.func.dfg.value_type(arg);
-                let table_index_type = self.func.tables[table].index_type;
-                if index_type != table_index_type {
-                    return errors.nonfatal((
-                        inst,
-                        self.context(inst),
-                        format!(
-                            "index type {} differs from table index type {}",
-                            index_type, table_index_type,
-                        ),
-                    ));
-                }
-            }
-            ir::InstructionData::UnaryGlobalValue { global_value, .. } => {
-                if let Some(isa) = self.isa {
-                    let inst_type = self.func.dfg.value_type(self.func.dfg.first_result(inst));
-                    let global_type = self.func.global_values[global_value].global_type(isa);
-                    if inst_type != global_type {
-                        return errors.nonfatal((
-                            inst, self.context(inst),
-                            format!(
-                                "global_value instruction with type {} references global value with type {}",
-                                inst_type, global_type
-                            )),
-                        );
-                    }
-                }
-            }
-            _ => {}
-        }
-        Ok(())
-    }
-
-    fn cfg_integrity(
-        &self,
-        cfg: &ControlFlowGraph,
-        errors: &mut VerifierErrors,
-    ) -> VerifierStepResult<()> {
-        let mut expected_succs = BTreeSet::<Block>::new();
-        let mut got_succs = BTreeSet::<Block>::new();
-        let mut expected_preds = BTreeSet::<Inst>::new();
-        let mut got_preds = BTreeSet::<Inst>::new();
-
-        for block in self.func.layout.blocks() {
-            expected_succs.extend(self.expected_cfg.succ_iter(block));
-            got_succs.extend(cfg.succ_iter(block));
-
-            let missing_succs: Vec<Block> =
-                expected_succs.difference(&got_succs).cloned().collect();
-            if !missing_succs.is_empty() {
-                errors.report((
-                    block,
-                    format!("cfg lacked the following successor(s) {:?}", missing_succs),
-                ));
-                continue;
-            }
-
-            let excess_succs: Vec<Block> = got_succs.difference(&expected_succs).cloned().collect();
-            if !excess_succs.is_empty() {
-                errors.report((
-                    block,
-                    format!("cfg had unexpected successor(s) {:?}", excess_succs),
-                ));
-                continue;
-            }
-
-            expected_preds.extend(
-                self.expected_cfg
-                    .pred_iter(block)
-                    .map(|BlockPredecessor { inst, .. }| inst),
-            );
-            got_preds.extend(
-                cfg.pred_iter(block)
-                    .map(|BlockPredecessor { inst, .. }| inst),
-            );
-
-            let missing_preds: Vec<Inst> = expected_preds.difference(&got_preds).cloned().collect();
-            if !missing_preds.is_empty() {
-                errors.report((
-                    block,
-                    format!(
-                        "cfg lacked the following predecessor(s) {:?}",
-                        missing_preds
-                    ),
-                ));
-                continue;
-            }
-
-            let excess_preds: Vec<Inst> = got_preds.difference(&expected_preds).cloned().collect();
-            if !excess_preds.is_empty() {
-                errors.report((
-                    block,
-                    format!("cfg had unexpected predecessor(s) {:?}", excess_preds),
-                ));
-                continue;
-            }
-
-            expected_succs.clear();
-            got_succs.clear();
-            expected_preds.clear();
-            got_preds.clear();
-        }
-        errors.as_result()
-    }
-
-    fn immediate_constraints(
-        &self,
-        inst: Inst,
-        errors: &mut VerifierErrors,
-    ) -> VerifierStepResult<()> {
-        let inst_data = &self.func.dfg[inst];
-
-        match *inst_data {
-            ir::InstructionData::Store { flags, .. }
-            | ir::InstructionData::StoreComplex { flags, .. } => {
-                if flags.readonly() {
-                    errors.fatal((
-                        inst,
-                        self.context(inst),
-                        "A store instruction cannot have the `readonly` MemFlag",
-                    ))
-                } else {
-                    Ok(())
-                }
-            }
-            ir::InstructionData::BinaryImm8 {
-                opcode: ir::instructions::Opcode::Extractlane,
-                imm: lane,
-                arg,
-                ..
-            }
-            | ir::InstructionData::TernaryImm8 {
-                opcode: ir::instructions::Opcode::Insertlane,
-                imm: lane,
-                args: [arg, _],
-                ..
-            } => {
-                // We must be specific about the opcodes above because other instructions are using
-                // the same formats.
-                let ty = self.func.dfg.value_type(arg);
-                if u16::from(lane) >= ty.lane_count() {
-                    errors.fatal((
-                        inst,
-                        self.context(inst),
-                        format!("The lane {} does not index into the type {}", lane, ty,),
-                    ))
-                } else {
-                    Ok(())
-                }
-            }
-            _ => Ok(()),
-        }
-    }
-
-    fn typecheck_function_signature(&self, errors: &mut VerifierErrors) -> VerifierStepResult<()> {
-        self.func
-            .signature
-            .params
-            .iter()
-            .enumerate()
-            .filter(|(_, &param)| param.value_type == types::INVALID)
-            .for_each(|(i, _)| {
-                errors.report((
-                    AnyEntity::Function,
-                    format!("Parameter at position {} has an invalid type", i),
-                ));
-            });
-
-        self.func
-            .signature
-            .returns
-            .iter()
-            .enumerate()
-            .filter(|(_, &ret)| ret.value_type == types::INVALID)
-            .for_each(|(i, _)| {
-                errors.report((
-                    AnyEntity::Function,
-                    format!("Return value at position {} has an invalid type", i),
-                ))
-            });
-
-        self.func
-            .signature
-            .returns
-            .iter()
-            .enumerate()
-            .for_each(|(i, ret)| {
-                if let ArgumentPurpose::StructArgument(_) = ret.purpose {
-                    errors.report((
-                        AnyEntity::Function,
-                        format!("Return value at position {} can't be an struct argument", i),
-                    ))
-                }
-            });
-
-        if errors.has_error() {
-            Err(())
-        } else {
-            Ok(())
-        }
-    }
-
-    pub fn run(&self, errors: &mut VerifierErrors) -> VerifierStepResult<()> {
-        self.verify_global_values(errors)?;
-        self.verify_heaps(errors)?;
-        self.verify_tables(errors)?;
-        self.verify_jump_tables(errors)?;
-        self.typecheck_entry_block_params(errors)?;
-        self.typecheck_function_signature(errors)?;
-
-        for block in self.func.layout.blocks() {
-            if self.func.layout.first_inst(block).is_none() {
-                return errors.fatal((block, format!("{} cannot be empty", block)));
-            }
-            for inst in self.func.layout.block_insts(block) {
-                self.block_integrity(block, inst, errors)?;
-                self.instruction_integrity(inst, errors)?;
-                self.typecheck(inst, errors)?;
-                self.immediate_constraints(inst, errors)?;
-            }
-
-            self.encodable_as_bb(block, errors)?;
-        }
-
-        verify_flags(self.func, &self.expected_cfg, errors)?;
-
-        if !errors.is_empty() {
-            log::warn!(
-                "Found verifier errors in function:\n{}",
-                pretty_verifier_error(self.func, None, errors.clone())
-            );
-        }
-
-        Ok(())
-    }
-}
-
-#[cfg(test)]
-mod tests {
-    use super::{Verifier, VerifierError, VerifierErrors};
-    use crate::entity::EntityList;
-    use crate::ir::instructions::{InstructionData, Opcode};
-    use crate::ir::{types, AbiParam, Function};
-    use crate::settings;
-
-    macro_rules! assert_err_with_msg {
-        ($e:expr, $msg:expr) => {
-            match $e.0.get(0) {
-                None => panic!("Expected an error"),
-                Some(&VerifierError { ref message, .. }) => {
-                    if !message.contains($msg) {
-                        #[cfg(feature = "std")]
-                        panic!("'{}' did not contain the substring '{}'", message, $msg);
-                        #[cfg(not(feature = "std"))]
-                        panic!("error message did not contain the expected substring");
-                    }
-                }
-            }
-        };
-    }
-
-    #[test]
-    fn empty() {
-        let func = Function::new();
-        let flags = &settings::Flags::new(settings::builder());
-        let verifier = Verifier::new(&func, flags.into());
-        let mut errors = VerifierErrors::default();
-
-        assert_eq!(verifier.run(&mut errors), Ok(()));
-        assert!(errors.0.is_empty());
-    }
-
-    #[test]
-    fn bad_instruction_format() {
-        let mut func = Function::new();
-        let block0 = func.dfg.make_block();
-        func.layout.append_block(block0);
-        let nullary_with_bad_opcode = func.dfg.make_inst(InstructionData::UnaryImm {
-            opcode: Opcode::F32const,
-            imm: 0.into(),
-        });
-        func.layout.append_inst(nullary_with_bad_opcode, block0);
-        func.layout.append_inst(
-            func.dfg.make_inst(InstructionData::Jump {
-                opcode: Opcode::Jump,
-                destination: block0,
-                args: EntityList::default(),
-            }),
-            block0,
-        );
-        let flags = &settings::Flags::new(settings::builder());
-        let verifier = Verifier::new(&func, flags.into());
-        let mut errors = VerifierErrors::default();
-
-        let _ = verifier.run(&mut errors);
-
-        assert_err_with_msg!(errors, "instruction format");
-    }
-
-    #[test]
-    fn test_function_invalid_param() {
-        let mut func = Function::new();
-        func.signature.params.push(AbiParam::new(types::INVALID));
-
-        let mut errors = VerifierErrors::default();
-        let flags = &settings::Flags::new(settings::builder());
-        let verifier = Verifier::new(&func, flags.into());
-
-        let _ = verifier.typecheck_function_signature(&mut errors);
-        assert_err_with_msg!(errors, "Parameter at position 0 has an invalid type");
-    }
-
-    #[test]
-    fn test_function_invalid_return_value() {
-        let mut func = Function::new();
-        func.signature.returns.push(AbiParam::new(types::INVALID));
-
-        let mut errors = VerifierErrors::default();
-        let flags = &settings::Flags::new(settings::builder());
-        let verifier = Verifier::new(&func, flags.into());
-
-        let _ = verifier.typecheck_function_signature(&mut errors);
-        assert_err_with_msg!(errors, "Return value at position 0 has an invalid type");
-    }
-
-    #[test]
-    fn test_printing_contextual_errors() {
-        // Build function.
-        let mut func = Function::new();
-        let block0 = func.dfg.make_block();
-        func.layout.append_block(block0);
-
-        // Build instruction: v0, v1 = iconst 42
-        let inst = func.dfg.make_inst(InstructionData::UnaryImm {
-            opcode: Opcode::Iconst,
-            imm: 42.into(),
-        });
-        func.dfg.append_result(inst, types::I32);
-        func.dfg.append_result(inst, types::I32);
-        func.layout.append_inst(inst, block0);
-
-        // Setup verifier.
-        let mut errors = VerifierErrors::default();
-        let flags = &settings::Flags::new(settings::builder());
-        let verifier = Verifier::new(&func, flags.into());
-
-        // Now the error message, when printed, should contain the instruction sequence causing the
-        // error (i.e. v0, v1 = iconst.i32 42) and not only its entity value (i.e. inst0)
-        let _ = verifier.typecheck_results(inst, types::I32, &mut errors);
-        assert_eq!(
-            format!("{}", errors.0[0]),
-            "inst0 (v0, v1 = iconst.i32 42): has more result values than expected"
-        )
-    }
-
-    #[test]
-    fn test_empty_block() {
-        let mut func = Function::new();
-        let block0 = func.dfg.make_block();
-        func.layout.append_block(block0);
-
-        let flags = &settings::Flags::new(settings::builder());
-        let verifier = Verifier::new(&func, flags.into());
-        let mut errors = VerifierErrors::default();
-        let _ = verifier.run(&mut errors);
-
-        assert_err_with_msg!(errors, "block0 cannot be empty");
-    }
-}
diff --git a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/write.rs b/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/write.rs
deleted file mode 100644
index d046da505..000000000
--- a/collector/compile-benchmarks/cranelift-codegen-0.82.1/src/write.rs
+++ /dev/null
@@ -1,697 +0,0 @@
-//! Converting Cranelift IR to text.
-//!
-//! The `write` module provides the `write_function` function which converts an IR `Function` to an
-//! equivalent textual form. This textual form can be read back by the `cranelift-reader` crate.
-
-use crate::entity::SecondaryMap;
-use crate::ir::entities::AnyEntity;
-use crate::ir::{Block, DataFlowGraph, Function, Inst, SigRef, Type, Value, ValueDef};
-use crate::packed_option::ReservedValue;
-use alloc::string::String;
-use alloc::vec::Vec;
-use core::fmt::{self, Write};
-
-/// A `FuncWriter` used to decorate functions during printing.
-pub trait FuncWriter {
-    /// Write the basic block header for the current function.
-    fn write_block_header(
-        &mut self,
-        w: &mut dyn Write,
-        func: &Function,
-        block: Block,
-        indent: usize,
-    ) -> fmt::Result;
-
-    /// Write the given `inst` to `w`.
-    fn write_instruction(
-        &mut self,
-        w: &mut dyn Write,
-        func: &Function,
-        aliases: &SecondaryMap<Value, Vec<Value>>,
-        inst: Inst,
-        indent: usize,
-    ) -> fmt::Result;
-
-    /// Write the preamble to `w`. By default, this uses `write_entity_definition`.
-    fn write_preamble(&mut self, w: &mut dyn Write, func: &Function) -> Result<bool, fmt::Error> {
-        self.super_preamble(w, func)
-    }
-
-    /// Default impl of `write_preamble`
-    fn super_preamble(&mut self, w: &mut dyn Write, func: &Function) -> Result<bool, fmt::Error> {
-        let mut any = false;
-
-        for (ss, slot) in func.stack_slots.iter() {
-            any = true;
-            self.write_entity_definition(w, func, ss.into(), slot)?;
-        }
-
-        for (gv, gv_data) in &func.global_values {
-            any = true;
-            self.write_entity_definition(w, func, gv.into(), gv_data)?;
-        }
-
-        for (heap, heap_data) in &func.heaps {
-            if !heap_data.index_type.is_invalid() {
-                any = true;
-                self.write_entity_definition(w, func, heap.into(), heap_data)?;
-            }
-        }
-
-        for (table, table_data) in &func.tables {
-            if !table_data.index_type.is_invalid() {
-                any = true;
-                self.write_entity_definition(w, func, table.into(), table_data)?;
-            }
-        }
-
-        // Write out all signatures before functions since function declarations can refer to
-        // signatures.
-        for (sig, sig_data) in &func.dfg.signatures {
-            any = true;
-            self.write_entity_definition(w, func, sig.into(), &sig_data)?;
-        }
-
-        for (fnref, ext_func) in &func.dfg.ext_funcs {
-            if ext_func.signature != SigRef::reserved_value() {
-                any = true;
-                self.write_entity_definition(w, func, fnref.into(), ext_func)?;
-            }
-        }
-
-        for (jt, jt_data) in &func.jump_tables {
-            any = true;
-            self.write_entity_definition(w, func, jt.into(), jt_data)?;
-        }
-
-        for (&cref, cval) in func.dfg.constants.iter() {
-            any = true;
-            self.write_entity_definition(w, func, cref.into(), cval)?;
-        }
-
-        if let Some(limit) = func.stack_limit {
-            any = true;
-            self.write_entity_definition(w, func, AnyEntity::StackLimit, &limit)?;
-        }
-
-        Ok(any)
-    }
-
-    /// Write an entity definition defined in the preamble to `w`.
-    fn write_entity_definition(
-        &mut self,
-        w: &mut dyn Write,
-        func: &Function,
-        entity: AnyEntity,
-        value: &dyn fmt::Display,
-    ) -> fmt::Result {
-        self.super_entity_definition(w, func, entity, value)
-    }
-
-    /// Default impl of `write_entity_definition`
-    #[allow(unused_variables)]
-    fn super_entity_definition(
-        &mut self,
-        w: &mut dyn Write,
-        func: &Function,
-        entity: AnyEntity,
-        value: &dyn fmt::Display,
-    ) -> fmt::Result {
-        writeln!(w, "    {} = {}", entity, value)
-    }
-}
-
-/// A `PlainWriter` that doesn't decorate the function.
-pub struct PlainWriter;
-
-impl FuncWriter for PlainWriter {
-    fn write_instruction(
-        &mut self,
-        w: &mut dyn Write,
-        func: &Function,
-        aliases: &SecondaryMap<Value, Vec<Value>>,
-        inst: Inst,
-        indent: usize,
-    ) -> fmt::Result {
-        write_instruction(w, func, aliases, inst, indent)
-    }
-
-    fn write_block_header(
-        &mut self,
-        w: &mut dyn Write,
-        func: &Function,
-        block: Block,
-        indent: usize,
-    ) -> fmt::Result {
-        write_block_header(w, func, block, indent)
-    }
-}
-
-/// Write `func` to `w` as equivalent text.
-/// Use `isa` to emit ISA-dependent annotations.
-pub fn write_function(w: &mut dyn Write, func: &Function) -> fmt::Result {
-    decorate_function(&mut PlainWriter, w, func)
-}
-
-/// Create a reverse-alias map from a value to all aliases having that value as a direct target
-fn alias_map(func: &Function) -> SecondaryMap<Value, Vec<Value>> {
-    let mut aliases = SecondaryMap::<_, Vec<_>>::new();
-    for v in func.dfg.values() {
-        // VADFS returns the immediate target of an alias
-        if let Some(k) = func.dfg.value_alias_dest_for_serialization(v) {
-            aliases[k].push(v);
-        }
-    }
-    aliases
-}
-
-/// Writes `func` to `w` as text.
-/// write_function_plain is passed as 'closure' to print instructions as text.
-/// pretty_function_error is passed as 'closure' to add error decoration.
-pub fn decorate_function<FW: FuncWriter>(
-    func_w: &mut FW,
-    w: &mut dyn Write,
-    func: &Function,
-) -> fmt::Result {
-    write!(w, "function ")?;
-    write_spec(w, func)?;
-    writeln!(w, " {{")?;
-    let aliases = alias_map(func);
-    let mut any = func_w.write_preamble(w, func)?;
-    for block in &func.layout {
-        if any {
-            writeln!(w)?;
-        }
-        decorate_block(func_w, w, func, &aliases, block)?;
-        any = true;
-    }
-    writeln!(w, "}}")
-}
-
-//----------------------------------------------------------------------
-//
-// Function spec.
-
-fn write_spec(w: &mut dyn Write, func: &Function) -> fmt::Result {
-    write!(w, "{}{}", func.name, func.signature)
-}
-
-//----------------------------------------------------------------------
-//
-// Basic blocks
-
-fn write_arg(w: &mut dyn Write, func: &Function, arg: Value) -> fmt::Result {
-    write!(w, "{}: {}", arg, func.dfg.value_type(arg))
-}
-
-/// Write out the basic block header, outdented:
-///
-///    block1:
-///    block1(v1: i32):
-///    block10(v4: f64, v5: b1):
-///
-pub fn write_block_header(
-    w: &mut dyn Write,
-    func: &Function,
-    block: Block,
-    indent: usize,
-) -> fmt::Result {
-    let cold = if func.layout.is_cold(block) {
-        " cold"
-    } else {
-        ""
-    };
-
-    // The `indent` is the instruction indentation. block headers are 4 spaces out from that.
-    write!(w, "{1:0$}{2}", indent - 4, "", block)?;
-
-    let mut args = func.dfg.block_params(block).iter().cloned();
-    match args.next() {
-        None => return writeln!(w, "{}:", cold),
-        Some(arg) => {
-            write!(w, "(")?;
-            write_arg(w, func, arg)?;
-        }
-    }
-    // Remaining arguments.
-    for arg in args {
-        write!(w, ", ")?;
-        write_arg(w, func, arg)?;
-    }
-    writeln!(w, "){}:", cold)
-}
-
-fn decorate_block<FW: FuncWriter>(
-    func_w: &mut FW,
-    w: &mut dyn Write,
-    func: &Function,
-    aliases: &SecondaryMap<Value, Vec<Value>>,
-    block: Block,
-) -> fmt::Result {
-    // Indent all instructions if any srclocs are present.
-    let indent = if func.srclocs.is_empty() { 4 } else { 36 };
-
-    func_w.write_block_header(w, func, block, indent)?;
-    for a in func.dfg.block_params(block).iter().cloned() {
-        write_value_aliases(w, aliases, a, indent)?;
-    }
-
-    for inst in func.layout.block_insts(block) {
-        func_w.write_instruction(w, func, aliases, inst, indent)?;
-    }
-
-    Ok(())
-}
-
-//----------------------------------------------------------------------
-//
-// Instructions
-
-// Should `inst` be printed with a type suffix?
-//
-// Polymorphic instructions may need a suffix indicating the value of the controlling type variable
-// if it can't be trivially inferred.
-//
-fn type_suffix(func: &Function, inst: Inst) -> Option<Type> {
-    let inst_data = &func.dfg[inst];
-    let constraints = inst_data.opcode().constraints();
-
-    if !constraints.is_polymorphic() {
-        return None;
-    }
-
-    // If the controlling type variable can be inferred from the type of the designated value input
-    // operand, we don't need the type suffix.
-    if constraints.use_typevar_operand() {
-        let ctrl_var = inst_data.typevar_operand(&func.dfg.value_lists).unwrap();
-        let def_block = match func.dfg.value_def(ctrl_var) {
-            ValueDef::Result(instr, _) => func.layout.inst_block(instr),
-            ValueDef::Param(block, _) => Some(block),
-        };
-        if def_block.is_some() && def_block == func.layout.inst_block(inst) {
-            return None;
-        }
-    }
-
-    let rtype = func.dfg.ctrl_typevar(inst);
-    assert!(
-        !rtype.is_invalid(),
-        "Polymorphic instruction must produce a result"
-    );
-    Some(rtype)
-}
-
-/// Write out any aliases to the given target, including indirect aliases
-fn write_value_aliases(
-    w: &mut dyn Write,
-    aliases: &SecondaryMap<Value, Vec<Value>>,
-    target: Value,
-    indent: usize,
-) -> fmt::Result {
-    let mut todo_stack = vec![target];
-    while let Some(target) = todo_stack.pop() {
-        for &a in &aliases[target] {
-            writeln!(w, "{1:0$}{2} -> {3}", indent, "", a, target)?;
-            todo_stack.push(a);
-        }
-    }
-
-    Ok(())
-}
-
-fn write_instruction(
-    w: &mut dyn Write,
-    func: &Function,
-    aliases: &SecondaryMap<Value, Vec<Value>>,
-    inst: Inst,
-    indent: usize,
-) -> fmt::Result {
-    // Prefix containing source location, encoding, and value locations.
-    let mut s = String::with_capacity(16);
-
-    // Source location goes first.
-    let srcloc = func.srclocs[inst];
-    if !srcloc.is_default() {
-        write!(s, "{} ", srcloc)?;
-    }
-
-    // Write out prefix and indent the instruction.
-    write!(w, "{1:0$}", indent, s)?;
-
-    // Write out the result values, if any.
-    let mut has_results = false;
-    for r in func.dfg.inst_results(inst) {
-        if !has_results {
-            has_results = true;
-            write!(w, "{}", r)?;
-        } else {
-            write!(w, ", {}", r)?;
-        }
-    }
-    if has_results {
-        write!(w, " = ")?;
-    }
-
-    // Then the opcode, possibly with a '.type' suffix.
-    let opcode = func.dfg[inst].opcode();
-
-    match type_suffix(func, inst) {
-        Some(suf) => write!(w, "{}.{}", opcode, suf)?,
-        None => write!(w, "{}", opcode)?,
-    }
-
-    write_operands(w, &func.dfg, inst)?;
-    writeln!(w)?;
-
-    // Value aliases come out on lines after the instruction defining the referent.
-    for r in func.dfg.inst_results(inst) {
-        write_value_aliases(w, aliases, *r, indent)?;
-    }
-    Ok(())
-}
-
-/// Write the operands of `inst` to `w` with a prepended space.
-pub fn write_operands(w: &mut dyn Write, dfg: &DataFlowGraph, inst: Inst) -> fmt::Result {
-    let pool = &dfg.value_lists;
-    use crate::ir::instructions::InstructionData::*;
-    match dfg[inst] {
-        AtomicRmw { op, args, .. } => write!(w, " {}, {}, {}", op, args[0], args[1]),
-        AtomicCas { args, .. } => write!(w, " {}, {}, {}", args[0], args[1], args[2]),
-        LoadNoOffset { flags, arg, .. } => write!(w, "{} {}", flags, arg),
-        StoreNoOffset { flags, args, .. } => write!(w, "{} {}, {}", flags, args[0], args[1]),
-        Unary { arg, .. } => write!(w, " {}", arg),
-        UnaryImm { imm, .. } => write!(w, " {}", imm),
-        UnaryIeee32 { imm, .. } => write!(w, " {}", imm),
-        UnaryIeee64 { imm, .. } => write!(w, " {}", imm),
-        UnaryBool { imm, .. } => write!(w, " {}", imm),
-        UnaryGlobalValue { global_value, .. } => write!(w, " {}", global_value),
-        UnaryConst {
-            constant_handle, ..
-        } => write!(w, " {}", constant_handle),
-        Binary { args, .. } => write!(w, " {}, {}", args[0], args[1]),
-        BinaryImm8 { arg, imm, .. } => write!(w, " {}, {}", arg, imm),
-        BinaryImm64 { arg, imm, .. } => write!(w, " {}, {}", arg, imm),
-        Ternary { args, .. } => write!(w, " {}, {}, {}", args[0], args[1], args[2]),
-        MultiAry { ref args, .. } => {
-            if args.is_empty() {
-                write!(w, "")
-            } else {
-                write!(w, " {}", DisplayValues(args.as_slice(pool)))
-            }
-        }
-        NullAry { .. } => write!(w, " "),
-        TernaryImm8 { imm, args, .. } => write!(w, " {}, {}, {}", args[0], args[1], imm),
-        Shuffle { imm, args, .. } => {
-            let data = dfg.immediates.get(imm).expect(
-                "Expected the shuffle mask to already be inserted into the immediates table",
-            );
-            write!(w, " {}, {}, {}", args[0], args[1], data)
-        }
-        IntCompare { cond, args, .. } => write!(w, " {} {}, {}", cond, args[0], args[1]),
-        IntCompareImm { cond, arg, imm, .. } => write!(w, " {} {}, {}", cond, arg, imm),
-        IntCond { cond, arg, .. } => write!(w, " {} {}", cond, arg),
-        FloatCompare { cond, args, .. } => write!(w, " {} {}, {}", cond, args[0], args[1]),
-        FloatCond { cond, arg, .. } => write!(w, " {} {}", cond, arg),
-        IntSelect { cond, args, .. } => {
-            write!(w, " {} {}, {}, {}", cond, args[0], args[1], args[2])
-        }
-        Jump {
-            destination,
-            ref args,
-            ..
-        } => {
-            write!(w, " {}", destination)?;
-            write_block_args(w, args.as_slice(pool))
-        }
-        Branch {
-            destination,
-            ref args,
-            ..
-        } => {
-            let args = args.as_slice(pool);
-            write!(w, " {}, {}", args[0], destination)?;
-            write_block_args(w, &args[1..])
-        }
-        BranchInt {
-            cond,
-            destination,
-            ref args,
-            ..
-        } => {
-            let args = args.as_slice(pool);
-            write!(w, " {} {}, {}", cond, args[0], destination)?;
-            write_block_args(w, &args[1..])
-        }
-        BranchFloat {
-            cond,
-            destination,
-            ref args,
-            ..
-        } => {
-            let args = args.as_slice(pool);
-            write!(w, " {} {}, {}", cond, args[0], destination)?;
-            write_block_args(w, &args[1..])
-        }
-        BranchIcmp {
-            cond,
-            destination,
-            ref args,
-            ..
-        } => {
-            let args = args.as_slice(pool);
-            write!(w, " {} {}, {}, {}", cond, args[0], args[1], destination)?;
-            write_block_args(w, &args[2..])
-        }
-        BranchTable {
-            arg,
-            destination,
-            table,
-            ..
-        } => write!(w, " {}, {}, {}", arg, destination, table),
-        Call {
-            func_ref, ref args, ..
-        } => write!(w, " {}({})", func_ref, DisplayValues(args.as_slice(pool))),
-        CallIndirect {
-            sig_ref, ref args, ..
-        } => {
-            let args = args.as_slice(pool);
-            write!(
-                w,
-                " {}, {}({})",
-                sig_ref,
-                args[0],
-                DisplayValues(&args[1..])
-            )
-        }
-        FuncAddr { func_ref, .. } => write!(w, " {}", func_ref),
-        StackLoad {
-            stack_slot, offset, ..
-        } => write!(w, " {}{}", stack_slot, offset),
-        StackStore {
-            arg,
-            stack_slot,
-            offset,
-            ..
-        } => write!(w, " {}, {}{}", arg, stack_slot, offset),
-        HeapAddr { heap, arg, imm, .. } => write!(w, " {}, {}, {}", heap, arg, imm),
-        TableAddr { table, arg, .. } => write!(w, " {}, {}", table, arg),
-        Load {
-            flags, arg, offset, ..
-        } => write!(w, "{} {}{}", flags, arg, offset),
-        LoadComplex {
-            flags,
-            ref args,
-            offset,
-            ..
-        } => {
-            let args = args.as_slice(pool);
-            write!(
-                w,
-                "{} {}{}",
-                flags,
-                DisplayValuesWithDelimiter(&args, '+'),
-                offset
-            )
-        }
-        Store {
-            flags,
-            args,
-            offset,
-            ..
-        } => write!(w, "{} {}, {}{}", flags, args[0], args[1], offset),
-        StoreComplex {
-            flags,
-            ref args,
-            offset,
-            ..
-        } => {
-            let args = args.as_slice(pool);
-            write!(
-                w,
-                "{} {}, {}{}",
-                flags,
-                args[0],
-                DisplayValuesWithDelimiter(&args[1..], '+'),
-                offset
-            )
-        }
-        Trap { code, .. } => write!(w, " {}", code),
-        CondTrap { arg, code, .. } => write!(w, " {}, {}", arg, code),
-        IntCondTrap {
-            cond, arg, code, ..
-        } => write!(w, " {} {}, {}", cond, arg, code),
-        FloatCondTrap {
-            cond, arg, code, ..
-        } => write!(w, " {} {}, {}", cond, arg, code),
-    }
-}
-
-/// Write block args using optional parantheses.
-fn write_block_args(w: &mut dyn Write, args: &[Value]) -> fmt::Result {
-    if args.is_empty() {
-        Ok(())
-    } else {
-        write!(w, "({})", DisplayValues(args))
-    }
-}
-
-/// Displayable slice of values.
-struct DisplayValues<'a>(&'a [Value]);
-
-impl<'a> fmt::Display for DisplayValues<'a> {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        for (i, val) in self.0.iter().enumerate() {
-            if i == 0 {
-                write!(f, "{}", val)?;
-            } else {
-                write!(f, ", {}", val)?;
-            }
-        }
-        Ok(())
-    }
-}
-
-struct DisplayValuesWithDelimiter<'a>(&'a [Value], char);
-
-impl<'a> fmt::Display for DisplayValuesWithDelimiter<'a> {
-    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        for (i, val) in self.0.iter().enumerate() {
-            if i == 0 {
-                write!(f, "{}", val)?;
-            } else {
-                write!(f, "{}{}", self.1, val)?;
-            }
-        }
-        Ok(())
-    }
-}
-
-#[cfg(test)]
-mod tests {
-    use crate::cursor::{Cursor, CursorPosition, FuncCursor};
-    use crate::ir::types;
-    use crate::ir::{ExternalName, Function, InstBuilder, StackSlotData, StackSlotKind};
-    use alloc::string::ToString;
-
-    #[test]
-    fn basic() {
-        let mut f = Function::new();
-        assert_eq!(f.to_string(), "function u0:0() fast {\n}\n");
-
-        f.name = ExternalName::testcase("foo");
-        assert_eq!(f.to_string(), "function %foo() fast {\n}\n");
-
-        f.create_stack_slot(StackSlotData::new(StackSlotKind::ExplicitSlot, 4));
-        assert_eq!(
-            f.to_string(),
-            "function %foo() fast {\n    ss0 = explicit_slot 4\n}\n"
-        );
-
-        let block = f.dfg.make_block();
-        f.layout.append_block(block);
-        assert_eq!(
-            f.to_string(),
-            "function %foo() fast {\n    ss0 = explicit_slot 4\n\nblock0:\n}\n"
-        );
-
-        f.dfg.append_block_param(block, types::I8);
-        assert_eq!(
-            f.to_string(),
-            "function %foo() fast {\n    ss0 = explicit_slot 4\n\nblock0(v0: i8):\n}\n"
-        );
-
-        f.dfg.append_block_param(block, types::F32.by(4).unwrap());
-        assert_eq!(
-            f.to_string(),
-            "function %foo() fast {\n    ss0 = explicit_slot 4\n\nblock0(v0: i8, v1: f32x4):\n}\n"
-        );
-
-        {
-            let mut cursor = FuncCursor::new(&mut f);
-            cursor.set_position(CursorPosition::After(block));
-            cursor.ins().return_(&[])
-        };
-        assert_eq!(
-            f.to_string(),
-            "function %foo() fast {\n    ss0 = explicit_slot 4\n\nblock0(v0: i8, v1: f32x4):\n    return\n}\n"
-        );
-    }
-
-    #[test]
-    fn aliases() {
-        use crate::ir::InstBuilder;
-
-        let mut func = Function::new();
-        {
-            let block0 = func.dfg.make_block();
-            let mut pos = FuncCursor::new(&mut func);
-            pos.insert_block(block0);
-
-            // make some detached values for change_to_alias
-            let v0 = pos.func.dfg.append_block_param(block0, types::I32);
-            let v1 = pos.func.dfg.append_block_param(block0, types::I32);
-            let v2 = pos.func.dfg.append_block_param(block0, types::I32);
-            pos.func.dfg.detach_block_params(block0);
-
-            // alias to a param--will be printed at beginning of block defining param
-            let v3 = pos.func.dfg.append_block_param(block0, types::I32);
-            pos.func.dfg.change_to_alias(v0, v3);
-
-            // alias to an alias--should print attached to alias, not ultimate target
-            pos.func.dfg.make_value_alias_for_serialization(v0, v2); // v0 <- v2
-
-            // alias to a result--will be printed after instruction producing result
-            let _dummy0 = pos.ins().iconst(types::I32, 42);
-            let v4 = pos.ins().iadd(v0, v0);
-            pos.func.dfg.change_to_alias(v1, v4);
-            let _dummy1 = pos.ins().iconst(types::I32, 23);
-            let _v7 = pos.ins().iadd(v1, v1);
-        }
-        assert_eq!(
-            func.to_string(),
-            "function u0:0() fast {\nblock0(v3: i32):\n    v0 -> v3\n    v2 -> v0\n    v4 = iconst.i32 42\n    v5 = iadd v0, v0\n    v1 -> v5\n    v6 = iconst.i32 23\n    v7 = iadd v1, v1\n}\n"
-        );
-    }
-
-    #[test]
-    fn cold_blocks() {
-        let mut func = Function::new();
-        {
-            let mut pos = FuncCursor::new(&mut func);
-
-            let block0 = pos.func.dfg.make_block();
-            pos.insert_block(block0);
-            pos.func.layout.set_cold(block0);
-
-            let block1 = pos.func.dfg.make_block();
-            pos.insert_block(block1);
-            pos.func.dfg.append_block_param(block1, types::I32);
-            pos.func.layout.set_cold(block1);
-        }
-
-        assert_eq!(
-            func.to_string(),
-            "function u0:0() fast {\nblock0 cold:\n\nblock1(v0: i32) cold:\n}\n"
-        );
-    }
-}