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m-ou-sem-ou-se
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Rollup merge of #81753 - tmiasko:inline-instruction-set, r=oli-obk
Never MIR inline functions with a different instruction set
2 parents e8aaa14 + eb5e2d0 commit 728c955

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5 files changed

+152
-1
lines changed

5 files changed

+152
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lines changed

‎compiler/rustc_attr/src/builtin.rs

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@@ -74,7 +74,7 @@ pub enum InlineAttr {
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Never,
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}
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#[derive(Clone, Encodable, Decodable, Debug)]
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#[derive(Clone, Encodable, Decodable, Debug, PartialEq, Eq)]
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pub enum InstructionSetAttr {
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ArmA32,
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ArmT32,

‎compiler/rustc_mir/src/transform/inline.rs

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@@ -281,6 +281,11 @@ impl Inliner<'tcx> {
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return false;
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}
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if self.codegen_fn_attrs.instruction_set != codegen_fn_attrs.instruction_set {
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debug!("`callee has incompatible instruction set - not inlining");
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return false;
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}
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let hinted = match codegen_fn_attrs.inline {
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// Just treat inline(always) as a hint for now,
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// there are cases that prevent inlining that we

‎src/test/mir-opt/inline/inline-instruction-set.rs

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@@ -0,0 +1,54 @@
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// Checks that only functions with the compatible instruction_set attributes are inlined.
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//
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// compile-flags: --target thumbv4t-none-eabi
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// needs-llvm-components: arm
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#![crate_type = "lib"]
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#![feature(rustc_attrs)]
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#![feature(no_core, lang_items)]
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#![feature(isa_attribute)]
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#![no_core]
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#[rustc_builtin_macro]
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#[macro_export]
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macro_rules! asm {
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("assembly template",
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$(operands,)*
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$(options($(option),*))?
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) => {
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/* compiler built-in */
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};
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}
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#[lang = "sized"]
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trait Sized {}
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#[lang = "copy"]
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trait Copy {}
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#[instruction_set(arm::a32)]
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#[inline]
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fn instruction_set_a32() {}
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#[instruction_set(arm::t32)]
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#[inline]
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fn instruction_set_t32() {}
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#[inline]
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fn instruction_set_default() {}
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// EMIT_MIR inline_instruction_set.t32.Inline.diff
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#[instruction_set(arm::t32)]
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pub fn t32() {
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instruction_set_a32();
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instruction_set_t32();
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// The default instruction set is currently
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// conservatively assumed to be incompatible.
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instruction_set_default();
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}
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// EMIT_MIR inline_instruction_set.default.Inline.diff
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pub fn default() {
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instruction_set_a32();
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instruction_set_t32();
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instruction_set_default();
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}

‎src/test/mir-opt/inline/inline_instruction_set.default.Inline.diff

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@@ -0,0 +1,45 @@
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- // MIR for `default` before Inline
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+ // MIR for `default` after Inline
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fn default() -> () {
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let mut _0: (); // return place in scope 0 at $DIR/inline-instruction-set.rs:50:18: 50:18
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let _1: (); // in scope 0 at $DIR/inline-instruction-set.rs:51:5: 51:26
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let _2: (); // in scope 0 at $DIR/inline-instruction-set.rs:52:5: 52:26
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let _3: (); // in scope 0 at $DIR/inline-instruction-set.rs:53:5: 53:30
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+ scope 1 (inlined instruction_set_default) { // at $DIR/inline-instruction-set.rs:53:5: 53:30
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+ }
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bb0: {
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StorageLive(_1); // scope 0 at $DIR/inline-instruction-set.rs:51:5: 51:26
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_1 = instruction_set_a32() -> bb1; // scope 0 at $DIR/inline-instruction-set.rs:51:5: 51:26
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// mir::Constant
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// + span: $DIR/inline-instruction-set.rs:51:5: 51:24
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// + literal: Const { ty: fn() {instruction_set_a32}, val: Value(Scalar(<ZST>)) }
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}
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bb1: {
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StorageDead(_1); // scope 0 at $DIR/inline-instruction-set.rs:51:26: 51:27
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StorageLive(_2); // scope 0 at $DIR/inline-instruction-set.rs:52:5: 52:26
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_2 = instruction_set_t32() -> bb2; // scope 0 at $DIR/inline-instruction-set.rs:52:5: 52:26
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// mir::Constant
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// + span: $DIR/inline-instruction-set.rs:52:5: 52:24
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// + literal: Const { ty: fn() {instruction_set_t32}, val: Value(Scalar(<ZST>)) }
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}
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bb2: {
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StorageDead(_2); // scope 0 at $DIR/inline-instruction-set.rs:52:26: 52:27
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StorageLive(_3); // scope 0 at $DIR/inline-instruction-set.rs:53:5: 53:30
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- _3 = instruction_set_default() -> bb3; // scope 0 at $DIR/inline-instruction-set.rs:53:5: 53:30
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- // mir::Constant
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- // + span: $DIR/inline-instruction-set.rs:53:5: 53:28
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- // + literal: Const { ty: fn() {instruction_set_default}, val: Value(Scalar(<ZST>)) }
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- }
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-
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- bb3: {
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+ _3 = const (); // scope 1 at $DIR/inline-instruction-set.rs:53:5: 53:30
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StorageDead(_3); // scope 0 at $DIR/inline-instruction-set.rs:53:30: 53:31
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_0 = const (); // scope 0 at $DIR/inline-instruction-set.rs:50:18: 54:2
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return; // scope 0 at $DIR/inline-instruction-set.rs:54:2: 54:2
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}
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}
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‎src/test/mir-opt/inline/inline_instruction_set.t32.Inline.diff

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@@ -0,0 +1,47 @@
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- // MIR for `t32` before Inline
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+ // MIR for `t32` after Inline
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fn t32() -> () {
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let mut _0: (); // return place in scope 0 at $DIR/inline-instruction-set.rs:41:14: 41:14
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let _1: (); // in scope 0 at $DIR/inline-instruction-set.rs:42:5: 42:26
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let _2: (); // in scope 0 at $DIR/inline-instruction-set.rs:43:5: 43:26
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let _3: (); // in scope 0 at $DIR/inline-instruction-set.rs:46:5: 46:30
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+ scope 1 (inlined instruction_set_t32) { // at $DIR/inline-instruction-set.rs:43:5: 43:26
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+ }
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bb0: {
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StorageLive(_1); // scope 0 at $DIR/inline-instruction-set.rs:42:5: 42:26
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_1 = instruction_set_a32() -> bb1; // scope 0 at $DIR/inline-instruction-set.rs:42:5: 42:26
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// mir::Constant
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// + span: $DIR/inline-instruction-set.rs:42:5: 42:24
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// + literal: Const { ty: fn() {instruction_set_a32}, val: Value(Scalar(<ZST>)) }
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}
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bb1: {
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StorageDead(_1); // scope 0 at $DIR/inline-instruction-set.rs:42:26: 42:27
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StorageLive(_2); // scope 0 at $DIR/inline-instruction-set.rs:43:5: 43:26
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- _2 = instruction_set_t32() -> bb2; // scope 0 at $DIR/inline-instruction-set.rs:43:5: 43:26
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- // mir::Constant
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- // + span: $DIR/inline-instruction-set.rs:43:5: 43:24
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- // + literal: Const { ty: fn() {instruction_set_t32}, val: Value(Scalar(<ZST>)) }
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- }
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-
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- bb2: {
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+ _2 = const (); // scope 1 at $DIR/inline-instruction-set.rs:43:5: 43:26
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StorageDead(_2); // scope 0 at $DIR/inline-instruction-set.rs:43:26: 43:27
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StorageLive(_3); // scope 0 at $DIR/inline-instruction-set.rs:46:5: 46:30
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- _3 = instruction_set_default() -> bb3; // scope 0 at $DIR/inline-instruction-set.rs:46:5: 46:30
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+ _3 = instruction_set_default() -> bb2; // scope 0 at $DIR/inline-instruction-set.rs:46:5: 46:30
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// mir::Constant
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// + span: $DIR/inline-instruction-set.rs:46:5: 46:28
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// + literal: Const { ty: fn() {instruction_set_default}, val: Value(Scalar(<ZST>)) }
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}
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- bb3: {
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+ bb2: {
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StorageDead(_3); // scope 0 at $DIR/inline-instruction-set.rs:46:30: 46:31
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_0 = const (); // scope 0 at $DIR/inline-instruction-set.rs:41:14: 47:2
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return; // scope 0 at $DIR/inline-instruction-set.rs:47:2: 47:2
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}
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}
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