remove non-functional riscv codepath

Author: RalfJung

src/tools/miri/src/shims/native_lib/trace/parent.rs

@@ -501,18 +501,6 @@ fn handle_segfault(
                         }
                         _ => (),
                     },
-                #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
-                arch::ArchOperand::RiscVOperand(risc_voperand) => {
-                    match risc_voperand {
-                        arch::riscv::RiscVOperand::Mem(_) => {
-                            // We get basically no info here.
-                            let push = addr..addr.strict_add(size);
-                            acc_events.push(AccessEvent::Read(push.clone()));
-                            acc_events.push(AccessEvent::Write(push));
-                        }
-                        _ => (),
-                    }
-                }
                 _ => unimplemented!(),
             }
         }