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psumberapsumbera
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fix sparc64 ABI for aggregates with floating point members
1 parent 6414e0b commit 128ceec

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8 files changed

+272
-58
lines changed

8 files changed

+272
-58
lines changed

‎compiler/rustc_codegen_cranelift/src/abi/pass_mode.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -71,7 +71,7 @@ fn cast_target_to_abi_params(cast: CastTarget) -> SmallVec<[AbiParam; 2]> {
7171
.prefix
7272
.iter()
7373
.flatten()
74-
.map(|&kind| reg_to_abi_param(Reg { kind, size: cast.prefix_chunk_size }))
74+
.map(|&reg| reg_to_abi_param(reg))
7575
.chain((0..rest_count).map(|_| reg_to_abi_param(cast.rest.unit)))
7676
.collect::<SmallVec<_>>();
7777

‎compiler/rustc_codegen_gcc/src/abi.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -48,8 +48,8 @@ impl GccType for CastTarget {
4848
let mut args: Vec<_> = self
4949
.prefix
5050
.iter()
51-
.flat_map(|option_kind| {
52-
option_kind.map(|kind| Reg { kind, size: self.prefix_chunk_size }.gcc_type(cx))
51+
.flat_map(|option_reg| {
52+
option_reg.map(|reg| reg.gcc_type(cx))
5353
})
5454
.chain((0..rest_count).map(|_| rest_gcc_unit))
5555
.collect();

‎compiler/rustc_codegen_llvm/src/abi.rs

Lines changed: 15 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -181,9 +181,7 @@ impl LlvmType for CastTarget {
181181
let mut args: Vec<_> = self
182182
.prefix
183183
.iter()
184-
.flat_map(|option_kind| {
185-
option_kind.map(|kind| Reg { kind, size: self.prefix_chunk_size }.llvm_type(cx))
186-
})
184+
.flat_map(|option_reg| option_reg.map(|reg| reg.llvm_type(cx)))
187185
.chain((0..rest_count).map(|_| rest_ll_unit))
188186
.collect();
189187

@@ -466,6 +464,9 @@ impl<'tcx> FnAbiLlvmExt<'tcx> for FnAbi<'tcx, Ty<'tcx>> {
466464
);
467465
}
468466
}
467+
PassMode::Cast(cast) => {
468+
cast.attrs.apply_attrs_to_llfn(llvm::AttributePlace::ReturnValue, cx, llfn);
469+
}
469470
_ => {}
470471
}
471472
for arg in &self.args {
@@ -497,8 +498,8 @@ impl<'tcx> FnAbiLlvmExt<'tcx> for FnAbi<'tcx, Ty<'tcx>> {
497498
apply(a);
498499
apply(b);
499500
}
500-
PassMode::Cast(_) => {
501-
apply(&ArgAttributes::new());
501+
PassMode::Cast(cast) => {
502+
apply(&cast.attrs);
502503
}
503504
}
504505
}
@@ -533,6 +534,13 @@ impl<'tcx> FnAbiLlvmExt<'tcx> for FnAbi<'tcx, Ty<'tcx>> {
533534
);
534535
}
535536
}
537+
PassMode::Cast(cast) => {
538+
cast.attrs.apply_attrs_to_callsite(
539+
llvm::AttributePlace::ReturnValue,
540+
&bx.cx,
541+
callsite,
542+
);
543+
}
536544
_ => {}
537545
}
538546
if let abi::Abi::Scalar(scalar) = self.ret.layout.abi {
@@ -577,8 +585,8 @@ impl<'tcx> FnAbiLlvmExt<'tcx> for FnAbi<'tcx, Ty<'tcx>> {
577585
apply(bx.cx, a);
578586
apply(bx.cx, b);
579587
}
580-
PassMode::Cast(_) => {
581-
apply(bx.cx, &ArgAttributes::new());
588+
PassMode::Cast(cast) => {
589+
apply(bx.cx, &cast.attrs);
582590
}
583591
}
584592
}

‎compiler/rustc_target/src/abi/call/mips64.rs

Lines changed: 11 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,6 @@
1-
use crate::abi::call::{ArgAbi, ArgExtension, CastTarget, FnAbi, PassMode, Reg, RegKind, Uniform};
1+
use crate::abi::call::{
2+
ArgAbi, ArgAttribute, ArgAttributes, ArgExtension, CastTarget, FnAbi, PassMode, Reg, Uniform,
3+
};
24
use crate::abi::{self, HasDataLayout, Size, TyAbiInterface};
35

46
fn extend_integer_width_mips<Ty>(arg: &mut ArgAbi<'_, Ty>, bits: u64) {
@@ -115,15 +117,15 @@ where
115117
for _ in 0..((offset - last_offset).bits() / 64)
116118
.min((prefix.len() - prefix_index) as u64)
117119
{
118-
prefix[prefix_index] = Some(RegKind::Integer);
120+
prefix[prefix_index] = Some(Reg::i64());
119121
prefix_index += 1;
120122
}
121123

122124
if prefix_index == prefix.len() {
123125
break;
124126
}
125127

126-
prefix[prefix_index] = Some(RegKind::Float);
128+
prefix[prefix_index] = Some(Reg::f64());
127129
prefix_index += 1;
128130
last_offset = offset + Reg::f64().size;
129131
}
@@ -137,8 +139,13 @@ where
137139
let rest_size = size - Size::from_bytes(8) * prefix_index as u64;
138140
arg.cast_to(CastTarget {
139141
prefix,
140-
prefix_chunk_size: Size::from_bytes(8),
141142
rest: Uniform { unit: Reg::i64(), total: rest_size },
143+
attrs: ArgAttributes {
144+
regular: ArgAttribute::default(),
145+
arg_ext: ArgExtension::None,
146+
pointee_size: Size::ZERO,
147+
pointee_align: None,
148+
},
142149
});
143150
}
144151

‎compiler/rustc_target/src/abi/call/mod.rs

Lines changed: 29 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -214,9 +214,9 @@ impl Uniform {
214214

215215
#[derive(Clone, Copy, PartialEq, Eq, Hash, Debug, HashStable_Generic)]
216216
pub struct CastTarget {
217-
pub prefix: [Option<RegKind>; 8],
218-
pub prefix_chunk_size: Size,
217+
pub prefix: [Option<Reg>; 8],
219218
pub rest: Uniform,
219+
pub attrs: ArgAttributes,
220220
}
221221

222222
impl From<Reg> for CastTarget {
@@ -227,29 +227,48 @@ impl From<Reg> for CastTarget {
227227

228228
impl From<Uniform> for CastTarget {
229229
fn from(uniform: Uniform) -> CastTarget {
230-
CastTarget { prefix: [None; 8], prefix_chunk_size: Size::ZERO, rest: uniform }
230+
CastTarget {
231+
prefix: [None; 8],
232+
rest: uniform,
233+
attrs: ArgAttributes {
234+
regular: ArgAttribute::default(),
235+
arg_ext: ArgExtension::None,
236+
pointee_size: Size::ZERO,
237+
pointee_align: None,
238+
},
239+
}
231240
}
232241
}
233242

234243
impl CastTarget {
235244
pub fn pair(a: Reg, b: Reg) -> CastTarget {
236245
CastTarget {
237-
prefix: [Some(a.kind), None, None, None, None, None, None, None],
238-
prefix_chunk_size: a.size,
246+
prefix: [Some(a), None, None, None, None, None, None, None],
239247
rest: Uniform::from(b),
248+
attrs: ArgAttributes {
249+
regular: ArgAttribute::default(),
250+
arg_ext: ArgExtension::None,
251+
pointee_size: Size::ZERO,
252+
pointee_align: None,
253+
},
240254
}
241255
}
242256

243-
pub fn size<C: HasDataLayout>(&self, cx: &C) -> Size {
244-
(self.prefix_chunk_size * self.prefix.iter().filter(|x| x.is_some()).count() as u64)
245-
.align_to(self.rest.align(cx))
246-
+ self.rest.total
257+
pub fn size<C: HasDataLayout>(&self, _cx: &C) -> Size {
258+
let mut size = self.rest.total;
259+
for i in 0..self.prefix.iter().count() {
260+
match self.prefix[i] {
261+
Some(v) => size += Size { raw: v.size.bytes() },
262+
None => {}
263+
}
264+
}
265+
return size;
247266
}
248267

249268
pub fn align<C: HasDataLayout>(&self, cx: &C) -> Align {
250269
self.prefix
251270
.iter()
252-
.filter_map(|x| x.map(|kind| Reg { kind, size: self.prefix_chunk_size }.align(cx)))
271+
.filter_map(|x| x.map(|reg| reg.align(cx)))
253272
.fold(cx.data_layout().aggregate_align.abi.max(self.rest.align(cx)), |acc, align| {
254273
acc.max(align)
255274
})

‎compiler/rustc_target/src/abi/call/sparc64.rs

Lines changed: 93 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,9 @@
11
// FIXME: This needs an audit for correctness and completeness.
22

3-
use crate::abi::call::{ArgAbi, FnAbi, Reg, RegKind, Uniform};
4-
use crate::abi::{HasDataLayout, TyAbiInterface};
3+
use crate::abi::call::{
4+
ArgAbi, ArgAttribute, ArgAttributes, ArgExtension, CastTarget, FnAbi, Reg, RegKind, Uniform,
5+
};
6+
use crate::abi::{self, HasDataLayout, Size, TyAbiInterface};
57

68
fn is_homogeneous_aggregate<'a, Ty, C>(cx: &C, arg: &mut ArgAbi<'a, Ty>) -> Option<Uniform>
79
where
@@ -16,41 +18,15 @@ where
1618

1719
let valid_unit = match unit.kind {
1820
RegKind::Integer => false,
19-
RegKind::Float => true,
21+
RegKind::Float => false,
2022
RegKind::Vector => arg.layout.size.bits() == 128,
2123
};
2224

2325
valid_unit.then_some(Uniform { unit, total: arg.layout.size })
2426
})
2527
}
2628

27-
fn classify_ret<'a, Ty, C>(cx: &C, ret: &mut ArgAbi<'a, Ty>)
28-
where
29-
Ty: TyAbiInterface<'a, C> + Copy,
30-
C: HasDataLayout,
31-
{
32-
if !ret.layout.is_aggregate() {
33-
ret.extend_integer_width_to(64);
34-
return;
35-
}
36-
37-
if let Some(uniform) = is_homogeneous_aggregate(cx, ret) {
38-
ret.cast_to(uniform);
39-
return;
40-
}
41-
let size = ret.layout.size;
42-
let bits = size.bits();
43-
if bits <= 256 {
44-
let unit = Reg::i64();
45-
ret.cast_to(Uniform { unit, total: size });
46-
return;
47-
}
48-
49-
// don't return aggregates in registers
50-
ret.make_indirect();
51-
}
52-
53-
fn classify_arg<'a, Ty, C>(cx: &C, arg: &mut ArgAbi<'a, Ty>)
29+
fn classify_arg<'a, Ty, C>(cx: &C, arg: &mut ArgAbi<'a, Ty>, in_registers_max: Size)
5430
where
5531
Ty: TyAbiInterface<'a, C> + Copy,
5632
C: HasDataLayout,
@@ -60,13 +36,97 @@ where
6036
return;
6137
}
6238

39+
// This doesn't intentionally handle structures with floats which needs
40+
// special care below.
6341
if let Some(uniform) = is_homogeneous_aggregate(cx, arg) {
6442
arg.cast_to(uniform);
6543
return;
6644
}
6745

46+
if let abi::FieldsShape::Arbitrary { .. } = arg.layout.fields {
47+
let dl = cx.data_layout();
48+
let size = arg.layout.size;
49+
let mut prefix = [None; 8];
50+
let mut prefix_index = 0;
51+
let mut last_offset = Size::ZERO;
52+
let mut has_float = false;
53+
let mut arg_attribute = ArgAttribute::default();
54+
55+
for i in 0..arg.layout.fields.count() {
56+
let field = arg.layout.field(cx, i);
57+
let offset = arg.layout.fields.offset(i);
58+
59+
if let abi::Abi::Scalar(scalar) = &field.abi {
60+
if scalar.value == abi::F32 || scalar.value == abi::F64 {
61+
has_float = true;
62+
63+
if !last_offset.is_aligned(dl.f64_align.abi) && last_offset < offset {
64+
if prefix_index == prefix.len() {
65+
break;
66+
}
67+
prefix[prefix_index] = Some(Reg::i32());
68+
prefix_index += 1;
69+
last_offset = last_offset + Reg::i32().size;
70+
}
71+
72+
for _ in 0..((offset - last_offset).bits() / 64)
73+
.min((prefix.len() - prefix_index) as u64)
74+
{
75+
prefix[prefix_index] = Some(Reg::i64());
76+
prefix_index += 1;
77+
last_offset = last_offset + Reg::i64().size;
78+
}
79+
80+
if last_offset < offset {
81+
if prefix_index == prefix.len() {
82+
break;
83+
}
84+
prefix[prefix_index] = Some(Reg::i32());
85+
prefix_index += 1;
86+
last_offset = last_offset + Reg::i32().size;
87+
}
88+
89+
if prefix_index == prefix.len() {
90+
break;
91+
}
92+
93+
if scalar.value == abi::F32 {
94+
arg_attribute = ArgAttribute::InReg;
95+
prefix[prefix_index] = Some(Reg::f32());
96+
last_offset = offset + Reg::f32().size;
97+
} else {
98+
prefix[prefix_index] = Some(Reg::f64());
99+
last_offset = offset + Reg::f64().size;
100+
}
101+
prefix_index += 1;
102+
}
103+
}
104+
}
105+
106+
if has_float && arg.layout.size <= in_registers_max {
107+
let mut rest_size = size - last_offset;
108+
109+
if (rest_size.raw % 8) != 0 && prefix_index < prefix.len() {
110+
prefix[prefix_index] = Some(Reg::i32());
111+
rest_size = rest_size - Reg::i32().size;
112+
}
113+
114+
arg.cast_to(CastTarget {
115+
prefix,
116+
rest: Uniform { unit: Reg::i64(), total: rest_size },
117+
attrs: ArgAttributes {
118+
regular: arg_attribute,
119+
arg_ext: ArgExtension::None,
120+
pointee_size: Size::ZERO,
121+
pointee_align: None,
122+
},
123+
});
124+
return;
125+
}
126+
}
127+
68128
let total = arg.layout.size;
69-
if total.bits() > 128 {
129+
if total > in_registers_max {
70130
arg.make_indirect();
71131
return;
72132
}
@@ -80,13 +140,13 @@ where
80140
C: HasDataLayout,
81141
{
82142
if !fn_abi.ret.is_ignore() {
83-
classify_ret(cx, &mut fn_abi.ret);
143+
classify_arg(cx, &mut fn_abi.ret, Size { raw: 32 });
84144
}
85145

86146
for arg in &mut fn_abi.args {
87147
if arg.is_ignore() {
88148
continue;
89149
}
90-
classify_arg(cx, arg);
150+
classify_arg(cx, arg, Size { raw: 16 });
91151
}
92152
}

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