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Promote tier 3 riscv32 ESP-IDF targets to tier 2 #864
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Important This issue is not meant to be used for technical discussion. There is a Zulip stream for that. Concerns or objections can formally be registered here by adding a comment.
Concerns can be lifted with:
See documentation at https://forge.rust-lang.org |
@rfcbot concern ask-libs-consensus-on-limited-std-support We should ask lib team consensus on promoting RISC-V 32bit ESP-IDF targets,
EDIT: library team nomination at rust-lang/rust#140042. |
@rfcbot concern fd-duplication The idea that an OwnedFd can be duplicated is fundamental in several Unix-like file handling algorithms and Rust in general (BorrowedFd as ToOwned). It's the exact kind of stdlib blind spot we're trying to prevent. Upstream issue: espressif/esp-idf#7412 |
Would you elaborate on those fundamental Unix-like file handling algorithms?
If you mean Am I missing something? My point of view is that (a) cloning file handles with |
Proposal
I would like to propose promoting the RISC-V 32bit ESP-IDF targets,
riscv32imc-esp-espidf
,riscv32imac-esp-espidf
, &riscv32imafc-esp-espidf
to tier 2.Tier 2 target requirements
In general, RISC-V is an open specification, used and accessible to anyone, including individuals.
The
*-espidf
targets are specific for the Espressif line of MCUs and their ESP-IDF operating system (which is largely POSIX compatible).With that said, the ESP IDF is:
Open source
Having a high popularity (the “de facto” SDK for developing C-based firmware on top of the Espressif MCUs)
…so we believe it is not the case at all that it is used by a closed group.
@MabezDev, @ivmarkov, and I (@SergioGasquez) will maintain the targets.
I don't foresee this being an issue.
The maintainers will ensure we avoid undue burden for the general Rust community.
There is a QEMU fork of Espressif that supports ESP32-C3. Also there is an experimental feature for running ESP-IDF applications on Linux, which is available for all the RISC-V targets, Wokwi simulation could also be an option as its supports all the targets.
We already have some documentation, see *-espidf chapter of the The rustc book
The
riscv32XXX-esp-espidf
targets are indeed very similar to their bare-metal counterparts (riscv32XXX-unknown-core-elf
). Where they do differ (but this is key) is in having the following additional properties set on the-espidf
targets:This allows the STD code to branch where necessary for these targets, as done by all others that do support the Rust Standard Library.
core
,alloc
, andpanic_abort
are fully implemented.std
is fully implemented as well, except for support for processes and signals, which are stubbed out.We do understand that not implementing processes (and therefore signals) is a bit controversial, but with that said, an MCU target cannot feasibly implement those, as often there is just no notion of “multiple processes” there (as is the case with ESP-IDF).
So we do believe we cannot possibly support processes and signals indeed, and thus we fall in the same category as other Tier 2 targets, like wasm, where neither processes, nor even other core aspects of the Standard Library, like multi-threading, BSD sockets, or even mutexes are implemented.
RISC-V is a well-established and well-maintained LLVM backend. To the best of my knowledge, the backend won't cause the generated code to have undefined behavior.
The C calling convention is supported.
This should not be a problem at all. The only dependency the
*-espidf
targets need is onlibc
which is already a listed dependency in the Standard Library and which does support ESP-IDF.There is no need for any native libraries to be present in the CI, and as such building the Standard Library for ESP-IDF only requires the Rust compiler and nothing else.
The targets will not build host tools. With that said:
To the best of my knowledge, this will not induce a burden on the current CI infra.
Cross-compilation is supported and documented in the platform support document. In fact, cross-compilation is the only way to build for these targets.
There are no additional license issues to worry about.
Agree.
Agree.
They apply, they currently are tier 3 targets.
Tier 2 with host tools
Given that the target runs on MCUs, it will not have any host tools.
Mentors or Reviewers
We asked @davidtwco and @Amanieu, but no response from their side yet. Anyone is welcome, but they do have some context already.
Process
The main points of the Major Change Process are as follows:
@rustbot second
.-C flag
, then full team check-off is required.@rfcbot fcp merge
on either the MCP or the PR.You can read more about Major Change Proposals on forge.
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