Skip to content

Add base_isa setting for RISC-V #941

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Jun 27, 2025
Merged

Conversation

romancardenas
Copy link
Contributor

Currently, riscv-rt macros use environment variables to capture characteristics of the target (e.g., RV64 vs RV32, vector table alignment...). While riscv-rt properly sets a few environment variables in itsbuild.rs script for its internals, these environment variables do not outlive the compilation of other crates (e.g., PACs). Thus, PACs, as users of riscv-rt macros, must also define the RISCV_RT_BASE_ISA environment variable to make sure that the generated code supports vectored mode.

This PR includes this field in the settings.yaml file. As ignoring this field may lead to programs hanging, I also included warning messages to recommend that PAC maintainers include this field if their target supports vectored mode.

@romancardenas romancardenas requested a review from a team as a code owner June 26, 2025 18:27
@burrbull
Copy link
Member

Fix errors, please.

@burrbull burrbull added this pull request to the merge queue Jun 27, 2025
Merged via the queue into rust-embedded:master with commit 23464b3 Jun 27, 2025
59 checks passed
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

2 participants