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Merge pull request #150 from rust-embedded/remove-fcsr
Transition to cargo workspace
2 parents 4ab67d6 + c92affa commit 8071b55

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‎.github/workflows/changelog.yaml

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name: Check CHANGELOG.md
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name: Changelog check
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on:
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merge_group:
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- name: Checkout code
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uses: actions/checkout@v4
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- name: Check for CHANGELOG.md
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- name: Check which component is modified
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uses: dorny/paths-filter@v2
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id: changes
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with:
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filters: |
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riscv:
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- 'riscv/**'
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- name: Check for CHANGELOG.md (riscv)
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if: steps.changes.outputs.riscv == 'true'
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uses: dangoslen/changelog-enforcer@v3
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with:
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changeLogPath: ./riscv/CHANGELOG.md
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skipLabels: 'skip changelog'
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missingUpdateErrorMessage: 'Please add a changelog entry in the CHANGELOG.md file.'
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missingUpdateErrorMessage: 'Please add a changelog entry in the riscv/CHANGELOG.md file.'

‎Cargo.toml

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[package]
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name = "riscv"
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version = "0.10.1"
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edition = "2021"
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rust-version = "1.59"
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repository = "https://github.com/rust-embedded/riscv"
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authors = ["The RISC-V Team <[email protected]>"]
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categories = ["embedded", "hardware-support", "no-std"]
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description = "Low level access to RISC-V processors"
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keywords = ["riscv", "register", "peripheral"]
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license = "ISC"
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[package.metadata.docs.rs]
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all-features = true
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default-target = "riscv64imac-unknown-none-elf"
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targets = [
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"riscv32i-unknown-none-elf", "riscv32imc-unknown-none-elf", "riscv32imac-unknown-none-elf",
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"riscv64imac-unknown-none-elf", "riscv64gc-unknown-none-elf",
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[workspace]
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resolver = "2"
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members = [
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"riscv",
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]
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[features]
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critical-section-single-hart = ["critical-section/restore-state-bool"]
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[dependencies]
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critical-section = "1.1.2"
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embedded-hal = "1.0.0-rc.1"

‎CHANGELOG.md renamed to ‎riscv/CHANGELOG.md

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‎riscv/Cargo.toml

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[package]
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name = "riscv"
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version = "0.10.1"
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edition = "2021"
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rust-version = "1.59"
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repository = "https://github.com/rust-embedded/riscv"
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authors = ["The RISC-V Team <[email protected]>"]
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categories = ["embedded", "hardware-support", "no-std"]
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description = "Low level access to RISC-V processors"
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keywords = ["riscv", "register", "peripheral"]
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license = "ISC"
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[package.metadata.docs.rs]
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all-features = true
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default-target = "riscv64imac-unknown-none-elf"
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targets = [
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"riscv32i-unknown-none-elf", "riscv32imc-unknown-none-elf", "riscv32imac-unknown-none-elf",
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"riscv64imac-unknown-none-elf", "riscv64gc-unknown-none-elf",
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]
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[features]
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critical-section-single-hart = ["critical-section/restore-state-bool"]
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[dependencies]
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critical-section = "1.1.2"
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embedded-hal = "1.0.0-rc.1"

‎build.rs renamed to ‎riscv/build.rs

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‎src/asm.rs renamed to ‎riscv/src/asm.rs

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‎src/critical_section.rs renamed to ‎riscv/src/critical_section.rs

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‎src/delay.rs renamed to ‎riscv/src/delay.rs

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‎src/interrupt.rs renamed to ‎riscv/src/interrupt.rs

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‎src/lib.rs renamed to ‎riscv/src/lib.rs

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‎src/macros.rs renamed to ‎riscv/src/macros.rs

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‎src/register.rs renamed to ‎riscv/src/register.rs

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‎src/register/cycle.rs renamed to ‎riscv/src/register/cycle.rs

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‎src/register/cycleh.rs renamed to ‎riscv/src/register/cycleh.rs

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‎src/register/hpmcounterx.rs renamed to ‎riscv/src/register/hpmcounterx.rs

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‎src/register/instret.rs renamed to ‎riscv/src/register/instret.rs

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‎src/register/instreth.rs renamed to ‎riscv/src/register/instreth.rs

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‎src/register/macros.rs renamed to ‎riscv/src/register/macros.rs

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‎src/register/marchid.rs renamed to ‎riscv/src/register/marchid.rs

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‎src/register/mcause.rs renamed to ‎riscv/src/register/mcause.rs

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‎src/register/mcounteren.rs renamed to ‎riscv/src/register/mcounteren.rs

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‎src/register/mcycle.rs renamed to ‎riscv/src/register/mcycle.rs

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‎src/register/mcycleh.rs renamed to ‎riscv/src/register/mcycleh.rs

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‎src/register/medeleg.rs renamed to ‎riscv/src/register/medeleg.rs

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‎src/register/mepc.rs renamed to ‎riscv/src/register/mepc.rs

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‎src/register/mhartid.rs renamed to ‎riscv/src/register/mhartid.rs

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‎src/register/mhpmcounterx.rs renamed to ‎riscv/src/register/mhpmcounterx.rs

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‎src/register/mhpmeventx.rs renamed to ‎riscv/src/register/mhpmeventx.rs

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‎src/register/mideleg.rs renamed to ‎riscv/src/register/mideleg.rs

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‎src/register/mie.rs renamed to ‎riscv/src/register/mie.rs

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‎src/register/mimpid.rs renamed to ‎riscv/src/register/mimpid.rs

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‎src/register/minstret.rs renamed to ‎riscv/src/register/minstret.rs

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‎src/register/minstreth.rs renamed to ‎riscv/src/register/minstreth.rs

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‎src/register/mip.rs renamed to ‎riscv/src/register/mip.rs

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‎src/register/misa.rs renamed to ‎riscv/src/register/misa.rs

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‎src/register/mscratch.rs renamed to ‎riscv/src/register/mscratch.rs

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‎src/register/mstatus.rs renamed to ‎riscv/src/register/mstatus.rs

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‎src/register/mstatush.rs renamed to ‎riscv/src/register/mstatush.rs

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‎src/register/mtval.rs renamed to ‎riscv/src/register/mtval.rs

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‎src/register/mtvec.rs renamed to ‎riscv/src/register/mtvec.rs

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‎src/register/mvendorid.rs renamed to ‎riscv/src/register/mvendorid.rs

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‎src/register/pmpaddrx.rs renamed to ‎riscv/src/register/pmpaddrx.rs

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‎src/register/pmpcfgx.rs renamed to ‎riscv/src/register/pmpcfgx.rs

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‎src/register/satp.rs renamed to ‎riscv/src/register/satp.rs

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‎src/register/scause.rs renamed to ‎riscv/src/register/scause.rs

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‎src/register/scounteren.rs renamed to ‎riscv/src/register/scounteren.rs

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‎src/register/sepc.rs renamed to ‎riscv/src/register/sepc.rs

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‎src/register/sie.rs renamed to ‎riscv/src/register/sie.rs

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‎src/register/sip.rs renamed to ‎riscv/src/register/sip.rs

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‎src/register/sscratch.rs renamed to ‎riscv/src/register/sscratch.rs

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‎src/register/sstatus.rs renamed to ‎riscv/src/register/sstatus.rs

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‎src/register/stval.rs renamed to ‎riscv/src/register/stval.rs

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‎src/register/stvec.rs renamed to ‎riscv/src/register/stvec.rs

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‎src/register/time.rs renamed to ‎riscv/src/register/time.rs

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‎src/register/timeh.rs renamed to ‎riscv/src/register/timeh.rs

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