rust-embedded
diff --git a/‎riscv-rt/asm.S
+2-4 b/‎riscv-rt/asm.S
+2-4
diff --git a/‎riscv-rt/bin/riscv32i-unknown-none-elf.a
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diff --git a/‎riscv-rt/bin/riscv32ic-unknown-none-elf.a
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diff --git a/‎riscv-rt/bin/riscv32if-unknown-none-elf.a
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diff --git a/‎riscv-rt/bin/riscv32ifc-unknown-none-elf.a
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diff --git a/‎riscv-rt/bin/riscv32ifd-unknown-none-elf.a
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diff --git a/‎riscv-rt/bin/riscv32ifdc-unknown-none-elf.a
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diff --git a/‎riscv-rt/bin/riscv32im-unknown-none-elf.a
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diff --git a/‎riscv-rt/bin/riscv32imc-unknown-none-elf.a
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diff --git a/‎riscv-rt/bin/riscv32imf-unknown-none-elf.a
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diff --git a/‎riscv-rt/bin/riscv32imfc-unknown-none-elf.a
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diff --git a/‎riscv-rt/bin/riscv32imfd-unknown-none-elf.a
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diff --git a/‎riscv-rt/bin/riscv32imfdc-unknown-none-elf.a
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diff --git a/‎riscv-rt/bin/riscv64i-unknown-none-elf.a
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diff --git a/‎riscv-rt/bin/riscv64ic-unknown-none-elf.a
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diff --git a/‎riscv-rt/bin/riscv64if-unknown-none-elf.a
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diff --git a/‎riscv-rt/bin/riscv64ifc-unknown-none-elf.a
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diff --git a/‎riscv-rt/bin/riscv64ifd-unknown-none-elf.a
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diff --git a/‎riscv-rt/bin/riscv64ifdc-unknown-none-elf.a
32 Bytes b/‎riscv-rt/bin/riscv64ifdc-unknown-none-elf.a
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diff --git a/‎riscv-rt/bin/riscv64im-unknown-none-elf.a
40 Bytes b/‎riscv-rt/bin/riscv64im-unknown-none-elf.a
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diff --git a/‎riscv-rt/bin/riscv64imc-unknown-none-elf.a
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diff --git a/‎riscv-rt/bin/riscv64imf-unknown-none-elf.a
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diff --git a/‎riscv-rt/bin/riscv64imfc-unknown-none-elf.a
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diff --git a/‎riscv-rt/bin/riscv64imfd-unknown-none-elf.a
40 Bytes b/‎riscv-rt/bin/riscv64imfd-unknown-none-elf.a
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diff --git a/‎riscv-rt/bin/riscv64imfdc-unknown-none-elf.a
32 Bytes b/‎riscv-rt/bin/riscv64imfdc-unknown-none-elf.a
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diff --git a/‎riscv-rt/link.x
+6 b/‎riscv-rt/link.x
+6
diff --git a/‎riscv-rt/src/lib.rs
+3-2 b/‎riscv-rt/src/lib.rs
+3-2
@@ -124,11 +124,9 @@ _abs_start:
     restores caller saved registers and then returns.
 */
 .section .trap, "ax"
-.global _start_trap
-/* Make it .weak so PAC/HAL can provide their own if needed. */
-.weak _start_trap
+.global default_start_trap
 
-_start_trap:
+default_start_trap:
     addi sp, sp, -16*REGBYTES
 
     STORE ra, 0*REGBYTES(sp)
 
@@ -34,6 +34,12 @@ PROVIDE(_setup_interrupts = default_setup_interrupts);
 */
 PROVIDE(_mp_hook = default_mp_hook);
 
+/* # Start trap function override
+  By default uses the riscv crates default trap handler
+  but by providing the `_start_trap` symbol external crates can override.
+*/
+PROVIDE(_start_trap = default_start_trap);
+
 SECTIONS
 {
   .text.dummy (NOLOAD) :
 
@@ -392,6 +392,7 @@ pub unsafe extern "C" fn start_rust() -> ! {
 /// Registers saved in trap handler
 #[allow(missing_docs)]
 #[repr(C)]
+#[derive(Debug)]
 pub struct TrapFrame {
     pub ra: usize,
     pub t0: usize,
@@ -496,8 +497,8 @@ extern "C" {
 
 #[doc(hidden)]
 pub union Vector {
-    handler: unsafe extern "C" fn(),
-    reserved: usize,
+    pub handler: unsafe extern "C" fn(),
+    pub reserved: usize,
 }
 
 #[doc(hidden)]