Merge #249

249: More v0.6.3 backports r=jonas-schievink a=adamgreig

I think this includes the remainder of the non-breaking changes since v0.6.2, with a couple of exceptions:

* #240 seemed low-impact but had loads of separate commits to cherry-pick
* #220 is I think non-breaking but was quite a substantial change, perhaps I could still include it

~~I did include #226 which adds a new field to `Peripherals`, but as I understand it that should be a non-breaking change since it's non-exhaustive.~~

I've updated the CHANGELOG with all the changes from this PR and the previous #248.

Co-authored-by: Cliff L. Biffle <[email protected]>
Co-authored-by: Peter Taylor <[email protected]>
Co-authored-by: Hugues de Valon <[email protected]>
Co-authored-by: Jonas Schievink <[email protected]>
Co-authored-by: Adam Greig <[email protected]>

Author: 6 people

CHANGELOG.md

@@ -7,6 +7,23 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+## [v0.6.3] - 2020-07-20
+
+### Added
+
+- Initial Cortex-M Security Extension support for armv8m
+- `UDF` intrinsic
+- Methods to enable/disable exceptions in SCB
+
+### Fixed
+
+- Fix bug in `asm::delay` not updating status clobber flags
+- Swapped to `llvm_asm!` to support inline assembly on new nightlies
+- Our precompiled assembly routines have additional debug information
+- ITM `is_fifo_ready` improved to support armv8
+- Cache enabling moved to pre-built assembly routines to prevent possible
+  undefined behaviour
+
 ## [v0.6.2] - 2020-01-12
 
 ### Added
@@ -572,7 +589,8 @@ fn main() {
 - Functions to get the vector table
 - Wrappers over miscellaneous instructions like `bkpt`
 
-[Unreleased]: https://github.com/rust-embedded/cortex-m/compare/v0.6.2...HEAD
+[Unreleased]: https://github.com/rust-embedded/cortex-m/compare/v0.6.3...HEAD
+[v0.6.3]: https://github.com/rust-embedded/cortex-m/compare/v0.6.2...v0.6.3
 [v0.6.2]: https://github.com/rust-embedded/cortex-m/compare/v0.6.1...v0.6.2
 [v0.6.1]: https://github.com/rust-embedded/cortex-m/compare/v0.6.0...v0.6.1
 [v0.6.0]: https://github.com/rust-embedded/cortex-m/compare/v0.5.8...v0.6.0

asm-v7.s

@@ -1,3 +1,4 @@
+  .syntax unified
   .cfi_sections .debug_frame
 
   .section .text.__basepri_max
@@ -39,3 +40,39 @@ __faultmask:
   bx lr
   .cfi_endproc
   .size __faultmask, . - __faultmask
+
+  .section .text.__enable_icache
+  .global __enable_icache
+  .thumb_func
+  .cfi_startproc
+__enable_icache:
+  ldr r0, =0xE000ED14       @ CCR
+  mrs r2, PRIMASK           @ save critical nesting info
+  cpsid i                   @ mask interrupts
+  ldr r1, [r0]              @ read CCR
+  orr.w r1, r1, #(1 << 17)  @ Set bit 17, IC
+  str r1, [r0]              @ write it back
+  dsb                       @ ensure store completes
+  isb                       @ synchronize pipeline
+  msr PRIMASK, r2           @ unnest critical section
+  bx lr
+  .cfi_endproc
+  .size __enable_icache, . - __enable_icache
+
+  .section .text.__enable_dcache
+  .global __enable_dcache
+  .thumb_func
+  .cfi_startproc
+__enable_dcache:
+  ldr r0, =0xE000ED14       @ CCR
+  mrs r2, PRIMASK           @ save critical nesting info
+  cpsid i                   @ mask interrupts
+  ldr r1, [r0]              @ read CCR
+  orr.w r1, r1, #(1 << 16)  @ Set bit 16, DC
+  str r1, [r0]              @ write it back
+  dsb                       @ ensure store completes
+  isb                       @ synchronize pipeline
+  msr PRIMASK, r2           @ unnest critical section
+  bx lr
+  .cfi_endproc
+  .size __enable_dcache, . - __enable_dcache

bin/thumbv6m-none-eabi.a

@@ -6,7 +6,7 @@ fn main() {
     let out_dir = PathBuf::from(env::var("OUT_DIR").unwrap());
     let name = env::var("CARGO_PKG_NAME").unwrap();
 
-    if target.starts_with("thumb") && env::var_os("CARGO_FEATURE_INLINE_ASM").is_none() {
+    if target.starts_with("thumb") {
         fs::copy(
             format!("bin/{}.a", target),
             out_dir.join(format!("lib{}.a", name)),