diff --git a/cortex-ar/CHANGELOG.md b/cortex-ar/CHANGELOG.md
index 48076ba..617bca0 100644
--- a/cortex-ar/CHANGELOG.md
+++ b/cortex-ar/CHANGELOG.md
@@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+### Added
+
+- `dmb` data memory barrier in ASM module.
+
 ## [v0.2.0]
 
 ### Added
diff --git a/cortex-ar/src/asm.rs b/cortex-ar/src/asm.rs
index 2695b41..9a50644 100644
--- a/cortex-ar/src/asm.rs
+++ b/cortex-ar/src/asm.rs
@@ -2,6 +2,20 @@
 
 use core::sync::atomic::{compiler_fence, Ordering};
 
+/// Data Memory Barrier
+///
+/// Ensures that all explicit memory accesses that appear in program order before the `DMB`
+/// instruction are observed before any explicit memory accesses that appear in program order
+/// after the `DMB` instruction.
+#[inline]
+pub fn dmb() {
+    compiler_fence(Ordering::SeqCst);
+    unsafe {
+        core::arch::asm!("dmb", options(nostack, preserves_flags));
+    }
+    compiler_fence(Ordering::SeqCst);
+}
+
 /// Data Synchronization Barrier
 ///
 /// Acts as a special kind of memory barrier. No instruction in program order after this instruction