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dtwooddtwood
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Change some stuff
1 parent 9546379 commit 282ea0c

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3 files changed

+117
-108
lines changed

3 files changed

+117
-108
lines changed

‎tm4c129x-hal/Cargo.toml‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@ repository = "https://github.com/thejpster/tm4c-hal/tm4c129x-hal"
1515
edition = "2018"
1616

1717
[dependencies]
18-
bare-metal = "*"
18+
bare-metal = "0.2.4"
1919
cortex-m = "0.5"
2020
nb = "0.1"
2121
tm4c129x = "0.7"
@@ -33,7 +33,7 @@ version = "0.2"
3333
features = ["unproven"]
3434

3535
[dependencies.smoltcp]
36-
git = "https://github.com/m-labs/smoltcp"
36+
version = "0.5.0"
3737
default_features = false
3838
features = [
3939
"proto-ipv4",
@@ -51,7 +51,7 @@ version = "1.0"
5151
default-features = false
5252

5353
[dependencies.vcell]
54-
version = "*"
54+
version = "0.1.0"
5555
features = ["const-fn"]
5656

5757
[features]

‎tm4c129x-hal/src/edes_old.rs‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,5 @@
1+
#![allow(dead_code)]
2+
13
pub const DES0_TX_CTRL_OWN: u32 = 2147483648;
24
pub const DES0_TX_CTRL_INTERRUPT: u32 = 1073741824;
35
pub const DES0_TX_CTRL_LAST_SEG: u32 = 536870912;

‎tm4c129x-hal/src/ethernet.rs‎

Lines changed: 112 additions & 105 deletions
Original file line numberDiff line numberDiff line change
@@ -62,9 +62,9 @@ impl EphyReg {
6262
}
6363
}
6464

65-
const NUM_TX_DESCRIPTORS: usize = 10;
65+
const NUM_TX_DESCRIPTORS: usize = 1;
6666
const NUM_RX_DESCRIPTORS: usize = 10;
67-
static RX_DESCRIPTORS: [RDES; NUM_TX_DESCRIPTORS] = [
67+
static RX_DESCRIPTORS: [RDES; NUM_RX_DESCRIPTORS] = [
6868
RDES::new(),
6969
RDES::new(),
7070
RDES::new(),
@@ -76,22 +76,14 @@ static RX_DESCRIPTORS: [RDES; NUM_TX_DESCRIPTORS] = [
7676
RDES::new(),
7777
RDES::new(),
7878
];
79-
static TX_DESCRIPTORS: [TDES; NUM_RX_DESCRIPTORS] = [
80-
TDES::new(),
81-
TDES::new(),
82-
TDES::new(),
83-
TDES::new(),
84-
TDES::new(),
85-
TDES::new(),
86-
TDES::new(),
87-
TDES::new(),
88-
TDES::new(),
89-
TDES::new(),
90-
];
79+
static TX_DESCRIPTORS: [TDES; NUM_TX_DESCRIPTORS] = [TDES::new()];
9180

9281
const RX_BUFFER_SIZE: usize = 1536;
9382
static mut RX_BUFFERS: [[u8; RX_BUFFER_SIZE]; NUM_RX_DESCRIPTORS] =
9483
[[0; RX_BUFFER_SIZE]; NUM_RX_DESCRIPTORS];
84+
const TX_BUFFER_SIZE: usize = RX_BUFFER_SIZE;
85+
static mut TX_BUFFERS: [[u8; TX_BUFFER_SIZE]; NUM_TX_DESCRIPTORS] =
86+
[[0; TX_BUFFER_SIZE]; NUM_TX_DESCRIPTORS];
9587

9688
fn emac_reset(emac0: &EMAC0) {
9789
emac0.dmabusmod.modify(|_, w| w.swr().set_bit());
@@ -137,37 +129,24 @@ fn emac_phy_config_set(
137129

138130
fn emac_init(
139131
emac0: &EMAC0,
140-
_sysclk: u32,
132+
sysclk: u32,
141133
mut rx_burst: u32,
142134
mut tx_burst: u32,
143135
desc_skip_size: u32,
144136
) {
145-
// uint32_t ui32Val, ui32Div;
146-
147-
// //
148-
// // Parameter sanity checks.
149-
// //
150-
// ASSERT(ui32DescSkipSize < 32);
137+
// Parameter sanity checks.
151138
assert!(desc_skip_size < 32);
152-
// ASSERT(ui32TxBurst < (32 * 8));
153139
assert!(tx_burst < 32 * 8);
154-
// ASSERT(ui32RxBurst < (32 * 8));
155140
assert!(rx_burst < 32 * 8);
156141

157-
// //
158-
// // Make sure that the DMA software reset is clear before continuing.
159-
// //
160-
// while(HWREG(EMAC0_BASE + EMAC_O_DMABUSMOD) & EMAC_DMABUSMOD_SWR)
161-
// {
162-
// }
142+
// Make sure that the DMA software reset is clear before continuing.
163143
while emac0.dmabusmod.read().swr().bit_is_set() {}
164144

165145
emac0.dmabusmod.modify(|_, w| {
166146
// Set common flags. Note that this driver assumes we are always using 8 word
167147
// descriptors so we need to OR in EMAC_DMABUSMOD_ATDS here.
168148

169149
// Do we need to use the 8X burst length multiplier?
170-
171150
if tx_burst > 32 || rx_burst > 32 {
172151
// Divide both burst lengths by 8 and set the 8X burst length multiplier.
173152
w._8xpbl().set_bit();
@@ -201,28 +180,23 @@ fn emac_init(
201180
w
202181
});
203182

204-
// //
205-
// // Default the MII CSR clock divider based on the fastest system clock.
206-
// //
207-
// ui32Div = g_pi16MIIClockDiv[NUM_CLOCK_DIVISORS - 1].ui32Divisor;
208-
209-
// //
210-
// // Find the MII CSR clock divider to use based on the current system clock.
211-
// //
212-
// for(ui32Val = 0; ui32Val < NUM_CLOCK_DIVISORS; ui32Val++)
213-
// {
214-
// if(ui32SysClk <= g_pi16MIIClockDiv[ui32Val].ui32SysClockMax)
215-
// {
216-
// ui32Div = g_pi16MIIClockDiv[ui32Val].ui32Divisor;
217-
// break;
218-
// }
219-
// }
220-
221-
// //
222-
// // Set the MII CSR clock speed.
223-
// //
224-
// HWREG(ui32Base + EMAC_O_MIIADDR) = ((HWREG(ui32Base + EMAC_O_MIIADDR) &
225-
// ~EMAC_MIIADDR_CR_M) | ui32Div);
183+
unsafe {
184+
emac0.miiaddr.modify(|_, w| {
185+
w.cr().bits(if sysclk < 20_000_000 {
186+
panic!()
187+
} else if sysclk < 35_000_000 {
188+
0x8
189+
} else if sysclk < 60_000_000 {
190+
0xc
191+
} else if sysclk < 100_000_000 {
192+
0x0
193+
} else if sysclk < 150_000_000 {
194+
0x4
195+
} else {
196+
panic!()
197+
})
198+
});
199+
}
226200

227201
// Disable all the MMC interrupts as these are enabled by default at reset.
228202
unsafe {
@@ -268,6 +242,7 @@ pub struct EthernetDevice {
268242
tx_index: usize,
269243
rx_index: usize,
270244
emac0: EMAC0,
245+
tx_descriptor_reserved: [bool; NUM_TX_DESCRIPTORS],
271246
}
272247

273248
impl EthernetDevice {
@@ -337,21 +312,30 @@ impl EthernetDevice {
337312

338313
unsafe {
339314
for i in 0..NUM_TX_DESCRIPTORS {
315+
TX_DESCRIPTORS[i].tdes0.write(|w| {
316+
w.bits(
317+
DES0_TX_CTRL_LAST_SEG
318+
| DES0_TX_CTRL_FIRST_SEG
319+
| DES0_TX_CTRL_CHAINED
320+
| DES0_TX_CTRL_IP_ALL_CKHSUMS,
321+
)
322+
});
340323
TX_DESCRIPTORS[i]
341324
.tdes1
342325
.write(|w| w.bits(DES1_TX_CTRL_SADDR_INSERT));
326+
TX_DESCRIPTORS[i]
327+
.tdes2
328+
.write(|w| w.bits(&mut TX_BUFFERS[i] as *mut _ as *mut _ as u32));
343329
TX_DESCRIPTORS[i].tdes3.write(|w| {
344330
w.bits(if i == NUM_TX_DESCRIPTORS - 1 {
345331
&TX_DESCRIPTORS[0]
346332
} else {
347333
&TX_DESCRIPTORS[i + 1]
348334
} as *const _ as u32)
349335
});
350-
TX_DESCRIPTORS[i].tdes0.write(|w| w.bits(0));
351336
}
352337

353338
for i in 0..NUM_RX_DESCRIPTORS {
354-
RX_DESCRIPTORS[i].rdes0.write(|w| w.bits(DES0_RX_CTRL_OWN));
355339
RX_DESCRIPTORS[i].rdes1.write(|w| {
356340
w.bits(
357341
DES1_RX_CTRL_CHAINED
@@ -368,6 +352,7 @@ impl EthernetDevice {
368352
&RX_DESCRIPTORS[i + 1]
369353
} as *const _ as u32)
370354
});
355+
RX_DESCRIPTORS[i].rdes0.write(|w| w.own().set_bit());
371356
}
372357

373358
emac0
@@ -392,6 +377,11 @@ impl EthernetDevice {
392377
// unsafe {
393378
// EMACIntClear(emac0_base, EMACIntStatus(emac0_base, false));
394379
// }
380+
unsafe {
381+
emac0.dmaim.write(|w| w.bits(0xffff_ffff));
382+
emac0.ephyim.write(|w| w.bits(0xffff_ffff));
383+
}
384+
395385
emac_tx_enable(&emac0);
396386
emac_rx_enable(&emac0);
397387
nvic.enable(tm4c129x::Interrupt::EMAC0);
@@ -400,6 +390,7 @@ impl EthernetDevice {
400390
rx_index: 0,
401391
tx_index: 0,
402392
emac0,
393+
tx_descriptor_reserved: [false; NUM_TX_DESCRIPTORS],
403394
}
404395
}
405396
}
@@ -410,39 +401,65 @@ impl<'a> Device<'a> for EthernetDevice {
410401

411402
fn receive(&'a mut self) -> Option<(Self::RxToken, Self::TxToken)> {
412403
// Make sure that we own the receive descriptor.
413-
unsafe {
414-
if RX_DESCRIPTORS[self.rx_index].rdes0.read().bits() & DES0_RX_CTRL_OWN
415-
== DES0_RX_CTRL_OWN
416-
{
417-
return None;
418-
}
404+
let rx_descriptor = &RX_DESCRIPTORS[self.rx_index];
405+
if rx_descriptor.rdes0.read().own().bit_is_set() {
406+
return None;
419407
}
420408

421-
let result = Some((
422-
RxToken {
423-
descriptor: &RX_DESCRIPTORS[self.rx_index],
424-
},
425-
TxToken {
426-
index: &mut self.tx_index,
427-
emac0: &mut self.emac0,
428-
},
429-
));
409+
let tx_reservation = &mut self.tx_descriptor_reserved[self.tx_index];
410+
if *tx_reservation {
411+
return None;
412+
}
413+
let tx_descriptor = &TX_DESCRIPTORS[self.tx_index];
414+
if tx_descriptor.tdes0.read().own().bit_is_set() {
415+
return None;
416+
}
417+
let tx_buffer = unsafe { &mut TX_BUFFERS[self.tx_index] };
430418

431419
self.rx_index += 1;
432420
if self.rx_index == NUM_RX_DESCRIPTORS {
433421
self.rx_index = 0;
434422
}
423+
self.tx_index += 1;
424+
if self.tx_index == NUM_TX_DESCRIPTORS {
425+
self.tx_index = 0;
426+
}
435427

436-
result
428+
Some((
429+
RxToken {
430+
descriptor: rx_descriptor,
431+
},
432+
TxToken {
433+
descriptor: tx_descriptor,
434+
buffer: tx_buffer,
435+
reservation: tx_reservation,
436+
emac0: &self.emac0,
437+
},
438+
))
437439
}
438440

439-
fn transmit(&'a mut self) -> Option<(Self::TxToken)> {
440-
let result = Some(TxToken {
441-
index: &mut self.tx_index,
442-
emac0: &mut self.emac0,
443-
});
441+
fn transmit(&'a mut self) -> Option<Self::TxToken> {
442+
let tx_reservation = &mut self.tx_descriptor_reserved[self.tx_index];
443+
if *tx_reservation {
444+
return None;
445+
}
446+
let tx_descriptor = &TX_DESCRIPTORS[self.tx_index];
447+
if tx_descriptor.tdes0.read().own().bit_is_set() {
448+
return None;
449+
}
450+
let tx_buffer = unsafe { &mut TX_BUFFERS[self.tx_index] };
444451

445-
result
452+
self.tx_index += 1;
453+
if self.tx_index == NUM_TX_DESCRIPTORS {
454+
self.tx_index = 0;
455+
}
456+
457+
Some(TxToken {
458+
descriptor: tx_descriptor,
459+
buffer: tx_buffer,
460+
reservation: tx_reservation,
461+
emac0: &self.emac0,
462+
})
446463
}
447464

448465
fn capabilities(&self) -> DeviceCapabilities {
@@ -498,60 +515,50 @@ impl<'a> phy::RxToken for RxToken<'a> {
498515
} else {
499516
result = Err(smoltcp::Error::Checksum);
500517
}
501-
self.descriptor.rdes0.write(|w| w.bits(DES0_RX_CTRL_OWN));
518+
self.descriptor.rdes0.write(|w| w.own().set_bit());
502519
}
503520

504521
result
505522
}
506523
}
507524

508525
pub struct TxToken<'a> {
509-
index: &'a mut usize,
510-
emac0: &'a mut EMAC0,
526+
descriptor: &'a TDES,
527+
buffer: &'a mut [u8],
528+
reservation: &'a mut bool,
529+
emac0: &'a EMAC0,
530+
}
531+
532+
impl<'a> Drop for TxToken<'a> {
533+
fn drop(&mut self) {
534+
*self.reservation = false;
535+
}
511536
}
512537

513538
impl<'a> phy::TxToken for TxToken<'a> {
514539
fn consume<R, F>(self, _timestamp: Instant, len: usize, f: F) -> smoltcp::Result<R>
515540
where
516541
F: FnOnce(&mut [u8]) -> smoltcp::Result<R>,
517542
{
518-
let descriptor = &TX_DESCRIPTORS[*self.index];
519-
*self.index += 1;
520-
if *self.index == NUM_TX_DESCRIPTORS {
521-
*self.index = 0;
522-
}
523-
524-
while descriptor.tdes0.read().bits() & DES0_TX_CTRL_OWN == DES0_TX_CTRL_OWN {}
525-
526-
assert!(len <= RX_BUFFER_SIZE);
543+
assert!(self.descriptor.tdes0.read().own().bit_is_clear());
527544

528-
let mut data: [u8; RX_BUFFER_SIZE] = unsafe { core::mem::uninitialized() };
529-
let result = f(&mut data);
545+
assert!(len <= self.buffer.len());
546+
let result = f(self.buffer);
530547

531548
// Fill in the packet size and pointer, and tell the transmitter to start work.
532549
unsafe {
533-
descriptor.tdes1.write(|w| w.bits(len as u32));
534-
descriptor
535-
.tdes2
536-
.write(|w| w.bits(&mut data as *mut _ as *mut _ as u32));
537-
descriptor.tdes0.write(|w| {
538-
w.bits(
539-
DES0_TX_CTRL_LAST_SEG
540-
| DES0_TX_CTRL_FIRST_SEG
541-
| DES0_TX_CTRL_CHAINED
542-
| DES0_TX_CTRL_OWN
543-
| DES0_TX_CTRL_IP_ALL_CKHSUMS,
544-
)
545-
});
550+
self.descriptor
551+
.tdes1
552+
.write(|w| w.tbs1().bits(len.try_into().unwrap()));
546553
}
554+
self.descriptor.tdes0.modify(|_, w| w.own().set_bit());
555+
*self.reservation = false;
547556

548557
// Tell the DMA to reacquire the descriptor now that we've filled it in. This
549558
// call is benign if the transmitter hasn't stalled and checking the state takes
550559
// longer than just issuing a poll demand so we do this for all packets.
551560
self.emac0.txpolld.write(|w| w);
552561

553-
while descriptor.tdes0.read().bits() & DES0_TX_CTRL_OWN == DES0_TX_CTRL_OWN {}
554-
555562
result
556563
}
557564
}

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