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liweiwei
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add support for cbo.zero in cmo extension
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11 files changed

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‎riscv-target/sail-riscv-c/device/rv32i_m/cmo/Makefile.include‎

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TARGET_SIM ?= riscv_sim_RV32 -V
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TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS)
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BLOCKSZ ?= 16
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ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
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$(error Target simulator executable '$(TARGET_SIM)` not found)
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endif
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RUN_CMD=\
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$(TARGET_SIM) $(TARGET_FLAGS) -B $(BLOCKSZ) \
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--test-signature=$(*).signature.output \
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$(<)
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RISCV_PREFIX ?= riscv32-unknown-elf-
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RISCV_GCC ?= $(RISCV_PREFIX)gcc
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RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump
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RISCV_GCC_OPTS ?= -g -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles $(RVTEST_DEFINES)
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COMPILE_CMD = $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
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-I$(ROOTDIR)/riscv-test-suite/env/ \
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-I$(TARGETDIR)/$(RISCV_TARGET)/ \
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-T$(TARGETDIR)/$(RISCV_TARGET)/link.ld \
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$$(<) -o $$@
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OBJ_CMD = $$(RISCV_OBJDUMP) $$@ -D > [email protected]; \
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$$(RISCV_OBJDUMP) $$@ --source > [email protected]
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COMPILE_TARGET=\
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$(COMPILE_CMD); \
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if [ $$$$? -ne 0 ] ; \
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then \
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echo "\e[31m$$(RISCV_GCC) failed for target $$(@) \e[39m" ; \
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exit 1 ; \
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fi ; \
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$(OBJ_CMD); \
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if [ $$$$? -ne 0 ] ; \
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then \
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echo "\e[31m $$(RISCV_OBJDUMP) failed for target $$(@) \e[39m" ; \
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exit 1 ; \
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fi ;
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RUN_TARGET=\
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$(RUN_CMD)

‎riscv-target/sail-riscv-c/device/rv64i_m/cmo/Makefile.include‎

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TARGET_SIM ?= riscv_sim_RV64 -V
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TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS)
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BLOCKSZ ?= 16
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ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
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$(error Target simulator executable '$(TARGET_SIM)` not found)
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endif
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RUN_CMD=\
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$(TARGET_SIM) $(TARGET_FLAGS) -B $(BLOCKSZ)\
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--test-signature=$(*).signature.output \
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$(<)
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RISCV_PREFIX ?= riscv64-unknown-elf-
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RISCV_GCC ?= $(RISCV_PREFIX)gcc
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RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump
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RISCV_GCC_OPTS ?= -g -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles $(RVTEST_DEFINES)
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COMPILE_CMD = $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
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-I$(ROOTDIR)/riscv-test-suite/env/ \
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-I$(TARGETDIR)/$(RISCV_TARGET)/ \
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-T$(TARGETDIR)/$(RISCV_TARGET)/link.ld \
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$$(<) -o $$@
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OBJ_CMD = $$(RISCV_OBJDUMP) $$@ -D > [email protected]; \
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$$(RISCV_OBJDUMP) $$@ --source > [email protected]
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COMPILE_TARGET=\
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$(COMPILE_CMD); \
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if [ $$$$? -ne 0 ] ; \
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then \
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echo "\e[31m$$(RISCV_GCC) failed for target $$(@) \e[39m" ; \
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exit 1 ; \
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fi ; \
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$(OBJ_CMD); \
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if [ $$$$? -ne 0 ] ; \
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then \
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echo "\e[31m $$(RISCV_OBJDUMP) failed for target $$(@) \e[39m" ; \
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exit 1 ; \
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fi ;
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RUN_TARGET=\
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$(RUN_CMD)

‎riscv-test-suite/env/arch_test.h‎

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@@ -781,6 +781,13 @@ inst rs2, imm_val(rs1) ;\
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nop ;\
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nop
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#define TEST_CBO_ZERO(swreg,rs1,inst,imm_val,offset) ;\
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LI(rs1, offset*(BLOCKSZ*8/XLEN)+(imm_val&(BLOCKSZ-1))) ;\
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add rs1,swreg,rs1 ;\
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inst rs1 ;\
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nop ;\
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nop
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#define TEST_LOAD(swreg,testreg,index,rs1,destreg,imm_val,offset,inst,adj) ;\
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LA(rs1,rvtest_data+(index*4)+adj-imm_val) ;\
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inst destreg, imm_val(rs1) ;\

‎riscv-test-suite/rv32i_m/cmo/Makefile‎

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include ../../Makefile.include
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$(eval $(call compile_template,-march=rv32i -mabi=ilp32 -DXLEN=$(XLEN) -DBLOCKSZ=$(BLOCKSZ)))

‎riscv-test-suite/rv32i_m/cmo/Makefrag‎

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# RISC-V Architecture Test RV32I Makefrag
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#
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# Copyright (c) 2017, Codasip Ltd.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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# * Redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer.
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# * Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution.
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# * Neither the name of the Codasip Ltd. nor the
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# names of its contributors may be used to endorse or promote products
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# derived from this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY
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# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Description: Makefrag for RV32I architectural tests
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rv32i_sc_tests = \
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cbo.zero-01
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rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests))
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target_tests += $(rv32i_tests)

‎riscv-test-suite/rv32i_m/cmo/references/cbo.zero-01.reference_output‎

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