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Weiwei Li
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add support for cbo.zero in cmo extension
update CHANGELOG
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‎CHANGELOG.md‎

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# CHANGELOG
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## [3.6.9] - 2023-06-25
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- Add support for Zicboz extension
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## [3.6.8] - 2023-06-22
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- Fix broken hyperlink in README
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‎coverage/rvi_cmo.cgf‎

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# For Licence details look at https://github.com/riscv-software-src/riscv-ctg/-/blob/master/LICENSE.incore
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cbozero:
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config:
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- check ISA:=regex(.*I.*Zicboz.*Zicsr.*)
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opcode:
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cbo.zero: 0
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rs1:
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<<: *all_regs_mx0
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val_comb:
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abstract_comb:
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'walking_ones("rs1_val", 12, False)': 0
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'walking_zeros("rs1_val", 12, False)': 0
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'uniform_random(10, 100, ["rs1_val"], [12])': 0

‎riscv-test-suite/env/arch_test.h‎

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#define EXCPT_CAUSE_MSK ((1<<4)-1)
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#endif
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// set defaults
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#ifndef RVMODEL_CBZ_BLOCKSIZE
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#define RVMODEL_CBZ_BLOCKSIZE 64
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#endif
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// set defaults
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#ifndef RVMODEL_CMO_BLOCKSIZE
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#define RVMODEL_CMO_BLOCKSIZE 64
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#endif
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//==========================================================================================
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// By default, it is defined as nop for the implementation that does not support Zifencei
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// Implementations that support Zifencei may use the fence.i instruction.

‎riscv-test-suite/env/test_macros.h‎

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@@ -391,6 +391,14 @@ nop ;\
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csrr flagreg, fcsr ;\
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RVTEST_SIGUPD_F(swreg,destreg,flagreg)
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#define TEST_CBO_ZERO(swreg,rs1,inst,imm_val) ;\
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LI(rs1,imm_val&(RVMODEL_CBZ_BLOCKSIZE-1)) ;\
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add rs1,rs1,swreg ;\
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inst (rs1) ;\
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nop ;\
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nop ;\
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ADDI(swreg, swreg, RVMODEL_CBZ_BLOCKSIZE)
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#define TEST_CSR_FIELD(ADDRESS,TEMP_REG,MASK_REG,NEG_MASK_REG,VAL,DEST_REG,OFFSET,BASE_REG) ;\
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LI(TEMP_REG,VAL) ;\
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and TEMP_REG,TEMP_REG,MASK_REG ;\

‎riscv-test-suite/rv32i_m/CMO/src/cbo.zero-01.S‎

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// -----------
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// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
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// version : 0.10.4
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// timestamp : Wed Feb 22 09:04:22 2023 GMT
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// usage : riscv_ctg \
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// -- cgf // --cgf /workspace/riscv-ctg/sample_cgfs/dataset.cgf \
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// --cgf /workspace/riscv-ctg/sample_cgfs/rv32i_cbo.cgf \
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\
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// -- xlen 32 \
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// --randomize \
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// -----------
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//
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// -----------
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// Copyright (c) 2020. RISC-V International. All rights reserved.
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// SPDX-License-Identifier: BSD-3-Clause
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// -----------
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//
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// This assembly file tests the cbo.zero instruction of the RISC-V RV32ZicbozZicsr extension for the cbozero covergroup.
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//
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#include "model_test.h"
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#include "arch_test.h"
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RVTEST_ISA("RV32IZicbozZicsr")
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.section .text.init
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.globl rvtest_entry_point
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rvtest_entry_point:
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RVMODEL_BOOT
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RVTEST_CODE_BEGIN
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#ifdef TEST_CASE_1
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RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zicboz.*Zicsr.*);def TEST_CASE_1=True;",cbozero)
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RVTEST_SIGBASE(x2,signature_x2_1)
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inst_0:
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// rs1==x30, rs1_val == 0x4a9
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// opcode: cbo.zero ; op1:x30; op1val:0x4a9
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TEST_CBO_ZERO(x2,x30,cbo.zero,0x4a9)
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inst_1:
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// rs1==x9, rs1_val == 0xeb4
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// opcode: cbo.zero ; op1:x9; op1val:0xeb4
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TEST_CBO_ZERO(x2,x9,cbo.zero,0xeb4)
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inst_2:
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// rs1==x22, rs1_val == 0xe8e
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// opcode: cbo.zero ; op1:x22; op1val:0xe8e
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TEST_CBO_ZERO(x2,x22,cbo.zero,0xe8e)
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inst_3:
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// rs1==x27, rs1_val == 0x597
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// opcode: cbo.zero ; op1:x27; op1val:0x597
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TEST_CBO_ZERO(x2,x27,cbo.zero,0x597)
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inst_4:
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// rs1==x16, rs1_val == 4094,
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// opcode: cbo.zero ; op1:x16; op1val:0xffe
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TEST_CBO_ZERO(x2,x16,cbo.zero,0xffe)
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inst_5:
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// rs1==x12, rs1_val == 4093,
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// opcode: cbo.zero ; op1:x12; op1val:0xffd
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TEST_CBO_ZERO(x2,x12,cbo.zero,0xffd)
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inst_6:
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// rs1==x21, rs1_val == 4091,
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// opcode: cbo.zero ; op1:x21; op1val:0xffb
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TEST_CBO_ZERO(x2,x21,cbo.zero,0xffb)
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inst_7:
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// rs1==x28, rs1_val == 4087,
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// opcode: cbo.zero ; op1:x28; op1val:0xff7
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TEST_CBO_ZERO(x2,x28,cbo.zero,0xff7)
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inst_8:
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// rs1==x25, rs1_val == 4079,
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// opcode: cbo.zero ; op1:x25; op1val:0xfef
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TEST_CBO_ZERO(x2,x25,cbo.zero,0xfef)
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inst_9:
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// rs1==x6, rs1_val == 4063,
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// opcode: cbo.zero ; op1:x6; op1val:0xfdf
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TEST_CBO_ZERO(x2,x6,cbo.zero,0xfdf)
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inst_10:
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// rs1==x1, rs1_val == 4031,
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// opcode: cbo.zero ; op1:x1; op1val:0xfbf
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TEST_CBO_ZERO(x2,x1,cbo.zero,0xfbf)
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inst_11:
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// rs1==x4, rs1_val == 3967,
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// opcode: cbo.zero ; op1:x4; op1val:0xf7f
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TEST_CBO_ZERO(x2,x4,cbo.zero,0xf7f)
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inst_12:
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// rs1==x7, rs1_val == 3839,
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// opcode: cbo.zero ; op1:x7; op1val:0xeff
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TEST_CBO_ZERO(x2,x7,cbo.zero,0xeff)
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inst_13:
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// rs1==x3, rs1_val == 3583,
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// opcode: cbo.zero ; op1:x3; op1val:0xdff
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TEST_CBO_ZERO(x2,x3,cbo.zero,0xdff)
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inst_14:
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// rs1==x18, rs1_val == 3071,
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// opcode: cbo.zero ; op1:x18; op1val:0xbff
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TEST_CBO_ZERO(x2,x18,cbo.zero,0xbff)
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inst_15:
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// rs1==x10, rs1_val == 2047,
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// opcode: cbo.zero ; op1:x10; op1val:0x7ff
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TEST_CBO_ZERO(x2,x10,cbo.zero,0x7ff)
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inst_16:
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// rs1==x8, rs1_val == 1,
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// opcode: cbo.zero ; op1:x8; op1val:0x1
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TEST_CBO_ZERO(x2,x8,cbo.zero,0x1)
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inst_17:
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// rs1==x23, rs1_val == 2,
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// opcode: cbo.zero ; op1:x23; op1val:0x2
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TEST_CBO_ZERO(x2,x23,cbo.zero,0x2)
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inst_18:
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// rs1==x13, rs1_val == 4,
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// opcode: cbo.zero ; op1:x13; op1val:0x4
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TEST_CBO_ZERO(x2,x13,cbo.zero,0x4)
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inst_19:
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// rs1==x17, rs1_val == 8,
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// opcode: cbo.zero ; op1:x17; op1val:0x8
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TEST_CBO_ZERO(x2,x17,cbo.zero,0x8)
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inst_20:
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// rs1==x31, rs1_val == 16,
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// opcode: cbo.zero ; op1:x31; op1val:0x10
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TEST_CBO_ZERO(x2,x31,cbo.zero,0x10)
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inst_21:
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// rs1==x29, rs1_val == 32,
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// opcode: cbo.zero ; op1:x29; op1val:0x20
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TEST_CBO_ZERO(x2,x29,cbo.zero,0x20)
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inst_22:
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// rs1==x11, rs1_val == 64,
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// opcode: cbo.zero ; op1:x11; op1val:0x40
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TEST_CBO_ZERO(x2,x11,cbo.zero,0x40)
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inst_23:
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// rs1==x5, rs1_val == 128,
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// opcode: cbo.zero ; op1:x5; op1val:0x80
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TEST_CBO_ZERO(x2,x5,cbo.zero,0x80)
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inst_24:
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// rs1==x24, rs1_val == 256,
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// opcode: cbo.zero ; op1:x24; op1val:0x100
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TEST_CBO_ZERO(x2,x24,cbo.zero,0x100)
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inst_25:
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// rs1==x15, rs1_val == 512,
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// opcode: cbo.zero ; op1:x15; op1val:0x200
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TEST_CBO_ZERO(x2,x15,cbo.zero,0x200)
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inst_26:
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// rs1==x14, rs1_val == 1024,
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// opcode: cbo.zero ; op1:x14; op1val:0x400
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TEST_CBO_ZERO(x2,x14,cbo.zero,0x400)
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inst_27:
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// rs1==x19, rs1_val == 2048,
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// opcode: cbo.zero ; op1:x19; op1val:0x800
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TEST_CBO_ZERO(x2,x19,cbo.zero,0x800)
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RVTEST_SIGBASE(x1,signature_x1_0)
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inst_28:
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// rs1==x20, rs1_val == 0xc93
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// opcode: cbo.zero ; op1:x20; op1val:0xc93
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TEST_CBO_ZERO(x1,x20,cbo.zero,0xc93)
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inst_29:
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// rs1==x26, rs1_val == 0xb31
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// opcode: cbo.zero ; op1:x26; op1val:0xb31
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TEST_CBO_ZERO(x1,x26,cbo.zero,0xb31)
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inst_30:
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// rs1==x2, rs1_val == 0xddf
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// opcode: cbo.zero ; op1:x2; op1val:0xddf
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TEST_CBO_ZERO(x1,x2,cbo.zero,0xddf)
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inst_31:
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// rs1_val == 0x384
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// opcode: cbo.zero ; op1:x31; op1val:0x384
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TEST_CBO_ZERO(x1,x31,cbo.zero,0x384)
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inst_32:
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// rs1_val == 0x3e1
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// opcode: cbo.zero ; op1:x31; op1val:0x3e1
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TEST_CBO_ZERO(x1,x31,cbo.zero,0x3e1)
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inst_33:
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// rs1_val == 0x290
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// opcode: cbo.zero ; op1:x31; op1val:0x290
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TEST_CBO_ZERO(x1,x31,cbo.zero,0x290)
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inst_34:
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// rs1_val == 0xe97
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// opcode: cbo.zero ; op1:x31; op1val:0xe97
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TEST_CBO_ZERO(x1,x31,cbo.zero,0xe97)
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inst_35:
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// rs1_val == 0x86d
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// opcode: cbo.zero ; op1:x31; op1val:0x86d
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TEST_CBO_ZERO(x1,x31,cbo.zero,0x86d)
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inst_36:
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// rs1_val == 0x188
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// opcode: cbo.zero ; op1:x31; op1val:0x188
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TEST_CBO_ZERO(x1,x31,cbo.zero,0x188)
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inst_37:
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// rs1_val == 0x68b
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// opcode: cbo.zero ; op1:x31; op1val:0x68b
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TEST_CBO_ZERO(x1,x31,cbo.zero,0x68b)
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inst_38:
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// rs1_val == 0xabb
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// opcode: cbo.zero ; op1:x31; op1val:0xabb
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TEST_CBO_ZERO(x1,x31,cbo.zero,0xabb)
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inst_39:
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// rs1_val == 0x759
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// opcode: cbo.zero ; op1:x31; op1val:0x759
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TEST_CBO_ZERO(x1,x31,cbo.zero,0x759)
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inst_40:
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// rs1_val == 0x9e6
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// opcode: cbo.zero ; op1:x31; op1val:0x9e6
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TEST_CBO_ZERO(x1,x31,cbo.zero,0x9e6)
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inst_41:
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// rs1_val == 0x686
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// opcode: cbo.zero ; op1:x31; op1val:0x686
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TEST_CBO_ZERO(x1,x31,cbo.zero,0x686)
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inst_42:
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// rs1_val == 0x5b5
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// opcode: cbo.zero ; op1:x31; op1val:0x5b5
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TEST_CBO_ZERO(x1,x31,cbo.zero,0x5b5)
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inst_43:
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// rs1_val == 0x481
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// opcode: cbo.zero ; op1:x31; op1val:0x481
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TEST_CBO_ZERO(x1,x31,cbo.zero,0x481)
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#endif
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RVTEST_CODE_END
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RVMODEL_HALT
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RVTEST_DATA_BEGIN
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.align 4
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rvtest_data:
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.word 0xbabecafe
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.word 0xabecafeb
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.word 0xbecafeba
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.word 0xecafebab
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RVTEST_DATA_END
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RVMODEL_DATA_BEGIN
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rvtest_sig_begin:
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sig_begin_canary:
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CANARY;
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signature_x2_0:
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.fill 0*((RVMODEL_CBZ_BLOCKSIZE)/4),4,0xdeadbeef
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signature_x2_1:
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.fill 28*((RVMODEL_CBZ_BLOCKSIZE)/4),4,0xdeadbeef
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signature_x1_0:
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.fill 16*((RVMODEL_CBZ_BLOCKSIZE)/4),4,0xdeadbeef
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#ifdef rvtest_mtrap_routine
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tsig_begin_canary:
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CANARY;
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mtrap_sigptr:
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.fill 64*XLEN/32,4,0xdeadbeef
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tsig_end_canary:
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CANARY;
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#endif
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#ifdef rvtest_gpr_save
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gpr_save:
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.fill 32*XLEN/32,4,0xdeadbeef
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#endif
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sig_end_canary:
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CANARY;
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rvtest_sig_end:
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RVMODEL_DATA_END

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