disassembly working (to a degree)

Author: redraincatching

README.md

@@ -0,0 +1,13 @@
+# `asha` - a RISC-V decompiler written in Rust
+// technically it's just a disassembler for now, still a work in progress
+
+`asha` is a decompiler that I'm writing as a final year project. 
+
+## Current RISC-V extension support 
+- RV32I
+- RV64I
+
+## Current comparison to `llvm-objdump`
+|![](https://github.com/redraincatching/asha/raw/main/images/objdump_comparison.png)|![](https://github.com/redraincatching/asha/raw/main/images/asha_comparison.png)|
+|:---------------------:|:-------------:|
+| `llvm-objdump` output | `asha` output |

images/asha_comparison.png

@@ -2,16 +2,14 @@ use crate::instructions::*;
 
 /// # instruction decoding
 /// TODO: explain this
-fn disassemble(instruction: Instruction) -> Option<InstructionType> {
+pub fn disassemble(instruction: Instruction) -> Option<InstructionType> {
     // check if the instruction is valid
     if (instruction == 0) || (instruction == 0xFFFFFFFF) || (instruction & 0b11 != 0b11) {
         return None
     } 
 
     // determine which function it is
     if let Some((name, i_type)) = determine_name(&instruction) {
-        // TODO: match on instruction type and change register operands using the enum
-
         match i_type {
             IT::R => Some(InstructionType::R { 
                 name, 
@@ -47,6 +45,7 @@ fn disassemble(instruction: Instruction) -> Option<InstructionType> {
                 rd: ABIRegister::from(retrieve!(rd instruction) as u8),
                 imm: retrieve!(jimm instruction)
             })
+            // TODO: extend for R4
         }        
     } else { 
         None 
@@ -55,35 +54,64 @@ fn disassemble(instruction: Instruction) -> Option<InstructionType> {
 
 /// # Determine the function name
 /// TODO: better documentation for all of these, honestly
-/// TODO: account for R4 instructions here too, could just do it in the table with correct masks?
-fn determine_name(instruction: &Instruction) -> Option<(String, IT)> {
+/// TODO: account for R4 instructions here too
+fn determine_name(instruction: &Instruction) -> Option<(&'static str, IT)> {
     // this function was revealed to me in a dream
 
-    // what i actually want to do here is combine the three fields into a single binary number
-    // and get which one it is with a jump table
-    // something like (funct7.unwrap_or(0) << 8 | funct3.unwrap_or(0) << 5 | opcode as u32)
     let opcode: u8 = retrieve!(opcode instruction).try_into().unwrap();
-    let funct3: u8 = retrieve!(funct3 instruction).try_into().unwrap();
-    let funct7: u8 = retrieve!(funct7 instruction).try_into().unwrap();
+    let i_type = determine_type(opcode)?;
+
+    let funct3: u8;
+    let funct7: u8;
+
+    // U and J-type only use opcode
+    if !(i_type == IT::U || i_type == IT::J) {
+        funct3 = retrieve!(funct3 instruction).try_into().unwrap();
+
+        // only R uses funct7 (and also _one_ singular i-type)
+        if i_type == IT::R || opcode == 0b00100 {
+            funct7 = retrieve!(funct7 instruction).try_into().unwrap();
+        } else {
+            funct7 = 0;
+        }
+
+    } else {
+        funct3 = 0;
+        funct7 = 0;
+    }
 
     // use the from_bits to convert
-    if let Some((name, i_type)) = from_bits(opcode, funct3, funct7) {
-        Some((name, i_type))
+    from_bits(opcode, funct3, funct7).map(|name| (name, i_type))
+}
+
+/// Determine the type of instruction, and therefore which fields to match on
+fn determine_type(opcode: u8) -> Option<IT> {
+    let bf = OpcodeBitfield::from_opcode(opcode);
+    
+    if (bf.op4 && bf.op2) || (bf.op3 && bf.op2 && !bf.op0) {
+        Some(IT::R)
+    } else if (!bf.op4 && !bf.op3 && !bf.op2) || (!bf.op4 && !bf.op3 && !bf.op0) || (bf.op4 && bf.op3 && !bf.op1 && bf.op0) {
+        Some(IT::I)
+    } else if !bf.op4 && bf.op3 && !bf.op2 {
+        Some(IT::S)
+    } else if bf.op4 && bf.op3 && !bf.op0 {
+        Some(IT::B)
+    } else if bf.op2 && bf.op0 {
+        Some(IT::U)
+    } else if bf.op3 && !bf.op2 && bf.op1 {
+        Some(IT::J)
+    //} else if bf.op4 && !bf.op3 && !bf.op2 {
+    //    Some(IT::R4)
     } else {
         None
-    } 
+    }
 }
 
 /// Convert from bit fields to instruction
-/// TODO: swap this from a match statement to a phf, see https://github.com/rust-phf/rust-phf
-/// also of note, https://github.com/abonander/mime_guess/pull/14/files
-fn from_bits(opcode: u8, funct3: u8, funct7: u8) -> Option<(String, IT)> {
-    // convert to single value 
-    match (opcode, funct3, funct7) {
-        // RV32I
-        (0b01100, 0b000, 0b0000000) => Some(("add".to_string(), IT::R)),
-        _ => None
-    }
+fn from_bits(opcode: u8, funct3: u8, funct7: u8) -> Option<&'static str> {
+    // convert to array so that the phf map can use it as a key
+    let key: [u8; 3] = [opcode, funct3, funct7];
+    INSTRUCTIONS.get(&key).cloned()
 }
 
 #[cfg(test)]
@@ -92,23 +120,69 @@ mod test {
 
     #[test]
     fn test_decoding() {
-        // TODO: replace these with ones with nontrivial operands
-        let r_type = 0x4000503b;  // sraw
-        let u_type = 0x00000037;  // lui
-        let i_type = 0x00002003;  // lw
-        let b_type = 0x00000063;  // beq
-        let s_type = 0x4000503b;  // sraw
-        let j_type = 0x00003023;  // sd
+        let r_type = 0x40c5d53b;  // sraw a0, a1, a2
+        let u_type = 0x076192b7;  // lui t0, 30233
+        let i_type = 0x05002083;  // lw ra, 80
+        let b_type = 0x00928263;  // beq t0, s1, 4
+        let s_type = 0x01103523;  // sd a7, 10
+        let j_type = 0x04c0016f;  // jal sp, 76
 
         assert_eq!(
             disassemble(r_type), 
-            // TODO: test versions with ABI and raw identifiers?
-            // or maybe not
             Some(InstructionType::R { 
-                name: "sraw".to_string(),
-                rd: ABIRegister::zero, 
+                name: "sraw",
+                rd: ABIRegister::a0, 
+                rs1: ABIRegister::a1,
+                rs2: ABIRegister::a2 
+            })
+        );
+
+        assert_eq!(
+            disassemble(u_type), 
+            Some(InstructionType::U { 
+                name: "lui",
+                rd: ABIRegister::t0,
+                imm: 30233 
+            })
+        );
+
+        assert_eq!(
+            disassemble(i_type),
+            Some(InstructionType::I { 
+                name: "lw", 
+                rd: ABIRegister::ra,
+                rs1: ABIRegister::zero, 
+                imm: 80 
+            })
+        );
+
+        assert_eq!(
+            disassemble(b_type),
+            Some(InstructionType::B { 
+                name: "beq",
+                rs1: ABIRegister::t0,
+                rs2: ABIRegister::s1,
+                imm: 4 
+            })
+        );
+
+        assert_eq!(
+            disassemble(s_type),
+            Some(InstructionType::S { 
+                name: "sd",
                 rs1: ABIRegister::zero,
-                rs2: ABIRegister::zero 
-            }));
+                rs2: ABIRegister::a7,
+                imm: 10 
+            })
+        );
+
+        assert_eq!(
+            disassemble(j_type),
+            Some(InstructionType::J { 
+                name: "jal",
+                rd: ABIRegister::sp,
+                imm: 76 
+            })
+        );
     }
 }