diff --git a/src/dos/dos.cpp b/src/dos/dos.cpp
index 442ba62d..1e352e25 100644
--- a/src/dos/dos.cpp
+++ b/src/dos/dos.cpp
@@ -437,6 +437,7 @@ static Bitu DOS_21Handler(void) {
 			int a = (14 - dos.date.month)/12;
 			int y = dos.date.year - a;
 			int m = dos.date.month + 12*a - 2;
+			reg_ah=0x2a;
 			reg_al=(dos.date.day+y+(y/4)-(y/100)+(y/400)+(31*m)/12) % 7;
 			reg_cx=dos.date.year;
 			reg_dh=dos.date.month;
diff --git a/src/dos/dos_memory.cpp b/src/dos/dos_memory.cpp
index e03b55f0..f5553686 100644
--- a/src/dos/dos_memory.cpp
+++ b/src/dos/dos_memory.cpp
@@ -224,7 +224,8 @@ bool DOS_ResizeMemory(Bit16u segment,Bit16u * blocks) {
 	DOS_MCB	mcb_next(segment+total);
 	if (*blocks<=total) {
 		if (GCC_UNLIKELY(*blocks==total)) {
-			/* Nothing to do */
+			/* Size unchanged */
+			mcb.SetPSPSeg(dos.psp());
 			return true;
 		}
 		/* Shrinking MCB */
@@ -272,7 +273,11 @@ bool DOS_ResizeMemory(Bit16u segment,Bit16u * blocks) {
 	}
 	mcb.SetSize(total);
 	mcb.SetPSPSeg(dos.psp());
-	if (*blocks==total) return true;	/* block fit exactly */
+	if (*blocks==total) {
+		/* block fit exactly */
+		mcb.SetPSPSeg(dos.psp());
+		return true;
+	}
 
 	*blocks=total;	/* return maximum */
 	DOS_SetError(DOSERR_INSUFFICIENT_MEMORY);
diff --git a/src/hardware/mpu401.cpp b/src/hardware/mpu401.cpp
index f29af826..b7340d9c 100644
--- a/src/hardware/mpu401.cpp
+++ b/src/hardware/mpu401.cpp
@@ -625,7 +625,6 @@ static void MPU401_Reset(void) {
 	mpu.clock.cth_rate=60;
 	mpu.clock.cth_counter=0;
 	mpu.clock.cth_savecount=0;
-	ClrQueue();
 	mpu.state.req_mask=0;
 	mpu.condbuf.counter=0;
 	mpu.condbuf.type=T_OVERFLOW;
diff --git a/src/hardware/vga_seq.cpp b/src/hardware/vga_seq.cpp
index f39243b3..2c36d239 100644
--- a/src/hardware/vga_seq.cpp
+++ b/src/hardware/vga_seq.cpp
@@ -96,7 +96,7 @@ void write_p3c5(Bitu /*port*/,Bitu val,Bitu iolen) {
 		/* 
 			0  Set if in an alphanumeric mode, clear in graphics modes.
 			1  Set if more than 64kbytes on the adapter.
-			2  Enables Odd/Even addressing mode if set. Odd/Even mode places all odd
+			2  Disables Odd/Even addressing mode if set. Odd/Even mode places all odd
 				bytes in plane 1&3, and all even bytes in plane 0&2.
 			3  If set address bit 0-1 selects video memory planes (256 color mode),
 				rather than the Map Mask and Read Map Select Registers.
diff --git a/src/ints/bios_disk.cpp b/src/ints/bios_disk.cpp
index 35979281..f9cb5aaf 100644
--- a/src/ints/bios_disk.cpp
+++ b/src/ints/bios_disk.cpp
@@ -39,7 +39,10 @@ diskGeo DiskGeometryList[] = {
 	{ 720,  9, 2, 80, 3},	// DS/DD 3.5"
 	{1200, 15, 2, 80, 2},	// DS/HD 5.25"
 	{1440, 18, 2, 80, 4},	// DS/HD 3.5"
+	{1520, 19, 2, 80, 2},	// DS/HD 5.25" (XDF)
 	{1680, 21, 2, 80, 4},	// DS/HD 3.5"  (DMF)
+	{1720, 21, 2, 82, 4},	// DS/HD 3.5"  (DMF)
+	{1840, 23, 2, 80, 4},	// DS/HD 3.5"  (XDF)
 	{2880, 36, 2, 80, 6},	// DS/ED 3.5"
 	{0, 0, 0, 0, 0}
 };
diff --git a/src/ints/ems.cpp b/src/ints/ems.cpp
index 4905c8cc..cac45c26 100644
--- a/src/ints/ems.cpp
+++ b/src/ints/ems.cpp
@@ -478,7 +478,7 @@ static Bit8u EMM_GetPagesForAllHandles(PhysPt table,Bit16u & handles) {
 }
 
 static Bit8u EMM_PartialPageMapping(void) {
-	PhysPt list,data;Bit16u count;
+	PhysPt list,data;Bit16u count,page;
 	switch (reg_al) {
 	case 0x00:	/* Save Partial Page Map */
 		list = SegPhys(ds)+reg_si;
@@ -488,38 +488,41 @@ static Bit8u EMM_PartialPageMapping(void) {
 		for (;count>0;count--) {
 			Bit16u segment=mem_readw(list);list+=2;
 			if ((segment>=EMM_PAGEFRAME) && (segment<EMM_PAGEFRAME+0x1000)) {
-				Bit16u page = (segment-EMM_PAGEFRAME) / (EMM_PAGE_SIZE>>4);
-				mem_writew(data,segment);data+=2;
-				MEM_BlockWrite(data,&emm_mappings[page],sizeof(EMM_Mapping));
-				data+=sizeof(EMM_Mapping);
+				page=(segment-EMM_PAGEFRAME)>>10;
+				mem_writeb(data++,(Bit8u)page);
+				mem_writeb(data++,(Bit8u)emm_mappings[page].handle);
+				mem_writew(data,emm_mappings[page].page);
 			} else if ((ems_type==1) || (ems_type==3) || ((segment>=EMM_PAGEFRAME-0x1000) && (segment<EMM_PAGEFRAME)) || ((segment>=0xa000) && (segment<0xb000))) {
-				mem_writew(data,segment);data+=2;
-				MEM_BlockWrite(data,&emm_segmentmappings[segment>>10],sizeof(EMM_Mapping));
-				data+=sizeof(EMM_Mapping);
+				page=segment>>10;
+				mem_writeb(data++,(Bit8u)page);
+				mem_writeb(data++,(Bit8u)emm_segmentmappings[page].handle);
+				mem_writew(data,emm_segmentmappings[page].page);
 			} else {
 				return EMM_ILL_PHYS;
 			}
+			data+=2;
 		}
 		break;
 	case 0x01:	/* Restore Partial Page Map */
 		data = SegPhys(ds)+reg_si;
 		count= mem_readw(data);data+=2;
 		for (;count>0;count--) {
-			Bit16u segment=mem_readw(data);data+=2;
-			if ((segment>=EMM_PAGEFRAME) && (segment<EMM_PAGEFRAME+0x1000)) {
-				Bit16u page = (segment-EMM_PAGEFRAME) / (EMM_PAGE_SIZE>>4);
-				MEM_BlockRead(data,&emm_mappings[page],sizeof(EMM_Mapping));
-			} else if ((ems_type==1) || (ems_type==3) || ((segment>=EMM_PAGEFRAME-0x1000) && (segment<EMM_PAGEFRAME)) || ((segment>=0xa000) && (segment<0xb000))) {
-				MEM_BlockRead(data,&emm_segmentmappings[segment>>10],sizeof(EMM_Mapping));
+			page=(Bit16u)mem_readb(data++);
+			if (page<EMM_MAX_PHYS) {
+				emm_mappings[page].handle=(Bit16u)mem_readb(data++);
+				emm_mappings[page].page=mem_readw(data);
+			} else if (page<0x40) {
+				emm_segmentmappings[page].handle=(Bit16u)mem_readb(data++);
+				emm_segmentmappings[page].page=mem_readw(data);
 			} else {
 				return EMM_ILL_PHYS;
 			}
-			data+=sizeof(EMM_Mapping);
+			data+=2;
 		}
 		return EMM_RestoreMappingTable();
 		break;
 	case 0x02:	/* Get Partial Page Map Array Size */
-		reg_al=(Bit8u)(2+reg_bx*(2+sizeof(EMM_Mapping)));
+		reg_al=(Bit8u)(2+reg_bx*4);
 		break;
 	default:
 		LOG(LOG_MISC,LOG_ERROR)("EMS:Call %2X Subfunction %2X not supported",reg_ah,reg_al);
@@ -915,7 +918,7 @@ static Bitu INT67_Handler(void) {
 				/* adjust paging entries for page frame (if mapped) */
 				for (ct=0; ct<4; ct++) {
 					Bit16u handle=emm_mappings[ct].handle;
-					if (handle!=0xffff) {
+					if (handle!=NULL_HANDLE) {
 						Bit16u memh=(Bit16u)MEM_NextHandleAt(emm_handles[handle].mem,emm_mappings[ct].page*4);
 						Bit16u entry_addr=reg_di+(EMM_PAGEFRAME>>6)+(ct*0x10);
 						real_writew(SegValue(es),entry_addr+0x00+0x01,(memh+0)*0x10);		// mapping of 1/4 of page
@@ -976,7 +979,7 @@ static Bitu INT67_Handler(void) {
 					else if (mem_seg<EMM_PAGEFRAME+0xc00) phys_page=2;
 					else phys_page=3;
 					Bit16u handle=emm_mappings[phys_page].handle;
-					if (handle==0xffff) {
+					if (handle==NULL_HANDLE) {
 						reg_ah=EMM_ILL_PHYS;
 						break;
 					} else {
diff --git a/src/ints/int10_modes.cpp b/src/ints/int10_modes.cpp
index 76e0646e..49c5f621 100644
--- a/src/ints/int10_modes.cpp
+++ b/src/ints/int10_modes.cpp
@@ -798,28 +798,29 @@ bool INT10_SetVideoMode(Bit16u mode) {
 	/* Program Sequencer */
 	Bit8u seq_data[SEQ_REGS];
 	memset(seq_data,0,SEQ_REGS);
-	seq_data[1]|=0x01;	//8 dot fonts by default
-	if (CurMode->special & _EGA_HALF_CLOCK) seq_data[1]|=0x08; //Check for half clock
-	if ((machine==MCH_EGA) && (CurMode->special & _EGA_HALF_CLOCK)) seq_data[1]|=0x02;
-	seq_data[4]|=0x02;	//More than 64kb
+	seq_data[1]|=0x01;					//8-dot fonts by default
+	if (CurMode->special & _EGA_HALF_CLOCK) {
+		seq_data[1]|=0x08;				//Double width
+		if (machine==MCH_EGA) seq_data[1]|=0x02;
+	}
+	seq_data[4]|=0x02;					//More than 64kb
 	switch (CurMode->type) {
 	case M_TEXT:
 		if (CurMode->cwidth==9) seq_data[1] &= ~1;
 		seq_data[2]|=0x3;				//Enable plane 0 and 1
-		seq_data[4]|=0x01;				//Alpanumeric
-		if (IS_VGA_ARCH) seq_data[4]|=0x04;				//odd/even enabled
+		seq_data[4]|=0x01;				//Alphanumeric
 		break;
 	case M_CGA2:
-		seq_data[2]|=0xf;				//Enable plane 0
-		if (machine==MCH_EGA) seq_data[4]|=0x04;		//odd/even enabled
+		seq_data[2]|=0x1;				//Enable plane 0
+		seq_data[4]|=0x04;				//odd/even disabled
 		break;
 	case M_CGA4:
-		if (machine==MCH_EGA) seq_data[2]|=0x03;		//Enable plane 0 and 1
+		seq_data[2]|=0x03;				//Enable plane 0 and 1
 		break;
 	case M_LIN4:
 	case M_EGA:
 		seq_data[2]|=0xf;				//Enable all planes for writing
-		if (machine==MCH_EGA) seq_data[4]|=0x04;		//odd/even enabled
+		seq_data[4]|=0x04;				//odd/even disabled
 		break;
 	case M_LIN8:						//Seems to have the same reg layout from testing
 	case M_LIN15:
@@ -827,7 +828,7 @@ bool INT10_SetVideoMode(Bit16u mode) {
 	case M_LIN32:
 	case M_VGA:
 		seq_data[2]|=0xf;				//Enable all planes for writing
-		seq_data[4]|=0xc;				//Graphics - odd/even - Chained
+		seq_data[4]|=0xc;				//Graphics - odd/even disabled - Chained
 		break;
 	}
 	for (Bit8u ct=0;ct<SEQ_REGS;ct++) {
diff --git a/src/ints/int10_put_pixel.cpp b/src/ints/int10_put_pixel.cpp
index e589b6b1..63c8e4f3 100644
--- a/src/ints/int10_put_pixel.cpp
+++ b/src/ints/int10_put_pixel.cpp
@@ -136,6 +136,8 @@ void INT10_PutPixel(Bit16u x,Bit16u y,Bit8u page,Bit8u color) {
 		}
 	case M_EGA:
 		{
+			/* Enable writing to all planes */
+			IO_Write(0x3c4,0x2);IO_Write(0x3c5,0xf);
 			/* Set the correct bitmask for the pixel position */
 			IO_Write(0x3ce,0x8);Bit8u mask=128>>(x&7);IO_Write(0x3cf,mask);
 			/* Set the color to set/reset register */
diff --git a/src/ints/int10_vesa.cpp b/src/ints/int10_vesa.cpp
index d8978b42..5aed681b 100644
--- a/src/ints/int10_vesa.cpp
+++ b/src/ints/int10_vesa.cpp
@@ -259,7 +259,7 @@ Bit8u VESA_GetSVGAModeInformation(Bit16u mode,Bit16u seg,Bit16u off) {
 	var_write(&minfo.Reserved_page,0x1);
 	var_write(&minfo.XCharSize,mblock->cwidth);
 	var_write(&minfo.YCharSize,mblock->cheight);
-	if (!int10.vesa_nolfb) var_write(&minfo.PhysBasePtr,S3_LFB_BASE);
+	if (modeAttributes & 0x80) var_write(&minfo.PhysBasePtr,S3_LFB_BASE);
 
 	MEM_BlockWrite(buf,&minfo,sizeof(MODE_INFO));
 	return VESA_SUCCESS;
@@ -508,11 +508,12 @@ Bit8u VESA_GetDisplayStart(Bit16u & x,Bit16u & y) {
 	IO_Read(0x3da);              // reset attribute flipflop
 	IO_Write(0x3c0,0x13 | 0x20); // panning register, screen on
 	Bit8u panning = IO_Read(0x3c1);
+	if ((CurMode->type == M_TEXT) && (panning > 7)) panning = 0;
 
 	Bitu virtual_screen_width = vga.config.scan_len * pixels_per_offset;
 	Bitu start_pixel = vga.config.display_start * (pixels_per_offset/2) 
 		+ panning / panning_factor;
-	
+
 	y = start_pixel / virtual_screen_width;
 	x = start_pixel % virtual_screen_width;
 	return VESA_SUCCESS;
diff --git a/src/ints/int10_vptable.cpp b/src/ints/int10_vptable.cpp
index 50261093..0aa08e8a 100644
--- a/src/ints/int10_vptable.cpp
+++ b/src/ints/int10_vptable.cpp
@@ -96,25 +96,49 @@ const Bit8u vparams_tandy_td[] = {
 
 static Bit8u video_parameter_table_vga[0x40*0x1d]={
 // video parameter table for mode 0 (cga emulation)
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x28, 0x18, 0x08, 0x00, 0x08, // bios data
+  0x09, 0x03, 0x00, 0x02, // sequencer registers
+  0x63, // misc output registers
+  0x2d, 0x27, 0x28, 0x90, 0x2b, 0xa0, 0xbf, 0x1f,       // crtc registers 0-7
+  0x00, 0xc7, 0x06, 0x07, 0x00, 0x00, 0x00, 0x00,       // crtc registers 8-15
+  0x9c, 0x8e, 0x8f, 0x14, 0x1f, 0x96, 0xb9, 0xa3, 0xff, // crtc registers 16-24
+  0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,       // attr registers 0-7
+  0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,       // attr registers 8-15
+  0x08, 0x00, 0x0f, 0x00, // attr registers 16-19
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x00, 0xff, // graphics registers 0-8
 // video parameter table for mode 1 (cga emulation)
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x28, 0x18, 0x08, 0x00, 0x08, // bios data
+  0x09, 0x03, 0x00, 0x02, // sequencer registers
+  0x63, // misc output registers
+  0x2d, 0x27, 0x28, 0x90, 0x2b, 0xa0, 0xbf, 0x1f,       // crtc registers 0-7
+  0x00, 0xc7, 0x06, 0x07, 0x00, 0x00, 0x00, 0x00,       // crtc registers 8-15
+  0x9c, 0x8e, 0x8f, 0x14, 0x1f, 0x96, 0xb9, 0xa3, 0xff, // crtc registers 16-24
+  0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,       // attr registers 0-7
+  0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,       // attr registers 8-15
+  0x08, 0x00, 0x0f, 0x00, // attr registers 16-19
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x00, 0xff, // graphics registers 0-8
 // video parameter table for mode 2 (cga emulation)
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x50, 0x18, 0x08, 0x00, 0x10, // bios data
+  0x01, 0x03, 0x00, 0x02, // sequencer registers
+  0x63, // misc output registers
+  0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,       // crtc registers 0-7
+  0x00, 0xc7, 0x06, 0x07, 0x00, 0x00, 0x00, 0x00,       // crtc registers 8-15
+  0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, 0xff, // crtc registers 16-24
+  0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,       // attr registers 0-7
+  0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,       // attr registers 8-15
+  0x08, 0x00, 0x0f, 0x00, // attr registers 16-19
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x00, 0xff, // graphics registers 0-8
 // video parameter table for mode 3 (cga emulation)
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x50, 0x18, 0x08, 0x00, 0x10, // bios data
+  0x01, 0x03, 0x00, 0x02, // sequencer registers
+  0x63, // misc output registers
+  0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,       // crtc registers 0-7
+  0x00, 0xc7, 0x06, 0x07, 0x00, 0x00, 0x00, 0x00,       // crtc registers 8-15
+  0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, 0xff, // crtc registers 16-24
+  0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,       // attr registers 0-7
+  0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,       // attr registers 8-15
+  0x08, 0x00, 0x0f, 0x00, // attr registers 16-19
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x00, 0xff, // graphics registers 0-8
 // video parameter table for mode 4
   0x28, 0x18, 0x08, 0x00, 0x40, // bios data
   0x09, 0x00, 0x00, 0x02, // sequencer registers
@@ -239,25 +263,49 @@ static Bit8u video_parameter_table_vga[0x40*0x1d]={
   0x01, 0x00, 0x0f, 0x00, // attr registers 16-19
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff, // graphics registers 0-8
 // video parameter table for mode 0 (350 lines)
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x28, 0x18, 0x0e, 0x00, 0x08, // bios data
+  0x09, 0x03, 0x00, 0x02, // sequencer registers
+  0xa3, // misc output registers
+  0x2d, 0x27, 0x28, 0x90, 0x2b, 0xa0, 0xbf, 0x1f,       // crtc registers 0-7
+  0x00, 0x4d, 0x0b, 0x0c, 0x00, 0x00, 0x00, 0x00,       // crtc registers 8-15
+  0x83, 0x85, 0x5d, 0x14, 0x1f, 0x63, 0xba, 0xa3, 0xff, // crtc registers 16-24
+  0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07,       // attr registers 0-7
+  0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,       // attr registers 8-15
+  0x08, 0x00, 0x0f, 0x00, // attr registers 16-19
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x00, 0xff, // graphics registers 0-8
 // video parameter table for mode 1 (350 lines)
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x28, 0x18, 0x0e, 0x00, 0x08, // bios data
+  0x09, 0x03, 0x00, 0x02, // sequencer registers
+  0xa3, // misc output registers
+  0x2d, 0x27, 0x28, 0x90, 0x2b, 0xa0, 0xbf, 0x1f,       // crtc registers 0-7
+  0x00, 0x4d, 0x0b, 0x0c, 0x00, 0x00, 0x00, 0x00,       // crtc registers 8-15
+  0x83, 0x85, 0x5d, 0x14, 0x1f, 0x63, 0xba, 0xa3, 0xff, // crtc registers 16-24
+  0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07,       // attr registers 0-7
+  0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,       // attr registers 8-15
+  0x08, 0x00, 0x0f, 0x00, // attr registers 16-19
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x00, 0xff, // graphics registers 0-8
 // video parameter table for mode 2 (350 lines)
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x50, 0x18, 0x0e, 0x00, 0x10, // bios data
+  0x01, 0x03, 0x00, 0x02, // sequencer registers
+  0xa3, // misc output registers
+  0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,       // crtc registers 0-7
+  0x00, 0x4d, 0x0b, 0x0c, 0x00, 0x00, 0x00, 0x00,       // crtc registers 8-15
+  0x83, 0x85, 0x5d, 0x28, 0x1f, 0x63, 0xba, 0xa3, 0xff, // crtc registers 16-24
+  0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07,       // attr registers 0-7
+  0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,       // attr registers 8-15
+  0x08, 0x00, 0x0f, 0x00, // attr registers 16-19
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x00, 0xff, // graphics registers 0-8
 // video parameter table for mode 3 (350 lines)
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x50, 0x18, 0x0e, 0x00, 0x10, // bios data
+  0x01, 0x03, 0x00, 0x02, // sequencer registers
+  0xa3, // misc output registers
+  0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,       // crtc registers 0-7
+  0x00, 0x4d, 0x0b, 0x0c, 0x00, 0x00, 0x00, 0x00,       // crtc registers 8-15
+  0x83, 0x85, 0x5d, 0x28, 0x1f, 0x63, 0xba, 0xa3, 0xff, // crtc registers 16-24
+  0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07,       // attr registers 0-7
+  0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,       // attr registers 8-15
+  0x08, 0x00, 0x0f, 0x00, // attr registers 16-19
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x00, 0xff, // graphics registers 0-8
 // video parameter table for mode e
   0x28, 0x18, 0x10, 0x00, 0x08, // bios data
   0x08, 0x0f, 0x00, 0x07, // sequencer registers
@@ -328,25 +376,49 @@ static Bit8u video_parameter_table_vga[0x40*0x1d]={
 
 static Bit8u video_parameter_table_ega[0x40*0x17]={
 // video parameter table for mode 0 (cga emulation)
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x28, 0x18, 0x08, 0x00, 0x08, // bios data
+  0x0b, 0x03, 0x00, 0x03, // sequencer registers
+  0x23, // misc output registers
+  0x37, 0x27, 0x2d, 0x37, 0x31, 0x15, 0x04, 0x11,       // crtc registers 0-7
+  0x00, 0x07, 0x06, 0x07, 0x00, 0x00, 0x00, 0x00,       // crtc registers 8-15
+  0xe1, 0x24, 0xc7, 0x14, 0x08, 0xe0, 0xf0, 0xa3, 0xff, // crtc registers 16-24
+  0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,       // attr registers 0-7
+  0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,       // attr registers 8-15
+  0x08, 0x00, 0x0f, 0x00, // attr registers 16-19
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x00, 0xff, // graphics registers 0-8
 // video parameter table for mode 1 (cga emulation)
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x28, 0x18, 0x08, 0x00, 0x08, // bios data
+  0x0b, 0x03, 0x00, 0x03, // sequencer registers
+  0x23, // misc output registers
+  0x37, 0x27, 0x2d, 0x37, 0x31, 0x15, 0x04, 0x11,       // crtc registers 0-7
+  0x00, 0x07, 0x06, 0x07, 0x00, 0x00, 0x00, 0x00,       // crtc registers 8-15
+  0xe1, 0x24, 0xc7, 0x14, 0x08, 0xe0, 0xf0, 0xa3, 0xff, // crtc registers 16-24
+  0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,       // attr registers 0-7
+  0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,       // attr registers 8-15
+  0x08, 0x00, 0x0f, 0x00, // attr registers 16-19
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x00, 0xff, // graphics registers 0-8
 // video parameter table for mode 2 (cga emulation)
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x50, 0x18, 0x08, 0x00, 0x10, // bios data
+  0x01, 0x03, 0x00, 0x03, // sequencer registers
+  0x23, // misc output registers
+  0x70, 0x4f, 0x5c, 0x2f, 0x5f, 0x07, 0x04, 0x11,       // crtc registers 0-7
+  0x00, 0x07, 0x06, 0x07, 0x00, 0x00, 0x00, 0x00,       // crtc registers 8-15
+  0xe1, 0x24, 0xc7, 0x28, 0x08, 0xe0, 0xf0, 0xa3, 0xff, // crtc registers 16-24
+  0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,       // attr registers 0-7
+  0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,       // attr registers 8-15
+  0x08, 0x00, 0x0f, 0x00, // attr registers 16-19
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x00, 0xff, // graphics registers 0-8
 // video parameter table for mode 3 (cga emulation)
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x50, 0x18, 0x08, 0x00, 0x10, // bios data
+  0x01, 0x03, 0x00, 0x03, // sequencer registers
+  0x23, // misc output registers
+  0x70, 0x4f, 0x5c, 0x2f, 0x5f, 0x07, 0x04, 0x11,       // crtc registers 0-7
+  0x00, 0x07, 0x06, 0x07, 0x00, 0x00, 0x00, 0x00,       // crtc registers 8-15
+  0xe1, 0x24, 0xc7, 0x28, 0x08, 0xe0, 0xf0, 0xa3, 0xff, // crtc registers 16-24
+  0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,       // attr registers 0-7
+  0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,       // attr registers 8-15
+  0x08, 0x00, 0x0f, 0x00, // attr registers 16-19
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x00, 0xff, // graphics registers 0-8
 // video parameter table for mode 4
   0x28, 0x18, 0x08, 0x00, 0x40, // bios data
   0x09, 0x03, 0x00, 0x02, // sequencer registers
diff --git a/src/shell/shell_batch.cpp b/src/shell/shell_batch.cpp
index 74026d90..fae2555d 100644
--- a/src/shell/shell_batch.cpp
+++ b/src/shell/shell_batch.cpp
@@ -65,6 +65,13 @@ bool BatchFile::ReadLine(char * line) {
 		n=1;
 		DOS_ReadFile(file_handle,&c,&n);
 		if (n>0) {
+			if (c==0x1a) {
+				// Stop at EOF character
+				n=0;
+				this->location=0;
+				DOS_SeekFile(file_handle,&(this->location),DOS_SEEK_END);
+				break;
+			}
 			/* Why are we filtering this ?
 			 * Exclusion list: tab for batch files 
 			 * escape for ansi