Skip to content

Latest commit

 

History

History
5 lines (5 loc) · 434 Bytes

README.md

File metadata and controls

5 lines (5 loc) · 434 Bytes

NVMSA2017

This code is for our paper called "Runtime and reconfiguration dual-aware placement for SRAM-NVM hybrid FPGAs." In this code, we modified the open source tool called VTR to adapt for our experiments. Firstly, we make VTR adapt the emerging Non-volatile FPGA architecture by changing the input configuration codes; and we optimize the code of routing and placing algorithm to make VTR runtime and reconfiguration aware.