Add DR8 register to USART peripheral

Author: gpgreen

devices/common_patches/usart_dr8.yaml

@@ -0,0 +1,15 @@
+_add:
+  DR8:
+    description: Direct 8-bit access to data register
+    access: read-write
+    addressOffset: 0x4
+    alternateRegister: DR
+    size: 0x8
+    fields:
+      DR:
+        bitOffset: 0
+        bitWidth: 8
+        description: Data register
+
+DR8:
+  DR: [0, 0xFF]

devices/py32f002a.yaml

@@ -4,6 +4,10 @@ _svd: ../svd/py32f002a.svd
   _include:
     - common_patches/spi_dr8.yaml
 
+"USART*":
+  _include:
+    - common_patches/usart_dr8.yaml
+
 _include:
  - ./common_patches/pwr_f002a.yaml
  - ./common_patches/syscfg_f002a.yaml

devices/py32f002b.yaml

@@ -4,6 +4,10 @@ _svd: ../svd/py32f002b.svd
   _include:
     - common_patches/spi_dr8.yaml
 
+"USART*":
+  _include:
+    - common_patches/usart_dr8.yaml
+
 _include:
  - ./common_patches/syscfg_f002b.yaml
  - ../peripherals/flash/flash_f002b.yaml

devices/py32f003.yaml

@@ -4,6 +4,10 @@ _svd: ../svd/py32f003.svd
   _include:
     - common_patches/spi_dr8.yaml
 
+"USART*":
+  _include:
+    - common_patches/usart_dr8.yaml
+
 _include:
  - ../peripherals/flash/flash_f0.yaml
  - ../peripherals/pwr/pwr_f0.yaml

devices/py32f030.yaml

@@ -4,6 +4,10 @@ _svd: ../svd/py32f030.svd
   _include:
     - common_patches/spi_dr8.yaml
 
+"USART*":
+  _include:
+    - common_patches/usart_dr8.yaml
+
 _include:
  - ../peripherals/flash/flash_f0.yaml
  - ../peripherals/pwr/pwr_f0.yaml