All notable changes to this project will be documented in this file.
The format is based on Keep a Changelog and this project adheres to Semantic Versioning.
- Waive Verilator linter for lints not matching our code style
tc_sram_xilinx: Fix be assignment
tc_sram_xilinx: Support ByteWidth != 8
tc_clk_or2: A new generic tech cell for balanced clock OR-gates.tc_clk_mux2: Added warning about misusingtc_clk_mux2cells.
tc_sram_impl: Wrapper fortc_sramwith implementation-specific keys and IO
tc_sram: Improve simulation performance
tc_clk_xilinx: AddIS_FUNCTIONALparameter to matchtc_clk_gatinginterface
- Added optional
IS_FUNCTIONALflag totc_clk_gatingcell to optionally mark them as not required for functionality.
Skipped
Skipped
- Add
pad_functional_xilinx
- Bender targets
- Deprecated xilinx
clk_cells replaced by wrappers
Skipped
- Add
deprecated/pulp_clk_cells_xilinx.svtoBender.yml
tc_sram_xilinx: Remove unsupportedstringtype fromSimInitparameter.IPApproX:Addtc_sramtosrc_files.ymlfor proper compilation with IPApproX
Bender:Add deprecatedpulp_clock_gating_asyncfor compatibility toudma_core.
Bender:Addrtl/tc_sramto targetrtl, to prevent overwriting of target specific implementations.
tc_sram: Drop string literal from parameterSimInitdefinition as synopsys throws an elaboration error.tc_clk:tc_clk_delay: Add Verilator and synthesis guards.
- Add
tc_sramandtc_sram_xilinx, with testbench for verifying technology specific implementations.
- Add Readme
- Add Contribution Guide
- Move modules of similar topic to a single file. This makes it easier to add new modules.
- Move separation between
clusterandpulptodeprecatedfolder. There should be a single solution to a tech-cell.
- Polish release
- Keep Changelog
- Move to sources subfolder
- Initial commit.