[WIP] Fix xbar routing

For some reasons to be fully grasped, the AXI xbar generates ports with
different endianness than the connection we, i.e., we connect the first
xbar output ([0]) to tcdm, but in turns out the port carrying the
information is [2]

Author: alex96295

rtl/cluster_bus_wrap.sv

@@ -101,12 +101,12 @@ module cluster_bus_wrap
   master_resp_t [NB_MASTER-1:0] axi_master_resps;
 
   // assign here your axi masters
-  `AXI_ASSIGN_REQ_STRUCT(tcdm_master_req_o, axi_master_reqs[0])
-  `AXI_ASSIGN_RESP_STRUCT(axi_master_resps[0], tcdm_master_resp_i)
+  `AXI_ASSIGN_REQ_STRUCT(tcdm_master_req_o, axi_master_reqs[2])
+  `AXI_ASSIGN_RESP_STRUCT(axi_master_resps[2], tcdm_master_resp_i)
   `AXI_ASSIGN_REQ_STRUCT(periph_master_req_o, axi_master_reqs[1])
   `AXI_ASSIGN_RESP_STRUCT(axi_master_resps[1], periph_master_resp_i)
-  `AXI_ASSIGN_REQ_STRUCT(ext_master_req_o, axi_master_reqs[2])
-  `AXI_ASSIGN_RESP_STRUCT(axi_master_resps[2], ext_master_resp_i)
+  `AXI_ASSIGN_REQ_STRUCT(ext_master_req_o, axi_master_reqs[0])
+  `AXI_ASSIGN_RESP_STRUCT(axi_master_resps[0], ext_master_resp_i)
 
   // Address Map Rule
   typedef struct packed {