fix printing from all cores

Author: da-gazzi

tb/mock_uart.sv

@@ -60,7 +60,7 @@ module mock_uart  #(
 
     function void uart_tx(byte ch);
         if(ch==8'h0A) begin
-          $display("[TB UART] %s", stringa);        
+          $display("[TB UART %2d] %s", UART_IDX, stringa);        
           charnum = 0;
           stringa = '0;
         end else begin

tb/mock_uart_axi.sv

@@ -16,22 +16,25 @@ module mock_uart_axi #(
   parameter int unsigned AxiIw = 0,
   parameter int unsigned AxiAw = 0,
   parameter int unsigned AxiDw = 0,
-  parameter int unsigned AxiUw = 0
+  parameter int unsigned AxiUw = 0,
+  parameter logic [AxiAw-1:0] BaseAddr = 0,
+  parameter int unsigned N_CORES = 8
+
   )(
     input logic      clk_i,
     input logic      rst_ni,
     input logic      test_i,
     AXI_BUS.Slave    uart
  );
-   
-  logic         uart_penable;
-  logic         uart_pwrite;
-  logic [AxiAw-1:0]  uart_paddr;
-  logic         uart_psel;
-  logic [31:0]  uart_pwdata;
-  logic [31:0]  uart_prdata;
-  logic         uart_pready;
-  logic         uart_pslverr;
+
+  logic                      uart_penable;
+  logic                      uart_pwrite;
+  logic [AxiAw-1:0]          uart_paddr;
+  logic [N_CORES-1:0]        uart_psel;
+  logic               [31:0] uart_pwdata;
+  logic [N_CORES-1:0] [31:0] uart_prdata;
+  logic [N_CORES-1:0]        uart_pready;
+  logic [N_CORES-1:0]        uart_pslverr;
 
   AXI_LITE #(
     .AXI_DATA_WIDTH(AxiDw),
@@ -77,12 +80,15 @@ module mock_uart_axi #(
     logic [AxiAw-1:0] end_addr;
   } rule_t;
 
-  rule_t [0:0] rule;
-  assign rule[0] = '{0, '0, '1};
-  
+  rule_t [0:N_CORES-1] rule;
+  // each mock UART only has 2 words of address space
+  for (genvar g=0; g<N_CORES; g++) begin
+    assign rule[g] = '{g, BaseAddr + 8*g, BaseAddr + 8*(g+1)-1};
+  end
+
   axi_lite_to_apb_intf #(
-    .NoApbSlaves     (1),
-    .NoRules         (1),
+    .NoApbSlaves     (N_CORES),
+    .NoRules         (N_CORES),
     .AddrWidth       (AxiAw),
     .DataWidth       (32),
     .PipelineRequest (1'b0),
@@ -106,17 +112,22 @@ module mock_uart_axi #(
   );
 
   /* pragma translate_off */
-  mock_uart i_mock_uart0 (
-      .clk_i     ( clk_i        ),
-      .rst_ni    ( rst_ni       ),
-      .penable_i ( uart_penable ),
-      .pwrite_i  ( uart_pwrite  ),
-      .paddr_i   ( uart_paddr[31:0]   ),
-      .psel_i    ( uart_psel    ),
-      .pwdata_i  ( uart_pwdata  ),
-      .prdata_o  ( uart_prdata  ),
-      .pready_o  ( uart_pready  ),
-      .pslverr_o ( uart_pslverr )
- );
+  for (genvar g=0; g<N_CORES; g++) begin
+    // one mock UART per core
+    mock_uart #(
+      .UART_IDX( g )
+    ) i_mock_uart0 (
+      .clk_i    ( clk_i                  ),
+      .rst_ni   ( rst_ni                 ),
+      .penable_i( uart_penable           ),
+      .pwrite_i ( uart_pwrite            ),
+      .paddr_i  ( uart_paddr[31:0] - g*8 ), // Mock UART expects to be addressed starting at 0
+      .psel_i   ( uart_psel[g]           ),
+      .pwdata_i ( uart_pwdata            ),
+      .prdata_o ( uart_prdata[g]         ),
+      .pready_o ( uart_pready[g]         ),
+      .pslverr_o( uart_pslverr[g]        )
+    );
+  end
 
 endmodule

tb/pulp_cluster_tb.sv

@@ -176,10 +176,12 @@ module pulp_cluster_tb;
   );
 
   mock_uart_axi #(
-   .AxiIw ( AxiIwMst ),
-   .AxiAw ( AxiAw    ),
-   .AxiDw ( AxiDw    ),
-   .AxiUw ( AxiUw    )
+   .AxiIw   ( AxiIwMst      ),
+   .AxiAw   ( AxiAw         ),
+   .AxiDw   ( AxiDw         ),
+   .AxiUw   ( AxiUw         ),
+   .N_CORES ( 8             ),
+   .BaseAddr( 32'h4000_0000 )
   ) i_mock_uart (
      .clk_i  ( s_clk         ),
      .rst_ni ( s_rstn        ),