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DanielKellerMDanielKellerM
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Refactor dmac_wrap instantiation to support both wide and narrow port configurations based on WidePortShouldBeEnabled. Update AXI request/response handling and introduce a multiplexer for merging cluster bus and DMA narrow master requests. Enhance isolation and CDC instantiation for wide port scenarios.
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‎rtl/pulp_cluster.sv‎

Lines changed: 217 additions & 143 deletions
Original file line numberDiff line numberDiff line change
@@ -806,50 +806,97 @@ cluster_interconnect_wrap #(
806806
//***************************************************
807807
//*********************DMAC WRAP*********************
808808
//***************************************************
809-
dmac_wrap #(
810-
.NB_CORES ( Cfg.NumCores ),
811-
.NB_OUTSND_BURSTS ( Cfg.DmaNumOutstandingBursts ),
812-
.AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ),
813-
.AXI_DATA_WIDTH ( WidePortShouldBeEnabled ? Cfg.AxiDataOutWideWidth : Cfg.AxiDataOutWidth ),
814-
.AXI_ID_WIDTH ( WidePortShouldBeEnabled ? Cfg.AxiIdOutWideWidth : AxiIdOutWidth ),
815-
.AXI_USER_WIDTH ( Cfg.AxiUserWidth ),
816-
.PE_ID_WIDTH ( Cfg.NumCores + 1 ),
817-
.DATA_WIDTH ( DataWidth ),
818-
.ADDR_WIDTH ( AddrWidth ),
819-
.BE_WIDTH ( BeWidth ),
820-
.axi_req_t ( WidePortShouldBeEnabled ? c2s_wide_req_t : c2s_out_int_req_t ),
821-
.axi_resp_t ( WidePortShouldBeEnabled ? c2s_wide_resp_t : c2s_out_int_resp_t ),
822-
`ifdef TARGET_MCHAN
823-
.NB_CTRLS ( Cfg.NumCores + 2 ),
824-
.MCHAN_BURST_LENGTH ( Cfg.DmaBurstLength ),
825-
.TCDM_ADD_WIDTH ( TcdmAddrWidth )
826-
`else
827-
.NB_PE_PORTS ( 2 ),
828-
.NUM_BIDIR_STREAMS ( 1 ),
829-
.GLOBAL_QUEUE_DEPTH ( 2 ),
830-
.MUX_READ ( 1'b1 ),
831-
.TCDM_MEM2BANKS ( !Cfg.DmaUseHwpePort )
832-
`endif
833-
) dmac_wrap_i (
834-
.clk_i ( clk_i ),
835-
.rst_ni ( rst_ni ),
836-
.test_mode_i ( test_mode_i ),
837-
.pe_ctrl_slave ( s_periph_dma_bus[1:0] ),
838-
.ctrl_slave ( s_core_dmactrl_bus ),
839-
.tcdm_master ( s_hci_dma ),
840-
`ifdef TARGET_MCHAN
841-
.ext_master_req_o ( /* MCHAN uses narrow port - not connected to wide */ ),
842-
.ext_master_resp_i ( '0 ),
843-
`else
844-
.ext_master_req_o ( WidePortShouldBeEnabled ? {s_dma_master_req} : {s_dma_narrow_master_req} ),
845-
.ext_master_resp_i ( WidePortShouldBeEnabled ? {s_dma_master_resp} : {s_dma_narrow_master_resp} ),
846-
`endif
847-
.term_event_o ( s_dma_event ),
848-
.term_irq_o ( s_dma_irq ),
849-
.term_event_pe_o ( {s_dma_fc_event, s_dma_cl_event} ),
850-
.term_irq_pe_o ( {s_dma_fc_irq, s_dma_cl_irq} ),
851-
.busy_o ( s_dmac_busy )
852-
);
809+
if (WidePortShouldBeEnabled) begin : gen_wide_port_idma
810+
dmac_wrap #(
811+
.NB_CORES ( Cfg.NumCores ),
812+
.NB_OUTSND_BURSTS ( Cfg.DmaNumOutstandingBursts ),
813+
.AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ),
814+
.AXI_DATA_WIDTH ( Cfg.AxiDataOutWideWidth ),
815+
.AXI_ID_WIDTH ( Cfg.AxiIdOutWideWidth ),
816+
.AXI_USER_WIDTH ( Cfg.AxiUserWidth ),
817+
.PE_ID_WIDTH ( Cfg.NumCores + 1 ),
818+
.DATA_WIDTH ( DataWidth ),
819+
.ADDR_WIDTH ( AddrWidth ),
820+
.BE_WIDTH ( BeWidth ),
821+
.axi_req_t ( c2s_wide_req_t ),
822+
.axi_resp_t ( c2s_wide_resp_t ),
823+
`ifdef TARGET_MCHAN
824+
.NB_CTRLS ( Cfg.NumCores + 2 ),
825+
.MCHAN_BURST_LENGTH ( Cfg.DmaBurstLength ),
826+
.TCDM_ADD_WIDTH ( TcdmAddrWidth )
827+
`else
828+
.NB_PE_PORTS ( 2 ),
829+
.NUM_BIDIR_STREAMS ( 1 ),
830+
.GLOBAL_QUEUE_DEPTH ( 2 ),
831+
.MUX_READ ( 1'b1 ),
832+
.TCDM_MEM2BANKS ( !Cfg.DmaUseHwpePort )
833+
`endif
834+
) dmac_wrap_i (
835+
.clk_i ( clk_i ),
836+
.rst_ni ( rst_ni ),
837+
.test_mode_i ( test_mode_i ),
838+
.pe_ctrl_slave ( s_periph_dma_bus[1:0] ),
839+
.ctrl_slave ( s_core_dmactrl_bus ),
840+
.tcdm_master ( s_hci_dma ),
841+
`ifdef TARGET_MCHAN
842+
.ext_master_req_o ( /* MCHAN uses narrow port - not connected to wide */ ),
843+
.ext_master_resp_i ( '0 ),
844+
`else
845+
.ext_master_req_o ( {s_dma_narrow_master_req} ),
846+
.ext_master_resp_i ( {s_dma_narrow_master_resp} ),
847+
`endif
848+
.term_event_o ( s_dma_event ),
849+
.term_irq_o ( s_dma_irq ),
850+
.term_event_pe_o ( {s_dma_fc_event, s_dma_cl_event} ),
851+
.term_irq_pe_o ( {s_dma_fc_irq, s_dma_cl_irq} ),
852+
.busy_o ( s_dmac_busy )
853+
);
854+
end else begin : gen_narrow_port_idma
855+
dmac_wrap #(
856+
.NB_CORES ( Cfg.NumCores ),
857+
.NB_OUTSND_BURSTS ( Cfg.DmaNumOutstandingBursts ),
858+
.AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ),
859+
.AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ),
860+
.AXI_ID_WIDTH ( AxiIdOutWidth ),
861+
.AXI_USER_WIDTH ( Cfg.AxiUserWidth ),
862+
.PE_ID_WIDTH ( Cfg.NumCores + 1 ),
863+
.DATA_WIDTH ( DataWidth ),
864+
.ADDR_WIDTH ( AddrWidth ),
865+
.BE_WIDTH ( BeWidth ),
866+
.axi_req_t ( c2s_out_int_req_t ),
867+
.axi_resp_t ( c2s_out_int_resp_t ),
868+
`ifdef TARGET_MCHAN
869+
.NB_CTRLS ( Cfg.NumCores + 2 ),
870+
.MCHAN_BURST_LENGTH ( Cfg.DmaBurstLength ),
871+
.TCDM_ADD_WIDTH ( TcdmAddrWidth )
872+
`else
873+
.NB_PE_PORTS ( 2 ),
874+
.NUM_BIDIR_STREAMS ( 1 ),
875+
.GLOBAL_QUEUE_DEPTH ( 2 ),
876+
.MUX_READ ( 1'b1 ),
877+
.TCDM_MEM2BANKS ( !Cfg.DmaUseHwpePort )
878+
`endif
879+
) dmac_wrap_i (
880+
.clk_i ( clk_i ),
881+
.rst_ni ( rst_ni ),
882+
.test_mode_i ( test_mode_i ),
883+
.pe_ctrl_slave ( s_periph_dma_bus[1:0] ),
884+
.ctrl_slave ( s_core_dmactrl_bus ),
885+
.tcdm_master ( s_hci_dma ),
886+
`ifdef TARGET_MCHAN
887+
.ext_master_req_o ( /* MCHAN uses narrow port - not connected to wide */ ),
888+
.ext_master_resp_i ( '0 ),
889+
`else
890+
.ext_master_req_o ( {s_dma_narrow_master_req} ),
891+
.ext_master_resp_i ( {s_dma_narrow_master_resp} ),
892+
`endif
893+
.term_event_o ( s_dma_event ),
894+
.term_irq_o ( s_dma_irq ),
895+
.term_event_pe_o ( {s_dma_fc_event, s_dma_cl_event} ),
896+
.term_irq_pe_o ( {s_dma_fc_irq, s_dma_cl_irq} ),
897+
.busy_o ( s_dmac_busy )
898+
);
899+
end
853900

854901

855902
//***************************************************
@@ -1686,54 +1733,76 @@ c2s_remap_resp_t src_remap_resp;
16861733

16871734
// Connect DMA narrow master when wide port disabled, otherwise cluster bus master
16881735
if (WidePortShouldBeEnabled) begin : gen_cluster_bus_narrow_master
1689-
`AXI_ASSIGN_REQ_STRUCT(src_remap_req,s_data_master_req)
1690-
`AXI_ASSIGN_RESP_STRUCT(s_data_master_resp,src_remap_resp)
1736+
`AXI_ASSIGN_REQ_STRUCT(src_remap_req, s_data_master_req)
1737+
`AXI_ASSIGN_RESP_STRUCT(s_data_master_resp, src_remap_resp)
16911738
end else begin : gen_dma_narrow_master
1692-
// Merge cluster bus master and DMA narrow master
1693-
c2s_remap_req_t [1:0] narrow_master_reqs;
1739+
// Merge cluster bus master and DMA narrow master via AXI multiplexer
1740+
localparam int SlvIdWidth = AxiIdOutWidth;
1741+
localparam int MstIdWidth = AxiIdOutWidth + 1;
1742+
1743+
// Widened AW channel for mux output
1744+
`AXI_TYPEDEF_AW_CHAN_T(c2s_mux_aw_chan_t, logic[Cfg.AxiAddrWidth-1:0], logic[MstIdWidth-1:0], logic[Cfg.AxiUserWidth-1:0])
1745+
`AXI_TYPEDEF_W_CHAN_T(c2s_mux_w_chan_t, logic[Cfg.AxiDataOutWidth-1:0], logic[Cfg.AxiDataOutWidth/8-1:0], logic[Cfg.AxiUserWidth-1:0])
1746+
`AXI_TYPEDEF_B_CHAN_T(c2s_mux_b_chan_t, logic[MstIdWidth-1:0], logic[Cfg.AxiUserWidth-1:0])
1747+
`AXI_TYPEDEF_AR_CHAN_T(c2s_mux_ar_chan_t, logic[Cfg.AxiAddrWidth-1:0], logic[MstIdWidth-1:0], logic[Cfg.AxiUserWidth-1:0])
1748+
`AXI_TYPEDEF_R_CHAN_T(c2s_mux_r_chan_t, logic[Cfg.AxiDataOutWidth-1:0], logic[MstIdWidth-1:0], logic[Cfg.AxiUserWidth-1:0])
1749+
1750+
`AXI_TYPEDEF_REQ_T(c2s_mux_req_t, c2s_mux_aw_chan_t, c2s_mux_w_chan_t, c2s_mux_ar_chan_t)
1751+
`AXI_TYPEDEF_RESP_T(c2s_mux_resp_t, c2s_mux_b_chan_t, c2s_mux_r_chan_t)
1752+
1753+
// Arrays for the two slave ports
1754+
c2s_remap_req_t [1:0] narrow_master_reqs;
16941755
c2s_remap_resp_t [1:0] narrow_master_resps;
1695-
1696-
`AXI_ASSIGN_REQ_STRUCT(narrow_master_reqs[0],s_data_master_req) // Cluster bus
1697-
`AXI_ASSIGN_REQ_STRUCT(narrow_master_reqs[1],s_dma_narrow_master_req) // DMA narrow
1698-
`AXI_ASSIGN_RESP_STRUCT(s_data_master_resp,narrow_master_resps[0])
1699-
`AXI_ASSIGN_RESP_STRUCT(s_dma_narrow_master_resp,narrow_master_resps[1])
1700-
1701-
// Simple AXI crossbar to merge two narrow masters
1702-
axi_xbar #(
1703-
.Cfg ( '{
1704-
NoSlvPorts: 2,
1705-
NoMstPorts: 1,
1706-
MaxMstTrans: 4,
1707-
MaxSlvTrans: 4,
1708-
FallThrough: 1'b0,
1709-
LatencyMode: axi_pkg::CUT_ALL_AX,
1710-
PipelineStages: 0,
1711-
AxiIdWidthSlvPorts: AxiIdOutWidth,
1712-
AxiIdUsedSlvPorts: AxiIdOutWidth,
1713-
UniqueIds: 1'b1,
1714-
AxiAddrWidth: Cfg.AxiAddrWidth,
1715-
AxiDataWidth: Cfg.AxiDataOutWidth,
1716-
NoAddrRules: 1
1717-
} ),
1718-
.ATOPs ( 1'b1 ),
1719-
.Connectivity ( '1 ),
1720-
.slv_req_t ( c2s_remap_req_t ),
1721-
.slv_resp_t ( c2s_remap_resp_t ),
1722-
.mst_req_t ( c2s_remap_req_t ),
1723-
.mst_resp_t ( c2s_remap_resp_t ),
1724-
.rule_t ( axi_pkg::xbar_rule_32_t )
1725-
) i_narrow_master_xbar (
1726-
.clk_i ( clk_i ),
1727-
.rst_ni ( rst_ni ),
1728-
.test_i ( test_mode_i ),
1729-
.slv_ports_req_i ( narrow_master_reqs ),
1730-
.slv_ports_resp_o( narrow_master_resps ),
1731-
.mst_ports_req_o ( src_remap_req ),
1732-
.mst_ports_resp_i( src_remap_resp ),
1733-
.addr_map_i ( '{'{idx: 0, start_addr: '0, end_addr: '1}} ),
1734-
.en_default_mst_port_i( '1 ),
1735-
.default_mst_port_i ( '0 )
1756+
c2s_mux_req_t mux_req;
1757+
c2s_mux_resp_t mux_resp;
1758+
1759+
// Bind cluster-bus and DMA inputs
1760+
`AXI_ASSIGN_REQ_STRUCT(narrow_master_reqs[0], s_data_master_req)
1761+
`AXI_ASSIGN_REQ_STRUCT(narrow_master_reqs[1], s_dma_narrow_master_req)
1762+
1763+
// 2-to-1 AXI multiplexer (prepending ID bit)
1764+
axi_mux #(
1765+
.SlvAxiIDWidth ( AxiIdOutWidth ),
1766+
.slv_aw_chan_t ( c2s_remap_aw_chan_t ), .mst_aw_chan_t ( c2s_mux_aw_chan_t ),
1767+
.w_chan_t ( c2s_remap_w_chan_t ),
1768+
.slv_b_chan_t ( c2s_remap_b_chan_t ), .mst_b_chan_t ( c2s_mux_b_chan_t ),
1769+
.slv_ar_chan_t ( c2s_remap_ar_chan_t ), .mst_ar_chan_t ( c2s_mux_ar_chan_t ),
1770+
.slv_r_chan_t ( c2s_remap_r_chan_t ), .mst_r_chan_t ( c2s_mux_r_chan_t ),
1771+
.slv_req_t ( c2s_remap_req_t ), .slv_resp_t ( c2s_remap_resp_t ),
1772+
.mst_req_t ( c2s_mux_req_t ), .mst_resp_t ( c2s_mux_resp_t ),
1773+
.NoSlvPorts ( 2 ), .FallThrough(1'b1)
1774+
) i_idma_narrow_mux (
1775+
.clk_i ( clk_i ),
1776+
.rst_ni ( rst_ni ),
1777+
.test_i ( test_mode_i ),
1778+
// Inputs: cluster-bus first, then DMA narrow
1779+
.slv_reqs_i ( narrow_master_reqs ),
1780+
.slv_resps_o ( narrow_master_resps ),
1781+
// Output of mux feeds ID shrink stage
1782+
.mst_req_o ( mux_req ),
1783+
.mst_resp_i ( mux_resp )
1784+
);
1785+
1786+
axi_id_remap #(
1787+
.AxiSlvPortIdWidth ( MstIdWidth ), // ID width = AxiIdOutWidth + 1
1788+
.AxiSlvPortMaxUniqIds ( 4 ),
1789+
.AxiMaxTxnsPerId ( Cfg.AxiMaxOutTrans ),
1790+
.AxiMstPortIdWidth ( AxiIdOutWidth ),
1791+
.slv_req_t ( c2s_mux_req_t ),
1792+
.slv_resp_t ( c2s_mux_resp_t ),
1793+
.mst_req_t ( c2s_remap_req_t ),
1794+
.mst_resp_t ( c2s_remap_resp_t )
1795+
) i_idma_narrow_id_shrink (
1796+
.clk_i ( clk_i ),
1797+
.rst_ni ( rst_ni ),
1798+
.slv_req_i ( mux_req ),
1799+
.slv_resp_o ( mux_resp ),
1800+
.mst_req_o ( src_remap_req ),
1801+
.mst_resp_i ( src_remap_resp )
17361802
);
1803+
// Drive external responses from narrow_master_resps
1804+
`AXI_ASSIGN_RESP_STRUCT(s_data_master_resp, narrow_master_resps[0])
1805+
`AXI_ASSIGN_RESP_STRUCT(s_dma_narrow_master_resp, narrow_master_resps[1])
17371806
end
17381807

17391808
if (Cfg.AxiIdOutWidth != AxiIdOutWidth) begin : gen_c2s_idwremap
@@ -1816,62 +1885,67 @@ axi_cdc_src #(
18161885
c2s_wide_req_t src_wide_req, isolate_src_wide_req;
18171886
c2s_wide_resp_t src_wide_resp, isolate_src_wide_resp;
18181887

1819-
assign isolate_src_wide_req = s_dma_master_req;
1820-
assign s_dma_master_resp = isolate_src_wide_resp;
1888+
// Route DMA master request/response based on WidePortShouldBeEnabled
1889+
assign isolate_src_wide_req = WidePortShouldBeEnabled ? s_dma_master_req : s_dma_narrow_master_req;
1890+
assign s_dma_master_resp = WidePortShouldBeEnabled ? isolate_src_wide_resp : s_dma_narrow_master_resp;
18211891

1822-
axi_isolate #(
1823-
.NumPending ( 8 ),
1824-
.TerminateTransaction ( 1 ),
1825-
.AtopSupport ( 1 ),
1826-
.AxiAddrWidth ( Cfg.AxiAddrWidth ),
1827-
.AxiDataWidth ( Cfg.AxiDataOutWideWidth ),
1828-
.AxiIdWidth ( Cfg.AxiIdOutWideWidth ),
1829-
.AxiUserWidth ( Cfg.AxiUserWidth ),
1830-
.axi_req_t ( c2s_wide_req_t ),
1831-
.axi_resp_t ( c2s_wide_resp_t )
1832-
) i_axi_wide_master_isolate (
1833-
.clk_i ( clk_i ),
1834-
.rst_ni ( rst_ni ),
1835-
.slv_req_i ( isolate_src_wide_req ),
1836-
.slv_resp_o ( isolate_src_wide_resp ),
1837-
.mst_req_o ( src_wide_req ),
1838-
.mst_resp_i ( src_wide_resp ),
1839-
.isolate_i ( axi_isolate_synch ),
1840-
.isolated_o ( axi_isolated_wide_o )
1841-
);
1842-
1843-
axi_cdc_src #(
1844-
.aw_chan_t ( c2s_wide_aw_chan_t ),
1845-
.w_chan_t ( c2s_wide_w_chan_t ),
1846-
.b_chan_t ( c2s_wide_b_chan_t ),
1847-
.r_chan_t ( c2s_wide_r_chan_t ),
1848-
.ar_chan_t ( c2s_wide_ar_chan_t ),
1849-
.axi_req_t ( c2s_wide_req_t ),
1850-
.axi_resp_t ( c2s_wide_resp_t ),
1851-
.LogDepth ( Cfg.AxiCdcLogDepth ),
1852-
.SyncStages ( Cfg.AxiCdcSyncStages )
1853-
) axi_wide_master_cdc_i (
1854-
.src_rst_ni ( pwr_on_rst_ni ),
1855-
.src_clk_i ( clk_i ),
1856-
.src_req_i ( src_wide_req ),
1857-
.src_resp_o ( src_wide_resp ),
1858-
.async_data_master_aw_wptr_o ( async_wide_master_aw_wptr_o ),
1859-
.async_data_master_aw_rptr_i ( async_wide_master_aw_rptr_i ),
1860-
.async_data_master_aw_data_o ( async_wide_master_aw_data_o ),
1861-
.async_data_master_w_wptr_o ( async_wide_master_w_wptr_o ),
1862-
.async_data_master_w_rptr_i ( async_wide_master_w_rptr_i ),
1863-
.async_data_master_w_data_o ( async_wide_master_w_data_o ),
1864-
.async_data_master_ar_wptr_o ( async_wide_master_ar_wptr_o ),
1865-
.async_data_master_ar_rptr_i ( async_wide_master_ar_rptr_i ),
1866-
.async_data_master_ar_data_o ( async_wide_master_ar_data_o ),
1867-
.async_data_master_b_wptr_i ( async_wide_master_b_wptr_i ),
1868-
.async_data_master_b_rptr_o ( async_wide_master_b_rptr_o ),
1869-
.async_data_master_b_data_i ( async_wide_master_b_data_i ),
1870-
.async_data_master_r_wptr_i ( async_wide_master_r_wptr_i ),
1871-
.async_data_master_r_rptr_o ( async_wide_master_r_rptr_o ),
1872-
.async_data_master_r_data_i ( async_wide_master_r_data_i )
1873-
);
1892+
// Instantiate wide port isolation and CDC only when enabled
1893+
generate
1894+
if (WidePortShouldBeEnabled) begin : gen_wide_port
1895+
axi_isolate #(
1896+
.NumPending ( 8 ),
1897+
.TerminateTransaction ( 1 ),
1898+
.AtopSupport ( 1 ),
1899+
.AxiAddrWidth ( Cfg.AxiAddrWidth ),
1900+
.AxiDataWidth ( Cfg.AxiDataOutWideWidth ),
1901+
.AxiIdWidth ( Cfg.AxiIdOutWideWidth ),
1902+
.AxiUserWidth ( Cfg.AxiUserWidth ),
1903+
.axi_req_t ( c2s_wide_req_t ),
1904+
.axi_resp_t ( c2s_wide_resp_t )
1905+
) i_axi_wide_master_isolate (
1906+
.clk_i ( clk_i ),
1907+
.rst_ni ( rst_ni ),
1908+
.slv_req_i ( isolate_src_wide_req ),
1909+
.slv_resp_o ( isolate_src_wide_resp ),
1910+
.mst_req_o ( src_wide_req ),
1911+
.mst_resp_i ( src_wide_resp ),
1912+
.isolate_i ( axi_isolate_synch ),
1913+
.isolated_o ( axi_isolated_wide_o )
1914+
);
18741915

1916+
axi_cdc_src #(
1917+
.aw_chan_t ( c2s_wide_aw_chan_t ),
1918+
.w_chan_t ( c2s_wide_w_chan_t ),
1919+
.b_chan_t ( c2s_wide_b_chan_t ),
1920+
.r_chan_t ( c2s_wide_r_chan_t ),
1921+
.ar_chan_t ( c2s_wide_ar_chan_t ),
1922+
.axi_req_t ( c2s_wide_req_t ),
1923+
.axi_resp_t ( c2s_wide_resp_t ),
1924+
.LogDepth ( Cfg.AxiCdcLogDepth ),
1925+
.SyncStages ( Cfg.AxiCdcSyncStages )
1926+
) axi_wide_master_cdc_i (
1927+
.src_rst_ni ( pwr_on_rst_ni ),
1928+
.src_clk_i ( clk_i ),
1929+
.src_req_i ( src_wide_req ),
1930+
.src_resp_o ( src_wide_resp ),
1931+
.async_data_master_aw_wptr_o ( async_wide_master_aw_wptr_o ),
1932+
.async_data_master_aw_rptr_i ( async_wide_master_aw_rptr_i ),
1933+
.async_data_master_aw_data_o ( async_wide_master_aw_data_o ),
1934+
.async_data_master_w_wptr_o ( async_wide_master_w_wptr_o ),
1935+
.async_data_master_w_rptr_i ( async_wide_master_w_rptr_i ),
1936+
.async_data_master_w_data_o ( async_wide_master_w_data_o ),
1937+
.async_data_master_ar_wptr_o ( async_wide_master_ar_wptr_o ),
1938+
.async_data_master_ar_rptr_i ( async_wide_master_ar_rptr_i ),
1939+
.async_data_master_ar_data_o ( async_wide_master_ar_data_o ),
1940+
.async_data_master_b_wptr_i ( async_wide_master_b_wptr_i ),
1941+
.async_data_master_b_rptr_o ( async_wide_master_b_rptr_o ),
1942+
.async_data_master_b_data_i ( async_wide_master_b_data_i ),
1943+
.async_data_master_r_wptr_i ( async_wide_master_r_wptr_i ),
1944+
.async_data_master_r_rptr_o ( async_wide_master_r_rptr_o ),
1945+
.async_data_master_r_data_i ( async_wide_master_r_data_i )
1946+
);
1947+
end
1948+
endgenerate
18751949

18761950
// SOC TO CLUSTER
18771951
`AXI_TYPEDEF_AW_CHAN_T(s2c_aw_chan_t,logic[Cfg.AxiAddrWidth-1:0],logic[Cfg.AxiIdInWidth-1:0],logic[Cfg.AxiUserWidth-1:0])

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