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LuigiGhiondaLuigiGhionda
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Split AXI structs to fix axi_id_remap use
1 parent 861d02c commit 0cb948a

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+113
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‎rtl/pulp_cluster.sv‎

Lines changed: 113 additions & 94 deletions
Original file line numberDiff line numberDiff line change
@@ -443,76 +443,76 @@ hci_core_intf #(
443443
.clk ( clk_i )
444444
);
445445

446+
// ***********************************************************************************************+
447+
// ***********************************************************************************************+
448+
// ***********************************************************************************************+
449+
// ***********************************************************************************************+
450+
// ***********************************************************************************************+
451+
452+
//***************************************************
453+
/* synchronous AXI interfaces internal to the cluster */
454+
//***************************************************
455+
446456
// SOC TO CLUSTER
447-
`AXI_TYPEDEF_AW_CHAN_T(s2c_aw_chan_t,logic[Cfg.AxiAddrWidth-1:0],logic[Cfg.AxiIdInWidth-1:0],logic[Cfg.AxiUserWidth-1:0])
448-
`AXI_TYPEDEF_W_CHAN_T(s2c_w_chan_t,logic[Cfg.AxiDataInWidth-1:0],logic[Cfg.AxiDataInWidth/8-1:0],logic[Cfg.AxiUserWidth-1:0])
449-
`AXI_TYPEDEF_B_CHAN_T(s2c_b_chan_t,logic[Cfg.AxiIdInWidth-1:0],logic[Cfg.AxiUserWidth-1:0])
450-
`AXI_TYPEDEF_AR_CHAN_T(s2c_ar_chan_t,logic[Cfg.AxiAddrWidth-1:0],logic[Cfg.AxiIdInWidth-1:0],logic[Cfg.AxiUserWidth-1:0])
451-
`AXI_TYPEDEF_R_CHAN_T(s2c_r_chan_t,logic[Cfg.AxiDataInWidth-1:0],logic[Cfg.AxiIdInWidth-1:0],logic[Cfg.AxiUserWidth-1:0])
457+
`AXI_TYPEDEF_AW_CHAN_T(s2c_in_int_aw_chan_t,logic[Cfg.AxiAddrWidth-1:0],logic[AxiIdInWidth-1:0],logic[Cfg.AxiUserWidth-1:0])
458+
`AXI_TYPEDEF_W_CHAN_T(s2c_in_int_w_chan_t,logic[Cfg.AxiDataInWidth-1:0],logic[Cfg.AxiDataInWidth/8-1:0],logic[Cfg.AxiUserWidth-1:0])
459+
`AXI_TYPEDEF_B_CHAN_T(s2c_in_int_b_chan_t,logic[AxiIdInWidth-1:0],logic[Cfg.AxiUserWidth-1:0])
460+
`AXI_TYPEDEF_AR_CHAN_T(s2c_in_int_ar_chan_t,logic[Cfg.AxiAddrWidth-1:0],logic[AxiIdInWidth-1:0],logic[Cfg.AxiUserWidth-1:0])
461+
`AXI_TYPEDEF_R_CHAN_T(s2c_in_int_r_chan_t,logic[Cfg.AxiDataInWidth-1:0],logic[AxiIdInWidth-1:0],logic[Cfg.AxiUserWidth-1:0])
452462

453-
`AXI_TYPEDEF_REQ_T(s2c_req_t,s2c_aw_chan_t,s2c_w_chan_t,s2c_ar_chan_t)
454-
`AXI_TYPEDEF_RESP_T(s2c_resp_t,s2c_b_chan_t,s2c_r_chan_t)
463+
`AXI_TYPEDEF_REQ_T(s2c_in_int_req_t,s2c_in_int_aw_chan_t,s2c_in_int_w_chan_t,s2c_in_int_ar_chan_t)
464+
`AXI_TYPEDEF_RESP_T(s2c_in_int_resp_t,s2c_in_int_b_chan_t,s2c_in_int_r_chan_t)
455465

456466
// CLUSTER TO SOC
457-
`AXI_TYPEDEF_AW_CHAN_T(c2s_aw_chan_t,logic[Cfg.AxiAddrWidth-1:0],logic[Cfg.AxiIdOutWidth-1:0],logic[Cfg.AxiUserWidth-1:0])
458-
`AXI_TYPEDEF_W_CHAN_T(c2s_w_chan_t,logic[Cfg.AxiDataOutWidth-1:0],logic[Cfg.AxiDataOutWidth/8-1:0],logic[Cfg.AxiUserWidth-1:0])
459-
`AXI_TYPEDEF_B_CHAN_T(c2s_b_chan_t,logic[Cfg.AxiIdOutWidth-1:0],logic[Cfg.AxiUserWidth-1:0])
460-
`AXI_TYPEDEF_AR_CHAN_T(c2s_ar_chan_t,logic[Cfg.AxiAddrWidth-1:0],logic[Cfg.AxiIdOutWidth-1:0],logic[Cfg.AxiUserWidth-1:0])
461-
`AXI_TYPEDEF_R_CHAN_T(c2s_r_chan_t,logic[Cfg.AxiDataOutWidth-1:0],logic[Cfg.AxiIdOutWidth-1:0],logic[Cfg.AxiUserWidth-1:0])
467+
`AXI_TYPEDEF_AW_CHAN_T(c2s_out_int_aw_chan_t,logic[Cfg.AxiAddrWidth-1:0],logic[AxiIdOutWidth-1:0],logic[Cfg.AxiUserWidth-1:0])
468+
`AXI_TYPEDEF_W_CHAN_T(c2s_out_int_w_chan_t,logic[Cfg.AxiDataOutWidth-1:0],logic[Cfg.AxiDataOutWidth/8-1:0],logic[Cfg.AxiUserWidth-1:0])
469+
`AXI_TYPEDEF_B_CHAN_T(c2s_out_int_b_chan_t,logic[AxiIdOutWidth-1:0],logic[Cfg.AxiUserWidth-1:0])
470+
`AXI_TYPEDEF_AR_CHAN_T(c2s_out_int_ar_chan_t,logic[Cfg.AxiAddrWidth-1:0],logic[AxiIdOutWidth-1:0],logic[Cfg.AxiUserWidth-1:0])
471+
`AXI_TYPEDEF_R_CHAN_T(c2s_out_int_r_chan_t,logic[Cfg.AxiDataOutWidth-1:0],logic[AxiIdOutWidth-1:0],logic[Cfg.AxiUserWidth-1:0])
462472

463-
`AXI_TYPEDEF_REQ_T(c2s_req_t,c2s_aw_chan_t,c2s_w_chan_t,c2s_ar_chan_t)
464-
`AXI_TYPEDEF_RESP_T(c2s_resp_t,c2s_b_chan_t,c2s_r_chan_t)
473+
`AXI_TYPEDEF_REQ_T(c2s_out_int_req_t,c2s_out_int_aw_chan_t,c2s_out_int_w_chan_t,c2s_out_int_ar_chan_t)
474+
`AXI_TYPEDEF_RESP_T(c2s_out_int_resp_t,c2s_out_int_b_chan_t,c2s_out_int_r_chan_t)
465475

466-
typedef s2c_aw_chan_t c2s_in_aw_chan_t;
467-
typedef c2s_w_chan_t c2s_in_w_chan_t;
468-
typedef s2c_b_chan_t c2s_in_b_chan_t;
469-
typedef s2c_ar_chan_t c2s_in_ar_chan_t;
470-
471-
`AXI_TYPEDEF_R_CHAN_T(c2s_in_r_chan_t,logic[Cfg.AxiDataOutWidth-1:0],logic[Cfg.AxiIdInWidth-1:0],logic[Cfg.AxiUserWidth-1:0])
476+
typedef s2c_in_int_aw_chan_t c2s_in_int_aw_chan_t;
477+
typedef c2s_out_int_w_chan_t c2s_in_int_w_chan_t;
478+
typedef s2c_in_int_b_chan_t c2s_in_int_b_chan_t;
479+
typedef s2c_in_int_ar_chan_t c2s_in_int_ar_chan_t;
472480

481+
`AXI_TYPEDEF_R_CHAN_T(c2s_in_int_r_chan_t,logic[Cfg.AxiDataOutWidth-1:0],logic[AxiIdInWidth-1:0],logic[Cfg.AxiUserWidth-1:0])
473482

474-
`AXI_TYPEDEF_REQ_T(c2s_in_req_t, c2s_in_aw_chan_t, c2s_in_w_chan_t, c2s_in_ar_chan_t)
475-
`AXI_TYPEDEF_RESP_T(c2s_in_resp_t, c2s_in_b_chan_t, c2s_in_r_chan_t)
476483

484+
`AXI_TYPEDEF_REQ_T(c2s_in_int_req_t, c2s_in_int_aw_chan_t, c2s_in_int_w_chan_t, c2s_in_int_ar_chan_t)
485+
`AXI_TYPEDEF_RESP_T(c2s_in_int_resp_t, c2s_in_int_b_chan_t, c2s_in_int_r_chan_t)
477486

478-
c2s_in_req_t s_data_slave_64_req;
479-
c2s_in_resp_t s_data_slave_64_resp;
480487

481-
s2c_req_t s_data_slave_32_req;
482-
s2c_resp_t s_data_slave_32_resp;
488+
c2s_in_int_req_t s_data_slave_64_req;
489+
c2s_in_int_resp_t s_data_slave_64_resp;
483490

484-
c2s_req_t s_data_master_req;
485-
c2s_resp_t s_data_master_resp;
491+
s2c_in_int_req_t s_data_slave_32_req;
492+
s2c_in_int_resp_t s_data_slave_32_resp;
486493

487-
c2s_in_req_t s_core_instr_bus_req;
488-
c2s_in_resp_t s_core_instr_bus_resp;
494+
c2s_out_int_req_t s_data_master_req;
495+
c2s_out_int_resp_t s_data_master_resp;
489496

490-
// ***********************************************************************************************+
491-
// ***********************************************************************************************+
492-
// ***********************************************************************************************+
493-
// ***********************************************************************************************+
494-
// ***********************************************************************************************+
495-
496-
//***************************************************
497-
/* synchronous AXI interfaces internal to the cluster */
498-
//***************************************************
497+
c2s_in_int_req_t s_core_instr_bus_req;
498+
c2s_in_int_resp_t s_core_instr_bus_resp;
499499

500500

501501
// core per2axi -> ext
502-
c2s_in_req_t s_core_ext_bus_req;
503-
c2s_in_resp_t s_core_ext_bus_resp;
502+
c2s_in_int_req_t s_core_ext_bus_req;
503+
c2s_in_int_resp_t s_core_ext_bus_resp;
504504

505505
// DMA -> ext
506-
c2s_in_req_t s_dma_ext_bus_req;
507-
c2s_in_resp_t s_dma_ext_bus_resp;
506+
c2s_in_int_req_t s_dma_ext_bus_req;
507+
c2s_in_int_resp_t s_dma_ext_bus_resp;
508508

509509
// ext -> axi2mem
510-
c2s_req_t s_ext_tcdm_bus_req;
511-
c2s_resp_t s_ext_tcdm_bus_resp;
510+
c2s_out_int_req_t s_ext_tcdm_bus_req;
511+
c2s_out_int_resp_t s_ext_tcdm_bus_resp;
512512

513-
// cluster bus -> axi2per
514-
c2s_req_t s_ext_mperiph_bus_req;
515-
c2s_resp_t s_ext_mperiph_bus_resp;
513+
// cluster bus -> axi2per
514+
c2s_out_int_req_t s_ext_mperiph_bus_req;
515+
c2s_out_int_resp_t s_ext_mperiph_bus_resp;
516516

517517
/* reset generator */
518518
rstgen rstgen_i (
@@ -538,24 +538,24 @@ cluster_bus_wrap #(
538538
.AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ),
539539
.AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ),
540540
.AXI_USER_WIDTH ( Cfg.AxiUserWidth ),
541-
.AXI_ID_IN_WIDTH ( AxiIdInWidth ),
542-
.AXI_ID_OUT_WIDTH ( AxiIdOutWidth ),
541+
.AXI_ID_IN_WIDTH ( AxiIdInWidth ),
542+
.AXI_ID_OUT_WIDTH ( AxiIdOutWidth ),
543543
.BaseAddr ( Cfg.ClusterBaseAddr ),
544544
.ClusterPeripheralsOffs ( Cfg.ClusterPeriphOffs ),
545545
.ClusterExternalOffs ( Cfg.ClusterExternalOffs ),
546-
.slave_req_t ( c2s_in_req_t ),
547-
.slave_resp_t ( c2s_in_resp_t ),
548-
.master_req_t ( c2s_req_t ),
549-
.master_resp_t ( c2s_resp_t ),
550-
.slave_aw_chan_t ( c2s_in_aw_chan_t ),
551-
.master_aw_chan_t ( c2s_aw_chan_t ),
552-
.w_chan_t ( c2s_w_chan_t ),
553-
.slave_b_chan_t ( c2s_in_b_chan_t ),
554-
.master_b_chan_t ( c2s_b_chan_t ),
555-
.slave_ar_chan_t ( c2s_in_ar_chan_t ),
556-
.master_ar_chan_t ( c2s_ar_chan_t ),
557-
.slave_r_chan_t ( c2s_in_r_chan_t ),
558-
.master_r_chan_t ( c2s_r_chan_t )
546+
.slave_req_t ( c2s_in_int_req_t ),
547+
.slave_resp_t ( c2s_in_int_resp_t ),
548+
.master_req_t ( c2s_out_int_req_t ),
549+
.master_resp_t ( c2s_out_int_resp_t ),
550+
.slave_aw_chan_t ( c2s_in_int_aw_chan_t ),
551+
.master_aw_chan_t ( c2s_out_int_aw_chan_t ),
552+
.w_chan_t ( c2s_out_int_w_chan_t ),
553+
.slave_b_chan_t ( c2s_in_int_b_chan_t ),
554+
.master_b_chan_t ( c2s_out_int_b_chan_t ),
555+
.slave_ar_chan_t ( c2s_in_int_ar_chan_t ),
556+
.master_ar_chan_t ( c2s_out_int_ar_chan_t ),
557+
.slave_r_chan_t ( c2s_in_int_r_chan_t ),
558+
.master_r_chan_t ( c2s_out_int_r_chan_t )
559559
) cluster_bus_wrap_i (
560560
.clk_i ( clk_i ),
561561
.rst_ni ( rst_ni ),
@@ -582,9 +582,9 @@ axi2mem_wrap #(
582582
.AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ),
583583
.AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ),
584584
.AXI_USER_WIDTH ( Cfg.AxiUserWidth ),
585-
.AXI_ID_WIDTH ( AxiIdOutWidth ),
586-
.axi_req_t ( c2s_req_t ),
587-
.axi_resp_t ( c2s_resp_t )
585+
.AXI_ID_WIDTH ( AxiIdOutWidth ),
586+
.axi_req_t ( c2s_out_int_req_t ),
587+
.axi_resp_t ( c2s_out_int_resp_t )
588588
) axi2mem_wrap_i (
589589
.clk_i ( clk_i ),
590590
.rst_ni ( rst_ni ),
@@ -598,10 +598,10 @@ axi2mem_wrap #(
598598
axi2per_wrap #(
599599
.AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ),
600600
.AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ),
601-
.AXI_ID_WIDTH ( AxiIdOutWidth ),
601+
.AXI_ID_WIDTH ( AxiIdOutWidth ),
602602
.AXI_USER_WIDTH ( Cfg.AxiUserWidth ),
603-
.axi_req_t ( c2s_req_t ),
604-
.axi_resp_t ( c2s_resp_t )
603+
.axi_req_t ( c2s_out_int_req_t ),
604+
.axi_resp_t ( c2s_out_int_resp_t )
605605
) axi2per_wrap_i (
606606
.clk_i ( clk_i ),
607607
.rst_ni ( rst_ni ),
@@ -638,9 +638,9 @@ per2axi_wrap #(
638638
.AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ),
639639
.AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ),
640640
.AXI_USER_WIDTH ( Cfg.AxiUserWidth ),
641-
.AXI_ID_WIDTH ( AxiIdInWidth ),
642-
.axi_req_t ( c2s_in_req_t ),
643-
.axi_resp_t ( c2s_in_resp_t )
641+
.AXI_ID_WIDTH ( AxiIdInWidth ),
642+
.axi_req_t ( c2s_in_int_req_t ),
643+
.axi_resp_t ( c2s_in_int_resp_t )
644644
) per2axi_wrap_i (
645645
.clk_i ( clk_i ),
646646
.rst_ni ( rst_ni ),
@@ -718,8 +718,8 @@ dmac_wrap #(
718718
.DATA_WIDTH ( DataWidth ),
719719
.ADDR_WIDTH ( AddrWidth ),
720720
.BE_WIDTH ( BeWidth ),
721-
.axi_req_t ( c2s_in_req_t ),
722-
.axi_resp_t ( c2s_in_resp_t ),
721+
.axi_req_t ( c2s_in_int_req_t ),
722+
.axi_resp_t ( c2s_in_int_resp_t ),
723723
`ifdef TARGET_MCHAN
724724
.NB_CTRLS ( Cfg.NumCores + 2 ),
725725
.MCHAN_BURST_LENGTH ( Cfg.DmaBurstLength ),
@@ -1091,7 +1091,7 @@ generate
10911091
.reg_rsp_t ( hmr_reg_rsp_t ),
10921092
// We use any axi_req_t to just let the unit not complain about
10931093
// undeclared r_ready and b_ready signals.
1094-
.axi_req_t ( c2s_in_req_t ),
1094+
.axi_req_t ( c2s_in_int_req_t ),
10951095
.rapid_recovery_t ( rapid_recovery_pkg::rapid_recovery_t )
10961096
) i_hmr_unit (
10971097
.clk_i ( clk_i ),
@@ -1256,8 +1256,8 @@ if (Cfg.SnitchICache) begin : gen_snitch_icache
12561256
.FetchDataWidth ( Cfg.iCachePrivateDataWidth ),
12571257
.AxiAddrWidth ( AddrWidth ),
12581258
.AxiDataWidth ( Cfg.AxiDataOutWidth ),
1259-
.axi_req_t ( c2s_in_req_t ),
1260-
.axi_rsp_t ( c2s_in_resp_t )
1259+
.axi_req_t ( c2s_in_int_req_t ),
1260+
.axi_rsp_t ( c2s_in_int_resp_t )
12611261
) icache_top_i (
12621262
.clk_i ( clk_i ),
12631263
.rst_ni ( rst_ni ),
@@ -1503,6 +1503,15 @@ tcdm_banks_wrap #(
15031503
//********************************************************
15041504
//**************** AXI REGISTER SLICES *******************
15051505
//********************************************************
1506+
// CLUSTER TO SOC
1507+
`AXI_TYPEDEF_AW_CHAN_T(c2s_aw_chan_t,logic[Cfg.AxiAddrWidth-1:0],logic[Cfg.AxiIdOutWidth-1:0],logic[Cfg.AxiUserWidth-1:0])
1508+
`AXI_TYPEDEF_W_CHAN_T(c2s_w_chan_t,logic[Cfg.AxiDataOutWidth-1:0],logic[Cfg.AxiDataOutWidth/8-1:0],logic[Cfg.AxiUserWidth-1:0])
1509+
`AXI_TYPEDEF_B_CHAN_T(c2s_b_chan_t,logic[Cfg.AxiIdOutWidth-1:0],logic[Cfg.AxiUserWidth-1:0])
1510+
`AXI_TYPEDEF_AR_CHAN_T(c2s_ar_chan_t,logic[Cfg.AxiAddrWidth-1:0],logic[Cfg.AxiIdOutWidth-1:0],logic[Cfg.AxiUserWidth-1:0])
1511+
`AXI_TYPEDEF_R_CHAN_T(c2s_r_chan_t,logic[Cfg.AxiDataOutWidth-1:0],logic[Cfg.AxiIdOutWidth-1:0],logic[Cfg.AxiUserWidth-1:0])
1512+
1513+
`AXI_TYPEDEF_REQ_T(c2s_req_t,c2s_aw_chan_t,c2s_w_chan_t,c2s_ar_chan_t)
1514+
`AXI_TYPEDEF_RESP_T(c2s_resp_t,c2s_b_chan_t,c2s_r_chan_t)
15061515

15071516
c2s_req_t src_req, isolate_src_req ;
15081517
c2s_resp_t src_resp, isolate_src_resp;
@@ -1648,6 +1657,16 @@ axi_cdc_src #(
16481657
.async_data_master_r_data_i ( async_data_master_r_data_i )
16491658
);
16501659

1660+
// SOC TO CLUSTER
1661+
`AXI_TYPEDEF_AW_CHAN_T(s2c_aw_chan_t,logic[Cfg.AxiAddrWidth-1:0],logic[Cfg.AxiIdInWidth-1:0],logic[Cfg.AxiUserWidth-1:0])
1662+
`AXI_TYPEDEF_W_CHAN_T(s2c_w_chan_t,logic[Cfg.AxiDataInWidth-1:0],logic[Cfg.AxiDataInWidth/8-1:0],logic[Cfg.AxiUserWidth-1:0])
1663+
`AXI_TYPEDEF_B_CHAN_T(s2c_b_chan_t,logic[Cfg.AxiIdInWidth-1:0],logic[Cfg.AxiUserWidth-1:0])
1664+
`AXI_TYPEDEF_AR_CHAN_T(s2c_ar_chan_t,logic[Cfg.AxiAddrWidth-1:0],logic[Cfg.AxiIdInWidth-1:0],logic[Cfg.AxiUserWidth-1:0])
1665+
`AXI_TYPEDEF_R_CHAN_T(s2c_r_chan_t,logic[Cfg.AxiDataInWidth-1:0],logic[Cfg.AxiIdInWidth-1:0],logic[Cfg.AxiUserWidth-1:0])
1666+
1667+
`AXI_TYPEDEF_REQ_T(s2c_req_t,s2c_aw_chan_t,s2c_w_chan_t,s2c_ar_chan_t)
1668+
`AXI_TYPEDEF_RESP_T(s2c_resp_t,s2c_b_chan_t,s2c_r_chan_t)
1669+
16511670
s2c_req_t dst_req;
16521671
s2c_resp_t dst_resp;
16531672

@@ -1727,23 +1746,23 @@ if (Cfg.AxiDataInWidth != Cfg.AxiDataOutWidth) begin
17271746
`AXI_ASSIGN_RESP_STRUCT(dst_remap_resp,s_data_slave_32_resp)
17281747

17291748
axi_dw_converter_intf #(
1730-
.AXI_ID_WIDTH ( AxiIdInWidth ),
1731-
.AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ),
1732-
.AXI_SLV_PORT_DATA_WIDTH ( Cfg.AxiDataInWidth ),
1733-
.AXI_MST_PORT_DATA_WIDTH ( Cfg.AxiDataOutWidth),
1734-
.AXI_USER_WIDTH ( Cfg.AxiUserWidth ),
1735-
.AXI_MAX_READS ( 1 ),
1736-
.aw_chan_t ( s2c_aw_chan_t ),
1737-
.mst_w_chan_t ( c2s_w_chan_t ),
1738-
.slv_w_chan_t ( s2c_w_chan_t ),
1739-
.b_chan_t ( s2c_b_chan_t ),
1740-
.ar_chan_t ( s2c_ar_chan_t ),
1741-
.mst_r_chan_t ( c2s_in_r_chan_t ),
1742-
.slv_r_chan_t ( s2c_r_chan_t ),
1743-
.axi_mst_req_t ( c2s_in_req_t ),
1744-
.axi_mst_resp_t ( c2s_in_resp_t ),
1745-
.axi_slv_req_t ( s2c_req_t ),
1746-
.axi_slv_resp_t ( s2c_resp_t )
1749+
.AXI_ID_WIDTH ( AxiIdInWidth ),
1750+
.AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ),
1751+
.AXI_SLV_PORT_DATA_WIDTH ( Cfg.AxiDataInWidth ),
1752+
.AXI_MST_PORT_DATA_WIDTH ( Cfg.AxiDataOutWidth ),
1753+
.AXI_USER_WIDTH ( Cfg.AxiUserWidth ),
1754+
.AXI_MAX_READS ( 1 ),
1755+
.aw_chan_t ( s2c_in_int_aw_chan_t ),
1756+
.mst_w_chan_t ( c2s_w_chan_t ),
1757+
.slv_w_chan_t ( s2c_in_int_w_chan_t ),
1758+
.b_chan_t ( s2c_in_int_b_chan_t ),
1759+
.ar_chan_t ( s2c_in_int_ar_chan_t ),
1760+
.mst_r_chan_t ( c2s_in_int_r_chan_t ),
1761+
.slv_r_chan_t ( s2c_in_int_r_chan_t ),
1762+
.axi_mst_req_t ( c2s_in_int_req_t ),
1763+
.axi_mst_resp_t ( c2s_in_int_resp_t ),
1764+
.axi_slv_req_t ( s2c_in_int_req_t ),
1765+
.axi_slv_resp_t ( s2c_in_int_resp_t )
17471766
) axi_dw_UPSIZE_32_64_wrap_i (
17481767
.clk_i ( clk_i ),
17491768
.rst_ni ( s_rst_n ),

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