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Converted fmt slice to new aux chain
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‎src/fpnew_opgroup_fmt_slice.sv‎

Lines changed: 59 additions & 97 deletions
Original file line numberDiff line numberDiff line change
@@ -58,9 +58,7 @@ module fpnew_opgroup_fmt_slice #(
5858

5959
localparam int unsigned FP_WIDTH = fpnew_pkg::fp_width(FpFormat);
6060
localparam int unsigned SIMD_WIDTH = unsigned'(Width/NUM_LANES);
61-
localparam int unsigned AUX_BITS = 2;
6261

63-
logic [NUM_LANES-1:0] lane_in_ready, lane_out_valid; // Handshake signals for the lanes
6462
logic vectorial_op, cmp_op;
6563

6664
logic [NUM_LANES*FP_WIDTH-1:0] slice_result;
@@ -70,10 +68,8 @@ module fpnew_opgroup_fmt_slice #(
7068
fpnew_pkg::status_t [NUM_LANES-1:0] lane_status;
7169
logic [NUM_LANES-1:0] lane_ext_bit; // only the first one is actually used
7270
fpnew_pkg::classmask_e [NUM_LANES-1:0] lane_class_mask;
73-
TagType [NUM_LANES-1:0] lane_tags; // only the first one is actually used
7471
logic [NUM_LANES-1:0] lane_masks;
75-
logic [NUM_LANES-1:0] lane_busy, lane_is_class; // dito
76-
logic [NUM_LANES-1:0][AUX_BITS-1:0] lane_aux; // dito
72+
logic [NUM_LANES-1:0] lane_is_class; // only the first one is actually used
7773

7874
logic result_is_vector, result_is_class, result_is_cmp;
7975

@@ -84,11 +80,43 @@ module fpnew_opgroup_fmt_slice #(
8480
// -----------
8581
// RSR supported only on SDOTP module
8682
assign rnd_mode = (rnd_mode_i == fpnew_pkg::RSR) ? fpnew_pkg::RNE : rnd_mode_i;
87-
88-
assign in_ready_o = lane_in_ready[0]; // Upstream ready is given by first lane
8983
assign vectorial_op = vectorial_op_i & EnableVectors; // only do vectorial stuff if enabled
9084
assign cmp_op = (op_i == fpnew_pkg::CMP);
9185

86+
// ---------------
87+
// Generate Aux Chain
88+
// ---------------
89+
// Signals to transmit reg enable to other modules
90+
logic [NUM_LANES-1:0] in_lane_active, out_lane_active;
91+
logic [NUM_LANES-1:0][NumPipeRegs-1:0] lane_reg_enable;
92+
93+
fpnew_aux #(
94+
.NumPipeRegs( NumPipeRegs ),
95+
.TagType ( TagType ),
96+
.AuxType ( logic ),
97+
.NumLanes ( NUM_LANES )
98+
) i_aux (
99+
.clk_i,
100+
.rst_ni,
101+
.tag_i,
102+
.aux_i ( cmp_op ),
103+
.is_vector_i ( vectorial_op ),
104+
.lane_active_i ( in_lane_active ),
105+
.in_valid_i,
106+
.in_ready_o,
107+
.flush_i,
108+
.tag_o,
109+
.aux_o ( result_is_cmp ),
110+
.is_vector_o ( result_is_vector ),
111+
.lane_active_o ( out_lane_active ),
112+
.out_valid_o,
113+
.out_ready_i,
114+
.busy_o,
115+
.reg_enable_o ( /* Unused */ ),
116+
.vector_reg_enable_o ( /* Unused */ ),
117+
.lane_reg_enable_o ( lane_reg_enable )
118+
);
119+
92120
// ---------------
93121
// Generate Lanes
94122
// ---------------
@@ -98,15 +126,13 @@ module fpnew_opgroup_fmt_slice #(
98126

99127
// Generate instances only if needed, lane 0 always generated
100128
if ((lane == 0) || EnableVectors) begin : active_lane
101-
logic in_valid, out_valid, out_ready; // lane-local handshake
102129

103130
logic [NUM_OPERANDS-1:0][FP_WIDTH-1:0] local_operands; // lane-local operands
104131
logic [FP_WIDTH-1:0] op_result; // lane-local results
105132
fpnew_pkg::status_t op_status;
106-
logic [AUX_BITS-1:0] local_aux_data_input;
107133

108-
assign local_aux_data_input = {vectorial_op, cmp_op};
109-
assign in_valid = in_valid_i & ((lane == 0) | vectorial_op); // upper lanes only for vectors
134+
assign in_lane_active[lane] = (lane == 0) | vectorial_op; // upper lanes only for vectors
135+
110136
// Slice out the operands for this lane
111137
always_comb begin : prepare_input
112138
for (int i = 0; i < int'(NUM_OPERANDS); i++) begin
@@ -119,116 +145,58 @@ module fpnew_opgroup_fmt_slice #(
119145
fpnew_fma #(
120146
.FpFormat ( FpFormat ),
121147
.NumPipeRegs ( NumPipeRegs ),
122-
.PipeConfig ( PipeConfig ),
123-
.TagType ( TagType ),
124-
.AuxType ( logic [AUX_BITS-1:0] )
148+
.PipeConfig ( PipeConfig )
125149
) i_fma (
126150
.clk_i,
127151
.rst_ni,
128152
.operands_i ( local_operands ),
129153
.is_boxed_i ( is_boxed_i[NUM_OPERANDS-1:0] ),
130-
.rnd_mode_i ( rnd_mode ),
154+
.rnd_mode_i ( rnd_mode ),
131155
.op_i,
132156
.op_mod_i,
133-
.tag_i,
134-
.mask_i ( simd_mask_i[lane] ),
135-
.aux_i ( local_aux_data_input ), // Remember whether operation was vectorial
136-
.in_valid_i ( in_valid ),
137-
.in_ready_o ( lane_in_ready[lane] ),
138-
.flush_i,
139-
.result_o ( op_result ),
140-
.status_o ( op_status ),
141-
.extension_bit_o ( lane_ext_bit[lane] ),
142-
.tag_o ( lane_tags[lane] ),
143-
.mask_o ( lane_masks[lane] ),
144-
.aux_o ( lane_aux[lane] ),
145-
.out_valid_o ( out_valid ),
146-
.out_ready_i ( out_ready ),
147-
.busy_o ( lane_busy[lane] )
157+
.mask_i ( simd_mask_i[lane] ),
158+
.result_o ( op_result ),
159+
.status_o ( op_status ),
160+
.extension_bit_o ( lane_ext_bit[lane] ),
161+
.mask_o ( lane_masks[lane] ),
162+
.reg_enable_i ( lane_reg_enable[lane] )
148163
);
149164
assign lane_is_class[lane] = 1'b0;
150165
assign lane_class_mask[lane] = fpnew_pkg::NEGINF;
151-
end else if (OpGroup == fpnew_pkg::DIVSQRT) begin : lane_instance
152-
// fpnew_divsqrt #(
153-
// .FpFormat (FpFormat),
154-
// .NumPipeRegs(NumPipeRegs),
155-
// .PipeConfig (PipeConfig),
156-
// .TagType (TagType),
157-
// .AuxType (logic)
158-
// ) i_divsqrt (
159-
// .clk_i,
160-
// .rst_ni,
161-
// .operands_i ( local_operands ),
162-
// .is_boxed_i ( is_boxed_i[NUM_OPERANDS-1:0] ),
163-
// .rnd_mode_i ( rnd_mode ),
164-
// .op_i,
165-
// .op_mod_i,
166-
// .tag_i,
167-
// .aux_i ( vectorial_op ), // Remember whether operation was vectorial
168-
// .in_valid_i ( in_valid ),
169-
// .in_ready_o ( lane_in_ready[lane] ),
170-
// .flush_i,
171-
// .result_o ( op_result ),
172-
// .status_o ( op_status ),
173-
// .extension_bit_o ( lane_ext_bit[lane] ),
174-
// .tag_o ( lane_tags[lane] ),
175-
// .aux_o ( lane_aux[lane] ),
176-
// .out_valid_o ( out_valid ),
177-
// .out_ready_i ( out_ready ),
178-
// .busy_o ( lane_busy[lane] )
179-
// );
180-
// assign lane_is_class[lane] = 1'b0;
181166
end else if (OpGroup == fpnew_pkg::NONCOMP) begin : lane_instance
182167
fpnew_noncomp #(
183168
.FpFormat ( FpFormat ),
184169
.NumPipeRegs( NumPipeRegs ),
185-
.PipeConfig ( PipeConfig ),
186-
.TagType ( TagType ),
187-
.AuxType ( logic [AUX_BITS-1:0] )
170+
.PipeConfig ( PipeConfig )
188171
) i_noncomp (
189172
.clk_i,
190173
.rst_ni,
191174
.operands_i ( local_operands ),
192175
.is_boxed_i ( is_boxed_i[NUM_OPERANDS-1:0] ),
193-
.rnd_mode_i ( rnd_mode ),
176+
.rnd_mode_i ( rnd_mode ),
194177
.op_i,
195178
.op_mod_i,
196-
.tag_i,
197-
.mask_i ( simd_mask_i[lane] ),
198-
.aux_i ( local_aux_data_input ), // Remember whether operation was vectorial
199-
.in_valid_i ( in_valid ),
200-
.in_ready_o ( lane_in_ready[lane] ),
201-
.flush_i,
202-
.result_o ( op_result ),
203-
.status_o ( op_status ),
204-
.extension_bit_o ( lane_ext_bit[lane] ),
205-
.class_mask_o ( lane_class_mask[lane] ),
206-
.is_class_o ( lane_is_class[lane] ),
207-
.tag_o ( lane_tags[lane] ),
208-
.mask_o ( lane_masks[lane] ),
209-
.aux_o ( lane_aux[lane] ),
210-
.out_valid_o ( out_valid ),
211-
.out_ready_i ( out_ready ),
212-
.busy_o ( lane_busy[lane] )
179+
.mask_i ( simd_mask_i[lane] ),
180+
.result_o ( op_result ),
181+
.status_o ( op_status ),
182+
.extension_bit_o ( lane_ext_bit[lane] ),
183+
.class_mask_o ( lane_class_mask[lane] ),
184+
.is_class_o ( lane_is_class[lane] ),
185+
.mask_o ( lane_masks[lane] ),
186+
.reg_enable_i ( lane_reg_enable[lane] )
213187
);
214188
end // ADD OTHER OPTIONS HERE
215189

216-
// Handshakes are only done if the lane is actually used
217-
assign out_ready = out_ready_i & ((lane == 0) | result_is_vector);
218-
assign lane_out_valid[lane] = out_valid & ((lane == 0) | result_is_vector);
219-
220190
// Properly NaN-box or sign-extend the slice result if not in use
221-
assign local_result = lane_out_valid[lane] ? op_result : '{default: lane_ext_bit[0]};
222-
assign lane_status[lane] = lane_out_valid[lane] ? op_status : '0;
191+
assign local_result = out_lane_active[lane] ? op_result : '{default: lane_ext_bit[0]};
192+
assign lane_status[lane] = out_lane_active[lane] ? op_status : '0;
223193

224194
// Otherwise generate constant sign-extension
225195
end else begin
226-
assign lane_out_valid[lane] = 1'b0; // unused lane
227-
assign lane_in_ready[lane] = 1'b0; // unused lane
228196
assign local_result = '{default: lane_ext_bit[0]}; // sign-extend/nan box
229197
assign lane_status[lane] = '0;
230-
assign lane_busy[lane] = 1'b0;
231198
assign lane_is_class[lane] = 1'b0;
199+
assign in_lane_active[lane] = 1'b0; // Lane does not exist, it can never be active
232200
end
233201

234202
// Insert lane result into slice result
@@ -267,8 +235,6 @@ module fpnew_opgroup_fmt_slice #(
267235
// ------------
268236
// Output Side
269237
// ------------
270-
assign result_is_vector = lane_aux[0][1];
271-
assign result_is_cmp = lane_aux[0][0];
272238
assign result_is_class = lane_is_class[0];
273239

274240
assign slice_regular_result = $signed({extension_bit_o, slice_result});
@@ -294,11 +260,7 @@ module fpnew_opgroup_fmt_slice #(
294260
assign result_o = result_is_class ? slice_class_result : slice_regular_result;
295261
end
296262

297-
assign extension_bit_o = lane_ext_bit[0]; // upper lanes unused
298-
assign tag_o = lane_tags[0]; // upper lanes unused
299-
assign busy_o = (| lane_busy);
300-
assign out_valid_o = lane_out_valid[0]; // upper lanes unused
301-
263+
assign extension_bit_o = lane_ext_bit[0]; // upper lanes unused
302264

303265
// Collapse the lane status
304266
always_comb begin : output_processing

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