diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 0f75f06cf..bd973a0dc 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -27,7 +27,6 @@ jobs: uses: actions/setup-python@v2 with: python-version: 3.9 - cache: pip - name: Install Python requirements run: pip install -r requirements.txt diff --git a/.github/workflows/lint.yml b/.github/workflows/lint.yml index cc665785e..599377eef 100644 --- a/.github/workflows/lint.yml +++ b/.github/workflows/lint.yml @@ -82,7 +82,6 @@ jobs: uses: actions/setup-python@v2 with: python-version: 3.9 - cache: pip - name: Install Python requirements run: pip install -r requirements.txt diff --git a/.github/workflows/publish-docs.yml b/.github/workflows/publish-docs.yml index 7d8f9e11a..e9f3c1304 100644 --- a/.github/workflows/publish-docs.yml +++ b/.github/workflows/publish-docs.yml @@ -26,7 +26,6 @@ jobs: uses: actions/setup-python@v2 with: python-version: 3.9 - cache: pip - name: Install Python requirements run: pip install -r requirements.txt diff --git a/Bender.lock b/Bender.lock index 5697c9872..f7486a8cb 100644 --- a/Bender.lock +++ b/Bender.lock @@ -14,6 +14,17 @@ packages: dependencies: - apb - register_interface + ara: + revision: 2895ba907e9eb14b3464609dc791a969d159a7c3 + version: null + source: + Git: https://github.com/pulp-platform/ara.git + dependencies: + - apb + - axi + - common_cells + - cva6 + - tech_cells_generic axi: revision: 39f5f2d51c5e524f6fc5cf8b6e901f7dcc5622d7 version: 0.39.6 @@ -99,7 +110,7 @@ packages: Git: https://github.com/pulp-platform/common_verification.git dependencies: [] cva6: - revision: 9338c2ca7cf1a47aef54322f89ce867825c3c8d5 + revision: 99eac9a649001bdf5b8f9da52e0ca73d5c48db1c version: null source: Git: https://github.com/pulp-platform/cva6.git @@ -116,8 +127,8 @@ packages: dependencies: - axi fpnew: - revision: f231041c610f270ffc03cbdac38739ddb6426572 - version: null + revision: e5aa6a01b5bbe1675c3aa8872e1203413ded83d1 + version: 0.2.3 source: Git: https://github.com/pulp-platform/cvfpu.git dependencies: diff --git a/Bender.yml b/Bender.yml index 30817f2c4..66a22b0ea 100644 --- a/Bender.yml +++ b/Bender.yml @@ -22,7 +22,8 @@ dependencies: clint: { git: "https://github.com/pulp-platform/clint.git", version: 0.2.0 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.33.0 } common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.0 } - cva6: { git: "https://github.com/pulp-platform/cva6.git", rev: pulp-v1.0.0 } + cva6: { git: "https://github.com/pulp-platform/cva6.git", rev: pulp-v2.0.0-alpha.1 } + ara: { git: "https://github.com/pulp-platform/ara.git", rev: 2895ba907e9eb14b3464609dc791a969d159a7c3 } # mp/cheshire-integration-fix iDMA: { git: "https://github.com/pulp-platform/iDMA.git", version: 0.6.3 } irq_router: { git: "https://github.com/pulp-platform/irq_router.git", version: 0.0.1-beta.1 } opentitan_peripherals: { git: "https://github.com/pulp-platform/opentitan_peripherals.git", version: 0.4.0 } diff --git a/cheshire.mk b/cheshire.mk index f22f3632f..9bd385f2f 100644 --- a/cheshire.mk +++ b/cheshire.mk @@ -16,7 +16,7 @@ VLOG_ARGS ?= -suppress 2583 -suppress 13314 -timescale 1ns/1ps VLOGAN_ARGS ?= -kdb -nc -assert svaext +v2k -timescale=1ns/1ps # Common Bender flags for Cheshire RTL -CHS_BENDER_RTL_FLAGS ?= -t rtl -t cva6 -t cv64a6_imafdcsclic_sv39 +CHS_BENDER_RTL_FLAGS ?= -t rtl -t cva6 -t cv64a6_imafdchsclic_sv39_wb # Define used paths (prefixed to avoid name conflicts) CHS_ROOT ?= $(shell $(BENDER) path cheshire) @@ -63,7 +63,7 @@ chs-clean-deps: ###################### CHS_NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/cheshire-nonfree.git -CHS_NONFREE_COMMIT ?= 99aa8d9 +CHS_NONFREE_COMMIT ?= 5eb95050b2c043250d717046939ac78f24845d56 CHS_PHONY += chs-nonfree-init chs-nonfree-init: diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv index 4e31078b1..5ac6d6342 100644 --- a/hw/cheshire_pkg.sv +++ b/hw/cheshire_pkg.sv @@ -138,6 +138,7 @@ package cheshire_pkg; bit Clic; bit IrqRouter; bit BusErr; + bit Ara; // Parameters for Debug Module jtag_idcode_t DbgIdCode; dw_bt DbgMaxReqs; @@ -196,6 +197,9 @@ package cheshire_pkg; aw_bt AxiRtNumAddrRegions; bit AxiRtCutPaths; bit AxiRtEnableChecks; + // Parameters for Ara + byte_bt AraNrLanes; + word_bt AraVLEN; } cheshire_cfg_t; ////////////////// @@ -295,6 +299,7 @@ package cheshire_pkg; typedef struct packed { aw_bt [2**MaxCoresWidth-1:0] cores; aw_bt dbg; + aw_bt ara; aw_bt dma; aw_bt slink; aw_bt vga; @@ -308,6 +313,7 @@ package cheshire_pkg; int unsigned i = 0; for (int j = 0; j < cfg.NumCores; j++) begin ret.cores[i] = i; i++; end ret.dbg = i; + if (cfg.Ara) begin i++; ret.ara = i; end if (cfg.Dma) begin i++; ret.dma = i; end if (cfg.SerialLink) begin i++; ret.slink = i; end if (cfg.Vga) begin i++; ret.vga = i; end @@ -480,74 +486,44 @@ package cheshire_pkg; endcase endfunction - function automatic config_pkg::cva6_cfg_t gen_cva6_cfg(cheshire_cfg_t cfg); + function automatic config_pkg::cva6_user_cfg_t gen_cva6_cfg(cheshire_cfg_t cfg); doub_bt SizeSpm = get_llc_size(cfg); doub_bt SizeLlcOut = cfg.LlcOutRegionEnd - cfg.LlcOutRegionStart; doub_bt CieBase = cfg.Cva6ExtCieOnTop ? 64'h8000_0000 - cfg.Cva6ExtCieLength : 64'h2000_0000; doub_bt NoCieBase = cfg.Cva6ExtCieOnTop ? 64'h2000_0000 : 64'h2000_0000 + cfg.Cva6ExtCieLength; - return config_pkg::cva6_cfg_t'{ - NrCommitPorts : 2, - AxiAddrWidth : cfg.AddrWidth, - AxiDataWidth : cfg.AxiDataWidth, - AxiIdWidth : Cva6IdWidth, - AxiUserWidth : cfg.AxiUserWidth, - NrLoadBufEntries : 2, - FpuEn : 1, - XF16 : 0, - XF16ALT : 0, - XF8 : 0, - XF8ALT : 0, - RVA : 1, - RVB : 0, - RVV : 0, - RVC : 1, - RVH : 1, - RVZCB : 1, - XFVec : 0, - CvxifEn : 0, - ZiCondExtEn : 1, - RVSCLIC : cfg.Clic, - RVF : 1, - RVD : 1, - FpPresent : 1, - NSX : 0, - FLen : 64, - RVFVec : 0, - XF16Vec : 0, - XF16ALTVec : 0, - XF8Vec : 0, - NrRgprPorts : 0, - NrWbPorts : 0, - EnableAccelerator : 0, - RVS : 1, - RVU : 1, - HaltAddress : 'h800, // Relative to AmDbg - ExceptionAddress : 'h810, // Relative to AmDbg - RASDepth : cfg.Cva6RASDepth, - BTBEntries : cfg.Cva6BTBEntries, - BHTEntries : cfg.Cva6BHTEntries, - DmBaseAddress : AmDbg, - TvalEn : 1, - NrPMPEntries : cfg.Cva6NrPMPEntries, - PMPCfgRstVal : {16{64'h0}}, - PMPAddrRstVal : {16{64'h0}}, - PMPEntryReadOnly : 16'd0, - NOCType : config_pkg::NOC_TYPE_AXI4_ATOP, - CLICNumInterruptSrc : NumCoreIrqs + NumIntIntrs + cfg.NumExtClicIntrs, - NrNonIdempotentRules : 2, // Periphs, ExtNonCIE - NonIdempotentAddrBase : {64'h0000_0000, NoCieBase}, - NonIdempotentLength : {64'h1000_0000, 64'h6000_0000 - cfg.Cva6ExtCieLength}, - NrExecuteRegionRules : 5, // Debug, Bootrom, AllSPM, LLCOut, ExtCIE - ExecuteRegionAddrBase : {AmDbg, AmBrom, AmSpm, cfg.LlcOutRegionStart, CieBase}, - ExecuteRegionLength : {64'h40000, 64'h40000, 2*SizeSpm, SizeLlcOut, cfg.Cva6ExtCieLength}, - NrCachedRegionRules : 3, // CachedSPM, LLCOut, ExtCIE - CachedRegionAddrBase : {AmSpm, cfg.LlcOutRegionStart, CieBase}, - CachedRegionLength : {SizeSpm, SizeLlcOut, cfg.Cva6ExtCieLength}, - MaxOutstandingStores : 7, - DebugEn : 1, - NonIdemPotenceEn : 0, - AxiBurstWriteEn : 0 - }; + // Base our config on the upstream default for this variant + config_pkg::cva6_user_cfg_t ret = cva6_config_pkg::cva6_cfg; + // Modify what we need to + ret.AxiAddrWidth = cfg.AddrWidth; + ret.AxiDataWidth = cfg.AxiDataWidth; + ret.AxiIdWidth = Cva6IdWidth; + ret.AxiUserWidth = cfg.AxiUserWidth; + ret.CvxifEn = 0; + ret.DmBaseAddress = AmDbg; + ret.HaltAddress = 'h800; // Relative to AmDbg + ret.ExceptionAddress = 'h810; // Relative to AmDbg + ret.NrNonIdempotentRules = 2; // Periphs, ExtNonCI; + ret.NonIdempotentAddrBase = {64'h0000_0000, NoCieBase}; + ret.NOCType = config_pkg::NOC_TYPE_AXI4_ATOP; + ret.NonIdempotentLength = {64'h1000_0000, 64'h6000_0000 - cfg.Cva6ExtCieLength}; + ret.NrExecuteRegionRules = 5; // Debug, Bootrom, AllSPM, LLCOut, ExtCI; + ret.ExecuteRegionAddrBase = {AmDbg, AmBrom, AmSpm, cfg.LlcOutRegionStart, CieBase}; + ret.ExecuteRegionLength = {64'h40000, 64'h40000, 2*SizeSpm, SizeLlcOut, cfg.Cva6ExtCieLength}; + ret.NrCachedRegionRules = 3; // CachedSPM, LLCOut, ExtCI; + ret.CachedRegionAddrBase = {AmSpm, cfg.LlcOutRegionStart, CieBase}; + ret.CachedRegionLength = {SizeSpm, SizeLlcOut, cfg.Cva6ExtCieLength}; + ret.DebugEn = 1; + ret.RVSCLIC = cfg.Clic; + ret.CLICNumInterruptSrc = NumCoreIrqs + NumIntIntrs + cfg.NumExtClicIntrs; + // TODO: Should some things be removed from the main config? + // TODO: Should other things be added to the main config? + // TODO: Tune missing parameters of interest (esp. cache and interconnect) properly + ret.RASDepth = cfg.Cva6RASDepth; + ret.BTBEntries = cfg.Cva6BTBEntries; + ret.BHTEntries = cfg.Cva6BHTEntries; + ret.NrPMPEntries = cfg.Cva6NrPMPEntries; + // Return modified config + return ret; endfunction //////////////// @@ -612,6 +588,7 @@ package cheshire_pkg; Clic : 0, IrqRouter : 0, BusErr : 1, + Ara : 0, // Debug DbgIdCode : CheshireIdCode, DbgMaxReqs : 4, @@ -669,6 +646,9 @@ package cheshire_pkg; AxiRtWBufferDepth : 16, AxiRtNumAddrRegions : 2, AxiRtCutPaths : 1, + // Ara + AraNrLanes : 2, + AraVLEN : 2048, // All non-set values should be zero default: '0 }; diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index 234061a1a..12d5b144a 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -112,6 +112,7 @@ module cheshire_soc import cheshire_pkg::*; #( `include "common_cells/registers.svh" `include "common_cells/assertions.svh" `include "cheshire/typedef.svh" + `include "ara/intf_typedef.svh" // Declare interface types internally `CHESHIRE_TYPEDEF_ALL(, Cfg) @@ -554,11 +555,10 @@ module cheshire_soc import cheshire_pkg::*; #( // Cores // ///////////// - // TODO: Implement X interface support - `CHESHIRE_TYPEDEF_AXI_CT(axi_cva6, addr_t, cva6_id_t, axi_data_t, axi_strb_t, axi_user_t) - localparam config_pkg::cva6_cfg_t Cva6Cfg = gen_cva6_cfg(Cfg); + localparam config_pkg::cva6_user_cfg_t Cva6UsrCfg = gen_cva6_cfg(Cfg); + localparam config_pkg::cva6_cfg_t Cva6Cfg = build_config_pkg::build_config(Cva6UsrCfg); // Boot from boot ROM only if available, otherwise from platform ROM localparam logic [63:0] BootAddr = 64'(Cfg.Bootrom ? AmBrom : Cfg.PlatformRom); @@ -587,6 +587,50 @@ module cheshire_soc import cheshire_pkg::*; #( assign intr.intn.bus_err.cores = core_bus_err_intr_comb; + // TODO: Implement X interface support + // Define the exception type + `CVA6_TYPEDEF_EXCEPTION(exception_t, Cva6Cfg); + // Standard interface + `CVA6_INTF_TYPEDEF_ACC_REQ(accelerator_req_t, Cva6Cfg, fpnew_pkg::roundmode_e); + `CVA6_INTF_TYPEDEF_ACC_RESP(accelerator_resp_t, Cva6Cfg, exception_t); + // MMU interface + `CVA6_INTF_TYPEDEF_MMU_REQ(acc_mmu_req_t, Cva6Cfg); + `CVA6_INTF_TYPEDEF_MMU_RESP(acc_mmu_resp_t, Cva6Cfg, exception_t); + // Accelerator - CVA6's top-level interface + `CVA6_INTF_TYPEDEF_CVA6_TO_ACC(cva6_to_acc_t, accelerator_req_t, acc_mmu_resp_t); + `CVA6_INTF_TYPEDEF_ACC_TO_CVA6(acc_to_cva6_t, accelerator_resp_t, acc_mmu_req_t); + + // Configure Ara with the right AXI id width + typedef logic [Cfg.AxiMstIdWidth-1:0] ara_id_t; + // Default Ara AXI data width + localparam int unsigned AraDataWideWidth = 32 * Cfg.AraNrLanes; + typedef logic [AraDataWideWidth -1 : 0] axi_ara_wide_data_t; + typedef logic [AraDataWideWidth/8 -1 : 0] axi_ara_wide_strb_t; + `AXI_TYPEDEF_ALL( + axi_ara_wide, addr_t, ara_id_t, axi_ara_wide_data_t, axi_ara_wide_strb_t, axi_user_t) + axi_ara_wide_req_t axi_ara_wide_req_inval, axi_ara_wide_req; + axi_ara_wide_resp_t axi_ara_wide_resp_inval, axi_ara_wide_resp; + + // Accelerator ports + cva6_to_acc_t acc_req; + acc_to_cva6_t acc_resp; + + // CVA6-Ara memory consistency + logic acc_cons_en; + logic [Cfg.AddrWidth-1:0] inval_addr; + logic inval_valid; + logic inval_ready; + + // Pack invalidation interface into acc interface + acc_to_cva6_t acc_resp_pack; + always_comb begin : pack_inval + acc_resp_pack = acc_resp; + acc_resp_pack.acc_resp.inval_valid = inval_valid; + acc_resp_pack.acc_resp.inval_addr = inval_addr; + inval_ready = acc_req.acc_req.inval_ready; + acc_cons_en = acc_req.acc_req.acc_cons_en; + end + for (genvar i = 0; i < NumIntHarts; i++) begin : gen_cva6_cores axi_cva6_req_t core_out_req, core_ur_req; axi_cva6_rsp_t core_out_rsp, core_ur_rsp; @@ -600,14 +644,20 @@ module cheshire_soc import cheshire_pkg::*; #( riscv::priv_lvl_t clic_irq_priv; cva6 #( - .CVA6Cfg ( Cva6Cfg ), - .axi_ar_chan_t ( axi_cva6_ar_chan_t ), - .axi_aw_chan_t ( axi_cva6_aw_chan_t ), - .axi_w_chan_t ( axi_cva6_w_chan_t ), - .b_chan_t ( axi_cva6_b_chan_t ), - .r_chan_t ( axi_cva6_r_chan_t ), - .noc_req_t ( axi_cva6_req_t ), - .noc_resp_t ( axi_cva6_rsp_t ) + .CVA6Cfg ( Cva6Cfg ), + .axi_ar_chan_t ( axi_cva6_ar_chan_t ), + .axi_aw_chan_t ( axi_cva6_aw_chan_t ), + .axi_w_chan_t ( axi_cva6_w_chan_t ), + .b_chan_t ( axi_cva6_b_chan_t ), + .r_chan_t ( axi_cva6_r_chan_t ), + .cvxif_req_t ( cva6_to_acc_t ), + .cvxif_resp_t ( acc_to_cva6_t ), + .noc_req_t ( axi_cva6_req_t ), + .noc_resp_t ( axi_cva6_rsp_t ), + .accelerator_req_t ( accelerator_req_t ), + .accelerator_resp_t ( accelerator_resp_t ), + .acc_mmu_req_t ( acc_mmu_req_t ), + .acc_mmu_resp_t ( acc_mmu_resp_t ) ) i_core_cva6 ( .clk_i, .rst_ni, @@ -626,8 +676,8 @@ module cheshire_soc import cheshire_pkg::*; #( .clic_kill_req_i ( clic_irq_kill_req ), .clic_kill_ack_o ( clic_irq_kill_ack ), .rvfi_probes_o ( ), - .cvxif_req_o ( ), - .cvxif_resp_i ( '0 ), + .cvxif_req_o ( acc_req ), + .cvxif_resp_i ( acc_resp_pack ), .noc_req_o ( core_out_req ), .noc_resp_i ( core_out_rsp ) ); @@ -747,6 +797,103 @@ module cheshire_soc import cheshire_pkg::*; #( .mst_req_o ( axi_in_req[AxiIn.cores[i]] ), .mst_resp_i ( axi_in_rsp[AxiIn.cores[i]] ) ); + + // Generate Ara RVV vector processor if enabled + if (Cfg.Ara) begin : gen_ara + axi_mst_req_t axi_ara_narrow_req; + axi_mst_rsp_t axi_ara_narrow_resp; + + ara #( + .NrLanes ( Cfg.AraNrLanes ), + .VLEN ( Cfg.AraVLEN ), + .OSSupport ( 1'b1 ), + .CVA6Cfg ( Cva6Cfg ), + .exception_t ( exception_t ), + .accelerator_req_t (accelerator_req_t ), + .accelerator_resp_t(accelerator_resp_t), + .acc_mmu_req_t (acc_mmu_req_t ), + .acc_mmu_resp_t (acc_mmu_resp_t ), + .cva6_to_acc_t (cva6_to_acc_t ), + .acc_to_cva6_t (acc_to_cva6_t ), + .AxiDataWidth ( AraDataWideWidth ), + .AxiAddrWidth ( Cfg.AddrWidth ), + .axi_ar_t ( axi_ara_wide_ar_chan_t ), + .axi_r_t ( axi_ara_wide_r_chan_t ), + .axi_aw_t ( axi_ara_wide_aw_chan_t ), + .axi_w_t ( axi_ara_wide_w_chan_t ), + .axi_b_t ( axi_ara_wide_b_chan_t ), + .axi_req_t ( axi_ara_wide_req_t ), + .axi_resp_t ( axi_ara_wide_resp_t ) + ) i_ara ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .scan_enable_i ( 1'b0 ), + .scan_data_i ( 1'b0 ), + .scan_data_o ( /* Unused */ ), + .acc_req_i ( acc_req ), + .acc_resp_o ( acc_resp ), + .axi_req_o ( axi_ara_wide_req ), + .axi_resp_i ( axi_ara_wide_resp ) + ); + + // Issue invalidations to CVA6 L1D$ + axi_inval_filter #( + .MaxTxns ( 4 ), + .AddrWidth ( Cfg.AddrWidth ), + .L1LineWidth( Cva6Cfg.DCACHE_LINE_WIDTH/8 ), + .aw_chan_t ( axi_ara_wide_aw_chan_t ), + .req_t ( axi_ara_wide_req_t ), + .resp_t ( axi_ara_wide_resp_t ) + ) i_ara_axi_inval_filter ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .en_i ( acc_cons_en ), + .slv_req_i ( axi_ara_wide_req ), + .slv_resp_o ( axi_ara_wide_resp ), + .mst_req_o ( axi_ara_wide_req_inval ), + .mst_resp_i ( axi_ara_wide_resp_inval ), + .inval_addr_o ( inval_addr ), + .inval_valid_o( inval_valid ), + .inval_ready_i( inval_ready ) + ); + + // Convert from AraDataWideWidth (axi_ara_wide) to Cfg.AxiDataWidth (axi_ara_narrow) + axi_dw_converter #( + .AxiSlvPortDataWidth ( AraDataWideWidth ), + .AxiMstPortDataWidth ( Cfg.AxiDataWidth ), + .AxiMaxReads ( 4 ), // TODO: Tune this w.r.t. ARA_NR_LANES + .AxiAddrWidth ( Cfg.AddrWidth ), + .AxiIdWidth ( Cfg.AxiMstIdWidth ), + .aw_chan_t ( axi_ara_wide_aw_chan_t ), + .mst_w_chan_t ( axi_mst_w_chan_t ), + .slv_w_chan_t ( axi_ara_wide_w_chan_t ), + .b_chan_t ( axi_ara_wide_b_chan_t ), + .ar_chan_t ( axi_ara_wide_ar_chan_t ), + .mst_r_chan_t ( axi_mst_r_chan_t ), + .slv_r_chan_t ( axi_ara_wide_r_chan_t ), + .axi_mst_req_t ( axi_mst_req_t ), + .axi_mst_resp_t ( axi_mst_rsp_t ), + .axi_slv_req_t ( axi_ara_wide_req_t ), + .axi_slv_resp_t ( axi_ara_wide_resp_t ) + ) i_ara_axi_dw_converter ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .slv_req_i ( axi_ara_wide_req_inval ), + .slv_resp_o ( axi_ara_wide_resp_inval ), + .mst_req_o ( axi_ara_narrow_req ), + .mst_resp_i ( axi_ara_narrow_resp ) + ); + + // Assign to crossbar input/master + assign axi_in_req[AxiIn.ara] = axi_ara_narrow_req; + assign axi_ara_narrow_resp = axi_in_rsp[AxiIn.ara]; + + end else begin : gen_no_ara + // Tie-to-safe the Ara-related signals + assign acc_resp = '0; + assign inval_valid = '0; + assign inval_addr = '0; + end end ///////////////////////// @@ -1729,4 +1876,7 @@ module cheshire_soc import cheshire_pkg::*; #( // TODO: many other things I most likely forgot // TODO: check that LLC only exists if its output is connected (the reverse is allowed) + if (Cfg.Ara && (NumIntHarts > 1)) + $error("Ara is only compatible with a single-core architecture."); + endmodule diff --git a/target/sim/src/tb_cheshire_pkg.sv b/target/sim/src/tb_cheshire_pkg.sv index 8197b2dfa..ff5bca9bf 100644 --- a/target/sim/src/tb_cheshire_pkg.sv +++ b/target/sim/src/tb_cheshire_pkg.sv @@ -23,11 +23,21 @@ package tb_cheshire_pkg; return ret; endfunction + // A dedicated Ara config + function automatic cheshire_cfg_t gen_cheshire_ara_cfg(); + cheshire_cfg_t ret = DefaultCfg; + ret.Ara = 1; + ret.AraNrLanes = 2; + ret.AraVLEN = 2048; + return ret; + endfunction + // Number of Cheshire configurations - localparam int unsigned NumCheshireConfigs = 32'd3; + localparam int unsigned NumCheshireConfigs = 32'd4; // Assemble a configuration array indexed by a numeric parameter localparam cheshire_cfg_t [NumCheshireConfigs-1:0] TbCheshireConfigs = { + gen_cheshire_ara_cfg(), // 3: Ara-enabled configuration gen_cheshire_clic_cfg(), // 2: CLIC-enabled configuration gen_cheshire_rt_cfg(), // 1: RT-enabled configuration DefaultCfg // 0: Default configuration diff --git a/target/sim/vsim/start.cheshire_soc.tcl b/target/sim/vsim/start.cheshire_soc.tcl index f54312ece..71211098c 100644 --- a/target/sim/vsim/start.cheshire_soc.tcl +++ b/target/sim/vsim/start.cheshire_soc.tcl @@ -24,7 +24,7 @@ if { ![info exists CXX_PATH] } { # Set voptargs only if not already set to make overridable. # Default on fast simulation flags. if { ![info exists VOPTARGS] } { - set VOPTARGS "-O5 +acc=p+tb_cheshire_soc. +noacc=p+cheshire_soc. +acc=r+stream_xbar" + set VOPTARGS "-O5 +acc=npr+tb_cheshire_soc. +acc=npr+cheshire_soc. +acc=r+stream_xbar" } set flags "-permissive -suppress 3009 -suppress 8386 -error 7 -cpppath ${CXX_PATH} " diff --git a/target/xilinx/src/cheshire_top_xilinx.sv b/target/xilinx/src/cheshire_top_xilinx.sv index de7ca9d1b..35b371949 100644 --- a/target/xilinx/src/cheshire_top_xilinx.sv +++ b/target/xilinx/src/cheshire_top_xilinx.sv @@ -108,6 +108,11 @@ module cheshire_top_xilinx import cheshire_pkg::*; ( ret.Usb = 1; `else ret.Usb = 0; + `endif + `ifdef ARA + ret.Ara = 1; + ret.AraVLEN = `ifdef VLEN `VLEN `else 0 `endif; + ret.AraNrLanes = `ifdef NR_LANES `NR_LANES `else 0 `endif; `endif return ret; endfunction