rdl: Parametrize serial link properly

Author: fischeti

cheshire.mk

@@ -35,9 +35,6 @@ DRAM_RTL_SIM_ROOT := $(shell $(BENDER) path dram_rtl_sim)
 REGTOOL ?= $(CHS_REG_DIR)/vendor/lowrisc_opentitan/util/regtool.py
 PEAKRDL ?= peakrdl
 
-PEAKRDL_INCLUDES  := -I $(CHS_ROOT)/hw/regs
-PEAKRDL_INCLUDES  += -I $(CHS_SLINK_DIR)/src/regs
-
 
 ################
 # Dependencies #
@@ -77,6 +74,19 @@ chs-nonfree-init:
 
 -include $(CHS_ROOT)/nonfree/nonfree.mk
 
+########################
+# SystemRDL components #
+########################
+
+PEAKRDL_INCLUDES  := -I $(CHS_ROOT)/hw/regs
+
+# Serial Link
+SLINK_NUM_LANES ?= 4
+include $(CHS_SLINK_DIR)/slink.mk
+
+PEAKRDL_INCLUDES += -I $(CHS_SLINK_DIR)/src/regs
+PEAKRDL_PARAMS   += -P SlinkNumLanes=$(SLINK_NUM_LANES)
+
 ############
 # Build SW #
 ############
@@ -92,8 +102,8 @@ $(CHS_ROOT)/hw/regs/cheshire_soc_regs_pkg.sv $(CHS_ROOT)/hw/regs/cheshire_soc_re
 	$(PEAKRDL) regblock $< -o $(CHS_ROOT)/hw/regs/ --cpuif apb4-flat --default-reset arst_n --module-name cheshire_soc_regs
 	@sed -i '1i// Copyright 2025 ETH Zurich and University of Bologna.\n// Solderpad Hardware License, Version 0.51, see LICENSE for details.\n// SPDX-License-Identifier: SHL-0.51\n' $(CHS_ROOT)/hw/regs/cheshire_soc_regs.sv $(CHS_ROOT)/hw/regs/cheshire_soc_regs_pkg.sv
 
-$(CHS_ROOT)/hw/cheshire_addrmap_pkg.sv: $(CHS_ROOT)/hw/cheshire.rdl
-	$(PEAKRDL) raw-header $< --format svpkg --no-prefix $(PEAKRDL_INCLUDES) --license-str $$'Copyright 2025 ETH Zurich and University of Bologna.\nSolderpad Hardware License, Version 0.51, see LICENSE for details.\nSPDX-License-Identifier: SHL-0.51' -o $@
+$(CHS_ROOT)/hw/cheshire_addrmap_pkg.sv: $(CHS_ROOT)/hw/cheshire.rdl $(CHS_SLINK_DIR)/.generated
+	$(PEAKRDL) raw-header $< --format svpkg --no-prefix $(PEAKRDL_INCLUDES) $(PEAKRDL_PARAMS) --license-str $$'Copyright 2025 ETH Zurich and University of Bologna.\nSolderpad Hardware License, Version 0.51, see LICENSE for details.\nSPDX-License-Identifier: SHL-0.51' -o $@
 
 # CLINT
 CLINTCORES ?= 1
@@ -118,10 +128,6 @@ include $(AXI_VGA_ROOT)/axi_vga.mk
 $(AXI_VGA_ROOT)/.generated:
 	flock -x $@ $(MAKE) axi_vga && touch $@
 
-# Custom serial link
-SLINK_NUM_LANES ?= 4
-include $(CHS_SLINK_DIR)/slink.mk
-
 # iDMA
 include $(IDMA_ROOT)/idma.mk
 

hw/cheshire.rdl

@@ -24,7 +24,7 @@ addrmap periph_stub_t #(longint unsigned Size = 0x1000) {
     external reg { field {} _end[31:0]   = 0; } _end   @(Size - 4);
 };
 
-addrmap cheshire {
+addrmap cheshire #(longint unsigned SlinkNumLanes = 4) {
     desc = "Cheshire SoC system address map";
 
     ////////////////////
@@ -101,9 +101,8 @@ addrmap cheshire {
     // GPIO (4 KiB)
     periph_stub_t #(.Size(0x0000_1000)) gpio    @0x0300_5000;
 
-    // Serial link (4 KiB)
-    // TODO(fischeti): Parametrize
-    slink_reg slink                             @0x0300_6000;
+    // Serial link registers
+    slink_reg #(.NumLanes(SlinkNumLanes)) slink @0x0300_6000;
 
     // AXI VGA (4 KiB)
     periph_stub_t #(.Size(0x0000_1000)) vga     @0x0300_7000;