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Rename parameters with No* to Num* when referring to number
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‎doc/axi_demux.md‎

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@@ -23,7 +23,7 @@ This demultiplexer is configured through the parameters listed in the following
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| Name | Type | Definition |
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|:---------------------|:-------------------|:-----------|
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| `IdWidth` | `int unsigned` | The AXI ID width (of all ports). |
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| `NoMstPorts` | `int unsigned` | The number of AXI master ports of the demultiplexer (in other words, how many AXI slave modules can be attached). |
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| `NumMstPorts` | `int unsigned` | The number of AXI master ports of the demultiplexer (in other words, how many AXI slave modules can be attached). |
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| `MaxTrans` | `int unsigned` | The slave port can have at most this many transactions [in flight](../doc#in-flight). |
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| `LookBits` | `int unsigned` | The number of ID bits (starting at the least significant) the demultiplexer uses to determine the uniqueness of an AXI ID (see section *Ordering and Stalls* below). This value has to be less or equal than `IdWidth`. |
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| `UniqueIds` | `bit` | If you can guarantee that the ID of each transaction is always unique among all in-flight transactions in the same direction, setting this parameter to `1'b1` simplifies the demultiplexer (see section *Ordering and Stalls* below). Defaults to `1'b0`. |

‎doc/axi_lite_demux.md‎

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@@ -19,7 +19,7 @@ This demultiplexer is configured through the parameters listed in the following
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| Name | Type | Definition |
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|:---------------------|:-------------------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
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| `NoMstPorts` | `int unsigned` | The number of AXI4-Lite master ports of the demultiplexer (in other words, how many AXI4-Lite slave modules can be attached). |
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| `NumMstPorts` | `int unsigned` | The number of AXI4-Lite master ports of the demultiplexer (in other words, how many AXI4-Lite slave modules can be attached). |
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| `MaxTrans` | `int unsigned` | The slave port can have at most this many transactions [in flight](../doc#in-flight). |
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| `FallThrough` | `bit` | Routing decisions on the AW channel fall through to the W channel (i.e. don't consume a cycle). Enabling this allows the demultiplexer to accept a W beat in the same cycle as the corresponding AW beat, but it increases the combinatorial path of the W channel with logic from `slv_aw_select_i`. |
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| `SpillXX` | `bit` | Inserts one spill register on the respective channel (AW, W, B, AR, and R) before the demultiplexer. |

‎doc/axi_lite_mux.md‎

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@@ -10,7 +10,7 @@ The following table shows the parameters of the module. The module further requi
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| Name | Type | Function |
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|:--------------|:---------------|:---------------------------------------------------------------------------------------------------------------|
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| `NoSlvPorts` | `int unsigned` | How many slave ports the multiplexer features. This many master modules can be connected to the multiplexer. |
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| `NumSlvPorts` | `int unsigned` | How many slave ports the multiplexer features. This many master modules can be connected to the multiplexer. |
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| `MaxWTrans` | `int unsigned` | The depth of the FIFO holding the highest bits of the ID between the AW and W channel. |
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| `FallThrough` | `bit` | Is the FIFO between the AW and W channel in fall-through mode. Enabling will lead to an additional delay cycle |
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| `SpillXX` | `bit` | Enables the optional spill-register on the respective channel. |

‎doc/axi_lite_xbar.md‎

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@@ -28,8 +28,8 @@ The crossbar is configured through the `Cfg` parameter with a `axi_pkg::xbar_cfg
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| Name | Type | Definition |
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|:------------------|:-------------------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
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| `NoSlvPorts` | `int unsigned` | The number of AXI4-Lite slave ports of the crossbar (in other words, how many AXI4-Lite master modules can be attached). |
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| `NoMstPorts` | `int unsigned` | The number of AXI4-Lite master ports of the crossbar (in other words, how many AXI4-Lite slave modules can be attached). |
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| `NumSlvPorts` | `int unsigned` | The number of AXI4-Lite slave ports of the crossbar (in other words, how many AXI4-Lite master modules can be attached). |
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| `NumMstPorts` | `int unsigned` | The number of AXI4-Lite master ports of the crossbar (in other words, how many AXI4-Lite slave modules can be attached). |
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| `MaxMstTrans` | `int unsigned` | Each slave port can have at most this many transactions [in flight](../doc#in-flight). |
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| `MaxSlvTrans` | `int unsigned` | Each master port can have at most this many transactions [in flight](../doc#in-flight). |
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| `FallThrough` | `bit` | Routing decisions on the AW channel fall through to the W channel. Enabling this allows the crossbar to accept a W beat in the same cycle as the corresponding AW beat, but it increases the combinatorial path of the W channel with logic from the AW channel. |
@@ -38,7 +38,7 @@ The crossbar is configured through the `Cfg` parameter with a `axi_pkg::xbar_cfg
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| `IdUsedSlvPorts` | `int unsigned` | Not used by the AXI4-Lite crossbar. Set `default: '0`. |
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| `AddrWidth` | `int unsigned` | The AXI4-Lite address width. |
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| `DataWidth` | `int unsigned` | The AXI4-Lite data width. |
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| `NoAddrRules` | `int unsigned` | The number of address map rules. |
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| `NumAddrRules` | `int unsigned` | The number of address map rules. |
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The other parameters are types to define the ports of the crossbar. The `*_chan_t` and `*_req_t`/`*_rsp_t` types must be bound in accordance to the configuration with the `AXI_TYPEDEF` macros defined in `axi/typedef.svh`. The `rule_t` type must be bound to an address decoding rule with the same address width as in the configuration, and `axi_pkg` contains definitions for 64- and 32-bit addresses.
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‎doc/axi_mux.md‎

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@@ -7,7 +7,7 @@ The opposite function to the AXI demultiplexer is performed by the AXI Multiplex
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The Multiplexer module is has a simpler structure than the demultiplexer introduced in the previous section. The requests on the AW and AR channels get merged with the same round robin arbitration used for merging the responses in the demultiplexer. One key difference however is the mechanism how the multiplexer determines from which slave port a request came. It uses for this the higher bits of the `axi_id` field of a request. The number of bits can be calculated with:
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```systemverilog
10-
$clog2(NoSlavePorts)
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$clog2(NumSlavePorts)
1111
```
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This restricts the type of ID which can be sent through each slave port of the module. When the higher ID bits do not correspond to the index of the port the following response will be sent back through to the wrong master, leading to a breakdown of the functionality. So for using this module it is recommended to extend each AXI ID by the required amount of bits indicating the index of the respective slave port, before being sent over this module.
@@ -25,7 +25,7 @@ The following table shows the parameters of the module. The module further requi
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| Name | Type | Function |
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|:------------ |:-------------- |:----------------------------------------------------------------------------------------------------------- |
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| `IdWidth` | `int unsigned` | The width of the AXI transaction ID in bits. |
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| `NoSlvPorts` | `int unsigned` | How many slave ports the multiplexer features. This many master modules can be connected to the multiplexer.|
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| `NumSlvPorts`| `int unsigned` | How many slave ports the multiplexer features. This many master modules can be connected to the multiplexer.|
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| `MaxWTrans` | `int unsigned` | The depth of the FIFO holding the highest bits of the ID between the AW and W channel. |
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| `FallThrough`| `bit` | Is the FIFO between the AW and W channel in fall-through mode. Enabling will lead to longer cycle delays. |
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| `SpillXX` | `bit` | Enables the optional spill-register on the respective channel. |

‎doc/axi_xbar.md‎

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@@ -12,7 +12,7 @@ A block-diagram of the crossbar is shown below:
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The crossbar has a configurable number of slave and master ports.
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The ID width of the master ports is wider than that of the slave ports. The additional ID bits are used by the internal multiplexers to route responses. The ID width of the master ports must be `IdWidthSlvPorts + $clog_2(NoSlvPorts)`.
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The ID width of the master ports is wider than that of the slave ports. The additional ID bits are used by the internal multiplexers to route responses. The ID width of the master ports must be `IdWidthSlvPorts + $clog_2(NumSlvPorts)`.
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## Address Map
@@ -41,8 +41,8 @@ The crossbar is configured through the `Cfg` parameter with a `axi_pkg::xbar_cfg
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| Name | Type | Definition |
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|:------------------|:-------------------|:-----------|
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| `NoSlvPorts` | `int unsigned` | The number of AXI slave ports of the crossbar (in other words, how many AXI master modules can be attached). |
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| `NoMstPorts` | `int unsigned` | The number of AXI master ports of the crossbar (in other words, how many AXI slave modules can be attached). |
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| `NumSlvPorts` | `int unsigned` | The number of AXI slave ports of the crossbar (in other words, how many AXI master modules can be attached). |
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| `NumMstPorts` | `int unsigned` | The number of AXI master ports of the crossbar (in other words, how many AXI slave modules can be attached). |
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| `MaxMstTrans` | `int unsigned` | Each slave port can have at most this many transactions [in flight](../doc#in-flight). |
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| `MaxSlvTrans` | `int unsigned` | Each master port can have at most this many transactions per ID [in flight](../doc#in-flight). |
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| `FallThrough` | `bit` | Routing decisions on the AW channel fall through to the W channel. Enabling this allows the crossbar to accept a W beat in the same cycle as the corresponding AW beat, but it increases the combinatorial path of the W channel with logic from the AW channel. |
@@ -52,7 +52,7 @@ The crossbar is configured through the `Cfg` parameter with a `axi_pkg::xbar_cfg
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| `UniqueIds` | `bit` | If you can guarantee that the ID of each transaction is always unique among all in-flight transactions in the same direction, setting this parameter to `1'b1` simplifies the crossbar. See the [`axi_demux` documentation](axi_demux#ordering-and-stalls) for details. |
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| `AddrWidth` | `int unsigned` | The AXI address width. |
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| `DataWidth` | `int unsigned` | The AXI data width. |
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| `NoAddrRules` | `int unsigned` | The number of address map rules. |
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| `NumAddrRules` | `int unsigned` | The number of address map rules. |
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The other parameters are types to define the ports of the crossbar. The `*_chan_t` and `*_req_t`/`*_rsp_t` types must be bound in accordance to the configuration with the `AXI_TYPEDEF` macros defined in `axi/typedef.svh`. The `rule_t` type must be bound to an address decoding rule with the same address width as in the configuration, and `axi_pkg` contains definitions for 64- and 32-bit addresses.
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‎scripts/axi_intercon_gen.py‎

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@@ -329,22 +329,22 @@ def write(self):
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ns = len(self.slaves)
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raw += """
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localparam int unsigned NoMasters = 32'd{}; // How many Axi Masters there are
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localparam int unsigned NoSlaves = 32'd{}; // How many Axi Slaves there are
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localparam int unsigned NumMasters = 32'd{}; // How many Axi Masters there are
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localparam int unsigned NumSlaves = 32'd{}; // How many Axi Slaves there are
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// axi configuration
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localparam int unsigned IdWidthMasters = 32'd{};
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localparam int unsigned IdUsed = 32'd{}; // Has to be <= IdWidthMasters
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localparam int unsigned IdWidthSlaves = IdWidthMasters + $clog2(NoMasters);
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localparam int unsigned IdWidthSlaves = IdWidthMasters + $clog2(NumMasters);
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localparam int unsigned AddrWidth = 32'd32; // Address Width
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localparam int unsigned DataWidth = 32'd64; // Data Width
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localparam int unsigned StrbWidth = DataWidth / 8;
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localparam int unsigned UserWidth = 1;
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""".format(nm, ns, max_idw, max_idw)
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raw += " localparam axi_pkg::xbar_cfg_t xbar_cfg = '{\n"
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raw += """
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NoSlvPorts: NoMasters,
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NoMstPorts: NoSlaves,
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NumSlvPorts: NumMasters,
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NumMstPorts: NumSlaves,
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MaxMstTrans: 10,
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MaxSlvTrans: 6,
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FallThrough: 1'b0,
@@ -354,7 +354,7 @@ def write(self):
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UniqueIds: 1'b0,
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AddrWidth: AddrWidth,
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DataWidth: DataWidth,
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NoAddrRules: NoSlaves
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NumAddrRules: NumSlaves
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"""
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raw += " };\n"
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raw += """

‎src/axi_burst_splitter.sv‎

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@@ -75,7 +75,7 @@ module axi_burst_splitter #(
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.r_chan_t ( r_chan_t ),
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.axi_req_t ( axi_req_t ),
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.axi_rsp_t ( axi_rsp_t ),
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.NoMstPorts ( 2 ),
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.NumMstPorts ( 2 ),
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.MaxTrans ( MaxTxns ),
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.LookBits ( IdWidth ),
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.FallThrough ( 1'b1 ),

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